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-rw-r--r--drivers/char/Kconfig2
-rw-r--r--drivers/char/watchdog/Kconfig8
-rw-r--r--drivers/char/watchdog/shwdt.c110
-rw-r--r--drivers/input/touchscreen/hp680_ts_input.c14
-rw-r--r--drivers/net/stnic.c2
-rw-r--r--drivers/rtc/Kconfig10
-rw-r--r--drivers/rtc/Makefile1
-rw-r--r--drivers/rtc/rtc-sh.c467
-rw-r--r--drivers/serial/Kconfig9
-rw-r--r--drivers/serial/sh-sci.c1146
-rw-r--r--drivers/serial/sh-sci.h90
-rw-r--r--drivers/video/backlight/hp680_bl.c4
-rw-r--r--drivers/video/console/Kconfig2
-rw-r--r--drivers/video/hitfb.c229
-rw-r--r--drivers/video/pvr2fb.c22
15 files changed, 1234 insertions, 882 deletions
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 6a3d3af45c59..1b21c3a911d9 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -747,7 +747,7 @@ config NVRAM
747 747
748config RTC 748config RTC
749 tristate "Enhanced Real Time Clock Support" 749 tristate "Enhanced Real Time Clock Support"
750 depends on !PPC && !PARISC && !IA64 && !M68K && (!SPARC || PCI) && !FRV && !ARM 750 depends on !PPC && !PARISC && !IA64 && !M68K && (!SPARC || PCI) && !FRV && !ARM && !SUPERH
751 ---help--- 751 ---help---
752 If you say Y here and create a character special file /dev/rtc with 752 If you say Y here and create a character special file /dev/rtc with
753 major number 10 and minor number 135 using mknod ("man mknod"), you 753 major number 10 and minor number 135 using mknod ("man mknod"), you
diff --git a/drivers/char/watchdog/Kconfig b/drivers/char/watchdog/Kconfig
index fff89c2d88fd..f114d7b5bb2a 100644
--- a/drivers/char/watchdog/Kconfig
+++ b/drivers/char/watchdog/Kconfig
@@ -510,6 +510,14 @@ config SH_WDT
510 To compile this driver as a module, choose M here: the 510 To compile this driver as a module, choose M here: the
511 module will be called shwdt. 511 module will be called shwdt.
512 512
513config SH_WDT_MMAP
514 bool "Allow mmap of SH WDT"
515 default n
516 depends on SH_WDT
517 help
518 If you say Y here, user applications will be able to mmap the
519 WDT/CPG registers.
520#
513# SPARC64 Architecture 521# SPARC64 Architecture
514 522
515config WATCHDOG_CP1XXX 523config WATCHDOG_CP1XXX
diff --git a/drivers/char/watchdog/shwdt.c b/drivers/char/watchdog/shwdt.c
index 1355038f1044..e5b8c64f1d65 100644
--- a/drivers/char/watchdog/shwdt.c
+++ b/drivers/char/watchdog/shwdt.c
@@ -27,7 +27,7 @@
27#include <linux/notifier.h> 27#include <linux/notifier.h>
28#include <linux/ioport.h> 28#include <linux/ioport.h>
29#include <linux/fs.h> 29#include <linux/fs.h>
30 30#include <linux/mm.h>
31#include <asm/io.h> 31#include <asm/io.h>
32#include <asm/uaccess.h> 32#include <asm/uaccess.h>
33#include <asm/watchdog.h> 33#include <asm/watchdog.h>
@@ -125,7 +125,6 @@ static void sh_wdt_start(void)
125 125
126/** 126/**
127 * sh_wdt_stop - Stop the Watchdog 127 * sh_wdt_stop - Stop the Watchdog
128 *
129 * Stops the watchdog. 128 * Stops the watchdog.
130 */ 129 */
131static void sh_wdt_stop(void) 130static void sh_wdt_stop(void)
@@ -141,22 +140,20 @@ static void sh_wdt_stop(void)
141 140
142/** 141/**
143 * sh_wdt_keepalive - Keep the Userspace Watchdog Alive 142 * sh_wdt_keepalive - Keep the Userspace Watchdog Alive
144 *
145 * The Userspace watchdog got a KeepAlive: schedule the next heartbeat. 143 * The Userspace watchdog got a KeepAlive: schedule the next heartbeat.
146 */ 144 */
147static void sh_wdt_keepalive(void) 145static inline void sh_wdt_keepalive(void)
148{ 146{
149 next_heartbeat = jiffies + (heartbeat * HZ); 147 next_heartbeat = jiffies + (heartbeat * HZ);
150} 148}
151 149
152/** 150/**
153 * sh_wdt_set_heartbeat - Set the Userspace Watchdog heartbeat 151 * sh_wdt_set_heartbeat - Set the Userspace Watchdog heartbeat
154 *
155 * Set the Userspace Watchdog heartbeat 152 * Set the Userspace Watchdog heartbeat
156 */ 153 */
157static int sh_wdt_set_heartbeat(int t) 154static int sh_wdt_set_heartbeat(int t)
158{ 155{
159 if ((t < 1) || (t > 3600)) /* arbitrary upper limit */ 156 if (unlikely((t < 1) || (t > 3600))) /* arbitrary upper limit */
160 return -EINVAL; 157 return -EINVAL;
161 158
162 heartbeat = t; 159 heartbeat = t;
@@ -165,7 +162,6 @@ static int sh_wdt_set_heartbeat(int t)
165 162
166/** 163/**
167 * sh_wdt_ping - Ping the Watchdog 164 * sh_wdt_ping - Ping the Watchdog
168 *
169 * @data: Unused 165 * @data: Unused
170 * 166 *
171 * Clears overflow bit, resets timer counter. 167 * Clears overflow bit, resets timer counter.
@@ -182,14 +178,13 @@ static void sh_wdt_ping(unsigned long data)
182 sh_wdt_write_cnt(0); 178 sh_wdt_write_cnt(0);
183 179
184 mod_timer(&timer, next_ping_period(clock_division_ratio)); 180 mod_timer(&timer, next_ping_period(clock_division_ratio));
185 } else { 181 } else
186 printk(KERN_WARNING PFX "Heartbeat lost! Will not ping the watchdog\n"); 182 printk(KERN_WARNING PFX "Heartbeat lost! Will not ping "
187 } 183 "the watchdog\n");
188} 184}
189 185
190/** 186/**
191 * sh_wdt_open - Open the Device 187 * sh_wdt_open - Open the Device
192 *
193 * @inode: inode of device 188 * @inode: inode of device
194 * @file: file handle of device 189 * @file: file handle of device
195 * 190 *
@@ -209,7 +204,6 @@ static int sh_wdt_open(struct inode *inode, struct file *file)
209 204
210/** 205/**
211 * sh_wdt_close - Close the Device 206 * sh_wdt_close - Close the Device
212 *
213 * @inode: inode of device 207 * @inode: inode of device
214 * @file: file handle of device 208 * @file: file handle of device
215 * 209 *
@@ -220,7 +214,8 @@ static int sh_wdt_close(struct inode *inode, struct file *file)
220 if (shwdt_expect_close == 42) { 214 if (shwdt_expect_close == 42) {
221 sh_wdt_stop(); 215 sh_wdt_stop();
222 } else { 216 } else {
223 printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); 217 printk(KERN_CRIT PFX "Unexpected close, not "
218 "stopping watchdog!\n");
224 sh_wdt_keepalive(); 219 sh_wdt_keepalive();
225 } 220 }
226 221
@@ -232,7 +227,6 @@ static int sh_wdt_close(struct inode *inode, struct file *file)
232 227
233/** 228/**
234 * sh_wdt_write - Write to Device 229 * sh_wdt_write - Write to Device
235 *
236 * @file: file handle of device 230 * @file: file handle of device
237 * @buf: buffer to write 231 * @buf: buffer to write
238 * @count: length of buffer 232 * @count: length of buffer
@@ -264,8 +258,56 @@ static ssize_t sh_wdt_write(struct file *file, const char *buf,
264} 258}
265 259
266/** 260/**
267 * sh_wdt_ioctl - Query Device 261 * sh_wdt_mmap - map WDT/CPG registers into userspace
262 * @file: file structure for the device
263 * @vma: VMA to map the registers into
264 *
265 * A simple mmap() implementation for the corner cases where the counter
266 * needs to be mapped in userspace directly. Due to the relatively small
267 * size of the area, neighbouring registers not necessarily tied to the
268 * CPG will also be accessible through the register page, so this remains
269 * configurable for users that really know what they're doing.
268 * 270 *
271 * Additionaly, the register page maps in the CPG register base relative
272 * to the nearest page-aligned boundary, which requires that userspace do
273 * the appropriate CPU subtype math for calculating the page offset for
274 * the counter value.
275 */
276static int sh_wdt_mmap(struct file *file, struct vm_area_struct *vma)
277{
278 int ret = -ENOSYS;
279
280#ifdef CONFIG_SH_WDT_MMAP
281 unsigned long addr;
282
283 /* Only support the simple cases where we map in a register page. */
284 if (((vma->vm_end - vma->vm_start) != PAGE_SIZE) || vma->vm_pgoff)
285 return -EINVAL;
286
287 /*
288 * Pick WTCNT as the start, it's usually the first register after the
289 * FRQCR, and neither one are generally page-aligned out of the box.
290 */
291 addr = WTCNT & ~(PAGE_SIZE - 1);
292
293 vma->vm_flags |= VM_IO;
294 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
295
296 if (io_remap_pfn_range(vma, vma->vm_start, addr >> PAGE_SHIFT,
297 PAGE_SIZE, vma->vm_page_prot)) {
298 printk(KERN_ERR PFX "%s: io_remap_pfn_range failed\n",
299 __FUNCTION__);
300 return -EAGAIN;
301 }
302
303 ret = 0;
304#endif
305
306 return ret;
307}
308
309/**
310 * sh_wdt_ioctl - Query Device
269 * @inode: inode of device 311 * @inode: inode of device
270 * @file: file handle of device 312 * @file: file handle of device
271 * @cmd: watchdog command 313 * @cmd: watchdog command
@@ -326,7 +368,6 @@ static int sh_wdt_ioctl(struct inode *inode, struct file *file,
326 368
327/** 369/**
328 * sh_wdt_notify_sys - Notifier Handler 370 * sh_wdt_notify_sys - Notifier Handler
329 *
330 * @this: notifier block 371 * @this: notifier block
331 * @code: notifier event 372 * @code: notifier event
332 * @unused: unused 373 * @unused: unused
@@ -337,9 +378,8 @@ static int sh_wdt_ioctl(struct inode *inode, struct file *file,
337static int sh_wdt_notify_sys(struct notifier_block *this, 378static int sh_wdt_notify_sys(struct notifier_block *this,
338 unsigned long code, void *unused) 379 unsigned long code, void *unused)
339{ 380{
340 if (code == SYS_DOWN || code == SYS_HALT) { 381 if (code == SYS_DOWN || code == SYS_HALT)
341 sh_wdt_stop(); 382 sh_wdt_stop();
342 }
343 383
344 return NOTIFY_DONE; 384 return NOTIFY_DONE;
345} 385}
@@ -351,10 +391,12 @@ static const struct file_operations sh_wdt_fops = {
351 .ioctl = sh_wdt_ioctl, 391 .ioctl = sh_wdt_ioctl,
352 .open = sh_wdt_open, 392 .open = sh_wdt_open,
353 .release = sh_wdt_close, 393 .release = sh_wdt_close,
394 .mmap = sh_wdt_mmap,
354}; 395};
355 396
356static struct watchdog_info sh_wdt_info = { 397static struct watchdog_info sh_wdt_info = {
357 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, 398 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
399 WDIOF_MAGICCLOSE,
358 .firmware_version = 1, 400 .firmware_version = 1,
359 .identity = "SH WDT", 401 .identity = "SH WDT",
360}; 402};
@@ -371,7 +413,6 @@ static struct miscdevice sh_wdt_miscdev = {
371 413
372/** 414/**
373 * sh_wdt_init - Initialize module 415 * sh_wdt_init - Initialize module
374 *
375 * Registers the device and notifier handler. Actual device 416 * Registers the device and notifier handler. Actual device
376 * initialization is handled by sh_wdt_open(). 417 * initialization is handled by sh_wdt_open().
377 */ 418 */
@@ -381,15 +422,15 @@ static int __init sh_wdt_init(void)
381 422
382 if ((clock_division_ratio < 0x5) || (clock_division_ratio > 0x7)) { 423 if ((clock_division_ratio < 0x5) || (clock_division_ratio > 0x7)) {
383 clock_division_ratio = WTCSR_CKS_4096; 424 clock_division_ratio = WTCSR_CKS_4096;
384 printk(KERN_INFO PFX "clock_division_ratio value must be 0x5<=x<=0x7, using %d\n", 425 printk(KERN_INFO PFX "clock_division_ratio value must "
385 clock_division_ratio); 426 "be 0x5<=x<=0x7, using %d\n", clock_division_ratio);
386 } 427 }
387 428
388 if (sh_wdt_set_heartbeat(heartbeat)) 429 rc = sh_wdt_set_heartbeat(heartbeat);
389 { 430 if (unlikely(rc)) {
390 heartbeat = WATCHDOG_HEARTBEAT; 431 heartbeat = WATCHDOG_HEARTBEAT;
391 printk(KERN_INFO PFX "heartbeat value must be 1<=x<=3600, using %d\n", 432 printk(KERN_INFO PFX "heartbeat value must "
392 heartbeat); 433 "be 1<=x<=3600, using %d\n", heartbeat);
393 } 434 }
394 435
395 init_timer(&timer); 436 init_timer(&timer);
@@ -397,15 +438,16 @@ static int __init sh_wdt_init(void)
397 timer.data = 0; 438 timer.data = 0;
398 439
399 rc = register_reboot_notifier(&sh_wdt_notifier); 440 rc = register_reboot_notifier(&sh_wdt_notifier);
400 if (rc) { 441 if (unlikely(rc)) {
401 printk(KERN_ERR PFX "Can't register reboot notifier (err=%d)\n", rc); 442 printk(KERN_ERR PFX "Can't register reboot notifier (err=%d)\n",
443 rc);
402 return rc; 444 return rc;
403 } 445 }
404 446
405 rc = misc_register(&sh_wdt_miscdev); 447 rc = misc_register(&sh_wdt_miscdev);
406 if (rc) { 448 if (unlikely(rc)) {
407 printk(KERN_ERR PFX "Can't register miscdev on minor=%d (err=%d)\n", 449 printk(KERN_ERR PFX "Can't register miscdev on "
408 sh_wdt_miscdev.minor, rc); 450 "minor=%d (err=%d)\n", sh_wdt_miscdev.minor, rc);
409 unregister_reboot_notifier(&sh_wdt_notifier); 451 unregister_reboot_notifier(&sh_wdt_notifier);
410 return rc; 452 return rc;
411 } 453 }
@@ -418,7 +460,6 @@ static int __init sh_wdt_init(void)
418 460
419/** 461/**
420 * sh_wdt_exit - Deinitialize module 462 * sh_wdt_exit - Deinitialize module
421 *
422 * Unregisters the device and notifier handler. Actual device 463 * Unregisters the device and notifier handler. Actual device
423 * deinitialization is handled by sh_wdt_close(). 464 * deinitialization is handled by sh_wdt_close().
424 */ 465 */
@@ -434,14 +475,13 @@ MODULE_LICENSE("GPL");
434MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); 475MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
435 476
436module_param(clock_division_ratio, int, 0); 477module_param(clock_division_ratio, int, 0);
437MODULE_PARM_DESC(clock_division_ratio, "Clock division ratio. Valid ranges are from 0x5 (1.31ms) to 0x7 (5.25ms). Defaults to 0x7."); 478MODULE_PARM_DESC(clock_division_ratio, "Clock division ratio. Valid ranges are from 0x5 (1.31ms) to 0x7 (5.25ms). (default=" __MODULE_STRING(clock_division_ratio) ")");
438 479
439module_param(heartbeat, int, 0); 480module_param(heartbeat, int, 0);
440MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (1<=heartbeat<=3600, default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); 481MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (1<=heartbeat<=3600, default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
441 482
442module_param(nowayout, int, 0); 483module_param(nowayout, int, 0);
443MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)"); 484MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
444 485
445module_init(sh_wdt_init); 486module_init(sh_wdt_init);
446module_exit(sh_wdt_exit); 487module_exit(sh_wdt_exit);
447
diff --git a/drivers/input/touchscreen/hp680_ts_input.c b/drivers/input/touchscreen/hp680_ts_input.c
index fa97e0f79e7e..ee6c2f40cdf6 100644
--- a/drivers/input/touchscreen/hp680_ts_input.c
+++ b/drivers/input/touchscreen/hp680_ts_input.c
@@ -15,7 +15,6 @@
15#define HP680_TS_ABS_Y_MIN 80 15#define HP680_TS_ABS_Y_MIN 80
16#define HP680_TS_ABS_Y_MAX 910 16#define HP680_TS_ABS_Y_MAX 910
17 17
18#define SCPCR 0xa4000116
19#define PHDR 0xa400012e 18#define PHDR 0xa400012e
20#define SCPDR 0xa4000136 19#define SCPDR 0xa4000136
21 20
@@ -77,19 +76,6 @@ static irqreturn_t hp680_ts_interrupt(int irq, void *dev, struct pt_regs *regs)
77 76
78static int __init hp680_ts_init(void) 77static int __init hp680_ts_init(void)
79{ 78{
80 u8 scpdr;
81 u16 scpcr;
82
83 scpdr = ctrl_inb(SCPDR);
84 scpdr |= SCPDR_TS_SCAN_X | SCPDR_TS_SCAN_Y;
85 scpdr &= ~SCPDR_TS_SCAN_ENABLE;
86 ctrl_outb(scpdr, SCPDR);
87
88 scpcr = ctrl_inw(SCPCR);
89 scpcr &= ~SCPCR_TS_MASK;
90 scpcr |= SCPCR_TS_ENABLE;
91 ctrl_outw(scpcr, SCPCR);
92
93 hp680_ts_dev = input_allocate_device(); 79 hp680_ts_dev = input_allocate_device();
94 if (!hp680_ts_dev) 80 if (!hp680_ts_dev)
95 return -ENOMEM; 81 return -ENOMEM;
diff --git a/drivers/net/stnic.c b/drivers/net/stnic.c
index 3fd7a4fee665..e6f90427160c 100644
--- a/drivers/net/stnic.c
+++ b/drivers/net/stnic.c
@@ -19,7 +19,7 @@
19 19
20#include <asm/system.h> 20#include <asm/system.h>
21#include <asm/io.h> 21#include <asm/io.h>
22#include <asm/se/se.h> 22#include <asm/se.h>
23#include <asm/machvec.h> 23#include <asm/machvec.h>
24#ifdef CONFIG_SH_STANDARD_BIOS 24#ifdef CONFIG_SH_STANDARD_BIOS
25#include <asm/sh_bios.h> 25#include <asm/sh_bios.h>
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 7ff1d88094b6..33a7b720539b 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -238,6 +238,16 @@ config RTC_DRV_SA1100
238 To compile this driver as a module, choose M here: the 238 To compile this driver as a module, choose M here: the
239 module will be called rtc-sa1100. 239 module will be called rtc-sa1100.
240 240
241config RTC_DRV_SH
242 tristate "SuperH On-Chip RTC"
243 depends on RTC_CLASS && SUPERH
244 help
245 Say Y here to enable support for the on-chip RTC found in
246 most SuperH processors.
247
248 To compile this driver as a module, choose M here: the
249 module will be called rtc-sh.
250
241config RTC_DRV_VR41XX 251config RTC_DRV_VR41XX
242 tristate "NEC VR41XX" 252 tristate "NEC VR41XX"
243 depends on RTC_CLASS && CPU_VR41XX 253 depends on RTC_CLASS && CPU_VR41XX
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index bbcfb09d81d9..e72d467ab214 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -31,3 +31,4 @@ obj-$(CONFIG_RTC_DRV_PL031) += rtc-pl031.o
31obj-$(CONFIG_RTC_DRV_MAX6902) += rtc-max6902.o 31obj-$(CONFIG_RTC_DRV_MAX6902) += rtc-max6902.o
32obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020.o 32obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020.o
33obj-$(CONFIG_RTC_DRV_AT91) += rtc-at91.o 33obj-$(CONFIG_RTC_DRV_AT91) += rtc-at91.o
34obj-$(CONFIG_RTC_DRV_SH) += rtc-sh.o
diff --git a/drivers/rtc/rtc-sh.c b/drivers/rtc/rtc-sh.c
new file mode 100644
index 000000000000..d2ce0c8bb8f3
--- /dev/null
+++ b/drivers/rtc/rtc-sh.c
@@ -0,0 +1,467 @@
1/*
2 * SuperH On-Chip RTC Support
3 *
4 * Copyright (C) 2006 Paul Mundt
5 *
6 * Based on the old arch/sh/kernel/cpu/rtc.c by:
7 *
8 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
9 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/bcd.h>
18#include <linux/rtc.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/seq_file.h>
22#include <linux/interrupt.h>
23#include <linux/spinlock.h>
24#include <asm/io.h>
25
26#ifdef CONFIG_CPU_SH3
27#define rtc_reg_size sizeof(u16)
28#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */
29#elif defined(CONFIG_CPU_SH4)
30#define rtc_reg_size sizeof(u32)
31#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
32#endif
33
34#define RTC_REG(r) ((r) * rtc_reg_size)
35
36#define R64CNT RTC_REG(0)
37#define RSECCNT RTC_REG(1)
38#define RMINCNT RTC_REG(2)
39#define RHRCNT RTC_REG(3)
40#define RWKCNT RTC_REG(4)
41#define RDAYCNT RTC_REG(5)
42#define RMONCNT RTC_REG(6)
43#define RYRCNT RTC_REG(7)
44#define RSECAR RTC_REG(8)
45#define RMINAR RTC_REG(9)
46#define RHRAR RTC_REG(10)
47#define RWKAR RTC_REG(11)
48#define RDAYAR RTC_REG(12)
49#define RMONAR RTC_REG(13)
50#define RCR1 RTC_REG(14)
51#define RCR2 RTC_REG(15)
52
53/* RCR1 Bits */
54#define RCR1_CF 0x80 /* Carry Flag */
55#define RCR1_CIE 0x10 /* Carry Interrupt Enable */
56#define RCR1_AIE 0x08 /* Alarm Interrupt Enable */
57#define RCR1_AF 0x01 /* Alarm Flag */
58
59/* RCR2 Bits */
60#define RCR2_PEF 0x80 /* PEriodic interrupt Flag */
61#define RCR2_PESMASK 0x70 /* Periodic interrupt Set */
62#define RCR2_RTCEN 0x08 /* ENable RTC */
63#define RCR2_ADJ 0x04 /* ADJustment (30-second) */
64#define RCR2_RESET 0x02 /* Reset bit */
65#define RCR2_START 0x01 /* Start bit */
66
67struct sh_rtc {
68 void __iomem *regbase;
69 unsigned long regsize;
70 struct resource *res;
71 unsigned int alarm_irq, periodic_irq, carry_irq;
72 struct rtc_device *rtc_dev;
73 spinlock_t lock;
74};
75
76static irqreturn_t sh_rtc_interrupt(int irq, void *id, struct pt_regs *regs)
77{
78 struct platform_device *pdev = id;
79 struct sh_rtc *rtc = platform_get_drvdata(pdev);
80 unsigned int tmp, events = 0;
81
82 spin_lock(&rtc->lock);
83
84 tmp = readb(rtc->regbase + RCR1);
85
86 if (tmp & RCR1_AF)
87 events |= RTC_AF | RTC_IRQF;
88
89 tmp &= ~(RCR1_CF | RCR1_AF);
90
91 writeb(tmp, rtc->regbase + RCR1);
92
93 rtc_update_irq(&rtc->rtc_dev->class_dev, 1, events);
94
95 spin_unlock(&rtc->lock);
96
97 return IRQ_HANDLED;
98}
99
100static irqreturn_t sh_rtc_periodic(int irq, void *id, struct pt_regs *regs)
101{
102 struct sh_rtc *rtc = dev_get_drvdata(id);
103
104 spin_lock(&rtc->lock);
105
106 rtc_update_irq(&rtc->rtc_dev->class_dev, 1, RTC_PF | RTC_IRQF);
107
108 spin_unlock(&rtc->lock);
109
110 return IRQ_HANDLED;
111}
112
113static inline void sh_rtc_setpie(struct device *dev, unsigned int enable)
114{
115 struct sh_rtc *rtc = dev_get_drvdata(dev);
116 unsigned int tmp;
117
118 spin_lock_irq(&rtc->lock);
119
120 tmp = readb(rtc->regbase + RCR2);
121
122 if (enable) {
123 tmp &= ~RCR2_PESMASK;
124 tmp |= RCR2_PEF | (2 << 4);
125 } else
126 tmp &= ~(RCR2_PESMASK | RCR2_PEF);
127
128 writeb(tmp, rtc->regbase + RCR2);
129
130 spin_unlock_irq(&rtc->lock);
131}
132
133static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
134{
135 struct sh_rtc *rtc = dev_get_drvdata(dev);
136 unsigned int tmp;
137
138 spin_lock_irq(&rtc->lock);
139
140 tmp = readb(rtc->regbase + RCR1);
141
142 if (enable)
143 tmp |= RCR1_AIE;
144 else
145 tmp &= ~RCR1_AIE;
146
147 writeb(tmp, rtc->regbase + RCR1);
148
149 spin_unlock_irq(&rtc->lock);
150}
151
152static int sh_rtc_open(struct device *dev)
153{
154 struct sh_rtc *rtc = dev_get_drvdata(dev);
155 unsigned int tmp;
156 int ret;
157
158 tmp = readb(rtc->regbase + RCR1);
159 tmp &= ~RCR1_CF;
160 tmp |= RCR1_CIE;
161 writeb(tmp, rtc->regbase + RCR1);
162
163 ret = request_irq(rtc->periodic_irq, sh_rtc_periodic, SA_INTERRUPT,
164 "sh-rtc period", dev);
165 if (unlikely(ret)) {
166 dev_err(dev, "request period IRQ failed with %d, IRQ %d\n",
167 ret, rtc->periodic_irq);
168 return ret;
169 }
170
171 ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, SA_INTERRUPT,
172 "sh-rtc carry", dev);
173 if (unlikely(ret)) {
174 dev_err(dev, "request carry IRQ failed with %d, IRQ %d\n",
175 ret, rtc->carry_irq);
176 free_irq(rtc->periodic_irq, dev);
177 goto err_bad_carry;
178 }
179
180 ret = request_irq(rtc->alarm_irq, sh_rtc_interrupt, SA_INTERRUPT,
181 "sh-rtc alarm", dev);
182 if (unlikely(ret)) {
183 dev_err(dev, "request alarm IRQ failed with %d, IRQ %d\n",
184 ret, rtc->alarm_irq);
185 goto err_bad_alarm;
186 }
187
188 return 0;
189
190err_bad_alarm:
191 free_irq(rtc->carry_irq, dev);
192err_bad_carry:
193 free_irq(rtc->periodic_irq, dev);
194
195 return ret;
196}
197
198static void sh_rtc_release(struct device *dev)
199{
200 struct sh_rtc *rtc = dev_get_drvdata(dev);
201
202 sh_rtc_setpie(dev, 0);
203
204 free_irq(rtc->periodic_irq, dev);
205 free_irq(rtc->carry_irq, dev);
206 free_irq(rtc->alarm_irq, dev);
207}
208
209static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
210{
211 struct sh_rtc *rtc = dev_get_drvdata(dev);
212 unsigned int tmp;
213
214 tmp = readb(rtc->regbase + RCR1);
215 seq_printf(seq, "alarm_IRQ\t: %s\n",
216 (tmp & RCR1_AIE) ? "yes" : "no");
217 seq_printf(seq, "carry_IRQ\t: %s\n",
218 (tmp & RCR1_CIE) ? "yes" : "no");
219
220 tmp = readb(rtc->regbase + RCR2);
221 seq_printf(seq, "periodic_IRQ\t: %s\n",
222 (tmp & RCR2_PEF) ? "yes" : "no");
223
224 return 0;
225}
226
227static int sh_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
228{
229 unsigned int ret = -ENOIOCTLCMD;
230
231 switch (cmd) {
232 case RTC_PIE_OFF:
233 case RTC_PIE_ON:
234 sh_rtc_setpie(dev, cmd == RTC_PIE_ON);
235 ret = 0;
236 break;
237 case RTC_AIE_OFF:
238 case RTC_AIE_ON:
239 sh_rtc_setaie(dev, cmd == RTC_AIE_ON);
240 ret = 0;
241 break;
242 }
243
244 return ret;
245}
246
247static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
248{
249 struct platform_device *pdev = to_platform_device(dev);
250 struct sh_rtc *rtc = platform_get_drvdata(pdev);
251 unsigned int sec128, sec2, yr, yr100, cf_bit;
252
253 do {
254 unsigned int tmp;
255
256 spin_lock_irq(&rtc->lock);
257
258 tmp = readb(rtc->regbase + RCR1);
259 tmp &= ~RCR1_CF; /* Clear CF-bit */
260 tmp |= RCR1_CIE;
261 writeb(tmp, rtc->regbase + RCR1);
262
263 sec128 = readb(rtc->regbase + R64CNT);
264
265 tm->tm_sec = BCD2BIN(readb(rtc->regbase + RSECCNT));
266 tm->tm_min = BCD2BIN(readb(rtc->regbase + RMINCNT));
267 tm->tm_hour = BCD2BIN(readb(rtc->regbase + RHRCNT));
268 tm->tm_wday = BCD2BIN(readb(rtc->regbase + RWKCNT));
269 tm->tm_mday = BCD2BIN(readb(rtc->regbase + RDAYCNT));
270 tm->tm_mon = BCD2BIN(readb(rtc->regbase + RMONCNT));
271
272#if defined(CONFIG_CPU_SH4)
273 yr = readw(rtc->regbase + RYRCNT);
274 yr100 = BCD2BIN(yr >> 8);
275 yr &= 0xff;
276#else
277 yr = readb(rtc->regbase + RYRCNT);
278 yr100 = BCD2BIN((yr == 0x99) ? 0x19 : 0x20);
279#endif
280
281 tm->tm_year = (yr100 * 100 + BCD2BIN(yr)) - 1900;
282
283 sec2 = readb(rtc->regbase + R64CNT);
284 cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF;
285
286 spin_unlock_irq(&rtc->lock);
287 } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0);
288
289#if RTC_BIT_INVERTED != 0
290 if ((sec128 & RTC_BIT_INVERTED))
291 tm->tm_sec--;
292#endif
293
294 dev_dbg(&dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
295 "mday=%d, mon=%d, year=%d, wday=%d\n",
296 __FUNCTION__,
297 tm->tm_sec, tm->tm_min, tm->tm_hour,
298 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
299
300 if (rtc_valid_tm(tm) < 0)
301 dev_err(dev, "invalid date\n");
302
303 return 0;
304}
305
306static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
307{
308 struct platform_device *pdev = to_platform_device(dev);
309 struct sh_rtc *rtc = platform_get_drvdata(pdev);
310 unsigned int tmp;
311 int year;
312
313 spin_lock_irq(&rtc->lock);
314
315 /* Reset pre-scaler & stop RTC */
316 tmp = readb(rtc->regbase + RCR2);
317 tmp |= RCR2_RESET;
318 writeb(tmp, rtc->regbase + RCR2);
319
320 writeb(BIN2BCD(tm->tm_sec), rtc->regbase + RSECCNT);
321 writeb(BIN2BCD(tm->tm_min), rtc->regbase + RMINCNT);
322 writeb(BIN2BCD(tm->tm_hour), rtc->regbase + RHRCNT);
323 writeb(BIN2BCD(tm->tm_wday), rtc->regbase + RWKCNT);
324 writeb(BIN2BCD(tm->tm_mday), rtc->regbase + RDAYCNT);
325 writeb(BIN2BCD(tm->tm_mon), rtc->regbase + RMONCNT);
326
327#ifdef CONFIG_CPU_SH3
328 year = tm->tm_year % 100;
329 writeb(BIN2BCD(year), rtc->regbase + RYRCNT);
330#else
331 year = (BIN2BCD((tm->tm_year + 1900) / 100) << 8) |
332 BIN2BCD(tm->tm_year % 100);
333 writew(year, rtc->regbase + RYRCNT);
334#endif
335
336 /* Start RTC */
337 tmp = readb(rtc->regbase + RCR2);
338 tmp &= ~RCR2_RESET;
339 tmp |= RCR2_RTCEN | RCR2_START;
340 writeb(tmp, rtc->regbase + RCR2);
341
342 spin_unlock_irq(&rtc->lock);
343
344 return 0;
345}
346
347static struct rtc_class_ops sh_rtc_ops = {
348 .open = sh_rtc_open,
349 .release = sh_rtc_release,
350 .ioctl = sh_rtc_ioctl,
351 .read_time = sh_rtc_read_time,
352 .set_time = sh_rtc_set_time,
353 .proc = sh_rtc_proc,
354};
355
356static int __devinit sh_rtc_probe(struct platform_device *pdev)
357{
358 struct sh_rtc *rtc;
359 struct resource *res;
360 int ret = -ENOENT;
361
362 rtc = kzalloc(sizeof(struct sh_rtc), GFP_KERNEL);
363 if (unlikely(!rtc))
364 return -ENOMEM;
365
366 spin_lock_init(&rtc->lock);
367
368 rtc->periodic_irq = platform_get_irq(pdev, 0);
369 if (unlikely(rtc->periodic_irq < 0)) {
370 dev_err(&pdev->dev, "No IRQ for period\n");
371 goto err_badres;
372 }
373
374 rtc->carry_irq = platform_get_irq(pdev, 1);
375 if (unlikely(rtc->carry_irq < 0)) {
376 dev_err(&pdev->dev, "No IRQ for carry\n");
377 goto err_badres;
378 }
379
380 rtc->alarm_irq = platform_get_irq(pdev, 2);
381 if (unlikely(rtc->alarm_irq < 0)) {
382 dev_err(&pdev->dev, "No IRQ for alarm\n");
383 goto err_badres;
384 }
385
386 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
387 if (unlikely(res == NULL)) {
388 dev_err(&pdev->dev, "No IO resource\n");
389 goto err_badres;
390 }
391
392 rtc->regsize = res->end - res->start + 1;
393
394 rtc->res = request_mem_region(res->start, rtc->regsize, pdev->name);
395 if (unlikely(!rtc->res)) {
396 ret = -EBUSY;
397 goto err_badres;
398 }
399
400 rtc->regbase = (void __iomem *)rtc->res->start;
401 if (unlikely(!rtc->regbase)) {
402 ret = -EINVAL;
403 goto err_badmap;
404 }
405
406 rtc->rtc_dev = rtc_device_register("sh", &pdev->dev,
407 &sh_rtc_ops, THIS_MODULE);
408 if (IS_ERR(rtc)) {
409 ret = PTR_ERR(rtc->rtc_dev);
410 goto err_badmap;
411 }
412
413 platform_set_drvdata(pdev, rtc);
414
415 return 0;
416
417err_badmap:
418 release_resource(rtc->res);
419err_badres:
420 kfree(rtc);
421
422 return ret;
423}
424
425static int __devexit sh_rtc_remove(struct platform_device *pdev)
426{
427 struct sh_rtc *rtc = platform_get_drvdata(pdev);
428
429 if (likely(rtc->rtc_dev))
430 rtc_device_unregister(rtc->rtc_dev);
431
432 sh_rtc_setpie(&pdev->dev, 0);
433 sh_rtc_setaie(&pdev->dev, 0);
434
435 release_resource(rtc->res);
436
437 platform_set_drvdata(pdev, NULL);
438
439 kfree(rtc);
440
441 return 0;
442}
443static struct platform_driver sh_rtc_platform_driver = {
444 .driver = {
445 .name = "sh-rtc",
446 .owner = THIS_MODULE,
447 },
448 .probe = sh_rtc_probe,
449 .remove = __devexit_p(sh_rtc_remove),
450};
451
452static int __init sh_rtc_init(void)
453{
454 return platform_driver_register(&sh_rtc_platform_driver);
455}
456
457static void __exit sh_rtc_exit(void)
458{
459 platform_driver_unregister(&sh_rtc_platform_driver);
460}
461
462module_init(sh_rtc_init);
463module_exit(sh_rtc_exit);
464
465MODULE_DESCRIPTION("SuperH on-chip RTC driver");
466MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
467MODULE_LICENSE("GPL");
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 5b48ac22c9c5..261eaa442953 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -642,12 +642,17 @@ config V850E_UART_CONSOLE
642 select SERIAL_CORE_CONSOLE 642 select SERIAL_CORE_CONSOLE
643 643
644config SERIAL_SH_SCI 644config SERIAL_SH_SCI
645 tristate "SH SCI(F) serial port support" 645 tristate "SuperH SCI(F) serial port support"
646 depends on SUPERH || H8300 646 depends on SUPERH || H8300
647 select SERIAL_CORE 647 select SERIAL_CORE
648 648
649config SERIAL_SH_SCI_NR_UARTS
650 int "Maximum number of SCI(F) serial ports"
651 depends on SERIAL_SH_SCI
652 default "2"
653
649config SERIAL_SH_SCI_CONSOLE 654config SERIAL_SH_SCI_CONSOLE
650 bool "Support for console on SH SCI(F)" 655 bool "Support for console on SuperH SCI(F)"
651 depends on SERIAL_SH_SCI=y 656 depends on SERIAL_SH_SCI=y
652 select SERIAL_CORE_CONSOLE 657 select SERIAL_CORE_CONSOLE
653 658
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index cbede06cac27..f336ba6778dd 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * 5 *
6 * Copyright (C) 2002, 2003, 2004 Paul Mundt 6 * Copyright (C) 2002 - 2006 Paul Mundt
7 * 7 *
8 * based off of the old drivers/char/sh-sci.c by: 8 * based off of the old drivers/char/sh-sci.c by:
9 * 9 *
@@ -20,10 +20,9 @@
20 20
21#undef DEBUG 21#undef DEBUG
22 22
23#include <linux/config.h>
23#include <linux/module.h> 24#include <linux/module.h>
24#include <linux/errno.h> 25#include <linux/errno.h>
25#include <linux/signal.h>
26#include <linux/sched.h>
27#include <linux/timer.h> 26#include <linux/timer.h>
28#include <linux/interrupt.h> 27#include <linux/interrupt.h>
29#include <linux/tty.h> 28#include <linux/tty.h>
@@ -32,71 +31,77 @@
32#include <linux/major.h> 31#include <linux/major.h>
33#include <linux/string.h> 32#include <linux/string.h>
34#include <linux/sysrq.h> 33#include <linux/sysrq.h>
35#include <linux/fcntl.h>
36#include <linux/ptrace.h>
37#include <linux/ioport.h> 34#include <linux/ioport.h>
38#include <linux/mm.h> 35#include <linux/mm.h>
39#include <linux/slab.h>
40#include <linux/init.h> 36#include <linux/init.h>
41#include <linux/delay.h> 37#include <linux/delay.h>
42#include <linux/console.h> 38#include <linux/console.h>
43#include <linux/bitops.h> 39#include <linux/platform_device.h>
44#include <linux/generic_serial.h>
45 40
46#ifdef CONFIG_CPU_FREQ 41#ifdef CONFIG_CPU_FREQ
47#include <linux/notifier.h> 42#include <linux/notifier.h>
48#include <linux/cpufreq.h> 43#include <linux/cpufreq.h>
49#endif 44#endif
50 45
51#include <asm/system.h>
52#include <asm/io.h>
53#include <asm/irq.h>
54#include <asm/uaccess.h>
55
56#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64) 46#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
57#include <asm/clock.h> 47#include <asm/clock.h>
58#endif
59
60#ifdef CONFIG_SH_STANDARD_BIOS
61#include <asm/sh_bios.h> 48#include <asm/sh_bios.h>
49#include <asm/kgdb.h>
62#endif 50#endif
63 51
52#include <asm/sci.h>
53
64#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 54#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
65#define SUPPORT_SYSRQ 55#define SUPPORT_SYSRQ
66#endif 56#endif
67 57
68#include "sh-sci.h" 58#include "sh-sci.h"
69 59
70#ifdef CONFIG_SH_KGDB 60struct sci_port {
71#include <asm/kgdb.h> 61 struct uart_port port;
62
63 /* Port type */
64 unsigned int type;
65
66 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
67 unsigned int irqs[SCIx_NR_IRQS];
68
69 /* Port pin configuration */
70 void (*init_pins)(struct uart_port *port,
71 unsigned int cflag);
72 72
73static int kgdb_get_char(struct sci_port *port); 73 /* Port enable callback */
74static void kgdb_put_char(struct sci_port *port, char c); 74 void (*enable)(struct uart_port *port);
75static void kgdb_handle_error(struct sci_port *port); 75
76 /* Port disable callback */
77 void (*disable)(struct uart_port *port);
78
79 /* Break timer */
80 struct timer_list break_timer;
81 int break_flag;
82};
83
84#ifdef CONFIG_SH_KGDB
76static struct sci_port *kgdb_sci_port; 85static struct sci_port *kgdb_sci_port;
77#endif /* CONFIG_SH_KGDB */ 86#endif
78 87
79#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 88#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
80static struct sci_port *serial_console_port = 0; 89static struct sci_port *serial_console_port;
81#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 90#endif
82 91
83/* Function prototypes */ 92/* Function prototypes */
84static void sci_stop_tx(struct uart_port *port); 93static void sci_stop_tx(struct uart_port *port);
85static void sci_start_tx(struct uart_port *port);
86static void sci_start_rx(struct uart_port *port, unsigned int tty_start);
87static void sci_stop_rx(struct uart_port *port);
88static int sci_request_irq(struct sci_port *port);
89static void sci_free_irq(struct sci_port *port);
90
91static struct sci_port sci_ports[];
92static struct uart_driver sci_uart_driver;
93 94
94#define SCI_NPORTS sci_uart_driver.nr 95#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
95 96
96#if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB) 97static struct sci_port sci_ports[SCI_NPORTS];
98static struct uart_driver sci_uart_driver;
97 99
98static void handle_error(struct uart_port *port) 100#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \
99{ /* Clear error flags */ 101 defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
102static inline void handle_error(struct uart_port *port)
103{
104 /* Clear error flags */
100 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 105 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
101} 106}
102 107
@@ -106,8 +111,8 @@ static int get_char(struct uart_port *port)
106 unsigned short status; 111 unsigned short status;
107 int c; 112 int c;
108 113
109 local_irq_save(flags); 114 spin_lock_irqsave(&port->lock, flags);
110 do { 115 do {
111 status = sci_in(port, SCxSR); 116 status = sci_in(port, SCxSR);
112 if (status & SCxSR_ERRORS(port)) { 117 if (status & SCxSR_ERRORS(port)) {
113 handle_error(port); 118 handle_error(port);
@@ -117,38 +122,19 @@ static int get_char(struct uart_port *port)
117 c = sci_in(port, SCxRDR); 122 c = sci_in(port, SCxRDR);
118 sci_in(port, SCxSR); /* Dummy read */ 123 sci_in(port, SCxSR); /* Dummy read */
119 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 124 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
120 local_irq_restore(flags); 125 spin_unlock_irqrestore(&port->lock, flags);
121 126
122 return c; 127 return c;
123} 128}
124
125/* Taken from sh-stub.c of GDB 4.18 */
126static const char hexchars[] = "0123456789abcdef";
127
128static __inline__ char highhex(int x)
129{
130 return hexchars[(x >> 4) & 0xf];
131}
132
133static __inline__ char lowhex(int x)
134{
135 return hexchars[x & 0xf];
136}
137
138#endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */ 129#endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
139 130
140/* 131#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)
141 * Send the packet in buffer. The host gets one chance to read it.
142 * This routine does not wait for a positive acknowledge.
143 */
144
145#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
146static void put_char(struct uart_port *port, char c) 132static void put_char(struct uart_port *port, char c)
147{ 133{
148 unsigned long flags; 134 unsigned long flags;
149 unsigned short status; 135 unsigned short status;
150 136
151 local_irq_save(flags); 137 spin_lock_irqsave(&port->lock, flags);
152 138
153 do { 139 do {
154 status = sci_in(port, SCxSR); 140 status = sci_in(port, SCxSR);
@@ -158,9 +144,11 @@ static void put_char(struct uart_port *port, char c)
158 sci_in(port, SCxSR); /* Dummy read */ 144 sci_in(port, SCxSR); /* Dummy read */
159 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 145 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
160 146
161 local_irq_restore(flags); 147 spin_unlock_irqrestore(&port->lock, flags);
162} 148}
149#endif
163 150
151#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
164static void put_string(struct sci_port *sci_port, const char *buffer, int count) 152static void put_string(struct sci_port *sci_port, const char *buffer, int count)
165{ 153{
166 struct uart_port *port = &sci_port->port; 154 struct uart_port *port = &sci_port->port;
@@ -213,96 +201,28 @@ static void put_string(struct sci_port *sci_port, const char *buffer, int count)
213} 201}
214#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 202#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
215 203
216
217#ifdef CONFIG_SH_KGDB 204#ifdef CONFIG_SH_KGDB
218
219/* Is the SCI ready, ie is there a char waiting? */
220static int kgdb_is_char_ready(struct sci_port *port)
221{
222 unsigned short status = sci_in(port, SCxSR);
223
224 if (status & (SCxSR_ERRORS(port) | SCxSR_BRK(port)))
225 kgdb_handle_error(port);
226
227 return (status & SCxSR_RDxF(port));
228}
229
230/* Write a char */
231static void kgdb_put_char(struct sci_port *port, char c)
232{
233 unsigned short status;
234
235 do
236 status = sci_in(port, SCxSR);
237 while (!(status & SCxSR_TDxE(port)));
238
239 sci_out(port, SCxTDR, c);
240 sci_in(port, SCxSR); /* Dummy read */
241 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
242}
243
244/* Get a char if there is one, else ret -1 */
245static int kgdb_get_char(struct sci_port *port)
246{
247 int c;
248
249 if (kgdb_is_char_ready(port) == 0)
250 c = -1;
251 else {
252 c = sci_in(port, SCxRDR);
253 sci_in(port, SCxSR); /* Dummy read */
254 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
255 }
256
257 return c;
258}
259
260/* Called from kgdbstub.c to get a character, i.e. is blocking */
261static int kgdb_sci_getchar(void) 205static int kgdb_sci_getchar(void)
262{ 206{
263 volatile int c; 207 int c;
264 208
265 /* Keep trying to read a character, this could be neater */ 209 /* Keep trying to read a character, this could be neater */
266 while ((c = kgdb_get_char(kgdb_sci_port)) < 0); 210 while ((c = get_char(kgdb_sci_port)) < 0)
211 cpu_relax();
267 212
268 return c; 213 return c;
269} 214}
270 215
271/* Called from kgdbstub.c to put a character, just a wrapper */ 216static inline void kgdb_sci_putchar(int c)
272static void kgdb_sci_putchar(int c)
273{
274
275 kgdb_put_char(kgdb_sci_port, c);
276}
277
278/* Clear any errors on the SCI */
279static void kgdb_handle_error(struct sci_port *port)
280{ 217{
281 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); /* Clear error flags */ 218 put_char(kgdb_sci_port, c);
282} 219}
283
284/* Breakpoint if there's a break sent on the serial port */
285static void kgdb_break_interrupt(int irq, void *ptr, struct pt_regs *regs)
286{
287 struct sci_port *port = ptr;
288 unsigned short status = sci_in(port, SCxSR);
289
290 if (status & SCxSR_BRK(port)) {
291
292 /* Break into the debugger if a break is detected */
293 BREAKPOINT();
294
295 /* Clear */
296 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
297 }
298}
299
300#endif /* CONFIG_SH_KGDB */ 220#endif /* CONFIG_SH_KGDB */
301 221
302#if defined(__H8300S__) 222#if defined(__H8300S__)
303enum { sci_disable, sci_enable }; 223enum { sci_disable, sci_enable };
304 224
305static void h8300_sci_enable(struct uart_port* port, unsigned int ctrl) 225static void h8300_sci_config(struct uart_port* port, unsigned int ctrl)
306{ 226{
307 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL; 227 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
308 int ch = (port->mapbase - SMR0) >> 3; 228 int ch = (port->mapbase - SMR0) >> 3;
@@ -314,32 +234,66 @@ static void h8300_sci_enable(struct uart_port* port, unsigned int ctrl)
314 *mstpcrl &= ~mask; 234 *mstpcrl &= ~mask;
315 } 235 }
316} 236}
237
238static inline void h8300_sci_enable(struct uart_port *port)
239{
240 h8300_sci_config(port, sci_enable);
241}
242
243static inline void h8300_sci_disable(struct uart_port *port)
244{
245 h8300_sci_config(port, sci_disable);
246}
317#endif 247#endif
318 248
319#if defined(SCI_ONLY) || defined(SCI_AND_SCIF) 249#if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
320#if defined(__H8300H__) || defined(__H8300S__) 250 defined(__H8300H__) || defined(__H8300S__)
321static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag) 251static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
322{ 252{
323 int ch = (port->mapbase - SMR0) >> 3; 253 int ch = (port->mapbase - SMR0) >> 3;
324 254
325 /* set DDR regs */ 255 /* set DDR regs */
326 H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].rx,H8300_GPIO_INPUT); 256 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
327 H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].tx,H8300_GPIO_OUTPUT); 257 h8300_sci_pins[ch].rx,
258 H8300_GPIO_INPUT);
259 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
260 h8300_sci_pins[ch].tx,
261 H8300_GPIO_OUTPUT);
262
328 /* tx mark output*/ 263 /* tx mark output*/
329 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; 264 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
330} 265}
266#else
267#define sci_init_pins_sci NULL
268#endif
269
270#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
271static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
272{
273 unsigned int fcr_val = 0;
274
275 if (cflag & CRTSCTS)
276 fcr_val |= SCFCR_MCE;
277
278 sci_out(port, SCFCR, fcr_val);
279}
280#else
281#define sci_init_pins_irda NULL
331#endif 282#endif
283
284#ifdef SCI_ONLY
285#define sci_init_pins_scif NULL
332#endif 286#endif
333 287
334#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF) 288#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
335#if defined(CONFIG_CPU_SUBTYPE_SH7300) 289#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
336/* SH7300 doesn't use RTS/CTS */ 290/* SH7300 doesn't use RTS/CTS */
337static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 291static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
338{ 292{
339 sci_out(port, SCFCR, 0); 293 sci_out(port, SCFCR, 0);
340} 294}
341#elif defined(CONFIG_CPU_SH3) 295#elif defined(CONFIG_CPU_SH3)
342/* For SH7705, SH7707, SH7709, SH7709A, SH7729 */ 296/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
343static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 297static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
344{ 298{
345 unsigned int fcr_val = 0; 299 unsigned int fcr_val = 0;
@@ -366,20 +320,7 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
366 320
367 sci_out(port, SCFCR, fcr_val); 321 sci_out(port, SCFCR, fcr_val);
368} 322}
369
370#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
371static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
372{
373 unsigned int fcr_val = 0;
374
375 if (cflag & CRTSCTS)
376 fcr_val |= SCFCR_MCE;
377
378 sci_out(port, SCFCR, fcr_val);
379}
380#endif
381#else 323#else
382
383/* For SH7750 */ 324/* For SH7750 */
384static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 325static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
385{ 326{
@@ -388,7 +329,9 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
388 if (cflag & CRTSCTS) { 329 if (cflag & CRTSCTS) {
389 fcr_val |= SCFCR_MCE; 330 fcr_val |= SCFCR_MCE;
390 } else { 331 } else {
391#ifdef CONFIG_CPU_SUBTYPE_SH7780 332#ifdef CONFIG_CPU_SUBTYPE_SH7343
333 /* Nothing */
334#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
392 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */ 335 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
393#else 336#else
394 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */ 337 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
@@ -396,10 +339,41 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
396 } 339 }
397 sci_out(port, SCFCR, fcr_val); 340 sci_out(port, SCFCR, fcr_val);
398} 341}
342#endif
343
344#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
345static inline int scif_txroom(struct uart_port *port)
346{
347 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
348}
349
350static inline int scif_rxroom(struct uart_port *port)
351{
352 return sci_in(port, SCRFDR) & 0x7f;
353}
354#else
355static inline int scif_txroom(struct uart_port *port)
356{
357 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
358}
399 359
360static inline int scif_rxroom(struct uart_port *port)
361{
362 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
363}
400#endif 364#endif
401#endif /* SCIF_ONLY || SCI_AND_SCIF */ 365#endif /* SCIF_ONLY || SCI_AND_SCIF */
402 366
367static inline int sci_txroom(struct uart_port *port)
368{
369 return ((sci_in(port, SCxSR) & SCI_TDRE) != 0);
370}
371
372static inline int sci_rxroom(struct uart_port *port)
373{
374 return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0);
375}
376
403/* ********************************************************************** * 377/* ********************************************************************** *
404 * the interrupt related routines * 378 * the interrupt related routines *
405 * ********************************************************************** */ 379 * ********************************************************************** */
@@ -408,14 +382,12 @@ static void sci_transmit_chars(struct uart_port *port)
408{ 382{
409 struct circ_buf *xmit = &port->info->xmit; 383 struct circ_buf *xmit = &port->info->xmit;
410 unsigned int stopped = uart_tx_stopped(port); 384 unsigned int stopped = uart_tx_stopped(port);
411 unsigned long flags;
412 unsigned short status; 385 unsigned short status;
413 unsigned short ctrl; 386 unsigned short ctrl;
414 int count, txroom; 387 int count;
415 388
416 status = sci_in(port, SCxSR); 389 status = sci_in(port, SCxSR);
417 if (!(status & SCxSR_TDxE(port))) { 390 if (!(status & SCxSR_TDxE(port))) {
418 local_irq_save(flags);
419 ctrl = sci_in(port, SCSCR); 391 ctrl = sci_in(port, SCSCR);
420 if (uart_circ_empty(xmit)) { 392 if (uart_circ_empty(xmit)) {
421 ctrl &= ~SCI_CTRL_FLAGS_TIE; 393 ctrl &= ~SCI_CTRL_FLAGS_TIE;
@@ -423,25 +395,15 @@ static void sci_transmit_chars(struct uart_port *port)
423 ctrl |= SCI_CTRL_FLAGS_TIE; 395 ctrl |= SCI_CTRL_FLAGS_TIE;
424 } 396 }
425 sci_out(port, SCSCR, ctrl); 397 sci_out(port, SCSCR, ctrl);
426 local_irq_restore(flags);
427 return; 398 return;
428 } 399 }
429 400
430#if !defined(SCI_ONLY) 401#ifndef SCI_ONLY
431 if (port->type == PORT_SCIF) { 402 if (port->type == PORT_SCIF)
432#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780) 403 count = scif_txroom(port);
433 txroom = SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f); 404 else
434#else
435 txroom = SCIF_TXROOM_MAX - (sci_in(port, SCFDR)>>8);
436#endif
437 } else {
438 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
439 }
440#else
441 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
442#endif 405#endif
443 406 count = sci_txroom(port);
444 count = txroom;
445 407
446 do { 408 do {
447 unsigned char c; 409 unsigned char c;
@@ -468,7 +430,6 @@ static void sci_transmit_chars(struct uart_port *port)
468 if (uart_circ_empty(xmit)) { 430 if (uart_circ_empty(xmit)) {
469 sci_stop_tx(port); 431 sci_stop_tx(port);
470 } else { 432 } else {
471 local_irq_save(flags);
472 ctrl = sci_in(port, SCSCR); 433 ctrl = sci_in(port, SCSCR);
473 434
474#if !defined(SCI_ONLY) 435#if !defined(SCI_ONLY)
@@ -480,7 +441,6 @@ static void sci_transmit_chars(struct uart_port *port)
480 441
481 ctrl |= SCI_CTRL_FLAGS_TIE; 442 ctrl |= SCI_CTRL_FLAGS_TIE;
482 sci_out(port, SCSCR, ctrl); 443 sci_out(port, SCSCR, ctrl);
483 local_irq_restore(flags);
484 } 444 }
485} 445}
486 446
@@ -490,6 +450,7 @@ static void sci_transmit_chars(struct uart_port *port)
490static inline void sci_receive_chars(struct uart_port *port, 450static inline void sci_receive_chars(struct uart_port *port,
491 struct pt_regs *regs) 451 struct pt_regs *regs)
492{ 452{
453 struct sci_port *sci_port = (struct sci_port *)port;
493 struct tty_struct *tty = port->info->tty; 454 struct tty_struct *tty = port->info->tty;
494 int i, count, copied = 0; 455 int i, count, copied = 0;
495 unsigned short status; 456 unsigned short status;
@@ -501,18 +462,11 @@ static inline void sci_receive_chars(struct uart_port *port,
501 462
502 while (1) { 463 while (1) {
503#if !defined(SCI_ONLY) 464#if !defined(SCI_ONLY)
504 if (port->type == PORT_SCIF) { 465 if (port->type == PORT_SCIF)
505#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780) 466 count = scif_rxroom(port);
506 count = sci_in(port, SCRFDR) & 0x7f; 467 else
507#else
508 count = sci_in(port, SCFDR)&SCIF_RFDC_MASK ;
509#endif
510 } else {
511 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
512 }
513#else
514 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
515#endif 468#endif
469 count = sci_rxroom(port);
516 470
517 /* Don't copy more bytes than there is room for in the buffer */ 471 /* Don't copy more bytes than there is room for in the buffer */
518 count = tty_buffer_request_room(tty, count); 472 count = tty_buffer_request_room(tty, count);
@@ -523,11 +477,10 @@ static inline void sci_receive_chars(struct uart_port *port,
523 477
524 if (port->type == PORT_SCI) { 478 if (port->type == PORT_SCI) {
525 char c = sci_in(port, SCxRDR); 479 char c = sci_in(port, SCxRDR);
526 if(((struct sci_port *)port)->break_flag 480 if (uart_handle_sysrq_char(port, c, regs) || sci_port->break_flag)
527 || uart_handle_sysrq_char(port, c, regs)) {
528 count = 0; 481 count = 0;
529 } else { 482 else {
530 tty_insert_flip_char(tty, c, TTY_NORMAL); 483 tty_insert_flip_char(tty, c, TTY_NORMAL);
531 } 484 }
532 } else { 485 } else {
533 for (i=0; i<count; i++) { 486 for (i=0; i<count; i++) {
@@ -535,15 +488,17 @@ static inline void sci_receive_chars(struct uart_port *port,
535 status = sci_in(port, SCxSR); 488 status = sci_in(port, SCxSR);
536#if defined(CONFIG_CPU_SH3) 489#if defined(CONFIG_CPU_SH3)
537 /* Skip "chars" during break */ 490 /* Skip "chars" during break */
538 if (((struct sci_port *)port)->break_flag) { 491 if (sci_port->break_flag) {
539 if ((c == 0) && 492 if ((c == 0) &&
540 (status & SCxSR_FER(port))) { 493 (status & SCxSR_FER(port))) {
541 count--; i--; 494 count--; i--;
542 continue; 495 continue;
543 } 496 }
497
544 /* Nonzero => end-of-break */ 498 /* Nonzero => end-of-break */
545 pr_debug("scif: debounce<%02x>\n", c); 499 pr_debug("scif: debounce<%02x>\n", c);
546 ((struct sci_port *)port)->break_flag = 0; 500 sci_port->break_flag = 0;
501
547 if (STEPFN(c)) { 502 if (STEPFN(c)) {
548 count--; i--; 503 count--; i--;
549 continue; 504 continue;
@@ -600,15 +555,17 @@ static void sci_schedule_break_timer(struct sci_port *port)
600/* Ensure that two consecutive samples find the break over. */ 555/* Ensure that two consecutive samples find the break over. */
601static void sci_break_timer(unsigned long data) 556static void sci_break_timer(unsigned long data)
602{ 557{
603 struct sci_port * port = (struct sci_port *)data; 558 struct sci_port *port = (struct sci_port *)data;
604 if(sci_rxd_in(&port->port) == 0) { 559
560 if (sci_rxd_in(&port->port) == 0) {
605 port->break_flag = 1; 561 port->break_flag = 1;
606 sci_schedule_break_timer(port); 562 sci_schedule_break_timer(port);
607 } else if(port->break_flag == 1){ 563 } else if (port->break_flag == 1) {
608 /* break is over. */ 564 /* break is over. */
609 port->break_flag = 2; 565 port->break_flag = 2;
610 sci_schedule_break_timer(port); 566 sci_schedule_break_timer(port);
611 } else port->break_flag = 0; 567 } else
568 port->break_flag = 0;
612} 569}
613 570
614static inline int sci_handle_errors(struct uart_port *port) 571static inline int sci_handle_errors(struct uart_port *port)
@@ -617,40 +574,41 @@ static inline int sci_handle_errors(struct uart_port *port)
617 unsigned short status = sci_in(port, SCxSR); 574 unsigned short status = sci_in(port, SCxSR);
618 struct tty_struct *tty = port->info->tty; 575 struct tty_struct *tty = port->info->tty;
619 576
620 if (status&SCxSR_ORER(port)) { 577 if (status & SCxSR_ORER(port)) {
621 /* overrun error */ 578 /* overrun error */
622 if(tty_insert_flip_char(tty, 0, TTY_OVERRUN)) 579 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
623 copied++; 580 copied++;
624 pr_debug("sci: overrun error\n"); 581 pr_debug("sci: overrun error\n");
625 } 582 }
626 583
627 if (status&SCxSR_FER(port)) { 584 if (status & SCxSR_FER(port)) {
628 if (sci_rxd_in(port) == 0) { 585 if (sci_rxd_in(port) == 0) {
629 /* Notify of BREAK */ 586 /* Notify of BREAK */
630 struct sci_port * sci_port = (struct sci_port *)port; 587 struct sci_port *sci_port = (struct sci_port *)port;
631 if(!sci_port->break_flag) { 588
632 sci_port->break_flag = 1; 589 if (!sci_port->break_flag) {
633 sci_schedule_break_timer((struct sci_port *)port); 590 sci_port->break_flag = 1;
591 sci_schedule_break_timer(sci_port);
592
634 /* Do sysrq handling. */ 593 /* Do sysrq handling. */
635 if(uart_handle_break(port)) 594 if (uart_handle_break(port))
636 return 0; 595 return 0;
637 pr_debug("sci: BREAK detected\n"); 596 pr_debug("sci: BREAK detected\n");
638 if(tty_insert_flip_char(tty, 0, TTY_BREAK)) 597 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
639 copied++; 598 copied++;
640 } 599 }
641 } 600 } else {
642 else {
643 /* frame error */ 601 /* frame error */
644 if(tty_insert_flip_char(tty, 0, TTY_FRAME)) 602 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
645 copied++; 603 copied++;
646 pr_debug("sci: frame error\n"); 604 pr_debug("sci: frame error\n");
647 } 605 }
648 } 606 }
649 607
650 if (status&SCxSR_PER(port)) { 608 if (status & SCxSR_PER(port)) {
651 if(tty_insert_flip_char(tty, 0, TTY_PARITY))
652 copied++;
653 /* parity error */ 609 /* parity error */
610 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
611 copied++;
654 pr_debug("sci: parity error\n"); 612 pr_debug("sci: parity error\n");
655 } 613 }
656 614
@@ -673,7 +631,7 @@ static inline int sci_handle_breaks(struct uart_port *port)
673 s->break_flag = 1; 631 s->break_flag = 1;
674#endif 632#endif
675 /* Notify of BREAK */ 633 /* Notify of BREAK */
676 if(tty_insert_flip_char(tty, 0, TTY_BREAK)) 634 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
677 copied++; 635 copied++;
678 pr_debug("sci: BREAK detected\n"); 636 pr_debug("sci: BREAK detected\n");
679 } 637 }
@@ -682,7 +640,7 @@ static inline int sci_handle_breaks(struct uart_port *port)
682 /* XXX: Handle SCIF overrun error */ 640 /* XXX: Handle SCIF overrun error */
683 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) { 641 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
684 sci_out(port, SCLSR, 0); 642 sci_out(port, SCLSR, 0);
685 if(tty_insert_flip_char(tty, 0, TTY_OVERRUN)) { 643 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
686 copied++; 644 copied++;
687 pr_debug("sci: overrun error\n"); 645 pr_debug("sci: overrun error\n");
688 } 646 }
@@ -691,13 +649,12 @@ static inline int sci_handle_breaks(struct uart_port *port)
691 649
692 if (copied) 650 if (copied)
693 tty_flip_buffer_push(tty); 651 tty_flip_buffer_push(tty);
652
694 return copied; 653 return copied;
695} 654}
696 655
697static irqreturn_t sci_rx_interrupt(int irq, void *ptr, struct pt_regs *regs) 656static irqreturn_t sci_rx_interrupt(int irq, void *port, struct pt_regs *regs)
698{ 657{
699 struct uart_port *port = ptr;
700
701 /* I think sci_receive_chars has to be called irrespective 658 /* I think sci_receive_chars has to be called irrespective
702 * of whether the I_IXOFF is set, otherwise, how is the interrupt 659 * of whether the I_IXOFF is set, otherwise, how is the interrupt
703 * to be disabled? 660 * to be disabled?
@@ -711,7 +668,9 @@ static irqreturn_t sci_tx_interrupt(int irq, void *ptr, struct pt_regs *regs)
711{ 668{
712 struct uart_port *port = ptr; 669 struct uart_port *port = ptr;
713 670
671 spin_lock_irq(&port->lock);
714 sci_transmit_chars(port); 672 sci_transmit_chars(port);
673 spin_unlock_irq(&port->lock);
715 674
716 return IRQ_HANDLED; 675 return IRQ_HANDLED;
717} 676}
@@ -755,6 +714,12 @@ static irqreturn_t sci_br_interrupt(int irq, void *ptr, struct pt_regs *regs)
755 714
756 /* Handle BREAKs */ 715 /* Handle BREAKs */
757 sci_handle_breaks(port); 716 sci_handle_breaks(port);
717
718#ifdef CONFIG_SH_KGDB
719 /* Break into the debugger if a break is detected */
720 BREAKPOINT();
721#endif
722
758 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); 723 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
759 724
760 return IRQ_HANDLED; 725 return IRQ_HANDLED;
@@ -769,16 +734,16 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr, struct pt_regs *regs)
769 scr_status = sci_in(port,SCSCR); 734 scr_status = sci_in(port,SCSCR);
770 735
771 /* Tx Interrupt */ 736 /* Tx Interrupt */
772 if ((ssr_status&0x0020) && (scr_status&0x0080)) 737 if ((ssr_status & 0x0020) && (scr_status & 0x0080))
773 sci_tx_interrupt(irq, ptr, regs); 738 sci_tx_interrupt(irq, ptr, regs);
774 /* Rx Interrupt */ 739 /* Rx Interrupt */
775 if ((ssr_status&0x0002) && (scr_status&0x0040)) 740 if ((ssr_status & 0x0002) && (scr_status & 0x0040))
776 sci_rx_interrupt(irq, ptr, regs); 741 sci_rx_interrupt(irq, ptr, regs);
777 /* Error Interrupt */ 742 /* Error Interrupt */
778 if ((ssr_status&0x0080) && (scr_status&0x0400)) 743 if ((ssr_status & 0x0080) && (scr_status & 0x0400))
779 sci_er_interrupt(irq, ptr, regs); 744 sci_er_interrupt(irq, ptr, regs);
780 /* Break Interrupt */ 745 /* Break Interrupt */
781 if ((ssr_status&0x0010) && (scr_status&0x0200)) 746 if ((ssr_status & 0x0010) && (scr_status & 0x0200))
782 sci_br_interrupt(irq, ptr, regs); 747 sci_br_interrupt(irq, ptr, regs);
783 748
784 return IRQ_HANDLED; 749 return IRQ_HANDLED;
@@ -789,7 +754,8 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr, struct pt_regs *regs)
789 * Here we define a transistion notifier so that we can update all of our 754 * Here we define a transistion notifier so that we can update all of our
790 * ports' baud rate when the peripheral clock changes. 755 * ports' baud rate when the peripheral clock changes.
791 */ 756 */
792static int sci_notifier(struct notifier_block *self, unsigned long phase, void *p) 757static int sci_notifier(struct notifier_block *self,
758 unsigned long phase, void *p)
793{ 759{
794 struct cpufreq_freqs *freqs = p; 760 struct cpufreq_freqs *freqs = p;
795 int i; 761 int i;
@@ -816,8 +782,9 @@ static int sci_notifier(struct notifier_block *self, unsigned long phase, void *
816 clk_put(clk); 782 clk_put(clk);
817 } 783 }
818 784
819 printk("%s: got a postchange notification for cpu %d (old %d, new %d)\n", 785 printk(KERN_INFO "%s: got a postchange notification "
820 __FUNCTION__, freqs->cpu, freqs->old, freqs->new); 786 "for cpu %d (old %d, new %d)\n",
787 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
821 } 788 }
822 789
823 return NOTIFY_OK; 790 return NOTIFY_OK;
@@ -841,8 +808,9 @@ static int sci_request_irq(struct sci_port *port)
841 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n"); 808 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
842 return -ENODEV; 809 return -ENODEV;
843 } 810 }
844 if (request_irq(port->irqs[0], sci_mpxed_interrupt, IRQF_DISABLED, 811
845 "sci", port)) { 812 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
813 SA_INTERRUPT, "sci", port)) {
846 printk(KERN_ERR "sci: Cannot allocate irq.\n"); 814 printk(KERN_ERR "sci: Cannot allocate irq.\n");
847 return -ENODEV; 815 return -ENODEV;
848 } 816 }
@@ -850,8 +818,8 @@ static int sci_request_irq(struct sci_port *port)
850 for (i = 0; i < ARRAY_SIZE(handlers); i++) { 818 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
851 if (!port->irqs[i]) 819 if (!port->irqs[i])
852 continue; 820 continue;
853 if (request_irq(port->irqs[i], handlers[i], IRQF_DISABLED, 821 if (request_irq(port->irqs[i], handlers[i],
854 desc[i], port)) { 822 SA_INTERRUPT, desc[i], port)) {
855 printk(KERN_ERR "sci: Cannot allocate irq.\n"); 823 printk(KERN_ERR "sci: Cannot allocate irq.\n");
856 return -ENODEV; 824 return -ENODEV;
857 } 825 }
@@ -903,50 +871,42 @@ static unsigned int sci_get_mctrl(struct uart_port *port)
903 871
904static void sci_start_tx(struct uart_port *port) 872static void sci_start_tx(struct uart_port *port)
905{ 873{
906 struct sci_port *s = &sci_ports[port->line]; 874 unsigned short ctrl;
907 875
908 disable_irq(s->irqs[SCIx_TXI_IRQ]); 876 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
909 sci_transmit_chars(port); 877 ctrl = sci_in(port, SCSCR);
910 enable_irq(s->irqs[SCIx_TXI_IRQ]); 878 ctrl |= SCI_CTRL_FLAGS_TIE;
879 sci_out(port, SCSCR, ctrl);
911} 880}
912 881
913static void sci_stop_tx(struct uart_port *port) 882static void sci_stop_tx(struct uart_port *port)
914{ 883{
915 unsigned long flags;
916 unsigned short ctrl; 884 unsigned short ctrl;
917 885
918 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 886 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
919 local_irq_save(flags);
920 ctrl = sci_in(port, SCSCR); 887 ctrl = sci_in(port, SCSCR);
921 ctrl &= ~SCI_CTRL_FLAGS_TIE; 888 ctrl &= ~SCI_CTRL_FLAGS_TIE;
922 sci_out(port, SCSCR, ctrl); 889 sci_out(port, SCSCR, ctrl);
923 local_irq_restore(flags);
924} 890}
925 891
926static void sci_start_rx(struct uart_port *port, unsigned int tty_start) 892static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
927{ 893{
928 unsigned long flags;
929 unsigned short ctrl; 894 unsigned short ctrl;
930 895
931 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */ 896 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
932 local_irq_save(flags);
933 ctrl = sci_in(port, SCSCR); 897 ctrl = sci_in(port, SCSCR);
934 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE; 898 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
935 sci_out(port, SCSCR, ctrl); 899 sci_out(port, SCSCR, ctrl);
936 local_irq_restore(flags);
937} 900}
938 901
939static void sci_stop_rx(struct uart_port *port) 902static void sci_stop_rx(struct uart_port *port)
940{ 903{
941 unsigned long flags;
942 unsigned short ctrl; 904 unsigned short ctrl;
943 905
944 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */ 906 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
945 local_irq_save(flags);
946 ctrl = sci_in(port, SCSCR); 907 ctrl = sci_in(port, SCSCR);
947 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE); 908 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
948 sci_out(port, SCSCR, ctrl); 909 sci_out(port, SCSCR, ctrl);
949 local_irq_restore(flags);
950} 910}
951 911
952static void sci_enable_ms(struct uart_port *port) 912static void sci_enable_ms(struct uart_port *port)
@@ -963,9 +923,8 @@ static int sci_startup(struct uart_port *port)
963{ 923{
964 struct sci_port *s = &sci_ports[port->line]; 924 struct sci_port *s = &sci_ports[port->line];
965 925
966#if defined(__H8300S__) 926 if (s->enable)
967 h8300_sci_enable(port, sci_enable); 927 s->enable(port);
968#endif
969 928
970 sci_request_irq(s); 929 sci_request_irq(s);
971 sci_start_tx(port); 930 sci_start_tx(port);
@@ -982,9 +941,8 @@ static void sci_shutdown(struct uart_port *port)
982 sci_stop_tx(port); 941 sci_stop_tx(port);
983 sci_free_irq(s); 942 sci_free_irq(s);
984 943
985#if defined(__H8300S__) 944 if (s->disable)
986 h8300_sci_enable(port, sci_disable); 945 s->disable(port);
987#endif
988} 946}
989 947
990static void sci_set_termios(struct uart_port *port, struct termios *termios, 948static void sci_set_termios(struct uart_port *port, struct termios *termios,
@@ -997,6 +955,23 @@ static void sci_set_termios(struct uart_port *port, struct termios *termios,
997 955
998 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 956 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
999 957
958 switch (baud) {
959 case 0:
960 t = -1;
961 break;
962 default:
963 {
964#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
965 struct clk *clk = clk_get("module_clk");
966 t = SCBRR_VALUE(baud, clk_get_rate(clk));
967 clk_put(clk);
968#else
969 t = SCBRR_VALUE(baud);
970#endif
971 }
972 break;
973 }
974
1000 spin_lock_irqsave(&port->lock, flags); 975 spin_lock_irqsave(&port->lock, flags);
1001 976
1002 do { 977 do {
@@ -1006,9 +981,8 @@ static void sci_set_termios(struct uart_port *port, struct termios *termios,
1006 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 981 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1007 982
1008#if !defined(SCI_ONLY) 983#if !defined(SCI_ONLY)
1009 if (port->type == PORT_SCIF) { 984 if (port->type == PORT_SCIF)
1010 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 985 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1011 }
1012#endif 986#endif
1013 987
1014 smr_val = sci_in(port, SCSMR) & 3; 988 smr_val = sci_in(port, SCSMR) & 3;
@@ -1025,23 +999,6 @@ static void sci_set_termios(struct uart_port *port, struct termios *termios,
1025 999
1026 sci_out(port, SCSMR, smr_val); 1000 sci_out(port, SCSMR, smr_val);
1027 1001
1028 switch (baud) {
1029 case 0:
1030 t = -1;
1031 break;
1032 default:
1033 {
1034#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1035 struct clk *clk = clk_get("module_clk");
1036 t = SCBRR_VALUE(baud, clk_get_rate(clk));
1037 clk_put(clk);
1038#else
1039 t = SCBRR_VALUE(baud);
1040#endif
1041 }
1042 break;
1043 }
1044
1045 if (t > 0) { 1002 if (t > 0) {
1046 if(t >= 256) { 1003 if(t >= 256) {
1047 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); 1004 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
@@ -1092,11 +1049,23 @@ static void sci_config_port(struct uart_port *port, int flags)
1092 1049
1093 port->type = s->type; 1050 port->type = s->type;
1094 1051
1052 switch (port->type) {
1053 case PORT_SCI:
1054 s->init_pins = sci_init_pins_sci;
1055 break;
1056 case PORT_SCIF:
1057 s->init_pins = sci_init_pins_scif;
1058 break;
1059 case PORT_IRDA:
1060 s->init_pins = sci_init_pins_irda;
1061 break;
1062 }
1063
1095#if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 1064#if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1096 if (port->mapbase == 0) 1065 if (port->mapbase == 0)
1097 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF"); 1066 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1098 1067
1099 port->membase = (void *)port->mapbase; 1068 port->membase = (void __iomem *)port->mapbase;
1100#endif 1069#endif
1101} 1070}
1102 1071
@@ -1132,412 +1101,61 @@ static struct uart_ops sci_uart_ops = {
1132 .verify_port = sci_verify_port, 1101 .verify_port = sci_verify_port,
1133}; 1102};
1134 1103
1135static struct sci_port sci_ports[] = { 1104static void __init sci_init_ports(void)
1136#if defined(CONFIG_CPU_SUBTYPE_SH7708) 1105{
1137 { 1106 static int first = 1;
1138 .port = { 1107 int i;
1139 .membase = (void *)0xfffffe80, 1108
1140 .mapbase = 0xfffffe80, 1109 if (!first)
1141 .iotype = UPIO_MEM, 1110 return;
1142 .irq = 25, 1111
1143 .ops = &sci_uart_ops, 1112 first = 0;
1144 .flags = UPF_BOOT_AUTOCONF, 1113
1145 .line = 0, 1114 for (i = 0; i < SCI_NPORTS; i++) {
1146 }, 1115 sci_ports[i].port.ops = &sci_uart_ops;
1147 .type = PORT_SCI, 1116 sci_ports[i].port.iotype = UPIO_MEM;
1148 .irqs = SCI_IRQS, 1117 sci_ports[i].port.line = i;
1149 }, 1118 sci_ports[i].port.fifosize = 1;
1150#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 1119
1151 { 1120#if defined(__H8300H__) || defined(__H8300S__)
1152 .port = { 1121#ifdef __H8300S__
1153 .membase = (void *)SCIF0, 1122 sci_ports[i].enable = h8300_sci_enable;
1154 .mapbase = SCIF0, 1123 sci_ports[i].disable = h8300_sci_disable;
1155 .iotype = UPIO_MEM, 1124#endif
1156 .irq = 55, 1125 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1157 .ops = &sci_uart_ops, 1126#elif defined(CONFIG_SUPERH64)
1158 .flags = UPF_BOOT_AUTOCONF, 1127 sci_ports[i].port.uartclk = current_cpu_data.module_clock * 16;
1159 .line = 0,
1160 },
1161 .type = PORT_SCIF,
1162 .irqs = SH3_IRDA_IRQS,
1163 .init_pins = sci_init_pins_scif,
1164 },
1165 {
1166 .port = {
1167 .membase = (void *)SCIF2,
1168 .mapbase = SCIF2,
1169 .iotype = UPIO_MEM,
1170 .irq = 59,
1171 .ops = &sci_uart_ops,
1172 .flags = UPF_BOOT_AUTOCONF,
1173 .line = 1,
1174 },
1175 .type = PORT_SCIF,
1176 .irqs = SH3_SCIF_IRQS,
1177 .init_pins = sci_init_pins_scif,
1178 }
1179#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
1180 {
1181 .port = {
1182 .membase = (void *)0xfffffe80,
1183 .mapbase = 0xfffffe80,
1184 .iotype = UPIO_MEM,
1185 .irq = 25,
1186 .ops = &sci_uart_ops,
1187 .flags = UPF_BOOT_AUTOCONF,
1188 .line = 0,
1189 },
1190 .type = PORT_SCI,
1191 .irqs = SCI_IRQS,
1192 },
1193 {
1194 .port = {
1195 .membase = (void *)0xa4000150,
1196 .mapbase = 0xa4000150,
1197 .iotype = UPIO_MEM,
1198 .irq = 59,
1199 .ops = &sci_uart_ops,
1200 .flags = UPF_BOOT_AUTOCONF,
1201 .line = 1,
1202 },
1203 .type = PORT_SCIF,
1204 .irqs = SH3_SCIF_IRQS,
1205 .init_pins = sci_init_pins_scif,
1206 },
1207 {
1208 .port = {
1209 .membase = (void *)0xa4000140,
1210 .mapbase = 0xa4000140,
1211 .iotype = UPIO_MEM,
1212 .irq = 55,
1213 .ops = &sci_uart_ops,
1214 .flags = UPF_BOOT_AUTOCONF,
1215 .line = 2,
1216 },
1217 .type = PORT_IRDA,
1218 .irqs = SH3_IRDA_IRQS,
1219 .init_pins = sci_init_pins_irda,
1220 }
1221#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
1222 {
1223 .port = {
1224 .membase = (void *)0xA4430000,
1225 .mapbase = 0xA4430000,
1226 .iotype = UPIO_MEM,
1227 .irq = 25,
1228 .ops = &sci_uart_ops,
1229 .flags = UPF_BOOT_AUTOCONF,
1230 .line = 0,
1231 },
1232 .type = PORT_SCIF,
1233 .irqs = SH7300_SCIF0_IRQS,
1234 .init_pins = sci_init_pins_scif,
1235 },
1236#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
1237 {
1238 .port = {
1239 .membase = (void *)0xffe00000,
1240 .mapbase = 0xffe00000,
1241 .iotype = UPIO_MEM,
1242 .irq = 25,
1243 .ops = &sci_uart_ops,
1244 .flags = UPF_BOOT_AUTOCONF,
1245 .line = 0,
1246 },
1247 .type = PORT_SCIF,
1248 .irqs = SH73180_SCIF_IRQS,
1249 .init_pins = sci_init_pins_scif,
1250 },
1251#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1252 {
1253 .port = {
1254 .membase = (void *)0xffe80000,
1255 .mapbase = 0xffe80000,
1256 .iotype = UPIO_MEM,
1257 .irq = 43,
1258 .ops = &sci_uart_ops,
1259 .flags = UPF_BOOT_AUTOCONF,
1260 .line = 0,
1261 },
1262 .type = PORT_SCIF,
1263 .irqs = SH4_SCIF_IRQS,
1264 .init_pins = sci_init_pins_scif,
1265 },
1266#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
1267 {
1268 .port = {
1269 .membase = (void *)0xffe00000,
1270 .mapbase = 0xffe00000,
1271 .iotype = UPIO_MEM,
1272 .irq = 25,
1273 .ops = &sci_uart_ops,
1274 .flags = UPF_BOOT_AUTOCONF,
1275 .line = 0,
1276 },
1277 .type = PORT_SCI,
1278 .irqs = SCI_IRQS,
1279 },
1280 {
1281 .port = {
1282 .membase = (void *)0xffe80000,
1283 .mapbase = 0xffe80000,
1284 .iotype = UPIO_MEM,
1285 .irq = 43,
1286 .ops = &sci_uart_ops,
1287 .flags = UPF_BOOT_AUTOCONF,
1288 .line = 1,
1289 },
1290 .type = PORT_SCIF,
1291 .irqs = SH4_SCIF_IRQS,
1292 .init_pins = sci_init_pins_scif,
1293 },
1294#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
1295 {
1296 .port = {
1297 .membase = (void *)0xfe600000,
1298 .mapbase = 0xfe600000,
1299 .iotype = UPIO_MEM,
1300 .irq = 55,
1301 .ops = &sci_uart_ops,
1302 .flags = UPF_BOOT_AUTOCONF,
1303 .line = 0,
1304 },
1305 .type = PORT_SCIF,
1306 .irqs = SH7760_SCIF0_IRQS,
1307 .init_pins = sci_init_pins_scif,
1308 },
1309 {
1310 .port = {
1311 .membase = (void *)0xfe610000,
1312 .mapbase = 0xfe610000,
1313 .iotype = UPIO_MEM,
1314 .irq = 75,
1315 .ops = &sci_uart_ops,
1316 .flags = UPF_BOOT_AUTOCONF,
1317 .line = 1,
1318 },
1319 .type = PORT_SCIF,
1320 .irqs = SH7760_SCIF1_IRQS,
1321 .init_pins = sci_init_pins_scif,
1322 },
1323 {
1324 .port = {
1325 .membase = (void *)0xfe620000,
1326 .mapbase = 0xfe620000,
1327 .iotype = UPIO_MEM,
1328 .irq = 79,
1329 .ops = &sci_uart_ops,
1330 .flags = UPF_BOOT_AUTOCONF,
1331 .line = 2,
1332 },
1333 .type = PORT_SCIF,
1334 .irqs = SH7760_SCIF2_IRQS,
1335 .init_pins = sci_init_pins_scif,
1336 },
1337#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
1338 {
1339 .port = {
1340 .membase = (void *)0xffe00000,
1341 .mapbase = 0xffe00000,
1342 .iotype = UPIO_MEM,
1343 .irq = 26,
1344 .ops = &sci_uart_ops,
1345 .flags = UPF_BOOT_AUTOCONF,
1346 .line = 0,
1347 },
1348 .type = PORT_SCIF,
1349 .irqs = STB1_SCIF1_IRQS,
1350 .init_pins = sci_init_pins_scif,
1351 },
1352 {
1353 .port = {
1354 .membase = (void *)0xffe80000,
1355 .mapbase = 0xffe80000,
1356 .iotype = UPIO_MEM,
1357 .irq = 43,
1358 .ops = &sci_uart_ops,
1359 .flags = UPF_BOOT_AUTOCONF,
1360 .line = 1,
1361 },
1362 .type = PORT_SCIF,
1363 .irqs = SH4_SCIF_IRQS,
1364 .init_pins = sci_init_pins_scif,
1365 },
1366#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1367 {
1368 .port = {
1369 .iotype = UPIO_MEM,
1370 .irq = 42,
1371 .ops = &sci_uart_ops,
1372 .flags = UPF_BOOT_AUTOCONF,
1373 .line = 0,
1374 },
1375 .type = PORT_SCIF,
1376 .irqs = SH5_SCIF_IRQS,
1377 .init_pins = sci_init_pins_scif,
1378 },
1379#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1380 {
1381 .port = {
1382 .membase = (void *)0x00ffffb0,
1383 .mapbase = 0x00ffffb0,
1384 .iotype = UPIO_MEM,
1385 .irq = 54,
1386 .ops = &sci_uart_ops,
1387 .flags = UPF_BOOT_AUTOCONF,
1388 .line = 0,
1389 },
1390 .type = PORT_SCI,
1391 .irqs = H8300H_SCI_IRQS0,
1392 .init_pins = sci_init_pins_sci,
1393 },
1394 {
1395 .port = {
1396 .membase = (void *)0x00ffffb8,
1397 .mapbase = 0x00ffffb8,
1398 .iotype = UPIO_MEM,
1399 .irq = 58,
1400 .ops = &sci_uart_ops,
1401 .flags = UPF_BOOT_AUTOCONF,
1402 .line = 1,
1403 },
1404 .type = PORT_SCI,
1405 .irqs = H8300H_SCI_IRQS1,
1406 .init_pins = sci_init_pins_sci,
1407 },
1408 {
1409 .port = {
1410 .membase = (void *)0x00ffffc0,
1411 .mapbase = 0x00ffffc0,
1412 .iotype = UPIO_MEM,
1413 .irq = 62,
1414 .ops = &sci_uart_ops,
1415 .flags = UPF_BOOT_AUTOCONF,
1416 .line = 2,
1417 },
1418 .type = PORT_SCI,
1419 .irqs = H8300H_SCI_IRQS2,
1420 .init_pins = sci_init_pins_sci,
1421 },
1422#elif defined(CONFIG_H8S2678)
1423 {
1424 .port = {
1425 .membase = (void *)0x00ffff78,
1426 .mapbase = 0x00ffff78,
1427 .iotype = UPIO_MEM,
1428 .irq = 90,
1429 .ops = &sci_uart_ops,
1430 .flags = UPF_BOOT_AUTOCONF,
1431 .line = 0,
1432 },
1433 .type = PORT_SCI,
1434 .irqs = H8S_SCI_IRQS0,
1435 .init_pins = sci_init_pins_sci,
1436 },
1437 {
1438 .port = {
1439 .membase = (void *)0x00ffff80,
1440 .mapbase = 0x00ffff80,
1441 .iotype = UPIO_MEM,
1442 .irq = 94,
1443 .ops = &sci_uart_ops,
1444 .flags = UPF_BOOT_AUTOCONF,
1445 .line = 1,
1446 },
1447 .type = PORT_SCI,
1448 .irqs = H8S_SCI_IRQS1,
1449 .init_pins = sci_init_pins_sci,
1450 },
1451 {
1452 .port = {
1453 .membase = (void *)0x00ffff88,
1454 .mapbase = 0x00ffff88,
1455 .iotype = UPIO_MEM,
1456 .irq = 98,
1457 .ops = &sci_uart_ops,
1458 .flags = UPF_BOOT_AUTOCONF,
1459 .line = 2,
1460 },
1461 .type = PORT_SCI,
1462 .irqs = H8S_SCI_IRQS2,
1463 .init_pins = sci_init_pins_sci,
1464 },
1465#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
1466 {
1467 .port = {
1468 .membase = (void *)0xff923000,
1469 .mapbase = 0xff923000,
1470 .iotype = UPIO_MEM,
1471 .irq = 61,
1472 .ops = &sci_uart_ops,
1473 .flags = UPF_BOOT_AUTOCONF,
1474 .line = 0,
1475 },
1476 .type = PORT_SCIF,
1477 .irqs = SH7770_SCIF0_IRQS,
1478 .init_pins = sci_init_pins_scif,
1479 },
1480 {
1481 .port = {
1482 .membase = (void *)0xff924000,
1483 .mapbase = 0xff924000,
1484 .iotype = UPIO_MEM,
1485 .irq = 62,
1486 .ops = &sci_uart_ops,
1487 .flags = UPF_BOOT_AUTOCONF,
1488 .line = 1,
1489 },
1490 .type = PORT_SCIF,
1491 .irqs = SH7770_SCIF1_IRQS,
1492 .init_pins = sci_init_pins_scif,
1493 },
1494 {
1495 .port = {
1496 .membase = (void *)0xff925000,
1497 .mapbase = 0xff925000,
1498 .iotype = UPIO_MEM,
1499 .irq = 63,
1500 .ops = &sci_uart_ops,
1501 .flags = UPF_BOOT_AUTOCONF,
1502 .line = 2,
1503 },
1504 .type = PORT_SCIF,
1505 .irqs = SH7770_SCIF2_IRQS,
1506 .init_pins = sci_init_pins_scif,
1507 },
1508#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
1509 {
1510 .port = {
1511 .membase = (void *)0xffe00000,
1512 .mapbase = 0xffe00000,
1513 .iotype = UPIO_MEM,
1514 .irq = 43,
1515 .ops = &sci_uart_ops,
1516 .flags = UPF_BOOT_AUTOCONF,
1517 .line = 0,
1518 },
1519 .type = PORT_SCIF,
1520 .irqs = SH7780_SCIF0_IRQS,
1521 .init_pins = sci_init_pins_scif,
1522 },
1523 {
1524 .port = {
1525 .membase = (void *)0xffe10000,
1526 .mapbase = 0xffe10000,
1527 .iotype = UPIO_MEM,
1528 .irq = 79,
1529 .ops = &sci_uart_ops,
1530 .flags = UPF_BOOT_AUTOCONF,
1531 .line = 1,
1532 },
1533 .type = PORT_SCIF,
1534 .irqs = SH7780_SCIF1_IRQS,
1535 .init_pins = sci_init_pins_scif,
1536 },
1537#else 1128#else
1538#error "CPU subtype not defined" 1129 /*
1130 * XXX: We should use a proper SCI/SCIF clock
1131 */
1132 {
1133 struct clk *clk = clk_get("module_clk");
1134 sci_ports[i].port.uartclk = clk_get_rate(clk) * 16;
1135 clk_put(clk);
1136 }
1539#endif 1137#endif
1540}; 1138
1139 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1140 sci_ports[i].break_timer.function = sci_break_timer;
1141
1142 init_timer(&sci_ports[i].break_timer);
1143 }
1144}
1145
1146int __init early_sci_setup(struct uart_port *port)
1147{
1148 if (unlikely(port->line > SCI_NPORTS))
1149 return -ENODEV;
1150
1151 sci_init_ports();
1152
1153 sci_ports[port->line].port.membase = port->membase;
1154 sci_ports[port->line].port.mapbase = port->mapbase;
1155 sci_ports[port->line].port.type = port->type;
1156
1157 return 0;
1158}
1541 1159
1542#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 1160#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1543/* 1161/*
@@ -1559,34 +1177,38 @@ static int __init serial_console_setup(struct console *co, char *options)
1559 int flow = 'n'; 1177 int flow = 'n';
1560 int ret; 1178 int ret;
1561 1179
1180 /*
1181 * Check whether an invalid uart number has been specified, and
1182 * if so, search for the first available port that does have
1183 * console support.
1184 */
1185 if (co->index >= SCI_NPORTS)
1186 co->index = 0;
1187
1562 serial_console_port = &sci_ports[co->index]; 1188 serial_console_port = &sci_ports[co->index];
1563 port = &serial_console_port->port; 1189 port = &serial_console_port->port;
1564 port->type = serial_console_port->type;
1565
1566#ifdef CONFIG_SUPERH64
1567 /* This is especially needed on sh64 to remap the SCIF */
1568 sci_config_port(port, 0);
1569#endif
1570 1190
1571 /* 1191 /*
1572 * We need to set the initial uartclk here, since otherwise it will 1192 * Also need to check port->type, we don't actually have any
1573 * only ever be setup at sci_init() time. 1193 * UPIO_PORT ports, but uart_report_port() handily misreports
1194 * it anyways if we don't have a port available by the time this is
1195 * called.
1574 */ 1196 */
1575#if defined(__H8300H__) || defined(__H8300S__) 1197 if (!port->type)
1576 port->uartclk = CONFIG_CPU_CLOCK; 1198 return -ENODEV;
1199 if (!port->membase || !port->mapbase)
1200 return -ENODEV;
1201
1202 spin_lock_init(&port->lock);
1203
1204 port->type = serial_console_port->type;
1205
1206 if (port->flags & UPF_IOREMAP)
1207 sci_config_port(port, 0);
1208
1209 if (serial_console_port->enable)
1210 serial_console_port->enable(port);
1577 1211
1578#if defined(__H8300S__)
1579 h8300_sci_enable(port, sci_enable);
1580#endif
1581#elif defined(CONFIG_SUPERH64)
1582 port->uartclk = current_cpu_data.module_clock * 16;
1583#else
1584 {
1585 struct clk *clk = clk_get("module_clk");
1586 port->uartclk = clk_get_rate(clk) * 16;
1587 clk_put(clk);
1588 }
1589#endif
1590 if (options) 1212 if (options)
1591 uart_parse_options(options, &baud, &parity, &bits, &flow); 1213 uart_parse_options(options, &baud, &parity, &bits, &flow);
1592 1214
@@ -1604,17 +1226,17 @@ static struct console serial_console = {
1604 .device = uart_console_device, 1226 .device = uart_console_device,
1605 .write = serial_console_write, 1227 .write = serial_console_write,
1606 .setup = serial_console_setup, 1228 .setup = serial_console_setup,
1607 .flags = CON_PRINTBUFFER, 1229 .flags = CON_PRINTBUFFER,
1608 .index = -1, 1230 .index = -1,
1609 .data = &sci_uart_driver, 1231 .data = &sci_uart_driver,
1610}; 1232};
1611 1233
1612static int __init sci_console_init(void) 1234static int __init sci_console_init(void)
1613{ 1235{
1236 sci_init_ports();
1614 register_console(&serial_console); 1237 register_console(&serial_console);
1615 return 0; 1238 return 0;
1616} 1239}
1617
1618console_initcall(sci_console_init); 1240console_initcall(sci_console_init);
1619#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 1241#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1620 1242
@@ -1649,6 +1271,8 @@ int __init kgdb_console_setup(struct console *co, char *options)
1649 int parity = 'n'; 1271 int parity = 'n';
1650 int flow = 'n'; 1272 int flow = 'n';
1651 1273
1274 spin_lock_init(&port->lock);
1275
1652 if (co->index != kgdb_portnum) 1276 if (co->index != kgdb_portnum)
1653 co->index = kgdb_portnum; 1277 co->index = kgdb_portnum;
1654 1278
@@ -1677,10 +1301,10 @@ static struct console kgdb_console = {
1677/* Register the KGDB console so we get messages (d'oh!) */ 1301/* Register the KGDB console so we get messages (d'oh!) */
1678static int __init kgdb_console_init(void) 1302static int __init kgdb_console_init(void)
1679{ 1303{
1304 sci_init_ports();
1680 register_console(&kgdb_console); 1305 register_console(&kgdb_console);
1681 return 0; 1306 return 0;
1682} 1307}
1683
1684console_initcall(kgdb_console_init); 1308console_initcall(kgdb_console_init);
1685#endif /* CONFIG_SH_KGDB_CONSOLE */ 1309#endif /* CONFIG_SH_KGDB_CONSOLE */
1686 1310
@@ -1701,60 +1325,132 @@ static struct uart_driver sci_uart_driver = {
1701 .dev_name = "ttySC", 1325 .dev_name = "ttySC",
1702 .major = SCI_MAJOR, 1326 .major = SCI_MAJOR,
1703 .minor = SCI_MINOR_START, 1327 .minor = SCI_MINOR_START,
1328 .nr = SCI_NPORTS,
1704 .cons = SCI_CONSOLE, 1329 .cons = SCI_CONSOLE,
1705}; 1330};
1706 1331
1707static int __init sci_init(void) 1332/*
1333 * Register a set of serial devices attached to a platform device. The
1334 * list is terminated with a zero flags entry, which means we expect
1335 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1336 * remapping (such as sh64) should also set UPF_IOREMAP.
1337 */
1338static int __devinit sci_probe(struct platform_device *dev)
1708{ 1339{
1709 int chan, ret; 1340 struct plat_sci_port *p = dev->dev.platform_data;
1341 int i;
1710 1342
1711 printk("%s", banner); 1343 for (i = 0; p && p->flags != 0 && i < SCI_NPORTS; p++, i++) {
1344 struct sci_port *sciport = &sci_ports[i];
1712 1345
1713 sci_uart_driver.nr = ARRAY_SIZE(sci_ports); 1346 sciport->port.mapbase = p->mapbase;
1714 1347
1715 ret = uart_register_driver(&sci_uart_driver); 1348 /*
1716 if (ret == 0) { 1349 * For the simple (and majority of) cases where we don't need
1717 for (chan = 0; chan < SCI_NPORTS; chan++) { 1350 * to do any remapping, just cast the cookie directly.
1718 struct sci_port *sciport = &sci_ports[chan]; 1351 */
1352 if (p->mapbase && !p->membase && !(p->flags & UPF_IOREMAP))
1353 p->membase = (void __iomem *)p->mapbase;
1719 1354
1720#if defined(__H8300H__) || defined(__H8300S__) 1355 sciport->port.membase = p->membase;
1721 sciport->port.uartclk = CONFIG_CPU_CLOCK; 1356
1722#elif defined(CONFIG_SUPERH64) 1357 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1723 sciport->port.uartclk = current_cpu_data.module_clock * 16; 1358 sciport->port.flags = p->flags;
1724#else 1359 sciport->port.dev = &dev->dev;
1725 struct clk *clk = clk_get("module_clk"); 1360
1726 sciport->port.uartclk = clk_get_rate(clk) * 16; 1361 sciport->type = sciport->port.type = p->type;
1727 clk_put(clk); 1362
1728#endif 1363 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1729 uart_add_one_port(&sci_uart_driver, &sciport->port); 1364
1730 sciport->break_timer.data = (unsigned long)sciport; 1365 uart_add_one_port(&sci_uart_driver, &sciport->port);
1731 sciport->break_timer.function = sci_break_timer;
1732 init_timer(&sciport->break_timer);
1733 }
1734 } 1366 }
1735 1367
1736#ifdef CONFIG_CPU_FREQ 1368#ifdef CONFIG_CPU_FREQ
1737 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER); 1369 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1738 printk("sci: CPU frequency notifier registered\n"); 1370 dev_info(&dev->dev, "sci: CPU frequency notifier registered\n");
1739#endif 1371#endif
1740 1372
1741#ifdef CONFIG_SH_STANDARD_BIOS 1373#ifdef CONFIG_SH_STANDARD_BIOS
1742 sh_bios_gdb_detach(); 1374 sh_bios_gdb_detach();
1743#endif 1375#endif
1744 1376
1745 return ret; 1377 return 0;
1746} 1378}
1747 1379
1748static void __exit sci_exit(void) 1380static int __devexit sci_remove(struct platform_device *dev)
1381{
1382 int i;
1383
1384 for (i = 0; i < SCI_NPORTS; i++)
1385 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1386
1387 return 0;
1388}
1389
1390static int sci_suspend(struct platform_device *dev, pm_message_t state)
1749{ 1391{
1750 int chan; 1392 int i;
1393
1394 for (i = 0; i < SCI_NPORTS; i++) {
1395 struct sci_port *p = &sci_ports[i];
1396
1397 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1398 uart_suspend_port(&sci_uart_driver, &p->port);
1399 }
1751 1400
1752 for (chan = 0; chan < SCI_NPORTS; chan++) 1401 return 0;
1753 uart_remove_one_port(&sci_uart_driver, &sci_ports[chan].port); 1402}
1754 1403
1404static int sci_resume(struct platform_device *dev)
1405{
1406 int i;
1407
1408 for (i = 0; i < SCI_NPORTS; i++) {
1409 struct sci_port *p = &sci_ports[i];
1410
1411 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1412 uart_resume_port(&sci_uart_driver, &p->port);
1413 }
1414
1415 return 0;
1416}
1417
1418static struct platform_driver sci_driver = {
1419 .probe = sci_probe,
1420 .remove = __devexit_p(sci_remove),
1421 .suspend = sci_suspend,
1422 .resume = sci_resume,
1423 .driver = {
1424 .name = "sh-sci",
1425 .owner = THIS_MODULE,
1426 },
1427};
1428
1429static int __init sci_init(void)
1430{
1431 int ret;
1432
1433 printk(banner);
1434
1435 sci_init_ports();
1436
1437 ret = uart_register_driver(&sci_uart_driver);
1438 if (likely(ret == 0)) {
1439 ret = platform_driver_register(&sci_driver);
1440 if (unlikely(ret))
1441 uart_unregister_driver(&sci_uart_driver);
1442 }
1443
1444 return ret;
1445}
1446
1447static void __exit sci_exit(void)
1448{
1449 platform_driver_unregister(&sci_driver);
1755 uart_unregister_driver(&sci_uart_driver); 1450 uart_unregister_driver(&sci_uart_driver);
1756} 1451}
1757 1452
1758module_init(sci_init); 1453module_init(sci_init);
1759module_exit(sci_exit); 1454module_exit(sci_exit);
1760 1455
1456MODULE_LICENSE("GPL");
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index ab320fa3237c..28643c4dc850 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -10,7 +10,9 @@
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003). 10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004). 11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
12 */ 12 */
13#include <linux/config.h>
13#include <linux/serial_core.h> 14#include <linux/serial_core.h>
15#include <asm/io.h>
14 16
15#if defined(__H8300H__) || defined(__H8300S__) 17#if defined(__H8300H__) || defined(__H8300S__)
16#include <asm/gpio.h> 18#include <asm/gpio.h>
@@ -22,40 +24,13 @@
22#endif 24#endif
23#endif 25#endif
24 26
25/* Offsets into the sci_port->irqs array */
26#define SCIx_ERI_IRQ 0
27#define SCIx_RXI_IRQ 1
28#define SCIx_TXI_IRQ 2
29
30/* ERI, RXI, TXI, BRI */
31#define SCI_IRQS { 23, 24, 25, 0 }
32#define SH3_SCIF_IRQS { 56, 57, 59, 58 }
33#define SH3_IRDA_IRQS { 52, 53, 55, 54 }
34#define SH4_SCIF_IRQS { 40, 41, 43, 42 }
35#define STB1_SCIF1_IRQS {23, 24, 26, 25 }
36#define SH7760_SCIF0_IRQS { 52, 53, 55, 54 }
37#define SH7760_SCIF1_IRQS { 72, 73, 75, 74 }
38#define SH7760_SCIF2_IRQS { 76, 77, 79, 78 }
39#define SH7300_SCIF0_IRQS {80, 80, 80, 80 }
40#define SH73180_SCIF_IRQS {80, 81, 83, 82 }
41#define H8300H_SCI_IRQS0 {52, 53, 54, 0 }
42#define H8300H_SCI_IRQS1 {56, 57, 58, 0 }
43#define H8300H_SCI_IRQS2 {60, 61, 62, 0 }
44#define H8S_SCI_IRQS0 {88, 89, 90, 0 }
45#define H8S_SCI_IRQS1 {92, 93, 94, 0 }
46#define H8S_SCI_IRQS2 {96, 97, 98, 0 }
47#define SH5_SCIF_IRQS {39, 40, 42, 0 }
48#define SH7770_SCIF0_IRQS {61, 61, 61, 61 }
49#define SH7770_SCIF1_IRQS {62, 62, 62, 62 }
50#define SH7770_SCIF2_IRQS {63, 63, 63, 63 }
51#define SH7780_SCIF0_IRQS {40, 41, 43, 42 }
52#define SH7780_SCIF1_IRQS {76, 77, 79, 78 }
53
54#if defined(CONFIG_CPU_SUBTYPE_SH7708) 27#if defined(CONFIG_CPU_SUBTYPE_SH7708)
55# define SCSPTR 0xffffff7c /* 8 bit */ 28# define SCSPTR 0xffffff7c /* 8 bit */
56# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 29# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
57# define SCI_ONLY 30# define SCI_ONLY
58#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) 31#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7706)
59# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 34# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
60# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 35# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
61# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 36# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
@@ -99,12 +74,23 @@
99# define SCPDR 0xA4050136 /* 16 bit SCIF */ 74# define SCPDR 0xA4050136 /* 16 bit SCIF */
100# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 75# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
101# define SCIF_ONLY 76# define SCIF_ONLY
77#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
78# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
79# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
80# define SCIF_ONLY
102#elif defined(CONFIG_CPU_SUBTYPE_SH73180) 81#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
103# define SCPDR 0xA4050138 /* 16 bit SCIF */ 82# define SCPDR 0xA4050138 /* 16 bit SCIF */
104# define SCSPTR2 SCPDR 83# define SCSPTR2 SCPDR
105# define SCIF_ORER 0x0001 /* overrun error bit */ 84# define SCIF_ORER 0x0001 /* overrun error bit */
106# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */ 85# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */
107# define SCIF_ONLY 86# define SCIF_ONLY
87#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
88# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
89# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
90# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
91# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
92# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
93# define SCIF_ONLY
108#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 94#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
109# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 95# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
110# define SCIF_ORER 0x0001 /* overrun error bit */ 96# define SCIF_ORER 0x0001 /* overrun error bit */
@@ -145,7 +131,7 @@
145#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 131#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
146# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 132# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
147# define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 133# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
148# define SCIF_OPER 0x0001 /* Overrun error bit */ 134# define SCIF_ORER 0x0001 /* Overrun error bit */
149# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 135# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
150# define SCIF_ONLY 136# define SCIF_ONLY
151#else 137#else
@@ -273,15 +259,6 @@
273 */ 259 */
274#define SCI_EVENT_WRITE_WAKEUP 0 260#define SCI_EVENT_WRITE_WAKEUP 0
275 261
276struct sci_port {
277 struct uart_port port;
278 int type;
279 unsigned char irqs[4]; /* ERI, RXI, TXI, BRI */
280 void (*init_pins)(struct uart_port *port, unsigned int cflag);
281 int break_flag;
282 struct timer_list break_timer;
283};
284
285#define SCI_IN(size, offset) \ 262#define SCI_IN(size, offset) \
286 unsigned int addr = port->mapbase + (offset); \ 263 unsigned int addr = port->mapbase + (offset); \
287 if ((size) == 8) { \ 264 if ((size) == 8) { \
@@ -336,7 +313,9 @@ struct sci_port {
336 } 313 }
337 314
338#ifdef CONFIG_CPU_SH3 315#ifdef CONFIG_CPU_SH3
339#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 316#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
317 defined(CONFIG_CPU_SUBTYPE_SH7705) || \
318 defined(CONFIG_CPU_SUBTYPE_SH7710)
340#define SCIF_FNS(name, scif_offset, scif_size) \ 319#define SCIF_FNS(name, scif_offset, scif_size) \
341 CPU_SCIF_FNS(name, scif_offset, scif_size) 320 CPU_SCIF_FNS(name, scif_offset, scif_size)
342#else 321#else
@@ -362,7 +341,9 @@ struct sci_port {
362 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 341 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
363#endif 342#endif
364 343
365#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 344#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
345 defined(CONFIG_CPU_SUBTYPE_SH7705) || \
346 defined(CONFIG_CPU_SUBTYPE_SH7710)
366SCIF_FNS(SCSMR, 0x00, 16) 347SCIF_FNS(SCSMR, 0x00, 16)
367SCIF_FNS(SCBRR, 0x04, 8) 348SCIF_FNS(SCBRR, 0x04, 8)
368SCIF_FNS(SCSCR, 0x08, 16) 349SCIF_FNS(SCSCR, 0x08, 16)
@@ -447,7 +428,9 @@ static inline int sci_rxd_in(struct uart_port *port)
447 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */ 428 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
448 return 1; 429 return 1;
449} 430}
450#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) 431#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
432 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
433 defined(CONFIG_CPU_SUBTYPE_SH7706)
451static inline int sci_rxd_in(struct uart_port *port) 434static inline int sci_rxd_in(struct uart_port *port)
452{ 435{
453 if (port->mapbase == 0xfffffe80) 436 if (port->mapbase == 0xfffffe80)
@@ -467,6 +450,13 @@ static inline int sci_rxd_in(struct uart_port *port)
467 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ 450 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
468 return 1; 451 return 1;
469} 452}
453#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
454static inline int sci_rxd_in(struct uart_port *port)
455{
456 if (port->mapbase == SCSPTR0)
457 return ctrl_inw(SCSPTR0 + 0x10) & 0x01 ? 1 : 0;
458 return 1;
459}
470#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 460#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
471 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 461 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
472 defined(CONFIG_CPU_SUBTYPE_SH4_202) 462 defined(CONFIG_CPU_SUBTYPE_SH4_202)
@@ -504,6 +494,19 @@ static inline int sci_rxd_in(struct uart_port *port)
504{ 494{
505 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */ 495 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
506} 496}
497#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
498static inline int sci_rxd_in(struct uart_port *port)
499{
500 if (port->mapbase == 0xffe00000)
501 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
502 if (port->mapbase == 0xffe10000)
503 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
504 if (port->mapbase == 0xffe20000)
505 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
506 if (port->mapbase == 0xffe30000)
507 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
508 return 1;
509}
507#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) 510#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
508static inline int sci_rxd_in(struct uart_port *port) 511static inline int sci_rxd_in(struct uart_port *port)
509{ 512{
@@ -587,4 +590,3 @@ static inline int sci_rxd_in(struct uart_port *port)
587#else /* Generic SH */ 590#else /* Generic SH */
588#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) 591#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
589#endif 592#endif
590
diff --git a/drivers/video/backlight/hp680_bl.c b/drivers/video/backlight/hp680_bl.c
index ffc72ae3ada8..fe1488374f62 100644
--- a/drivers/video/backlight/hp680_bl.c
+++ b/drivers/video/backlight/hp680_bl.c
@@ -20,7 +20,7 @@
20 20
21#include <asm/cpu/dac.h> 21#include <asm/cpu/dac.h>
22#include <asm/hp6xx/hp6xx.h> 22#include <asm/hp6xx/hp6xx.h>
23#include <asm/hd64461/hd64461.h> 23#include <asm/hd64461.h>
24 24
25#define HP680_MAX_INTENSITY 255 25#define HP680_MAX_INTENSITY 255
26#define HP680_DEFAULT_INTENSITY 10 26#define HP680_DEFAULT_INTENSITY 10
@@ -163,6 +163,6 @@ static void __exit hp680bl_exit(void)
163module_init(hp680bl_init); 163module_init(hp680bl_init);
164module_exit(hp680bl_exit); 164module_exit(hp680bl_exit);
165 165
166MODULE_AUTHOR("Andriy Skulysh <askulysh@image.kiev.ua>"); 166MODULE_AUTHOR("Andriy Skulysh <askulysh@gmail.com>");
167MODULE_DESCRIPTION("HP Jornada 680 Backlight Driver"); 167MODULE_DESCRIPTION("HP Jornada 680 Backlight Driver");
168MODULE_LICENSE("GPL"); 168MODULE_LICENSE("GPL");
diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig
index 4444bef68fba..aa3935df852a 100644
--- a/drivers/video/console/Kconfig
+++ b/drivers/video/console/Kconfig
@@ -6,7 +6,7 @@ menu "Console display driver support"
6 6
7config VGA_CONSOLE 7config VGA_CONSOLE
8 bool "VGA text console" if EMBEDDED || !X86 8 bool "VGA text console" if EMBEDDED || !X86
9 depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE 9 depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH
10 default y 10 default y
11 help 11 help
12 Saying Y here will allow you to use Linux in text mode through a 12 Saying Y here will allow you to use Linux in text mode through a
diff --git a/drivers/video/hitfb.c b/drivers/video/hitfb.c
index 4cc6b454265e..3afb472763c0 100644
--- a/drivers/video/hitfb.c
+++ b/drivers/video/hitfb.c
@@ -4,7 +4,7 @@
4 * (C) 1999 Mihai Spatar 4 * (C) 1999 Mihai Spatar
5 * (C) 2000 YAEGASHI Takeshi 5 * (C) 2000 YAEGASHI Takeshi
6 * (C) 2003, 2004 Paul Mundt 6 * (C) 2003, 2004 Paul Mundt
7 * (C) 2003, 2004 Andriy Skulysh 7 * (C) 2003, 2004, 2006 Andriy Skulysh
8 * 8 *
9 * This file is subject to the terms and conditions of the GNU General Public 9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for 10 * License. See the file COPYING in the main directory of this archive for
@@ -20,18 +20,16 @@
20#include <linux/slab.h> 20#include <linux/slab.h>
21#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/platform_device.h>
23#include <linux/fb.h> 24#include <linux/fb.h>
24 25
25#include <asm/machvec.h> 26#include <asm/machvec.h>
26#include <asm/uaccess.h> 27#include <asm/uaccess.h>
27#include <asm/pgtable.h> 28#include <asm/pgtable.h>
28#include <asm/io.h> 29#include <asm/io.h>
29#include <asm/hd64461/hd64461.h> 30#include <asm/hd64461.h>
30
31#ifdef MACH_HP600
32#include <asm/cpu/dac.h> 31#include <asm/cpu/dac.h>
33#include <asm/hp6xx/hp6xx.h> 32#include <asm/hp6xx/hp6xx.h>
34#endif
35 33
36#define WIDTH 640 34#define WIDTH 640
37 35
@@ -45,7 +43,6 @@ static struct fb_var_screeninfo hitfb_var __initdata = {
45static struct fb_fix_screeninfo hitfb_fix __initdata = { 43static struct fb_fix_screeninfo hitfb_fix __initdata = {
46 .id = "Hitachi HD64461", 44 .id = "Hitachi HD64461",
47 .type = FB_TYPE_PACKED_PIXELS, 45 .type = FB_TYPE_PACKED_PIXELS,
48 .ypanstep = 8,
49 .accel = FB_ACCEL_NONE, 46 .accel = FB_ACCEL_NONE,
50}; 47};
51 48
@@ -73,26 +70,14 @@ static inline void hitfb_accel_set_dest(int truecolor, u16 dx, u16 dy,
73 if (truecolor) 70 if (truecolor)
74 saddr <<= 1; 71 saddr <<= 1;
75 72
76 fb_writew(width, HD64461_BBTDWR); 73 fb_writew(width-1, HD64461_BBTDWR);
77 fb_writew(height, HD64461_BBTDHR); 74 fb_writew(height-1, HD64461_BBTDHR);
78 75
79 fb_writew(saddr & 0xffff, HD64461_BBTDSARL); 76 fb_writew(saddr & 0xffff, HD64461_BBTDSARL);
80 fb_writew(saddr >> 16, HD64461_BBTDSARH); 77 fb_writew(saddr >> 16, HD64461_BBTDSARH);
81 78
82} 79}
83 80
84static inline void hitfb_accel_solidfill(int truecolor, u16 dx, u16 dy,
85 u16 width, u16 height, u16 color)
86{
87 hitfb_accel_set_dest(truecolor, dx, dy, width, height);
88
89 fb_writew(0x00f0, HD64461_BBTROPR);
90 fb_writew(16, HD64461_BBTMDR);
91 fb_writew(color, HD64461_GRSCR);
92
93 hitfb_accel_start(truecolor);
94}
95
96static inline void hitfb_accel_bitblt(int truecolor, u16 sx, u16 sy, u16 dx, 81static inline void hitfb_accel_bitblt(int truecolor, u16 sx, u16 sy, u16 dx,
97 u16 dy, u16 width, u16 height, u16 rop, 82 u16 dy, u16 width, u16 height, u16 rop,
98 u32 mask_addr) 83 u32 mask_addr)
@@ -100,6 +85,8 @@ static inline void hitfb_accel_bitblt(int truecolor, u16 sx, u16 sy, u16 dx,
100 u32 saddr, daddr; 85 u32 saddr, daddr;
101 u32 maddr = 0; 86 u32 maddr = 0;
102 87
88 height--;
89 width--;
103 fb_writew(rop, HD64461_BBTROPR); 90 fb_writew(rop, HD64461_BBTROPR);
104 if ((sy < dy) || ((sy == dy) && (sx <= dx))) { 91 if ((sy < dy) || ((sy == dy) && (sx <= dx))) {
105 saddr = WIDTH * (sy + height) + sx + width; 92 saddr = WIDTH * (sy + height) + sx + width;
@@ -146,6 +133,7 @@ static void hitfb_fillrect(struct fb_info *p, const struct fb_fillrect *rect)
146 if (rect->rop != ROP_COPY) 133 if (rect->rop != ROP_COPY)
147 cfb_fillrect(p, rect); 134 cfb_fillrect(p, rect);
148 else { 135 else {
136 hitfb_accel_wait();
149 fb_writew(0x00f0, HD64461_BBTROPR); 137 fb_writew(0x00f0, HD64461_BBTROPR);
150 fb_writew(16, HD64461_BBTMDR); 138 fb_writew(16, HD64461_BBTMDR);
151 139
@@ -161,16 +149,15 @@ static void hitfb_fillrect(struct fb_info *p, const struct fb_fillrect *rect)
161 rect->height); 149 rect->height);
162 hitfb_accel_start(0); 150 hitfb_accel_start(0);
163 } 151 }
164 hitfb_accel_wait();
165 } 152 }
166} 153}
167 154
168static void hitfb_copyarea(struct fb_info *p, const struct fb_copyarea *area) 155static void hitfb_copyarea(struct fb_info *p, const struct fb_copyarea *area)
169{ 156{
157 hitfb_accel_wait();
170 hitfb_accel_bitblt(p->var.bits_per_pixel == 16, area->sx, area->sy, 158 hitfb_accel_bitblt(p->var.bits_per_pixel == 16, area->sx, area->sy,
171 area->dx, area->dy, area->width, area->height, 159 area->dx, area->dy, area->width, area->height,
172 0x00cc, 0); 160 0x00cc, 0);
173 hitfb_accel_wait();
174} 161}
175 162
176static int hitfb_pan_display(struct fb_var_screeninfo *var, 163static int hitfb_pan_display(struct fb_var_screeninfo *var,
@@ -182,7 +169,7 @@ static int hitfb_pan_display(struct fb_var_screeninfo *var,
182 if (xoffset != 0) 169 if (xoffset != 0)
183 return -EINVAL; 170 return -EINVAL;
184 171
185 fb_writew(yoffset, HD64461_LCDCBAR); 172 fb_writew((yoffset*info->fix.line_length)>>10, HD64461_LCDCBAR);
186 173
187 return 0; 174 return 0;
188} 175}
@@ -192,12 +179,6 @@ int hitfb_blank(int blank_mode, struct fb_info *info)
192 unsigned short v; 179 unsigned short v;
193 180
194 if (blank_mode) { 181 if (blank_mode) {
195#ifdef MACH_HP600
196 sh_dac_disable(DAC_LCD_BRIGHTNESS);
197 v = fb_readw(HD64461_GPBDR);
198 v |= HD64461_GPBDR_LCDOFF;
199 fb_writew(v, HD64461_GPBDR);
200#endif
201 v = fb_readw(HD64461_LDR1); 182 v = fb_readw(HD64461_LDR1);
202 v &= ~HD64461_LDR1_DON; 183 v &= ~HD64461_LDR1_DON;
203 fb_writew(v, HD64461_LDR1); 184 fb_writew(v, HD64461_LDR1);
@@ -213,19 +194,18 @@ int hitfb_blank(int blank_mode, struct fb_info *info)
213 v = fb_readw(HD64461_STBCR); 194 v = fb_readw(HD64461_STBCR);
214 v &= ~HD64461_STBCR_SLCDST; 195 v &= ~HD64461_STBCR_SLCDST;
215 fb_writew(v, HD64461_STBCR); 196 fb_writew(v, HD64461_STBCR);
216#ifdef MACH_HP600
217 sh_dac_enable(DAC_LCD_BRIGHTNESS);
218 v = fb_readw(HD64461_GPBDR);
219 v &= ~HD64461_GPBDR_LCDOFF;
220 fb_writew(v, HD64461_GPBDR);
221#endif
222 v = fb_readw(HD64461_LDR1);
223 v |= HD64461_LDR1_DON;
224 fb_writew(v, HD64461_LDR1);
225 197
226 v = fb_readw(HD64461_LCDCCR); 198 v = fb_readw(HD64461_LCDCCR);
227 v &= ~HD64461_LCDCCR_MOFF; 199 v &= ~(HD64461_LCDCCR_MOFF | HD64461_LCDCCR_STREQ);
228 fb_writew(v, HD64461_LCDCCR); 200 fb_writew(v, HD64461_LCDCCR);
201
202 do {
203 v = fb_readw(HD64461_LCDCCR);
204 } while(v&HD64461_LCDCCR_STBACK);
205
206 v = fb_readw(HD64461_LDR1);
207 v |= HD64461_LDR1_DON;
208 fb_writew(v, HD64461_LDR1);
229 } 209 }
230 return 0; 210 return 0;
231} 211}
@@ -233,7 +213,7 @@ int hitfb_blank(int blank_mode, struct fb_info *info)
233static int hitfb_setcolreg(unsigned regno, unsigned red, unsigned green, 213static int hitfb_setcolreg(unsigned regno, unsigned red, unsigned green,
234 unsigned blue, unsigned transp, struct fb_info *info) 214 unsigned blue, unsigned transp, struct fb_info *info)
235{ 215{
236 if (regno >= info->cmap.len) 216 if (regno >= 256)
237 return 1; 217 return 1;
238 218
239 switch (info->var.bits_per_pixel) { 219 switch (info->var.bits_per_pixel) {
@@ -244,6 +224,8 @@ static int hitfb_setcolreg(unsigned regno, unsigned red, unsigned green,
244 fb_writew(blue >> 10, HD64461_CPTWDR); 224 fb_writew(blue >> 10, HD64461_CPTWDR);
245 break; 225 break;
246 case 16: 226 case 16:
227 if (regno >= 16)
228 return 1;
247 ((u32 *) (info->pseudo_palette))[regno] = 229 ((u32 *) (info->pseudo_palette))[regno] =
248 ((red & 0xf800)) | 230 ((red & 0xf800)) |
249 ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11); 231 ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11);
@@ -252,26 +234,113 @@ static int hitfb_setcolreg(unsigned regno, unsigned red, unsigned green,
252 return 0; 234 return 0;
253} 235}
254 236
237static int hitfb_sync(struct fb_info *info)
238{
239 hitfb_accel_wait();
240
241 return 0;
242}
243
244static int hitfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
245{
246 int maxy;
247
248 var->xres = info->var.xres;
249 var->xres_virtual = info->var.xres;
250 var->yres = info->var.yres;
251
252 if ((var->bits_per_pixel != 8) && (var->bits_per_pixel != 16))
253 var->bits_per_pixel = info->var.bits_per_pixel;
254
255 if (var->yres_virtual < var->yres)
256 var->yres_virtual = var->yres;
257
258 maxy = info->fix.smem_len / var->xres;
259
260 if (var->bits_per_pixel == 16)
261 maxy /= 2;
262
263 if (var->yres_virtual > maxy)
264 var->yres_virtual = maxy;
265
266 var->xoffset = 0;
267 var->yoffset = 0;
268
269 switch (var->bits_per_pixel) {
270 case 8:
271 var->red.offset = 0;
272 var->red.length = 8;
273 var->green.offset = 0;
274 var->green.length = 8;
275 var->blue.offset = 0;
276 var->blue.length = 8;
277 var->transp.offset = 0;
278 var->transp.length = 0;
279 break;
280 case 16: /* RGB 565 */
281 var->red.offset = 11;
282 var->red.length = 5;
283 var->green.offset = 5;
284 var->green.length = 6;
285 var->blue.offset = 0;
286 var->blue.length = 5;
287 var->transp.offset = 0;
288 var->transp.length = 0;
289 break;
290 }
291
292 return 0;
293}
294
295static int hitfb_set_par(struct fb_info *info)
296{
297 unsigned short ldr3;
298
299 switch (info->var.bits_per_pixel) {
300 case 8:
301 info->fix.line_length = info->var.xres;
302 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
303 info->fix.ypanstep = 16;
304 break;
305 case 16:
306 info->fix.line_length = info->var.xres*2;
307 info->fix.visual = FB_VISUAL_TRUECOLOR;
308 info->fix.ypanstep = 8;
309 break;
310 }
311
312 fb_writew(info->fix.line_length, HD64461_LCDCLOR);
313 ldr3 = fb_readw(HD64461_LDR3);
314 ldr3 &= ~15;
315 ldr3 |= (info->var.bits_per_pixel == 8) ? 4 : 8;
316 fb_writew(ldr3, HD64461_LDR3);
317 return 0;
318}
319
255static struct fb_ops hitfb_ops = { 320static struct fb_ops hitfb_ops = {
256 .owner = THIS_MODULE, 321 .owner = THIS_MODULE,
322 .fb_check_var = hitfb_check_var,
323 .fb_set_par = hitfb_set_par,
257 .fb_setcolreg = hitfb_setcolreg, 324 .fb_setcolreg = hitfb_setcolreg,
258 .fb_blank = hitfb_blank, 325 .fb_blank = hitfb_blank,
326 .fb_sync = hitfb_sync,
259 .fb_pan_display = hitfb_pan_display, 327 .fb_pan_display = hitfb_pan_display,
260 .fb_fillrect = hitfb_fillrect, 328 .fb_fillrect = hitfb_fillrect,
261 .fb_copyarea = hitfb_copyarea, 329 .fb_copyarea = hitfb_copyarea,
262 .fb_imageblit = cfb_imageblit, 330 .fb_imageblit = cfb_imageblit,
263}; 331};
264 332
265int __init hitfb_init(void) 333static int __init hitfb_probe(struct platform_device *dev)
266{ 334{
267 unsigned short lcdclor, ldr3, ldvndr; 335 unsigned short lcdclor, ldr3, ldvndr;
268 int size;
269 336
270 if (fb_get_options("hitfb", NULL)) 337 if (fb_get_options("hitfb", NULL))
271 return -ENODEV; 338 return -ENODEV;
272 339
340 hitfb_fix.mmio_start = CONFIG_HD64461_IOBASE+0x1000;
341 hitfb_fix.mmio_len = 0x1000;
273 hitfb_fix.smem_start = CONFIG_HD64461_IOBASE + 0x02000000; 342 hitfb_fix.smem_start = CONFIG_HD64461_IOBASE + 0x02000000;
274 hitfb_fix.smem_len = (MACH_HP690) ? 1024 * 1024 : 512 * 1024; 343 hitfb_fix.smem_len = 512 * 1024;
275 344
276 lcdclor = fb_readw(HD64461_LCDCLOR); 345 lcdclor = fb_readw(HD64461_LCDCLOR);
277 ldvndr = fb_readw(HD64461_LDVNDR); 346 ldvndr = fb_readw(HD64461_LDVNDR);
@@ -321,12 +390,12 @@ int __init hitfb_init(void)
321 fb_info.var = hitfb_var; 390 fb_info.var = hitfb_var;
322 fb_info.fix = hitfb_fix; 391 fb_info.fix = hitfb_fix;
323 fb_info.pseudo_palette = pseudo_palette; 392 fb_info.pseudo_palette = pseudo_palette;
324 fb_info.flags = FBINFO_DEFAULT; 393 fb_info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN |
394 FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA;
325 395
326 fb_info.screen_base = (void *)hitfb_fix.smem_start; 396 fb_info.screen_base = (void *)hitfb_fix.smem_start;
327 397
328 size = (fb_info.var.bits_per_pixel == 8) ? 256 : 16; 398 fb_alloc_cmap(&fb_info.cmap, 256, 0);
329 fb_alloc_cmap(&fb_info.cmap, size, 0);
330 399
331 if (register_framebuffer(&fb_info) < 0) 400 if (register_framebuffer(&fb_info) < 0)
332 return -EINVAL; 401 return -EINVAL;
@@ -336,9 +405,75 @@ int __init hitfb_init(void)
336 return 0; 405 return 0;
337} 406}
338 407
408static int __devexit hitfb_remove(struct platform_device *dev)
409{
410 return unregister_framebuffer(&fb_info);
411}
412
413#ifdef CONFIG_PM
414static int hitfb_suspend(struct platform_device *dev, pm_message_t state)
415{
416 u16 v;
417
418 hitfb_blank(1,0);
419 v = fb_readw(HD64461_STBCR);
420 v |= HD64461_STBCR_SLCKE_IST;
421 fb_writew(v, HD64461_STBCR);
422
423 return 0;
424}
425
426static int hitfb_resume(struct platform_device *dev)
427{
428 u16 v;
429
430 v = fb_readw(HD64461_STBCR);
431 v &= ~HD64461_STBCR_SLCKE_OST;
432 msleep(100);
433 v = fb_readw(HD64461_STBCR);
434 v &= ~HD64461_STBCR_SLCKE_IST;
435 fb_writew(v, HD64461_STBCR);
436 hitfb_blank(0,0);
437
438 return 0;
439}
440#endif
441
442static struct platform_driver hitfb_driver = {
443 .probe = hitfb_probe,
444 .remove = __devexit_p(hitfb_remove),
445#ifdef CONFIG_PM
446 .suspend = hitfb_suspend,
447 .resume = hitfb_resume,
448#endif
449 .driver = {
450 .name = "hitfb",
451 },
452};
453
454static struct platform_device hitfb_device = {
455 .name = "hitfb",
456 .id = -1,
457};
458
459static int __init hitfb_init(void)
460{
461 int ret;
462
463 ret = platform_driver_register(&hitfb_driver);
464 if (!ret) {
465 ret = platform_device_register(&hitfb_device);
466 if (ret)
467 platform_driver_unregister(&hitfb_driver);
468 }
469 return ret;
470}
471
472
339static void __exit hitfb_exit(void) 473static void __exit hitfb_exit(void)
340{ 474{
341 unregister_framebuffer(&fb_info); 475 platform_device_unregister(&hitfb_device);
476 platform_driver_unregister(&hitfb_driver);
342} 477}
343 478
344module_init(hitfb_init); 479module_init(hitfb_init);
diff --git a/drivers/video/pvr2fb.c b/drivers/video/pvr2fb.c
index 940ba2be55e9..78dc59a1751b 100644
--- a/drivers/video/pvr2fb.c
+++ b/drivers/video/pvr2fb.c
@@ -187,7 +187,7 @@ static short do_blank = 0; /* (Un)Blank the screen */
187static unsigned int is_blanked = 0; /* Is the screen blanked? */ 187static unsigned int is_blanked = 0; /* Is the screen blanked? */
188 188
189#ifdef CONFIG_SH_STORE_QUEUES 189#ifdef CONFIG_SH_STORE_QUEUES
190static struct sq_mapping *pvr2fb_map; 190static unsigned long pvr2fb_map;
191#endif 191#endif
192 192
193#ifdef CONFIG_SH_DMA 193#ifdef CONFIG_SH_DMA
@@ -213,15 +213,17 @@ static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id, struct pt_regs *fp);
213static int pvr2_init_cable(void); 213static int pvr2_init_cable(void);
214static int pvr2_get_param(const struct pvr2_params *p, const char *s, 214static int pvr2_get_param(const struct pvr2_params *p, const char *s,
215 int val, int size); 215 int val, int size);
216#ifdef CONFIG_SH_DMA
216static ssize_t pvr2fb_write(struct file *file, const char *buf, 217static ssize_t pvr2fb_write(struct file *file, const char *buf,
217 size_t count, loff_t *ppos); 218 size_t count, loff_t *ppos);
219#endif
218 220
219static struct fb_ops pvr2fb_ops = { 221static struct fb_ops pvr2fb_ops = {
220 .owner = THIS_MODULE, 222 .owner = THIS_MODULE,
221 .fb_setcolreg = pvr2fb_setcolreg, 223 .fb_setcolreg = pvr2fb_setcolreg,
222 .fb_blank = pvr2fb_blank, 224 .fb_blank = pvr2fb_blank,
223 .fb_check_var = pvr2fb_check_var, 225 .fb_check_var = pvr2fb_check_var,
224 .fb_set_par = pvr2fb_set_par, 226 .fb_set_par = pvr2fb_set_par,
225#ifdef CONFIG_SH_DMA 227#ifdef CONFIG_SH_DMA
226 .fb_write = pvr2fb_write, 228 .fb_write = pvr2fb_write,
227#endif 229#endif
@@ -783,7 +785,7 @@ static int __init pvr2fb_common_init(void)
783 goto out_err; 785 goto out_err;
784 } 786 }
785 787
786 fb_memset((unsigned long)fb_info->screen_base, 0, pvr2_fix.smem_len); 788 fb_memset(fb_info->screen_base, 0, pvr2_fix.smem_len);
787 789
788 pvr2_fix.ypanstep = nopan ? 0 : 1; 790 pvr2_fix.ypanstep = nopan ? 0 : 1;
789 pvr2_fix.ywrapstep = nowrap ? 0 : 1; 791 pvr2_fix.ywrapstep = nowrap ? 0 : 1;
@@ -820,7 +822,7 @@ static int __init pvr2fb_common_init(void)
820 modememused >> 10, (unsigned long)(fb_info->fix.smem_len >> 10)); 822 modememused >> 10, (unsigned long)(fb_info->fix.smem_len >> 10));
821 printk("fb%d: Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n", 823 printk("fb%d: Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n",
822 fb_info->node, fb_info->var.xres, fb_info->var.yres, 824 fb_info->node, fb_info->var.xres, fb_info->var.yres,
823 fb_info->var.bits_per_pixel, 825 fb_info->var.bits_per_pixel,
824 get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel), 826 get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel),
825 (char *)pvr2_get_param(cables, NULL, cable_type, 3), 827 (char *)pvr2_get_param(cables, NULL, cable_type, 3),
826 (char *)pvr2_get_param(outputs, NULL, video_output, 3)); 828 (char *)pvr2_get_param(outputs, NULL, video_output, 3));
@@ -829,10 +831,10 @@ static int __init pvr2fb_common_init(void)
829 printk(KERN_NOTICE "fb%d: registering with SQ API\n", fb_info->node); 831 printk(KERN_NOTICE "fb%d: registering with SQ API\n", fb_info->node);
830 832
831 pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len, 833 pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len,
832 fb_info->fix.id); 834 fb_info->fix.id, pgprot_val(PAGE_SHARED));
833 835
834 printk(KERN_NOTICE "fb%d: Mapped video memory to SQ addr 0x%lx\n", 836 printk(KERN_NOTICE "fb%d: Mapped video memory to SQ addr 0x%lx\n",
835 fb_info->node, pvr2fb_map->sq_addr); 837 fb_info->node, pvr2fb_map);
836#endif 838#endif
837 839
838 return 0; 840 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-25 00:50:12 -0500