10 files changed, 687 insertions, 81 deletions

diff --git a/drivers/atm/Makefile b/drivers/atm/Makefile
index b5077ce8cb40..1b16f8166b09 100644
--- a/drivers/atm/Makefile
+++ b/drivers/atm/Makefile
@@ -41,7 +41,7 @@ ifeq ($(CONFIG_ATM_FORE200E_PCA),y)
   # guess the target endianess to choose the right PCA-200E firmware image
   ifeq ($(CONFIG_ATM_FORE200E_PCA_DEFAULT_FW),y)
     byteorder.h                 := include$(if $(patsubst $(srctree),,$(objtree)),2)/asm/byteorder.h
-    CONFIG_ATM_FORE200E_PCA_FW  := $(obj)/pca200e$(if $(shell $(CC) -E -dM $(byteorder.h) | grep ' __LITTLE_ENDIAN '),.bin,_ecd.bin2)
+    CONFIG_ATM_FORE200E_PCA_FW  := $(obj)/pca200e$(if $(shell $(CC) $(CPPFLAGS) -E -dM $(byteorder.h) | grep ' __LITTLE_ENDIAN '),.bin,_ecd.bin2)
   endif
 endif
 
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 432c17e1e0e6..85072446d772 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -306,6 +306,7 @@ config BLK_DEV_LOOP
 config BLK_DEV_CRYPTOLOOP
         tristate "Cryptoloop Support"
         select CRYPTO
+        select CRYPTO_CBC
         depends on BLK_DEV_LOOP
         ---help---
           Say Y here if you want to be able to use the ciphers that are 
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index adb554153f67..e816535ab305 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -51,4 +51,17 @@ config CRYPTO_DEV_PADLOCK_SHA
           If unsure say M. The compiled module will be
           called padlock-sha.ko
 
+config CRYPTO_DEV_GEODE
+        tristate "Support for the Geode LX AES engine"
+        depends on CRYPTO && X86_32
+        select CRYPTO_ALGAPI
+        select CRYPTO_BLKCIPHER
+        default m
+        help
+          Say 'Y' here to use the AMD Geode LX processor on-board AES
+          engine for the CryptoAPI AES alogrithm.
+
+          To compile this driver as a module, choose M here: the module
+          will be called geode-aes.
+
 endmenu
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 4c3d0ec1cf80..6059cf869414 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_CRYPTO_DEV_PADLOCK) += padlock.o
 obj-$(CONFIG_CRYPTO_DEV_PADLOCK_AES) += padlock-aes.o
 obj-$(CONFIG_CRYPTO_DEV_PADLOCK_SHA) += padlock-sha.o
+obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-aes.o
diff --git a/drivers/crypto/geode-aes.c b/drivers/crypto/geode-aes.c
new file mode 100644
index 000000000000..43a68398656f
--- /dev/null
+++ b/drivers/crypto/geode-aes.c
@@ -0,0 +1,474 @@
+ /* Copyright (C) 2004-2006, Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/crypto.h>
+#include <linux/spinlock.h>
+#include <crypto/algapi.h>
+
+#include <asm/io.h>
+#include <asm/delay.h>
+
+#include "geode-aes.h"
+
+/* Register definitions */
+
+#define AES_CTRLA_REG  0x0000
+
+#define AES_CTRL_START     0x01
+#define AES_CTRL_DECRYPT   0x00
+#define AES_CTRL_ENCRYPT   0x02
+#define AES_CTRL_WRKEY     0x04
+#define AES_CTRL_DCA       0x08
+#define AES_CTRL_SCA       0x10
+#define AES_CTRL_CBC       0x20
+
+#define AES_INTR_REG  0x0008
+
+#define AES_INTRA_PENDING (1 << 16)
+#define AES_INTRB_PENDING (1 << 17)
+
+#define AES_INTR_PENDING  (AES_INTRA_PENDING | AES_INTRB_PENDING)
+#define AES_INTR_MASK     0x07
+
+#define AES_SOURCEA_REG   0x0010
+#define AES_DSTA_REG      0x0014
+#define AES_LENA_REG      0x0018
+#define AES_WRITEKEY0_REG 0x0030
+#define AES_WRITEIV0_REG  0x0040
+
+/*  A very large counter that is used to gracefully bail out of an
+ *  operation in case of trouble
+ */
+
+#define AES_OP_TIMEOUT    0x50000
+
+/* Static structures */
+
+static void __iomem * _iobase;
+static spinlock_t lock;
+
+/* Write a 128 bit field (either a writable key or IV) */
+static inline void
+_writefield(u32 offset, void *value)
+{
+        int i;
+        for(i = 0; i < 4; i++)
+                iowrite32(((u32 *) value)[i], _iobase + offset + (i * 4));
+}
+
+/* Read a 128 bit field (either a writable key or IV) */
+static inline void
+_readfield(u32 offset, void *value)
+{
+        int i;
+        for(i = 0; i < 4; i++)
+                ((u32 *) value)[i] = ioread32(_iobase + offset + (i * 4));
+}
+
+static int
+do_crypt(void *src, void *dst, int len, u32 flags)
+{
+        u32 status;
+        u32 counter = AES_OP_TIMEOUT;
+
+        iowrite32(virt_to_phys(src), _iobase + AES_SOURCEA_REG);
+        iowrite32(virt_to_phys(dst), _iobase + AES_DSTA_REG);
+        iowrite32(len,  _iobase + AES_LENA_REG);
+
+        /* Start the operation */
+        iowrite32(AES_CTRL_START | flags, _iobase + AES_CTRLA_REG);
+
+        do
+                status = ioread32(_iobase + AES_INTR_REG);
+        while(!(status & AES_INTRA_PENDING) && --counter);
+
+        /* Clear the event */
+        iowrite32((status & 0xFF) | AES_INTRA_PENDING, _iobase + AES_INTR_REG);
+        return counter ? 0 : 1;
+}
+
+static unsigned int
+geode_aes_crypt(struct geode_aes_op *op)
+{
+
+        u32 flags = 0;
+        int iflags;
+
+        if (op->len == 0 || op->src == op->dst)
+                return 0;
+
+        if (op->flags & AES_FLAGS_COHERENT)
+                flags |= (AES_CTRL_DCA | AES_CTRL_SCA);
+
+        if (op->dir == AES_DIR_ENCRYPT)
+                flags |= AES_CTRL_ENCRYPT;
+
+        /* Start the critical section */
+
+        spin_lock_irqsave(&lock, iflags);
+
+        if (op->mode == AES_MODE_CBC) {
+                flags |= AES_CTRL_CBC;
+                _writefield(AES_WRITEIV0_REG, op->iv);
+        }
+
+        if (op->flags & AES_FLAGS_USRKEY) {
+                flags |= AES_CTRL_WRKEY;
+                _writefield(AES_WRITEKEY0_REG, op->key);
+        }
+
+        do_crypt(op->src, op->dst, op->len, flags);
+
+        if (op->mode == AES_MODE_CBC)
+                _readfield(AES_WRITEIV0_REG, op->iv);
+
+        spin_unlock_irqrestore(&lock, iflags);
+
+        return op->len;
+}
+
+/* CRYPTO-API Functions */
+
+static int
+geode_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int len)
+{
+        struct geode_aes_op *op = crypto_tfm_ctx(tfm);
+
+        if (len != AES_KEY_LENGTH) {
+                tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+                return -EINVAL;
+        }
+
+        memcpy(op->key, key, len);
+        return 0;
+}
+
+static void
+geode_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
+{
+        struct geode_aes_op *op = crypto_tfm_ctx(tfm);
+
+        if ((out == NULL) || (in == NULL))
+                return;
+
+        op->src = (void *) in;
+        op->dst = (void *) out;
+        op->mode = AES_MODE_ECB;
+        op->flags = 0;
+        op->len = AES_MIN_BLOCK_SIZE;
+        op->dir = AES_DIR_ENCRYPT;
+
+        geode_aes_crypt(op);
+}
+
+
+static void
+geode_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
+{
+        struct geode_aes_op *op = crypto_tfm_ctx(tfm);
+
+        if ((out == NULL) || (in == NULL))
+                return;
+
+        op->src = (void *) in;
+        op->dst = (void *) out;
+        op->mode = AES_MODE_ECB;
+        op->flags = 0;
+        op->len = AES_MIN_BLOCK_SIZE;
+        op->dir = AES_DIR_DECRYPT;
+
+        geode_aes_crypt(op);
+}
+
+
+static struct crypto_alg geode_alg = {
+        .cra_name               =       "aes",
+        .cra_driver_name        =       "geode-aes-128",
+        .cra_priority           =       300,
+        .cra_alignmask          =       15,
+        .cra_flags              =       CRYPTO_ALG_TYPE_CIPHER,
+        .cra_blocksize          =       AES_MIN_BLOCK_SIZE,
+        .cra_ctxsize            =       sizeof(struct geode_aes_op),
+        .cra_module             =       THIS_MODULE,
+        .cra_list               =       LIST_HEAD_INIT(geode_alg.cra_list),
+        .cra_u                  =       {
+                .cipher = {
+                        .cia_min_keysize        =  AES_KEY_LENGTH,
+                        .cia_max_keysize        =  AES_KEY_LENGTH,
+                        .cia_setkey             =  geode_setkey,
+                        .cia_encrypt            =  geode_encrypt,
+                        .cia_decrypt            =  geode_decrypt
+                }
+        }
+};
+
+static int
+geode_cbc_decrypt(struct blkcipher_desc *desc,
+                  struct scatterlist *dst, struct scatterlist *src,
+                  unsigned int nbytes)
+{
+        struct geode_aes_op *op = crypto_blkcipher_ctx(desc->tfm);
+        struct blkcipher_walk walk;
+        int err, ret;
+
+        blkcipher_walk_init(&walk, dst, src, nbytes);
+        err = blkcipher_walk_virt(desc, &walk);
+
+        while((nbytes = walk.nbytes)) {
+                op->src = walk.src.virt.addr,
+                op->dst = walk.dst.virt.addr;
+                op->mode = AES_MODE_CBC;
+                op->len = nbytes - (nbytes % AES_MIN_BLOCK_SIZE);
+                op->dir = AES_DIR_DECRYPT;
+
+                memcpy(op->iv, walk.iv, AES_IV_LENGTH);
+
+                ret = geode_aes_crypt(op);
+
+                memcpy(walk.iv, op->iv, AES_IV_LENGTH);
+                nbytes -= ret;
+
+                err = blkcipher_walk_done(desc, &walk, nbytes);
+        }
+
+        return err;
+}
+
+static int
+geode_cbc_encrypt(struct blkcipher_desc *desc,
+                  struct scatterlist *dst, struct scatterlist *src,
+                  unsigned int nbytes)
+{
+        struct geode_aes_op *op = crypto_blkcipher_ctx(desc->tfm);
+        struct blkcipher_walk walk;
+        int err, ret;
+
+        blkcipher_walk_init(&walk, dst, src, nbytes);
+        err = blkcipher_walk_virt(desc, &walk);
+
+        while((nbytes = walk.nbytes)) {
+                op->src = walk.src.virt.addr,
+                op->dst = walk.dst.virt.addr;
+                op->mode = AES_MODE_CBC;
+                op->len = nbytes - (nbytes % AES_MIN_BLOCK_SIZE);
+                op->dir = AES_DIR_ENCRYPT;
+
+                memcpy(op->iv, walk.iv, AES_IV_LENGTH);
+
+                ret = geode_aes_crypt(op);
+                nbytes -= ret;
+                err = blkcipher_walk_done(desc, &walk, nbytes);
+        }
+
+        return err;
+}
+
+static struct crypto_alg geode_cbc_alg = {
+        .cra_name               =       "cbc(aes)",
+        .cra_driver_name        =       "cbc-aes-geode-128",
+        .cra_priority           =       400,
+        .cra_flags              =       CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          =       AES_MIN_BLOCK_SIZE,
+        .cra_ctxsize            =       sizeof(struct geode_aes_op),
+        .cra_alignmask          =       15,
+        .cra_type               =       &crypto_blkcipher_type,
+        .cra_module             =       THIS_MODULE,
+        .cra_list               =       LIST_HEAD_INIT(geode_cbc_alg.cra_list),
+        .cra_u                  =       {
+                .blkcipher = {
+                        .min_keysize            =       AES_KEY_LENGTH,
+                        .max_keysize            =       AES_KEY_LENGTH,
+                        .setkey                 =       geode_setkey,
+                        .encrypt                =       geode_cbc_encrypt,
+                        .decrypt                =       geode_cbc_decrypt,
+                }
+        }
+};
+
+static int
+geode_ecb_decrypt(struct blkcipher_desc *desc,
+                  struct scatterlist *dst, struct scatterlist *src,
+                  unsigned int nbytes)
+{
+        struct geode_aes_op *op = crypto_blkcipher_ctx(desc->tfm);
+        struct blkcipher_walk walk;
+        int err, ret;
+
+        blkcipher_walk_init(&walk, dst, src, nbytes);
+        err = blkcipher_walk_virt(desc, &walk);
+
+        while((nbytes = walk.nbytes)) {
+                op->src = walk.src.virt.addr,
+                op->dst = walk.dst.virt.addr;
+                op->mode = AES_MODE_ECB;
+                op->len = nbytes - (nbytes % AES_MIN_BLOCK_SIZE);
+                op->dir = AES_DIR_DECRYPT;
+
+                ret = geode_aes_crypt(op);
+                nbytes -= ret;
+                err = blkcipher_walk_done(desc, &walk, nbytes);
+        }
+
+        return err;
+}
+
+static int
+geode_ecb_encrypt(struct blkcipher_desc *desc,
+                  struct scatterlist *dst, struct scatterlist *src,
+                  unsigned int nbytes)
+{
+        struct geode_aes_op *op = crypto_blkcipher_ctx(desc->tfm);
+        struct blkcipher_walk walk;
+        int err, ret;
+
+        blkcipher_walk_init(&walk, dst, src, nbytes);
+        err = blkcipher_walk_virt(desc, &walk);
+
+        while((nbytes = walk.nbytes)) {
+                op->src = walk.src.virt.addr,
+                op->dst = walk.dst.virt.addr;
+                op->mode = AES_MODE_ECB;
+                op->len = nbytes - (nbytes % AES_MIN_BLOCK_SIZE);
+                op->dir = AES_DIR_ENCRYPT;
+
+                ret = geode_aes_crypt(op);
+                nbytes -= ret;
+                ret =  blkcipher_walk_done(desc, &walk, nbytes);
+        }
+
+        return err;
+}
+
+static struct crypto_alg geode_ecb_alg = {
+        .cra_name               =       "ecb(aes)",
+        .cra_driver_name        =       "ecb-aes-geode-128",
+        .cra_priority           =       400,
+        .cra_flags              =       CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          =       AES_MIN_BLOCK_SIZE,
+        .cra_ctxsize            =       sizeof(struct geode_aes_op),
+        .cra_alignmask          =       15,
+        .cra_type               =       &crypto_blkcipher_type,
+        .cra_module             =       THIS_MODULE,
+        .cra_list               =       LIST_HEAD_INIT(geode_ecb_alg.cra_list),
+        .cra_u                  =       {
+                .blkcipher = {
+                        .min_keysize            =       AES_KEY_LENGTH,
+                        .max_keysize            =       AES_KEY_LENGTH,
+                        .setkey                 =       geode_setkey,
+                        .encrypt                =       geode_ecb_encrypt,
+                        .decrypt                =       geode_ecb_decrypt,
+                }
+        }
+};
+
+static void
+geode_aes_remove(struct pci_dev *dev)
+{
+        crypto_unregister_alg(&geode_alg);
+        crypto_unregister_alg(&geode_ecb_alg);
+        crypto_unregister_alg(&geode_cbc_alg);
+
+        pci_iounmap(dev, _iobase);
+        _iobase = NULL;
+
+        pci_release_regions(dev);
+        pci_disable_device(dev);
+}
+
+
+static int
+geode_aes_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+        int ret;
+
+        if ((ret = pci_enable_device(dev)))
+                return ret;
+
+        if ((ret = pci_request_regions(dev, "geode-aes-128")))
+                goto eenable;
+
+        _iobase = pci_iomap(dev, 0, 0);
+
+        if (_iobase == NULL) {
+                ret = -ENOMEM;
+                goto erequest;
+        }
+
+        spin_lock_init(&lock);
+
+        /* Clear any pending activity */
+        iowrite32(AES_INTR_PENDING | AES_INTR_MASK, _iobase + AES_INTR_REG);
+
+        if ((ret = crypto_register_alg(&geode_alg)))
+                goto eiomap;
+
+        if ((ret = crypto_register_alg(&geode_ecb_alg)))
+                goto ealg;
+
+        if ((ret = crypto_register_alg(&geode_cbc_alg)))
+                goto eecb;
+
+        printk(KERN_NOTICE "geode-aes: GEODE AES engine enabled.\n");
+        return 0;
+
+ eecb:
+        crypto_unregister_alg(&geode_ecb_alg);
+
+ ealg:
+        crypto_unregister_alg(&geode_alg);
+
+ eiomap:
+        pci_iounmap(dev, _iobase);
+
+ erequest:
+        pci_release_regions(dev);
+
+ eenable:
+        pci_disable_device(dev);
+
+        printk(KERN_ERR "geode-aes:  GEODE AES initialization failed.\n");
+        return ret;
+}
+
+static struct pci_device_id geode_aes_tbl[] = {
+        { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LX_AES, PCI_ANY_ID, PCI_ANY_ID} ,
+        { 0, }
+};
+
+MODULE_DEVICE_TABLE(pci, geode_aes_tbl);
+
+static struct pci_driver geode_aes_driver = {
+        .name = "Geode LX AES",
+        .id_table = geode_aes_tbl,
+        .probe = geode_aes_probe,
+        .remove = __devexit_p(geode_aes_remove)
+};
+
+static int __init
+geode_aes_init(void)
+{
+        return pci_module_init(&geode_aes_driver);
+}
+
+static void __exit
+geode_aes_exit(void)
+{
+        pci_unregister_driver(&geode_aes_driver);
+}
+
+MODULE_AUTHOR("Advanced Micro Devices, Inc.");
+MODULE_DESCRIPTION("Geode LX Hardware AES driver");
+MODULE_LICENSE("GPL");
+
+module_init(geode_aes_init);
+module_exit(geode_aes_exit);
diff --git a/drivers/crypto/geode-aes.h b/drivers/crypto/geode-aes.h
new file mode 100644
index 000000000000..8003a36f3a83
--- /dev/null
+++ b/drivers/crypto/geode-aes.h
@@ -0,0 +1,40 @@
+/* Copyright (C) 2003-2006, Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _GEODE_AES_H_
+#define _GEODE_AES_H_
+
+#define AES_KEY_LENGTH 16
+#define AES_IV_LENGTH  16
+
+#define AES_MIN_BLOCK_SIZE 16
+
+#define AES_MODE_ECB 0
+#define AES_MODE_CBC 1
+
+#define AES_DIR_DECRYPT 0
+#define AES_DIR_ENCRYPT 1
+
+#define AES_FLAGS_USRKEY   (1 << 0)
+#define AES_FLAGS_COHERENT (1 << 1)
+
+struct geode_aes_op {
+
+        void *src;
+        void *dst;
+
+        u32 mode;
+        u32 dir;
+        u32 flags;
+        int len;
+
+        u8 key[AES_KEY_LENGTH];
+        u8 iv[AES_IV_LENGTH];
+};
+
+#endif
diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c
index c7bee4f2eedb..a1086ee8cccd 100644
--- a/drivers/md/dm-crypt.c
+++ b/drivers/md/dm-crypt.c
@@ -20,6 +20,7 @@
 #include <asm/atomic.h>
 #include <linux/scatterlist.h>
 #include <asm/page.h>
+#include <asm/unaligned.h>
 
 #include "dm.h"
 
@@ -85,7 +86,10 @@ struct crypt_config {
          */
         struct crypt_iv_operations *iv_gen_ops;
         char *iv_mode;
-        struct crypto_cipher *iv_gen_private;
+        union {
+                struct crypto_cipher *essiv_tfm;
+                int benbi_shift;
+        } iv_gen_private;
         sector_t iv_offset;
         unsigned int iv_size;
 
@@ -113,6 +117,9 @@ static struct kmem_cache *_crypt_io_pool;
  *        encrypted with the bulk cipher using a salt as key. The salt
  *        should be derived from the bulk cipher's key via hashing.
  *
+ * benbi: the 64-bit "big-endian 'narrow block'-count", starting at 1
+ *        (needed for LRW-32-AES and possible other narrow block modes)
+ *
  * plumb: unimplemented, see:
  * http://article.gmane.org/gmane.linux.kernel.device-mapper.dm-crypt/454
  */
@@ -191,21 +198,61 @@ static int crypt_iv_essiv_ctr(struct crypt_config *cc, struct dm_target *ti,
         }
         kfree(salt);
 
-        cc->iv_gen_private = essiv_tfm;
+        cc->iv_gen_private.essiv_tfm = essiv_tfm;
         return 0;
 }
 
 static void crypt_iv_essiv_dtr(struct crypt_config *cc)
 {
-        crypto_free_cipher(cc->iv_gen_private);
-        cc->iv_gen_private = NULL;
+        crypto_free_cipher(cc->iv_gen_private.essiv_tfm);
+        cc->iv_gen_private.essiv_tfm = NULL;
 }
 
 static int crypt_iv_essiv_gen(struct crypt_config *cc, u8 *iv, sector_t sector)
 {
         memset(iv, 0, cc->iv_size);
         *(u64 *)iv = cpu_to_le64(sector);
-        crypto_cipher_encrypt_one(cc->iv_gen_private, iv, iv);
+        crypto_cipher_encrypt_one(cc->iv_gen_private.essiv_tfm, iv, iv);
+        return 0;
+}
+
+static int crypt_iv_benbi_ctr(struct crypt_config *cc, struct dm_target *ti,
+                              const char *opts)
+{
+        unsigned int bs = crypto_blkcipher_blocksize(cc->tfm);
+        int log = long_log2(bs);
+
+        /* we need to calculate how far we must shift the sector count
+         * to get the cipher block count, we use this shift in _gen */
+
+        if (1 << log != bs) {
+                ti->error = "cypher blocksize is not a power of 2";
+                return -EINVAL;
+        }
+
+        if (log > 9) {
+                ti->error = "cypher blocksize is > 512";
+                return -EINVAL;
+        }
+
+        cc->iv_gen_private.benbi_shift = 9 - log;
+
+        return 0;
+}
+
+static void crypt_iv_benbi_dtr(struct crypt_config *cc)
+{
+}
+
+static int crypt_iv_benbi_gen(struct crypt_config *cc, u8 *iv, sector_t sector)
+{
+        __be64 val;
+
+        memset(iv, 0, cc->iv_size - sizeof(u64)); /* rest is cleared below */
+
+        val = cpu_to_be64(((u64)sector << cc->iv_gen_private.benbi_shift) + 1);
+        put_unaligned(val, (__be64 *)(iv + cc->iv_size - sizeof(u64)));
+
         return 0;
 }
 
@@ -219,13 +266,18 @@ static struct crypt_iv_operations crypt_iv_essiv_ops = {
         .generator = crypt_iv_essiv_gen
 };
 
+static struct crypt_iv_operations crypt_iv_benbi_ops = {
+        .ctr       = crypt_iv_benbi_ctr,
+        .dtr       = crypt_iv_benbi_dtr,
+        .generator = crypt_iv_benbi_gen
+};
 
 static int
 crypt_convert_scatterlist(struct crypt_config *cc, struct scatterlist *out,
                           struct scatterlist *in, unsigned int length,
                           int write, sector_t sector)
 {
-        u8 iv[cc->iv_size];
+        u8 iv[cc->iv_size] __attribute__ ((aligned(__alignof__(u64))));
         struct blkcipher_desc desc = {
                 .tfm = cc->tfm,
                 .info = iv,
@@ -768,7 +820,7 @@ static int crypt_ctr(struct dm_target *ti, unsigned int argc, char **argv)
         cc->tfm = tfm;
 
         /*
-         * Choose ivmode. Valid modes: "plain", "essiv:<esshash>".
+         * Choose ivmode. Valid modes: "plain", "essiv:<esshash>", "benbi".
          * See comments at iv code
          */
 
@@ -778,6 +830,8 @@ static int crypt_ctr(struct dm_target *ti, unsigned int argc, char **argv)
                 cc->iv_gen_ops = &crypt_iv_plain_ops;
         else if (strcmp(ivmode, "essiv") == 0)
                 cc->iv_gen_ops = &crypt_iv_essiv_ops;
+        else if (strcmp(ivmode, "benbi") == 0)
+                cc->iv_gen_ops = &crypt_iv_benbi_ops;
         else {
                 ti->error = "Invalid IV mode";
                 goto bad2;
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index f9a1c88a4283..9137e239fac2 100644
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -704,9 +704,9 @@ static int pxa_irda_stop(struct net_device *dev)
         return 0;
 }
 
-static int pxa_irda_suspend(struct device *_dev, pm_message_t state)
+static int pxa_irda_suspend(struct platform_device *_dev, pm_message_t state)
 {
-        struct net_device *dev = dev_get_drvdata(_dev);
+        struct net_device *dev = platform_get_drvdata(_dev);
         struct pxa_irda *si;
 
         if (dev && netif_running(dev)) {
@@ -718,9 +718,9 @@ static int pxa_irda_suspend(struct device *_dev, pm_message_t state)
         return 0;
 }
 
-static int pxa_irda_resume(struct device *_dev)
+static int pxa_irda_resume(struct platform_device *_dev)
 {
-        struct net_device *dev = dev_get_drvdata(_dev);
+        struct net_device *dev = platform_get_drvdata(_dev);
         struct pxa_irda *si;
 
         if (dev && netif_running(dev)) {
@@ -746,9 +746,8 @@ static int pxa_irda_init_iobuf(iobuff_t *io, int size)
         return io->head ? 0 : -ENOMEM;
 }
 
-static int pxa_irda_probe(struct device *_dev)
+static int pxa_irda_probe(struct platform_device *pdev)
 {
-        struct platform_device *pdev = to_platform_device(_dev);
         struct net_device *dev;
         struct pxa_irda *si;
         unsigned int baudrate_mask;
@@ -822,9 +821,9 @@ err_mem_1:
         return err;
 }
 
-static int pxa_irda_remove(struct device *_dev)
+static int pxa_irda_remove(struct platform_device *_dev)
 {
-        struct net_device *dev = dev_get_drvdata(_dev);
+        struct net_device *dev = platform_get_drvdata(_dev);
 
         if (dev) {
                 struct pxa_irda *si = netdev_priv(dev);
@@ -840,9 +839,10 @@ static int pxa_irda_remove(struct device *_dev)
         return 0;
 }
 
-static struct device_driver pxa_ir_driver = {
-        .name           = "pxa2xx-ir",
-        .bus            = &platform_bus_type,
+static struct platform_driver pxa_ir_driver = {
+        .driver         = {
+                .name   = "pxa2xx-ir",
+        },
         .probe          = pxa_irda_probe,
         .remove         = pxa_irda_remove,
         .suspend        = pxa_irda_suspend,
@@ -851,12 +851,12 @@ static struct device_driver pxa_ir_driver = {
 
 static int __init pxa_irda_init(void)
 {
-        return driver_register(&pxa_ir_driver);
+        return platform_driver_register(&pxa_ir_driver);
 }
 
 static void __exit pxa_irda_exit(void)
 {
-        driver_unregister(&pxa_ir_driver);
+        platform_driver_unregister(&pxa_ir_driver);
 }
 
 module_init(pxa_irda_init);
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index d9123c9adc1e..571320ae87ab 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -68,8 +68,8 @@
 
 #define DRV_MODULE_NAME         "tg3"
 #define PFX DRV_MODULE_NAME     ": "
-#define DRV_MODULE_VERSION      "3.69"
-#define DRV_MODULE_RELDATE      "November 15, 2006"
+#define DRV_MODULE_VERSION      "3.70"
+#define DRV_MODULE_RELDATE      "December 1, 2006"
 
 #define TG3_DEF_MAC_MODE        0
 #define TG3_DEF_RX_MODE         0
@@ -192,6 +192,7 @@ static struct pci_device_id tg3_pci_tbl[] = {
         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
+        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
@@ -1061,7 +1062,7 @@ static void tg3_frob_aux_power(struct tg3 *tp)
 {
         struct tg3 *tp_peer = tp;
 
-        if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
+        if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
                 return;
 
         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
@@ -1212,8 +1213,8 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
                                       power_control);
                 udelay(100);    /* Delay after power state change */
 
-                /* Switch out of Vaux if it is not a LOM */
-                if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
+                /* Switch out of Vaux if it is a NIC */
+                if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
 
                 return 0;
@@ -1401,8 +1402,10 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
 static void tg3_link_report(struct tg3 *tp)
 {
         if (!netif_carrier_ok(tp->dev)) {
-                printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
-        } else {
+                if (netif_msg_link(tp))
+                        printk(KERN_INFO PFX "%s: Link is down.\n",
+                               tp->dev->name);
+        } else if (netif_msg_link(tp)) {
                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
                        tp->dev->name,
                        (tp->link_config.active_speed == SPEED_1000 ?
@@ -1557,12 +1560,6 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
 
                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
         } else if (tp->link_config.speed == SPEED_INVALID) {
-                tp->link_config.advertising =
-                        (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
-                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
-                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
-                         ADVERTISED_Autoneg | ADVERTISED_MII);
-
                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
                         tp->link_config.advertising &=
                                 ~(ADVERTISED_1000baseT_Half |
@@ -1706,25 +1703,36 @@ static int tg3_init_5401phy_dsp(struct tg3 *tp)
         return err;
 }
 
-static int tg3_copper_is_advertising_all(struct tg3 *tp)
+static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
 {
-        u32 adv_reg, all_mask;
+        u32 adv_reg, all_mask = 0;
+
+        if (mask & ADVERTISED_10baseT_Half)
+                all_mask |= ADVERTISE_10HALF;
+        if (mask & ADVERTISED_10baseT_Full)
+                all_mask |= ADVERTISE_10FULL;
+        if (mask & ADVERTISED_100baseT_Half)
+                all_mask |= ADVERTISE_100HALF;
+        if (mask & ADVERTISED_100baseT_Full)
+                all_mask |= ADVERTISE_100FULL;
 
         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
                 return 0;
 
-        all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
-                    ADVERTISE_100HALF | ADVERTISE_100FULL);
         if ((adv_reg & all_mask) != all_mask)
                 return 0;
         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
                 u32 tg3_ctrl;
 
+                all_mask = 0;
+                if (mask & ADVERTISED_1000baseT_Half)
+                        all_mask |= ADVERTISE_1000HALF;
+                if (mask & ADVERTISED_1000baseT_Full)
+                        all_mask |= ADVERTISE_1000FULL;
+
                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
                         return 0;
 
-                all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
-                            MII_TG3_CTRL_ADV_1000_FULL);
                 if ((tg3_ctrl & all_mask) != all_mask)
                         return 0;
         }
@@ -1884,7 +1892,8 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
                                 /* Force autoneg restart if we are exiting
                                  * low power mode.
                                  */
-                                if (!tg3_copper_is_advertising_all(tp))
+                                if (!tg3_copper_is_advertising_all(tp,
+                                                tp->link_config.advertising))
                                         current_link_up = 0;
                         } else {
                                 current_link_up = 0;
@@ -3703,8 +3712,9 @@ static void tg3_tx_timeout(struct net_device *dev)
 {
         struct tg3 *tp = netdev_priv(dev);
 
-        printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
-               dev->name);
+        if (netif_msg_tx_err(tp))
+                printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
+                       dev->name);
 
         schedule_work(&tp->reset_task);
 }
@@ -6396,16 +6406,17 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
         udelay(40);
 
         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
-         * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
+         * If TG3_FLG2_IS_NIC is zero, we should read the
          * register to preserve the GPIO settings for LOMs. The GPIOs,
          * whether used as inputs or outputs, are set by boot code after
          * reset.
          */
-        if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
+        if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
                 u32 gpio_mask;
 
-                gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
-                            GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
+                gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
+                            GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
+                            GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
 
                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
@@ -6417,8 +6428,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
 
                 /* GPIO1 must be driven high for eeprom write protect */
-                tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
-                                       GRC_LCLCTRL_GPIO_OUTPUT1);
+                if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
+                        tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
+                                               GRC_LCLCTRL_GPIO_OUTPUT1);
         }
         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
         udelay(100);
@@ -8656,7 +8668,9 @@ static int tg3_test_registers(struct tg3 *tp)
         return 0;
 
 out:
-        printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
+        if (netif_msg_hw(tp))
+                printk(KERN_ERR PFX "Register test failed at offset %x\n",
+                       offset);
         tw32(offset, save_val);
         return -EIO;
 }
@@ -8781,17 +8795,20 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
                                         tg3_writephy(tp, 0x10, phy & ~0x4000);
                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
                         }
-                }
-                val = BMCR_LOOPBACK | BMCR_FULLDPLX;
-                if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
-                        val |= BMCR_SPEED100;
-                else
-                        val |= BMCR_SPEED1000;
+                        val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
+                } else
+                        val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
 
                 tg3_writephy(tp, MII_BMCR, val);
                 udelay(40);
-                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
+
+                mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
+                           MAC_MODE_LINK_POLARITY;
+                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
+                        mac_mode |= MAC_MODE_PORT_MODE_MII;
+                } else
+                        mac_mode |= MAC_MODE_PORT_MODE_GMII;
 
                 /* reset to prevent losing 1st rx packet intermittently */
                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
@@ -8799,12 +8816,6 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
                         udelay(10);
                         tw32_f(MAC_RX_MODE, tp->rx_mode);
                 }
-                mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
-                           MAC_MODE_LINK_POLARITY;
-                if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
-                        mac_mode |= MAC_MODE_PORT_MODE_MII;
-                else
-                        mac_mode |= MAC_MODE_PORT_MODE_GMII;
                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
@@ -9456,16 +9467,12 @@ static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
 static void __devinit tg3_nvram_init(struct tg3 *tp)
 {
-        int j;
-
         tw32_f(GRC_EEPROM_ADDR,
              (EEPROM_ADDR_FSM_RESET |
               (EEPROM_DEFAULT_CLOCK_PERIOD <<
                EEPROM_ADDR_CLKPERD_SHIFT)));
 
-        /* XXX schedule_timeout() ... */
-        for (j = 0; j < 100; j++)
-                udelay(10);
+        msleep(1);
 
         /* Enable seeprom accesses. */
         tw32_f(GRC_LOCAL_CTRL,
@@ -9526,12 +9533,12 @@ static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
               EEPROM_ADDR_ADDR_MASK) |
              EEPROM_ADDR_READ | EEPROM_ADDR_START);
 
-        for (i = 0; i < 10000; i++) {
+        for (i = 0; i < 1000; i++) {
                 tmp = tr32(GRC_EEPROM_ADDR);
 
                 if (tmp & EEPROM_ADDR_COMPLETE)
                         break;
-                udelay(100);
+                msleep(1);
         }
         if (!(tmp & EEPROM_ADDR_COMPLETE))
                 return -EBUSY;
@@ -9656,12 +9663,12 @@ static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
                         EEPROM_ADDR_START |
                         EEPROM_ADDR_WRITE);
 
-                for (j = 0; j < 10000; j++) {
+                for (j = 0; j < 1000; j++) {
                         val = tr32(GRC_EEPROM_ADDR);
 
                         if (val & EEPROM_ADDR_COMPLETE)
                                 break;
-                        udelay(100);
+                        msleep(1);
                 }
                 if (!(val & EEPROM_ADDR_COMPLETE)) {
                         rc = -EBUSY;
@@ -9965,8 +9972,10 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
 
         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
-                if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM))
+                if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
+                        tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
+                }
                 return;
         }
 
@@ -10066,10 +10075,17 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
 
-                if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)
+                if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
-                else
+                        if ((tp->pdev->subsystem_vendor ==
+                             PCI_VENDOR_ID_ARIMA) &&
+                            (tp->pdev->subsystem_device == 0x205a ||
+                             tp->pdev->subsystem_device == 0x2063))
+                                tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
+                } else {
                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
+                        tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
+                }
 
                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
@@ -10147,7 +10163,7 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
 
         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
-                u32 bmsr, adv_reg, tg3_ctrl;
+                u32 bmsr, adv_reg, tg3_ctrl, mask;
 
                 tg3_readphy(tp, MII_BMSR, &bmsr);
                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
@@ -10171,7 +10187,10 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
                 }
 
-                if (!tg3_copper_is_advertising_all(tp)) {
+                mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
+                        ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
+                        ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
+                if (!tg3_copper_is_advertising_all(tp, mask)) {
                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
 
                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
@@ -10695,7 +10714,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
 
         /* Get eeprom hw config before calling tg3_set_power_state().
-         * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
+         * In particular, the TG3_FLG2_IS_NIC flag must be
          * determined before calling tg3_set_power_state() so that
          * we know whether or not to switch out of Vaux power.
          * When the flag is set, it means that GPIO1 is used for eeprom
@@ -10862,7 +10881,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
-              tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)) ||
+              tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
+              tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
 
@@ -11912,13 +11932,15 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
 
         pci_set_drvdata(pdev, dev);
 
-        printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
+        printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
                dev->name,
                tp->board_part_number,
                tp->pci_chip_rev_id,
                tg3_phy_string(tp),
                tg3_bus_string(tp, str),
-               (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
+               ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
+                ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
+                 "10/100/1000Base-T")));
 
         for (i = 0; i < 6; i++)
                 printk("%2.2x%c", dev->dev_addr[i],
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 92f53000bce6..dfaf4ed127bd 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2233,6 +2233,7 @@ struct tg3 {
 #define TG3_FLG2_PCI_EXPRESS            0x00000200
 #define TG3_FLG2_ASF_NEW_HANDSHAKE      0x00000400
 #define TG3_FLG2_HW_AUTONEG             0x00000800
+#define TG3_FLG2_IS_NIC                 0x00001000
 #define TG3_FLG2_PHY_SERDES             0x00002000
 #define TG3_FLG2_CAPACITIVE_COUPLING    0x00004000
 #define TG3_FLG2_FLASH                  0x00008000