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-rw-r--r--drivers/net/s2io.c54
-rw-r--r--drivers/net/s2io.h5
2 files changed, 40 insertions, 19 deletions
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c
index abf910e40334..e083351e3f42 100644
--- a/drivers/net/s2io.c
+++ b/drivers/net/s2io.c
@@ -67,7 +67,7 @@
67 67
68/* S2io Driver name & version. */ 68/* S2io Driver name & version. */
69static char s2io_driver_name[] = "Neterion"; 69static char s2io_driver_name[] = "Neterion";
70static char s2io_driver_version[] = "Version 2.0.2.0"; 70static char s2io_driver_version[] = "Version 2.0.2.1";
71 71
72static inline int RXD_IS_UP2DT(RxD_t *rxdp) 72static inline int RXD_IS_UP2DT(RxD_t *rxdp)
73{ 73{
@@ -301,6 +301,8 @@ static unsigned int bimodal = 0;
301#ifndef CONFIG_S2IO_NAPI 301#ifndef CONFIG_S2IO_NAPI
302static unsigned int indicate_max_pkts; 302static unsigned int indicate_max_pkts;
303#endif 303#endif
304/* Frequency of Rx desc syncs expressed as power of 2 */
305static unsigned int rxsync_frequency = 3;
304 306
305/* 307/*
306 * S2IO device table. 308 * S2IO device table.
@@ -837,7 +839,7 @@ static int init_nic(struct s2io_nic *nic)
837 */ 839 */
838 if (nic->device_type & XFRAME_II_DEVICE) { 840 if (nic->device_type & XFRAME_II_DEVICE) {
839 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) { 841 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
840 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt], 842 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
841 &bar0->dtx_control, UF); 843 &bar0->dtx_control, UF);
842 if (dtx_cnt & 0x1) 844 if (dtx_cnt & 0x1)
843 msleep(1); /* Necessary!! */ 845 msleep(1); /* Necessary!! */
@@ -2083,6 +2085,7 @@ int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2083#ifndef CONFIG_S2IO_NAPI 2085#ifndef CONFIG_S2IO_NAPI
2084 unsigned long flags; 2086 unsigned long flags;
2085#endif 2087#endif
2088 RxD_t *first_rxdp = NULL;
2086 2089
2087 mac_control = &nic->mac_control; 2090 mac_control = &nic->mac_control;
2088 config = &nic->config; 2091 config = &nic->config;
@@ -2202,6 +2205,10 @@ int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2202 if (!skb) { 2205 if (!skb) {
2203 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name); 2206 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2204 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n"); 2207 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2208 if (first_rxdp) {
2209 wmb();
2210 first_rxdp->Control_1 |= RXD_OWN_XENA;
2211 }
2205 return -ENOMEM; 2212 return -ENOMEM;
2206 } 2213 }
2207#ifndef CONFIG_2BUFF_MODE 2214#ifndef CONFIG_2BUFF_MODE
@@ -2212,7 +2219,8 @@ int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2212 rxdp->Control_2 &= (~MASK_BUFFER0_SIZE); 2219 rxdp->Control_2 &= (~MASK_BUFFER0_SIZE);
2213 rxdp->Control_2 |= SET_BUFFER0_SIZE(size); 2220 rxdp->Control_2 |= SET_BUFFER0_SIZE(size);
2214 rxdp->Host_Control = (unsigned long) (skb); 2221 rxdp->Host_Control = (unsigned long) (skb);
2215 rxdp->Control_1 |= RXD_OWN_XENA; 2222 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2223 rxdp->Control_1 |= RXD_OWN_XENA;
2216 off++; 2224 off++;
2217 off %= (MAX_RXDS_PER_BLOCK + 1); 2225 off %= (MAX_RXDS_PER_BLOCK + 1);
2218 mac_control->rings[ring_no].rx_curr_put_info.offset = off; 2226 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
@@ -2239,17 +2247,34 @@ int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2239 rxdp->Control_2 |= SET_BUFFER1_SIZE(1); /* dummy. */ 2247 rxdp->Control_2 |= SET_BUFFER1_SIZE(1); /* dummy. */
2240 rxdp->Control_2 |= BIT(0); /* Set Buffer_Empty bit. */ 2248 rxdp->Control_2 |= BIT(0); /* Set Buffer_Empty bit. */
2241 rxdp->Host_Control = (u64) ((unsigned long) (skb)); 2249 rxdp->Host_Control = (u64) ((unsigned long) (skb));
2242 rxdp->Control_1 |= RXD_OWN_XENA; 2250 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2251 rxdp->Control_1 |= RXD_OWN_XENA;
2243 off++; 2252 off++;
2244 mac_control->rings[ring_no].rx_curr_put_info.offset = off; 2253 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2245#endif 2254#endif
2246 rxdp->Control_2 |= SET_RXD_MARKER; 2255 rxdp->Control_2 |= SET_RXD_MARKER;
2247 2256
2257 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2258 if (first_rxdp) {
2259 wmb();
2260 first_rxdp->Control_1 |= RXD_OWN_XENA;
2261 }
2262 first_rxdp = rxdp;
2263 }
2248 atomic_inc(&nic->rx_bufs_left[ring_no]); 2264 atomic_inc(&nic->rx_bufs_left[ring_no]);
2249 alloc_tab++; 2265 alloc_tab++;
2250 } 2266 }
2251 2267
2252 end: 2268 end:
2269 /* Transfer ownership of first descriptor to adapter just before
2270 * exiting. Before that, use memory barrier so that ownership
2271 * and other fields are seen by adapter correctly.
2272 */
2273 if (first_rxdp) {
2274 wmb();
2275 first_rxdp->Control_1 |= RXD_OWN_XENA;
2276 }
2277
2253 return SUCCESS; 2278 return SUCCESS;
2254} 2279}
2255 2280
@@ -2783,16 +2808,16 @@ void s2io_reset(nic_t * sp)
2783 s2io_set_swapper(sp); 2808 s2io_set_swapper(sp);
2784 2809
2785 /* Clear certain PCI/PCI-X fields after reset */ 2810 /* Clear certain PCI/PCI-X fields after reset */
2786 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd); 2811 if (sp->device_type == XFRAME_II_DEVICE) {
2787 pci_cmd &= 0x7FFF; /* Clear parity err detect bit */ 2812 /* Clear parity err detect bit */
2788 pci_write_config_word(sp->pdev, PCI_COMMAND, pci_cmd); 2813 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
2789 2814
2790 val64 = readq(&bar0->txpic_int_reg); 2815 /* Clearing PCIX Ecc status register */
2791 val64 &= ~BIT(62); /* Clearing PCI_STATUS error reflected here */ 2816 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
2792 writeq(val64, &bar0->txpic_int_reg);
2793 2817
2794 /* Clearing PCIX Ecc status register */ 2818 /* Clearing PCI_STATUS error reflected here */
2795 pci_write_config_dword(sp->pdev, 0x68, 0); 2819 writeq(BIT(62), &bar0->txpic_int_reg);
2820 }
2796 2821
2797 /* Reset device statistics maintained by OS */ 2822 /* Reset device statistics maintained by OS */
2798 memset(&sp->stats, 0, sizeof (struct net_device_stats)); 2823 memset(&sp->stats, 0, sizeof (struct net_device_stats));
@@ -3168,8 +3193,6 @@ int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3168 val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr; 3193 val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
3169 writeq(val64, &tx_fifo->TxDL_Pointer); 3194 writeq(val64, &tx_fifo->TxDL_Pointer);
3170 3195
3171 wmb();
3172
3173 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST | 3196 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
3174 TX_FIFO_LAST_LIST); 3197 TX_FIFO_LAST_LIST);
3175 3198
@@ -3179,6 +3202,8 @@ int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3179#endif 3202#endif
3180 writeq(val64, &tx_fifo->List_Control); 3203 writeq(val64, &tx_fifo->List_Control);
3181 3204
3205 mmiowb();
3206
3182 put_off++; 3207 put_off++;
3183 put_off %= mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1; 3208 put_off %= mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3184 mac_control->fifos[queue].tx_curr_put_info.offset = put_off; 3209 mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
@@ -5172,6 +5197,7 @@ module_param(bimodal, bool, 0);
5172#ifndef CONFIG_S2IO_NAPI 5197#ifndef CONFIG_S2IO_NAPI
5173module_param(indicate_max_pkts, int, 0); 5198module_param(indicate_max_pkts, int, 0);
5174#endif 5199#endif
5200module_param(rxsync_frequency, int, 0);
5175 5201
5176/** 5202/**
5177 * s2io_init_nic - Initialization of the adapter . 5203 * s2io_init_nic - Initialization of the adapter .
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h
index 946314503daa..5d9270730ca2 100644
--- a/drivers/net/s2io.h
+++ b/drivers/net/s2io.h
@@ -13,11 +13,6 @@
13#ifndef _S2IO_H 13#ifndef _S2IO_H
14#define _S2IO_H 14#define _S2IO_H
15 15
16/* Enable 2 buffer mode by default for SGI system */
17#ifdef CONFIG_IA64_SGI_SN2
18#define CONFIG_2BUFF_MODE
19#endif
20
21#define TBD 0 16#define TBD 0
22#define BIT(loc) (0x8000000000000000ULL >> (loc)) 17#define BIT(loc) (0x8000000000000000ULL >> (loc))
23#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz)) 18#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))