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-rw-r--r--drivers/net/fec.c24
1 files changed, 13 insertions, 11 deletions
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index c3229713b1e2..74798bee672e 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -339,7 +339,8 @@ fec_restart(struct net_device *ndev, int duplex)
339 const struct platform_device_id *id_entry = 339 const struct platform_device_id *id_entry =
340 platform_get_device_id(fep->pdev); 340 platform_get_device_id(fep->pdev);
341 int i; 341 int i;
342 u32 val, temp_mac[2]; 342 u32 temp_mac[2];
343 u32 rcntl = OPT_FRAME_SIZE | 0x04;
343 344
344 /* Whack a reset. We should wait for this. */ 345 /* Whack a reset. We should wait for this. */
345 writel(1, fep->hwp + FEC_ECNTRL); 346 writel(1, fep->hwp + FEC_ECNTRL);
@@ -388,14 +389,14 @@ fec_restart(struct net_device *ndev, int duplex)
388 389
389 /* Enable MII mode */ 390 /* Enable MII mode */
390 if (duplex) { 391 if (duplex) {
391 /* MII enable / FD enable */ 392 /* FD enable */
392 writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
393 writel(0x04, fep->hwp + FEC_X_CNTRL); 393 writel(0x04, fep->hwp + FEC_X_CNTRL);
394 } else { 394 } else {
395 /* MII enable / No Rcv on Xmit */ 395 /* No Rcv on Xmit */
396 writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL); 396 rcntl |= 0x02;
397 writel(0x0, fep->hwp + FEC_X_CNTRL); 397 writel(0x0, fep->hwp + FEC_X_CNTRL);
398 } 398 }
399
399 fep->full_duplex = duplex; 400 fep->full_duplex = duplex;
400 401
401 /* Set MII speed */ 402 /* Set MII speed */
@@ -406,21 +407,21 @@ fec_restart(struct net_device *ndev, int duplex)
406 * differently on enet-mac. 407 * differently on enet-mac.
407 */ 408 */
408 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 409 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
409 val = readl(fep->hwp + FEC_R_CNTRL); 410 /* Enable flow control and length check */
411 rcntl |= 0x40000000 | 0x00000020;
410 412
411 /* MII or RMII */ 413 /* MII or RMII */
412 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 414 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
413 val |= (1 << 8); 415 rcntl |= (1 << 8);
414 else 416 else
415 val &= ~(1 << 8); 417 rcntl &= ~(1 << 8);
416 418
417 /* 10M or 100M */ 419 /* 10M or 100M */
418 if (fep->phy_dev && fep->phy_dev->speed == SPEED_100) 420 if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
419 val &= ~(1 << 9); 421 rcntl &= ~(1 << 9);
420 else 422 else
421 val |= (1 << 9); 423 rcntl |= (1 << 9);
422 424
423 writel(val, fep->hwp + FEC_R_CNTRL);
424 } else { 425 } else {
425#ifdef FEC_MIIGSK_ENR 426#ifdef FEC_MIIGSK_ENR
426 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) { 427 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
@@ -440,6 +441,7 @@ fec_restart(struct net_device *ndev, int duplex)
440 } 441 }
441#endif 442#endif
442 } 443 }
444 writel(rcntl, fep->hwp + FEC_R_CNTRL);
443 445
444 /* And last, enable the transmit and receive processing */ 446 /* And last, enable the transmit and receive processing */
445 writel(2, fep->hwp + FEC_ECNTRL); 447 writel(2, fep->hwp + FEC_ECNTRL);