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-rw-r--r--drivers/gpu/drm/ati_pcigart.c10
-rw-r--r--drivers/gpu/drm/drm_bufs.c4
-rw-r--r--drivers/gpu/drm/drm_crtc_helper.c29
-rw-r--r--drivers/gpu/drm/drm_edid.c17
-rw-r--r--drivers/gpu/drm/drm_fb_helper.c11
-rw-r--r--drivers/gpu/drm/drm_pci.c8
-rw-r--r--drivers/gpu/drm/i2c/ch7006_drv.c5
-rw-r--r--drivers/gpu/drm/i2c/ch7006_mode.c5
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c2
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c2
-rw-r--r--drivers/gpu/drm/nouveau/Kconfig5
-rw-r--r--drivers/gpu/drm/nouveau/Makefile5
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c808
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.h1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.c262
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_channel.c47
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_connector.c39
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dma.c108
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dma.h10
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dp.c36
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.c10
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h102
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fbcon.c41
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fbcon.h1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fence.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_gem.c53
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_grctx.c161
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_grctx.h133
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_irq.c8
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c102
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_object.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_reg.h16
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c175
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_ttm.c30
-rw-r--r--drivers/gpu/drm/nouveau/nv04_crtc.c10
-rw-r--r--drivers/gpu/drm/nouveau/nv04_dac.c43
-rw-r--r--drivers/gpu/drm/nouveau/nv04_dfp.c8
-rw-r--r--drivers/gpu/drm/nouveau/nv04_display.c11
-rw-r--r--drivers/gpu/drm/nouveau/nv04_fbcon.c41
-rw-r--r--drivers/gpu/drm/nouveau/nv04_fifo.c34
-rw-r--r--drivers/gpu/drm/nouveau/nv04_graph.c161
-rw-r--r--drivers/gpu/drm/nouveau/nv04_instmem.c2
-rw-r--r--drivers/gpu/drm/nouveau/nv10_fb.c32
-rw-r--r--drivers/gpu/drm/nouveau/nv10_graph.c225
-rw-r--r--drivers/gpu/drm/nouveau/nv17_tv.c119
-rw-r--r--drivers/gpu/drm/nouveau/nv20_graph.c61
-rw-r--r--drivers/gpu/drm/nouveau/nv40_fb.c53
-rw-r--r--drivers/gpu/drm/nouveau/nv40_graph.c310
-rw-r--r--drivers/gpu/drm/nouveau/nv40_grctx.c678
-rw-r--r--drivers/gpu/drm/nouveau/nv50_crtc.c44
-rw-r--r--drivers/gpu/drm/nouveau/nv50_cursor.c8
-rw-r--r--drivers/gpu/drm/nouveau/nv50_dac.c20
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c37
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fbcon.c23
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fifo.c10
-rw-r--r--drivers/gpu/drm/nouveau/nv50_graph.c13
-rw-r--r--drivers/gpu/drm/nouveau/nv50_sor.c29
-rw-r--r--drivers/gpu/drm/ttm/ttm_bo.c61
-rw-r--r--drivers/gpu/drm/ttm/ttm_lock.c2
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c16
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.c63
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.h3
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_fb.c8
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c3
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_kms.c12
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c9
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_resource.c62
67 files changed, 3000 insertions, 1461 deletions
diff --git a/drivers/gpu/drm/ati_pcigart.c b/drivers/gpu/drm/ati_pcigart.c
index 628eae3e9b83..a1fce68e3bbe 100644
--- a/drivers/gpu/drm/ati_pcigart.c
+++ b/drivers/gpu/drm/ati_pcigart.c
@@ -39,8 +39,7 @@ static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
39 struct drm_ati_pcigart_info *gart_info) 39 struct drm_ati_pcigart_info *gart_info)
40{ 40{
41 gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size, 41 gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size,
42 PAGE_SIZE, 42 PAGE_SIZE);
43 gart_info->table_mask);
44 if (gart_info->table_handle == NULL) 43 if (gart_info->table_handle == NULL)
45 return -ENOMEM; 44 return -ENOMEM;
46 45
@@ -112,6 +111,13 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga
112 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) { 111 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
113 DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n"); 112 DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
114 113
114 if (pci_set_dma_mask(dev->pdev, gart_info->table_mask)) {
115 DRM_ERROR("fail to set dma mask to 0x%Lx\n",
116 gart_info->table_mask);
117 ret = 1;
118 goto done;
119 }
120
115 ret = drm_ati_alloc_pcigart_table(dev, gart_info); 121 ret = drm_ati_alloc_pcigart_table(dev, gart_info);
116 if (ret) { 122 if (ret) {
117 DRM_ERROR("cannot allocate PCI GART page!\n"); 123 DRM_ERROR("cannot allocate PCI GART page!\n");
diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index 3d09e304f6f4..8417cc4c43f1 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -326,7 +326,7 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset,
326 * As we're limiting the address to 2^32-1 (or less), 326 * As we're limiting the address to 2^32-1 (or less),
327 * casting it down to 32 bits is no problem, but we 327 * casting it down to 32 bits is no problem, but we
328 * need to point to a 64bit variable first. */ 328 * need to point to a 64bit variable first. */
329 dmah = drm_pci_alloc(dev, map->size, map->size, 0xffffffffUL); 329 dmah = drm_pci_alloc(dev, map->size, map->size);
330 if (!dmah) { 330 if (!dmah) {
331 kfree(map); 331 kfree(map);
332 return -ENOMEM; 332 return -ENOMEM;
@@ -885,7 +885,7 @@ int drm_addbufs_pci(struct drm_device * dev, struct drm_buf_desc * request)
885 885
886 while (entry->buf_count < count) { 886 while (entry->buf_count < count) {
887 887
888 dmah = drm_pci_alloc(dev, PAGE_SIZE << page_order, 0x1000, 0xfffffffful); 888 dmah = drm_pci_alloc(dev, PAGE_SIZE << page_order, 0x1000);
889 889
890 if (!dmah) { 890 if (!dmah) {
891 /* Set count correctly so we free the proper amount. */ 891 /* Set count correctly so we free the proper amount. */
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index 4231d6db72ec..7d0f00a935fa 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -216,7 +216,7 @@ bool drm_helper_crtc_in_use(struct drm_crtc *crtc)
216EXPORT_SYMBOL(drm_helper_crtc_in_use); 216EXPORT_SYMBOL(drm_helper_crtc_in_use);
217 217
218/** 218/**
219 * drm_disable_unused_functions - disable unused objects 219 * drm_helper_disable_unused_functions - disable unused objects
220 * @dev: DRM device 220 * @dev: DRM device
221 * 221 *
222 * LOCKING: 222 * LOCKING:
@@ -702,7 +702,7 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
702 if (encoder->crtc != crtc) 702 if (encoder->crtc != crtc)
703 continue; 703 continue;
704 704
705 DRM_INFO("%s: set mode %s %x\n", drm_get_encoder_name(encoder), 705 DRM_DEBUG("%s: set mode %s %x\n", drm_get_encoder_name(encoder),
706 mode->name, mode->base.id); 706 mode->name, mode->base.id);
707 encoder_funcs = encoder->helper_private; 707 encoder_funcs = encoder->helper_private;
708 encoder_funcs->mode_set(encoder, mode, adjusted_mode); 708 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
@@ -1032,7 +1032,8 @@ bool drm_helper_initial_config(struct drm_device *dev)
1032 /* 1032 /*
1033 * we shouldn't end up with no modes here. 1033 * we shouldn't end up with no modes here.
1034 */ 1034 */
1035 WARN(!count, "No connectors reported connected with modes\n"); 1035 if (count == 0)
1036 printk(KERN_INFO "No connectors reported connected with modes\n");
1036 1037
1037 drm_setup_crtcs(dev); 1038 drm_setup_crtcs(dev);
1038 1039
@@ -1162,6 +1163,9 @@ EXPORT_SYMBOL(drm_helper_mode_fill_fb_struct);
1162int drm_helper_resume_force_mode(struct drm_device *dev) 1163int drm_helper_resume_force_mode(struct drm_device *dev)
1163{ 1164{
1164 struct drm_crtc *crtc; 1165 struct drm_crtc *crtc;
1166 struct drm_encoder *encoder;
1167 struct drm_encoder_helper_funcs *encoder_funcs;
1168 struct drm_crtc_helper_funcs *crtc_funcs;
1165 int ret; 1169 int ret;
1166 1170
1167 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1171 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
@@ -1174,6 +1178,25 @@ int drm_helper_resume_force_mode(struct drm_device *dev)
1174 1178
1175 if (ret == false) 1179 if (ret == false)
1176 DRM_ERROR("failed to set mode on crtc %p\n", crtc); 1180 DRM_ERROR("failed to set mode on crtc %p\n", crtc);
1181
1182 /* Turn off outputs that were already powered off */
1183 if (drm_helper_choose_crtc_dpms(crtc)) {
1184 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1185
1186 if(encoder->crtc != crtc)
1187 continue;
1188
1189 encoder_funcs = encoder->helper_private;
1190 if (encoder_funcs->dpms)
1191 (*encoder_funcs->dpms) (encoder,
1192 drm_helper_choose_encoder_dpms(encoder));
1193
1194 crtc_funcs = crtc->helper_private;
1195 if (crtc_funcs->dpms)
1196 (*crtc_funcs->dpms) (crtc,
1197 drm_helper_choose_crtc_dpms(crtc));
1198 }
1199 }
1177 } 1200 }
1178 /* disable the unused connectors while restoring the modesetting */ 1201 /* disable the unused connectors while restoring the modesetting */
1179 drm_helper_disable_unused_functions(dev); 1202 drm_helper_disable_unused_functions(dev);
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 5c9f79877cbf..f665b05592f3 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -633,8 +633,7 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
633 return NULL; 633 return NULL;
634 } 634 }
635 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 635 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
636 printk(KERN_WARNING "integrated sync not supported\n"); 636 printk(KERN_WARNING "composite sync not supported\n");
637 return NULL;
638 } 637 }
639 638
640 /* it is incorrect if hsync/vsync width is zero */ 639 /* it is incorrect if hsync/vsync width is zero */
@@ -911,23 +910,27 @@ static int drm_cvt_modes(struct drm_connector *connector,
911 struct drm_device *dev = connector->dev; 910 struct drm_device *dev = connector->dev;
912 struct cvt_timing *cvt; 911 struct cvt_timing *cvt;
913 const int rates[] = { 60, 85, 75, 60, 50 }; 912 const int rates[] = { 60, 85, 75, 60, 50 };
913 const u8 empty[3] = { 0, 0, 0 };
914 914
915 for (i = 0; i < 4; i++) { 915 for (i = 0; i < 4; i++) {
916 int uninitialized_var(width), height; 916 int uninitialized_var(width), height;
917 cvt = &(timing->data.other_data.data.cvt[i]); 917 cvt = &(timing->data.other_data.data.cvt[i]);
918 918
919 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 8) + 1) * 2; 919 if (!memcmp(cvt->code, empty, 3))
920 switch (cvt->code[1] & 0xc0) { 920 continue;
921
922 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
923 switch (cvt->code[1] & 0x0c) {
921 case 0x00: 924 case 0x00:
922 width = height * 4 / 3; 925 width = height * 4 / 3;
923 break; 926 break;
924 case 0x40: 927 case 0x04:
925 width = height * 16 / 9; 928 width = height * 16 / 9;
926 break; 929 break;
927 case 0x80: 930 case 0x08:
928 width = height * 16 / 10; 931 width = height * 16 / 10;
929 break; 932 break;
930 case 0xc0: 933 case 0x0c:
931 width = height * 15 / 9; 934 width = height * 15 / 9;
932 break; 935 break;
933 } 936 }
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 1b49fa055f4f..1c2b7d44ec05 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -156,7 +156,7 @@ static bool drm_fb_helper_connector_parse_command_line(struct drm_connector *con
156 force = DRM_FORCE_ON; 156 force = DRM_FORCE_ON;
157 break; 157 break;
158 case 'D': 158 case 'D':
159 if ((connector->connector_type != DRM_MODE_CONNECTOR_DVII) || 159 if ((connector->connector_type != DRM_MODE_CONNECTOR_DVII) &&
160 (connector->connector_type != DRM_MODE_CONNECTOR_HDMIB)) 160 (connector->connector_type != DRM_MODE_CONNECTOR_HDMIB))
161 force = DRM_FORCE_ON; 161 force = DRM_FORCE_ON;
162 else 162 else
@@ -606,11 +606,10 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo *var,
606 return -EINVAL; 606 return -EINVAL;
607 607
608 /* Need to resize the fb object !!! */ 608 /* Need to resize the fb object !!! */
609 if (var->xres > fb->width || var->yres > fb->height) { 609 if (var->bits_per_pixel > fb->bits_per_pixel || var->xres > fb->width || var->yres > fb->height) {
610 DRM_ERROR("Requested width/height is greater than current fb " 610 DRM_DEBUG("fb userspace requested width/height/bpp is greater than current fb "
611 "object %dx%d > %dx%d\n", var->xres, var->yres, 611 "object %dx%d-%d > %dx%d-%d\n", var->xres, var->yres, var->bits_per_pixel,
612 fb->width, fb->height); 612 fb->width, fb->height, fb->bits_per_pixel);
613 DRM_ERROR("Need resizing code.\n");
614 return -EINVAL; 613 return -EINVAL;
615 } 614 }
616 615
diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
index 577094fb1995..e68ebf92fa2a 100644
--- a/drivers/gpu/drm/drm_pci.c
+++ b/drivers/gpu/drm/drm_pci.c
@@ -47,8 +47,7 @@
47/** 47/**
48 * \brief Allocate a PCI consistent memory block, for DMA. 48 * \brief Allocate a PCI consistent memory block, for DMA.
49 */ 49 */
50drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t align, 50drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t align)
51 dma_addr_t maxaddr)
52{ 51{
53 drm_dma_handle_t *dmah; 52 drm_dma_handle_t *dmah;
54#if 1 53#if 1
@@ -63,11 +62,6 @@ drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t ali
63 if (align > size) 62 if (align > size)
64 return NULL; 63 return NULL;
65 64
66 if (pci_set_dma_mask(dev->pdev, maxaddr) != 0) {
67 DRM_ERROR("Setting pci dma mask failed\n");
68 return NULL;
69 }
70
71 dmah = kmalloc(sizeof(drm_dma_handle_t), GFP_KERNEL); 65 dmah = kmalloc(sizeof(drm_dma_handle_t), GFP_KERNEL);
72 if (!dmah) 66 if (!dmah)
73 return NULL; 67 return NULL;
diff --git a/drivers/gpu/drm/i2c/ch7006_drv.c b/drivers/gpu/drm/i2c/ch7006_drv.c
index 9422a74c8b54..81681a07a806 100644
--- a/drivers/gpu/drm/i2c/ch7006_drv.c
+++ b/drivers/gpu/drm/i2c/ch7006_drv.c
@@ -408,6 +408,11 @@ static int ch7006_probe(struct i2c_client *client, const struct i2c_device_id *i
408 408
409 ch7006_info(client, "Detected version ID: %x\n", val); 409 ch7006_info(client, "Detected version ID: %x\n", val);
410 410
411 /* I don't know what this is for, but otherwise I get no
412 * signal.
413 */
414 ch7006_write(client, 0x3d, 0x0);
415
411 return 0; 416 return 0;
412 417
413fail: 418fail:
diff --git a/drivers/gpu/drm/i2c/ch7006_mode.c b/drivers/gpu/drm/i2c/ch7006_mode.c
index 87f5445092e8..e447dfb63890 100644
--- a/drivers/gpu/drm/i2c/ch7006_mode.c
+++ b/drivers/gpu/drm/i2c/ch7006_mode.c
@@ -427,11 +427,6 @@ void ch7006_state_load(struct i2c_client *client,
427 ch7006_load_reg(client, state, CH7006_SUBC_INC7); 427 ch7006_load_reg(client, state, CH7006_SUBC_INC7);
428 ch7006_load_reg(client, state, CH7006_PLL_CONTROL); 428 ch7006_load_reg(client, state, CH7006_PLL_CONTROL);
429 ch7006_load_reg(client, state, CH7006_CALC_SUBC_INC0); 429 ch7006_load_reg(client, state, CH7006_CALC_SUBC_INC0);
430
431 /* I don't know what this is for, but otherwise I get no
432 * signal.
433 */
434 ch7006_write(client, 0x3d, 0x0);
435} 430}
436 431
437void ch7006_state_save(struct i2c_client *client, 432void ch7006_state_save(struct i2c_client *client,
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 701bfeac7f57..02607ed61399 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -123,7 +123,7 @@ static int i915_init_phys_hws(struct drm_device *dev)
123 drm_i915_private_t *dev_priv = dev->dev_private; 123 drm_i915_private_t *dev_priv = dev->dev_private;
124 /* Program Hardware Status Page */ 124 /* Program Hardware Status Page */
125 dev_priv->status_page_dmah = 125 dev_priv->status_page_dmah =
126 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); 126 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
127 127
128 if (!dev_priv->status_page_dmah) { 128 if (!dev_priv->status_page_dmah) {
129 DRM_ERROR("Can not allocate hardware status page\n"); 129 DRM_ERROR("Can not allocate hardware status page\n");
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 917b8377ae28..c7f0cbec4e84 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4708,7 +4708,7 @@ int i915_gem_init_phys_object(struct drm_device *dev,
4708 4708
4709 phys_obj->id = id; 4709 phys_obj->id = id;
4710 4710
4711 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff); 4711 phys_obj->handle = drm_pci_alloc(dev, size, 0);
4712 if (!phys_obj->handle) { 4712 if (!phys_obj->handle) {
4713 ret = -ENOMEM; 4713 ret = -ENOMEM;
4714 goto kfree_obj; 4714 goto kfree_obj;
diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig
index b1bc1ea182b8..1175429da102 100644
--- a/drivers/gpu/drm/nouveau/Kconfig
+++ b/drivers/gpu/drm/nouveau/Kconfig
@@ -30,12 +30,11 @@ config DRM_NOUVEAU_DEBUG
30 via debugfs. 30 via debugfs.
31 31
32menu "I2C encoder or helper chips" 32menu "I2C encoder or helper chips"
33 depends on DRM && I2C 33 depends on DRM && DRM_KMS_HELPER && I2C
34 34
35config DRM_I2C_CH7006 35config DRM_I2C_CH7006
36 tristate "Chrontel ch7006 TV encoder" 36 tristate "Chrontel ch7006 TV encoder"
37 depends on DRM_NOUVEAU 37 default m if DRM_NOUVEAU
38 default m
39 help 38 help
40 Support for Chrontel ch7006 and similar TV encoders, found 39 Support for Chrontel ch7006 and similar TV encoders, found
41 on some nVidia video cards. 40 on some nVidia video cards.
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 1d90d4d0144f..48c290b5da8c 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -8,14 +8,15 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
8 nouveau_sgdma.o nouveau_dma.o \ 8 nouveau_sgdma.o nouveau_dma.o \
9 nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \ 9 nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \
10 nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \ 10 nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \
11 nouveau_display.o nouveau_connector.o nouveau_fbcon.o \ 11 nouveau_display.o nouveau_connector.o nouveau_fbcon.o \
12 nouveau_dp.o \ 12 nouveau_dp.o nouveau_grctx.o \
13 nv04_timer.o \ 13 nv04_timer.o \
14 nv04_mc.o nv40_mc.o nv50_mc.o \ 14 nv04_mc.o nv40_mc.o nv50_mc.o \
15 nv04_fb.o nv10_fb.o nv40_fb.o \ 15 nv04_fb.o nv10_fb.o nv40_fb.o \
16 nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o \ 16 nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o \
17 nv04_graph.o nv10_graph.o nv20_graph.o \ 17 nv04_graph.o nv10_graph.o nv20_graph.o \
18 nv40_graph.o nv50_graph.o \ 18 nv40_graph.o nv50_graph.o \
19 nv40_grctx.o \
19 nv04_instmem.o nv50_instmem.o \ 20 nv04_instmem.o nv50_instmem.o \
20 nv50_crtc.o nv50_dac.o nv50_sor.o \ 21 nv50_crtc.o nv50_dac.o nv50_sor.o \
21 nv50_cursor.o nv50_display.o nv50_fbcon.o \ 22 nv50_cursor.o nv50_display.o nv50_fbcon.o \
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 5eec5ed69489..d7f8d8b4a4b8 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -181,43 +181,42 @@ struct methods {
181 const char desc[8]; 181 const char desc[8];
182 void (*loadbios)(struct drm_device *, uint8_t *); 182 void (*loadbios)(struct drm_device *, uint8_t *);
183 const bool rw; 183 const bool rw;
184 int score;
185}; 184};
186 185
187static struct methods nv04_methods[] = { 186static struct methods nv04_methods[] = {
188 { "PROM", load_vbios_prom, false }, 187 { "PROM", load_vbios_prom, false },
189 { "PRAMIN", load_vbios_pramin, true }, 188 { "PRAMIN", load_vbios_pramin, true },
190 { "PCIROM", load_vbios_pci, true }, 189 { "PCIROM", load_vbios_pci, true },
191 { }
192}; 190};
193 191
194static struct methods nv50_methods[] = { 192static struct methods nv50_methods[] = {
195 { "PRAMIN", load_vbios_pramin, true }, 193 { "PRAMIN", load_vbios_pramin, true },
196 { "PROM", load_vbios_prom, false }, 194 { "PROM", load_vbios_prom, false },
197 { "PCIROM", load_vbios_pci, true }, 195 { "PCIROM", load_vbios_pci, true },
198 { }
199}; 196};
200 197
198#define METHODCNT 3
199
201static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) 200static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
202{ 201{
203 struct drm_nouveau_private *dev_priv = dev->dev_private; 202 struct drm_nouveau_private *dev_priv = dev->dev_private;
204 struct methods *methods, *method; 203 struct methods *methods;
204 int i;
205 int testscore = 3; 205 int testscore = 3;
206 int scores[METHODCNT];
206 207
207 if (nouveau_vbios) { 208 if (nouveau_vbios) {
208 method = nv04_methods; 209 methods = nv04_methods;
209 while (method->loadbios) { 210 for (i = 0; i < METHODCNT; i++)
210 if (!strcasecmp(nouveau_vbios, method->desc)) 211 if (!strcasecmp(nouveau_vbios, methods[i].desc))
211 break; 212 break;
212 method++;
213 }
214 213
215 if (method->loadbios) { 214 if (i < METHODCNT) {
216 NV_INFO(dev, "Attempting to use BIOS image from %s\n", 215 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
217 method->desc); 216 methods[i].desc);
218 217
219 method->loadbios(dev, data); 218 methods[i].loadbios(dev, data);
220 if (score_vbios(dev, data, method->rw)) 219 if (score_vbios(dev, data, methods[i].rw))
221 return true; 220 return true;
222 } 221 }
223 222
@@ -229,28 +228,24 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
229 else 228 else
230 methods = nv50_methods; 229 methods = nv50_methods;
231 230
232 method = methods; 231 for (i = 0; i < METHODCNT; i++) {
233 while (method->loadbios) {
234 NV_TRACE(dev, "Attempting to load BIOS image from %s\n", 232 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
235 method->desc); 233 methods[i].desc);
236 data[0] = data[1] = 0; /* avoid reuse of previous image */ 234 data[0] = data[1] = 0; /* avoid reuse of previous image */
237 method->loadbios(dev, data); 235 methods[i].loadbios(dev, data);
238 method->score = score_vbios(dev, data, method->rw); 236 scores[i] = score_vbios(dev, data, methods[i].rw);
239 if (method->score == testscore) 237 if (scores[i] == testscore)
240 return true; 238 return true;
241 method++;
242 } 239 }
243 240
244 while (--testscore > 0) { 241 while (--testscore > 0) {
245 method = methods; 242 for (i = 0; i < METHODCNT; i++) {
246 while (method->loadbios) { 243 if (scores[i] == testscore) {
247 if (method->score == testscore) {
248 NV_TRACE(dev, "Using BIOS image from %s\n", 244 NV_TRACE(dev, "Using BIOS image from %s\n",
249 method->desc); 245 methods[i].desc);
250 method->loadbios(dev, data); 246 methods[i].loadbios(dev, data);
251 return true; 247 return true;
252 } 248 }
253 method++;
254 } 249 }
255 } 250 }
256 251
@@ -261,10 +256,7 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
261struct init_tbl_entry { 256struct init_tbl_entry {
262 char *name; 257 char *name;
263 uint8_t id; 258 uint8_t id;
264 int length; 259 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
265 int length_offset;
266 int length_multiplier;
267 bool (*handler)(struct nvbios *, uint16_t, struct init_exec *);
268}; 260};
269 261
270struct bit_entry { 262struct bit_entry {
@@ -318,63 +310,22 @@ valid_reg(struct nvbios *bios, uint32_t reg)
318 struct drm_device *dev = bios->dev; 310 struct drm_device *dev = bios->dev;
319 311
320 /* C51 has misaligned regs on purpose. Marvellous */ 312 /* C51 has misaligned regs on purpose. Marvellous */
321 if (reg & 0x2 || (reg & 0x1 && dev_priv->VBIOS.pub.chip_version != 0x51)) { 313 if (reg & 0x2 ||
322 NV_ERROR(dev, "========== misaligned reg 0x%08X ==========\n", 314 (reg & 0x1 && dev_priv->VBIOS.pub.chip_version != 0x51))
323 reg); 315 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
324 return 0; 316
325 } 317 /* warn on C51 regs that haven't been verified accessible in tracing */
326 /*
327 * Warn on C51 regs that have not been verified accessible in
328 * mmiotracing
329 */
330 if (reg & 0x1 && dev_priv->VBIOS.pub.chip_version == 0x51 && 318 if (reg & 0x1 && dev_priv->VBIOS.pub.chip_version == 0x51 &&
331 reg != 0x130d && reg != 0x1311 && reg != 0x60081d) 319 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
332 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n", 320 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
333 reg); 321 reg);
334 322
335 /* Trust the init scripts on G80 */ 323 if (reg >= (8*1024*1024)) {
336 if (dev_priv->card_type >= NV_50) 324 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
337 return 1; 325 return 0;
338
339 #define WITHIN(x, y, z) ((x >= y) && (x < y + z))
340 if (WITHIN(reg, NV_PMC_OFFSET, NV_PMC_SIZE))
341 return 1;
342 if (WITHIN(reg, NV_PBUS_OFFSET, NV_PBUS_SIZE))
343 return 1;
344 if (WITHIN(reg, NV_PFIFO_OFFSET, NV_PFIFO_SIZE))
345 return 1;
346 if (dev_priv->VBIOS.pub.chip_version >= 0x30 &&
347 (WITHIN(reg, 0x4000, 0x600) || reg == 0x00004600))
348 return 1;
349 if (dev_priv->VBIOS.pub.chip_version >= 0x40 &&
350 WITHIN(reg, 0xc000, 0x48))
351 return 1;
352 if (dev_priv->VBIOS.pub.chip_version >= 0x17 && reg == 0x0000d204)
353 return 1;
354 if (dev_priv->VBIOS.pub.chip_version >= 0x40) {
355 if (reg == 0x00011014 || reg == 0x00020328)
356 return 1;
357 if (WITHIN(reg, 0x88000, NV_PBUS_SIZE)) /* new PBUS */
358 return 1;
359 } 326 }
360 if (WITHIN(reg, NV_PFB_OFFSET, NV_PFB_SIZE))
361 return 1;
362 if (WITHIN(reg, NV_PEXTDEV_OFFSET, NV_PEXTDEV_SIZE))
363 return 1;
364 if (WITHIN(reg, NV_PCRTC0_OFFSET, NV_PCRTC0_SIZE * 2))
365 return 1;
366 if (WITHIN(reg, NV_PRAMDAC0_OFFSET, NV_PRAMDAC0_SIZE * 2))
367 return 1;
368 if (dev_priv->VBIOS.pub.chip_version >= 0x17 && reg == 0x0070fff0)
369 return 1;
370 if (dev_priv->VBIOS.pub.chip_version == 0x51 &&
371 WITHIN(reg, NV_PRAMIN_OFFSET, NV_PRAMIN_SIZE))
372 return 1;
373 #undef WITHIN
374
375 NV_ERROR(dev, "========== unknown reg 0x%08X ==========\n", reg);
376 327
377 return 0; 328 return 1;
378} 329}
379 330
380static bool 331static bool
@@ -820,7 +771,7 @@ static uint32_t get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
820 } 771 }
821} 772}
822 773
823static bool 774static int
824init_io_restrict_prog(struct nvbios *bios, uint16_t offset, 775init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
825 struct init_exec *iexec) 776 struct init_exec *iexec)
826{ 777{
@@ -852,9 +803,10 @@ init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
852 uint32_t reg = ROM32(bios->data[offset + 7]); 803 uint32_t reg = ROM32(bios->data[offset + 7]);
853 uint8_t config; 804 uint8_t config;
854 uint32_t configval; 805 uint32_t configval;
806 int len = 11 + count * 4;
855 807
856 if (!iexec->execute) 808 if (!iexec->execute)
857 return true; 809 return len;
858 810
859 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 811 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
860 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 812 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
@@ -865,7 +817,7 @@ init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
865 NV_ERROR(bios->dev, 817 NV_ERROR(bios->dev,
866 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 818 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
867 offset, config, count); 819 offset, config, count);
868 return false; 820 return 0;
869 } 821 }
870 822
871 configval = ROM32(bios->data[offset + 11 + config * 4]); 823 configval = ROM32(bios->data[offset + 11 + config * 4]);
@@ -874,10 +826,10 @@ init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
874 826
875 bios_wr32(bios, reg, configval); 827 bios_wr32(bios, reg, configval);
876 828
877 return true; 829 return len;
878} 830}
879 831
880static bool 832static int
881init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 833init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
882{ 834{
883 /* 835 /*
@@ -912,10 +864,10 @@ init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
912 864
913 iexec->repeat = false; 865 iexec->repeat = false;
914 866
915 return true; 867 return 2;
916} 868}
917 869
918static bool 870static int
919init_io_restrict_pll(struct nvbios *bios, uint16_t offset, 871init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
920 struct init_exec *iexec) 872 struct init_exec *iexec)
921{ 873{
@@ -951,9 +903,10 @@ init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
951 uint32_t reg = ROM32(bios->data[offset + 8]); 903 uint32_t reg = ROM32(bios->data[offset + 8]);
952 uint8_t config; 904 uint8_t config;
953 uint16_t freq; 905 uint16_t freq;
906 int len = 12 + count * 2;
954 907
955 if (!iexec->execute) 908 if (!iexec->execute)
956 return true; 909 return len;
957 910
958 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 911 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
959 "Shift: 0x%02X, IO Flag Condition: 0x%02X, " 912 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
@@ -966,7 +919,7 @@ init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
966 NV_ERROR(bios->dev, 919 NV_ERROR(bios->dev,
967 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 920 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
968 offset, config, count); 921 offset, config, count);
969 return false; 922 return 0;
970 } 923 }
971 924
972 freq = ROM16(bios->data[offset + 12 + config * 2]); 925 freq = ROM16(bios->data[offset + 12 + config * 2]);
@@ -986,10 +939,10 @@ init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
986 939
987 setPLL(bios, reg, freq * 10); 940 setPLL(bios, reg, freq * 10);
988 941
989 return true; 942 return len;
990} 943}
991 944
992static bool 945static int
993init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 946init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
994{ 947{
995 /* 948 /*
@@ -1007,12 +960,12 @@ init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1007 * we're not in repeat mode 960 * we're not in repeat mode
1008 */ 961 */
1009 if (iexec->repeat) 962 if (iexec->repeat)
1010 return false; 963 return 0;
1011 964
1012 return true; 965 return 1;
1013} 966}
1014 967
1015static bool 968static int
1016init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 969init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1017{ 970{
1018 /* 971 /*
@@ -1041,7 +994,7 @@ init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1041 uint8_t crtcdata; 994 uint8_t crtcdata;
1042 995
1043 if (!iexec->execute) 996 if (!iexec->execute)
1044 return true; 997 return 11;
1045 998
1046 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, " 999 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1047 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n", 1000 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
@@ -1060,10 +1013,10 @@ init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1060 crtcdata |= (uint8_t)data; 1013 crtcdata |= (uint8_t)data;
1061 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata); 1014 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1062 1015
1063 return true; 1016 return 11;
1064} 1017}
1065 1018
1066static bool 1019static int
1067init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1020init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1068{ 1021{
1069 /* 1022 /*
@@ -1079,10 +1032,10 @@ init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1079 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset); 1032 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1080 1033
1081 iexec->execute = !iexec->execute; 1034 iexec->execute = !iexec->execute;
1082 return true; 1035 return 1;
1083} 1036}
1084 1037
1085static bool 1038static int
1086init_io_flag_condition(struct nvbios *bios, uint16_t offset, 1039init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1087 struct init_exec *iexec) 1040 struct init_exec *iexec)
1088{ 1041{
@@ -1100,7 +1053,7 @@ init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1100 uint8_t cond = bios->data[offset + 1]; 1053 uint8_t cond = bios->data[offset + 1];
1101 1054
1102 if (!iexec->execute) 1055 if (!iexec->execute)
1103 return true; 1056 return 2;
1104 1057
1105 if (io_flag_condition_met(bios, offset, cond)) 1058 if (io_flag_condition_met(bios, offset, cond))
1106 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 1059 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
@@ -1109,10 +1062,10 @@ init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1109 iexec->execute = false; 1062 iexec->execute = false;
1110 } 1063 }
1111 1064
1112 return true; 1065 return 2;
1113} 1066}
1114 1067
1115static bool 1068static int
1116init_idx_addr_latched(struct nvbios *bios, uint16_t offset, 1069init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1117 struct init_exec *iexec) 1070 struct init_exec *iexec)
1118{ 1071{
@@ -1140,11 +1093,12 @@ init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1140 uint32_t mask = ROM32(bios->data[offset + 9]); 1093 uint32_t mask = ROM32(bios->data[offset + 9]);
1141 uint32_t data = ROM32(bios->data[offset + 13]); 1094 uint32_t data = ROM32(bios->data[offset + 13]);
1142 uint8_t count = bios->data[offset + 17]; 1095 uint8_t count = bios->data[offset + 17];
1096 int len = 18 + count * 2;
1143 uint32_t value; 1097 uint32_t value;
1144 int i; 1098 int i;
1145 1099
1146 if (!iexec->execute) 1100 if (!iexec->execute)
1147 return true; 1101 return len;
1148 1102
1149 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, " 1103 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1150 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n", 1104 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
@@ -1164,10 +1118,10 @@ init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1164 bios_wr32(bios, controlreg, value); 1118 bios_wr32(bios, controlreg, value);
1165 } 1119 }
1166 1120
1167 return true; 1121 return len;
1168} 1122}
1169 1123
1170static bool 1124static int
1171init_io_restrict_pll2(struct nvbios *bios, uint16_t offset, 1125init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1172 struct init_exec *iexec) 1126 struct init_exec *iexec)
1173{ 1127{
@@ -1196,25 +1150,26 @@ init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1196 uint8_t shift = bios->data[offset + 5]; 1150 uint8_t shift = bios->data[offset + 5];
1197 uint8_t count = bios->data[offset + 6]; 1151 uint8_t count = bios->data[offset + 6];
1198 uint32_t reg = ROM32(bios->data[offset + 7]); 1152 uint32_t reg = ROM32(bios->data[offset + 7]);
1153 int len = 11 + count * 4;
1199 uint8_t config; 1154 uint8_t config;
1200 uint32_t freq; 1155 uint32_t freq;
1201 1156
1202 if (!iexec->execute) 1157 if (!iexec->execute)
1203 return true; 1158 return len;
1204 1159
1205 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1160 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1206 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 1161 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1207 offset, crtcport, crtcindex, mask, shift, count, reg); 1162 offset, crtcport, crtcindex, mask, shift, count, reg);
1208 1163
1209 if (!reg) 1164 if (!reg)
1210 return true; 1165 return len;
1211 1166
1212 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1167 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1213 if (config > count) { 1168 if (config > count) {
1214 NV_ERROR(bios->dev, 1169 NV_ERROR(bios->dev,
1215 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1170 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1216 offset, config, count); 1171 offset, config, count);
1217 return false; 1172 return 0;
1218 } 1173 }
1219 1174
1220 freq = ROM32(bios->data[offset + 11 + config * 4]); 1175 freq = ROM32(bios->data[offset + 11 + config * 4]);
@@ -1224,10 +1179,10 @@ init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1224 1179
1225 setPLL(bios, reg, freq); 1180 setPLL(bios, reg, freq);
1226 1181
1227 return true; 1182 return len;
1228} 1183}
1229 1184
1230static bool 1185static int
1231init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1186init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1232{ 1187{
1233 /* 1188 /*
@@ -1244,16 +1199,16 @@ init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1244 uint32_t freq = ROM32(bios->data[offset + 5]); 1199 uint32_t freq = ROM32(bios->data[offset + 5]);
1245 1200
1246 if (!iexec->execute) 1201 if (!iexec->execute)
1247 return true; 1202 return 9;
1248 1203
1249 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n", 1204 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1250 offset, reg, freq); 1205 offset, reg, freq);
1251 1206
1252 setPLL(bios, reg, freq); 1207 setPLL(bios, reg, freq);
1253 return true; 1208 return 9;
1254} 1209}
1255 1210
1256static bool 1211static int
1257init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1212init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1258{ 1213{
1259 /* 1214 /*
@@ -1277,12 +1232,13 @@ init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1277 uint8_t i2c_index = bios->data[offset + 1]; 1232 uint8_t i2c_index = bios->data[offset + 1];
1278 uint8_t i2c_address = bios->data[offset + 2]; 1233 uint8_t i2c_address = bios->data[offset + 2];
1279 uint8_t count = bios->data[offset + 3]; 1234 uint8_t count = bios->data[offset + 3];
1235 int len = 4 + count * 3;
1280 struct nouveau_i2c_chan *chan; 1236 struct nouveau_i2c_chan *chan;
1281 struct i2c_msg msg; 1237 struct i2c_msg msg;
1282 int i; 1238 int i;
1283 1239
1284 if (!iexec->execute) 1240 if (!iexec->execute)
1285 return true; 1241 return len;
1286 1242
1287 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1243 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1288 "Count: 0x%02X\n", 1244 "Count: 0x%02X\n",
@@ -1290,7 +1246,7 @@ init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1290 1246
1291 chan = init_i2c_device_find(bios->dev, i2c_index); 1247 chan = init_i2c_device_find(bios->dev, i2c_index);
1292 if (!chan) 1248 if (!chan)
1293 return false; 1249 return 0;
1294 1250
1295 for (i = 0; i < count; i++) { 1251 for (i = 0; i < count; i++) {
1296 uint8_t i2c_reg = bios->data[offset + 4 + i * 3]; 1252 uint8_t i2c_reg = bios->data[offset + 4 + i * 3];
@@ -1303,7 +1259,7 @@ init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1303 msg.len = 1; 1259 msg.len = 1;
1304 msg.buf = &value; 1260 msg.buf = &value;
1305 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1261 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
1306 return false; 1262 return 0;
1307 1263
1308 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 1264 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1309 "Mask: 0x%02X, Data: 0x%02X\n", 1265 "Mask: 0x%02X, Data: 0x%02X\n",
@@ -1317,14 +1273,14 @@ init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1317 msg.len = 1; 1273 msg.len = 1;
1318 msg.buf = &value; 1274 msg.buf = &value;
1319 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1275 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
1320 return false; 1276 return 0;
1321 } 1277 }
1322 } 1278 }
1323 1279
1324 return true; 1280 return len;
1325} 1281}
1326 1282
1327static bool 1283static int
1328init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1284init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1329{ 1285{
1330 /* 1286 /*
@@ -1346,12 +1302,13 @@ init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1346 uint8_t i2c_index = bios->data[offset + 1]; 1302 uint8_t i2c_index = bios->data[offset + 1];
1347 uint8_t i2c_address = bios->data[offset + 2]; 1303 uint8_t i2c_address = bios->data[offset + 2];
1348 uint8_t count = bios->data[offset + 3]; 1304 uint8_t count = bios->data[offset + 3];
1305 int len = 4 + count * 2;
1349 struct nouveau_i2c_chan *chan; 1306 struct nouveau_i2c_chan *chan;
1350 struct i2c_msg msg; 1307 struct i2c_msg msg;
1351 int i; 1308 int i;
1352 1309
1353 if (!iexec->execute) 1310 if (!iexec->execute)
1354 return true; 1311 return len;
1355 1312
1356 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1313 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1357 "Count: 0x%02X\n", 1314 "Count: 0x%02X\n",
@@ -1359,7 +1316,7 @@ init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1359 1316
1360 chan = init_i2c_device_find(bios->dev, i2c_index); 1317 chan = init_i2c_device_find(bios->dev, i2c_index);
1361 if (!chan) 1318 if (!chan)
1362 return false; 1319 return 0;
1363 1320
1364 for (i = 0; i < count; i++) { 1321 for (i = 0; i < count; i++) {
1365 uint8_t i2c_reg = bios->data[offset + 4 + i * 2]; 1322 uint8_t i2c_reg = bios->data[offset + 4 + i * 2];
@@ -1374,14 +1331,14 @@ init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1374 msg.len = 1; 1331 msg.len = 1;
1375 msg.buf = &data; 1332 msg.buf = &data;
1376 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1333 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
1377 return false; 1334 return 0;
1378 } 1335 }
1379 } 1336 }
1380 1337
1381 return true; 1338 return len;
1382} 1339}
1383 1340
1384static bool 1341static int
1385init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1342init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1386{ 1343{
1387 /* 1344 /*
@@ -1401,13 +1358,14 @@ init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1401 uint8_t i2c_index = bios->data[offset + 1]; 1358 uint8_t i2c_index = bios->data[offset + 1];
1402 uint8_t i2c_address = bios->data[offset + 2]; 1359 uint8_t i2c_address = bios->data[offset + 2];
1403 uint8_t count = bios->data[offset + 3]; 1360 uint8_t count = bios->data[offset + 3];
1361 int len = 4 + count;
1404 struct nouveau_i2c_chan *chan; 1362 struct nouveau_i2c_chan *chan;
1405 struct i2c_msg msg; 1363 struct i2c_msg msg;
1406 uint8_t data[256]; 1364 uint8_t data[256];
1407 int i; 1365 int i;
1408 1366
1409 if (!iexec->execute) 1367 if (!iexec->execute)
1410 return true; 1368 return len;
1411 1369
1412 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1370 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1413 "Count: 0x%02X\n", 1371 "Count: 0x%02X\n",
@@ -1415,7 +1373,7 @@ init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1415 1373
1416 chan = init_i2c_device_find(bios->dev, i2c_index); 1374 chan = init_i2c_device_find(bios->dev, i2c_index);
1417 if (!chan) 1375 if (!chan)
1418 return false; 1376 return 0;
1419 1377
1420 for (i = 0; i < count; i++) { 1378 for (i = 0; i < count; i++) {
1421 data[i] = bios->data[offset + 4 + i]; 1379 data[i] = bios->data[offset + 4 + i];
@@ -1429,13 +1387,13 @@ init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1429 msg.len = count; 1387 msg.len = count;
1430 msg.buf = data; 1388 msg.buf = data;
1431 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1389 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
1432 return false; 1390 return 0;
1433 } 1391 }
1434 1392
1435 return true; 1393 return len;
1436} 1394}
1437 1395
1438static bool 1396static int
1439init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1397init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1440{ 1398{
1441 /* 1399 /*
@@ -1460,7 +1418,7 @@ init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1460 uint32_t reg, value; 1418 uint32_t reg, value;
1461 1419
1462 if (!iexec->execute) 1420 if (!iexec->execute)
1463 return true; 1421 return 5;
1464 1422
1465 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, " 1423 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1466 "Mask: 0x%02X, Data: 0x%02X\n", 1424 "Mask: 0x%02X, Data: 0x%02X\n",
@@ -1468,7 +1426,7 @@ init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1468 1426
1469 reg = get_tmds_index_reg(bios->dev, mlv); 1427 reg = get_tmds_index_reg(bios->dev, mlv);
1470 if (!reg) 1428 if (!reg)
1471 return false; 1429 return 0;
1472 1430
1473 bios_wr32(bios, reg, 1431 bios_wr32(bios, reg,
1474 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE); 1432 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
@@ -1476,10 +1434,10 @@ init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1476 bios_wr32(bios, reg + 4, value); 1434 bios_wr32(bios, reg + 4, value);
1477 bios_wr32(bios, reg, tmdsaddr); 1435 bios_wr32(bios, reg, tmdsaddr);
1478 1436
1479 return true; 1437 return 5;
1480} 1438}
1481 1439
1482static bool 1440static int
1483init_zm_tmds_group(struct nvbios *bios, uint16_t offset, 1441init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1484 struct init_exec *iexec) 1442 struct init_exec *iexec)
1485{ 1443{
@@ -1500,18 +1458,19 @@ init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1500 1458
1501 uint8_t mlv = bios->data[offset + 1]; 1459 uint8_t mlv = bios->data[offset + 1];
1502 uint8_t count = bios->data[offset + 2]; 1460 uint8_t count = bios->data[offset + 2];
1461 int len = 3 + count * 2;
1503 uint32_t reg; 1462 uint32_t reg;
1504 int i; 1463 int i;
1505 1464
1506 if (!iexec->execute) 1465 if (!iexec->execute)
1507 return true; 1466 return len;
1508 1467
1509 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n", 1468 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1510 offset, mlv, count); 1469 offset, mlv, count);
1511 1470
1512 reg = get_tmds_index_reg(bios->dev, mlv); 1471 reg = get_tmds_index_reg(bios->dev, mlv);
1513 if (!reg) 1472 if (!reg)
1514 return false; 1473 return 0;
1515 1474
1516 for (i = 0; i < count; i++) { 1475 for (i = 0; i < count; i++) {
1517 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2]; 1476 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
@@ -1521,10 +1480,10 @@ init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1521 bios_wr32(bios, reg, tmdsaddr); 1480 bios_wr32(bios, reg, tmdsaddr);
1522 } 1481 }
1523 1482
1524 return true; 1483 return len;
1525} 1484}
1526 1485
1527static bool 1486static int
1528init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset, 1487init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1529 struct init_exec *iexec) 1488 struct init_exec *iexec)
1530{ 1489{
@@ -1547,11 +1506,12 @@ init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1547 uint8_t crtcindex2 = bios->data[offset + 2]; 1506 uint8_t crtcindex2 = bios->data[offset + 2];
1548 uint8_t baseaddr = bios->data[offset + 3]; 1507 uint8_t baseaddr = bios->data[offset + 3];
1549 uint8_t count = bios->data[offset + 4]; 1508 uint8_t count = bios->data[offset + 4];
1509 int len = 5 + count;
1550 uint8_t oldaddr, data; 1510 uint8_t oldaddr, data;
1551 int i; 1511 int i;
1552 1512
1553 if (!iexec->execute) 1513 if (!iexec->execute)
1554 return true; 1514 return len;
1555 1515
1556 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, " 1516 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1557 "BaseAddr: 0x%02X, Count: 0x%02X\n", 1517 "BaseAddr: 0x%02X, Count: 0x%02X\n",
@@ -1568,10 +1528,10 @@ init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1568 1528
1569 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr); 1529 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1570 1530
1571 return true; 1531 return len;
1572} 1532}
1573 1533
1574static bool 1534static int
1575init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1535init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1576{ 1536{
1577 /* 1537 /*
@@ -1592,7 +1552,7 @@ init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1592 uint8_t value; 1552 uint8_t value;
1593 1553
1594 if (!iexec->execute) 1554 if (!iexec->execute)
1595 return true; 1555 return 4;
1596 1556
1597 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n", 1557 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1598 offset, crtcindex, mask, data); 1558 offset, crtcindex, mask, data);
@@ -1601,10 +1561,10 @@ init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1601 value |= data; 1561 value |= data;
1602 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value); 1562 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1603 1563
1604 return true; 1564 return 4;
1605} 1565}
1606 1566
1607static bool 1567static int
1608init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1568init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1609{ 1569{
1610 /* 1570 /*
@@ -1621,14 +1581,14 @@ init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1621 uint8_t data = bios->data[offset + 2]; 1581 uint8_t data = bios->data[offset + 2];
1622 1582
1623 if (!iexec->execute) 1583 if (!iexec->execute)
1624 return true; 1584 return 3;
1625 1585
1626 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data); 1586 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1627 1587
1628 return true; 1588 return 3;
1629} 1589}
1630 1590
1631static bool 1591static int
1632init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1592init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1633{ 1593{
1634 /* 1594 /*
@@ -1645,18 +1605,19 @@ init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1645 */ 1605 */
1646 1606
1647 uint8_t count = bios->data[offset + 1]; 1607 uint8_t count = bios->data[offset + 1];
1608 int len = 2 + count * 2;
1648 int i; 1609 int i;
1649 1610
1650 if (!iexec->execute) 1611 if (!iexec->execute)
1651 return true; 1612 return len;
1652 1613
1653 for (i = 0; i < count; i++) 1614 for (i = 0; i < count; i++)
1654 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec); 1615 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1655 1616
1656 return true; 1617 return len;
1657} 1618}
1658 1619
1659static bool 1620static int
1660init_condition_time(struct nvbios *bios, uint16_t offset, 1621init_condition_time(struct nvbios *bios, uint16_t offset,
1661 struct init_exec *iexec) 1622 struct init_exec *iexec)
1662{ 1623{
@@ -1680,7 +1641,7 @@ init_condition_time(struct nvbios *bios, uint16_t offset,
1680 unsigned cnt; 1641 unsigned cnt;
1681 1642
1682 if (!iexec->execute) 1643 if (!iexec->execute)
1683 return true; 1644 return 3;
1684 1645
1685 if (retries > 100) 1646 if (retries > 100)
1686 retries = 100; 1647 retries = 100;
@@ -1711,10 +1672,10 @@ init_condition_time(struct nvbios *bios, uint16_t offset,
1711 iexec->execute = false; 1672 iexec->execute = false;
1712 } 1673 }
1713 1674
1714 return true; 1675 return 3;
1715} 1676}
1716 1677
1717static bool 1678static int
1718init_zm_reg_sequence(struct nvbios *bios, uint16_t offset, 1679init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1719 struct init_exec *iexec) 1680 struct init_exec *iexec)
1720{ 1681{
@@ -1734,10 +1695,11 @@ init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1734 1695
1735 uint32_t basereg = ROM32(bios->data[offset + 1]); 1696 uint32_t basereg = ROM32(bios->data[offset + 1]);
1736 uint32_t count = bios->data[offset + 5]; 1697 uint32_t count = bios->data[offset + 5];
1698 int len = 6 + count * 4;
1737 int i; 1699 int i;
1738 1700
1739 if (!iexec->execute) 1701 if (!iexec->execute)
1740 return true; 1702 return len;
1741 1703
1742 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n", 1704 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1743 offset, basereg, count); 1705 offset, basereg, count);
@@ -1749,10 +1711,10 @@ init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1749 bios_wr32(bios, reg, data); 1711 bios_wr32(bios, reg, data);
1750 } 1712 }
1751 1713
1752 return true; 1714 return len;
1753} 1715}
1754 1716
1755static bool 1717static int
1756init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1718init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1757{ 1719{
1758 /* 1720 /*
@@ -1768,7 +1730,7 @@ init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1768 uint16_t sub_offset = ROM16(bios->data[offset + 1]); 1730 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1769 1731
1770 if (!iexec->execute) 1732 if (!iexec->execute)
1771 return true; 1733 return 3;
1772 1734
1773 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n", 1735 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1774 offset, sub_offset); 1736 offset, sub_offset);
@@ -1777,10 +1739,10 @@ init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1777 1739
1778 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset); 1740 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1779 1741
1780 return true; 1742 return 3;
1781} 1743}
1782 1744
1783static bool 1745static int
1784init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1746init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1785{ 1747{
1786 /* 1748 /*
@@ -1808,7 +1770,7 @@ init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1808 uint32_t srcvalue, dstvalue; 1770 uint32_t srcvalue, dstvalue;
1809 1771
1810 if (!iexec->execute) 1772 if (!iexec->execute)
1811 return true; 1773 return 22;
1812 1774
1813 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, " 1775 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
1814 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n", 1776 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
@@ -1827,10 +1789,10 @@ init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1827 1789
1828 bios_wr32(bios, dstreg, dstvalue | srcvalue); 1790 bios_wr32(bios, dstreg, dstvalue | srcvalue);
1829 1791
1830 return true; 1792 return 22;
1831} 1793}
1832 1794
1833static bool 1795static int
1834init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1796init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1835{ 1797{
1836 /* 1798 /*
@@ -1848,14 +1810,14 @@ init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1848 uint8_t data = bios->data[offset + 4]; 1810 uint8_t data = bios->data[offset + 4];
1849 1811
1850 if (!iexec->execute) 1812 if (!iexec->execute)
1851 return true; 1813 return 5;
1852 1814
1853 bios_idxprt_wr(bios, crtcport, crtcindex, data); 1815 bios_idxprt_wr(bios, crtcport, crtcindex, data);
1854 1816
1855 return true; 1817 return 5;
1856} 1818}
1857 1819
1858static bool 1820static int
1859init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1821init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1860{ 1822{
1861 /* 1823 /*
@@ -1904,7 +1866,7 @@ init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1904 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 1866 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
1905 1867
1906 if (dev_priv->card_type >= NV_50) 1868 if (dev_priv->card_type >= NV_50)
1907 return true; 1869 return 1;
1908 1870
1909 /* 1871 /*
1910 * On every card I've seen, this step gets done for us earlier in 1872 * On every card I've seen, this step gets done for us earlier in
@@ -1922,10 +1884,10 @@ init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1922 /* write back the saved configuration value */ 1884 /* write back the saved configuration value */
1923 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0); 1885 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0);
1924 1886
1925 return true; 1887 return 1;
1926} 1888}
1927 1889
1928static bool 1890static int
1929init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1891init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1930{ 1892{
1931 /* 1893 /*
@@ -1959,10 +1921,10 @@ init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1959 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */ 1921 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
1960 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20); 1922 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
1961 1923
1962 return true; 1924 return 13;
1963} 1925}
1964 1926
1965static bool 1927static int
1966init_configure_mem(struct nvbios *bios, uint16_t offset, 1928init_configure_mem(struct nvbios *bios, uint16_t offset,
1967 struct init_exec *iexec) 1929 struct init_exec *iexec)
1968{ 1930{
@@ -1983,7 +1945,7 @@ init_configure_mem(struct nvbios *bios, uint16_t offset,
1983 uint32_t reg, data; 1945 uint32_t reg, data;
1984 1946
1985 if (bios->major_version > 2) 1947 if (bios->major_version > 2)
1986 return false; 1948 return 0;
1987 1949
1988 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd( 1950 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
1989 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20); 1951 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
@@ -2015,10 +1977,10 @@ init_configure_mem(struct nvbios *bios, uint16_t offset,
2015 bios_wr32(bios, reg, data); 1977 bios_wr32(bios, reg, data);
2016 } 1978 }
2017 1979
2018 return true; 1980 return 1;
2019} 1981}
2020 1982
2021static bool 1983static int
2022init_configure_clk(struct nvbios *bios, uint16_t offset, 1984init_configure_clk(struct nvbios *bios, uint16_t offset,
2023 struct init_exec *iexec) 1985 struct init_exec *iexec)
2024{ 1986{
@@ -2038,7 +2000,7 @@ init_configure_clk(struct nvbios *bios, uint16_t offset,
2038 int clock; 2000 int clock;
2039 2001
2040 if (bios->major_version > 2) 2002 if (bios->major_version > 2)
2041 return false; 2003 return 0;
2042 2004
2043 clock = ROM16(bios->data[meminitoffs + 4]) * 10; 2005 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2044 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock); 2006 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
@@ -2048,10 +2010,10 @@ init_configure_clk(struct nvbios *bios, uint16_t offset,
2048 clock *= 2; 2010 clock *= 2;
2049 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock); 2011 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2050 2012
2051 return true; 2013 return 1;
2052} 2014}
2053 2015
2054static bool 2016static int
2055init_configure_preinit(struct nvbios *bios, uint16_t offset, 2017init_configure_preinit(struct nvbios *bios, uint16_t offset,
2056 struct init_exec *iexec) 2018 struct init_exec *iexec)
2057{ 2019{
@@ -2071,15 +2033,15 @@ init_configure_preinit(struct nvbios *bios, uint16_t offset,
2071 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6)); 2033 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
2072 2034
2073 if (bios->major_version > 2) 2035 if (bios->major_version > 2)
2074 return false; 2036 return 0;
2075 2037
2076 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, 2038 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2077 NV_CIO_CRE_SCRATCH4__INDEX, cr3c); 2039 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2078 2040
2079 return true; 2041 return 1;
2080} 2042}
2081 2043
2082static bool 2044static int
2083init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2045init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2084{ 2046{
2085 /* 2047 /*
@@ -2099,7 +2061,7 @@ init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2099 uint8_t data = bios->data[offset + 4]; 2061 uint8_t data = bios->data[offset + 4];
2100 2062
2101 if (!iexec->execute) 2063 if (!iexec->execute)
2102 return true; 2064 return 5;
2103 2065
2104 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n", 2066 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2105 offset, crtcport, mask, data); 2067 offset, crtcport, mask, data);
@@ -2158,15 +2120,15 @@ init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2158 for (i = 0; i < 2; i++) 2120 for (i = 0; i < 2; i++)
2159 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32( 2121 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2160 bios, 0x614108 + (i*0x800)) & 0x0fffffff); 2122 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
2161 return true; 2123 return 5;
2162 } 2124 }
2163 2125
2164 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) | 2126 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2165 data); 2127 data);
2166 return true; 2128 return 5;
2167} 2129}
2168 2130
2169static bool 2131static int
2170init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2132init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2171{ 2133{
2172 /* 2134 /*
@@ -2181,7 +2143,7 @@ init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2181 uint8_t sub = bios->data[offset + 1]; 2143 uint8_t sub = bios->data[offset + 1];
2182 2144
2183 if (!iexec->execute) 2145 if (!iexec->execute)
2184 return true; 2146 return 2;
2185 2147
2186 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub); 2148 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2187 2149
@@ -2191,10 +2153,10 @@ init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2191 2153
2192 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub); 2154 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2193 2155
2194 return true; 2156 return 2;
2195} 2157}
2196 2158
2197static bool 2159static int
2198init_ram_condition(struct nvbios *bios, uint16_t offset, 2160init_ram_condition(struct nvbios *bios, uint16_t offset,
2199 struct init_exec *iexec) 2161 struct init_exec *iexec)
2200{ 2162{
@@ -2215,7 +2177,7 @@ init_ram_condition(struct nvbios *bios, uint16_t offset,
2215 uint8_t data; 2177 uint8_t data;
2216 2178
2217 if (!iexec->execute) 2179 if (!iexec->execute)
2218 return true; 2180 return 3;
2219 2181
2220 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask; 2182 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask;
2221 2183
@@ -2229,10 +2191,10 @@ init_ram_condition(struct nvbios *bios, uint16_t offset,
2229 iexec->execute = false; 2191 iexec->execute = false;
2230 } 2192 }
2231 2193
2232 return true; 2194 return 3;
2233} 2195}
2234 2196
2235static bool 2197static int
2236init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2198init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2237{ 2199{
2238 /* 2200 /*
@@ -2251,17 +2213,17 @@ init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2251 uint32_t data = ROM32(bios->data[offset + 9]); 2213 uint32_t data = ROM32(bios->data[offset + 9]);
2252 2214
2253 if (!iexec->execute) 2215 if (!iexec->execute)
2254 return true; 2216 return 13;
2255 2217
2256 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n", 2218 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2257 offset, reg, mask, data); 2219 offset, reg, mask, data);
2258 2220
2259 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data); 2221 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2260 2222
2261 return true; 2223 return 13;
2262} 2224}
2263 2225
2264static bool 2226static int
2265init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2227init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2266{ 2228{
2267 /* 2229 /*
@@ -2285,7 +2247,7 @@ init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2285 int i; 2247 int i;
2286 2248
2287 if (!iexec->execute) 2249 if (!iexec->execute)
2288 return true; 2250 return 2;
2289 2251
2290 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, " 2252 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2291 "Count: 0x%02X\n", 2253 "Count: 0x%02X\n",
@@ -2300,10 +2262,10 @@ init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2300 bios_wr32(bios, reg, data); 2262 bios_wr32(bios, reg, data);
2301 } 2263 }
2302 2264
2303 return true; 2265 return 2;
2304} 2266}
2305 2267
2306static bool 2268static int
2307init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2269init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2308{ 2270{
2309 /* 2271 /*
@@ -2315,10 +2277,10 @@ init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2315 */ 2277 */
2316 2278
2317 /* mild retval abuse to stop parsing this table */ 2279 /* mild retval abuse to stop parsing this table */
2318 return false; 2280 return 0;
2319} 2281}
2320 2282
2321static bool 2283static int
2322init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2284init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2323{ 2285{
2324 /* 2286 /*
@@ -2330,15 +2292,15 @@ init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2330 */ 2292 */
2331 2293
2332 if (iexec->execute) 2294 if (iexec->execute)
2333 return true; 2295 return 1;
2334 2296
2335 iexec->execute = true; 2297 iexec->execute = true;
2336 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset); 2298 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2337 2299
2338 return true; 2300 return 1;
2339} 2301}
2340 2302
2341static bool 2303static int
2342init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2304init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2343{ 2305{
2344 /* 2306 /*
@@ -2353,7 +2315,7 @@ init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2353 unsigned time = ROM16(bios->data[offset + 1]); 2315 unsigned time = ROM16(bios->data[offset + 1]);
2354 2316
2355 if (!iexec->execute) 2317 if (!iexec->execute)
2356 return true; 2318 return 3;
2357 2319
2358 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n", 2320 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2359 offset, time); 2321 offset, time);
@@ -2363,10 +2325,10 @@ init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2363 else 2325 else
2364 msleep((time + 900) / 1000); 2326 msleep((time + 900) / 1000);
2365 2327
2366 return true; 2328 return 3;
2367} 2329}
2368 2330
2369static bool 2331static int
2370init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2332init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2371{ 2333{
2372 /* 2334 /*
@@ -2383,7 +2345,7 @@ init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2383 uint8_t cond = bios->data[offset + 1]; 2345 uint8_t cond = bios->data[offset + 1];
2384 2346
2385 if (!iexec->execute) 2347 if (!iexec->execute)
2386 return true; 2348 return 2;
2387 2349
2388 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond); 2350 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2389 2351
@@ -2394,10 +2356,10 @@ init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2394 iexec->execute = false; 2356 iexec->execute = false;
2395 } 2357 }
2396 2358
2397 return true; 2359 return 2;
2398} 2360}
2399 2361
2400static bool 2362static int
2401init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2363init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2402{ 2364{
2403 /* 2365 /*
@@ -2414,7 +2376,7 @@ init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2414 uint8_t cond = bios->data[offset + 1]; 2376 uint8_t cond = bios->data[offset + 1];
2415 2377
2416 if (!iexec->execute) 2378 if (!iexec->execute)
2417 return true; 2379 return 2;
2418 2380
2419 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond); 2381 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2420 2382
@@ -2425,10 +2387,10 @@ init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2425 iexec->execute = false; 2387 iexec->execute = false;
2426 } 2388 }
2427 2389
2428 return true; 2390 return 2;
2429} 2391}
2430 2392
2431static bool 2393static int
2432init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2394init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2433{ 2395{
2434 /* 2396 /*
@@ -2451,7 +2413,7 @@ init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2451 uint8_t value; 2413 uint8_t value;
2452 2414
2453 if (!iexec->execute) 2415 if (!iexec->execute)
2454 return true; 2416 return 6;
2455 2417
2456 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 2418 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2457 "Data: 0x%02X\n", 2419 "Data: 0x%02X\n",
@@ -2460,10 +2422,10 @@ init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2460 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data; 2422 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2461 bios_idxprt_wr(bios, crtcport, crtcindex, value); 2423 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2462 2424
2463 return true; 2425 return 6;
2464} 2426}
2465 2427
2466static bool 2428static int
2467init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2429init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2468{ 2430{
2469 /* 2431 /*
@@ -2481,16 +2443,16 @@ init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2481 uint16_t freq = ROM16(bios->data[offset + 5]); 2443 uint16_t freq = ROM16(bios->data[offset + 5]);
2482 2444
2483 if (!iexec->execute) 2445 if (!iexec->execute)
2484 return true; 2446 return 7;
2485 2447
2486 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq); 2448 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
2487 2449
2488 setPLL(bios, reg, freq * 10); 2450 setPLL(bios, reg, freq * 10);
2489 2451
2490 return true; 2452 return 7;
2491} 2453}
2492 2454
2493static bool 2455static int
2494init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2456init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2495{ 2457{
2496 /* 2458 /*
@@ -2507,17 +2469,17 @@ init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2507 uint32_t value = ROM32(bios->data[offset + 5]); 2469 uint32_t value = ROM32(bios->data[offset + 5]);
2508 2470
2509 if (!iexec->execute) 2471 if (!iexec->execute)
2510 return true; 2472 return 9;
2511 2473
2512 if (reg == 0x000200) 2474 if (reg == 0x000200)
2513 value |= 1; 2475 value |= 1;
2514 2476
2515 bios_wr32(bios, reg, value); 2477 bios_wr32(bios, reg, value);
2516 2478
2517 return true; 2479 return 9;
2518} 2480}
2519 2481
2520static bool 2482static int
2521init_ram_restrict_pll(struct nvbios *bios, uint16_t offset, 2483init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2522 struct init_exec *iexec) 2484 struct init_exec *iexec)
2523{ 2485{
@@ -2543,14 +2505,15 @@ init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2543 uint8_t type = bios->data[offset + 1]; 2505 uint8_t type = bios->data[offset + 1];
2544 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]); 2506 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
2545 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry; 2507 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
2508 int len = 2 + bios->ram_restrict_group_count * 4;
2546 int i; 2509 int i;
2547 2510
2548 if (!iexec->execute) 2511 if (!iexec->execute)
2549 return true; 2512 return len;
2550 2513
2551 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) { 2514 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
2552 NV_ERROR(dev, "PLL limits table not version 3.x\n"); 2515 NV_ERROR(dev, "PLL limits table not version 3.x\n");
2553 return true; /* deliberate, allow default clocks to remain */ 2516 return len; /* deliberate, allow default clocks to remain */
2554 } 2517 }
2555 2518
2556 entry = pll_limits + pll_limits[1]; 2519 entry = pll_limits + pll_limits[1];
@@ -2563,15 +2526,15 @@ init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2563 offset, type, reg, freq); 2526 offset, type, reg, freq);
2564 2527
2565 setPLL(bios, reg, freq); 2528 setPLL(bios, reg, freq);
2566 return true; 2529 return len;
2567 } 2530 }
2568 } 2531 }
2569 2532
2570 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type); 2533 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
2571 return true; 2534 return len;
2572} 2535}
2573 2536
2574static bool 2537static int
2575init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2538init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2576{ 2539{
2577 /* 2540 /*
@@ -2581,10 +2544,10 @@ init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2581 * 2544 *
2582 */ 2545 */
2583 2546
2584 return true; 2547 return 1;
2585} 2548}
2586 2549
2587static bool 2550static int
2588init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2551init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2589{ 2552{
2590 /* 2553 /*
@@ -2594,10 +2557,10 @@ init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2594 * 2557 *
2595 */ 2558 */
2596 2559
2597 return true; 2560 return 1;
2598} 2561}
2599 2562
2600static bool 2563static int
2601init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2564init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2602{ 2565{
2603 /* 2566 /*
@@ -2615,14 +2578,17 @@ init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2615 const uint8_t *gpio_entry; 2578 const uint8_t *gpio_entry;
2616 int i; 2579 int i;
2617 2580
2581 if (!iexec->execute)
2582 return 1;
2583
2618 if (bios->bdcb.version != 0x40) { 2584 if (bios->bdcb.version != 0x40) {
2619 NV_ERROR(bios->dev, "DCB table not version 4.0\n"); 2585 NV_ERROR(bios->dev, "DCB table not version 4.0\n");
2620 return false; 2586 return 0;
2621 } 2587 }
2622 2588
2623 if (!bios->bdcb.gpio_table_ptr) { 2589 if (!bios->bdcb.gpio_table_ptr) {
2624 NV_WARN(bios->dev, "Invalid pointer to INIT_8E table\n"); 2590 NV_WARN(bios->dev, "Invalid pointer to INIT_8E table\n");
2625 return false; 2591 return 0;
2626 } 2592 }
2627 2593
2628 gpio_entry = gpio_table + gpio_table[1]; 2594 gpio_entry = gpio_table + gpio_table[1];
@@ -2660,13 +2626,10 @@ init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2660 bios_wr32(bios, r, v); 2626 bios_wr32(bios, r, v);
2661 } 2627 }
2662 2628
2663 return true; 2629 return 1;
2664} 2630}
2665 2631
2666/* hack to avoid moving the itbl_entry array before this function */ 2632static int
2667int init_ram_restrict_zm_reg_group_blocklen;
2668
2669static bool
2670init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset, 2633init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2671 struct init_exec *iexec) 2634 struct init_exec *iexec)
2672{ 2635{
@@ -2692,21 +2655,21 @@ init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2692 uint8_t regincrement = bios->data[offset + 5]; 2655 uint8_t regincrement = bios->data[offset + 5];
2693 uint8_t count = bios->data[offset + 6]; 2656 uint8_t count = bios->data[offset + 6];
2694 uint32_t strap_ramcfg, data; 2657 uint32_t strap_ramcfg, data;
2695 uint16_t blocklen; 2658 /* previously set by 'M' BIT table */
2659 uint16_t blocklen = bios->ram_restrict_group_count * 4;
2660 int len = 7 + count * blocklen;
2696 uint8_t index; 2661 uint8_t index;
2697 int i; 2662 int i;
2698 2663
2699 /* previously set by 'M' BIT table */
2700 blocklen = init_ram_restrict_zm_reg_group_blocklen;
2701 2664
2702 if (!iexec->execute) 2665 if (!iexec->execute)
2703 return true; 2666 return len;
2704 2667
2705 if (!blocklen) { 2668 if (!blocklen) {
2706 NV_ERROR(bios->dev, 2669 NV_ERROR(bios->dev,
2707 "0x%04X: Zero block length - has the M table " 2670 "0x%04X: Zero block length - has the M table "
2708 "been parsed?\n", offset); 2671 "been parsed?\n", offset);
2709 return false; 2672 return 0;
2710 } 2673 }
2711 2674
2712 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf; 2675 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
@@ -2724,10 +2687,10 @@ init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2724 reg += regincrement; 2687 reg += regincrement;
2725 } 2688 }
2726 2689
2727 return true; 2690 return len;
2728} 2691}
2729 2692
2730static bool 2693static int
2731init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2694init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2732{ 2695{
2733 /* 2696 /*
@@ -2744,14 +2707,14 @@ init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2744 uint32_t dstreg = ROM32(bios->data[offset + 5]); 2707 uint32_t dstreg = ROM32(bios->data[offset + 5]);
2745 2708
2746 if (!iexec->execute) 2709 if (!iexec->execute)
2747 return true; 2710 return 9;
2748 2711
2749 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg)); 2712 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
2750 2713
2751 return true; 2714 return 9;
2752} 2715}
2753 2716
2754static bool 2717static int
2755init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset, 2718init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
2756 struct init_exec *iexec) 2719 struct init_exec *iexec)
2757{ 2720{
@@ -2769,20 +2732,21 @@ init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
2769 2732
2770 uint32_t reg = ROM32(bios->data[offset + 1]); 2733 uint32_t reg = ROM32(bios->data[offset + 1]);
2771 uint8_t count = bios->data[offset + 5]; 2734 uint8_t count = bios->data[offset + 5];
2735 int len = 6 + count * 4;
2772 int i; 2736 int i;
2773 2737
2774 if (!iexec->execute) 2738 if (!iexec->execute)
2775 return true; 2739 return len;
2776 2740
2777 for (i = 0; i < count; i++) { 2741 for (i = 0; i < count; i++) {
2778 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]); 2742 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
2779 bios_wr32(bios, reg, data); 2743 bios_wr32(bios, reg, data);
2780 } 2744 }
2781 2745
2782 return true; 2746 return len;
2783} 2747}
2784 2748
2785static bool 2749static int
2786init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2750init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2787{ 2751{
2788 /* 2752 /*
@@ -2793,10 +2757,10 @@ init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2793 * Seemingly does nothing 2757 * Seemingly does nothing
2794 */ 2758 */
2795 2759
2796 return true; 2760 return 1;
2797} 2761}
2798 2762
2799static bool 2763static int
2800init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2764init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2801{ 2765{
2802 /* 2766 /*
@@ -2829,13 +2793,13 @@ init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2829 val <<= bios->data[offset + 16]; 2793 val <<= bios->data[offset + 16];
2830 2794
2831 if (!iexec->execute) 2795 if (!iexec->execute)
2832 return true; 2796 return 17;
2833 2797
2834 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val); 2798 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
2835 return true; 2799 return 17;
2836} 2800}
2837 2801
2838static bool 2802static int
2839init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2803init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2840{ 2804{
2841 /* 2805 /*
@@ -2859,13 +2823,13 @@ init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2859 val = (val & mask) | ((val + add) & ~mask); 2823 val = (val & mask) | ((val + add) & ~mask);
2860 2824
2861 if (!iexec->execute) 2825 if (!iexec->execute)
2862 return true; 2826 return 13;
2863 2827
2864 bios_wr32(bios, reg, val); 2828 bios_wr32(bios, reg, val);
2865 return true; 2829 return 13;
2866} 2830}
2867 2831
2868static bool 2832static int
2869init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2833init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2870{ 2834{
2871 /* 2835 /*
@@ -2883,32 +2847,33 @@ init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2883 struct drm_device *dev = bios->dev; 2847 struct drm_device *dev = bios->dev;
2884 struct nouveau_i2c_chan *auxch; 2848 struct nouveau_i2c_chan *auxch;
2885 uint32_t addr = ROM32(bios->data[offset + 1]); 2849 uint32_t addr = ROM32(bios->data[offset + 1]);
2886 uint8_t len = bios->data[offset + 5]; 2850 uint8_t count = bios->data[offset + 5];
2851 int len = 6 + count * 2;
2887 int ret, i; 2852 int ret, i;
2888 2853
2889 if (!bios->display.output) { 2854 if (!bios->display.output) {
2890 NV_ERROR(dev, "INIT_AUXCH: no active output\n"); 2855 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
2891 return false; 2856 return 0;
2892 } 2857 }
2893 2858
2894 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 2859 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
2895 if (!auxch) { 2860 if (!auxch) {
2896 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n", 2861 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
2897 bios->display.output->i2c_index); 2862 bios->display.output->i2c_index);
2898 return false; 2863 return 0;
2899 } 2864 }
2900 2865
2901 if (!iexec->execute) 2866 if (!iexec->execute)
2902 return true; 2867 return len;
2903 2868
2904 offset += 6; 2869 offset += 6;
2905 for (i = 0; i < len; i++, offset += 2) { 2870 for (i = 0; i < count; i++, offset += 2) {
2906 uint8_t data; 2871 uint8_t data;
2907 2872
2908 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1); 2873 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
2909 if (ret) { 2874 if (ret) {
2910 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret); 2875 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
2911 return false; 2876 return 0;
2912 } 2877 }
2913 2878
2914 data &= bios->data[offset + 0]; 2879 data &= bios->data[offset + 0];
@@ -2917,14 +2882,14 @@ init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2917 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1); 2882 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
2918 if (ret) { 2883 if (ret) {
2919 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret); 2884 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
2920 return false; 2885 return 0;
2921 } 2886 }
2922 } 2887 }
2923 2888
2924 return true; 2889 return len;
2925} 2890}
2926 2891
2927static bool 2892static int
2928init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2893init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2929{ 2894{
2930 /* 2895 /*
@@ -2941,106 +2906,99 @@ init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2941 struct drm_device *dev = bios->dev; 2906 struct drm_device *dev = bios->dev;
2942 struct nouveau_i2c_chan *auxch; 2907 struct nouveau_i2c_chan *auxch;
2943 uint32_t addr = ROM32(bios->data[offset + 1]); 2908 uint32_t addr = ROM32(bios->data[offset + 1]);
2944 uint8_t len = bios->data[offset + 5]; 2909 uint8_t count = bios->data[offset + 5];
2910 int len = 6 + count;
2945 int ret, i; 2911 int ret, i;
2946 2912
2947 if (!bios->display.output) { 2913 if (!bios->display.output) {
2948 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n"); 2914 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
2949 return false; 2915 return 0;
2950 } 2916 }
2951 2917
2952 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 2918 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
2953 if (!auxch) { 2919 if (!auxch) {
2954 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n", 2920 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
2955 bios->display.output->i2c_index); 2921 bios->display.output->i2c_index);
2956 return false; 2922 return 0;
2957 } 2923 }
2958 2924
2959 if (!iexec->execute) 2925 if (!iexec->execute)
2960 return true; 2926 return len;
2961 2927
2962 offset += 6; 2928 offset += 6;
2963 for (i = 0; i < len; i++, offset++) { 2929 for (i = 0; i < count; i++, offset++) {
2964 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1); 2930 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
2965 if (ret) { 2931 if (ret) {
2966 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret); 2932 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
2967 return false; 2933 return 0;
2968 } 2934 }
2969 } 2935 }
2970 2936
2971 return true; 2937 return len;
2972} 2938}
2973 2939
2974static struct init_tbl_entry itbl_entry[] = { 2940static struct init_tbl_entry itbl_entry[] = {
2975 /* command name , id , length , offset , mult , command handler */ 2941 /* command name , id , length , offset , mult , command handler */
2976 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */ 2942 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
2977 { "INIT_IO_RESTRICT_PROG" , 0x32, 11 , 6 , 4 , init_io_restrict_prog }, 2943 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
2978 { "INIT_REPEAT" , 0x33, 2 , 0 , 0 , init_repeat }, 2944 { "INIT_REPEAT" , 0x33, init_repeat },
2979 { "INIT_IO_RESTRICT_PLL" , 0x34, 12 , 7 , 2 , init_io_restrict_pll }, 2945 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
2980 { "INIT_END_REPEAT" , 0x36, 1 , 0 , 0 , init_end_repeat }, 2946 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
2981 { "INIT_COPY" , 0x37, 11 , 0 , 0 , init_copy }, 2947 { "INIT_COPY" , 0x37, init_copy },
2982 { "INIT_NOT" , 0x38, 1 , 0 , 0 , init_not }, 2948 { "INIT_NOT" , 0x38, init_not },
2983 { "INIT_IO_FLAG_CONDITION" , 0x39, 2 , 0 , 0 , init_io_flag_condition }, 2949 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
2984 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, 18 , 17 , 2 , init_idx_addr_latched }, 2950 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
2985 { "INIT_IO_RESTRICT_PLL2" , 0x4A, 11 , 6 , 4 , init_io_restrict_pll2 }, 2951 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
2986 { "INIT_PLL2" , 0x4B, 9 , 0 , 0 , init_pll2 }, 2952 { "INIT_PLL2" , 0x4B, init_pll2 },
2987 { "INIT_I2C_BYTE" , 0x4C, 4 , 3 , 3 , init_i2c_byte }, 2953 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
2988 { "INIT_ZM_I2C_BYTE" , 0x4D, 4 , 3 , 2 , init_zm_i2c_byte }, 2954 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
2989 { "INIT_ZM_I2C" , 0x4E, 4 , 3 , 1 , init_zm_i2c }, 2955 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
2990 { "INIT_TMDS" , 0x4F, 5 , 0 , 0 , init_tmds }, 2956 { "INIT_TMDS" , 0x4F, init_tmds },
2991 { "INIT_ZM_TMDS_GROUP" , 0x50, 3 , 2 , 2 , init_zm_tmds_group }, 2957 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
2992 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, 5 , 4 , 1 , init_cr_idx_adr_latch }, 2958 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
2993 { "INIT_CR" , 0x52, 4 , 0 , 0 , init_cr }, 2959 { "INIT_CR" , 0x52, init_cr },
2994 { "INIT_ZM_CR" , 0x53, 3 , 0 , 0 , init_zm_cr }, 2960 { "INIT_ZM_CR" , 0x53, init_zm_cr },
2995 { "INIT_ZM_CR_GROUP" , 0x54, 2 , 1 , 2 , init_zm_cr_group }, 2961 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
2996 { "INIT_CONDITION_TIME" , 0x56, 3 , 0 , 0 , init_condition_time }, 2962 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
2997 { "INIT_ZM_REG_SEQUENCE" , 0x58, 6 , 5 , 4 , init_zm_reg_sequence }, 2963 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
2998 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */ 2964 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
2999 { "INIT_SUB_DIRECT" , 0x5B, 3 , 0 , 0 , init_sub_direct }, 2965 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3000 { "INIT_COPY_NV_REG" , 0x5F, 22 , 0 , 0 , init_copy_nv_reg }, 2966 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3001 { "INIT_ZM_INDEX_IO" , 0x62, 5 , 0 , 0 , init_zm_index_io }, 2967 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3002 { "INIT_COMPUTE_MEM" , 0x63, 1 , 0 , 0 , init_compute_mem }, 2968 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3003 { "INIT_RESET" , 0x65, 13 , 0 , 0 , init_reset }, 2969 { "INIT_RESET" , 0x65, init_reset },
3004 { "INIT_CONFIGURE_MEM" , 0x66, 1 , 0 , 0 , init_configure_mem }, 2970 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3005 { "INIT_CONFIGURE_CLK" , 0x67, 1 , 0 , 0 , init_configure_clk }, 2971 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3006 { "INIT_CONFIGURE_PREINIT" , 0x68, 1 , 0 , 0 , init_configure_preinit }, 2972 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3007 { "INIT_IO" , 0x69, 5 , 0 , 0 , init_io }, 2973 { "INIT_IO" , 0x69, init_io },
3008 { "INIT_SUB" , 0x6B, 2 , 0 , 0 , init_sub }, 2974 { "INIT_SUB" , 0x6B, init_sub },
3009 { "INIT_RAM_CONDITION" , 0x6D, 3 , 0 , 0 , init_ram_condition }, 2975 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3010 { "INIT_NV_REG" , 0x6E, 13 , 0 , 0 , init_nv_reg }, 2976 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3011 { "INIT_MACRO" , 0x6F, 2 , 0 , 0 , init_macro }, 2977 { "INIT_MACRO" , 0x6F, init_macro },
3012 { "INIT_DONE" , 0x71, 1 , 0 , 0 , init_done }, 2978 { "INIT_DONE" , 0x71, init_done },
3013 { "INIT_RESUME" , 0x72, 1 , 0 , 0 , init_resume }, 2979 { "INIT_RESUME" , 0x72, init_resume },
3014 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */ 2980 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
3015 { "INIT_TIME" , 0x74, 3 , 0 , 0 , init_time }, 2981 { "INIT_TIME" , 0x74, init_time },
3016 { "INIT_CONDITION" , 0x75, 2 , 0 , 0 , init_condition }, 2982 { "INIT_CONDITION" , 0x75, init_condition },
3017 { "INIT_IO_CONDITION" , 0x76, 2 , 0 , 0 , init_io_condition }, 2983 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3018 { "INIT_INDEX_IO" , 0x78, 6 , 0 , 0 , init_index_io }, 2984 { "INIT_INDEX_IO" , 0x78, init_index_io },
3019 { "INIT_PLL" , 0x79, 7 , 0 , 0 , init_pll }, 2985 { "INIT_PLL" , 0x79, init_pll },
3020 { "INIT_ZM_REG" , 0x7A, 9 , 0 , 0 , init_zm_reg }, 2986 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3021 /* INIT_RAM_RESTRICT_PLL's length is adjusted by the BIT M table */ 2987 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3022 { "INIT_RAM_RESTRICT_PLL" , 0x87, 2 , 0 , 0 , init_ram_restrict_pll }, 2988 { "INIT_8C" , 0x8C, init_8c },
3023 { "INIT_8C" , 0x8C, 1 , 0 , 0 , init_8c }, 2989 { "INIT_8D" , 0x8D, init_8d },
3024 { "INIT_8D" , 0x8D, 1 , 0 , 0 , init_8d }, 2990 { "INIT_GPIO" , 0x8E, init_gpio },
3025 { "INIT_GPIO" , 0x8E, 1 , 0 , 0 , init_gpio }, 2991 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3026 /* INIT_RAM_RESTRICT_ZM_REG_GROUP's mult is loaded by M table in BIT */ 2992 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3027 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, 7 , 6 , 0 , init_ram_restrict_zm_reg_group }, 2993 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3028 { "INIT_COPY_ZM_REG" , 0x90, 9 , 0 , 0 , init_copy_zm_reg }, 2994 { "INIT_RESERVED" , 0x92, init_reserved },
3029 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, 6 , 5 , 4 , init_zm_reg_group_addr_latched }, 2995 { "INIT_96" , 0x96, init_96 },
3030 { "INIT_RESERVED" , 0x92, 1 , 0 , 0 , init_reserved }, 2996 { "INIT_97" , 0x97, init_97 },
3031 { "INIT_96" , 0x96, 17 , 0 , 0 , init_96 }, 2997 { "INIT_AUXCH" , 0x98, init_auxch },
3032 { "INIT_97" , 0x97, 13 , 0 , 0 , init_97 }, 2998 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3033 { "INIT_AUXCH" , 0x98, 6 , 5 , 2 , init_auxch }, 2999 { NULL , 0 , NULL }
3034 { "INIT_ZM_AUXCH" , 0x99, 6 , 5 , 1 , init_zm_auxch },
3035 { NULL , 0 , 0 , 0 , 0 , NULL }
3036}; 3000};
3037 3001
3038static unsigned int get_init_table_entry_length(struct nvbios *bios, unsigned int offset, int i)
3039{
3040 /* Calculates the length of a given init table entry. */
3041 return itbl_entry[i].length + bios->data[offset + itbl_entry[i].length_offset]*itbl_entry[i].length_multiplier;
3042}
3043
3044#define MAX_TABLE_OPS 1000 3002#define MAX_TABLE_OPS 1000
3045 3003
3046static int 3004static int
@@ -3056,7 +3014,7 @@ parse_init_table(struct nvbios *bios, unsigned int offset,
3056 * is changed back to EXECUTE. 3014 * is changed back to EXECUTE.
3057 */ 3015 */
3058 3016
3059 int count = 0, i; 3017 int count = 0, i, res;
3060 uint8_t id; 3018 uint8_t id;
3061 3019
3062 /* 3020 /*
@@ -3076,22 +3034,21 @@ parse_init_table(struct nvbios *bios, unsigned int offset,
3076 offset, itbl_entry[i].id, itbl_entry[i].name); 3034 offset, itbl_entry[i].id, itbl_entry[i].name);
3077 3035
3078 /* execute eventual command handler */ 3036 /* execute eventual command handler */
3079 if (itbl_entry[i].handler) 3037 res = (*itbl_entry[i].handler)(bios, offset, iexec);
3080 if (!(*itbl_entry[i].handler)(bios, offset, iexec)) 3038 if (!res)
3081 break; 3039 break;
3040 /*
3041 * Add the offset of the current command including all data
3042 * of that command. The offset will then be pointing on the
3043 * next op code.
3044 */
3045 offset += res;
3082 } else { 3046 } else {
3083 NV_ERROR(bios->dev, 3047 NV_ERROR(bios->dev,
3084 "0x%04X: Init table command not found: " 3048 "0x%04X: Init table command not found: "
3085 "0x%02X\n", offset, id); 3049 "0x%02X\n", offset, id);
3086 return -ENOENT; 3050 return -ENOENT;
3087 } 3051 }
3088
3089 /*
3090 * Add the offset of the current command including all data
3091 * of that command. The offset will then be pointing on the
3092 * next op code.
3093 */
3094 offset += get_init_table_entry_length(bios, offset, i);
3095 } 3052 }
3096 3053
3097 if (offset >= bios->length) 3054 if (offset >= bios->length)
@@ -3198,16 +3155,25 @@ static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entr
3198 } 3155 }
3199#ifdef __powerpc__ 3156#ifdef __powerpc__
3200 /* Powerbook specific quirks */ 3157 /* Powerbook specific quirks */
3201 if (script == LVDS_RESET && ((dev->pci_device & 0xffff) == 0x0179 || (dev->pci_device & 0xffff) == 0x0329)) 3158 if ((dev->pci_device & 0xffff) == 0x0179 ||
3202 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72); 3159 (dev->pci_device & 0xffff) == 0x0189 ||
3203 if ((dev->pci_device & 0xffff) == 0x0179 || (dev->pci_device & 0xffff) == 0x0189 || (dev->pci_device & 0xffff) == 0x0329) { 3160 (dev->pci_device & 0xffff) == 0x0329) {
3204 if (script == LVDS_PANEL_ON) { 3161 if (script == LVDS_RESET) {
3205 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) | (1 << 31)); 3162 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3206 bios_wr32(bios, NV_PCRTC_GPIO_EXT, bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1); 3163
3207 } 3164 } else if (script == LVDS_PANEL_ON) {
3208 if (script == LVDS_PANEL_OFF) { 3165 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3209 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) & ~(1 << 31)); 3166 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3210 bios_wr32(bios, NV_PCRTC_GPIO_EXT, bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3); 3167 | (1 << 31));
3168 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3169 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
3170
3171 } else if (script == LVDS_PANEL_OFF) {
3172 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3173 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3174 & ~(1 << 31));
3175 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3176 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
3211 } 3177 }
3212 } 3178 }
3213#endif 3179#endif
@@ -3854,7 +3820,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3854 * script tables is a pointer to the script to execute. 3820 * script tables is a pointer to the script to execute.
3855 */ 3821 */
3856 3822
3857 NV_DEBUG(dev, "Searching for output entry for %d %d %d\n", 3823 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
3858 dcbent->type, dcbent->location, dcbent->or); 3824 dcbent->type, dcbent->location, dcbent->or);
3859 otable = bios_output_config_match(dev, dcbent, table[1] + 3825 otable = bios_output_config_match(dev, dcbent, table[1] +
3860 bios->display.script_table_ptr, 3826 bios->display.script_table_ptr,
@@ -3884,7 +3850,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3884 if (pxclk == 0) { 3850 if (pxclk == 0) {
3885 script = ROM16(otable[6]); 3851 script = ROM16(otable[6]);
3886 if (!script) { 3852 if (!script) {
3887 NV_DEBUG(dev, "output script 0 not found\n"); 3853 NV_DEBUG_KMS(dev, "output script 0 not found\n");
3888 return 1; 3854 return 1;
3889 } 3855 }
3890 3856
@@ -3894,7 +3860,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3894 if (pxclk == -1) { 3860 if (pxclk == -1) {
3895 script = ROM16(otable[8]); 3861 script = ROM16(otable[8]);
3896 if (!script) { 3862 if (!script) {
3897 NV_DEBUG(dev, "output script 1 not found\n"); 3863 NV_DEBUG_KMS(dev, "output script 1 not found\n");
3898 return 1; 3864 return 1;
3899 } 3865 }
3900 3866
@@ -3907,7 +3873,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3907 else 3873 else
3908 script = 0; 3874 script = 0;
3909 if (!script) { 3875 if (!script) {
3910 NV_DEBUG(dev, "output script 2 not found\n"); 3876 NV_DEBUG_KMS(dev, "output script 2 not found\n");
3911 return 1; 3877 return 1;
3912 } 3878 }
3913 3879
@@ -3931,7 +3897,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3931 if (script) 3897 if (script)
3932 script = clkcmptable(bios, script, -pxclk); 3898 script = clkcmptable(bios, script, -pxclk);
3933 if (!script) { 3899 if (!script) {
3934 NV_DEBUG(dev, "clock script 1 not found\n"); 3900 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
3935 return 1; 3901 return 1;
3936 } 3902 }
3937 3903
@@ -4606,10 +4572,6 @@ parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4606 * stuff that we don't use - their use currently unknown 4572 * stuff that we don't use - their use currently unknown
4607 */ 4573 */
4608 4574
4609 uint16_t rr_strap_xlat;
4610 uint8_t rr_group_count;
4611 int i;
4612
4613 /* 4575 /*
4614 * Older bios versions don't have a sufficiently long table for 4576 * Older bios versions don't have a sufficiently long table for
4615 * what we want 4577 * what we want
@@ -4618,24 +4580,13 @@ parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4618 return 0; 4580 return 0;
4619 4581
4620 if (bitentry->id[1] < 2) { 4582 if (bitentry->id[1] < 2) {
4621 rr_group_count = bios->data[bitentry->offset + 2]; 4583 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
4622 rr_strap_xlat = ROM16(bios->data[bitentry->offset + 3]); 4584 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
4623 } else { 4585 } else {
4624 rr_group_count = bios->data[bitentry->offset + 0]; 4586 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
4625 rr_strap_xlat = ROM16(bios->data[bitentry->offset + 1]); 4587 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
4626 } 4588 }
4627 4589
4628 /* adjust length of INIT_87 */
4629 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != 0x87); i++);
4630 itbl_entry[i].length += rr_group_count * 4;
4631
4632 /* set up multiplier for INIT_RAM_RESTRICT_ZM_REG_GROUP */
4633 for (; itbl_entry[i].name && (itbl_entry[i].id != 0x8f); i++);
4634 itbl_entry[i].length_multiplier = rr_group_count * 4;
4635
4636 init_ram_restrict_zm_reg_group_blocklen = itbl_entry[i].length_multiplier;
4637 bios->ram_restrict_tbl_ptr = rr_strap_xlat;
4638
4639 return 0; 4590 return 0;
4640} 4591}
4641 4592
@@ -5234,7 +5185,7 @@ parse_dcb_connector_table(struct nvbios *bios)
5234 int i; 5185 int i;
5235 5186
5236 if (!bios->bdcb.connector_table_ptr) { 5187 if (!bios->bdcb.connector_table_ptr) {
5237 NV_DEBUG(dev, "No DCB connector table present\n"); 5188 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
5238 return; 5189 return;
5239 } 5190 }
5240 5191
@@ -5451,52 +5402,49 @@ static bool
5451parse_dcb15_entry(struct drm_device *dev, struct parsed_dcb *dcb, 5402parse_dcb15_entry(struct drm_device *dev, struct parsed_dcb *dcb,
5452 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 5403 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5453{ 5404{
5454 if (conn != 0xf0003f00 && conn != 0xf2247f10 && conn != 0xf2204001 && 5405 switch (conn & 0x0000000f) {
5455 conn != 0xf2204301 && conn != 0xf2204311 && conn != 0xf2208001 && 5406 case 0:
5456 conn != 0xf2244001 && conn != 0xf2244301 && conn != 0xf2244311 && 5407 entry->type = OUTPUT_ANALOG;
5457 conn != 0xf4204011 && conn != 0xf4208011 && conn != 0xf4248011 && 5408 break;
5458 conn != 0xf2045ff2 && conn != 0xf2045f14 && conn != 0xf207df14 && 5409 case 1:
5459 conn != 0xf2205004 && conn != 0xf2209004) { 5410 entry->type = OUTPUT_TV;
5460 NV_ERROR(dev, "Unknown DCB 1.5 entry, please report\n"); 5411 break;
5461 5412 case 2:
5462 /* cause output setting to fail for !TV, so message is seen */ 5413 case 3:
5463 if ((conn & 0xf) != 0x1)
5464 dcb->entries = 0;
5465
5466 return false;
5467 }
5468 /* most of the below is a "best guess" atm */
5469 entry->type = conn & 0xf;
5470 if (entry->type == 2)
5471 /* another way of specifying straps based lvds... */
5472 entry->type = OUTPUT_LVDS; 5414 entry->type = OUTPUT_LVDS;
5473 if (entry->type == 4) { /* digital */ 5415 break;
5474 if (conn & 0x10) 5416 case 4:
5475 entry->type = OUTPUT_LVDS; 5417 switch ((conn & 0x000000f0) >> 4) {
5476 else 5418 case 0:
5477 entry->type = OUTPUT_TMDS; 5419 entry->type = OUTPUT_TMDS;
5420 break;
5421 case 1:
5422 entry->type = OUTPUT_LVDS;
5423 break;
5424 default:
5425 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n",
5426 (conn & 0x000000f0) >> 4);
5427 return false;
5428 }
5429 break;
5430 default:
5431 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
5432 return false;
5478 } 5433 }
5479 /* what's in bits 5-13? could be some encoder maker thing, in tv case */ 5434
5480 entry->i2c_index = (conn >> 14) & 0xf; 5435 entry->i2c_index = (conn & 0x0003c000) >> 14;
5481 /* raw heads field is in range 0-1, so move to 1-2 */ 5436 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
5482 entry->heads = ((conn >> 18) & 0x7) + 1; 5437 entry->or = entry->heads; /* same as heads, hopefully safe enough */
5483 entry->location = (conn >> 21) & 0xf; 5438 entry->location = (conn & 0x01e00000) >> 21;
5484 /* unused: entry->bus = (conn >> 25) & 0x7; */ 5439 entry->bus = (conn & 0x0e000000) >> 25;
5485 /* set or to be same as heads -- hopefully safe enough */
5486 entry->or = entry->heads;
5487 entry->duallink_possible = false; 5440 entry->duallink_possible = false;
5488 5441
5489 switch (entry->type) { 5442 switch (entry->type) {
5490 case OUTPUT_ANALOG: 5443 case OUTPUT_ANALOG:
5491 entry->crtconf.maxfreq = (conf & 0xffff) * 10; 5444 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5492 break; 5445 break;
5493 case OUTPUT_LVDS: 5446 case OUTPUT_TV:
5494 /* 5447 entry->tvconf.has_component_output = false;
5495 * This is probably buried in conn's unknown bits.
5496 * This will upset EDID-ful models, if they exist
5497 */
5498 entry->lvdsconf.use_straps_for_mode = true;
5499 entry->lvdsconf.use_power_scripts = true;
5500 break; 5448 break;
5501 case OUTPUT_TMDS: 5449 case OUTPUT_TMDS:
5502 /* 5450 /*
@@ -5505,8 +5453,12 @@ parse_dcb15_entry(struct drm_device *dev, struct parsed_dcb *dcb,
5505 */ 5453 */
5506 fabricate_vga_output(dcb, entry->i2c_index, entry->heads); 5454 fabricate_vga_output(dcb, entry->i2c_index, entry->heads);
5507 break; 5455 break;
5508 case OUTPUT_TV: 5456 case OUTPUT_LVDS:
5509 entry->tvconf.has_component_output = false; 5457 if ((conn & 0x00003f00) != 0x10)
5458 entry->lvdsconf.use_straps_for_mode = true;
5459 entry->lvdsconf.use_power_scripts = true;
5460 break;
5461 default:
5510 break; 5462 break;
5511 } 5463 }
5512 5464
@@ -5581,11 +5533,13 @@ void merge_like_dcb_entries(struct drm_device *dev, struct parsed_dcb *dcb)
5581 dcb->entries = newentries; 5533 dcb->entries = newentries;
5582} 5534}
5583 5535
5584static int parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) 5536static int
5537parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads)
5585{ 5538{
5539 struct drm_nouveau_private *dev_priv = dev->dev_private;
5586 struct bios_parsed_dcb *bdcb = &bios->bdcb; 5540 struct bios_parsed_dcb *bdcb = &bios->bdcb;
5587 struct parsed_dcb *dcb; 5541 struct parsed_dcb *dcb;
5588 uint16_t dcbptr, i2ctabptr = 0; 5542 uint16_t dcbptr = 0, i2ctabptr = 0;
5589 uint8_t *dcbtable; 5543 uint8_t *dcbtable;
5590 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES; 5544 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
5591 bool configblock = true; 5545 bool configblock = true;
@@ -5596,16 +5550,18 @@ static int parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool two
5596 dcb->entries = 0; 5550 dcb->entries = 0;
5597 5551
5598 /* get the offset from 0x36 */ 5552 /* get the offset from 0x36 */
5599 dcbptr = ROM16(bios->data[0x36]); 5553 if (dev_priv->card_type > NV_04) {
5554 dcbptr = ROM16(bios->data[0x36]);
5555 if (dcbptr == 0x0000)
5556 NV_WARN(dev, "No output data (DCB) found in BIOS\n");
5557 }
5600 5558
5559 /* this situation likely means a really old card, pre DCB */
5601 if (dcbptr == 0x0) { 5560 if (dcbptr == 0x0) {
5602 NV_WARN(dev, "No output data (DCB) found in BIOS, " 5561 NV_INFO(dev, "Assuming a CRT output exists\n");
5603 "assuming a CRT output exists\n");
5604 /* this situation likely means a really old card, pre DCB */
5605 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); 5562 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5606 5563
5607 if (nv04_tv_identify(dev, 5564 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
5608 bios->legacy.i2c_indices.tv) >= 0)
5609 fabricate_tv_output(dcb, twoHeads); 5565 fabricate_tv_output(dcb, twoHeads);
5610 5566
5611 return 0; 5567 return 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h
index 1d5f10bd78ed..058e98c76d89 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h
@@ -227,6 +227,7 @@ struct nvbios {
227 227
228 uint16_t pll_limit_tbl_ptr; 228 uint16_t pll_limit_tbl_ptr;
229 uint16_t ram_restrict_tbl_ptr; 229 uint16_t ram_restrict_tbl_ptr;
230 uint8_t ram_restrict_group_count;
230 231
231 uint16_t some_script_ptr; /* BIT I + 14 */ 232 uint16_t some_script_ptr; /* BIT I + 14 */
232 uint16_t init96_tbl_ptr; /* BIT I + 16 */ 233 uint16_t init96_tbl_ptr; /* BIT I + 16 */
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index aa2dfbc3e351..db0ed4c13f98 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -33,10 +33,13 @@
33#include "nouveau_drv.h" 33#include "nouveau_drv.h"
34#include "nouveau_dma.h" 34#include "nouveau_dma.h"
35 35
36#include <linux/log2.h>
37
36static void 38static void
37nouveau_bo_del_ttm(struct ttm_buffer_object *bo) 39nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
38{ 40{
39 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); 41 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
42 struct drm_device *dev = dev_priv->dev;
40 struct nouveau_bo *nvbo = nouveau_bo(bo); 43 struct nouveau_bo *nvbo = nouveau_bo(bo);
41 44
42 ttm_bo_kunmap(&nvbo->kmap); 45 ttm_bo_kunmap(&nvbo->kmap);
@@ -44,12 +47,87 @@ nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
44 if (unlikely(nvbo->gem)) 47 if (unlikely(nvbo->gem))
45 DRM_ERROR("bo %p still attached to GEM object\n", bo); 48 DRM_ERROR("bo %p still attached to GEM object\n", bo);
46 49
50 if (nvbo->tile)
51 nv10_mem_expire_tiling(dev, nvbo->tile, NULL);
52
47 spin_lock(&dev_priv->ttm.bo_list_lock); 53 spin_lock(&dev_priv->ttm.bo_list_lock);
48 list_del(&nvbo->head); 54 list_del(&nvbo->head);
49 spin_unlock(&dev_priv->ttm.bo_list_lock); 55 spin_unlock(&dev_priv->ttm.bo_list_lock);
50 kfree(nvbo); 56 kfree(nvbo);
51} 57}
52 58
59static void
60nouveau_bo_fixup_align(struct drm_device *dev,
61 uint32_t tile_mode, uint32_t tile_flags,
62 int *align, int *size)
63{
64 struct drm_nouveau_private *dev_priv = dev->dev_private;
65
66 /*
67 * Some of the tile_flags have a periodic structure of N*4096 bytes,
68 * align to to that as well as the page size. Overallocate memory to
69 * avoid corruption of other buffer objects.
70 */
71 if (dev_priv->card_type == NV_50) {
72 uint32_t block_size = nouveau_mem_fb_amount(dev) >> 15;
73 int i;
74
75 switch (tile_flags) {
76 case 0x1800:
77 case 0x2800:
78 case 0x4800:
79 case 0x7a00:
80 *size = roundup(*size, block_size);
81 if (is_power_of_2(block_size)) {
82 *size += 3 * block_size;
83 for (i = 1; i < 10; i++) {
84 *align = 12 * i * block_size;
85 if (!(*align % 65536))
86 break;
87 }
88 } else {
89 *size += 6 * block_size;
90 for (i = 1; i < 10; i++) {
91 *align = 8 * i * block_size;
92 if (!(*align % 65536))
93 break;
94 }
95 }
96 break;
97 default:
98 break;
99 }
100
101 } else {
102 if (tile_mode) {
103 if (dev_priv->chipset >= 0x40) {
104 *align = 65536;
105 *size = roundup(*size, 64 * tile_mode);
106
107 } else if (dev_priv->chipset >= 0x30) {
108 *align = 32768;
109 *size = roundup(*size, 64 * tile_mode);
110
111 } else if (dev_priv->chipset >= 0x20) {
112 *align = 16384;
113 *size = roundup(*size, 64 * tile_mode);
114
115 } else if (dev_priv->chipset >= 0x10) {
116 *align = 16384;
117 *size = roundup(*size, 32 * tile_mode);
118 }
119 }
120 }
121
122 /* ALIGN works only on powers of two. */
123 *size = roundup(*size, PAGE_SIZE);
124
125 if (dev_priv->card_type == NV_50) {
126 *size = roundup(*size, 65536);
127 *align = max(65536, *align);
128 }
129}
130
53int 131int
54nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, 132nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
55 int size, int align, uint32_t flags, uint32_t tile_mode, 133 int size, int align, uint32_t flags, uint32_t tile_mode,
@@ -58,7 +136,7 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
58{ 136{
59 struct drm_nouveau_private *dev_priv = dev->dev_private; 137 struct drm_nouveau_private *dev_priv = dev->dev_private;
60 struct nouveau_bo *nvbo; 138 struct nouveau_bo *nvbo;
61 int ret, n = 0; 139 int ret = 0;
62 140
63 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); 141 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
64 if (!nvbo) 142 if (!nvbo)
@@ -70,59 +148,14 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
70 nvbo->tile_mode = tile_mode; 148 nvbo->tile_mode = tile_mode;
71 nvbo->tile_flags = tile_flags; 149 nvbo->tile_flags = tile_flags;
72 150
73 /* 151 nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size);
74 * Some of the tile_flags have a periodic structure of N*4096 bytes,
75 * align to to that as well as the page size. Overallocate memory to
76 * avoid corruption of other buffer objects.
77 */
78 switch (tile_flags) {
79 case 0x1800:
80 case 0x2800:
81 case 0x4800:
82 case 0x7a00:
83 if (dev_priv->chipset >= 0xA0) {
84 /* This is based on high end cards with 448 bits
85 * memory bus, could be different elsewhere.*/
86 size += 6 * 28672;
87 /* 8 * 28672 is the actual alignment requirement,
88 * but we must also align to page size. */
89 align = 2 * 8 * 28672;
90 } else if (dev_priv->chipset >= 0x90) {
91 size += 3 * 16384;
92 align = 12 * 16834;
93 } else {
94 size += 3 * 8192;
95 /* 12 * 8192 is the actual alignment requirement,
96 * but we must also align to page size. */
97 align = 2 * 12 * 8192;
98 }
99 break;
100 default:
101 break;
102 }
103
104 align >>= PAGE_SHIFT; 152 align >>= PAGE_SHIFT;
105 153
106 size = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
107 if (dev_priv->card_type == NV_50) {
108 size = (size + 65535) & ~65535;
109 if (align < (65536 / PAGE_SIZE))
110 align = (65536 / PAGE_SIZE);
111 }
112
113 if (flags & TTM_PL_FLAG_VRAM)
114 nvbo->placements[n++] = TTM_PL_FLAG_VRAM | TTM_PL_MASK_CACHING;
115 if (flags & TTM_PL_FLAG_TT)
116 nvbo->placements[n++] = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
117 nvbo->placement.fpfn = 0; 154 nvbo->placement.fpfn = 0;
118 nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0; 155 nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0;
119 nvbo->placement.placement = nvbo->placements; 156 nouveau_bo_placement_set(nvbo, flags);
120 nvbo->placement.busy_placement = nvbo->placements;
121 nvbo->placement.num_placement = n;
122 nvbo->placement.num_busy_placement = n;
123 157
124 nvbo->channel = chan; 158 nvbo->channel = chan;
125 nouveau_bo_placement_set(nvbo, flags);
126 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size, 159 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
127 ttm_bo_type_device, &nvbo->placement, align, 0, 160 ttm_bo_type_device, &nvbo->placement, align, 0,
128 false, NULL, size, nouveau_bo_del_ttm); 161 false, NULL, size, nouveau_bo_del_ttm);
@@ -154,6 +187,11 @@ nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t memtype)
154 nvbo->placement.busy_placement = nvbo->placements; 187 nvbo->placement.busy_placement = nvbo->placements;
155 nvbo->placement.num_placement = n; 188 nvbo->placement.num_placement = n;
156 nvbo->placement.num_busy_placement = n; 189 nvbo->placement.num_busy_placement = n;
190
191 if (nvbo->pin_refcnt) {
192 while (n--)
193 nvbo->placements[n] |= TTM_PL_FLAG_NO_EVICT;
194 }
157} 195}
158 196
159int 197int
@@ -400,16 +438,23 @@ nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
400 struct nouveau_bo *nvbo = nouveau_bo(bo); 438 struct nouveau_bo *nvbo = nouveau_bo(bo);
401 439
402 switch (bo->mem.mem_type) { 440 switch (bo->mem.mem_type) {
441 case TTM_PL_VRAM:
442 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT |
443 TTM_PL_FLAG_SYSTEM);
444 break;
403 default: 445 default:
404 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM); 446 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM);
405 break; 447 break;
406 } 448 }
449
450 *pl = nvbo->placement;
407} 451}
408 452
409 453
410/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access 454/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
411 * TTM_PL_{VRAM,TT} directly. 455 * TTM_PL_{VRAM,TT} directly.
412 */ 456 */
457
413static int 458static int
414nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan, 459nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
415 struct nouveau_bo *nvbo, bool evict, bool no_wait, 460 struct nouveau_bo *nvbo, bool evict, bool no_wait,
@@ -424,6 +469,8 @@ nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
424 469
425 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, 470 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL,
426 evict, no_wait, new_mem); 471 evict, no_wait, new_mem);
472 if (nvbo->channel && nvbo->channel != chan)
473 ret = nouveau_fence_wait(fence, NULL, false, false);
427 nouveau_fence_unref((void *)&fence); 474 nouveau_fence_unref((void *)&fence);
428 return ret; 475 return ret;
429} 476}
@@ -444,22 +491,20 @@ nouveau_bo_mem_ctxdma(struct nouveau_bo *nvbo, struct nouveau_channel *chan,
444} 491}
445 492
446static int 493static int
447nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, int no_wait, 494nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
448 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) 495 int no_wait, struct ttm_mem_reg *new_mem)
449{ 496{
450 struct nouveau_bo *nvbo = nouveau_bo(bo); 497 struct nouveau_bo *nvbo = nouveau_bo(bo);
451 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); 498 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
499 struct ttm_mem_reg *old_mem = &bo->mem;
452 struct nouveau_channel *chan; 500 struct nouveau_channel *chan;
453 uint64_t src_offset, dst_offset; 501 uint64_t src_offset, dst_offset;
454 uint32_t page_count; 502 uint32_t page_count;
455 int ret; 503 int ret;
456 504
457 chan = nvbo->channel; 505 chan = nvbo->channel;
458 if (!chan || nvbo->tile_flags || nvbo->no_vm) { 506 if (!chan || nvbo->tile_flags || nvbo->no_vm)
459 chan = dev_priv->channel; 507 chan = dev_priv->channel;
460 if (!chan)
461 return -EINVAL;
462 }
463 508
464 src_offset = old_mem->mm_node->start << PAGE_SHIFT; 509 src_offset = old_mem->mm_node->start << PAGE_SHIFT;
465 dst_offset = new_mem->mm_node->start << PAGE_SHIFT; 510 dst_offset = new_mem->mm_node->start << PAGE_SHIFT;
@@ -539,7 +584,7 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
539 584
540 placement.fpfn = placement.lpfn = 0; 585 placement.fpfn = placement.lpfn = 0;
541 placement.num_placement = placement.num_busy_placement = 1; 586 placement.num_placement = placement.num_busy_placement = 1;
542 placement.placement = &placement_memtype; 587 placement.placement = placement.busy_placement = &placement_memtype;
543 588
544 tmp_mem = *new_mem; 589 tmp_mem = *new_mem;
545 tmp_mem.mm_node = NULL; 590 tmp_mem.mm_node = NULL;
@@ -551,7 +596,7 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
551 if (ret) 596 if (ret)
552 goto out; 597 goto out;
553 598
554 ret = nouveau_bo_move_m2mf(bo, true, no_wait, &bo->mem, &tmp_mem); 599 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait, &tmp_mem);
555 if (ret) 600 if (ret)
556 goto out; 601 goto out;
557 602
@@ -577,7 +622,7 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
577 622
578 placement.fpfn = placement.lpfn = 0; 623 placement.fpfn = placement.lpfn = 0;
579 placement.num_placement = placement.num_busy_placement = 1; 624 placement.num_placement = placement.num_busy_placement = 1;
580 placement.placement = &placement_memtype; 625 placement.placement = placement.busy_placement = &placement_memtype;
581 626
582 tmp_mem = *new_mem; 627 tmp_mem = *new_mem;
583 tmp_mem.mm_node = NULL; 628 tmp_mem.mm_node = NULL;
@@ -589,7 +634,7 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
589 if (ret) 634 if (ret)
590 goto out; 635 goto out;
591 636
592 ret = nouveau_bo_move_m2mf(bo, true, no_wait, &bo->mem, new_mem); 637 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem);
593 if (ret) 638 if (ret)
594 goto out; 639 goto out;
595 640
@@ -604,51 +649,106 @@ out:
604} 649}
605 650
606static int 651static int
607nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, 652nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
608 bool no_wait, struct ttm_mem_reg *new_mem) 653 struct nouveau_tile_reg **new_tile)
609{ 654{
610 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); 655 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
611 struct nouveau_bo *nvbo = nouveau_bo(bo);
612 struct drm_device *dev = dev_priv->dev; 656 struct drm_device *dev = dev_priv->dev;
613 struct ttm_mem_reg *old_mem = &bo->mem; 657 struct nouveau_bo *nvbo = nouveau_bo(bo);
658 uint64_t offset;
614 int ret; 659 int ret;
615 660
616 if (dev_priv->card_type == NV_50 && new_mem->mem_type == TTM_PL_VRAM && 661 if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
617 !nvbo->no_vm) { 662 /* Nothing to do. */
618 uint64_t offset = new_mem->mm_node->start << PAGE_SHIFT; 663 *new_tile = NULL;
664 return 0;
665 }
619 666
667 offset = new_mem->mm_node->start << PAGE_SHIFT;
668
669 if (dev_priv->card_type == NV_50) {
620 ret = nv50_mem_vm_bind_linear(dev, 670 ret = nv50_mem_vm_bind_linear(dev,
621 offset + dev_priv->vm_vram_base, 671 offset + dev_priv->vm_vram_base,
622 new_mem->size, nvbo->tile_flags, 672 new_mem->size, nvbo->tile_flags,
623 offset); 673 offset);
624 if (ret) 674 if (ret)
625 return ret; 675 return ret;
676
677 } else if (dev_priv->card_type >= NV_10) {
678 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
679 nvbo->tile_mode);
626 } 680 }
627 681
628 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE) 682 return 0;
629 return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); 683}
684
685static void
686nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
687 struct nouveau_tile_reg *new_tile,
688 struct nouveau_tile_reg **old_tile)
689{
690 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
691 struct drm_device *dev = dev_priv->dev;
630 692
693 if (dev_priv->card_type >= NV_10 &&
694 dev_priv->card_type < NV_50) {
695 if (*old_tile)
696 nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj);
697
698 *old_tile = new_tile;
699 }
700}
701
702static int
703nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
704 bool no_wait, struct ttm_mem_reg *new_mem)
705{
706 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
707 struct nouveau_bo *nvbo = nouveau_bo(bo);
708 struct ttm_mem_reg *old_mem = &bo->mem;
709 struct nouveau_tile_reg *new_tile = NULL;
710 int ret = 0;
711
712 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
713 if (ret)
714 return ret;
715
716 /* Software copy if the card isn't up and running yet. */
717 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE ||
718 !dev_priv->channel) {
719 ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
720 goto out;
721 }
722
723 /* Fake bo copy. */
631 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) { 724 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
632 BUG_ON(bo->mem.mm_node != NULL); 725 BUG_ON(bo->mem.mm_node != NULL);
633 bo->mem = *new_mem; 726 bo->mem = *new_mem;
634 new_mem->mm_node = NULL; 727 new_mem->mm_node = NULL;
635 return 0; 728 goto out;
636 } 729 }
637 730
638 if (new_mem->mem_type == TTM_PL_SYSTEM) { 731 /* Hardware assisted copy. */
639 if (old_mem->mem_type == TTM_PL_SYSTEM) 732 if (new_mem->mem_type == TTM_PL_SYSTEM)
640 return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); 733 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait, new_mem);
641 if (nouveau_bo_move_flipd(bo, evict, intr, no_wait, new_mem)) 734 else if (old_mem->mem_type == TTM_PL_SYSTEM)
642 return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); 735 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait, new_mem);
643 } else if (old_mem->mem_type == TTM_PL_SYSTEM) { 736 else
644 if (nouveau_bo_move_flips(bo, evict, intr, no_wait, new_mem)) 737 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem);
645 return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
646 } else {
647 if (nouveau_bo_move_m2mf(bo, evict, no_wait, old_mem, new_mem))
648 return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
649 }
650 738
651 return 0; 739 if (!ret)
740 goto out;
741
742 /* Fallback to software copy. */
743 ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
744
745out:
746 if (ret)
747 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
748 else
749 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
750
751 return ret;
652} 752}
653 753
654static int 754static int
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 9aaa972f8822..343d718a9667 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -158,6 +158,8 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
158 return ret; 158 return ret;
159 } 159 }
160 160
161 nouveau_dma_pre_init(chan);
162
161 /* Locate channel's user control regs */ 163 /* Locate channel's user control regs */
162 if (dev_priv->card_type < NV_40) 164 if (dev_priv->card_type < NV_40)
163 user = NV03_USER(channel); 165 user = NV03_USER(channel);
@@ -235,47 +237,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
235 return 0; 237 return 0;
236} 238}
237 239
238int
239nouveau_channel_idle(struct nouveau_channel *chan)
240{
241 struct drm_device *dev = chan->dev;
242 struct drm_nouveau_private *dev_priv = dev->dev_private;
243 struct nouveau_engine *engine = &dev_priv->engine;
244 uint32_t caches;
245 int idle;
246
247 if (!chan) {
248 NV_ERROR(dev, "no channel...\n");
249 return 1;
250 }
251
252 caches = nv_rd32(dev, NV03_PFIFO_CACHES);
253 nv_wr32(dev, NV03_PFIFO_CACHES, caches & ~1);
254
255 if (engine->fifo.channel_id(dev) != chan->id) {
256 struct nouveau_gpuobj *ramfc =
257 chan->ramfc ? chan->ramfc->gpuobj : NULL;
258
259 if (!ramfc) {
260 NV_ERROR(dev, "No RAMFC for channel %d\n", chan->id);
261 return 1;
262 }
263
264 engine->instmem.prepare_access(dev, false);
265 if (nv_ro32(dev, ramfc, 0) != nv_ro32(dev, ramfc, 1))
266 idle = 0;
267 else
268 idle = 1;
269 engine->instmem.finish_access(dev);
270 } else {
271 idle = (nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET) ==
272 nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
273 }
274
275 nv_wr32(dev, NV03_PFIFO_CACHES, caches);
276 return idle;
277}
278
279/* stops a fifo */ 240/* stops a fifo */
280void 241void
281nouveau_channel_free(struct nouveau_channel *chan) 242nouveau_channel_free(struct nouveau_channel *chan)
@@ -414,7 +375,9 @@ nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
414 init->subchan[0].grclass = 0x0039; 375 init->subchan[0].grclass = 0x0039;
415 else 376 else
416 init->subchan[0].grclass = 0x5039; 377 init->subchan[0].grclass = 0x5039;
417 init->nr_subchan = 1; 378 init->subchan[1].handle = NvSw;
379 init->subchan[1].grclass = NV_SW;
380 init->nr_subchan = 2;
418 381
419 /* Named memory object area */ 382 /* Named memory object area */
420 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem, 383 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 032cf098fa1c..7e6d673f3a23 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -24,9 +24,12 @@
24 * 24 *
25 */ 25 */
26 26
27#include <acpi/button.h>
28
27#include "drmP.h" 29#include "drmP.h"
28#include "drm_edid.h" 30#include "drm_edid.h"
29#include "drm_crtc_helper.h" 31#include "drm_crtc_helper.h"
32
30#include "nouveau_reg.h" 33#include "nouveau_reg.h"
31#include "nouveau_drv.h" 34#include "nouveau_drv.h"
32#include "nouveau_encoder.h" 35#include "nouveau_encoder.h"
@@ -83,14 +86,16 @@ nouveau_encoder_connector_get(struct nouveau_encoder *encoder)
83static void 86static void
84nouveau_connector_destroy(struct drm_connector *drm_connector) 87nouveau_connector_destroy(struct drm_connector *drm_connector)
85{ 88{
86 struct nouveau_connector *connector = nouveau_connector(drm_connector); 89 struct nouveau_connector *nv_connector =
87 struct drm_device *dev = connector->base.dev; 90 nouveau_connector(drm_connector);
91 struct drm_device *dev = nv_connector->base.dev;
88 92
89 NV_DEBUG(dev, "\n"); 93 NV_DEBUG_KMS(dev, "\n");
90 94
91 if (!connector) 95 if (!nv_connector)
92 return; 96 return;
93 97
98 kfree(nv_connector->edid);
94 drm_sysfs_connector_remove(drm_connector); 99 drm_sysfs_connector_remove(drm_connector);
95 drm_connector_cleanup(drm_connector); 100 drm_connector_cleanup(drm_connector);
96 kfree(drm_connector); 101 kfree(drm_connector);
@@ -233,10 +238,21 @@ nouveau_connector_detect(struct drm_connector *connector)
233 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 238 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
234 nv_encoder = find_encoder_by_type(connector, OUTPUT_LVDS); 239 nv_encoder = find_encoder_by_type(connector, OUTPUT_LVDS);
235 if (nv_encoder && nv_connector->native_mode) { 240 if (nv_encoder && nv_connector->native_mode) {
241#ifdef CONFIG_ACPI
242 if (!nouveau_ignorelid && !acpi_lid_open())
243 return connector_status_disconnected;
244#endif
236 nouveau_connector_set_encoder(connector, nv_encoder); 245 nouveau_connector_set_encoder(connector, nv_encoder);
237 return connector_status_connected; 246 return connector_status_connected;
238 } 247 }
239 248
249 /* Cleanup the previous EDID block. */
250 if (nv_connector->edid) {
251 drm_mode_connector_update_edid_property(connector, NULL);
252 kfree(nv_connector->edid);
253 nv_connector->edid = NULL;
254 }
255
240 i2c = nouveau_connector_ddc_detect(connector, &nv_encoder); 256 i2c = nouveau_connector_ddc_detect(connector, &nv_encoder);
241 if (i2c) { 257 if (i2c) {
242 nouveau_connector_ddc_prepare(connector, &flags); 258 nouveau_connector_ddc_prepare(connector, &flags);
@@ -247,7 +263,7 @@ nouveau_connector_detect(struct drm_connector *connector)
247 if (!nv_connector->edid) { 263 if (!nv_connector->edid) {
248 NV_ERROR(dev, "DDC responded, but no EDID for %s\n", 264 NV_ERROR(dev, "DDC responded, but no EDID for %s\n",
249 drm_get_connector_name(connector)); 265 drm_get_connector_name(connector));
250 return connector_status_disconnected; 266 goto detect_analog;
251 } 267 }
252 268
253 if (nv_encoder->dcb->type == OUTPUT_DP && 269 if (nv_encoder->dcb->type == OUTPUT_DP &&
@@ -281,6 +297,7 @@ nouveau_connector_detect(struct drm_connector *connector)
281 return connector_status_connected; 297 return connector_status_connected;
282 } 298 }
283 299
300detect_analog:
284 nv_encoder = find_encoder_by_type(connector, OUTPUT_ANALOG); 301 nv_encoder = find_encoder_by_type(connector, OUTPUT_ANALOG);
285 if (!nv_encoder) 302 if (!nv_encoder)
286 nv_encoder = find_encoder_by_type(connector, OUTPUT_TV); 303 nv_encoder = find_encoder_by_type(connector, OUTPUT_TV);
@@ -420,7 +437,7 @@ nouveau_connector_native_mode(struct nouveau_connector *connector)
420 /* Use preferred mode if there is one.. */ 437 /* Use preferred mode if there is one.. */
421 list_for_each_entry(mode, &connector->base.probed_modes, head) { 438 list_for_each_entry(mode, &connector->base.probed_modes, head) {
422 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 439 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
423 NV_DEBUG(dev, "native mode from preferred\n"); 440 NV_DEBUG_KMS(dev, "native mode from preferred\n");
424 return drm_mode_duplicate(dev, mode); 441 return drm_mode_duplicate(dev, mode);
425 } 442 }
426 } 443 }
@@ -445,7 +462,7 @@ nouveau_connector_native_mode(struct nouveau_connector *connector)
445 largest = mode; 462 largest = mode;
446 } 463 }
447 464
448 NV_DEBUG(dev, "native mode from largest: %dx%d@%d\n", 465 NV_DEBUG_KMS(dev, "native mode from largest: %dx%d@%d\n",
449 high_w, high_h, high_v); 466 high_w, high_h, high_v);
450 return largest ? drm_mode_duplicate(dev, largest) : NULL; 467 return largest ? drm_mode_duplicate(dev, largest) : NULL;
451} 468}
@@ -687,8 +704,12 @@ nouveau_connector_create_lvds(struct drm_device *dev,
687 */ 704 */
688 if (!nv_connector->edid && !nv_connector->native_mode && 705 if (!nv_connector->edid && !nv_connector->native_mode &&
689 !dev_priv->VBIOS.pub.fp_no_ddc) { 706 !dev_priv->VBIOS.pub.fp_no_ddc) {
690 nv_connector->edid = 707 struct edid *edid =
691 (struct edid *)nouveau_bios_embedded_edid(dev); 708 (struct edid *)nouveau_bios_embedded_edid(dev);
709 if (edid) {
710 nv_connector->edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
711 *(nv_connector->edid) = *edid;
712 }
692 } 713 }
693 714
694 if (!nv_connector->edid) 715 if (!nv_connector->edid)
@@ -725,7 +746,7 @@ nouveau_connector_create(struct drm_device *dev, int index, int type)
725 struct drm_encoder *encoder; 746 struct drm_encoder *encoder;
726 int ret; 747 int ret;
727 748
728 NV_DEBUG(dev, "\n"); 749 NV_DEBUG_KMS(dev, "\n");
729 750
730 nv_connector = kzalloc(sizeof(*nv_connector), GFP_KERNEL); 751 nv_connector = kzalloc(sizeof(*nv_connector), GFP_KERNEL);
731 if (!nv_connector) 752 if (!nv_connector)
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c
index 703553687b20..50d9e67745af 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.c
@@ -29,12 +29,22 @@
29#include "nouveau_drv.h" 29#include "nouveau_drv.h"
30#include "nouveau_dma.h" 30#include "nouveau_dma.h"
31 31
32void
33nouveau_dma_pre_init(struct nouveau_channel *chan)
34{
35 chan->dma.max = (chan->pushbuf_bo->bo.mem.size >> 2) - 2;
36 chan->dma.put = 0;
37 chan->dma.cur = chan->dma.put;
38 chan->dma.free = chan->dma.max - chan->dma.cur;
39}
40
32int 41int
33nouveau_dma_init(struct nouveau_channel *chan) 42nouveau_dma_init(struct nouveau_channel *chan)
34{ 43{
35 struct drm_device *dev = chan->dev; 44 struct drm_device *dev = chan->dev;
36 struct drm_nouveau_private *dev_priv = dev->dev_private; 45 struct drm_nouveau_private *dev_priv = dev->dev_private;
37 struct nouveau_gpuobj *m2mf = NULL; 46 struct nouveau_gpuobj *m2mf = NULL;
47 struct nouveau_gpuobj *nvsw = NULL;
38 int ret, i; 48 int ret, i;
39 49
40 /* Create NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */ 50 /* Create NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */
@@ -47,6 +57,15 @@ nouveau_dma_init(struct nouveau_channel *chan)
47 if (ret) 57 if (ret)
48 return ret; 58 return ret;
49 59
60 /* Create an NV_SW object for various sync purposes */
61 ret = nouveau_gpuobj_sw_new(chan, NV_SW, &nvsw);
62 if (ret)
63 return ret;
64
65 ret = nouveau_gpuobj_ref_add(dev, chan, NvSw, nvsw, NULL);
66 if (ret)
67 return ret;
68
50 /* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */ 69 /* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */
51 ret = nouveau_notifier_alloc(chan, NvNotify0, 32, &chan->m2mf_ntfy); 70 ret = nouveau_notifier_alloc(chan, NvNotify0, 32, &chan->m2mf_ntfy);
52 if (ret) 71 if (ret)
@@ -64,12 +83,6 @@ nouveau_dma_init(struct nouveau_channel *chan)
64 return ret; 83 return ret;
65 } 84 }
66 85
67 /* Initialise DMA vars */
68 chan->dma.max = (chan->pushbuf_bo->bo.mem.size >> 2) - 2;
69 chan->dma.put = 0;
70 chan->dma.cur = chan->dma.put;
71 chan->dma.free = chan->dma.max - chan->dma.cur;
72
73 /* Insert NOPS for NOUVEAU_DMA_SKIPS */ 86 /* Insert NOPS for NOUVEAU_DMA_SKIPS */
74 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); 87 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
75 if (ret) 88 if (ret)
@@ -87,6 +100,13 @@ nouveau_dma_init(struct nouveau_channel *chan)
87 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1); 100 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
88 OUT_RING(chan, NvNotify0); 101 OUT_RING(chan, NvNotify0);
89 102
103 /* Initialise NV_SW */
104 ret = RING_SPACE(chan, 2);
105 if (ret)
106 return ret;
107 BEGIN_RING(chan, NvSubSw, 0, 1);
108 OUT_RING(chan, NvSw);
109
90 /* Sit back and pray the channel works.. */ 110 /* Sit back and pray the channel works.. */
91 FIRE_RING(chan); 111 FIRE_RING(chan);
92 112
@@ -106,47 +126,52 @@ OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords)
106 chan->dma.cur += nr_dwords; 126 chan->dma.cur += nr_dwords;
107} 127}
108 128
109static inline bool 129/* Fetch and adjust GPU GET pointer
110READ_GET(struct nouveau_channel *chan, uint32_t *get) 130 *
131 * Returns:
132 * value >= 0, the adjusted GET pointer
133 * -EINVAL if GET pointer currently outside main push buffer
134 * -EBUSY if timeout exceeded
135 */
136static inline int
137READ_GET(struct nouveau_channel *chan, uint32_t *prev_get, uint32_t *timeout)
111{ 138{
112 uint32_t val; 139 uint32_t val;
113 140
114 val = nvchan_rd32(chan, chan->user_get); 141 val = nvchan_rd32(chan, chan->user_get);
115 if (val < chan->pushbuf_base || 142
116 val >= chan->pushbuf_base + chan->pushbuf_bo->bo.mem.size) { 143 /* reset counter as long as GET is still advancing, this is
117 /* meaningless to dma_wait() except to know whether the 144 * to avoid misdetecting a GPU lockup if the GPU happens to
118 * GPU has stalled or not 145 * just be processing an operation that takes a long time
119 */ 146 */
120 *get = val; 147 if (val != *prev_get) {
121 return false; 148 *prev_get = val;
149 *timeout = 0;
150 }
151
152 if ((++*timeout & 0xff) == 0) {
153 DRM_UDELAY(1);
154 if (*timeout > 100000)
155 return -EBUSY;
122 } 156 }
123 157
124 *get = (val - chan->pushbuf_base) >> 2; 158 if (val < chan->pushbuf_base ||
125 return true; 159 val > chan->pushbuf_base + (chan->dma.max << 2))
160 return -EINVAL;
161
162 return (val - chan->pushbuf_base) >> 2;
126} 163}
127 164
128int 165int
129nouveau_dma_wait(struct nouveau_channel *chan, int size) 166nouveau_dma_wait(struct nouveau_channel *chan, int size)
130{ 167{
131 uint32_t get, prev_get = 0, cnt = 0; 168 uint32_t prev_get = 0, cnt = 0;
132 bool get_valid; 169 int get;
133 170
134 while (chan->dma.free < size) { 171 while (chan->dma.free < size) {
135 /* reset counter as long as GET is still advancing, this is 172 get = READ_GET(chan, &prev_get, &cnt);
136 * to avoid misdetecting a GPU lockup if the GPU happens to 173 if (unlikely(get == -EBUSY))
137 * just be processing an operation that takes a long time 174 return -EBUSY;
138 */
139 get_valid = READ_GET(chan, &get);
140 if (get != prev_get) {
141 prev_get = get;
142 cnt = 0;
143 }
144
145 if ((++cnt & 0xff) == 0) {
146 DRM_UDELAY(1);
147 if (cnt > 100000)
148 return -EBUSY;
149 }
150 175
151 /* loop until we have a usable GET pointer. the value 176 /* loop until we have a usable GET pointer. the value
152 * we read from the GPU may be outside the main ring if 177 * we read from the GPU may be outside the main ring if
@@ -157,7 +182,7 @@ nouveau_dma_wait(struct nouveau_channel *chan, int size)
157 * from the SKIPS area, so the code below doesn't have to deal 182 * from the SKIPS area, so the code below doesn't have to deal
158 * with some fun corner cases. 183 * with some fun corner cases.
159 */ 184 */
160 if (!get_valid || get < NOUVEAU_DMA_SKIPS) 185 if (unlikely(get == -EINVAL) || get < NOUVEAU_DMA_SKIPS)
161 continue; 186 continue;
162 187
163 if (get <= chan->dma.cur) { 188 if (get <= chan->dma.cur) {
@@ -183,6 +208,19 @@ nouveau_dma_wait(struct nouveau_channel *chan, int size)
183 * after processing the currently pending commands. 208 * after processing the currently pending commands.
184 */ 209 */
185 OUT_RING(chan, chan->pushbuf_base | 0x20000000); 210 OUT_RING(chan, chan->pushbuf_base | 0x20000000);
211
212 /* wait for GET to depart from the skips area.
213 * prevents writing GET==PUT and causing a race
214 * condition that causes us to think the GPU is
215 * idle when it's not.
216 */
217 do {
218 get = READ_GET(chan, &prev_get, &cnt);
219 if (unlikely(get == -EBUSY))
220 return -EBUSY;
221 if (unlikely(get == -EINVAL))
222 continue;
223 } while (get <= NOUVEAU_DMA_SKIPS);
186 WRITE_PUT(NOUVEAU_DMA_SKIPS); 224 WRITE_PUT(NOUVEAU_DMA_SKIPS);
187 225
188 /* we're now submitting commands at the start of 226 /* we're now submitting commands at the start of
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h
index 04e85d8f757e..dabfd655f93e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.h
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.h
@@ -46,10 +46,11 @@
46/* Hardcoded object assignments to subchannels (subchannel id). */ 46/* Hardcoded object assignments to subchannels (subchannel id). */
47enum { 47enum {
48 NvSubM2MF = 0, 48 NvSubM2MF = 0,
49 NvSub2D = 1, 49 NvSubSw = 1,
50 NvSubCtxSurf2D = 1, 50 NvSub2D = 2,
51 NvSubGdiRect = 2, 51 NvSubCtxSurf2D = 2,
52 NvSubImageBlit = 3 52 NvSubGdiRect = 3,
53 NvSubImageBlit = 4
53}; 54};
54 55
55/* Object handles. */ 56/* Object handles. */
@@ -67,6 +68,7 @@ enum {
67 NvClipRect = 0x8000000b, 68 NvClipRect = 0x8000000b,
68 NvGdiRect = 0x8000000c, 69 NvGdiRect = 0x8000000c,
69 NvImageBlit = 0x8000000d, 70 NvImageBlit = 0x8000000d,
71 NvSw = 0x8000000e,
70 72
71 /* G80+ display objects */ 73 /* G80+ display objects */
72 NvEvoVRAM = 0x01000000, 74 NvEvoVRAM = 0x01000000,
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c
index de61f4640e12..dd4937224220 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -187,7 +187,7 @@ nouveau_dp_link_train_adjust(struct drm_encoder *encoder, uint8_t *config)
187 if (ret) 187 if (ret)
188 return false; 188 return false;
189 189
190 NV_DEBUG(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]); 190 NV_DEBUG_KMS(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]);
191 191
192 /* Keep all lanes at the same level.. */ 192 /* Keep all lanes at the same level.. */
193 for (i = 0; i < nv_encoder->dp.link_nr; i++) { 193 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
@@ -228,7 +228,7 @@ nouveau_dp_link_train_commit(struct drm_encoder *encoder, uint8_t *config)
228 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1); 228 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
229 int dpe_headerlen, ret, i; 229 int dpe_headerlen, ret, i;
230 230
231 NV_DEBUG(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n", 231 NV_DEBUG_KMS(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n",
232 config[0], config[1], config[2], config[3]); 232 config[0], config[1], config[2], config[3]);
233 233
234 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen); 234 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
@@ -276,12 +276,12 @@ nouveau_dp_link_train(struct drm_encoder *encoder)
276 bool cr_done, cr_max_vs, eq_done; 276 bool cr_done, cr_max_vs, eq_done;
277 int ret = 0, i, tries, voltage; 277 int ret = 0, i, tries, voltage;
278 278
279 NV_DEBUG(dev, "link training!!\n"); 279 NV_DEBUG_KMS(dev, "link training!!\n");
280train: 280train:
281 cr_done = eq_done = false; 281 cr_done = eq_done = false;
282 282
283 /* set link configuration */ 283 /* set link configuration */
284 NV_DEBUG(dev, "\tbegin train: bw %d, lanes %d\n", 284 NV_DEBUG_KMS(dev, "\tbegin train: bw %d, lanes %d\n",
285 nv_encoder->dp.link_bw, nv_encoder->dp.link_nr); 285 nv_encoder->dp.link_bw, nv_encoder->dp.link_nr);
286 286
287 ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw); 287 ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw);
@@ -297,7 +297,7 @@ train:
297 return false; 297 return false;
298 298
299 /* clock recovery */ 299 /* clock recovery */
300 NV_DEBUG(dev, "\tbegin cr\n"); 300 NV_DEBUG_KMS(dev, "\tbegin cr\n");
301 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1); 301 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1);
302 if (ret) 302 if (ret)
303 goto stop; 303 goto stop;
@@ -314,7 +314,7 @@ train:
314 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2); 314 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2);
315 if (ret) 315 if (ret)
316 break; 316 break;
317 NV_DEBUG(dev, "\t\tstatus: 0x%02x 0x%02x\n", 317 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
318 status[0], status[1]); 318 status[0], status[1]);
319 319
320 cr_done = true; 320 cr_done = true;
@@ -346,7 +346,7 @@ train:
346 goto stop; 346 goto stop;
347 347
348 /* channel equalisation */ 348 /* channel equalisation */
349 NV_DEBUG(dev, "\tbegin eq\n"); 349 NV_DEBUG_KMS(dev, "\tbegin eq\n");
350 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2); 350 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2);
351 if (ret) 351 if (ret)
352 goto stop; 352 goto stop;
@@ -357,7 +357,7 @@ train:
357 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3); 357 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3);
358 if (ret) 358 if (ret)
359 break; 359 break;
360 NV_DEBUG(dev, "\t\tstatus: 0x%02x 0x%02x\n", 360 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
361 status[0], status[1]); 361 status[0], status[1]);
362 362
363 eq_done = true; 363 eq_done = true;
@@ -395,9 +395,9 @@ stop:
395 395
396 /* retry at a lower setting, if possible */ 396 /* retry at a lower setting, if possible */
397 if (!ret && !(eq_done && cr_done)) { 397 if (!ret && !(eq_done && cr_done)) {
398 NV_DEBUG(dev, "\twe failed\n"); 398 NV_DEBUG_KMS(dev, "\twe failed\n");
399 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) { 399 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) {
400 NV_DEBUG(dev, "retry link training at low rate\n"); 400 NV_DEBUG_KMS(dev, "retry link training at low rate\n");
401 nv_encoder->dp.link_bw = DP_LINK_BW_1_62; 401 nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
402 goto train; 402 goto train;
403 } 403 }
@@ -418,7 +418,7 @@ nouveau_dp_detect(struct drm_encoder *encoder)
418 if (ret) 418 if (ret)
419 return false; 419 return false;
420 420
421 NV_DEBUG(dev, "encoder: link_bw %d, link_nr %d\n" 421 NV_DEBUG_KMS(dev, "encoder: link_bw %d, link_nr %d\n"
422 "display: link_bw %d, link_nr %d version 0x%02x\n", 422 "display: link_bw %d, link_nr %d version 0x%02x\n",
423 nv_encoder->dcb->dpconf.link_bw, 423 nv_encoder->dcb->dpconf.link_bw,
424 nv_encoder->dcb->dpconf.link_nr, 424 nv_encoder->dcb->dpconf.link_nr,
@@ -446,7 +446,7 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
446 uint32_t tmp, ctrl, stat = 0, data32[4] = {}; 446 uint32_t tmp, ctrl, stat = 0, data32[4] = {};
447 int ret = 0, i, index = auxch->rd; 447 int ret = 0, i, index = auxch->rd;
448 448
449 NV_DEBUG(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr); 449 NV_DEBUG_KMS(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr);
450 450
451 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd)); 451 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
452 nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp | 0x00100000); 452 nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp | 0x00100000);
@@ -472,7 +472,7 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
472 if (!(cmd & 1)) { 472 if (!(cmd & 1)) {
473 memcpy(data32, data, data_nr); 473 memcpy(data32, data, data_nr);
474 for (i = 0; i < 4; i++) { 474 for (i = 0; i < 4; i++) {
475 NV_DEBUG(dev, "wr %d: 0x%08x\n", i, data32[i]); 475 NV_DEBUG_KMS(dev, "wr %d: 0x%08x\n", i, data32[i]);
476 nv_wr32(dev, NV50_AUXCH_DATA_OUT(index, i), data32[i]); 476 nv_wr32(dev, NV50_AUXCH_DATA_OUT(index, i), data32[i]);
477 } 477 }
478 } 478 }
@@ -490,7 +490,8 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
490 if (!nv_wait(NV50_AUXCH_CTRL(index), 0x00010000, 0x00000000)) { 490 if (!nv_wait(NV50_AUXCH_CTRL(index), 0x00010000, 0x00000000)) {
491 NV_ERROR(dev, "expected bit 16 == 0, got 0x%08x\n", 491 NV_ERROR(dev, "expected bit 16 == 0, got 0x%08x\n",
492 nv_rd32(dev, NV50_AUXCH_CTRL(index))); 492 nv_rd32(dev, NV50_AUXCH_CTRL(index)));
493 return -EBUSY; 493 ret = -EBUSY;
494 goto out;
494 } 495 }
495 496
496 udelay(400); 497 udelay(400);
@@ -501,10 +502,15 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
501 break; 502 break;
502 } 503 }
503 504
505 if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) {
506 ret = -EREMOTEIO;
507 goto out;
508 }
509
504 if (cmd & 1) { 510 if (cmd & 1) {
505 for (i = 0; i < 4; i++) { 511 for (i = 0; i < 4; i++) {
506 data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i)); 512 data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i));
507 NV_DEBUG(dev, "rd %d: 0x%08x\n", i, data32[i]); 513 NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]);
508 } 514 }
509 memcpy(data, data32, data_nr); 515 memcpy(data, data32, data_nr);
510 } 516 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c
index 3f943c01e995..343ab7f17ccc 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.c
@@ -35,6 +35,10 @@
35 35
36#include "drm_pciids.h" 36#include "drm_pciids.h"
37 37
38MODULE_PARM_DESC(ctxfw, "Use external firmware blob for grctx init (NV40)");
39int nouveau_ctxfw = 0;
40module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
41
38MODULE_PARM_DESC(noagp, "Disable AGP"); 42MODULE_PARM_DESC(noagp, "Disable AGP");
39int nouveau_noagp; 43int nouveau_noagp;
40module_param_named(noagp, nouveau_noagp, int, 0400); 44module_param_named(noagp, nouveau_noagp, int, 0400);
@@ -67,6 +71,10 @@ MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
67int nouveau_uscript_tmds = -1; 71int nouveau_uscript_tmds = -1;
68module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400); 72module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
69 73
74MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
75int nouveau_ignorelid = 0;
76module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
77
70MODULE_PARM_DESC(tv_norm, "Default TV norm.\n" 78MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
71 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n" 79 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
72 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n" 80 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
@@ -273,7 +281,7 @@ nouveau_pci_resume(struct pci_dev *pdev)
273 281
274 for (i = 0; i < dev_priv->engine.fifo.channels; i++) { 282 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
275 chan = dev_priv->fifos[i]; 283 chan = dev_priv->fifos[i];
276 if (!chan) 284 if (!chan || !chan->pushbuf_bo)
277 continue; 285 continue;
278 286
279 for (j = 0; j < NOUVEAU_DMA_SKIPS; j++) 287 for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 88b4c7b77e7f..6b9690418bc7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -54,15 +54,24 @@ struct nouveau_fpriv {
54#include "nouveau_drm.h" 54#include "nouveau_drm.h"
55#include "nouveau_reg.h" 55#include "nouveau_reg.h"
56#include "nouveau_bios.h" 56#include "nouveau_bios.h"
57struct nouveau_grctx;
57 58
58#define MAX_NUM_DCB_ENTRIES 16 59#define MAX_NUM_DCB_ENTRIES 16
59 60
60#define NOUVEAU_MAX_CHANNEL_NR 128 61#define NOUVEAU_MAX_CHANNEL_NR 128
62#define NOUVEAU_MAX_TILE_NR 15
61 63
62#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
63#define NV50_VM_BLOCK (512*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL)
64#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
65 67
68struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73};
74
66struct nouveau_bo { 75struct nouveau_bo {
67 struct ttm_buffer_object bo; 76 struct ttm_buffer_object bo;
68 struct ttm_placement placement; 77 struct ttm_placement placement;
@@ -82,6 +91,7 @@ struct nouveau_bo {
82 91
83 uint32_t tile_mode; 92 uint32_t tile_mode;
84 uint32_t tile_flags; 93 uint32_t tile_flags;
94 struct nouveau_tile_reg *tile;
85 95
86 struct drm_gem_object *gem; 96 struct drm_gem_object *gem;
87 struct drm_file *cpu_filp; 97 struct drm_file *cpu_filp;
@@ -276,8 +286,13 @@ struct nouveau_timer_engine {
276}; 286};
277 287
278struct nouveau_fb_engine { 288struct nouveau_fb_engine {
289 int num_tiles;
290
279 int (*init)(struct drm_device *dev); 291 int (*init)(struct drm_device *dev);
280 void (*takedown)(struct drm_device *dev); 292 void (*takedown)(struct drm_device *dev);
293
294 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
295 uint32_t size, uint32_t pitch);
281}; 296};
282 297
283struct nouveau_fifo_engine { 298struct nouveau_fifo_engine {
@@ -291,6 +306,8 @@ struct nouveau_fifo_engine {
291 void (*disable)(struct drm_device *); 306 void (*disable)(struct drm_device *);
292 void (*enable)(struct drm_device *); 307 void (*enable)(struct drm_device *);
293 bool (*reassign)(struct drm_device *, bool enable); 308 bool (*reassign)(struct drm_device *, bool enable);
309 bool (*cache_flush)(struct drm_device *dev);
310 bool (*cache_pull)(struct drm_device *dev, bool enable);
294 311
295 int (*channel_id)(struct drm_device *); 312 int (*channel_id)(struct drm_device *);
296 313
@@ -317,6 +334,7 @@ struct nouveau_pgraph_engine {
317 bool accel_blocked; 334 bool accel_blocked;
318 void *ctxprog; 335 void *ctxprog;
319 void *ctxvals; 336 void *ctxvals;
337 int grctx_size;
320 338
321 int (*init)(struct drm_device *); 339 int (*init)(struct drm_device *);
322 void (*takedown)(struct drm_device *); 340 void (*takedown)(struct drm_device *);
@@ -328,6 +346,9 @@ struct nouveau_pgraph_engine {
328 void (*destroy_context)(struct nouveau_channel *); 346 void (*destroy_context)(struct nouveau_channel *);
329 int (*load_context)(struct nouveau_channel *); 347 int (*load_context)(struct nouveau_channel *);
330 int (*unload_context)(struct drm_device *); 348 int (*unload_context)(struct drm_device *);
349
350 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
351 uint32_t size, uint32_t pitch);
331}; 352};
332 353
333struct nouveau_engine { 354struct nouveau_engine {
@@ -488,6 +509,8 @@ struct drm_nouveau_private {
488 void __iomem *ramin; 509 void __iomem *ramin;
489 uint32_t ramin_size; 510 uint32_t ramin_size;
490 511
512 struct nouveau_bo *vga_ram;
513
491 struct workqueue_struct *wq; 514 struct workqueue_struct *wq;
492 struct work_struct irq_work; 515 struct work_struct irq_work;
493 516
@@ -546,6 +569,12 @@ struct drm_nouveau_private {
546 unsigned long sg_handle; 569 unsigned long sg_handle;
547 } gart_info; 570 } gart_info;
548 571
572 /* nv10-nv40 tiling regions */
573 struct {
574 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
575 spinlock_t lock;
576 } tile;
577
549 /* G8x/G9x virtual address space */ 578 /* G8x/G9x virtual address space */
550 uint64_t vm_gart_base; 579 uint64_t vm_gart_base;
551 uint64_t vm_gart_size; 580 uint64_t vm_gart_size;
@@ -647,6 +676,8 @@ extern int nouveau_fbpercrtc;
647extern char *nouveau_tv_norm; 676extern char *nouveau_tv_norm;
648extern int nouveau_reg_debug; 677extern int nouveau_reg_debug;
649extern char *nouveau_vbios; 678extern char *nouveau_vbios;
679extern int nouveau_ctxfw;
680extern int nouveau_ignorelid;
650 681
651/* nouveau_state.c */ 682/* nouveau_state.c */
652extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 683extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
@@ -682,6 +713,13 @@ extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
682extern int nouveau_mem_init(struct drm_device *); 713extern int nouveau_mem_init(struct drm_device *);
683extern int nouveau_mem_init_agp(struct drm_device *); 714extern int nouveau_mem_init_agp(struct drm_device *);
684extern void nouveau_mem_close(struct drm_device *); 715extern void nouveau_mem_close(struct drm_device *);
716extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
717 uint32_t addr,
718 uint32_t size,
719 uint32_t pitch);
720extern void nv10_mem_expire_tiling(struct drm_device *dev,
721 struct nouveau_tile_reg *tile,
722 struct nouveau_fence *fence);
685extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 723extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
686 uint32_t size, uint32_t flags, 724 uint32_t size, uint32_t flags,
687 uint64_t phys); 725 uint64_t phys);
@@ -710,7 +748,6 @@ extern int nouveau_channel_alloc(struct drm_device *dev,
710 struct drm_file *file_priv, 748 struct drm_file *file_priv,
711 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 749 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
712extern void nouveau_channel_free(struct nouveau_channel *); 750extern void nouveau_channel_free(struct nouveau_channel *);
713extern int nouveau_channel_idle(struct nouveau_channel *chan);
714 751
715/* nouveau_object.c */ 752/* nouveau_object.c */
716extern int nouveau_gpuobj_early_init(struct drm_device *); 753extern int nouveau_gpuobj_early_init(struct drm_device *);
@@ -753,6 +790,8 @@ extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
753 uint32_t *o_ret); 790 uint32_t *o_ret);
754extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 791extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
755 struct nouveau_gpuobj **); 792 struct nouveau_gpuobj **);
793extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
794 struct nouveau_gpuobj **);
756extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 795extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
757 struct drm_file *); 796 struct drm_file *);
758extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 797extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
@@ -801,6 +840,7 @@ nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
801#endif 840#endif
802 841
803/* nouveau_dma.c */ 842/* nouveau_dma.c */
843extern void nouveau_dma_pre_init(struct nouveau_channel *);
804extern int nouveau_dma_init(struct nouveau_channel *); 844extern int nouveau_dma_init(struct nouveau_channel *);
805extern int nouveau_dma_wait(struct nouveau_channel *, int size); 845extern int nouveau_dma_wait(struct nouveau_channel *, int size);
806 846
@@ -876,16 +916,22 @@ extern void nv04_fb_takedown(struct drm_device *);
876/* nv10_fb.c */ 916/* nv10_fb.c */
877extern int nv10_fb_init(struct drm_device *); 917extern int nv10_fb_init(struct drm_device *);
878extern void nv10_fb_takedown(struct drm_device *); 918extern void nv10_fb_takedown(struct drm_device *);
919extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
920 uint32_t, uint32_t);
879 921
880/* nv40_fb.c */ 922/* nv40_fb.c */
881extern int nv40_fb_init(struct drm_device *); 923extern int nv40_fb_init(struct drm_device *);
882extern void nv40_fb_takedown(struct drm_device *); 924extern void nv40_fb_takedown(struct drm_device *);
925extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
926 uint32_t, uint32_t);
883 927
884/* nv04_fifo.c */ 928/* nv04_fifo.c */
885extern int nv04_fifo_init(struct drm_device *); 929extern int nv04_fifo_init(struct drm_device *);
886extern void nv04_fifo_disable(struct drm_device *); 930extern void nv04_fifo_disable(struct drm_device *);
887extern void nv04_fifo_enable(struct drm_device *); 931extern void nv04_fifo_enable(struct drm_device *);
888extern bool nv04_fifo_reassign(struct drm_device *, bool); 932extern bool nv04_fifo_reassign(struct drm_device *, bool);
933extern bool nv04_fifo_cache_flush(struct drm_device *);
934extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
889extern int nv04_fifo_channel_id(struct drm_device *); 935extern int nv04_fifo_channel_id(struct drm_device *);
890extern int nv04_fifo_create_context(struct nouveau_channel *); 936extern int nv04_fifo_create_context(struct nouveau_channel *);
891extern void nv04_fifo_destroy_context(struct nouveau_channel *); 937extern void nv04_fifo_destroy_context(struct nouveau_channel *);
@@ -938,6 +984,8 @@ extern void nv10_graph_destroy_context(struct nouveau_channel *);
938extern int nv10_graph_load_context(struct nouveau_channel *); 984extern int nv10_graph_load_context(struct nouveau_channel *);
939extern int nv10_graph_unload_context(struct drm_device *); 985extern int nv10_graph_unload_context(struct drm_device *);
940extern void nv10_graph_context_switch(struct drm_device *); 986extern void nv10_graph_context_switch(struct drm_device *);
987extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
988 uint32_t, uint32_t);
941 989
942/* nv20_graph.c */ 990/* nv20_graph.c */
943extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 991extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
@@ -949,6 +997,8 @@ extern int nv20_graph_unload_context(struct drm_device *);
949extern int nv20_graph_init(struct drm_device *); 997extern int nv20_graph_init(struct drm_device *);
950extern void nv20_graph_takedown(struct drm_device *); 998extern void nv20_graph_takedown(struct drm_device *);
951extern int nv30_graph_init(struct drm_device *); 999extern int nv30_graph_init(struct drm_device *);
1000extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1001 uint32_t, uint32_t);
952 1002
953/* nv40_graph.c */ 1003/* nv40_graph.c */
954extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1004extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
@@ -959,9 +1009,9 @@ extern int nv40_graph_create_context(struct nouveau_channel *);
959extern void nv40_graph_destroy_context(struct nouveau_channel *); 1009extern void nv40_graph_destroy_context(struct nouveau_channel *);
960extern int nv40_graph_load_context(struct nouveau_channel *); 1010extern int nv40_graph_load_context(struct nouveau_channel *);
961extern int nv40_graph_unload_context(struct drm_device *); 1011extern int nv40_graph_unload_context(struct drm_device *);
962extern int nv40_grctx_init(struct drm_device *); 1012extern void nv40_grctx_init(struct nouveau_grctx *);
963extern void nv40_grctx_fini(struct drm_device *); 1013extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
964extern void nv40_grctx_vals_load(struct drm_device *, struct nouveau_gpuobj *); 1014 uint32_t, uint32_t);
965 1015
966/* nv50_graph.c */ 1016/* nv50_graph.c */
967extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1017extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
@@ -975,6 +1025,12 @@ extern int nv50_graph_load_context(struct nouveau_channel *);
975extern int nv50_graph_unload_context(struct drm_device *); 1025extern int nv50_graph_unload_context(struct drm_device *);
976extern void nv50_graph_context_switch(struct drm_device *); 1026extern void nv50_graph_context_switch(struct drm_device *);
977 1027
1028/* nouveau_grctx.c */
1029extern int nouveau_grctx_prog_load(struct drm_device *);
1030extern void nouveau_grctx_vals_load(struct drm_device *,
1031 struct nouveau_gpuobj *);
1032extern void nouveau_grctx_fini(struct drm_device *);
1033
978/* nv04_instmem.c */ 1034/* nv04_instmem.c */
979extern int nv04_instmem_init(struct drm_device *); 1035extern int nv04_instmem_init(struct drm_device *);
980extern void nv04_instmem_takedown(struct drm_device *); 1036extern void nv04_instmem_takedown(struct drm_device *);
@@ -1023,8 +1079,7 @@ extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1023 1079
1024/* nv04_dac.c */ 1080/* nv04_dac.c */
1025extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry); 1081extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry);
1026extern enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder, 1082extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1027 struct drm_connector *connector);
1028extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1083extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1029extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1084extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1030 1085
@@ -1042,9 +1097,6 @@ extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1042 1097
1043/* nv17_tv.c */ 1098/* nv17_tv.c */
1044extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry); 1099extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1045extern enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder,
1046 struct drm_connector *connector,
1047 uint32_t pin_mask);
1048 1100
1049/* nv04_display.c */ 1101/* nv04_display.c */
1050extern int nv04_display_create(struct drm_device *); 1102extern int nv04_display_create(struct drm_device *);
@@ -1207,14 +1259,24 @@ static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1207 pci_name(d->pdev), ##arg) 1259 pci_name(d->pdev), ##arg)
1208#ifndef NV_DEBUG_NOTRACE 1260#ifndef NV_DEBUG_NOTRACE
1209#define NV_DEBUG(d, fmt, arg...) do { \ 1261#define NV_DEBUG(d, fmt, arg...) do { \
1210 if (drm_debug) { \ 1262 if (drm_debug & DRM_UT_DRIVER) { \
1263 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1264 __LINE__, ##arg); \
1265 } \
1266} while (0)
1267#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1268 if (drm_debug & DRM_UT_KMS) { \
1211 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1269 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1212 __LINE__, ##arg); \ 1270 __LINE__, ##arg); \
1213 } \ 1271 } \
1214} while (0) 1272} while (0)
1215#else 1273#else
1216#define NV_DEBUG(d, fmt, arg...) do { \ 1274#define NV_DEBUG(d, fmt, arg...) do { \
1217 if (drm_debug) \ 1275 if (drm_debug & DRM_UT_DRIVER) \
1276 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1277} while (0)
1278#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1279 if (drm_debug & DRM_UT_KMS) \
1218 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1280 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1219} while (0) 1281} while (0)
1220#endif 1282#endif
@@ -1273,14 +1335,14 @@ nv_two_reg_pll(struct drm_device *dev)
1273 return false; 1335 return false;
1274} 1336}
1275 1337
1276#define NV50_NVSW 0x0000506e 1338#define NV_SW 0x0000506e
1277#define NV50_NVSW_DMA_SEMAPHORE 0x00000060 1339#define NV_SW_DMA_SEMAPHORE 0x00000060
1278#define NV50_NVSW_SEMAPHORE_OFFSET 0x00000064 1340#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1279#define NV50_NVSW_SEMAPHORE_ACQUIRE 0x00000068 1341#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1280#define NV50_NVSW_SEMAPHORE_RELEASE 0x0000006c 1342#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1281#define NV50_NVSW_DMA_VBLSEM 0x0000018c 1343#define NV_SW_DMA_VBLSEM 0x0000018c
1282#define NV50_NVSW_VBLSEM_OFFSET 0x00000400 1344#define NV_SW_VBLSEM_OFFSET 0x00000400
1283#define NV50_NVSW_VBLSEM_RELEASE_VALUE 0x00000404 1345#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1284#define NV50_NVSW_VBLSEM_RELEASE 0x00000408 1346#define NV_SW_VBLSEM_RELEASE 0x00000408
1285 1347
1286#endif /* __NOUVEAU_DRV_H__ */ 1348#endif /* __NOUVEAU_DRV_H__ */
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 36e8c5e4503a..0b05c869e0e7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -58,14 +58,13 @@ nouveau_fbcon_sync(struct fb_info *info)
58 struct nouveau_channel *chan = dev_priv->channel; 58 struct nouveau_channel *chan = dev_priv->channel;
59 int ret, i; 59 int ret, i;
60 60
61 if (!chan->accel_done || 61 if (!chan || !chan->accel_done ||
62 info->state != FBINFO_STATE_RUNNING || 62 info->state != FBINFO_STATE_RUNNING ||
63 info->flags & FBINFO_HWACCEL_DISABLED) 63 info->flags & FBINFO_HWACCEL_DISABLED)
64 return 0; 64 return 0;
65 65
66 if (RING_SPACE(chan, 4)) { 66 if (RING_SPACE(chan, 4)) {
67 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 67 nouveau_fbcon_gpu_lockup(info);
68 info->flags |= FBINFO_HWACCEL_DISABLED;
69 return 0; 68 return 0;
70 } 69 }
71 70
@@ -86,8 +85,7 @@ nouveau_fbcon_sync(struct fb_info *info)
86 } 85 }
87 86
88 if (ret) { 87 if (ret) {
89 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 88 nouveau_fbcon_gpu_lockup(info);
90 info->flags |= FBINFO_HWACCEL_DISABLED;
91 return 0; 89 return 0;
92 } 90 }
93 91
@@ -212,11 +210,11 @@ nouveau_fbcon_create(struct drm_device *dev, uint32_t fb_width,
212 210
213 mode_cmd.bpp = surface_bpp; 211 mode_cmd.bpp = surface_bpp;
214 mode_cmd.pitch = mode_cmd.width * (mode_cmd.bpp >> 3); 212 mode_cmd.pitch = mode_cmd.width * (mode_cmd.bpp >> 3);
215 mode_cmd.pitch = ALIGN(mode_cmd.pitch, 256); 213 mode_cmd.pitch = roundup(mode_cmd.pitch, 256);
216 mode_cmd.depth = surface_depth; 214 mode_cmd.depth = surface_depth;
217 215
218 size = mode_cmd.pitch * mode_cmd.height; 216 size = mode_cmd.pitch * mode_cmd.height;
219 size = ALIGN(size, PAGE_SIZE); 217 size = roundup(size, PAGE_SIZE);
220 218
221 ret = nouveau_gem_new(dev, dev_priv->channel, size, 0, TTM_PL_FLAG_VRAM, 219 ret = nouveau_gem_new(dev, dev_priv->channel, size, 0, TTM_PL_FLAG_VRAM,
222 0, 0x0000, false, true, &nvbo); 220 0, 0x0000, false, true, &nvbo);
@@ -318,14 +316,16 @@ nouveau_fbcon_create(struct drm_device *dev, uint32_t fb_width,
318 par->nouveau_fb = nouveau_fb; 316 par->nouveau_fb = nouveau_fb;
319 par->dev = dev; 317 par->dev = dev;
320 318
321 switch (dev_priv->card_type) { 319 if (dev_priv->channel) {
322 case NV_50: 320 switch (dev_priv->card_type) {
323 nv50_fbcon_accel_init(info); 321 case NV_50:
324 break; 322 nv50_fbcon_accel_init(info);
325 default: 323 break;
326 nv04_fbcon_accel_init(info); 324 default:
327 break; 325 nv04_fbcon_accel_init(info);
328 }; 326 break;
327 };
328 }
329 329
330 nouveau_fbcon_zfill(dev); 330 nouveau_fbcon_zfill(dev);
331 331
@@ -347,7 +347,7 @@ out:
347int 347int
348nouveau_fbcon_probe(struct drm_device *dev) 348nouveau_fbcon_probe(struct drm_device *dev)
349{ 349{
350 NV_DEBUG(dev, "\n"); 350 NV_DEBUG_KMS(dev, "\n");
351 351
352 return drm_fb_helper_single_fb_probe(dev, 32, nouveau_fbcon_create); 352 return drm_fb_helper_single_fb_probe(dev, 32, nouveau_fbcon_create);
353} 353}
@@ -378,3 +378,12 @@ nouveau_fbcon_remove(struct drm_device *dev, struct drm_framebuffer *fb)
378 378
379 return 0; 379 return 0;
380} 380}
381
382void nouveau_fbcon_gpu_lockup(struct fb_info *info)
383{
384 struct nouveau_fbcon_par *par = info->par;
385 struct drm_device *dev = par->dev;
386
387 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
388 info->flags |= FBINFO_HWACCEL_DISABLED;
389}
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.h b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
index 8531140fedbc..462e0b87b4bd 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.h
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
@@ -43,5 +43,6 @@ void nouveau_fbcon_zfill(struct drm_device *dev);
43int nv04_fbcon_accel_init(struct fb_info *info); 43int nv04_fbcon_accel_init(struct fb_info *info);
44int nv50_fbcon_accel_init(struct fb_info *info); 44int nv50_fbcon_accel_init(struct fb_info *info);
45 45
46void nouveau_fbcon_gpu_lockup(struct fb_info *info);
46#endif /* __NV50_FBCON_H__ */ 47#endif /* __NV50_FBCON_H__ */
47 48
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
index dacac9a0842a..faddf53ff9ed 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -142,7 +142,7 @@ nouveau_fence_emit(struct nouveau_fence *fence)
142 list_add_tail(&fence->entry, &chan->fence.pending); 142 list_add_tail(&fence->entry, &chan->fence.pending);
143 spin_unlock_irqrestore(&chan->fence.lock, flags); 143 spin_unlock_irqrestore(&chan->fence.lock, flags);
144 144
145 BEGIN_RING(chan, NvSubM2MF, USE_REFCNT ? 0x0050 : 0x0150, 1); 145 BEGIN_RING(chan, NvSubSw, USE_REFCNT ? 0x0050 : 0x0150, 1);
146 OUT_RING(chan, fence->sequence); 146 OUT_RING(chan, fence->sequence);
147 FIRE_RING(chan); 147 FIRE_RING(chan);
148 148
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 18fd8ac9fca7..6ac804b0c9f9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -220,7 +220,6 @@ nouveau_gem_set_domain(struct drm_gem_object *gem, uint32_t read_domains,
220} 220}
221 221
222struct validate_op { 222struct validate_op {
223 struct nouveau_fence *fence;
224 struct list_head vram_list; 223 struct list_head vram_list;
225 struct list_head gart_list; 224 struct list_head gart_list;
226 struct list_head both_list; 225 struct list_head both_list;
@@ -252,17 +251,11 @@ validate_fini_list(struct list_head *list, struct nouveau_fence *fence)
252} 251}
253 252
254static void 253static void
255validate_fini(struct validate_op *op, bool success) 254validate_fini(struct validate_op *op, struct nouveau_fence* fence)
256{ 255{
257 struct nouveau_fence *fence = op->fence; 256 validate_fini_list(&op->vram_list, fence);
258 257 validate_fini_list(&op->gart_list, fence);
259 if (unlikely(!success)) 258 validate_fini_list(&op->both_list, fence);
260 op->fence = NULL;
261
262 validate_fini_list(&op->vram_list, op->fence);
263 validate_fini_list(&op->gart_list, op->fence);
264 validate_fini_list(&op->both_list, op->fence);
265 nouveau_fence_unref((void *)&fence);
266} 259}
267 260
268static int 261static int
@@ -328,6 +321,7 @@ retry:
328 else { 321 else {
329 NV_ERROR(dev, "invalid valid domains: 0x%08x\n", 322 NV_ERROR(dev, "invalid valid domains: 0x%08x\n",
330 b->valid_domains); 323 b->valid_domains);
324 list_add_tail(&nvbo->entry, &op->both_list);
331 validate_fini(op, NULL); 325 validate_fini(op, NULL);
332 return -EINVAL; 326 return -EINVAL;
333 } 327 }
@@ -420,10 +414,6 @@ nouveau_gem_pushbuf_validate(struct nouveau_channel *chan,
420 INIT_LIST_HEAD(&op->gart_list); 414 INIT_LIST_HEAD(&op->gart_list);
421 INIT_LIST_HEAD(&op->both_list); 415 INIT_LIST_HEAD(&op->both_list);
422 416
423 ret = nouveau_fence_new(chan, &op->fence, false);
424 if (ret)
425 return ret;
426
427 if (nr_buffers == 0) 417 if (nr_buffers == 0)
428 return 0; 418 return 0;
429 419
@@ -477,13 +467,14 @@ u_memcpya(uint64_t user, unsigned nmemb, unsigned size)
477static int 467static int
478nouveau_gem_pushbuf_reloc_apply(struct nouveau_channel *chan, int nr_bo, 468nouveau_gem_pushbuf_reloc_apply(struct nouveau_channel *chan, int nr_bo,
479 struct drm_nouveau_gem_pushbuf_bo *bo, 469 struct drm_nouveau_gem_pushbuf_bo *bo,
480 int nr_relocs, uint64_t ptr_relocs, 470 unsigned nr_relocs, uint64_t ptr_relocs,
481 int nr_dwords, int first_dword, 471 unsigned nr_dwords, unsigned first_dword,
482 uint32_t *pushbuf, bool is_iomem) 472 uint32_t *pushbuf, bool is_iomem)
483{ 473{
484 struct drm_nouveau_gem_pushbuf_reloc *reloc = NULL; 474 struct drm_nouveau_gem_pushbuf_reloc *reloc = NULL;
485 struct drm_device *dev = chan->dev; 475 struct drm_device *dev = chan->dev;
486 int ret = 0, i; 476 int ret = 0;
477 unsigned i;
487 478
488 reloc = u_memcpya(ptr_relocs, nr_relocs, sizeof(*reloc)); 479 reloc = u_memcpya(ptr_relocs, nr_relocs, sizeof(*reloc));
489 if (IS_ERR(reloc)) 480 if (IS_ERR(reloc))
@@ -541,6 +532,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
541 struct drm_nouveau_gem_pushbuf_bo *bo = NULL; 532 struct drm_nouveau_gem_pushbuf_bo *bo = NULL;
542 struct nouveau_channel *chan; 533 struct nouveau_channel *chan;
543 struct validate_op op; 534 struct validate_op op;
535 struct nouveau_fence* fence = 0;
544 uint32_t *pushbuf = NULL; 536 uint32_t *pushbuf = NULL;
545 int ret = 0, do_reloc = 0, i; 537 int ret = 0, do_reloc = 0, i;
546 538
@@ -597,7 +589,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
597 589
598 OUT_RINGp(chan, pushbuf, req->nr_dwords); 590 OUT_RINGp(chan, pushbuf, req->nr_dwords);
599 591
600 ret = nouveau_fence_emit(op.fence); 592 ret = nouveau_fence_new(chan, &fence, true);
601 if (ret) { 593 if (ret) {
602 NV_ERROR(dev, "error fencing pushbuf: %d\n", ret); 594 NV_ERROR(dev, "error fencing pushbuf: %d\n", ret);
603 WIND_RING(chan); 595 WIND_RING(chan);
@@ -605,7 +597,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
605 } 597 }
606 598
607 if (nouveau_gem_pushbuf_sync(chan)) { 599 if (nouveau_gem_pushbuf_sync(chan)) {
608 ret = nouveau_fence_wait(op.fence, NULL, false, false); 600 ret = nouveau_fence_wait(fence, NULL, false, false);
609 if (ret) { 601 if (ret) {
610 for (i = 0; i < req->nr_dwords; i++) 602 for (i = 0; i < req->nr_dwords; i++)
611 NV_ERROR(dev, "0x%08x\n", pushbuf[i]); 603 NV_ERROR(dev, "0x%08x\n", pushbuf[i]);
@@ -614,7 +606,8 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
614 } 606 }
615 607
616out: 608out:
617 validate_fini(&op, ret == 0); 609 validate_fini(&op, fence);
610 nouveau_fence_unref((void**)&fence);
618 mutex_unlock(&dev->struct_mutex); 611 mutex_unlock(&dev->struct_mutex);
619 kfree(pushbuf); 612 kfree(pushbuf);
620 kfree(bo); 613 kfree(bo);
@@ -634,6 +627,7 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data,
634 struct drm_gem_object *gem; 627 struct drm_gem_object *gem;
635 struct nouveau_bo *pbbo; 628 struct nouveau_bo *pbbo;
636 struct validate_op op; 629 struct validate_op op;
630 struct nouveau_fence* fence = 0;
637 int i, ret = 0, do_reloc = 0; 631 int i, ret = 0, do_reloc = 0;
638 632
639 NOUVEAU_CHECK_INITIALISED_WITH_RETURN; 633 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
@@ -675,6 +669,18 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data,
675 } 669 }
676 pbbo = nouveau_gem_object(gem); 670 pbbo = nouveau_gem_object(gem);
677 671
672 if ((req->offset & 3) || req->nr_dwords < 2 ||
673 (unsigned long)req->offset > (unsigned long)pbbo->bo.mem.size ||
674 (unsigned long)req->nr_dwords >
675 ((unsigned long)(pbbo->bo.mem.size - req->offset ) >> 2)) {
676 NV_ERROR(dev, "pb call misaligned or out of bounds: "
677 "%d + %d * 4 > %ld\n",
678 req->offset, req->nr_dwords, pbbo->bo.mem.size);
679 ret = -EINVAL;
680 drm_gem_object_unreference(gem);
681 goto out;
682 }
683
678 ret = ttm_bo_reserve(&pbbo->bo, false, false, true, 684 ret = ttm_bo_reserve(&pbbo->bo, false, false, true,
679 chan->fence.sequence); 685 chan->fence.sequence);
680 if (ret) { 686 if (ret) {
@@ -772,7 +778,7 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data,
772 OUT_RING(chan, 0); 778 OUT_RING(chan, 0);
773 } 779 }
774 780
775 ret = nouveau_fence_emit(op.fence); 781 ret = nouveau_fence_new(chan, &fence, true);
776 if (ret) { 782 if (ret) {
777 NV_ERROR(dev, "error fencing pushbuf: %d\n", ret); 783 NV_ERROR(dev, "error fencing pushbuf: %d\n", ret);
778 WIND_RING(chan); 784 WIND_RING(chan);
@@ -780,7 +786,8 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data,
780 } 786 }
781 787
782out: 788out:
783 validate_fini(&op, ret == 0); 789 validate_fini(&op, fence);
790 nouveau_fence_unref((void**)&fence);
784 mutex_unlock(&dev->struct_mutex); 791 mutex_unlock(&dev->struct_mutex);
785 kfree(bo); 792 kfree(bo);
786 793
diff --git a/drivers/gpu/drm/nouveau/nouveau_grctx.c b/drivers/gpu/drm/nouveau/nouveau_grctx.c
new file mode 100644
index 000000000000..419f4c2b3b89
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_grctx.c
@@ -0,0 +1,161 @@
1/*
2 * Copyright 2009 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <linux/firmware.h>
26
27#include "drmP.h"
28#include "nouveau_drv.h"
29
30struct nouveau_ctxprog {
31 uint32_t signature;
32 uint8_t version;
33 uint16_t length;
34 uint32_t data[];
35} __attribute__ ((packed));
36
37struct nouveau_ctxvals {
38 uint32_t signature;
39 uint8_t version;
40 uint32_t length;
41 struct {
42 uint32_t offset;
43 uint32_t value;
44 } data[];
45} __attribute__ ((packed));
46
47int
48nouveau_grctx_prog_load(struct drm_device *dev)
49{
50 struct drm_nouveau_private *dev_priv = dev->dev_private;
51 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
52 const int chipset = dev_priv->chipset;
53 const struct firmware *fw;
54 const struct nouveau_ctxprog *cp;
55 const struct nouveau_ctxvals *cv;
56 char name[32];
57 int ret, i;
58
59 if (pgraph->accel_blocked)
60 return -ENODEV;
61
62 if (!pgraph->ctxprog) {
63 sprintf(name, "nouveau/nv%02x.ctxprog", chipset);
64 ret = request_firmware(&fw, name, &dev->pdev->dev);
65 if (ret) {
66 NV_ERROR(dev, "No ctxprog for NV%02x\n", chipset);
67 return ret;
68 }
69
70 pgraph->ctxprog = kmalloc(fw->size, GFP_KERNEL);
71 if (!pgraph->ctxprog) {
72 NV_ERROR(dev, "OOM copying ctxprog\n");
73 release_firmware(fw);
74 return -ENOMEM;
75 }
76 memcpy(pgraph->ctxprog, fw->data, fw->size);
77
78 cp = pgraph->ctxprog;
79 if (le32_to_cpu(cp->signature) != 0x5043564e ||
80 cp->version != 0 ||
81 le16_to_cpu(cp->length) != ((fw->size - 7) / 4)) {
82 NV_ERROR(dev, "ctxprog invalid\n");
83 release_firmware(fw);
84 nouveau_grctx_fini(dev);
85 return -EINVAL;
86 }
87 release_firmware(fw);
88 }
89
90 if (!pgraph->ctxvals) {
91 sprintf(name, "nouveau/nv%02x.ctxvals", chipset);
92 ret = request_firmware(&fw, name, &dev->pdev->dev);
93 if (ret) {
94 NV_ERROR(dev, "No ctxvals for NV%02x\n", chipset);
95 nouveau_grctx_fini(dev);
96 return ret;
97 }
98
99 pgraph->ctxvals = kmalloc(fw->size, GFP_KERNEL);
100 if (!pgraph->ctxprog) {
101 NV_ERROR(dev, "OOM copying ctxprog\n");
102 release_firmware(fw);
103 nouveau_grctx_fini(dev);
104 return -ENOMEM;
105 }
106 memcpy(pgraph->ctxvals, fw->data, fw->size);
107
108 cv = (void *)pgraph->ctxvals;
109 if (le32_to_cpu(cv->signature) != 0x5643564e ||
110 cv->version != 0 ||
111 le32_to_cpu(cv->length) != ((fw->size - 9) / 8)) {
112 NV_ERROR(dev, "ctxvals invalid\n");
113 release_firmware(fw);
114 nouveau_grctx_fini(dev);
115 return -EINVAL;
116 }
117 release_firmware(fw);
118 }
119
120 cp = pgraph->ctxprog;
121
122 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
123 for (i = 0; i < le16_to_cpu(cp->length); i++)
124 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA,
125 le32_to_cpu(cp->data[i]));
126
127 return 0;
128}
129
130void
131nouveau_grctx_fini(struct drm_device *dev)
132{
133 struct drm_nouveau_private *dev_priv = dev->dev_private;
134 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
135
136 if (pgraph->ctxprog) {
137 kfree(pgraph->ctxprog);
138 pgraph->ctxprog = NULL;
139 }
140
141 if (pgraph->ctxvals) {
142 kfree(pgraph->ctxprog);
143 pgraph->ctxvals = NULL;
144 }
145}
146
147void
148nouveau_grctx_vals_load(struct drm_device *dev, struct nouveau_gpuobj *ctx)
149{
150 struct drm_nouveau_private *dev_priv = dev->dev_private;
151 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
152 struct nouveau_ctxvals *cv = pgraph->ctxvals;
153 int i;
154
155 if (!cv)
156 return;
157
158 for (i = 0; i < le32_to_cpu(cv->length); i++)
159 nv_wo32(dev, ctx, le32_to_cpu(cv->data[i].offset),
160 le32_to_cpu(cv->data[i].value));
161}
diff --git a/drivers/gpu/drm/nouveau/nouveau_grctx.h b/drivers/gpu/drm/nouveau/nouveau_grctx.h
new file mode 100644
index 000000000000..5d39c4ce8006
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_grctx.h
@@ -0,0 +1,133 @@
1#ifndef __NOUVEAU_GRCTX_H__
2#define __NOUVEAU_GRCTX_H__
3
4struct nouveau_grctx {
5 struct drm_device *dev;
6
7 enum {
8 NOUVEAU_GRCTX_PROG,
9 NOUVEAU_GRCTX_VALS
10 } mode;
11 void *data;
12
13 uint32_t ctxprog_max;
14 uint32_t ctxprog_len;
15 uint32_t ctxprog_reg;
16 int ctxprog_label[32];
17 uint32_t ctxvals_pos;
18 uint32_t ctxvals_base;
19};
20
21#ifdef CP_CTX
22static inline void
23cp_out(struct nouveau_grctx *ctx, uint32_t inst)
24{
25 uint32_t *ctxprog = ctx->data;
26
27 if (ctx->mode != NOUVEAU_GRCTX_PROG)
28 return;
29
30 BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max);
31 ctxprog[ctx->ctxprog_len++] = inst;
32}
33
34static inline void
35cp_lsr(struct nouveau_grctx *ctx, uint32_t val)
36{
37 cp_out(ctx, CP_LOAD_SR | val);
38}
39
40static inline void
41cp_ctx(struct nouveau_grctx *ctx, uint32_t reg, uint32_t length)
42{
43 ctx->ctxprog_reg = (reg - 0x00400000) >> 2;
44
45 ctx->ctxvals_base = ctx->ctxvals_pos;
46 ctx->ctxvals_pos = ctx->ctxvals_base + length;
47
48 if (length > (CP_CTX_COUNT >> CP_CTX_COUNT_SHIFT)) {
49 cp_lsr(ctx, length);
50 length = 0;
51 }
52
53 cp_out(ctx, CP_CTX | (length << CP_CTX_COUNT_SHIFT) | ctx->ctxprog_reg);
54}
55
56static inline void
57cp_name(struct nouveau_grctx *ctx, int name)
58{
59 uint32_t *ctxprog = ctx->data;
60 int i;
61
62 if (ctx->mode != NOUVEAU_GRCTX_PROG)
63 return;
64
65 ctx->ctxprog_label[name] = ctx->ctxprog_len;
66 for (i = 0; i < ctx->ctxprog_len; i++) {
67 if ((ctxprog[i] & 0xfff00000) != 0xff400000)
68 continue;
69 if ((ctxprog[i] & CP_BRA_IP) != ((name) << CP_BRA_IP_SHIFT))
70 continue;
71 ctxprog[i] = (ctxprog[i] & 0x00ff00ff) |
72 (ctx->ctxprog_len << CP_BRA_IP_SHIFT);
73 }
74}
75
76static inline void
77_cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name)
78{
79 int ip = 0;
80
81 if (mod != 2) {
82 ip = ctx->ctxprog_label[name] << CP_BRA_IP_SHIFT;
83 if (ip == 0)
84 ip = 0xff000000 | (name << CP_BRA_IP_SHIFT);
85 }
86
87 cp_out(ctx, CP_BRA | (mod << 18) | ip | flag |
88 (state ? 0 : CP_BRA_IF_CLEAR));
89}
90#define cp_bra(c,f,s,n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
91#ifdef CP_BRA_MOD
92#define cp_cal(c,f,s,n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
93#define cp_ret(c,f,s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0)
94#endif
95
96static inline void
97_cp_wait(struct nouveau_grctx *ctx, int flag, int state)
98{
99 cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0));
100}
101#define cp_wait(c,f,s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
102
103static inline void
104_cp_set(struct nouveau_grctx *ctx, int flag, int state)
105{
106 cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0));
107}
108#define cp_set(c,f,s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
109
110static inline void
111cp_pos(struct nouveau_grctx *ctx, int offset)
112{
113 ctx->ctxvals_pos = offset;
114 ctx->ctxvals_base = ctx->ctxvals_pos;
115
116 cp_lsr(ctx, ctx->ctxvals_pos);
117 cp_out(ctx, CP_SET_CONTEXT_POINTER);
118}
119
120static inline void
121gr_def(struct nouveau_grctx *ctx, uint32_t reg, uint32_t val)
122{
123 if (ctx->mode != NOUVEAU_GRCTX_VALS)
124 return;
125
126 reg = (reg - 0x00400000) / 4;
127 reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base;
128
129 nv_wo32(ctx->dev, ctx->data, reg, val);
130}
131#endif
132
133#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c
index 370c72c968d1..3b9bad66162a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_irq.c
+++ b/drivers/gpu/drm/nouveau/nouveau_irq.c
@@ -483,6 +483,13 @@ nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource)
483 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { 483 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
484 if (nouveau_pgraph_intr_swmthd(dev, &trap)) 484 if (nouveau_pgraph_intr_swmthd(dev, &trap))
485 unhandled = 1; 485 unhandled = 1;
486 } else if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
487 uint32_t v = nv_rd32(dev, 0x402000);
488 nv_wr32(dev, 0x402000, v);
489
490 /* dump the error anyway for now: it's useful for
491 Gallium development */
492 unhandled = 1;
486 } else { 493 } else {
487 unhandled = 1; 494 unhandled = 1;
488 } 495 }
@@ -635,6 +642,7 @@ nv50_pgraph_irq_handler(struct drm_device *dev)
635 642
636 if ((nv_rd32(dev, 0x400500) & isb) != isb) 643 if ((nv_rd32(dev, 0x400500) & isb) != isb)
637 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | isb); 644 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | isb);
645 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
638 } 646 }
639 647
640 nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING); 648 nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 5158a12f7844..8f3a12f614ed 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -192,6 +192,92 @@ void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap)
192} 192}
193 193
194/* 194/*
195 * NV10-NV40 tiling helpers
196 */
197
198static void
199nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
200 uint32_t size, uint32_t pitch)
201{
202 struct drm_nouveau_private *dev_priv = dev->dev_private;
203 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
204 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
205 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
206 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
207
208 tile->addr = addr;
209 tile->size = size;
210 tile->used = !!pitch;
211 nouveau_fence_unref((void **)&tile->fence);
212
213 if (!pfifo->cache_flush(dev))
214 return;
215
216 pfifo->reassign(dev, false);
217 pfifo->cache_flush(dev);
218 pfifo->cache_pull(dev, false);
219
220 nouveau_wait_for_idle(dev);
221
222 pgraph->set_region_tiling(dev, i, addr, size, pitch);
223 pfb->set_region_tiling(dev, i, addr, size, pitch);
224
225 pfifo->cache_pull(dev, true);
226 pfifo->reassign(dev, true);
227}
228
229struct nouveau_tile_reg *
230nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
231 uint32_t pitch)
232{
233 struct drm_nouveau_private *dev_priv = dev->dev_private;
234 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
235 struct nouveau_tile_reg *tile = dev_priv->tile.reg, *found = NULL;
236 int i;
237
238 spin_lock(&dev_priv->tile.lock);
239
240 for (i = 0; i < pfb->num_tiles; i++) {
241 if (tile[i].used)
242 /* Tile region in use. */
243 continue;
244
245 if (tile[i].fence &&
246 !nouveau_fence_signalled(tile[i].fence, NULL))
247 /* Pending tile region. */
248 continue;
249
250 if (max(tile[i].addr, addr) <
251 min(tile[i].addr + tile[i].size, addr + size))
252 /* Kill an intersecting tile region. */
253 nv10_mem_set_region_tiling(dev, i, 0, 0, 0);
254
255 if (pitch && !found) {
256 /* Free tile region. */
257 nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
258 found = &tile[i];
259 }
260 }
261
262 spin_unlock(&dev_priv->tile.lock);
263
264 return found;
265}
266
267void
268nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile,
269 struct nouveau_fence *fence)
270{
271 if (fence) {
272 /* Mark it as pending. */
273 tile->fence = fence;
274 nouveau_fence_ref(fence);
275 }
276
277 tile->used = false;
278}
279
280/*
195 * NV50 VM helpers 281 * NV50 VM helpers
196 */ 282 */
197int 283int
@@ -297,9 +383,8 @@ void nouveau_mem_close(struct drm_device *dev)
297{ 383{
298 struct drm_nouveau_private *dev_priv = dev->dev_private; 384 struct drm_nouveau_private *dev_priv = dev->dev_private;
299 385
300 if (dev_priv->ttm.bdev.man[TTM_PL_PRIV0].has_type) 386 nouveau_bo_unpin(dev_priv->vga_ram);
301 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_PRIV0); 387 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
302 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
303 388
304 ttm_bo_device_release(&dev_priv->ttm.bdev); 389 ttm_bo_device_release(&dev_priv->ttm.bdev);
305 390
@@ -513,6 +598,7 @@ nouveau_mem_init(struct drm_device *dev)
513 598
514 INIT_LIST_HEAD(&dev_priv->ttm.bo_list); 599 INIT_LIST_HEAD(&dev_priv->ttm.bo_list);
515 spin_lock_init(&dev_priv->ttm.bo_list_lock); 600 spin_lock_init(&dev_priv->ttm.bo_list_lock);
601 spin_lock_init(&dev_priv->tile.lock);
516 602
517 dev_priv->fb_available_size = nouveau_mem_fb_amount(dev); 603 dev_priv->fb_available_size = nouveau_mem_fb_amount(dev);
518 604
@@ -535,6 +621,15 @@ nouveau_mem_init(struct drm_device *dev)
535 return ret; 621 return ret;
536 } 622 }
537 623
624 ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
625 0, 0, true, true, &dev_priv->vga_ram);
626 if (ret == 0)
627 ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
628 if (ret) {
629 NV_WARN(dev, "failed to reserve VGA memory\n");
630 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
631 }
632
538 /* GART */ 633 /* GART */
539#if !defined(__powerpc__) && !defined(__ia64__) 634#if !defined(__powerpc__) && !defined(__ia64__)
540 if (drm_device_is_agp(dev) && dev->agp) { 635 if (drm_device_is_agp(dev) && dev->agp) {
@@ -566,6 +661,7 @@ nouveau_mem_init(struct drm_device *dev)
566 dev_priv->fb_mtrr = drm_mtrr_add(drm_get_resource_start(dev, 1), 661 dev_priv->fb_mtrr = drm_mtrr_add(drm_get_resource_start(dev, 1),
567 drm_get_resource_len(dev, 1), 662 drm_get_resource_len(dev, 1),
568 DRM_MTRR_WC); 663 DRM_MTRR_WC);
664
569 return 0; 665 return 0;
570} 666}
571 667
diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c
index 93379bb81bea..6c2cf81716df 100644
--- a/drivers/gpu/drm/nouveau/nouveau_object.c
+++ b/drivers/gpu/drm/nouveau/nouveau_object.c
@@ -881,7 +881,7 @@ nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class,
881 return 0; 881 return 0;
882} 882}
883 883
884static int 884int
885nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class, 885nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class,
886 struct nouveau_gpuobj **gpuobj_ret) 886 struct nouveau_gpuobj **gpuobj_ret)
887{ 887{
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h
index fa1b0e7165b9..251f1b3b38b9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_reg.h
+++ b/drivers/gpu/drm/nouveau/nouveau_reg.h
@@ -349,19 +349,19 @@
349#define NV04_PGRAPH_BLEND 0x00400824 349#define NV04_PGRAPH_BLEND 0x00400824
350#define NV04_PGRAPH_STORED_FMT 0x00400830 350#define NV04_PGRAPH_STORED_FMT 0x00400830
351#define NV04_PGRAPH_PATT_COLORRAM 0x00400900 351#define NV04_PGRAPH_PATT_COLORRAM 0x00400900
352#define NV40_PGRAPH_TILE0(i) (0x00400900 + (i*16)) 352#define NV20_PGRAPH_TILE(i) (0x00400900 + (i*16))
353#define NV40_PGRAPH_TLIMIT0(i) (0x00400904 + (i*16)) 353#define NV20_PGRAPH_TLIMIT(i) (0x00400904 + (i*16))
354#define NV40_PGRAPH_TSIZE0(i) (0x00400908 + (i*16)) 354#define NV20_PGRAPH_TSIZE(i) (0x00400908 + (i*16))
355#define NV40_PGRAPH_TSTATUS0(i) (0x0040090C + (i*16)) 355#define NV20_PGRAPH_TSTATUS(i) (0x0040090C + (i*16))
356#define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16)) 356#define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16))
357#define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16)) 357#define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16))
358#define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16)) 358#define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16))
359#define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16)) 359#define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16))
360#define NV04_PGRAPH_U_RAM 0x00400D00 360#define NV04_PGRAPH_U_RAM 0x00400D00
361#define NV47_PGRAPH_TILE0(i) (0x00400D00 + (i*16)) 361#define NV47_PGRAPH_TILE(i) (0x00400D00 + (i*16))
362#define NV47_PGRAPH_TLIMIT0(i) (0x00400D04 + (i*16)) 362#define NV47_PGRAPH_TLIMIT(i) (0x00400D04 + (i*16))
363#define NV47_PGRAPH_TSIZE0(i) (0x00400D08 + (i*16)) 363#define NV47_PGRAPH_TSIZE(i) (0x00400D08 + (i*16))
364#define NV47_PGRAPH_TSTATUS0(i) (0x00400D0C + (i*16)) 364#define NV47_PGRAPH_TSTATUS(i) (0x00400D0C + (i*16))
365#define NV04_PGRAPH_V_RAM 0x00400D40 365#define NV04_PGRAPH_V_RAM 0x00400D40
366#define NV04_PGRAPH_W_RAM 0x00400D80 366#define NV04_PGRAPH_W_RAM 0x00400D80
367#define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40 367#define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 2ed41d339f6a..f2d0187ba152 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -76,6 +76,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
76 engine->fifo.disable = nv04_fifo_disable; 76 engine->fifo.disable = nv04_fifo_disable;
77 engine->fifo.enable = nv04_fifo_enable; 77 engine->fifo.enable = nv04_fifo_enable;
78 engine->fifo.reassign = nv04_fifo_reassign; 78 engine->fifo.reassign = nv04_fifo_reassign;
79 engine->fifo.cache_flush = nv04_fifo_cache_flush;
80 engine->fifo.cache_pull = nv04_fifo_cache_pull;
79 engine->fifo.channel_id = nv04_fifo_channel_id; 81 engine->fifo.channel_id = nv04_fifo_channel_id;
80 engine->fifo.create_context = nv04_fifo_create_context; 82 engine->fifo.create_context = nv04_fifo_create_context;
81 engine->fifo.destroy_context = nv04_fifo_destroy_context; 83 engine->fifo.destroy_context = nv04_fifo_destroy_context;
@@ -100,6 +102,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
100 engine->timer.takedown = nv04_timer_takedown; 102 engine->timer.takedown = nv04_timer_takedown;
101 engine->fb.init = nv10_fb_init; 103 engine->fb.init = nv10_fb_init;
102 engine->fb.takedown = nv10_fb_takedown; 104 engine->fb.takedown = nv10_fb_takedown;
105 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
103 engine->graph.grclass = nv10_graph_grclass; 106 engine->graph.grclass = nv10_graph_grclass;
104 engine->graph.init = nv10_graph_init; 107 engine->graph.init = nv10_graph_init;
105 engine->graph.takedown = nv10_graph_takedown; 108 engine->graph.takedown = nv10_graph_takedown;
@@ -109,12 +112,15 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
109 engine->graph.fifo_access = nv04_graph_fifo_access; 112 engine->graph.fifo_access = nv04_graph_fifo_access;
110 engine->graph.load_context = nv10_graph_load_context; 113 engine->graph.load_context = nv10_graph_load_context;
111 engine->graph.unload_context = nv10_graph_unload_context; 114 engine->graph.unload_context = nv10_graph_unload_context;
115 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
112 engine->fifo.channels = 32; 116 engine->fifo.channels = 32;
113 engine->fifo.init = nv10_fifo_init; 117 engine->fifo.init = nv10_fifo_init;
114 engine->fifo.takedown = nouveau_stub_takedown; 118 engine->fifo.takedown = nouveau_stub_takedown;
115 engine->fifo.disable = nv04_fifo_disable; 119 engine->fifo.disable = nv04_fifo_disable;
116 engine->fifo.enable = nv04_fifo_enable; 120 engine->fifo.enable = nv04_fifo_enable;
117 engine->fifo.reassign = nv04_fifo_reassign; 121 engine->fifo.reassign = nv04_fifo_reassign;
122 engine->fifo.cache_flush = nv04_fifo_cache_flush;
123 engine->fifo.cache_pull = nv04_fifo_cache_pull;
118 engine->fifo.channel_id = nv10_fifo_channel_id; 124 engine->fifo.channel_id = nv10_fifo_channel_id;
119 engine->fifo.create_context = nv10_fifo_create_context; 125 engine->fifo.create_context = nv10_fifo_create_context;
120 engine->fifo.destroy_context = nv10_fifo_destroy_context; 126 engine->fifo.destroy_context = nv10_fifo_destroy_context;
@@ -139,6 +145,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
139 engine->timer.takedown = nv04_timer_takedown; 145 engine->timer.takedown = nv04_timer_takedown;
140 engine->fb.init = nv10_fb_init; 146 engine->fb.init = nv10_fb_init;
141 engine->fb.takedown = nv10_fb_takedown; 147 engine->fb.takedown = nv10_fb_takedown;
148 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
142 engine->graph.grclass = nv20_graph_grclass; 149 engine->graph.grclass = nv20_graph_grclass;
143 engine->graph.init = nv20_graph_init; 150 engine->graph.init = nv20_graph_init;
144 engine->graph.takedown = nv20_graph_takedown; 151 engine->graph.takedown = nv20_graph_takedown;
@@ -148,12 +155,15 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
148 engine->graph.fifo_access = nv04_graph_fifo_access; 155 engine->graph.fifo_access = nv04_graph_fifo_access;
149 engine->graph.load_context = nv20_graph_load_context; 156 engine->graph.load_context = nv20_graph_load_context;
150 engine->graph.unload_context = nv20_graph_unload_context; 157 engine->graph.unload_context = nv20_graph_unload_context;
158 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
151 engine->fifo.channels = 32; 159 engine->fifo.channels = 32;
152 engine->fifo.init = nv10_fifo_init; 160 engine->fifo.init = nv10_fifo_init;
153 engine->fifo.takedown = nouveau_stub_takedown; 161 engine->fifo.takedown = nouveau_stub_takedown;
154 engine->fifo.disable = nv04_fifo_disable; 162 engine->fifo.disable = nv04_fifo_disable;
155 engine->fifo.enable = nv04_fifo_enable; 163 engine->fifo.enable = nv04_fifo_enable;
156 engine->fifo.reassign = nv04_fifo_reassign; 164 engine->fifo.reassign = nv04_fifo_reassign;
165 engine->fifo.cache_flush = nv04_fifo_cache_flush;
166 engine->fifo.cache_pull = nv04_fifo_cache_pull;
157 engine->fifo.channel_id = nv10_fifo_channel_id; 167 engine->fifo.channel_id = nv10_fifo_channel_id;
158 engine->fifo.create_context = nv10_fifo_create_context; 168 engine->fifo.create_context = nv10_fifo_create_context;
159 engine->fifo.destroy_context = nv10_fifo_destroy_context; 169 engine->fifo.destroy_context = nv10_fifo_destroy_context;
@@ -178,6 +188,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
178 engine->timer.takedown = nv04_timer_takedown; 188 engine->timer.takedown = nv04_timer_takedown;
179 engine->fb.init = nv10_fb_init; 189 engine->fb.init = nv10_fb_init;
180 engine->fb.takedown = nv10_fb_takedown; 190 engine->fb.takedown = nv10_fb_takedown;
191 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
181 engine->graph.grclass = nv30_graph_grclass; 192 engine->graph.grclass = nv30_graph_grclass;
182 engine->graph.init = nv30_graph_init; 193 engine->graph.init = nv30_graph_init;
183 engine->graph.takedown = nv20_graph_takedown; 194 engine->graph.takedown = nv20_graph_takedown;
@@ -187,12 +198,15 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
187 engine->graph.destroy_context = nv20_graph_destroy_context; 198 engine->graph.destroy_context = nv20_graph_destroy_context;
188 engine->graph.load_context = nv20_graph_load_context; 199 engine->graph.load_context = nv20_graph_load_context;
189 engine->graph.unload_context = nv20_graph_unload_context; 200 engine->graph.unload_context = nv20_graph_unload_context;
201 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
190 engine->fifo.channels = 32; 202 engine->fifo.channels = 32;
191 engine->fifo.init = nv10_fifo_init; 203 engine->fifo.init = nv10_fifo_init;
192 engine->fifo.takedown = nouveau_stub_takedown; 204 engine->fifo.takedown = nouveau_stub_takedown;
193 engine->fifo.disable = nv04_fifo_disable; 205 engine->fifo.disable = nv04_fifo_disable;
194 engine->fifo.enable = nv04_fifo_enable; 206 engine->fifo.enable = nv04_fifo_enable;
195 engine->fifo.reassign = nv04_fifo_reassign; 207 engine->fifo.reassign = nv04_fifo_reassign;
208 engine->fifo.cache_flush = nv04_fifo_cache_flush;
209 engine->fifo.cache_pull = nv04_fifo_cache_pull;
196 engine->fifo.channel_id = nv10_fifo_channel_id; 210 engine->fifo.channel_id = nv10_fifo_channel_id;
197 engine->fifo.create_context = nv10_fifo_create_context; 211 engine->fifo.create_context = nv10_fifo_create_context;
198 engine->fifo.destroy_context = nv10_fifo_destroy_context; 212 engine->fifo.destroy_context = nv10_fifo_destroy_context;
@@ -218,6 +232,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
218 engine->timer.takedown = nv04_timer_takedown; 232 engine->timer.takedown = nv04_timer_takedown;
219 engine->fb.init = nv40_fb_init; 233 engine->fb.init = nv40_fb_init;
220 engine->fb.takedown = nv40_fb_takedown; 234 engine->fb.takedown = nv40_fb_takedown;
235 engine->fb.set_region_tiling = nv40_fb_set_region_tiling;
221 engine->graph.grclass = nv40_graph_grclass; 236 engine->graph.grclass = nv40_graph_grclass;
222 engine->graph.init = nv40_graph_init; 237 engine->graph.init = nv40_graph_init;
223 engine->graph.takedown = nv40_graph_takedown; 238 engine->graph.takedown = nv40_graph_takedown;
@@ -227,12 +242,15 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
227 engine->graph.destroy_context = nv40_graph_destroy_context; 242 engine->graph.destroy_context = nv40_graph_destroy_context;
228 engine->graph.load_context = nv40_graph_load_context; 243 engine->graph.load_context = nv40_graph_load_context;
229 engine->graph.unload_context = nv40_graph_unload_context; 244 engine->graph.unload_context = nv40_graph_unload_context;
245 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
230 engine->fifo.channels = 32; 246 engine->fifo.channels = 32;
231 engine->fifo.init = nv40_fifo_init; 247 engine->fifo.init = nv40_fifo_init;
232 engine->fifo.takedown = nouveau_stub_takedown; 248 engine->fifo.takedown = nouveau_stub_takedown;
233 engine->fifo.disable = nv04_fifo_disable; 249 engine->fifo.disable = nv04_fifo_disable;
234 engine->fifo.enable = nv04_fifo_enable; 250 engine->fifo.enable = nv04_fifo_enable;
235 engine->fifo.reassign = nv04_fifo_reassign; 251 engine->fifo.reassign = nv04_fifo_reassign;
252 engine->fifo.cache_flush = nv04_fifo_cache_flush;
253 engine->fifo.cache_pull = nv04_fifo_cache_pull;
236 engine->fifo.channel_id = nv10_fifo_channel_id; 254 engine->fifo.channel_id = nv10_fifo_channel_id;
237 engine->fifo.create_context = nv40_fifo_create_context; 255 engine->fifo.create_context = nv40_fifo_create_context;
238 engine->fifo.destroy_context = nv40_fifo_destroy_context; 256 engine->fifo.destroy_context = nv40_fifo_destroy_context;
@@ -299,12 +317,57 @@ nouveau_vga_set_decode(void *priv, bool state)
299 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 317 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
300} 318}
301 319
320static int
321nouveau_card_init_channel(struct drm_device *dev)
322{
323 struct drm_nouveau_private *dev_priv = dev->dev_private;
324 struct nouveau_gpuobj *gpuobj;
325 int ret;
326
327 ret = nouveau_channel_alloc(dev, &dev_priv->channel,
328 (struct drm_file *)-2,
329 NvDmaFB, NvDmaTT);
330 if (ret)
331 return ret;
332
333 gpuobj = NULL;
334 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
335 0, nouveau_mem_fb_amount(dev),
336 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
337 &gpuobj);
338 if (ret)
339 goto out_err;
340
341 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
342 gpuobj, NULL);
343 if (ret)
344 goto out_err;
345
346 gpuobj = NULL;
347 ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
348 dev_priv->gart_info.aper_size,
349 NV_DMA_ACCESS_RW, &gpuobj, NULL);
350 if (ret)
351 goto out_err;
352
353 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
354 gpuobj, NULL);
355 if (ret)
356 goto out_err;
357
358 return 0;
359out_err:
360 nouveau_gpuobj_del(dev, &gpuobj);
361 nouveau_channel_free(dev_priv->channel);
362 dev_priv->channel = NULL;
363 return ret;
364}
365
302int 366int
303nouveau_card_init(struct drm_device *dev) 367nouveau_card_init(struct drm_device *dev)
304{ 368{
305 struct drm_nouveau_private *dev_priv = dev->dev_private; 369 struct drm_nouveau_private *dev_priv = dev->dev_private;
306 struct nouveau_engine *engine; 370 struct nouveau_engine *engine;
307 struct nouveau_gpuobj *gpuobj;
308 int ret; 371 int ret;
309 372
310 NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state); 373 NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
@@ -317,7 +380,7 @@ nouveau_card_init(struct drm_device *dev)
317 /* Initialise internal driver API hooks */ 380 /* Initialise internal driver API hooks */
318 ret = nouveau_init_engine_ptrs(dev); 381 ret = nouveau_init_engine_ptrs(dev);
319 if (ret) 382 if (ret)
320 return ret; 383 goto out;
321 engine = &dev_priv->engine; 384 engine = &dev_priv->engine;
322 dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED; 385 dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
323 386
@@ -325,12 +388,12 @@ nouveau_card_init(struct drm_device *dev)
325 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 388 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
326 ret = nouveau_bios_init(dev); 389 ret = nouveau_bios_init(dev);
327 if (ret) 390 if (ret)
328 return ret; 391 goto out;
329 } 392 }
330 393
331 ret = nouveau_gpuobj_early_init(dev); 394 ret = nouveau_gpuobj_early_init(dev);
332 if (ret) 395 if (ret)
333 return ret; 396 goto out_bios;
334 397
335 /* Initialise instance memory, must happen before mem_init so we 398 /* Initialise instance memory, must happen before mem_init so we
336 * know exactly how much VRAM we're able to use for "normal" 399 * know exactly how much VRAM we're able to use for "normal"
@@ -338,100 +401,68 @@ nouveau_card_init(struct drm_device *dev)
338 */ 401 */
339 ret = engine->instmem.init(dev); 402 ret = engine->instmem.init(dev);
340 if (ret) 403 if (ret)
341 return ret; 404 goto out_gpuobj_early;
342 405
343 /* Setup the memory manager */ 406 /* Setup the memory manager */
344 ret = nouveau_mem_init(dev); 407 ret = nouveau_mem_init(dev);
345 if (ret) 408 if (ret)
346 return ret; 409 goto out_instmem;
347 410
348 ret = nouveau_gpuobj_init(dev); 411 ret = nouveau_gpuobj_init(dev);
349 if (ret) 412 if (ret)
350 return ret; 413 goto out_mem;
351 414
352 /* PMC */ 415 /* PMC */
353 ret = engine->mc.init(dev); 416 ret = engine->mc.init(dev);
354 if (ret) 417 if (ret)
355 return ret; 418 goto out_gpuobj;
356 419
357 /* PTIMER */ 420 /* PTIMER */
358 ret = engine->timer.init(dev); 421 ret = engine->timer.init(dev);
359 if (ret) 422 if (ret)
360 return ret; 423 goto out_mc;
361 424
362 /* PFB */ 425 /* PFB */
363 ret = engine->fb.init(dev); 426 ret = engine->fb.init(dev);
364 if (ret) 427 if (ret)
365 return ret; 428 goto out_timer;
366 429
367 /* PGRAPH */ 430 /* PGRAPH */
368 ret = engine->graph.init(dev); 431 ret = engine->graph.init(dev);
369 if (ret) 432 if (ret)
370 return ret; 433 goto out_fb;
371 434
372 /* PFIFO */ 435 /* PFIFO */
373 ret = engine->fifo.init(dev); 436 ret = engine->fifo.init(dev);
374 if (ret) 437 if (ret)
375 return ret; 438 goto out_graph;
376 439
377 /* this call irq_preinstall, register irq handler and 440 /* this call irq_preinstall, register irq handler and
378 * call irq_postinstall 441 * call irq_postinstall
379 */ 442 */
380 ret = drm_irq_install(dev); 443 ret = drm_irq_install(dev);
381 if (ret) 444 if (ret)
382 return ret; 445 goto out_fifo;
383 446
384 ret = drm_vblank_init(dev, 0); 447 ret = drm_vblank_init(dev, 0);
385 if (ret) 448 if (ret)
386 return ret; 449 goto out_irq;
387 450
388 /* what about PVIDEO/PCRTC/PRAMDAC etc? */ 451 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
389 452
390 ret = nouveau_channel_alloc(dev, &dev_priv->channel, 453 if (!engine->graph.accel_blocked) {
391 (struct drm_file *)-2, 454 ret = nouveau_card_init_channel(dev);
392 NvDmaFB, NvDmaTT); 455 if (ret)
393 if (ret) 456 goto out_irq;
394 return ret;
395
396 gpuobj = NULL;
397 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
398 0, nouveau_mem_fb_amount(dev),
399 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
400 &gpuobj);
401 if (ret)
402 return ret;
403
404 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
405 gpuobj, NULL);
406 if (ret) {
407 nouveau_gpuobj_del(dev, &gpuobj);
408 return ret;
409 }
410
411 gpuobj = NULL;
412 ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
413 dev_priv->gart_info.aper_size,
414 NV_DMA_ACCESS_RW, &gpuobj, NULL);
415 if (ret)
416 return ret;
417
418 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
419 gpuobj, NULL);
420 if (ret) {
421 nouveau_gpuobj_del(dev, &gpuobj);
422 return ret;
423 } 457 }
424 458
425 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 459 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
426 if (dev_priv->card_type >= NV_50) { 460 if (dev_priv->card_type >= NV_50)
427 ret = nv50_display_create(dev); 461 ret = nv50_display_create(dev);
428 if (ret) 462 else
429 return ret;
430 } else {
431 ret = nv04_display_create(dev); 463 ret = nv04_display_create(dev);
432 if (ret) 464 if (ret)
433 return ret; 465 goto out_irq;
434 }
435 } 466 }
436 467
437 ret = nouveau_backlight_init(dev); 468 ret = nouveau_backlight_init(dev);
@@ -444,6 +475,32 @@ nouveau_card_init(struct drm_device *dev)
444 drm_helper_initial_config(dev); 475 drm_helper_initial_config(dev);
445 476
446 return 0; 477 return 0;
478
479out_irq:
480 drm_irq_uninstall(dev);
481out_fifo:
482 engine->fifo.takedown(dev);
483out_graph:
484 engine->graph.takedown(dev);
485out_fb:
486 engine->fb.takedown(dev);
487out_timer:
488 engine->timer.takedown(dev);
489out_mc:
490 engine->mc.takedown(dev);
491out_gpuobj:
492 nouveau_gpuobj_takedown(dev);
493out_mem:
494 nouveau_mem_close(dev);
495out_instmem:
496 engine->instmem.takedown(dev);
497out_gpuobj_early:
498 nouveau_gpuobj_late_takedown(dev);
499out_bios:
500 nouveau_bios_takedown(dev);
501out:
502 vga_client_register(dev->pdev, NULL, NULL, NULL);
503 return ret;
447} 504}
448 505
449static void nouveau_card_takedown(struct drm_device *dev) 506static void nouveau_card_takedown(struct drm_device *dev)
@@ -468,6 +525,7 @@ static void nouveau_card_takedown(struct drm_device *dev)
468 engine->mc.takedown(dev); 525 engine->mc.takedown(dev);
469 526
470 mutex_lock(&dev->struct_mutex); 527 mutex_lock(&dev->struct_mutex);
528 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
471 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT); 529 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
472 mutex_unlock(&dev->struct_mutex); 530 mutex_unlock(&dev->struct_mutex);
473 nouveau_sgdma_takedown(dev); 531 nouveau_sgdma_takedown(dev);
@@ -585,7 +643,10 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
585 dev_priv->chipset = (reg0 & 0xff00000) >> 20; 643 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
586 /* NV04 or NV05 */ 644 /* NV04 or NV05 */
587 } else if ((reg0 & 0xff00fff0) == 0x20004000) { 645 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
588 dev_priv->chipset = 0x04; 646 if (reg0 & 0x00f00000)
647 dev_priv->chipset = 0x05;
648 else
649 dev_priv->chipset = 0x04;
589 } else 650 } else
590 dev_priv->chipset = 0xff; 651 dev_priv->chipset = 0xff;
591 652
@@ -665,8 +726,8 @@ static void nouveau_close(struct drm_device *dev)
665{ 726{
666 struct drm_nouveau_private *dev_priv = dev->dev_private; 727 struct drm_nouveau_private *dev_priv = dev->dev_private;
667 728
668 /* In the case of an error dev_priv may not be be allocated yet */ 729 /* In the case of an error dev_priv may not be allocated yet */
669 if (dev_priv && dev_priv->card_type) 730 if (dev_priv)
670 nouveau_card_takedown(dev); 731 nouveau_card_takedown(dev);
671} 732}
672 733
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c
index 187eb84e4da5..c385d50f041b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -28,45 +28,17 @@
28 28
29#include "nouveau_drv.h" 29#include "nouveau_drv.h"
30 30
31static struct vm_operations_struct nouveau_ttm_vm_ops;
32static const struct vm_operations_struct *ttm_vm_ops;
33
34static int
35nouveau_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
36{
37 struct ttm_buffer_object *bo = vma->vm_private_data;
38 int ret;
39
40 if (unlikely(bo == NULL))
41 return VM_FAULT_NOPAGE;
42
43 ret = ttm_vm_ops->fault(vma, vmf);
44 return ret;
45}
46
47int 31int
48nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma) 32nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma)
49{ 33{
50 struct drm_file *file_priv = filp->private_data; 34 struct drm_file *file_priv = filp->private_data;
51 struct drm_nouveau_private *dev_priv = 35 struct drm_nouveau_private *dev_priv =
52 file_priv->minor->dev->dev_private; 36 file_priv->minor->dev->dev_private;
53 int ret;
54 37
55 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) 38 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
56 return drm_mmap(filp, vma); 39 return drm_mmap(filp, vma);
57 40
58 ret = ttm_bo_mmap(filp, vma, &dev_priv->ttm.bdev); 41 return ttm_bo_mmap(filp, vma, &dev_priv->ttm.bdev);
59 if (unlikely(ret != 0))
60 return ret;
61
62 if (unlikely(ttm_vm_ops == NULL)) {
63 ttm_vm_ops = vma->vm_ops;
64 nouveau_ttm_vm_ops = *ttm_vm_ops;
65 nouveau_ttm_vm_ops.fault = &nouveau_ttm_fault;
66 }
67
68 vma->vm_ops = &nouveau_ttm_vm_ops;
69 return 0;
70} 42}
71 43
72static int 44static int
diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
index b91363606055..d2f143ed97c1 100644
--- a/drivers/gpu/drm/nouveau/nv04_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
@@ -143,10 +143,10 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod
143 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; 143 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
144 144
145 if (pv->NM2) 145 if (pv->NM2)
146 NV_TRACE(dev, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", 146 NV_DEBUG_KMS(dev, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
147 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); 147 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
148 else 148 else
149 NV_TRACE(dev, "vpll: n %d m %d log2p %d\n", 149 NV_DEBUG_KMS(dev, "vpll: n %d m %d log2p %d\n",
150 pv->N1, pv->M1, pv->log2P); 150 pv->N1, pv->M1, pv->log2P);
151 151
152 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 152 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
@@ -160,7 +160,7 @@ nv_crtc_dpms(struct drm_crtc *crtc, int mode)
160 unsigned char seq1 = 0, crtc17 = 0; 160 unsigned char seq1 = 0, crtc17 = 0;
161 unsigned char crtc1A; 161 unsigned char crtc1A;
162 162
163 NV_TRACE(dev, "Setting dpms mode %d on CRTC %d\n", mode, 163 NV_DEBUG_KMS(dev, "Setting dpms mode %d on CRTC %d\n", mode,
164 nv_crtc->index); 164 nv_crtc->index);
165 165
166 if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */ 166 if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
@@ -603,7 +603,7 @@ nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
603 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 603 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
604 struct drm_nouveau_private *dev_priv = dev->dev_private; 604 struct drm_nouveau_private *dev_priv = dev->dev_private;
605 605
606 NV_DEBUG(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index); 606 NV_DEBUG_KMS(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index);
607 drm_mode_debug_printmodeline(adjusted_mode); 607 drm_mode_debug_printmodeline(adjusted_mode);
608 608
609 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ 609 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */
@@ -703,7 +703,7 @@ static void nv_crtc_destroy(struct drm_crtc *crtc)
703{ 703{
704 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 704 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
705 705
706 NV_DEBUG(crtc->dev, "\n"); 706 NV_DEBUG_KMS(crtc->dev, "\n");
707 707
708 if (!nv_crtc) 708 if (!nv_crtc)
709 return; 709 return;
diff --git a/drivers/gpu/drm/nouveau/nv04_dac.c b/drivers/gpu/drm/nouveau/nv04_dac.c
index a5fa51714e87..d0e038d28948 100644
--- a/drivers/gpu/drm/nouveau/nv04_dac.c
+++ b/drivers/gpu/drm/nouveau/nv04_dac.c
@@ -205,23 +205,22 @@ out:
205 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1); 205 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);
206 206
207 if (blue == 0x18) { 207 if (blue == 0x18) {
208 NV_TRACE(dev, "Load detected on head A\n"); 208 NV_INFO(dev, "Load detected on head A\n");
209 return connector_status_connected; 209 return connector_status_connected;
210 } 210 }
211 211
212 return connector_status_disconnected; 212 return connector_status_disconnected;
213} 213}
214 214
215enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder, 215uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
216 struct drm_connector *connector)
217{ 216{
218 struct drm_device *dev = encoder->dev; 217 struct drm_device *dev = encoder->dev;
219 struct drm_nouveau_private *dev_priv = dev->dev_private; 218 struct drm_nouveau_private *dev_priv = dev->dev_private;
220 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; 219 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
221 uint32_t testval, regoffset = nv04_dac_output_offset(encoder); 220 uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder);
222 uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, 221 uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput,
223 saved_rtest_ctrl, saved_gpio0, saved_gpio1, temp, routput; 222 saved_rtest_ctrl, saved_gpio0, saved_gpio1, temp, routput;
224 int head, present = 0; 223 int head;
225 224
226#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20) 225#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
227 if (dcb->type == OUTPUT_TV) { 226 if (dcb->type == OUTPUT_TV) {
@@ -287,13 +286,7 @@ enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
287 temp | NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED); 286 temp | NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED);
288 msleep(5); 287 msleep(5);
289 288
290 temp = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset); 289 sample = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
291
292 if (dcb->type == OUTPUT_TV)
293 present = (nv17_tv_detect(encoder, connector, temp)
294 == connector_status_connected);
295 else
296 present = temp & NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI;
297 290
298 temp = NVReadRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL); 291 temp = NVReadRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL);
299 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL, 292 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL,
@@ -310,15 +303,25 @@ enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
310 nv17_gpio_set(dev, DCB_GPIO_TVDAC1, saved_gpio1); 303 nv17_gpio_set(dev, DCB_GPIO_TVDAC1, saved_gpio1);
311 nv17_gpio_set(dev, DCB_GPIO_TVDAC0, saved_gpio0); 304 nv17_gpio_set(dev, DCB_GPIO_TVDAC0, saved_gpio0);
312 305
313 if (present) { 306 return sample;
314 NV_INFO(dev, "Load detected on output %c\n", '@' + ffs(dcb->or)); 307}
308
309static enum drm_connector_status
310nv17_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
311{
312 struct drm_device *dev = encoder->dev;
313 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
314 uint32_t sample = nv17_dac_sample_load(encoder);
315
316 if (sample & NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI) {
317 NV_INFO(dev, "Load detected on output %c\n",
318 '@' + ffs(dcb->or));
315 return connector_status_connected; 319 return connector_status_connected;
320 } else {
321 return connector_status_disconnected;
316 } 322 }
317
318 return connector_status_disconnected;
319} 323}
320 324
321
322static bool nv04_dac_mode_fixup(struct drm_encoder *encoder, 325static bool nv04_dac_mode_fixup(struct drm_encoder *encoder,
323 struct drm_display_mode *mode, 326 struct drm_display_mode *mode,
324 struct drm_display_mode *adjusted_mode) 327 struct drm_display_mode *adjusted_mode)
@@ -350,14 +353,10 @@ static void nv04_dac_mode_set(struct drm_encoder *encoder,
350 struct drm_display_mode *mode, 353 struct drm_display_mode *mode,
351 struct drm_display_mode *adjusted_mode) 354 struct drm_display_mode *adjusted_mode)
352{ 355{
353 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
354 struct drm_device *dev = encoder->dev; 356 struct drm_device *dev = encoder->dev;
355 struct drm_nouveau_private *dev_priv = dev->dev_private; 357 struct drm_nouveau_private *dev_priv = dev->dev_private;
356 int head = nouveau_crtc(encoder->crtc)->index; 358 int head = nouveau_crtc(encoder->crtc)->index;
357 359
358 NV_TRACE(dev, "%s called for encoder %d\n", __func__,
359 nv_encoder->dcb->index);
360
361 if (nv_gf4_disp_arch(dev)) { 360 if (nv_gf4_disp_arch(dev)) {
362 struct drm_encoder *rebind; 361 struct drm_encoder *rebind;
363 uint32_t dac_offset = nv04_dac_output_offset(encoder); 362 uint32_t dac_offset = nv04_dac_output_offset(encoder);
@@ -466,7 +465,7 @@ static void nv04_dac_destroy(struct drm_encoder *encoder)
466{ 465{
467 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 466 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
468 467
469 NV_DEBUG(encoder->dev, "\n"); 468 NV_DEBUG_KMS(encoder->dev, "\n");
470 469
471 drm_encoder_cleanup(encoder); 470 drm_encoder_cleanup(encoder);
472 kfree(nv_encoder); 471 kfree(nv_encoder);
diff --git a/drivers/gpu/drm/nouveau/nv04_dfp.c b/drivers/gpu/drm/nouveau/nv04_dfp.c
index e5b33339d595..483f875bdb6a 100644
--- a/drivers/gpu/drm/nouveau/nv04_dfp.c
+++ b/drivers/gpu/drm/nouveau/nv04_dfp.c
@@ -261,7 +261,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
261 struct drm_display_mode *output_mode = &nv_encoder->mode; 261 struct drm_display_mode *output_mode = &nv_encoder->mode;
262 uint32_t mode_ratio, panel_ratio; 262 uint32_t mode_ratio, panel_ratio;
263 263
264 NV_DEBUG(dev, "Output mode on CRTC %d:\n", nv_crtc->index); 264 NV_DEBUG_KMS(dev, "Output mode on CRTC %d:\n", nv_crtc->index);
265 drm_mode_debug_printmodeline(output_mode); 265 drm_mode_debug_printmodeline(output_mode);
266 266
267 /* Initialize the FP registers in this CRTC. */ 267 /* Initialize the FP registers in this CRTC. */
@@ -413,7 +413,9 @@ static void nv04_dfp_commit(struct drm_encoder *encoder)
413 struct dcb_entry *dcbe = nv_encoder->dcb; 413 struct dcb_entry *dcbe = nv_encoder->dcb;
414 int head = nouveau_crtc(encoder->crtc)->index; 414 int head = nouveau_crtc(encoder->crtc)->index;
415 415
416 NV_TRACE(dev, "%s called for encoder %d\n", __func__, nv_encoder->dcb->index); 416 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
417 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
418 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
417 419
418 if (dcbe->type == OUTPUT_TMDS) 420 if (dcbe->type == OUTPUT_TMDS)
419 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock); 421 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
@@ -550,7 +552,7 @@ static void nv04_dfp_destroy(struct drm_encoder *encoder)
550{ 552{
551 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 553 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
552 554
553 NV_DEBUG(encoder->dev, "\n"); 555 NV_DEBUG_KMS(encoder->dev, "\n");
554 556
555 drm_encoder_cleanup(encoder); 557 drm_encoder_cleanup(encoder);
556 kfree(nv_encoder); 558 kfree(nv_encoder);
diff --git a/drivers/gpu/drm/nouveau/nv04_display.c b/drivers/gpu/drm/nouveau/nv04_display.c
index b47c757ff48b..ef77215fa5b9 100644
--- a/drivers/gpu/drm/nouveau/nv04_display.c
+++ b/drivers/gpu/drm/nouveau/nv04_display.c
@@ -99,10 +99,11 @@ nv04_display_create(struct drm_device *dev)
99 uint16_t connector[16] = { 0 }; 99 uint16_t connector[16] = { 0 };
100 int i, ret; 100 int i, ret;
101 101
102 NV_DEBUG(dev, "\n"); 102 NV_DEBUG_KMS(dev, "\n");
103 103
104 if (nv_two_heads(dev)) 104 if (nv_two_heads(dev))
105 nv04_display_store_initial_head_owner(dev); 105 nv04_display_store_initial_head_owner(dev);
106 nouveau_hw_save_vga_fonts(dev, 1);
106 107
107 drm_mode_config_init(dev); 108 drm_mode_config_init(dev);
108 drm_mode_create_scaling_mode_property(dev); 109 drm_mode_create_scaling_mode_property(dev);
@@ -203,8 +204,6 @@ nv04_display_create(struct drm_device *dev)
203 /* Save previous state */ 204 /* Save previous state */
204 NVLockVgaCrtcs(dev, false); 205 NVLockVgaCrtcs(dev, false);
205 206
206 nouveau_hw_save_vga_fonts(dev, 1);
207
208 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 207 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
209 crtc->funcs->save(crtc); 208 crtc->funcs->save(crtc);
210 209
@@ -223,7 +222,7 @@ nv04_display_destroy(struct drm_device *dev)
223 struct drm_encoder *encoder; 222 struct drm_encoder *encoder;
224 struct drm_crtc *crtc; 223 struct drm_crtc *crtc;
225 224
226 NV_DEBUG(dev, "\n"); 225 NV_DEBUG_KMS(dev, "\n");
227 226
228 /* Turn every CRTC off. */ 227 /* Turn every CRTC off. */
229 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 228 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
@@ -246,9 +245,9 @@ nv04_display_destroy(struct drm_device *dev)
246 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 245 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
247 crtc->funcs->restore(crtc); 246 crtc->funcs->restore(crtc);
248 247
249 nouveau_hw_save_vga_fonts(dev, 0);
250
251 drm_mode_config_cleanup(dev); 248 drm_mode_config_cleanup(dev);
249
250 nouveau_hw_save_vga_fonts(dev, 0);
252} 251}
253 252
254void 253void
diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c
index 09a31071ee58..d910873c1368 100644
--- a/drivers/gpu/drm/nouveau/nv04_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c
@@ -39,8 +39,7 @@ nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
39 return; 39 return;
40 40
41 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 4)) { 41 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 4)) {
42 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 42 nouveau_fbcon_gpu_lockup(info);
43 info->flags |= FBINFO_HWACCEL_DISABLED;
44 } 43 }
45 44
46 if (info->flags & FBINFO_HWACCEL_DISABLED) { 45 if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -62,14 +61,12 @@ nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
62 struct drm_device *dev = par->dev; 61 struct drm_device *dev = par->dev;
63 struct drm_nouveau_private *dev_priv = dev->dev_private; 62 struct drm_nouveau_private *dev_priv = dev->dev_private;
64 struct nouveau_channel *chan = dev_priv->channel; 63 struct nouveau_channel *chan = dev_priv->channel;
65 uint32_t color = ((uint32_t *) info->pseudo_palette)[rect->color];
66 64
67 if (info->state != FBINFO_STATE_RUNNING) 65 if (info->state != FBINFO_STATE_RUNNING)
68 return; 66 return;
69 67
70 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 7)) { 68 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 7)) {
71 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 69 nouveau_fbcon_gpu_lockup(info);
72 info->flags |= FBINFO_HWACCEL_DISABLED;
73 } 70 }
74 71
75 if (info->flags & FBINFO_HWACCEL_DISABLED) { 72 if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -80,7 +77,11 @@ nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
80 BEGIN_RING(chan, NvSubGdiRect, 0x02fc, 1); 77 BEGIN_RING(chan, NvSubGdiRect, 0x02fc, 1);
81 OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3); 78 OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3);
82 BEGIN_RING(chan, NvSubGdiRect, 0x03fc, 1); 79 BEGIN_RING(chan, NvSubGdiRect, 0x03fc, 1);
83 OUT_RING(chan, color); 80 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
81 info->fix.visual == FB_VISUAL_DIRECTCOLOR)
82 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
83 else
84 OUT_RING(chan, rect->color);
84 BEGIN_RING(chan, NvSubGdiRect, 0x0400, 2); 85 BEGIN_RING(chan, NvSubGdiRect, 0x0400, 2);
85 OUT_RING(chan, (rect->dx << 16) | rect->dy); 86 OUT_RING(chan, (rect->dx << 16) | rect->dy);
86 OUT_RING(chan, (rect->width << 16) | rect->height); 87 OUT_RING(chan, (rect->width << 16) | rect->height);
@@ -109,8 +110,7 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
109 } 110 }
110 111
111 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 8)) { 112 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 8)) {
112 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 113 nouveau_fbcon_gpu_lockup(info);
113 info->flags |= FBINFO_HWACCEL_DISABLED;
114 } 114 }
115 115
116 if (info->flags & FBINFO_HWACCEL_DISABLED) { 116 if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -144,8 +144,7 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
144 int iter_len = dsize > 128 ? 128 : dsize; 144 int iter_len = dsize > 128 ? 128 : dsize;
145 145
146 if (RING_SPACE(chan, iter_len + 1)) { 146 if (RING_SPACE(chan, iter_len + 1)) {
147 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 147 nouveau_fbcon_gpu_lockup(info);
148 info->flags |= FBINFO_HWACCEL_DISABLED;
149 cfb_imageblit(info, image); 148 cfb_imageblit(info, image);
150 return; 149 return;
151 } 150 }
@@ -184,6 +183,7 @@ nv04_fbcon_accel_init(struct fb_info *info)
184 struct drm_device *dev = par->dev; 183 struct drm_device *dev = par->dev;
185 struct drm_nouveau_private *dev_priv = dev->dev_private; 184 struct drm_nouveau_private *dev_priv = dev->dev_private;
186 struct nouveau_channel *chan = dev_priv->channel; 185 struct nouveau_channel *chan = dev_priv->channel;
186 const int sub = NvSubCtxSurf2D;
187 int surface_fmt, pattern_fmt, rect_fmt; 187 int surface_fmt, pattern_fmt, rect_fmt;
188 int ret; 188 int ret;
189 189
@@ -242,30 +242,29 @@ nv04_fbcon_accel_init(struct fb_info *info)
242 return ret; 242 return ret;
243 243
244 if (RING_SPACE(chan, 49)) { 244 if (RING_SPACE(chan, 49)) {
245 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 245 nouveau_fbcon_gpu_lockup(info);
246 info->flags |= FBINFO_HWACCEL_DISABLED;
247 return 0; 246 return 0;
248 } 247 }
249 248
250 BEGIN_RING(chan, 1, 0x0000, 1); 249 BEGIN_RING(chan, sub, 0x0000, 1);
251 OUT_RING(chan, NvCtxSurf2D); 250 OUT_RING(chan, NvCtxSurf2D);
252 BEGIN_RING(chan, 1, 0x0184, 2); 251 BEGIN_RING(chan, sub, 0x0184, 2);
253 OUT_RING(chan, NvDmaFB); 252 OUT_RING(chan, NvDmaFB);
254 OUT_RING(chan, NvDmaFB); 253 OUT_RING(chan, NvDmaFB);
255 BEGIN_RING(chan, 1, 0x0300, 4); 254 BEGIN_RING(chan, sub, 0x0300, 4);
256 OUT_RING(chan, surface_fmt); 255 OUT_RING(chan, surface_fmt);
257 OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16)); 256 OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16));
258 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); 257 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
259 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); 258 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
260 259
261 BEGIN_RING(chan, 1, 0x0000, 1); 260 BEGIN_RING(chan, sub, 0x0000, 1);
262 OUT_RING(chan, NvRop); 261 OUT_RING(chan, NvRop);
263 BEGIN_RING(chan, 1, 0x0300, 1); 262 BEGIN_RING(chan, sub, 0x0300, 1);
264 OUT_RING(chan, 0x55); 263 OUT_RING(chan, 0x55);
265 264
266 BEGIN_RING(chan, 1, 0x0000, 1); 265 BEGIN_RING(chan, sub, 0x0000, 1);
267 OUT_RING(chan, NvImagePatt); 266 OUT_RING(chan, NvImagePatt);
268 BEGIN_RING(chan, 1, 0x0300, 8); 267 BEGIN_RING(chan, sub, 0x0300, 8);
269 OUT_RING(chan, pattern_fmt); 268 OUT_RING(chan, pattern_fmt);
270#ifdef __BIG_ENDIAN 269#ifdef __BIG_ENDIAN
271 OUT_RING(chan, 2); 270 OUT_RING(chan, 2);
@@ -279,9 +278,9 @@ nv04_fbcon_accel_init(struct fb_info *info)
279 OUT_RING(chan, ~0); 278 OUT_RING(chan, ~0);
280 OUT_RING(chan, ~0); 279 OUT_RING(chan, ~0);
281 280
282 BEGIN_RING(chan, 1, 0x0000, 1); 281 BEGIN_RING(chan, sub, 0x0000, 1);
283 OUT_RING(chan, NvClipRect); 282 OUT_RING(chan, NvClipRect);
284 BEGIN_RING(chan, 1, 0x0300, 2); 283 BEGIN_RING(chan, sub, 0x0300, 2);
285 OUT_RING(chan, 0); 284 OUT_RING(chan, 0);
286 OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual); 285 OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual);
287 286
diff --git a/drivers/gpu/drm/nouveau/nv04_fifo.c b/drivers/gpu/drm/nouveau/nv04_fifo.c
index 0c3cd53c7313..f31347b8c9b0 100644
--- a/drivers/gpu/drm/nouveau/nv04_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv04_fifo.c
@@ -71,6 +71,40 @@ nv04_fifo_reassign(struct drm_device *dev, bool enable)
71 return (reassign == 1); 71 return (reassign == 1);
72} 72}
73 73
74bool
75nv04_fifo_cache_flush(struct drm_device *dev)
76{
77 struct drm_nouveau_private *dev_priv = dev->dev_private;
78 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
79 uint64_t start = ptimer->read(dev);
80
81 do {
82 if (nv_rd32(dev, NV03_PFIFO_CACHE1_GET) ==
83 nv_rd32(dev, NV03_PFIFO_CACHE1_PUT))
84 return true;
85
86 } while (ptimer->read(dev) - start < 100000000);
87
88 NV_ERROR(dev, "Timeout flushing the PFIFO cache.\n");
89
90 return false;
91}
92
93bool
94nv04_fifo_cache_pull(struct drm_device *dev, bool enable)
95{
96 uint32_t pull = nv_rd32(dev, NV04_PFIFO_CACHE1_PULL0);
97
98 if (enable) {
99 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull | 1);
100 } else {
101 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull & ~1);
102 nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
103 }
104
105 return !!(pull & 1);
106}
107
74int 108int
75nv04_fifo_channel_id(struct drm_device *dev) 109nv04_fifo_channel_id(struct drm_device *dev)
76{ 110{
diff --git a/drivers/gpu/drm/nouveau/nv04_graph.c b/drivers/gpu/drm/nouveau/nv04_graph.c
index 396ee92118f6..e260986ea65a 100644
--- a/drivers/gpu/drm/nouveau/nv04_graph.c
+++ b/drivers/gpu/drm/nouveau/nv04_graph.c
@@ -28,6 +28,10 @@
28#include "nouveau_drv.h" 28#include "nouveau_drv.h"
29 29
30static uint32_t nv04_graph_ctx_regs[] = { 30static uint32_t nv04_graph_ctx_regs[] = {
31 0x0040053c,
32 0x00400544,
33 0x00400540,
34 0x00400548,
31 NV04_PGRAPH_CTX_SWITCH1, 35 NV04_PGRAPH_CTX_SWITCH1,
32 NV04_PGRAPH_CTX_SWITCH2, 36 NV04_PGRAPH_CTX_SWITCH2,
33 NV04_PGRAPH_CTX_SWITCH3, 37 NV04_PGRAPH_CTX_SWITCH3,
@@ -102,69 +106,69 @@ static uint32_t nv04_graph_ctx_regs[] = {
102 NV04_PGRAPH_PATT_COLOR0, 106 NV04_PGRAPH_PATT_COLOR0,
103 NV04_PGRAPH_PATT_COLOR1, 107 NV04_PGRAPH_PATT_COLOR1,
104 NV04_PGRAPH_PATT_COLORRAM+0x00, 108 NV04_PGRAPH_PATT_COLORRAM+0x00,
105 NV04_PGRAPH_PATT_COLORRAM+0x01,
106 NV04_PGRAPH_PATT_COLORRAM+0x02,
107 NV04_PGRAPH_PATT_COLORRAM+0x03,
108 NV04_PGRAPH_PATT_COLORRAM+0x04, 109 NV04_PGRAPH_PATT_COLORRAM+0x04,
109 NV04_PGRAPH_PATT_COLORRAM+0x05,
110 NV04_PGRAPH_PATT_COLORRAM+0x06,
111 NV04_PGRAPH_PATT_COLORRAM+0x07,
112 NV04_PGRAPH_PATT_COLORRAM+0x08, 110 NV04_PGRAPH_PATT_COLORRAM+0x08,
113 NV04_PGRAPH_PATT_COLORRAM+0x09, 111 NV04_PGRAPH_PATT_COLORRAM+0x0c,
114 NV04_PGRAPH_PATT_COLORRAM+0x0A,
115 NV04_PGRAPH_PATT_COLORRAM+0x0B,
116 NV04_PGRAPH_PATT_COLORRAM+0x0C,
117 NV04_PGRAPH_PATT_COLORRAM+0x0D,
118 NV04_PGRAPH_PATT_COLORRAM+0x0E,
119 NV04_PGRAPH_PATT_COLORRAM+0x0F,
120 NV04_PGRAPH_PATT_COLORRAM+0x10, 112 NV04_PGRAPH_PATT_COLORRAM+0x10,
121 NV04_PGRAPH_PATT_COLORRAM+0x11,
122 NV04_PGRAPH_PATT_COLORRAM+0x12,
123 NV04_PGRAPH_PATT_COLORRAM+0x13,
124 NV04_PGRAPH_PATT_COLORRAM+0x14, 113 NV04_PGRAPH_PATT_COLORRAM+0x14,
125 NV04_PGRAPH_PATT_COLORRAM+0x15,
126 NV04_PGRAPH_PATT_COLORRAM+0x16,
127 NV04_PGRAPH_PATT_COLORRAM+0x17,
128 NV04_PGRAPH_PATT_COLORRAM+0x18, 114 NV04_PGRAPH_PATT_COLORRAM+0x18,
129 NV04_PGRAPH_PATT_COLORRAM+0x19, 115 NV04_PGRAPH_PATT_COLORRAM+0x1c,
130 NV04_PGRAPH_PATT_COLORRAM+0x1A,
131 NV04_PGRAPH_PATT_COLORRAM+0x1B,
132 NV04_PGRAPH_PATT_COLORRAM+0x1C,
133 NV04_PGRAPH_PATT_COLORRAM+0x1D,
134 NV04_PGRAPH_PATT_COLORRAM+0x1E,
135 NV04_PGRAPH_PATT_COLORRAM+0x1F,
136 NV04_PGRAPH_PATT_COLORRAM+0x20, 116 NV04_PGRAPH_PATT_COLORRAM+0x20,
137 NV04_PGRAPH_PATT_COLORRAM+0x21,
138 NV04_PGRAPH_PATT_COLORRAM+0x22,
139 NV04_PGRAPH_PATT_COLORRAM+0x23,
140 NV04_PGRAPH_PATT_COLORRAM+0x24, 117 NV04_PGRAPH_PATT_COLORRAM+0x24,
141 NV04_PGRAPH_PATT_COLORRAM+0x25,
142 NV04_PGRAPH_PATT_COLORRAM+0x26,
143 NV04_PGRAPH_PATT_COLORRAM+0x27,
144 NV04_PGRAPH_PATT_COLORRAM+0x28, 118 NV04_PGRAPH_PATT_COLORRAM+0x28,
145 NV04_PGRAPH_PATT_COLORRAM+0x29, 119 NV04_PGRAPH_PATT_COLORRAM+0x2c,
146 NV04_PGRAPH_PATT_COLORRAM+0x2A,
147 NV04_PGRAPH_PATT_COLORRAM+0x2B,
148 NV04_PGRAPH_PATT_COLORRAM+0x2C,
149 NV04_PGRAPH_PATT_COLORRAM+0x2D,
150 NV04_PGRAPH_PATT_COLORRAM+0x2E,
151 NV04_PGRAPH_PATT_COLORRAM+0x2F,
152 NV04_PGRAPH_PATT_COLORRAM+0x30, 120 NV04_PGRAPH_PATT_COLORRAM+0x30,
153 NV04_PGRAPH_PATT_COLORRAM+0x31,
154 NV04_PGRAPH_PATT_COLORRAM+0x32,
155 NV04_PGRAPH_PATT_COLORRAM+0x33,
156 NV04_PGRAPH_PATT_COLORRAM+0x34, 121 NV04_PGRAPH_PATT_COLORRAM+0x34,
157 NV04_PGRAPH_PATT_COLORRAM+0x35,
158 NV04_PGRAPH_PATT_COLORRAM+0x36,
159 NV04_PGRAPH_PATT_COLORRAM+0x37,
160 NV04_PGRAPH_PATT_COLORRAM+0x38, 122 NV04_PGRAPH_PATT_COLORRAM+0x38,
161 NV04_PGRAPH_PATT_COLORRAM+0x39, 123 NV04_PGRAPH_PATT_COLORRAM+0x3c,
162 NV04_PGRAPH_PATT_COLORRAM+0x3A, 124 NV04_PGRAPH_PATT_COLORRAM+0x40,
163 NV04_PGRAPH_PATT_COLORRAM+0x3B, 125 NV04_PGRAPH_PATT_COLORRAM+0x44,
164 NV04_PGRAPH_PATT_COLORRAM+0x3C, 126 NV04_PGRAPH_PATT_COLORRAM+0x48,
165 NV04_PGRAPH_PATT_COLORRAM+0x3D, 127 NV04_PGRAPH_PATT_COLORRAM+0x4c,
166 NV04_PGRAPH_PATT_COLORRAM+0x3E, 128 NV04_PGRAPH_PATT_COLORRAM+0x50,
167 NV04_PGRAPH_PATT_COLORRAM+0x3F, 129 NV04_PGRAPH_PATT_COLORRAM+0x54,
130 NV04_PGRAPH_PATT_COLORRAM+0x58,
131 NV04_PGRAPH_PATT_COLORRAM+0x5c,
132 NV04_PGRAPH_PATT_COLORRAM+0x60,
133 NV04_PGRAPH_PATT_COLORRAM+0x64,
134 NV04_PGRAPH_PATT_COLORRAM+0x68,
135 NV04_PGRAPH_PATT_COLORRAM+0x6c,
136 NV04_PGRAPH_PATT_COLORRAM+0x70,
137 NV04_PGRAPH_PATT_COLORRAM+0x74,
138 NV04_PGRAPH_PATT_COLORRAM+0x78,
139 NV04_PGRAPH_PATT_COLORRAM+0x7c,
140 NV04_PGRAPH_PATT_COLORRAM+0x80,
141 NV04_PGRAPH_PATT_COLORRAM+0x84,
142 NV04_PGRAPH_PATT_COLORRAM+0x88,
143 NV04_PGRAPH_PATT_COLORRAM+0x8c,
144 NV04_PGRAPH_PATT_COLORRAM+0x90,
145 NV04_PGRAPH_PATT_COLORRAM+0x94,
146 NV04_PGRAPH_PATT_COLORRAM+0x98,
147 NV04_PGRAPH_PATT_COLORRAM+0x9c,
148 NV04_PGRAPH_PATT_COLORRAM+0xa0,
149 NV04_PGRAPH_PATT_COLORRAM+0xa4,
150 NV04_PGRAPH_PATT_COLORRAM+0xa8,
151 NV04_PGRAPH_PATT_COLORRAM+0xac,
152 NV04_PGRAPH_PATT_COLORRAM+0xb0,
153 NV04_PGRAPH_PATT_COLORRAM+0xb4,
154 NV04_PGRAPH_PATT_COLORRAM+0xb8,
155 NV04_PGRAPH_PATT_COLORRAM+0xbc,
156 NV04_PGRAPH_PATT_COLORRAM+0xc0,
157 NV04_PGRAPH_PATT_COLORRAM+0xc4,
158 NV04_PGRAPH_PATT_COLORRAM+0xc8,
159 NV04_PGRAPH_PATT_COLORRAM+0xcc,
160 NV04_PGRAPH_PATT_COLORRAM+0xd0,
161 NV04_PGRAPH_PATT_COLORRAM+0xd4,
162 NV04_PGRAPH_PATT_COLORRAM+0xd8,
163 NV04_PGRAPH_PATT_COLORRAM+0xdc,
164 NV04_PGRAPH_PATT_COLORRAM+0xe0,
165 NV04_PGRAPH_PATT_COLORRAM+0xe4,
166 NV04_PGRAPH_PATT_COLORRAM+0xe8,
167 NV04_PGRAPH_PATT_COLORRAM+0xec,
168 NV04_PGRAPH_PATT_COLORRAM+0xf0,
169 NV04_PGRAPH_PATT_COLORRAM+0xf4,
170 NV04_PGRAPH_PATT_COLORRAM+0xf8,
171 NV04_PGRAPH_PATT_COLORRAM+0xfc,
168 NV04_PGRAPH_PATTERN, 172 NV04_PGRAPH_PATTERN,
169 0x0040080c, 173 0x0040080c,
170 NV04_PGRAPH_PATTERN_SHAPE, 174 NV04_PGRAPH_PATTERN_SHAPE,
@@ -247,14 +251,6 @@ static uint32_t nv04_graph_ctx_regs[] = {
247 0x004004f8, 251 0x004004f8,
248 0x0040047c, 252 0x0040047c,
249 0x004004fc, 253 0x004004fc,
250 0x0040053c,
251 0x00400544,
252 0x00400540,
253 0x00400548,
254 0x00400560,
255 0x00400568,
256 0x00400564,
257 0x0040056c,
258 0x00400534, 254 0x00400534,
259 0x00400538, 255 0x00400538,
260 0x00400514, 256 0x00400514,
@@ -341,9 +337,8 @@ static uint32_t nv04_graph_ctx_regs[] = {
341 0x00400500, 337 0x00400500,
342 0x00400504, 338 0x00400504,
343 NV04_PGRAPH_VALID1, 339 NV04_PGRAPH_VALID1,
344 NV04_PGRAPH_VALID2 340 NV04_PGRAPH_VALID2,
345 341 NV04_PGRAPH_DEBUG_3
346
347}; 342};
348 343
349struct graph_state { 344struct graph_state {
@@ -388,6 +383,18 @@ nv04_graph_context_switch(struct drm_device *dev)
388 pgraph->fifo_access(dev, true); 383 pgraph->fifo_access(dev, true);
389} 384}
390 385
386static uint32_t *ctx_reg(struct graph_state *ctx, uint32_t reg)
387{
388 int i;
389
390 for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) {
391 if (nv04_graph_ctx_regs[i] == reg)
392 return &ctx->nv04[i];
393 }
394
395 return NULL;
396}
397
391int nv04_graph_create_context(struct nouveau_channel *chan) 398int nv04_graph_create_context(struct nouveau_channel *chan)
392{ 399{
393 struct graph_state *pgraph_ctx; 400 struct graph_state *pgraph_ctx;
@@ -398,15 +405,8 @@ int nv04_graph_create_context(struct nouveau_channel *chan)
398 if (pgraph_ctx == NULL) 405 if (pgraph_ctx == NULL)
399 return -ENOMEM; 406 return -ENOMEM;
400 407
401 /* dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; */ 408 *ctx_reg(pgraph_ctx, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31;
402 pgraph_ctx->nv04[0] = 0x0001ffff; 409
403 /* is it really needed ??? */
404#if 0
405 dev_priv->fifos[channel].pgraph_ctx[1] =
406 nv_rd32(dev, NV_PGRAPH_DEBUG_4);
407 dev_priv->fifos[channel].pgraph_ctx[2] =
408 nv_rd32(dev, 0x004006b0);
409#endif
410 return 0; 410 return 0;
411} 411}
412 412
@@ -429,9 +429,13 @@ int nv04_graph_load_context(struct nouveau_channel *chan)
429 nv_wr32(dev, nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]); 429 nv_wr32(dev, nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]);
430 430
431 nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10010100); 431 nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
432 nv_wr32(dev, NV04_PGRAPH_CTX_USER, chan->id << 24); 432
433 tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
434 nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp | chan->id << 24);
435
433 tmp = nv_rd32(dev, NV04_PGRAPH_FFINTFC_ST2); 436 tmp = nv_rd32(dev, NV04_PGRAPH_FFINTFC_ST2);
434 nv_wr32(dev, NV04_PGRAPH_FFINTFC_ST2, tmp & 0x000fffff); 437 nv_wr32(dev, NV04_PGRAPH_FFINTFC_ST2, tmp & 0x000fffff);
438
435 return 0; 439 return 0;
436} 440}
437 441
@@ -494,7 +498,7 @@ int nv04_graph_init(struct drm_device *dev)
494 nv_wr32(dev, NV04_PGRAPH_STATE , 0xFFFFFFFF); 498 nv_wr32(dev, NV04_PGRAPH_STATE , 0xFFFFFFFF);
495 nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL , 0x10000100); 499 nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL , 0x10000100);
496 tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff; 500 tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
497 tmp |= dev_priv->engine.fifo.channels << 24; 501 tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
498 nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp); 502 nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp);
499 503
500 /* These don't belong here, they're part of a per-channel context */ 504 /* These don't belong here, they're part of a per-channel context */
@@ -533,7 +537,7 @@ nv04_graph_mthd_set_operation(struct nouveau_channel *chan, int grclass,
533 int mthd, uint32_t data) 537 int mthd, uint32_t data)
534{ 538{
535 struct drm_device *dev = chan->dev; 539 struct drm_device *dev = chan->dev;
536 uint32_t instance = nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff; 540 uint32_t instance = (nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff) << 4;
537 int subc = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; 541 int subc = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
538 uint32_t tmp; 542 uint32_t tmp;
539 543
@@ -543,11 +547,11 @@ nv04_graph_mthd_set_operation(struct nouveau_channel *chan, int grclass,
543 547
544 nv_wi32(dev, instance, tmp); 548 nv_wi32(dev, instance, tmp);
545 nv_wr32(dev, NV04_PGRAPH_CTX_SWITCH1, tmp); 549 nv_wr32(dev, NV04_PGRAPH_CTX_SWITCH1, tmp);
546 nv_wr32(dev, NV04_PGRAPH_CTX_CACHE1 + subc, tmp); 550 nv_wr32(dev, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp);
547 return 0; 551 return 0;
548} 552}
549 553
550static struct nouveau_pgraph_object_method nv04_graph_mthds_m2mf[] = { 554static struct nouveau_pgraph_object_method nv04_graph_mthds_sw[] = {
551 { 0x0150, nv04_graph_mthd_set_ref }, 555 { 0x0150, nv04_graph_mthd_set_ref },
552 {} 556 {}
553}; 557};
@@ -558,7 +562,7 @@ static struct nouveau_pgraph_object_method nv04_graph_mthds_set_operation[] = {
558}; 562};
559 563
560struct nouveau_pgraph_object_class nv04_graph_grclass[] = { 564struct nouveau_pgraph_object_class nv04_graph_grclass[] = {
561 { 0x0039, false, nv04_graph_mthds_m2mf }, 565 { 0x0039, false, NULL },
562 { 0x004a, false, nv04_graph_mthds_set_operation }, /* gdirect */ 566 { 0x004a, false, nv04_graph_mthds_set_operation }, /* gdirect */
563 { 0x005f, false, nv04_graph_mthds_set_operation }, /* imageblit */ 567 { 0x005f, false, nv04_graph_mthds_set_operation }, /* imageblit */
564 { 0x0061, false, nv04_graph_mthds_set_operation }, /* ifc */ 568 { 0x0061, false, nv04_graph_mthds_set_operation }, /* ifc */
@@ -574,6 +578,7 @@ struct nouveau_pgraph_object_class nv04_graph_grclass[] = {
574 { 0x0053, false, NULL }, /* surf3d */ 578 { 0x0053, false, NULL }, /* surf3d */
575 { 0x0054, false, NULL }, /* tex_tri */ 579 { 0x0054, false, NULL }, /* tex_tri */
576 { 0x0055, false, NULL }, /* multitex_tri */ 580 { 0x0055, false, NULL }, /* multitex_tri */
581 { 0x506e, true, nv04_graph_mthds_sw },
577 {} 582 {}
578}; 583};
579 584
diff --git a/drivers/gpu/drm/nouveau/nv04_instmem.c b/drivers/gpu/drm/nouveau/nv04_instmem.c
index a20c206625a2..a3b9563a6f60 100644
--- a/drivers/gpu/drm/nouveau/nv04_instmem.c
+++ b/drivers/gpu/drm/nouveau/nv04_instmem.c
@@ -30,7 +30,7 @@ nv04_instmem_determine_amount(struct drm_device *dev)
30 * of vram. For now, only reserve a small piece until we know 30 * of vram. For now, only reserve a small piece until we know
31 * more about what each chipset requires. 31 * more about what each chipset requires.
32 */ 32 */
33 switch (dev_priv->chipset & 0xf0) { 33 switch (dev_priv->chipset) {
34 case 0x40: 34 case 0x40:
35 case 0x47: 35 case 0x47:
36 case 0x49: 36 case 0x49:
diff --git a/drivers/gpu/drm/nouveau/nv10_fb.c b/drivers/gpu/drm/nouveau/nv10_fb.c
index 79e2d104d70a..cc5cda44e501 100644
--- a/drivers/gpu/drm/nouveau/nv10_fb.c
+++ b/drivers/gpu/drm/nouveau/nv10_fb.c
@@ -3,17 +3,37 @@
3#include "nouveau_drv.h" 3#include "nouveau_drv.h"
4#include "nouveau_drm.h" 4#include "nouveau_drm.h"
5 5
6void
7nv10_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
8 uint32_t size, uint32_t pitch)
9{
10 struct drm_nouveau_private *dev_priv = dev->dev_private;
11 uint32_t limit = max(1u, addr + size) - 1;
12
13 if (pitch) {
14 if (dev_priv->card_type >= NV_20)
15 addr |= 1;
16 else
17 addr |= 1 << 31;
18 }
19
20 nv_wr32(dev, NV10_PFB_TLIMIT(i), limit);
21 nv_wr32(dev, NV10_PFB_TSIZE(i), pitch);
22 nv_wr32(dev, NV10_PFB_TILE(i), addr);
23}
24
6int 25int
7nv10_fb_init(struct drm_device *dev) 26nv10_fb_init(struct drm_device *dev)
8{ 27{
9 uint32_t fb_bar_size; 28 struct drm_nouveau_private *dev_priv = dev->dev_private;
29 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
10 int i; 30 int i;
11 31
12 fb_bar_size = drm_get_resource_len(dev, 0) - 1; 32 pfb->num_tiles = NV10_PFB_TILE__SIZE;
13 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) { 33
14 nv_wr32(dev, NV10_PFB_TILE(i), 0); 34 /* Turn all the tiling regions off. */
15 nv_wr32(dev, NV10_PFB_TLIMIT(i), fb_bar_size); 35 for (i = 0; i < pfb->num_tiles; i++)
16 } 36 pfb->set_region_tiling(dev, i, 0, 0, 0);
17 37
18 return 0; 38 return 0;
19} 39}
diff --git a/drivers/gpu/drm/nouveau/nv10_graph.c b/drivers/gpu/drm/nouveau/nv10_graph.c
index 6bf6804bb0ef..fcf2cdd19493 100644
--- a/drivers/gpu/drm/nouveau/nv10_graph.c
+++ b/drivers/gpu/drm/nouveau/nv10_graph.c
@@ -389,49 +389,50 @@ struct graph_state {
389 int nv10[ARRAY_SIZE(nv10_graph_ctx_regs)]; 389 int nv10[ARRAY_SIZE(nv10_graph_ctx_regs)];
390 int nv17[ARRAY_SIZE(nv17_graph_ctx_regs)]; 390 int nv17[ARRAY_SIZE(nv17_graph_ctx_regs)];
391 struct pipe_state pipe_state; 391 struct pipe_state pipe_state;
392 uint32_t lma_window[4];
392}; 393};
393 394
395#define PIPE_SAVE(dev, state, addr) \
396 do { \
397 int __i; \
398 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \
399 for (__i = 0; __i < ARRAY_SIZE(state); __i++) \
400 state[__i] = nv_rd32(dev, NV10_PGRAPH_PIPE_DATA); \
401 } while (0)
402
403#define PIPE_RESTORE(dev, state, addr) \
404 do { \
405 int __i; \
406 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \
407 for (__i = 0; __i < ARRAY_SIZE(state); __i++) \
408 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, state[__i]); \
409 } while (0)
410
394static void nv10_graph_save_pipe(struct nouveau_channel *chan) 411static void nv10_graph_save_pipe(struct nouveau_channel *chan)
395{ 412{
396 struct drm_device *dev = chan->dev; 413 struct drm_device *dev = chan->dev;
397 struct graph_state *pgraph_ctx = chan->pgraph_ctx; 414 struct graph_state *pgraph_ctx = chan->pgraph_ctx;
398 struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state; 415 struct pipe_state *pipe = &pgraph_ctx->pipe_state;
399 int i; 416
400#define PIPE_SAVE(addr) \ 417 PIPE_SAVE(dev, pipe->pipe_0x4400, 0x4400);
401 do { \ 418 PIPE_SAVE(dev, pipe->pipe_0x0200, 0x0200);
402 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \ 419 PIPE_SAVE(dev, pipe->pipe_0x6400, 0x6400);
403 for (i = 0; i < ARRAY_SIZE(fifo_pipe_state->pipe_##addr); i++) \ 420 PIPE_SAVE(dev, pipe->pipe_0x6800, 0x6800);
404 fifo_pipe_state->pipe_##addr[i] = nv_rd32(dev, NV10_PGRAPH_PIPE_DATA); \ 421 PIPE_SAVE(dev, pipe->pipe_0x6c00, 0x6c00);
405 } while (0) 422 PIPE_SAVE(dev, pipe->pipe_0x7000, 0x7000);
406 423 PIPE_SAVE(dev, pipe->pipe_0x7400, 0x7400);
407 PIPE_SAVE(0x4400); 424 PIPE_SAVE(dev, pipe->pipe_0x7800, 0x7800);
408 PIPE_SAVE(0x0200); 425 PIPE_SAVE(dev, pipe->pipe_0x0040, 0x0040);
409 PIPE_SAVE(0x6400); 426 PIPE_SAVE(dev, pipe->pipe_0x0000, 0x0000);
410 PIPE_SAVE(0x6800);
411 PIPE_SAVE(0x6c00);
412 PIPE_SAVE(0x7000);
413 PIPE_SAVE(0x7400);
414 PIPE_SAVE(0x7800);
415 PIPE_SAVE(0x0040);
416 PIPE_SAVE(0x0000);
417
418#undef PIPE_SAVE
419} 427}
420 428
421static void nv10_graph_load_pipe(struct nouveau_channel *chan) 429static void nv10_graph_load_pipe(struct nouveau_channel *chan)
422{ 430{
423 struct drm_device *dev = chan->dev; 431 struct drm_device *dev = chan->dev;
424 struct graph_state *pgraph_ctx = chan->pgraph_ctx; 432 struct graph_state *pgraph_ctx = chan->pgraph_ctx;
425 struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state; 433 struct pipe_state *pipe = &pgraph_ctx->pipe_state;
426 int i;
427 uint32_t xfmode0, xfmode1; 434 uint32_t xfmode0, xfmode1;
428#define PIPE_RESTORE(addr) \ 435 int i;
429 do { \
430 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \
431 for (i = 0; i < ARRAY_SIZE(fifo_pipe_state->pipe_##addr); i++) \
432 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, fifo_pipe_state->pipe_##addr[i]); \
433 } while (0)
434
435 436
436 nouveau_wait_for_idle(dev); 437 nouveau_wait_for_idle(dev);
437 /* XXX check haiku comments */ 438 /* XXX check haiku comments */
@@ -457,24 +458,22 @@ static void nv10_graph_load_pipe(struct nouveau_channel *chan)
457 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000008); 458 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000008);
458 459
459 460
460 PIPE_RESTORE(0x0200); 461 PIPE_RESTORE(dev, pipe->pipe_0x0200, 0x0200);
461 nouveau_wait_for_idle(dev); 462 nouveau_wait_for_idle(dev);
462 463
463 /* restore XFMODE */ 464 /* restore XFMODE */
464 nv_wr32(dev, NV10_PGRAPH_XFMODE0, xfmode0); 465 nv_wr32(dev, NV10_PGRAPH_XFMODE0, xfmode0);
465 nv_wr32(dev, NV10_PGRAPH_XFMODE1, xfmode1); 466 nv_wr32(dev, NV10_PGRAPH_XFMODE1, xfmode1);
466 PIPE_RESTORE(0x6400); 467 PIPE_RESTORE(dev, pipe->pipe_0x6400, 0x6400);
467 PIPE_RESTORE(0x6800); 468 PIPE_RESTORE(dev, pipe->pipe_0x6800, 0x6800);
468 PIPE_RESTORE(0x6c00); 469 PIPE_RESTORE(dev, pipe->pipe_0x6c00, 0x6c00);
469 PIPE_RESTORE(0x7000); 470 PIPE_RESTORE(dev, pipe->pipe_0x7000, 0x7000);
470 PIPE_RESTORE(0x7400); 471 PIPE_RESTORE(dev, pipe->pipe_0x7400, 0x7400);
471 PIPE_RESTORE(0x7800); 472 PIPE_RESTORE(dev, pipe->pipe_0x7800, 0x7800);
472 PIPE_RESTORE(0x4400); 473 PIPE_RESTORE(dev, pipe->pipe_0x4400, 0x4400);
473 PIPE_RESTORE(0x0000); 474 PIPE_RESTORE(dev, pipe->pipe_0x0000, 0x0000);
474 PIPE_RESTORE(0x0040); 475 PIPE_RESTORE(dev, pipe->pipe_0x0040, 0x0040);
475 nouveau_wait_for_idle(dev); 476 nouveau_wait_for_idle(dev);
476
477#undef PIPE_RESTORE
478} 477}
479 478
480static void nv10_graph_create_pipe(struct nouveau_channel *chan) 479static void nv10_graph_create_pipe(struct nouveau_channel *chan)
@@ -808,6 +807,20 @@ void nv10_graph_destroy_context(struct nouveau_channel *chan)
808 chan->pgraph_ctx = NULL; 807 chan->pgraph_ctx = NULL;
809} 808}
810 809
810void
811nv10_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
812 uint32_t size, uint32_t pitch)
813{
814 uint32_t limit = max(1u, addr + size) - 1;
815
816 if (pitch)
817 addr |= 1 << 31;
818
819 nv_wr32(dev, NV10_PGRAPH_TLIMIT(i), limit);
820 nv_wr32(dev, NV10_PGRAPH_TSIZE(i), pitch);
821 nv_wr32(dev, NV10_PGRAPH_TILE(i), addr);
822}
823
811int nv10_graph_init(struct drm_device *dev) 824int nv10_graph_init(struct drm_device *dev)
812{ 825{
813 struct drm_nouveau_private *dev_priv = dev->dev_private; 826 struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -832,21 +845,16 @@ int nv10_graph_init(struct drm_device *dev)
832 (1<<31)); 845 (1<<31));
833 if (dev_priv->chipset >= 0x17) { 846 if (dev_priv->chipset >= 0x17) {
834 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x1f000000); 847 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x1f000000);
848 nv_wr32(dev, 0x400a10, 0x3ff3fb6);
849 nv_wr32(dev, 0x400838, 0x2f8684);
850 nv_wr32(dev, 0x40083c, 0x115f3f);
835 nv_wr32(dev, 0x004006b0, 0x40000020); 851 nv_wr32(dev, 0x004006b0, 0x40000020);
836 } else 852 } else
837 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000); 853 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000);
838 854
839 /* copy tile info from PFB */ 855 /* Turn all the tiling regions off. */
840 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) { 856 for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
841 nv_wr32(dev, NV10_PGRAPH_TILE(i), 857 nv10_graph_set_region_tiling(dev, i, 0, 0, 0);
842 nv_rd32(dev, NV10_PFB_TILE(i)));
843 nv_wr32(dev, NV10_PGRAPH_TLIMIT(i),
844 nv_rd32(dev, NV10_PFB_TLIMIT(i)));
845 nv_wr32(dev, NV10_PGRAPH_TSIZE(i),
846 nv_rd32(dev, NV10_PFB_TSIZE(i)));
847 nv_wr32(dev, NV10_PGRAPH_TSTATUS(i),
848 nv_rd32(dev, NV10_PFB_TSTATUS(i)));
849 }
850 858
851 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH1, 0x00000000); 859 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH1, 0x00000000);
852 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH2, 0x00000000); 860 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH2, 0x00000000);
@@ -867,6 +875,115 @@ void nv10_graph_takedown(struct drm_device *dev)
867{ 875{
868} 876}
869 877
878static int
879nv17_graph_mthd_lma_window(struct nouveau_channel *chan, int grclass,
880 int mthd, uint32_t data)
881{
882 struct drm_device *dev = chan->dev;
883 struct graph_state *ctx = chan->pgraph_ctx;
884 struct pipe_state *pipe = &ctx->pipe_state;
885 struct drm_nouveau_private *dev_priv = dev->dev_private;
886 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
887 uint32_t pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3];
888 uint32_t xfmode0, xfmode1;
889 int i;
890
891 ctx->lma_window[(mthd - 0x1638) / 4] = data;
892
893 if (mthd != 0x1644)
894 return 0;
895
896 nouveau_wait_for_idle(dev);
897
898 PIPE_SAVE(dev, pipe_0x0040, 0x0040);
899 PIPE_SAVE(dev, pipe->pipe_0x0200, 0x0200);
900
901 PIPE_RESTORE(dev, ctx->lma_window, 0x6790);
902
903 nouveau_wait_for_idle(dev);
904
905 xfmode0 = nv_rd32(dev, NV10_PGRAPH_XFMODE0);
906 xfmode1 = nv_rd32(dev, NV10_PGRAPH_XFMODE1);
907
908 PIPE_SAVE(dev, pipe->pipe_0x4400, 0x4400);
909 PIPE_SAVE(dev, pipe_0x64c0, 0x64c0);
910 PIPE_SAVE(dev, pipe_0x6ab0, 0x6ab0);
911 PIPE_SAVE(dev, pipe_0x6a80, 0x6a80);
912
913 nouveau_wait_for_idle(dev);
914
915 nv_wr32(dev, NV10_PGRAPH_XFMODE0, 0x10000000);
916 nv_wr32(dev, NV10_PGRAPH_XFMODE1, 0x00000000);
917 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
918 for (i = 0; i < 4; i++)
919 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
920 for (i = 0; i < 4; i++)
921 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000);
922
923 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
924 for (i = 0; i < 3; i++)
925 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
926
927 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
928 for (i = 0; i < 3; i++)
929 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000);
930
931 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
932 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000008);
933
934 PIPE_RESTORE(dev, pipe->pipe_0x0200, 0x0200);
935
936 nouveau_wait_for_idle(dev);
937
938 PIPE_RESTORE(dev, pipe_0x0040, 0x0040);
939
940 nv_wr32(dev, NV10_PGRAPH_XFMODE0, xfmode0);
941 nv_wr32(dev, NV10_PGRAPH_XFMODE1, xfmode1);
942
943 PIPE_RESTORE(dev, pipe_0x64c0, 0x64c0);
944 PIPE_RESTORE(dev, pipe_0x6ab0, 0x6ab0);
945 PIPE_RESTORE(dev, pipe_0x6a80, 0x6a80);
946 PIPE_RESTORE(dev, pipe->pipe_0x4400, 0x4400);
947
948 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0);
949 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000);
950
951 nouveau_wait_for_idle(dev);
952
953 pgraph->fifo_access(dev, true);
954
955 return 0;
956}
957
958static int
959nv17_graph_mthd_lma_enable(struct nouveau_channel *chan, int grclass,
960 int mthd, uint32_t data)
961{
962 struct drm_device *dev = chan->dev;
963 struct drm_nouveau_private *dev_priv = dev->dev_private;
964 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
965
966 nouveau_wait_for_idle(dev);
967
968 nv_wr32(dev, NV10_PGRAPH_DEBUG_4,
969 nv_rd32(dev, NV10_PGRAPH_DEBUG_4) | 0x1 << 8);
970 nv_wr32(dev, 0x004006b0,
971 nv_rd32(dev, 0x004006b0) | 0x8 << 24);
972
973 pgraph->fifo_access(dev, true);
974
975 return 0;
976}
977
978static struct nouveau_pgraph_object_method nv17_graph_celsius_mthds[] = {
979 { 0x1638, nv17_graph_mthd_lma_window },
980 { 0x163c, nv17_graph_mthd_lma_window },
981 { 0x1640, nv17_graph_mthd_lma_window },
982 { 0x1644, nv17_graph_mthd_lma_window },
983 { 0x1658, nv17_graph_mthd_lma_enable },
984 {}
985};
986
870struct nouveau_pgraph_object_class nv10_graph_grclass[] = { 987struct nouveau_pgraph_object_class nv10_graph_grclass[] = {
871 { 0x0030, false, NULL }, /* null */ 988 { 0x0030, false, NULL }, /* null */
872 { 0x0039, false, NULL }, /* m2mf */ 989 { 0x0039, false, NULL }, /* m2mf */
@@ -887,6 +1004,6 @@ struct nouveau_pgraph_object_class nv10_graph_grclass[] = {
887 { 0x0095, false, NULL }, /* multitex_tri */ 1004 { 0x0095, false, NULL }, /* multitex_tri */
888 { 0x0056, false, NULL }, /* celcius (nv10) */ 1005 { 0x0056, false, NULL }, /* celcius (nv10) */
889 { 0x0096, false, NULL }, /* celcius (nv11) */ 1006 { 0x0096, false, NULL }, /* celcius (nv11) */
890 { 0x0099, false, NULL }, /* celcius (nv17) */ 1007 { 0x0099, false, nv17_graph_celsius_mthds }, /* celcius (nv17) */
891 {} 1008 {}
892}; 1009};
diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c
index 46cfd9c60478..58b917c3341b 100644
--- a/drivers/gpu/drm/nouveau/nv17_tv.c
+++ b/drivers/gpu/drm/nouveau/nv17_tv.c
@@ -33,13 +33,103 @@
33#include "nouveau_hw.h" 33#include "nouveau_hw.h"
34#include "nv17_tv.h" 34#include "nv17_tv.h"
35 35
36enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder, 36static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
37 struct drm_connector *connector,
38 uint32_t pin_mask)
39{ 37{
38 struct drm_device *dev = encoder->dev;
39 struct drm_nouveau_private *dev_priv = dev->dev_private;
40 uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
41 uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
42 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
43 uint32_t sample = 0;
44 int head;
45
46#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
47 testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
48 if (dev_priv->vbios->tvdactestval)
49 testval = dev_priv->vbios->tvdactestval;
50
51 dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
52 head = (dacclk & 0x100) >> 8;
53
54 /* Save the previous state. */
55 gpio1 = nv17_gpio_get(dev, DCB_GPIO_TVDAC1);
56 gpio0 = nv17_gpio_get(dev, DCB_GPIO_TVDAC0);
57 fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
58 fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
59 fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
60 fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
61 test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
62 ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
63 ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
64 ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
65
66 /* Prepare the DAC for load detection. */
67 nv17_gpio_set(dev, DCB_GPIO_TVDAC1, true);
68 nv17_gpio_set(dev, DCB_GPIO_TVDAC0, true);
69
70 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
71 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
72 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);
73 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
74 NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
75 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 |
76 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
77 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |
78 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS);
79
80 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
81
82 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
83 (dacclk & ~0xff) | 0x22);
84 msleep(1);
85 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
86 (dacclk & ~0xff) | 0x21);
87
88 NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
89 NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
90
91 /* Sample pin 0x4 (usually S-video luma). */
92 NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
93 msleep(20);
94 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
95 & 0x4 << 28;
96
97 /* Sample the remaining pins. */
98 NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
99 msleep(20);
100 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
101 & 0xa << 28;
102
103 /* Restore the previous state. */
104 NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
105 NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
106 NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
107 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
108 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
109 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
110 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
111 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
112 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
113 nv17_gpio_set(dev, DCB_GPIO_TVDAC1, gpio1);
114 nv17_gpio_set(dev, DCB_GPIO_TVDAC0, gpio0);
115
116 return sample;
117}
118
119static enum drm_connector_status
120nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
121{
122 struct drm_device *dev = encoder->dev;
123 struct drm_nouveau_private *dev_priv = dev->dev_private;
124 struct drm_mode_config *conf = &dev->mode_config;
40 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 125 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
126 struct dcb_entry *dcb = tv_enc->base.dcb;
41 127
42 tv_enc->pin_mask = pin_mask >> 28 & 0xe; 128 if (dev_priv->chipset == 0x42 ||
129 dev_priv->chipset == 0x43)
130 tv_enc->pin_mask = nv42_tv_sample_load(encoder) >> 28 & 0xe;
131 else
132 tv_enc->pin_mask = nv17_dac_sample_load(encoder) >> 28 & 0xe;
43 133
44 switch (tv_enc->pin_mask) { 134 switch (tv_enc->pin_mask) {
45 case 0x2: 135 case 0x2:
@@ -50,7 +140,7 @@ enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder,
50 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO; 140 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
51 break; 141 break;
52 case 0xe: 142 case 0xe:
53 if (nouveau_encoder(encoder)->dcb->tvconf.has_component_output) 143 if (dcb->tvconf.has_component_output)
54 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component; 144 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component;
55 else 145 else
56 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART; 146 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
@@ -61,11 +151,16 @@ enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder,
61 } 151 }
62 152
63 drm_connector_property_set_value(connector, 153 drm_connector_property_set_value(connector,
64 encoder->dev->mode_config.tv_subconnector_property, 154 conf->tv_subconnector_property,
65 tv_enc->subconnector); 155 tv_enc->subconnector);
66 156
67 return tv_enc->subconnector ? connector_status_connected : 157 if (tv_enc->subconnector) {
68 connector_status_disconnected; 158 NV_INFO(dev, "Load detected on output %c\n",
159 '@' + ffs(dcb->or));
160 return connector_status_connected;
161 } else {
162 return connector_status_disconnected;
163 }
69} 164}
70 165
71static const struct { 166static const struct {
@@ -219,7 +314,7 @@ static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
219 return; 314 return;
220 nouveau_encoder(encoder)->last_dpms = mode; 315 nouveau_encoder(encoder)->last_dpms = mode;
221 316
222 NV_TRACE(dev, "Setting dpms mode %d on TV encoder (output %d)\n", 317 NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
223 mode, nouveau_encoder(encoder)->dcb->index); 318 mode, nouveau_encoder(encoder)->dcb->index);
224 319
225 regs->ptv_200 &= ~1; 320 regs->ptv_200 &= ~1;
@@ -619,7 +714,7 @@ static void nv17_tv_destroy(struct drm_encoder *encoder)
619{ 714{
620 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 715 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
621 716
622 NV_DEBUG(encoder->dev, "\n"); 717 NV_DEBUG_KMS(encoder->dev, "\n");
623 718
624 drm_encoder_cleanup(encoder); 719 drm_encoder_cleanup(encoder);
625 kfree(tv_enc); 720 kfree(tv_enc);
@@ -633,7 +728,7 @@ static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = {
633 .prepare = nv17_tv_prepare, 728 .prepare = nv17_tv_prepare,
634 .commit = nv17_tv_commit, 729 .commit = nv17_tv_commit,
635 .mode_set = nv17_tv_mode_set, 730 .mode_set = nv17_tv_mode_set,
636 .detect = nv17_dac_detect, 731 .detect = nv17_tv_detect,
637}; 732};
638 733
639static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = { 734static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = {
diff --git a/drivers/gpu/drm/nouveau/nv20_graph.c b/drivers/gpu/drm/nouveau/nv20_graph.c
index 18ba74f19703..d6fc0a82f03d 100644
--- a/drivers/gpu/drm/nouveau/nv20_graph.c
+++ b/drivers/gpu/drm/nouveau/nv20_graph.c
@@ -514,6 +514,27 @@ nv20_graph_rdi(struct drm_device *dev)
514 nouveau_wait_for_idle(dev); 514 nouveau_wait_for_idle(dev);
515} 515}
516 516
517void
518nv20_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
519 uint32_t size, uint32_t pitch)
520{
521 uint32_t limit = max(1u, addr + size) - 1;
522
523 if (pitch)
524 addr |= 1;
525
526 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
527 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
528 nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
529
530 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
531 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, limit);
532 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
533 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, pitch);
534 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
535 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, addr);
536}
537
517int 538int
518nv20_graph_init(struct drm_device *dev) 539nv20_graph_init(struct drm_device *dev)
519{ 540{
@@ -572,27 +593,10 @@ nv20_graph_init(struct drm_device *dev)
572 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030); 593 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030);
573 } 594 }
574 595
575 /* copy tile info from PFB */ 596 /* Turn all the tiling regions off. */
576 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) { 597 for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
577 nv_wr32(dev, 0x00400904 + i * 0x10, 598 nv20_graph_set_region_tiling(dev, i, 0, 0, 0);
578 nv_rd32(dev, NV10_PFB_TLIMIT(i))); 599
579 /* which is NV40_PGRAPH_TLIMIT0(i) ?? */
580 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + i * 4);
581 nv_wr32(dev, NV10_PGRAPH_RDI_DATA,
582 nv_rd32(dev, NV10_PFB_TLIMIT(i)));
583 nv_wr32(dev, 0x00400908 + i * 0x10,
584 nv_rd32(dev, NV10_PFB_TSIZE(i)));
585 /* which is NV40_PGRAPH_TSIZE0(i) ?? */
586 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + i * 4);
587 nv_wr32(dev, NV10_PGRAPH_RDI_DATA,
588 nv_rd32(dev, NV10_PFB_TSIZE(i)));
589 nv_wr32(dev, 0x00400900 + i * 0x10,
590 nv_rd32(dev, NV10_PFB_TILE(i)));
591 /* which is NV40_PGRAPH_TILE0(i) ?? */
592 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + i * 4);
593 nv_wr32(dev, NV10_PGRAPH_RDI_DATA,
594 nv_rd32(dev, NV10_PFB_TILE(i)));
595 }
596 for (i = 0; i < 8; i++) { 600 for (i = 0; i < 8; i++) {
597 nv_wr32(dev, 0x400980 + i * 4, nv_rd32(dev, 0x100300 + i * 4)); 601 nv_wr32(dev, 0x400980 + i * 4, nv_rd32(dev, 0x100300 + i * 4));
598 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0090 + i * 4); 602 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0090 + i * 4);
@@ -704,18 +708,9 @@ nv30_graph_init(struct drm_device *dev)
704 708
705 nv_wr32(dev, 0x4000c0, 0x00000016); 709 nv_wr32(dev, 0x4000c0, 0x00000016);
706 710
707 /* copy tile info from PFB */ 711 /* Turn all the tiling regions off. */
708 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) { 712 for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
709 nv_wr32(dev, 0x00400904 + i * 0x10, 713 nv20_graph_set_region_tiling(dev, i, 0, 0, 0);
710 nv_rd32(dev, NV10_PFB_TLIMIT(i)));
711 /* which is NV40_PGRAPH_TLIMIT0(i) ?? */
712 nv_wr32(dev, 0x00400908 + i * 0x10,
713 nv_rd32(dev, NV10_PFB_TSIZE(i)));
714 /* which is NV40_PGRAPH_TSIZE0(i) ?? */
715 nv_wr32(dev, 0x00400900 + i * 0x10,
716 nv_rd32(dev, NV10_PFB_TILE(i)));
717 /* which is NV40_PGRAPH_TILE0(i) ?? */
718 }
719 714
720 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100); 715 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
721 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF); 716 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
diff --git a/drivers/gpu/drm/nouveau/nv40_fb.c b/drivers/gpu/drm/nouveau/nv40_fb.c
index ca1d27107a8e..3cd07d8d5bd7 100644
--- a/drivers/gpu/drm/nouveau/nv40_fb.c
+++ b/drivers/gpu/drm/nouveau/nv40_fb.c
@@ -3,12 +3,37 @@
3#include "nouveau_drv.h" 3#include "nouveau_drv.h"
4#include "nouveau_drm.h" 4#include "nouveau_drm.h"
5 5
6void
7nv40_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
8 uint32_t size, uint32_t pitch)
9{
10 struct drm_nouveau_private *dev_priv = dev->dev_private;
11 uint32_t limit = max(1u, addr + size) - 1;
12
13 if (pitch)
14 addr |= 1;
15
16 switch (dev_priv->chipset) {
17 case 0x40:
18 nv_wr32(dev, NV10_PFB_TLIMIT(i), limit);
19 nv_wr32(dev, NV10_PFB_TSIZE(i), pitch);
20 nv_wr32(dev, NV10_PFB_TILE(i), addr);
21 break;
22
23 default:
24 nv_wr32(dev, NV40_PFB_TLIMIT(i), limit);
25 nv_wr32(dev, NV40_PFB_TSIZE(i), pitch);
26 nv_wr32(dev, NV40_PFB_TILE(i), addr);
27 break;
28 }
29}
30
6int 31int
7nv40_fb_init(struct drm_device *dev) 32nv40_fb_init(struct drm_device *dev)
8{ 33{
9 struct drm_nouveau_private *dev_priv = dev->dev_private; 34 struct drm_nouveau_private *dev_priv = dev->dev_private;
10 uint32_t fb_bar_size, tmp; 35 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
11 int num_tiles; 36 uint32_t tmp;
12 int i; 37 int i;
13 38
14 /* This is strictly a NV4x register (don't know about NV5x). */ 39 /* This is strictly a NV4x register (don't know about NV5x). */
@@ -23,35 +48,23 @@ nv40_fb_init(struct drm_device *dev)
23 case 0x45: 48 case 0x45:
24 tmp = nv_rd32(dev, NV10_PFB_CLOSE_PAGE2); 49 tmp = nv_rd32(dev, NV10_PFB_CLOSE_PAGE2);
25 nv_wr32(dev, NV10_PFB_CLOSE_PAGE2, tmp & ~(1 << 15)); 50 nv_wr32(dev, NV10_PFB_CLOSE_PAGE2, tmp & ~(1 << 15));
26 num_tiles = NV10_PFB_TILE__SIZE; 51 pfb->num_tiles = NV10_PFB_TILE__SIZE;
27 break; 52 break;
28 case 0x46: /* G72 */ 53 case 0x46: /* G72 */
29 case 0x47: /* G70 */ 54 case 0x47: /* G70 */
30 case 0x49: /* G71 */ 55 case 0x49: /* G71 */
31 case 0x4b: /* G73 */ 56 case 0x4b: /* G73 */
32 case 0x4c: /* C51 (G7X version) */ 57 case 0x4c: /* C51 (G7X version) */
33 num_tiles = NV40_PFB_TILE__SIZE_1; 58 pfb->num_tiles = NV40_PFB_TILE__SIZE_1;
34 break; 59 break;
35 default: 60 default:
36 num_tiles = NV40_PFB_TILE__SIZE_0; 61 pfb->num_tiles = NV40_PFB_TILE__SIZE_0;
37 break; 62 break;
38 } 63 }
39 64
40 fb_bar_size = drm_get_resource_len(dev, 0) - 1; 65 /* Turn all the tiling regions off. */
41 switch (dev_priv->chipset) { 66 for (i = 0; i < pfb->num_tiles; i++)
42 case 0x40: 67 pfb->set_region_tiling(dev, i, 0, 0, 0);
43 for (i = 0; i < num_tiles; i++) {
44 nv_wr32(dev, NV10_PFB_TILE(i), 0);
45 nv_wr32(dev, NV10_PFB_TLIMIT(i), fb_bar_size);
46 }
47 break;
48 default:
49 for (i = 0; i < num_tiles; i++) {
50 nv_wr32(dev, NV40_PFB_TILE(i), 0);
51 nv_wr32(dev, NV40_PFB_TLIMIT(i), fb_bar_size);
52 }
53 break;
54 }
55 68
56 return 0; 69 return 0;
57} 70}
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index 7e8547cb5833..53e8afe1dcd1 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -24,36 +24,10 @@
24 * 24 *
25 */ 25 */
26 26
27#include <linux/firmware.h>
28
29#include "drmP.h" 27#include "drmP.h"
30#include "drm.h" 28#include "drm.h"
31#include "nouveau_drv.h" 29#include "nouveau_drv.h"
32 30#include "nouveau_grctx.h"
33MODULE_FIRMWARE("nouveau/nv40.ctxprog");
34MODULE_FIRMWARE("nouveau/nv40.ctxvals");
35MODULE_FIRMWARE("nouveau/nv41.ctxprog");
36MODULE_FIRMWARE("nouveau/nv41.ctxvals");
37MODULE_FIRMWARE("nouveau/nv42.ctxprog");
38MODULE_FIRMWARE("nouveau/nv42.ctxvals");
39MODULE_FIRMWARE("nouveau/nv43.ctxprog");
40MODULE_FIRMWARE("nouveau/nv43.ctxvals");
41MODULE_FIRMWARE("nouveau/nv44.ctxprog");
42MODULE_FIRMWARE("nouveau/nv44.ctxvals");
43MODULE_FIRMWARE("nouveau/nv46.ctxprog");
44MODULE_FIRMWARE("nouveau/nv46.ctxvals");
45MODULE_FIRMWARE("nouveau/nv47.ctxprog");
46MODULE_FIRMWARE("nouveau/nv47.ctxvals");
47MODULE_FIRMWARE("nouveau/nv49.ctxprog");
48MODULE_FIRMWARE("nouveau/nv49.ctxvals");
49MODULE_FIRMWARE("nouveau/nv4a.ctxprog");
50MODULE_FIRMWARE("nouveau/nv4a.ctxvals");
51MODULE_FIRMWARE("nouveau/nv4b.ctxprog");
52MODULE_FIRMWARE("nouveau/nv4b.ctxvals");
53MODULE_FIRMWARE("nouveau/nv4c.ctxprog");
54MODULE_FIRMWARE("nouveau/nv4c.ctxvals");
55MODULE_FIRMWARE("nouveau/nv4e.ctxprog");
56MODULE_FIRMWARE("nouveau/nv4e.ctxvals");
57 31
58struct nouveau_channel * 32struct nouveau_channel *
59nv40_graph_channel(struct drm_device *dev) 33nv40_graph_channel(struct drm_device *dev)
@@ -83,27 +57,30 @@ nv40_graph_create_context(struct nouveau_channel *chan)
83{ 57{
84 struct drm_device *dev = chan->dev; 58 struct drm_device *dev = chan->dev;
85 struct drm_nouveau_private *dev_priv = dev->dev_private; 59 struct drm_nouveau_private *dev_priv = dev->dev_private;
86 struct nouveau_gpuobj *ctx; 60 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
87 int ret; 61 int ret;
88 62
89 /* Allocate a 175KiB block of PRAMIN to store the context. This 63 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
90 * is massive overkill for a lot of chipsets, but it should be safe 64 16, NVOBJ_FLAG_ZERO_ALLOC,
91 * until we're able to implement this properly (will happen at more 65 &chan->ramin_grctx);
92 * or less the same time we're able to write our own context programs.
93 */
94 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 175*1024, 16,
95 NVOBJ_FLAG_ZERO_ALLOC,
96 &chan->ramin_grctx);
97 if (ret) 66 if (ret)
98 return ret; 67 return ret;
99 ctx = chan->ramin_grctx->gpuobj;
100 68
101 /* Initialise default context values */ 69 /* Initialise default context values */
102 dev_priv->engine.instmem.prepare_access(dev, true); 70 dev_priv->engine.instmem.prepare_access(dev, true);
103 nv40_grctx_vals_load(dev, ctx); 71 if (!pgraph->ctxprog) {
104 nv_wo32(dev, ctx, 0, ctx->im_pramin->start); 72 struct nouveau_grctx ctx = {};
105 dev_priv->engine.instmem.finish_access(dev);
106 73
74 ctx.dev = chan->dev;
75 ctx.mode = NOUVEAU_GRCTX_VALS;
76 ctx.data = chan->ramin_grctx->gpuobj;
77 nv40_grctx_init(&ctx);
78 } else {
79 nouveau_grctx_vals_load(dev, chan->ramin_grctx->gpuobj);
80 }
81 nv_wo32(dev, chan->ramin_grctx->gpuobj, 0,
82 chan->ramin_grctx->gpuobj->im_pramin->start);
83 dev_priv->engine.instmem.finish_access(dev);
107 return 0; 84 return 0;
108} 85}
109 86
@@ -204,137 +181,46 @@ nv40_graph_unload_context(struct drm_device *dev)
204 return ret; 181 return ret;
205} 182}
206 183
207struct nouveau_ctxprog {
208 uint32_t signature;
209 uint8_t version;
210 uint16_t length;
211 uint32_t data[];
212} __attribute__ ((packed));
213
214struct nouveau_ctxvals {
215 uint32_t signature;
216 uint8_t version;
217 uint32_t length;
218 struct {
219 uint32_t offset;
220 uint32_t value;
221 } data[];
222} __attribute__ ((packed));
223
224int
225nv40_grctx_init(struct drm_device *dev)
226{
227 struct drm_nouveau_private *dev_priv = dev->dev_private;
228 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
229 const int chipset = dev_priv->chipset;
230 const struct firmware *fw;
231 const struct nouveau_ctxprog *cp;
232 const struct nouveau_ctxvals *cv;
233 char name[32];
234 int ret, i;
235
236 pgraph->accel_blocked = true;
237
238 if (!pgraph->ctxprog) {
239 sprintf(name, "nouveau/nv%02x.ctxprog", chipset);
240 ret = request_firmware(&fw, name, &dev->pdev->dev);
241 if (ret) {
242 NV_ERROR(dev, "No ctxprog for NV%02x\n", chipset);
243 return ret;
244 }
245
246 pgraph->ctxprog = kmalloc(fw->size, GFP_KERNEL);
247 if (!pgraph->ctxprog) {
248 NV_ERROR(dev, "OOM copying ctxprog\n");
249 release_firmware(fw);
250 return -ENOMEM;
251 }
252 memcpy(pgraph->ctxprog, fw->data, fw->size);
253
254 cp = pgraph->ctxprog;
255 if (le32_to_cpu(cp->signature) != 0x5043564e ||
256 cp->version != 0 ||
257 le16_to_cpu(cp->length) != ((fw->size - 7) / 4)) {
258 NV_ERROR(dev, "ctxprog invalid\n");
259 release_firmware(fw);
260 nv40_grctx_fini(dev);
261 return -EINVAL;
262 }
263 release_firmware(fw);
264 }
265
266 if (!pgraph->ctxvals) {
267 sprintf(name, "nouveau/nv%02x.ctxvals", chipset);
268 ret = request_firmware(&fw, name, &dev->pdev->dev);
269 if (ret) {
270 NV_ERROR(dev, "No ctxvals for NV%02x\n", chipset);
271 nv40_grctx_fini(dev);
272 return ret;
273 }
274
275 pgraph->ctxvals = kmalloc(fw->size, GFP_KERNEL);
276 if (!pgraph->ctxprog) {
277 NV_ERROR(dev, "OOM copying ctxprog\n");
278 release_firmware(fw);
279 nv40_grctx_fini(dev);
280 return -ENOMEM;
281 }
282 memcpy(pgraph->ctxvals, fw->data, fw->size);
283
284 cv = (void *)pgraph->ctxvals;
285 if (le32_to_cpu(cv->signature) != 0x5643564e ||
286 cv->version != 0 ||
287 le32_to_cpu(cv->length) != ((fw->size - 9) / 8)) {
288 NV_ERROR(dev, "ctxvals invalid\n");
289 release_firmware(fw);
290 nv40_grctx_fini(dev);
291 return -EINVAL;
292 }
293 release_firmware(fw);
294 }
295
296 cp = pgraph->ctxprog;
297
298 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
299 for (i = 0; i < le16_to_cpu(cp->length); i++)
300 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA,
301 le32_to_cpu(cp->data[i]));
302
303 pgraph->accel_blocked = false;
304 return 0;
305}
306
307void 184void
308nv40_grctx_fini(struct drm_device *dev) 185nv40_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
186 uint32_t size, uint32_t pitch)
309{ 187{
310 struct drm_nouveau_private *dev_priv = dev->dev_private; 188 struct drm_nouveau_private *dev_priv = dev->dev_private;
311 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 189 uint32_t limit = max(1u, addr + size) - 1;
312
313 if (pgraph->ctxprog) {
314 kfree(pgraph->ctxprog);
315 pgraph->ctxprog = NULL;
316 }
317 190
318 if (pgraph->ctxvals) { 191 if (pitch)
319 kfree(pgraph->ctxprog); 192 addr |= 1;
320 pgraph->ctxvals = NULL;
321 }
322}
323 193
324void 194 switch (dev_priv->chipset) {
325nv40_grctx_vals_load(struct drm_device *dev, struct nouveau_gpuobj *ctx) 195 case 0x44:
326{ 196 case 0x4a:
327 struct drm_nouveau_private *dev_priv = dev->dev_private; 197 case 0x4e:
328 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 198 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
329 struct nouveau_ctxvals *cv = pgraph->ctxvals; 199 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
330 int i; 200 nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
201 break;
331 202
332 if (!cv) 203 case 0x46:
333 return; 204 case 0x47:
205 case 0x49:
206 case 0x4b:
207 nv_wr32(dev, NV47_PGRAPH_TSIZE(i), pitch);
208 nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), limit);
209 nv_wr32(dev, NV47_PGRAPH_TILE(i), addr);
210 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
211 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
212 nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
213 break;
334 214
335 for (i = 0; i < le32_to_cpu(cv->length); i++) 215 default:
336 nv_wo32(dev, ctx, le32_to_cpu(cv->data[i].offset), 216 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
337 le32_to_cpu(cv->data[i].value)); 217 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
218 nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
219 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
220 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
221 nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
222 break;
223 }
338} 224}
339 225
340/* 226/*
@@ -351,7 +237,8 @@ nv40_graph_init(struct drm_device *dev)
351{ 237{
352 struct drm_nouveau_private *dev_priv = 238 struct drm_nouveau_private *dev_priv =
353 (struct drm_nouveau_private *)dev->dev_private; 239 (struct drm_nouveau_private *)dev->dev_private;
354 uint32_t vramsz, tmp; 240 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
241 uint32_t vramsz;
355 int i, j; 242 int i, j;
356 243
357 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & 244 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
@@ -359,7 +246,26 @@ nv40_graph_init(struct drm_device *dev)
359 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | 246 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
360 NV_PMC_ENABLE_PGRAPH); 247 NV_PMC_ENABLE_PGRAPH);
361 248
362 nv40_grctx_init(dev); 249 if (nouveau_ctxfw) {
250 nouveau_grctx_prog_load(dev);
251 dev_priv->engine.graph.grctx_size = 175 * 1024;
252 }
253
254 if (!dev_priv->engine.graph.ctxprog) {
255 struct nouveau_grctx ctx = {};
256 uint32_t cp[256];
257
258 ctx.dev = dev;
259 ctx.mode = NOUVEAU_GRCTX_PROG;
260 ctx.data = cp;
261 ctx.ctxprog_max = 256;
262 nv40_grctx_init(&ctx);
263 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
264
265 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
266 for (i = 0; i < ctx.ctxprog_len; i++)
267 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
268 }
363 269
364 /* No context present currently */ 270 /* No context present currently */
365 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); 271 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
@@ -429,74 +335,9 @@ nv40_graph_init(struct drm_device *dev)
429 nv_wr32(dev, 0x400b38, 0x2ffff800); 335 nv_wr32(dev, 0x400b38, 0x2ffff800);
430 nv_wr32(dev, 0x400b3c, 0x00006000); 336 nv_wr32(dev, 0x400b3c, 0x00006000);
431 337
432 /* copy tile info from PFB */ 338 /* Turn all the tiling regions off. */
433 switch (dev_priv->chipset) { 339 for (i = 0; i < pfb->num_tiles; i++)
434 case 0x40: /* vanilla NV40 */ 340 nv40_graph_set_region_tiling(dev, i, 0, 0, 0);
435 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {
436 tmp = nv_rd32(dev, NV10_PFB_TILE(i));
437 nv_wr32(dev, NV40_PGRAPH_TILE0(i), tmp);
438 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tmp);
439 tmp = nv_rd32(dev, NV10_PFB_TLIMIT(i));
440 nv_wr32(dev, NV40_PGRAPH_TLIMIT0(i), tmp);
441 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tmp);
442 tmp = nv_rd32(dev, NV10_PFB_TSIZE(i));
443 nv_wr32(dev, NV40_PGRAPH_TSIZE0(i), tmp);
444 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tmp);
445 tmp = nv_rd32(dev, NV10_PFB_TSTATUS(i));
446 nv_wr32(dev, NV40_PGRAPH_TSTATUS0(i), tmp);
447 nv_wr32(dev, NV40_PGRAPH_TSTATUS1(i), tmp);
448 }
449 break;
450 case 0x44:
451 case 0x4a:
452 case 0x4e: /* NV44-based cores don't have 0x406900? */
453 for (i = 0; i < NV40_PFB_TILE__SIZE_0; i++) {
454 tmp = nv_rd32(dev, NV40_PFB_TILE(i));
455 nv_wr32(dev, NV40_PGRAPH_TILE0(i), tmp);
456 tmp = nv_rd32(dev, NV40_PFB_TLIMIT(i));
457 nv_wr32(dev, NV40_PGRAPH_TLIMIT0(i), tmp);
458 tmp = nv_rd32(dev, NV40_PFB_TSIZE(i));
459 nv_wr32(dev, NV40_PGRAPH_TSIZE0(i), tmp);
460 tmp = nv_rd32(dev, NV40_PFB_TSTATUS(i));
461 nv_wr32(dev, NV40_PGRAPH_TSTATUS0(i), tmp);
462 }
463 break;
464 case 0x46:
465 case 0x47:
466 case 0x49:
467 case 0x4b: /* G7X-based cores */
468 for (i = 0; i < NV40_PFB_TILE__SIZE_1; i++) {
469 tmp = nv_rd32(dev, NV40_PFB_TILE(i));
470 nv_wr32(dev, NV47_PGRAPH_TILE0(i), tmp);
471 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tmp);
472 tmp = nv_rd32(dev, NV40_PFB_TLIMIT(i));
473 nv_wr32(dev, NV47_PGRAPH_TLIMIT0(i), tmp);
474 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tmp);
475 tmp = nv_rd32(dev, NV40_PFB_TSIZE(i));
476 nv_wr32(dev, NV47_PGRAPH_TSIZE0(i), tmp);
477 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tmp);
478 tmp = nv_rd32(dev, NV40_PFB_TSTATUS(i));
479 nv_wr32(dev, NV47_PGRAPH_TSTATUS0(i), tmp);
480 nv_wr32(dev, NV40_PGRAPH_TSTATUS1(i), tmp);
481 }
482 break;
483 default: /* everything else */
484 for (i = 0; i < NV40_PFB_TILE__SIZE_0; i++) {
485 tmp = nv_rd32(dev, NV40_PFB_TILE(i));
486 nv_wr32(dev, NV40_PGRAPH_TILE0(i), tmp);
487 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tmp);
488 tmp = nv_rd32(dev, NV40_PFB_TLIMIT(i));
489 nv_wr32(dev, NV40_PGRAPH_TLIMIT0(i), tmp);
490 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tmp);
491 tmp = nv_rd32(dev, NV40_PFB_TSIZE(i));
492 nv_wr32(dev, NV40_PGRAPH_TSIZE0(i), tmp);
493 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tmp);
494 tmp = nv_rd32(dev, NV40_PFB_TSTATUS(i));
495 nv_wr32(dev, NV40_PGRAPH_TSTATUS0(i), tmp);
496 nv_wr32(dev, NV40_PGRAPH_TSTATUS1(i), tmp);
497 }
498 break;
499 }
500 341
501 /* begin RAM config */ 342 /* begin RAM config */
502 vramsz = drm_get_resource_len(dev, 0) - 1; 343 vramsz = drm_get_resource_len(dev, 0) - 1;
@@ -539,6 +380,7 @@ nv40_graph_init(struct drm_device *dev)
539 380
540void nv40_graph_takedown(struct drm_device *dev) 381void nv40_graph_takedown(struct drm_device *dev)
541{ 382{
383 nouveau_grctx_fini(dev);
542} 384}
543 385
544struct nouveau_pgraph_object_class nv40_graph_grclass[] = { 386struct nouveau_pgraph_object_class nv40_graph_grclass[] = {
diff --git a/drivers/gpu/drm/nouveau/nv40_grctx.c b/drivers/gpu/drm/nouveau/nv40_grctx.c
new file mode 100644
index 000000000000..11b11c31f543
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv40_grctx.c
@@ -0,0 +1,678 @@
1/*
2 * Copyright 2009 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25/* NVIDIA context programs handle a number of other conditions which are
26 * not implemented in our versions. It's not clear why NVIDIA context
27 * programs have this code, nor whether it's strictly necessary for
28 * correct operation. We'll implement additional handling if/when we
29 * discover it's necessary.
30 *
31 * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state"
32 * flag is set, this gets saved into the context.
33 * - On context save, the context program for all cards load nsource
34 * into a flag register and check for ILLEGAL_MTHD. If it's set,
35 * opcode 0x60000d is called before resuming normal operation.
36 * - Some context programs check more conditions than the above. NV44
37 * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001))
38 * and calls 0x60000d before resuming normal operation.
39 * - At the very beginning of NVIDIA's context programs, flag 9 is checked
40 * and if true 0x800001 is called with count=0, pos=0, the flag is cleared
41 * and then the ctxprog is aborted. It looks like a complicated NOP,
42 * its purpose is unknown.
43 * - In the section of code that loads the per-vs state, NVIDIA check
44 * flag 10. If it's set, they only transfer the small 0x300 byte block
45 * of state + the state for a single vs as opposed to the state for
46 * all vs units. It doesn't seem likely that it'll occur in normal
47 * operation, especially seeing as it appears NVIDIA may have screwed
48 * up the ctxprogs for some cards and have an invalid instruction
49 * rather than a cp_lsr(ctx, dwords_for_1_vs_unit) instruction.
50 * - There's a number of places where context offset 0 (where we place
51 * the PRAMIN offset of the context) is loaded into either 0x408000,
52 * 0x408004 or 0x408008. Not sure what's up there either.
53 * - The ctxprogs for some cards save 0x400a00 again during the cleanup
54 * path for auto-loadctx.
55 */
56
57#define CP_FLAG_CLEAR 0
58#define CP_FLAG_SET 1
59#define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0)
60#define CP_FLAG_SWAP_DIRECTION_LOAD 0
61#define CP_FLAG_SWAP_DIRECTION_SAVE 1
62#define CP_FLAG_USER_SAVE ((0 * 32) + 5)
63#define CP_FLAG_USER_SAVE_NOT_PENDING 0
64#define CP_FLAG_USER_SAVE_PENDING 1
65#define CP_FLAG_USER_LOAD ((0 * 32) + 6)
66#define CP_FLAG_USER_LOAD_NOT_PENDING 0
67#define CP_FLAG_USER_LOAD_PENDING 1
68#define CP_FLAG_STATUS ((3 * 32) + 0)
69#define CP_FLAG_STATUS_IDLE 0
70#define CP_FLAG_STATUS_BUSY 1
71#define CP_FLAG_AUTO_SAVE ((3 * 32) + 4)
72#define CP_FLAG_AUTO_SAVE_NOT_PENDING 0
73#define CP_FLAG_AUTO_SAVE_PENDING 1
74#define CP_FLAG_AUTO_LOAD ((3 * 32) + 5)
75#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0
76#define CP_FLAG_AUTO_LOAD_PENDING 1
77#define CP_FLAG_UNK54 ((3 * 32) + 6)
78#define CP_FLAG_UNK54_CLEAR 0
79#define CP_FLAG_UNK54_SET 1
80#define CP_FLAG_ALWAYS ((3 * 32) + 8)
81#define CP_FLAG_ALWAYS_FALSE 0
82#define CP_FLAG_ALWAYS_TRUE 1
83#define CP_FLAG_UNK57 ((3 * 32) + 9)
84#define CP_FLAG_UNK57_CLEAR 0
85#define CP_FLAG_UNK57_SET 1
86
87#define CP_CTX 0x00100000
88#define CP_CTX_COUNT 0x000fc000
89#define CP_CTX_COUNT_SHIFT 14
90#define CP_CTX_REG 0x00003fff
91#define CP_LOAD_SR 0x00200000
92#define CP_LOAD_SR_VALUE 0x000fffff
93#define CP_BRA 0x00400000
94#define CP_BRA_IP 0x0000ff00
95#define CP_BRA_IP_SHIFT 8
96#define CP_BRA_IF_CLEAR 0x00000080
97#define CP_BRA_FLAG 0x0000007f
98#define CP_WAIT 0x00500000
99#define CP_WAIT_SET 0x00000080
100#define CP_WAIT_FLAG 0x0000007f
101#define CP_SET 0x00700000
102#define CP_SET_1 0x00000080
103#define CP_SET_FLAG 0x0000007f
104#define CP_NEXT_TO_SWAP 0x00600007
105#define CP_NEXT_TO_CURRENT 0x00600009
106#define CP_SET_CONTEXT_POINTER 0x0060000a
107#define CP_END 0x0060000e
108#define CP_LOAD_MAGIC_UNK01 0x00800001 /* unknown */
109#define CP_LOAD_MAGIC_NV44TCL 0x00800029 /* per-vs state (0x4497) */
110#define CP_LOAD_MAGIC_NV40TCL 0x00800041 /* per-vs state (0x4097) */
111
112#include "drmP.h"
113#include "nouveau_drv.h"
114#include "nouveau_grctx.h"
115
116/* TODO:
117 * - get vs count from 0x1540
118 * - document unimplemented bits compared to nvidia
119 * - nsource handling
120 * - R0 & 0x0200 handling
121 * - single-vs handling
122 * - 400314 bit 0
123 */
124
125static int
126nv40_graph_4097(struct drm_device *dev)
127{
128 struct drm_nouveau_private *dev_priv = dev->dev_private;
129
130 if ((dev_priv->chipset & 0xf0) == 0x60)
131 return 0;
132
133 return !!(0x0baf & (1 << dev_priv->chipset));
134}
135
136static int
137nv40_graph_vs_count(struct drm_device *dev)
138{
139 struct drm_nouveau_private *dev_priv = dev->dev_private;
140
141 switch (dev_priv->chipset) {
142 case 0x47:
143 case 0x49:
144 case 0x4b:
145 return 8;
146 case 0x40:
147 return 6;
148 case 0x41:
149 case 0x42:
150 return 5;
151 case 0x43:
152 case 0x44:
153 case 0x46:
154 case 0x4a:
155 return 3;
156 case 0x4c:
157 case 0x4e:
158 case 0x67:
159 default:
160 return 1;
161 }
162}
163
164
165enum cp_label {
166 cp_check_load = 1,
167 cp_setup_auto_load,
168 cp_setup_load,
169 cp_setup_save,
170 cp_swap_state,
171 cp_swap_state3d_3_is_save,
172 cp_prepare_exit,
173 cp_exit,
174};
175
176static void
177nv40_graph_construct_general(struct nouveau_grctx *ctx)
178{
179 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
180 int i;
181
182 cp_ctx(ctx, 0x4000a4, 1);
183 gr_def(ctx, 0x4000a4, 0x00000008);
184 cp_ctx(ctx, 0x400144, 58);
185 gr_def(ctx, 0x400144, 0x00000001);
186 cp_ctx(ctx, 0x400314, 1);
187 gr_def(ctx, 0x400314, 0x00000000);
188 cp_ctx(ctx, 0x400400, 10);
189 cp_ctx(ctx, 0x400480, 10);
190 cp_ctx(ctx, 0x400500, 19);
191 gr_def(ctx, 0x400514, 0x00040000);
192 gr_def(ctx, 0x400524, 0x55555555);
193 gr_def(ctx, 0x400528, 0x55555555);
194 gr_def(ctx, 0x40052c, 0x55555555);
195 gr_def(ctx, 0x400530, 0x55555555);
196 cp_ctx(ctx, 0x400560, 6);
197 gr_def(ctx, 0x400568, 0x0000ffff);
198 gr_def(ctx, 0x40056c, 0x0000ffff);
199 cp_ctx(ctx, 0x40057c, 5);
200 cp_ctx(ctx, 0x400710, 3);
201 gr_def(ctx, 0x400710, 0x20010001);
202 gr_def(ctx, 0x400714, 0x0f73ef00);
203 cp_ctx(ctx, 0x400724, 1);
204 gr_def(ctx, 0x400724, 0x02008821);
205 cp_ctx(ctx, 0x400770, 3);
206 if (dev_priv->chipset == 0x40) {
207 cp_ctx(ctx, 0x400814, 4);
208 cp_ctx(ctx, 0x400828, 5);
209 cp_ctx(ctx, 0x400840, 5);
210 gr_def(ctx, 0x400850, 0x00000040);
211 cp_ctx(ctx, 0x400858, 4);
212 gr_def(ctx, 0x400858, 0x00000040);
213 gr_def(ctx, 0x40085c, 0x00000040);
214 gr_def(ctx, 0x400864, 0x80000000);
215 cp_ctx(ctx, 0x40086c, 9);
216 gr_def(ctx, 0x40086c, 0x80000000);
217 gr_def(ctx, 0x400870, 0x80000000);
218 gr_def(ctx, 0x400874, 0x80000000);
219 gr_def(ctx, 0x400878, 0x80000000);
220 gr_def(ctx, 0x400888, 0x00000040);
221 gr_def(ctx, 0x40088c, 0x80000000);
222 cp_ctx(ctx, 0x4009c0, 8);
223 gr_def(ctx, 0x4009cc, 0x80000000);
224 gr_def(ctx, 0x4009dc, 0x80000000);
225 } else {
226 cp_ctx(ctx, 0x400840, 20);
227 if (!nv40_graph_4097(ctx->dev)) {
228 for (i = 0; i < 8; i++)
229 gr_def(ctx, 0x400860 + (i * 4), 0x00000001);
230 }
231 gr_def(ctx, 0x400880, 0x00000040);
232 gr_def(ctx, 0x400884, 0x00000040);
233 gr_def(ctx, 0x400888, 0x00000040);
234 cp_ctx(ctx, 0x400894, 11);
235 gr_def(ctx, 0x400894, 0x00000040);
236 if (nv40_graph_4097(ctx->dev)) {
237 for (i = 0; i < 8; i++)
238 gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000);
239 }
240 cp_ctx(ctx, 0x4008e0, 2);
241 cp_ctx(ctx, 0x4008f8, 2);
242 if (dev_priv->chipset == 0x4c ||
243 (dev_priv->chipset & 0xf0) == 0x60)
244 cp_ctx(ctx, 0x4009f8, 1);
245 }
246 cp_ctx(ctx, 0x400a00, 73);
247 gr_def(ctx, 0x400b0c, 0x0b0b0b0c);
248 cp_ctx(ctx, 0x401000, 4);
249 cp_ctx(ctx, 0x405004, 1);
250 switch (dev_priv->chipset) {
251 case 0x47:
252 case 0x49:
253 case 0x4b:
254 cp_ctx(ctx, 0x403448, 1);
255 gr_def(ctx, 0x403448, 0x00001010);
256 break;
257 default:
258 cp_ctx(ctx, 0x403440, 1);
259 switch (dev_priv->chipset) {
260 case 0x40:
261 gr_def(ctx, 0x403440, 0x00000010);
262 break;
263 case 0x44:
264 case 0x46:
265 case 0x4a:
266 gr_def(ctx, 0x403440, 0x00003010);
267 break;
268 case 0x41:
269 case 0x42:
270 case 0x43:
271 case 0x4c:
272 case 0x4e:
273 case 0x67:
274 default:
275 gr_def(ctx, 0x403440, 0x00001010);
276 break;
277 }
278 break;
279 }
280}
281
282static void
283nv40_graph_construct_state3d(struct nouveau_grctx *ctx)
284{
285 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
286 int i;
287
288 if (dev_priv->chipset == 0x40) {
289 cp_ctx(ctx, 0x401880, 51);
290 gr_def(ctx, 0x401940, 0x00000100);
291 } else
292 if (dev_priv->chipset == 0x46 || dev_priv->chipset == 0x47 ||
293 dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b) {
294 cp_ctx(ctx, 0x401880, 32);
295 for (i = 0; i < 16; i++)
296 gr_def(ctx, 0x401880 + (i * 4), 0x00000111);
297 if (dev_priv->chipset == 0x46)
298 cp_ctx(ctx, 0x401900, 16);
299 cp_ctx(ctx, 0x401940, 3);
300 }
301 cp_ctx(ctx, 0x40194c, 18);
302 gr_def(ctx, 0x401954, 0x00000111);
303 gr_def(ctx, 0x401958, 0x00080060);
304 gr_def(ctx, 0x401974, 0x00000080);
305 gr_def(ctx, 0x401978, 0xffff0000);
306 gr_def(ctx, 0x40197c, 0x00000001);
307 gr_def(ctx, 0x401990, 0x46400000);
308 if (dev_priv->chipset == 0x40) {
309 cp_ctx(ctx, 0x4019a0, 2);
310 cp_ctx(ctx, 0x4019ac, 5);
311 } else {
312 cp_ctx(ctx, 0x4019a0, 1);
313 cp_ctx(ctx, 0x4019b4, 3);
314 }
315 gr_def(ctx, 0x4019bc, 0xffff0000);
316 switch (dev_priv->chipset) {
317 case 0x46:
318 case 0x47:
319 case 0x49:
320 case 0x4b:
321 cp_ctx(ctx, 0x4019c0, 18);
322 for (i = 0; i < 16; i++)
323 gr_def(ctx, 0x4019c0 + (i * 4), 0x88888888);
324 break;
325 }
326 cp_ctx(ctx, 0x401a08, 8);
327 gr_def(ctx, 0x401a10, 0x0fff0000);
328 gr_def(ctx, 0x401a14, 0x0fff0000);
329 gr_def(ctx, 0x401a1c, 0x00011100);
330 cp_ctx(ctx, 0x401a2c, 4);
331 cp_ctx(ctx, 0x401a44, 26);
332 for (i = 0; i < 16; i++)
333 gr_def(ctx, 0x401a44 + (i * 4), 0x07ff0000);
334 gr_def(ctx, 0x401a8c, 0x4b7fffff);
335 if (dev_priv->chipset == 0x40) {
336 cp_ctx(ctx, 0x401ab8, 3);
337 } else {
338 cp_ctx(ctx, 0x401ab8, 1);
339 cp_ctx(ctx, 0x401ac0, 1);
340 }
341 cp_ctx(ctx, 0x401ad0, 8);
342 gr_def(ctx, 0x401ad0, 0x30201000);
343 gr_def(ctx, 0x401ad4, 0x70605040);
344 gr_def(ctx, 0x401ad8, 0xb8a89888);
345 gr_def(ctx, 0x401adc, 0xf8e8d8c8);
346 cp_ctx(ctx, 0x401b10, dev_priv->chipset == 0x40 ? 2 : 1);
347 gr_def(ctx, 0x401b10, 0x40100000);
348 cp_ctx(ctx, 0x401b18, dev_priv->chipset == 0x40 ? 6 : 5);
349 gr_def(ctx, 0x401b28, dev_priv->chipset == 0x40 ?
350 0x00000004 : 0x00000000);
351 cp_ctx(ctx, 0x401b30, 25);
352 gr_def(ctx, 0x401b34, 0x0000ffff);
353 gr_def(ctx, 0x401b68, 0x435185d6);
354 gr_def(ctx, 0x401b6c, 0x2155b699);
355 gr_def(ctx, 0x401b70, 0xfedcba98);
356 gr_def(ctx, 0x401b74, 0x00000098);
357 gr_def(ctx, 0x401b84, 0xffffffff);
358 gr_def(ctx, 0x401b88, 0x00ff7000);
359 gr_def(ctx, 0x401b8c, 0x0000ffff);
360 if (dev_priv->chipset != 0x44 && dev_priv->chipset != 0x4a &&
361 dev_priv->chipset != 0x4e)
362 cp_ctx(ctx, 0x401b94, 1);
363 cp_ctx(ctx, 0x401b98, 8);
364 gr_def(ctx, 0x401b9c, 0x00ff0000);
365 cp_ctx(ctx, 0x401bc0, 9);
366 gr_def(ctx, 0x401be0, 0x00ffff00);
367 cp_ctx(ctx, 0x401c00, 192);
368 for (i = 0; i < 16; i++) { /* fragment texture units */
369 gr_def(ctx, 0x401c40 + (i * 4), 0x00018488);
370 gr_def(ctx, 0x401c80 + (i * 4), 0x00028202);
371 gr_def(ctx, 0x401d00 + (i * 4), 0x0000aae4);
372 gr_def(ctx, 0x401d40 + (i * 4), 0x01012000);
373 gr_def(ctx, 0x401d80 + (i * 4), 0x00080008);
374 gr_def(ctx, 0x401e00 + (i * 4), 0x00100008);
375 }
376 for (i = 0; i < 4; i++) { /* vertex texture units */
377 gr_def(ctx, 0x401e90 + (i * 4), 0x0001bc80);
378 gr_def(ctx, 0x401ea0 + (i * 4), 0x00000202);
379 gr_def(ctx, 0x401ec0 + (i * 4), 0x00000008);
380 gr_def(ctx, 0x401ee0 + (i * 4), 0x00080008);
381 }
382 cp_ctx(ctx, 0x400f5c, 3);
383 gr_def(ctx, 0x400f5c, 0x00000002);
384 cp_ctx(ctx, 0x400f84, 1);
385}
386
387static void
388nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx)
389{
390 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
391 int i;
392
393 cp_ctx(ctx, 0x402000, 1);
394 cp_ctx(ctx, 0x402404, dev_priv->chipset == 0x40 ? 1 : 2);
395 switch (dev_priv->chipset) {
396 case 0x40:
397 gr_def(ctx, 0x402404, 0x00000001);
398 break;
399 case 0x4c:
400 case 0x4e:
401 case 0x67:
402 gr_def(ctx, 0x402404, 0x00000020);
403 break;
404 case 0x46:
405 case 0x49:
406 case 0x4b:
407 gr_def(ctx, 0x402404, 0x00000421);
408 break;
409 default:
410 gr_def(ctx, 0x402404, 0x00000021);
411 }
412 if (dev_priv->chipset != 0x40)
413 gr_def(ctx, 0x402408, 0x030c30c3);
414 switch (dev_priv->chipset) {
415 case 0x44:
416 case 0x46:
417 case 0x4a:
418 case 0x4c:
419 case 0x4e:
420 case 0x67:
421 cp_ctx(ctx, 0x402440, 1);
422 gr_def(ctx, 0x402440, 0x00011001);
423 break;
424 default:
425 break;
426 }
427 cp_ctx(ctx, 0x402480, dev_priv->chipset == 0x40 ? 8 : 9);
428 gr_def(ctx, 0x402488, 0x3e020200);
429 gr_def(ctx, 0x40248c, 0x00ffffff);
430 switch (dev_priv->chipset) {
431 case 0x40:
432 gr_def(ctx, 0x402490, 0x60103f00);
433 break;
434 case 0x47:
435 gr_def(ctx, 0x402490, 0x40103f00);
436 break;
437 case 0x41:
438 case 0x42:
439 case 0x49:
440 case 0x4b:
441 gr_def(ctx, 0x402490, 0x20103f00);
442 break;
443 default:
444 gr_def(ctx, 0x402490, 0x0c103f00);
445 break;
446 }
447 gr_def(ctx, 0x40249c, dev_priv->chipset <= 0x43 ?
448 0x00020000 : 0x00040000);
449 cp_ctx(ctx, 0x402500, 31);
450 gr_def(ctx, 0x402530, 0x00008100);
451 if (dev_priv->chipset == 0x40)
452 cp_ctx(ctx, 0x40257c, 6);
453 cp_ctx(ctx, 0x402594, 16);
454 cp_ctx(ctx, 0x402800, 17);
455 gr_def(ctx, 0x402800, 0x00000001);
456 switch (dev_priv->chipset) {
457 case 0x47:
458 case 0x49:
459 case 0x4b:
460 cp_ctx(ctx, 0x402864, 1);
461 gr_def(ctx, 0x402864, 0x00001001);
462 cp_ctx(ctx, 0x402870, 3);
463 gr_def(ctx, 0x402878, 0x00000003);
464 if (dev_priv->chipset != 0x47) { /* belong at end!! */
465 cp_ctx(ctx, 0x402900, 1);
466 cp_ctx(ctx, 0x402940, 1);
467 cp_ctx(ctx, 0x402980, 1);
468 cp_ctx(ctx, 0x4029c0, 1);
469 cp_ctx(ctx, 0x402a00, 1);
470 cp_ctx(ctx, 0x402a40, 1);
471 cp_ctx(ctx, 0x402a80, 1);
472 cp_ctx(ctx, 0x402ac0, 1);
473 }
474 break;
475 case 0x40:
476 cp_ctx(ctx, 0x402844, 1);
477 gr_def(ctx, 0x402844, 0x00000001);
478 cp_ctx(ctx, 0x402850, 1);
479 break;
480 default:
481 cp_ctx(ctx, 0x402844, 1);
482 gr_def(ctx, 0x402844, 0x00001001);
483 cp_ctx(ctx, 0x402850, 2);
484 gr_def(ctx, 0x402854, 0x00000003);
485 break;
486 }
487
488 cp_ctx(ctx, 0x402c00, 4);
489 gr_def(ctx, 0x402c00, dev_priv->chipset == 0x40 ?
490 0x80800001 : 0x00888001);
491 switch (dev_priv->chipset) {
492 case 0x47:
493 case 0x49:
494 case 0x4b:
495 cp_ctx(ctx, 0x402c20, 40);
496 for (i = 0; i < 32; i++)
497 gr_def(ctx, 0x402c40 + (i * 4), 0xffffffff);
498 cp_ctx(ctx, 0x4030b8, 13);
499 gr_def(ctx, 0x4030dc, 0x00000005);
500 gr_def(ctx, 0x4030e8, 0x0000ffff);
501 break;
502 default:
503 cp_ctx(ctx, 0x402c10, 4);
504 if (dev_priv->chipset == 0x40)
505 cp_ctx(ctx, 0x402c20, 36);
506 else
507 if (dev_priv->chipset <= 0x42)
508 cp_ctx(ctx, 0x402c20, 24);
509 else
510 if (dev_priv->chipset <= 0x4a)
511 cp_ctx(ctx, 0x402c20, 16);
512 else
513 cp_ctx(ctx, 0x402c20, 8);
514 cp_ctx(ctx, 0x402cb0, dev_priv->chipset == 0x40 ? 12 : 13);
515 gr_def(ctx, 0x402cd4, 0x00000005);
516 if (dev_priv->chipset != 0x40)
517 gr_def(ctx, 0x402ce0, 0x0000ffff);
518 break;
519 }
520
521 cp_ctx(ctx, 0x403400, dev_priv->chipset == 0x40 ? 4 : 3);
522 cp_ctx(ctx, 0x403410, dev_priv->chipset == 0x40 ? 4 : 3);
523 cp_ctx(ctx, 0x403420, nv40_graph_vs_count(ctx->dev));
524 for (i = 0; i < nv40_graph_vs_count(ctx->dev); i++)
525 gr_def(ctx, 0x403420 + (i * 4), 0x00005555);
526
527 if (dev_priv->chipset != 0x40) {
528 cp_ctx(ctx, 0x403600, 1);
529 gr_def(ctx, 0x403600, 0x00000001);
530 }
531 cp_ctx(ctx, 0x403800, 1);
532
533 cp_ctx(ctx, 0x403c18, 1);
534 gr_def(ctx, 0x403c18, 0x00000001);
535 switch (dev_priv->chipset) {
536 case 0x46:
537 case 0x47:
538 case 0x49:
539 case 0x4b:
540 cp_ctx(ctx, 0x405018, 1);
541 gr_def(ctx, 0x405018, 0x08e00001);
542 cp_ctx(ctx, 0x405c24, 1);
543 gr_def(ctx, 0x405c24, 0x000e3000);
544 break;
545 }
546 if (dev_priv->chipset != 0x4e)
547 cp_ctx(ctx, 0x405800, 11);
548 cp_ctx(ctx, 0x407000, 1);
549}
550
551static void
552nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx)
553{
554 int len = nv40_graph_4097(ctx->dev) ? 0x0684 : 0x0084;
555
556 cp_out (ctx, 0x300000);
557 cp_lsr (ctx, len - 4);
558 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_swap_state3d_3_is_save);
559 cp_lsr (ctx, len);
560 cp_name(ctx, cp_swap_state3d_3_is_save);
561 cp_out (ctx, 0x800001);
562
563 ctx->ctxvals_pos += len;
564}
565
566static void
567nv40_graph_construct_shader(struct nouveau_grctx *ctx)
568{
569 struct drm_device *dev = ctx->dev;
570 struct drm_nouveau_private *dev_priv = dev->dev_private;
571 struct nouveau_gpuobj *obj = ctx->data;
572 int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset;
573 int offset, i;
574
575 vs_nr = nv40_graph_vs_count(ctx->dev);
576 vs_nr_b0 = 363;
577 vs_nr_b1 = dev_priv->chipset == 0x40 ? 128 : 64;
578 if (dev_priv->chipset == 0x40) {
579 b0_offset = 0x2200/4; /* 33a0 */
580 b1_offset = 0x55a0/4; /* 1500 */
581 vs_len = 0x6aa0/4;
582 } else
583 if (dev_priv->chipset == 0x41 || dev_priv->chipset == 0x42) {
584 b0_offset = 0x2200/4; /* 2200 */
585 b1_offset = 0x4400/4; /* 0b00 */
586 vs_len = 0x4f00/4;
587 } else {
588 b0_offset = 0x1d40/4; /* 2200 */
589 b1_offset = 0x3f40/4; /* 0b00 : 0a40 */
590 vs_len = nv40_graph_4097(dev) ? 0x4a40/4 : 0x4980/4;
591 }
592
593 cp_lsr(ctx, vs_len * vs_nr + 0x300/4);
594 cp_out(ctx, nv40_graph_4097(dev) ? 0x800041 : 0x800029);
595
596 offset = ctx->ctxvals_pos;
597 ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len));
598
599 if (ctx->mode != NOUVEAU_GRCTX_VALS)
600 return;
601
602 offset += 0x0280/4;
603 for (i = 0; i < 16; i++, offset += 2)
604 nv_wo32(dev, obj, offset, 0x3f800000);
605
606 for (vs = 0; vs < vs_nr; vs++, offset += vs_len) {
607 for (i = 0; i < vs_nr_b0 * 6; i += 6)
608 nv_wo32(dev, obj, offset + b0_offset + i, 0x00000001);
609 for (i = 0; i < vs_nr_b1 * 4; i += 4)
610 nv_wo32(dev, obj, offset + b1_offset + i, 0x3f800000);
611 }
612}
613
614void
615nv40_grctx_init(struct nouveau_grctx *ctx)
616{
617 /* decide whether we're loading/unloading the context */
618 cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
619 cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save);
620
621 cp_name(ctx, cp_check_load);
622 cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load);
623 cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load);
624 cp_bra (ctx, ALWAYS, TRUE, cp_exit);
625
626 /* setup for context load */
627 cp_name(ctx, cp_setup_auto_load);
628 cp_wait(ctx, STATUS, IDLE);
629 cp_out (ctx, CP_NEXT_TO_SWAP);
630 cp_name(ctx, cp_setup_load);
631 cp_wait(ctx, STATUS, IDLE);
632 cp_set (ctx, SWAP_DIRECTION, LOAD);
633 cp_out (ctx, 0x00910880); /* ?? */
634 cp_out (ctx, 0x00901ffe); /* ?? */
635 cp_out (ctx, 0x01940000); /* ?? */
636 cp_lsr (ctx, 0x20);
637 cp_out (ctx, 0x0060000b); /* ?? */
638 cp_wait(ctx, UNK57, CLEAR);
639 cp_out (ctx, 0x0060000c); /* ?? */
640 cp_bra (ctx, ALWAYS, TRUE, cp_swap_state);
641
642 /* setup for context save */
643 cp_name(ctx, cp_setup_save);
644 cp_set (ctx, SWAP_DIRECTION, SAVE);
645
646 /* general PGRAPH state */
647 cp_name(ctx, cp_swap_state);
648 cp_pos (ctx, 0x00020/4);
649 nv40_graph_construct_general(ctx);
650 cp_wait(ctx, STATUS, IDLE);
651
652 /* 3D state, block 1 */
653 cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit);
654 nv40_graph_construct_state3d(ctx);
655 cp_wait(ctx, STATUS, IDLE);
656
657 /* 3D state, block 2 */
658 nv40_graph_construct_state3d_2(ctx);
659
660 /* Some other block of "random" state */
661 nv40_graph_construct_state3d_3(ctx);
662
663 /* Per-vertex shader state */
664 cp_pos (ctx, ctx->ctxvals_pos);
665 nv40_graph_construct_shader(ctx);
666
667 /* pre-exit state updates */
668 cp_name(ctx, cp_prepare_exit);
669 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load);
670 cp_bra (ctx, USER_SAVE, PENDING, cp_exit);
671 cp_out (ctx, CP_NEXT_TO_CURRENT);
672
673 cp_name(ctx, cp_exit);
674 cp_set (ctx, USER_SAVE, NOT_PENDING);
675 cp_set (ctx, USER_LOAD, NOT_PENDING);
676 cp_out (ctx, CP_END);
677}
678
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
index f8e28a1e44e7..40b7360841f8 100644
--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -45,7 +45,7 @@ nv50_crtc_lut_load(struct drm_crtc *crtc)
45 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); 45 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
46 int i; 46 int i;
47 47
48 NV_DEBUG(crtc->dev, "\n"); 48 NV_DEBUG_KMS(crtc->dev, "\n");
49 49
50 for (i = 0; i < 256; i++) { 50 for (i = 0; i < 256; i++) {
51 writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0); 51 writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0);
@@ -68,8 +68,8 @@ nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
68 struct nouveau_channel *evo = dev_priv->evo; 68 struct nouveau_channel *evo = dev_priv->evo;
69 int index = nv_crtc->index, ret; 69 int index = nv_crtc->index, ret;
70 70
71 NV_DEBUG(dev, "index %d\n", nv_crtc->index); 71 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
72 NV_DEBUG(dev, "%s\n", blanked ? "blanked" : "unblanked"); 72 NV_DEBUG_KMS(dev, "%s\n", blanked ? "blanked" : "unblanked");
73 73
74 if (blanked) { 74 if (blanked) {
75 nv_crtc->cursor.hide(nv_crtc, false); 75 nv_crtc->cursor.hide(nv_crtc, false);
@@ -139,7 +139,7 @@ nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool on, bool update)
139 struct nouveau_channel *evo = dev_priv->evo; 139 struct nouveau_channel *evo = dev_priv->evo;
140 int ret; 140 int ret;
141 141
142 NV_DEBUG(dev, "\n"); 142 NV_DEBUG_KMS(dev, "\n");
143 143
144 ret = RING_SPACE(evo, 2 + (update ? 2 : 0)); 144 ret = RING_SPACE(evo, 2 + (update ? 2 : 0));
145 if (ret) { 145 if (ret) {
@@ -193,7 +193,7 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update)
193 uint32_t outX, outY, horiz, vert; 193 uint32_t outX, outY, horiz, vert;
194 int ret; 194 int ret;
195 195
196 NV_DEBUG(dev, "\n"); 196 NV_DEBUG_KMS(dev, "\n");
197 197
198 switch (scaling_mode) { 198 switch (scaling_mode) {
199 case DRM_MODE_SCALE_NONE: 199 case DRM_MODE_SCALE_NONE:
@@ -301,7 +301,7 @@ nv50_crtc_destroy(struct drm_crtc *crtc)
301 struct drm_device *dev = crtc->dev; 301 struct drm_device *dev = crtc->dev;
302 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 302 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
303 303
304 NV_DEBUG(dev, "\n"); 304 NV_DEBUG_KMS(dev, "\n");
305 305
306 if (!crtc) 306 if (!crtc)
307 return; 307 return;
@@ -432,16 +432,36 @@ nv50_crtc_prepare(struct drm_crtc *crtc)
432 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 432 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
433 struct drm_device *dev = crtc->dev; 433 struct drm_device *dev = crtc->dev;
434 struct drm_encoder *encoder; 434 struct drm_encoder *encoder;
435 uint32_t dac = 0, sor = 0;
435 436
436 NV_DEBUG(dev, "index %d\n", nv_crtc->index); 437 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
437 438
438 /* Disconnect all unused encoders. */ 439 /* Disconnect all unused encoders. */
439 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 440 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
440 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 441 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
441 442
442 if (drm_helper_encoder_in_use(encoder)) 443 if (!drm_helper_encoder_in_use(encoder))
443 continue; 444 continue;
444 445
446 if (nv_encoder->dcb->type == OUTPUT_ANALOG ||
447 nv_encoder->dcb->type == OUTPUT_TV)
448 dac |= (1 << nv_encoder->or);
449 else
450 sor |= (1 << nv_encoder->or);
451 }
452
453 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
454 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
455
456 if (nv_encoder->dcb->type == OUTPUT_ANALOG ||
457 nv_encoder->dcb->type == OUTPUT_TV) {
458 if (dac & (1 << nv_encoder->or))
459 continue;
460 } else {
461 if (sor & (1 << nv_encoder->or))
462 continue;
463 }
464
445 nv_encoder->disconnect(nv_encoder); 465 nv_encoder->disconnect(nv_encoder);
446 } 466 }
447 467
@@ -458,7 +478,7 @@ nv50_crtc_commit(struct drm_crtc *crtc)
458 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 478 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
459 int ret; 479 int ret;
460 480
461 NV_DEBUG(dev, "index %d\n", nv_crtc->index); 481 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
462 482
463 nv50_crtc_blank(nv_crtc, false); 483 nv50_crtc_blank(nv_crtc, false);
464 484
@@ -497,7 +517,7 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, int x, int y,
497 struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb); 517 struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb);
498 int ret, format; 518 int ret, format;
499 519
500 NV_DEBUG(dev, "index %d\n", nv_crtc->index); 520 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
501 521
502 switch (drm_fb->depth) { 522 switch (drm_fb->depth) {
503 case 8: 523 case 8:
@@ -612,7 +632,7 @@ nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
612 632
613 *nv_crtc->mode = *adjusted_mode; 633 *nv_crtc->mode = *adjusted_mode;
614 634
615 NV_DEBUG(dev, "index %d\n", nv_crtc->index); 635 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
616 636
617 hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 637 hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
618 vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 638 vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
@@ -706,7 +726,7 @@ nv50_crtc_create(struct drm_device *dev, int index)
706 struct nouveau_crtc *nv_crtc = NULL; 726 struct nouveau_crtc *nv_crtc = NULL;
707 int ret, i; 727 int ret, i;
708 728
709 NV_DEBUG(dev, "\n"); 729 NV_DEBUG_KMS(dev, "\n");
710 730
711 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); 731 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
712 if (!nv_crtc) 732 if (!nv_crtc)
diff --git a/drivers/gpu/drm/nouveau/nv50_cursor.c b/drivers/gpu/drm/nouveau/nv50_cursor.c
index e2e79a8f220d..753e723adb3a 100644
--- a/drivers/gpu/drm/nouveau/nv50_cursor.c
+++ b/drivers/gpu/drm/nouveau/nv50_cursor.c
@@ -41,7 +41,7 @@ nv50_cursor_show(struct nouveau_crtc *nv_crtc, bool update)
41 struct drm_device *dev = nv_crtc->base.dev; 41 struct drm_device *dev = nv_crtc->base.dev;
42 int ret; 42 int ret;
43 43
44 NV_DEBUG(dev, "\n"); 44 NV_DEBUG_KMS(dev, "\n");
45 45
46 if (update && nv_crtc->cursor.visible) 46 if (update && nv_crtc->cursor.visible)
47 return; 47 return;
@@ -76,7 +76,7 @@ nv50_cursor_hide(struct nouveau_crtc *nv_crtc, bool update)
76 struct drm_device *dev = nv_crtc->base.dev; 76 struct drm_device *dev = nv_crtc->base.dev;
77 int ret; 77 int ret;
78 78
79 NV_DEBUG(dev, "\n"); 79 NV_DEBUG_KMS(dev, "\n");
80 80
81 if (update && !nv_crtc->cursor.visible) 81 if (update && !nv_crtc->cursor.visible)
82 return; 82 return;
@@ -116,7 +116,7 @@ nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
116static void 116static void
117nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) 117nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
118{ 118{
119 NV_DEBUG(nv_crtc->base.dev, "\n"); 119 NV_DEBUG_KMS(nv_crtc->base.dev, "\n");
120 if (offset == nv_crtc->cursor.offset) 120 if (offset == nv_crtc->cursor.offset)
121 return; 121 return;
122 122
@@ -143,7 +143,7 @@ nv50_cursor_fini(struct nouveau_crtc *nv_crtc)
143 struct drm_device *dev = nv_crtc->base.dev; 143 struct drm_device *dev = nv_crtc->base.dev;
144 int idx = nv_crtc->index; 144 int idx = nv_crtc->index;
145 145
146 NV_DEBUG(dev, "\n"); 146 NV_DEBUG_KMS(dev, "\n");
147 147
148 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(idx), 0); 148 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(idx), 0);
149 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(idx), 149 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(idx),
diff --git a/drivers/gpu/drm/nouveau/nv50_dac.c b/drivers/gpu/drm/nouveau/nv50_dac.c
index fb5838e3be24..f08f042a8e10 100644
--- a/drivers/gpu/drm/nouveau/nv50_dac.c
+++ b/drivers/gpu/drm/nouveau/nv50_dac.c
@@ -44,7 +44,7 @@ nv50_dac_disconnect(struct nouveau_encoder *nv_encoder)
44 struct nouveau_channel *evo = dev_priv->evo; 44 struct nouveau_channel *evo = dev_priv->evo;
45 int ret; 45 int ret;
46 46
47 NV_DEBUG(dev, "Disconnecting DAC %d\n", nv_encoder->or); 47 NV_DEBUG_KMS(dev, "Disconnecting DAC %d\n", nv_encoder->or);
48 48
49 ret = RING_SPACE(evo, 2); 49 ret = RING_SPACE(evo, 2);
50 if (ret) { 50 if (ret) {
@@ -81,11 +81,11 @@ nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
81 /* Use bios provided value if possible. */ 81 /* Use bios provided value if possible. */
82 if (dev_priv->vbios->dactestval) { 82 if (dev_priv->vbios->dactestval) {
83 load_pattern = dev_priv->vbios->dactestval; 83 load_pattern = dev_priv->vbios->dactestval;
84 NV_DEBUG(dev, "Using bios provided load_pattern of %d\n", 84 NV_DEBUG_KMS(dev, "Using bios provided load_pattern of %d\n",
85 load_pattern); 85 load_pattern);
86 } else { 86 } else {
87 load_pattern = 340; 87 load_pattern = 340;
88 NV_DEBUG(dev, "Using default load_pattern of %d\n", 88 NV_DEBUG_KMS(dev, "Using default load_pattern of %d\n",
89 load_pattern); 89 load_pattern);
90 } 90 }
91 91
@@ -103,9 +103,9 @@ nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
103 status = connector_status_connected; 103 status = connector_status_connected;
104 104
105 if (status == connector_status_connected) 105 if (status == connector_status_connected)
106 NV_DEBUG(dev, "Load was detected on output with or %d\n", or); 106 NV_DEBUG_KMS(dev, "Load was detected on output with or %d\n", or);
107 else 107 else
108 NV_DEBUG(dev, "Load was not detected on output with or %d\n", or); 108 NV_DEBUG_KMS(dev, "Load was not detected on output with or %d\n", or);
109 109
110 return status; 110 return status;
111} 111}
@@ -118,7 +118,7 @@ nv50_dac_dpms(struct drm_encoder *encoder, int mode)
118 uint32_t val; 118 uint32_t val;
119 int or = nv_encoder->or; 119 int or = nv_encoder->or;
120 120
121 NV_DEBUG(dev, "or %d mode %d\n", or, mode); 121 NV_DEBUG_KMS(dev, "or %d mode %d\n", or, mode);
122 122
123 /* wait for it to be done */ 123 /* wait for it to be done */
124 if (!nv_wait(NV50_PDISPLAY_DAC_DPMS_CTRL(or), 124 if (!nv_wait(NV50_PDISPLAY_DAC_DPMS_CTRL(or),
@@ -173,7 +173,7 @@ nv50_dac_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
173 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 173 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
174 struct nouveau_connector *connector; 174 struct nouveau_connector *connector;
175 175
176 NV_DEBUG(encoder->dev, "or %d\n", nv_encoder->or); 176 NV_DEBUG_KMS(encoder->dev, "or %d\n", nv_encoder->or);
177 177
178 connector = nouveau_encoder_connector_get(nv_encoder); 178 connector = nouveau_encoder_connector_get(nv_encoder);
179 if (!connector) { 179 if (!connector) {
@@ -213,7 +213,7 @@ nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
213 uint32_t mode_ctl = 0, mode_ctl2 = 0; 213 uint32_t mode_ctl = 0, mode_ctl2 = 0;
214 int ret; 214 int ret;
215 215
216 NV_DEBUG(dev, "or %d\n", nv_encoder->or); 216 NV_DEBUG_KMS(dev, "or %d\n", nv_encoder->or);
217 217
218 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON); 218 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
219 219
@@ -264,7 +264,7 @@ nv50_dac_destroy(struct drm_encoder *encoder)
264 if (!encoder) 264 if (!encoder)
265 return; 265 return;
266 266
267 NV_DEBUG(encoder->dev, "\n"); 267 NV_DEBUG_KMS(encoder->dev, "\n");
268 268
269 drm_encoder_cleanup(encoder); 269 drm_encoder_cleanup(encoder);
270 kfree(nv_encoder); 270 kfree(nv_encoder);
@@ -280,7 +280,7 @@ nv50_dac_create(struct drm_device *dev, struct dcb_entry *entry)
280 struct nouveau_encoder *nv_encoder; 280 struct nouveau_encoder *nv_encoder;
281 struct drm_encoder *encoder; 281 struct drm_encoder *encoder;
282 282
283 NV_DEBUG(dev, "\n"); 283 NV_DEBUG_KMS(dev, "\n");
284 NV_INFO(dev, "Detected a DAC output\n"); 284 NV_INFO(dev, "Detected a DAC output\n");
285 285
286 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 286 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 12c5ee63495b..90f0bf59fbcd 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -188,7 +188,7 @@ nv50_display_init(struct drm_device *dev)
188 uint64_t start; 188 uint64_t start;
189 int ret, i; 189 int ret, i;
190 190
191 NV_DEBUG(dev, "\n"); 191 NV_DEBUG_KMS(dev, "\n");
192 192
193 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004)); 193 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
194 /* 194 /*
@@ -232,7 +232,7 @@ nv50_display_init(struct drm_device *dev)
232 nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0); 232 nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
233 /* RAM is clamped to 256 MiB. */ 233 /* RAM is clamped to 256 MiB. */
234 ram_amount = nouveau_mem_fb_amount(dev); 234 ram_amount = nouveau_mem_fb_amount(dev);
235 NV_DEBUG(dev, "ram_amount %d\n", ram_amount); 235 NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
236 if (ram_amount > 256*1024*1024) 236 if (ram_amount > 256*1024*1024)
237 ram_amount = 256*1024*1024; 237 ram_amount = 256*1024*1024;
238 nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1); 238 nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
@@ -398,7 +398,7 @@ static int nv50_display_disable(struct drm_device *dev)
398 struct drm_crtc *drm_crtc; 398 struct drm_crtc *drm_crtc;
399 int ret, i; 399 int ret, i;
400 400
401 NV_DEBUG(dev, "\n"); 401 NV_DEBUG_KMS(dev, "\n");
402 402
403 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) { 403 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
404 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc); 404 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
@@ -469,7 +469,7 @@ int nv50_display_create(struct drm_device *dev)
469 uint32_t connector[16] = {}; 469 uint32_t connector[16] = {};
470 int ret, i; 470 int ret, i;
471 471
472 NV_DEBUG(dev, "\n"); 472 NV_DEBUG_KMS(dev, "\n");
473 473
474 /* init basic kernel modesetting */ 474 /* init basic kernel modesetting */
475 drm_mode_config_init(dev); 475 drm_mode_config_init(dev);
@@ -573,7 +573,7 @@ int nv50_display_destroy(struct drm_device *dev)
573{ 573{
574 struct drm_nouveau_private *dev_priv = dev->dev_private; 574 struct drm_nouveau_private *dev_priv = dev->dev_private;
575 575
576 NV_DEBUG(dev, "\n"); 576 NV_DEBUG_KMS(dev, "\n");
577 577
578 drm_mode_config_cleanup(dev); 578 drm_mode_config_cleanup(dev);
579 579
@@ -617,7 +617,7 @@ nv50_display_irq_head(struct drm_device *dev, int *phead,
617 * CRTC separately, and submission will be blocked by the GPU 617 * CRTC separately, and submission will be blocked by the GPU
618 * until we handle each in turn. 618 * until we handle each in turn.
619 */ 619 */
620 NV_DEBUG(dev, "0x610030: 0x%08x\n", unk30); 620 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
621 head = ffs((unk30 >> 9) & 3) - 1; 621 head = ffs((unk30 >> 9) & 3) - 1;
622 if (head < 0) 622 if (head < 0)
623 return -EINVAL; 623 return -EINVAL;
@@ -661,7 +661,7 @@ nv50_display_irq_head(struct drm_device *dev, int *phead,
661 or = i; 661 or = i;
662 } 662 }
663 663
664 NV_DEBUG(dev, "type %d, or %d\n", type, or); 664 NV_DEBUG_KMS(dev, "type %d, or %d\n", type, or);
665 if (type == OUTPUT_ANY) { 665 if (type == OUTPUT_ANY) {
666 NV_ERROR(dev, "unknown encoder!!\n"); 666 NV_ERROR(dev, "unknown encoder!!\n");
667 return -1; 667 return -1;
@@ -690,9 +690,21 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcbent,
690 int pxclk) 690 int pxclk)
691{ 691{
692 struct drm_nouveau_private *dev_priv = dev->dev_private; 692 struct drm_nouveau_private *dev_priv = dev->dev_private;
693 struct nouveau_connector *nv_connector = NULL;
694 struct drm_encoder *encoder;
693 struct nvbios *bios = &dev_priv->VBIOS; 695 struct nvbios *bios = &dev_priv->VBIOS;
694 uint32_t mc, script = 0, or; 696 uint32_t mc, script = 0, or;
695 697
698 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
699 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
700
701 if (nv_encoder->dcb != dcbent)
702 continue;
703
704 nv_connector = nouveau_encoder_connector_get(nv_encoder);
705 break;
706 }
707
696 or = ffs(dcbent->or) - 1; 708 or = ffs(dcbent->or) - 1;
697 mc = nv50_display_mode_ctrl(dev, dcbent->type != OUTPUT_ANALOG, or); 709 mc = nv50_display_mode_ctrl(dev, dcbent->type != OUTPUT_ANALOG, or);
698 switch (dcbent->type) { 710 switch (dcbent->type) {
@@ -711,6 +723,11 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcbent,
711 } else 723 } else
712 if (bios->fp.strapless_is_24bit & 1) 724 if (bios->fp.strapless_is_24bit & 1)
713 script |= 0x0200; 725 script |= 0x0200;
726
727 if (nv_connector && nv_connector->edid &&
728 (nv_connector->edid->revision >= 4) &&
729 (nv_connector->edid->input & 0x70) >= 0x20)
730 script |= 0x0200;
714 } 731 }
715 732
716 if (nouveau_uscript_lvds >= 0) { 733 if (nouveau_uscript_lvds >= 0) {
@@ -811,7 +828,7 @@ nv50_display_unk20_handler(struct drm_device *dev)
811 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff; 828 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff;
812 script = nv50_display_script_select(dev, dcbent, pclk); 829 script = nv50_display_script_select(dev, dcbent, pclk);
813 830
814 NV_DEBUG(dev, "head %d pxclk: %dKHz\n", head, pclk); 831 NV_DEBUG_KMS(dev, "head %d pxclk: %dKHz\n", head, pclk);
815 832
816 if (dcbent->type != OUTPUT_DP) 833 if (dcbent->type != OUTPUT_DP)
817 nouveau_bios_run_display_table(dev, dcbent, 0, -2); 834 nouveau_bios_run_display_table(dev, dcbent, 0, -2);
@@ -870,7 +887,7 @@ nv50_display_irq_handler_bh(struct work_struct *work)
870 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); 887 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
871 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); 888 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
872 889
873 NV_DEBUG(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1); 890 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
874 891
875 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10) 892 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
876 nv50_display_unk10_handler(dev); 893 nv50_display_unk10_handler(dev);
@@ -974,7 +991,7 @@ nv50_display_irq_handler(struct drm_device *dev)
974 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); 991 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
975 uint32_t clock; 992 uint32_t clock;
976 993
977 NV_DEBUG(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1); 994 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
978 995
979 if (!intr0 && !(intr1 & ~delayed)) 996 if (!intr0 && !(intr1 & ~delayed))
980 break; 997 break;
diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c
index 6bcc6d39e9b0..e4f279ee61cf 100644
--- a/drivers/gpu/drm/nouveau/nv50_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c
@@ -16,9 +16,7 @@ nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
16 16
17 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && 17 if (!(info->flags & FBINFO_HWACCEL_DISABLED) &&
18 RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11)) { 18 RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11)) {
19 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 19 nouveau_fbcon_gpu_lockup(info);
20
21 info->flags |= FBINFO_HWACCEL_DISABLED;
22 } 20 }
23 21
24 if (info->flags & FBINFO_HWACCEL_DISABLED) { 22 if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -31,7 +29,11 @@ nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
31 OUT_RING(chan, 1); 29 OUT_RING(chan, 1);
32 } 30 }
33 BEGIN_RING(chan, NvSub2D, 0x0588, 1); 31 BEGIN_RING(chan, NvSub2D, 0x0588, 1);
34 OUT_RING(chan, rect->color); 32 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
33 info->fix.visual == FB_VISUAL_DIRECTCOLOR)
34 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
35 else
36 OUT_RING(chan, rect->color);
35 BEGIN_RING(chan, NvSub2D, 0x0600, 4); 37 BEGIN_RING(chan, NvSub2D, 0x0600, 4);
36 OUT_RING(chan, rect->dx); 38 OUT_RING(chan, rect->dx);
37 OUT_RING(chan, rect->dy); 39 OUT_RING(chan, rect->dy);
@@ -56,9 +58,7 @@ nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
56 return; 58 return;
57 59
58 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 12)) { 60 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 12)) {
59 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 61 nouveau_fbcon_gpu_lockup(info);
60
61 info->flags |= FBINFO_HWACCEL_DISABLED;
62 } 62 }
63 63
64 if (info->flags & FBINFO_HWACCEL_DISABLED) { 64 if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -101,8 +101,7 @@ nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
101 } 101 }
102 102
103 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 11)) { 103 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 11)) {
104 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 104 nouveau_fbcon_gpu_lockup(info);
105 info->flags |= FBINFO_HWACCEL_DISABLED;
106 } 105 }
107 106
108 if (info->flags & FBINFO_HWACCEL_DISABLED) { 107 if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -135,9 +134,7 @@ nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
135 int push = dwords > 2047 ? 2047 : dwords; 134 int push = dwords > 2047 ? 2047 : dwords;
136 135
137 if (RING_SPACE(chan, push + 1)) { 136 if (RING_SPACE(chan, push + 1)) {
138 NV_ERROR(dev, 137 nouveau_fbcon_gpu_lockup(info);
139 "GPU lockup - switching to software fbcon\n");
140 info->flags |= FBINFO_HWACCEL_DISABLED;
141 cfb_imageblit(info, image); 138 cfb_imageblit(info, image);
142 return; 139 return;
143 } 140 }
@@ -199,7 +196,7 @@ nv50_fbcon_accel_init(struct fb_info *info)
199 196
200 ret = RING_SPACE(chan, 59); 197 ret = RING_SPACE(chan, 59);
201 if (ret) { 198 if (ret) {
202 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"); 199 nouveau_fbcon_gpu_lockup(info);
203 return ret; 200 return ret;
204 } 201 }
205 202
diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c
index 77ae1aaa0bce..32b244bcb482 100644
--- a/drivers/gpu/drm/nouveau/nv50_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv50_fifo.c
@@ -272,7 +272,7 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
272 return ret; 272 return ret;
273 ramfc = chan->ramfc->gpuobj; 273 ramfc = chan->ramfc->gpuobj;
274 274
275 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096, 256, 275 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096, 1024,
276 0, &chan->cache); 276 0, &chan->cache);
277 if (ret) 277 if (ret)
278 return ret; 278 return ret;
@@ -384,8 +384,8 @@ nv50_fifo_load_context(struct nouveau_channel *chan)
384 nv_wr32(dev, NV40_PFIFO_CACHE1_DATA(ptr), 384 nv_wr32(dev, NV40_PFIFO_CACHE1_DATA(ptr),
385 nv_ro32(dev, cache, (ptr * 2) + 1)); 385 nv_ro32(dev, cache, (ptr * 2) + 1));
386 } 386 }
387 nv_wr32(dev, 0x3210, cnt << 2); 387 nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, cnt << 2);
388 nv_wr32(dev, 0x3270, 0); 388 nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
389 389
390 /* guessing that all the 0x34xx regs aren't on NV50 */ 390 /* guessing that all the 0x34xx regs aren't on NV50 */
391 if (!IS_G80) { 391 if (!IS_G80) {
@@ -398,8 +398,6 @@ nv50_fifo_load_context(struct nouveau_channel *chan)
398 398
399 dev_priv->engine.instmem.finish_access(dev); 399 dev_priv->engine.instmem.finish_access(dev);
400 400
401 nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
402 nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
403 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16)); 401 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16));
404 return 0; 402 return 0;
405} 403}
@@ -416,7 +414,7 @@ nv50_fifo_unload_context(struct drm_device *dev)
416 NV_DEBUG(dev, "\n"); 414 NV_DEBUG(dev, "\n");
417 415
418 chid = pfifo->channel_id(dev); 416 chid = pfifo->channel_id(dev);
419 if (chid < 0 || chid >= dev_priv->engine.fifo.channels) 417 if (chid < 1 || chid >= dev_priv->engine.fifo.channels - 1)
420 return 0; 418 return 0;
421 419
422 chan = dev_priv->fifos[chid]; 420 chan = dev_priv->fifos[chid];
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index 177d8229336f..20319e59d368 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -84,7 +84,7 @@ nv50_graph_init_regs__nv(struct drm_device *dev)
84 nv_wr32(dev, 0x400804, 0xc0000000); 84 nv_wr32(dev, 0x400804, 0xc0000000);
85 nv_wr32(dev, 0x406800, 0xc0000000); 85 nv_wr32(dev, 0x406800, 0xc0000000);
86 nv_wr32(dev, 0x400c04, 0xc0000000); 86 nv_wr32(dev, 0x400c04, 0xc0000000);
87 nv_wr32(dev, 0x401804, 0xc0000000); 87 nv_wr32(dev, 0x401800, 0xc0000000);
88 nv_wr32(dev, 0x405018, 0xc0000000); 88 nv_wr32(dev, 0x405018, 0xc0000000);
89 nv_wr32(dev, 0x402000, 0xc0000000); 89 nv_wr32(dev, 0x402000, 0xc0000000);
90 90
@@ -107,9 +107,13 @@ nv50_graph_init_regs(struct drm_device *dev)
107static int 107static int
108nv50_graph_init_ctxctl(struct drm_device *dev) 108nv50_graph_init_ctxctl(struct drm_device *dev)
109{ 109{
110 struct drm_nouveau_private *dev_priv = dev->dev_private;
111
110 NV_DEBUG(dev, "\n"); 112 NV_DEBUG(dev, "\n");
111 113
112 nv40_grctx_init(dev); 114 nouveau_grctx_prog_load(dev);
115 if (!dev_priv->engine.graph.ctxprog)
116 dev_priv->engine.graph.accel_blocked = true;
113 117
114 nv_wr32(dev, 0x400320, 4); 118 nv_wr32(dev, 0x400320, 4);
115 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0); 119 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
@@ -140,7 +144,7 @@ void
140nv50_graph_takedown(struct drm_device *dev) 144nv50_graph_takedown(struct drm_device *dev)
141{ 145{
142 NV_DEBUG(dev, "\n"); 146 NV_DEBUG(dev, "\n");
143 nv40_grctx_fini(dev); 147 nouveau_grctx_fini(dev);
144} 148}
145 149
146void 150void
@@ -207,7 +211,7 @@ nv50_graph_create_context(struct nouveau_channel *chan)
207 dev_priv->engine.instmem.finish_access(dev); 211 dev_priv->engine.instmem.finish_access(dev);
208 212
209 dev_priv->engine.instmem.prepare_access(dev, true); 213 dev_priv->engine.instmem.prepare_access(dev, true);
210 nv40_grctx_vals_load(dev, ctx); 214 nouveau_grctx_vals_load(dev, ctx);
211 nv_wo32(dev, ctx, 0x00000/4, chan->ramin->instance >> 12); 215 nv_wo32(dev, ctx, 0x00000/4, chan->ramin->instance >> 12);
212 if ((dev_priv->chipset & 0xf0) == 0xa0) 216 if ((dev_priv->chipset & 0xf0) == 0xa0)
213 nv_wo32(dev, ctx, 0x00004/4, 0x00000000); 217 nv_wo32(dev, ctx, 0x00004/4, 0x00000000);
@@ -278,6 +282,7 @@ nv50_graph_unload_context(struct drm_device *dev)
278 return 0; 282 return 0;
279 inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE; 283 inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
280 284
285 nouveau_wait_for_idle(dev);
281 nv_wr32(dev, 0x400500, fifo & ~1); 286 nv_wr32(dev, 0x400500, fifo & ~1);
282 nv_wr32(dev, 0x400784, inst); 287 nv_wr32(dev, 0x400784, inst);
283 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20); 288 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c
index 8c280463a664..ecf1936b8224 100644
--- a/drivers/gpu/drm/nouveau/nv50_sor.c
+++ b/drivers/gpu/drm/nouveau/nv50_sor.c
@@ -44,7 +44,7 @@ nv50_sor_disconnect(struct nouveau_encoder *nv_encoder)
44 struct nouveau_channel *evo = dev_priv->evo; 44 struct nouveau_channel *evo = dev_priv->evo;
45 int ret; 45 int ret;
46 46
47 NV_DEBUG(dev, "Disconnecting SOR %d\n", nv_encoder->or); 47 NV_DEBUG_KMS(dev, "Disconnecting SOR %d\n", nv_encoder->or);
48 48
49 ret = RING_SPACE(evo, 2); 49 ret = RING_SPACE(evo, 2);
50 if (ret) { 50 if (ret) {
@@ -70,7 +70,7 @@ nv50_sor_dp_link_train(struct drm_encoder *encoder)
70 } 70 }
71 71
72 if (dpe->script0) { 72 if (dpe->script0) {
73 NV_DEBUG(dev, "SOR-%d: running DP script 0\n", nv_encoder->or); 73 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 0\n", nv_encoder->or);
74 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script0), 74 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script0),
75 nv_encoder->dcb); 75 nv_encoder->dcb);
76 } 76 }
@@ -79,7 +79,7 @@ nv50_sor_dp_link_train(struct drm_encoder *encoder)
79 NV_ERROR(dev, "SOR-%d: link training failed\n", nv_encoder->or); 79 NV_ERROR(dev, "SOR-%d: link training failed\n", nv_encoder->or);
80 80
81 if (dpe->script1) { 81 if (dpe->script1) {
82 NV_DEBUG(dev, "SOR-%d: running DP script 1\n", nv_encoder->or); 82 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 1\n", nv_encoder->or);
83 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script1), 83 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script1),
84 nv_encoder->dcb); 84 nv_encoder->dcb);
85 } 85 }
@@ -90,10 +90,23 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
90{ 90{
91 struct drm_device *dev = encoder->dev; 91 struct drm_device *dev = encoder->dev;
92 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 92 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
93 struct drm_encoder *enc;
93 uint32_t val; 94 uint32_t val;
94 int or = nv_encoder->or; 95 int or = nv_encoder->or;
95 96
96 NV_DEBUG(dev, "or %d mode %d\n", or, mode); 97 NV_DEBUG_KMS(dev, "or %d mode %d\n", or, mode);
98
99 nv_encoder->last_dpms = mode;
100 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
101 struct nouveau_encoder *nvenc = nouveau_encoder(enc);
102
103 if (nvenc == nv_encoder ||
104 nvenc->dcb->or != nv_encoder->dcb->or)
105 continue;
106
107 if (nvenc->last_dpms == DRM_MODE_DPMS_ON)
108 return;
109 }
97 110
98 /* wait for it to be done */ 111 /* wait for it to be done */
99 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_CTRL(or), 112 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_CTRL(or),
@@ -142,7 +155,7 @@ nv50_sor_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
142 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 155 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
143 struct nouveau_connector *connector; 156 struct nouveau_connector *connector;
144 157
145 NV_DEBUG(encoder->dev, "or %d\n", nv_encoder->or); 158 NV_DEBUG_KMS(encoder->dev, "or %d\n", nv_encoder->or);
146 159
147 connector = nouveau_encoder_connector_get(nv_encoder); 160 connector = nouveau_encoder_connector_get(nv_encoder);
148 if (!connector) { 161 if (!connector) {
@@ -182,7 +195,7 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
182 uint32_t mode_ctl = 0; 195 uint32_t mode_ctl = 0;
183 int ret; 196 int ret;
184 197
185 NV_DEBUG(dev, "or %d\n", nv_encoder->or); 198 NV_DEBUG_KMS(dev, "or %d\n", nv_encoder->or);
186 199
187 nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON); 200 nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON);
188 201
@@ -246,7 +259,7 @@ nv50_sor_destroy(struct drm_encoder *encoder)
246 if (!encoder) 259 if (!encoder)
247 return; 260 return;
248 261
249 NV_DEBUG(encoder->dev, "\n"); 262 NV_DEBUG_KMS(encoder->dev, "\n");
250 263
251 drm_encoder_cleanup(encoder); 264 drm_encoder_cleanup(encoder);
252 265
@@ -265,7 +278,7 @@ nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry)
265 bool dum; 278 bool dum;
266 int type; 279 int type;
267 280
268 NV_DEBUG(dev, "\n"); 281 NV_DEBUG_KMS(dev, "\n");
269 282
270 switch (entry->type) { 283 switch (entry->type) {
271 case OUTPUT_TMDS: 284 case OUTPUT_TMDS:
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 2920f9a279e1..8036b6e189ee 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -426,7 +426,8 @@ moved:
426 bdev->man[bo->mem.mem_type].gpu_offset; 426 bdev->man[bo->mem.mem_type].gpu_offset;
427 bo->cur_placement = bo->mem.placement; 427 bo->cur_placement = bo->mem.placement;
428 spin_unlock(&bo->lock); 428 spin_unlock(&bo->lock);
429 } 429 } else
430 bo->offset = 0;
430 431
431 return 0; 432 return 0;
432 433
@@ -523,52 +524,44 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
523static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) 524static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all)
524{ 525{
525 struct ttm_bo_global *glob = bdev->glob; 526 struct ttm_bo_global *glob = bdev->glob;
526 struct ttm_buffer_object *entry, *nentry; 527 struct ttm_buffer_object *entry = NULL;
527 struct list_head *list, *next; 528 int ret = 0;
528 int ret;
529 529
530 spin_lock(&glob->lru_lock); 530 spin_lock(&glob->lru_lock);
531 list_for_each_safe(list, next, &bdev->ddestroy) { 531 if (list_empty(&bdev->ddestroy))
532 entry = list_entry(list, struct ttm_buffer_object, ddestroy); 532 goto out_unlock;
533 nentry = NULL;
534 533
535 /* 534 entry = list_first_entry(&bdev->ddestroy,
536 * Protect the next list entry from destruction while we 535 struct ttm_buffer_object, ddestroy);
537 * unlock the lru_lock. 536 kref_get(&entry->list_kref);
538 */ 537
538 for (;;) {
539 struct ttm_buffer_object *nentry = NULL;
539 540
540 if (next != &bdev->ddestroy) { 541 if (entry->ddestroy.next != &bdev->ddestroy) {
541 nentry = list_entry(next, struct ttm_buffer_object, 542 nentry = list_first_entry(&entry->ddestroy,
542 ddestroy); 543 struct ttm_buffer_object, ddestroy);
543 kref_get(&nentry->list_kref); 544 kref_get(&nentry->list_kref);
544 } 545 }
545 kref_get(&entry->list_kref);
546 546
547 spin_unlock(&glob->lru_lock); 547 spin_unlock(&glob->lru_lock);
548 ret = ttm_bo_cleanup_refs(entry, remove_all); 548 ret = ttm_bo_cleanup_refs(entry, remove_all);
549 kref_put(&entry->list_kref, ttm_bo_release_list); 549 kref_put(&entry->list_kref, ttm_bo_release_list);
550 entry = nentry;
551
552 if (ret || !entry)
553 goto out;
550 554
551 spin_lock(&glob->lru_lock); 555 spin_lock(&glob->lru_lock);
552 if (nentry) { 556 if (list_empty(&entry->ddestroy))
553 bool next_onlist = !list_empty(next);
554 spin_unlock(&glob->lru_lock);
555 kref_put(&nentry->list_kref, ttm_bo_release_list);
556 spin_lock(&glob->lru_lock);
557 /*
558 * Someone might have raced us and removed the
559 * next entry from the list. We don't bother restarting
560 * list traversal.
561 */
562
563 if (!next_onlist)
564 break;
565 }
566 if (ret)
567 break; 557 break;
568 } 558 }
569 ret = !list_empty(&bdev->ddestroy);
570 spin_unlock(&glob->lru_lock);
571 559
560out_unlock:
561 spin_unlock(&glob->lru_lock);
562out:
563 if (entry)
564 kref_put(&entry->list_kref, ttm_bo_release_list);
572 return ret; 565 return ret;
573} 566}
574 567
@@ -1844,6 +1837,9 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink)
1844 * anyone tries to access a ttm page. 1837 * anyone tries to access a ttm page.
1845 */ 1838 */
1846 1839
1840 if (bo->bdev->driver->swap_notify)
1841 bo->bdev->driver->swap_notify(bo);
1842
1847 ret = ttm_tt_swapout(bo->ttm, bo->persistant_swap_storage); 1843 ret = ttm_tt_swapout(bo->ttm, bo->persistant_swap_storage);
1848out: 1844out:
1849 1845
@@ -1864,3 +1860,4 @@ void ttm_bo_swapout_all(struct ttm_bo_device *bdev)
1864 while (ttm_bo_swapout(&bdev->glob->shrink) == 0) 1860 while (ttm_bo_swapout(&bdev->glob->shrink) == 0)
1865 ; 1861 ;
1866} 1862}
1863EXPORT_SYMBOL(ttm_bo_swapout_all);
diff --git a/drivers/gpu/drm/ttm/ttm_lock.c b/drivers/gpu/drm/ttm/ttm_lock.c
index f619ebcaa4ec..3d172ef04ee1 100644
--- a/drivers/gpu/drm/ttm/ttm_lock.c
+++ b/drivers/gpu/drm/ttm/ttm_lock.c
@@ -288,6 +288,7 @@ void ttm_suspend_unlock(struct ttm_lock *lock)
288 wake_up_all(&lock->queue); 288 wake_up_all(&lock->queue);
289 spin_unlock(&lock->lock); 289 spin_unlock(&lock->lock);
290} 290}
291EXPORT_SYMBOL(ttm_suspend_unlock);
291 292
292static bool __ttm_suspend_lock(struct ttm_lock *lock) 293static bool __ttm_suspend_lock(struct ttm_lock *lock)
293{ 294{
@@ -309,3 +310,4 @@ void ttm_suspend_lock(struct ttm_lock *lock)
309{ 310{
310 wait_event(lock->queue, __ttm_suspend_lock(lock)); 311 wait_event(lock->queue, __ttm_suspend_lock(lock));
311} 312}
313EXPORT_SYMBOL(ttm_suspend_lock);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c b/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c
index d6f2d2b882e9..37a81925b158 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c
@@ -172,6 +172,18 @@ static int vmw_verify_access(struct ttm_buffer_object *bo, struct file *filp)
172 return 0; 172 return 0;
173} 173}
174 174
175static void vmw_move_notify(struct ttm_buffer_object *bo,
176 struct ttm_mem_reg *new_mem)
177{
178 if (new_mem->mem_type != TTM_PL_SYSTEM)
179 vmw_dmabuf_gmr_unbind(bo);
180}
181
182static void vmw_swap_notify(struct ttm_buffer_object *bo)
183{
184 vmw_dmabuf_gmr_unbind(bo);
185}
186
175/** 187/**
176 * FIXME: We're using the old vmware polling method to sync. 188 * FIXME: We're using the old vmware polling method to sync.
177 * Do this with fences instead. 189 * Do this with fences instead.
@@ -225,5 +237,7 @@ struct ttm_bo_driver vmw_bo_driver = {
225 .sync_obj_wait = vmw_sync_obj_wait, 237 .sync_obj_wait = vmw_sync_obj_wait,
226 .sync_obj_flush = vmw_sync_obj_flush, 238 .sync_obj_flush = vmw_sync_obj_flush,
227 .sync_obj_unref = vmw_sync_obj_unref, 239 .sync_obj_unref = vmw_sync_obj_unref,
228 .sync_obj_ref = vmw_sync_obj_ref 240 .sync_obj_ref = vmw_sync_obj_ref,
241 .move_notify = vmw_move_notify,
242 .swap_notify = vmw_swap_notify
229}; 243};
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 1db1ef30be2b..dedd121d8fe7 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -147,6 +147,8 @@ static char *vmw_devname = "vmwgfx";
147 147
148static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 148static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
149static void vmw_master_init(struct vmw_master *); 149static void vmw_master_init(struct vmw_master *);
150static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
151 void *ptr);
150 152
151static void vmw_print_capabilities(uint32_t capabilities) 153static void vmw_print_capabilities(uint32_t capabilities)
152{ 154{
@@ -217,6 +219,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
217 219
218 dev_priv->dev = dev; 220 dev_priv->dev = dev;
219 dev_priv->vmw_chipset = chipset; 221 dev_priv->vmw_chipset = chipset;
222 dev_priv->last_read_sequence = (uint32_t) -100;
220 mutex_init(&dev_priv->hw_mutex); 223 mutex_init(&dev_priv->hw_mutex);
221 mutex_init(&dev_priv->cmdbuf_mutex); 224 mutex_init(&dev_priv->cmdbuf_mutex);
222 rwlock_init(&dev_priv->resource_lock); 225 rwlock_init(&dev_priv->resource_lock);
@@ -351,6 +354,9 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
351 vmw_fb_init(dev_priv); 354 vmw_fb_init(dev_priv);
352 } 355 }
353 356
357 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
358 register_pm_notifier(&dev_priv->pm_nb);
359
354 return 0; 360 return 0;
355 361
356out_no_device: 362out_no_device:
@@ -385,6 +391,8 @@ static int vmw_driver_unload(struct drm_device *dev)
385 391
386 DRM_INFO(VMWGFX_DRIVER_NAME " unload.\n"); 392 DRM_INFO(VMWGFX_DRIVER_NAME " unload.\n");
387 393
394 unregister_pm_notifier(&dev_priv->pm_nb);
395
388 if (!dev_priv->stealth) { 396 if (!dev_priv->stealth) {
389 vmw_fb_close(dev_priv); 397 vmw_fb_close(dev_priv);
390 vmw_kms_close(dev_priv); 398 vmw_kms_close(dev_priv);
@@ -650,6 +658,57 @@ static void vmw_remove(struct pci_dev *pdev)
650 drm_put_dev(dev); 658 drm_put_dev(dev);
651} 659}
652 660
661static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
662 void *ptr)
663{
664 struct vmw_private *dev_priv =
665 container_of(nb, struct vmw_private, pm_nb);
666 struct vmw_master *vmaster = dev_priv->active_master;
667
668 switch (val) {
669 case PM_HIBERNATION_PREPARE:
670 case PM_SUSPEND_PREPARE:
671 ttm_suspend_lock(&vmaster->lock);
672
673 /**
674 * This empties VRAM and unbinds all GMR bindings.
675 * Buffer contents is moved to swappable memory.
676 */
677 ttm_bo_swapout_all(&dev_priv->bdev);
678 break;
679 case PM_POST_HIBERNATION:
680 case PM_POST_SUSPEND:
681 ttm_suspend_unlock(&vmaster->lock);
682 break;
683 case PM_RESTORE_PREPARE:
684 break;
685 case PM_POST_RESTORE:
686 break;
687 default:
688 break;
689 }
690 return 0;
691}
692
693/**
694 * These might not be needed with the virtual SVGA device.
695 */
696
697int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
698{
699 pci_save_state(pdev);
700 pci_disable_device(pdev);
701 pci_set_power_state(pdev, PCI_D3hot);
702 return 0;
703}
704
705int vmw_pci_resume(struct pci_dev *pdev)
706{
707 pci_set_power_state(pdev, PCI_D0);
708 pci_restore_state(pdev);
709 return pci_enable_device(pdev);
710}
711
653static struct drm_driver driver = { 712static struct drm_driver driver = {
654 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | 713 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
655 DRIVER_MODESET, 714 DRIVER_MODESET,
@@ -689,7 +748,9 @@ static struct drm_driver driver = {
689 .name = VMWGFX_DRIVER_NAME, 748 .name = VMWGFX_DRIVER_NAME,
690 .id_table = vmw_pci_id_list, 749 .id_table = vmw_pci_id_list,
691 .probe = vmw_probe, 750 .probe = vmw_probe,
692 .remove = vmw_remove 751 .remove = vmw_remove,
752 .suspend = vmw_pci_suspend,
753 .resume = vmw_pci_resume
693 }, 754 },
694 .name = VMWGFX_DRIVER_NAME, 755 .name = VMWGFX_DRIVER_NAME,
695 .desc = VMWGFX_DRIVER_DESC, 756 .desc = VMWGFX_DRIVER_DESC,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index e61bd85b6975..7532b9b47eec 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -32,6 +32,7 @@
32#include "drmP.h" 32#include "drmP.h"
33#include "vmwgfx_drm.h" 33#include "vmwgfx_drm.h"
34#include "drm_hashtab.h" 34#include "drm_hashtab.h"
35#include "linux/suspend.h"
35#include "ttm/ttm_bo_driver.h" 36#include "ttm/ttm_bo_driver.h"
36#include "ttm/ttm_object.h" 37#include "ttm/ttm_object.h"
37#include "ttm/ttm_lock.h" 38#include "ttm/ttm_lock.h"
@@ -258,6 +259,7 @@ struct vmw_private {
258 259
259 struct vmw_master *active_master; 260 struct vmw_master *active_master;
260 struct vmw_master fbdev_master; 261 struct vmw_master fbdev_master;
262 struct notifier_block pm_nb;
261}; 263};
262 264
263static inline struct vmw_private *vmw_priv(struct drm_device *dev) 265static inline struct vmw_private *vmw_priv(struct drm_device *dev)
@@ -353,6 +355,7 @@ extern int vmw_dmabuf_to_start_of_vram(struct vmw_private *vmw_priv,
353 struct vmw_dma_buffer *bo); 355 struct vmw_dma_buffer *bo);
354extern int vmw_dmabuf_from_vram(struct vmw_private *vmw_priv, 356extern int vmw_dmabuf_from_vram(struct vmw_private *vmw_priv,
355 struct vmw_dma_buffer *bo); 357 struct vmw_dma_buffer *bo);
358extern void vmw_dmabuf_gmr_unbind(struct ttm_buffer_object *bo);
356extern int vmw_stream_claim_ioctl(struct drm_device *dev, void *data, 359extern int vmw_stream_claim_ioctl(struct drm_device *dev, void *data,
357 struct drm_file *file_priv); 360 struct drm_file *file_priv);
358extern int vmw_stream_unref_ioctl(struct drm_device *dev, void *data, 361extern int vmw_stream_unref_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
index 641dde76ada1..4f4f6432be8b 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
@@ -649,14 +649,6 @@ int vmw_dmabuf_to_start_of_vram(struct vmw_private *vmw_priv,
649 if (unlikely(ret != 0)) 649 if (unlikely(ret != 0))
650 goto err_unlock; 650 goto err_unlock;
651 651
652 if (vmw_bo->gmr_bound) {
653 vmw_gmr_unbind(vmw_priv, vmw_bo->gmr_id);
654 spin_lock(&bo->glob->lru_lock);
655 ida_remove(&vmw_priv->gmr_ida, vmw_bo->gmr_id);
656 spin_unlock(&bo->glob->lru_lock);
657 vmw_bo->gmr_bound = NULL;
658 }
659
660 ret = ttm_bo_validate(bo, &ne_placement, false, false); 652 ret = ttm_bo_validate(bo, &ne_placement, false, false);
661 ttm_bo_unreserve(bo); 653 ttm_bo_unreserve(bo);
662err_unlock: 654err_unlock:
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
index 01feb48af333..f7d5f70b52dd 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
@@ -98,8 +98,7 @@ int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
98 (unsigned int) min, 98 (unsigned int) min,
99 (unsigned int) fifo->capabilities); 99 (unsigned int) fifo->capabilities);
100 100
101 dev_priv->fence_seq = (uint32_t) -100; 101 dev_priv->fence_seq = dev_priv->last_read_sequence;
102 dev_priv->last_read_sequence = (uint32_t) -100;
103 iowrite32(dev_priv->last_read_sequence, fifo_mem + SVGA_FIFO_FENCE); 102 iowrite32(dev_priv->last_read_sequence, fifo_mem + SVGA_FIFO_FENCE);
104 103
105 return vmw_fifo_send_fence(dev_priv, &dummy); 104 return vmw_fifo_send_fence(dev_priv, &dummy);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index b1af76e371c3..686692de209a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -553,9 +553,7 @@ int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
553 } *cmd; 553 } *cmd;
554 int i, increment = 1; 554 int i, increment = 1;
555 555
556 if (!num_clips || 556 if (!num_clips) {
557 !(dev_priv->fifo.capabilities &
558 SVGA_FIFO_CAP_SCREEN_OBJECT)) {
559 num_clips = 1; 557 num_clips = 1;
560 clips = &norect; 558 clips = &norect;
561 norect.x1 = norect.y1 = 0; 559 norect.x1 = norect.y1 = 0;
@@ -574,10 +572,10 @@ int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
574 572
575 for (i = 0; i < num_clips; i++, clips += increment) { 573 for (i = 0; i < num_clips; i++, clips += increment) {
576 cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE); 574 cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
577 cmd[i].body.x = cpu_to_le32(clips[i].x1); 575 cmd[i].body.x = cpu_to_le32(clips->x1);
578 cmd[i].body.y = cpu_to_le32(clips[i].y1); 576 cmd[i].body.y = cpu_to_le32(clips->y1);
579 cmd[i].body.width = cpu_to_le32(clips[i].x2 - clips[i].x1); 577 cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
580 cmd[i].body.height = cpu_to_le32(clips[i].y2 - clips[i].y1); 578 cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
581 } 579 }
582 580
583 vmw_fifo_commit(dev_priv, sizeof(*cmd) * num_clips); 581 vmw_fifo_commit(dev_priv, sizeof(*cmd) * num_clips);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c b/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
index bb6e6a096d25..5b6eabeb7f51 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
@@ -104,7 +104,6 @@ static int vmw_dmabuf_pin_in_vram(struct vmw_private *dev_priv,
104 bool pin, bool interruptible) 104 bool pin, bool interruptible)
105{ 105{
106 struct ttm_buffer_object *bo = &buf->base; 106 struct ttm_buffer_object *bo = &buf->base;
107 struct ttm_bo_global *glob = bo->glob;
108 struct ttm_placement *overlay_placement = &vmw_vram_placement; 107 struct ttm_placement *overlay_placement = &vmw_vram_placement;
109 int ret; 108 int ret;
110 109
@@ -116,14 +115,6 @@ static int vmw_dmabuf_pin_in_vram(struct vmw_private *dev_priv,
116 if (unlikely(ret != 0)) 115 if (unlikely(ret != 0))
117 goto err; 116 goto err;
118 117
119 if (buf->gmr_bound) {
120 vmw_gmr_unbind(dev_priv, buf->gmr_id);
121 spin_lock(&glob->lru_lock);
122 ida_remove(&dev_priv->gmr_ida, buf->gmr_id);
123 spin_unlock(&glob->lru_lock);
124 buf->gmr_bound = NULL;
125 }
126
127 if (pin) 118 if (pin)
128 overlay_placement = &vmw_vram_ne_placement; 119 overlay_placement = &vmw_vram_ne_placement;
129 120
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
index c012d5927f65..e0878077e8aa 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
@@ -599,6 +599,27 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
599 if (unlikely(ret != 0)) 599 if (unlikely(ret != 0))
600 goto out_err1; 600 goto out_err1;
601 601
602
603 if (srf->flags & (1 << 9) &&
604 srf->num_sizes == 1 &&
605 srf->sizes[0].width == 64 &&
606 srf->sizes[0].height == 64 &&
607 srf->format == SVGA3D_A8R8G8B8) {
608
609 srf->snooper.image = kmalloc(64 * 64 * 4, GFP_KERNEL);
610 /* clear the image */
611 if (srf->snooper.image) {
612 memset(srf->snooper.image, 0x00, 64 * 64 * 4);
613 } else {
614 DRM_ERROR("Failed to allocate cursor_image\n");
615 ret = -ENOMEM;
616 goto out_err1;
617 }
618 } else {
619 srf->snooper.image = NULL;
620 }
621 srf->snooper.crtc = NULL;
622
602 user_srf->base.shareable = false; 623 user_srf->base.shareable = false;
603 user_srf->base.tfile = NULL; 624 user_srf->base.tfile = NULL;
604 625
@@ -622,24 +643,6 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
622 return ret; 643 return ret;
623 } 644 }
624 645
625 if (srf->flags & (1 << 9) &&
626 srf->num_sizes == 1 &&
627 srf->sizes[0].width == 64 &&
628 srf->sizes[0].height == 64 &&
629 srf->format == SVGA3D_A8R8G8B8) {
630
631 srf->snooper.image = kmalloc(64 * 64 * 4, GFP_KERNEL);
632 /* clear the image */
633 if (srf->snooper.image)
634 memset(srf->snooper.image, 0x00, 64 * 64 * 4);
635 else
636 DRM_ERROR("Failed to allocate cursor_image\n");
637
638 } else {
639 srf->snooper.image = NULL;
640 }
641 srf->snooper.crtc = NULL;
642
643 rep->sid = user_srf->base.hash.key; 646 rep->sid = user_srf->base.hash.key;
644 if (rep->sid == SVGA3D_INVALID_ID) 647 if (rep->sid == SVGA3D_INVALID_ID)
645 DRM_ERROR("Created bad Surface ID.\n"); 648 DRM_ERROR("Created bad Surface ID.\n");
@@ -754,20 +757,29 @@ static size_t vmw_dmabuf_acc_size(struct ttm_bo_global *glob,
754 return bo_user_size + page_array_size; 757 return bo_user_size + page_array_size;
755} 758}
756 759
757void vmw_dmabuf_bo_free(struct ttm_buffer_object *bo) 760void vmw_dmabuf_gmr_unbind(struct ttm_buffer_object *bo)
758{ 761{
759 struct vmw_dma_buffer *vmw_bo = vmw_dma_buffer(bo); 762 struct vmw_dma_buffer *vmw_bo = vmw_dma_buffer(bo);
760 struct ttm_bo_global *glob = bo->glob; 763 struct ttm_bo_global *glob = bo->glob;
761 struct vmw_private *dev_priv = 764 struct vmw_private *dev_priv =
762 container_of(bo->bdev, struct vmw_private, bdev); 765 container_of(bo->bdev, struct vmw_private, bdev);
763 766
764 ttm_mem_global_free(glob->mem_glob, bo->acc_size);
765 if (vmw_bo->gmr_bound) { 767 if (vmw_bo->gmr_bound) {
766 vmw_gmr_unbind(dev_priv, vmw_bo->gmr_id); 768 vmw_gmr_unbind(dev_priv, vmw_bo->gmr_id);
767 spin_lock(&glob->lru_lock); 769 spin_lock(&glob->lru_lock);
768 ida_remove(&dev_priv->gmr_ida, vmw_bo->gmr_id); 770 ida_remove(&dev_priv->gmr_ida, vmw_bo->gmr_id);
769 spin_unlock(&glob->lru_lock); 771 spin_unlock(&glob->lru_lock);
772 vmw_bo->gmr_bound = false;
770 } 773 }
774}
775
776void vmw_dmabuf_bo_free(struct ttm_buffer_object *bo)
777{
778 struct vmw_dma_buffer *vmw_bo = vmw_dma_buffer(bo);
779 struct ttm_bo_global *glob = bo->glob;
780
781 vmw_dmabuf_gmr_unbind(bo);
782 ttm_mem_global_free(glob->mem_glob, bo->acc_size);
771 kfree(vmw_bo); 783 kfree(vmw_bo);
772} 784}
773 785
@@ -813,18 +825,10 @@ int vmw_dmabuf_init(struct vmw_private *dev_priv,
813static void vmw_user_dmabuf_destroy(struct ttm_buffer_object *bo) 825static void vmw_user_dmabuf_destroy(struct ttm_buffer_object *bo)
814{ 826{
815 struct vmw_user_dma_buffer *vmw_user_bo = vmw_user_dma_buffer(bo); 827 struct vmw_user_dma_buffer *vmw_user_bo = vmw_user_dma_buffer(bo);
816 struct vmw_dma_buffer *vmw_bo = &vmw_user_bo->dma;
817 struct ttm_bo_global *glob = bo->glob; 828 struct ttm_bo_global *glob = bo->glob;
818 struct vmw_private *dev_priv =
819 container_of(bo->bdev, struct vmw_private, bdev);
820 829
830 vmw_dmabuf_gmr_unbind(bo);
821 ttm_mem_global_free(glob->mem_glob, bo->acc_size); 831 ttm_mem_global_free(glob->mem_glob, bo->acc_size);
822 if (vmw_bo->gmr_bound) {
823 vmw_gmr_unbind(dev_priv, vmw_bo->gmr_id);
824 spin_lock(&glob->lru_lock);
825 ida_remove(&dev_priv->gmr_ida, vmw_bo->gmr_id);
826 spin_unlock(&glob->lru_lock);
827 }
828 kfree(vmw_user_bo); 832 kfree(vmw_user_bo);
829} 833}
830 834
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 14:54:26 -0500