diff options
Diffstat (limited to 'drivers')
62 files changed, 949 insertions, 1408 deletions
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 20ab3ffce559..6d664849cc09 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c | |||
@@ -446,16 +446,12 @@ static inline int ahci_nr_ports(u32 cap) | |||
446 | return (cap & 0x1f) + 1; | 446 | return (cap & 0x1f) + 1; |
447 | } | 447 | } |
448 | 448 | ||
449 | static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port) | 449 | static inline void __iomem *ahci_port_base(void __iomem *base, |
450 | unsigned int port) | ||
450 | { | 451 | { |
451 | return base + 0x100 + (port * 0x80); | 452 | return base + 0x100 + (port * 0x80); |
452 | } | 453 | } |
453 | 454 | ||
454 | static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port) | ||
455 | { | ||
456 | return (void __iomem *) ahci_port_base_ul((unsigned long)base, port); | ||
457 | } | ||
458 | |||
459 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) | 455 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) |
460 | { | 456 | { |
461 | unsigned int sc_reg; | 457 | unsigned int sc_reg; |
@@ -469,7 +465,7 @@ static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) | |||
469 | return 0xffffffffU; | 465 | return 0xffffffffU; |
470 | } | 466 | } |
471 | 467 | ||
472 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); | 468 | return readl(ap->ioaddr.scr_addr + (sc_reg * 4)); |
473 | } | 469 | } |
474 | 470 | ||
475 | 471 | ||
@@ -487,7 +483,7 @@ static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in, | |||
487 | return; | 483 | return; |
488 | } | 484 | } |
489 | 485 | ||
490 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); | 486 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
491 | } | 487 | } |
492 | 488 | ||
493 | static void ahci_start_engine(void __iomem *port_mmio) | 489 | static void ahci_start_engine(void __iomem *port_mmio) |
@@ -729,7 +725,7 @@ static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev, | |||
729 | 725 | ||
730 | static unsigned int ahci_dev_classify(struct ata_port *ap) | 726 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
731 | { | 727 | { |
732 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; | 728 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
733 | struct ata_taskfile tf; | 729 | struct ata_taskfile tf; |
734 | u32 tmp; | 730 | u32 tmp; |
735 | 731 | ||
@@ -757,7 +753,7 @@ static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, | |||
757 | 753 | ||
758 | static int ahci_clo(struct ata_port *ap) | 754 | static int ahci_clo(struct ata_port *ap) |
759 | { | 755 | { |
760 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; | 756 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
761 | struct ahci_host_priv *hpriv = ap->host->private_data; | 757 | struct ahci_host_priv *hpriv = ap->host->private_data; |
762 | u32 tmp; | 758 | u32 tmp; |
763 | 759 | ||
@@ -779,7 +775,7 @@ static int ahci_clo(struct ata_port *ap) | |||
779 | static int ahci_softreset(struct ata_port *ap, unsigned int *class) | 775 | static int ahci_softreset(struct ata_port *ap, unsigned int *class) |
780 | { | 776 | { |
781 | struct ahci_port_priv *pp = ap->private_data; | 777 | struct ahci_port_priv *pp = ap->private_data; |
782 | void __iomem *mmio = ap->host->mmio_base; | 778 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
783 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | 779 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
784 | const u32 cmd_fis_len = 5; /* five dwords */ | 780 | const u32 cmd_fis_len = 5; /* five dwords */ |
785 | const char *reason = NULL; | 781 | const char *reason = NULL; |
@@ -887,7 +883,7 @@ static int ahci_hardreset(struct ata_port *ap, unsigned int *class) | |||
887 | struct ahci_port_priv *pp = ap->private_data; | 883 | struct ahci_port_priv *pp = ap->private_data; |
888 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | 884 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
889 | struct ata_taskfile tf; | 885 | struct ata_taskfile tf; |
890 | void __iomem *mmio = ap->host->mmio_base; | 886 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
891 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | 887 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
892 | int rc; | 888 | int rc; |
893 | 889 | ||
@@ -915,7 +911,7 @@ static int ahci_hardreset(struct ata_port *ap, unsigned int *class) | |||
915 | 911 | ||
916 | static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class) | 912 | static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class) |
917 | { | 913 | { |
918 | void __iomem *mmio = ap->host->mmio_base; | 914 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
919 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | 915 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
920 | int rc; | 916 | int rc; |
921 | 917 | ||
@@ -940,7 +936,7 @@ static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class) | |||
940 | 936 | ||
941 | static void ahci_postreset(struct ata_port *ap, unsigned int *class) | 937 | static void ahci_postreset(struct ata_port *ap, unsigned int *class) |
942 | { | 938 | { |
943 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; | 939 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
944 | u32 new_tmp, tmp; | 940 | u32 new_tmp, tmp; |
945 | 941 | ||
946 | ata_std_postreset(ap, class); | 942 | ata_std_postreset(ap, class); |
@@ -959,7 +955,7 @@ static void ahci_postreset(struct ata_port *ap, unsigned int *class) | |||
959 | 955 | ||
960 | static u8 ahci_check_status(struct ata_port *ap) | 956 | static u8 ahci_check_status(struct ata_port *ap) |
961 | { | 957 | { |
962 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; | 958 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
963 | 959 | ||
964 | return readl(mmio + PORT_TFDATA) & 0xFF; | 960 | return readl(mmio + PORT_TFDATA) & 0xFF; |
965 | } | 961 | } |
@@ -1105,7 +1101,7 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) | |||
1105 | 1101 | ||
1106 | static void ahci_host_intr(struct ata_port *ap) | 1102 | static void ahci_host_intr(struct ata_port *ap) |
1107 | { | 1103 | { |
1108 | void __iomem *mmio = ap->host->mmio_base; | 1104 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
1109 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | 1105 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1110 | struct ata_eh_info *ehi = &ap->eh_info; | 1106 | struct ata_eh_info *ehi = &ap->eh_info; |
1111 | struct ahci_port_priv *pp = ap->private_data; | 1107 | struct ahci_port_priv *pp = ap->private_data; |
@@ -1203,7 +1199,7 @@ static irqreturn_t ahci_interrupt(int irq, void *dev_instance) | |||
1203 | VPRINTK("ENTER\n"); | 1199 | VPRINTK("ENTER\n"); |
1204 | 1200 | ||
1205 | hpriv = host->private_data; | 1201 | hpriv = host->private_data; |
1206 | mmio = host->mmio_base; | 1202 | mmio = host->iomap[AHCI_PCI_BAR]; |
1207 | 1203 | ||
1208 | /* sigh. 0xffffffff is a valid return from h/w */ | 1204 | /* sigh. 0xffffffff is a valid return from h/w */ |
1209 | irq_stat = readl(mmio + HOST_IRQ_STAT); | 1205 | irq_stat = readl(mmio + HOST_IRQ_STAT); |
@@ -1248,7 +1244,7 @@ static irqreturn_t ahci_interrupt(int irq, void *dev_instance) | |||
1248 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) | 1244 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
1249 | { | 1245 | { |
1250 | struct ata_port *ap = qc->ap; | 1246 | struct ata_port *ap = qc->ap; |
1251 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; | 1247 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
1252 | 1248 | ||
1253 | if (qc->tf.protocol == ATA_PROT_NCQ) | 1249 | if (qc->tf.protocol == ATA_PROT_NCQ) |
1254 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | 1250 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); |
@@ -1260,7 +1256,7 @@ static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) | |||
1260 | 1256 | ||
1261 | static void ahci_freeze(struct ata_port *ap) | 1257 | static void ahci_freeze(struct ata_port *ap) |
1262 | { | 1258 | { |
1263 | void __iomem *mmio = ap->host->mmio_base; | 1259 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
1264 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | 1260 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1265 | 1261 | ||
1266 | /* turn IRQ off */ | 1262 | /* turn IRQ off */ |
@@ -1269,7 +1265,7 @@ static void ahci_freeze(struct ata_port *ap) | |||
1269 | 1265 | ||
1270 | static void ahci_thaw(struct ata_port *ap) | 1266 | static void ahci_thaw(struct ata_port *ap) |
1271 | { | 1267 | { |
1272 | void __iomem *mmio = ap->host->mmio_base; | 1268 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
1273 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | 1269 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1274 | u32 tmp; | 1270 | u32 tmp; |
1275 | 1271 | ||
@@ -1284,7 +1280,7 @@ static void ahci_thaw(struct ata_port *ap) | |||
1284 | 1280 | ||
1285 | static void ahci_error_handler(struct ata_port *ap) | 1281 | static void ahci_error_handler(struct ata_port *ap) |
1286 | { | 1282 | { |
1287 | void __iomem *mmio = ap->host->mmio_base; | 1283 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
1288 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | 1284 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1289 | 1285 | ||
1290 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { | 1286 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
@@ -1300,7 +1296,7 @@ static void ahci_error_handler(struct ata_port *ap) | |||
1300 | 1296 | ||
1301 | static void ahci_vt8251_error_handler(struct ata_port *ap) | 1297 | static void ahci_vt8251_error_handler(struct ata_port *ap) |
1302 | { | 1298 | { |
1303 | void __iomem *mmio = ap->host->mmio_base; | 1299 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
1304 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | 1300 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1305 | 1301 | ||
1306 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { | 1302 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
@@ -1317,7 +1313,7 @@ static void ahci_vt8251_error_handler(struct ata_port *ap) | |||
1317 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) | 1313 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
1318 | { | 1314 | { |
1319 | struct ata_port *ap = qc->ap; | 1315 | struct ata_port *ap = qc->ap; |
1320 | void __iomem *mmio = ap->host->mmio_base; | 1316 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
1321 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | 1317 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1322 | 1318 | ||
1323 | if (qc->flags & ATA_QCFLAG_FAILED) | 1319 | if (qc->flags & ATA_QCFLAG_FAILED) |
@@ -1334,7 +1330,7 @@ static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) | |||
1334 | { | 1330 | { |
1335 | struct ahci_host_priv *hpriv = ap->host->private_data; | 1331 | struct ahci_host_priv *hpriv = ap->host->private_data; |
1336 | struct ahci_port_priv *pp = ap->private_data; | 1332 | struct ahci_port_priv *pp = ap->private_data; |
1337 | void __iomem *mmio = ap->host->mmio_base; | 1333 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
1338 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | 1334 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1339 | const char *emsg = NULL; | 1335 | const char *emsg = NULL; |
1340 | int rc; | 1336 | int rc; |
@@ -1355,7 +1351,7 @@ static int ahci_port_resume(struct ata_port *ap) | |||
1355 | { | 1351 | { |
1356 | struct ahci_port_priv *pp = ap->private_data; | 1352 | struct ahci_port_priv *pp = ap->private_data; |
1357 | struct ahci_host_priv *hpriv = ap->host->private_data; | 1353 | struct ahci_host_priv *hpriv = ap->host->private_data; |
1358 | void __iomem *mmio = ap->host->mmio_base; | 1354 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
1359 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | 1355 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1360 | 1356 | ||
1361 | ahci_power_up(port_mmio, hpriv->cap); | 1357 | ahci_power_up(port_mmio, hpriv->cap); |
@@ -1367,7 +1363,7 @@ static int ahci_port_resume(struct ata_port *ap) | |||
1367 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) | 1363 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
1368 | { | 1364 | { |
1369 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | 1365 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
1370 | void __iomem *mmio = host->mmio_base; | 1366 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
1371 | u32 ctl; | 1367 | u32 ctl; |
1372 | 1368 | ||
1373 | if (mesg.event == PM_EVENT_SUSPEND) { | 1369 | if (mesg.event == PM_EVENT_SUSPEND) { |
@@ -1388,7 +1384,7 @@ static int ahci_pci_device_resume(struct pci_dev *pdev) | |||
1388 | { | 1384 | { |
1389 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | 1385 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
1390 | struct ahci_host_priv *hpriv = host->private_data; | 1386 | struct ahci_host_priv *hpriv = host->private_data; |
1391 | void __iomem *mmio = host->mmio_base; | 1387 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
1392 | int rc; | 1388 | int rc; |
1393 | 1389 | ||
1394 | rc = ata_pci_device_do_resume(pdev); | 1390 | rc = ata_pci_device_do_resume(pdev); |
@@ -1414,7 +1410,7 @@ static int ahci_port_start(struct ata_port *ap) | |||
1414 | struct device *dev = ap->host->dev; | 1410 | struct device *dev = ap->host->dev; |
1415 | struct ahci_host_priv *hpriv = ap->host->private_data; | 1411 | struct ahci_host_priv *hpriv = ap->host->private_data; |
1416 | struct ahci_port_priv *pp; | 1412 | struct ahci_port_priv *pp; |
1417 | void __iomem *mmio = ap->host->mmio_base; | 1413 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
1418 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | 1414 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1419 | void *mem; | 1415 | void *mem; |
1420 | dma_addr_t mem_dma; | 1416 | dma_addr_t mem_dma; |
@@ -1474,7 +1470,7 @@ static int ahci_port_start(struct ata_port *ap) | |||
1474 | static void ahci_port_stop(struct ata_port *ap) | 1470 | static void ahci_port_stop(struct ata_port *ap) |
1475 | { | 1471 | { |
1476 | struct ahci_host_priv *hpriv = ap->host->private_data; | 1472 | struct ahci_host_priv *hpriv = ap->host->private_data; |
1477 | void __iomem *mmio = ap->host->mmio_base; | 1473 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
1478 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | 1474 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1479 | const char *emsg = NULL; | 1475 | const char *emsg = NULL; |
1480 | int rc; | 1476 | int rc; |
@@ -1485,11 +1481,11 @@ static void ahci_port_stop(struct ata_port *ap) | |||
1485 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); | 1481 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); |
1486 | } | 1482 | } |
1487 | 1483 | ||
1488 | static void ahci_setup_port(struct ata_ioports *port, unsigned long base, | 1484 | static void ahci_setup_port(struct ata_ioports *port, void __iomem *base, |
1489 | unsigned int port_idx) | 1485 | unsigned int port_idx) |
1490 | { | 1486 | { |
1491 | VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx); | 1487 | VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx); |
1492 | base = ahci_port_base_ul(base, port_idx); | 1488 | base = ahci_port_base(base, port_idx); |
1493 | VPRINTK("base now==0x%lx\n", base); | 1489 | VPRINTK("base now==0x%lx\n", base); |
1494 | 1490 | ||
1495 | port->cmd_addr = base; | 1491 | port->cmd_addr = base; |
@@ -1502,7 +1498,7 @@ static int ahci_host_init(struct ata_probe_ent *probe_ent) | |||
1502 | { | 1498 | { |
1503 | struct ahci_host_priv *hpriv = probe_ent->private_data; | 1499 | struct ahci_host_priv *hpriv = probe_ent->private_data; |
1504 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | 1500 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); |
1505 | void __iomem *mmio = probe_ent->mmio_base; | 1501 | void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR]; |
1506 | unsigned int i, cap_n_ports, using_dac; | 1502 | unsigned int i, cap_n_ports, using_dac; |
1507 | int rc; | 1503 | int rc; |
1508 | 1504 | ||
@@ -1569,7 +1565,7 @@ static int ahci_host_init(struct ata_probe_ent *probe_ent) | |||
1569 | } | 1565 | } |
1570 | 1566 | ||
1571 | for (i = 0; i < probe_ent->n_ports; i++) | 1567 | for (i = 0; i < probe_ent->n_ports; i++) |
1572 | ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i); | 1568 | ahci_setup_port(&probe_ent->port[i], mmio, i); |
1573 | 1569 | ||
1574 | ahci_init_controller(mmio, pdev, probe_ent->n_ports, | 1570 | ahci_init_controller(mmio, pdev, probe_ent->n_ports, |
1575 | probe_ent->port_flags, hpriv); | 1571 | probe_ent->port_flags, hpriv); |
@@ -1583,7 +1579,7 @@ static void ahci_print_info(struct ata_probe_ent *probe_ent) | |||
1583 | { | 1579 | { |
1584 | struct ahci_host_priv *hpriv = probe_ent->private_data; | 1580 | struct ahci_host_priv *hpriv = probe_ent->private_data; |
1585 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | 1581 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); |
1586 | void __iomem *mmio = probe_ent->mmio_base; | 1582 | void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR]; |
1587 | u32 vers, cap, impl, speed; | 1583 | u32 vers, cap, impl, speed; |
1588 | const char *speed_s; | 1584 | const char *speed_s; |
1589 | u16 cc; | 1585 | u16 cc; |
@@ -1657,8 +1653,6 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1657 | struct device *dev = &pdev->dev; | 1653 | struct device *dev = &pdev->dev; |
1658 | struct ata_probe_ent *probe_ent; | 1654 | struct ata_probe_ent *probe_ent; |
1659 | struct ahci_host_priv *hpriv; | 1655 | struct ahci_host_priv *hpriv; |
1660 | unsigned long base; | ||
1661 | void __iomem *mmio_base; | ||
1662 | int rc; | 1656 | int rc; |
1663 | 1657 | ||
1664 | VPRINTK("ENTER\n"); | 1658 | VPRINTK("ENTER\n"); |
@@ -1679,11 +1673,11 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1679 | if (rc) | 1673 | if (rc) |
1680 | return rc; | 1674 | return rc; |
1681 | 1675 | ||
1682 | rc = pci_request_regions(pdev, DRV_NAME); | 1676 | rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); |
1683 | if (rc) { | 1677 | if (rc == -EBUSY) |
1684 | pcim_pin_device(pdev); | 1678 | pcim_pin_device(pdev); |
1679 | if (rc) | ||
1685 | return rc; | 1680 | return rc; |
1686 | } | ||
1687 | 1681 | ||
1688 | if (pci_enable_msi(pdev)) | 1682 | if (pci_enable_msi(pdev)) |
1689 | pci_intx(pdev, 1); | 1683 | pci_intx(pdev, 1); |
@@ -1695,11 +1689,6 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1695 | probe_ent->dev = pci_dev_to_dev(pdev); | 1689 | probe_ent->dev = pci_dev_to_dev(pdev); |
1696 | INIT_LIST_HEAD(&probe_ent->node); | 1690 | INIT_LIST_HEAD(&probe_ent->node); |
1697 | 1691 | ||
1698 | mmio_base = pcim_iomap(pdev, AHCI_PCI_BAR, 0); | ||
1699 | if (mmio_base == NULL) | ||
1700 | return -ENOMEM; | ||
1701 | base = (unsigned long) mmio_base; | ||
1702 | |||
1703 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); | 1692 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
1704 | if (!hpriv) | 1693 | if (!hpriv) |
1705 | return -ENOMEM; | 1694 | return -ENOMEM; |
@@ -1712,7 +1701,7 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1712 | 1701 | ||
1713 | probe_ent->irq = pdev->irq; | 1702 | probe_ent->irq = pdev->irq; |
1714 | probe_ent->irq_flags = IRQF_SHARED; | 1703 | probe_ent->irq_flags = IRQF_SHARED; |
1715 | probe_ent->mmio_base = mmio_base; | 1704 | probe_ent->iomap = pcim_iomap_table(pdev); |
1716 | probe_ent->private_data = hpriv; | 1705 | probe_ent->private_data = hpriv; |
1717 | 1706 | ||
1718 | /* initialize adapter */ | 1707 | /* initialize adapter */ |
diff --git a/drivers/ata/ata_generic.c b/drivers/ata/ata_generic.c index a25cbd653b0c..c79887f31841 100644 --- a/drivers/ata/ata_generic.c +++ b/drivers/ata/ata_generic.c | |||
@@ -79,7 +79,7 @@ static int generic_set_mode(struct ata_port *ap, struct ata_device **unused) | |||
79 | 79 | ||
80 | /* Bits 5 and 6 indicate if DMA is active on master/slave */ | 80 | /* Bits 5 and 6 indicate if DMA is active on master/slave */ |
81 | if (ap->ioaddr.bmdma_addr) | 81 | if (ap->ioaddr.bmdma_addr) |
82 | dma_enabled = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | 82 | dma_enabled = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
83 | 83 | ||
84 | for (i = 0; i < ATA_MAX_DEVICES; i++) { | 84 | for (i = 0; i < ATA_MAX_DEVICES; i++) { |
85 | struct ata_device *dev = &ap->device[i]; | 85 | struct ata_device *dev = &ap->device[i]; |
@@ -138,7 +138,7 @@ static struct ata_port_operations generic_port_ops = { | |||
138 | .bmdma_stop = ata_bmdma_stop, | 138 | .bmdma_stop = ata_bmdma_stop, |
139 | .bmdma_status = ata_bmdma_status, | 139 | .bmdma_status = ata_bmdma_status, |
140 | 140 | ||
141 | .data_xfer = ata_pio_data_xfer, | 141 | .data_xfer = ata_data_xfer, |
142 | 142 | ||
143 | .freeze = ata_bmdma_freeze, | 143 | .freeze = ata_bmdma_freeze, |
144 | .thaw = ata_bmdma_thaw, | 144 | .thaw = ata_bmdma_thaw, |
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c index c6bf1a338d1a..37fe6c2b8ca2 100644 --- a/drivers/ata/ata_piix.c +++ b/drivers/ata/ata_piix.c | |||
@@ -299,7 +299,7 @@ static const struct ata_port_operations piix_pata_ops = { | |||
299 | .bmdma_status = ata_bmdma_status, | 299 | .bmdma_status = ata_bmdma_status, |
300 | .qc_prep = ata_qc_prep, | 300 | .qc_prep = ata_qc_prep, |
301 | .qc_issue = ata_qc_issue_prot, | 301 | .qc_issue = ata_qc_issue_prot, |
302 | .data_xfer = ata_pio_data_xfer, | 302 | .data_xfer = ata_data_xfer, |
303 | 303 | ||
304 | .freeze = ata_bmdma_freeze, | 304 | .freeze = ata_bmdma_freeze, |
305 | .thaw = ata_bmdma_thaw, | 305 | .thaw = ata_bmdma_thaw, |
@@ -330,7 +330,7 @@ static const struct ata_port_operations ich_pata_ops = { | |||
330 | .bmdma_status = ata_bmdma_status, | 330 | .bmdma_status = ata_bmdma_status, |
331 | .qc_prep = ata_qc_prep, | 331 | .qc_prep = ata_qc_prep, |
332 | .qc_issue = ata_qc_issue_prot, | 332 | .qc_issue = ata_qc_issue_prot, |
333 | .data_xfer = ata_pio_data_xfer, | 333 | .data_xfer = ata_data_xfer, |
334 | 334 | ||
335 | .freeze = ata_bmdma_freeze, | 335 | .freeze = ata_bmdma_freeze, |
336 | .thaw = ata_bmdma_thaw, | 336 | .thaw = ata_bmdma_thaw, |
@@ -358,7 +358,7 @@ static const struct ata_port_operations piix_sata_ops = { | |||
358 | .bmdma_status = ata_bmdma_status, | 358 | .bmdma_status = ata_bmdma_status, |
359 | .qc_prep = ata_qc_prep, | 359 | .qc_prep = ata_qc_prep, |
360 | .qc_issue = ata_qc_issue_prot, | 360 | .qc_issue = ata_qc_issue_prot, |
361 | .data_xfer = ata_pio_data_xfer, | 361 | .data_xfer = ata_data_xfer, |
362 | 362 | ||
363 | .freeze = ata_bmdma_freeze, | 363 | .freeze = ata_bmdma_freeze, |
364 | .thaw = ata_bmdma_thaw, | 364 | .thaw = ata_bmdma_thaw, |
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index ed11ee41673c..f210dbd4cbe6 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c | |||
@@ -601,51 +601,7 @@ void ata_dev_disable(struct ata_device *dev) | |||
601 | } | 601 | } |
602 | 602 | ||
603 | /** | 603 | /** |
604 | * ata_pio_devchk - PATA device presence detection | 604 | * ata_devchk - PATA device presence detection |
605 | * @ap: ATA channel to examine | ||
606 | * @device: Device to examine (starting at zero) | ||
607 | * | ||
608 | * This technique was originally described in | ||
609 | * Hale Landis's ATADRVR (www.ata-atapi.com), and | ||
610 | * later found its way into the ATA/ATAPI spec. | ||
611 | * | ||
612 | * Write a pattern to the ATA shadow registers, | ||
613 | * and if a device is present, it will respond by | ||
614 | * correctly storing and echoing back the | ||
615 | * ATA shadow register contents. | ||
616 | * | ||
617 | * LOCKING: | ||
618 | * caller. | ||
619 | */ | ||
620 | |||
621 | static unsigned int ata_pio_devchk(struct ata_port *ap, | ||
622 | unsigned int device) | ||
623 | { | ||
624 | struct ata_ioports *ioaddr = &ap->ioaddr; | ||
625 | u8 nsect, lbal; | ||
626 | |||
627 | ap->ops->dev_select(ap, device); | ||
628 | |||
629 | outb(0x55, ioaddr->nsect_addr); | ||
630 | outb(0xaa, ioaddr->lbal_addr); | ||
631 | |||
632 | outb(0xaa, ioaddr->nsect_addr); | ||
633 | outb(0x55, ioaddr->lbal_addr); | ||
634 | |||
635 | outb(0x55, ioaddr->nsect_addr); | ||
636 | outb(0xaa, ioaddr->lbal_addr); | ||
637 | |||
638 | nsect = inb(ioaddr->nsect_addr); | ||
639 | lbal = inb(ioaddr->lbal_addr); | ||
640 | |||
641 | if ((nsect == 0x55) && (lbal == 0xaa)) | ||
642 | return 1; /* we found a device */ | ||
643 | |||
644 | return 0; /* nothing found */ | ||
645 | } | ||
646 | |||
647 | /** | ||
648 | * ata_mmio_devchk - PATA device presence detection | ||
649 | * @ap: ATA channel to examine | 605 | * @ap: ATA channel to examine |
650 | * @device: Device to examine (starting at zero) | 606 | * @device: Device to examine (starting at zero) |
651 | * | 607 | * |
@@ -662,25 +618,24 @@ static unsigned int ata_pio_devchk(struct ata_port *ap, | |||
662 | * caller. | 618 | * caller. |
663 | */ | 619 | */ |
664 | 620 | ||
665 | static unsigned int ata_mmio_devchk(struct ata_port *ap, | 621 | static unsigned int ata_devchk(struct ata_port *ap, unsigned int device) |
666 | unsigned int device) | ||
667 | { | 622 | { |
668 | struct ata_ioports *ioaddr = &ap->ioaddr; | 623 | struct ata_ioports *ioaddr = &ap->ioaddr; |
669 | u8 nsect, lbal; | 624 | u8 nsect, lbal; |
670 | 625 | ||
671 | ap->ops->dev_select(ap, device); | 626 | ap->ops->dev_select(ap, device); |
672 | 627 | ||
673 | writeb(0x55, (void __iomem *) ioaddr->nsect_addr); | 628 | iowrite8(0x55, ioaddr->nsect_addr); |
674 | writeb(0xaa, (void __iomem *) ioaddr->lbal_addr); | 629 | iowrite8(0xaa, ioaddr->lbal_addr); |
675 | 630 | ||
676 | writeb(0xaa, (void __iomem *) ioaddr->nsect_addr); | 631 | iowrite8(0xaa, ioaddr->nsect_addr); |
677 | writeb(0x55, (void __iomem *) ioaddr->lbal_addr); | 632 | iowrite8(0x55, ioaddr->lbal_addr); |
678 | 633 | ||
679 | writeb(0x55, (void __iomem *) ioaddr->nsect_addr); | 634 | iowrite8(0x55, ioaddr->nsect_addr); |
680 | writeb(0xaa, (void __iomem *) ioaddr->lbal_addr); | 635 | iowrite8(0xaa, ioaddr->lbal_addr); |
681 | 636 | ||
682 | nsect = readb((void __iomem *) ioaddr->nsect_addr); | 637 | nsect = ioread8(ioaddr->nsect_addr); |
683 | lbal = readb((void __iomem *) ioaddr->lbal_addr); | 638 | lbal = ioread8(ioaddr->lbal_addr); |
684 | 639 | ||
685 | if ((nsect == 0x55) && (lbal == 0xaa)) | 640 | if ((nsect == 0x55) && (lbal == 0xaa)) |
686 | return 1; /* we found a device */ | 641 | return 1; /* we found a device */ |
@@ -689,27 +644,6 @@ static unsigned int ata_mmio_devchk(struct ata_port *ap, | |||
689 | } | 644 | } |
690 | 645 | ||
691 | /** | 646 | /** |
692 | * ata_devchk - PATA device presence detection | ||
693 | * @ap: ATA channel to examine | ||
694 | * @device: Device to examine (starting at zero) | ||
695 | * | ||
696 | * Dispatch ATA device presence detection, depending | ||
697 | * on whether we are using PIO or MMIO to talk to the | ||
698 | * ATA shadow registers. | ||
699 | * | ||
700 | * LOCKING: | ||
701 | * caller. | ||
702 | */ | ||
703 | |||
704 | static unsigned int ata_devchk(struct ata_port *ap, | ||
705 | unsigned int device) | ||
706 | { | ||
707 | if (ap->flags & ATA_FLAG_MMIO) | ||
708 | return ata_mmio_devchk(ap, device); | ||
709 | return ata_pio_devchk(ap, device); | ||
710 | } | ||
711 | |||
712 | /** | ||
713 | * ata_dev_classify - determine device type based on ATA-spec signature | 647 | * ata_dev_classify - determine device type based on ATA-spec signature |
714 | * @tf: ATA taskfile register set for device to be identified | 648 | * @tf: ATA taskfile register set for device to be identified |
715 | * | 649 | * |
@@ -926,11 +860,7 @@ void ata_std_dev_select (struct ata_port *ap, unsigned int device) | |||
926 | else | 860 | else |
927 | tmp = ATA_DEVICE_OBS | ATA_DEV1; | 861 | tmp = ATA_DEVICE_OBS | ATA_DEV1; |
928 | 862 | ||
929 | if (ap->flags & ATA_FLAG_MMIO) { | 863 | iowrite8(tmp, ap->ioaddr.device_addr); |
930 | writeb(tmp, (void __iomem *) ap->ioaddr.device_addr); | ||
931 | } else { | ||
932 | outb(tmp, ap->ioaddr.device_addr); | ||
933 | } | ||
934 | ata_pause(ap); /* needed; also flushes, for mmio */ | 864 | ata_pause(ap); /* needed; also flushes, for mmio */ |
935 | } | 865 | } |
936 | 866 | ||
@@ -2616,13 +2546,8 @@ static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask) | |||
2616 | u8 nsect, lbal; | 2546 | u8 nsect, lbal; |
2617 | 2547 | ||
2618 | ap->ops->dev_select(ap, 1); | 2548 | ap->ops->dev_select(ap, 1); |
2619 | if (ap->flags & ATA_FLAG_MMIO) { | 2549 | nsect = ioread8(ioaddr->nsect_addr); |
2620 | nsect = readb((void __iomem *) ioaddr->nsect_addr); | 2550 | lbal = ioread8(ioaddr->lbal_addr); |
2621 | lbal = readb((void __iomem *) ioaddr->lbal_addr); | ||
2622 | } else { | ||
2623 | nsect = inb(ioaddr->nsect_addr); | ||
2624 | lbal = inb(ioaddr->lbal_addr); | ||
2625 | } | ||
2626 | if ((nsect == 1) && (lbal == 1)) | 2551 | if ((nsect == 1) && (lbal == 1)) |
2627 | break; | 2552 | break; |
2628 | if (time_after(jiffies, timeout)) { | 2553 | if (time_after(jiffies, timeout)) { |
@@ -2650,19 +2575,11 @@ static unsigned int ata_bus_softreset(struct ata_port *ap, | |||
2650 | DPRINTK("ata%u: bus reset via SRST\n", ap->id); | 2575 | DPRINTK("ata%u: bus reset via SRST\n", ap->id); |
2651 | 2576 | ||
2652 | /* software reset. causes dev0 to be selected */ | 2577 | /* software reset. causes dev0 to be selected */ |
2653 | if (ap->flags & ATA_FLAG_MMIO) { | 2578 | iowrite8(ap->ctl, ioaddr->ctl_addr); |
2654 | writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr); | 2579 | udelay(20); /* FIXME: flush */ |
2655 | udelay(20); /* FIXME: flush */ | 2580 | iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr); |
2656 | writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr); | 2581 | udelay(20); /* FIXME: flush */ |
2657 | udelay(20); /* FIXME: flush */ | 2582 | iowrite8(ap->ctl, ioaddr->ctl_addr); |
2658 | writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr); | ||
2659 | } else { | ||
2660 | outb(ap->ctl, ioaddr->ctl_addr); | ||
2661 | udelay(10); | ||
2662 | outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr); | ||
2663 | udelay(10); | ||
2664 | outb(ap->ctl, ioaddr->ctl_addr); | ||
2665 | } | ||
2666 | 2583 | ||
2667 | /* spec mandates ">= 2ms" before checking status. | 2584 | /* spec mandates ">= 2ms" before checking status. |
2668 | * We wait 150ms, because that was the magic delay used for | 2585 | * We wait 150ms, because that was the magic delay used for |
@@ -2763,10 +2680,7 @@ void ata_bus_reset(struct ata_port *ap) | |||
2763 | 2680 | ||
2764 | if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) { | 2681 | if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) { |
2765 | /* set up device control for ATA_FLAG_SATA_RESET */ | 2682 | /* set up device control for ATA_FLAG_SATA_RESET */ |
2766 | if (ap->flags & ATA_FLAG_MMIO) | 2683 | iowrite8(ap->ctl, ioaddr->ctl_addr); |
2767 | writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr); | ||
2768 | else | ||
2769 | outb(ap->ctl, ioaddr->ctl_addr); | ||
2770 | } | 2684 | } |
2771 | 2685 | ||
2772 | DPRINTK("EXIT\n"); | 2686 | DPRINTK("EXIT\n"); |
@@ -3159,12 +3073,8 @@ void ata_std_postreset(struct ata_port *ap, unsigned int *classes) | |||
3159 | } | 3073 | } |
3160 | 3074 | ||
3161 | /* set up device control */ | 3075 | /* set up device control */ |
3162 | if (ap->ioaddr.ctl_addr) { | 3076 | if (ap->ioaddr.ctl_addr) |
3163 | if (ap->flags & ATA_FLAG_MMIO) | 3077 | iowrite8(ap->ctl, ap->ioaddr.ctl_addr); |
3164 | writeb(ap->ctl, (void __iomem *) ap->ioaddr.ctl_addr); | ||
3165 | else | ||
3166 | outb(ap->ctl, ap->ioaddr.ctl_addr); | ||
3167 | } | ||
3168 | 3078 | ||
3169 | DPRINTK("EXIT\n"); | 3079 | DPRINTK("EXIT\n"); |
3170 | } | 3080 | } |
@@ -3880,53 +3790,7 @@ void swap_buf_le16(u16 *buf, unsigned int buf_words) | |||
3880 | } | 3790 | } |
3881 | 3791 | ||
3882 | /** | 3792 | /** |
3883 | * ata_mmio_data_xfer - Transfer data by MMIO | 3793 | * ata_data_xfer - Transfer data by PIO |
3884 | * @adev: device for this I/O | ||
3885 | * @buf: data buffer | ||
3886 | * @buflen: buffer length | ||
3887 | * @write_data: read/write | ||
3888 | * | ||
3889 | * Transfer data from/to the device data register by MMIO. | ||
3890 | * | ||
3891 | * LOCKING: | ||
3892 | * Inherited from caller. | ||
3893 | */ | ||
3894 | |||
3895 | void ata_mmio_data_xfer(struct ata_device *adev, unsigned char *buf, | ||
3896 | unsigned int buflen, int write_data) | ||
3897 | { | ||
3898 | struct ata_port *ap = adev->ap; | ||
3899 | unsigned int i; | ||
3900 | unsigned int words = buflen >> 1; | ||
3901 | u16 *buf16 = (u16 *) buf; | ||
3902 | void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr; | ||
3903 | |||
3904 | /* Transfer multiple of 2 bytes */ | ||
3905 | if (write_data) { | ||
3906 | for (i = 0; i < words; i++) | ||
3907 | writew(le16_to_cpu(buf16[i]), mmio); | ||
3908 | } else { | ||
3909 | for (i = 0; i < words; i++) | ||
3910 | buf16[i] = cpu_to_le16(readw(mmio)); | ||
3911 | } | ||
3912 | |||
3913 | /* Transfer trailing 1 byte, if any. */ | ||
3914 | if (unlikely(buflen & 0x01)) { | ||
3915 | u16 align_buf[1] = { 0 }; | ||
3916 | unsigned char *trailing_buf = buf + buflen - 1; | ||
3917 | |||
3918 | if (write_data) { | ||
3919 | memcpy(align_buf, trailing_buf, 1); | ||
3920 | writew(le16_to_cpu(align_buf[0]), mmio); | ||
3921 | } else { | ||
3922 | align_buf[0] = cpu_to_le16(readw(mmio)); | ||
3923 | memcpy(trailing_buf, align_buf, 1); | ||
3924 | } | ||
3925 | } | ||
3926 | } | ||
3927 | |||
3928 | /** | ||
3929 | * ata_pio_data_xfer - Transfer data by PIO | ||
3930 | * @adev: device to target | 3794 | * @adev: device to target |
3931 | * @buf: data buffer | 3795 | * @buf: data buffer |
3932 | * @buflen: buffer length | 3796 | * @buflen: buffer length |
@@ -3937,18 +3801,17 @@ void ata_mmio_data_xfer(struct ata_device *adev, unsigned char *buf, | |||
3937 | * LOCKING: | 3801 | * LOCKING: |
3938 | * Inherited from caller. | 3802 | * Inherited from caller. |
3939 | */ | 3803 | */ |
3940 | 3804 | void ata_data_xfer(struct ata_device *adev, unsigned char *buf, | |
3941 | void ata_pio_data_xfer(struct ata_device *adev, unsigned char *buf, | 3805 | unsigned int buflen, int write_data) |
3942 | unsigned int buflen, int write_data) | ||
3943 | { | 3806 | { |
3944 | struct ata_port *ap = adev->ap; | 3807 | struct ata_port *ap = adev->ap; |
3945 | unsigned int words = buflen >> 1; | 3808 | unsigned int words = buflen >> 1; |
3946 | 3809 | ||
3947 | /* Transfer multiple of 2 bytes */ | 3810 | /* Transfer multiple of 2 bytes */ |
3948 | if (write_data) | 3811 | if (write_data) |
3949 | outsw(ap->ioaddr.data_addr, buf, words); | 3812 | iowrite16_rep(ap->ioaddr.data_addr, buf, words); |
3950 | else | 3813 | else |
3951 | insw(ap->ioaddr.data_addr, buf, words); | 3814 | ioread16_rep(ap->ioaddr.data_addr, buf, words); |
3952 | 3815 | ||
3953 | /* Transfer trailing 1 byte, if any. */ | 3816 | /* Transfer trailing 1 byte, if any. */ |
3954 | if (unlikely(buflen & 0x01)) { | 3817 | if (unlikely(buflen & 0x01)) { |
@@ -3957,16 +3820,16 @@ void ata_pio_data_xfer(struct ata_device *adev, unsigned char *buf, | |||
3957 | 3820 | ||
3958 | if (write_data) { | 3821 | if (write_data) { |
3959 | memcpy(align_buf, trailing_buf, 1); | 3822 | memcpy(align_buf, trailing_buf, 1); |
3960 | outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr); | 3823 | iowrite16(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr); |
3961 | } else { | 3824 | } else { |
3962 | align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr)); | 3825 | align_buf[0] = cpu_to_le16(ioread16(ap->ioaddr.data_addr)); |
3963 | memcpy(trailing_buf, align_buf, 1); | 3826 | memcpy(trailing_buf, align_buf, 1); |
3964 | } | 3827 | } |
3965 | } | 3828 | } |
3966 | } | 3829 | } |
3967 | 3830 | ||
3968 | /** | 3831 | /** |
3969 | * ata_pio_data_xfer_noirq - Transfer data by PIO | 3832 | * ata_data_xfer_noirq - Transfer data by PIO |
3970 | * @adev: device to target | 3833 | * @adev: device to target |
3971 | * @buf: data buffer | 3834 | * @buf: data buffer |
3972 | * @buflen: buffer length | 3835 | * @buflen: buffer length |
@@ -3978,13 +3841,12 @@ void ata_pio_data_xfer(struct ata_device *adev, unsigned char *buf, | |||
3978 | * LOCKING: | 3841 | * LOCKING: |
3979 | * Inherited from caller. | 3842 | * Inherited from caller. |
3980 | */ | 3843 | */ |
3981 | 3844 | void ata_data_xfer_noirq(struct ata_device *adev, unsigned char *buf, | |
3982 | void ata_pio_data_xfer_noirq(struct ata_device *adev, unsigned char *buf, | 3845 | unsigned int buflen, int write_data) |
3983 | unsigned int buflen, int write_data) | ||
3984 | { | 3846 | { |
3985 | unsigned long flags; | 3847 | unsigned long flags; |
3986 | local_irq_save(flags); | 3848 | local_irq_save(flags); |
3987 | ata_pio_data_xfer(adev, buf, buflen, write_data); | 3849 | ata_data_xfer(adev, buf, buflen, write_data); |
3988 | local_irq_restore(flags); | 3850 | local_irq_restore(flags); |
3989 | } | 3851 | } |
3990 | 3852 | ||
@@ -5770,7 +5632,7 @@ int ata_device_add(const struct ata_probe_ent *ent) | |||
5770 | host->n_ports = ent->n_ports; | 5632 | host->n_ports = ent->n_ports; |
5771 | host->irq = ent->irq; | 5633 | host->irq = ent->irq; |
5772 | host->irq2 = ent->irq2; | 5634 | host->irq2 = ent->irq2; |
5773 | host->mmio_base = ent->mmio_base; | 5635 | host->iomap = ent->iomap; |
5774 | host->private_data = ent->private_data; | 5636 | host->private_data = ent->private_data; |
5775 | 5637 | ||
5776 | /* register each port bound to this device */ | 5638 | /* register each port bound to this device */ |
@@ -5808,8 +5670,8 @@ int ata_device_add(const struct ata_probe_ent *ent) | |||
5808 | (ap->pio_mask << ATA_SHIFT_PIO); | 5670 | (ap->pio_mask << ATA_SHIFT_PIO); |
5809 | 5671 | ||
5810 | /* print per-port info to dmesg */ | 5672 | /* print per-port info to dmesg */ |
5811 | ata_port_printk(ap, KERN_INFO, "%cATA max %s cmd 0x%lX " | 5673 | ata_port_printk(ap, KERN_INFO, "%cATA max %s cmd 0x%p " |
5812 | "ctl 0x%lX bmdma 0x%lX irq %d\n", | 5674 | "ctl 0x%p bmdma 0x%p irq %d\n", |
5813 | ap->flags & ATA_FLAG_SATA ? 'S' : 'P', | 5675 | ap->flags & ATA_FLAG_SATA ? 'S' : 'P', |
5814 | ata_mode_string(xfer_mode_mask), | 5676 | ata_mode_string(xfer_mode_mask), |
5815 | ap->ioaddr.cmd_addr, | 5677 | ap->ioaddr.cmd_addr, |
@@ -6328,9 +6190,8 @@ EXPORT_SYMBOL_GPL(ata_altstatus); | |||
6328 | EXPORT_SYMBOL_GPL(ata_exec_command); | 6190 | EXPORT_SYMBOL_GPL(ata_exec_command); |
6329 | EXPORT_SYMBOL_GPL(ata_port_start); | 6191 | EXPORT_SYMBOL_GPL(ata_port_start); |
6330 | EXPORT_SYMBOL_GPL(ata_interrupt); | 6192 | EXPORT_SYMBOL_GPL(ata_interrupt); |
6331 | EXPORT_SYMBOL_GPL(ata_mmio_data_xfer); | 6193 | EXPORT_SYMBOL_GPL(ata_data_xfer); |
6332 | EXPORT_SYMBOL_GPL(ata_pio_data_xfer); | 6194 | EXPORT_SYMBOL_GPL(ata_data_xfer_noirq); |
6333 | EXPORT_SYMBOL_GPL(ata_pio_data_xfer_noirq); | ||
6334 | EXPORT_SYMBOL_GPL(ata_qc_prep); | 6195 | EXPORT_SYMBOL_GPL(ata_qc_prep); |
6335 | EXPORT_SYMBOL_GPL(ata_noop_qc_prep); | 6196 | EXPORT_SYMBOL_GPL(ata_noop_qc_prep); |
6336 | EXPORT_SYMBOL_GPL(ata_bmdma_setup); | 6197 | EXPORT_SYMBOL_GPL(ata_bmdma_setup); |
diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c index 21efe92a7135..c561b3be4a97 100644 --- a/drivers/ata/libata-sff.c +++ b/drivers/ata/libata-sff.c | |||
@@ -56,10 +56,7 @@ u8 ata_irq_on(struct ata_port *ap) | |||
56 | ap->ctl &= ~ATA_NIEN; | 56 | ap->ctl &= ~ATA_NIEN; |
57 | ap->last_ctl = ap->ctl; | 57 | ap->last_ctl = ap->ctl; |
58 | 58 | ||
59 | if (ap->flags & ATA_FLAG_MMIO) | 59 | iowrite8(ap->ctl, ioaddr->ctl_addr); |
60 | writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr); | ||
61 | else | ||
62 | outb(ap->ctl, ioaddr->ctl_addr); | ||
63 | tmp = ata_wait_idle(ap); | 60 | tmp = ata_wait_idle(ap); |
64 | 61 | ||
65 | ap->ops->irq_clear(ap); | 62 | ap->ops->irq_clear(ap); |
@@ -68,7 +65,7 @@ u8 ata_irq_on(struct ata_port *ap) | |||
68 | } | 65 | } |
69 | 66 | ||
70 | /** | 67 | /** |
71 | * ata_tf_load_pio - send taskfile registers to host controller | 68 | * ata_tf_load - send taskfile registers to host controller |
72 | * @ap: Port to which output is sent | 69 | * @ap: Port to which output is sent |
73 | * @tf: ATA taskfile register set | 70 | * @tf: ATA taskfile register set |
74 | * | 71 | * |
@@ -78,81 +75,23 @@ u8 ata_irq_on(struct ata_port *ap) | |||
78 | * Inherited from caller. | 75 | * Inherited from caller. |
79 | */ | 76 | */ |
80 | 77 | ||
81 | static void ata_tf_load_pio(struct ata_port *ap, const struct ata_taskfile *tf) | 78 | void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
82 | { | ||
83 | struct ata_ioports *ioaddr = &ap->ioaddr; | ||
84 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | ||
85 | |||
86 | if (tf->ctl != ap->last_ctl) { | ||
87 | outb(tf->ctl, ioaddr->ctl_addr); | ||
88 | ap->last_ctl = tf->ctl; | ||
89 | ata_wait_idle(ap); | ||
90 | } | ||
91 | |||
92 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | ||
93 | outb(tf->hob_feature, ioaddr->feature_addr); | ||
94 | outb(tf->hob_nsect, ioaddr->nsect_addr); | ||
95 | outb(tf->hob_lbal, ioaddr->lbal_addr); | ||
96 | outb(tf->hob_lbam, ioaddr->lbam_addr); | ||
97 | outb(tf->hob_lbah, ioaddr->lbah_addr); | ||
98 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | ||
99 | tf->hob_feature, | ||
100 | tf->hob_nsect, | ||
101 | tf->hob_lbal, | ||
102 | tf->hob_lbam, | ||
103 | tf->hob_lbah); | ||
104 | } | ||
105 | |||
106 | if (is_addr) { | ||
107 | outb(tf->feature, ioaddr->feature_addr); | ||
108 | outb(tf->nsect, ioaddr->nsect_addr); | ||
109 | outb(tf->lbal, ioaddr->lbal_addr); | ||
110 | outb(tf->lbam, ioaddr->lbam_addr); | ||
111 | outb(tf->lbah, ioaddr->lbah_addr); | ||
112 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | ||
113 | tf->feature, | ||
114 | tf->nsect, | ||
115 | tf->lbal, | ||
116 | tf->lbam, | ||
117 | tf->lbah); | ||
118 | } | ||
119 | |||
120 | if (tf->flags & ATA_TFLAG_DEVICE) { | ||
121 | outb(tf->device, ioaddr->device_addr); | ||
122 | VPRINTK("device 0x%X\n", tf->device); | ||
123 | } | ||
124 | |||
125 | ata_wait_idle(ap); | ||
126 | } | ||
127 | |||
128 | /** | ||
129 | * ata_tf_load_mmio - send taskfile registers to host controller | ||
130 | * @ap: Port to which output is sent | ||
131 | * @tf: ATA taskfile register set | ||
132 | * | ||
133 | * Outputs ATA taskfile to standard ATA host controller using MMIO. | ||
134 | * | ||
135 | * LOCKING: | ||
136 | * Inherited from caller. | ||
137 | */ | ||
138 | |||
139 | static void ata_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) | ||
140 | { | 79 | { |
141 | struct ata_ioports *ioaddr = &ap->ioaddr; | 80 | struct ata_ioports *ioaddr = &ap->ioaddr; |
142 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | 81 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; |
143 | 82 | ||
144 | if (tf->ctl != ap->last_ctl) { | 83 | if (tf->ctl != ap->last_ctl) { |
145 | writeb(tf->ctl, (void __iomem *) ap->ioaddr.ctl_addr); | 84 | iowrite8(tf->ctl, ioaddr->ctl_addr); |
146 | ap->last_ctl = tf->ctl; | 85 | ap->last_ctl = tf->ctl; |
147 | ata_wait_idle(ap); | 86 | ata_wait_idle(ap); |
148 | } | 87 | } |
149 | 88 | ||
150 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | 89 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { |
151 | writeb(tf->hob_feature, (void __iomem *) ioaddr->feature_addr); | 90 | iowrite8(tf->hob_feature, ioaddr->feature_addr); |
152 | writeb(tf->hob_nsect, (void __iomem *) ioaddr->nsect_addr); | 91 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); |
153 | writeb(tf->hob_lbal, (void __iomem *) ioaddr->lbal_addr); | 92 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); |
154 | writeb(tf->hob_lbam, (void __iomem *) ioaddr->lbam_addr); | 93 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); |
155 | writeb(tf->hob_lbah, (void __iomem *) ioaddr->lbah_addr); | 94 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); |
156 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | 95 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", |
157 | tf->hob_feature, | 96 | tf->hob_feature, |
158 | tf->hob_nsect, | 97 | tf->hob_nsect, |
@@ -162,11 +101,11 @@ static void ata_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) | |||
162 | } | 101 | } |
163 | 102 | ||
164 | if (is_addr) { | 103 | if (is_addr) { |
165 | writeb(tf->feature, (void __iomem *) ioaddr->feature_addr); | 104 | iowrite8(tf->feature, ioaddr->feature_addr); |
166 | writeb(tf->nsect, (void __iomem *) ioaddr->nsect_addr); | 105 | iowrite8(tf->nsect, ioaddr->nsect_addr); |
167 | writeb(tf->lbal, (void __iomem *) ioaddr->lbal_addr); | 106 | iowrite8(tf->lbal, ioaddr->lbal_addr); |
168 | writeb(tf->lbam, (void __iomem *) ioaddr->lbam_addr); | 107 | iowrite8(tf->lbam, ioaddr->lbam_addr); |
169 | writeb(tf->lbah, (void __iomem *) ioaddr->lbah_addr); | 108 | iowrite8(tf->lbah, ioaddr->lbah_addr); |
170 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | 109 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", |
171 | tf->feature, | 110 | tf->feature, |
172 | tf->nsect, | 111 | tf->nsect, |
@@ -176,108 +115,34 @@ static void ata_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) | |||
176 | } | 115 | } |
177 | 116 | ||
178 | if (tf->flags & ATA_TFLAG_DEVICE) { | 117 | if (tf->flags & ATA_TFLAG_DEVICE) { |
179 | writeb(tf->device, (void __iomem *) ioaddr->device_addr); | 118 | iowrite8(tf->device, ioaddr->device_addr); |
180 | VPRINTK("device 0x%X\n", tf->device); | 119 | VPRINTK("device 0x%X\n", tf->device); |
181 | } | 120 | } |
182 | 121 | ||
183 | ata_wait_idle(ap); | 122 | ata_wait_idle(ap); |
184 | } | 123 | } |
185 | 124 | ||
186 | |||
187 | /** | ||
188 | * ata_tf_load - send taskfile registers to host controller | ||
189 | * @ap: Port to which output is sent | ||
190 | * @tf: ATA taskfile register set | ||
191 | * | ||
192 | * Outputs ATA taskfile to standard ATA host controller using MMIO | ||
193 | * or PIO as indicated by the ATA_FLAG_MMIO flag. | ||
194 | * Writes the control, feature, nsect, lbal, lbam, and lbah registers. | ||
195 | * Optionally (ATA_TFLAG_LBA48) writes hob_feature, hob_nsect, | ||
196 | * hob_lbal, hob_lbam, and hob_lbah. | ||
197 | * | ||
198 | * This function waits for idle (!BUSY and !DRQ) after writing | ||
199 | * registers. If the control register has a new value, this | ||
200 | * function also waits for idle after writing control and before | ||
201 | * writing the remaining registers. | ||
202 | * | ||
203 | * May be used as the tf_load() entry in ata_port_operations. | ||
204 | * | ||
205 | * LOCKING: | ||
206 | * Inherited from caller. | ||
207 | */ | ||
208 | void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) | ||
209 | { | ||
210 | if (ap->flags & ATA_FLAG_MMIO) | ||
211 | ata_tf_load_mmio(ap, tf); | ||
212 | else | ||
213 | ata_tf_load_pio(ap, tf); | ||
214 | } | ||
215 | |||
216 | /** | ||
217 | * ata_exec_command_pio - issue ATA command to host controller | ||
218 | * @ap: port to which command is being issued | ||
219 | * @tf: ATA taskfile register set | ||
220 | * | ||
221 | * Issues PIO write to ATA command register, with proper | ||
222 | * synchronization with interrupt handler / other threads. | ||
223 | * | ||
224 | * LOCKING: | ||
225 | * spin_lock_irqsave(host lock) | ||
226 | */ | ||
227 | |||
228 | static void ata_exec_command_pio(struct ata_port *ap, const struct ata_taskfile *tf) | ||
229 | { | ||
230 | DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command); | ||
231 | |||
232 | outb(tf->command, ap->ioaddr.command_addr); | ||
233 | ata_pause(ap); | ||
234 | } | ||
235 | |||
236 | |||
237 | /** | 125 | /** |
238 | * ata_exec_command_mmio - issue ATA command to host controller | 126 | * ata_exec_command - issue ATA command to host controller |
239 | * @ap: port to which command is being issued | 127 | * @ap: port to which command is being issued |
240 | * @tf: ATA taskfile register set | 128 | * @tf: ATA taskfile register set |
241 | * | 129 | * |
242 | * Issues MMIO write to ATA command register, with proper | 130 | * Issues ATA command, with proper synchronization with interrupt |
243 | * synchronization with interrupt handler / other threads. | 131 | * handler / other threads. |
244 | * | ||
245 | * FIXME: missing write posting for 400nS delay enforcement | ||
246 | * | 132 | * |
247 | * LOCKING: | 133 | * LOCKING: |
248 | * spin_lock_irqsave(host lock) | 134 | * spin_lock_irqsave(host lock) |
249 | */ | 135 | */ |
250 | 136 | void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) | |
251 | static void ata_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) | ||
252 | { | 137 | { |
253 | DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command); | 138 | DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command); |
254 | 139 | ||
255 | writeb(tf->command, (void __iomem *) ap->ioaddr.command_addr); | 140 | iowrite8(tf->command, ap->ioaddr.command_addr); |
256 | ata_pause(ap); | 141 | ata_pause(ap); |
257 | } | 142 | } |
258 | 143 | ||
259 | |||
260 | /** | ||
261 | * ata_exec_command - issue ATA command to host controller | ||
262 | * @ap: port to which command is being issued | ||
263 | * @tf: ATA taskfile register set | ||
264 | * | ||
265 | * Issues PIO/MMIO write to ATA command register, with proper | ||
266 | * synchronization with interrupt handler / other threads. | ||
267 | * | ||
268 | * LOCKING: | ||
269 | * spin_lock_irqsave(host lock) | ||
270 | */ | ||
271 | void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) | ||
272 | { | ||
273 | if (ap->flags & ATA_FLAG_MMIO) | ||
274 | ata_exec_command_mmio(ap, tf); | ||
275 | else | ||
276 | ata_exec_command_pio(ap, tf); | ||
277 | } | ||
278 | |||
279 | /** | 144 | /** |
280 | * ata_tf_read_pio - input device's ATA taskfile shadow registers | 145 | * ata_tf_read - input device's ATA taskfile shadow registers |
281 | * @ap: Port from which input is read | 146 | * @ap: Port from which input is read |
282 | * @tf: ATA taskfile register set for storing input | 147 | * @tf: ATA taskfile register set for storing input |
283 | * | 148 | * |
@@ -287,121 +152,28 @@ void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) | |||
287 | * LOCKING: | 152 | * LOCKING: |
288 | * Inherited from caller. | 153 | * Inherited from caller. |
289 | */ | 154 | */ |
290 | 155 | void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | |
291 | static void ata_tf_read_pio(struct ata_port *ap, struct ata_taskfile *tf) | ||
292 | { | ||
293 | struct ata_ioports *ioaddr = &ap->ioaddr; | ||
294 | |||
295 | tf->command = ata_check_status(ap); | ||
296 | tf->feature = inb(ioaddr->error_addr); | ||
297 | tf->nsect = inb(ioaddr->nsect_addr); | ||
298 | tf->lbal = inb(ioaddr->lbal_addr); | ||
299 | tf->lbam = inb(ioaddr->lbam_addr); | ||
300 | tf->lbah = inb(ioaddr->lbah_addr); | ||
301 | tf->device = inb(ioaddr->device_addr); | ||
302 | |||
303 | if (tf->flags & ATA_TFLAG_LBA48) { | ||
304 | outb(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | ||
305 | tf->hob_feature = inb(ioaddr->error_addr); | ||
306 | tf->hob_nsect = inb(ioaddr->nsect_addr); | ||
307 | tf->hob_lbal = inb(ioaddr->lbal_addr); | ||
308 | tf->hob_lbam = inb(ioaddr->lbam_addr); | ||
309 | tf->hob_lbah = inb(ioaddr->lbah_addr); | ||
310 | } | ||
311 | } | ||
312 | |||
313 | /** | ||
314 | * ata_tf_read_mmio - input device's ATA taskfile shadow registers | ||
315 | * @ap: Port from which input is read | ||
316 | * @tf: ATA taskfile register set for storing input | ||
317 | * | ||
318 | * Reads ATA taskfile registers for currently-selected device | ||
319 | * into @tf via MMIO. | ||
320 | * | ||
321 | * LOCKING: | ||
322 | * Inherited from caller. | ||
323 | */ | ||
324 | |||
325 | static void ata_tf_read_mmio(struct ata_port *ap, struct ata_taskfile *tf) | ||
326 | { | 156 | { |
327 | struct ata_ioports *ioaddr = &ap->ioaddr; | 157 | struct ata_ioports *ioaddr = &ap->ioaddr; |
328 | 158 | ||
329 | tf->command = ata_check_status(ap); | 159 | tf->command = ata_check_status(ap); |
330 | tf->feature = readb((void __iomem *)ioaddr->error_addr); | 160 | tf->feature = ioread8(ioaddr->error_addr); |
331 | tf->nsect = readb((void __iomem *)ioaddr->nsect_addr); | 161 | tf->nsect = ioread8(ioaddr->nsect_addr); |
332 | tf->lbal = readb((void __iomem *)ioaddr->lbal_addr); | 162 | tf->lbal = ioread8(ioaddr->lbal_addr); |
333 | tf->lbam = readb((void __iomem *)ioaddr->lbam_addr); | 163 | tf->lbam = ioread8(ioaddr->lbam_addr); |
334 | tf->lbah = readb((void __iomem *)ioaddr->lbah_addr); | 164 | tf->lbah = ioread8(ioaddr->lbah_addr); |
335 | tf->device = readb((void __iomem *)ioaddr->device_addr); | 165 | tf->device = ioread8(ioaddr->device_addr); |
336 | 166 | ||
337 | if (tf->flags & ATA_TFLAG_LBA48) { | 167 | if (tf->flags & ATA_TFLAG_LBA48) { |
338 | writeb(tf->ctl | ATA_HOB, (void __iomem *) ap->ioaddr.ctl_addr); | 168 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); |
339 | tf->hob_feature = readb((void __iomem *)ioaddr->error_addr); | 169 | tf->hob_feature = ioread8(ioaddr->error_addr); |
340 | tf->hob_nsect = readb((void __iomem *)ioaddr->nsect_addr); | 170 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); |
341 | tf->hob_lbal = readb((void __iomem *)ioaddr->lbal_addr); | 171 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); |
342 | tf->hob_lbam = readb((void __iomem *)ioaddr->lbam_addr); | 172 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); |
343 | tf->hob_lbah = readb((void __iomem *)ioaddr->lbah_addr); | 173 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); |
344 | } | 174 | } |
345 | } | 175 | } |
346 | 176 | ||
347 | |||
348 | /** | ||
349 | * ata_tf_read - input device's ATA taskfile shadow registers | ||
350 | * @ap: Port from which input is read | ||
351 | * @tf: ATA taskfile register set for storing input | ||
352 | * | ||
353 | * Reads ATA taskfile registers for currently-selected device | ||
354 | * into @tf. | ||
355 | * | ||
356 | * Reads nsect, lbal, lbam, lbah, and device. If ATA_TFLAG_LBA48 | ||
357 | * is set, also reads the hob registers. | ||
358 | * | ||
359 | * May be used as the tf_read() entry in ata_port_operations. | ||
360 | * | ||
361 | * LOCKING: | ||
362 | * Inherited from caller. | ||
363 | */ | ||
364 | void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | ||
365 | { | ||
366 | if (ap->flags & ATA_FLAG_MMIO) | ||
367 | ata_tf_read_mmio(ap, tf); | ||
368 | else | ||
369 | ata_tf_read_pio(ap, tf); | ||
370 | } | ||
371 | |||
372 | /** | ||
373 | * ata_check_status_pio - Read device status reg & clear interrupt | ||
374 | * @ap: port where the device is | ||
375 | * | ||
376 | * Reads ATA taskfile status register for currently-selected device | ||
377 | * and return its value. This also clears pending interrupts | ||
378 | * from this device | ||
379 | * | ||
380 | * LOCKING: | ||
381 | * Inherited from caller. | ||
382 | */ | ||
383 | static u8 ata_check_status_pio(struct ata_port *ap) | ||
384 | { | ||
385 | return inb(ap->ioaddr.status_addr); | ||
386 | } | ||
387 | |||
388 | /** | ||
389 | * ata_check_status_mmio - Read device status reg & clear interrupt | ||
390 | * @ap: port where the device is | ||
391 | * | ||
392 | * Reads ATA taskfile status register for currently-selected device | ||
393 | * via MMIO and return its value. This also clears pending interrupts | ||
394 | * from this device | ||
395 | * | ||
396 | * LOCKING: | ||
397 | * Inherited from caller. | ||
398 | */ | ||
399 | static u8 ata_check_status_mmio(struct ata_port *ap) | ||
400 | { | ||
401 | return readb((void __iomem *) ap->ioaddr.status_addr); | ||
402 | } | ||
403 | |||
404 | |||
405 | /** | 177 | /** |
406 | * ata_check_status - Read device status reg & clear interrupt | 178 | * ata_check_status - Read device status reg & clear interrupt |
407 | * @ap: port where the device is | 179 | * @ap: port where the device is |
@@ -410,19 +182,14 @@ static u8 ata_check_status_mmio(struct ata_port *ap) | |||
410 | * and return its value. This also clears pending interrupts | 182 | * and return its value. This also clears pending interrupts |
411 | * from this device | 183 | * from this device |
412 | * | 184 | * |
413 | * May be used as the check_status() entry in ata_port_operations. | ||
414 | * | ||
415 | * LOCKING: | 185 | * LOCKING: |
416 | * Inherited from caller. | 186 | * Inherited from caller. |
417 | */ | 187 | */ |
418 | u8 ata_check_status(struct ata_port *ap) | 188 | u8 ata_check_status(struct ata_port *ap) |
419 | { | 189 | { |
420 | if (ap->flags & ATA_FLAG_MMIO) | 190 | return ioread8(ap->ioaddr.status_addr); |
421 | return ata_check_status_mmio(ap); | ||
422 | return ata_check_status_pio(ap); | ||
423 | } | 191 | } |
424 | 192 | ||
425 | |||
426 | /** | 193 | /** |
427 | * ata_altstatus - Read device alternate status reg | 194 | * ata_altstatus - Read device alternate status reg |
428 | * @ap: port where the device is | 195 | * @ap: port where the device is |
@@ -441,58 +208,52 @@ u8 ata_altstatus(struct ata_port *ap) | |||
441 | if (ap->ops->check_altstatus) | 208 | if (ap->ops->check_altstatus) |
442 | return ap->ops->check_altstatus(ap); | 209 | return ap->ops->check_altstatus(ap); |
443 | 210 | ||
444 | if (ap->flags & ATA_FLAG_MMIO) | 211 | return ioread8(ap->ioaddr.altstatus_addr); |
445 | return readb((void __iomem *)ap->ioaddr.altstatus_addr); | ||
446 | return inb(ap->ioaddr.altstatus_addr); | ||
447 | } | 212 | } |
448 | 213 | ||
449 | /** | 214 | /** |
450 | * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction | 215 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction |
451 | * @qc: Info associated with this ATA transaction. | 216 | * @qc: Info associated with this ATA transaction. |
452 | * | 217 | * |
453 | * LOCKING: | 218 | * LOCKING: |
454 | * spin_lock_irqsave(host lock) | 219 | * spin_lock_irqsave(host lock) |
455 | */ | 220 | */ |
456 | 221 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | |
457 | static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc) | ||
458 | { | 222 | { |
459 | struct ata_port *ap = qc->ap; | 223 | struct ata_port *ap = qc->ap; |
460 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | 224 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); |
461 | u8 dmactl; | 225 | u8 dmactl; |
462 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; | ||
463 | 226 | ||
464 | /* load PRD table addr. */ | 227 | /* load PRD table addr. */ |
465 | mb(); /* make sure PRD table writes are visible to controller */ | 228 | mb(); /* make sure PRD table writes are visible to controller */ |
466 | writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS); | 229 | iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); |
467 | 230 | ||
468 | /* specify data direction, triple-check start bit is clear */ | 231 | /* specify data direction, triple-check start bit is clear */ |
469 | dmactl = readb(mmio + ATA_DMA_CMD); | 232 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
470 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | 233 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); |
471 | if (!rw) | 234 | if (!rw) |
472 | dmactl |= ATA_DMA_WR; | 235 | dmactl |= ATA_DMA_WR; |
473 | writeb(dmactl, mmio + ATA_DMA_CMD); | 236 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
474 | 237 | ||
475 | /* issue r/w command */ | 238 | /* issue r/w command */ |
476 | ap->ops->exec_command(ap, &qc->tf); | 239 | ap->ops->exec_command(ap, &qc->tf); |
477 | } | 240 | } |
478 | 241 | ||
479 | /** | 242 | /** |
480 | * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction | 243 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction |
481 | * @qc: Info associated with this ATA transaction. | 244 | * @qc: Info associated with this ATA transaction. |
482 | * | 245 | * |
483 | * LOCKING: | 246 | * LOCKING: |
484 | * spin_lock_irqsave(host lock) | 247 | * spin_lock_irqsave(host lock) |
485 | */ | 248 | */ |
486 | 249 | void ata_bmdma_start (struct ata_queued_cmd *qc) | |
487 | static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc) | ||
488 | { | 250 | { |
489 | struct ata_port *ap = qc->ap; | 251 | struct ata_port *ap = qc->ap; |
490 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; | ||
491 | u8 dmactl; | 252 | u8 dmactl; |
492 | 253 | ||
493 | /* start host DMA transaction */ | 254 | /* start host DMA transaction */ |
494 | dmactl = readb(mmio + ATA_DMA_CMD); | 255 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
495 | writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD); | 256 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
496 | 257 | ||
497 | /* Strictly, one may wish to issue a readb() here, to | 258 | /* Strictly, one may wish to issue a readb() here, to |
498 | * flush the mmio write. However, control also passes | 259 | * flush the mmio write. However, control also passes |
@@ -508,96 +269,6 @@ static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc) | |||
508 | } | 269 | } |
509 | 270 | ||
510 | /** | 271 | /** |
511 | * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO) | ||
512 | * @qc: Info associated with this ATA transaction. | ||
513 | * | ||
514 | * LOCKING: | ||
515 | * spin_lock_irqsave(host lock) | ||
516 | */ | ||
517 | |||
518 | static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc) | ||
519 | { | ||
520 | struct ata_port *ap = qc->ap; | ||
521 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | ||
522 | u8 dmactl; | ||
523 | |||
524 | /* load PRD table addr. */ | ||
525 | outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); | ||
526 | |||
527 | /* specify data direction, triple-check start bit is clear */ | ||
528 | dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
529 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | ||
530 | if (!rw) | ||
531 | dmactl |= ATA_DMA_WR; | ||
532 | outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
533 | |||
534 | /* issue r/w command */ | ||
535 | ap->ops->exec_command(ap, &qc->tf); | ||
536 | } | ||
537 | |||
538 | /** | ||
539 | * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO) | ||
540 | * @qc: Info associated with this ATA transaction. | ||
541 | * | ||
542 | * LOCKING: | ||
543 | * spin_lock_irqsave(host lock) | ||
544 | */ | ||
545 | |||
546 | static void ata_bmdma_start_pio (struct ata_queued_cmd *qc) | ||
547 | { | ||
548 | struct ata_port *ap = qc->ap; | ||
549 | u8 dmactl; | ||
550 | |||
551 | /* start host DMA transaction */ | ||
552 | dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
553 | outb(dmactl | ATA_DMA_START, | ||
554 | ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
555 | } | ||
556 | |||
557 | |||
558 | /** | ||
559 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction | ||
560 | * @qc: Info associated with this ATA transaction. | ||
561 | * | ||
562 | * Writes the ATA_DMA_START flag to the DMA command register. | ||
563 | * | ||
564 | * May be used as the bmdma_start() entry in ata_port_operations. | ||
565 | * | ||
566 | * LOCKING: | ||
567 | * spin_lock_irqsave(host lock) | ||
568 | */ | ||
569 | void ata_bmdma_start(struct ata_queued_cmd *qc) | ||
570 | { | ||
571 | if (qc->ap->flags & ATA_FLAG_MMIO) | ||
572 | ata_bmdma_start_mmio(qc); | ||
573 | else | ||
574 | ata_bmdma_start_pio(qc); | ||
575 | } | ||
576 | |||
577 | |||
578 | /** | ||
579 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction | ||
580 | * @qc: Info associated with this ATA transaction. | ||
581 | * | ||
582 | * Writes address of PRD table to device's PRD Table Address | ||
583 | * register, sets the DMA control register, and calls | ||
584 | * ops->exec_command() to start the transfer. | ||
585 | * | ||
586 | * May be used as the bmdma_setup() entry in ata_port_operations. | ||
587 | * | ||
588 | * LOCKING: | ||
589 | * spin_lock_irqsave(host lock) | ||
590 | */ | ||
591 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | ||
592 | { | ||
593 | if (qc->ap->flags & ATA_FLAG_MMIO) | ||
594 | ata_bmdma_setup_mmio(qc); | ||
595 | else | ||
596 | ata_bmdma_setup_pio(qc); | ||
597 | } | ||
598 | |||
599 | |||
600 | /** | ||
601 | * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. | 272 | * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. |
602 | * @ap: Port associated with this ATA transaction. | 273 | * @ap: Port associated with this ATA transaction. |
603 | * | 274 | * |
@@ -608,23 +279,16 @@ void ata_bmdma_setup(struct ata_queued_cmd *qc) | |||
608 | * LOCKING: | 279 | * LOCKING: |
609 | * spin_lock_irqsave(host lock) | 280 | * spin_lock_irqsave(host lock) |
610 | */ | 281 | */ |
611 | |||
612 | void ata_bmdma_irq_clear(struct ata_port *ap) | 282 | void ata_bmdma_irq_clear(struct ata_port *ap) |
613 | { | 283 | { |
614 | if (!ap->ioaddr.bmdma_addr) | 284 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
285 | |||
286 | if (!mmio) | ||
615 | return; | 287 | return; |
616 | 288 | ||
617 | if (ap->flags & ATA_FLAG_MMIO) { | 289 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); |
618 | void __iomem *mmio = | ||
619 | ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS; | ||
620 | writeb(readb(mmio), mmio); | ||
621 | } else { | ||
622 | unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS; | ||
623 | outb(inb(addr), addr); | ||
624 | } | ||
625 | } | 290 | } |
626 | 291 | ||
627 | |||
628 | /** | 292 | /** |
629 | * ata_bmdma_status - Read PCI IDE BMDMA status | 293 | * ata_bmdma_status - Read PCI IDE BMDMA status |
630 | * @ap: Port associated with this ATA transaction. | 294 | * @ap: Port associated with this ATA transaction. |
@@ -636,19 +300,11 @@ void ata_bmdma_irq_clear(struct ata_port *ap) | |||
636 | * LOCKING: | 300 | * LOCKING: |
637 | * spin_lock_irqsave(host lock) | 301 | * spin_lock_irqsave(host lock) |
638 | */ | 302 | */ |
639 | |||
640 | u8 ata_bmdma_status(struct ata_port *ap) | 303 | u8 ata_bmdma_status(struct ata_port *ap) |
641 | { | 304 | { |
642 | u8 host_stat; | 305 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); |
643 | if (ap->flags & ATA_FLAG_MMIO) { | ||
644 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; | ||
645 | host_stat = readb(mmio + ATA_DMA_STATUS); | ||
646 | } else | ||
647 | host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | ||
648 | return host_stat; | ||
649 | } | 306 | } |
650 | 307 | ||
651 | |||
652 | /** | 308 | /** |
653 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | 309 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer |
654 | * @qc: Command we are ending DMA for | 310 | * @qc: Command we are ending DMA for |
@@ -660,21 +316,14 @@ u8 ata_bmdma_status(struct ata_port *ap) | |||
660 | * LOCKING: | 316 | * LOCKING: |
661 | * spin_lock_irqsave(host lock) | 317 | * spin_lock_irqsave(host lock) |
662 | */ | 318 | */ |
663 | |||
664 | void ata_bmdma_stop(struct ata_queued_cmd *qc) | 319 | void ata_bmdma_stop(struct ata_queued_cmd *qc) |
665 | { | 320 | { |
666 | struct ata_port *ap = qc->ap; | 321 | struct ata_port *ap = qc->ap; |
667 | if (ap->flags & ATA_FLAG_MMIO) { | 322 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
668 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; | ||
669 | 323 | ||
670 | /* clear start/stop bit */ | 324 | /* clear start/stop bit */ |
671 | writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | 325 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, |
672 | mmio + ATA_DMA_CMD); | 326 | mmio + ATA_DMA_CMD); |
673 | } else { | ||
674 | /* clear start/stop bit */ | ||
675 | outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START, | ||
676 | ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
677 | } | ||
678 | 327 | ||
679 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | 328 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ |
680 | ata_altstatus(ap); /* dummy read */ | 329 | ata_altstatus(ap); /* dummy read */ |
@@ -696,10 +345,7 @@ void ata_bmdma_freeze(struct ata_port *ap) | |||
696 | ap->ctl |= ATA_NIEN; | 345 | ap->ctl |= ATA_NIEN; |
697 | ap->last_ctl = ap->ctl; | 346 | ap->last_ctl = ap->ctl; |
698 | 347 | ||
699 | if (ap->flags & ATA_FLAG_MMIO) | 348 | iowrite8(ap->ctl, ioaddr->ctl_addr); |
700 | writeb(ap->ctl, (void __iomem *)ioaddr->ctl_addr); | ||
701 | else | ||
702 | outb(ap->ctl, ioaddr->ctl_addr); | ||
703 | 349 | ||
704 | /* Under certain circumstances, some controllers raise IRQ on | 350 | /* Under certain circumstances, some controllers raise IRQ on |
705 | * ATA_NIEN manipulation. Also, many controllers fail to mask | 351 | * ATA_NIEN manipulation. Also, many controllers fail to mask |
@@ -868,11 +514,24 @@ static int ata_resources_present(struct pci_dev *pdev, int port) | |||
868 | struct ata_probe_ent * | 514 | struct ata_probe_ent * |
869 | ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int ports) | 515 | ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int ports) |
870 | { | 516 | { |
871 | struct ata_probe_ent *probe_ent = | 517 | struct ata_probe_ent *probe_ent; |
872 | ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]); | 518 | int i, p = 0; |
873 | int p = 0; | 519 | void __iomem * const *iomap; |
874 | unsigned long bmdma; | 520 | |
521 | /* iomap BARs */ | ||
522 | for (i = 0; i < 4; i++) { | ||
523 | if (pcim_iomap(pdev, i, 0) == NULL) { | ||
524 | dev_printk(KERN_ERR, &pdev->dev, | ||
525 | "failed to iomap PCI BAR %d\n", i); | ||
526 | return NULL; | ||
527 | } | ||
528 | } | ||
529 | |||
530 | pcim_iomap(pdev, 4, 0); /* may fail */ | ||
531 | iomap = pcim_iomap_table(pdev); | ||
875 | 532 | ||
533 | /* alloc and init probe_ent */ | ||
534 | probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]); | ||
876 | if (!probe_ent) | 535 | if (!probe_ent) |
877 | return NULL; | 536 | return NULL; |
878 | 537 | ||
@@ -887,33 +546,30 @@ ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int | |||
887 | ports &= ~ATA_PORT_SECONDARY; | 546 | ports &= ~ATA_PORT_SECONDARY; |
888 | 547 | ||
889 | if (ports & ATA_PORT_PRIMARY) { | 548 | if (ports & ATA_PORT_PRIMARY) { |
890 | probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 0); | 549 | probe_ent->port[p].cmd_addr = iomap[0]; |
891 | probe_ent->port[p].altstatus_addr = | 550 | probe_ent->port[p].altstatus_addr = |
892 | probe_ent->port[p].ctl_addr = | 551 | probe_ent->port[p].ctl_addr = (void __iomem *) |
893 | pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS; | 552 | ((unsigned long)iomap[1] | ATA_PCI_CTL_OFS); |
894 | bmdma = pci_resource_start(pdev, 4); | 553 | if (iomap[4]) { |
895 | if (bmdma) { | ||
896 | if ((!(port[p]->flags & ATA_FLAG_IGN_SIMPLEX)) && | 554 | if ((!(port[p]->flags & ATA_FLAG_IGN_SIMPLEX)) && |
897 | (inb(bmdma + 2) & 0x80)) | 555 | (ioread8(iomap[4] + 2) & 0x80)) |
898 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; | 556 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
899 | probe_ent->port[p].bmdma_addr = bmdma; | 557 | probe_ent->port[p].bmdma_addr = iomap[4]; |
900 | } | 558 | } |
901 | ata_std_ports(&probe_ent->port[p]); | 559 | ata_std_ports(&probe_ent->port[p]); |
902 | p++; | 560 | p++; |
903 | } | 561 | } |
904 | 562 | ||
905 | if (ports & ATA_PORT_SECONDARY) { | 563 | if (ports & ATA_PORT_SECONDARY) { |
906 | probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 2); | 564 | probe_ent->port[p].cmd_addr = iomap[2]; |
907 | probe_ent->port[p].altstatus_addr = | 565 | probe_ent->port[p].altstatus_addr = |
908 | probe_ent->port[p].ctl_addr = | 566 | probe_ent->port[p].ctl_addr = (void __iomem *) |
909 | pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS; | 567 | ((unsigned long)iomap[3] | ATA_PCI_CTL_OFS); |
910 | bmdma = pci_resource_start(pdev, 4); | 568 | if (iomap[4]) { |
911 | if (bmdma) { | ||
912 | bmdma += 8; | ||
913 | if ((!(port[p]->flags & ATA_FLAG_IGN_SIMPLEX)) && | 569 | if ((!(port[p]->flags & ATA_FLAG_IGN_SIMPLEX)) && |
914 | (inb(bmdma + 2) & 0x80)) | 570 | (ioread8(iomap[4] + 10) & 0x80)) |
915 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; | 571 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
916 | probe_ent->port[p].bmdma_addr = bmdma; | 572 | probe_ent->port[p].bmdma_addr = iomap[4] + 8; |
917 | } | 573 | } |
918 | ata_std_ports(&probe_ent->port[p]); | 574 | ata_std_ports(&probe_ent->port[p]); |
919 | probe_ent->pinfo2 = port[1]; | 575 | probe_ent->pinfo2 = port[1]; |
@@ -924,13 +580,29 @@ ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int | |||
924 | return probe_ent; | 580 | return probe_ent; |
925 | } | 581 | } |
926 | 582 | ||
927 | |||
928 | static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, | 583 | static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, |
929 | struct ata_port_info **port, int port_mask) | 584 | struct ata_port_info **port, int port_mask) |
930 | { | 585 | { |
931 | struct ata_probe_ent *probe_ent; | 586 | struct ata_probe_ent *probe_ent; |
932 | unsigned long bmdma = pci_resource_start(pdev, 4); | 587 | void __iomem *iomap[5] = { }, *bmdma; |
588 | |||
589 | if (port_mask & ATA_PORT_PRIMARY) { | ||
590 | iomap[0] = devm_ioport_map(&pdev->dev, ATA_PRIMARY_CMD, 8); | ||
591 | iomap[1] = devm_ioport_map(&pdev->dev, ATA_PRIMARY_CTL, 1); | ||
592 | if (!iomap[0] || !iomap[1]) | ||
593 | return NULL; | ||
594 | } | ||
595 | |||
596 | if (port_mask & ATA_PORT_SECONDARY) { | ||
597 | iomap[2] = devm_ioport_map(&pdev->dev, ATA_SECONDARY_CMD, 8); | ||
598 | iomap[3] = devm_ioport_map(&pdev->dev, ATA_SECONDARY_CTL, 1); | ||
599 | if (!iomap[2] || !iomap[3]) | ||
600 | return NULL; | ||
601 | } | ||
602 | |||
603 | bmdma = pcim_iomap(pdev, 4, 16); /* may fail */ | ||
933 | 604 | ||
605 | /* alloc and init probe_ent */ | ||
934 | probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]); | 606 | probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]); |
935 | if (!probe_ent) | 607 | if (!probe_ent) |
936 | return NULL; | 608 | return NULL; |
@@ -940,13 +612,13 @@ static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, | |||
940 | 612 | ||
941 | if (port_mask & ATA_PORT_PRIMARY) { | 613 | if (port_mask & ATA_PORT_PRIMARY) { |
942 | probe_ent->irq = ATA_PRIMARY_IRQ(pdev); | 614 | probe_ent->irq = ATA_PRIMARY_IRQ(pdev); |
943 | probe_ent->port[0].cmd_addr = ATA_PRIMARY_CMD; | 615 | probe_ent->port[0].cmd_addr = iomap[0]; |
944 | probe_ent->port[0].altstatus_addr = | 616 | probe_ent->port[0].altstatus_addr = |
945 | probe_ent->port[0].ctl_addr = ATA_PRIMARY_CTL; | 617 | probe_ent->port[0].ctl_addr = iomap[1]; |
946 | if (bmdma) { | 618 | if (bmdma) { |
947 | probe_ent->port[0].bmdma_addr = bmdma; | 619 | probe_ent->port[0].bmdma_addr = bmdma; |
948 | if ((!(port[0]->flags & ATA_FLAG_IGN_SIMPLEX)) && | 620 | if ((!(port[0]->flags & ATA_FLAG_IGN_SIMPLEX)) && |
949 | (inb(bmdma + 2) & 0x80)) | 621 | (ioread8(bmdma + 2) & 0x80)) |
950 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; | 622 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
951 | } | 623 | } |
952 | ata_std_ports(&probe_ent->port[0]); | 624 | ata_std_ports(&probe_ent->port[0]); |
@@ -958,13 +630,13 @@ static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, | |||
958 | probe_ent->irq2 = ATA_SECONDARY_IRQ(pdev); | 630 | probe_ent->irq2 = ATA_SECONDARY_IRQ(pdev); |
959 | else | 631 | else |
960 | probe_ent->irq = ATA_SECONDARY_IRQ(pdev); | 632 | probe_ent->irq = ATA_SECONDARY_IRQ(pdev); |
961 | probe_ent->port[1].cmd_addr = ATA_SECONDARY_CMD; | 633 | probe_ent->port[1].cmd_addr = iomap[2]; |
962 | probe_ent->port[1].altstatus_addr = | 634 | probe_ent->port[1].altstatus_addr = |
963 | probe_ent->port[1].ctl_addr = ATA_SECONDARY_CTL; | 635 | probe_ent->port[1].ctl_addr = iomap[3]; |
964 | if (bmdma) { | 636 | if (bmdma) { |
965 | probe_ent->port[1].bmdma_addr = bmdma + 8; | 637 | probe_ent->port[1].bmdma_addr = bmdma + 8; |
966 | if ((!(port[1]->flags & ATA_FLAG_IGN_SIMPLEX)) && | 638 | if ((!(port[1]->flags & ATA_FLAG_IGN_SIMPLEX)) && |
967 | (inb(bmdma + 10) & 0x80)) | 639 | (ioread8(bmdma + 10) & 0x80)) |
968 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; | 640 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
969 | } | 641 | } |
970 | ata_std_ports(&probe_ent->port[1]); | 642 | ata_std_ports(&probe_ent->port[1]); |
diff --git a/drivers/ata/pata_ali.c b/drivers/ata/pata_ali.c index f4fdb10211e3..dffa1f539fc9 100644 --- a/drivers/ata/pata_ali.c +++ b/drivers/ata/pata_ali.c | |||
@@ -370,7 +370,7 @@ static struct ata_port_operations ali_early_port_ops = { | |||
370 | .qc_prep = ata_qc_prep, | 370 | .qc_prep = ata_qc_prep, |
371 | .qc_issue = ata_qc_issue_prot, | 371 | .qc_issue = ata_qc_issue_prot, |
372 | 372 | ||
373 | .data_xfer = ata_pio_data_xfer, | 373 | .data_xfer = ata_data_xfer, |
374 | 374 | ||
375 | .irq_handler = ata_interrupt, | 375 | .irq_handler = ata_interrupt, |
376 | .irq_clear = ata_bmdma_irq_clear, | 376 | .irq_clear = ata_bmdma_irq_clear, |
@@ -409,7 +409,7 @@ static struct ata_port_operations ali_20_port_ops = { | |||
409 | .qc_prep = ata_qc_prep, | 409 | .qc_prep = ata_qc_prep, |
410 | .qc_issue = ata_qc_issue_prot, | 410 | .qc_issue = ata_qc_issue_prot, |
411 | 411 | ||
412 | .data_xfer = ata_pio_data_xfer, | 412 | .data_xfer = ata_data_xfer, |
413 | 413 | ||
414 | .irq_handler = ata_interrupt, | 414 | .irq_handler = ata_interrupt, |
415 | .irq_clear = ata_bmdma_irq_clear, | 415 | .irq_clear = ata_bmdma_irq_clear, |
@@ -445,7 +445,7 @@ static struct ata_port_operations ali_c2_port_ops = { | |||
445 | .qc_prep = ata_qc_prep, | 445 | .qc_prep = ata_qc_prep, |
446 | .qc_issue = ata_qc_issue_prot, | 446 | .qc_issue = ata_qc_issue_prot, |
447 | 447 | ||
448 | .data_xfer = ata_pio_data_xfer, | 448 | .data_xfer = ata_data_xfer, |
449 | 449 | ||
450 | .irq_handler = ata_interrupt, | 450 | .irq_handler = ata_interrupt, |
451 | .irq_clear = ata_bmdma_irq_clear, | 451 | .irq_clear = ata_bmdma_irq_clear, |
@@ -480,7 +480,7 @@ static struct ata_port_operations ali_c5_port_ops = { | |||
480 | .qc_prep = ata_qc_prep, | 480 | .qc_prep = ata_qc_prep, |
481 | .qc_issue = ata_qc_issue_prot, | 481 | .qc_issue = ata_qc_issue_prot, |
482 | 482 | ||
483 | .data_xfer = ata_pio_data_xfer, | 483 | .data_xfer = ata_data_xfer, |
484 | 484 | ||
485 | .irq_handler = ata_interrupt, | 485 | .irq_handler = ata_interrupt, |
486 | .irq_clear = ata_bmdma_irq_clear, | 486 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_amd.c b/drivers/ata/pata_amd.c index 7ee0c83c657a..ed0e4f6fc715 100644 --- a/drivers/ata/pata_amd.c +++ b/drivers/ata/pata_amd.c | |||
@@ -362,7 +362,7 @@ static struct ata_port_operations amd33_port_ops = { | |||
362 | .qc_prep = ata_qc_prep, | 362 | .qc_prep = ata_qc_prep, |
363 | .qc_issue = ata_qc_issue_prot, | 363 | .qc_issue = ata_qc_issue_prot, |
364 | 364 | ||
365 | .data_xfer = ata_pio_data_xfer, | 365 | .data_xfer = ata_data_xfer, |
366 | 366 | ||
367 | .irq_handler = ata_interrupt, | 367 | .irq_handler = ata_interrupt, |
368 | .irq_clear = ata_bmdma_irq_clear, | 368 | .irq_clear = ata_bmdma_irq_clear, |
@@ -394,7 +394,7 @@ static struct ata_port_operations amd66_port_ops = { | |||
394 | .qc_prep = ata_qc_prep, | 394 | .qc_prep = ata_qc_prep, |
395 | .qc_issue = ata_qc_issue_prot, | 395 | .qc_issue = ata_qc_issue_prot, |
396 | 396 | ||
397 | .data_xfer = ata_pio_data_xfer, | 397 | .data_xfer = ata_data_xfer, |
398 | 398 | ||
399 | .irq_handler = ata_interrupt, | 399 | .irq_handler = ata_interrupt, |
400 | .irq_clear = ata_bmdma_irq_clear, | 400 | .irq_clear = ata_bmdma_irq_clear, |
@@ -426,7 +426,7 @@ static struct ata_port_operations amd100_port_ops = { | |||
426 | .qc_prep = ata_qc_prep, | 426 | .qc_prep = ata_qc_prep, |
427 | .qc_issue = ata_qc_issue_prot, | 427 | .qc_issue = ata_qc_issue_prot, |
428 | 428 | ||
429 | .data_xfer = ata_pio_data_xfer, | 429 | .data_xfer = ata_data_xfer, |
430 | 430 | ||
431 | .irq_handler = ata_interrupt, | 431 | .irq_handler = ata_interrupt, |
432 | .irq_clear = ata_bmdma_irq_clear, | 432 | .irq_clear = ata_bmdma_irq_clear, |
@@ -458,7 +458,7 @@ static struct ata_port_operations amd133_port_ops = { | |||
458 | .qc_prep = ata_qc_prep, | 458 | .qc_prep = ata_qc_prep, |
459 | .qc_issue = ata_qc_issue_prot, | 459 | .qc_issue = ata_qc_issue_prot, |
460 | 460 | ||
461 | .data_xfer = ata_pio_data_xfer, | 461 | .data_xfer = ata_data_xfer, |
462 | 462 | ||
463 | .irq_handler = ata_interrupt, | 463 | .irq_handler = ata_interrupt, |
464 | .irq_clear = ata_bmdma_irq_clear, | 464 | .irq_clear = ata_bmdma_irq_clear, |
@@ -490,7 +490,7 @@ static struct ata_port_operations nv100_port_ops = { | |||
490 | .qc_prep = ata_qc_prep, | 490 | .qc_prep = ata_qc_prep, |
491 | .qc_issue = ata_qc_issue_prot, | 491 | .qc_issue = ata_qc_issue_prot, |
492 | 492 | ||
493 | .data_xfer = ata_pio_data_xfer, | 493 | .data_xfer = ata_data_xfer, |
494 | 494 | ||
495 | .irq_handler = ata_interrupt, | 495 | .irq_handler = ata_interrupt, |
496 | .irq_clear = ata_bmdma_irq_clear, | 496 | .irq_clear = ata_bmdma_irq_clear, |
@@ -522,7 +522,7 @@ static struct ata_port_operations nv133_port_ops = { | |||
522 | .qc_prep = ata_qc_prep, | 522 | .qc_prep = ata_qc_prep, |
523 | .qc_issue = ata_qc_issue_prot, | 523 | .qc_issue = ata_qc_issue_prot, |
524 | 524 | ||
525 | .data_xfer = ata_pio_data_xfer, | 525 | .data_xfer = ata_data_xfer, |
526 | 526 | ||
527 | .irq_handler = ata_interrupt, | 527 | .irq_handler = ata_interrupt, |
528 | .irq_clear = ata_bmdma_irq_clear, | 528 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_artop.c b/drivers/ata/pata_artop.c index 5baea1222227..ace5a98dd59d 100644 --- a/drivers/ata/pata_artop.c +++ b/drivers/ata/pata_artop.c | |||
@@ -341,7 +341,7 @@ static const struct ata_port_operations artop6210_ops = { | |||
341 | .qc_prep = ata_qc_prep, | 341 | .qc_prep = ata_qc_prep, |
342 | .qc_issue = ata_qc_issue_prot, | 342 | .qc_issue = ata_qc_issue_prot, |
343 | 343 | ||
344 | .data_xfer = ata_pio_data_xfer, | 344 | .data_xfer = ata_data_xfer, |
345 | 345 | ||
346 | .irq_handler = ata_interrupt, | 346 | .irq_handler = ata_interrupt, |
347 | .irq_clear = ata_bmdma_irq_clear, | 347 | .irq_clear = ata_bmdma_irq_clear, |
@@ -371,7 +371,7 @@ static const struct ata_port_operations artop6260_ops = { | |||
371 | .bmdma_status = ata_bmdma_status, | 371 | .bmdma_status = ata_bmdma_status, |
372 | .qc_prep = ata_qc_prep, | 372 | .qc_prep = ata_qc_prep, |
373 | .qc_issue = ata_qc_issue_prot, | 373 | .qc_issue = ata_qc_issue_prot, |
374 | .data_xfer = ata_pio_data_xfer, | 374 | .data_xfer = ata_data_xfer, |
375 | 375 | ||
376 | .irq_handler = ata_interrupt, | 376 | .irq_handler = ata_interrupt, |
377 | .irq_clear = ata_bmdma_irq_clear, | 377 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_atiixp.c b/drivers/ata/pata_atiixp.c index 2bfb99493a72..f89ef7b15999 100644 --- a/drivers/ata/pata_atiixp.c +++ b/drivers/ata/pata_atiixp.c | |||
@@ -252,7 +252,7 @@ static struct ata_port_operations atiixp_port_ops = { | |||
252 | .qc_prep = ata_qc_prep, | 252 | .qc_prep = ata_qc_prep, |
253 | .qc_issue = ata_qc_issue_prot, | 253 | .qc_issue = ata_qc_issue_prot, |
254 | 254 | ||
255 | .data_xfer = ata_pio_data_xfer, | 255 | .data_xfer = ata_data_xfer, |
256 | 256 | ||
257 | .irq_handler = ata_interrupt, | 257 | .irq_handler = ata_interrupt, |
258 | .irq_clear = ata_bmdma_irq_clear, | 258 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_cmd64x.c b/drivers/ata/pata_cmd64x.c index d97aa9bb0500..3a75978c1aee 100644 --- a/drivers/ata/pata_cmd64x.c +++ b/drivers/ata/pata_cmd64x.c | |||
@@ -313,7 +313,7 @@ static struct ata_port_operations cmd64x_port_ops = { | |||
313 | .qc_prep = ata_qc_prep, | 313 | .qc_prep = ata_qc_prep, |
314 | .qc_issue = ata_qc_issue_prot, | 314 | .qc_issue = ata_qc_issue_prot, |
315 | 315 | ||
316 | .data_xfer = ata_pio_data_xfer, | 316 | .data_xfer = ata_data_xfer, |
317 | 317 | ||
318 | .irq_handler = ata_interrupt, | 318 | .irq_handler = ata_interrupt, |
319 | .irq_clear = ata_bmdma_irq_clear, | 319 | .irq_clear = ata_bmdma_irq_clear, |
@@ -345,7 +345,7 @@ static struct ata_port_operations cmd646r1_port_ops = { | |||
345 | .qc_prep = ata_qc_prep, | 345 | .qc_prep = ata_qc_prep, |
346 | .qc_issue = ata_qc_issue_prot, | 346 | .qc_issue = ata_qc_issue_prot, |
347 | 347 | ||
348 | .data_xfer = ata_pio_data_xfer, | 348 | .data_xfer = ata_data_xfer, |
349 | 349 | ||
350 | .irq_handler = ata_interrupt, | 350 | .irq_handler = ata_interrupt, |
351 | .irq_clear = ata_bmdma_irq_clear, | 351 | .irq_clear = ata_bmdma_irq_clear, |
@@ -377,7 +377,7 @@ static struct ata_port_operations cmd648_port_ops = { | |||
377 | .qc_prep = ata_qc_prep, | 377 | .qc_prep = ata_qc_prep, |
378 | .qc_issue = ata_qc_issue_prot, | 378 | .qc_issue = ata_qc_issue_prot, |
379 | 379 | ||
380 | .data_xfer = ata_pio_data_xfer, | 380 | .data_xfer = ata_data_xfer, |
381 | 381 | ||
382 | .irq_handler = ata_interrupt, | 382 | .irq_handler = ata_interrupt, |
383 | .irq_clear = ata_bmdma_irq_clear, | 383 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_cs5520.c b/drivers/ata/pata_cs5520.c index 63bdcbe45583..801a00efa3ee 100644 --- a/drivers/ata/pata_cs5520.c +++ b/drivers/ata/pata_cs5520.c | |||
@@ -99,9 +99,9 @@ static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int | |||
99 | static void cs5520_enable_dma(struct ata_port *ap, struct ata_device *adev) | 99 | static void cs5520_enable_dma(struct ata_port *ap, struct ata_device *adev) |
100 | { | 100 | { |
101 | /* Set the DMA enable/disable flag */ | 101 | /* Set the DMA enable/disable flag */ |
102 | u8 reg = inb(ap->ioaddr.bmdma_addr + 0x02); | 102 | u8 reg = ioread8(ap->ioaddr.bmdma_addr + 0x02); |
103 | reg |= 1<<(adev->devno + 5); | 103 | reg |= 1<<(adev->devno + 5); |
104 | outb(reg, ap->ioaddr.bmdma_addr + 0x02); | 104 | iowrite8(reg, ap->ioaddr.bmdma_addr + 0x02); |
105 | } | 105 | } |
106 | 106 | ||
107 | /** | 107 | /** |
@@ -193,7 +193,7 @@ static struct ata_port_operations cs5520_port_ops = { | |||
193 | .bmdma_status = ata_bmdma_status, | 193 | .bmdma_status = ata_bmdma_status, |
194 | .qc_prep = ata_qc_prep, | 194 | .qc_prep = ata_qc_prep, |
195 | .qc_issue = ata_qc_issue_prot, | 195 | .qc_issue = ata_qc_issue_prot, |
196 | .data_xfer = ata_pio_data_xfer, | 196 | .data_xfer = ata_data_xfer, |
197 | 197 | ||
198 | .irq_handler = ata_interrupt, | 198 | .irq_handler = ata_interrupt, |
199 | .irq_clear = ata_bmdma_irq_clear, | 199 | .irq_clear = ata_bmdma_irq_clear, |
@@ -204,6 +204,7 @@ static struct ata_port_operations cs5520_port_ops = { | |||
204 | static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id) | 204 | static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
205 | { | 205 | { |
206 | u8 pcicfg; | 206 | u8 pcicfg; |
207 | void *iomap[5]; | ||
207 | static struct ata_probe_ent probe[2]; | 208 | static struct ata_probe_ent probe[2]; |
208 | int ports = 0; | 209 | int ports = 0; |
209 | 210 | ||
@@ -234,6 +235,16 @@ static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_devic | |||
234 | return -ENODEV; | 235 | return -ENODEV; |
235 | } | 236 | } |
236 | 237 | ||
238 | /* Map IO ports */ | ||
239 | iomap[0] = devm_ioport_map(&dev->dev, 0x1F0, 8); | ||
240 | iomap[1] = devm_ioport_map(&dev->dev, 0x3F6, 1); | ||
241 | iomap[2] = devm_ioport_map(&dev->dev, 0x170, 8); | ||
242 | iomap[3] = devm_ioport_map(&dev->dev, 0x376, 1); | ||
243 | iomap[4] = pcim_iomap(dev, 2, 0); | ||
244 | |||
245 | if (!iomap[0] || !iomap[1] || !iomap[2] || !iomap[3] || !iomap[4]) | ||
246 | return -ENOMEM; | ||
247 | |||
237 | /* We have to do our own plumbing as the PCI setup for this | 248 | /* We have to do our own plumbing as the PCI setup for this |
238 | chipset is non-standard so we can't punt to the libata code */ | 249 | chipset is non-standard so we can't punt to the libata code */ |
239 | 250 | ||
@@ -247,10 +258,10 @@ static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_devic | |||
247 | probe[0].irq_flags = 0; | 258 | probe[0].irq_flags = 0; |
248 | probe[0].port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST; | 259 | probe[0].port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST; |
249 | probe[0].n_ports = 1; | 260 | probe[0].n_ports = 1; |
250 | probe[0].port[0].cmd_addr = 0x1F0; | 261 | probe[0].port[0].cmd_addr = iomap[0]; |
251 | probe[0].port[0].ctl_addr = 0x3F6; | 262 | probe[0].port[0].ctl_addr = iomap[1]; |
252 | probe[0].port[0].altstatus_addr = 0x3F6; | 263 | probe[0].port[0].altstatus_addr = iomap[1]; |
253 | probe[0].port[0].bmdma_addr = pci_resource_start(dev, 2); | 264 | probe[0].port[0].bmdma_addr = iomap[4]; |
254 | 265 | ||
255 | /* The secondary lurks at different addresses but is otherwise | 266 | /* The secondary lurks at different addresses but is otherwise |
256 | the same beastie */ | 267 | the same beastie */ |
@@ -258,10 +269,10 @@ static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_devic | |||
258 | probe[1] = probe[0]; | 269 | probe[1] = probe[0]; |
259 | INIT_LIST_HEAD(&probe[1].node); | 270 | INIT_LIST_HEAD(&probe[1].node); |
260 | probe[1].irq = 15; | 271 | probe[1].irq = 15; |
261 | probe[1].port[0].cmd_addr = 0x170; | 272 | probe[1].port[0].cmd_addr = iomap[2]; |
262 | probe[1].port[0].ctl_addr = 0x376; | 273 | probe[1].port[0].ctl_addr = iomap[3]; |
263 | probe[1].port[0].altstatus_addr = 0x376; | 274 | probe[1].port[0].altstatus_addr = iomap[3]; |
264 | probe[1].port[0].bmdma_addr = pci_resource_start(dev, 2) + 8; | 275 | probe[1].port[0].bmdma_addr = iomap[4] + 8; |
265 | 276 | ||
266 | /* Let libata fill in the port details */ | 277 | /* Let libata fill in the port details */ |
267 | ata_std_ports(&probe[0].port[0]); | 278 | ata_std_ports(&probe[0].port[0]); |
diff --git a/drivers/ata/pata_cs5530.c b/drivers/ata/pata_cs5530.c index 29d459be19be..b9fd5388b476 100644 --- a/drivers/ata/pata_cs5530.c +++ b/drivers/ata/pata_cs5530.c | |||
@@ -37,6 +37,13 @@ | |||
37 | #define DRV_NAME "pata_cs5530" | 37 | #define DRV_NAME "pata_cs5530" |
38 | #define DRV_VERSION "0.7.1" | 38 | #define DRV_VERSION "0.7.1" |
39 | 39 | ||
40 | static void __iomem *cs5530_port_base(struct ata_port *ap) | ||
41 | { | ||
42 | unsigned long bmdma = (unsigned long)ap->ioaddr.bmdma_addr; | ||
43 | |||
44 | return (void __iomem *)((bmdma & ~0x0F) + 0x20 + 0x10 * ap->port_no); | ||
45 | } | ||
46 | |||
40 | /** | 47 | /** |
41 | * cs5530_set_piomode - PIO setup | 48 | * cs5530_set_piomode - PIO setup |
42 | * @ap: ATA interface | 49 | * @ap: ATA interface |
@@ -52,19 +59,19 @@ static void cs5530_set_piomode(struct ata_port *ap, struct ata_device *adev) | |||
52 | {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, | 59 | {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, |
53 | {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010} | 60 | {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010} |
54 | }; | 61 | }; |
55 | unsigned long base = ( ap->ioaddr.bmdma_addr & ~0x0F) + 0x20 + 0x10 * ap->port_no; | 62 | void __iomem *base = cs5530_port_base(ap); |
56 | u32 tuning; | 63 | u32 tuning; |
57 | int format; | 64 | int format; |
58 | 65 | ||
59 | /* Find out which table to use */ | 66 | /* Find out which table to use */ |
60 | tuning = inl(base + 0x04); | 67 | tuning = ioread32(base + 0x04); |
61 | format = (tuning & 0x80000000UL) ? 1 : 0; | 68 | format = (tuning & 0x80000000UL) ? 1 : 0; |
62 | 69 | ||
63 | /* Now load the right timing register */ | 70 | /* Now load the right timing register */ |
64 | if (adev->devno) | 71 | if (adev->devno) |
65 | base += 0x08; | 72 | base += 0x08; |
66 | 73 | ||
67 | outl(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base); | 74 | iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base); |
68 | } | 75 | } |
69 | 76 | ||
70 | /** | 77 | /** |
@@ -79,12 +86,12 @@ static void cs5530_set_piomode(struct ata_port *ap, struct ata_device *adev) | |||
79 | 86 | ||
80 | static void cs5530_set_dmamode(struct ata_port *ap, struct ata_device *adev) | 87 | static void cs5530_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
81 | { | 88 | { |
82 | unsigned long base = ( ap->ioaddr.bmdma_addr & ~0x0F) + 0x20 + 0x10 * ap->port_no; | 89 | void __iomem *base = cs5530_port_base(ap); |
83 | u32 tuning, timing = 0; | 90 | u32 tuning, timing = 0; |
84 | u8 reg; | 91 | u8 reg; |
85 | 92 | ||
86 | /* Find out which table to use */ | 93 | /* Find out which table to use */ |
87 | tuning = inl(base + 0x04); | 94 | tuning = ioread32(base + 0x04); |
88 | 95 | ||
89 | switch(adev->dma_mode) { | 96 | switch(adev->dma_mode) { |
90 | case XFER_UDMA_0: | 97 | case XFER_UDMA_0: |
@@ -105,20 +112,20 @@ static void cs5530_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |||
105 | /* Merge in the PIO format bit */ | 112 | /* Merge in the PIO format bit */ |
106 | timing |= (tuning & 0x80000000UL); | 113 | timing |= (tuning & 0x80000000UL); |
107 | if (adev->devno == 0) /* Master */ | 114 | if (adev->devno == 0) /* Master */ |
108 | outl(timing, base + 0x04); | 115 | iowrite32(timing, base + 0x04); |
109 | else { | 116 | else { |
110 | if (timing & 0x00100000) | 117 | if (timing & 0x00100000) |
111 | tuning |= 0x00100000; /* UDMA for both */ | 118 | tuning |= 0x00100000; /* UDMA for both */ |
112 | else | 119 | else |
113 | tuning &= ~0x00100000; /* MWDMA for both */ | 120 | tuning &= ~0x00100000; /* MWDMA for both */ |
114 | outl(tuning, base + 0x04); | 121 | iowrite32(tuning, base + 0x04); |
115 | outl(timing, base + 0x0C); | 122 | iowrite32(timing, base + 0x0C); |
116 | } | 123 | } |
117 | 124 | ||
118 | /* Set the DMA capable bit in the BMDMA area */ | 125 | /* Set the DMA capable bit in the BMDMA area */ |
119 | reg = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | 126 | reg = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); |
120 | reg |= (1 << (5 + adev->devno)); | 127 | reg |= (1 << (5 + adev->devno)); |
121 | outb(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | 128 | iowrite8(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); |
122 | 129 | ||
123 | /* Remember the last DMA setup we did */ | 130 | /* Remember the last DMA setup we did */ |
124 | 131 | ||
@@ -210,7 +217,7 @@ static struct ata_port_operations cs5530_port_ops = { | |||
210 | .qc_prep = ata_qc_prep, | 217 | .qc_prep = ata_qc_prep, |
211 | .qc_issue = cs5530_qc_issue_prot, | 218 | .qc_issue = cs5530_qc_issue_prot, |
212 | 219 | ||
213 | .data_xfer = ata_pio_data_xfer, | 220 | .data_xfer = ata_data_xfer, |
214 | 221 | ||
215 | .irq_handler = ata_interrupt, | 222 | .irq_handler = ata_interrupt, |
216 | .irq_clear = ata_bmdma_irq_clear, | 223 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_cs5535.c b/drivers/ata/pata_cs5535.c index dd3958d2cff9..500f863cb987 100644 --- a/drivers/ata/pata_cs5535.c +++ b/drivers/ata/pata_cs5535.c | |||
@@ -214,7 +214,7 @@ static struct ata_port_operations cs5535_port_ops = { | |||
214 | .qc_prep = ata_qc_prep, | 214 | .qc_prep = ata_qc_prep, |
215 | .qc_issue = ata_qc_issue_prot, | 215 | .qc_issue = ata_qc_issue_prot, |
216 | 216 | ||
217 | .data_xfer = ata_pio_data_xfer, | 217 | .data_xfer = ata_data_xfer, |
218 | 218 | ||
219 | .irq_handler = ata_interrupt, | 219 | .irq_handler = ata_interrupt, |
220 | .irq_clear = ata_bmdma_irq_clear, | 220 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_cypress.c b/drivers/ata/pata_cypress.c index 8479186a2373..4ca103d668ed 100644 --- a/drivers/ata/pata_cypress.c +++ b/drivers/ata/pata_cypress.c | |||
@@ -165,7 +165,7 @@ static struct ata_port_operations cy82c693_port_ops = { | |||
165 | .qc_prep = ata_qc_prep, | 165 | .qc_prep = ata_qc_prep, |
166 | .qc_issue = ata_qc_issue_prot, | 166 | .qc_issue = ata_qc_issue_prot, |
167 | 167 | ||
168 | .data_xfer = ata_pio_data_xfer, | 168 | .data_xfer = ata_data_xfer, |
169 | 169 | ||
170 | .irq_handler = ata_interrupt, | 170 | .irq_handler = ata_interrupt, |
171 | .irq_clear = ata_bmdma_irq_clear, | 171 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_efar.c b/drivers/ata/pata_efar.c index 66814ee64d05..a112dac98dd9 100644 --- a/drivers/ata/pata_efar.c +++ b/drivers/ata/pata_efar.c | |||
@@ -261,7 +261,7 @@ static const struct ata_port_operations efar_ops = { | |||
261 | .bmdma_status = ata_bmdma_status, | 261 | .bmdma_status = ata_bmdma_status, |
262 | .qc_prep = ata_qc_prep, | 262 | .qc_prep = ata_qc_prep, |
263 | .qc_issue = ata_qc_issue_prot, | 263 | .qc_issue = ata_qc_issue_prot, |
264 | .data_xfer = ata_pio_data_xfer, | 264 | .data_xfer = ata_data_xfer, |
265 | 265 | ||
266 | .irq_handler = ata_interrupt, | 266 | .irq_handler = ata_interrupt, |
267 | .irq_clear = ata_bmdma_irq_clear, | 267 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_hpt366.c b/drivers/ata/pata_hpt366.c index 8b826102dbd9..819d7a392781 100644 --- a/drivers/ata/pata_hpt366.c +++ b/drivers/ata/pata_hpt366.c | |||
@@ -361,7 +361,7 @@ static struct ata_port_operations hpt366_port_ops = { | |||
361 | .qc_prep = ata_qc_prep, | 361 | .qc_prep = ata_qc_prep, |
362 | .qc_issue = ata_qc_issue_prot, | 362 | .qc_issue = ata_qc_issue_prot, |
363 | 363 | ||
364 | .data_xfer = ata_pio_data_xfer, | 364 | .data_xfer = ata_data_xfer, |
365 | 365 | ||
366 | .irq_handler = ata_interrupt, | 366 | .irq_handler = ata_interrupt, |
367 | .irq_clear = ata_bmdma_irq_clear, | 367 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_hpt37x.c b/drivers/ata/pata_hpt37x.c index 09e8be56ba36..c6d8774df0de 100644 --- a/drivers/ata/pata_hpt37x.c +++ b/drivers/ata/pata_hpt37x.c | |||
@@ -634,24 +634,24 @@ static void hpt370_bmdma_stop(struct ata_queued_cmd *qc) | |||
634 | { | 634 | { |
635 | struct ata_port *ap = qc->ap; | 635 | struct ata_port *ap = qc->ap; |
636 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | 636 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
637 | u8 dma_stat = inb(ap->ioaddr.bmdma_addr + 2); | 637 | u8 dma_stat = ioread8(ap->ioaddr.bmdma_addr + 2); |
638 | u8 dma_cmd; | 638 | u8 dma_cmd; |
639 | unsigned long bmdma = ap->ioaddr.bmdma_addr; | 639 | void __iomem *bmdma = ap->ioaddr.bmdma_addr; |
640 | 640 | ||
641 | if (dma_stat & 0x01) { | 641 | if (dma_stat & 0x01) { |
642 | udelay(20); | 642 | udelay(20); |
643 | dma_stat = inb(bmdma + 2); | 643 | dma_stat = ioread8(bmdma + 2); |
644 | } | 644 | } |
645 | if (dma_stat & 0x01) { | 645 | if (dma_stat & 0x01) { |
646 | /* Clear the engine */ | 646 | /* Clear the engine */ |
647 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | 647 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
648 | udelay(10); | 648 | udelay(10); |
649 | /* Stop DMA */ | 649 | /* Stop DMA */ |
650 | dma_cmd = inb(bmdma ); | 650 | dma_cmd = ioread8(bmdma ); |
651 | outb(dma_cmd & 0xFE, bmdma); | 651 | iowrite8(dma_cmd & 0xFE, bmdma); |
652 | /* Clear Error */ | 652 | /* Clear Error */ |
653 | dma_stat = inb(bmdma + 2); | 653 | dma_stat = ioread8(bmdma + 2); |
654 | outb(dma_stat | 0x06 , bmdma + 2); | 654 | iowrite8(dma_stat | 0x06 , bmdma + 2); |
655 | /* Clear the engine */ | 655 | /* Clear the engine */ |
656 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | 656 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
657 | udelay(10); | 657 | udelay(10); |
@@ -796,7 +796,7 @@ static struct ata_port_operations hpt370_port_ops = { | |||
796 | .qc_prep = ata_qc_prep, | 796 | .qc_prep = ata_qc_prep, |
797 | .qc_issue = ata_qc_issue_prot, | 797 | .qc_issue = ata_qc_issue_prot, |
798 | 798 | ||
799 | .data_xfer = ata_pio_data_xfer, | 799 | .data_xfer = ata_data_xfer, |
800 | 800 | ||
801 | .irq_handler = ata_interrupt, | 801 | .irq_handler = ata_interrupt, |
802 | .irq_clear = ata_bmdma_irq_clear, | 802 | .irq_clear = ata_bmdma_irq_clear, |
@@ -833,7 +833,7 @@ static struct ata_port_operations hpt370a_port_ops = { | |||
833 | .qc_prep = ata_qc_prep, | 833 | .qc_prep = ata_qc_prep, |
834 | .qc_issue = ata_qc_issue_prot, | 834 | .qc_issue = ata_qc_issue_prot, |
835 | 835 | ||
836 | .data_xfer = ata_pio_data_xfer, | 836 | .data_xfer = ata_data_xfer, |
837 | 837 | ||
838 | .irq_handler = ata_interrupt, | 838 | .irq_handler = ata_interrupt, |
839 | .irq_clear = ata_bmdma_irq_clear, | 839 | .irq_clear = ata_bmdma_irq_clear, |
@@ -871,7 +871,7 @@ static struct ata_port_operations hpt372_port_ops = { | |||
871 | .qc_prep = ata_qc_prep, | 871 | .qc_prep = ata_qc_prep, |
872 | .qc_issue = ata_qc_issue_prot, | 872 | .qc_issue = ata_qc_issue_prot, |
873 | 873 | ||
874 | .data_xfer = ata_pio_data_xfer, | 874 | .data_xfer = ata_data_xfer, |
875 | 875 | ||
876 | .irq_handler = ata_interrupt, | 876 | .irq_handler = ata_interrupt, |
877 | .irq_clear = ata_bmdma_irq_clear, | 877 | .irq_clear = ata_bmdma_irq_clear, |
@@ -909,7 +909,7 @@ static struct ata_port_operations hpt374_port_ops = { | |||
909 | .qc_prep = ata_qc_prep, | 909 | .qc_prep = ata_qc_prep, |
910 | .qc_issue = ata_qc_issue_prot, | 910 | .qc_issue = ata_qc_issue_prot, |
911 | 911 | ||
912 | .data_xfer = ata_pio_data_xfer, | 912 | .data_xfer = ata_data_xfer, |
913 | 913 | ||
914 | .irq_handler = ata_interrupt, | 914 | .irq_handler = ata_interrupt, |
915 | .irq_clear = ata_bmdma_irq_clear, | 915 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_hpt3x2n.c b/drivers/ata/pata_hpt3x2n.c index 9f8ec576317c..b56dc4a7185b 100644 --- a/drivers/ata/pata_hpt3x2n.c +++ b/drivers/ata/pata_hpt3x2n.c | |||
@@ -263,26 +263,26 @@ static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc) | |||
263 | 263 | ||
264 | static void hpt3x2n_set_clock(struct ata_port *ap, int source) | 264 | static void hpt3x2n_set_clock(struct ata_port *ap, int source) |
265 | { | 265 | { |
266 | unsigned long bmdma = ap->ioaddr.bmdma_addr; | 266 | void __iomem *bmdma = ap->ioaddr.bmdma_addr; |
267 | 267 | ||
268 | /* Tristate the bus */ | 268 | /* Tristate the bus */ |
269 | outb(0x80, bmdma+0x73); | 269 | iowrite8(0x80, bmdma+0x73); |
270 | outb(0x80, bmdma+0x77); | 270 | iowrite8(0x80, bmdma+0x77); |
271 | 271 | ||
272 | /* Switch clock and reset channels */ | 272 | /* Switch clock and reset channels */ |
273 | outb(source, bmdma+0x7B); | 273 | iowrite8(source, bmdma+0x7B); |
274 | outb(0xC0, bmdma+0x79); | 274 | iowrite8(0xC0, bmdma+0x79); |
275 | 275 | ||
276 | /* Reset state machines */ | 276 | /* Reset state machines */ |
277 | outb(0x37, bmdma+0x70); | 277 | iowrite8(0x37, bmdma+0x70); |
278 | outb(0x37, bmdma+0x74); | 278 | iowrite8(0x37, bmdma+0x74); |
279 | 279 | ||
280 | /* Complete reset */ | 280 | /* Complete reset */ |
281 | outb(0x00, bmdma+0x79); | 281 | iowrite8(0x00, bmdma+0x79); |
282 | 282 | ||
283 | /* Reconnect channels to bus */ | 283 | /* Reconnect channels to bus */ |
284 | outb(0x00, bmdma+0x73); | 284 | iowrite8(0x00, bmdma+0x73); |
285 | outb(0x00, bmdma+0x77); | 285 | iowrite8(0x00, bmdma+0x77); |
286 | } | 286 | } |
287 | 287 | ||
288 | /* Check if our partner interface is busy */ | 288 | /* Check if our partner interface is busy */ |
@@ -373,7 +373,7 @@ static struct ata_port_operations hpt3x2n_port_ops = { | |||
373 | .qc_prep = ata_qc_prep, | 373 | .qc_prep = ata_qc_prep, |
374 | .qc_issue = hpt3x2n_qc_issue_prot, | 374 | .qc_issue = hpt3x2n_qc_issue_prot, |
375 | 375 | ||
376 | .data_xfer = ata_pio_data_xfer, | 376 | .data_xfer = ata_data_xfer, |
377 | 377 | ||
378 | .irq_handler = ata_interrupt, | 378 | .irq_handler = ata_interrupt, |
379 | .irq_clear = ata_bmdma_irq_clear, | 379 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_hpt3x3.c b/drivers/ata/pata_hpt3x3.c index faa2db44ba7f..46fc417856cc 100644 --- a/drivers/ata/pata_hpt3x3.c +++ b/drivers/ata/pata_hpt3x3.c | |||
@@ -148,7 +148,7 @@ static struct ata_port_operations hpt3x3_port_ops = { | |||
148 | .qc_prep = ata_qc_prep, | 148 | .qc_prep = ata_qc_prep, |
149 | .qc_issue = ata_qc_issue_prot, | 149 | .qc_issue = ata_qc_issue_prot, |
150 | 150 | ||
151 | .data_xfer = ata_pio_data_xfer, | 151 | .data_xfer = ata_data_xfer, |
152 | 152 | ||
153 | .irq_handler = ata_interrupt, | 153 | .irq_handler = ata_interrupt, |
154 | .irq_clear = ata_bmdma_irq_clear, | 154 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_isapnp.c b/drivers/ata/pata_isapnp.c index 38a42eae598e..4d9ab268cf28 100644 --- a/drivers/ata/pata_isapnp.c +++ b/drivers/ata/pata_isapnp.c | |||
@@ -53,7 +53,7 @@ static struct ata_port_operations isapnp_port_ops = { | |||
53 | .qc_prep = ata_qc_prep, | 53 | .qc_prep = ata_qc_prep, |
54 | .qc_issue = ata_qc_issue_prot, | 54 | .qc_issue = ata_qc_issue_prot, |
55 | 55 | ||
56 | .data_xfer = ata_pio_data_xfer, | 56 | .data_xfer = ata_data_xfer, |
57 | 57 | ||
58 | .irq_handler = ata_interrupt, | 58 | .irq_handler = ata_interrupt, |
59 | .irq_clear = ata_bmdma_irq_clear, | 59 | .irq_clear = ata_bmdma_irq_clear, |
@@ -73,6 +73,7 @@ static struct ata_port_operations isapnp_port_ops = { | |||
73 | static int isapnp_init_one(struct pnp_dev *idev, const struct pnp_device_id *dev_id) | 73 | static int isapnp_init_one(struct pnp_dev *idev, const struct pnp_device_id *dev_id) |
74 | { | 74 | { |
75 | struct ata_probe_ent ae; | 75 | struct ata_probe_ent ae; |
76 | void __iomem *cmd_addr, *ctl_addr; | ||
76 | 77 | ||
77 | if (pnp_port_valid(idev, 0) == 0) | 78 | if (pnp_port_valid(idev, 0) == 0) |
78 | return -ENODEV; | 79 | return -ENODEV; |
@@ -81,6 +82,10 @@ static int isapnp_init_one(struct pnp_dev *idev, const struct pnp_device_id *dev | |||
81 | if (pnp_irq_valid(idev, 0) == 0) | 82 | if (pnp_irq_valid(idev, 0) == 0) |
82 | return -ENODEV; | 83 | return -ENODEV; |
83 | 84 | ||
85 | cmd_addr = devm_ioport_map(&idev->dev, pnp_port_start(idev, 0), 8); | ||
86 | if (!cmd_addr) | ||
87 | return -ENOMEM; | ||
88 | |||
84 | memset(&ae, 0, sizeof(struct ata_probe_ent)); | 89 | memset(&ae, 0, sizeof(struct ata_probe_ent)); |
85 | INIT_LIST_HEAD(&ae.node); | 90 | INIT_LIST_HEAD(&ae.node); |
86 | ae.dev = &idev->dev; | 91 | ae.dev = &idev->dev; |
@@ -91,11 +96,13 @@ static int isapnp_init_one(struct pnp_dev *idev, const struct pnp_device_id *dev | |||
91 | ae.irq = pnp_irq(idev, 0); | 96 | ae.irq = pnp_irq(idev, 0); |
92 | ae.irq_flags = 0; | 97 | ae.irq_flags = 0; |
93 | ae.port_flags = ATA_FLAG_SLAVE_POSS; | 98 | ae.port_flags = ATA_FLAG_SLAVE_POSS; |
94 | ae.port[0].cmd_addr = pnp_port_start(idev, 0); | 99 | ae.port[0].cmd_addr = cmd_addr; |
95 | 100 | ||
96 | if (pnp_port_valid(idev, 1) == 0) { | 101 | if (pnp_port_valid(idev, 1) == 0) { |
97 | ae.port[0].altstatus_addr = pnp_port_start(idev, 1); | 102 | ctl_addr = devm_ioport_map(&idev->dev, |
98 | ae.port[0].ctl_addr = pnp_port_start(idev, 1); | 103 | pnp_port_start(idev, 1), 1); |
104 | ae.port[0].altstatus_addr = ctl_addr; | ||
105 | ae.port[0].ctl_addr = ctl_addr; | ||
99 | ae.port_flags |= ATA_FLAG_SRST; | 106 | ae.port_flags |= ATA_FLAG_SRST; |
100 | } | 107 | } |
101 | ata_std_ports(&ae.port[0]); | 108 | ata_std_ports(&ae.port[0]); |
diff --git a/drivers/ata/pata_it8213.c b/drivers/ata/pata_it8213.c index 383a611b662e..ec128316903d 100644 --- a/drivers/ata/pata_it8213.c +++ b/drivers/ata/pata_it8213.c | |||
@@ -273,7 +273,7 @@ static const struct ata_port_operations it8213_ops = { | |||
273 | .bmdma_status = ata_bmdma_status, | 273 | .bmdma_status = ata_bmdma_status, |
274 | .qc_prep = ata_qc_prep, | 274 | .qc_prep = ata_qc_prep, |
275 | .qc_issue = ata_qc_issue_prot, | 275 | .qc_issue = ata_qc_issue_prot, |
276 | .data_xfer = ata_pio_data_xfer, | 276 | .data_xfer = ata_data_xfer, |
277 | 277 | ||
278 | .irq_handler = ata_interrupt, | 278 | .irq_handler = ata_interrupt, |
279 | .irq_clear = ata_bmdma_irq_clear, | 279 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_it821x.c b/drivers/ata/pata_it821x.c index f23365b92c0f..e8a6e7d73b72 100644 --- a/drivers/ata/pata_it821x.c +++ b/drivers/ata/pata_it821x.c | |||
@@ -492,7 +492,7 @@ static int it821x_smart_set_mode(struct ata_port *ap, struct ata_device **unused | |||
492 | /* Bits 5 and 6 indicate if DMA is active on master/slave */ | 492 | /* Bits 5 and 6 indicate if DMA is active on master/slave */ |
493 | /* It is possible that BMDMA isn't allocated */ | 493 | /* It is possible that BMDMA isn't allocated */ |
494 | if (ap->ioaddr.bmdma_addr) | 494 | if (ap->ioaddr.bmdma_addr) |
495 | dma_enabled = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | 495 | dma_enabled = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
496 | 496 | ||
497 | for (i = 0; i < ATA_MAX_DEVICES; i++) { | 497 | for (i = 0; i < ATA_MAX_DEVICES; i++) { |
498 | struct ata_device *dev = &ap->device[i]; | 498 | struct ata_device *dev = &ap->device[i]; |
@@ -674,7 +674,7 @@ static struct ata_port_operations it821x_smart_port_ops = { | |||
674 | .qc_prep = ata_qc_prep, | 674 | .qc_prep = ata_qc_prep, |
675 | .qc_issue = it821x_smart_qc_issue_prot, | 675 | .qc_issue = it821x_smart_qc_issue_prot, |
676 | 676 | ||
677 | .data_xfer = ata_pio_data_xfer, | 677 | .data_xfer = ata_data_xfer, |
678 | 678 | ||
679 | .irq_handler = ata_interrupt, | 679 | .irq_handler = ata_interrupt, |
680 | .irq_clear = ata_bmdma_irq_clear, | 680 | .irq_clear = ata_bmdma_irq_clear, |
@@ -708,7 +708,7 @@ static struct ata_port_operations it821x_passthru_port_ops = { | |||
708 | .qc_prep = ata_qc_prep, | 708 | .qc_prep = ata_qc_prep, |
709 | .qc_issue = it821x_passthru_qc_issue_prot, | 709 | .qc_issue = it821x_passthru_qc_issue_prot, |
710 | 710 | ||
711 | .data_xfer = ata_pio_data_xfer, | 711 | .data_xfer = ata_data_xfer, |
712 | 712 | ||
713 | .irq_clear = ata_bmdma_irq_clear, | 713 | .irq_clear = ata_bmdma_irq_clear, |
714 | .irq_handler = ata_interrupt, | 714 | .irq_handler = ata_interrupt, |
diff --git a/drivers/ata/pata_ixp4xx_cf.c b/drivers/ata/pata_ixp4xx_cf.c index 230067d281e3..d9ee1837b7ff 100644 --- a/drivers/ata/pata_ixp4xx_cf.c +++ b/drivers/ata/pata_ixp4xx_cf.c | |||
@@ -140,9 +140,9 @@ static struct ata_port_operations ixp4xx_port_ops = { | |||
140 | static void ixp4xx_setup_port(struct ata_ioports *ioaddr, | 140 | static void ixp4xx_setup_port(struct ata_ioports *ioaddr, |
141 | struct ixp4xx_pata_data *data) | 141 | struct ixp4xx_pata_data *data) |
142 | { | 142 | { |
143 | ioaddr->cmd_addr = (unsigned long) data->cs0; | 143 | ioaddr->cmd_addr = data->cs0; |
144 | ioaddr->altstatus_addr = (unsigned long) data->cs1 + 0x06; | 144 | ioaddr->altstatus_addr = data->cs1 + 0x06; |
145 | ioaddr->ctl_addr = (unsigned long) data->cs1 + 0x06; | 145 | ioaddr->ctl_addr = data->cs1 + 0x06; |
146 | 146 | ||
147 | ata_std_ports(ioaddr); | 147 | ata_std_ports(ioaddr); |
148 | 148 | ||
@@ -152,19 +152,19 @@ static void ixp4xx_setup_port(struct ata_ioports *ioaddr, | |||
152 | * ixp4xx in little endian mode. | 152 | * ixp4xx in little endian mode. |
153 | */ | 153 | */ |
154 | 154 | ||
155 | ioaddr->data_addr ^= 0x02; | 155 | *(unsigned long *)&ioaddr->data_addr ^= 0x02; |
156 | ioaddr->cmd_addr ^= 0x03; | 156 | *(unsigned long *)&ioaddr->cmd_addr ^= 0x03; |
157 | ioaddr->altstatus_addr ^= 0x03; | 157 | *(unsigned long *)&ioaddr->altstatus_addr ^= 0x03; |
158 | ioaddr->ctl_addr ^= 0x03; | 158 | *(unsigned long *)&ioaddr->ctl_addr ^= 0x03; |
159 | ioaddr->error_addr ^= 0x03; | 159 | *(unsigned long *)&ioaddr->error_addr ^= 0x03; |
160 | ioaddr->feature_addr ^= 0x03; | 160 | *(unsigned long *)&ioaddr->feature_addr ^= 0x03; |
161 | ioaddr->nsect_addr ^= 0x03; | 161 | *(unsigned long *)&ioaddr->nsect_addr ^= 0x03; |
162 | ioaddr->lbal_addr ^= 0x03; | 162 | *(unsigned long *)&ioaddr->lbal_addr ^= 0x03; |
163 | ioaddr->lbam_addr ^= 0x03; | 163 | *(unsigned long *)&ioaddr->lbam_addr ^= 0x03; |
164 | ioaddr->lbah_addr ^= 0x03; | 164 | *(unsigned long *)&ioaddr->lbah_addr ^= 0x03; |
165 | ioaddr->device_addr ^= 0x03; | 165 | *(unsigned long *)&ioaddr->device_addr ^= 0x03; |
166 | ioaddr->status_addr ^= 0x03; | 166 | *(unsigned long *)&ioaddr->status_addr ^= 0x03; |
167 | ioaddr->command_addr ^= 0x03; | 167 | *(unsigned long *)&ioaddr->command_addr ^= 0x03; |
168 | #endif | 168 | #endif |
169 | } | 169 | } |
170 | 170 | ||
diff --git a/drivers/ata/pata_jmicron.c b/drivers/ata/pata_jmicron.c index 128a30958210..26365c107818 100644 --- a/drivers/ata/pata_jmicron.c +++ b/drivers/ata/pata_jmicron.c | |||
@@ -161,7 +161,7 @@ static const struct ata_port_operations jmicron_ops = { | |||
161 | .bmdma_status = ata_bmdma_status, | 161 | .bmdma_status = ata_bmdma_status, |
162 | .qc_prep = ata_qc_prep, | 162 | .qc_prep = ata_qc_prep, |
163 | .qc_issue = ata_qc_issue_prot, | 163 | .qc_issue = ata_qc_issue_prot, |
164 | .data_xfer = ata_pio_data_xfer, | 164 | .data_xfer = ata_data_xfer, |
165 | 165 | ||
166 | /* IRQ-related hooks */ | 166 | /* IRQ-related hooks */ |
167 | .irq_handler = ata_interrupt, | 167 | .irq_handler = ata_interrupt, |
diff --git a/drivers/ata/pata_legacy.c b/drivers/ata/pata_legacy.c index 9532b9bb6d2f..78b5f7136e1e 100644 --- a/drivers/ata/pata_legacy.c +++ b/drivers/ata/pata_legacy.c | |||
@@ -164,7 +164,7 @@ static struct ata_port_operations simple_port_ops = { | |||
164 | .qc_prep = ata_qc_prep, | 164 | .qc_prep = ata_qc_prep, |
165 | .qc_issue = ata_qc_issue_prot, | 165 | .qc_issue = ata_qc_issue_prot, |
166 | 166 | ||
167 | .data_xfer = ata_pio_data_xfer_noirq, | 167 | .data_xfer = ata_data_xfer_noirq, |
168 | 168 | ||
169 | .irq_handler = ata_interrupt, | 169 | .irq_handler = ata_interrupt, |
170 | .irq_clear = ata_bmdma_irq_clear, | 170 | .irq_clear = ata_bmdma_irq_clear, |
@@ -187,7 +187,7 @@ static struct ata_port_operations legacy_port_ops = { | |||
187 | .qc_prep = ata_qc_prep, | 187 | .qc_prep = ata_qc_prep, |
188 | .qc_issue = ata_qc_issue_prot, | 188 | .qc_issue = ata_qc_issue_prot, |
189 | 189 | ||
190 | .data_xfer = ata_pio_data_xfer_noirq, | 190 | .data_xfer = ata_data_xfer_noirq, |
191 | 191 | ||
192 | .irq_handler = ata_interrupt, | 192 | .irq_handler = ata_interrupt, |
193 | .irq_clear = ata_bmdma_irq_clear, | 193 | .irq_clear = ata_bmdma_irq_clear, |
@@ -253,31 +253,33 @@ static void pdc_data_xfer_vlb(struct ata_device *adev, unsigned char *buf, unsig | |||
253 | local_irq_save(flags); | 253 | local_irq_save(flags); |
254 | 254 | ||
255 | /* Perform the 32bit I/O synchronization sequence */ | 255 | /* Perform the 32bit I/O synchronization sequence */ |
256 | inb(ap->ioaddr.nsect_addr); | 256 | ioread8(ap->ioaddr.nsect_addr); |
257 | inb(ap->ioaddr.nsect_addr); | 257 | ioread8(ap->ioaddr.nsect_addr); |
258 | inb(ap->ioaddr.nsect_addr); | 258 | ioread8(ap->ioaddr.nsect_addr); |
259 | 259 | ||
260 | /* Now the data */ | 260 | /* Now the data */ |
261 | 261 | ||
262 | if (write_data) | 262 | if (write_data) |
263 | outsl(ap->ioaddr.data_addr, buf, buflen >> 2); | 263 | iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
264 | else | 264 | else |
265 | insl(ap->ioaddr.data_addr, buf, buflen >> 2); | 265 | ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
266 | 266 | ||
267 | if (unlikely(slop)) { | 267 | if (unlikely(slop)) { |
268 | u32 pad; | 268 | u32 pad; |
269 | if (write_data) { | 269 | if (write_data) { |
270 | memcpy(&pad, buf + buflen - slop, slop); | 270 | memcpy(&pad, buf + buflen - slop, slop); |
271 | outl(le32_to_cpu(pad), ap->ioaddr.data_addr); | 271 | pad = le32_to_cpu(pad); |
272 | iowrite32(pad, ap->ioaddr.data_addr); | ||
272 | } else { | 273 | } else { |
273 | pad = cpu_to_le16(inl(ap->ioaddr.data_addr)); | 274 | pad = ioread32(ap->ioaddr.data_addr); |
275 | pad = cpu_to_le16(pad); | ||
274 | memcpy(buf + buflen - slop, &pad, slop); | 276 | memcpy(buf + buflen - slop, &pad, slop); |
275 | } | 277 | } |
276 | } | 278 | } |
277 | local_irq_restore(flags); | 279 | local_irq_restore(flags); |
278 | } | 280 | } |
279 | else | 281 | else |
280 | ata_pio_data_xfer_noirq(adev, buf, buflen, write_data); | 282 | ata_data_xfer_noirq(adev, buf, buflen, write_data); |
281 | } | 283 | } |
282 | 284 | ||
283 | static struct ata_port_operations pdc20230_port_ops = { | 285 | static struct ata_port_operations pdc20230_port_ops = { |
@@ -326,8 +328,8 @@ static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) | |||
326 | inb(0x3E6); | 328 | inb(0x3E6); |
327 | inb(0x3E6); | 329 | inb(0x3E6); |
328 | 330 | ||
329 | outb(recover << 4 | active, ap->ioaddr.device_addr); | 331 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
330 | inb(ap->ioaddr.status_addr); | 332 | ioread8(ap->ioaddr.status_addr); |
331 | } | 333 | } |
332 | 334 | ||
333 | static struct ata_port_operations ht6560a_port_ops = { | 335 | static struct ata_port_operations ht6560a_port_ops = { |
@@ -345,7 +347,7 @@ static struct ata_port_operations ht6560a_port_ops = { | |||
345 | .qc_prep = ata_qc_prep, | 347 | .qc_prep = ata_qc_prep, |
346 | .qc_issue = ata_qc_issue_prot, | 348 | .qc_issue = ata_qc_issue_prot, |
347 | 349 | ||
348 | .data_xfer = ata_pio_data_xfer, /* Check vlb/noirq */ | 350 | .data_xfer = ata_data_xfer, /* Check vlb/noirq */ |
349 | 351 | ||
350 | .irq_handler = ata_interrupt, | 352 | .irq_handler = ata_interrupt, |
351 | .irq_clear = ata_bmdma_irq_clear, | 353 | .irq_clear = ata_bmdma_irq_clear, |
@@ -379,7 +381,7 @@ static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) | |||
379 | inb(0x3E6); | 381 | inb(0x3E6); |
380 | inb(0x3E6); | 382 | inb(0x3E6); |
381 | 383 | ||
382 | outb(recover << 4 | active, ap->ioaddr.device_addr); | 384 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
383 | 385 | ||
384 | if (adev->class != ATA_DEV_ATA) { | 386 | if (adev->class != ATA_DEV_ATA) { |
385 | u8 rconf = inb(0x3E6); | 387 | u8 rconf = inb(0x3E6); |
@@ -388,7 +390,7 @@ static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) | |||
388 | outb(rconf, 0x3E6); | 390 | outb(rconf, 0x3E6); |
389 | } | 391 | } |
390 | } | 392 | } |
391 | inb(ap->ioaddr.status_addr); | 393 | ioread8(ap->ioaddr.status_addr); |
392 | } | 394 | } |
393 | 395 | ||
394 | static struct ata_port_operations ht6560b_port_ops = { | 396 | static struct ata_port_operations ht6560b_port_ops = { |
@@ -406,7 +408,7 @@ static struct ata_port_operations ht6560b_port_ops = { | |||
406 | .qc_prep = ata_qc_prep, | 408 | .qc_prep = ata_qc_prep, |
407 | .qc_issue = ata_qc_issue_prot, | 409 | .qc_issue = ata_qc_issue_prot, |
408 | 410 | ||
409 | .data_xfer = ata_pio_data_xfer, /* FIXME: Check 32bit and noirq */ | 411 | .data_xfer = ata_data_xfer, /* FIXME: Check 32bit and noirq */ |
410 | 412 | ||
411 | .irq_handler = ata_interrupt, | 413 | .irq_handler = ata_interrupt, |
412 | .irq_clear = ata_bmdma_irq_clear, | 414 | .irq_clear = ata_bmdma_irq_clear, |
@@ -454,12 +456,12 @@ static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev | |||
454 | u8 rc; | 456 | u8 rc; |
455 | 457 | ||
456 | /* Enter configuration mode */ | 458 | /* Enter configuration mode */ |
457 | inw(ap->ioaddr.error_addr); | 459 | ioread16(ap->ioaddr.error_addr); |
458 | inw(ap->ioaddr.error_addr); | 460 | ioread16(ap->ioaddr.error_addr); |
459 | outb(3, ap->ioaddr.nsect_addr); | 461 | iowrite8(3, ap->ioaddr.nsect_addr); |
460 | 462 | ||
461 | /* Read VLB clock strapping */ | 463 | /* Read VLB clock strapping */ |
462 | clock = 1000000000 / khz[inb(ap->ioaddr.lbah_addr) & 0x03]; | 464 | clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; |
463 | 465 | ||
464 | /* Get the timing data in cycles */ | 466 | /* Get the timing data in cycles */ |
465 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); | 467 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); |
@@ -477,33 +479,33 @@ static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev | |||
477 | setup = FIT(t.setup, 1, 4) - 1; | 479 | setup = FIT(t.setup, 1, 4) - 1; |
478 | 480 | ||
479 | /* Select the right timing bank for write timing */ | 481 | /* Select the right timing bank for write timing */ |
480 | rc = inb(ap->ioaddr.lbal_addr); | 482 | rc = ioread8(ap->ioaddr.lbal_addr); |
481 | rc &= 0x7F; | 483 | rc &= 0x7F; |
482 | rc |= (adev->devno << 7); | 484 | rc |= (adev->devno << 7); |
483 | outb(rc, ap->ioaddr.lbal_addr); | 485 | iowrite8(rc, ap->ioaddr.lbal_addr); |
484 | 486 | ||
485 | /* Write the timings */ | 487 | /* Write the timings */ |
486 | outb(active << 4 | recover, ap->ioaddr.error_addr); | 488 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
487 | 489 | ||
488 | /* Select the right bank for read timings, also | 490 | /* Select the right bank for read timings, also |
489 | load the shared timings for address */ | 491 | load the shared timings for address */ |
490 | rc = inb(ap->ioaddr.device_addr); | 492 | rc = ioread8(ap->ioaddr.device_addr); |
491 | rc &= 0xC0; | 493 | rc &= 0xC0; |
492 | rc |= adev->devno; /* Index select */ | 494 | rc |= adev->devno; /* Index select */ |
493 | rc |= (setup << 4) | 0x04; | 495 | rc |= (setup << 4) | 0x04; |
494 | outb(rc, ap->ioaddr.device_addr); | 496 | iowrite8(rc, ap->ioaddr.device_addr); |
495 | 497 | ||
496 | /* Load the read timings */ | 498 | /* Load the read timings */ |
497 | outb(active << 4 | recover, ap->ioaddr.data_addr); | 499 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
498 | 500 | ||
499 | /* Ensure the timing register mode is right */ | 501 | /* Ensure the timing register mode is right */ |
500 | rc = inb (ap->ioaddr.lbal_addr); | 502 | rc = ioread8(ap->ioaddr.lbal_addr); |
501 | rc &= 0x73; | 503 | rc &= 0x73; |
502 | rc |= 0x84; | 504 | rc |= 0x84; |
503 | outb(rc, ap->ioaddr.lbal_addr); | 505 | iowrite8(rc, ap->ioaddr.lbal_addr); |
504 | 506 | ||
505 | /* Exit command mode */ | 507 | /* Exit command mode */ |
506 | outb(0x83, ap->ioaddr.nsect_addr); | 508 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
507 | } | 509 | } |
508 | 510 | ||
509 | 511 | ||
@@ -522,7 +524,7 @@ static struct ata_port_operations opti82c611a_port_ops = { | |||
522 | .qc_prep = ata_qc_prep, | 524 | .qc_prep = ata_qc_prep, |
523 | .qc_issue = ata_qc_issue_prot, | 525 | .qc_issue = ata_qc_issue_prot, |
524 | 526 | ||
525 | .data_xfer = ata_pio_data_xfer, | 527 | .data_xfer = ata_data_xfer, |
526 | 528 | ||
527 | .irq_handler = ata_interrupt, | 529 | .irq_handler = ata_interrupt, |
528 | .irq_clear = ata_bmdma_irq_clear, | 530 | .irq_clear = ata_bmdma_irq_clear, |
@@ -551,9 +553,9 @@ static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |||
551 | sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */ | 553 | sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */ |
552 | 554 | ||
553 | /* Enter configuration mode */ | 555 | /* Enter configuration mode */ |
554 | inw(ap->ioaddr.error_addr); | 556 | ioread16(ap->ioaddr.error_addr); |
555 | inw(ap->ioaddr.error_addr); | 557 | ioread16(ap->ioaddr.error_addr); |
556 | outb(3, ap->ioaddr.nsect_addr); | 558 | iowrite8(3, ap->ioaddr.nsect_addr); |
557 | 559 | ||
558 | /* Read VLB clock strapping */ | 560 | /* Read VLB clock strapping */ |
559 | clock = 1000000000 / khz[sysclk]; | 561 | clock = 1000000000 / khz[sysclk]; |
@@ -574,33 +576,33 @@ static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |||
574 | setup = FIT(t.setup, 1, 4) - 1; | 576 | setup = FIT(t.setup, 1, 4) - 1; |
575 | 577 | ||
576 | /* Select the right timing bank for write timing */ | 578 | /* Select the right timing bank for write timing */ |
577 | rc = inb(ap->ioaddr.lbal_addr); | 579 | rc = ioread8(ap->ioaddr.lbal_addr); |
578 | rc &= 0x7F; | 580 | rc &= 0x7F; |
579 | rc |= (adev->devno << 7); | 581 | rc |= (adev->devno << 7); |
580 | outb(rc, ap->ioaddr.lbal_addr); | 582 | iowrite8(rc, ap->ioaddr.lbal_addr); |
581 | 583 | ||
582 | /* Write the timings */ | 584 | /* Write the timings */ |
583 | outb(active << 4 | recover, ap->ioaddr.error_addr); | 585 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
584 | 586 | ||
585 | /* Select the right bank for read timings, also | 587 | /* Select the right bank for read timings, also |
586 | load the shared timings for address */ | 588 | load the shared timings for address */ |
587 | rc = inb(ap->ioaddr.device_addr); | 589 | rc = ioread8(ap->ioaddr.device_addr); |
588 | rc &= 0xC0; | 590 | rc &= 0xC0; |
589 | rc |= adev->devno; /* Index select */ | 591 | rc |= adev->devno; /* Index select */ |
590 | rc |= (setup << 4) | 0x04; | 592 | rc |= (setup << 4) | 0x04; |
591 | outb(rc, ap->ioaddr.device_addr); | 593 | iowrite8(rc, ap->ioaddr.device_addr); |
592 | 594 | ||
593 | /* Load the read timings */ | 595 | /* Load the read timings */ |
594 | outb(active << 4 | recover, ap->ioaddr.data_addr); | 596 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
595 | 597 | ||
596 | /* Ensure the timing register mode is right */ | 598 | /* Ensure the timing register mode is right */ |
597 | rc = inb (ap->ioaddr.lbal_addr); | 599 | rc = ioread8(ap->ioaddr.lbal_addr); |
598 | rc &= 0x73; | 600 | rc &= 0x73; |
599 | rc |= 0x84; | 601 | rc |= 0x84; |
600 | outb(rc, ap->ioaddr.lbal_addr); | 602 | iowrite8(rc, ap->ioaddr.lbal_addr); |
601 | 603 | ||
602 | /* Exit command mode */ | 604 | /* Exit command mode */ |
603 | outb(0x83, ap->ioaddr.nsect_addr); | 605 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
604 | 606 | ||
605 | /* We need to know this for quad device on the MVB */ | 607 | /* We need to know this for quad device on the MVB */ |
606 | ap->host->private_data = ap; | 608 | ap->host->private_data = ap; |
@@ -650,7 +652,7 @@ static struct ata_port_operations opti82c46x_port_ops = { | |||
650 | .qc_prep = ata_qc_prep, | 652 | .qc_prep = ata_qc_prep, |
651 | .qc_issue = opti82c46x_qc_issue_prot, | 653 | .qc_issue = opti82c46x_qc_issue_prot, |
652 | 654 | ||
653 | .data_xfer = ata_pio_data_xfer, | 655 | .data_xfer = ata_data_xfer, |
654 | 656 | ||
655 | .irq_handler = ata_interrupt, | 657 | .irq_handler = ata_interrupt, |
656 | .irq_clear = ata_bmdma_irq_clear, | 658 | .irq_clear = ata_bmdma_irq_clear, |
@@ -676,6 +678,7 @@ static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl | |||
676 | struct ata_probe_ent ae; | 678 | struct ata_probe_ent ae; |
677 | struct platform_device *pdev; | 679 | struct platform_device *pdev; |
678 | struct ata_port_operations *ops = &legacy_port_ops; | 680 | struct ata_port_operations *ops = &legacy_port_ops; |
681 | void __iomem *io_addr, *ctrl_addr; | ||
679 | int pio_modes = pio_mask; | 682 | int pio_modes = pio_mask; |
680 | u32 mask = (1 << port); | 683 | u32 mask = (1 << port); |
681 | int ret; | 684 | int ret; |
@@ -689,6 +692,12 @@ static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl | |||
689 | devm_request_region(&pdev->dev, ctrl, 1, "pata_legacy") == NULL) | 692 | devm_request_region(&pdev->dev, ctrl, 1, "pata_legacy") == NULL) |
690 | goto fail; | 693 | goto fail; |
691 | 694 | ||
695 | ret = -ENOMEM; | ||
696 | io_addr = devm_ioport_map(&pdev->dev, io, 8); | ||
697 | ctrl_addr = devm_ioport_map(&pdev->dev, ctrl, 1); | ||
698 | if (!io_addr || !ctrl_addr) | ||
699 | goto fail; | ||
700 | |||
692 | if (ht6560a & mask) { | 701 | if (ht6560a & mask) { |
693 | ops = &ht6560a_port_ops; | 702 | ops = &ht6560a_port_ops; |
694 | pio_modes = 0x07; | 703 | pio_modes = 0x07; |
@@ -754,9 +763,9 @@ static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl | |||
754 | ae.irq = irq; | 763 | ae.irq = irq; |
755 | ae.irq_flags = 0; | 764 | ae.irq_flags = 0; |
756 | ae.port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST; | 765 | ae.port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST; |
757 | ae.port[0].cmd_addr = io; | 766 | ae.port[0].cmd_addr = io_addr; |
758 | ae.port[0].altstatus_addr = ctrl; | 767 | ae.port[0].altstatus_addr = ctrl_addr; |
759 | ae.port[0].ctl_addr = ctrl; | 768 | ae.port[0].ctl_addr = ctrl_addr; |
760 | ata_std_ports(&ae.port[0]); | 769 | ata_std_ports(&ae.port[0]); |
761 | ae.private_data = ld; | 770 | ae.private_data = ld; |
762 | 771 | ||
diff --git a/drivers/ata/pata_marvell.c b/drivers/ata/pata_marvell.c index 0a4409546a02..586cbb750c99 100644 --- a/drivers/ata/pata_marvell.c +++ b/drivers/ata/pata_marvell.c | |||
@@ -57,7 +57,7 @@ static int marvell_pre_reset(struct ata_port *ap) | |||
57 | switch(ap->port_no) | 57 | switch(ap->port_no) |
58 | { | 58 | { |
59 | case 0: | 59 | case 0: |
60 | if (inb(ap->ioaddr.bmdma_addr + 1) & 1) | 60 | if (ioread8(ap->ioaddr.bmdma_addr + 1) & 1) |
61 | ap->cbl = ATA_CBL_PATA40; | 61 | ap->cbl = ATA_CBL_PATA40; |
62 | else | 62 | else |
63 | ap->cbl = ATA_CBL_PATA80; | 63 | ap->cbl = ATA_CBL_PATA80; |
@@ -129,7 +129,7 @@ static const struct ata_port_operations marvell_ops = { | |||
129 | .bmdma_status = ata_bmdma_status, | 129 | .bmdma_status = ata_bmdma_status, |
130 | .qc_prep = ata_qc_prep, | 130 | .qc_prep = ata_qc_prep, |
131 | .qc_issue = ata_qc_issue_prot, | 131 | .qc_issue = ata_qc_issue_prot, |
132 | .data_xfer = ata_pio_data_xfer, | 132 | .data_xfer = ata_data_xfer, |
133 | 133 | ||
134 | /* Timeout handling */ | 134 | /* Timeout handling */ |
135 | .irq_handler = ata_interrupt, | 135 | .irq_handler = ata_interrupt, |
diff --git a/drivers/ata/pata_mpc52xx.c b/drivers/ata/pata_mpc52xx.c index 5320ea854365..8a9d80c3628e 100644 --- a/drivers/ata/pata_mpc52xx.c +++ b/drivers/ata/pata_mpc52xx.c | |||
@@ -295,7 +295,7 @@ static struct ata_port_operations mpc52xx_ata_port_ops = { | |||
295 | .error_handler = mpc52xx_ata_error_handler, | 295 | .error_handler = mpc52xx_ata_error_handler, |
296 | .qc_prep = ata_qc_prep, | 296 | .qc_prep = ata_qc_prep, |
297 | .qc_issue = ata_qc_issue_prot, | 297 | .qc_issue = ata_qc_issue_prot, |
298 | .data_xfer = ata_mmio_data_xfer, | 298 | .data_xfer = ata_data_xfer, |
299 | .irq_handler = ata_interrupt, | 299 | .irq_handler = ata_interrupt, |
300 | .irq_clear = ata_bmdma_irq_clear, | 300 | .irq_clear = ata_bmdma_irq_clear, |
301 | .port_start = ata_port_start, | 301 | .port_start = ata_port_start, |
@@ -308,7 +308,7 @@ static struct ata_probe_ent mpc52xx_ata_probe_ent = { | |||
308 | .pio_mask = 0x1f, /* Up to PIO4 */ | 308 | .pio_mask = 0x1f, /* Up to PIO4 */ |
309 | .mwdma_mask = 0x00, /* No MWDMA */ | 309 | .mwdma_mask = 0x00, /* No MWDMA */ |
310 | .udma_mask = 0x00, /* No UDMA */ | 310 | .udma_mask = 0x00, /* No UDMA */ |
311 | .port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | ATA_FLAG_MMIO, | 311 | .port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, |
312 | .irq_flags = 0, | 312 | .irq_flags = 0, |
313 | }; | 313 | }; |
314 | 314 | ||
@@ -324,18 +324,18 @@ mpc52xx_ata_init_one(struct device *dev, struct mpc52xx_ata_priv *priv) | |||
324 | ae->irq = priv->ata_irq; | 324 | ae->irq = priv->ata_irq; |
325 | 325 | ||
326 | aio->cmd_addr = 0; /* Don't have a classic reg block */ | 326 | aio->cmd_addr = 0; /* Don't have a classic reg block */ |
327 | aio->altstatus_addr = (unsigned long)&priv->ata_regs->tf_control; | 327 | aio->altstatus_addr = &priv->ata_regs->tf_control; |
328 | aio->ctl_addr = (unsigned long)&priv->ata_regs->tf_control; | 328 | aio->ctl_addr = &priv->ata_regs->tf_control; |
329 | aio->data_addr = (unsigned long)&priv->ata_regs->tf_data; | 329 | aio->data_addr = &priv->ata_regs->tf_data; |
330 | aio->error_addr = (unsigned long)&priv->ata_regs->tf_features; | 330 | aio->error_addr = &priv->ata_regs->tf_features; |
331 | aio->feature_addr = (unsigned long)&priv->ata_regs->tf_features; | 331 | aio->feature_addr = &priv->ata_regs->tf_features; |
332 | aio->nsect_addr = (unsigned long)&priv->ata_regs->tf_sec_count; | 332 | aio->nsect_addr = &priv->ata_regs->tf_sec_count; |
333 | aio->lbal_addr = (unsigned long)&priv->ata_regs->tf_sec_num; | 333 | aio->lbal_addr = &priv->ata_regs->tf_sec_num; |
334 | aio->lbam_addr = (unsigned long)&priv->ata_regs->tf_cyl_low; | 334 | aio->lbam_addr = &priv->ata_regs->tf_cyl_low; |
335 | aio->lbah_addr = (unsigned long)&priv->ata_regs->tf_cyl_high; | 335 | aio->lbah_addr = &priv->ata_regs->tf_cyl_high; |
336 | aio->device_addr = (unsigned long)&priv->ata_regs->tf_dev_head; | 336 | aio->device_addr = &priv->ata_regs->tf_dev_head; |
337 | aio->status_addr = (unsigned long)&priv->ata_regs->tf_command; | 337 | aio->status_addr = &priv->ata_regs->tf_command; |
338 | aio->command_addr = (unsigned long)&priv->ata_regs->tf_command; | 338 | aio->command_addr = &priv->ata_regs->tf_command; |
339 | 339 | ||
340 | ae->private_data = priv; | 340 | ae->private_data = priv; |
341 | 341 | ||
diff --git a/drivers/ata/pata_mpiix.c b/drivers/ata/pata_mpiix.c index c4a1b10f3bca..9837faf0f620 100644 --- a/drivers/ata/pata_mpiix.c +++ b/drivers/ata/pata_mpiix.c | |||
@@ -188,7 +188,7 @@ static struct ata_port_operations mpiix_port_ops = { | |||
188 | 188 | ||
189 | .qc_prep = ata_qc_prep, | 189 | .qc_prep = ata_qc_prep, |
190 | .qc_issue = mpiix_qc_issue_prot, | 190 | .qc_issue = mpiix_qc_issue_prot, |
191 | .data_xfer = ata_pio_data_xfer, | 191 | .data_xfer = ata_data_xfer, |
192 | 192 | ||
193 | .irq_handler = ata_interrupt, | 193 | .irq_handler = ata_interrupt, |
194 | .irq_clear = ata_bmdma_irq_clear, | 194 | .irq_clear = ata_bmdma_irq_clear, |
@@ -199,10 +199,11 @@ static struct ata_port_operations mpiix_port_ops = { | |||
199 | static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id) | 199 | static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
200 | { | 200 | { |
201 | /* Single threaded by the PCI probe logic */ | 201 | /* Single threaded by the PCI probe logic */ |
202 | static struct ata_probe_ent probe[2]; | 202 | static struct ata_probe_ent probe; |
203 | static int printed_version; | 203 | static int printed_version; |
204 | void __iomem *cmd_addr, *ctl_addr; | ||
204 | u16 idetim; | 205 | u16 idetim; |
205 | int enabled; | 206 | int irq; |
206 | 207 | ||
207 | if (!printed_version++) | 208 | if (!printed_version++) |
208 | dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n"); | 209 | dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n"); |
@@ -215,43 +216,43 @@ static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |||
215 | if (!(idetim & ENABLED)) | 216 | if (!(idetim & ENABLED)) |
216 | return -ENODEV; | 217 | return -ENODEV; |
217 | 218 | ||
219 | if (!(idetim & SECONDARY)) { | ||
220 | irq = 14; | ||
221 | cmd_addr = devm_ioport_map(&dev->dev, 0x1F0, 8); | ||
222 | ctl_addr = devm_ioport_map(&dev->dev, 0x3F6, 1); | ||
223 | } else { | ||
224 | irq = 15; | ||
225 | cmd_addr = devm_ioport_map(&dev->dev, 0x170, 8); | ||
226 | ctl_addr = devm_ioport_map(&dev->dev, 0x376, 1); | ||
227 | } | ||
228 | |||
229 | if (!cmd_addr || !ctl_addr) | ||
230 | return -ENOMEM; | ||
231 | |||
218 | /* We do our own plumbing to avoid leaking special cases for whacko | 232 | /* We do our own plumbing to avoid leaking special cases for whacko |
219 | ancient hardware into the core code. There are two issues to | 233 | ancient hardware into the core code. There are two issues to |
220 | worry about. #1 The chip is a bridge so if in legacy mode and | 234 | worry about. #1 The chip is a bridge so if in legacy mode and |
221 | without BARs set fools the setup. #2 If you pci_disable_device | 235 | without BARs set fools the setup. #2 If you pci_disable_device |
222 | the MPIIX your box goes castors up */ | 236 | the MPIIX your box goes castors up */ |
223 | 237 | ||
224 | INIT_LIST_HEAD(&probe[0].node); | 238 | INIT_LIST_HEAD(&probe.node); |
225 | probe[0].dev = pci_dev_to_dev(dev); | 239 | probe.dev = pci_dev_to_dev(dev); |
226 | probe[0].port_ops = &mpiix_port_ops; | 240 | probe.port_ops = &mpiix_port_ops; |
227 | probe[0].sht = &mpiix_sht; | 241 | probe.sht = &mpiix_sht; |
228 | probe[0].pio_mask = 0x1F; | 242 | probe.pio_mask = 0x1F; |
229 | probe[0].irq = 14; | 243 | probe.irq = irq; |
230 | probe[0].irq_flags = SA_SHIRQ; | 244 | probe.irq_flags = SA_SHIRQ; |
231 | probe[0].port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST; | 245 | probe.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST; |
232 | probe[0].n_ports = 1; | 246 | probe.n_ports = 1; |
233 | probe[0].port[0].cmd_addr = 0x1F0; | 247 | probe.port[0].cmd_addr = cmd_addr; |
234 | probe[0].port[0].ctl_addr = 0x3F6; | 248 | probe.port[0].ctl_addr = ctl_addr; |
235 | probe[0].port[0].altstatus_addr = 0x3F6; | 249 | probe.port[0].altstatus_addr = ctl_addr; |
236 | |||
237 | /* The secondary lurks at different addresses but is otherwise | ||
238 | the same beastie */ | ||
239 | |||
240 | INIT_LIST_HEAD(&probe[1].node); | ||
241 | probe[1] = probe[0]; | ||
242 | probe[1].irq = 15; | ||
243 | probe[1].port[0].cmd_addr = 0x170; | ||
244 | probe[1].port[0].ctl_addr = 0x376; | ||
245 | probe[1].port[0].altstatus_addr = 0x376; | ||
246 | 250 | ||
247 | /* Let libata fill in the port details */ | 251 | /* Let libata fill in the port details */ |
248 | ata_std_ports(&probe[0].port[0]); | 252 | ata_std_ports(&probe.port[0]); |
249 | ata_std_ports(&probe[1].port[0]); | ||
250 | 253 | ||
251 | /* Now add the port that is active */ | 254 | /* Now add the port that is active */ |
252 | enabled = (idetim & SECONDARY) ? 1 : 0; | 255 | if (ata_device_add(&probe)) |
253 | |||
254 | if (ata_device_add(&probe[enabled])) | ||
255 | return 0; | 256 | return 0; |
256 | return -ENODEV; | 257 | return -ENODEV; |
257 | } | 258 | } |
diff --git a/drivers/ata/pata_netcell.c b/drivers/ata/pata_netcell.c index 2a2f8df70582..23365a0ff9b0 100644 --- a/drivers/ata/pata_netcell.c +++ b/drivers/ata/pata_netcell.c | |||
@@ -89,7 +89,7 @@ static const struct ata_port_operations netcell_ops = { | |||
89 | .bmdma_status = ata_bmdma_status, | 89 | .bmdma_status = ata_bmdma_status, |
90 | .qc_prep = ata_qc_prep, | 90 | .qc_prep = ata_qc_prep, |
91 | .qc_issue = ata_qc_issue_prot, | 91 | .qc_issue = ata_qc_issue_prot, |
92 | .data_xfer = ata_pio_data_xfer, | 92 | .data_xfer = ata_data_xfer, |
93 | 93 | ||
94 | /* IRQ-related hooks */ | 94 | /* IRQ-related hooks */ |
95 | .irq_handler = ata_interrupt, | 95 | .irq_handler = ata_interrupt, |
diff --git a/drivers/ata/pata_ns87410.c b/drivers/ata/pata_ns87410.c index fdafd92c92a9..95c4e0b3f2d4 100644 --- a/drivers/ata/pata_ns87410.c +++ b/drivers/ata/pata_ns87410.c | |||
@@ -179,7 +179,7 @@ static struct ata_port_operations ns87410_port_ops = { | |||
179 | .qc_prep = ata_qc_prep, | 179 | .qc_prep = ata_qc_prep, |
180 | .qc_issue = ns87410_qc_issue_prot, | 180 | .qc_issue = ns87410_qc_issue_prot, |
181 | 181 | ||
182 | .data_xfer = ata_pio_data_xfer, | 182 | .data_xfer = ata_data_xfer, |
183 | 183 | ||
184 | .irq_handler = ata_interrupt, | 184 | .irq_handler = ata_interrupt, |
185 | .irq_clear = ata_bmdma_irq_clear, | 185 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_oldpiix.c b/drivers/ata/pata_oldpiix.c index df9f7fd4b4e5..95d570a30a2f 100644 --- a/drivers/ata/pata_oldpiix.c +++ b/drivers/ata/pata_oldpiix.c | |||
@@ -259,7 +259,7 @@ static const struct ata_port_operations oldpiix_pata_ops = { | |||
259 | .bmdma_status = ata_bmdma_status, | 259 | .bmdma_status = ata_bmdma_status, |
260 | .qc_prep = ata_qc_prep, | 260 | .qc_prep = ata_qc_prep, |
261 | .qc_issue = oldpiix_qc_issue_prot, | 261 | .qc_issue = oldpiix_qc_issue_prot, |
262 | .data_xfer = ata_pio_data_xfer, | 262 | .data_xfer = ata_data_xfer, |
263 | 263 | ||
264 | .irq_handler = ata_interrupt, | 264 | .irq_handler = ata_interrupt, |
265 | .irq_clear = ata_bmdma_irq_clear, | 265 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_opti.c b/drivers/ata/pata_opti.c index 58951ccd1e4d..e76302631597 100644 --- a/drivers/ata/pata_opti.c +++ b/drivers/ata/pata_opti.c | |||
@@ -95,18 +95,18 @@ static void opti_error_handler(struct ata_port *ap) | |||
95 | 95 | ||
96 | static void opti_write_reg(struct ata_port *ap, u8 val, int reg) | 96 | static void opti_write_reg(struct ata_port *ap, u8 val, int reg) |
97 | { | 97 | { |
98 | unsigned long regio = ap->ioaddr.cmd_addr; | 98 | void __iomem *regio = ap->ioaddr.cmd_addr; |
99 | 99 | ||
100 | /* These 3 unlock the control register access */ | 100 | /* These 3 unlock the control register access */ |
101 | inw(regio + 1); | 101 | ioread16(regio + 1); |
102 | inw(regio + 1); | 102 | ioread16(regio + 1); |
103 | outb(3, regio + 2); | 103 | iowrite8(3, regio + 2); |
104 | 104 | ||
105 | /* Do the I/O */ | 105 | /* Do the I/O */ |
106 | outb(val, regio + reg); | 106 | iowrite8(val, regio + reg); |
107 | 107 | ||
108 | /* Relock */ | 108 | /* Relock */ |
109 | outb(0x83, regio + 2); | 109 | iowrite8(0x83, regio + 2); |
110 | } | 110 | } |
111 | 111 | ||
112 | /** | 112 | /** |
@@ -124,7 +124,7 @@ static void opti_set_piomode(struct ata_port *ap, struct ata_device *adev) | |||
124 | struct ata_device *pair = ata_dev_pair(adev); | 124 | struct ata_device *pair = ata_dev_pair(adev); |
125 | int clock; | 125 | int clock; |
126 | int pio = adev->pio_mode - XFER_PIO_0; | 126 | int pio = adev->pio_mode - XFER_PIO_0; |
127 | unsigned long regio = ap->ioaddr.cmd_addr; | 127 | void __iomem *regio = ap->ioaddr.cmd_addr; |
128 | u8 addr; | 128 | u8 addr; |
129 | 129 | ||
130 | /* Address table precomputed with prefetch off and a DCLK of 2 */ | 130 | /* Address table precomputed with prefetch off and a DCLK of 2 */ |
@@ -137,8 +137,8 @@ static void opti_set_piomode(struct ata_port *ap, struct ata_device *adev) | |||
137 | { 0x58, 0x44, 0x32, 0x22, 0x21 } | 137 | { 0x58, 0x44, 0x32, 0x22, 0x21 } |
138 | }; | 138 | }; |
139 | 139 | ||
140 | outb(0xff, regio + 5); | 140 | iowrite8(0xff, regio + 5); |
141 | clock = inw(regio + 5) & 1; | 141 | clock = ioread16(regio + 5) & 1; |
142 | 142 | ||
143 | /* | 143 | /* |
144 | * As with many controllers the address setup time is shared | 144 | * As with many controllers the address setup time is shared |
@@ -205,7 +205,7 @@ static struct ata_port_operations opti_port_ops = { | |||
205 | .qc_prep = ata_qc_prep, | 205 | .qc_prep = ata_qc_prep, |
206 | .qc_issue = ata_qc_issue_prot, | 206 | .qc_issue = ata_qc_issue_prot, |
207 | 207 | ||
208 | .data_xfer = ata_pio_data_xfer, | 208 | .data_xfer = ata_data_xfer, |
209 | 209 | ||
210 | .irq_handler = ata_interrupt, | 210 | .irq_handler = ata_interrupt, |
211 | .irq_clear = ata_bmdma_irq_clear, | 211 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_optidma.c b/drivers/ata/pata_optidma.c index 74d2e7a28da0..067fca1fa8a1 100644 --- a/drivers/ata/pata_optidma.c +++ b/drivers/ata/pata_optidma.c | |||
@@ -91,12 +91,12 @@ static void optidma_error_handler(struct ata_port *ap) | |||
91 | 91 | ||
92 | static void optidma_unlock(struct ata_port *ap) | 92 | static void optidma_unlock(struct ata_port *ap) |
93 | { | 93 | { |
94 | unsigned long regio = ap->ioaddr.cmd_addr; | 94 | void __iomem *regio = ap->ioaddr.cmd_addr; |
95 | 95 | ||
96 | /* These 3 unlock the control register access */ | 96 | /* These 3 unlock the control register access */ |
97 | inw(regio + 1); | 97 | ioread16(regio + 1); |
98 | inw(regio + 1); | 98 | ioread16(regio + 1); |
99 | outb(3, regio + 2); | 99 | iowrite8(3, regio + 2); |
100 | } | 100 | } |
101 | 101 | ||
102 | /** | 102 | /** |
@@ -108,10 +108,10 @@ static void optidma_unlock(struct ata_port *ap) | |||
108 | 108 | ||
109 | static void optidma_lock(struct ata_port *ap) | 109 | static void optidma_lock(struct ata_port *ap) |
110 | { | 110 | { |
111 | unsigned long regio = ap->ioaddr.cmd_addr; | 111 | void __iomem *regio = ap->ioaddr.cmd_addr; |
112 | 112 | ||
113 | /* Relock */ | 113 | /* Relock */ |
114 | outb(0x83, regio + 2); | 114 | iowrite8(0x83, regio + 2); |
115 | } | 115 | } |
116 | 116 | ||
117 | /** | 117 | /** |
@@ -133,7 +133,7 @@ static void optidma_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mo | |||
133 | struct ata_device *pair = ata_dev_pair(adev); | 133 | struct ata_device *pair = ata_dev_pair(adev); |
134 | int pio = adev->pio_mode - XFER_PIO_0; | 134 | int pio = adev->pio_mode - XFER_PIO_0; |
135 | int dma = adev->dma_mode - XFER_MW_DMA_0; | 135 | int dma = adev->dma_mode - XFER_MW_DMA_0; |
136 | unsigned long regio = ap->ioaddr.cmd_addr; | 136 | void __iomem *regio = ap->ioaddr.cmd_addr; |
137 | u8 addr; | 137 | u8 addr; |
138 | 138 | ||
139 | /* Address table precomputed with a DCLK of 2 */ | 139 | /* Address table precomputed with a DCLK of 2 */ |
@@ -178,20 +178,20 @@ static void optidma_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mo | |||
178 | 178 | ||
179 | /* Commence primary programming sequence */ | 179 | /* Commence primary programming sequence */ |
180 | /* First we load the device number into the timing select */ | 180 | /* First we load the device number into the timing select */ |
181 | outb(adev->devno, regio + MISC_REG); | 181 | iowrite8(adev->devno, regio + MISC_REG); |
182 | /* Now we load the data timings into read data/write data */ | 182 | /* Now we load the data timings into read data/write data */ |
183 | if (mode < XFER_MW_DMA_0) { | 183 | if (mode < XFER_MW_DMA_0) { |
184 | outb(data_rec_timing[pci_clock][pio], regio + READ_REG); | 184 | iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG); |
185 | outb(data_rec_timing[pci_clock][pio], regio + WRITE_REG); | 185 | iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG); |
186 | } else if (mode < XFER_UDMA_0) { | 186 | } else if (mode < XFER_UDMA_0) { |
187 | outb(dma_data_rec_timing[pci_clock][dma], regio + READ_REG); | 187 | iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG); |
188 | outb(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG); | 188 | iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG); |
189 | } | 189 | } |
190 | /* Finally we load the address setup into the misc register */ | 190 | /* Finally we load the address setup into the misc register */ |
191 | outb(addr | adev->devno, regio + MISC_REG); | 191 | iowrite8(addr | adev->devno, regio + MISC_REG); |
192 | 192 | ||
193 | /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */ | 193 | /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */ |
194 | outb(0x85, regio + CNTRL_REG); | 194 | iowrite8(0x85, regio + CNTRL_REG); |
195 | 195 | ||
196 | /* Switch back to IDE mode */ | 196 | /* Switch back to IDE mode */ |
197 | optidma_lock(ap); | 197 | optidma_lock(ap); |
@@ -389,7 +389,7 @@ static struct ata_port_operations optidma_port_ops = { | |||
389 | .qc_prep = ata_qc_prep, | 389 | .qc_prep = ata_qc_prep, |
390 | .qc_issue = ata_qc_issue_prot, | 390 | .qc_issue = ata_qc_issue_prot, |
391 | 391 | ||
392 | .data_xfer = ata_pio_data_xfer, | 392 | .data_xfer = ata_data_xfer, |
393 | 393 | ||
394 | .irq_handler = ata_interrupt, | 394 | .irq_handler = ata_interrupt, |
395 | .irq_clear = ata_bmdma_irq_clear, | 395 | .irq_clear = ata_bmdma_irq_clear, |
@@ -422,7 +422,7 @@ static struct ata_port_operations optiplus_port_ops = { | |||
422 | .qc_prep = ata_qc_prep, | 422 | .qc_prep = ata_qc_prep, |
423 | .qc_issue = ata_qc_issue_prot, | 423 | .qc_issue = ata_qc_issue_prot, |
424 | 424 | ||
425 | .data_xfer = ata_pio_data_xfer, | 425 | .data_xfer = ata_data_xfer, |
426 | 426 | ||
427 | .irq_handler = ata_interrupt, | 427 | .irq_handler = ata_interrupt, |
428 | .irq_clear = ata_bmdma_irq_clear, | 428 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_pcmcia.c b/drivers/ata/pata_pcmcia.c index 5a9b24950f99..1830e9166943 100644 --- a/drivers/ata/pata_pcmcia.c +++ b/drivers/ata/pata_pcmcia.c | |||
@@ -88,7 +88,7 @@ static struct ata_port_operations pcmcia_port_ops = { | |||
88 | .qc_prep = ata_qc_prep, | 88 | .qc_prep = ata_qc_prep, |
89 | .qc_issue = ata_qc_issue_prot, | 89 | .qc_issue = ata_qc_issue_prot, |
90 | 90 | ||
91 | .data_xfer = ata_pio_data_xfer_noirq, | 91 | .data_xfer = ata_data_xfer_noirq, |
92 | 92 | ||
93 | .irq_handler = ata_interrupt, | 93 | .irq_handler = ata_interrupt, |
94 | .irq_clear = ata_bmdma_irq_clear, | 94 | .irq_clear = ata_bmdma_irq_clear, |
@@ -121,6 +121,7 @@ static int pcmcia_init_one(struct pcmcia_device *pdev) | |||
121 | cistpl_cftable_entry_t *cfg; | 121 | cistpl_cftable_entry_t *cfg; |
122 | int pass, last_ret = 0, last_fn = 0, is_kme = 0, ret = -ENOMEM; | 122 | int pass, last_ret = 0, last_fn = 0, is_kme = 0, ret = -ENOMEM; |
123 | unsigned long io_base, ctl_base; | 123 | unsigned long io_base, ctl_base; |
124 | void __iomem *io_addr, *ctl_addr; | ||
124 | 125 | ||
125 | info = kzalloc(sizeof(*info), GFP_KERNEL); | 126 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
126 | if (info == NULL) | 127 | if (info == NULL) |
@@ -231,10 +232,17 @@ next_entry: | |||
231 | CS_CHECK(RequestIRQ, pcmcia_request_irq(pdev, &pdev->irq)); | 232 | CS_CHECK(RequestIRQ, pcmcia_request_irq(pdev, &pdev->irq)); |
232 | CS_CHECK(RequestConfiguration, pcmcia_request_configuration(pdev, &pdev->conf)); | 233 | CS_CHECK(RequestConfiguration, pcmcia_request_configuration(pdev, &pdev->conf)); |
233 | 234 | ||
235 | /* iomap */ | ||
236 | ret = -ENOMEM; | ||
237 | io_addr = devm_ioport_map(&pdev->dev, io_base, 8); | ||
238 | ctl_addr = devm_ioport_map(&pdev->dev, ctl_base, 1); | ||
239 | if (!io_addr || !ctl_addr) | ||
240 | goto failed; | ||
241 | |||
234 | /* Success. Disable the IRQ nIEN line, do quirks */ | 242 | /* Success. Disable the IRQ nIEN line, do quirks */ |
235 | outb(0x02, ctl_base); | 243 | iowrite8(0x02, ctl_addr); |
236 | if (is_kme) | 244 | if (is_kme) |
237 | outb(0x81, ctl_base + 0x01); | 245 | iowrite8(0x81, ctl_addr + 0x01); |
238 | 246 | ||
239 | /* FIXME: Could be more ports at base + 0x10 but we only deal with | 247 | /* FIXME: Could be more ports at base + 0x10 but we only deal with |
240 | one right now */ | 248 | one right now */ |
@@ -256,11 +264,12 @@ next_entry: | |||
256 | ae.irq = pdev->irq.AssignedIRQ; | 264 | ae.irq = pdev->irq.AssignedIRQ; |
257 | ae.irq_flags = SA_SHIRQ; | 265 | ae.irq_flags = SA_SHIRQ; |
258 | ae.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST; | 266 | ae.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST; |
259 | ae.port[0].cmd_addr = io_base; | 267 | ae.port[0].cmd_addr = io_addr; |
260 | ae.port[0].altstatus_addr = ctl_base; | 268 | ae.port[0].altstatus_addr = ctl_addr; |
261 | ae.port[0].ctl_addr = ctl_base; | 269 | ae.port[0].ctl_addr = ctl_addr; |
262 | ata_std_ports(&ae.port[0]); | 270 | ata_std_ports(&ae.port[0]); |
263 | 271 | ||
272 | ret = -ENODEV; | ||
264 | if (ata_device_add(&ae) == 0) | 273 | if (ata_device_add(&ae) == 0) |
265 | goto failed; | 274 | goto failed; |
266 | 275 | ||
diff --git a/drivers/ata/pata_pdc2027x.c b/drivers/ata/pata_pdc2027x.c index 1c106b866c79..2ff91bbbab06 100644 --- a/drivers/ata/pata_pdc2027x.c +++ b/drivers/ata/pata_pdc2027x.c | |||
@@ -45,6 +45,8 @@ | |||
45 | #endif | 45 | #endif |
46 | 46 | ||
47 | enum { | 47 | enum { |
48 | PDC_MMIO_BAR = 5, | ||
49 | |||
48 | PDC_UDMA_100 = 0, | 50 | PDC_UDMA_100 = 0, |
49 | PDC_UDMA_133 = 1, | 51 | PDC_UDMA_133 = 1, |
50 | 52 | ||
@@ -158,7 +160,7 @@ static struct ata_port_operations pdc2027x_pata100_ops = { | |||
158 | .bmdma_status = ata_bmdma_status, | 160 | .bmdma_status = ata_bmdma_status, |
159 | .qc_prep = ata_qc_prep, | 161 | .qc_prep = ata_qc_prep, |
160 | .qc_issue = ata_qc_issue_prot, | 162 | .qc_issue = ata_qc_issue_prot, |
161 | .data_xfer = ata_mmio_data_xfer, | 163 | .data_xfer = ata_data_xfer, |
162 | 164 | ||
163 | .freeze = ata_bmdma_freeze, | 165 | .freeze = ata_bmdma_freeze, |
164 | .thaw = ata_bmdma_thaw, | 166 | .thaw = ata_bmdma_thaw, |
@@ -190,7 +192,7 @@ static struct ata_port_operations pdc2027x_pata133_ops = { | |||
190 | .bmdma_status = ata_bmdma_status, | 192 | .bmdma_status = ata_bmdma_status, |
191 | .qc_prep = ata_qc_prep, | 193 | .qc_prep = ata_qc_prep, |
192 | .qc_issue = ata_qc_issue_prot, | 194 | .qc_issue = ata_qc_issue_prot, |
193 | .data_xfer = ata_mmio_data_xfer, | 195 | .data_xfer = ata_data_xfer, |
194 | 196 | ||
195 | .freeze = ata_bmdma_freeze, | 197 | .freeze = ata_bmdma_freeze, |
196 | .thaw = ata_bmdma_thaw, | 198 | .thaw = ata_bmdma_thaw, |
@@ -239,7 +241,7 @@ MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl); | |||
239 | */ | 241 | */ |
240 | static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset) | 242 | static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset) |
241 | { | 243 | { |
242 | return ap->host->mmio_base + ap->port_no * 0x100 + offset; | 244 | return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset; |
243 | } | 245 | } |
244 | 246 | ||
245 | /** | 247 | /** |
@@ -520,18 +522,19 @@ static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc) | |||
520 | 522 | ||
521 | static long pdc_read_counter(struct ata_probe_ent *probe_ent) | 523 | static long pdc_read_counter(struct ata_probe_ent *probe_ent) |
522 | { | 524 | { |
525 | void __iomem *mmio_base = probe_ent->iomap[PDC_MMIO_BAR]; | ||
523 | long counter; | 526 | long counter; |
524 | int retry = 1; | 527 | int retry = 1; |
525 | u32 bccrl, bccrh, bccrlv, bccrhv; | 528 | u32 bccrl, bccrh, bccrlv, bccrhv; |
526 | 529 | ||
527 | retry: | 530 | retry: |
528 | bccrl = readl(probe_ent->mmio_base + PDC_BYTE_COUNT) & 0xffff; | 531 | bccrl = readl(mmio_base + PDC_BYTE_COUNT) & 0xffff; |
529 | bccrh = readl(probe_ent->mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff; | 532 | bccrh = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff; |
530 | rmb(); | 533 | rmb(); |
531 | 534 | ||
532 | /* Read the counter values again for verification */ | 535 | /* Read the counter values again for verification */ |
533 | bccrlv = readl(probe_ent->mmio_base + PDC_BYTE_COUNT) & 0xffff; | 536 | bccrlv = readl(mmio_base + PDC_BYTE_COUNT) & 0xffff; |
534 | bccrhv = readl(probe_ent->mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff; | 537 | bccrhv = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff; |
535 | rmb(); | 538 | rmb(); |
536 | 539 | ||
537 | counter = (bccrh << 15) | bccrl; | 540 | counter = (bccrh << 15) | bccrl; |
@@ -562,7 +565,7 @@ retry: | |||
562 | */ | 565 | */ |
563 | static void pdc_adjust_pll(struct ata_probe_ent *probe_ent, long pll_clock, unsigned int board_idx) | 566 | static void pdc_adjust_pll(struct ata_probe_ent *probe_ent, long pll_clock, unsigned int board_idx) |
564 | { | 567 | { |
565 | 568 | void __iomem *mmio_base = probe_ent->iomap[PDC_MMIO_BAR]; | |
566 | u16 pll_ctl; | 569 | u16 pll_ctl; |
567 | long pll_clock_khz = pll_clock / 1000; | 570 | long pll_clock_khz = pll_clock / 1000; |
568 | long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ; | 571 | long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ; |
@@ -581,7 +584,7 @@ static void pdc_adjust_pll(struct ata_probe_ent *probe_ent, long pll_clock, unsi | |||
581 | /* Show the current clock value of PLL control register | 584 | /* Show the current clock value of PLL control register |
582 | * (maybe already configured by the firmware) | 585 | * (maybe already configured by the firmware) |
583 | */ | 586 | */ |
584 | pll_ctl = readw(probe_ent->mmio_base + PDC_PLL_CTL); | 587 | pll_ctl = readw(mmio_base + PDC_PLL_CTL); |
585 | 588 | ||
586 | PDPRINTK("pll_ctl[%X]\n", pll_ctl); | 589 | PDPRINTK("pll_ctl[%X]\n", pll_ctl); |
587 | #endif | 590 | #endif |
@@ -621,8 +624,8 @@ static void pdc_adjust_pll(struct ata_probe_ent *probe_ent, long pll_clock, unsi | |||
621 | 624 | ||
622 | PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl); | 625 | PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl); |
623 | 626 | ||
624 | writew(pll_ctl, probe_ent->mmio_base + PDC_PLL_CTL); | 627 | writew(pll_ctl, mmio_base + PDC_PLL_CTL); |
625 | readw(probe_ent->mmio_base + PDC_PLL_CTL); /* flush */ | 628 | readw(mmio_base + PDC_PLL_CTL); /* flush */ |
626 | 629 | ||
627 | /* Wait the PLL circuit to be stable */ | 630 | /* Wait the PLL circuit to be stable */ |
628 | mdelay(30); | 631 | mdelay(30); |
@@ -632,7 +635,7 @@ static void pdc_adjust_pll(struct ata_probe_ent *probe_ent, long pll_clock, unsi | |||
632 | * Show the current clock value of PLL control register | 635 | * Show the current clock value of PLL control register |
633 | * (maybe configured by the firmware) | 636 | * (maybe configured by the firmware) |
634 | */ | 637 | */ |
635 | pll_ctl = readw(probe_ent->mmio_base + PDC_PLL_CTL); | 638 | pll_ctl = readw(mmio_base + PDC_PLL_CTL); |
636 | 639 | ||
637 | PDPRINTK("pll_ctl[%X]\n", pll_ctl); | 640 | PDPRINTK("pll_ctl[%X]\n", pll_ctl); |
638 | #endif | 641 | #endif |
@@ -648,6 +651,7 @@ static void pdc_adjust_pll(struct ata_probe_ent *probe_ent, long pll_clock, unsi | |||
648 | */ | 651 | */ |
649 | static long pdc_detect_pll_input_clock(struct ata_probe_ent *probe_ent) | 652 | static long pdc_detect_pll_input_clock(struct ata_probe_ent *probe_ent) |
650 | { | 653 | { |
654 | void __iomem *mmio_base = probe_ent->iomap[PDC_MMIO_BAR]; | ||
651 | u32 scr; | 655 | u32 scr; |
652 | long start_count, end_count; | 656 | long start_count, end_count; |
653 | long pll_clock; | 657 | long pll_clock; |
@@ -656,10 +660,10 @@ static long pdc_detect_pll_input_clock(struct ata_probe_ent *probe_ent) | |||
656 | start_count = pdc_read_counter(probe_ent); | 660 | start_count = pdc_read_counter(probe_ent); |
657 | 661 | ||
658 | /* Start the test mode */ | 662 | /* Start the test mode */ |
659 | scr = readl(probe_ent->mmio_base + PDC_SYS_CTL); | 663 | scr = readl(mmio_base + PDC_SYS_CTL); |
660 | PDPRINTK("scr[%X]\n", scr); | 664 | PDPRINTK("scr[%X]\n", scr); |
661 | writel(scr | (0x01 << 14), probe_ent->mmio_base + PDC_SYS_CTL); | 665 | writel(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL); |
662 | readl(probe_ent->mmio_base + PDC_SYS_CTL); /* flush */ | 666 | readl(mmio_base + PDC_SYS_CTL); /* flush */ |
663 | 667 | ||
664 | /* Let the counter run for 100 ms. */ | 668 | /* Let the counter run for 100 ms. */ |
665 | mdelay(100); | 669 | mdelay(100); |
@@ -668,10 +672,10 @@ static long pdc_detect_pll_input_clock(struct ata_probe_ent *probe_ent) | |||
668 | end_count = pdc_read_counter(probe_ent); | 672 | end_count = pdc_read_counter(probe_ent); |
669 | 673 | ||
670 | /* Stop the test mode */ | 674 | /* Stop the test mode */ |
671 | scr = readl(probe_ent->mmio_base + PDC_SYS_CTL); | 675 | scr = readl(mmio_base + PDC_SYS_CTL); |
672 | PDPRINTK("scr[%X]\n", scr); | 676 | PDPRINTK("scr[%X]\n", scr); |
673 | writel(scr & ~(0x01 << 14), probe_ent->mmio_base + PDC_SYS_CTL); | 677 | writel(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL); |
674 | readl(probe_ent->mmio_base + PDC_SYS_CTL); /* flush */ | 678 | readl(mmio_base + PDC_SYS_CTL); /* flush */ |
675 | 679 | ||
676 | /* calculate the input clock in Hz */ | 680 | /* calculate the input clock in Hz */ |
677 | pll_clock = (start_count - end_count) * 10; | 681 | pll_clock = (start_count - end_count) * 10; |
@@ -716,7 +720,7 @@ static int pdc_hardware_init(struct pci_dev *pdev, struct ata_probe_ent *pe, uns | |||
716 | * @port: ata ioports to setup | 720 | * @port: ata ioports to setup |
717 | * @base: base address | 721 | * @base: base address |
718 | */ | 722 | */ |
719 | static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base) | 723 | static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base) |
720 | { | 724 | { |
721 | port->cmd_addr = | 725 | port->cmd_addr = |
722 | port->data_addr = base; | 726 | port->data_addr = base; |
@@ -750,7 +754,6 @@ static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_de | |||
750 | unsigned int board_idx = (unsigned int) ent->driver_data; | 754 | unsigned int board_idx = (unsigned int) ent->driver_data; |
751 | 755 | ||
752 | struct ata_probe_ent *probe_ent; | 756 | struct ata_probe_ent *probe_ent; |
753 | unsigned long base; | ||
754 | void __iomem *mmio_base; | 757 | void __iomem *mmio_base; |
755 | int rc; | 758 | int rc; |
756 | 759 | ||
@@ -761,7 +764,7 @@ static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_de | |||
761 | if (rc) | 764 | if (rc) |
762 | return rc; | 765 | return rc; |
763 | 766 | ||
764 | rc = pci_request_regions(pdev, DRV_NAME); | 767 | rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); |
765 | if (rc) | 768 | if (rc) |
766 | return rc; | 769 | return rc; |
767 | 770 | ||
@@ -781,12 +784,6 @@ static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_de | |||
781 | probe_ent->dev = pci_dev_to_dev(pdev); | 784 | probe_ent->dev = pci_dev_to_dev(pdev); |
782 | INIT_LIST_HEAD(&probe_ent->node); | 785 | INIT_LIST_HEAD(&probe_ent->node); |
783 | 786 | ||
784 | mmio_base = pcim_iomap(pdev, 5, 0); | ||
785 | if (!mmio_base) | ||
786 | return -ENOMEM; | ||
787 | |||
788 | base = (unsigned long) mmio_base; | ||
789 | |||
790 | probe_ent->sht = pdc2027x_port_info[board_idx].sht; | 787 | probe_ent->sht = pdc2027x_port_info[board_idx].sht; |
791 | probe_ent->port_flags = pdc2027x_port_info[board_idx].flags; | 788 | probe_ent->port_flags = pdc2027x_port_info[board_idx].flags; |
792 | probe_ent->pio_mask = pdc2027x_port_info[board_idx].pio_mask; | 789 | probe_ent->pio_mask = pdc2027x_port_info[board_idx].pio_mask; |
@@ -796,12 +793,14 @@ static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_de | |||
796 | 793 | ||
797 | probe_ent->irq = pdev->irq; | 794 | probe_ent->irq = pdev->irq; |
798 | probe_ent->irq_flags = SA_SHIRQ; | 795 | probe_ent->irq_flags = SA_SHIRQ; |
799 | probe_ent->mmio_base = mmio_base; | 796 | probe_ent->iomap = pcim_iomap_table(pdev); |
797 | |||
798 | mmio_base = probe_ent->iomap[PDC_MMIO_BAR]; | ||
800 | 799 | ||
801 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x17c0); | 800 | pdc_ata_setup_port(&probe_ent->port[0], mmio_base + 0x17c0); |
802 | probe_ent->port[0].bmdma_addr = base + 0x1000; | 801 | probe_ent->port[0].bmdma_addr = mmio_base + 0x1000; |
803 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x15c0); | 802 | pdc_ata_setup_port(&probe_ent->port[1], mmio_base + 0x15c0); |
804 | probe_ent->port[1].bmdma_addr = base + 0x1008; | 803 | probe_ent->port[1].bmdma_addr = mmio_base + 0x1008; |
805 | 804 | ||
806 | probe_ent->n_ports = 2; | 805 | probe_ent->n_ports = 2; |
807 | 806 | ||
diff --git a/drivers/ata/pata_pdc202xx_old.c b/drivers/ata/pata_pdc202xx_old.c index c52e1e8aa2d2..7e194d81c1b6 100644 --- a/drivers/ata/pata_pdc202xx_old.c +++ b/drivers/ata/pata_pdc202xx_old.c | |||
@@ -170,17 +170,17 @@ static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc) | |||
170 | struct ata_taskfile *tf = &qc->tf; | 170 | struct ata_taskfile *tf = &qc->tf; |
171 | int sel66 = ap->port_no ? 0x08: 0x02; | 171 | int sel66 = ap->port_no ? 0x08: 0x02; |
172 | 172 | ||
173 | unsigned long master = ap->host->ports[0]->ioaddr.bmdma_addr; | 173 | void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr; |
174 | unsigned long clock = master + 0x11; | 174 | void __iomem *clock = master + 0x11; |
175 | unsigned long atapi_reg = master + 0x20 + (4 * ap->port_no); | 175 | void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no); |
176 | 176 | ||
177 | u32 len; | 177 | u32 len; |
178 | 178 | ||
179 | /* Check we keep host level locking here */ | 179 | /* Check we keep host level locking here */ |
180 | if (adev->dma_mode >= XFER_UDMA_2) | 180 | if (adev->dma_mode >= XFER_UDMA_2) |
181 | outb(inb(clock) | sel66, clock); | 181 | iowrite8(ioread8(clock) | sel66, clock); |
182 | else | 182 | else |
183 | outb(inb(clock) & ~sel66, clock); | 183 | iowrite8(ioread8(clock) & ~sel66, clock); |
184 | 184 | ||
185 | /* The DMA clocks may have been trashed by a reset. FIXME: make conditional | 185 | /* The DMA clocks may have been trashed by a reset. FIXME: make conditional |
186 | and move to qc_issue ? */ | 186 | and move to qc_issue ? */ |
@@ -196,7 +196,7 @@ static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc) | |||
196 | else | 196 | else |
197 | len |= 0x05000000; | 197 | len |= 0x05000000; |
198 | 198 | ||
199 | outl(len, atapi_reg); | 199 | iowrite32(len, atapi_reg); |
200 | } | 200 | } |
201 | 201 | ||
202 | /* Activate DMA */ | 202 | /* Activate DMA */ |
@@ -219,19 +219,19 @@ static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc) | |||
219 | 219 | ||
220 | int sel66 = ap->port_no ? 0x08: 0x02; | 220 | int sel66 = ap->port_no ? 0x08: 0x02; |
221 | /* The clock bits are in the same register for both channels */ | 221 | /* The clock bits are in the same register for both channels */ |
222 | unsigned long master = ap->host->ports[0]->ioaddr.bmdma_addr; | 222 | void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr; |
223 | unsigned long clock = master + 0x11; | 223 | void __iomem *clock = master + 0x11; |
224 | unsigned long atapi_reg = master + 0x20 + (4 * ap->port_no); | 224 | void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no); |
225 | 225 | ||
226 | /* Cases the state machine will not complete correctly */ | 226 | /* Cases the state machine will not complete correctly */ |
227 | if (tf->protocol == ATA_PROT_ATAPI_DMA || ( tf->flags & ATA_TFLAG_LBA48)) { | 227 | if (tf->protocol == ATA_PROT_ATAPI_DMA || ( tf->flags & ATA_TFLAG_LBA48)) { |
228 | outl(0, atapi_reg); | 228 | iowrite32(0, atapi_reg); |
229 | outb(inb(clock) & ~sel66, clock); | 229 | iowrite8(ioread8(clock) & ~sel66, clock); |
230 | } | 230 | } |
231 | /* Check we keep host level locking here */ | 231 | /* Check we keep host level locking here */ |
232 | /* Flip back to 33Mhz for PIO */ | 232 | /* Flip back to 33Mhz for PIO */ |
233 | if (adev->dma_mode >= XFER_UDMA_2) | 233 | if (adev->dma_mode >= XFER_UDMA_2) |
234 | outb(inb(clock) & ~sel66, clock); | 234 | iowrite8(ioread8(clock) & ~sel66, clock); |
235 | 235 | ||
236 | ata_bmdma_stop(qc); | 236 | ata_bmdma_stop(qc); |
237 | } | 237 | } |
@@ -294,7 +294,7 @@ static struct ata_port_operations pdc2024x_port_ops = { | |||
294 | 294 | ||
295 | .qc_prep = ata_qc_prep, | 295 | .qc_prep = ata_qc_prep, |
296 | .qc_issue = ata_qc_issue_prot, | 296 | .qc_issue = ata_qc_issue_prot, |
297 | .data_xfer = ata_pio_data_xfer, | 297 | .data_xfer = ata_data_xfer, |
298 | 298 | ||
299 | .irq_handler = ata_interrupt, | 299 | .irq_handler = ata_interrupt, |
300 | .irq_clear = ata_bmdma_irq_clear, | 300 | .irq_clear = ata_bmdma_irq_clear, |
@@ -326,7 +326,7 @@ static struct ata_port_operations pdc2026x_port_ops = { | |||
326 | 326 | ||
327 | .qc_prep = ata_qc_prep, | 327 | .qc_prep = ata_qc_prep, |
328 | .qc_issue = ata_qc_issue_prot, | 328 | .qc_issue = ata_qc_issue_prot, |
329 | .data_xfer = ata_pio_data_xfer, | 329 | .data_xfer = ata_data_xfer, |
330 | 330 | ||
331 | .irq_handler = ata_interrupt, | 331 | .irq_handler = ata_interrupt, |
332 | .irq_clear = ata_bmdma_irq_clear, | 332 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_platform.c b/drivers/ata/pata_platform.c index 8a261a3daeda..b35fc29f4db5 100644 --- a/drivers/ata/pata_platform.c +++ b/drivers/ata/pata_platform.c | |||
@@ -83,7 +83,7 @@ static struct ata_port_operations pata_platform_port_ops = { | |||
83 | .qc_prep = ata_qc_prep, | 83 | .qc_prep = ata_qc_prep, |
84 | .qc_issue = ata_qc_issue_prot, | 84 | .qc_issue = ata_qc_issue_prot, |
85 | 85 | ||
86 | .data_xfer = ata_pio_data_xfer_noirq, | 86 | .data_xfer = ata_data_xfer_noirq, |
87 | 87 | ||
88 | .irq_handler = ata_interrupt, | 88 | .irq_handler = ata_interrupt, |
89 | .irq_clear = ata_bmdma_irq_clear, | 89 | .irq_clear = ata_bmdma_irq_clear, |
@@ -134,7 +134,6 @@ static int __devinit pata_platform_probe(struct platform_device *pdev) | |||
134 | struct resource *io_res, *ctl_res; | 134 | struct resource *io_res, *ctl_res; |
135 | struct ata_probe_ent ae; | 135 | struct ata_probe_ent ae; |
136 | unsigned int mmio; | 136 | unsigned int mmio; |
137 | int ret; | ||
138 | 137 | ||
139 | /* | 138 | /* |
140 | * Simple resource validation .. | 139 | * Simple resource validation .. |
@@ -188,48 +187,29 @@ static int __devinit pata_platform_probe(struct platform_device *pdev) | |||
188 | * Handle the MMIO case | 187 | * Handle the MMIO case |
189 | */ | 188 | */ |
190 | if (mmio) { | 189 | if (mmio) { |
191 | ae.port_flags |= ATA_FLAG_MMIO; | 190 | ae.port[0].cmd_addr = devm_ioremap(&pdev->dev, io_res->start, |
192 | 191 | io_res->end - io_res->start + 1); | |
193 | ae.port[0].cmd_addr = (unsigned long) | 192 | ae.port[0].ctl_addr = devm_ioremap(&pdev->dev, ctl_res->start, |
194 | devm_ioremap(&pdev->dev, io_res->start, | 193 | ctl_res->end - ctl_res->start + 1); |
195 | io_res->end - io_res->start + 1); | ||
196 | if (unlikely(!ae.port[0].cmd_addr)) { | ||
197 | dev_err(&pdev->dev, "failed to remap IO base\n"); | ||
198 | return -ENXIO; | ||
199 | } | ||
200 | |||
201 | ae.port[0].ctl_addr = (unsigned long) | ||
202 | devm_ioremap(&pdev->dev, ctl_res->start, | ||
203 | ctl_res->end - ctl_res->start + 1); | ||
204 | if (unlikely(!ae.port[0].ctl_addr)) { | ||
205 | dev_err(&pdev->dev, "failed to remap CTL base\n"); | ||
206 | ret = -ENXIO; | ||
207 | goto bad_remap; | ||
208 | } | ||
209 | } else { | 194 | } else { |
210 | ae.port[0].cmd_addr = io_res->start; | 195 | ae.port[0].cmd_addr = devm_ioport_map(&pdev->dev, io_res->start, |
211 | ae.port[0].ctl_addr = ctl_res->start; | 196 | io_res->end - io_res->start + 1); |
197 | ae.port[0].ctl_addr = devm_ioport_map(&pdev->dev, ctl_res->start, | ||
198 | ctl_res->end - ctl_res->start + 1); | ||
199 | } | ||
200 | if (!ae.port[0].cmd_addr || !ae.port[0].ctl_addr) { | ||
201 | dev_err(&pdev->dev, "failed to map IO/CTL base\n"); | ||
202 | return -ENOMEM; | ||
212 | } | 203 | } |
213 | 204 | ||
214 | ae.port[0].altstatus_addr = ae.port[0].ctl_addr; | 205 | ae.port[0].altstatus_addr = ae.port[0].ctl_addr; |
215 | 206 | ||
216 | pata_platform_setup_port(&ae.port[0], pdev->dev.platform_data); | 207 | pata_platform_setup_port(&ae.port[0], pdev->dev.platform_data); |
217 | 208 | ||
218 | if (unlikely(ata_device_add(&ae) == 0)) { | 209 | if (unlikely(ata_device_add(&ae) == 0)) |
219 | ret = -ENODEV; | 210 | return -ENODEV; |
220 | goto add_failed; | ||
221 | } | ||
222 | 211 | ||
223 | return 0; | 212 | return 0; |
224 | |||
225 | add_failed: | ||
226 | if (ae.port[0].ctl_addr && mmio) | ||
227 | iounmap((void __iomem *)ae.port[0].ctl_addr); | ||
228 | bad_remap: | ||
229 | if (ae.port[0].cmd_addr && mmio) | ||
230 | iounmap((void __iomem *)ae.port[0].cmd_addr); | ||
231 | |||
232 | return ret; | ||
233 | } | 213 | } |
234 | 214 | ||
235 | /** | 215 | /** |
diff --git a/drivers/ata/pata_qdi.c b/drivers/ata/pata_qdi.c index 4413960042a9..5b86effa0bbd 100644 --- a/drivers/ata/pata_qdi.c +++ b/drivers/ata/pata_qdi.c | |||
@@ -131,22 +131,24 @@ static void qdi_data_xfer(struct ata_device *adev, unsigned char *buf, unsigned | |||
131 | 131 | ||
132 | if (ata_id_has_dword_io(adev->id)) { | 132 | if (ata_id_has_dword_io(adev->id)) { |
133 | if (write_data) | 133 | if (write_data) |
134 | outsl(ap->ioaddr.data_addr, buf, buflen >> 2); | 134 | iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
135 | else | 135 | else |
136 | insl(ap->ioaddr.data_addr, buf, buflen >> 2); | 136 | ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
137 | 137 | ||
138 | if (unlikely(slop)) { | 138 | if (unlikely(slop)) { |
139 | u32 pad; | 139 | u32 pad; |
140 | if (write_data) { | 140 | if (write_data) { |
141 | memcpy(&pad, buf + buflen - slop, slop); | 141 | memcpy(&pad, buf + buflen - slop, slop); |
142 | outl(le32_to_cpu(pad), ap->ioaddr.data_addr); | 142 | pad = le32_to_cpu(pad); |
143 | iowrite32(pad, ap->ioaddr.data_addr); | ||
143 | } else { | 144 | } else { |
144 | pad = cpu_to_le32(inl(ap->ioaddr.data_addr)); | 145 | pad = ioread32(ap->ioaddr.data_addr); |
146 | pad = cpu_to_le32(pad); | ||
145 | memcpy(buf + buflen - slop, &pad, slop); | 147 | memcpy(buf + buflen - slop, &pad, slop); |
146 | } | 148 | } |
147 | } | 149 | } |
148 | } else | 150 | } else |
149 | ata_pio_data_xfer(adev, buf, buflen, write_data); | 151 | ata_data_xfer(adev, buf, buflen, write_data); |
150 | } | 152 | } |
151 | 153 | ||
152 | static struct scsi_host_template qdi_sht = { | 154 | static struct scsi_host_template qdi_sht = { |
@@ -234,10 +236,9 @@ static __init int qdi_init_one(unsigned long port, int type, unsigned long io, i | |||
234 | { | 236 | { |
235 | struct ata_probe_ent ae; | 237 | struct ata_probe_ent ae; |
236 | struct platform_device *pdev; | 238 | struct platform_device *pdev; |
239 | void __iomem *io_addr, *ctl_addr; | ||
237 | int ret; | 240 | int ret; |
238 | 241 | ||
239 | unsigned long ctrl = io + 0x206; | ||
240 | |||
241 | /* | 242 | /* |
242 | * Fill in a probe structure first of all | 243 | * Fill in a probe structure first of all |
243 | */ | 244 | */ |
@@ -246,6 +247,12 @@ static __init int qdi_init_one(unsigned long port, int type, unsigned long io, i | |||
246 | if (IS_ERR(pdev)) | 247 | if (IS_ERR(pdev)) |
247 | return PTR_ERR(pdev); | 248 | return PTR_ERR(pdev); |
248 | 249 | ||
250 | ret = -ENOMEM; | ||
251 | io_addr = devm_ioport_map(&pdev->dev, io, 8); | ||
252 | ctl_addr = devm_ioport_map(&pdev->dev, io + 0x206, 1); | ||
253 | if (!io_addr || !ctl_addr) | ||
254 | goto fail; | ||
255 | |||
249 | memset(&ae, 0, sizeof(struct ata_probe_ent)); | 256 | memset(&ae, 0, sizeof(struct ata_probe_ent)); |
250 | INIT_LIST_HEAD(&ae.node); | 257 | INIT_LIST_HEAD(&ae.node); |
251 | ae.dev = &pdev->dev; | 258 | ae.dev = &pdev->dev; |
@@ -263,9 +270,9 @@ static __init int qdi_init_one(unsigned long port, int type, unsigned long io, i | |||
263 | ae.irq = irq; | 270 | ae.irq = irq; |
264 | ae.irq_flags = 0; | 271 | ae.irq_flags = 0; |
265 | ae.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST; | 272 | ae.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST; |
266 | ae.port[0].cmd_addr = io; | 273 | ae.port[0].cmd_addr = io_addr; |
267 | ae.port[0].altstatus_addr = ctrl; | 274 | ae.port[0].altstatus_addr = ctl_addr; |
268 | ae.port[0].ctl_addr = ctrl; | 275 | ae.port[0].ctl_addr = ctl_addr; |
269 | ata_std_ports(&ae.port[0]); | 276 | ata_std_ports(&ae.port[0]); |
270 | 277 | ||
271 | /* | 278 | /* |
@@ -278,14 +285,17 @@ static __init int qdi_init_one(unsigned long port, int type, unsigned long io, i | |||
278 | qdi_data[nr_qdi_host].platform_dev = pdev; | 285 | qdi_data[nr_qdi_host].platform_dev = pdev; |
279 | 286 | ||
280 | printk(KERN_INFO DRV_NAME": qd%d at 0x%lx.\n", type, io); | 287 | printk(KERN_INFO DRV_NAME": qd%d at 0x%lx.\n", type, io); |
281 | ret = ata_device_add(&ae); | 288 | |
282 | if (ret == 0) { | 289 | ret = -ENODEV; |
283 | platform_device_unregister(pdev); | 290 | if (!ata_device_add(&ae)) |
284 | return -ENODEV; | 291 | goto fail; |
285 | } | ||
286 | 292 | ||
287 | qdi_host[nr_qdi_host++] = dev_get_drvdata(&pdev->dev); | 293 | qdi_host[nr_qdi_host++] = dev_get_drvdata(&pdev->dev); |
288 | return 0; | 294 | return 0; |
295 | |||
296 | fail: | ||
297 | platform_device_unregister(pdev); | ||
298 | return ret; | ||
289 | } | 299 | } |
290 | 300 | ||
291 | /** | 301 | /** |
diff --git a/drivers/ata/pata_radisys.c b/drivers/ata/pata_radisys.c index ca9c97056c1b..a391bd2fa8fe 100644 --- a/drivers/ata/pata_radisys.c +++ b/drivers/ata/pata_radisys.c | |||
@@ -255,7 +255,7 @@ static const struct ata_port_operations radisys_pata_ops = { | |||
255 | .bmdma_status = ata_bmdma_status, | 255 | .bmdma_status = ata_bmdma_status, |
256 | .qc_prep = ata_qc_prep, | 256 | .qc_prep = ata_qc_prep, |
257 | .qc_issue = radisys_qc_issue_prot, | 257 | .qc_issue = radisys_qc_issue_prot, |
258 | .data_xfer = ata_pio_data_xfer, | 258 | .data_xfer = ata_data_xfer, |
259 | 259 | ||
260 | .irq_handler = ata_interrupt, | 260 | .irq_handler = ata_interrupt, |
261 | .irq_clear = ata_bmdma_irq_clear, | 261 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_rz1000.c b/drivers/ata/pata_rz1000.c index c99331bbbdd9..4a4d2e5be09b 100644 --- a/drivers/ata/pata_rz1000.c +++ b/drivers/ata/pata_rz1000.c | |||
@@ -115,7 +115,7 @@ static struct ata_port_operations rz1000_port_ops = { | |||
115 | .qc_prep = ata_qc_prep, | 115 | .qc_prep = ata_qc_prep, |
116 | .qc_issue = ata_qc_issue_prot, | 116 | .qc_issue = ata_qc_issue_prot, |
117 | 117 | ||
118 | .data_xfer = ata_pio_data_xfer, | 118 | .data_xfer = ata_data_xfer, |
119 | 119 | ||
120 | .freeze = ata_bmdma_freeze, | 120 | .freeze = ata_bmdma_freeze, |
121 | .thaw = ata_bmdma_thaw, | 121 | .thaw = ata_bmdma_thaw, |
diff --git a/drivers/ata/pata_sc1200.c b/drivers/ata/pata_sc1200.c index 75638ccc0183..8d3e7c57b22c 100644 --- a/drivers/ata/pata_sc1200.c +++ b/drivers/ata/pata_sc1200.c | |||
@@ -220,7 +220,7 @@ static struct ata_port_operations sc1200_port_ops = { | |||
220 | .qc_prep = ata_qc_prep, | 220 | .qc_prep = ata_qc_prep, |
221 | .qc_issue = sc1200_qc_issue_prot, | 221 | .qc_issue = sc1200_qc_issue_prot, |
222 | 222 | ||
223 | .data_xfer = ata_pio_data_xfer, | 223 | .data_xfer = ata_data_xfer, |
224 | 224 | ||
225 | .irq_handler = ata_interrupt, | 225 | .irq_handler = ata_interrupt, |
226 | .irq_clear = ata_bmdma_irq_clear, | 226 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_serverworks.c b/drivers/ata/pata_serverworks.c index 46ea1e8af4f4..c41a1d3b5b7d 100644 --- a/drivers/ata/pata_serverworks.c +++ b/drivers/ata/pata_serverworks.c | |||
@@ -348,7 +348,7 @@ static struct ata_port_operations serverworks_osb4_port_ops = { | |||
348 | .qc_prep = ata_qc_prep, | 348 | .qc_prep = ata_qc_prep, |
349 | .qc_issue = ata_qc_issue_prot, | 349 | .qc_issue = ata_qc_issue_prot, |
350 | 350 | ||
351 | .data_xfer = ata_pio_data_xfer, | 351 | .data_xfer = ata_data_xfer, |
352 | 352 | ||
353 | .irq_handler = ata_interrupt, | 353 | .irq_handler = ata_interrupt, |
354 | .irq_clear = ata_bmdma_irq_clear, | 354 | .irq_clear = ata_bmdma_irq_clear, |
@@ -381,7 +381,7 @@ static struct ata_port_operations serverworks_csb_port_ops = { | |||
381 | .qc_prep = ata_qc_prep, | 381 | .qc_prep = ata_qc_prep, |
382 | .qc_issue = ata_qc_issue_prot, | 382 | .qc_issue = ata_qc_issue_prot, |
383 | 383 | ||
384 | .data_xfer = ata_pio_data_xfer, | 384 | .data_xfer = ata_data_xfer, |
385 | 385 | ||
386 | .irq_handler = ata_interrupt, | 386 | .irq_handler = ata_interrupt, |
387 | .irq_clear = ata_bmdma_irq_clear, | 387 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_sil680.c b/drivers/ata/pata_sil680.c index 955c1d3a5739..992e22537023 100644 --- a/drivers/ata/pata_sil680.c +++ b/drivers/ata/pata_sil680.c | |||
@@ -252,7 +252,7 @@ static struct ata_port_operations sil680_port_ops = { | |||
252 | .qc_prep = ata_qc_prep, | 252 | .qc_prep = ata_qc_prep, |
253 | .qc_issue = ata_qc_issue_prot, | 253 | .qc_issue = ata_qc_issue_prot, |
254 | 254 | ||
255 | .data_xfer = ata_pio_data_xfer, | 255 | .data_xfer = ata_data_xfer, |
256 | 256 | ||
257 | .irq_handler = ata_interrupt, | 257 | .irq_handler = ata_interrupt, |
258 | .irq_clear = ata_bmdma_irq_clear, | 258 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_sis.c b/drivers/ata/pata_sis.c index 88ed2aad4629..c82d75b96f60 100644 --- a/drivers/ata/pata_sis.c +++ b/drivers/ata/pata_sis.c | |||
@@ -603,7 +603,7 @@ static const struct ata_port_operations sis_133_ops = { | |||
603 | .bmdma_status = ata_bmdma_status, | 603 | .bmdma_status = ata_bmdma_status, |
604 | .qc_prep = ata_qc_prep, | 604 | .qc_prep = ata_qc_prep, |
605 | .qc_issue = ata_qc_issue_prot, | 605 | .qc_issue = ata_qc_issue_prot, |
606 | .data_xfer = ata_pio_data_xfer, | 606 | .data_xfer = ata_data_xfer, |
607 | 607 | ||
608 | .irq_handler = ata_interrupt, | 608 | .irq_handler = ata_interrupt, |
609 | .irq_clear = ata_bmdma_irq_clear, | 609 | .irq_clear = ata_bmdma_irq_clear, |
@@ -634,7 +634,7 @@ static const struct ata_port_operations sis_133_early_ops = { | |||
634 | .bmdma_status = ata_bmdma_status, | 634 | .bmdma_status = ata_bmdma_status, |
635 | .qc_prep = ata_qc_prep, | 635 | .qc_prep = ata_qc_prep, |
636 | .qc_issue = ata_qc_issue_prot, | 636 | .qc_issue = ata_qc_issue_prot, |
637 | .data_xfer = ata_pio_data_xfer, | 637 | .data_xfer = ata_data_xfer, |
638 | 638 | ||
639 | .irq_handler = ata_interrupt, | 639 | .irq_handler = ata_interrupt, |
640 | .irq_clear = ata_bmdma_irq_clear, | 640 | .irq_clear = ata_bmdma_irq_clear, |
@@ -666,7 +666,7 @@ static const struct ata_port_operations sis_100_ops = { | |||
666 | .bmdma_status = ata_bmdma_status, | 666 | .bmdma_status = ata_bmdma_status, |
667 | .qc_prep = ata_qc_prep, | 667 | .qc_prep = ata_qc_prep, |
668 | .qc_issue = ata_qc_issue_prot, | 668 | .qc_issue = ata_qc_issue_prot, |
669 | .data_xfer = ata_pio_data_xfer, | 669 | .data_xfer = ata_data_xfer, |
670 | 670 | ||
671 | .irq_handler = ata_interrupt, | 671 | .irq_handler = ata_interrupt, |
672 | .irq_clear = ata_bmdma_irq_clear, | 672 | .irq_clear = ata_bmdma_irq_clear, |
@@ -697,7 +697,7 @@ static const struct ata_port_operations sis_66_ops = { | |||
697 | .bmdma_status = ata_bmdma_status, | 697 | .bmdma_status = ata_bmdma_status, |
698 | .qc_prep = ata_qc_prep, | 698 | .qc_prep = ata_qc_prep, |
699 | .qc_issue = ata_qc_issue_prot, | 699 | .qc_issue = ata_qc_issue_prot, |
700 | .data_xfer = ata_pio_data_xfer, | 700 | .data_xfer = ata_data_xfer, |
701 | 701 | ||
702 | .irq_handler = ata_interrupt, | 702 | .irq_handler = ata_interrupt, |
703 | .irq_clear = ata_bmdma_irq_clear, | 703 | .irq_clear = ata_bmdma_irq_clear, |
@@ -728,7 +728,7 @@ static const struct ata_port_operations sis_old_ops = { | |||
728 | .bmdma_status = ata_bmdma_status, | 728 | .bmdma_status = ata_bmdma_status, |
729 | .qc_prep = ata_qc_prep, | 729 | .qc_prep = ata_qc_prep, |
730 | .qc_issue = ata_qc_issue_prot, | 730 | .qc_issue = ata_qc_issue_prot, |
731 | .data_xfer = ata_pio_data_xfer, | 731 | .data_xfer = ata_data_xfer, |
732 | 732 | ||
733 | .irq_handler = ata_interrupt, | 733 | .irq_handler = ata_interrupt, |
734 | .irq_clear = ata_bmdma_irq_clear, | 734 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_sl82c105.c b/drivers/ata/pata_sl82c105.c index d118a1822c45..c7770f8df8d3 100644 --- a/drivers/ata/pata_sl82c105.c +++ b/drivers/ata/pata_sl82c105.c | |||
@@ -262,7 +262,7 @@ static struct ata_port_operations sl82c105_port_ops = { | |||
262 | .qc_prep = ata_qc_prep, | 262 | .qc_prep = ata_qc_prep, |
263 | .qc_issue = ata_qc_issue_prot, | 263 | .qc_issue = ata_qc_issue_prot, |
264 | 264 | ||
265 | .data_xfer = ata_pio_data_xfer, | 265 | .data_xfer = ata_data_xfer, |
266 | 266 | ||
267 | .irq_handler = ata_interrupt, | 267 | .irq_handler = ata_interrupt, |
268 | .irq_clear = ata_bmdma_irq_clear, | 268 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_triflex.c b/drivers/ata/pata_triflex.c index 57385a2f8286..60f2eea3c838 100644 --- a/drivers/ata/pata_triflex.c +++ b/drivers/ata/pata_triflex.c | |||
@@ -221,7 +221,7 @@ static struct ata_port_operations triflex_port_ops = { | |||
221 | .qc_prep = ata_qc_prep, | 221 | .qc_prep = ata_qc_prep, |
222 | .qc_issue = ata_qc_issue_prot, | 222 | .qc_issue = ata_qc_issue_prot, |
223 | 223 | ||
224 | .data_xfer = ata_pio_data_xfer, | 224 | .data_xfer = ata_data_xfer, |
225 | 225 | ||
226 | .irq_handler = ata_interrupt, | 226 | .irq_handler = ata_interrupt, |
227 | .irq_clear = ata_bmdma_irq_clear, | 227 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_via.c b/drivers/ata/pata_via.c index 2b262363b96a..236276d6ef3b 100644 --- a/drivers/ata/pata_via.c +++ b/drivers/ata/pata_via.c | |||
@@ -334,7 +334,7 @@ static struct ata_port_operations via_port_ops = { | |||
334 | .qc_prep = ata_qc_prep, | 334 | .qc_prep = ata_qc_prep, |
335 | .qc_issue = ata_qc_issue_prot, | 335 | .qc_issue = ata_qc_issue_prot, |
336 | 336 | ||
337 | .data_xfer = ata_pio_data_xfer, | 337 | .data_xfer = ata_data_xfer, |
338 | 338 | ||
339 | .irq_handler = ata_interrupt, | 339 | .irq_handler = ata_interrupt, |
340 | .irq_clear = ata_bmdma_irq_clear, | 340 | .irq_clear = ata_bmdma_irq_clear, |
@@ -367,7 +367,7 @@ static struct ata_port_operations via_port_ops_noirq = { | |||
367 | .qc_prep = ata_qc_prep, | 367 | .qc_prep = ata_qc_prep, |
368 | .qc_issue = ata_qc_issue_prot, | 368 | .qc_issue = ata_qc_issue_prot, |
369 | 369 | ||
370 | .data_xfer = ata_pio_data_xfer_noirq, | 370 | .data_xfer = ata_data_xfer_noirq, |
371 | 371 | ||
372 | .irq_handler = ata_interrupt, | 372 | .irq_handler = ata_interrupt, |
373 | .irq_clear = ata_bmdma_irq_clear, | 373 | .irq_clear = ata_bmdma_irq_clear, |
diff --git a/drivers/ata/pata_winbond.c b/drivers/ata/pata_winbond.c index bba04a6e3708..d24488bf5644 100644 --- a/drivers/ata/pata_winbond.c +++ b/drivers/ata/pata_winbond.c | |||
@@ -100,22 +100,24 @@ static void winbond_data_xfer(struct ata_device *adev, unsigned char *buf, unsig | |||
100 | 100 | ||
101 | if (ata_id_has_dword_io(adev->id)) { | 101 | if (ata_id_has_dword_io(adev->id)) { |
102 | if (write_data) | 102 | if (write_data) |
103 | outsl(ap->ioaddr.data_addr, buf, buflen >> 2); | 103 | iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
104 | else | 104 | else |
105 | insl(ap->ioaddr.data_addr, buf, buflen >> 2); | 105 | ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
106 | 106 | ||
107 | if (unlikely(slop)) { | 107 | if (unlikely(slop)) { |
108 | u32 pad; | 108 | u32 pad; |
109 | if (write_data) { | 109 | if (write_data) { |
110 | memcpy(&pad, buf + buflen - slop, slop); | 110 | memcpy(&pad, buf + buflen - slop, slop); |
111 | outl(le32_to_cpu(pad), ap->ioaddr.data_addr); | 111 | pad = le32_to_cpu(pad); |
112 | iowrite32(pad, ap->ioaddr.data_addr); | ||
112 | } else { | 113 | } else { |
113 | pad = cpu_to_le16(inl(ap->ioaddr.data_addr)); | 114 | pad = ioread32(ap->ioaddr.data_addr); |
115 | pad = cpu_to_le16(pad); | ||
114 | memcpy(buf + buflen - slop, &pad, slop); | 116 | memcpy(buf + buflen - slop, &pad, slop); |
115 | } | 117 | } |
116 | } | 118 | } |
117 | } else | 119 | } else |
118 | ata_pio_data_xfer(adev, buf, buflen, write_data); | 120 | ata_data_xfer(adev, buf, buflen, write_data); |
119 | } | 121 | } |
120 | 122 | ||
121 | static struct scsi_host_template winbond_sht = { | 123 | static struct scsi_host_template winbond_sht = { |
@@ -197,6 +199,8 @@ static __init int winbond_init_one(unsigned long port) | |||
197 | return 0; | 199 | return 0; |
198 | 200 | ||
199 | for (i = 0; i < 2 ; i ++) { | 201 | for (i = 0; i < 2 ; i ++) { |
202 | unsigned long cmd_port = 0x1F0 - (0x80 * i); | ||
203 | void __iomem *cmd_addr, *ctl_addr; | ||
200 | 204 | ||
201 | if (reg & (1 << i)) { | 205 | if (reg & (1 << i)) { |
202 | /* | 206 | /* |
@@ -207,6 +211,13 @@ static __init int winbond_init_one(unsigned long port) | |||
207 | if (IS_ERR(pdev)) | 211 | if (IS_ERR(pdev)) |
208 | return PTR_ERR(pdev); | 212 | return PTR_ERR(pdev); |
209 | 213 | ||
214 | cmd_addr = devm_ioport_map(&pdev->dev, cmd_port, 8); | ||
215 | ctl_addr = devm_ioport_map(&pdev->dev, cmd_port + 0x0206, 1); | ||
216 | if (!cmd_addr || !ctl_addr) { | ||
217 | platform_device_unregister(pdev); | ||
218 | return -ENOMEM; | ||
219 | } | ||
220 | |||
210 | memset(&ae, 0, sizeof(struct ata_probe_ent)); | 221 | memset(&ae, 0, sizeof(struct ata_probe_ent)); |
211 | INIT_LIST_HEAD(&ae.node); | 222 | INIT_LIST_HEAD(&ae.node); |
212 | ae.dev = &pdev->dev; | 223 | ae.dev = &pdev->dev; |
@@ -220,9 +231,9 @@ static __init int winbond_init_one(unsigned long port) | |||
220 | ae.irq = 14 + i; | 231 | ae.irq = 14 + i; |
221 | ae.irq_flags = 0; | 232 | ae.irq_flags = 0; |
222 | ae.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST; | 233 | ae.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST; |
223 | ae.port[0].cmd_addr = 0x1F0 - (0x80 * i); | 234 | ae.port[0].cmd_addr = cmd_addr; |
224 | ae.port[0].altstatus_addr = ae.port[0].cmd_addr + 0x0206; | 235 | ae.port[0].altstatus_addr = ctl_addr; |
225 | ae.port[0].ctl_addr = ae.port[0].altstatus_addr; | 236 | ae.port[0].ctl_addr = ctl_addr; |
226 | ata_std_ports(&ae.port[0]); | 237 | ata_std_ports(&ae.port[0]); |
227 | /* | 238 | /* |
228 | * Hook in a private data structure per channel | 239 | * Hook in a private data structure per channel |
diff --git a/drivers/ata/pdc_adma.c b/drivers/ata/pdc_adma.c index a6bf7cbdfdc5..71e17df83f48 100644 --- a/drivers/ata/pdc_adma.c +++ b/drivers/ata/pdc_adma.c | |||
@@ -51,9 +51,15 @@ | |||
51 | #define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40)) | 51 | #define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40)) |
52 | 52 | ||
53 | /* macro to calculate base address for ADMA regs */ | 53 | /* macro to calculate base address for ADMA regs */ |
54 | #define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20)) | 54 | #define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20)) |
55 | |||
56 | /* macro to obtain addresses from ata_host */ | ||
57 | #define ADMA_HOST_REGS(host,port_no) \ | ||
58 | ADMA_REGS((host)->iomap[ADMA_MMIO_BAR], port_no) | ||
55 | 59 | ||
56 | enum { | 60 | enum { |
61 | ADMA_MMIO_BAR = 4, | ||
62 | |||
57 | ADMA_PORTS = 2, | 63 | ADMA_PORTS = 2, |
58 | ADMA_CPB_BYTES = 40, | 64 | ADMA_CPB_BYTES = 40, |
59 | ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16, | 65 | ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16, |
@@ -166,7 +172,7 @@ static const struct ata_port_operations adma_ata_ops = { | |||
166 | .qc_prep = adma_qc_prep, | 172 | .qc_prep = adma_qc_prep, |
167 | .qc_issue = adma_qc_issue, | 173 | .qc_issue = adma_qc_issue, |
168 | .eng_timeout = adma_eng_timeout, | 174 | .eng_timeout = adma_eng_timeout, |
169 | .data_xfer = ata_mmio_data_xfer, | 175 | .data_xfer = ata_data_xfer, |
170 | .irq_handler = adma_intr, | 176 | .irq_handler = adma_intr, |
171 | .irq_clear = adma_irq_clear, | 177 | .irq_clear = adma_irq_clear, |
172 | .port_start = adma_port_start, | 178 | .port_start = adma_port_start, |
@@ -234,11 +240,10 @@ static void adma_reset_engine(void __iomem *chan) | |||
234 | static void adma_reinit_engine(struct ata_port *ap) | 240 | static void adma_reinit_engine(struct ata_port *ap) |
235 | { | 241 | { |
236 | struct adma_port_priv *pp = ap->private_data; | 242 | struct adma_port_priv *pp = ap->private_data; |
237 | void __iomem *mmio_base = ap->host->mmio_base; | 243 | void __iomem *chan = ADMA_HOST_REGS(ap->host, ap->port_no); |
238 | void __iomem *chan = ADMA_REGS(mmio_base, ap->port_no); | ||
239 | 244 | ||
240 | /* mask/clear ATA interrupts */ | 245 | /* mask/clear ATA interrupts */ |
241 | writeb(ATA_NIEN, (void __iomem *)ap->ioaddr.ctl_addr); | 246 | writeb(ATA_NIEN, ap->ioaddr.ctl_addr); |
242 | ata_check_status(ap); | 247 | ata_check_status(ap); |
243 | 248 | ||
244 | /* reset the ADMA engine */ | 249 | /* reset the ADMA engine */ |
@@ -262,7 +267,7 @@ static void adma_reinit_engine(struct ata_port *ap) | |||
262 | 267 | ||
263 | static inline void adma_enter_reg_mode(struct ata_port *ap) | 268 | static inline void adma_enter_reg_mode(struct ata_port *ap) |
264 | { | 269 | { |
265 | void __iomem *chan = ADMA_REGS(ap->host->mmio_base, ap->port_no); | 270 | void __iomem *chan = ADMA_HOST_REGS(ap->host, ap->port_no); |
266 | 271 | ||
267 | writew(aPIOMD4, chan + ADMA_CONTROL); | 272 | writew(aPIOMD4, chan + ADMA_CONTROL); |
268 | readb(chan + ADMA_STATUS); /* flush */ | 273 | readb(chan + ADMA_STATUS); /* flush */ |
@@ -409,7 +414,7 @@ static void adma_qc_prep(struct ata_queued_cmd *qc) | |||
409 | static inline void adma_packet_start(struct ata_queued_cmd *qc) | 414 | static inline void adma_packet_start(struct ata_queued_cmd *qc) |
410 | { | 415 | { |
411 | struct ata_port *ap = qc->ap; | 416 | struct ata_port *ap = qc->ap; |
412 | void __iomem *chan = ADMA_REGS(ap->host->mmio_base, ap->port_no); | 417 | void __iomem *chan = ADMA_HOST_REGS(ap->host, ap->port_no); |
413 | 418 | ||
414 | VPRINTK("ENTER, ap %p\n", ap); | 419 | VPRINTK("ENTER, ap %p\n", ap); |
415 | 420 | ||
@@ -442,13 +447,12 @@ static unsigned int adma_qc_issue(struct ata_queued_cmd *qc) | |||
442 | static inline unsigned int adma_intr_pkt(struct ata_host *host) | 447 | static inline unsigned int adma_intr_pkt(struct ata_host *host) |
443 | { | 448 | { |
444 | unsigned int handled = 0, port_no; | 449 | unsigned int handled = 0, port_no; |
445 | u8 __iomem *mmio_base = host->mmio_base; | ||
446 | 450 | ||
447 | for (port_no = 0; port_no < host->n_ports; ++port_no) { | 451 | for (port_no = 0; port_no < host->n_ports; ++port_no) { |
448 | struct ata_port *ap = host->ports[port_no]; | 452 | struct ata_port *ap = host->ports[port_no]; |
449 | struct adma_port_priv *pp; | 453 | struct adma_port_priv *pp; |
450 | struct ata_queued_cmd *qc; | 454 | struct ata_queued_cmd *qc; |
451 | void __iomem *chan = ADMA_REGS(mmio_base, port_no); | 455 | void __iomem *chan = ADMA_HOST_REGS(host, port_no); |
452 | u8 status = readb(chan + ADMA_STATUS); | 456 | u8 status = readb(chan + ADMA_STATUS); |
453 | 457 | ||
454 | if (status == 0) | 458 | if (status == 0) |
@@ -522,7 +526,7 @@ static irqreturn_t adma_intr(int irq, void *dev_instance) | |||
522 | return IRQ_RETVAL(handled); | 526 | return IRQ_RETVAL(handled); |
523 | } | 527 | } |
524 | 528 | ||
525 | static void adma_ata_setup_port(struct ata_ioports *port, unsigned long base) | 529 | static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base) |
526 | { | 530 | { |
527 | port->cmd_addr = | 531 | port->cmd_addr = |
528 | port->data_addr = base + 0x000; | 532 | port->data_addr = base + 0x000; |
@@ -570,7 +574,7 @@ static int adma_port_start(struct ata_port *ap) | |||
570 | 574 | ||
571 | static void adma_port_stop(struct ata_port *ap) | 575 | static void adma_port_stop(struct ata_port *ap) |
572 | { | 576 | { |
573 | adma_reset_engine(ADMA_REGS(ap->host->mmio_base, ap->port_no)); | 577 | adma_reset_engine(ADMA_HOST_REGS(ap->host, ap->port_no)); |
574 | } | 578 | } |
575 | 579 | ||
576 | static void adma_host_stop(struct ata_host *host) | 580 | static void adma_host_stop(struct ata_host *host) |
@@ -578,14 +582,14 @@ static void adma_host_stop(struct ata_host *host) | |||
578 | unsigned int port_no; | 582 | unsigned int port_no; |
579 | 583 | ||
580 | for (port_no = 0; port_no < ADMA_PORTS; ++port_no) | 584 | for (port_no = 0; port_no < ADMA_PORTS; ++port_no) |
581 | adma_reset_engine(ADMA_REGS(host->mmio_base, port_no)); | 585 | adma_reset_engine(ADMA_HOST_REGS(host, port_no)); |
582 | } | 586 | } |
583 | 587 | ||
584 | static void adma_host_init(unsigned int chip_id, | 588 | static void adma_host_init(unsigned int chip_id, |
585 | struct ata_probe_ent *probe_ent) | 589 | struct ata_probe_ent *probe_ent) |
586 | { | 590 | { |
587 | unsigned int port_no; | 591 | unsigned int port_no; |
588 | void __iomem *mmio_base = probe_ent->mmio_base; | 592 | void __iomem *mmio_base = probe_ent->iomap[ADMA_MMIO_BAR]; |
589 | 593 | ||
590 | /* enable/lock aGO operation */ | 594 | /* enable/lock aGO operation */ |
591 | writeb(7, mmio_base + ADMA_MODE_LOCK); | 595 | writeb(7, mmio_base + ADMA_MODE_LOCK); |
@@ -615,7 +619,7 @@ static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base) | |||
615 | } | 619 | } |
616 | 620 | ||
617 | static int adma_ata_init_one(struct pci_dev *pdev, | 621 | static int adma_ata_init_one(struct pci_dev *pdev, |
618 | const struct pci_device_id *ent) | 622 | const struct pci_device_id *ent) |
619 | { | 623 | { |
620 | static int printed_version; | 624 | static int printed_version; |
621 | struct ata_probe_ent *probe_ent = NULL; | 625 | struct ata_probe_ent *probe_ent = NULL; |
@@ -630,16 +634,13 @@ static int adma_ata_init_one(struct pci_dev *pdev, | |||
630 | if (rc) | 634 | if (rc) |
631 | return rc; | 635 | return rc; |
632 | 636 | ||
633 | rc = pci_request_regions(pdev, DRV_NAME); | ||
634 | if (rc) | ||
635 | return rc; | ||
636 | |||
637 | if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) | 637 | if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) |
638 | return -ENODEV; | 638 | return -ENODEV; |
639 | 639 | ||
640 | mmio_base = pcim_iomap(pdev, 4, 0); | 640 | rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME); |
641 | if (mmio_base == NULL) | 641 | if (rc) |
642 | return -ENOMEM; | 642 | return rc; |
643 | mmio_base = pcim_iomap_table(pdev)[ADMA_MMIO_BAR]; | ||
643 | 644 | ||
644 | rc = adma_set_dma_masks(pdev, mmio_base); | 645 | rc = adma_set_dma_masks(pdev, mmio_base); |
645 | if (rc) | 646 | if (rc) |
@@ -661,12 +662,12 @@ static int adma_ata_init_one(struct pci_dev *pdev, | |||
661 | 662 | ||
662 | probe_ent->irq = pdev->irq; | 663 | probe_ent->irq = pdev->irq; |
663 | probe_ent->irq_flags = IRQF_SHARED; | 664 | probe_ent->irq_flags = IRQF_SHARED; |
664 | probe_ent->mmio_base = mmio_base; | ||
665 | probe_ent->n_ports = ADMA_PORTS; | 665 | probe_ent->n_ports = ADMA_PORTS; |
666 | probe_ent->iomap = pcim_iomap_table(pdev); | ||
666 | 667 | ||
667 | for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) { | 668 | for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) { |
668 | adma_ata_setup_port(&probe_ent->port[port_no], | 669 | adma_ata_setup_port(&probe_ent->port[port_no], |
669 | ADMA_ATA_REGS((unsigned long)mmio_base, port_no)); | 670 | ADMA_ATA_REGS(mmio_base, port_no)); |
670 | } | 671 | } |
671 | 672 | ||
672 | pci_set_master(pdev); | 673 | pci_set_master(pdev); |
diff --git a/drivers/ata/sata_inic162x.c b/drivers/ata/sata_inic162x.c index c98e0227a60c..b2a6f77b38d6 100644 --- a/drivers/ata/sata_inic162x.c +++ b/drivers/ata/sata_inic162x.c | |||
@@ -147,7 +147,7 @@ static const int scr_map[] = { | |||
147 | 147 | ||
148 | static void __iomem * inic_port_base(struct ata_port *ap) | 148 | static void __iomem * inic_port_base(struct ata_port *ap) |
149 | { | 149 | { |
150 | return ap->host->mmio_base + ap->port_no * PORT_SIZE; | 150 | return ap->host->iomap[MMIO_BAR] + ap->port_no * PORT_SIZE; |
151 | } | 151 | } |
152 | 152 | ||
153 | static void __inic_set_pirq_mask(struct ata_port *ap, u8 mask) | 153 | static void __inic_set_pirq_mask(struct ata_port *ap, u8 mask) |
@@ -324,7 +324,7 @@ static void inic_host_intr(struct ata_port *ap) | |||
324 | static irqreturn_t inic_interrupt(int irq, void *dev_instance) | 324 | static irqreturn_t inic_interrupt(int irq, void *dev_instance) |
325 | { | 325 | { |
326 | struct ata_host *host = dev_instance; | 326 | struct ata_host *host = dev_instance; |
327 | void __iomem *mmio_base = host->mmio_base; | 327 | void __iomem *mmio_base = host->iomap[MMIO_BAR]; |
328 | u16 host_irq_stat; | 328 | u16 host_irq_stat; |
329 | int i, handled = 0;; | 329 | int i, handled = 0;; |
330 | 330 | ||
@@ -566,7 +566,7 @@ static struct ata_port_operations inic_port_ops = { | |||
566 | 566 | ||
567 | .qc_prep = ata_qc_prep, | 567 | .qc_prep = ata_qc_prep, |
568 | .qc_issue = inic_qc_issue, | 568 | .qc_issue = inic_qc_issue, |
569 | .data_xfer = ata_pio_data_xfer, | 569 | .data_xfer = ata_data_xfer, |
570 | 570 | ||
571 | .freeze = inic_freeze, | 571 | .freeze = inic_freeze, |
572 | .thaw = inic_thaw, | 572 | .thaw = inic_thaw, |
@@ -638,7 +638,7 @@ static int inic_pci_device_resume(struct pci_dev *pdev) | |||
638 | { | 638 | { |
639 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | 639 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
640 | struct inic_host_priv *hpriv = host->private_data; | 640 | struct inic_host_priv *hpriv = host->private_data; |
641 | void __iomem *mmio_base = host->mmio_base; | 641 | void __iomem *mmio_base = host->iomap[MMIO_BAR]; |
642 | int rc; | 642 | int rc; |
643 | 643 | ||
644 | ata_pci_device_do_resume(pdev); | 644 | ata_pci_device_do_resume(pdev); |
@@ -661,7 +661,7 @@ static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
661 | struct ata_port_info *pinfo = &inic_port_info; | 661 | struct ata_port_info *pinfo = &inic_port_info; |
662 | struct ata_probe_ent *probe_ent; | 662 | struct ata_probe_ent *probe_ent; |
663 | struct inic_host_priv *hpriv; | 663 | struct inic_host_priv *hpriv; |
664 | void __iomem *mmio_base; | 664 | void __iomem * const *iomap; |
665 | int i, rc; | 665 | int i, rc; |
666 | 666 | ||
667 | if (!printed_version++) | 667 | if (!printed_version++) |
@@ -675,9 +675,10 @@ static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
675 | if (rc) | 675 | if (rc) |
676 | return rc; | 676 | return rc; |
677 | 677 | ||
678 | mmio_base = pci_iomap(pdev, MMIO_BAR, 0); | 678 | rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME); |
679 | if (!mmio_base) | 679 | if (rc) |
680 | return -ENOMEM; | 680 | return rc; |
681 | iomap = pcim_iomap_table(pdev); | ||
681 | 682 | ||
682 | /* Set dma_mask. This devices doesn't support 64bit addressing. */ | 683 | /* Set dma_mask. This devices doesn't support 64bit addressing. */ |
683 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | 684 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
@@ -713,26 +714,25 @@ static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
713 | probe_ent->irq = pdev->irq; | 714 | probe_ent->irq = pdev->irq; |
714 | probe_ent->irq_flags = SA_SHIRQ; | 715 | probe_ent->irq_flags = SA_SHIRQ; |
715 | 716 | ||
716 | probe_ent->mmio_base = mmio_base; | 717 | probe_ent->iomap = iomap; |
717 | 718 | ||
718 | for (i = 0; i < NR_PORTS; i++) { | 719 | for (i = 0; i < NR_PORTS; i++) { |
719 | struct ata_ioports *port = &probe_ent->port[i]; | 720 | struct ata_ioports *port = &probe_ent->port[i]; |
720 | unsigned long port_base = | 721 | void __iomem *port_base = iomap[MMIO_BAR] + i * PORT_SIZE; |
721 | (unsigned long)mmio_base + i * PORT_SIZE; | ||
722 | 722 | ||
723 | port->cmd_addr = pci_resource_start(pdev, 2 * i); | 723 | port->cmd_addr = iomap[2 * i]; |
724 | port->altstatus_addr = | 724 | port->altstatus_addr = |
725 | port->ctl_addr = | 725 | port->ctl_addr = (void __iomem *) |
726 | pci_resource_start(pdev, 2 * i + 1) | ATA_PCI_CTL_OFS; | 726 | ((unsigned long)iomap[2 * i + 1] | ATA_PCI_CTL_OFS); |
727 | port->scr_addr = port_base + PORT_SCR; | 727 | port->scr_addr = port_base + PORT_SCR; |
728 | 728 | ||
729 | ata_std_ports(port); | 729 | ata_std_ports(port); |
730 | } | 730 | } |
731 | 731 | ||
732 | probe_ent->private_data = hpriv; | 732 | probe_ent->private_data = hpriv; |
733 | hpriv->cached_hctl = readw(mmio_base + HOST_CTL); | 733 | hpriv->cached_hctl = readw(iomap[MMIO_BAR] + HOST_CTL); |
734 | 734 | ||
735 | rc = init_controller(mmio_base, hpriv->cached_hctl); | 735 | rc = init_controller(iomap[MMIO_BAR], hpriv->cached_hctl); |
736 | if (rc) { | 736 | if (rc) { |
737 | dev_printk(KERN_ERR, &pdev->dev, | 737 | dev_printk(KERN_ERR, &pdev->dev, |
738 | "failed to initialize controller\n"); | 738 | "failed to initialize controller\n"); |
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index c073e453dcdd..7c578c275db0 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c | |||
@@ -404,7 +404,7 @@ static const struct ata_port_operations mv5_ops = { | |||
404 | 404 | ||
405 | .qc_prep = mv_qc_prep, | 405 | .qc_prep = mv_qc_prep, |
406 | .qc_issue = mv_qc_issue, | 406 | .qc_issue = mv_qc_issue, |
407 | .data_xfer = ata_mmio_data_xfer, | 407 | .data_xfer = ata_data_xfer, |
408 | 408 | ||
409 | .eng_timeout = mv_eng_timeout, | 409 | .eng_timeout = mv_eng_timeout, |
410 | 410 | ||
@@ -431,7 +431,7 @@ static const struct ata_port_operations mv6_ops = { | |||
431 | 431 | ||
432 | .qc_prep = mv_qc_prep, | 432 | .qc_prep = mv_qc_prep, |
433 | .qc_issue = mv_qc_issue, | 433 | .qc_issue = mv_qc_issue, |
434 | .data_xfer = ata_mmio_data_xfer, | 434 | .data_xfer = ata_data_xfer, |
435 | 435 | ||
436 | .eng_timeout = mv_eng_timeout, | 436 | .eng_timeout = mv_eng_timeout, |
437 | 437 | ||
@@ -458,7 +458,7 @@ static const struct ata_port_operations mv_iie_ops = { | |||
458 | 458 | ||
459 | .qc_prep = mv_qc_prep_iie, | 459 | .qc_prep = mv_qc_prep_iie, |
460 | .qc_issue = mv_qc_issue, | 460 | .qc_issue = mv_qc_issue, |
461 | .data_xfer = ata_mmio_data_xfer, | 461 | .data_xfer = ata_data_xfer, |
462 | 462 | ||
463 | .eng_timeout = mv_eng_timeout, | 463 | .eng_timeout = mv_eng_timeout, |
464 | 464 | ||
@@ -615,7 +615,7 @@ static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) | |||
615 | 615 | ||
616 | static inline void __iomem *mv_ap_base(struct ata_port *ap) | 616 | static inline void __iomem *mv_ap_base(struct ata_port *ap) |
617 | { | 617 | { |
618 | return mv_port_base(ap->host->mmio_base, ap->port_no); | 618 | return mv_port_base(ap->host->iomap[MV_PRIMARY_BAR], ap->port_no); |
619 | } | 619 | } |
620 | 620 | ||
621 | static inline int mv_get_hc_count(unsigned long port_flags) | 621 | static inline int mv_get_hc_count(unsigned long port_flags) |
@@ -1299,7 +1299,7 @@ static void mv_err_intr(struct ata_port *ap, int reset_allowed) | |||
1299 | */ | 1299 | */ |
1300 | static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc) | 1300 | static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc) |
1301 | { | 1301 | { |
1302 | void __iomem *mmio = host->mmio_base; | 1302 | void __iomem *mmio = host->iomap[MV_PRIMARY_BAR]; |
1303 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); | 1303 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
1304 | struct ata_queued_cmd *qc; | 1304 | struct ata_queued_cmd *qc; |
1305 | u32 hc_irq_cause; | 1305 | u32 hc_irq_cause; |
@@ -1342,8 +1342,7 @@ static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc) | |||
1342 | } else { | 1342 | } else { |
1343 | /* PIO: check for device (drive) interrupt */ | 1343 | /* PIO: check for device (drive) interrupt */ |
1344 | if ((DEV_IRQ << hard_port) & hc_irq_cause) { | 1344 | if ((DEV_IRQ << hard_port) & hc_irq_cause) { |
1345 | ata_status = readb((void __iomem *) | 1345 | ata_status = readb(ap->ioaddr.status_addr); |
1346 | ap->ioaddr.status_addr); | ||
1347 | handled = 1; | 1346 | handled = 1; |
1348 | /* ignore spurious intr if drive still BUSY */ | 1347 | /* ignore spurious intr if drive still BUSY */ |
1349 | if (ata_status & ATA_BUSY) { | 1348 | if (ata_status & ATA_BUSY) { |
@@ -1403,7 +1402,7 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance) | |||
1403 | { | 1402 | { |
1404 | struct ata_host *host = dev_instance; | 1403 | struct ata_host *host = dev_instance; |
1405 | unsigned int hc, handled = 0, n_hcs; | 1404 | unsigned int hc, handled = 0, n_hcs; |
1406 | void __iomem *mmio = host->mmio_base; | 1405 | void __iomem *mmio = host->iomap[MV_PRIMARY_BAR]; |
1407 | struct mv_host_priv *hpriv; | 1406 | struct mv_host_priv *hpriv; |
1408 | u32 irq_stat; | 1407 | u32 irq_stat; |
1409 | 1408 | ||
@@ -1479,22 +1478,24 @@ static unsigned int mv5_scr_offset(unsigned int sc_reg_in) | |||
1479 | 1478 | ||
1480 | static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in) | 1479 | static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in) |
1481 | { | 1480 | { |
1482 | void __iomem *mmio = mv5_phy_base(ap->host->mmio_base, ap->port_no); | 1481 | void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; |
1482 | void __iomem *addr = mv5_phy_base(mmio, ap->port_no); | ||
1483 | unsigned int ofs = mv5_scr_offset(sc_reg_in); | 1483 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
1484 | 1484 | ||
1485 | if (ofs != 0xffffffffU) | 1485 | if (ofs != 0xffffffffU) |
1486 | return readl(mmio + ofs); | 1486 | return readl(addr + ofs); |
1487 | else | 1487 | else |
1488 | return (u32) ofs; | 1488 | return (u32) ofs; |
1489 | } | 1489 | } |
1490 | 1490 | ||
1491 | static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) | 1491 | static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) |
1492 | { | 1492 | { |
1493 | void __iomem *mmio = mv5_phy_base(ap->host->mmio_base, ap->port_no); | 1493 | void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; |
1494 | void __iomem *addr = mv5_phy_base(mmio, ap->port_no); | ||
1494 | unsigned int ofs = mv5_scr_offset(sc_reg_in); | 1495 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
1495 | 1496 | ||
1496 | if (ofs != 0xffffffffU) | 1497 | if (ofs != 0xffffffffU) |
1497 | writelfl(val, mmio + ofs); | 1498 | writelfl(val, addr + ofs); |
1498 | } | 1499 | } |
1499 | 1500 | ||
1500 | static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio) | 1501 | static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio) |
@@ -1856,7 +1857,7 @@ static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio, | |||
1856 | static void mv_stop_and_reset(struct ata_port *ap) | 1857 | static void mv_stop_and_reset(struct ata_port *ap) |
1857 | { | 1858 | { |
1858 | struct mv_host_priv *hpriv = ap->host->private_data; | 1859 | struct mv_host_priv *hpriv = ap->host->private_data; |
1859 | void __iomem *mmio = ap->host->mmio_base; | 1860 | void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; |
1860 | 1861 | ||
1861 | mv_stop_dma(ap); | 1862 | mv_stop_dma(ap); |
1862 | 1863 | ||
@@ -1954,10 +1955,10 @@ comreset_retry: | |||
1954 | break; | 1955 | break; |
1955 | } | 1956 | } |
1956 | 1957 | ||
1957 | tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr); | 1958 | tf.lbah = readb(ap->ioaddr.lbah_addr); |
1958 | tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr); | 1959 | tf.lbam = readb(ap->ioaddr.lbam_addr); |
1959 | tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr); | 1960 | tf.lbal = readb(ap->ioaddr.lbal_addr); |
1960 | tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr); | 1961 | tf.nsect = readb(ap->ioaddr.nsect_addr); |
1961 | 1962 | ||
1962 | dev->class = ata_dev_classify(&tf); | 1963 | dev->class = ata_dev_classify(&tf); |
1963 | if (!ata_dev_enabled(dev)) { | 1964 | if (!ata_dev_enabled(dev)) { |
@@ -1989,17 +1990,17 @@ static void mv_phy_reset(struct ata_port *ap) | |||
1989 | */ | 1990 | */ |
1990 | static void mv_eng_timeout(struct ata_port *ap) | 1991 | static void mv_eng_timeout(struct ata_port *ap) |
1991 | { | 1992 | { |
1993 | void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; | ||
1992 | struct ata_queued_cmd *qc; | 1994 | struct ata_queued_cmd *qc; |
1993 | unsigned long flags; | 1995 | unsigned long flags; |
1994 | 1996 | ||
1995 | ata_port_printk(ap, KERN_ERR, "Entering mv_eng_timeout\n"); | 1997 | ata_port_printk(ap, KERN_ERR, "Entering mv_eng_timeout\n"); |
1996 | DPRINTK("All regs @ start of eng_timeout\n"); | 1998 | DPRINTK("All regs @ start of eng_timeout\n"); |
1997 | mv_dump_all_regs(ap->host->mmio_base, ap->port_no, | 1999 | mv_dump_all_regs(mmio, ap->port_no, to_pci_dev(ap->host->dev)); |
1998 | to_pci_dev(ap->host->dev)); | ||
1999 | 2000 | ||
2000 | qc = ata_qc_from_tag(ap, ap->active_tag); | 2001 | qc = ata_qc_from_tag(ap, ap->active_tag); |
2001 | printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n", | 2002 | printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n", |
2002 | ap->host->mmio_base, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd); | 2003 | mmio, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd); |
2003 | 2004 | ||
2004 | spin_lock_irqsave(&ap->host->lock, flags); | 2005 | spin_lock_irqsave(&ap->host->lock, flags); |
2005 | mv_err_intr(ap, 0); | 2006 | mv_err_intr(ap, 0); |
@@ -2027,7 +2028,7 @@ static void mv_eng_timeout(struct ata_port *ap) | |||
2027 | */ | 2028 | */ |
2028 | static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) | 2029 | static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) |
2029 | { | 2030 | { |
2030 | unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS; | 2031 | void __iomem *shd_base = port_mmio + SHD_BLK_OFS; |
2031 | unsigned serr_ofs; | 2032 | unsigned serr_ofs; |
2032 | 2033 | ||
2033 | /* PIO related setup | 2034 | /* PIO related setup |
@@ -2175,7 +2176,7 @@ static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent, | |||
2175 | unsigned int board_idx) | 2176 | unsigned int board_idx) |
2176 | { | 2177 | { |
2177 | int rc = 0, n_hc, port, hc; | 2178 | int rc = 0, n_hc, port, hc; |
2178 | void __iomem *mmio = probe_ent->mmio_base; | 2179 | void __iomem *mmio = probe_ent->iomap[MV_PRIMARY_BAR]; |
2179 | struct mv_host_priv *hpriv = probe_ent->private_data; | 2180 | struct mv_host_priv *hpriv = probe_ent->private_data; |
2180 | 2181 | ||
2181 | /* global interrupt mask */ | 2182 | /* global interrupt mask */ |
@@ -2297,7 +2298,6 @@ static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
2297 | struct ata_probe_ent *probe_ent; | 2298 | struct ata_probe_ent *probe_ent; |
2298 | struct mv_host_priv *hpriv; | 2299 | struct mv_host_priv *hpriv; |
2299 | unsigned int board_idx = (unsigned int)ent->driver_data; | 2300 | unsigned int board_idx = (unsigned int)ent->driver_data; |
2300 | void __iomem *mmio_base; | ||
2301 | int rc; | 2301 | int rc; |
2302 | 2302 | ||
2303 | if (!printed_version++) | 2303 | if (!printed_version++) |
@@ -2308,11 +2308,11 @@ static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
2308 | return rc; | 2308 | return rc; |
2309 | pci_set_master(pdev); | 2309 | pci_set_master(pdev); |
2310 | 2310 | ||
2311 | rc = pci_request_regions(pdev, DRV_NAME); | 2311 | rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); |
2312 | if (rc) { | 2312 | if (rc == -EBUSY) |
2313 | pcim_pin_device(pdev); | 2313 | pcim_pin_device(pdev); |
2314 | if (rc) | ||
2314 | return rc; | 2315 | return rc; |
2315 | } | ||
2316 | 2316 | ||
2317 | probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL); | 2317 | probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL); |
2318 | if (probe_ent == NULL) | 2318 | if (probe_ent == NULL) |
@@ -2321,10 +2321,6 @@ static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
2321 | probe_ent->dev = pci_dev_to_dev(pdev); | 2321 | probe_ent->dev = pci_dev_to_dev(pdev); |
2322 | INIT_LIST_HEAD(&probe_ent->node); | 2322 | INIT_LIST_HEAD(&probe_ent->node); |
2323 | 2323 | ||
2324 | mmio_base = pcim_iomap(pdev, MV_PRIMARY_BAR, 0); | ||
2325 | if (mmio_base == NULL) | ||
2326 | return -ENOMEM; | ||
2327 | |||
2328 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); | 2324 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
2329 | if (!hpriv) | 2325 | if (!hpriv) |
2330 | return -ENOMEM; | 2326 | return -ENOMEM; |
@@ -2337,7 +2333,7 @@ static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
2337 | 2333 | ||
2338 | probe_ent->irq = pdev->irq; | 2334 | probe_ent->irq = pdev->irq; |
2339 | probe_ent->irq_flags = IRQF_SHARED; | 2335 | probe_ent->irq_flags = IRQF_SHARED; |
2340 | probe_ent->mmio_base = mmio_base; | 2336 | probe_ent->iomap = pcim_iomap_table(pdev); |
2341 | probe_ent->private_data = hpriv; | 2337 | probe_ent->private_data = hpriv; |
2342 | 2338 | ||
2343 | /* initialize adapter */ | 2339 | /* initialize adapter */ |
diff --git a/drivers/ata/sata_nv.c b/drivers/ata/sata_nv.c index 18361a38aee7..b9ef6f5f4024 100644 --- a/drivers/ata/sata_nv.c +++ b/drivers/ata/sata_nv.c | |||
@@ -54,6 +54,8 @@ | |||
54 | #define NV_ADMA_DMA_BOUNDARY 0xffffffffUL | 54 | #define NV_ADMA_DMA_BOUNDARY 0xffffffffUL |
55 | 55 | ||
56 | enum { | 56 | enum { |
57 | NV_MMIO_BAR = 5, | ||
58 | |||
57 | NV_PORTS = 2, | 59 | NV_PORTS = 2, |
58 | NV_PIO_MASK = 0x1f, | 60 | NV_PIO_MASK = 0x1f, |
59 | NV_MWDMA_MASK = 0x07, | 61 | NV_MWDMA_MASK = 0x07, |
@@ -357,7 +359,7 @@ static const struct ata_port_operations nv_generic_ops = { | |||
357 | .thaw = ata_bmdma_thaw, | 359 | .thaw = ata_bmdma_thaw, |
358 | .error_handler = nv_error_handler, | 360 | .error_handler = nv_error_handler, |
359 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | 361 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
360 | .data_xfer = ata_pio_data_xfer, | 362 | .data_xfer = ata_data_xfer, |
361 | .irq_handler = nv_generic_interrupt, | 363 | .irq_handler = nv_generic_interrupt, |
362 | .irq_clear = ata_bmdma_irq_clear, | 364 | .irq_clear = ata_bmdma_irq_clear, |
363 | .scr_read = nv_scr_read, | 365 | .scr_read = nv_scr_read, |
@@ -382,7 +384,7 @@ static const struct ata_port_operations nv_nf2_ops = { | |||
382 | .thaw = nv_nf2_thaw, | 384 | .thaw = nv_nf2_thaw, |
383 | .error_handler = nv_error_handler, | 385 | .error_handler = nv_error_handler, |
384 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | 386 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
385 | .data_xfer = ata_pio_data_xfer, | 387 | .data_xfer = ata_data_xfer, |
386 | .irq_handler = nv_nf2_interrupt, | 388 | .irq_handler = nv_nf2_interrupt, |
387 | .irq_clear = ata_bmdma_irq_clear, | 389 | .irq_clear = ata_bmdma_irq_clear, |
388 | .scr_read = nv_scr_read, | 390 | .scr_read = nv_scr_read, |
@@ -407,7 +409,7 @@ static const struct ata_port_operations nv_ck804_ops = { | |||
407 | .thaw = nv_ck804_thaw, | 409 | .thaw = nv_ck804_thaw, |
408 | .error_handler = nv_error_handler, | 410 | .error_handler = nv_error_handler, |
409 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | 411 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
410 | .data_xfer = ata_pio_data_xfer, | 412 | .data_xfer = ata_data_xfer, |
411 | .irq_handler = nv_ck804_interrupt, | 413 | .irq_handler = nv_ck804_interrupt, |
412 | .irq_clear = ata_bmdma_irq_clear, | 414 | .irq_clear = ata_bmdma_irq_clear, |
413 | .scr_read = nv_scr_read, | 415 | .scr_read = nv_scr_read, |
@@ -434,7 +436,7 @@ static const struct ata_port_operations nv_adma_ops = { | |||
434 | .thaw = nv_ck804_thaw, | 436 | .thaw = nv_ck804_thaw, |
435 | .error_handler = nv_adma_error_handler, | 437 | .error_handler = nv_adma_error_handler, |
436 | .post_internal_cmd = nv_adma_bmdma_stop, | 438 | .post_internal_cmd = nv_adma_bmdma_stop, |
437 | .data_xfer = ata_mmio_data_xfer, | 439 | .data_xfer = ata_data_xfer, |
438 | .irq_handler = nv_adma_interrupt, | 440 | .irq_handler = nv_adma_interrupt, |
439 | .irq_clear = nv_adma_irq_clear, | 441 | .irq_clear = nv_adma_irq_clear, |
440 | .scr_read = nv_scr_read, | 442 | .scr_read = nv_scr_read, |
@@ -736,7 +738,7 @@ static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance) | |||
736 | 738 | ||
737 | /* if in ATA register mode, use standard ata interrupt handler */ | 739 | /* if in ATA register mode, use standard ata interrupt handler */ |
738 | if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) { | 740 | if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) { |
739 | u8 irq_stat = readb(host->mmio_base + NV_INT_STATUS_CK804) | 741 | u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804) |
740 | >> (NV_INT_PORT_SHIFT * i); | 742 | >> (NV_INT_PORT_SHIFT * i); |
741 | if(ata_tag_valid(ap->active_tag)) | 743 | if(ata_tag_valid(ap->active_tag)) |
742 | /** NV_INT_DEV indication seems unreliable at times | 744 | /** NV_INT_DEV indication seems unreliable at times |
@@ -827,7 +829,7 @@ static void nv_adma_irq_clear(struct ata_port *ap) | |||
827 | u16 status = readw(mmio + NV_ADMA_STAT); | 829 | u16 status = readw(mmio + NV_ADMA_STAT); |
828 | u32 notifier = readl(mmio + NV_ADMA_NOTIFIER); | 830 | u32 notifier = readl(mmio + NV_ADMA_NOTIFIER); |
829 | u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR); | 831 | u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR); |
830 | unsigned long dma_stat_addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS; | 832 | void __iomem *dma_stat_addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS; |
831 | 833 | ||
832 | /* clear ADMA status */ | 834 | /* clear ADMA status */ |
833 | writew(status, mmio + NV_ADMA_STAT); | 835 | writew(status, mmio + NV_ADMA_STAT); |
@@ -835,7 +837,7 @@ static void nv_adma_irq_clear(struct ata_port *ap) | |||
835 | pp->notifier_clear_block); | 837 | pp->notifier_clear_block); |
836 | 838 | ||
837 | /** clear legacy status */ | 839 | /** clear legacy status */ |
838 | outb(inb(dma_stat_addr), dma_stat_addr); | 840 | iowrite8(ioread8(dma_stat_addr), dma_stat_addr); |
839 | } | 841 | } |
840 | 842 | ||
841 | static void nv_adma_bmdma_setup(struct ata_queued_cmd *qc) | 843 | static void nv_adma_bmdma_setup(struct ata_queued_cmd *qc) |
@@ -851,15 +853,15 @@ static void nv_adma_bmdma_setup(struct ata_queued_cmd *qc) | |||
851 | } | 853 | } |
852 | 854 | ||
853 | /* load PRD table addr. */ | 855 | /* load PRD table addr. */ |
854 | outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); | 856 | iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); |
855 | 857 | ||
856 | /* specify data direction, triple-check start bit is clear */ | 858 | /* specify data direction, triple-check start bit is clear */ |
857 | dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | 859 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
858 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | 860 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); |
859 | if (!rw) | 861 | if (!rw) |
860 | dmactl |= ATA_DMA_WR; | 862 | dmactl |= ATA_DMA_WR; |
861 | 863 | ||
862 | outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | 864 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
863 | 865 | ||
864 | /* issue r/w command */ | 866 | /* issue r/w command */ |
865 | ata_exec_command(ap, &qc->tf); | 867 | ata_exec_command(ap, &qc->tf); |
@@ -877,9 +879,9 @@ static void nv_adma_bmdma_start(struct ata_queued_cmd *qc) | |||
877 | } | 879 | } |
878 | 880 | ||
879 | /* start host DMA transaction */ | 881 | /* start host DMA transaction */ |
880 | dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | 882 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
881 | outb(dmactl | ATA_DMA_START, | 883 | iowrite8(dmactl | ATA_DMA_START, |
882 | ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | 884 | ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
883 | } | 885 | } |
884 | 886 | ||
885 | static void nv_adma_bmdma_stop(struct ata_queued_cmd *qc) | 887 | static void nv_adma_bmdma_stop(struct ata_queued_cmd *qc) |
@@ -891,8 +893,8 @@ static void nv_adma_bmdma_stop(struct ata_queued_cmd *qc) | |||
891 | return; | 893 | return; |
892 | 894 | ||
893 | /* clear start/stop bit */ | 895 | /* clear start/stop bit */ |
894 | outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START, | 896 | iowrite8(ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START, |
895 | ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | 897 | ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
896 | 898 | ||
897 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | 899 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ |
898 | ata_altstatus(ap); /* dummy read */ | 900 | ata_altstatus(ap); /* dummy read */ |
@@ -904,7 +906,7 @@ static u8 nv_adma_bmdma_status(struct ata_port *ap) | |||
904 | 906 | ||
905 | WARN_ON(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)); | 907 | WARN_ON(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)); |
906 | 908 | ||
907 | return inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | 909 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); |
908 | } | 910 | } |
909 | 911 | ||
910 | static int nv_adma_port_start(struct ata_port *ap) | 912 | static int nv_adma_port_start(struct ata_port *ap) |
@@ -927,10 +929,10 @@ static int nv_adma_port_start(struct ata_port *ap) | |||
927 | if (!pp) | 929 | if (!pp) |
928 | return -ENOMEM; | 930 | return -ENOMEM; |
929 | 931 | ||
930 | mmio = ap->host->mmio_base + NV_ADMA_PORT + | 932 | mmio = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_PORT + |
931 | ap->port_no * NV_ADMA_PORT_SIZE; | 933 | ap->port_no * NV_ADMA_PORT_SIZE; |
932 | pp->ctl_block = mmio; | 934 | pp->ctl_block = mmio; |
933 | pp->gen_block = ap->host->mmio_base + NV_ADMA_GEN; | 935 | pp->gen_block = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_GEN; |
934 | pp->notifier_clear_block = pp->gen_block + | 936 | pp->notifier_clear_block = pp->gen_block + |
935 | NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no); | 937 | NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no); |
936 | 938 | ||
@@ -1046,26 +1048,26 @@ static int nv_adma_port_resume(struct ata_port *ap) | |||
1046 | 1048 | ||
1047 | static void nv_adma_setup_port(struct ata_probe_ent *probe_ent, unsigned int port) | 1049 | static void nv_adma_setup_port(struct ata_probe_ent *probe_ent, unsigned int port) |
1048 | { | 1050 | { |
1049 | void __iomem *mmio = probe_ent->mmio_base; | 1051 | void __iomem *mmio = probe_ent->iomap[NV_MMIO_BAR]; |
1050 | struct ata_ioports *ioport = &probe_ent->port[port]; | 1052 | struct ata_ioports *ioport = &probe_ent->port[port]; |
1051 | 1053 | ||
1052 | VPRINTK("ENTER\n"); | 1054 | VPRINTK("ENTER\n"); |
1053 | 1055 | ||
1054 | mmio += NV_ADMA_PORT + port * NV_ADMA_PORT_SIZE; | 1056 | mmio += NV_ADMA_PORT + port * NV_ADMA_PORT_SIZE; |
1055 | 1057 | ||
1056 | ioport->cmd_addr = (unsigned long) mmio; | 1058 | ioport->cmd_addr = mmio; |
1057 | ioport->data_addr = (unsigned long) mmio + (ATA_REG_DATA * 4); | 1059 | ioport->data_addr = mmio + (ATA_REG_DATA * 4); |
1058 | ioport->error_addr = | 1060 | ioport->error_addr = |
1059 | ioport->feature_addr = (unsigned long) mmio + (ATA_REG_ERR * 4); | 1061 | ioport->feature_addr = mmio + (ATA_REG_ERR * 4); |
1060 | ioport->nsect_addr = (unsigned long) mmio + (ATA_REG_NSECT * 4); | 1062 | ioport->nsect_addr = mmio + (ATA_REG_NSECT * 4); |
1061 | ioport->lbal_addr = (unsigned long) mmio + (ATA_REG_LBAL * 4); | 1063 | ioport->lbal_addr = mmio + (ATA_REG_LBAL * 4); |
1062 | ioport->lbam_addr = (unsigned long) mmio + (ATA_REG_LBAM * 4); | 1064 | ioport->lbam_addr = mmio + (ATA_REG_LBAM * 4); |
1063 | ioport->lbah_addr = (unsigned long) mmio + (ATA_REG_LBAH * 4); | 1065 | ioport->lbah_addr = mmio + (ATA_REG_LBAH * 4); |
1064 | ioport->device_addr = (unsigned long) mmio + (ATA_REG_DEVICE * 4); | 1066 | ioport->device_addr = mmio + (ATA_REG_DEVICE * 4); |
1065 | ioport->status_addr = | 1067 | ioport->status_addr = |
1066 | ioport->command_addr = (unsigned long) mmio + (ATA_REG_STATUS * 4); | 1068 | ioport->command_addr = mmio + (ATA_REG_STATUS * 4); |
1067 | ioport->altstatus_addr = | 1069 | ioport->altstatus_addr = |
1068 | ioport->ctl_addr = (unsigned long) mmio + 0x20; | 1070 | ioport->ctl_addr = mmio + 0x20; |
1069 | } | 1071 | } |
1070 | 1072 | ||
1071 | static int nv_adma_host_init(struct ata_probe_ent *probe_ent) | 1073 | static int nv_adma_host_init(struct ata_probe_ent *probe_ent) |
@@ -1252,7 +1254,7 @@ static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance) | |||
1252 | irqreturn_t ret; | 1254 | irqreturn_t ret; |
1253 | 1255 | ||
1254 | spin_lock(&host->lock); | 1256 | spin_lock(&host->lock); |
1255 | irq_stat = inb(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS); | 1257 | irq_stat = ioread8(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS); |
1256 | ret = nv_do_interrupt(host, irq_stat); | 1258 | ret = nv_do_interrupt(host, irq_stat); |
1257 | spin_unlock(&host->lock); | 1259 | spin_unlock(&host->lock); |
1258 | 1260 | ||
@@ -1266,7 +1268,7 @@ static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance) | |||
1266 | irqreturn_t ret; | 1268 | irqreturn_t ret; |
1267 | 1269 | ||
1268 | spin_lock(&host->lock); | 1270 | spin_lock(&host->lock); |
1269 | irq_stat = readb(host->mmio_base + NV_INT_STATUS_CK804); | 1271 | irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804); |
1270 | ret = nv_do_interrupt(host, irq_stat); | 1272 | ret = nv_do_interrupt(host, irq_stat); |
1271 | spin_unlock(&host->lock); | 1273 | spin_unlock(&host->lock); |
1272 | 1274 | ||
@@ -1278,7 +1280,7 @@ static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg) | |||
1278 | if (sc_reg > SCR_CONTROL) | 1280 | if (sc_reg > SCR_CONTROL) |
1279 | return 0xffffffffU; | 1281 | return 0xffffffffU; |
1280 | 1282 | ||
1281 | return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4)); | 1283 | return ioread32(ap->ioaddr.scr_addr + (sc_reg * 4)); |
1282 | } | 1284 | } |
1283 | 1285 | ||
1284 | static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | 1286 | static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) |
@@ -1286,36 +1288,36 @@ static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |||
1286 | if (sc_reg > SCR_CONTROL) | 1288 | if (sc_reg > SCR_CONTROL) |
1287 | return; | 1289 | return; |
1288 | 1290 | ||
1289 | iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4)); | 1291 | iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
1290 | } | 1292 | } |
1291 | 1293 | ||
1292 | static void nv_nf2_freeze(struct ata_port *ap) | 1294 | static void nv_nf2_freeze(struct ata_port *ap) |
1293 | { | 1295 | { |
1294 | unsigned long scr_addr = ap->host->ports[0]->ioaddr.scr_addr; | 1296 | void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr; |
1295 | int shift = ap->port_no * NV_INT_PORT_SHIFT; | 1297 | int shift = ap->port_no * NV_INT_PORT_SHIFT; |
1296 | u8 mask; | 1298 | u8 mask; |
1297 | 1299 | ||
1298 | mask = inb(scr_addr + NV_INT_ENABLE); | 1300 | mask = ioread8(scr_addr + NV_INT_ENABLE); |
1299 | mask &= ~(NV_INT_ALL << shift); | 1301 | mask &= ~(NV_INT_ALL << shift); |
1300 | outb(mask, scr_addr + NV_INT_ENABLE); | 1302 | iowrite8(mask, scr_addr + NV_INT_ENABLE); |
1301 | } | 1303 | } |
1302 | 1304 | ||
1303 | static void nv_nf2_thaw(struct ata_port *ap) | 1305 | static void nv_nf2_thaw(struct ata_port *ap) |
1304 | { | 1306 | { |
1305 | unsigned long scr_addr = ap->host->ports[0]->ioaddr.scr_addr; | 1307 | void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr; |
1306 | int shift = ap->port_no * NV_INT_PORT_SHIFT; | 1308 | int shift = ap->port_no * NV_INT_PORT_SHIFT; |
1307 | u8 mask; | 1309 | u8 mask; |
1308 | 1310 | ||
1309 | outb(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS); | 1311 | iowrite8(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS); |
1310 | 1312 | ||
1311 | mask = inb(scr_addr + NV_INT_ENABLE); | 1313 | mask = ioread8(scr_addr + NV_INT_ENABLE); |
1312 | mask |= (NV_INT_MASK << shift); | 1314 | mask |= (NV_INT_MASK << shift); |
1313 | outb(mask, scr_addr + NV_INT_ENABLE); | 1315 | iowrite8(mask, scr_addr + NV_INT_ENABLE); |
1314 | } | 1316 | } |
1315 | 1317 | ||
1316 | static void nv_ck804_freeze(struct ata_port *ap) | 1318 | static void nv_ck804_freeze(struct ata_port *ap) |
1317 | { | 1319 | { |
1318 | void __iomem *mmio_base = ap->host->mmio_base; | 1320 | void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR]; |
1319 | int shift = ap->port_no * NV_INT_PORT_SHIFT; | 1321 | int shift = ap->port_no * NV_INT_PORT_SHIFT; |
1320 | u8 mask; | 1322 | u8 mask; |
1321 | 1323 | ||
@@ -1326,7 +1328,7 @@ static void nv_ck804_freeze(struct ata_port *ap) | |||
1326 | 1328 | ||
1327 | static void nv_ck804_thaw(struct ata_port *ap) | 1329 | static void nv_ck804_thaw(struct ata_port *ap) |
1328 | { | 1330 | { |
1329 | void __iomem *mmio_base = ap->host->mmio_base; | 1331 | void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR]; |
1330 | int shift = ap->port_no * NV_INT_PORT_SHIFT; | 1332 | int shift = ap->port_no * NV_INT_PORT_SHIFT; |
1331 | u8 mask; | 1333 | u8 mask; |
1332 | 1334 | ||
@@ -1412,7 +1414,7 @@ static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1412 | struct nv_host_priv *hpriv; | 1414 | struct nv_host_priv *hpriv; |
1413 | int rc; | 1415 | int rc; |
1414 | u32 bar; | 1416 | u32 bar; |
1415 | unsigned long base; | 1417 | void __iomem *base; |
1416 | unsigned long type = ent->driver_data; | 1418 | unsigned long type = ent->driver_data; |
1417 | int mask_set = 0; | 1419 | int mask_set = 0; |
1418 | 1420 | ||
@@ -1464,15 +1466,14 @@ static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1464 | if (!probe_ent) | 1466 | if (!probe_ent) |
1465 | return -ENOMEM; | 1467 | return -ENOMEM; |
1466 | 1468 | ||
1467 | probe_ent->mmio_base = pcim_iomap(pdev, 5, 0); | 1469 | if (!pcim_iomap(pdev, NV_MMIO_BAR, 0)) |
1468 | if (!probe_ent->mmio_base) | ||
1469 | return -EIO; | 1470 | return -EIO; |
1471 | probe_ent->iomap = pcim_iomap_table(pdev); | ||
1470 | 1472 | ||
1471 | probe_ent->private_data = hpriv; | 1473 | probe_ent->private_data = hpriv; |
1472 | hpriv->type = type; | 1474 | hpriv->type = type; |
1473 | 1475 | ||
1474 | base = (unsigned long)probe_ent->mmio_base; | 1476 | base = probe_ent->iomap[NV_MMIO_BAR]; |
1475 | |||
1476 | probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET; | 1477 | probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET; |
1477 | probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET; | 1478 | probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET; |
1478 | 1479 | ||
diff --git a/drivers/ata/sata_promise.c b/drivers/ata/sata_promise.c index e09c609d4961..4fb47cad8229 100644 --- a/drivers/ata/sata_promise.c +++ b/drivers/ata/sata_promise.c | |||
@@ -50,6 +50,8 @@ | |||
50 | 50 | ||
51 | 51 | ||
52 | enum { | 52 | enum { |
53 | PDC_MMIO_BAR = 3, | ||
54 | |||
53 | /* register offsets */ | 55 | /* register offsets */ |
54 | PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ | 56 | PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ |
55 | PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ | 57 | PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ |
@@ -167,7 +169,7 @@ static const struct ata_port_operations pdc_sata_ops = { | |||
167 | .thaw = pdc_thaw, | 169 | .thaw = pdc_thaw, |
168 | .error_handler = pdc_error_handler, | 170 | .error_handler = pdc_error_handler, |
169 | .post_internal_cmd = pdc_post_internal_cmd, | 171 | .post_internal_cmd = pdc_post_internal_cmd, |
170 | .data_xfer = ata_mmio_data_xfer, | 172 | .data_xfer = ata_data_xfer, |
171 | .irq_handler = pdc_interrupt, | 173 | .irq_handler = pdc_interrupt, |
172 | .irq_clear = pdc_irq_clear, | 174 | .irq_clear = pdc_irq_clear, |
173 | 175 | ||
@@ -192,7 +194,7 @@ static const struct ata_port_operations pdc_old_sata_ops = { | |||
192 | .thaw = pdc_thaw, | 194 | .thaw = pdc_thaw, |
193 | .error_handler = pdc_error_handler, | 195 | .error_handler = pdc_error_handler, |
194 | .post_internal_cmd = pdc_post_internal_cmd, | 196 | .post_internal_cmd = pdc_post_internal_cmd, |
195 | .data_xfer = ata_mmio_data_xfer, | 197 | .data_xfer = ata_data_xfer, |
196 | .irq_handler = pdc_interrupt, | 198 | .irq_handler = pdc_interrupt, |
197 | .irq_clear = pdc_irq_clear, | 199 | .irq_clear = pdc_irq_clear, |
198 | 200 | ||
@@ -214,7 +216,7 @@ static const struct ata_port_operations pdc_pata_ops = { | |||
214 | 216 | ||
215 | .qc_prep = pdc_qc_prep, | 217 | .qc_prep = pdc_qc_prep, |
216 | .qc_issue = pdc_qc_issue_prot, | 218 | .qc_issue = pdc_qc_issue_prot, |
217 | .data_xfer = ata_mmio_data_xfer, | 219 | .data_xfer = ata_data_xfer, |
218 | .eng_timeout = pdc_eng_timeout, | 220 | .eng_timeout = pdc_eng_timeout, |
219 | .irq_handler = pdc_interrupt, | 221 | .irq_handler = pdc_interrupt, |
220 | .irq_clear = pdc_irq_clear, | 222 | .irq_clear = pdc_irq_clear, |
@@ -348,7 +350,7 @@ static int pdc_port_start(struct ata_port *ap) | |||
348 | 350 | ||
349 | static void pdc_reset_port(struct ata_port *ap) | 351 | static void pdc_reset_port(struct ata_port *ap) |
350 | { | 352 | { |
351 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT; | 353 | void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
352 | unsigned int i; | 354 | unsigned int i; |
353 | u32 tmp; | 355 | u32 tmp; |
354 | 356 | ||
@@ -394,7 +396,7 @@ static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) | |||
394 | { | 396 | { |
395 | if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA) | 397 | if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA) |
396 | return 0xffffffffU; | 398 | return 0xffffffffU; |
397 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); | 399 | return readl(ap->ioaddr.scr_addr + (sc_reg * 4)); |
398 | } | 400 | } |
399 | 401 | ||
400 | 402 | ||
@@ -403,7 +405,7 @@ static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |||
403 | { | 405 | { |
404 | if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA) | 406 | if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA) |
405 | return; | 407 | return; |
406 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); | 408 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
407 | } | 409 | } |
408 | 410 | ||
409 | static void pdc_atapi_pkt(struct ata_queued_cmd *qc) | 411 | static void pdc_atapi_pkt(struct ata_queued_cmd *qc) |
@@ -627,7 +629,7 @@ static inline unsigned int pdc_host_intr( struct ata_port *ap, | |||
627 | { | 629 | { |
628 | unsigned int handled = 0; | 630 | unsigned int handled = 0; |
629 | u32 tmp; | 631 | u32 tmp; |
630 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL; | 632 | void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL; |
631 | 633 | ||
632 | tmp = readl(mmio); | 634 | tmp = readl(mmio); |
633 | if (tmp & PDC_ERR_MASK) { | 635 | if (tmp & PDC_ERR_MASK) { |
@@ -656,7 +658,7 @@ static inline unsigned int pdc_host_intr( struct ata_port *ap, | |||
656 | static void pdc_irq_clear(struct ata_port *ap) | 658 | static void pdc_irq_clear(struct ata_port *ap) |
657 | { | 659 | { |
658 | struct ata_host *host = ap->host; | 660 | struct ata_host *host = ap->host; |
659 | void __iomem *mmio = host->mmio_base; | 661 | void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; |
660 | 662 | ||
661 | readl(mmio + PDC_INT_SEQMASK); | 663 | readl(mmio + PDC_INT_SEQMASK); |
662 | } | 664 | } |
@@ -672,12 +674,12 @@ static irqreturn_t pdc_interrupt (int irq, void *dev_instance) | |||
672 | 674 | ||
673 | VPRINTK("ENTER\n"); | 675 | VPRINTK("ENTER\n"); |
674 | 676 | ||
675 | if (!host || !host->mmio_base) { | 677 | if (!host || !host->iomap[PDC_MMIO_BAR]) { |
676 | VPRINTK("QUICK EXIT\n"); | 678 | VPRINTK("QUICK EXIT\n"); |
677 | return IRQ_NONE; | 679 | return IRQ_NONE; |
678 | } | 680 | } |
679 | 681 | ||
680 | mmio_base = host->mmio_base; | 682 | mmio_base = host->iomap[PDC_MMIO_BAR]; |
681 | 683 | ||
682 | /* reading should also clear interrupts */ | 684 | /* reading should also clear interrupts */ |
683 | mask = readl(mmio_base + PDC_INT_SEQMASK); | 685 | mask = readl(mmio_base + PDC_INT_SEQMASK); |
@@ -722,18 +724,19 @@ static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |||
722 | { | 724 | { |
723 | struct ata_port *ap = qc->ap; | 725 | struct ata_port *ap = qc->ap; |
724 | struct pdc_port_priv *pp = ap->private_data; | 726 | struct pdc_port_priv *pp = ap->private_data; |
727 | void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; | ||
725 | unsigned int port_no = ap->port_no; | 728 | unsigned int port_no = ap->port_no; |
726 | u8 seq = (u8) (port_no + 1); | 729 | u8 seq = (u8) (port_no + 1); |
727 | 730 | ||
728 | VPRINTK("ENTER, ap %p\n", ap); | 731 | VPRINTK("ENTER, ap %p\n", ap); |
729 | 732 | ||
730 | writel(0x00000001, ap->host->mmio_base + (seq * 4)); | 733 | writel(0x00000001, mmio + (seq * 4)); |
731 | readl(ap->host->mmio_base + (seq * 4)); /* flush */ | 734 | readl(mmio + (seq * 4)); /* flush */ |
732 | 735 | ||
733 | pp->pkt[2] = seq; | 736 | pp->pkt[2] = seq; |
734 | wmb(); /* flush PRD, pkt writes */ | 737 | wmb(); /* flush PRD, pkt writes */ |
735 | writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); | 738 | writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
736 | readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | 739 | readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ |
737 | } | 740 | } |
738 | 741 | ||
739 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) | 742 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) |
@@ -808,7 +811,7 @@ static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc) | |||
808 | return pdc_check_atapi_dma(qc); | 811 | return pdc_check_atapi_dma(qc); |
809 | } | 812 | } |
810 | 813 | ||
811 | static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base) | 814 | static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base) |
812 | { | 815 | { |
813 | port->cmd_addr = base; | 816 | port->cmd_addr = base; |
814 | port->data_addr = base; | 817 | port->data_addr = base; |
@@ -828,7 +831,7 @@ static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base) | |||
828 | 831 | ||
829 | static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe) | 832 | static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe) |
830 | { | 833 | { |
831 | void __iomem *mmio = pe->mmio_base; | 834 | void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; |
832 | struct pdc_host_priv *hp = pe->private_data; | 835 | struct pdc_host_priv *hp = pe->private_data; |
833 | int hotplug_offset; | 836 | int hotplug_offset; |
834 | u32 tmp; | 837 | u32 tmp; |
@@ -884,8 +887,7 @@ static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *e | |||
884 | static int printed_version; | 887 | static int printed_version; |
885 | struct ata_probe_ent *probe_ent; | 888 | struct ata_probe_ent *probe_ent; |
886 | struct pdc_host_priv *hp; | 889 | struct pdc_host_priv *hp; |
887 | unsigned long base; | 890 | void __iomem *base; |
888 | void __iomem *mmio_base; | ||
889 | unsigned int board_idx = (unsigned int) ent->driver_data; | 891 | unsigned int board_idx = (unsigned int) ent->driver_data; |
890 | int rc; | 892 | int rc; |
891 | u8 tmp; | 893 | u8 tmp; |
@@ -897,11 +899,11 @@ static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *e | |||
897 | if (rc) | 899 | if (rc) |
898 | return rc; | 900 | return rc; |
899 | 901 | ||
900 | rc = pci_request_regions(pdev, DRV_NAME); | 902 | rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); |
901 | if (rc) { | 903 | if (rc == -EBUSY) |
902 | pcim_pin_device(pdev); | 904 | pcim_pin_device(pdev); |
905 | if (rc) | ||
903 | return rc; | 906 | return rc; |
904 | } | ||
905 | 907 | ||
906 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | 908 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
907 | if (rc) | 909 | if (rc) |
@@ -917,11 +919,6 @@ static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *e | |||
917 | probe_ent->dev = pci_dev_to_dev(pdev); | 919 | probe_ent->dev = pci_dev_to_dev(pdev); |
918 | INIT_LIST_HEAD(&probe_ent->node); | 920 | INIT_LIST_HEAD(&probe_ent->node); |
919 | 921 | ||
920 | mmio_base = pcim_iomap(pdev, 3, 0); | ||
921 | if (mmio_base == NULL) | ||
922 | return -ENOMEM; | ||
923 | base = (unsigned long) mmio_base; | ||
924 | |||
925 | hp = devm_kzalloc(&pdev->dev, sizeof(*hp), GFP_KERNEL); | 922 | hp = devm_kzalloc(&pdev->dev, sizeof(*hp), GFP_KERNEL); |
926 | if (hp == NULL) | 923 | if (hp == NULL) |
927 | return -ENOMEM; | 924 | return -ENOMEM; |
@@ -937,7 +934,9 @@ static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *e | |||
937 | 934 | ||
938 | probe_ent->irq = pdev->irq; | 935 | probe_ent->irq = pdev->irq; |
939 | probe_ent->irq_flags = IRQF_SHARED; | 936 | probe_ent->irq_flags = IRQF_SHARED; |
940 | probe_ent->mmio_base = mmio_base; | 937 | probe_ent->iomap = pcim_iomap_table(pdev); |
938 | |||
939 | base = probe_ent->iomap[PDC_MMIO_BAR]; | ||
941 | 940 | ||
942 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x200); | 941 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x200); |
943 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x280); | 942 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x280); |
@@ -964,7 +963,7 @@ static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *e | |||
964 | /* Fall through */ | 963 | /* Fall through */ |
965 | case board_2037x: | 964 | case board_2037x: |
966 | /* TX2plus boards also have a PATA port */ | 965 | /* TX2plus boards also have a PATA port */ |
967 | tmp = readb(mmio_base + PDC_FLASH_CTL+1); | 966 | tmp = readb(base + PDC_FLASH_CTL+1); |
968 | if (!(tmp & 0x80)) { | 967 | if (!(tmp & 0x80)) { |
969 | probe_ent->n_ports = 3; | 968 | probe_ent->n_ports = 3; |
970 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | 969 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); |
diff --git a/drivers/ata/sata_qstor.c b/drivers/ata/sata_qstor.c index 339f61648af6..cd579b180274 100644 --- a/drivers/ata/sata_qstor.c +++ b/drivers/ata/sata_qstor.c | |||
@@ -43,6 +43,8 @@ | |||
43 | #define DRV_VERSION "0.06" | 43 | #define DRV_VERSION "0.06" |
44 | 44 | ||
45 | enum { | 45 | enum { |
46 | QS_MMIO_BAR = 4, | ||
47 | |||
46 | QS_PORTS = 4, | 48 | QS_PORTS = 4, |
47 | QS_MAX_PRD = LIBATA_MAX_PRD, | 49 | QS_MAX_PRD = LIBATA_MAX_PRD, |
48 | QS_CPB_ORDER = 6, | 50 | QS_CPB_ORDER = 6, |
@@ -155,7 +157,7 @@ static const struct ata_port_operations qs_ata_ops = { | |||
155 | .phy_reset = qs_phy_reset, | 157 | .phy_reset = qs_phy_reset, |
156 | .qc_prep = qs_qc_prep, | 158 | .qc_prep = qs_qc_prep, |
157 | .qc_issue = qs_qc_issue, | 159 | .qc_issue = qs_qc_issue, |
158 | .data_xfer = ata_mmio_data_xfer, | 160 | .data_xfer = ata_data_xfer, |
159 | .eng_timeout = qs_eng_timeout, | 161 | .eng_timeout = qs_eng_timeout, |
160 | .irq_handler = qs_intr, | 162 | .irq_handler = qs_intr, |
161 | .irq_clear = qs_irq_clear, | 163 | .irq_clear = qs_irq_clear, |
@@ -194,6 +196,11 @@ static struct pci_driver qs_ata_pci_driver = { | |||
194 | .remove = ata_pci_remove_one, | 196 | .remove = ata_pci_remove_one, |
195 | }; | 197 | }; |
196 | 198 | ||
199 | static void __iomem *qs_mmio_base(struct ata_host *host) | ||
200 | { | ||
201 | return host->iomap[QS_MMIO_BAR]; | ||
202 | } | ||
203 | |||
197 | static int qs_check_atapi_dma(struct ata_queued_cmd *qc) | 204 | static int qs_check_atapi_dma(struct ata_queued_cmd *qc) |
198 | { | 205 | { |
199 | return 1; /* ATAPI DMA not supported */ | 206 | return 1; /* ATAPI DMA not supported */ |
@@ -216,7 +223,7 @@ static void qs_irq_clear(struct ata_port *ap) | |||
216 | 223 | ||
217 | static inline void qs_enter_reg_mode(struct ata_port *ap) | 224 | static inline void qs_enter_reg_mode(struct ata_port *ap) |
218 | { | 225 | { |
219 | u8 __iomem *chan = ap->host->mmio_base + (ap->port_no * 0x4000); | 226 | u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000); |
220 | 227 | ||
221 | writeb(QS_CTR0_REG, chan + QS_CCT_CTR0); | 228 | writeb(QS_CTR0_REG, chan + QS_CCT_CTR0); |
222 | readb(chan + QS_CCT_CTR0); /* flush */ | 229 | readb(chan + QS_CCT_CTR0); /* flush */ |
@@ -224,7 +231,7 @@ static inline void qs_enter_reg_mode(struct ata_port *ap) | |||
224 | 231 | ||
225 | static inline void qs_reset_channel_logic(struct ata_port *ap) | 232 | static inline void qs_reset_channel_logic(struct ata_port *ap) |
226 | { | 233 | { |
227 | u8 __iomem *chan = ap->host->mmio_base + (ap->port_no * 0x4000); | 234 | u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000); |
228 | 235 | ||
229 | writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1); | 236 | writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1); |
230 | readb(chan + QS_CCT_CTR0); /* flush */ | 237 | readb(chan + QS_CCT_CTR0); /* flush */ |
@@ -254,14 +261,14 @@ static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg) | |||
254 | { | 261 | { |
255 | if (sc_reg > SCR_CONTROL) | 262 | if (sc_reg > SCR_CONTROL) |
256 | return ~0U; | 263 | return ~0U; |
257 | return readl((void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8))); | 264 | return readl(ap->ioaddr.scr_addr + (sc_reg * 8)); |
258 | } | 265 | } |
259 | 266 | ||
260 | static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | 267 | static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) |
261 | { | 268 | { |
262 | if (sc_reg > SCR_CONTROL) | 269 | if (sc_reg > SCR_CONTROL) |
263 | return; | 270 | return; |
264 | writel(val, (void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8))); | 271 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 8)); |
265 | } | 272 | } |
266 | 273 | ||
267 | static unsigned int qs_fill_sg(struct ata_queued_cmd *qc) | 274 | static unsigned int qs_fill_sg(struct ata_queued_cmd *qc) |
@@ -338,7 +345,7 @@ static void qs_qc_prep(struct ata_queued_cmd *qc) | |||
338 | static inline void qs_packet_start(struct ata_queued_cmd *qc) | 345 | static inline void qs_packet_start(struct ata_queued_cmd *qc) |
339 | { | 346 | { |
340 | struct ata_port *ap = qc->ap; | 347 | struct ata_port *ap = qc->ap; |
341 | u8 __iomem *chan = ap->host->mmio_base + (ap->port_no * 0x4000); | 348 | u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000); |
342 | 349 | ||
343 | VPRINTK("ENTER, ap %p\n", ap); | 350 | VPRINTK("ENTER, ap %p\n", ap); |
344 | 351 | ||
@@ -375,7 +382,7 @@ static inline unsigned int qs_intr_pkt(struct ata_host *host) | |||
375 | { | 382 | { |
376 | unsigned int handled = 0; | 383 | unsigned int handled = 0; |
377 | u8 sFFE; | 384 | u8 sFFE; |
378 | u8 __iomem *mmio_base = host->mmio_base; | 385 | u8 __iomem *mmio_base = qs_mmio_base(host); |
379 | 386 | ||
380 | do { | 387 | do { |
381 | u32 sff0 = readl(mmio_base + QS_HST_SFF); | 388 | u32 sff0 = readl(mmio_base + QS_HST_SFF); |
@@ -467,7 +474,7 @@ static irqreturn_t qs_intr(int irq, void *dev_instance) | |||
467 | return IRQ_RETVAL(handled); | 474 | return IRQ_RETVAL(handled); |
468 | } | 475 | } |
469 | 476 | ||
470 | static void qs_ata_setup_port(struct ata_ioports *port, unsigned long base) | 477 | static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base) |
471 | { | 478 | { |
472 | port->cmd_addr = | 479 | port->cmd_addr = |
473 | port->data_addr = base + 0x400; | 480 | port->data_addr = base + 0x400; |
@@ -489,7 +496,7 @@ static int qs_port_start(struct ata_port *ap) | |||
489 | { | 496 | { |
490 | struct device *dev = ap->host->dev; | 497 | struct device *dev = ap->host->dev; |
491 | struct qs_port_priv *pp; | 498 | struct qs_port_priv *pp; |
492 | void __iomem *mmio_base = ap->host->mmio_base; | 499 | void __iomem *mmio_base = qs_mmio_base(ap->host); |
493 | void __iomem *chan = mmio_base + (ap->port_no * 0x4000); | 500 | void __iomem *chan = mmio_base + (ap->port_no * 0x4000); |
494 | u64 addr; | 501 | u64 addr; |
495 | int rc; | 502 | int rc; |
@@ -516,7 +523,7 @@ static int qs_port_start(struct ata_port *ap) | |||
516 | 523 | ||
517 | static void qs_host_stop(struct ata_host *host) | 524 | static void qs_host_stop(struct ata_host *host) |
518 | { | 525 | { |
519 | void __iomem *mmio_base = host->mmio_base; | 526 | void __iomem *mmio_base = qs_mmio_base(host); |
520 | 527 | ||
521 | writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */ | 528 | writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */ |
522 | writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */ | 529 | writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */ |
@@ -524,7 +531,7 @@ static void qs_host_stop(struct ata_host *host) | |||
524 | 531 | ||
525 | static void qs_host_init(unsigned int chip_id, struct ata_probe_ent *pe) | 532 | static void qs_host_init(unsigned int chip_id, struct ata_probe_ent *pe) |
526 | { | 533 | { |
527 | void __iomem *mmio_base = pe->mmio_base; | 534 | void __iomem *mmio_base = pe->iomap[QS_MMIO_BAR]; |
528 | unsigned int port_no; | 535 | unsigned int port_no; |
529 | 536 | ||
530 | writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */ | 537 | writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */ |
@@ -599,8 +606,8 @@ static int qs_ata_init_one(struct pci_dev *pdev, | |||
599 | const struct pci_device_id *ent) | 606 | const struct pci_device_id *ent) |
600 | { | 607 | { |
601 | static int printed_version; | 608 | static int printed_version; |
602 | struct ata_probe_ent *probe_ent = NULL; | 609 | struct ata_probe_ent *probe_ent; |
603 | void __iomem *mmio_base; | 610 | void __iomem * const *iomap; |
604 | unsigned int board_idx = (unsigned int) ent->driver_data; | 611 | unsigned int board_idx = (unsigned int) ent->driver_data; |
605 | int rc, port_no; | 612 | int rc, port_no; |
606 | 613 | ||
@@ -611,18 +618,15 @@ static int qs_ata_init_one(struct pci_dev *pdev, | |||
611 | if (rc) | 618 | if (rc) |
612 | return rc; | 619 | return rc; |
613 | 620 | ||
614 | rc = pci_request_regions(pdev, DRV_NAME); | 621 | if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0) |
615 | if (rc) | ||
616 | return rc; | ||
617 | |||
618 | if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) | ||
619 | return -ENODEV; | 622 | return -ENODEV; |
620 | 623 | ||
621 | mmio_base = pcim_iomap(pdev, 4, 0); | 624 | rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME); |
622 | if (mmio_base == NULL) | 625 | if (rc) |
623 | return -ENOMEM; | 626 | return rc; |
627 | iomap = pcim_iomap_table(pdev); | ||
624 | 628 | ||
625 | rc = qs_set_dma_masks(pdev, mmio_base); | 629 | rc = qs_set_dma_masks(pdev, iomap[QS_MMIO_BAR]); |
626 | if (rc) | 630 | if (rc) |
627 | return rc; | 631 | return rc; |
628 | 632 | ||
@@ -642,12 +646,12 @@ static int qs_ata_init_one(struct pci_dev *pdev, | |||
642 | 646 | ||
643 | probe_ent->irq = pdev->irq; | 647 | probe_ent->irq = pdev->irq; |
644 | probe_ent->irq_flags = IRQF_SHARED; | 648 | probe_ent->irq_flags = IRQF_SHARED; |
645 | probe_ent->mmio_base = mmio_base; | 649 | probe_ent->iomap = iomap; |
646 | probe_ent->n_ports = QS_PORTS; | 650 | probe_ent->n_ports = QS_PORTS; |
647 | 651 | ||
648 | for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) { | 652 | for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) { |
649 | unsigned long chan = (unsigned long)mmio_base + | 653 | void __iomem *chan = |
650 | (port_no * 0x4000); | 654 | probe_ent->iomap[QS_MMIO_BAR] + (port_no * 0x4000); |
651 | qs_ata_setup_port(&probe_ent->port[port_no], chan); | 655 | qs_ata_setup_port(&probe_ent->port[port_no], chan); |
652 | } | 656 | } |
653 | 657 | ||
diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c index 00f2465dcdce..4a25093b2dda 100644 --- a/drivers/ata/sata_sil.c +++ b/drivers/ata/sata_sil.c | |||
@@ -49,6 +49,8 @@ | |||
49 | #define DRV_VERSION "2.0" | 49 | #define DRV_VERSION "2.0" |
50 | 50 | ||
51 | enum { | 51 | enum { |
52 | SIL_MMIO_BAR = 5, | ||
53 | |||
52 | /* | 54 | /* |
53 | * host flags | 55 | * host flags |
54 | */ | 56 | */ |
@@ -200,7 +202,7 @@ static const struct ata_port_operations sil_ops = { | |||
200 | .bmdma_status = ata_bmdma_status, | 202 | .bmdma_status = ata_bmdma_status, |
201 | .qc_prep = ata_qc_prep, | 203 | .qc_prep = ata_qc_prep, |
202 | .qc_issue = ata_qc_issue_prot, | 204 | .qc_issue = ata_qc_issue_prot, |
203 | .data_xfer = ata_mmio_data_xfer, | 205 | .data_xfer = ata_data_xfer, |
204 | .freeze = sil_freeze, | 206 | .freeze = sil_freeze, |
205 | .thaw = sil_thaw, | 207 | .thaw = sil_thaw, |
206 | .error_handler = ata_bmdma_error_handler, | 208 | .error_handler = ata_bmdma_error_handler, |
@@ -295,7 +297,8 @@ static void sil_post_set_mode (struct ata_port *ap) | |||
295 | { | 297 | { |
296 | struct ata_host *host = ap->host; | 298 | struct ata_host *host = ap->host; |
297 | struct ata_device *dev; | 299 | struct ata_device *dev; |
298 | void __iomem *addr = host->mmio_base + sil_port[ap->port_no].xfer_mode; | 300 | void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; |
301 | void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode; | ||
299 | u32 tmp, dev_mode[2]; | 302 | u32 tmp, dev_mode[2]; |
300 | unsigned int i; | 303 | unsigned int i; |
301 | 304 | ||
@@ -318,9 +321,9 @@ static void sil_post_set_mode (struct ata_port *ap) | |||
318 | readl(addr); /* flush */ | 321 | readl(addr); /* flush */ |
319 | } | 322 | } |
320 | 323 | ||
321 | static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg) | 324 | static inline void __iomem *sil_scr_addr(struct ata_port *ap, unsigned int sc_reg) |
322 | { | 325 | { |
323 | unsigned long offset = ap->ioaddr.scr_addr; | 326 | void __iomem *offset = ap->ioaddr.scr_addr; |
324 | 327 | ||
325 | switch (sc_reg) { | 328 | switch (sc_reg) { |
326 | case SCR_STATUS: | 329 | case SCR_STATUS: |
@@ -339,7 +342,7 @@ static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_re | |||
339 | 342 | ||
340 | static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg) | 343 | static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg) |
341 | { | 344 | { |
342 | void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg); | 345 | void __iomem *mmio = sil_scr_addr(ap, sc_reg); |
343 | if (mmio) | 346 | if (mmio) |
344 | return readl(mmio); | 347 | return readl(mmio); |
345 | return 0xffffffffU; | 348 | return 0xffffffffU; |
@@ -347,7 +350,7 @@ static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg) | |||
347 | 350 | ||
348 | static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | 351 | static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) |
349 | { | 352 | { |
350 | void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg); | 353 | void __iomem *mmio = sil_scr_addr(ap, sc_reg); |
351 | if (mmio) | 354 | if (mmio) |
352 | writel(val, mmio); | 355 | writel(val, mmio); |
353 | } | 356 | } |
@@ -442,7 +445,7 @@ static void sil_host_intr(struct ata_port *ap, u32 bmdma2) | |||
442 | static irqreturn_t sil_interrupt(int irq, void *dev_instance) | 445 | static irqreturn_t sil_interrupt(int irq, void *dev_instance) |
443 | { | 446 | { |
444 | struct ata_host *host = dev_instance; | 447 | struct ata_host *host = dev_instance; |
445 | void __iomem *mmio_base = host->mmio_base; | 448 | void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; |
446 | int handled = 0; | 449 | int handled = 0; |
447 | int i; | 450 | int i; |
448 | 451 | ||
@@ -474,7 +477,7 @@ static irqreturn_t sil_interrupt(int irq, void *dev_instance) | |||
474 | 477 | ||
475 | static void sil_freeze(struct ata_port *ap) | 478 | static void sil_freeze(struct ata_port *ap) |
476 | { | 479 | { |
477 | void __iomem *mmio_base = ap->host->mmio_base; | 480 | void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; |
478 | u32 tmp; | 481 | u32 tmp; |
479 | 482 | ||
480 | /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */ | 483 | /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */ |
@@ -489,7 +492,7 @@ static void sil_freeze(struct ata_port *ap) | |||
489 | 492 | ||
490 | static void sil_thaw(struct ata_port *ap) | 493 | static void sil_thaw(struct ata_port *ap) |
491 | { | 494 | { |
492 | void __iomem *mmio_base = ap->host->mmio_base; | 495 | void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; |
493 | u32 tmp; | 496 | u32 tmp; |
494 | 497 | ||
495 | /* clear IRQ */ | 498 | /* clear IRQ */ |
@@ -621,7 +624,6 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |||
621 | static int printed_version; | 624 | static int printed_version; |
622 | struct device *dev = &pdev->dev; | 625 | struct device *dev = &pdev->dev; |
623 | struct ata_probe_ent *probe_ent; | 626 | struct ata_probe_ent *probe_ent; |
624 | unsigned long base; | ||
625 | void __iomem *mmio_base; | 627 | void __iomem *mmio_base; |
626 | int rc; | 628 | int rc; |
627 | unsigned int i; | 629 | unsigned int i; |
@@ -633,11 +635,11 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |||
633 | if (rc) | 635 | if (rc) |
634 | return rc; | 636 | return rc; |
635 | 637 | ||
636 | rc = pci_request_regions(pdev, DRV_NAME); | 638 | rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME); |
637 | if (rc) { | 639 | if (rc == -EBUSY) |
638 | pcim_pin_device(pdev); | 640 | pcim_pin_device(pdev); |
641 | if (rc) | ||
639 | return rc; | 642 | return rc; |
640 | } | ||
641 | 643 | ||
642 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | 644 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
643 | if (rc) | 645 | if (rc) |
@@ -662,20 +664,16 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |||
662 | probe_ent->irq_flags = IRQF_SHARED; | 664 | probe_ent->irq_flags = IRQF_SHARED; |
663 | probe_ent->port_flags = sil_port_info[ent->driver_data].flags; | 665 | probe_ent->port_flags = sil_port_info[ent->driver_data].flags; |
664 | 666 | ||
665 | mmio_base = pcim_iomap(pdev, 5, 0); | 667 | probe_ent->iomap = pcim_iomap_table(pdev); |
666 | if (mmio_base == NULL) | ||
667 | return -ENOMEM; | ||
668 | |||
669 | probe_ent->mmio_base = mmio_base; | ||
670 | 668 | ||
671 | base = (unsigned long) mmio_base; | 669 | mmio_base = probe_ent->iomap[SIL_MMIO_BAR]; |
672 | 670 | ||
673 | for (i = 0; i < probe_ent->n_ports; i++) { | 671 | for (i = 0; i < probe_ent->n_ports; i++) { |
674 | probe_ent->port[i].cmd_addr = base + sil_port[i].tf; | 672 | probe_ent->port[i].cmd_addr = mmio_base + sil_port[i].tf; |
675 | probe_ent->port[i].altstatus_addr = | 673 | probe_ent->port[i].altstatus_addr = |
676 | probe_ent->port[i].ctl_addr = base + sil_port[i].ctl; | 674 | probe_ent->port[i].ctl_addr = mmio_base + sil_port[i].ctl; |
677 | probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma; | 675 | probe_ent->port[i].bmdma_addr = mmio_base + sil_port[i].bmdma; |
678 | probe_ent->port[i].scr_addr = base + sil_port[i].scr; | 676 | probe_ent->port[i].scr_addr = mmio_base + sil_port[i].scr; |
679 | ata_std_ports(&probe_ent->port[i]); | 677 | ata_std_ports(&probe_ent->port[i]); |
680 | } | 678 | } |
681 | 679 | ||
@@ -702,7 +700,7 @@ static int sil_pci_device_resume(struct pci_dev *pdev) | |||
702 | return rc; | 700 | return rc; |
703 | 701 | ||
704 | sil_init_controller(pdev, host->n_ports, host->ports[0]->flags, | 702 | sil_init_controller(pdev, host->n_ports, host->ports[0]->flags, |
705 | host->mmio_base); | 703 | host->iomap[SIL_MMIO_BAR]); |
706 | ata_host_resume(host); | 704 | ata_host_resume(host); |
707 | 705 | ||
708 | return 0; | 706 | return 0; |
diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c index c7a3c0275bee..9dcf11e2c7b3 100644 --- a/drivers/ata/sata_sil24.c +++ b/drivers/ata/sata_sil24.c | |||
@@ -60,6 +60,9 @@ struct sil24_port_multiplier { | |||
60 | }; | 60 | }; |
61 | 61 | ||
62 | enum { | 62 | enum { |
63 | SIL24_HOST_BAR = 0, | ||
64 | SIL24_PORT_BAR = 2, | ||
65 | |||
63 | /* | 66 | /* |
64 | * Global controller registers (128 bytes @ BAR0) | 67 | * Global controller registers (128 bytes @ BAR0) |
65 | */ | 68 | */ |
@@ -320,12 +323,6 @@ struct sil24_port_priv { | |||
320 | struct ata_taskfile tf; /* Cached taskfile registers */ | 323 | struct ata_taskfile tf; /* Cached taskfile registers */ |
321 | }; | 324 | }; |
322 | 325 | ||
323 | /* ap->host->private_data */ | ||
324 | struct sil24_host_priv { | ||
325 | void __iomem *host_base; /* global controller control (128 bytes @BAR0) */ | ||
326 | void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */ | ||
327 | }; | ||
328 | |||
329 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev); | 326 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev); |
330 | static u8 sil24_check_status(struct ata_port *ap); | 327 | static u8 sil24_check_status(struct ata_port *ap); |
331 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg); | 328 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg); |
@@ -462,7 +459,7 @@ static int sil24_tag(int tag) | |||
462 | 459 | ||
463 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev) | 460 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev) |
464 | { | 461 | { |
465 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; | 462 | void __iomem *port = ap->ioaddr.cmd_addr; |
466 | 463 | ||
467 | if (dev->cdb_len == 16) | 464 | if (dev->cdb_len == 16) |
468 | writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); | 465 | writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); |
@@ -473,7 +470,7 @@ static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev) | |||
473 | static inline void sil24_update_tf(struct ata_port *ap) | 470 | static inline void sil24_update_tf(struct ata_port *ap) |
474 | { | 471 | { |
475 | struct sil24_port_priv *pp = ap->private_data; | 472 | struct sil24_port_priv *pp = ap->private_data; |
476 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; | 473 | void __iomem *port = ap->ioaddr.cmd_addr; |
477 | struct sil24_prb __iomem *prb = port; | 474 | struct sil24_prb __iomem *prb = port; |
478 | u8 fis[6 * 4]; | 475 | u8 fis[6 * 4]; |
479 | 476 | ||
@@ -496,7 +493,7 @@ static int sil24_scr_map[] = { | |||
496 | 493 | ||
497 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg) | 494 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg) |
498 | { | 495 | { |
499 | void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; | 496 | void __iomem *scr_addr = ap->ioaddr.scr_addr; |
500 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { | 497 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
501 | void __iomem *addr; | 498 | void __iomem *addr; |
502 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; | 499 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
@@ -507,7 +504,7 @@ static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg) | |||
507 | 504 | ||
508 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) | 505 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) |
509 | { | 506 | { |
510 | void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; | 507 | void __iomem *scr_addr = ap->ioaddr.scr_addr; |
511 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { | 508 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
512 | void __iomem *addr; | 509 | void __iomem *addr; |
513 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; | 510 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
@@ -523,7 +520,7 @@ static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | |||
523 | 520 | ||
524 | static int sil24_init_port(struct ata_port *ap) | 521 | static int sil24_init_port(struct ata_port *ap) |
525 | { | 522 | { |
526 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; | 523 | void __iomem *port = ap->ioaddr.cmd_addr; |
527 | u32 tmp; | 524 | u32 tmp; |
528 | 525 | ||
529 | writel(PORT_CS_INIT, port + PORT_CTRL_STAT); | 526 | writel(PORT_CS_INIT, port + PORT_CTRL_STAT); |
@@ -539,7 +536,7 @@ static int sil24_init_port(struct ata_port *ap) | |||
539 | 536 | ||
540 | static int sil24_softreset(struct ata_port *ap, unsigned int *class) | 537 | static int sil24_softreset(struct ata_port *ap, unsigned int *class) |
541 | { | 538 | { |
542 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; | 539 | void __iomem *port = ap->ioaddr.cmd_addr; |
543 | struct sil24_port_priv *pp = ap->private_data; | 540 | struct sil24_port_priv *pp = ap->private_data; |
544 | struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; | 541 | struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; |
545 | dma_addr_t paddr = pp->cmd_block_dma; | 542 | dma_addr_t paddr = pp->cmd_block_dma; |
@@ -599,7 +596,7 @@ static int sil24_softreset(struct ata_port *ap, unsigned int *class) | |||
599 | 596 | ||
600 | static int sil24_hardreset(struct ata_port *ap, unsigned int *class) | 597 | static int sil24_hardreset(struct ata_port *ap, unsigned int *class) |
601 | { | 598 | { |
602 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; | 599 | void __iomem *port = ap->ioaddr.cmd_addr; |
603 | const char *reason; | 600 | const char *reason; |
604 | int tout_msec, rc; | 601 | int tout_msec, rc; |
605 | u32 tmp; | 602 | u32 tmp; |
@@ -716,7 +713,7 @@ static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) | |||
716 | { | 713 | { |
717 | struct ata_port *ap = qc->ap; | 714 | struct ata_port *ap = qc->ap; |
718 | struct sil24_port_priv *pp = ap->private_data; | 715 | struct sil24_port_priv *pp = ap->private_data; |
719 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; | 716 | void __iomem *port = ap->ioaddr.cmd_addr; |
720 | unsigned int tag = sil24_tag(qc->tag); | 717 | unsigned int tag = sil24_tag(qc->tag); |
721 | dma_addr_t paddr; | 718 | dma_addr_t paddr; |
722 | void __iomem *activate; | 719 | void __iomem *activate; |
@@ -737,7 +734,7 @@ static void sil24_irq_clear(struct ata_port *ap) | |||
737 | 734 | ||
738 | static void sil24_freeze(struct ata_port *ap) | 735 | static void sil24_freeze(struct ata_port *ap) |
739 | { | 736 | { |
740 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; | 737 | void __iomem *port = ap->ioaddr.cmd_addr; |
741 | 738 | ||
742 | /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear | 739 | /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear |
743 | * PORT_IRQ_ENABLE instead. | 740 | * PORT_IRQ_ENABLE instead. |
@@ -747,7 +744,7 @@ static void sil24_freeze(struct ata_port *ap) | |||
747 | 744 | ||
748 | static void sil24_thaw(struct ata_port *ap) | 745 | static void sil24_thaw(struct ata_port *ap) |
749 | { | 746 | { |
750 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; | 747 | void __iomem *port = ap->ioaddr.cmd_addr; |
751 | u32 tmp; | 748 | u32 tmp; |
752 | 749 | ||
753 | /* clear IRQ */ | 750 | /* clear IRQ */ |
@@ -760,7 +757,7 @@ static void sil24_thaw(struct ata_port *ap) | |||
760 | 757 | ||
761 | static void sil24_error_intr(struct ata_port *ap) | 758 | static void sil24_error_intr(struct ata_port *ap) |
762 | { | 759 | { |
763 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; | 760 | void __iomem *port = ap->ioaddr.cmd_addr; |
764 | struct ata_eh_info *ehi = &ap->eh_info; | 761 | struct ata_eh_info *ehi = &ap->eh_info; |
765 | int freeze = 0; | 762 | int freeze = 0; |
766 | u32 irq_stat; | 763 | u32 irq_stat; |
@@ -838,7 +835,7 @@ static void sil24_finish_qc(struct ata_queued_cmd *qc) | |||
838 | 835 | ||
839 | static inline void sil24_host_intr(struct ata_port *ap) | 836 | static inline void sil24_host_intr(struct ata_port *ap) |
840 | { | 837 | { |
841 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; | 838 | void __iomem *port = ap->ioaddr.cmd_addr; |
842 | u32 slot_stat, qc_active; | 839 | u32 slot_stat, qc_active; |
843 | int rc; | 840 | int rc; |
844 | 841 | ||
@@ -873,12 +870,12 @@ static inline void sil24_host_intr(struct ata_port *ap) | |||
873 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance) | 870 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance) |
874 | { | 871 | { |
875 | struct ata_host *host = dev_instance; | 872 | struct ata_host *host = dev_instance; |
876 | struct sil24_host_priv *hpriv = host->private_data; | 873 | void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; |
877 | unsigned handled = 0; | 874 | unsigned handled = 0; |
878 | u32 status; | 875 | u32 status; |
879 | int i; | 876 | int i; |
880 | 877 | ||
881 | status = readl(hpriv->host_base + HOST_IRQ_STAT); | 878 | status = readl(host_base + HOST_IRQ_STAT); |
882 | 879 | ||
883 | if (status == 0xffffffff) { | 880 | if (status == 0xffffffff) { |
884 | printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " | 881 | printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " |
@@ -1031,7 +1028,6 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1031 | unsigned int board_id = (unsigned int)ent->driver_data; | 1028 | unsigned int board_id = (unsigned int)ent->driver_data; |
1032 | struct ata_port_info *pinfo = &sil24_port_info[board_id]; | 1029 | struct ata_port_info *pinfo = &sil24_port_info[board_id]; |
1033 | struct ata_probe_ent *probe_ent; | 1030 | struct ata_probe_ent *probe_ent; |
1034 | struct sil24_host_priv *hpriv; | ||
1035 | void __iomem *host_base; | 1031 | void __iomem *host_base; |
1036 | void __iomem *port_base; | 1032 | void __iomem *port_base; |
1037 | int i, rc; | 1033 | int i, rc; |
@@ -1044,20 +1040,15 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1044 | if (rc) | 1040 | if (rc) |
1045 | return rc; | 1041 | return rc; |
1046 | 1042 | ||
1047 | rc = pci_request_regions(pdev, DRV_NAME); | 1043 | rc = pcim_iomap_regions(pdev, |
1044 | (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR), | ||
1045 | DRV_NAME); | ||
1048 | if (rc) | 1046 | if (rc) |
1049 | return rc; | 1047 | return rc; |
1050 | 1048 | ||
1051 | /* map mmio registers */ | 1049 | /* allocate & init probe_ent */ |
1052 | host_base = pcim_iomap(pdev, 0, 0); | ||
1053 | port_base = pcim_iomap(pdev, 2, 0); | ||
1054 | if (!host_base || !port_base) | ||
1055 | return -ENOMEM; | ||
1056 | |||
1057 | /* allocate & init probe_ent and hpriv */ | ||
1058 | probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL); | 1050 | probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL); |
1059 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); | 1051 | if (!probe_ent) |
1060 | if (!probe_ent || !hpriv) | ||
1061 | return -ENOMEM; | 1052 | return -ENOMEM; |
1062 | 1053 | ||
1063 | probe_ent->dev = pci_dev_to_dev(pdev); | 1054 | probe_ent->dev = pci_dev_to_dev(pdev); |
@@ -1073,10 +1064,10 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1073 | 1064 | ||
1074 | probe_ent->irq = pdev->irq; | 1065 | probe_ent->irq = pdev->irq; |
1075 | probe_ent->irq_flags = IRQF_SHARED; | 1066 | probe_ent->irq_flags = IRQF_SHARED; |
1076 | probe_ent->private_data = hpriv; | 1067 | probe_ent->iomap = pcim_iomap_table(pdev); |
1077 | 1068 | ||
1078 | hpriv->host_base = host_base; | 1069 | host_base = probe_ent->iomap[SIL24_HOST_BAR]; |
1079 | hpriv->port_base = port_base; | 1070 | port_base = probe_ent->iomap[SIL24_PORT_BAR]; |
1080 | 1071 | ||
1081 | /* | 1072 | /* |
1082 | * Configure the device | 1073 | * Configure the device |
@@ -1118,11 +1109,10 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1118 | } | 1109 | } |
1119 | 1110 | ||
1120 | for (i = 0; i < probe_ent->n_ports; i++) { | 1111 | for (i = 0; i < probe_ent->n_ports; i++) { |
1121 | unsigned long portu = | 1112 | void __iomem *port = port_base + i * PORT_REGS_SIZE; |
1122 | (unsigned long)port_base + i * PORT_REGS_SIZE; | ||
1123 | 1113 | ||
1124 | probe_ent->port[i].cmd_addr = portu; | 1114 | probe_ent->port[i].cmd_addr = port; |
1125 | probe_ent->port[i].scr_addr = portu + PORT_SCONTROL; | 1115 | probe_ent->port[i].scr_addr = port + PORT_SCONTROL; |
1126 | 1116 | ||
1127 | ata_std_ports(&probe_ent->port[i]); | 1117 | ata_std_ports(&probe_ent->port[i]); |
1128 | } | 1118 | } |
@@ -1143,7 +1133,8 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1143 | static int sil24_pci_device_resume(struct pci_dev *pdev) | 1133 | static int sil24_pci_device_resume(struct pci_dev *pdev) |
1144 | { | 1134 | { |
1145 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | 1135 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
1146 | struct sil24_host_priv *hpriv = host->private_data; | 1136 | void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; |
1137 | void __iomem *port_base = host->iomap[SIL24_PORT_BAR]; | ||
1147 | int rc; | 1138 | int rc; |
1148 | 1139 | ||
1149 | rc = ata_pci_device_do_resume(pdev); | 1140 | rc = ata_pci_device_do_resume(pdev); |
@@ -1151,10 +1142,10 @@ static int sil24_pci_device_resume(struct pci_dev *pdev) | |||
1151 | return rc; | 1142 | return rc; |
1152 | 1143 | ||
1153 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) | 1144 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) |
1154 | writel(HOST_CTRL_GLOBAL_RST, hpriv->host_base + HOST_CTRL); | 1145 | writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL); |
1155 | 1146 | ||
1156 | sil24_init_controller(pdev, host->n_ports, host->ports[0]->flags, | 1147 | sil24_init_controller(pdev, host->n_ports, host->ports[0]->flags, |
1157 | hpriv->host_base, hpriv->port_base); | 1148 | host_base, port_base); |
1158 | 1149 | ||
1159 | ata_host_resume(host); | 1150 | ata_host_resume(host); |
1160 | 1151 | ||
diff --git a/drivers/ata/sata_sis.c b/drivers/ata/sata_sis.c index 4bcb94866333..eee2097c10c0 100644 --- a/drivers/ata/sata_sis.c +++ b/drivers/ata/sata_sis.c | |||
@@ -117,7 +117,7 @@ static const struct ata_port_operations sis_ops = { | |||
117 | .bmdma_status = ata_bmdma_status, | 117 | .bmdma_status = ata_bmdma_status, |
118 | .qc_prep = ata_qc_prep, | 118 | .qc_prep = ata_qc_prep, |
119 | .qc_issue = ata_qc_issue_prot, | 119 | .qc_issue = ata_qc_issue_prot, |
120 | .data_xfer = ata_pio_data_xfer, | 120 | .data_xfer = ata_data_xfer, |
121 | .freeze = ata_bmdma_freeze, | 121 | .freeze = ata_bmdma_freeze, |
122 | .thaw = ata_bmdma_thaw, | 122 | .thaw = ata_bmdma_thaw, |
123 | .error_handler = ata_bmdma_error_handler, | 123 | .error_handler = ata_bmdma_error_handler, |
@@ -223,11 +223,11 @@ static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg) | |||
223 | 223 | ||
224 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | 224 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
225 | 225 | ||
226 | val = inl(ap->ioaddr.scr_addr + (sc_reg * 4)); | 226 | val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4)); |
227 | 227 | ||
228 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) || | 228 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) || |
229 | (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED)) | 229 | (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED)) |
230 | val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10); | 230 | val2 = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10); |
231 | 231 | ||
232 | return (val | val2) & 0xfffffffb; | 232 | return (val | val2) & 0xfffffffb; |
233 | } | 233 | } |
@@ -245,10 +245,10 @@ static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |||
245 | if (ap->flags & SIS_FLAG_CFGSCR) | 245 | if (ap->flags & SIS_FLAG_CFGSCR) |
246 | sis_scr_cfg_write(ap, sc_reg, val); | 246 | sis_scr_cfg_write(ap, sc_reg, val); |
247 | else { | 247 | else { |
248 | outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)); | 248 | iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
249 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) || | 249 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) || |
250 | (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED)) | 250 | (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED)) |
251 | outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10); | 251 | iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10); |
252 | } | 252 | } |
253 | } | 253 | } |
254 | 254 | ||
@@ -353,10 +353,14 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |||
353 | return -ENOMEM; | 353 | return -ENOMEM; |
354 | 354 | ||
355 | if (!(probe_ent->port_flags & SIS_FLAG_CFGSCR)) { | 355 | if (!(probe_ent->port_flags & SIS_FLAG_CFGSCR)) { |
356 | probe_ent->port[0].scr_addr = | 356 | void *mmio; |
357 | pci_resource_start(pdev, SIS_SCR_PCI_BAR); | 357 | |
358 | probe_ent->port[1].scr_addr = | 358 | mmio = pcim_iomap(pdev, SIS_SCR_PCI_BAR, 0); |
359 | pci_resource_start(pdev, SIS_SCR_PCI_BAR) + port2_start; | 359 | if (!mmio) |
360 | return -ENOMEM; | ||
361 | |||
362 | probe_ent->port[0].scr_addr = mmio; | ||
363 | probe_ent->port[1].scr_addr = mmio + port2_start; | ||
360 | } | 364 | } |
361 | 365 | ||
362 | pci_set_master(pdev); | 366 | pci_set_master(pdev); |
diff --git a/drivers/ata/sata_svw.c b/drivers/ata/sata_svw.c index 9c48b418ad7f..5ce4f593687d 100644 --- a/drivers/ata/sata_svw.c +++ b/drivers/ata/sata_svw.c | |||
@@ -135,31 +135,31 @@ static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) | |||
135 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | 135 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; |
136 | 136 | ||
137 | if (tf->ctl != ap->last_ctl) { | 137 | if (tf->ctl != ap->last_ctl) { |
138 | writeb(tf->ctl, (void __iomem *) ioaddr->ctl_addr); | 138 | writeb(tf->ctl, ioaddr->ctl_addr); |
139 | ap->last_ctl = tf->ctl; | 139 | ap->last_ctl = tf->ctl; |
140 | ata_wait_idle(ap); | 140 | ata_wait_idle(ap); |
141 | } | 141 | } |
142 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | 142 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { |
143 | writew(tf->feature | (((u16)tf->hob_feature) << 8), | 143 | writew(tf->feature | (((u16)tf->hob_feature) << 8), |
144 | (void __iomem *) ioaddr->feature_addr); | 144 | ioaddr->feature_addr); |
145 | writew(tf->nsect | (((u16)tf->hob_nsect) << 8), | 145 | writew(tf->nsect | (((u16)tf->hob_nsect) << 8), |
146 | (void __iomem *) ioaddr->nsect_addr); | 146 | ioaddr->nsect_addr); |
147 | writew(tf->lbal | (((u16)tf->hob_lbal) << 8), | 147 | writew(tf->lbal | (((u16)tf->hob_lbal) << 8), |
148 | (void __iomem *) ioaddr->lbal_addr); | 148 | ioaddr->lbal_addr); |
149 | writew(tf->lbam | (((u16)tf->hob_lbam) << 8), | 149 | writew(tf->lbam | (((u16)tf->hob_lbam) << 8), |
150 | (void __iomem *) ioaddr->lbam_addr); | 150 | ioaddr->lbam_addr); |
151 | writew(tf->lbah | (((u16)tf->hob_lbah) << 8), | 151 | writew(tf->lbah | (((u16)tf->hob_lbah) << 8), |
152 | (void __iomem *) ioaddr->lbah_addr); | 152 | ioaddr->lbah_addr); |
153 | } else if (is_addr) { | 153 | } else if (is_addr) { |
154 | writew(tf->feature, (void __iomem *) ioaddr->feature_addr); | 154 | writew(tf->feature, ioaddr->feature_addr); |
155 | writew(tf->nsect, (void __iomem *) ioaddr->nsect_addr); | 155 | writew(tf->nsect, ioaddr->nsect_addr); |
156 | writew(tf->lbal, (void __iomem *) ioaddr->lbal_addr); | 156 | writew(tf->lbal, ioaddr->lbal_addr); |
157 | writew(tf->lbam, (void __iomem *) ioaddr->lbam_addr); | 157 | writew(tf->lbam, ioaddr->lbam_addr); |
158 | writew(tf->lbah, (void __iomem *) ioaddr->lbah_addr); | 158 | writew(tf->lbah, ioaddr->lbah_addr); |
159 | } | 159 | } |
160 | 160 | ||
161 | if (tf->flags & ATA_TFLAG_DEVICE) | 161 | if (tf->flags & ATA_TFLAG_DEVICE) |
162 | writeb(tf->device, (void __iomem *) ioaddr->device_addr); | 162 | writeb(tf->device, ioaddr->device_addr); |
163 | 163 | ||
164 | ata_wait_idle(ap); | 164 | ata_wait_idle(ap); |
165 | } | 165 | } |
@@ -171,12 +171,12 @@ static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | |||
171 | u16 nsect, lbal, lbam, lbah, feature; | 171 | u16 nsect, lbal, lbam, lbah, feature; |
172 | 172 | ||
173 | tf->command = k2_stat_check_status(ap); | 173 | tf->command = k2_stat_check_status(ap); |
174 | tf->device = readw((void __iomem *)ioaddr->device_addr); | 174 | tf->device = readw(ioaddr->device_addr); |
175 | feature = readw((void __iomem *)ioaddr->error_addr); | 175 | feature = readw(ioaddr->error_addr); |
176 | nsect = readw((void __iomem *)ioaddr->nsect_addr); | 176 | nsect = readw(ioaddr->nsect_addr); |
177 | lbal = readw((void __iomem *)ioaddr->lbal_addr); | 177 | lbal = readw(ioaddr->lbal_addr); |
178 | lbam = readw((void __iomem *)ioaddr->lbam_addr); | 178 | lbam = readw(ioaddr->lbam_addr); |
179 | lbah = readw((void __iomem *)ioaddr->lbah_addr); | 179 | lbah = readw(ioaddr->lbah_addr); |
180 | 180 | ||
181 | tf->feature = feature; | 181 | tf->feature = feature; |
182 | tf->nsect = nsect; | 182 | tf->nsect = nsect; |
@@ -349,7 +349,7 @@ static const struct ata_port_operations k2_sata_ops = { | |||
349 | .bmdma_status = ata_bmdma_status, | 349 | .bmdma_status = ata_bmdma_status, |
350 | .qc_prep = ata_qc_prep, | 350 | .qc_prep = ata_qc_prep, |
351 | .qc_issue = ata_qc_issue_prot, | 351 | .qc_issue = ata_qc_issue_prot, |
352 | .data_xfer = ata_mmio_data_xfer, | 352 | .data_xfer = ata_data_xfer, |
353 | .freeze = ata_bmdma_freeze, | 353 | .freeze = ata_bmdma_freeze, |
354 | .thaw = ata_bmdma_thaw, | 354 | .thaw = ata_bmdma_thaw, |
355 | .error_handler = ata_bmdma_error_handler, | 355 | .error_handler = ata_bmdma_error_handler, |
@@ -361,7 +361,7 @@ static const struct ata_port_operations k2_sata_ops = { | |||
361 | .port_start = ata_port_start, | 361 | .port_start = ata_port_start, |
362 | }; | 362 | }; |
363 | 363 | ||
364 | static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base) | 364 | static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base) |
365 | { | 365 | { |
366 | port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET; | 366 | port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET; |
367 | port->data_addr = base + K2_SATA_TF_DATA_OFFSET; | 367 | port->data_addr = base + K2_SATA_TF_DATA_OFFSET; |
@@ -386,7 +386,6 @@ static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *e | |||
386 | static int printed_version; | 386 | static int printed_version; |
387 | struct device *dev = &pdev->dev; | 387 | struct device *dev = &pdev->dev; |
388 | struct ata_probe_ent *probe_ent; | 388 | struct ata_probe_ent *probe_ent; |
389 | unsigned long base; | ||
390 | void __iomem *mmio_base; | 389 | void __iomem *mmio_base; |
391 | const struct k2_board_info *board_info = | 390 | const struct k2_board_info *board_info = |
392 | &k2_board_info[ent->driver_data]; | 391 | &k2_board_info[ent->driver_data]; |
@@ -410,12 +409,12 @@ static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *e | |||
410 | if (pci_resource_len(pdev, 5) == 0) | 409 | if (pci_resource_len(pdev, 5) == 0) |
411 | return -ENODEV; | 410 | return -ENODEV; |
412 | 411 | ||
413 | /* Request PCI regions */ | 412 | /* Request and iomap PCI regions */ |
414 | rc = pci_request_regions(pdev, DRV_NAME); | 413 | rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME); |
415 | if (rc) { | 414 | if (rc == -EBUSY) |
416 | pcim_pin_device(pdev); | 415 | pcim_pin_device(pdev); |
416 | if (rc) | ||
417 | return rc; | 417 | return rc; |
418 | } | ||
419 | 418 | ||
420 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | 419 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
421 | if (rc) | 420 | if (rc) |
@@ -431,22 +430,6 @@ static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *e | |||
431 | probe_ent->dev = pci_dev_to_dev(pdev); | 430 | probe_ent->dev = pci_dev_to_dev(pdev); |
432 | INIT_LIST_HEAD(&probe_ent->node); | 431 | INIT_LIST_HEAD(&probe_ent->node); |
433 | 432 | ||
434 | mmio_base = pcim_iomap(pdev, 5, 0); | ||
435 | if (mmio_base == NULL) | ||
436 | return -ENOMEM; | ||
437 | base = (unsigned long) mmio_base; | ||
438 | |||
439 | /* Clear a magic bit in SCR1 according to Darwin, those help | ||
440 | * some funky seagate drives (though so far, those were already | ||
441 | * set by the firmware on the machines I had access to) | ||
442 | */ | ||
443 | writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000, | ||
444 | mmio_base + K2_SATA_SICR1_OFFSET); | ||
445 | |||
446 | /* Clear SATA error & interrupts we don't use */ | ||
447 | writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET); | ||
448 | writel(0x0, mmio_base + K2_SATA_SIM_OFFSET); | ||
449 | |||
450 | probe_ent->sht = &k2_sata_sht; | 433 | probe_ent->sht = &k2_sata_sht; |
451 | probe_ent->port_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | 434 | probe_ent->port_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
452 | ATA_FLAG_MMIO | board_info->port_flags; | 435 | ATA_FLAG_MMIO | board_info->port_flags; |
@@ -454,7 +437,7 @@ static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *e | |||
454 | probe_ent->n_ports = 4; | 437 | probe_ent->n_ports = 4; |
455 | probe_ent->irq = pdev->irq; | 438 | probe_ent->irq = pdev->irq; |
456 | probe_ent->irq_flags = IRQF_SHARED; | 439 | probe_ent->irq_flags = IRQF_SHARED; |
457 | probe_ent->mmio_base = mmio_base; | 440 | probe_ent->iomap = pcim_iomap_table(pdev); |
458 | 441 | ||
459 | /* We don't care much about the PIO/UDMA masks, but the core won't like us | 442 | /* We don't care much about the PIO/UDMA masks, but the core won't like us |
460 | * if we don't fill these | 443 | * if we don't fill these |
@@ -463,11 +446,25 @@ static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *e | |||
463 | probe_ent->mwdma_mask = 0x7; | 446 | probe_ent->mwdma_mask = 0x7; |
464 | probe_ent->udma_mask = 0x7f; | 447 | probe_ent->udma_mask = 0x7f; |
465 | 448 | ||
449 | mmio_base = probe_ent->iomap[5]; | ||
450 | |||
466 | /* different controllers have different number of ports - currently 4 or 8 */ | 451 | /* different controllers have different number of ports - currently 4 or 8 */ |
467 | /* All ports are on the same function. Multi-function device is no | 452 | /* All ports are on the same function. Multi-function device is no |
468 | * longer available. This should not be seen in any system. */ | 453 | * longer available. This should not be seen in any system. */ |
469 | for (i = 0; i < board_info->n_ports; i++) | 454 | for (i = 0; i < board_info->n_ports; i++) |
470 | k2_sata_setup_port(&probe_ent->port[i], base + i * K2_SATA_PORT_OFFSET); | 455 | k2_sata_setup_port(&probe_ent->port[i], |
456 | mmio_base + i * K2_SATA_PORT_OFFSET); | ||
457 | |||
458 | /* Clear a magic bit in SCR1 according to Darwin, those help | ||
459 | * some funky seagate drives (though so far, those were already | ||
460 | * set by the firmware on the machines I had access to) | ||
461 | */ | ||
462 | writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000, | ||
463 | mmio_base + K2_SATA_SICR1_OFFSET); | ||
464 | |||
465 | /* Clear SATA error & interrupts we don't use */ | ||
466 | writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET); | ||
467 | writel(0x0, mmio_base + K2_SATA_SIM_OFFSET); | ||
471 | 468 | ||
472 | pci_set_master(pdev); | 469 | pci_set_master(pdev); |
473 | 470 | ||
diff --git a/drivers/ata/sata_sx4.c b/drivers/ata/sata_sx4.c index d9838dcb4b01..f83038cf1b35 100644 --- a/drivers/ata/sata_sx4.c +++ b/drivers/ata/sata_sx4.c | |||
@@ -49,6 +49,9 @@ | |||
49 | 49 | ||
50 | 50 | ||
51 | enum { | 51 | enum { |
52 | PDC_MMIO_BAR = 3, | ||
53 | PDC_DIMM_BAR = 4, | ||
54 | |||
52 | PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */ | 55 | PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */ |
53 | 56 | ||
54 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ | 57 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ |
@@ -137,8 +140,6 @@ struct pdc_port_priv { | |||
137 | }; | 140 | }; |
138 | 141 | ||
139 | struct pdc_host_priv { | 142 | struct pdc_host_priv { |
140 | void __iomem *dimm_mmio; | ||
141 | |||
142 | unsigned int doing_hdma; | 143 | unsigned int doing_hdma; |
143 | unsigned int hdma_prod; | 144 | unsigned int hdma_prod; |
144 | unsigned int hdma_cons; | 145 | unsigned int hdma_cons; |
@@ -202,7 +203,7 @@ static const struct ata_port_operations pdc_20621_ops = { | |||
202 | .phy_reset = pdc_20621_phy_reset, | 203 | .phy_reset = pdc_20621_phy_reset, |
203 | .qc_prep = pdc20621_qc_prep, | 204 | .qc_prep = pdc20621_qc_prep, |
204 | .qc_issue = pdc20621_qc_issue_prot, | 205 | .qc_issue = pdc20621_qc_issue_prot, |
205 | .data_xfer = ata_mmio_data_xfer, | 206 | .data_xfer = ata_data_xfer, |
206 | .eng_timeout = pdc_eng_timeout, | 207 | .eng_timeout = pdc_eng_timeout, |
207 | .irq_handler = pdc20621_interrupt, | 208 | .irq_handler = pdc20621_interrupt, |
208 | .irq_clear = pdc20621_irq_clear, | 209 | .irq_clear = pdc20621_irq_clear, |
@@ -411,9 +412,8 @@ static void pdc20621_dma_prep(struct ata_queued_cmd *qc) | |||
411 | struct scatterlist *sg; | 412 | struct scatterlist *sg; |
412 | struct ata_port *ap = qc->ap; | 413 | struct ata_port *ap = qc->ap; |
413 | struct pdc_port_priv *pp = ap->private_data; | 414 | struct pdc_port_priv *pp = ap->private_data; |
414 | void __iomem *mmio = ap->host->mmio_base; | 415 | void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; |
415 | struct pdc_host_priv *hpriv = ap->host->private_data; | 416 | void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR]; |
416 | void __iomem *dimm_mmio = hpriv->dimm_mmio; | ||
417 | unsigned int portno = ap->port_no; | 417 | unsigned int portno = ap->port_no; |
418 | unsigned int i, idx, total_len = 0, sgt_len; | 418 | unsigned int i, idx, total_len = 0, sgt_len; |
419 | u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ]; | 419 | u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ]; |
@@ -472,9 +472,8 @@ static void pdc20621_nodata_prep(struct ata_queued_cmd *qc) | |||
472 | { | 472 | { |
473 | struct ata_port *ap = qc->ap; | 473 | struct ata_port *ap = qc->ap; |
474 | struct pdc_port_priv *pp = ap->private_data; | 474 | struct pdc_port_priv *pp = ap->private_data; |
475 | void __iomem *mmio = ap->host->mmio_base; | 475 | void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; |
476 | struct pdc_host_priv *hpriv = ap->host->private_data; | 476 | void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR]; |
477 | void __iomem *dimm_mmio = hpriv->dimm_mmio; | ||
478 | unsigned int portno = ap->port_no; | 477 | unsigned int portno = ap->port_no; |
479 | unsigned int i; | 478 | unsigned int i; |
480 | 479 | ||
@@ -524,7 +523,7 @@ static void __pdc20621_push_hdma(struct ata_queued_cmd *qc, | |||
524 | { | 523 | { |
525 | struct ata_port *ap = qc->ap; | 524 | struct ata_port *ap = qc->ap; |
526 | struct ata_host *host = ap->host; | 525 | struct ata_host *host = ap->host; |
527 | void __iomem *mmio = host->mmio_base; | 526 | void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; |
528 | 527 | ||
529 | /* hard-code chip #0 */ | 528 | /* hard-code chip #0 */ |
530 | mmio += PDC_CHIP0_OFS; | 529 | mmio += PDC_CHIP0_OFS; |
@@ -578,8 +577,7 @@ static void pdc20621_dump_hdma(struct ata_queued_cmd *qc) | |||
578 | { | 577 | { |
579 | struct ata_port *ap = qc->ap; | 578 | struct ata_port *ap = qc->ap; |
580 | unsigned int port_no = ap->port_no; | 579 | unsigned int port_no = ap->port_no; |
581 | struct pdc_host_priv *hpriv = ap->host->private_data; | 580 | void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR]; |
582 | void *dimm_mmio = hpriv->dimm_mmio; | ||
583 | 581 | ||
584 | dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP); | 582 | dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP); |
585 | dimm_mmio += PDC_DIMM_HOST_PKT; | 583 | dimm_mmio += PDC_DIMM_HOST_PKT; |
@@ -598,7 +596,7 @@ static void pdc20621_packet_start(struct ata_queued_cmd *qc) | |||
598 | struct ata_port *ap = qc->ap; | 596 | struct ata_port *ap = qc->ap; |
599 | struct ata_host *host = ap->host; | 597 | struct ata_host *host = ap->host; |
600 | unsigned int port_no = ap->port_no; | 598 | unsigned int port_no = ap->port_no; |
601 | void __iomem *mmio = host->mmio_base; | 599 | void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; |
602 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | 600 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); |
603 | u8 seq = (u8) (port_no + 1); | 601 | u8 seq = (u8) (port_no + 1); |
604 | unsigned int port_ofs; | 602 | unsigned int port_ofs; |
@@ -627,8 +625,8 @@ static void pdc20621_packet_start(struct ata_queued_cmd *qc) | |||
627 | readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ | 625 | readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ |
628 | 626 | ||
629 | writel(port_ofs + PDC_DIMM_ATA_PKT, | 627 | writel(port_ofs + PDC_DIMM_ATA_PKT, |
630 | (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); | 628 | ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
631 | readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); | 629 | readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
632 | VPRINTK("submitted ofs 0x%x (%u), seq %u\n", | 630 | VPRINTK("submitted ofs 0x%x (%u), seq %u\n", |
633 | port_ofs + PDC_DIMM_ATA_PKT, | 631 | port_ofs + PDC_DIMM_ATA_PKT, |
634 | port_ofs + PDC_DIMM_ATA_PKT, | 632 | port_ofs + PDC_DIMM_ATA_PKT, |
@@ -706,8 +704,8 @@ static inline unsigned int pdc20621_host_intr( struct ata_port *ap, | |||
706 | writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); | 704 | writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); |
707 | readl(mmio + PDC_20621_SEQCTL + (seq * 4)); | 705 | readl(mmio + PDC_20621_SEQCTL + (seq * 4)); |
708 | writel(port_ofs + PDC_DIMM_ATA_PKT, | 706 | writel(port_ofs + PDC_DIMM_ATA_PKT, |
709 | (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); | 707 | ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
710 | readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); | 708 | readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
711 | } | 709 | } |
712 | 710 | ||
713 | /* step two - execute ATA command */ | 711 | /* step two - execute ATA command */ |
@@ -740,7 +738,7 @@ static inline unsigned int pdc20621_host_intr( struct ata_port *ap, | |||
740 | static void pdc20621_irq_clear(struct ata_port *ap) | 738 | static void pdc20621_irq_clear(struct ata_port *ap) |
741 | { | 739 | { |
742 | struct ata_host *host = ap->host; | 740 | struct ata_host *host = ap->host; |
743 | void __iomem *mmio = host->mmio_base; | 741 | void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; |
744 | 742 | ||
745 | mmio += PDC_CHIP0_OFS; | 743 | mmio += PDC_CHIP0_OFS; |
746 | 744 | ||
@@ -758,12 +756,12 @@ static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance) | |||
758 | 756 | ||
759 | VPRINTK("ENTER\n"); | 757 | VPRINTK("ENTER\n"); |
760 | 758 | ||
761 | if (!host || !host->mmio_base) { | 759 | if (!host || !host->iomap[PDC_MMIO_BAR]) { |
762 | VPRINTK("QUICK EXIT\n"); | 760 | VPRINTK("QUICK EXIT\n"); |
763 | return IRQ_NONE; | 761 | return IRQ_NONE; |
764 | } | 762 | } |
765 | 763 | ||
766 | mmio_base = host->mmio_base; | 764 | mmio_base = host->iomap[PDC_MMIO_BAR]; |
767 | 765 | ||
768 | /* reading should also clear interrupts */ | 766 | /* reading should also clear interrupts */ |
769 | mmio_base += PDC_CHIP0_OFS; | 767 | mmio_base += PDC_CHIP0_OFS; |
@@ -864,7 +862,7 @@ static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile | |||
864 | } | 862 | } |
865 | 863 | ||
866 | 864 | ||
867 | static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base) | 865 | static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base) |
868 | { | 866 | { |
869 | port->cmd_addr = base; | 867 | port->cmd_addr = base; |
870 | port->data_addr = base; | 868 | port->data_addr = base; |
@@ -890,9 +888,8 @@ static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource, | |||
890 | u16 idx; | 888 | u16 idx; |
891 | u8 page_mask; | 889 | u8 page_mask; |
892 | long dist; | 890 | long dist; |
893 | void __iomem *mmio = pe->mmio_base; | 891 | void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; |
894 | struct pdc_host_priv *hpriv = pe->private_data; | 892 | void __iomem *dimm_mmio = pe->iomap[PDC_DIMM_BAR]; |
895 | void __iomem *dimm_mmio = hpriv->dimm_mmio; | ||
896 | 893 | ||
897 | /* hard-code chip #0 */ | 894 | /* hard-code chip #0 */ |
898 | mmio += PDC_CHIP0_OFS; | 895 | mmio += PDC_CHIP0_OFS; |
@@ -946,9 +943,8 @@ static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource, | |||
946 | u16 idx; | 943 | u16 idx; |
947 | u8 page_mask; | 944 | u8 page_mask; |
948 | long dist; | 945 | long dist; |
949 | void __iomem *mmio = pe->mmio_base; | 946 | void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; |
950 | struct pdc_host_priv *hpriv = pe->private_data; | 947 | void __iomem *dimm_mmio = pe->iomap[PDC_DIMM_BAR]; |
951 | void __iomem *dimm_mmio = hpriv->dimm_mmio; | ||
952 | 948 | ||
953 | /* hard-code chip #0 */ | 949 | /* hard-code chip #0 */ |
954 | mmio += PDC_CHIP0_OFS; | 950 | mmio += PDC_CHIP0_OFS; |
@@ -993,7 +989,7 @@ static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource, | |||
993 | static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device, | 989 | static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device, |
994 | u32 subaddr, u32 *pdata) | 990 | u32 subaddr, u32 *pdata) |
995 | { | 991 | { |
996 | void __iomem *mmio = pe->mmio_base; | 992 | void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; |
997 | u32 i2creg = 0; | 993 | u32 i2creg = 0; |
998 | u32 status; | 994 | u32 status; |
999 | u32 count =0; | 995 | u32 count =0; |
@@ -1052,7 +1048,7 @@ static int pdc20621_prog_dimm0(struct ata_probe_ent *pe) | |||
1052 | u32 data = 0; | 1048 | u32 data = 0; |
1053 | int size, i; | 1049 | int size, i; |
1054 | u8 bdimmsize; | 1050 | u8 bdimmsize; |
1055 | void __iomem *mmio = pe->mmio_base; | 1051 | void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; |
1056 | static const struct { | 1052 | static const struct { |
1057 | unsigned int reg; | 1053 | unsigned int reg; |
1058 | unsigned int ofs; | 1054 | unsigned int ofs; |
@@ -1114,8 +1110,8 @@ static int pdc20621_prog_dimm0(struct ata_probe_ent *pe) | |||
1114 | static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe) | 1110 | static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe) |
1115 | { | 1111 | { |
1116 | u32 data, spd0; | 1112 | u32 data, spd0; |
1117 | int error, i; | 1113 | int error, i; |
1118 | void __iomem *mmio = pe->mmio_base; | 1114 | void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; |
1119 | 1115 | ||
1120 | /* hard-code chip #0 */ | 1116 | /* hard-code chip #0 */ |
1121 | mmio += PDC_CHIP0_OFS; | 1117 | mmio += PDC_CHIP0_OFS; |
@@ -1169,7 +1165,7 @@ static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe) | |||
1169 | u32 ticks=0; | 1165 | u32 ticks=0; |
1170 | u32 clock=0; | 1166 | u32 clock=0; |
1171 | u32 fparam=0; | 1167 | u32 fparam=0; |
1172 | void __iomem *mmio = pe->mmio_base; | 1168 | void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; |
1173 | 1169 | ||
1174 | /* hard-code chip #0 */ | 1170 | /* hard-code chip #0 */ |
1175 | mmio += PDC_CHIP0_OFS; | 1171 | mmio += PDC_CHIP0_OFS; |
@@ -1293,7 +1289,7 @@ static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe) | |||
1293 | static void pdc_20621_init(struct ata_probe_ent *pe) | 1289 | static void pdc_20621_init(struct ata_probe_ent *pe) |
1294 | { | 1290 | { |
1295 | u32 tmp; | 1291 | u32 tmp; |
1296 | void __iomem *mmio = pe->mmio_base; | 1292 | void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; |
1297 | 1293 | ||
1298 | /* hard-code chip #0 */ | 1294 | /* hard-code chip #0 */ |
1299 | mmio += PDC_CHIP0_OFS; | 1295 | mmio += PDC_CHIP0_OFS; |
@@ -1325,9 +1321,7 @@ static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id * | |||
1325 | { | 1321 | { |
1326 | static int printed_version; | 1322 | static int printed_version; |
1327 | struct ata_probe_ent *probe_ent; | 1323 | struct ata_probe_ent *probe_ent; |
1328 | unsigned long base; | 1324 | void __iomem *base; |
1329 | void __iomem *mmio_base; | ||
1330 | void __iomem *dimm_mmio; | ||
1331 | struct pdc_host_priv *hpriv; | 1325 | struct pdc_host_priv *hpriv; |
1332 | unsigned int board_idx = (unsigned int) ent->driver_data; | 1326 | unsigned int board_idx = (unsigned int) ent->driver_data; |
1333 | int rc; | 1327 | int rc; |
@@ -1339,11 +1333,12 @@ static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id * | |||
1339 | if (rc) | 1333 | if (rc) |
1340 | return rc; | 1334 | return rc; |
1341 | 1335 | ||
1342 | rc = pci_request_regions(pdev, DRV_NAME); | 1336 | rc = pcim_iomap_regions(pdev, (1 << PDC_MMIO_BAR) | (1 << PDC_DIMM_BAR), |
1343 | if (rc) { | 1337 | DRV_NAME); |
1338 | if (rc == -EBUSY) | ||
1344 | pcim_pin_device(pdev); | 1339 | pcim_pin_device(pdev); |
1340 | if (rc) | ||
1345 | return rc; | 1341 | return rc; |
1346 | } | ||
1347 | 1342 | ||
1348 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | 1343 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
1349 | if (rc) | 1344 | if (rc) |
@@ -1359,21 +1354,10 @@ static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id * | |||
1359 | probe_ent->dev = pci_dev_to_dev(pdev); | 1354 | probe_ent->dev = pci_dev_to_dev(pdev); |
1360 | INIT_LIST_HEAD(&probe_ent->node); | 1355 | INIT_LIST_HEAD(&probe_ent->node); |
1361 | 1356 | ||
1362 | mmio_base = pcim_iomap(pdev, 3, 0); | ||
1363 | if (mmio_base == NULL) | ||
1364 | return -ENOMEM; | ||
1365 | base = (unsigned long) mmio_base; | ||
1366 | |||
1367 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); | 1357 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); |
1368 | if (!hpriv) | 1358 | if (!hpriv) |
1369 | return -ENOMEM; | 1359 | return -ENOMEM; |
1370 | 1360 | ||
1371 | dimm_mmio = pcim_iomap(pdev, 4, 0); | ||
1372 | if (!dimm_mmio) | ||
1373 | return -ENOMEM; | ||
1374 | |||
1375 | hpriv->dimm_mmio = dimm_mmio; | ||
1376 | |||
1377 | probe_ent->sht = pdc_port_info[board_idx].sht; | 1361 | probe_ent->sht = pdc_port_info[board_idx].sht; |
1378 | probe_ent->port_flags = pdc_port_info[board_idx].flags; | 1362 | probe_ent->port_flags = pdc_port_info[board_idx].flags; |
1379 | probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; | 1363 | probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; |
@@ -1383,10 +1367,10 @@ static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id * | |||
1383 | 1367 | ||
1384 | probe_ent->irq = pdev->irq; | 1368 | probe_ent->irq = pdev->irq; |
1385 | probe_ent->irq_flags = IRQF_SHARED; | 1369 | probe_ent->irq_flags = IRQF_SHARED; |
1386 | probe_ent->mmio_base = mmio_base; | 1370 | probe_ent->iomap = pcim_iomap_table(pdev); |
1387 | 1371 | ||
1388 | probe_ent->private_data = hpriv; | 1372 | probe_ent->private_data = hpriv; |
1389 | base += PDC_CHIP0_OFS; | 1373 | base = probe_ent->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS; |
1390 | 1374 | ||
1391 | probe_ent->n_ports = 4; | 1375 | probe_ent->n_ports = 4; |
1392 | pdc_sata_setup_port(&probe_ent->port[0], base + 0x200); | 1376 | pdc_sata_setup_port(&probe_ent->port[0], base + 0x200); |
diff --git a/drivers/ata/sata_uli.c b/drivers/ata/sata_uli.c index 22eed6d07495..77de7cbbe1ae 100644 --- a/drivers/ata/sata_uli.c +++ b/drivers/ata/sata_uli.c | |||
@@ -108,7 +108,7 @@ static const struct ata_port_operations uli_ops = { | |||
108 | .bmdma_status = ata_bmdma_status, | 108 | .bmdma_status = ata_bmdma_status, |
109 | .qc_prep = ata_qc_prep, | 109 | .qc_prep = ata_qc_prep, |
110 | .qc_issue = ata_qc_issue_prot, | 110 | .qc_issue = ata_qc_issue_prot, |
111 | .data_xfer = ata_pio_data_xfer, | 111 | .data_xfer = ata_data_xfer, |
112 | 112 | ||
113 | .freeze = ata_bmdma_freeze, | 113 | .freeze = ata_bmdma_freeze, |
114 | .thaw = ata_bmdma_thaw, | 114 | .thaw = ata_bmdma_thaw, |
@@ -188,6 +188,7 @@ static int uli_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |||
188 | int rc; | 188 | int rc; |
189 | unsigned int board_idx = (unsigned int) ent->driver_data; | 189 | unsigned int board_idx = (unsigned int) ent->driver_data; |
190 | struct uli_priv *hpriv; | 190 | struct uli_priv *hpriv; |
191 | void __iomem * const *iomap; | ||
191 | 192 | ||
192 | if (!printed_version++) | 193 | if (!printed_version++) |
193 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); | 194 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); |
@@ -220,24 +221,26 @@ static int uli_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |||
220 | 221 | ||
221 | probe_ent->private_data = hpriv; | 222 | probe_ent->private_data = hpriv; |
222 | 223 | ||
224 | iomap = pcim_iomap_table(pdev); | ||
225 | |||
223 | switch (board_idx) { | 226 | switch (board_idx) { |
224 | case uli_5287: | 227 | case uli_5287: |
225 | hpriv->scr_cfg_addr[0] = ULI5287_BASE; | 228 | hpriv->scr_cfg_addr[0] = ULI5287_BASE; |
226 | hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS; | 229 | hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS; |
227 | probe_ent->n_ports = 4; | 230 | probe_ent->n_ports = 4; |
228 | 231 | ||
229 | probe_ent->port[2].cmd_addr = pci_resource_start(pdev, 0) + 8; | 232 | probe_ent->port[2].cmd_addr = iomap[0] + 8; |
230 | probe_ent->port[2].altstatus_addr = | 233 | probe_ent->port[2].altstatus_addr = |
231 | probe_ent->port[2].ctl_addr = | 234 | probe_ent->port[2].ctl_addr = (void __iomem *) |
232 | (pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS) + 4; | 235 | ((unsigned long)iomap[1] | ATA_PCI_CTL_OFS) + 4; |
233 | probe_ent->port[2].bmdma_addr = pci_resource_start(pdev, 4) + 16; | 236 | probe_ent->port[2].bmdma_addr = iomap[4] + 16; |
234 | hpriv->scr_cfg_addr[2] = ULI5287_BASE + ULI5287_OFFS*4; | 237 | hpriv->scr_cfg_addr[2] = ULI5287_BASE + ULI5287_OFFS*4; |
235 | 238 | ||
236 | probe_ent->port[3].cmd_addr = pci_resource_start(pdev, 2) + 8; | 239 | probe_ent->port[3].cmd_addr = iomap[2] + 8; |
237 | probe_ent->port[3].altstatus_addr = | 240 | probe_ent->port[3].altstatus_addr = |
238 | probe_ent->port[3].ctl_addr = | 241 | probe_ent->port[3].ctl_addr = (void __iomem *) |
239 | (pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS) + 4; | 242 | ((unsigned long)iomap[3] | ATA_PCI_CTL_OFS) + 4; |
240 | probe_ent->port[3].bmdma_addr = pci_resource_start(pdev, 4) + 24; | 243 | probe_ent->port[3].bmdma_addr = iomap[4] + 24; |
241 | hpriv->scr_cfg_addr[3] = ULI5287_BASE + ULI5287_OFFS*5; | 244 | hpriv->scr_cfg_addr[3] = ULI5287_BASE + ULI5287_OFFS*5; |
242 | 245 | ||
243 | ata_std_ports(&probe_ent->port[2]); | 246 | ata_std_ports(&probe_ent->port[2]); |
diff --git a/drivers/ata/sata_via.c b/drivers/ata/sata_via.c index c7f527578d11..6b558195a76f 100644 --- a/drivers/ata/sata_via.c +++ b/drivers/ata/sata_via.c | |||
@@ -134,7 +134,7 @@ static const struct ata_port_operations vt6420_sata_ops = { | |||
134 | 134 | ||
135 | .qc_prep = ata_qc_prep, | 135 | .qc_prep = ata_qc_prep, |
136 | .qc_issue = ata_qc_issue_prot, | 136 | .qc_issue = ata_qc_issue_prot, |
137 | .data_xfer = ata_pio_data_xfer, | 137 | .data_xfer = ata_data_xfer, |
138 | 138 | ||
139 | .freeze = svia_noop_freeze, | 139 | .freeze = svia_noop_freeze, |
140 | .thaw = ata_bmdma_thaw, | 140 | .thaw = ata_bmdma_thaw, |
@@ -166,7 +166,7 @@ static const struct ata_port_operations vt6421_pata_ops = { | |||
166 | 166 | ||
167 | .qc_prep = ata_qc_prep, | 167 | .qc_prep = ata_qc_prep, |
168 | .qc_issue = ata_qc_issue_prot, | 168 | .qc_issue = ata_qc_issue_prot, |
169 | .data_xfer = ata_pio_data_xfer, | 169 | .data_xfer = ata_data_xfer, |
170 | 170 | ||
171 | .freeze = ata_bmdma_freeze, | 171 | .freeze = ata_bmdma_freeze, |
172 | .thaw = ata_bmdma_thaw, | 172 | .thaw = ata_bmdma_thaw, |
@@ -195,7 +195,7 @@ static const struct ata_port_operations vt6421_sata_ops = { | |||
195 | 195 | ||
196 | .qc_prep = ata_qc_prep, | 196 | .qc_prep = ata_qc_prep, |
197 | .qc_issue = ata_qc_issue_prot, | 197 | .qc_issue = ata_qc_issue_prot, |
198 | .data_xfer = ata_pio_data_xfer, | 198 | .data_xfer = ata_data_xfer, |
199 | 199 | ||
200 | .freeze = ata_bmdma_freeze, | 200 | .freeze = ata_bmdma_freeze, |
201 | .thaw = ata_bmdma_thaw, | 201 | .thaw = ata_bmdma_thaw, |
@@ -230,14 +230,14 @@ static u32 svia_scr_read (struct ata_port *ap, unsigned int sc_reg) | |||
230 | { | 230 | { |
231 | if (sc_reg > SCR_CONTROL) | 231 | if (sc_reg > SCR_CONTROL) |
232 | return 0xffffffffU; | 232 | return 0xffffffffU; |
233 | return inl(ap->ioaddr.scr_addr + (4 * sc_reg)); | 233 | return ioread32(ap->ioaddr.scr_addr + (4 * sc_reg)); |
234 | } | 234 | } |
235 | 235 | ||
236 | static void svia_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | 236 | static void svia_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) |
237 | { | 237 | { |
238 | if (sc_reg > SCR_CONTROL) | 238 | if (sc_reg > SCR_CONTROL) |
239 | return; | 239 | return; |
240 | outl(val, ap->ioaddr.scr_addr + (4 * sc_reg)); | 240 | iowrite32(val, ap->ioaddr.scr_addr + (4 * sc_reg)); |
241 | } | 241 | } |
242 | 242 | ||
243 | static void svia_noop_freeze(struct ata_port *ap) | 243 | static void svia_noop_freeze(struct ata_port *ap) |
@@ -387,31 +387,28 @@ static const unsigned int vt6421_bar_sizes[] = { | |||
387 | 16, 16, 16, 16, 32, 128 | 387 | 16, 16, 16, 16, 32, 128 |
388 | }; | 388 | }; |
389 | 389 | ||
390 | static unsigned long svia_scr_addr(unsigned long addr, unsigned int port) | 390 | static void __iomem * svia_scr_addr(void __iomem *addr, unsigned int port) |
391 | { | 391 | { |
392 | return addr + (port * 128); | 392 | return addr + (port * 128); |
393 | } | 393 | } |
394 | 394 | ||
395 | static unsigned long vt6421_scr_addr(unsigned long addr, unsigned int port) | 395 | static void __iomem * vt6421_scr_addr(void __iomem *addr, unsigned int port) |
396 | { | 396 | { |
397 | return addr + (port * 64); | 397 | return addr + (port * 64); |
398 | } | 398 | } |
399 | 399 | ||
400 | static void vt6421_init_addrs(struct ata_probe_ent *probe_ent, | 400 | static void vt6421_init_addrs(struct ata_probe_ent *probe_ent, |
401 | struct pci_dev *pdev, | 401 | void __iomem * const *iomap, unsigned int port) |
402 | unsigned int port) | ||
403 | { | 402 | { |
404 | unsigned long reg_addr = pci_resource_start(pdev, port); | 403 | void __iomem *reg_addr = iomap[port]; |
405 | unsigned long bmdma_addr = pci_resource_start(pdev, 4) + (port * 8); | 404 | void __iomem *bmdma_addr = iomap[4] + (port * 8); |
406 | unsigned long scr_addr; | ||
407 | 405 | ||
408 | probe_ent->port[port].cmd_addr = reg_addr; | 406 | probe_ent->port[port].cmd_addr = reg_addr; |
409 | probe_ent->port[port].altstatus_addr = | 407 | probe_ent->port[port].altstatus_addr = |
410 | probe_ent->port[port].ctl_addr = (reg_addr + 8) | ATA_PCI_CTL_OFS; | 408 | probe_ent->port[port].ctl_addr = (void __iomem *) |
409 | ((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS); | ||
411 | probe_ent->port[port].bmdma_addr = bmdma_addr; | 410 | probe_ent->port[port].bmdma_addr = bmdma_addr; |
412 | 411 | probe_ent->port[port].scr_addr = vt6421_scr_addr(iomap[5], port); | |
413 | scr_addr = vt6421_scr_addr(pci_resource_start(pdev, 5), port); | ||
414 | probe_ent->port[port].scr_addr = scr_addr; | ||
415 | 412 | ||
416 | ata_std_ports(&probe_ent->port[port]); | 413 | ata_std_ports(&probe_ent->port[port]); |
417 | } | 414 | } |
@@ -420,16 +417,16 @@ static struct ata_probe_ent *vt6420_init_probe_ent(struct pci_dev *pdev) | |||
420 | { | 417 | { |
421 | struct ata_probe_ent *probe_ent; | 418 | struct ata_probe_ent *probe_ent; |
422 | struct ata_port_info *ppi[2]; | 419 | struct ata_port_info *ppi[2]; |
420 | void __iomem * const *iomap; | ||
423 | 421 | ||
424 | ppi[0] = ppi[1] = &vt6420_port_info; | 422 | ppi[0] = ppi[1] = &vt6420_port_info; |
425 | probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY); | 423 | probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY); |
426 | if (!probe_ent) | 424 | if (!probe_ent) |
427 | return NULL; | 425 | return NULL; |
428 | 426 | ||
429 | probe_ent->port[0].scr_addr = | 427 | iomap = pcim_iomap_table(pdev); |
430 | svia_scr_addr(pci_resource_start(pdev, 5), 0); | 428 | probe_ent->port[0].scr_addr = svia_scr_addr(iomap[5], 0); |
431 | probe_ent->port[1].scr_addr = | 429 | probe_ent->port[1].scr_addr = svia_scr_addr(iomap[5], 1); |
432 | svia_scr_addr(pci_resource_start(pdev, 5), 1); | ||
433 | 430 | ||
434 | return probe_ent; | 431 | return probe_ent; |
435 | } | 432 | } |
@@ -458,7 +455,7 @@ static struct ata_probe_ent *vt6421_init_probe_ent(struct pci_dev *pdev) | |||
458 | probe_ent->udma_mask = 0x7f; | 455 | probe_ent->udma_mask = 0x7f; |
459 | 456 | ||
460 | for (i = 0; i < N_PORTS; i++) | 457 | for (i = 0; i < N_PORTS; i++) |
461 | vt6421_init_addrs(probe_ent, pdev, i); | 458 | vt6421_init_addrs(probe_ent, pcim_iomap_table(pdev), i); |
462 | 459 | ||
463 | return probe_ent; | 460 | return probe_ent; |
464 | } | 461 | } |
@@ -519,7 +516,7 @@ static int svia_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |||
519 | if (rc) | 516 | if (rc) |
520 | return rc; | 517 | return rc; |
521 | 518 | ||
522 | rc = pci_request_regions(pdev, DRV_NAME); | 519 | rc = pcim_iomap_regions(pdev, 0x1f, DRV_NAME); |
523 | if (rc) { | 520 | if (rc) { |
524 | pcim_pin_device(pdev); | 521 | pcim_pin_device(pdev); |
525 | return rc; | 522 | return rc; |
diff --git a/drivers/ata/sata_vsc.c b/drivers/ata/sata_vsc.c index af77f71bdaa5..7596e9ace50b 100644 --- a/drivers/ata/sata_vsc.c +++ b/drivers/ata/sata_vsc.c | |||
@@ -50,6 +50,8 @@ | |||
50 | #define DRV_VERSION "2.0" | 50 | #define DRV_VERSION "2.0" |
51 | 51 | ||
52 | enum { | 52 | enum { |
53 | VSC_MMIO_BAR = 0, | ||
54 | |||
53 | /* Interrupt register offsets (from chip base address) */ | 55 | /* Interrupt register offsets (from chip base address) */ |
54 | VSC_SATA_INT_STAT_OFFSET = 0x00, | 56 | VSC_SATA_INT_STAT_OFFSET = 0x00, |
55 | VSC_SATA_INT_MASK_OFFSET = 0x04, | 57 | VSC_SATA_INT_MASK_OFFSET = 0x04, |
@@ -104,7 +106,7 @@ static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) | |||
104 | { | 106 | { |
105 | if (sc_reg > SCR_CONTROL) | 107 | if (sc_reg > SCR_CONTROL) |
106 | return 0xffffffffU; | 108 | return 0xffffffffU; |
107 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); | 109 | return readl(ap->ioaddr.scr_addr + (sc_reg * 4)); |
108 | } | 110 | } |
109 | 111 | ||
110 | 112 | ||
@@ -113,7 +115,7 @@ static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |||
113 | { | 115 | { |
114 | if (sc_reg > SCR_CONTROL) | 116 | if (sc_reg > SCR_CONTROL) |
115 | return; | 117 | return; |
116 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); | 118 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
117 | } | 119 | } |
118 | 120 | ||
119 | 121 | ||
@@ -122,7 +124,7 @@ static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl) | |||
122 | void __iomem *mask_addr; | 124 | void __iomem *mask_addr; |
123 | u8 mask; | 125 | u8 mask; |
124 | 126 | ||
125 | mask_addr = ap->host->mmio_base + | 127 | mask_addr = ap->host->iomap[VSC_MMIO_BAR] + |
126 | VSC_SATA_INT_MASK_OFFSET + ap->port_no; | 128 | VSC_SATA_INT_MASK_OFFSET + ap->port_no; |
127 | mask = readb(mask_addr); | 129 | mask = readb(mask_addr); |
128 | if (ctl & ATA_NIEN) | 130 | if (ctl & ATA_NIEN) |
@@ -149,25 +151,25 @@ static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) | |||
149 | } | 151 | } |
150 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | 152 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { |
151 | writew(tf->feature | (((u16)tf->hob_feature) << 8), | 153 | writew(tf->feature | (((u16)tf->hob_feature) << 8), |
152 | (void __iomem *) ioaddr->feature_addr); | 154 | ioaddr->feature_addr); |
153 | writew(tf->nsect | (((u16)tf->hob_nsect) << 8), | 155 | writew(tf->nsect | (((u16)tf->hob_nsect) << 8), |
154 | (void __iomem *) ioaddr->nsect_addr); | 156 | ioaddr->nsect_addr); |
155 | writew(tf->lbal | (((u16)tf->hob_lbal) << 8), | 157 | writew(tf->lbal | (((u16)tf->hob_lbal) << 8), |
156 | (void __iomem *) ioaddr->lbal_addr); | 158 | ioaddr->lbal_addr); |
157 | writew(tf->lbam | (((u16)tf->hob_lbam) << 8), | 159 | writew(tf->lbam | (((u16)tf->hob_lbam) << 8), |
158 | (void __iomem *) ioaddr->lbam_addr); | 160 | ioaddr->lbam_addr); |
159 | writew(tf->lbah | (((u16)tf->hob_lbah) << 8), | 161 | writew(tf->lbah | (((u16)tf->hob_lbah) << 8), |
160 | (void __iomem *) ioaddr->lbah_addr); | 162 | ioaddr->lbah_addr); |
161 | } else if (is_addr) { | 163 | } else if (is_addr) { |
162 | writew(tf->feature, (void __iomem *) ioaddr->feature_addr); | 164 | writew(tf->feature, ioaddr->feature_addr); |
163 | writew(tf->nsect, (void __iomem *) ioaddr->nsect_addr); | 165 | writew(tf->nsect, ioaddr->nsect_addr); |
164 | writew(tf->lbal, (void __iomem *) ioaddr->lbal_addr); | 166 | writew(tf->lbal, ioaddr->lbal_addr); |
165 | writew(tf->lbam, (void __iomem *) ioaddr->lbam_addr); | 167 | writew(tf->lbam, ioaddr->lbam_addr); |
166 | writew(tf->lbah, (void __iomem *) ioaddr->lbah_addr); | 168 | writew(tf->lbah, ioaddr->lbah_addr); |
167 | } | 169 | } |
168 | 170 | ||
169 | if (tf->flags & ATA_TFLAG_DEVICE) | 171 | if (tf->flags & ATA_TFLAG_DEVICE) |
170 | writeb(tf->device, (void __iomem *) ioaddr->device_addr); | 172 | writeb(tf->device, ioaddr->device_addr); |
171 | 173 | ||
172 | ata_wait_idle(ap); | 174 | ata_wait_idle(ap); |
173 | } | 175 | } |
@@ -179,12 +181,12 @@ static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | |||
179 | u16 nsect, lbal, lbam, lbah, feature; | 181 | u16 nsect, lbal, lbam, lbah, feature; |
180 | 182 | ||
181 | tf->command = ata_check_status(ap); | 183 | tf->command = ata_check_status(ap); |
182 | tf->device = readw((void __iomem *) ioaddr->device_addr); | 184 | tf->device = readw(ioaddr->device_addr); |
183 | feature = readw((void __iomem *) ioaddr->error_addr); | 185 | feature = readw(ioaddr->error_addr); |
184 | nsect = readw((void __iomem *) ioaddr->nsect_addr); | 186 | nsect = readw(ioaddr->nsect_addr); |
185 | lbal = readw((void __iomem *) ioaddr->lbal_addr); | 187 | lbal = readw(ioaddr->lbal_addr); |
186 | lbam = readw((void __iomem *) ioaddr->lbam_addr); | 188 | lbam = readw(ioaddr->lbam_addr); |
187 | lbah = readw((void __iomem *) ioaddr->lbah_addr); | 189 | lbah = readw(ioaddr->lbah_addr); |
188 | 190 | ||
189 | tf->feature = feature; | 191 | tf->feature = feature; |
190 | tf->nsect = nsect; | 192 | tf->nsect = nsect; |
@@ -216,7 +218,8 @@ static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance) | |||
216 | 218 | ||
217 | spin_lock(&host->lock); | 219 | spin_lock(&host->lock); |
218 | 220 | ||
219 | int_status = readl(host->mmio_base + VSC_SATA_INT_STAT_OFFSET); | 221 | int_status = readl(host->iomap[VSC_MMIO_BAR] + |
222 | VSC_SATA_INT_STAT_OFFSET); | ||
220 | 223 | ||
221 | for (i = 0; i < host->n_ports; i++) { | 224 | for (i = 0; i < host->n_ports; i++) { |
222 | if (int_status & ((u32) 0xFF << (8 * i))) { | 225 | if (int_status & ((u32) 0xFF << (8 * i))) { |
@@ -300,7 +303,7 @@ static const struct ata_port_operations vsc_sata_ops = { | |||
300 | .bmdma_status = ata_bmdma_status, | 303 | .bmdma_status = ata_bmdma_status, |
301 | .qc_prep = ata_qc_prep, | 304 | .qc_prep = ata_qc_prep, |
302 | .qc_issue = ata_qc_issue_prot, | 305 | .qc_issue = ata_qc_issue_prot, |
303 | .data_xfer = ata_mmio_data_xfer, | 306 | .data_xfer = ata_data_xfer, |
304 | .freeze = ata_bmdma_freeze, | 307 | .freeze = ata_bmdma_freeze, |
305 | .thaw = ata_bmdma_thaw, | 308 | .thaw = ata_bmdma_thaw, |
306 | .error_handler = ata_bmdma_error_handler, | 309 | .error_handler = ata_bmdma_error_handler, |
@@ -312,7 +315,8 @@ static const struct ata_port_operations vsc_sata_ops = { | |||
312 | .port_start = ata_port_start, | 315 | .port_start = ata_port_start, |
313 | }; | 316 | }; |
314 | 317 | ||
315 | static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base) | 318 | static void __devinit vsc_sata_setup_port(struct ata_ioports *port, |
319 | void __iomem *base) | ||
316 | { | 320 | { |
317 | port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET; | 321 | port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET; |
318 | port->data_addr = base + VSC_SATA_TF_DATA_OFFSET; | 322 | port->data_addr = base + VSC_SATA_TF_DATA_OFFSET; |
@@ -329,16 +333,15 @@ static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned lon | |||
329 | port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET; | 333 | port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET; |
330 | port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET; | 334 | port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET; |
331 | port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET; | 335 | port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET; |
332 | writel(0, (void __iomem *) base + VSC_SATA_UP_DESCRIPTOR_OFFSET); | 336 | writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET); |
333 | writel(0, (void __iomem *) base + VSC_SATA_UP_DATA_BUFFER_OFFSET); | 337 | writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET); |
334 | } | 338 | } |
335 | 339 | ||
336 | 340 | ||
337 | static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | 341 | static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
338 | { | 342 | { |
339 | static int printed_version; | 343 | static int printed_version; |
340 | struct ata_probe_ent *probe_ent = NULL; | 344 | struct ata_probe_ent *probe_ent; |
341 | unsigned long base; | ||
342 | void __iomem *mmio_base; | 345 | void __iomem *mmio_base; |
343 | int rc; | 346 | int rc; |
344 | 347 | ||
@@ -355,11 +358,11 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d | |||
355 | if (pci_resource_len(pdev, 0) == 0) | 358 | if (pci_resource_len(pdev, 0) == 0) |
356 | return -ENODEV; | 359 | return -ENODEV; |
357 | 360 | ||
358 | rc = pci_request_regions(pdev, DRV_NAME); | 361 | rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME); |
359 | if (rc) { | 362 | if (rc == -EBUSY) |
360 | pcim_pin_device(pdev); | 363 | pcim_pin_device(pdev); |
364 | if (rc) | ||
361 | return rc; | 365 | return rc; |
362 | } | ||
363 | 366 | ||
364 | /* | 367 | /* |
365 | * Use 32 bit DMA mask, because 64 bit address support is poor. | 368 | * Use 32 bit DMA mask, because 64 bit address support is poor. |
@@ -377,11 +380,6 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d | |||
377 | probe_ent->dev = pci_dev_to_dev(pdev); | 380 | probe_ent->dev = pci_dev_to_dev(pdev); |
378 | INIT_LIST_HEAD(&probe_ent->node); | 381 | INIT_LIST_HEAD(&probe_ent->node); |
379 | 382 | ||
380 | mmio_base = pcim_iomap(pdev, 0, 0); | ||
381 | if (mmio_base == NULL) | ||
382 | return -ENOMEM; | ||
383 | base = (unsigned long) mmio_base; | ||
384 | |||
385 | /* | 383 | /* |
386 | * Due to a bug in the chip, the default cache line size can't be used | 384 | * Due to a bug in the chip, the default cache line size can't be used |
387 | */ | 385 | */ |
@@ -398,7 +396,7 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d | |||
398 | probe_ent->port_ops = &vsc_sata_ops; | 396 | probe_ent->port_ops = &vsc_sata_ops; |
399 | probe_ent->n_ports = 4; | 397 | probe_ent->n_ports = 4; |
400 | probe_ent->irq = pdev->irq; | 398 | probe_ent->irq = pdev->irq; |
401 | probe_ent->mmio_base = mmio_base; | 399 | probe_ent->iomap = pcim_iomap_table(pdev); |
402 | 400 | ||
403 | /* We don't care much about the PIO/UDMA masks, but the core won't like us | 401 | /* We don't care much about the PIO/UDMA masks, but the core won't like us |
404 | * if we don't fill these | 402 | * if we don't fill these |
@@ -407,11 +405,13 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d | |||
407 | probe_ent->mwdma_mask = 0x07; | 405 | probe_ent->mwdma_mask = 0x07; |
408 | probe_ent->udma_mask = 0x7f; | 406 | probe_ent->udma_mask = 0x7f; |
409 | 407 | ||
408 | mmio_base = probe_ent->iomap[VSC_MMIO_BAR]; | ||
409 | |||
410 | /* We have 4 ports per PCI function */ | 410 | /* We have 4 ports per PCI function */ |
411 | vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET); | 411 | vsc_sata_setup_port(&probe_ent->port[0], mmio_base + 1 * VSC_SATA_PORT_OFFSET); |
412 | vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET); | 412 | vsc_sata_setup_port(&probe_ent->port[1], mmio_base + 2 * VSC_SATA_PORT_OFFSET); |
413 | vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET); | 413 | vsc_sata_setup_port(&probe_ent->port[2], mmio_base + 3 * VSC_SATA_PORT_OFFSET); |
414 | vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET); | 414 | vsc_sata_setup_port(&probe_ent->port[3], mmio_base + 4 * VSC_SATA_PORT_OFFSET); |
415 | 415 | ||
416 | pci_set_master(pdev); | 416 | pci_set_master(pdev); |
417 | 417 | ||