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-rw-r--r--drivers/input/touchscreen/hp680_ts_input.c2
-rw-r--r--drivers/serial/sh-sci.c113
-rw-r--r--drivers/serial/sh-sci.h83
3 files changed, 150 insertions, 48 deletions
diff --git a/drivers/input/touchscreen/hp680_ts_input.c b/drivers/input/touchscreen/hp680_ts_input.c
index 249087472740..61c15024c2a0 100644
--- a/drivers/input/touchscreen/hp680_ts_input.c
+++ b/drivers/input/touchscreen/hp680_ts_input.c
@@ -21,7 +21,7 @@
21static void do_softint(void *data); 21static void do_softint(void *data);
22 22
23static struct input_dev *hp680_ts_dev; 23static struct input_dev *hp680_ts_dev;
24static DECLARE_WORK(work, do_softint, 0); 24static DECLARE_WORK(work, do_softint);
25 25
26static void do_softint(void *data) 26static void do_softint(void *data)
27{ 27{
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index 46c40bbc4bc6..1f89496d530e 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -46,6 +46,7 @@
46#endif 46#endif
47 47
48#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64) 48#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
49#include <linux/ctype.h>
49#include <asm/clock.h> 50#include <asm/clock.h>
50#include <asm/sh_bios.h> 51#include <asm/sh_bios.h>
51#include <asm/kgdb.h> 52#include <asm/kgdb.h>
@@ -61,7 +62,7 @@ struct sci_port {
61 unsigned int type; 62 unsigned int type;
62 63
63 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */ 64 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
64 unsigned int irqs[SCIx_NR_IRQS]; 65 unsigned int irqs[SCIx_NR_IRQS];
65 66
66 /* Port pin configuration */ 67 /* Port pin configuration */
67 void (*init_pins)(struct uart_port *port, 68 void (*init_pins)(struct uart_port *port,
@@ -76,6 +77,11 @@ struct sci_port {
76 /* Break timer */ 77 /* Break timer */
77 struct timer_list break_timer; 78 struct timer_list break_timer;
78 int break_flag; 79 int break_flag;
80
81#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
82 /* Port clock */
83 struct clk *clk;
84#endif
79}; 85};
80 86
81#ifdef CONFIG_SH_KGDB 87#ifdef CONFIG_SH_KGDB
@@ -163,7 +169,7 @@ static void put_string(struct sci_port *sci_port, const char *buffer, int count)
163 usegdb |= sh_bios_in_gdb_mode(); 169 usegdb |= sh_bios_in_gdb_mode();
164#endif 170#endif
165#ifdef CONFIG_SH_KGDB 171#ifdef CONFIG_SH_KGDB
166 usegdb |= (kgdb_in_gdb_mode && (port == kgdb_sci_port)); 172 usegdb |= (kgdb_in_gdb_mode && (sci_port == kgdb_sci_port));
167#endif 173#endif
168 174
169 if (usegdb) { 175 if (usegdb) {
@@ -204,7 +210,7 @@ static int kgdb_sci_getchar(void)
204 int c; 210 int c;
205 211
206 /* Keep trying to read a character, this could be neater */ 212 /* Keep trying to read a character, this could be neater */
207 while ((c = get_char(kgdb_sci_port)) < 0) 213 while ((c = get_char(&kgdb_sci_port->port)) < 0)
208 cpu_relax(); 214 cpu_relax();
209 215
210 return c; 216 return c;
@@ -212,7 +218,7 @@ static int kgdb_sci_getchar(void)
212 218
213static inline void kgdb_sci_putchar(int c) 219static inline void kgdb_sci_putchar(int c)
214{ 220{
215 put_char(kgdb_sci_port, c); 221 put_char(&kgdb_sci_port->port, c);
216} 222}
217#endif /* CONFIG_SH_KGDB */ 223#endif /* CONFIG_SH_KGDB */
218 224
@@ -283,12 +289,23 @@ static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
283#endif 289#endif
284 290
285#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF) 291#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
286#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710) 292#if defined(CONFIG_CPU_SUBTYPE_SH7300)
287/* SH7300 doesn't use RTS/CTS */ 293/* SH7300 doesn't use RTS/CTS */
288static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 294static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
289{ 295{
290 sci_out(port, SCFCR, 0); 296 sci_out(port, SCFCR, 0);
291} 297}
298#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
299static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
300{
301 unsigned int fcr_val = 0;
302
303 set_sh771x_scif_pfc(port);
304 if (cflag & CRTSCTS) {
305 fcr_val |= SCFCR_MCE;
306 }
307 sci_out(port, SCFCR, fcr_val);
308}
292#elif defined(CONFIG_CPU_SH3) 309#elif defined(CONFIG_CPU_SH3)
293/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */ 310/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
294static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 311static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
@@ -350,7 +367,7 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
350 } else { 367 } else {
351#ifdef CONFIG_CPU_SUBTYPE_SH7343 368#ifdef CONFIG_CPU_SUBTYPE_SH7343
352 /* Nothing */ 369 /* Nothing */
353#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 370#elif defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
354 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */ 371 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
355#else 372#else
356 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */ 373 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
@@ -360,7 +377,9 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
360} 377}
361#endif 378#endif
362 379
363#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780) 380#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
381 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
382 defined(CONFIG_CPU_SUBTYPE_SH7785)
364static inline int scif_txroom(struct uart_port *port) 383static inline int scif_txroom(struct uart_port *port)
365{ 384{
366 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f); 385 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
@@ -735,12 +754,6 @@ static irqreturn_t sci_br_interrupt(int irq, void *ptr)
735 754
736 /* Handle BREAKs */ 755 /* Handle BREAKs */
737 sci_handle_breaks(port); 756 sci_handle_breaks(port);
738
739#ifdef CONFIG_SH_KGDB
740 /* Break into the debugger if a break is detected */
741 BREAKPOINT();
742#endif
743
744 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); 757 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
745 758
746 return IRQ_HANDLED; 759 return IRQ_HANDLED;
@@ -947,6 +960,10 @@ static int sci_startup(struct uart_port *port)
947 if (s->enable) 960 if (s->enable)
948 s->enable(port); 961 s->enable(port);
949 962
963#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
964 s->clk = clk_get(NULL, "module_clk");
965#endif
966
950 sci_request_irq(s); 967 sci_request_irq(s);
951 sci_start_tx(port); 968 sci_start_tx(port);
952 sci_start_rx(port, 1); 969 sci_start_rx(port, 1);
@@ -964,6 +981,11 @@ static void sci_shutdown(struct uart_port *port)
964 981
965 if (s->disable) 982 if (s->disable)
966 s->disable(port); 983 s->disable(port);
984
985#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
986 clk_put(s->clk);
987 s->clk = NULL;
988#endif
967} 989}
968 990
969static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 991static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
@@ -971,7 +993,6 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
971{ 993{
972 struct sci_port *s = &sci_ports[port->line]; 994 struct sci_port *s = &sci_ports[port->line];
973 unsigned int status, baud, smr_val; 995 unsigned int status, baud, smr_val;
974 unsigned long flags;
975 int t; 996 int t;
976 997
977 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 998 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
@@ -983,18 +1004,14 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
983 default: 1004 default:
984 { 1005 {
985#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64) 1006#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
986 struct clk *clk = clk_get(NULL, "module_clk"); 1007 t = SCBRR_VALUE(baud, clk_get_rate(s->clk));
987 t = SCBRR_VALUE(baud, clk_get_rate(clk));
988 clk_put(clk);
989#else 1008#else
990 t = SCBRR_VALUE(baud); 1009 t = SCBRR_VALUE(baud);
991#endif 1010#endif
992 }
993 break; 1011 break;
1012 }
994 } 1013 }
995 1014
996 spin_lock_irqsave(&port->lock, flags);
997
998 do { 1015 do {
999 status = sci_in(port, SCxSR); 1016 status = sci_in(port, SCxSR);
1000 } while (!(status & SCxSR_TEND(port))); 1017 } while (!(status & SCxSR_TEND(port)));
@@ -1038,8 +1055,6 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1038 1055
1039 if ((termios->c_cflag & CREAD) != 0) 1056 if ((termios->c_cflag & CREAD) != 0)
1040 sci_start_rx(port,0); 1057 sci_start_rx(port,0);
1041
1042 spin_unlock_irqrestore(&port->lock, flags);
1043} 1058}
1044 1059
1045static const char *sci_type(struct uart_port *port) 1060static const char *sci_type(struct uart_port *port)
@@ -1220,10 +1235,13 @@ static int __init serial_console_setup(struct console *co, char *options)
1220 if (!port->membase || !port->mapbase) 1235 if (!port->membase || !port->mapbase)
1221 return -ENODEV; 1236 return -ENODEV;
1222 1237
1223 spin_lock_init(&port->lock);
1224
1225 port->type = serial_console_port->type; 1238 port->type = serial_console_port->type;
1226 1239
1240#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1241 if (!serial_console_port->clk)
1242 serial_console_port->clk = clk_get(NULL, "module_clk");
1243#endif
1244
1227 if (port->flags & UPF_IOREMAP) 1245 if (port->flags & UPF_IOREMAP)
1228 sci_config_port(port, 0); 1246 sci_config_port(port, 0);
1229 1247
@@ -1247,7 +1265,7 @@ static struct console serial_console = {
1247 .device = uart_console_device, 1265 .device = uart_console_device,
1248 .write = serial_console_write, 1266 .write = serial_console_write,
1249 .setup = serial_console_setup, 1267 .setup = serial_console_setup,
1250 .flags = CON_PRINTBUFFER, 1268 .flags = CON_PRINTBUFFER,
1251 .index = -1, 1269 .index = -1,
1252 .data = &sci_uart_driver, 1270 .data = &sci_uart_driver,
1253}; 1271};
@@ -1292,11 +1310,23 @@ int __init kgdb_console_setup(struct console *co, char *options)
1292 int parity = 'n'; 1310 int parity = 'n';
1293 int flow = 'n'; 1311 int flow = 'n';
1294 1312
1295 spin_lock_init(&port->lock);
1296
1297 if (co->index != kgdb_portnum) 1313 if (co->index != kgdb_portnum)
1298 co->index = kgdb_portnum; 1314 co->index = kgdb_portnum;
1299 1315
1316 kgdb_sci_port = &sci_ports[co->index];
1317 port = &kgdb_sci_port->port;
1318
1319 /*
1320 * Also need to check port->type, we don't actually have any
1321 * UPIO_PORT ports, but uart_report_port() handily misreports
1322 * it anyways if we don't have a port available by the time this is
1323 * called.
1324 */
1325 if (!port->type)
1326 return -ENODEV;
1327 if (!port->membase || !port->mapbase)
1328 return -ENODEV;
1329
1300 if (options) 1330 if (options)
1301 uart_parse_options(options, &baud, &parity, &bits, &flow); 1331 uart_parse_options(options, &baud, &parity, &bits, &flow);
1302 else 1332 else
@@ -1311,11 +1341,12 @@ int __init kgdb_console_setup(struct console *co, char *options)
1311 1341
1312#ifdef CONFIG_SH_KGDB_CONSOLE 1342#ifdef CONFIG_SH_KGDB_CONSOLE
1313static struct console kgdb_console = { 1343static struct console kgdb_console = {
1314 .name = "ttySC", 1344 .name = "ttySC",
1315 .write = kgdb_console_write, 1345 .device = uart_console_device,
1316 .setup = kgdb_console_setup, 1346 .write = kgdb_console_write,
1317 .flags = CON_PRINTBUFFER | CON_ENABLED, 1347 .setup = kgdb_console_setup,
1318 .index = -1, 1348 .flags = CON_PRINTBUFFER,
1349 .index = -1,
1319 .data = &sci_uart_driver, 1350 .data = &sci_uart_driver,
1320}; 1351};
1321 1352
@@ -1361,9 +1392,19 @@ static int __devinit sci_probe(struct platform_device *dev)
1361 struct plat_sci_port *p = dev->dev.platform_data; 1392 struct plat_sci_port *p = dev->dev.platform_data;
1362 int i; 1393 int i;
1363 1394
1364 for (i = 0; p && p->flags != 0 && i < SCI_NPORTS; p++, i++) { 1395 for (i = 0; p && p->flags != 0; p++, i++) {
1365 struct sci_port *sciport = &sci_ports[i]; 1396 struct sci_port *sciport = &sci_ports[i];
1366 1397
1398 /* Sanity check */
1399 if (unlikely(i == SCI_NPORTS)) {
1400 dev_notice(&dev->dev, "Attempting to register port "
1401 "%d when only %d are available.\n",
1402 i+1, SCI_NPORTS);
1403 dev_notice(&dev->dev, "Consider bumping "
1404 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1405 break;
1406 }
1407
1367 sciport->port.mapbase = p->mapbase; 1408 sciport->port.mapbase = p->mapbase;
1368 1409
1369 /* 1410 /*
@@ -1386,6 +1427,12 @@ static int __devinit sci_probe(struct platform_device *dev)
1386 uart_add_one_port(&sci_uart_driver, &sciport->port); 1427 uart_add_one_port(&sci_uart_driver, &sciport->port);
1387 } 1428 }
1388 1429
1430#if defined(CONFIG_SH_KGDB) && !defined(CONFIG_SH_KGDB_CONSOLE)
1431 kgdb_sci_port = &sci_ports[kgdb_portnum];
1432 kgdb_getchar = kgdb_sci_getchar;
1433 kgdb_putchar = kgdb_sci_putchar;
1434#endif
1435
1389#ifdef CONFIG_CPU_FREQ 1436#ifdef CONFIG_CPU_FREQ
1390 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER); 1437 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1391 dev_info(&dev->dev, "sci: CPU frequency notifier registered\n"); 1438 dev_info(&dev->dev, "sci: CPU frequency notifier registered\n");
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 77f7d6351ab1..fb04fb5f9843 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -73,9 +73,13 @@
73# define SCPDR 0xA4050136 /* 16 bit SCIF */ 73# define SCPDR 0xA4050136 /* 16 bit SCIF */
74# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 74# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
75# define SCIF_ONLY 75# define SCIF_ONLY
76#elif defined(CONFIG_CPU_SUBTYPE_SH7710) 76#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
77# define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 77# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
78# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 78# define SCI_NPORTS 2
79# define SCIF_ORER 0x0001 /* overrun error bit */
80# define PACR 0xa4050100
81# define PBCR 0xa4050102
82# define SCSCR_INIT(port) 0x3B
79# define SCIF_ONLY 83# define SCIF_ONLY
80#elif defined(CONFIG_CPU_SUBTYPE_SH73180) 84#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
81# define SCPDR 0xA4050138 /* 16 bit SCIF */ 85# define SCPDR 0xA4050138 /* 16 bit SCIF */
@@ -140,6 +144,16 @@
140# define SCIF_ORER 0x0001 /* Overrun error bit */ 144# define SCIF_ORER 0x0001 /* Overrun error bit */
141# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 145# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
142# define SCIF_ONLY 146# define SCIF_ONLY
147#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
148# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
149# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
150# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
151# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
152# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
153# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
154# define SCIF_OPER 0x0001 /* Overrun error bit */
155# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
156# define SCIF_ONLY
143#elif defined(CONFIG_CPU_SUBTYPE_SH7206) 157#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
144# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ 158# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
145# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ 159# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
@@ -163,7 +177,10 @@
163#define SCI_CTRL_FLAGS_RIE 0x40 /* all */ 177#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
164#define SCI_CTRL_FLAGS_TE 0x20 /* all */ 178#define SCI_CTRL_FLAGS_TE 0x20 /* all */
165#define SCI_CTRL_FLAGS_RE 0x10 /* all */ 179#define SCI_CTRL_FLAGS_RE 0x10 /* all */
166#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7780) 180#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
181 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
182 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
183 defined(CONFIG_CPU_SUBTYPE_SH7785)
167#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ 184#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
168#else 185#else
169#define SCI_CTRL_FLAGS_REIE 0 186#define SCI_CTRL_FLAGS_REIE 0
@@ -333,9 +350,15 @@
333 } 350 }
334 351
335#ifdef CONFIG_CPU_SH3 352#ifdef CONFIG_CPU_SH3
336#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \ 353#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
337 defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 354#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
338 defined(CONFIG_CPU_SUBTYPE_SH7710) 355 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
356 h8_sci_offset, h8_sci_size) \
357 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
358#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
359 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
360#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
361 defined(CONFIG_CPU_SUBTYPE_SH7705)
339#define SCIF_FNS(name, scif_offset, scif_size) \ 362#define SCIF_FNS(name, scif_offset, scif_size) \
340 CPU_SCIF_FNS(name, scif_offset, scif_size) 363 CPU_SCIF_FNS(name, scif_offset, scif_size)
341#else 364#else
@@ -362,8 +385,8 @@
362#endif 385#endif
363 386
364#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \ 387#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
365 defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 388 defined(CONFIG_CPU_SUBTYPE_SH7705)
366 defined(CONFIG_CPU_SUBTYPE_SH7710) 389
367SCIF_FNS(SCSMR, 0x00, 16) 390SCIF_FNS(SCSMR, 0x00, 16)
368SCIF_FNS(SCBRR, 0x04, 8) 391SCIF_FNS(SCBRR, 0x04, 8)
369SCIF_FNS(SCSCR, 0x08, 16) 392SCIF_FNS(SCSCR, 0x08, 16)
@@ -385,7 +408,9 @@ SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
385SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) 408SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
386SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) 409SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
387SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) 410SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
388#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780) 411#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
412 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
413 defined(CONFIG_CPU_SUBTYPE_SH7785)
389SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 414SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
390SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 415SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
391SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 416SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
@@ -471,13 +496,24 @@ static inline int sci_rxd_in(struct uart_port *port)
471 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ 496 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
472 return 1; 497 return 1;
473} 498}
474#elif defined(CONFIG_CPU_SUBTYPE_SH7710) 499#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
475static inline int sci_rxd_in(struct uart_port *port) 500static inline int sci_rxd_in(struct uart_port *port)
476{ 501{
477 if (port->mapbase == SCSPTR0) 502 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
478 return ctrl_inw(SCSPTR0 + 0x10) & 0x01 ? 1 : 0; 503}
479 return 1; 504static inline void set_sh771x_scif_pfc(struct uart_port *port)
505{
506 if (port->mapbase == 0xA4400000){
507 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
508 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
509 return;
510 }
511 if (port->mapbase == 0xA4410000){
512 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
513 return;
514 }
480} 515}
516
481#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 517#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
482 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 518 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
483 defined(CONFIG_CPU_SUBTYPE_SH4_202) 519 defined(CONFIG_CPU_SUBTYPE_SH4_202)
@@ -576,6 +612,23 @@ static inline int sci_rxd_in(struct uart_port *port)
576 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 612 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
577 return 1; 613 return 1;
578} 614}
615#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
616static inline int sci_rxd_in(struct uart_port *port)
617{
618 if (port->mapbase == 0xffea0000)
619 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
620 if (port->mapbase == 0xffeb0000)
621 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
622 if (port->mapbase == 0xffec0000)
623 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
624 if (port->mapbase == 0xffed0000)
625 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
626 if (port->mapbase == 0xffee0000)
627 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
628 if (port->mapbase == 0xffef0000)
629 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
630 return 1;
631}
579#elif defined(CONFIG_CPU_SUBTYPE_SH7206) 632#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
580static inline int sci_rxd_in(struct uart_port *port) 633static inline int sci_rxd_in(struct uart_port *port)
581{ 634{
@@ -634,7 +687,9 @@ static inline int sci_rxd_in(struct uart_port *port)
634 * -- Mitch Davis - 15 Jul 2000 687 * -- Mitch Davis - 15 Jul 2000
635 */ 688 */
636 689
637#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7780) 690#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
691 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
692 defined(CONFIG_CPU_SUBTYPE_SH7785)
638#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) 693#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
639#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 694#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
640#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 695#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)