4 files changed, 90 insertions, 43 deletions

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index c27f80e5d531..9d8ca990dde6 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -128,7 +128,7 @@ config TXX9_DMAC
 
 config SH_DMAE
         tristate "Renesas SuperH DMAC support"
-        depends on SUPERH && SH_DMA
+        depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE)
         depends on !SH_DMA_API
         select DMA_ENGINE
         help
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index 323afef77802..c2b0172a7589 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -811,7 +811,7 @@ static irqreturn_t sh_dmae_interrupt(int irq, void *data)
         return ret;
 }
 
-#if defined(CONFIG_CPU_SH4)
+#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 static irqreturn_t sh_dmae_err(int irq, void *data)
 {
         struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
@@ -1052,7 +1052,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
         /* Default transfer size of 32 bytes requires 32-byte alignment */
         shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
 
-#if defined(CONFIG_CPU_SH4)
+#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 
         if (!chanirq_res)
@@ -1077,7 +1077,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
 
 #else
         chanirq_res = errirq_res;
-#endif /* CONFIG_CPU_SH4 */
+#endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
 
         if (chanirq_res->start == chanirq_res->end &&
             !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
@@ -1124,7 +1124,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
 chan_probe_err:
         sh_dmae_chan_remove(shdev);
 eirqres:
-#if defined(CONFIG_CPU_SH4)
+#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
         free_irq(errirq, shdev);
 eirq_err:
 #endif
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 87ab0568bb0e..dec387d3f04d 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -529,7 +529,7 @@ config I2C_SH7760
 
 config I2C_SH_MOBILE
         tristate "SuperH Mobile I2C Controller"
-        depends on SUPERH
+        depends on SUPERH || ARCH_SHMOBILE
         help
           If you say yes to this option, support will be included for the
           built-in I2C interface on the Renesas SH-Mobile processor.
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index ffb405d7c6f2..598c49acaeb5 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -119,8 +119,10 @@ struct sh_mobile_i2c_data {
         struct i2c_adapter adap;
 
         struct clk *clk;
+        u_int8_t icic;
         u_int8_t iccl;
         u_int8_t icch;
+        u_int8_t flags;
 
         spinlock_t lock;
         wait_queue_head_t wait;
@@ -129,15 +131,17 @@ struct sh_mobile_i2c_data {
         int sr;
 };
 
+#define IIC_FLAG_HAS_ICIC67     (1 << 0)
+
 #define NORMAL_SPEED            100000 /* FAST_SPEED 400000 */
 
 /* Register offsets */
-#define ICDR(pd)                (pd->reg + 0x00)
-#define ICCR(pd)                (pd->reg + 0x04)
-#define ICSR(pd)                (pd->reg + 0x08)
-#define ICIC(pd)                (pd->reg + 0x0c)
-#define ICCL(pd)                (pd->reg + 0x10)
-#define ICCH(pd)                (pd->reg + 0x14)
+#define ICDR                    0x00
+#define ICCR                    0x04
+#define ICSR                    0x08
+#define ICIC                    0x0c
+#define ICCL                    0x10
+#define ICCH                    0x14
 
 /* Register bits */
 #define ICCR_ICE                0x80
@@ -155,11 +159,32 @@ struct sh_mobile_i2c_data {
 #define ICSR_WAIT               0x02
 #define ICSR_DTE                0x01
 
+#define ICIC_ICCLB8             0x80
+#define ICIC_ICCHB8             0x40
 #define ICIC_ALE                0x08
 #define ICIC_TACKE              0x04
 #define ICIC_WAITE              0x02
 #define ICIC_DTEE               0x01
 
+static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
+{
+        if (offs == ICIC)
+                data |= pd->icic;
+
+        iowrite8(data, pd->reg + offs);
+}
+
+static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
+{
+        return ioread8(pd->reg + offs);
+}
+
+static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
+                        unsigned char set, unsigned char clr)
+{
+        iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
+}
+
 static void activate_ch(struct sh_mobile_i2c_data *pd)
 {
         unsigned long i2c_clk;
@@ -187,6 +212,14 @@ static void activate_ch(struct sh_mobile_i2c_data *pd)
         else
                 pd->iccl = (u_int8_t)(num/denom);
 
+        /* one more bit of ICCL in ICIC */
+        if (pd->flags & IIC_FLAG_HAS_ICIC67) {
+                if ((num/denom) > 0xff)
+                        pd->icic |= ICIC_ICCLB8;
+                else
+                        pd->icic &= ~ICIC_ICCLB8;
+        }
+
         /* Calculate the value for icch. From the data sheet:
            icch = (p clock / transfer rate) * (H / (L + H)) */
         num = i2c_clk * 4;
@@ -196,25 +229,33 @@ static void activate_ch(struct sh_mobile_i2c_data *pd)
         else
                 pd->icch = (u_int8_t)(num/denom);
 
+        /* one more bit of ICCH in ICIC */
+        if (pd->flags & IIC_FLAG_HAS_ICIC67) {
+                if ((num/denom) > 0xff)
+                        pd->icic |= ICIC_ICCHB8;
+                else
+                        pd->icic &= ~ICIC_ICCHB8;
+        }
+
         /* Enable channel and configure rx ack */
-        iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));
+        iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 
         /* Mask all interrupts */
-        iowrite8(0, ICIC(pd));
+        iic_wr(pd, ICIC, 0);
 
         /* Set the clock */
-        iowrite8(pd->iccl, ICCL(pd));
-        iowrite8(pd->icch, ICCH(pd));
+        iic_wr(pd, ICCL, pd->iccl);
+        iic_wr(pd, ICCH, pd->icch);
 }
 
 static void deactivate_ch(struct sh_mobile_i2c_data *pd)
 {
         /* Clear/disable interrupts */
-        iowrite8(0, ICSR(pd));
-        iowrite8(0, ICIC(pd));
+        iic_wr(pd, ICSR, 0);
+        iic_wr(pd, ICIC, 0);
 
         /* Disable channel */
-        iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
+        iic_set_clr(pd, ICCR, 0, ICCR_ICE);
 
         /* Disable clock and mark device as idle */
         clk_disable(pd->clk);
@@ -233,35 +274,35 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
 
         switch (op) {
         case OP_START: /* issue start and trigger DTE interrupt */
-                iowrite8(0x94, ICCR(pd));
+                iic_wr(pd, ICCR, 0x94);
                 break;
         case OP_TX_FIRST: /* disable DTE interrupt and write data */
-                iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE, ICIC(pd));
-                iowrite8(data, ICDR(pd));
+                iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
+                iic_wr(pd, ICDR, data);
                 break;
         case OP_TX: /* write data */
-                iowrite8(data, ICDR(pd));
+                iic_wr(pd, ICDR, data);
                 break;
         case OP_TX_STOP: /* write data and issue a stop afterwards */
-                iowrite8(data, ICDR(pd));
-                iowrite8(0x90, ICCR(pd));
+                iic_wr(pd, ICDR, data);
+                iic_wr(pd, ICCR, 0x90);
                 break;
         case OP_TX_TO_RX: /* select read mode */
-                iowrite8(0x81, ICCR(pd));
+                iic_wr(pd, ICCR, 0x81);
                 break;
         case OP_RX: /* just read data */
-                ret = ioread8(ICDR(pd));
+                ret = iic_rd(pd, ICDR);
                 break;
         case OP_RX_STOP: /* enable DTE interrupt, issue stop */
-                iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
-                         ICIC(pd));
-                iowrite8(0xc0, ICCR(pd));
+                iic_wr(pd, ICIC,
+                       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
+                iic_wr(pd, ICCR, 0xc0);
                 break;
         case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
-                iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
-                         ICIC(pd));
-                ret = ioread8(ICDR(pd));
-                iowrite8(0xc0, ICCR(pd));
+                iic_wr(pd, ICIC,
+                       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
+                ret = iic_rd(pd, ICDR);
+                iic_wr(pd, ICCR, 0xc0);
                 break;
         }
 
@@ -367,7 +408,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
         unsigned char sr;
         int wakeup;
 
-        sr = ioread8(ICSR(pd));
+        sr = iic_rd(pd, ICSR);
         pd->sr |= sr; /* remember state */
 
         dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
@@ -376,7 +417,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
 
         if (sr & (ICSR_AL | ICSR_TACK)) {
                 /* don't interrupt transaction - continue to issue stop */
-                iowrite8(sr & ~(ICSR_AL | ICSR_TACK), ICSR(pd));
+                iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
                 wakeup = 0;
         } else if (pd->msg->flags & I2C_M_RD)
                 wakeup = sh_mobile_i2c_isr_rx(pd);
@@ -384,7 +425,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
                 wakeup = sh_mobile_i2c_isr_tx(pd);
 
         if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
-                iowrite8(sr & ~ICSR_WAIT, ICSR(pd));
+                iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
 
         if (wakeup) {
                 pd->sr |= SW_DONE;
@@ -402,21 +443,21 @@ static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
         }
 
         /* Initialize channel registers */
-        iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
+        iic_set_clr(pd, ICCR, 0, ICCR_ICE);
 
         /* Enable channel and configure rx ack */
-        iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));
+        iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 
         /* Set the clock */
-        iowrite8(pd->iccl, ICCL(pd));
-        iowrite8(pd->icch, ICCH(pd));
+        iic_wr(pd, ICCL, pd->iccl);
+        iic_wr(pd, ICCH, pd->icch);
 
         pd->msg = usr_msg;
         pd->pos = -1;
         pd->sr = 0;
 
         /* Enable all interrupts to begin with */
-        iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE | ICIC_DTEE, ICIC(pd));
+        iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
         return 0;
 }
 
@@ -451,7 +492,7 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
 
                 retry_count = 1000;
 again:
-                val = ioread8(ICSR(pd));
+                val = iic_rd(pd, ICSR);
 
                 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
 
@@ -576,6 +617,12 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
                 goto err_irq;
         }
 
+        /* The IIC blocks on SH-Mobile ARM processors
+         * come with two new bits in ICIC.
+         */
+        if (size > 0x17)
+                pd->flags |= IIC_FLAG_HAS_ICIC67;
+
         /* Enable Runtime PM for this device.
          *
          * Also tell the Runtime PM core to ignore children