diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/mfd/twl-core.c | 190 |
1 files changed, 163 insertions, 27 deletions
diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c index 29473c2c95ae..6ef7685a4cf8 100644 --- a/drivers/mfd/twl-core.c +++ b/drivers/mfd/twl-core.c | |||
@@ -47,6 +47,9 @@ | |||
47 | #include <linux/i2c.h> | 47 | #include <linux/i2c.h> |
48 | #include <linux/i2c/twl.h> | 48 | #include <linux/i2c/twl.h> |
49 | 49 | ||
50 | /* Register descriptions for audio */ | ||
51 | #include <linux/mfd/twl4030-audio.h> | ||
52 | |||
50 | #include "twl-core.h" | 53 | #include "twl-core.h" |
51 | 54 | ||
52 | /* | 55 | /* |
@@ -200,6 +203,105 @@ static struct twl_mapping twl4030_map[] = { | |||
200 | { 2, TWL5031_BASEADD_INTERRUPTS }, | 203 | { 2, TWL5031_BASEADD_INTERRUPTS }, |
201 | }; | 204 | }; |
202 | 205 | ||
206 | static struct reg_default twl4030_49_defaults[] = { | ||
207 | /* Audio Registers */ | ||
208 | { 0x01, 0x00}, /* CODEC_MODE */ | ||
209 | { 0x02, 0x00}, /* OPTION */ | ||
210 | /* 0x03 Unused */ | ||
211 | { 0x04, 0x00}, /* MICBIAS_CTL */ | ||
212 | { 0x05, 0x00}, /* ANAMICL */ | ||
213 | { 0x06, 0x00}, /* ANAMICR */ | ||
214 | { 0x07, 0x00}, /* AVADC_CTL */ | ||
215 | { 0x08, 0x00}, /* ADCMICSEL */ | ||
216 | { 0x09, 0x00}, /* DIGMIXING */ | ||
217 | { 0x0a, 0x0f}, /* ATXL1PGA */ | ||
218 | { 0x0b, 0x0f}, /* ATXR1PGA */ | ||
219 | { 0x0c, 0x0f}, /* AVTXL2PGA */ | ||
220 | { 0x0d, 0x0f}, /* AVTXR2PGA */ | ||
221 | { 0x0e, 0x00}, /* AUDIO_IF */ | ||
222 | { 0x0f, 0x00}, /* VOICE_IF */ | ||
223 | { 0x10, 0x3f}, /* ARXR1PGA */ | ||
224 | { 0x11, 0x3f}, /* ARXL1PGA */ | ||
225 | { 0x12, 0x3f}, /* ARXR2PGA */ | ||
226 | { 0x13, 0x3f}, /* ARXL2PGA */ | ||
227 | { 0x14, 0x25}, /* VRXPGA */ | ||
228 | { 0x15, 0x00}, /* VSTPGA */ | ||
229 | { 0x16, 0x00}, /* VRX2ARXPGA */ | ||
230 | { 0x17, 0x00}, /* AVDAC_CTL */ | ||
231 | { 0x18, 0x00}, /* ARX2VTXPGA */ | ||
232 | { 0x19, 0x32}, /* ARXL1_APGA_CTL*/ | ||
233 | { 0x1a, 0x32}, /* ARXR1_APGA_CTL*/ | ||
234 | { 0x1b, 0x32}, /* ARXL2_APGA_CTL*/ | ||
235 | { 0x1c, 0x32}, /* ARXR2_APGA_CTL*/ | ||
236 | { 0x1d, 0x00}, /* ATX2ARXPGA */ | ||
237 | { 0x1e, 0x00}, /* BT_IF */ | ||
238 | { 0x1f, 0x55}, /* BTPGA */ | ||
239 | { 0x20, 0x00}, /* BTSTPGA */ | ||
240 | { 0x21, 0x00}, /* EAR_CTL */ | ||
241 | { 0x22, 0x00}, /* HS_SEL */ | ||
242 | { 0x23, 0x00}, /* HS_GAIN_SET */ | ||
243 | { 0x24, 0x00}, /* HS_POPN_SET */ | ||
244 | { 0x25, 0x00}, /* PREDL_CTL */ | ||
245 | { 0x26, 0x00}, /* PREDR_CTL */ | ||
246 | { 0x27, 0x00}, /* PRECKL_CTL */ | ||
247 | { 0x28, 0x00}, /* PRECKR_CTL */ | ||
248 | { 0x29, 0x00}, /* HFL_CTL */ | ||
249 | { 0x2a, 0x00}, /* HFR_CTL */ | ||
250 | { 0x2b, 0x05}, /* ALC_CTL */ | ||
251 | { 0x2c, 0x00}, /* ALC_SET1 */ | ||
252 | { 0x2d, 0x00}, /* ALC_SET2 */ | ||
253 | { 0x2e, 0x00}, /* BOOST_CTL */ | ||
254 | { 0x2f, 0x00}, /* SOFTVOL_CTL */ | ||
255 | { 0x30, 0x13}, /* DTMF_FREQSEL */ | ||
256 | { 0x31, 0x00}, /* DTMF_TONEXT1H */ | ||
257 | { 0x32, 0x00}, /* DTMF_TONEXT1L */ | ||
258 | { 0x33, 0x00}, /* DTMF_TONEXT2H */ | ||
259 | { 0x34, 0x00}, /* DTMF_TONEXT2L */ | ||
260 | { 0x35, 0x79}, /* DTMF_TONOFF */ | ||
261 | { 0x36, 0x11}, /* DTMF_WANONOFF */ | ||
262 | { 0x37, 0x00}, /* I2S_RX_SCRAMBLE_H */ | ||
263 | { 0x38, 0x00}, /* I2S_RX_SCRAMBLE_M */ | ||
264 | { 0x39, 0x00}, /* I2S_RX_SCRAMBLE_L */ | ||
265 | { 0x3a, 0x06}, /* APLL_CTL */ | ||
266 | { 0x3b, 0x00}, /* DTMF_CTL */ | ||
267 | { 0x3c, 0x44}, /* DTMF_PGA_CTL2 (0x3C) */ | ||
268 | { 0x3d, 0x69}, /* DTMF_PGA_CTL1 (0x3D) */ | ||
269 | { 0x3e, 0x00}, /* MISC_SET_1 */ | ||
270 | { 0x3f, 0x00}, /* PCMBTMUX */ | ||
271 | /* 0x40 - 0x42 Unused */ | ||
272 | { 0x43, 0x00}, /* RX_PATH_SEL */ | ||
273 | { 0x44, 0x32}, /* VDL_APGA_CTL */ | ||
274 | { 0x45, 0x00}, /* VIBRA_CTL */ | ||
275 | { 0x46, 0x00}, /* VIBRA_SET */ | ||
276 | { 0x47, 0x00}, /* VIBRA_PWM_SET */ | ||
277 | { 0x48, 0x00}, /* ANAMIC_GAIN */ | ||
278 | { 0x49, 0x00}, /* MISC_SET_2 */ | ||
279 | /* End of Audio Registers */ | ||
280 | }; | ||
281 | |||
282 | static bool twl4030_49_nop_reg(struct device *dev, unsigned int reg) | ||
283 | { | ||
284 | switch (reg) { | ||
285 | case 0: | ||
286 | case 3: | ||
287 | case 40: | ||
288 | case 41: | ||
289 | case 42: | ||
290 | return false; | ||
291 | default: | ||
292 | return true; | ||
293 | } | ||
294 | } | ||
295 | |||
296 | static const struct regmap_range twl4030_49_volatile_ranges[] = { | ||
297 | regmap_reg_range(TWL4030_BASEADD_TEST, 0xff), | ||
298 | }; | ||
299 | |||
300 | static const struct regmap_access_table twl4030_49_volatile_table = { | ||
301 | .yes_ranges = twl4030_49_volatile_ranges, | ||
302 | .n_yes_ranges = ARRAY_SIZE(twl4030_49_volatile_ranges), | ||
303 | }; | ||
304 | |||
203 | static struct regmap_config twl4030_regmap_config[4] = { | 305 | static struct regmap_config twl4030_regmap_config[4] = { |
204 | { | 306 | { |
205 | /* Address 0x48 */ | 307 | /* Address 0x48 */ |
@@ -212,6 +314,15 @@ static struct regmap_config twl4030_regmap_config[4] = { | |||
212 | .reg_bits = 8, | 314 | .reg_bits = 8, |
213 | .val_bits = 8, | 315 | .val_bits = 8, |
214 | .max_register = 0xff, | 316 | .max_register = 0xff, |
317 | |||
318 | .readable_reg = twl4030_49_nop_reg, | ||
319 | .writeable_reg = twl4030_49_nop_reg, | ||
320 | |||
321 | .volatile_table = &twl4030_49_volatile_table, | ||
322 | |||
323 | .reg_defaults = twl4030_49_defaults, | ||
324 | .num_reg_defaults = ARRAY_SIZE(twl4030_49_defaults), | ||
325 | .cache_type = REGCACHE_RBTREE, | ||
215 | }, | 326 | }, |
216 | { | 327 | { |
217 | /* Address 0x4a */ | 328 | /* Address 0x4a */ |
@@ -302,35 +413,50 @@ unsigned int twl_rev(void) | |||
302 | EXPORT_SYMBOL(twl_rev); | 413 | EXPORT_SYMBOL(twl_rev); |
303 | 414 | ||
304 | /** | 415 | /** |
305 | * twl_i2c_write - Writes a n bit register in TWL4030/TWL5030/TWL60X0 | 416 | * twl_get_regmap - Get the regmap associated with the given module |
306 | * @mod_no: module number | 417 | * @mod_no: module number |
307 | * @value: an array of num_bytes+1 containing data to write | ||
308 | * @reg: register address (just offset will do) | ||
309 | * @num_bytes: number of bytes to transfer | ||
310 | * | 418 | * |
311 | * Returns the result of operation - 0 is success | 419 | * Returns the regmap pointer or NULL in case of failure. |
312 | */ | 420 | */ |
313 | int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes) | 421 | static struct regmap *twl_get_regmap(u8 mod_no) |
314 | { | 422 | { |
315 | int ret; | ||
316 | int sid; | 423 | int sid; |
317 | struct twl_client *twl; | 424 | struct twl_client *twl; |
318 | 425 | ||
319 | if (unlikely(!twl_priv || !twl_priv->ready)) { | 426 | if (unlikely(!twl_priv || !twl_priv->ready)) { |
320 | pr_err("%s: not initialized\n", DRIVER_NAME); | 427 | pr_err("%s: not initialized\n", DRIVER_NAME); |
321 | return -EPERM; | 428 | return NULL; |
322 | } | 429 | } |
323 | if (unlikely(mod_no >= twl_get_last_module())) { | 430 | if (unlikely(mod_no >= twl_get_last_module())) { |
324 | pr_err("%s: invalid module number %d\n", DRIVER_NAME, mod_no); | 431 | pr_err("%s: invalid module number %d\n", DRIVER_NAME, mod_no); |
325 | return -EPERM; | 432 | return NULL; |
326 | } | 433 | } |
327 | 434 | ||
328 | sid = twl_priv->twl_map[mod_no].sid; | 435 | sid = twl_priv->twl_map[mod_no].sid; |
329 | twl = &twl_priv->twl_modules[sid]; | 436 | twl = &twl_priv->twl_modules[sid]; |
330 | 437 | ||
331 | ret = regmap_bulk_write(twl->regmap, | 438 | return twl->regmap; |
332 | twl_priv->twl_map[mod_no].base + reg, value, | 439 | } |
333 | num_bytes); | 440 | |
441 | /** | ||
442 | * twl_i2c_write - Writes a n bit register in TWL4030/TWL5030/TWL60X0 | ||
443 | * @mod_no: module number | ||
444 | * @value: an array of num_bytes+1 containing data to write | ||
445 | * @reg: register address (just offset will do) | ||
446 | * @num_bytes: number of bytes to transfer | ||
447 | * | ||
448 | * Returns the result of operation - 0 is success | ||
449 | */ | ||
450 | int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes) | ||
451 | { | ||
452 | struct regmap *regmap = twl_get_regmap(mod_no); | ||
453 | int ret; | ||
454 | |||
455 | if (!regmap) | ||
456 | return -EPERM; | ||
457 | |||
458 | ret = regmap_bulk_write(regmap, twl_priv->twl_map[mod_no].base + reg, | ||
459 | value, num_bytes); | ||
334 | 460 | ||
335 | if (ret) | 461 | if (ret) |
336 | pr_err("%s: Write failed (mod %d, reg 0x%02x count %d)\n", | 462 | pr_err("%s: Write failed (mod %d, reg 0x%02x count %d)\n", |
@@ -351,25 +477,14 @@ EXPORT_SYMBOL(twl_i2c_write); | |||
351 | */ | 477 | */ |
352 | int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes) | 478 | int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes) |
353 | { | 479 | { |
480 | struct regmap *regmap = twl_get_regmap(mod_no); | ||
354 | int ret; | 481 | int ret; |
355 | int sid; | ||
356 | struct twl_client *twl; | ||
357 | 482 | ||
358 | if (unlikely(!twl_priv || !twl_priv->ready)) { | 483 | if (!regmap) |
359 | pr_err("%s: not initialized\n", DRIVER_NAME); | ||
360 | return -EPERM; | ||
361 | } | ||
362 | if (unlikely(mod_no >= twl_get_last_module())) { | ||
363 | pr_err("%s: invalid module number %d\n", DRIVER_NAME, mod_no); | ||
364 | return -EPERM; | 484 | return -EPERM; |
365 | } | ||
366 | |||
367 | sid = twl_priv->twl_map[mod_no].sid; | ||
368 | twl = &twl_priv->twl_modules[sid]; | ||
369 | 485 | ||
370 | ret = regmap_bulk_read(twl->regmap, | 486 | ret = regmap_bulk_read(regmap, twl_priv->twl_map[mod_no].base + reg, |
371 | twl_priv->twl_map[mod_no].base + reg, value, | 487 | value, num_bytes); |
372 | num_bytes); | ||
373 | 488 | ||
374 | if (ret) | 489 | if (ret) |
375 | pr_err("%s: Read failed (mod %d, reg 0x%02x count %d)\n", | 490 | pr_err("%s: Read failed (mod %d, reg 0x%02x count %d)\n", |
@@ -379,6 +494,27 @@ int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes) | |||
379 | } | 494 | } |
380 | EXPORT_SYMBOL(twl_i2c_read); | 495 | EXPORT_SYMBOL(twl_i2c_read); |
381 | 496 | ||
497 | /** | ||
498 | * twl_regcache_bypass - Configure the regcache bypass for the regmap associated | ||
499 | * with the module | ||
500 | * @mod_no: module number | ||
501 | * @enable: Regcache bypass state | ||
502 | * | ||
503 | * Returns 0 else failure. | ||
504 | */ | ||
505 | int twl_set_regcache_bypass(u8 mod_no, bool enable) | ||
506 | { | ||
507 | struct regmap *regmap = twl_get_regmap(mod_no); | ||
508 | |||
509 | if (!regmap) | ||
510 | return -EPERM; | ||
511 | |||
512 | regcache_cache_bypass(regmap, enable); | ||
513 | |||
514 | return 0; | ||
515 | } | ||
516 | EXPORT_SYMBOL(twl_set_regcache_bypass); | ||
517 | |||
382 | /*----------------------------------------------------------------------*/ | 518 | /*----------------------------------------------------------------------*/ |
383 | 519 | ||
384 | /** | 520 | /** |