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-rw-r--r--drivers/Kconfig2
-rw-r--r--drivers/Makefile3
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/samsung/Makefile8
-rw-r--r--drivers/clk/samsung/clk-exynos4.c1091
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c523
-rw-r--r--drivers/clk/samsung/clk-exynos5440.c139
-rw-r--r--drivers/clk/samsung/clk-pll.c419
-rw-r--r--drivers/clk/samsung/clk-pll.h41
-rw-r--r--drivers/clk/samsung/clk.c320
-rw-r--r--drivers/clk/samsung/clk.h289
-rw-r--r--drivers/clk/tegra/Makefile1
-rw-r--r--drivers/clk/tegra/clk-periph-gate.c11
-rw-r--r--drivers/clk/tegra/clk-periph.c14
-rw-r--r--drivers/clk/tegra/clk-pll.c1144
-rw-r--r--drivers/clk/tegra/clk-tegra114.c2085
-rw-r--r--drivers/clk/tegra/clk-tegra20.c184
-rw-r--r--drivers/clk/tegra/clk-tegra30.c276
-rw-r--r--drivers/clk/tegra/clk.c14
-rw-r--r--drivers/clk/tegra/clk.h98
-rw-r--r--drivers/clocksource/Kconfig8
-rw-r--r--drivers/clocksource/Makefile2
-rw-r--r--drivers/clocksource/cadence_ttc_timer.c436
-rw-r--r--drivers/clocksource/em_sti.c13
-rw-r--r--drivers/clocksource/exynos_mct.c568
-rw-r--r--drivers/clocksource/sh_cmt.c189
-rw-r--r--drivers/clocksource/sh_mtu2.c2
-rw-r--r--drivers/clocksource/sh_tmu.c2
-rw-r--r--drivers/gpio/Kconfig6
-rw-r--r--drivers/gpio/Makefile1
-rw-r--r--drivers/gpio/gpio-samsung.c9
-rw-r--r--drivers/gpio/gpio-vt8500.c355
-rw-r--r--drivers/irqchip/Kconfig8
-rw-r--r--drivers/irqchip/Makefile4
-rw-r--r--drivers/irqchip/exynos-combiner.c80
-rw-r--r--drivers/irqchip/irq-renesas-intc-irqpin.c547
-rw-r--r--drivers/irqchip/irq-renesas-irqc.c307
-rw-r--r--drivers/irqchip/irq-s3c24xx.c1356
-rw-r--r--drivers/irqchip/irq-vt8500.c259
-rw-r--r--drivers/of/base.c111
-rw-r--r--drivers/pinctrl/Kconfig1
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/pinctrl-bcm2835.c19
-rw-r--r--drivers/pinctrl/pinctrl-exynos.c108
-rw-r--r--drivers/pinctrl/pinctrl-samsung.c2
-rw-r--r--drivers/pinctrl/pinctrl-samsung.h1
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c6
-rw-r--r--drivers/pinctrl/vt8500/Kconfig52
-rw-r--r--drivers/pinctrl/vt8500/Makefile8
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-vt8500.c501
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wm8505.c532
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wm8650.c370
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wm8750.c409
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wm8850.c388
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wmt.c632
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wmt.h79
-rw-r--r--drivers/reset/Kconfig13
-rw-r--r--drivers/reset/Makefile1
-rw-r--r--drivers/reset/core.c297
-rw-r--r--drivers/video/atmel_lcdfb.c120
60 files changed, 13600 insertions, 866 deletions
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 8d96238549fa..9953a42809ec 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -164,4 +164,6 @@ source "drivers/irqchip/Kconfig"
164 164
165source "drivers/ipack/Kconfig" 165source "drivers/ipack/Kconfig"
166 166
167source "drivers/reset/Kconfig"
168
167endmenu 169endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 8e57688ebd95..130abc1dfd65 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -37,6 +37,9 @@ obj-$(CONFIG_XEN) += xen/
37# regulators early, since some subsystems rely on them to initialize 37# regulators early, since some subsystems rely on them to initialize
38obj-$(CONFIG_REGULATOR) += regulator/ 38obj-$(CONFIG_REGULATOR) += regulator/
39 39
40# reset controllers early, since gpu drivers might rely on them to initialize
41obj-$(CONFIG_RESET_CONTROLLER) += reset/
42
40# tty/ comes before char/ so that the VT console is the boot-time 43# tty/ comes before char/ so that the VT console is the boot-time
41# default. 44# default.
42obj-y += tty/ 45obj-y += tty/
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e7f7fe9b2f09..137d3e730f86 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_ARCH_U8500) += ux500/
29obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o 29obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
30obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o 30obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
31obj-$(CONFIG_ARCH_TEGRA) += tegra/ 31obj-$(CONFIG_ARCH_TEGRA) += tegra/
32obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
32 33
33obj-$(CONFIG_X86) += x86/ 34obj-$(CONFIG_X86) += x86/
34 35
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
new file mode 100644
index 000000000000..b7c232e67425
--- /dev/null
+++ b/drivers/clk/samsung/Makefile
@@ -0,0 +1,8 @@
1#
2# Samsung Clock specific Makefile
3#
4
5obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
6obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
7obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
8obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
new file mode 100644
index 000000000000..71046694d9dd
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -0,0 +1,1091 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for all Exynos4 SoCs.
11*/
12
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/clk-provider.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
19#include <plat/cpu.h>
20#include "clk.h"
21#include "clk-pll.h"
22
23/* Exynos4 clock controller register offsets */
24#define SRC_LEFTBUS 0x4200
25#define DIV_LEFTBUS 0x4500
26#define GATE_IP_LEFTBUS 0x4800
27#define E4X12_GATE_IP_IMAGE 0x4930
28#define SRC_RIGHTBUS 0x8200
29#define DIV_RIGHTBUS 0x8500
30#define GATE_IP_RIGHTBUS 0x8800
31#define E4X12_GATE_IP_PERIR 0x8960
32#define EPLL_LOCK 0xc010
33#define VPLL_LOCK 0xc020
34#define EPLL_CON0 0xc110
35#define EPLL_CON1 0xc114
36#define EPLL_CON2 0xc118
37#define VPLL_CON0 0xc120
38#define VPLL_CON1 0xc124
39#define VPLL_CON2 0xc128
40#define SRC_TOP0 0xc210
41#define SRC_TOP1 0xc214
42#define SRC_CAM 0xc220
43#define SRC_TV 0xc224
44#define SRC_MFC 0xcc28
45#define SRC_G3D 0xc22c
46#define E4210_SRC_IMAGE 0xc230
47#define SRC_LCD0 0xc234
48#define E4210_SRC_LCD1 0xc238
49#define E4X12_SRC_ISP 0xc238
50#define SRC_MAUDIO 0xc23c
51#define SRC_FSYS 0xc240
52#define SRC_PERIL0 0xc250
53#define SRC_PERIL1 0xc254
54#define E4X12_SRC_CAM1 0xc258
55#define SRC_MASK_TOP 0xc310
56#define SRC_MASK_CAM 0xc320
57#define SRC_MASK_TV 0xc324
58#define SRC_MASK_LCD0 0xc334
59#define E4210_SRC_MASK_LCD1 0xc338
60#define E4X12_SRC_MASK_ISP 0xc338
61#define SRC_MASK_MAUDIO 0xc33c
62#define SRC_MASK_FSYS 0xc340
63#define SRC_MASK_PERIL0 0xc350
64#define SRC_MASK_PERIL1 0xc354
65#define DIV_TOP 0xc510
66#define DIV_CAM 0xc520
67#define DIV_TV 0xc524
68#define DIV_MFC 0xc528
69#define DIV_G3D 0xc52c
70#define DIV_IMAGE 0xc530
71#define DIV_LCD0 0xc534
72#define E4210_DIV_LCD1 0xc538
73#define E4X12_DIV_ISP 0xc538
74#define DIV_MAUDIO 0xc53c
75#define DIV_FSYS0 0xc540
76#define DIV_FSYS1 0xc544
77#define DIV_FSYS2 0xc548
78#define DIV_FSYS3 0xc54c
79#define DIV_PERIL0 0xc550
80#define DIV_PERIL1 0xc554
81#define DIV_PERIL2 0xc558
82#define DIV_PERIL3 0xc55c
83#define DIV_PERIL4 0xc560
84#define DIV_PERIL5 0xc564
85#define E4X12_DIV_CAM1 0xc568
86#define GATE_SCLK_CAM 0xc820
87#define GATE_IP_CAM 0xc920
88#define GATE_IP_TV 0xc924
89#define GATE_IP_MFC 0xc928
90#define GATE_IP_G3D 0xc92c
91#define E4210_GATE_IP_IMAGE 0xc930
92#define GATE_IP_LCD0 0xc934
93#define E4210_GATE_IP_LCD1 0xc938
94#define E4X12_GATE_IP_ISP 0xc938
95#define E4X12_GATE_IP_MAUDIO 0xc93c
96#define GATE_IP_FSYS 0xc940
97#define GATE_IP_GPS 0xc94c
98#define GATE_IP_PERIL 0xc950
99#define E4210_GATE_IP_PERIR 0xc960
100#define GATE_BLOCK 0xc970
101#define E4X12_MPLL_CON0 0x10108
102#define SRC_DMC 0x10200
103#define SRC_MASK_DMC 0x10300
104#define DIV_DMC0 0x10500
105#define DIV_DMC1 0x10504
106#define GATE_IP_DMC 0x10900
107#define APLL_CON0 0x14100
108#define E4210_MPLL_CON0 0x14108
109#define SRC_CPU 0x14200
110#define DIV_CPU0 0x14500
111#define DIV_CPU1 0x14504
112#define GATE_SCLK_CPU 0x14800
113#define GATE_IP_CPU 0x14900
114#define E4X12_DIV_ISP0 0x18300
115#define E4X12_DIV_ISP1 0x18304
116#define E4X12_GATE_ISP0 0x18800
117#define E4X12_GATE_ISP1 0x18804
118
119/* the exynos4 soc type */
120enum exynos4_soc {
121 EXYNOS4210,
122 EXYNOS4X12,
123};
124
125/*
126 * Let each supported clock get a unique id. This id is used to lookup the clock
127 * for device tree based platforms. The clocks are categorized into three
128 * sections: core, sclk gate and bus interface gate clocks.
129 *
130 * When adding a new clock to this list, it is advised to choose a clock
131 * category and add it to the end of that category. That is because the the
132 * device tree source file is referring to these ids and any change in the
133 * sequence number of existing clocks will require corresponding change in the
134 * device tree files. This limitation would go away when pre-processor support
135 * for dtc would be available.
136 */
137enum exynos4_clks {
138 none,
139
140 /* core clocks */
141 xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll,
142 sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100,
143 aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core,
144 mout_apll, /* 20 */
145
146 /* gate for special clocks (sclk) */
147 sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0,
148 sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac,
149 sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0,
150 sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4,
151 sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
152 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
153 sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
154 sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
155 sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp,
156
157 /* gate clocks */
158 fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
159 smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi,
160 smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d,
161 smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1,
162 mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0,
163 sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie,
164 onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3,
165 uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc,
166 spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus,
167 spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif,
168 audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0,
169 fimc_lite1, ppmuispx, ppmuispmx, fimc_isp, fimc_drc, fimc_fd, mcuisp,
170 gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp,
171 mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp,
172 asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk,
173 spi1_isp_sclk, uart_isp_sclk,
174
175 /* mux clocks */
176 mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
177 mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d,
178 aclk400_mcuisp,
179
180 /* div clocks */
181 div_isp0 = 450, div_isp1, div_mcuisp0, div_mcuisp1, div_aclk200,
182 div_aclk400_mcuisp,
183
184 nr_clks,
185};
186
187/*
188 * list of controller registers to be saved and restored during a
189 * suspend/resume cycle.
190 */
191static __initdata unsigned long exynos4210_clk_save[] = {
192 E4210_SRC_IMAGE,
193 E4210_SRC_LCD1,
194 E4210_SRC_MASK_LCD1,
195 E4210_DIV_LCD1,
196 E4210_GATE_IP_IMAGE,
197 E4210_GATE_IP_LCD1,
198 E4210_GATE_IP_PERIR,
199 E4210_MPLL_CON0,
200};
201
202static __initdata unsigned long exynos4x12_clk_save[] = {
203 E4X12_GATE_IP_IMAGE,
204 E4X12_GATE_IP_PERIR,
205 E4X12_SRC_CAM1,
206 E4X12_DIV_ISP,
207 E4X12_DIV_CAM1,
208 E4X12_MPLL_CON0,
209};
210
211static __initdata unsigned long exynos4_clk_regs[] = {
212 SRC_LEFTBUS,
213 DIV_LEFTBUS,
214 GATE_IP_LEFTBUS,
215 SRC_RIGHTBUS,
216 DIV_RIGHTBUS,
217 GATE_IP_RIGHTBUS,
218 EPLL_CON0,
219 EPLL_CON1,
220 EPLL_CON2,
221 VPLL_CON0,
222 VPLL_CON1,
223 VPLL_CON2,
224 SRC_TOP0,
225 SRC_TOP1,
226 SRC_CAM,
227 SRC_TV,
228 SRC_MFC,
229 SRC_G3D,
230 SRC_LCD0,
231 SRC_MAUDIO,
232 SRC_FSYS,
233 SRC_PERIL0,
234 SRC_PERIL1,
235 SRC_MASK_TOP,
236 SRC_MASK_CAM,
237 SRC_MASK_TV,
238 SRC_MASK_LCD0,
239 SRC_MASK_MAUDIO,
240 SRC_MASK_FSYS,
241 SRC_MASK_PERIL0,
242 SRC_MASK_PERIL1,
243 DIV_TOP,
244 DIV_CAM,
245 DIV_TV,
246 DIV_MFC,
247 DIV_G3D,
248 DIV_IMAGE,
249 DIV_LCD0,
250 DIV_MAUDIO,
251 DIV_FSYS0,
252 DIV_FSYS1,
253 DIV_FSYS2,
254 DIV_FSYS3,
255 DIV_PERIL0,
256 DIV_PERIL1,
257 DIV_PERIL2,
258 DIV_PERIL3,
259 DIV_PERIL4,
260 DIV_PERIL5,
261 GATE_SCLK_CAM,
262 GATE_IP_CAM,
263 GATE_IP_TV,
264 GATE_IP_MFC,
265 GATE_IP_G3D,
266 GATE_IP_LCD0,
267 GATE_IP_FSYS,
268 GATE_IP_GPS,
269 GATE_IP_PERIL,
270 GATE_BLOCK,
271 SRC_MASK_DMC,
272 SRC_DMC,
273 DIV_DMC0,
274 DIV_DMC1,
275 GATE_IP_DMC,
276 APLL_CON0,
277 SRC_CPU,
278 DIV_CPU0,
279 DIV_CPU1,
280 GATE_SCLK_CPU,
281 GATE_IP_CPU,
282};
283
284/* list of all parent clock list */
285PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
286PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
287PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
288PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
289PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
290PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
291PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
292PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
293PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
294PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
295PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", };
296PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
297 "spdif_extclk", };
298PNAME(mout_onenand_p) = {"aclk133", "aclk160", };
299PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
300
301/* Exynos 4210-specific parent groups */
302PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", };
303PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", };
304PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", };
305PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m",
306 "sclk_usbphy0", "none", "sclk_hdmiphy",
307 "sclk_mpll", "sclk_epll", "sclk_vpll", };
308PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m",
309 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
310 "sclk_epll", "sclk_vpll" };
311PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m",
312 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
313 "sclk_epll", "sclk_vpll", };
314PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
315 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
316 "sclk_epll", "sclk_vpll", };
317PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
318PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
319
320/* Exynos 4x12-specific parent groups */
321PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
322PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", };
323PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
324PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
325 "none", "sclk_hdmiphy", "mout_mpll_user_t",
326 "sclk_epll", "sclk_vpll", };
327PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m",
328 "sclk_usbphy0", "xxti", "xusbxti",
329 "mout_mpll_user_t", "sclk_epll", "sclk_vpll" };
330PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m",
331 "sclk_usbphy0", "xxti", "xusbxti",
332 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
333PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
334 "sclk_usbphy0", "xxti", "xusbxti",
335 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
336PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", };
337PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
338PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
339PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
340
341/* fixed rate clocks generated outside the soc */
342struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
343 FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
344 FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
345};
346
347/* fixed rate clocks generated inside the soc */
348struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
349 FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
350 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
351 FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
352};
353
354struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
355 FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
356};
357
358/* list of mux clocks supported in all exynos4 soc's */
359struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
360 MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
361 CLK_SET_RATE_PARENT, 0),
362 MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
363 MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
364 MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
365 MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
366 CLK_SET_RATE_PARENT, 0),
367 MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
368 CLK_SET_RATE_PARENT, 0),
369 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
370 MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
371 MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"),
372 MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
373};
374
375/* list of mux clocks supported in exynos4210 soc */
376struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
377 MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
378 MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
379 MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
380 MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
381 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
382 MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
383 MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
384 MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
385 MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
386 MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
387 MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
388 MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
389 MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"),
390 MUX_A(mout_core, "mout_core", mout_core_p4210,
391 SRC_CPU, 16, 1, "mout_core"),
392 MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
393 SRC_TOP0, 8, 1, "sclk_vpll"),
394 MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
395 MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
396 MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
397 MUX(mout_fimc3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
398 MUX(mout_cam0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
399 MUX(mout_cam1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
400 MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
401 MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
402 MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
403 MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
404 CLK_SET_RATE_PARENT, 0),
405 MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
406 MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
407 MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
408 MUX(none, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
409 MUX(none, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
410 MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
411 MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
412 MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
413 MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
414 MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
415 MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
416 MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
417 MUX(none, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
418 MUX(none, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
419 MUX(none, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
420 MUX(none, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
421 MUX(none, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
422 MUX(none, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
423 MUX(none, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
424};
425
426/* list of mux clocks supported in exynos4x12 soc */
427struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
428 MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
429 SRC_CPU, 24, 1),
430 MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
431 MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
432 MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12,
433 SRC_TOP1, 12, 1),
434 MUX(none, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
435 SRC_TOP1, 16, 1),
436 MUX(aclk200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
437 MUX(aclk400_mcuisp, "aclk400_mcuisp", mout_user_aclk400_mcuisp_p4x12,
438 SRC_TOP1, 24, 1),
439 MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
440 MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
441 MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
442 MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
443 MUX(none, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
444 MUX(none, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
445 MUX(none, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
446 MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
447 MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
448 MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
449 MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p,
450 SRC_DMC, 12, 1, "sclk_mpll"),
451 MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p,
452 SRC_TOP0, 8, 1, "sclk_vpll"),
453 MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
454 MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
455 MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
456 MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
457 MUX(mout_fimc3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
458 MUX(mout_cam0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
459 MUX(mout_cam1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
460 MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
461 MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
462 MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
463 MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
464 CLK_SET_RATE_PARENT, 0),
465 MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
466 MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
467 MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
468 MUX(none, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
469 MUX(none, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
470 MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
471 MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
472 MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
473 MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
474 MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
475 MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
476 MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
477 MUX(none, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
478 MUX(none, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
479 MUX(none, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
480 MUX(none, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
481 MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
482 MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
483 MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
484 MUX(none, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
485 MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
486 MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
487 MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
488};
489
490/* list of divider clocks supported in all exynos4 soc's */
491struct samsung_div_clock exynos4_div_clks[] __initdata = {
492 DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3),
493 DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3),
494 DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
495 DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
496 DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
497 DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
498 DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
499 DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
500 DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
501 DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
502 DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
503 DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4,
504 CLK_SET_RATE_PARENT, 0),
505 DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
506 DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
507 DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
508 DIV(sclk_pcm0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
509 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
510 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
511 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
512 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
513 DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
514 DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
515 DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
516 DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
517 DIV(none, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
518 DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
519 DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
520 DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
521 DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
522 DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
523 DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
524 DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8),
525 DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
526 DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
527 DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
528 DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
529 DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
530 DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
531 DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
532 DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
533 DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
534 DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
535 DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
536 DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
537 DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
538 DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "arm_clk"),
539 DIV_A(sclk_apll, "sclk_apll", "mout_apll",
540 DIV_CPU0, 24, 3, "sclk_apll"),
541 DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
542 CLK_SET_RATE_PARENT, 0),
543 DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
544 CLK_SET_RATE_PARENT, 0),
545 DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
546 CLK_SET_RATE_PARENT, 0),
547 DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
548 CLK_SET_RATE_PARENT, 0),
549 DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
550 CLK_SET_RATE_PARENT, 0),
551};
552
553/* list of divider clocks supported in exynos4210 soc */
554struct samsung_div_clock exynos4210_div_clks[] __initdata = {
555 DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
556 DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
557 DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
558 DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
559 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
560 DIV_F(none, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
561 CLK_SET_RATE_PARENT, 0),
562};
563
564/* list of divider clocks supported in exynos4x12 soc */
565struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
566 DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
567 DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
568 DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
569 DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
570 DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
571 DIV(div_aclk200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
572 DIV(none, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
573 DIV(div_aclk400_mcuisp, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
574 DIV_TOP, 24, 3),
575 DIV(none, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
576 DIV(none, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
577 DIV(none, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
578 DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
579 DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
580 DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
581 DIV(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
582 DIV(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
583 DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
584 DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
585 DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
586};
587
588/* list of gate clocks supported in all exynos4 soc's */
589struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
590 /*
591 * After all Exynos4 based platforms are migrated to use device tree,
592 * the device name and clock alias names specified below for some
593 * of the clocks can be removed.
594 */
595 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
596 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 0),
597 GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
598 GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
599 GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
600 GATE(fimd1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
601 GATE(mie1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
602 GATE(dsim1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
603 GATE(smmu_fimd1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 0),
604 GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
605 GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
606 GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
607 CLK_SET_RATE_PARENT, 0),
608 GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
609 GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
610 GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
611 GATE(gps, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
612 GATE(smmu_gps, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
613 GATE(slimbus, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
614 GATE(sclk_cam0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
615 CLK_SET_RATE_PARENT, 0),
616 GATE(sclk_cam1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
617 CLK_SET_RATE_PARENT, 0),
618 GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0",
619 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
620 GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
621 CLK_SET_RATE_PARENT, 0),
622 GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
623 CLK_SET_RATE_PARENT, 0),
624 GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
625 GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
626 GATE_D(hdmi, "exynos4-hdmi", "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
627 GATE_A(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0, "timers"),
628 GATE_A(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0, "biu"),
629 GATE_A(usb_host, "usb_host", "aclk133",
630 GATE_IP_FSYS, 12, 0, 0, "usbhost"),
631 GATE_DA(sclk_fimc0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0",
632 SRC_MASK_CAM, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
633 GATE_DA(sclk_fimc1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1",
634 SRC_MASK_CAM, 4, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
635 GATE_DA(sclk_fimc2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2",
636 SRC_MASK_CAM, 8, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
637 GATE_DA(sclk_fimc3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3",
638 SRC_MASK_CAM, 12, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
639 GATE_DA(sclk_csis0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0",
640 SRC_MASK_CAM, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
641 GATE_DA(sclk_csis1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1",
642 SRC_MASK_CAM, 28, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
643 GATE_DA(sclk_fimd0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0",
644 SRC_MASK_LCD0, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
645 GATE_DA(sclk_mmc0, "exynos4-sdhci.0", "sclk_mmc0", "div_mmc_pre0",
646 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0,
647 "mmc_busclk.2"),
648 GATE_DA(sclk_mmc1, "exynos4-sdhci.1", "sclk_mmc1", "div_mmc_pre1",
649 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0,
650 "mmc_busclk.2"),
651 GATE_DA(sclk_mmc2, "exynos4-sdhci.2", "sclk_mmc2", "div_mmc_pre2",
652 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0,
653 "mmc_busclk.2"),
654 GATE_DA(sclk_mmc3, "exynos4-sdhci.3", "sclk_mmc3", "div_mmc_pre3",
655 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0,
656 "mmc_busclk.2"),
657 GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc_pre4",
658 SRC_MASK_FSYS, 16, CLK_SET_RATE_PARENT, 0, "ciu"),
659 GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0",
660 SRC_MASK_PERIL0, 0, CLK_SET_RATE_PARENT,
661 0, "clk_uart_baud0"),
662 GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1",
663 SRC_MASK_PERIL0, 4, CLK_SET_RATE_PARENT,
664 0, "clk_uart_baud0"),
665 GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2",
666 SRC_MASK_PERIL0, 8, CLK_SET_RATE_PARENT,
667 0, "clk_uart_baud0"),
668 GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3",
669 SRC_MASK_PERIL0, 12, CLK_SET_RATE_PARENT,
670 0, "clk_uart_baud0"),
671 GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4",
672 SRC_MASK_PERIL0, 16, CLK_SET_RATE_PARENT,
673 0, "clk_uart_baud0"),
674 GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
675 CLK_SET_RATE_PARENT, 0),
676 GATE_DA(sclk_spi0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0",
677 SRC_MASK_PERIL1, 16, CLK_SET_RATE_PARENT,
678 0, "spi_busclk0"),
679 GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1",
680 SRC_MASK_PERIL1, 20, CLK_SET_RATE_PARENT,
681 0, "spi_busclk0"),
682 GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2",
683 SRC_MASK_PERIL1, 24, CLK_SET_RATE_PARENT,
684 0, "spi_busclk0"),
685 GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160",
686 GATE_IP_CAM, 0, 0, 0, "fimc"),
687 GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160",
688 GATE_IP_CAM, 1, 0, 0, "fimc"),
689 GATE_DA(fimc2, "exynos4-fimc.2", "fimc2", "aclk160",
690 GATE_IP_CAM, 2, 0, 0, "fimc"),
691 GATE_DA(fimc3, "exynos4-fimc.3", "fimc3", "aclk160",
692 GATE_IP_CAM, 3, 0, 0, "fimc"),
693 GATE_DA(csis0, "s5p-mipi-csis.0", "csis0", "aclk160",
694 GATE_IP_CAM, 4, 0, 0, "fimc"),
695 GATE_DA(csis1, "s5p-mipi-csis.1", "csis1", "aclk160",
696 GATE_IP_CAM, 5, 0, 0, "fimc"),
697 GATE_DA(smmu_fimc0, "exynos-sysmmu.5", "smmu_fimc0", "aclk160",
698 GATE_IP_CAM, 7, 0, 0, "sysmmu"),
699 GATE_DA(smmu_fimc1, "exynos-sysmmu.6", "smmu_fimc1", "aclk160",
700 GATE_IP_CAM, 8, 0, 0, "sysmmu"),
701 GATE_DA(smmu_fimc2, "exynos-sysmmu.7", "smmu_fimc2", "aclk160",
702 GATE_IP_CAM, 9, 0, 0, "sysmmu"),
703 GATE_DA(smmu_fimc3, "exynos-sysmmu.8", "smmu_fimc3", "aclk160",
704 GATE_IP_CAM, 10, 0, 0, "sysmmu"),
705 GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160",
706 GATE_IP_CAM, 11, 0, 0, "sysmmu"),
707 GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
708 GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
709 GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160",
710 GATE_IP_TV, 4, 0, 0, "sysmmu"),
711 GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"),
712 GATE_DA(smmu_mfcl, "exynos-sysmmu.0", "smmu_mfcl", "aclk100",
713 GATE_IP_MFC, 1, 0, 0, "sysmmu"),
714 GATE_DA(smmu_mfcr, "exynos-sysmmu.1", "smmu_mfcr", "aclk100",
715 GATE_IP_MFC, 2, 0, 0, "sysmmu"),
716 GATE_DA(fimd0, "exynos4-fb.0", "fimd0", "aclk160",
717 GATE_IP_LCD0, 0, 0, 0, "fimd"),
718 GATE_DA(smmu_fimd0, "exynos-sysmmu.10", "smmu_fimd0", "aclk160",
719 GATE_IP_LCD0, 4, 0, 0, "sysmmu"),
720 GATE_DA(pdma0, "dma-pl330.0", "pdma0", "aclk133",
721 GATE_IP_FSYS, 0, 0, 0, "dma"),
722 GATE_DA(pdma1, "dma-pl330.1", "pdma1", "aclk133",
723 GATE_IP_FSYS, 1, 0, 0, "dma"),
724 GATE_DA(sdmmc0, "exynos4-sdhci.0", "sdmmc0", "aclk133",
725 GATE_IP_FSYS, 5, 0, 0, "hsmmc"),
726 GATE_DA(sdmmc1, "exynos4-sdhci.1", "sdmmc1", "aclk133",
727 GATE_IP_FSYS, 6, 0, 0, "hsmmc"),
728 GATE_DA(sdmmc2, "exynos4-sdhci.2", "sdmmc2", "aclk133",
729 GATE_IP_FSYS, 7, 0, 0, "hsmmc"),
730 GATE_DA(sdmmc3, "exynos4-sdhci.3", "sdmmc3", "aclk133",
731 GATE_IP_FSYS, 8, 0, 0, "hsmmc"),
732 GATE_DA(uart0, "exynos4210-uart.0", "uart0", "aclk100",
733 GATE_IP_PERIL, 0, 0, 0, "uart"),
734 GATE_DA(uart1, "exynos4210-uart.1", "uart1", "aclk100",
735 GATE_IP_PERIL, 1, 0, 0, "uart"),
736 GATE_DA(uart2, "exynos4210-uart.2", "uart2", "aclk100",
737 GATE_IP_PERIL, 2, 0, 0, "uart"),
738 GATE_DA(uart3, "exynos4210-uart.3", "uart3", "aclk100",
739 GATE_IP_PERIL, 3, 0, 0, "uart"),
740 GATE_DA(uart4, "exynos4210-uart.4", "uart4", "aclk100",
741 GATE_IP_PERIL, 4, 0, 0, "uart"),
742 GATE_DA(i2c0, "s3c2440-i2c.0", "i2c0", "aclk100",
743 GATE_IP_PERIL, 6, 0, 0, "i2c"),
744 GATE_DA(i2c1, "s3c2440-i2c.1", "i2c1", "aclk100",
745 GATE_IP_PERIL, 7, 0, 0, "i2c"),
746 GATE_DA(i2c2, "s3c2440-i2c.2", "i2c2", "aclk100",
747 GATE_IP_PERIL, 8, 0, 0, "i2c"),
748 GATE_DA(i2c3, "s3c2440-i2c.3", "i2c3", "aclk100",
749 GATE_IP_PERIL, 9, 0, 0, "i2c"),
750 GATE_DA(i2c4, "s3c2440-i2c.4", "i2c4", "aclk100",
751 GATE_IP_PERIL, 10, 0, 0, "i2c"),
752 GATE_DA(i2c5, "s3c2440-i2c.5", "i2c5", "aclk100",
753 GATE_IP_PERIL, 11, 0, 0, "i2c"),
754 GATE_DA(i2c6, "s3c2440-i2c.6", "i2c6", "aclk100",
755 GATE_IP_PERIL, 12, 0, 0, "i2c"),
756 GATE_DA(i2c7, "s3c2440-i2c.7", "i2c7", "aclk100",
757 GATE_IP_PERIL, 13, 0, 0, "i2c"),
758 GATE_DA(i2c_hdmi, "s3c2440-hdmiphy-i2c", "i2c-hdmi", "aclk100",
759 GATE_IP_PERIL, 14, 0, 0, "i2c"),
760 GATE_DA(spi0, "exynos4210-spi.0", "spi0", "aclk100",
761 GATE_IP_PERIL, 16, 0, 0, "spi"),
762 GATE_DA(spi1, "exynos4210-spi.1", "spi1", "aclk100",
763 GATE_IP_PERIL, 17, 0, 0, "spi"),
764 GATE_DA(spi2, "exynos4210-spi.2", "spi2", "aclk100",
765 GATE_IP_PERIL, 18, 0, 0, "spi"),
766 GATE_DA(i2s1, "samsung-i2s.1", "i2s1", "aclk100",
767 GATE_IP_PERIL, 20, 0, 0, "iis"),
768 GATE_DA(i2s2, "samsung-i2s.2", "i2s2", "aclk100",
769 GATE_IP_PERIL, 21, 0, 0, "iis"),
770 GATE_DA(pcm1, "samsung-pcm.1", "pcm1", "aclk100",
771 GATE_IP_PERIL, 22, 0, 0, "pcm"),
772 GATE_DA(pcm2, "samsung-pcm.2", "pcm2", "aclk100",
773 GATE_IP_PERIL, 23, 0, 0, "pcm"),
774 GATE_DA(spdif, "samsung-spdif", "spdif", "aclk100",
775 GATE_IP_PERIL, 26, 0, 0, "spdif"),
776 GATE_DA(ac97, "samsung-ac97", "ac97", "aclk100",
777 GATE_IP_PERIL, 27, 0, 0, "ac97"),
778};
779
780/* list of gate clocks supported in exynos4210 soc */
781struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
782 GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
783 GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
784 GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
785 GATE(mdma, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
786 GATE(smmu_g2d, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
787 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 0),
788 GATE(pcie_phy, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
789 GATE(sata_phy, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
790 GATE(sata, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
791 GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
792 GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
793 GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
794 GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
795 GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
796 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0),
797 GATE(smmu_rotator, "smmu_rotator", "aclk200",
798 E4210_GATE_IP_IMAGE, 4, 0, 0),
799 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1",
800 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
801 GATE(sclk_sata, "sclk_sata", "div_sata",
802 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
803 GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
804 GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
805 GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"),
806 GATE_A(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 0, 0, "mct"),
807 GATE_A(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
808 GATE_A(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 0, 0, "rtc"),
809 GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"),
810 GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1",
811 E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
812};
813
814/* list of gate clocks supported in exynos4x12 soc */
815struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
816 GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
817 GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
818 GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
819 GATE(mdma2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
820 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0),
821 GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
822 GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
823 GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0),
824 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0),
825 GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0",
826 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
827 GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
828 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
829 GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi",
830 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
831 GATE(smmu_rotator, "smmu_rotator", "aclk200",
832 E4X12_GATE_IP_IMAGE, 4, 0, 0),
833 GATE_A(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 0, 0, "mct"),
834 GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"),
835 GATE_A(keyif, "keyif", "aclk100",
836 E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"),
837 GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp",
838 E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0),
839 GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre",
840 E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0),
841 GATE(sclk_spi1_isp, "sclk_spi1_isp", "div_spi1_isp_pre",
842 E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0),
843 GATE(sclk_uart_isp, "sclk_uart_isp", "div_uart_isp",
844 E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0),
845 GATE(pwm_isp_sclk, "pwm_isp_sclk", "sclk_pwm_isp",
846 E4X12_GATE_IP_ISP, 0, 0, 0),
847 GATE(spi0_isp_sclk, "spi0_isp_sclk", "sclk_spi0_isp",
848 E4X12_GATE_IP_ISP, 1, 0, 0),
849 GATE(spi1_isp_sclk, "spi1_isp_sclk", "sclk_spi1_isp",
850 E4X12_GATE_IP_ISP, 2, 0, 0),
851 GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp",
852 E4X12_GATE_IP_ISP, 3, 0, 0),
853 GATE_A(wdt, "watchdog", "aclk100",
854 E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
855 GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100",
856 E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"),
857 GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100",
858 E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),
859 GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0,
860 CLK_IGNORE_UNUSED, 0),
861 GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1,
862 CLK_IGNORE_UNUSED, 0),
863 GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2,
864 CLK_IGNORE_UNUSED, 0),
865 GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
866 CLK_IGNORE_UNUSED, 0),
867 GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
868 CLK_IGNORE_UNUSED, 0),
869 GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
870 CLK_IGNORE_UNUSED, 0),
871 GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
872 CLK_IGNORE_UNUSED, 0),
873 GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
874 CLK_IGNORE_UNUSED, 0),
875 GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
876 CLK_IGNORE_UNUSED, 0),
877 GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
878 CLK_IGNORE_UNUSED, 0),
879 GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
880 CLK_IGNORE_UNUSED, 0),
881 GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
882 CLK_IGNORE_UNUSED, 0),
883 GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
884 CLK_IGNORE_UNUSED, 0),
885 GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
886 CLK_IGNORE_UNUSED, 0),
887 GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
888 CLK_IGNORE_UNUSED, 0),
889 GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
890 CLK_IGNORE_UNUSED, 0),
891 GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
892 CLK_IGNORE_UNUSED, 0),
893 GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
894 CLK_IGNORE_UNUSED, 0),
895 GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
896 CLK_IGNORE_UNUSED, 0),
897 GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
898 CLK_IGNORE_UNUSED, 0),
899 GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
900 CLK_IGNORE_UNUSED, 0),
901 GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
902 CLK_IGNORE_UNUSED, 0),
903 GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
904 CLK_IGNORE_UNUSED, 0),
905 GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
906 CLK_IGNORE_UNUSED, 0),
907 GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
908 CLK_IGNORE_UNUSED, 0),
909 GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
910 CLK_IGNORE_UNUSED, 0),
911};
912
913#ifdef CONFIG_OF
914static struct of_device_id exynos4_clk_ids[] __initdata = {
915 { .compatible = "samsung,exynos4210-clock",
916 .data = (void *)EXYNOS4210, },
917 { .compatible = "samsung,exynos4412-clock",
918 .data = (void *)EXYNOS4X12, },
919 { },
920};
921#endif
922
923/*
924 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
925 * resides in chipid register space, outside of the clock controller memory
926 * mapped space. So to determine the parent of fin_pll clock, the chipid
927 * controller is first remapped and the value of XOM[0] bit is read to
928 * determine the parent clock.
929 */
930static void __init exynos4_clk_register_finpll(void)
931{
932 struct samsung_fixed_rate_clock fclk;
933 struct device_node *np;
934 struct clk *clk;
935 void __iomem *chipid_base = S5P_VA_CHIPID;
936 unsigned long xom, finpll_f = 24000000;
937 char *parent_name;
938
939 np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
940 if (np)
941 chipid_base = of_iomap(np, 0);
942
943 if (chipid_base) {
944 xom = readl(chipid_base + 8);
945 parent_name = xom & 1 ? "xusbxti" : "xxti";
946 clk = clk_get(NULL, parent_name);
947 if (IS_ERR(clk)) {
948 pr_err("%s: failed to lookup parent clock %s, assuming "
949 "fin_pll clock frequency is 24MHz\n", __func__,
950 parent_name);
951 } else {
952 finpll_f = clk_get_rate(clk);
953 }
954 } else {
955 pr_err("%s: failed to map chipid registers, assuming "
956 "fin_pll clock frequency is 24MHz\n", __func__);
957 }
958
959 fclk.id = fin_pll;
960 fclk.name = "fin_pll";
961 fclk.parent_name = NULL;
962 fclk.flags = CLK_IS_ROOT;
963 fclk.fixed_rate = finpll_f;
964 samsung_clk_register_fixed_rate(&fclk, 1);
965
966 if (np)
967 iounmap(chipid_base);
968}
969
970/*
971 * This function allows non-dt platforms to specify the clock speed of the
972 * xxti and xusbxti clocks. These clocks are then registered with the specified
973 * clock speed.
974 */
975void __init exynos4_clk_register_fixed_ext(unsigned long xxti_f,
976 unsigned long xusbxti_f)
977{
978 exynos4_fixed_rate_ext_clks[0].fixed_rate = xxti_f;
979 exynos4_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
980 samsung_clk_register_fixed_rate(exynos4_fixed_rate_ext_clks,
981 ARRAY_SIZE(exynos4_fixed_rate_ext_clks));
982}
983
984static __initdata struct of_device_id ext_clk_match[] = {
985 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
986 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
987 {},
988};
989
990/* register exynos4 clocks */
991void __init exynos4_clk_init(struct device_node *np)
992{
993 void __iomem *reg_base;
994 struct clk *apll, *mpll, *epll, *vpll;
995 u32 exynos4_soc;
996
997 if (np) {
998 const struct of_device_id *match;
999 match = of_match_node(exynos4_clk_ids, np);
1000 exynos4_soc = (u32)match->data;
1001
1002 reg_base = of_iomap(np, 0);
1003 if (!reg_base)
1004 panic("%s: failed to map registers\n", __func__);
1005 } else {
1006 reg_base = S5P_VA_CMU;
1007 if (soc_is_exynos4210())
1008 exynos4_soc = EXYNOS4210;
1009 else if (soc_is_exynos4212() || soc_is_exynos4412())
1010 exynos4_soc = EXYNOS4X12;
1011 else
1012 panic("%s: unable to determine soc\n", __func__);
1013 }
1014
1015 if (exynos4_soc == EXYNOS4210)
1016 samsung_clk_init(np, reg_base, nr_clks,
1017 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1018 exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save));
1019 else
1020 samsung_clk_init(np, reg_base, nr_clks,
1021 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1022 exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save));
1023
1024 if (np)
1025 samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
1026 ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
1027 ext_clk_match);
1028
1029 exynos4_clk_register_finpll();
1030
1031 if (exynos4_soc == EXYNOS4210) {
1032 apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll",
1033 reg_base + APLL_CON0, pll_4508);
1034 mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll",
1035 reg_base + E4210_MPLL_CON0, pll_4508);
1036 epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll",
1037 reg_base + EPLL_CON0, pll_4600);
1038 vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc",
1039 reg_base + VPLL_CON0, pll_4650c);
1040 } else {
1041 apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
1042 reg_base + APLL_CON0);
1043 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
1044 reg_base + E4X12_MPLL_CON0);
1045 epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
1046 reg_base + EPLL_CON0);
1047 vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll",
1048 reg_base + VPLL_CON0);
1049 }
1050
1051 samsung_clk_add_lookup(apll, fout_apll);
1052 samsung_clk_add_lookup(mpll, fout_mpll);
1053 samsung_clk_add_lookup(epll, fout_epll);
1054 samsung_clk_add_lookup(vpll, fout_vpll);
1055
1056 samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
1057 ARRAY_SIZE(exynos4_fixed_rate_clks));
1058 samsung_clk_register_mux(exynos4_mux_clks,
1059 ARRAY_SIZE(exynos4_mux_clks));
1060 samsung_clk_register_div(exynos4_div_clks,
1061 ARRAY_SIZE(exynos4_div_clks));
1062 samsung_clk_register_gate(exynos4_gate_clks,
1063 ARRAY_SIZE(exynos4_gate_clks));
1064
1065 if (exynos4_soc == EXYNOS4210) {
1066 samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks,
1067 ARRAY_SIZE(exynos4210_fixed_rate_clks));
1068 samsung_clk_register_mux(exynos4210_mux_clks,
1069 ARRAY_SIZE(exynos4210_mux_clks));
1070 samsung_clk_register_div(exynos4210_div_clks,
1071 ARRAY_SIZE(exynos4210_div_clks));
1072 samsung_clk_register_gate(exynos4210_gate_clks,
1073 ARRAY_SIZE(exynos4210_gate_clks));
1074 } else {
1075 samsung_clk_register_mux(exynos4x12_mux_clks,
1076 ARRAY_SIZE(exynos4x12_mux_clks));
1077 samsung_clk_register_div(exynos4x12_div_clks,
1078 ARRAY_SIZE(exynos4x12_div_clks));
1079 samsung_clk_register_gate(exynos4x12_gate_clks,
1080 ARRAY_SIZE(exynos4x12_gate_clks));
1081 }
1082
1083 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
1084 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
1085 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
1086 _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
1087 _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
1088 _get_rate("arm_clk"));
1089}
1090CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4_clk_init);
1091CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
new file mode 100644
index 000000000000..bb54606ff035
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -0,0 +1,523 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for Exynos5250 SoC.
11*/
12
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/clk-provider.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
19#include <plat/cpu.h>
20#include "clk.h"
21#include "clk-pll.h"
22
23#define SRC_CPU 0x200
24#define DIV_CPU0 0x500
25#define SRC_CORE1 0x4204
26#define SRC_TOP0 0x10210
27#define SRC_TOP2 0x10218
28#define SRC_GSCL 0x10220
29#define SRC_DISP1_0 0x1022c
30#define SRC_MAU 0x10240
31#define SRC_FSYS 0x10244
32#define SRC_GEN 0x10248
33#define SRC_PERIC0 0x10250
34#define SRC_PERIC1 0x10254
35#define SRC_MASK_GSCL 0x10320
36#define SRC_MASK_DISP1_0 0x1032c
37#define SRC_MASK_MAU 0x10334
38#define SRC_MASK_FSYS 0x10340
39#define SRC_MASK_GEN 0x10344
40#define SRC_MASK_PERIC0 0x10350
41#define SRC_MASK_PERIC1 0x10354
42#define DIV_TOP0 0x10510
43#define DIV_TOP1 0x10514
44#define DIV_GSCL 0x10520
45#define DIV_DISP1_0 0x1052c
46#define DIV_GEN 0x1053c
47#define DIV_MAU 0x10544
48#define DIV_FSYS0 0x10548
49#define DIV_FSYS1 0x1054c
50#define DIV_FSYS2 0x10550
51#define DIV_PERIC0 0x10558
52#define DIV_PERIC1 0x1055c
53#define DIV_PERIC2 0x10560
54#define DIV_PERIC3 0x10564
55#define DIV_PERIC4 0x10568
56#define DIV_PERIC5 0x1056c
57#define GATE_IP_GSCL 0x10920
58#define GATE_IP_MFC 0x1092c
59#define GATE_IP_GEN 0x10934
60#define GATE_IP_FSYS 0x10944
61#define GATE_IP_PERIC 0x10950
62#define GATE_IP_PERIS 0x10960
63#define SRC_CDREX 0x20200
64#define PLL_DIV2_SEL 0x20a24
65#define GATE_IP_DISP1 0x10928
66
67/*
68 * Let each supported clock get a unique id. This id is used to lookup the clock
69 * for device tree based platforms. The clocks are categorized into three
70 * sections: core, sclk gate and bus interface gate clocks.
71 *
72 * When adding a new clock to this list, it is advised to choose a clock
73 * category and add it to the end of that category. That is because the the
74 * device tree source file is referring to these ids and any change in the
75 * sequence number of existing clocks will require corresponding change in the
76 * device tree files. This limitation would go away when pre-processor support
77 * for dtc would be available.
78 */
79enum exynos5250_clks {
80 none,
81
82 /* core clocks */
83 fin_pll,
84
85 /* gate for special clocks (sclk) */
86 sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb,
87 sclk_fimd1, sclk_mipi1, sclk_dp, sclk_hdmi, sclk_pixel, sclk_audio0,
88 sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
89 sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
90 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
91
92 /* gate clocks */
93 gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
94 smmu_gscl1, smmu_gscl2, smmu_gscl3, mfc, smmu_mfcl, smmu_mfcr, rotator,
95 jpeg, mdma1, smmu_rotator, smmu_jpeg, smmu_mdma1, pdma0, pdma1, sata,
96 usbotg, mipi_hsi, sdmmc0, sdmmc1, sdmmc2, sdmmc3, sromc, usb2, usb3,
97 sata_phyctrl, sata_phyi2c, uart0, uart1, uart2, uart3, uart4, i2c0,
98 i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, adc, spi0, spi1,
99 spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
100 hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
101 tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
102 wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
103
104 nr_clks,
105};
106
107/*
108 * list of controller registers to be saved and restored during a
109 * suspend/resume cycle.
110 */
111static __initdata unsigned long exynos5250_clk_regs[] = {
112 SRC_CPU,
113 DIV_CPU0,
114 SRC_CORE1,
115 SRC_TOP0,
116 SRC_TOP2,
117 SRC_GSCL,
118 SRC_DISP1_0,
119 SRC_MAU,
120 SRC_FSYS,
121 SRC_GEN,
122 SRC_PERIC0,
123 SRC_PERIC1,
124 SRC_MASK_GSCL,
125 SRC_MASK_DISP1_0,
126 SRC_MASK_MAU,
127 SRC_MASK_FSYS,
128 SRC_MASK_GEN,
129 SRC_MASK_PERIC0,
130 SRC_MASK_PERIC1,
131 DIV_TOP0,
132 DIV_TOP1,
133 DIV_GSCL,
134 DIV_DISP1_0,
135 DIV_GEN,
136 DIV_MAU,
137 DIV_FSYS0,
138 DIV_FSYS1,
139 DIV_FSYS2,
140 DIV_PERIC0,
141 DIV_PERIC1,
142 DIV_PERIC2,
143 DIV_PERIC3,
144 DIV_PERIC4,
145 DIV_PERIC5,
146 GATE_IP_GSCL,
147 GATE_IP_MFC,
148 GATE_IP_GEN,
149 GATE_IP_FSYS,
150 GATE_IP_PERIC,
151 GATE_IP_PERIS,
152 SRC_CDREX,
153 PLL_DIV2_SEL,
154 GATE_IP_DISP1,
155};
156
157/* list of all parent clock list */
158PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
159PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
160PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
161PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
162PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
163PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" };
164PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
165PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
166PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
167PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
168PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll" };
169PNAME(mout_bpll_user_p) = { "fin_pll", "sclk_bpll" };
170PNAME(mout_aclk166_p) = { "sclk_cpll", "sclk_mpll_user" };
171PNAME(mout_aclk200_p) = { "sclk_mpll_user", "sclk_bpll_user" };
172PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
173PNAME(mout_usb3_p) = { "sclk_mpll_user", "sclk_cpll" };
174PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
175 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
176 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
177 "sclk_cpll" };
178PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
179 "sclk_uhostphy", "sclk_hdmiphy",
180 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
181 "sclk_cpll" };
182PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
183 "sclk_uhostphy", "sclk_hdmiphy",
184 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
185 "sclk_cpll" };
186PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
187 "sclk_uhostphy", "sclk_hdmiphy",
188 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
189 "sclk_cpll" };
190PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
191 "spdif_extclk" };
192
193/* fixed rate clocks generated outside the soc */
194struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
195 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
196};
197
198/* fixed rate clocks generated inside the soc */
199struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
200 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
201 FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
202 FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
203 FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
204};
205
206struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
207 FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
208 FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
209};
210
211struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
212 MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
213 MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
214 MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
215 MUX(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
216 MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
217 MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
218 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
219 MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
220 MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1),
221 MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
222 MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
223 MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
224 MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
225 MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
226 MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
227 MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
228 MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
229 MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
230 MUX(none, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
231 MUX(none, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
232 MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
233 MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
234 MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
235 MUX(none, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
236 MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
237 MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
238 MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
239 MUX(none, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
240 MUX(none, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
241 MUX(none, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
242 MUX(none, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
243 MUX(none, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
244 MUX(none, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
245 MUX(none, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
246 MUX(none, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
247 MUX(none, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
248 MUX(none, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
249 MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
250 MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
251 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
252 MUX(none, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
253 MUX(none, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
254 MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
255};
256
257struct samsung_div_clock exynos5250_div_clks[] __initdata = {
258 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
259 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
260 DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3),
261 DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
262 DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3),
263 DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
264 DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
265 DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
266 DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
267 DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
268 DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
269 DIV(none, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
270 DIV(none, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
271 DIV(none, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
272 DIV(none, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
273 DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
274 DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
275 DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
276 DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
277 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
278 DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
279 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
280 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
281 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
282 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
283 DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
284 DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
285 DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
286 DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
287 DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
288 DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
289 DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
290 DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
291 DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
292 DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
293 DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
294 DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
295 DIV(none, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
296 DIV(none, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
297 DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
298 DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
299 DIV_F(none, "div_mipi1_pre", "div_mipi1",
300 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
301 DIV_F(none, "div_mmc_pre0", "div_mmc0",
302 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
303 DIV_F(none, "div_mmc_pre1", "div_mmc1",
304 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
305 DIV_F(none, "div_mmc_pre2", "div_mmc2",
306 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
307 DIV_F(none, "div_mmc_pre3", "div_mmc3",
308 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
309 DIV_F(none, "div_spi_pre0", "div_spi0",
310 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
311 DIV_F(none, "div_spi_pre1", "div_spi1",
312 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
313 DIV_F(none, "div_spi_pre2", "div_spi2",
314 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
315};
316
317struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
318 GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0),
319 GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0),
320 GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0),
321 GATE(gscl3, "gscl3", "aclk266", GATE_IP_GSCL, 3, 0, 0),
322 GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
323 GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
324 GATE(smmu_gscl0, "smmu_gscl0", "aclk266", GATE_IP_GSCL, 7, 0, 0),
325 GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0),
326 GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
327 GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
328 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
329 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
330 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
331 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
332 GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0),
333 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
334 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
335 GATE(smmu_jpeg, "smmu_jpeg", "aclk166", GATE_IP_GEN, 7, 0, 0),
336 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
337 GATE(pdma0, "pdma0", "aclk200", GATE_IP_FSYS, 1, 0, 0),
338 GATE(pdma1, "pdma1", "aclk200", GATE_IP_FSYS, 2, 0, 0),
339 GATE(sata, "sata", "aclk200", GATE_IP_FSYS, 6, 0, 0),
340 GATE(usbotg, "usbotg", "aclk200", GATE_IP_FSYS, 7, 0, 0),
341 GATE(mipi_hsi, "mipi_hsi", "aclk200", GATE_IP_FSYS, 8, 0, 0),
342 GATE(sdmmc0, "sdmmc0", "aclk200", GATE_IP_FSYS, 12, 0, 0),
343 GATE(sdmmc1, "sdmmc1", "aclk200", GATE_IP_FSYS, 13, 0, 0),
344 GATE(sdmmc2, "sdmmc2", "aclk200", GATE_IP_FSYS, 14, 0, 0),
345 GATE(sdmmc3, "sdmmc3", "aclk200", GATE_IP_FSYS, 15, 0, 0),
346 GATE(sromc, "sromc", "aclk200", GATE_IP_FSYS, 17, 0, 0),
347 GATE(usb2, "usb2", "aclk200", GATE_IP_FSYS, 18, 0, 0),
348 GATE(usb3, "usb3", "aclk200", GATE_IP_FSYS, 19, 0, 0),
349 GATE(sata_phyctrl, "sata_phyctrl", "aclk200", GATE_IP_FSYS, 24, 0, 0),
350 GATE(sata_phyi2c, "sata_phyi2c", "aclk200", GATE_IP_FSYS, 25, 0, 0),
351 GATE(uart0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
352 GATE(uart1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
353 GATE(uart2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
354 GATE(uart3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
355 GATE(uart4, "uart4", "aclk66", GATE_IP_PERIC, 4, 0, 0),
356 GATE(i2c0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
357 GATE(i2c1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
358 GATE(i2c2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
359 GATE(i2c3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
360 GATE(i2c4, "i2c4", "aclk66", GATE_IP_PERIC, 10, 0, 0),
361 GATE(i2c5, "i2c5", "aclk66", GATE_IP_PERIC, 11, 0, 0),
362 GATE(i2c6, "i2c6", "aclk66", GATE_IP_PERIC, 12, 0, 0),
363 GATE(i2c7, "i2c7", "aclk66", GATE_IP_PERIC, 13, 0, 0),
364 GATE(i2c_hdmi, "i2c_hdmi", "aclk66", GATE_IP_PERIC, 14, 0, 0),
365 GATE(adc, "adc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
366 GATE(spi0, "spi0", "aclk66", GATE_IP_PERIC, 16, 0, 0),
367 GATE(spi1, "spi1", "aclk66", GATE_IP_PERIC, 17, 0, 0),
368 GATE(spi2, "spi2", "aclk66", GATE_IP_PERIC, 18, 0, 0),
369 GATE(i2s1, "i2s1", "aclk66", GATE_IP_PERIC, 20, 0, 0),
370 GATE(i2s2, "i2s2", "aclk66", GATE_IP_PERIC, 21, 0, 0),
371 GATE(pcm1, "pcm1", "aclk66", GATE_IP_PERIC, 22, 0, 0),
372 GATE(pcm2, "pcm2", "aclk66", GATE_IP_PERIC, 23, 0, 0),
373 GATE(pwm, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
374 GATE(spdif, "spdif", "aclk66", GATE_IP_PERIC, 26, 0, 0),
375 GATE(ac97, "ac97", "aclk66", GATE_IP_PERIC, 27, 0, 0),
376 GATE(hsi2c0, "hsi2c0", "aclk66", GATE_IP_PERIC, 28, 0, 0),
377 GATE(hsi2c1, "hsi2c1", "aclk66", GATE_IP_PERIC, 29, 0, 0),
378 GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
379 GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
380 GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
381 GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
382 GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, 0, 0),
383 GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
384 GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
385 GATE(tzpc2, "tzpc2", "aclk66", GATE_IP_PERIS, 8, 0, 0),
386 GATE(tzpc3, "tzpc3", "aclk66", GATE_IP_PERIS, 9, 0, 0),
387 GATE(tzpc4, "tzpc4", "aclk66", GATE_IP_PERIS, 10, 0, 0),
388 GATE(tzpc5, "tzpc5", "aclk66", GATE_IP_PERIS, 11, 0, 0),
389 GATE(tzpc6, "tzpc6", "aclk66", GATE_IP_PERIS, 12, 0, 0),
390 GATE(tzpc7, "tzpc7", "aclk66", GATE_IP_PERIS, 13, 0, 0),
391 GATE(tzpc8, "tzpc8", "aclk66", GATE_IP_PERIS, 14, 0, 0),
392 GATE(tzpc9, "tzpc9", "aclk66", GATE_IP_PERIS, 15, 0, 0),
393 GATE(hdmi_cec, "hdmi_cec", "aclk66", GATE_IP_PERIS, 16, 0, 0),
394 GATE(mct, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
395 GATE(wdt, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
396 GATE(rtc, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
397 GATE(tmu, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
398 GATE(cmu_top, "cmu_top", "aclk66",
399 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
400 GATE(cmu_core, "cmu_core", "aclk66",
401 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
402 GATE(cmu_mem, "cmu_mem", "aclk66",
403 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
404 GATE(sclk_cam_bayer, "sclk_cam_bayer", "div_cam_bayer",
405 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
406 GATE(sclk_cam0, "sclk_cam0", "div_cam0",
407 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
408 GATE(sclk_cam1, "sclk_cam1", "div_cam1",
409 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
410 GATE(sclk_gscl_wa, "sclk_gscl_wa", "div_gscl_wa",
411 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
412 GATE(sclk_gscl_wb, "sclk_gscl_wb", "div_gscl_wb",
413 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
414 GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1",
415 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
416 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi1",
417 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
418 GATE(sclk_dp, "sclk_dp", "div_dp",
419 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
420 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
421 SRC_MASK_DISP1_0, 20, 0, 0),
422 GATE(sclk_audio0, "sclk_audio0", "div_audio0",
423 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
424 GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0",
425 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
426 GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1",
427 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
428 GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2",
429 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
430 GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3",
431 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
432 GATE(sclk_sata, "sclk_sata", "div_sata",
433 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
434 GATE(sclk_usb3, "sclk_usb3", "div_usb3",
435 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
436 GATE(sclk_jpeg, "sclk_jpeg", "div_jpeg",
437 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
438 GATE(sclk_uart0, "sclk_uart0", "div_uart0",
439 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
440 GATE(sclk_uart1, "sclk_uart1", "div_uart1",
441 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
442 GATE(sclk_uart2, "sclk_uart2", "div_uart2",
443 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
444 GATE(sclk_uart3, "sclk_uart3", "div_uart3",
445 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
446 GATE(sclk_pwm, "sclk_pwm", "div_pwm",
447 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
448 GATE(sclk_audio1, "sclk_audio1", "div_audio1",
449 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
450 GATE(sclk_audio2, "sclk_audio2", "div_audio2",
451 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
452 GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
453 SRC_MASK_PERIC1, 4, 0, 0),
454 GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0",
455 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
456 GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1",
457 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
458 GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2",
459 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
460 GATE(fimd1, "fimd1", "aclk200", GATE_IP_DISP1, 0, 0, 0),
461 GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0),
462 GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0),
463 GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
464 GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0),
465 GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0),
466};
467
468static __initdata struct of_device_id ext_clk_match[] = {
469 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
470 { },
471};
472
473/* register exynox5250 clocks */
474void __init exynos5250_clk_init(struct device_node *np)
475{
476 void __iomem *reg_base;
477 struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
478
479 if (np) {
480 reg_base = of_iomap(np, 0);
481 if (!reg_base)
482 panic("%s: failed to map registers\n", __func__);
483 } else {
484 panic("%s: unable to determine soc\n", __func__);
485 }
486
487 samsung_clk_init(np, reg_base, nr_clks,
488 exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs),
489 NULL, 0);
490 samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
491 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
492 ext_clk_match);
493
494 apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
495 reg_base + 0x100);
496 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
497 reg_base + 0x4100);
498 bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
499 reg_base + 0x20110);
500 gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
501 reg_base + 0x10150);
502 cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
503 reg_base + 0x10120);
504 epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
505 reg_base + 0x10130);
506 vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
507 reg_base + 0x10140);
508
509 samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
510 ARRAY_SIZE(exynos5250_fixed_rate_clks));
511 samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks,
512 ARRAY_SIZE(exynos5250_fixed_factor_clks));
513 samsung_clk_register_mux(exynos5250_mux_clks,
514 ARRAY_SIZE(exynos5250_mux_clks));
515 samsung_clk_register_div(exynos5250_div_clks,
516 ARRAY_SIZE(exynos5250_div_clks));
517 samsung_clk_register_gate(exynos5250_gate_clks,
518 ARRAY_SIZE(exynos5250_gate_clks));
519
520 pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
521 _get_rate("armclk"));
522}
523CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
new file mode 100644
index 000000000000..a0a094c06f19
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -0,0 +1,139 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Author: Thomas Abraham <thomas.ab@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos5440 SoC.
10*/
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17
18#include <plat/cpu.h>
19#include "clk.h"
20#include "clk-pll.h"
21
22#define CLKEN_OV_VAL 0xf8
23#define CPU_CLK_STATUS 0xfc
24#define MISC_DOUT1 0x558
25
26/*
27 * Let each supported clock get a unique id. This id is used to lookup the clock
28 * for device tree based platforms.
29 */
30enum exynos5440_clks {
31 none, xtal, arm_clk,
32
33 spi_baud = 16, pb0_250, pr0_250, pr1_250, b_250, b_125, b_200, sata,
34 usb, gmac0, cs250, pb0_250_o, pr0_250_o, pr1_250_o, b_250_o, b_125_o,
35 b_200_o, sata_o, usb_o, gmac0_o, cs250_o,
36
37 nr_clks,
38};
39
40/* parent clock name list */
41PNAME(mout_armclk_p) = { "cplla", "cpllb" };
42PNAME(mout_spi_p) = { "div125", "div200" };
43
44/* fixed rate clocks generated outside the soc */
45struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
46 FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0),
47};
48
49/* fixed rate clocks */
50struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
51 FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000),
52 FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
53 FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
54 FRATE(none, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000),
55 FRATE(none, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000),
56};
57
58/* fixed factor clocks */
59struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
60 FFACTOR(none, "div250", "ppll", 1, 4, 0),
61 FFACTOR(none, "div200", "ppll", 1, 5, 0),
62 FFACTOR(none, "div125", "div250", 1, 2, 0),
63};
64
65/* mux clocks */
66struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
67 MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
68 MUX_A(arm_clk, "arm_clk", mout_armclk_p,
69 CPU_CLK_STATUS, 0, 1, "armclk"),
70};
71
72/* divider clocks */
73struct samsung_div_clock exynos5440_div_clks[] __initdata = {
74 DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
75};
76
77/* gate clocks */
78struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
79 GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
80 GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
81 GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
82 GATE(b_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
83 GATE(b_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
84 GATE(b_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
85 GATE(sata, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
86 GATE(usb, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
87 GATE(gmac0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
88 GATE(cs250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
89 GATE(pb0_250_o, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
90 GATE(pr0_250_o, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
91 GATE(pr1_250_o, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
92 GATE(b_250_o, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
93 GATE(b_125_o, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
94 GATE(b_200_o, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
95 GATE(sata_o, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
96 GATE(usb_o, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
97 GATE(gmac0_o, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
98 GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
99};
100
101static __initdata struct of_device_id ext_clk_match[] = {
102 { .compatible = "samsung,clock-xtal", .data = (void *)0, },
103 {},
104};
105
106/* register exynos5440 clocks */
107void __init exynos5440_clk_init(struct device_node *np)
108{
109 void __iomem *reg_base;
110
111 reg_base = of_iomap(np, 0);
112 if (!reg_base) {
113 pr_err("%s: failed to map clock controller registers,"
114 " aborting clock initialization\n", __func__);
115 return;
116 }
117
118 samsung_clk_init(np, reg_base, nr_clks, NULL, 0, NULL, 0);
119 samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
120 ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
121
122 samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10);
123 samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);
124
125 samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks,
126 ARRAY_SIZE(exynos5440_fixed_rate_clks));
127 samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks,
128 ARRAY_SIZE(exynos5440_fixed_factor_clks));
129 samsung_clk_register_mux(exynos5440_mux_clks,
130 ARRAY_SIZE(exynos5440_mux_clks));
131 samsung_clk_register_div(exynos5440_div_clks,
132 ARRAY_SIZE(exynos5440_div_clks));
133 samsung_clk_register_gate(exynos5440_gate_clks,
134 ARRAY_SIZE(exynos5440_gate_clks));
135
136 pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("armclk"));
137 pr_info("exynos5440 clock initialization complete\n");
138}
139CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init);
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
new file mode 100644
index 000000000000..89135f6be116
--- /dev/null
+++ b/drivers/clk/samsung/clk-pll.c
@@ -0,0 +1,419 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This file contains the utility functions to register the pll clocks.
10*/
11
12#include <linux/errno.h>
13#include "clk.h"
14#include "clk-pll.h"
15
16/*
17 * PLL35xx Clock Type
18 */
19
20#define PLL35XX_MDIV_MASK (0x3FF)
21#define PLL35XX_PDIV_MASK (0x3F)
22#define PLL35XX_SDIV_MASK (0x7)
23#define PLL35XX_MDIV_SHIFT (16)
24#define PLL35XX_PDIV_SHIFT (8)
25#define PLL35XX_SDIV_SHIFT (0)
26
27struct samsung_clk_pll35xx {
28 struct clk_hw hw;
29 const void __iomem *con_reg;
30};
31
32#define to_clk_pll35xx(_hw) container_of(_hw, struct samsung_clk_pll35xx, hw)
33
34static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
35 unsigned long parent_rate)
36{
37 struct samsung_clk_pll35xx *pll = to_clk_pll35xx(hw);
38 u32 mdiv, pdiv, sdiv, pll_con;
39 u64 fvco = parent_rate;
40
41 pll_con = __raw_readl(pll->con_reg);
42 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
43 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
44 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
45
46 fvco *= mdiv;
47 do_div(fvco, (pdiv << sdiv));
48
49 return (unsigned long)fvco;
50}
51
52static const struct clk_ops samsung_pll35xx_clk_ops = {
53 .recalc_rate = samsung_pll35xx_recalc_rate,
54};
55
56struct clk * __init samsung_clk_register_pll35xx(const char *name,
57 const char *pname, const void __iomem *con_reg)
58{
59 struct samsung_clk_pll35xx *pll;
60 struct clk *clk;
61 struct clk_init_data init;
62
63 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
64 if (!pll) {
65 pr_err("%s: could not allocate pll clk %s\n", __func__, name);
66 return NULL;
67 }
68
69 init.name = name;
70 init.ops = &samsung_pll35xx_clk_ops;
71 init.flags = CLK_GET_RATE_NOCACHE;
72 init.parent_names = &pname;
73 init.num_parents = 1;
74
75 pll->hw.init = &init;
76 pll->con_reg = con_reg;
77
78 clk = clk_register(NULL, &pll->hw);
79 if (IS_ERR(clk)) {
80 pr_err("%s: failed to register pll clock %s\n", __func__,
81 name);
82 kfree(pll);
83 }
84
85 if (clk_register_clkdev(clk, name, NULL))
86 pr_err("%s: failed to register lookup for %s", __func__, name);
87
88 return clk;
89}
90
91/*
92 * PLL36xx Clock Type
93 */
94
95#define PLL36XX_KDIV_MASK (0xFFFF)
96#define PLL36XX_MDIV_MASK (0x1FF)
97#define PLL36XX_PDIV_MASK (0x3F)
98#define PLL36XX_SDIV_MASK (0x7)
99#define PLL36XX_MDIV_SHIFT (16)
100#define PLL36XX_PDIV_SHIFT (8)
101#define PLL36XX_SDIV_SHIFT (0)
102
103struct samsung_clk_pll36xx {
104 struct clk_hw hw;
105 const void __iomem *con_reg;
106};
107
108#define to_clk_pll36xx(_hw) container_of(_hw, struct samsung_clk_pll36xx, hw)
109
110static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
111 unsigned long parent_rate)
112{
113 struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw);
114 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
115 u64 fvco = parent_rate;
116
117 pll_con0 = __raw_readl(pll->con_reg);
118 pll_con1 = __raw_readl(pll->con_reg + 4);
119 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
120 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
121 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
122 kdiv = pll_con1 & PLL36XX_KDIV_MASK;
123
124 fvco *= (mdiv << 16) + kdiv;
125 do_div(fvco, (pdiv << sdiv));
126 fvco >>= 16;
127
128 return (unsigned long)fvco;
129}
130
131static const struct clk_ops samsung_pll36xx_clk_ops = {
132 .recalc_rate = samsung_pll36xx_recalc_rate,
133};
134
135struct clk * __init samsung_clk_register_pll36xx(const char *name,
136 const char *pname, const void __iomem *con_reg)
137{
138 struct samsung_clk_pll36xx *pll;
139 struct clk *clk;
140 struct clk_init_data init;
141
142 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
143 if (!pll) {
144 pr_err("%s: could not allocate pll clk %s\n", __func__, name);
145 return NULL;
146 }
147
148 init.name = name;
149 init.ops = &samsung_pll36xx_clk_ops;
150 init.flags = CLK_GET_RATE_NOCACHE;
151 init.parent_names = &pname;
152 init.num_parents = 1;
153
154 pll->hw.init = &init;
155 pll->con_reg = con_reg;
156
157 clk = clk_register(NULL, &pll->hw);
158 if (IS_ERR(clk)) {
159 pr_err("%s: failed to register pll clock %s\n", __func__,
160 name);
161 kfree(pll);
162 }
163
164 if (clk_register_clkdev(clk, name, NULL))
165 pr_err("%s: failed to register lookup for %s", __func__, name);
166
167 return clk;
168}
169
170/*
171 * PLL45xx Clock Type
172 */
173
174#define PLL45XX_MDIV_MASK (0x3FF)
175#define PLL45XX_PDIV_MASK (0x3F)
176#define PLL45XX_SDIV_MASK (0x7)
177#define PLL45XX_MDIV_SHIFT (16)
178#define PLL45XX_PDIV_SHIFT (8)
179#define PLL45XX_SDIV_SHIFT (0)
180
181struct samsung_clk_pll45xx {
182 struct clk_hw hw;
183 enum pll45xx_type type;
184 const void __iomem *con_reg;
185};
186
187#define to_clk_pll45xx(_hw) container_of(_hw, struct samsung_clk_pll45xx, hw)
188
189static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
190 unsigned long parent_rate)
191{
192 struct samsung_clk_pll45xx *pll = to_clk_pll45xx(hw);
193 u32 mdiv, pdiv, sdiv, pll_con;
194 u64 fvco = parent_rate;
195
196 pll_con = __raw_readl(pll->con_reg);
197 mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
198 pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
199 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
200
201 if (pll->type == pll_4508)
202 sdiv = sdiv - 1;
203
204 fvco *= mdiv;
205 do_div(fvco, (pdiv << sdiv));
206
207 return (unsigned long)fvco;
208}
209
210static const struct clk_ops samsung_pll45xx_clk_ops = {
211 .recalc_rate = samsung_pll45xx_recalc_rate,
212};
213
214struct clk * __init samsung_clk_register_pll45xx(const char *name,
215 const char *pname, const void __iomem *con_reg,
216 enum pll45xx_type type)
217{
218 struct samsung_clk_pll45xx *pll;
219 struct clk *clk;
220 struct clk_init_data init;
221
222 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
223 if (!pll) {
224 pr_err("%s: could not allocate pll clk %s\n", __func__, name);
225 return NULL;
226 }
227
228 init.name = name;
229 init.ops = &samsung_pll45xx_clk_ops;
230 init.flags = CLK_GET_RATE_NOCACHE;
231 init.parent_names = &pname;
232 init.num_parents = 1;
233
234 pll->hw.init = &init;
235 pll->con_reg = con_reg;
236 pll->type = type;
237
238 clk = clk_register(NULL, &pll->hw);
239 if (IS_ERR(clk)) {
240 pr_err("%s: failed to register pll clock %s\n", __func__,
241 name);
242 kfree(pll);
243 }
244
245 if (clk_register_clkdev(clk, name, NULL))
246 pr_err("%s: failed to register lookup for %s", __func__, name);
247
248 return clk;
249}
250
251/*
252 * PLL46xx Clock Type
253 */
254
255#define PLL46XX_MDIV_MASK (0x1FF)
256#define PLL46XX_PDIV_MASK (0x3F)
257#define PLL46XX_SDIV_MASK (0x7)
258#define PLL46XX_MDIV_SHIFT (16)
259#define PLL46XX_PDIV_SHIFT (8)
260#define PLL46XX_SDIV_SHIFT (0)
261
262#define PLL46XX_KDIV_MASK (0xFFFF)
263#define PLL4650C_KDIV_MASK (0xFFF)
264#define PLL46XX_KDIV_SHIFT (0)
265
266struct samsung_clk_pll46xx {
267 struct clk_hw hw;
268 enum pll46xx_type type;
269 const void __iomem *con_reg;
270};
271
272#define to_clk_pll46xx(_hw) container_of(_hw, struct samsung_clk_pll46xx, hw)
273
274static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
275 unsigned long parent_rate)
276{
277 struct samsung_clk_pll46xx *pll = to_clk_pll46xx(hw);
278 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
279 u64 fvco = parent_rate;
280
281 pll_con0 = __raw_readl(pll->con_reg);
282 pll_con1 = __raw_readl(pll->con_reg + 4);
283 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
284 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
285 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
286 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
287 pll_con1 & PLL46XX_KDIV_MASK;
288
289 shift = pll->type == pll_4600 ? 16 : 10;
290 fvco *= (mdiv << shift) + kdiv;
291 do_div(fvco, (pdiv << sdiv));
292 fvco >>= shift;
293
294 return (unsigned long)fvco;
295}
296
297static const struct clk_ops samsung_pll46xx_clk_ops = {
298 .recalc_rate = samsung_pll46xx_recalc_rate,
299};
300
301struct clk * __init samsung_clk_register_pll46xx(const char *name,
302 const char *pname, const void __iomem *con_reg,
303 enum pll46xx_type type)
304{
305 struct samsung_clk_pll46xx *pll;
306 struct clk *clk;
307 struct clk_init_data init;
308
309 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
310 if (!pll) {
311 pr_err("%s: could not allocate pll clk %s\n", __func__, name);
312 return NULL;
313 }
314
315 init.name = name;
316 init.ops = &samsung_pll46xx_clk_ops;
317 init.flags = CLK_GET_RATE_NOCACHE;
318 init.parent_names = &pname;
319 init.num_parents = 1;
320
321 pll->hw.init = &init;
322 pll->con_reg = con_reg;
323 pll->type = type;
324
325 clk = clk_register(NULL, &pll->hw);
326 if (IS_ERR(clk)) {
327 pr_err("%s: failed to register pll clock %s\n", __func__,
328 name);
329 kfree(pll);
330 }
331
332 if (clk_register_clkdev(clk, name, NULL))
333 pr_err("%s: failed to register lookup for %s", __func__, name);
334
335 return clk;
336}
337
338/*
339 * PLL2550x Clock Type
340 */
341
342#define PLL2550X_R_MASK (0x1)
343#define PLL2550X_P_MASK (0x3F)
344#define PLL2550X_M_MASK (0x3FF)
345#define PLL2550X_S_MASK (0x7)
346#define PLL2550X_R_SHIFT (20)
347#define PLL2550X_P_SHIFT (14)
348#define PLL2550X_M_SHIFT (4)
349#define PLL2550X_S_SHIFT (0)
350
351struct samsung_clk_pll2550x {
352 struct clk_hw hw;
353 const void __iomem *reg_base;
354 unsigned long offset;
355};
356
357#define to_clk_pll2550x(_hw) container_of(_hw, struct samsung_clk_pll2550x, hw)
358
359static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
360 unsigned long parent_rate)
361{
362 struct samsung_clk_pll2550x *pll = to_clk_pll2550x(hw);
363 u32 r, p, m, s, pll_stat;
364 u64 fvco = parent_rate;
365
366 pll_stat = __raw_readl(pll->reg_base + pll->offset * 3);
367 r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
368 if (!r)
369 return 0;
370 p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK;
371 m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK;
372 s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK;
373
374 fvco *= m;
375 do_div(fvco, (p << s));
376
377 return (unsigned long)fvco;
378}
379
380static const struct clk_ops samsung_pll2550x_clk_ops = {
381 .recalc_rate = samsung_pll2550x_recalc_rate,
382};
383
384struct clk * __init samsung_clk_register_pll2550x(const char *name,
385 const char *pname, const void __iomem *reg_base,
386 const unsigned long offset)
387{
388 struct samsung_clk_pll2550x *pll;
389 struct clk *clk;
390 struct clk_init_data init;
391
392 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
393 if (!pll) {
394 pr_err("%s: could not allocate pll clk %s\n", __func__, name);
395 return NULL;
396 }
397
398 init.name = name;
399 init.ops = &samsung_pll2550x_clk_ops;
400 init.flags = CLK_GET_RATE_NOCACHE;
401 init.parent_names = &pname;
402 init.num_parents = 1;
403
404 pll->hw.init = &init;
405 pll->reg_base = reg_base;
406 pll->offset = offset;
407
408 clk = clk_register(NULL, &pll->hw);
409 if (IS_ERR(clk)) {
410 pr_err("%s: failed to register pll clock %s\n", __func__,
411 name);
412 kfree(pll);
413 }
414
415 if (clk_register_clkdev(clk, name, NULL))
416 pr_err("%s: failed to register lookup for %s", __func__, name);
417
418 return clk;
419}
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
new file mode 100644
index 000000000000..f33786e9a78b
--- /dev/null
+++ b/drivers/clk/samsung/clk-pll.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for all PLL's in Samsung platforms
10*/
11
12#ifndef __SAMSUNG_CLK_PLL_H
13#define __SAMSUNG_CLK_PLL_H
14
15enum pll45xx_type {
16 pll_4500,
17 pll_4502,
18 pll_4508
19};
20
21enum pll46xx_type {
22 pll_4600,
23 pll_4650,
24 pll_4650c,
25};
26
27extern struct clk * __init samsung_clk_register_pll35xx(const char *name,
28 const char *pname, const void __iomem *con_reg);
29extern struct clk * __init samsung_clk_register_pll36xx(const char *name,
30 const char *pname, const void __iomem *con_reg);
31extern struct clk * __init samsung_clk_register_pll45xx(const char *name,
32 const char *pname, const void __iomem *con_reg,
33 enum pll45xx_type type);
34extern struct clk * __init samsung_clk_register_pll46xx(const char *name,
35 const char *pname, const void __iomem *con_reg,
36 enum pll46xx_type type);
37extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
38 const char *pname, const void __iomem *reg_base,
39 const unsigned long offset);
40
41#endif /* __SAMSUNG_CLK_PLL_H */
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
new file mode 100644
index 000000000000..cd3c40ab50f3
--- /dev/null
+++ b/drivers/clk/samsung/clk.c
@@ -0,0 +1,320 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This file includes utility functions to register clocks to common
11 * clock framework for Samsung platforms.
12*/
13
14#include <linux/syscore_ops.h>
15#include "clk.h"
16
17static DEFINE_SPINLOCK(lock);
18static struct clk **clk_table;
19static void __iomem *reg_base;
20#ifdef CONFIG_OF
21static struct clk_onecell_data clk_data;
22#endif
23
24#ifdef CONFIG_PM_SLEEP
25static struct samsung_clk_reg_dump *reg_dump;
26static unsigned long nr_reg_dump;
27
28static int samsung_clk_suspend(void)
29{
30 struct samsung_clk_reg_dump *rd = reg_dump;
31 unsigned long i;
32
33 for (i = 0; i < nr_reg_dump; i++, rd++)
34 rd->value = __raw_readl(reg_base + rd->offset);
35
36 return 0;
37}
38
39static void samsung_clk_resume(void)
40{
41 struct samsung_clk_reg_dump *rd = reg_dump;
42 unsigned long i;
43
44 for (i = 0; i < nr_reg_dump; i++, rd++)
45 __raw_writel(rd->value, reg_base + rd->offset);
46}
47
48static struct syscore_ops samsung_clk_syscore_ops = {
49 .suspend = samsung_clk_suspend,
50 .resume = samsung_clk_resume,
51};
52#endif /* CONFIG_PM_SLEEP */
53
54/* setup the essentials required to support clock lookup using ccf */
55void __init samsung_clk_init(struct device_node *np, void __iomem *base,
56 unsigned long nr_clks, unsigned long *rdump,
57 unsigned long nr_rdump, unsigned long *soc_rdump,
58 unsigned long nr_soc_rdump)
59{
60 reg_base = base;
61
62#ifdef CONFIG_PM_SLEEP
63 if (rdump && nr_rdump) {
64 unsigned int idx;
65 reg_dump = kzalloc(sizeof(struct samsung_clk_reg_dump)
66 * (nr_rdump + nr_soc_rdump), GFP_KERNEL);
67 if (!reg_dump) {
68 pr_err("%s: memory alloc for register dump failed\n",
69 __func__);
70 return;
71 }
72
73 for (idx = 0; idx < nr_rdump; idx++)
74 reg_dump[idx].offset = rdump[idx];
75 for (idx = 0; idx < nr_soc_rdump; idx++)
76 reg_dump[nr_rdump + idx].offset = soc_rdump[idx];
77 nr_reg_dump = nr_rdump + nr_soc_rdump;
78 register_syscore_ops(&samsung_clk_syscore_ops);
79 }
80#endif
81
82 clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
83 if (!clk_table)
84 panic("could not allocate clock lookup table\n");
85
86 if (!np)
87 return;
88
89#ifdef CONFIG_OF
90 clk_data.clks = clk_table;
91 clk_data.clk_num = nr_clks;
92 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
93#endif
94}
95
96/* add a clock instance to the clock lookup table used for dt based lookup */
97void samsung_clk_add_lookup(struct clk *clk, unsigned int id)
98{
99 if (clk_table && id)
100 clk_table[id] = clk;
101}
102
103/* register a list of aliases */
104void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
105 unsigned int nr_clk)
106{
107 struct clk *clk;
108 unsigned int idx, ret;
109
110 if (!clk_table) {
111 pr_err("%s: clock table missing\n", __func__);
112 return;
113 }
114
115 for (idx = 0; idx < nr_clk; idx++, list++) {
116 if (!list->id) {
117 pr_err("%s: clock id missing for index %d\n", __func__,
118 idx);
119 continue;
120 }
121
122 clk = clk_table[list->id];
123 if (!clk) {
124 pr_err("%s: failed to find clock %d\n", __func__,
125 list->id);
126 continue;
127 }
128
129 ret = clk_register_clkdev(clk, list->alias, list->dev_name);
130 if (ret)
131 pr_err("%s: failed to register lookup %s\n",
132 __func__, list->alias);
133 }
134}
135
136/* register a list of fixed clocks */
137void __init samsung_clk_register_fixed_rate(
138 struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
139{
140 struct clk *clk;
141 unsigned int idx, ret;
142
143 for (idx = 0; idx < nr_clk; idx++, list++) {
144 clk = clk_register_fixed_rate(NULL, list->name,
145 list->parent_name, list->flags, list->fixed_rate);
146 if (IS_ERR(clk)) {
147 pr_err("%s: failed to register clock %s\n", __func__,
148 list->name);
149 continue;
150 }
151
152 samsung_clk_add_lookup(clk, list->id);
153
154 /*
155 * Unconditionally add a clock lookup for the fixed rate clocks.
156 * There are not many of these on any of Samsung platforms.
157 */
158 ret = clk_register_clkdev(clk, list->name, NULL);
159 if (ret)
160 pr_err("%s: failed to register clock lookup for %s",
161 __func__, list->name);
162 }
163}
164
165/* register a list of fixed factor clocks */
166void __init samsung_clk_register_fixed_factor(
167 struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
168{
169 struct clk *clk;
170 unsigned int idx;
171
172 for (idx = 0; idx < nr_clk; idx++, list++) {
173 clk = clk_register_fixed_factor(NULL, list->name,
174 list->parent_name, list->flags, list->mult, list->div);
175 if (IS_ERR(clk)) {
176 pr_err("%s: failed to register clock %s\n", __func__,
177 list->name);
178 continue;
179 }
180
181 samsung_clk_add_lookup(clk, list->id);
182 }
183}
184
185/* register a list of mux clocks */
186void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
187 unsigned int nr_clk)
188{
189 struct clk *clk;
190 unsigned int idx, ret;
191
192 for (idx = 0; idx < nr_clk; idx++, list++) {
193 clk = clk_register_mux(NULL, list->name, list->parent_names,
194 list->num_parents, list->flags, reg_base + list->offset,
195 list->shift, list->width, list->mux_flags, &lock);
196 if (IS_ERR(clk)) {
197 pr_err("%s: failed to register clock %s\n", __func__,
198 list->name);
199 continue;
200 }
201
202 samsung_clk_add_lookup(clk, list->id);
203
204 /* register a clock lookup only if a clock alias is specified */
205 if (list->alias) {
206 ret = clk_register_clkdev(clk, list->alias,
207 list->dev_name);
208 if (ret)
209 pr_err("%s: failed to register lookup %s\n",
210 __func__, list->alias);
211 }
212 }
213}
214
215/* register a list of div clocks */
216void __init samsung_clk_register_div(struct samsung_div_clock *list,
217 unsigned int nr_clk)
218{
219 struct clk *clk;
220 unsigned int idx, ret;
221
222 for (idx = 0; idx < nr_clk; idx++, list++) {
223 if (list->table)
224 clk = clk_register_divider_table(NULL, list->name,
225 list->parent_name, list->flags,
226 reg_base + list->offset, list->shift,
227 list->width, list->div_flags,
228 list->table, &lock);
229 else
230 clk = clk_register_divider(NULL, list->name,
231 list->parent_name, list->flags,
232 reg_base + list->offset, list->shift,
233 list->width, list->div_flags, &lock);
234 if (IS_ERR(clk)) {
235 pr_err("%s: failed to register clock %s\n", __func__,
236 list->name);
237 continue;
238 }
239
240 samsung_clk_add_lookup(clk, list->id);
241
242 /* register a clock lookup only if a clock alias is specified */
243 if (list->alias) {
244 ret = clk_register_clkdev(clk, list->alias,
245 list->dev_name);
246 if (ret)
247 pr_err("%s: failed to register lookup %s\n",
248 __func__, list->alias);
249 }
250 }
251}
252
253/* register a list of gate clocks */
254void __init samsung_clk_register_gate(struct samsung_gate_clock *list,
255 unsigned int nr_clk)
256{
257 struct clk *clk;
258 unsigned int idx, ret;
259
260 for (idx = 0; idx < nr_clk; idx++, list++) {
261 clk = clk_register_gate(NULL, list->name, list->parent_name,
262 list->flags, reg_base + list->offset,
263 list->bit_idx, list->gate_flags, &lock);
264 if (IS_ERR(clk)) {
265 pr_err("%s: failed to register clock %s\n", __func__,
266 list->name);
267 continue;
268 }
269
270 /* register a clock lookup only if a clock alias is specified */
271 if (list->alias) {
272 ret = clk_register_clkdev(clk, list->alias,
273 list->dev_name);
274 if (ret)
275 pr_err("%s: failed to register lookup %s\n",
276 __func__, list->alias);
277 }
278
279 samsung_clk_add_lookup(clk, list->id);
280 }
281}
282
283/*
284 * obtain the clock speed of all external fixed clock sources from device
285 * tree and register it
286 */
287#ifdef CONFIG_OF
288void __init samsung_clk_of_register_fixed_ext(
289 struct samsung_fixed_rate_clock *fixed_rate_clk,
290 unsigned int nr_fixed_rate_clk,
291 struct of_device_id *clk_matches)
292{
293 const struct of_device_id *match;
294 struct device_node *np;
295 u32 freq;
296
297 for_each_matching_node_and_match(np, clk_matches, &match) {
298 if (of_property_read_u32(np, "clock-frequency", &freq))
299 continue;
300 fixed_rate_clk[(u32)match->data].fixed_rate = freq;
301 }
302 samsung_clk_register_fixed_rate(fixed_rate_clk, nr_fixed_rate_clk);
303}
304#endif
305
306/* utility function to get the rate of a specified clock */
307unsigned long _get_rate(const char *clk_name)
308{
309 struct clk *clk;
310 unsigned long rate;
311
312 clk = clk_get(NULL, clk_name);
313 if (IS_ERR(clk)) {
314 pr_err("%s: could not find clock %s\n", __func__, clk_name);
315 return 0;
316 }
317 rate = clk_get_rate(clk);
318 clk_put(clk);
319 return rate;
320}
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
new file mode 100644
index 000000000000..10b2111f0c0f
--- /dev/null
+++ b/drivers/clk/samsung/clk.h
@@ -0,0 +1,289 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for all Samsung platforms
11*/
12
13#ifndef __SAMSUNG_CLK_H
14#define __SAMSUNG_CLK_H
15
16#include <linux/clk.h>
17#include <linux/clkdev.h>
18#include <linux/io.h>
19#include <linux/clk-provider.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22
23#include <mach/map.h>
24
25/**
26 * struct samsung_clock_alias: information about mux clock
27 * @id: platform specific id of the clock.
28 * @dev_name: name of the device to which this clock belongs.
29 * @alias: optional clock alias name to be assigned to this clock.
30 */
31struct samsung_clock_alias {
32 unsigned int id;
33 const char *dev_name;
34 const char *alias;
35};
36
37#define ALIAS(_id, dname, a) \
38 { \
39 .id = _id, \
40 .dev_name = dname, \
41 .alias = a, \
42 }
43
44/**
45 * struct samsung_fixed_rate_clock: information about fixed-rate clock
46 * @id: platform specific id of the clock.
47 * @name: name of this fixed-rate clock.
48 * @parent_name: optional parent clock name.
49 * @flags: optional fixed-rate clock flags.
50 * @fixed-rate: fixed clock rate of this clock.
51 */
52struct samsung_fixed_rate_clock {
53 unsigned int id;
54 char *name;
55 const char *parent_name;
56 unsigned long flags;
57 unsigned long fixed_rate;
58};
59
60#define FRATE(_id, cname, pname, f, frate) \
61 { \
62 .id = _id, \
63 .name = cname, \
64 .parent_name = pname, \
65 .flags = f, \
66 .fixed_rate = frate, \
67 }
68
69/*
70 * struct samsung_fixed_factor_clock: information about fixed-factor clock
71 * @id: platform specific id of the clock.
72 * @name: name of this fixed-factor clock.
73 * @parent_name: parent clock name.
74 * @mult: fixed multiplication factor.
75 * @div: fixed division factor.
76 * @flags: optional fixed-factor clock flags.
77 */
78struct samsung_fixed_factor_clock {
79 unsigned int id;
80 char *name;
81 const char *parent_name;
82 unsigned long mult;
83 unsigned long div;
84 unsigned long flags;
85};
86
87#define FFACTOR(_id, cname, pname, m, d, f) \
88 { \
89 .id = _id, \
90 .name = cname, \
91 .parent_name = pname, \
92 .mult = m, \
93 .div = d, \
94 .flags = f, \
95 }
96
97/**
98 * struct samsung_mux_clock: information about mux clock
99 * @id: platform specific id of the clock.
100 * @dev_name: name of the device to which this clock belongs.
101 * @name: name of this mux clock.
102 * @parent_names: array of pointer to parent clock names.
103 * @num_parents: number of parents listed in @parent_names.
104 * @flags: optional flags for basic clock.
105 * @offset: offset of the register for configuring the mux.
106 * @shift: starting bit location of the mux control bit-field in @reg.
107 * @width: width of the mux control bit-field in @reg.
108 * @mux_flags: flags for mux-type clock.
109 * @alias: optional clock alias name to be assigned to this clock.
110 */
111struct samsung_mux_clock {
112 unsigned int id;
113 const char *dev_name;
114 const char *name;
115 const char **parent_names;
116 u8 num_parents;
117 unsigned long flags;
118 unsigned long offset;
119 u8 shift;
120 u8 width;
121 u8 mux_flags;
122 const char *alias;
123};
124
125#define __MUX(_id, dname, cname, pnames, o, s, w, f, mf, a) \
126 { \
127 .id = _id, \
128 .dev_name = dname, \
129 .name = cname, \
130 .parent_names = pnames, \
131 .num_parents = ARRAY_SIZE(pnames), \
132 .flags = f, \
133 .offset = o, \
134 .shift = s, \
135 .width = w, \
136 .mux_flags = mf, \
137 .alias = a, \
138 }
139
140#define MUX(_id, cname, pnames, o, s, w) \
141 __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, NULL)
142
143#define MUX_A(_id, cname, pnames, o, s, w, a) \
144 __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, a)
145
146#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
147 __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, NULL)
148
149/**
150 * @id: platform specific id of the clock.
151 * struct samsung_div_clock: information about div clock
152 * @dev_name: name of the device to which this clock belongs.
153 * @name: name of this div clock.
154 * @parent_name: name of the parent clock.
155 * @flags: optional flags for basic clock.
156 * @offset: offset of the register for configuring the div.
157 * @shift: starting bit location of the div control bit-field in @reg.
158 * @div_flags: flags for div-type clock.
159 * @alias: optional clock alias name to be assigned to this clock.
160 */
161struct samsung_div_clock {
162 unsigned int id;
163 const char *dev_name;
164 const char *name;
165 const char *parent_name;
166 unsigned long flags;
167 unsigned long offset;
168 u8 shift;
169 u8 width;
170 u8 div_flags;
171 const char *alias;
172 struct clk_div_table *table;
173};
174
175#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a, t) \
176 { \
177 .id = _id, \
178 .dev_name = dname, \
179 .name = cname, \
180 .parent_name = pname, \
181 .flags = f, \
182 .offset = o, \
183 .shift = s, \
184 .width = w, \
185 .div_flags = df, \
186 .alias = a, \
187 .table = t, \
188 }
189
190#define DIV(_id, cname, pname, o, s, w) \
191 __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, NULL)
192
193#define DIV_A(_id, cname, pname, o, s, w, a) \
194 __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a, NULL)
195
196#define DIV_F(_id, cname, pname, o, s, w, f, df) \
197 __DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL, NULL)
198
199#define DIV_T(_id, cname, pname, o, s, w, t) \
200 __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, t)
201
202/**
203 * struct samsung_gate_clock: information about gate clock
204 * @id: platform specific id of the clock.
205 * @dev_name: name of the device to which this clock belongs.
206 * @name: name of this gate clock.
207 * @parent_name: name of the parent clock.
208 * @flags: optional flags for basic clock.
209 * @offset: offset of the register for configuring the gate.
210 * @bit_idx: bit index of the gate control bit-field in @reg.
211 * @gate_flags: flags for gate-type clock.
212 * @alias: optional clock alias name to be assigned to this clock.
213 */
214struct samsung_gate_clock {
215 unsigned int id;
216 const char *dev_name;
217 const char *name;
218 const char *parent_name;
219 unsigned long flags;
220 unsigned long offset;
221 u8 bit_idx;
222 u8 gate_flags;
223 const char *alias;
224};
225
226#define __GATE(_id, dname, cname, pname, o, b, f, gf, a) \
227 { \
228 .id = _id, \
229 .dev_name = dname, \
230 .name = cname, \
231 .parent_name = pname, \
232 .flags = f, \
233 .offset = o, \
234 .bit_idx = b, \
235 .gate_flags = gf, \
236 .alias = a, \
237 }
238
239#define GATE(_id, cname, pname, o, b, f, gf) \
240 __GATE(_id, NULL, cname, pname, o, b, f, gf, NULL)
241
242#define GATE_A(_id, cname, pname, o, b, f, gf, a) \
243 __GATE(_id, NULL, cname, pname, o, b, f, gf, a)
244
245#define GATE_D(_id, dname, cname, pname, o, b, f, gf) \
246 __GATE(_id, dname, cname, pname, o, b, f, gf, NULL)
247
248#define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a) \
249 __GATE(_id, dname, cname, pname, o, b, f, gf, a)
250
251#define PNAME(x) static const char *x[] __initdata
252
253/**
254 * struct samsung_clk_reg_dump: register dump of clock controller registers.
255 * @offset: clock register offset from the controller base address.
256 * @value: the value to be register at offset.
257 */
258struct samsung_clk_reg_dump {
259 u32 offset;
260 u32 value;
261};
262
263extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
264 unsigned long nr_clks, unsigned long *rdump,
265 unsigned long nr_rdump, unsigned long *soc_rdump,
266 unsigned long nr_soc_rdump);
267extern void __init samsung_clk_of_register_fixed_ext(
268 struct samsung_fixed_rate_clock *fixed_rate_clk,
269 unsigned int nr_fixed_rate_clk,
270 struct of_device_id *clk_matches);
271
272extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
273
274extern void samsung_clk_register_alias(struct samsung_clock_alias *list,
275 unsigned int nr_clk);
276extern void __init samsung_clk_register_fixed_rate(
277 struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk);
278extern void __init samsung_clk_register_fixed_factor(
279 struct samsung_fixed_factor_clock *list, unsigned int nr_clk);
280extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list,
281 unsigned int nr_clk);
282extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list,
283 unsigned int nr_clk);
284extern void __init samsung_clk_register_gate(
285 struct samsung_gate_clock *clk_list, unsigned int nr_clk);
286
287extern unsigned long _get_rate(const char *clk_name);
288
289#endif /* __SAMSUNG_CLK_H */
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index 2b41b0f4f731..f49fac2d193a 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -9,3 +9,4 @@ obj-y += clk-super.o
9 9
10obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o 10obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
11obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o 11obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
12obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index 6dd533251e7b..bafee9895a24 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -41,7 +41,9 @@ static DEFINE_SPINLOCK(periph_ref_lock);
41#define write_rst_clr(val, gate) \ 41#define write_rst_clr(val, gate) \
42 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg)) 42 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
43 43
44#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32)) 44#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
45
46#define LVL2_CLK_GATE_OVRE 0x554
45 47
46/* Peripheral gate clock ops */ 48/* Peripheral gate clock ops */
47static int clk_periph_is_enabled(struct clk_hw *hw) 49static int clk_periph_is_enabled(struct clk_hw *hw)
@@ -83,6 +85,13 @@ static int clk_periph_enable(struct clk_hw *hw)
83 } 85 }
84 } 86 }
85 87
88 if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
89 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
90 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
91 udelay(1);
92 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
93 }
94
86 spin_unlock_irqrestore(&periph_ref_lock, flags); 95 spin_unlock_irqrestore(&periph_ref_lock, flags);
87 96
88 return 0; 97 return 0;
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index 788486e6331a..b2309d37a963 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -16,6 +16,7 @@
16 16
17#include <linux/clk.h> 17#include <linux/clk.h>
18#include <linux/clk-provider.h> 18#include <linux/clk-provider.h>
19#include <linux/export.h>
19#include <linux/slab.h> 20#include <linux/slab.h>
20#include <linux/err.h> 21#include <linux/err.h>
21 22
@@ -128,6 +129,7 @@ void tegra_periph_reset_deassert(struct clk *c)
128 129
129 tegra_periph_reset(gate, 0); 130 tegra_periph_reset(gate, 0);
130} 131}
132EXPORT_SYMBOL(tegra_periph_reset_deassert);
131 133
132void tegra_periph_reset_assert(struct clk *c) 134void tegra_periph_reset_assert(struct clk *c)
133{ 135{
@@ -147,6 +149,7 @@ void tegra_periph_reset_assert(struct clk *c)
147 149
148 tegra_periph_reset(gate, 1); 150 tegra_periph_reset(gate, 1);
149} 151}
152EXPORT_SYMBOL(tegra_periph_reset_assert);
150 153
151const struct clk_ops tegra_clk_periph_ops = { 154const struct clk_ops tegra_clk_periph_ops = {
152 .get_parent = clk_periph_get_parent, 155 .get_parent = clk_periph_get_parent,
@@ -170,14 +173,15 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = {
170static struct clk *_tegra_clk_register_periph(const char *name, 173static struct clk *_tegra_clk_register_periph(const char *name,
171 const char **parent_names, int num_parents, 174 const char **parent_names, int num_parents,
172 struct tegra_clk_periph *periph, 175 struct tegra_clk_periph *periph,
173 void __iomem *clk_base, u32 offset, bool div) 176 void __iomem *clk_base, u32 offset, bool div,
177 unsigned long flags)
174{ 178{
175 struct clk *clk; 179 struct clk *clk;
176 struct clk_init_data init; 180 struct clk_init_data init;
177 181
178 init.name = name; 182 init.name = name;
179 init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops; 183 init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
180 init.flags = div ? 0 : CLK_SET_RATE_PARENT; 184 init.flags = flags;
181 init.parent_names = parent_names; 185 init.parent_names = parent_names;
182 init.num_parents = num_parents; 186 init.num_parents = num_parents;
183 187
@@ -202,10 +206,10 @@ static struct clk *_tegra_clk_register_periph(const char *name,
202struct clk *tegra_clk_register_periph(const char *name, 206struct clk *tegra_clk_register_periph(const char *name,
203 const char **parent_names, int num_parents, 207 const char **parent_names, int num_parents,
204 struct tegra_clk_periph *periph, void __iomem *clk_base, 208 struct tegra_clk_periph *periph, void __iomem *clk_base,
205 u32 offset) 209 u32 offset, unsigned long flags)
206{ 210{
207 return _tegra_clk_register_periph(name, parent_names, num_parents, 211 return _tegra_clk_register_periph(name, parent_names, num_parents,
208 periph, clk_base, offset, true); 212 periph, clk_base, offset, true, flags);
209} 213}
210 214
211struct clk *tegra_clk_register_periph_nodiv(const char *name, 215struct clk *tegra_clk_register_periph_nodiv(const char *name,
@@ -214,5 +218,5 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
214 u32 offset) 218 u32 offset)
215{ 219{
216 return _tegra_clk_register_periph(name, parent_names, num_parents, 220 return _tegra_clk_register_periph(name, parent_names, num_parents,
217 periph, clk_base, offset, false); 221 periph, clk_base, offset, false, CLK_SET_RATE_PARENT);
218} 222}
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 165f24734c1b..17c2cc086eb4 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -79,6 +79,48 @@
79#define PLLE_SS_CTRL 0x68 79#define PLLE_SS_CTRL 0x68
80#define PLLE_SS_DISABLE (7 << 10) 80#define PLLE_SS_DISABLE (7 << 10)
81 81
82#define PLLE_AUX_PLLP_SEL BIT(2)
83#define PLLE_AUX_ENABLE_SWCTL BIT(4)
84#define PLLE_AUX_SEQ_ENABLE BIT(24)
85#define PLLE_AUX_PLLRE_SEL BIT(28)
86
87#define PLLE_MISC_PLLE_PTS BIT(8)
88#define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
89#define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
90#define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
91#define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
92#define PLLE_MISC_VREG_CTRL_SHIFT 2
93#define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
94
95#define PLLCX_MISC_STROBE BIT(31)
96#define PLLCX_MISC_RESET BIT(30)
97#define PLLCX_MISC_SDM_DIV_SHIFT 28
98#define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
99#define PLLCX_MISC_FILT_DIV_SHIFT 26
100#define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
101#define PLLCX_MISC_ALPHA_SHIFT 18
102#define PLLCX_MISC_DIV_LOW_RANGE \
103 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
104 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
105#define PLLCX_MISC_DIV_HIGH_RANGE \
106 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
107 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
108#define PLLCX_MISC_COEF_LOW_RANGE \
109 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
110#define PLLCX_MISC_KA_SHIFT 2
111#define PLLCX_MISC_KB_SHIFT 9
112#define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
113 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
114 PLLCX_MISC_DIV_LOW_RANGE | \
115 PLLCX_MISC_RESET)
116#define PLLCX_MISC1_DEFAULT 0x000d2308
117#define PLLCX_MISC2_DEFAULT 0x30211200
118#define PLLCX_MISC3_DEFAULT 0x200
119
120#define PMC_PLLM_WB0_OVERRIDE 0x1dc
121#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
122#define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK BIT(27)
123
82#define PMC_SATA_PWRGT 0x1ac 124#define PMC_SATA_PWRGT 0x1ac
83#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) 125#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
84#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) 126#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
@@ -101,6 +143,24 @@
101#define divn_max(p) (divn_mask(p)) 143#define divn_max(p) (divn_mask(p))
102#define divp_max(p) (1 << (divp_mask(p))) 144#define divp_max(p) (1 << (divp_mask(p)))
103 145
146
147#ifdef CONFIG_ARCH_TEGRA_114_SOC
148/* PLLXC has 4-bit PDIV, but entry 15 is not allowed in h/w */
149#define PLLXC_PDIV_MAX 14
150
151/* non-monotonic mapping below is not a typo */
152static u8 pllxc_p[PLLXC_PDIV_MAX + 1] = {
153 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
154 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32
155};
156
157#define PLLCX_PDIV_MAX 7
158static u8 pllcx_p[PLLCX_PDIV_MAX + 1] = {
159 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7 */
160 /* p: */ 1, 2, 3, 4, 6, 8, 12, 16
161};
162#endif
163
104static void clk_pll_enable_lock(struct tegra_clk_pll *pll) 164static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
105{ 165{
106 u32 val; 166 u32 val;
@@ -108,25 +168,36 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
108 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) 168 if (!(pll->flags & TEGRA_PLL_USE_LOCK))
109 return; 169 return;
110 170
171 if (!(pll->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
172 return;
173
111 val = pll_readl_misc(pll); 174 val = pll_readl_misc(pll);
112 val |= BIT(pll->params->lock_enable_bit_idx); 175 val |= BIT(pll->params->lock_enable_bit_idx);
113 pll_writel_misc(val, pll); 176 pll_writel_misc(val, pll);
114} 177}
115 178
116static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll, 179static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
117 void __iomem *lock_addr, u32 lock_bit_idx)
118{ 180{
119 int i; 181 int i;
120 u32 val; 182 u32 val, lock_mask;
183 void __iomem *lock_addr;
121 184
122 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) { 185 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
123 udelay(pll->params->lock_delay); 186 udelay(pll->params->lock_delay);
124 return 0; 187 return 0;
125 } 188 }
126 189
190 lock_addr = pll->clk_base;
191 if (pll->flags & TEGRA_PLL_LOCK_MISC)
192 lock_addr += pll->params->misc_reg;
193 else
194 lock_addr += pll->params->base_reg;
195
196 lock_mask = pll->params->lock_mask;
197
127 for (i = 0; i < pll->params->lock_delay; i++) { 198 for (i = 0; i < pll->params->lock_delay; i++) {
128 val = readl_relaxed(lock_addr); 199 val = readl_relaxed(lock_addr);
129 if (val & BIT(lock_bit_idx)) { 200 if ((val & lock_mask) == lock_mask) {
130 udelay(PLL_POST_LOCK_DELAY); 201 udelay(PLL_POST_LOCK_DELAY);
131 return 0; 202 return 0;
132 } 203 }
@@ -155,7 +226,7 @@ static int clk_pll_is_enabled(struct clk_hw *hw)
155 return val & PLL_BASE_ENABLE ? 1 : 0; 226 return val & PLL_BASE_ENABLE ? 1 : 0;
156} 227}
157 228
158static int _clk_pll_enable(struct clk_hw *hw) 229static void _clk_pll_enable(struct clk_hw *hw)
159{ 230{
160 struct tegra_clk_pll *pll = to_clk_pll(hw); 231 struct tegra_clk_pll *pll = to_clk_pll(hw);
161 u32 val; 232 u32 val;
@@ -163,7 +234,8 @@ static int _clk_pll_enable(struct clk_hw *hw)
163 clk_pll_enable_lock(pll); 234 clk_pll_enable_lock(pll);
164 235
165 val = pll_readl_base(pll); 236 val = pll_readl_base(pll);
166 val &= ~PLL_BASE_BYPASS; 237 if (pll->flags & TEGRA_PLL_BYPASS)
238 val &= ~PLL_BASE_BYPASS;
167 val |= PLL_BASE_ENABLE; 239 val |= PLL_BASE_ENABLE;
168 pll_writel_base(val, pll); 240 pll_writel_base(val, pll);
169 241
@@ -172,11 +244,6 @@ static int _clk_pll_enable(struct clk_hw *hw)
172 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 244 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
173 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 245 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
174 } 246 }
175
176 clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->base_reg,
177 pll->params->lock_bit_idx);
178
179 return 0;
180} 247}
181 248
182static void _clk_pll_disable(struct clk_hw *hw) 249static void _clk_pll_disable(struct clk_hw *hw)
@@ -185,7 +252,9 @@ static void _clk_pll_disable(struct clk_hw *hw)
185 u32 val; 252 u32 val;
186 253
187 val = pll_readl_base(pll); 254 val = pll_readl_base(pll);
188 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); 255 if (pll->flags & TEGRA_PLL_BYPASS)
256 val &= ~PLL_BASE_BYPASS;
257 val &= ~PLL_BASE_ENABLE;
189 pll_writel_base(val, pll); 258 pll_writel_base(val, pll);
190 259
191 if (pll->flags & TEGRA_PLLM) { 260 if (pll->flags & TEGRA_PLLM) {
@@ -204,7 +273,9 @@ static int clk_pll_enable(struct clk_hw *hw)
204 if (pll->lock) 273 if (pll->lock)
205 spin_lock_irqsave(pll->lock, flags); 274 spin_lock_irqsave(pll->lock, flags);
206 275
207 ret = _clk_pll_enable(hw); 276 _clk_pll_enable(hw);
277
278 ret = clk_pll_wait_for_lock(pll);
208 279
209 if (pll->lock) 280 if (pll->lock)
210 spin_unlock_irqrestore(pll->lock, flags); 281 spin_unlock_irqrestore(pll->lock, flags);
@@ -241,8 +312,6 @@ static int _get_table_rate(struct clk_hw *hw,
241 if (sel->input_rate == 0) 312 if (sel->input_rate == 0)
242 return -EINVAL; 313 return -EINVAL;
243 314
244 BUG_ON(sel->p < 1);
245
246 cfg->input_rate = sel->input_rate; 315 cfg->input_rate = sel->input_rate;
247 cfg->output_rate = sel->output_rate; 316 cfg->output_rate = sel->output_rate;
248 cfg->m = sel->m; 317 cfg->m = sel->m;
@@ -257,6 +326,7 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
257 unsigned long rate, unsigned long parent_rate) 326 unsigned long rate, unsigned long parent_rate)
258{ 327{
259 struct tegra_clk_pll *pll = to_clk_pll(hw); 328 struct tegra_clk_pll *pll = to_clk_pll(hw);
329 struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
260 unsigned long cfreq; 330 unsigned long cfreq;
261 u32 p_div = 0; 331 u32 p_div = 0;
262 332
@@ -290,88 +360,119 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
290 cfg->output_rate <<= 1) 360 cfg->output_rate <<= 1)
291 p_div++; 361 p_div++;
292 362
293 cfg->p = 1 << p_div;
294 cfg->m = parent_rate / cfreq; 363 cfg->m = parent_rate / cfreq;
295 cfg->n = cfg->output_rate / cfreq; 364 cfg->n = cfg->output_rate / cfreq;
296 cfg->cpcon = OUT_OF_TABLE_CPCON; 365 cfg->cpcon = OUT_OF_TABLE_CPCON;
297 366
298 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) || 367 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
299 cfg->p > divp_max(pll) || cfg->output_rate > pll->params->vco_max) { 368 (1 << p_div) > divp_max(pll)
369 || cfg->output_rate > pll->params->vco_max) {
300 pr_err("%s: Failed to set %s rate %lu\n", 370 pr_err("%s: Failed to set %s rate %lu\n",
301 __func__, __clk_get_name(hw->clk), rate); 371 __func__, __clk_get_name(hw->clk), rate);
302 return -EINVAL; 372 return -EINVAL;
303 } 373 }
304 374
375 if (p_tohw) {
376 p_div = 1 << p_div;
377 while (p_tohw->pdiv) {
378 if (p_div <= p_tohw->pdiv) {
379 cfg->p = p_tohw->hw_val;
380 break;
381 }
382 p_tohw++;
383 }
384 if (!p_tohw->pdiv)
385 return -EINVAL;
386 } else
387 cfg->p = p_div;
388
305 return 0; 389 return 0;
306} 390}
307 391
308static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 392static void _update_pll_mnp(struct tegra_clk_pll *pll,
309 unsigned long rate) 393 struct tegra_clk_pll_freq_table *cfg)
310{ 394{
311 struct tegra_clk_pll *pll = to_clk_pll(hw); 395 u32 val;
312 unsigned long flags = 0;
313 u32 divp, val, old_base;
314 int state;
315
316 divp = __ffs(cfg->p);
317
318 if (pll->flags & TEGRA_PLLU)
319 divp ^= 1;
320 396
321 if (pll->lock) 397 val = pll_readl_base(pll);
322 spin_lock_irqsave(pll->lock, flags);
323 398
324 old_base = val = pll_readl_base(pll);
325 val &= ~((divm_mask(pll) << pll->divm_shift) | 399 val &= ~((divm_mask(pll) << pll->divm_shift) |
326 (divn_mask(pll) << pll->divn_shift) | 400 (divn_mask(pll) << pll->divn_shift) |
327 (divp_mask(pll) << pll->divp_shift)); 401 (divp_mask(pll) << pll->divp_shift));
328 val |= ((cfg->m << pll->divm_shift) | 402 val |= ((cfg->m << pll->divm_shift) |
329 (cfg->n << pll->divn_shift) | 403 (cfg->n << pll->divn_shift) |
330 (divp << pll->divp_shift)); 404 (cfg->p << pll->divp_shift));
331 if (val == old_base) { 405
332 if (pll->lock) 406 pll_writel_base(val, pll);
333 spin_unlock_irqrestore(pll->lock, flags); 407}
334 return 0; 408
409static void _get_pll_mnp(struct tegra_clk_pll *pll,
410 struct tegra_clk_pll_freq_table *cfg)
411{
412 u32 val;
413
414 val = pll_readl_base(pll);
415
416 cfg->m = (val >> pll->divm_shift) & (divm_mask(pll));
417 cfg->n = (val >> pll->divn_shift) & (divn_mask(pll));
418 cfg->p = (val >> pll->divp_shift) & (divp_mask(pll));
419}
420
421static void _update_pll_cpcon(struct tegra_clk_pll *pll,
422 struct tegra_clk_pll_freq_table *cfg,
423 unsigned long rate)
424{
425 u32 val;
426
427 val = pll_readl_misc(pll);
428
429 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
430 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
431
432 if (pll->flags & TEGRA_PLL_SET_LFCON) {
433 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
434 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
435 val |= 1 << PLL_MISC_LFCON_SHIFT;
436 } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
437 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
438 if (rate >= (pll->params->vco_max >> 1))
439 val |= 1 << PLL_MISC_DCCON_SHIFT;
335 } 440 }
336 441
442 pll_writel_misc(val, pll);
443}
444
445static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
446 unsigned long rate)
447{
448 struct tegra_clk_pll *pll = to_clk_pll(hw);
449 int state, ret = 0;
450
337 state = clk_pll_is_enabled(hw); 451 state = clk_pll_is_enabled(hw);
338 452
339 if (state) { 453 if (state)
340 _clk_pll_disable(hw); 454 _clk_pll_disable(hw);
341 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
342 }
343 pll_writel_base(val, pll);
344 455
345 if (pll->flags & TEGRA_PLL_HAS_CPCON) { 456 _update_pll_mnp(pll, cfg);
346 val = pll_readl_misc(pll);
347 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
348 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
349 if (pll->flags & TEGRA_PLL_SET_LFCON) {
350 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
351 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
352 val |= 0x1 << PLL_MISC_LFCON_SHIFT;
353 } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
354 val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
355 if (rate >= (pll->params->vco_max >> 1))
356 val |= 0x1 << PLL_MISC_DCCON_SHIFT;
357 }
358 pll_writel_misc(val, pll);
359 }
360 457
361 if (pll->lock) 458 if (pll->flags & TEGRA_PLL_HAS_CPCON)
362 spin_unlock_irqrestore(pll->lock, flags); 459 _update_pll_cpcon(pll, cfg, rate);
363 460
364 if (state) 461 if (state) {
365 clk_pll_enable(hw); 462 _clk_pll_enable(hw);
463 ret = clk_pll_wait_for_lock(pll);
464 }
366 465
367 return 0; 466 return ret;
368} 467}
369 468
370static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 469static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
371 unsigned long parent_rate) 470 unsigned long parent_rate)
372{ 471{
373 struct tegra_clk_pll *pll = to_clk_pll(hw); 472 struct tegra_clk_pll *pll = to_clk_pll(hw);
374 struct tegra_clk_pll_freq_table cfg; 473 struct tegra_clk_pll_freq_table cfg, old_cfg;
474 unsigned long flags = 0;
475 int ret = 0;
375 476
376 if (pll->flags & TEGRA_PLL_FIXED) { 477 if (pll->flags & TEGRA_PLL_FIXED) {
377 if (rate != pll->fixed_rate) { 478 if (rate != pll->fixed_rate) {
@@ -387,7 +488,18 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
387 _calc_rate(hw, &cfg, rate, parent_rate)) 488 _calc_rate(hw, &cfg, rate, parent_rate))
388 return -EINVAL; 489 return -EINVAL;
389 490
390 return _program_pll(hw, &cfg, rate); 491 if (pll->lock)
492 spin_lock_irqsave(pll->lock, flags);
493
494 _get_pll_mnp(pll, &old_cfg);
495
496 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
497 ret = _program_pll(hw, &cfg, rate);
498
499 if (pll->lock)
500 spin_unlock_irqrestore(pll->lock, flags);
501
502 return ret;
391} 503}
392 504
393static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 505static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -409,7 +521,7 @@ static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
409 return -EINVAL; 521 return -EINVAL;
410 522
411 output_rate *= cfg.n; 523 output_rate *= cfg.n;
412 do_div(output_rate, cfg.m * cfg.p); 524 do_div(output_rate, cfg.m * (1 << cfg.p));
413 525
414 return output_rate; 526 return output_rate;
415} 527}
@@ -418,11 +530,15 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
418 unsigned long parent_rate) 530 unsigned long parent_rate)
419{ 531{
420 struct tegra_clk_pll *pll = to_clk_pll(hw); 532 struct tegra_clk_pll *pll = to_clk_pll(hw);
421 u32 val = pll_readl_base(pll); 533 struct tegra_clk_pll_freq_table cfg;
422 u32 divn = 0, divm = 0, divp = 0; 534 struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
535 u32 val;
423 u64 rate = parent_rate; 536 u64 rate = parent_rate;
537 int pdiv;
538
539 val = pll_readl_base(pll);
424 540
425 if (val & PLL_BASE_BYPASS) 541 if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
426 return parent_rate; 542 return parent_rate;
427 543
428 if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) { 544 if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
@@ -435,16 +551,29 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
435 return pll->fixed_rate; 551 return pll->fixed_rate;
436 } 552 }
437 553
438 divp = (val >> pll->divp_shift) & (divp_mask(pll)); 554 _get_pll_mnp(pll, &cfg);
439 if (pll->flags & TEGRA_PLLU)
440 divp ^= 1;
441 555
442 divn = (val >> pll->divn_shift) & (divn_mask(pll)); 556 if (p_tohw) {
443 divm = (val >> pll->divm_shift) & (divm_mask(pll)); 557 while (p_tohw->pdiv) {
444 divm *= (1 << divp); 558 if (cfg.p == p_tohw->hw_val) {
559 pdiv = p_tohw->pdiv;
560 break;
561 }
562 p_tohw++;
563 }
564
565 if (!p_tohw->pdiv) {
566 WARN_ON(1);
567 pdiv = 1;
568 }
569 } else
570 pdiv = 1 << cfg.p;
571
572 cfg.m *= pdiv;
573
574 rate *= cfg.n;
575 do_div(rate, cfg.m);
445 576
446 rate *= divn;
447 do_div(rate, divm);
448 return rate; 577 return rate;
449} 578}
450 579
@@ -538,8 +667,8 @@ static int clk_plle_enable(struct clk_hw *hw)
538 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); 667 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
539 pll_writel_base(val, pll); 668 pll_writel_base(val, pll);
540 669
541 clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->misc_reg, 670 clk_pll_wait_for_lock(pll);
542 pll->params->lock_bit_idx); 671
543 return 0; 672 return 0;
544} 673}
545 674
@@ -577,28 +706,531 @@ const struct clk_ops tegra_clk_plle_ops = {
577 .enable = clk_plle_enable, 706 .enable = clk_plle_enable,
578}; 707};
579 708
580static struct clk *_tegra_clk_register_pll(const char *name, 709#ifdef CONFIG_ARCH_TEGRA_114_SOC
581 const char *parent_name, void __iomem *clk_base, 710
582 void __iomem *pmc, unsigned long flags, 711static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
583 unsigned long fixed_rate, 712 unsigned long parent_rate)
584 struct tegra_clk_pll_params *pll_params, u8 pll_flags, 713{
585 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock, 714 if (parent_rate > pll_params->cf_max)
586 const struct clk_ops *ops) 715 return 2;
716 else
717 return 1;
718}
719
720static int clk_pll_iddq_enable(struct clk_hw *hw)
721{
722 struct tegra_clk_pll *pll = to_clk_pll(hw);
723 unsigned long flags = 0;
724
725 u32 val;
726 int ret;
727
728 if (pll->lock)
729 spin_lock_irqsave(pll->lock, flags);
730
731 val = pll_readl(pll->params->iddq_reg, pll);
732 val &= ~BIT(pll->params->iddq_bit_idx);
733 pll_writel(val, pll->params->iddq_reg, pll);
734 udelay(2);
735
736 _clk_pll_enable(hw);
737
738 ret = clk_pll_wait_for_lock(pll);
739
740 if (pll->lock)
741 spin_unlock_irqrestore(pll->lock, flags);
742
743 return 0;
744}
745
746static void clk_pll_iddq_disable(struct clk_hw *hw)
747{
748 struct tegra_clk_pll *pll = to_clk_pll(hw);
749 unsigned long flags = 0;
750 u32 val;
751
752 if (pll->lock)
753 spin_lock_irqsave(pll->lock, flags);
754
755 _clk_pll_disable(hw);
756
757 val = pll_readl(pll->params->iddq_reg, pll);
758 val |= BIT(pll->params->iddq_bit_idx);
759 pll_writel(val, pll->params->iddq_reg, pll);
760 udelay(2);
761
762 if (pll->lock)
763 spin_unlock_irqrestore(pll->lock, flags);
764}
765
766static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
767 struct tegra_clk_pll_freq_table *cfg,
768 unsigned long rate, unsigned long parent_rate)
769{
770 struct tegra_clk_pll *pll = to_clk_pll(hw);
771 unsigned int p;
772
773 if (!rate)
774 return -EINVAL;
775
776 p = DIV_ROUND_UP(pll->params->vco_min, rate);
777 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
778 cfg->p = p;
779 cfg->output_rate = rate * cfg->p;
780 cfg->n = cfg->output_rate * cfg->m / parent_rate;
781
782 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
783 return -EINVAL;
784
785 return 0;
786}
787
788static int _pll_ramp_calc_pll(struct clk_hw *hw,
789 struct tegra_clk_pll_freq_table *cfg,
790 unsigned long rate, unsigned long parent_rate)
791{
792 struct tegra_clk_pll *pll = to_clk_pll(hw);
793 int err = 0;
794
795 err = _get_table_rate(hw, cfg, rate, parent_rate);
796 if (err < 0)
797 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
798 else if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
799 WARN_ON(1);
800 err = -EINVAL;
801 goto out;
802 }
803
804 if (!cfg->p || (cfg->p > pll->params->max_p))
805 err = -EINVAL;
806
807out:
808 return err;
809}
810
811static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
812 unsigned long parent_rate)
813{
814 struct tegra_clk_pll *pll = to_clk_pll(hw);
815 struct tegra_clk_pll_freq_table cfg, old_cfg;
816 unsigned long flags = 0;
817 int ret = 0;
818 u8 old_p;
819
820 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
821 if (ret < 0)
822 return ret;
823
824 if (pll->lock)
825 spin_lock_irqsave(pll->lock, flags);
826
827 _get_pll_mnp(pll, &old_cfg);
828
829 old_p = pllxc_p[old_cfg.p];
830 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_p != cfg.p) {
831 cfg.p -= 1;
832 ret = _program_pll(hw, &cfg, rate);
833 }
834
835 if (pll->lock)
836 spin_unlock_irqrestore(pll->lock, flags);
837
838 return ret;
839}
840
841static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
842 unsigned long *prate)
843{
844 struct tegra_clk_pll_freq_table cfg;
845 int ret = 0;
846 u64 output_rate = *prate;
847
848 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
849 if (ret < 0)
850 return ret;
851
852 output_rate *= cfg.n;
853 do_div(output_rate, cfg.m * cfg.p);
854
855 return output_rate;
856}
857
858static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
859 unsigned long parent_rate)
860{
861 struct tegra_clk_pll_freq_table cfg;
862 struct tegra_clk_pll *pll = to_clk_pll(hw);
863 unsigned long flags = 0;
864 int state, ret = 0;
865 u32 val;
866
867 if (pll->lock)
868 spin_lock_irqsave(pll->lock, flags);
869
870 state = clk_pll_is_enabled(hw);
871 if (state) {
872 if (rate != clk_get_rate(hw->clk)) {
873 pr_err("%s: Cannot change active PLLM\n", __func__);
874 ret = -EINVAL;
875 goto out;
876 }
877 goto out;
878 }
879
880 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
881 if (ret < 0)
882 goto out;
883
884 cfg.p -= 1;
885
886 val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE);
887 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
888 val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE_2);
889 val = cfg.p ? (val | PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) :
890 (val & ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK);
891 writel_relaxed(val, pll->pmc + PMC_PLLM_WB0_OVERRIDE_2);
892
893 val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE);
894 val &= ~(divn_mask(pll) | divm_mask(pll));
895 val |= (cfg.m << pll->divm_shift) | (cfg.n << pll->divn_shift);
896 writel_relaxed(val, pll->pmc + PMC_PLLM_WB0_OVERRIDE);
897 } else
898 _update_pll_mnp(pll, &cfg);
899
900
901out:
902 if (pll->lock)
903 spin_unlock_irqrestore(pll->lock, flags);
904
905 return ret;
906}
907
908static void _pllcx_strobe(struct tegra_clk_pll *pll)
909{
910 u32 val;
911
912 val = pll_readl_misc(pll);
913 val |= PLLCX_MISC_STROBE;
914 pll_writel_misc(val, pll);
915 udelay(2);
916
917 val &= ~PLLCX_MISC_STROBE;
918 pll_writel_misc(val, pll);
919}
920
921static int clk_pllc_enable(struct clk_hw *hw)
922{
923 struct tegra_clk_pll *pll = to_clk_pll(hw);
924 u32 val;
925 int ret = 0;
926 unsigned long flags = 0;
927
928 if (pll->lock)
929 spin_lock_irqsave(pll->lock, flags);
930
931 _clk_pll_enable(hw);
932 udelay(2);
933
934 val = pll_readl_misc(pll);
935 val &= ~PLLCX_MISC_RESET;
936 pll_writel_misc(val, pll);
937 udelay(2);
938
939 _pllcx_strobe(pll);
940
941 ret = clk_pll_wait_for_lock(pll);
942
943 if (pll->lock)
944 spin_unlock_irqrestore(pll->lock, flags);
945
946 return ret;
947}
948
949static void _clk_pllc_disable(struct clk_hw *hw)
950{
951 struct tegra_clk_pll *pll = to_clk_pll(hw);
952 u32 val;
953
954 _clk_pll_disable(hw);
955
956 val = pll_readl_misc(pll);
957 val |= PLLCX_MISC_RESET;
958 pll_writel_misc(val, pll);
959 udelay(2);
960}
961
962static void clk_pllc_disable(struct clk_hw *hw)
963{
964 struct tegra_clk_pll *pll = to_clk_pll(hw);
965 unsigned long flags = 0;
966
967 if (pll->lock)
968 spin_lock_irqsave(pll->lock, flags);
969
970 _clk_pllc_disable(hw);
971
972 if (pll->lock)
973 spin_unlock_irqrestore(pll->lock, flags);
974}
975
976static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
977 unsigned long input_rate, u32 n)
978{
979 u32 val, n_threshold;
980
981 switch (input_rate) {
982 case 12000000:
983 n_threshold = 70;
984 break;
985 case 13000000:
986 case 26000000:
987 n_threshold = 71;
988 break;
989 case 16800000:
990 n_threshold = 55;
991 break;
992 case 19200000:
993 n_threshold = 48;
994 break;
995 default:
996 pr_err("%s: Unexpected reference rate %lu\n",
997 __func__, input_rate);
998 return -EINVAL;
999 }
1000
1001 val = pll_readl_misc(pll);
1002 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1003 val |= n <= n_threshold ?
1004 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1005 pll_writel_misc(val, pll);
1006
1007 return 0;
1008}
1009
1010static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1011 unsigned long parent_rate)
1012{
1013 struct tegra_clk_pll_freq_table cfg;
1014 struct tegra_clk_pll *pll = to_clk_pll(hw);
1015 unsigned long flags = 0;
1016 int state, ret = 0;
1017 u32 val;
1018 u16 old_m, old_n;
1019 u8 old_p;
1020
1021 if (pll->lock)
1022 spin_lock_irqsave(pll->lock, flags);
1023
1024 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1025 if (ret < 0)
1026 goto out;
1027
1028 val = pll_readl_base(pll);
1029 old_m = (val >> pll->divm_shift) & (divm_mask(pll));
1030 old_n = (val >> pll->divn_shift) & (divn_mask(pll));
1031 old_p = pllcx_p[(val >> pll->divp_shift) & (divp_mask(pll))];
1032
1033 if (cfg.m != old_m) {
1034 WARN_ON(1);
1035 goto out;
1036 }
1037
1038 if (old_n == cfg.n && old_p == cfg.p)
1039 goto out;
1040
1041 cfg.p -= 1;
1042
1043 state = clk_pll_is_enabled(hw);
1044 if (state)
1045 _clk_pllc_disable(hw);
1046
1047 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1048 if (ret < 0)
1049 goto out;
1050
1051 _update_pll_mnp(pll, &cfg);
1052
1053 if (state)
1054 ret = clk_pllc_enable(hw);
1055
1056out:
1057 if (pll->lock)
1058 spin_unlock_irqrestore(pll->lock, flags);
1059
1060 return ret;
1061}
1062
1063static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1064 struct tegra_clk_pll_freq_table *cfg,
1065 unsigned long rate, unsigned long parent_rate)
1066{
1067 u16 m, n;
1068 u64 output_rate = parent_rate;
1069
1070 m = _pll_fixed_mdiv(pll->params, parent_rate);
1071 n = rate * m / parent_rate;
1072
1073 output_rate *= n;
1074 do_div(output_rate, m);
1075
1076 if (cfg) {
1077 cfg->m = m;
1078 cfg->n = n;
1079 }
1080
1081 return output_rate;
1082}
1083static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1084 unsigned long parent_rate)
1085{
1086 struct tegra_clk_pll_freq_table cfg, old_cfg;
1087 struct tegra_clk_pll *pll = to_clk_pll(hw);
1088 unsigned long flags = 0;
1089 int state, ret = 0;
1090
1091 if (pll->lock)
1092 spin_lock_irqsave(pll->lock, flags);
1093
1094 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1095 _get_pll_mnp(pll, &old_cfg);
1096 cfg.p = old_cfg.p;
1097
1098 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1099 state = clk_pll_is_enabled(hw);
1100 if (state)
1101 _clk_pll_disable(hw);
1102
1103 _update_pll_mnp(pll, &cfg);
1104
1105 if (state) {
1106 _clk_pll_enable(hw);
1107 ret = clk_pll_wait_for_lock(pll);
1108 }
1109 }
1110
1111 if (pll->lock)
1112 spin_unlock_irqrestore(pll->lock, flags);
1113
1114 return ret;
1115}
1116
1117static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1118 unsigned long parent_rate)
1119{
1120 struct tegra_clk_pll_freq_table cfg;
1121 struct tegra_clk_pll *pll = to_clk_pll(hw);
1122 u64 rate = parent_rate;
1123
1124 _get_pll_mnp(pll, &cfg);
1125
1126 rate *= cfg.n;
1127 do_div(rate, cfg.m);
1128
1129 return rate;
1130}
1131
1132static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1133 unsigned long *prate)
1134{
1135 struct tegra_clk_pll *pll = to_clk_pll(hw);
1136
1137 return _pllre_calc_rate(pll, NULL, rate, *prate);
1138}
1139
1140static int clk_plle_tegra114_enable(struct clk_hw *hw)
1141{
1142 struct tegra_clk_pll *pll = to_clk_pll(hw);
1143 struct tegra_clk_pll_freq_table sel;
1144 u32 val;
1145 int ret;
1146 unsigned long flags = 0;
1147 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
1148
1149 if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate))
1150 return -EINVAL;
1151
1152 if (pll->lock)
1153 spin_lock_irqsave(pll->lock, flags);
1154
1155 val = pll_readl_base(pll);
1156 val &= ~BIT(29); /* Disable lock override */
1157 pll_writel_base(val, pll);
1158
1159 val = pll_readl(pll->params->aux_reg, pll);
1160 val |= PLLE_AUX_ENABLE_SWCTL;
1161 val &= ~PLLE_AUX_SEQ_ENABLE;
1162 pll_writel(val, pll->params->aux_reg, pll);
1163 udelay(1);
1164
1165 val = pll_readl_misc(pll);
1166 val |= PLLE_MISC_LOCK_ENABLE;
1167 val |= PLLE_MISC_IDDQ_SW_CTRL;
1168 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1169 val |= PLLE_MISC_PLLE_PTS;
1170 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
1171 pll_writel_misc(val, pll);
1172 udelay(5);
1173
1174 val = pll_readl(PLLE_SS_CTRL, pll);
1175 val |= PLLE_SS_DISABLE;
1176 pll_writel(val, PLLE_SS_CTRL, pll);
1177
1178 val = pll_readl_base(pll);
1179 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
1180 val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
1181 val |= sel.m << pll->divm_shift;
1182 val |= sel.n << pll->divn_shift;
1183 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1184 pll_writel_base(val, pll);
1185 udelay(1);
1186
1187 _clk_pll_enable(hw);
1188 ret = clk_pll_wait_for_lock(pll);
1189
1190 if (ret < 0)
1191 goto out;
1192
1193 /* TODO: enable hw control of xusb brick pll */
1194
1195out:
1196 if (pll->lock)
1197 spin_unlock_irqrestore(pll->lock, flags);
1198
1199 return ret;
1200}
1201
1202static void clk_plle_tegra114_disable(struct clk_hw *hw)
1203{
1204 struct tegra_clk_pll *pll = to_clk_pll(hw);
1205 unsigned long flags = 0;
1206 u32 val;
1207
1208 if (pll->lock)
1209 spin_lock_irqsave(pll->lock, flags);
1210
1211 _clk_pll_disable(hw);
1212
1213 val = pll_readl_misc(pll);
1214 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1215 pll_writel_misc(val, pll);
1216 udelay(1);
1217
1218 if (pll->lock)
1219 spin_unlock_irqrestore(pll->lock, flags);
1220}
1221#endif
1222
1223static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1224 void __iomem *pmc, unsigned long fixed_rate,
1225 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
1226 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
587{ 1227{
588 struct tegra_clk_pll *pll; 1228 struct tegra_clk_pll *pll;
589 struct clk *clk;
590 struct clk_init_data init;
591 1229
592 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1230 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
593 if (!pll) 1231 if (!pll)
594 return ERR_PTR(-ENOMEM); 1232 return ERR_PTR(-ENOMEM);
595 1233
596 init.name = name;
597 init.ops = ops;
598 init.flags = flags;
599 init.parent_names = (parent_name ? &parent_name : NULL);
600 init.num_parents = (parent_name ? 1 : 0);
601
602 pll->clk_base = clk_base; 1234 pll->clk_base = clk_base;
603 pll->pmc = pmc; 1235 pll->pmc = pmc;
604 1236
@@ -615,34 +1247,336 @@ static struct clk *_tegra_clk_register_pll(const char *name,
615 pll->divm_shift = PLL_BASE_DIVM_SHIFT; 1247 pll->divm_shift = PLL_BASE_DIVM_SHIFT;
616 pll->divm_width = PLL_BASE_DIVM_WIDTH; 1248 pll->divm_width = PLL_BASE_DIVM_WIDTH;
617 1249
1250 return pll;
1251}
1252
1253static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1254 const char *name, const char *parent_name, unsigned long flags,
1255 const struct clk_ops *ops)
1256{
1257 struct clk_init_data init;
1258
1259 init.name = name;
1260 init.ops = ops;
1261 init.flags = flags;
1262 init.parent_names = (parent_name ? &parent_name : NULL);
1263 init.num_parents = (parent_name ? 1 : 0);
1264
618 /* Data in .init is copied by clk_register(), so stack variable OK */ 1265 /* Data in .init is copied by clk_register(), so stack variable OK */
619 pll->hw.init = &init; 1266 pll->hw.init = &init;
620 1267
621 clk = clk_register(NULL, &pll->hw); 1268 return clk_register(NULL, &pll->hw);
622 if (IS_ERR(clk))
623 kfree(pll);
624
625 return clk;
626} 1269}
627 1270
628struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 1271struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
629 void __iomem *clk_base, void __iomem *pmc, 1272 void __iomem *clk_base, void __iomem *pmc,
630 unsigned long flags, unsigned long fixed_rate, 1273 unsigned long flags, unsigned long fixed_rate,
631 struct tegra_clk_pll_params *pll_params, u8 pll_flags, 1274 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
632 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock) 1275 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
633{ 1276{
634 return _tegra_clk_register_pll(name, parent_name, clk_base, pmc, 1277 struct tegra_clk_pll *pll;
635 flags, fixed_rate, pll_params, pll_flags, freq_table, 1278 struct clk *clk;
636 lock, &tegra_clk_pll_ops); 1279
1280 pll_flags |= TEGRA_PLL_BYPASS;
1281 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1282 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1283 freq_table, lock);
1284 if (IS_ERR(pll))
1285 return ERR_CAST(pll);
1286
1287 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1288 &tegra_clk_pll_ops);
1289 if (IS_ERR(clk))
1290 kfree(pll);
1291
1292 return clk;
637} 1293}
638 1294
639struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 1295struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
640 void __iomem *clk_base, void __iomem *pmc, 1296 void __iomem *clk_base, void __iomem *pmc,
641 unsigned long flags, unsigned long fixed_rate, 1297 unsigned long flags, unsigned long fixed_rate,
642 struct tegra_clk_pll_params *pll_params, u8 pll_flags, 1298 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
643 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock) 1299 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
644{ 1300{
645 return _tegra_clk_register_pll(name, parent_name, clk_base, pmc, 1301 struct tegra_clk_pll *pll;
646 flags, fixed_rate, pll_params, pll_flags, freq_table, 1302 struct clk *clk;
647 lock, &tegra_clk_plle_ops); 1303
1304 pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
1305 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1306 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1307 freq_table, lock);
1308 if (IS_ERR(pll))
1309 return ERR_CAST(pll);
1310
1311 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1312 &tegra_clk_plle_ops);
1313 if (IS_ERR(clk))
1314 kfree(pll);
1315
1316 return clk;
1317}
1318
1319#ifdef CONFIG_ARCH_TEGRA_114_SOC
1320const struct clk_ops tegra_clk_pllxc_ops = {
1321 .is_enabled = clk_pll_is_enabled,
1322 .enable = clk_pll_iddq_enable,
1323 .disable = clk_pll_iddq_disable,
1324 .recalc_rate = clk_pll_recalc_rate,
1325 .round_rate = clk_pll_ramp_round_rate,
1326 .set_rate = clk_pllxc_set_rate,
1327};
1328
1329const struct clk_ops tegra_clk_pllm_ops = {
1330 .is_enabled = clk_pll_is_enabled,
1331 .enable = clk_pll_iddq_enable,
1332 .disable = clk_pll_iddq_disable,
1333 .recalc_rate = clk_pll_recalc_rate,
1334 .round_rate = clk_pll_ramp_round_rate,
1335 .set_rate = clk_pllm_set_rate,
1336};
1337
1338const struct clk_ops tegra_clk_pllc_ops = {
1339 .is_enabled = clk_pll_is_enabled,
1340 .enable = clk_pllc_enable,
1341 .disable = clk_pllc_disable,
1342 .recalc_rate = clk_pll_recalc_rate,
1343 .round_rate = clk_pll_ramp_round_rate,
1344 .set_rate = clk_pllc_set_rate,
1345};
1346
1347const struct clk_ops tegra_clk_pllre_ops = {
1348 .is_enabled = clk_pll_is_enabled,
1349 .enable = clk_pll_iddq_enable,
1350 .disable = clk_pll_iddq_disable,
1351 .recalc_rate = clk_pllre_recalc_rate,
1352 .round_rate = clk_pllre_round_rate,
1353 .set_rate = clk_pllre_set_rate,
1354};
1355
1356const struct clk_ops tegra_clk_plle_tegra114_ops = {
1357 .is_enabled = clk_pll_is_enabled,
1358 .enable = clk_plle_tegra114_enable,
1359 .disable = clk_plle_tegra114_disable,
1360 .recalc_rate = clk_pll_recalc_rate,
1361};
1362
1363
1364struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1365 void __iomem *clk_base, void __iomem *pmc,
1366 unsigned long flags, unsigned long fixed_rate,
1367 struct tegra_clk_pll_params *pll_params,
1368 u32 pll_flags,
1369 struct tegra_clk_pll_freq_table *freq_table,
1370 spinlock_t *lock)
1371{
1372 struct tegra_clk_pll *pll;
1373 struct clk *clk;
1374
1375 if (!pll_params->pdiv_tohw)
1376 return ERR_PTR(-EINVAL);
1377
1378 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1379 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1380 freq_table, lock);
1381 if (IS_ERR(pll))
1382 return ERR_CAST(pll);
1383
1384 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1385 &tegra_clk_pllxc_ops);
1386 if (IS_ERR(clk))
1387 kfree(pll);
1388
1389 return clk;
1390}
1391
1392struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1393 void __iomem *clk_base, void __iomem *pmc,
1394 unsigned long flags, unsigned long fixed_rate,
1395 struct tegra_clk_pll_params *pll_params,
1396 u32 pll_flags,
1397 struct tegra_clk_pll_freq_table *freq_table,
1398 spinlock_t *lock, unsigned long parent_rate)
1399{
1400 u32 val;
1401 struct tegra_clk_pll *pll;
1402 struct clk *clk;
1403
1404 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1405 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1406 freq_table, lock);
1407 if (IS_ERR(pll))
1408 return ERR_CAST(pll);
1409
1410 /* program minimum rate by default */
1411
1412 val = pll_readl_base(pll);
1413 if (val & PLL_BASE_ENABLE)
1414 WARN_ON(val & pll_params->iddq_bit_idx);
1415 else {
1416 int m;
1417
1418 m = _pll_fixed_mdiv(pll_params, parent_rate);
1419 val = m << PLL_BASE_DIVM_SHIFT;
1420 val |= (pll_params->vco_min / parent_rate)
1421 << PLL_BASE_DIVN_SHIFT;
1422 pll_writel_base(val, pll);
1423 }
1424
1425 /* disable lock override */
1426
1427 val = pll_readl_misc(pll);
1428 val &= ~BIT(29);
1429 pll_writel_misc(val, pll);
1430
1431 pll_flags |= TEGRA_PLL_LOCK_MISC;
1432 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1433 &tegra_clk_pllre_ops);
1434 if (IS_ERR(clk))
1435 kfree(pll);
1436
1437 return clk;
1438}
1439
1440struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1441 void __iomem *clk_base, void __iomem *pmc,
1442 unsigned long flags, unsigned long fixed_rate,
1443 struct tegra_clk_pll_params *pll_params,
1444 u32 pll_flags,
1445 struct tegra_clk_pll_freq_table *freq_table,
1446 spinlock_t *lock)
1447{
1448 struct tegra_clk_pll *pll;
1449 struct clk *clk;
1450
1451 if (!pll_params->pdiv_tohw)
1452 return ERR_PTR(-EINVAL);
1453
1454 pll_flags |= TEGRA_PLL_BYPASS;
1455 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1456 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1457 freq_table, lock);
1458 if (IS_ERR(pll))
1459 return ERR_CAST(pll);
1460
1461 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1462 &tegra_clk_pllm_ops);
1463 if (IS_ERR(clk))
1464 kfree(pll);
1465
1466 return clk;
1467}
1468
1469struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1470 void __iomem *clk_base, void __iomem *pmc,
1471 unsigned long flags, unsigned long fixed_rate,
1472 struct tegra_clk_pll_params *pll_params,
1473 u32 pll_flags,
1474 struct tegra_clk_pll_freq_table *freq_table,
1475 spinlock_t *lock)
1476{
1477 struct clk *parent, *clk;
1478 struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
1479 struct tegra_clk_pll *pll;
1480 struct tegra_clk_pll_freq_table cfg;
1481 unsigned long parent_rate;
1482
1483 if (!p_tohw)
1484 return ERR_PTR(-EINVAL);
1485
1486 parent = __clk_lookup(parent_name);
1487 if (IS_ERR(parent)) {
1488 WARN(1, "parent clk %s of %s must be registered first\n",
1489 name, parent_name);
1490 return ERR_PTR(-EINVAL);
1491 }
1492
1493 pll_flags |= TEGRA_PLL_BYPASS;
1494 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1495 freq_table, lock);
1496 if (IS_ERR(pll))
1497 return ERR_CAST(pll);
1498
1499 parent_rate = __clk_get_rate(parent);
1500
1501 /*
1502 * Most of PLLC register fields are shadowed, and can not be read
1503 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
1504 * Initialize PLL to default state: disabled, reset; shadow registers
1505 * loaded with default parameters; dividers are preset for half of
1506 * minimum VCO rate (the latter assured that shadowed divider settings
1507 * are within supported range).
1508 */
1509
1510 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1511 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1512
1513 while (p_tohw->pdiv) {
1514 if (p_tohw->pdiv == 2) {
1515 cfg.p = p_tohw->hw_val;
1516 break;
1517 }
1518 p_tohw++;
1519 }
1520
1521 if (!p_tohw->pdiv) {
1522 WARN_ON(1);
1523 return ERR_PTR(-EINVAL);
1524 }
1525
1526 pll_writel_base(0, pll);
1527 _update_pll_mnp(pll, &cfg);
1528
1529 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
1530 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
1531 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
1532 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
1533
1534 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1535
1536 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1537 &tegra_clk_pllc_ops);
1538 if (IS_ERR(clk))
1539 kfree(pll);
1540
1541 return clk;
1542}
1543
1544struct clk *tegra_clk_register_plle_tegra114(const char *name,
1545 const char *parent_name,
1546 void __iomem *clk_base, unsigned long flags,
1547 unsigned long fixed_rate,
1548 struct tegra_clk_pll_params *pll_params,
1549 struct tegra_clk_pll_freq_table *freq_table,
1550 spinlock_t *lock)
1551{
1552 struct tegra_clk_pll *pll;
1553 struct clk *clk;
1554 u32 val, val_aux;
1555
1556 pll = _tegra_init_pll(clk_base, NULL, fixed_rate, pll_params,
1557 TEGRA_PLL_HAS_LOCK_ENABLE, freq_table, lock);
1558 if (IS_ERR(pll))
1559 return ERR_CAST(pll);
1560
1561 /* ensure parent is set to pll_re_vco */
1562
1563 val = pll_readl_base(pll);
1564 val_aux = pll_readl(pll_params->aux_reg, pll);
1565
1566 if (val & PLL_BASE_ENABLE) {
1567 if (!(val_aux & PLLE_AUX_PLLRE_SEL))
1568 WARN(1, "pll_e enabled with unsupported parent %s\n",
1569 (val & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : "pll_ref");
1570 } else {
1571 val_aux |= PLLE_AUX_PLLRE_SEL;
1572 pll_writel(val, pll_params->aux_reg, pll);
1573 }
1574
1575 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1576 &tegra_clk_plle_tegra114_ops);
1577 if (IS_ERR(clk))
1578 kfree(pll);
1579
1580 return clk;
648} 1581}
1582#endif
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
new file mode 100644
index 000000000000..d78e16ee161c
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -0,0 +1,2085 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/delay.h>
24#include <linux/clk/tegra.h>
25
26#include "clk.h"
27
28#define RST_DEVICES_L 0x004
29#define RST_DEVICES_H 0x008
30#define RST_DEVICES_U 0x00C
31#define RST_DEVICES_V 0x358
32#define RST_DEVICES_W 0x35C
33#define RST_DEVICES_X 0x28C
34#define RST_DEVICES_SET_L 0x300
35#define RST_DEVICES_CLR_L 0x304
36#define RST_DEVICES_SET_H 0x308
37#define RST_DEVICES_CLR_H 0x30c
38#define RST_DEVICES_SET_U 0x310
39#define RST_DEVICES_CLR_U 0x314
40#define RST_DEVICES_SET_V 0x430
41#define RST_DEVICES_CLR_V 0x434
42#define RST_DEVICES_SET_W 0x438
43#define RST_DEVICES_CLR_W 0x43c
44#define RST_DEVICES_NUM 5
45
46#define CLK_OUT_ENB_L 0x010
47#define CLK_OUT_ENB_H 0x014
48#define CLK_OUT_ENB_U 0x018
49#define CLK_OUT_ENB_V 0x360
50#define CLK_OUT_ENB_W 0x364
51#define CLK_OUT_ENB_X 0x280
52#define CLK_OUT_ENB_SET_L 0x320
53#define CLK_OUT_ENB_CLR_L 0x324
54#define CLK_OUT_ENB_SET_H 0x328
55#define CLK_OUT_ENB_CLR_H 0x32c
56#define CLK_OUT_ENB_SET_U 0x330
57#define CLK_OUT_ENB_CLR_U 0x334
58#define CLK_OUT_ENB_SET_V 0x440
59#define CLK_OUT_ENB_CLR_V 0x444
60#define CLK_OUT_ENB_SET_W 0x448
61#define CLK_OUT_ENB_CLR_W 0x44c
62#define CLK_OUT_ENB_SET_X 0x284
63#define CLK_OUT_ENB_CLR_X 0x288
64#define CLK_OUT_ENB_NUM 6
65
66#define PLLC_BASE 0x80
67#define PLLC_MISC2 0x88
68#define PLLC_MISC 0x8c
69#define PLLC2_BASE 0x4e8
70#define PLLC2_MISC 0x4ec
71#define PLLC3_BASE 0x4fc
72#define PLLC3_MISC 0x500
73#define PLLM_BASE 0x90
74#define PLLM_MISC 0x9c
75#define PLLP_BASE 0xa0
76#define PLLP_MISC 0xac
77#define PLLX_BASE 0xe0
78#define PLLX_MISC 0xe4
79#define PLLX_MISC2 0x514
80#define PLLX_MISC3 0x518
81#define PLLD_BASE 0xd0
82#define PLLD_MISC 0xdc
83#define PLLD2_BASE 0x4b8
84#define PLLD2_MISC 0x4bc
85#define PLLE_BASE 0xe8
86#define PLLE_MISC 0xec
87#define PLLA_BASE 0xb0
88#define PLLA_MISC 0xbc
89#define PLLU_BASE 0xc0
90#define PLLU_MISC 0xcc
91#define PLLRE_BASE 0x4c4
92#define PLLRE_MISC 0x4c8
93
94#define PLL_MISC_LOCK_ENABLE 18
95#define PLLC_MISC_LOCK_ENABLE 24
96#define PLLDU_MISC_LOCK_ENABLE 22
97#define PLLE_MISC_LOCK_ENABLE 9
98#define PLLRE_MISC_LOCK_ENABLE 30
99
100#define PLLC_IDDQ_BIT 26
101#define PLLX_IDDQ_BIT 3
102#define PLLRE_IDDQ_BIT 16
103
104#define PLL_BASE_LOCK BIT(27)
105#define PLLE_MISC_LOCK BIT(11)
106#define PLLRE_MISC_LOCK BIT(24)
107#define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
108
109#define PLLE_AUX 0x48c
110#define PLLC_OUT 0x84
111#define PLLM_OUT 0x94
112#define PLLP_OUTA 0xa4
113#define PLLP_OUTB 0xa8
114#define PLLA_OUT 0xb4
115
116#define AUDIO_SYNC_CLK_I2S0 0x4a0
117#define AUDIO_SYNC_CLK_I2S1 0x4a4
118#define AUDIO_SYNC_CLK_I2S2 0x4a8
119#define AUDIO_SYNC_CLK_I2S3 0x4ac
120#define AUDIO_SYNC_CLK_I2S4 0x4b0
121#define AUDIO_SYNC_CLK_SPDIF 0x4b4
122
123#define AUDIO_SYNC_DOUBLER 0x49c
124
125#define PMC_CLK_OUT_CNTRL 0x1a8
126#define PMC_DPD_PADS_ORIDE 0x1c
127#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
128#define PMC_CTRL 0
129#define PMC_CTRL_BLINK_ENB 7
130
131#define OSC_CTRL 0x50
132#define OSC_CTRL_OSC_FREQ_SHIFT 28
133#define OSC_CTRL_PLL_REF_DIV_SHIFT 26
134
135#define PLLXC_SW_MAX_P 6
136
137#define CCLKG_BURST_POLICY 0x368
138#define CCLKLP_BURST_POLICY 0x370
139#define SCLK_BURST_POLICY 0x028
140#define SYSTEM_CLK_RATE 0x030
141
142#define UTMIP_PLL_CFG2 0x488
143#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
144#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
145#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
146#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
147#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
148
149#define UTMIP_PLL_CFG1 0x484
150#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
151#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
152#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
153#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
154#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
155#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
156#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
157
158#define UTMIPLL_HW_PWRDN_CFG0 0x52c
159#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
160#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
161#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
162#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
163#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
164#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
165#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
166#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
167
168#define CLK_SOURCE_I2S0 0x1d8
169#define CLK_SOURCE_I2S1 0x100
170#define CLK_SOURCE_I2S2 0x104
171#define CLK_SOURCE_NDFLASH 0x160
172#define CLK_SOURCE_I2S3 0x3bc
173#define CLK_SOURCE_I2S4 0x3c0
174#define CLK_SOURCE_SPDIF_OUT 0x108
175#define CLK_SOURCE_SPDIF_IN 0x10c
176#define CLK_SOURCE_PWM 0x110
177#define CLK_SOURCE_ADX 0x638
178#define CLK_SOURCE_AMX 0x63c
179#define CLK_SOURCE_HDA 0x428
180#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
181#define CLK_SOURCE_SBC1 0x134
182#define CLK_SOURCE_SBC2 0x118
183#define CLK_SOURCE_SBC3 0x11c
184#define CLK_SOURCE_SBC4 0x1b4
185#define CLK_SOURCE_SBC5 0x3c8
186#define CLK_SOURCE_SBC6 0x3cc
187#define CLK_SOURCE_SATA_OOB 0x420
188#define CLK_SOURCE_SATA 0x424
189#define CLK_SOURCE_NDSPEED 0x3f8
190#define CLK_SOURCE_VFIR 0x168
191#define CLK_SOURCE_SDMMC1 0x150
192#define CLK_SOURCE_SDMMC2 0x154
193#define CLK_SOURCE_SDMMC3 0x1bc
194#define CLK_SOURCE_SDMMC4 0x164
195#define CLK_SOURCE_VDE 0x1c8
196#define CLK_SOURCE_CSITE 0x1d4
197#define CLK_SOURCE_LA 0x1f8
198#define CLK_SOURCE_TRACE 0x634
199#define CLK_SOURCE_OWR 0x1cc
200#define CLK_SOURCE_NOR 0x1d0
201#define CLK_SOURCE_MIPI 0x174
202#define CLK_SOURCE_I2C1 0x124
203#define CLK_SOURCE_I2C2 0x198
204#define CLK_SOURCE_I2C3 0x1b8
205#define CLK_SOURCE_I2C4 0x3c4
206#define CLK_SOURCE_I2C5 0x128
207#define CLK_SOURCE_UARTA 0x178
208#define CLK_SOURCE_UARTB 0x17c
209#define CLK_SOURCE_UARTC 0x1a0
210#define CLK_SOURCE_UARTD 0x1c0
211#define CLK_SOURCE_UARTE 0x1c4
212#define CLK_SOURCE_UARTA_DBG 0x178
213#define CLK_SOURCE_UARTB_DBG 0x17c
214#define CLK_SOURCE_UARTC_DBG 0x1a0
215#define CLK_SOURCE_UARTD_DBG 0x1c0
216#define CLK_SOURCE_UARTE_DBG 0x1c4
217#define CLK_SOURCE_3D 0x158
218#define CLK_SOURCE_2D 0x15c
219#define CLK_SOURCE_VI_SENSOR 0x1a8
220#define CLK_SOURCE_VI 0x148
221#define CLK_SOURCE_EPP 0x16c
222#define CLK_SOURCE_MSENC 0x1f0
223#define CLK_SOURCE_TSEC 0x1f4
224#define CLK_SOURCE_HOST1X 0x180
225#define CLK_SOURCE_HDMI 0x18c
226#define CLK_SOURCE_DISP1 0x138
227#define CLK_SOURCE_DISP2 0x13c
228#define CLK_SOURCE_CILAB 0x614
229#define CLK_SOURCE_CILCD 0x618
230#define CLK_SOURCE_CILE 0x61c
231#define CLK_SOURCE_DSIALP 0x620
232#define CLK_SOURCE_DSIBLP 0x624
233#define CLK_SOURCE_TSENSOR 0x3b8
234#define CLK_SOURCE_D_AUDIO 0x3d0
235#define CLK_SOURCE_DAM0 0x3d8
236#define CLK_SOURCE_DAM1 0x3dc
237#define CLK_SOURCE_DAM2 0x3e0
238#define CLK_SOURCE_ACTMON 0x3e8
239#define CLK_SOURCE_EXTERN1 0x3ec
240#define CLK_SOURCE_EXTERN2 0x3f0
241#define CLK_SOURCE_EXTERN3 0x3f4
242#define CLK_SOURCE_I2CSLOW 0x3fc
243#define CLK_SOURCE_SE 0x42c
244#define CLK_SOURCE_MSELECT 0x3b4
245#define CLK_SOURCE_SOC_THERM 0x644
246#define CLK_SOURCE_XUSB_HOST_SRC 0x600
247#define CLK_SOURCE_XUSB_FALCON_SRC 0x604
248#define CLK_SOURCE_XUSB_FS_SRC 0x608
249#define CLK_SOURCE_XUSB_SS_SRC 0x610
250#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
251#define CLK_SOURCE_EMC 0x19c
252
253static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
254
255static void __iomem *clk_base;
256static void __iomem *pmc_base;
257
258static DEFINE_SPINLOCK(pll_d_lock);
259static DEFINE_SPINLOCK(pll_d2_lock);
260static DEFINE_SPINLOCK(pll_u_lock);
261static DEFINE_SPINLOCK(pll_div_lock);
262static DEFINE_SPINLOCK(pll_re_lock);
263static DEFINE_SPINLOCK(clk_doubler_lock);
264static DEFINE_SPINLOCK(clk_out_lock);
265static DEFINE_SPINLOCK(sysrate_lock);
266
267static struct pdiv_map pllxc_p[] = {
268 { .pdiv = 1, .hw_val = 0 },
269 { .pdiv = 2, .hw_val = 1 },
270 { .pdiv = 3, .hw_val = 2 },
271 { .pdiv = 4, .hw_val = 3 },
272 { .pdiv = 5, .hw_val = 4 },
273 { .pdiv = 6, .hw_val = 5 },
274 { .pdiv = 8, .hw_val = 6 },
275 { .pdiv = 10, .hw_val = 7 },
276 { .pdiv = 12, .hw_val = 8 },
277 { .pdiv = 16, .hw_val = 9 },
278 { .pdiv = 12, .hw_val = 10 },
279 { .pdiv = 16, .hw_val = 11 },
280 { .pdiv = 20, .hw_val = 12 },
281 { .pdiv = 24, .hw_val = 13 },
282 { .pdiv = 32, .hw_val = 14 },
283 { .pdiv = 0, .hw_val = 0 },
284};
285
286static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
287 { 12000000, 624000000, 104, 0, 2},
288 { 12000000, 600000000, 100, 0, 2},
289 { 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */
290 { 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */
291 { 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */
292 { 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
293 { 0, 0, 0, 0, 0, 0 },
294};
295
296static struct tegra_clk_pll_params pll_c_params = {
297 .input_min = 12000000,
298 .input_max = 800000000,
299 .cf_min = 12000000,
300 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
301 .vco_min = 600000000,
302 .vco_max = 1400000000,
303 .base_reg = PLLC_BASE,
304 .misc_reg = PLLC_MISC,
305 .lock_mask = PLL_BASE_LOCK,
306 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
307 .lock_delay = 300,
308 .iddq_reg = PLLC_MISC,
309 .iddq_bit_idx = PLLC_IDDQ_BIT,
310 .max_p = PLLXC_SW_MAX_P,
311 .dyn_ramp_reg = PLLC_MISC2,
312 .stepa_shift = 17,
313 .stepb_shift = 9,
314 .pdiv_tohw = pllxc_p,
315};
316
317static struct pdiv_map pllc_p[] = {
318 { .pdiv = 1, .hw_val = 0 },
319 { .pdiv = 2, .hw_val = 1 },
320 { .pdiv = 4, .hw_val = 3 },
321 { .pdiv = 8, .hw_val = 5 },
322 { .pdiv = 16, .hw_val = 7 },
323 { .pdiv = 0, .hw_val = 0 },
324};
325
326static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
327 {12000000, 600000000, 100, 0, 2},
328 {13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */
329 {16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */
330 {19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */
331 {26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
332 {0, 0, 0, 0, 0, 0},
333};
334
335static struct tegra_clk_pll_params pll_c2_params = {
336 .input_min = 12000000,
337 .input_max = 48000000,
338 .cf_min = 12000000,
339 .cf_max = 19200000,
340 .vco_min = 600000000,
341 .vco_max = 1200000000,
342 .base_reg = PLLC2_BASE,
343 .misc_reg = PLLC2_MISC,
344 .lock_mask = PLL_BASE_LOCK,
345 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
346 .lock_delay = 300,
347 .pdiv_tohw = pllc_p,
348 .ext_misc_reg[0] = 0x4f0,
349 .ext_misc_reg[1] = 0x4f4,
350 .ext_misc_reg[2] = 0x4f8,
351};
352
353static struct tegra_clk_pll_params pll_c3_params = {
354 .input_min = 12000000,
355 .input_max = 48000000,
356 .cf_min = 12000000,
357 .cf_max = 19200000,
358 .vco_min = 600000000,
359 .vco_max = 1200000000,
360 .base_reg = PLLC3_BASE,
361 .misc_reg = PLLC3_MISC,
362 .lock_mask = PLL_BASE_LOCK,
363 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
364 .lock_delay = 300,
365 .pdiv_tohw = pllc_p,
366 .ext_misc_reg[0] = 0x504,
367 .ext_misc_reg[1] = 0x508,
368 .ext_misc_reg[2] = 0x50c,
369};
370
371static struct pdiv_map pllm_p[] = {
372 { .pdiv = 1, .hw_val = 0 },
373 { .pdiv = 2, .hw_val = 1 },
374 { .pdiv = 0, .hw_val = 0 },
375};
376
377static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
378 {12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */
379 {13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */
380 {16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */
381 {19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */
382 {26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
383 {0, 0, 0, 0, 0, 0},
384};
385
386static struct tegra_clk_pll_params pll_m_params = {
387 .input_min = 12000000,
388 .input_max = 500000000,
389 .cf_min = 12000000,
390 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
391 .vco_min = 400000000,
392 .vco_max = 1066000000,
393 .base_reg = PLLM_BASE,
394 .misc_reg = PLLM_MISC,
395 .lock_mask = PLL_BASE_LOCK,
396 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
397 .lock_delay = 300,
398 .max_p = 2,
399 .pdiv_tohw = pllm_p,
400};
401
402static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
403 {12000000, 216000000, 432, 12, 1, 8},
404 {13000000, 216000000, 432, 13, 1, 8},
405 {16800000, 216000000, 360, 14, 1, 8},
406 {19200000, 216000000, 360, 16, 1, 8},
407 {26000000, 216000000, 432, 26, 1, 8},
408 {0, 0, 0, 0, 0, 0},
409};
410
411static struct tegra_clk_pll_params pll_p_params = {
412 .input_min = 2000000,
413 .input_max = 31000000,
414 .cf_min = 1000000,
415 .cf_max = 6000000,
416 .vco_min = 200000000,
417 .vco_max = 700000000,
418 .base_reg = PLLP_BASE,
419 .misc_reg = PLLP_MISC,
420 .lock_mask = PLL_BASE_LOCK,
421 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
422 .lock_delay = 300,
423};
424
425static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
426 {9600000, 282240000, 147, 5, 0, 4},
427 {9600000, 368640000, 192, 5, 0, 4},
428 {9600000, 240000000, 200, 8, 0, 8},
429
430 {28800000, 282240000, 245, 25, 0, 8},
431 {28800000, 368640000, 320, 25, 0, 8},
432 {28800000, 240000000, 200, 24, 0, 8},
433 {0, 0, 0, 0, 0, 0},
434};
435
436
437static struct tegra_clk_pll_params pll_a_params = {
438 .input_min = 2000000,
439 .input_max = 31000000,
440 .cf_min = 1000000,
441 .cf_max = 6000000,
442 .vco_min = 200000000,
443 .vco_max = 700000000,
444 .base_reg = PLLA_BASE,
445 .misc_reg = PLLA_MISC,
446 .lock_mask = PLL_BASE_LOCK,
447 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
448 .lock_delay = 300,
449};
450
451static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
452 {12000000, 216000000, 864, 12, 2, 12},
453 {13000000, 216000000, 864, 13, 2, 12},
454 {16800000, 216000000, 720, 14, 2, 12},
455 {19200000, 216000000, 720, 16, 2, 12},
456 {26000000, 216000000, 864, 26, 2, 12},
457
458 {12000000, 594000000, 594, 12, 0, 12},
459 {13000000, 594000000, 594, 13, 0, 12},
460 {16800000, 594000000, 495, 14, 0, 12},
461 {19200000, 594000000, 495, 16, 0, 12},
462 {26000000, 594000000, 594, 26, 0, 12},
463
464 {12000000, 1000000000, 1000, 12, 0, 12},
465 {13000000, 1000000000, 1000, 13, 0, 12},
466 {19200000, 1000000000, 625, 12, 0, 12},
467 {26000000, 1000000000, 1000, 26, 0, 12},
468
469 {0, 0, 0, 0, 0, 0},
470};
471
472static struct tegra_clk_pll_params pll_d_params = {
473 .input_min = 2000000,
474 .input_max = 40000000,
475 .cf_min = 1000000,
476 .cf_max = 6000000,
477 .vco_min = 500000000,
478 .vco_max = 1000000000,
479 .base_reg = PLLD_BASE,
480 .misc_reg = PLLD_MISC,
481 .lock_mask = PLL_BASE_LOCK,
482 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
483 .lock_delay = 1000,
484};
485
486static struct tegra_clk_pll_params pll_d2_params = {
487 .input_min = 2000000,
488 .input_max = 40000000,
489 .cf_min = 1000000,
490 .cf_max = 6000000,
491 .vco_min = 500000000,
492 .vco_max = 1000000000,
493 .base_reg = PLLD2_BASE,
494 .misc_reg = PLLD2_MISC,
495 .lock_mask = PLL_BASE_LOCK,
496 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
497 .lock_delay = 1000,
498};
499
500static struct pdiv_map pllu_p[] = {
501 { .pdiv = 1, .hw_val = 1 },
502 { .pdiv = 2, .hw_val = 0 },
503 { .pdiv = 0, .hw_val = 0 },
504};
505
506static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
507 {12000000, 480000000, 960, 12, 0, 12},
508 {13000000, 480000000, 960, 13, 0, 12},
509 {16800000, 480000000, 400, 7, 0, 5},
510 {19200000, 480000000, 200, 4, 0, 3},
511 {26000000, 480000000, 960, 26, 0, 12},
512 {0, 0, 0, 0, 0, 0},
513};
514
515static struct tegra_clk_pll_params pll_u_params = {
516 .input_min = 2000000,
517 .input_max = 40000000,
518 .cf_min = 1000000,
519 .cf_max = 6000000,
520 .vco_min = 480000000,
521 .vco_max = 960000000,
522 .base_reg = PLLU_BASE,
523 .misc_reg = PLLU_MISC,
524 .lock_mask = PLL_BASE_LOCK,
525 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
526 .lock_delay = 1000,
527 .pdiv_tohw = pllu_p,
528};
529
530static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
531 /* 1 GHz */
532 {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */
533 {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */
534 {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */
535 {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */
536 {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
537
538 {0, 0, 0, 0, 0, 0},
539};
540
541static struct tegra_clk_pll_params pll_x_params = {
542 .input_min = 12000000,
543 .input_max = 800000000,
544 .cf_min = 12000000,
545 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
546 .vco_min = 700000000,
547 .vco_max = 2400000000U,
548 .base_reg = PLLX_BASE,
549 .misc_reg = PLLX_MISC,
550 .lock_mask = PLL_BASE_LOCK,
551 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
552 .lock_delay = 300,
553 .iddq_reg = PLLX_MISC3,
554 .iddq_bit_idx = PLLX_IDDQ_BIT,
555 .max_p = PLLXC_SW_MAX_P,
556 .dyn_ramp_reg = PLLX_MISC2,
557 .stepa_shift = 16,
558 .stepb_shift = 24,
559 .pdiv_tohw = pllxc_p,
560};
561
562static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
563 /* PLLE special case: use cpcon field to store cml divider value */
564 {336000000, 100000000, 100, 21, 16, 11},
565 {312000000, 100000000, 200, 26, 24, 13},
566 {0, 0, 0, 0, 0, 0},
567};
568
569static struct tegra_clk_pll_params pll_e_params = {
570 .input_min = 12000000,
571 .input_max = 1000000000,
572 .cf_min = 12000000,
573 .cf_max = 75000000,
574 .vco_min = 1600000000,
575 .vco_max = 2400000000U,
576 .base_reg = PLLE_BASE,
577 .misc_reg = PLLE_MISC,
578 .aux_reg = PLLE_AUX,
579 .lock_mask = PLLE_MISC_LOCK,
580 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
581 .lock_delay = 300,
582};
583
584static struct tegra_clk_pll_params pll_re_vco_params = {
585 .input_min = 12000000,
586 .input_max = 1000000000,
587 .cf_min = 12000000,
588 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
589 .vco_min = 300000000,
590 .vco_max = 600000000,
591 .base_reg = PLLRE_BASE,
592 .misc_reg = PLLRE_MISC,
593 .lock_mask = PLLRE_MISC_LOCK,
594 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
595 .lock_delay = 300,
596 .iddq_reg = PLLRE_MISC,
597 .iddq_bit_idx = PLLRE_IDDQ_BIT,
598};
599
600/* Peripheral clock registers */
601
602static struct tegra_clk_periph_regs periph_l_regs = {
603 .enb_reg = CLK_OUT_ENB_L,
604 .enb_set_reg = CLK_OUT_ENB_SET_L,
605 .enb_clr_reg = CLK_OUT_ENB_CLR_L,
606 .rst_reg = RST_DEVICES_L,
607 .rst_set_reg = RST_DEVICES_SET_L,
608 .rst_clr_reg = RST_DEVICES_CLR_L,
609};
610
611static struct tegra_clk_periph_regs periph_h_regs = {
612 .enb_reg = CLK_OUT_ENB_H,
613 .enb_set_reg = CLK_OUT_ENB_SET_H,
614 .enb_clr_reg = CLK_OUT_ENB_CLR_H,
615 .rst_reg = RST_DEVICES_H,
616 .rst_set_reg = RST_DEVICES_SET_H,
617 .rst_clr_reg = RST_DEVICES_CLR_H,
618};
619
620static struct tegra_clk_periph_regs periph_u_regs = {
621 .enb_reg = CLK_OUT_ENB_U,
622 .enb_set_reg = CLK_OUT_ENB_SET_U,
623 .enb_clr_reg = CLK_OUT_ENB_CLR_U,
624 .rst_reg = RST_DEVICES_U,
625 .rst_set_reg = RST_DEVICES_SET_U,
626 .rst_clr_reg = RST_DEVICES_CLR_U,
627};
628
629static struct tegra_clk_periph_regs periph_v_regs = {
630 .enb_reg = CLK_OUT_ENB_V,
631 .enb_set_reg = CLK_OUT_ENB_SET_V,
632 .enb_clr_reg = CLK_OUT_ENB_CLR_V,
633 .rst_reg = RST_DEVICES_V,
634 .rst_set_reg = RST_DEVICES_SET_V,
635 .rst_clr_reg = RST_DEVICES_CLR_V,
636};
637
638static struct tegra_clk_periph_regs periph_w_regs = {
639 .enb_reg = CLK_OUT_ENB_W,
640 .enb_set_reg = CLK_OUT_ENB_SET_W,
641 .enb_clr_reg = CLK_OUT_ENB_CLR_W,
642 .rst_reg = RST_DEVICES_W,
643 .rst_set_reg = RST_DEVICES_SET_W,
644 .rst_clr_reg = RST_DEVICES_CLR_W,
645};
646
647/* possible OSC frequencies in Hz */
648static unsigned long tegra114_input_freq[] = {
649 [0] = 13000000,
650 [1] = 16800000,
651 [4] = 19200000,
652 [5] = 38400000,
653 [8] = 12000000,
654 [9] = 48000000,
655 [12] = 260000000,
656};
657
658#define MASK(x) (BIT(x) - 1)
659
660#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
661 _clk_num, _regs, _gate_flags, _clk_id) \
662 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
663 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \
664 periph_clk_enb_refcnt, _gate_flags, _clk_id, \
665 _parents##_idx, 0)
666
667#define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
668 _clk_num, _regs, _gate_flags, _clk_id, flags)\
669 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
670 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \
671 periph_clk_enb_refcnt, _gate_flags, _clk_id, \
672 _parents##_idx, flags)
673
674#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
675 _clk_num, _regs, _gate_flags, _clk_id) \
676 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
677 29, MASK(3), 0, 0, 8, 1, 0, _regs, _clk_num, \
678 periph_clk_enb_refcnt, _gate_flags, _clk_id, \
679 _parents##_idx, 0)
680
681#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
682 _clk_num, _regs, _gate_flags, _clk_id) \
683 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
684 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
685 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
686 _clk_id, _parents##_idx, 0)
687
688#define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
689 _clk_num, _regs, _gate_flags, _clk_id, flags)\
690 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
691 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
692 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
693 _clk_id, _parents##_idx, flags)
694
695#define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\
696 _clk_num, _regs, _gate_flags, _clk_id) \
697 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
698 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
699 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
700 _clk_id, _parents##_idx, 0)
701
702#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
703 _clk_num, _regs, _clk_id) \
704 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
705 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,\
706 _clk_num, periph_clk_enb_refcnt, 0, _clk_id, \
707 _parents##_idx, 0)
708
709#define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\
710 _clk_num, _regs, _clk_id) \
711 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
712 30, MASK(2), 0, 0, 16, 0, 0, _regs, _clk_num, \
713 periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0)
714
715#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
716 _mux_shift, _mux_mask, _clk_num, _regs, \
717 _gate_flags, _clk_id) \
718 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
719 _mux_shift, _mux_mask, 0, 0, 0, 0, 0, _regs, \
720 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
721 _clk_id, _parents##_idx, 0)
722
723#define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \
724 _clk_num, _regs, _gate_flags, _clk_id) \
725 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \
726 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
727 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
728 _clk_id, _parents##_idx, 0)
729
730#define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset, _clk_num,\
731 _regs, _gate_flags, _clk_id) \
732 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \
733 _offset, 16, 0xE01F, 0, 0, 8, 1, 0, _regs, _clk_num, \
734 periph_clk_enb_refcnt, _gate_flags , _clk_id, \
735 mux_d_audio_clk_idx, 0)
736
737enum tegra114_clk {
738 rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
739 ndflash = 13, sdmmc1 = 14, sdmmc4 = 15, pwm = 17, i2s2 = 18, epp = 19,
740 gr_2d = 21, usbd = 22, isp = 23, gr_3d = 24, disp2 = 26, disp1 = 27,
741 host1x = 28, vcp = 29, i2s0 = 30, apbdma = 34, kbc = 36, kfuse = 40,
742 sbc1 = 41, nor = 42, sbc2 = 44, sbc3 = 46, i2c5 = 47, dsia = 48,
743 mipi = 50, hdmi = 51, csi = 52, i2c2 = 54, uartc = 55, mipi_cal = 56,
744 emc, usb2, usb3, vde = 61, bsea = 62, bsev = 63, uartd = 65,
745 i2c3 = 67, sbc4 = 68, sdmmc3 = 69, owr = 71, csite = 73,
746 la = 76, trace = 77, soc_therm = 78, dtv = 79, ndspeed = 80,
747 i2cslow = 81, dsib = 82, tsec = 83, xusb_host = 89, msenc = 91,
748 csus = 92, mselect = 99, tsensor = 100, i2s3 = 101, i2s4 = 102,
749 i2c4 = 103, sbc5 = 104, sbc6 = 105, d_audio, apbif = 107, dam0, dam1,
750 dam2, hda2codec_2x = 111, audio0_2x = 113, audio1_2x, audio2_2x,
751 audio3_2x, audio4_2x, spdif_2x, actmon = 119, extern1 = 120,
752 extern2 = 121, extern3 = 122, hda = 125, se = 127, hda2hdmi = 128,
753 cilab = 144, cilcd = 145, cile = 146, dsialp = 147, dsiblp = 148,
754 dds = 150, dp2 = 152, amx = 153, adx = 154, xusb_ss = 156, uartb = 192,
755 vfir, spdif_in, spdif_out, vi, vi_sensor, fuse, fuse_burn, clk_32k,
756 clk_m, clk_m_div2, clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_c2,
757 pll_c3, pll_m, pll_m_out1, pll_p, pll_p_out1, pll_p_out2, pll_p_out3,
758 pll_p_out4, pll_a, pll_a_out0, pll_d, pll_d_out0, pll_d2, pll_d2_out0,
759 pll_u, pll_u_480M, pll_u_60M, pll_u_48M, pll_u_12M, pll_x, pll_x_out0,
760 pll_re_vco, pll_re_out, pll_e_out0, spdif_in_sync, i2s0_sync,
761 i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, vimclk_sync, audio0,
762 audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3,
763 blink, xusb_host_src = 252, xusb_falcon_src, xusb_fs_src, xusb_ss_src,
764 xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp,
765
766 /* Mux clocks */
767
768 audio0_mux = 300, audio1_mux, audio2_mux, audio3_mux, audio4_mux,
769 spdif_mux, clk_out_1_mux, clk_out_2_mux, clk_out_3_mux, dsia_mux,
770 dsib_mux, clk_max,
771};
772
773struct utmi_clk_param {
774 /* Oscillator Frequency in KHz */
775 u32 osc_frequency;
776 /* UTMIP PLL Enable Delay Count */
777 u8 enable_delay_count;
778 /* UTMIP PLL Stable count */
779 u8 stable_count;
780 /* UTMIP PLL Active delay count */
781 u8 active_delay_count;
782 /* UTMIP PLL Xtal frequency count */
783 u8 xtal_freq_count;
784};
785
786static const struct utmi_clk_param utmi_parameters[] = {
787 {.osc_frequency = 13000000, .enable_delay_count = 0x02,
788 .stable_count = 0x33, .active_delay_count = 0x05,
789 .xtal_freq_count = 0x7F},
790 {.osc_frequency = 19200000, .enable_delay_count = 0x03,
791 .stable_count = 0x4B, .active_delay_count = 0x06,
792 .xtal_freq_count = 0xBB},
793 {.osc_frequency = 12000000, .enable_delay_count = 0x02,
794 .stable_count = 0x2F, .active_delay_count = 0x04,
795 .xtal_freq_count = 0x76},
796 {.osc_frequency = 26000000, .enable_delay_count = 0x04,
797 .stable_count = 0x66, .active_delay_count = 0x09,
798 .xtal_freq_count = 0xFE},
799 {.osc_frequency = 16800000, .enable_delay_count = 0x03,
800 .stable_count = 0x41, .active_delay_count = 0x0A,
801 .xtal_freq_count = 0xA4},
802};
803
804/* peripheral mux definitions */
805
806#define MUX_I2S_SPDIF(_id) \
807static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
808 #_id, "pll_p",\
809 "clk_m"};
810MUX_I2S_SPDIF(audio0)
811MUX_I2S_SPDIF(audio1)
812MUX_I2S_SPDIF(audio2)
813MUX_I2S_SPDIF(audio3)
814MUX_I2S_SPDIF(audio4)
815MUX_I2S_SPDIF(audio)
816
817#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
818#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
819#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
820#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
821#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
822#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
823
824static const char *mux_pllp_pllc_pllm_clkm[] = {
825 "pll_p", "pll_c", "pll_m", "clk_m"
826};
827#define mux_pllp_pllc_pllm_clkm_idx NULL
828
829static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
830#define mux_pllp_pllc_pllm_idx NULL
831
832static const char *mux_pllp_pllc_clk32_clkm[] = {
833 "pll_p", "pll_c", "clk_32k", "clk_m"
834};
835#define mux_pllp_pllc_clk32_clkm_idx NULL
836
837static const char *mux_plla_pllc_pllp_clkm[] = {
838 "pll_a_out0", "pll_c", "pll_p", "clk_m"
839};
840#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
841
842static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
843 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
844};
845static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
846 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
847};
848
849static const char *mux_pllp_clkm[] = {
850 "pll_p", "clk_m"
851};
852static u32 mux_pllp_clkm_idx[] = {
853 [0] = 0, [1] = 3,
854};
855
856static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
857 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
858};
859#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
860
861static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
862 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
863 "pll_d2_out0", "clk_m"
864};
865#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
866
867static const char *mux_pllm_pllc_pllp_plla[] = {
868 "pll_m", "pll_c", "pll_p", "pll_a_out0"
869};
870#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
871
872static const char *mux_pllp_pllc_clkm[] = {
873 "pll_p", "pll_c", "pll_m"
874};
875static u32 mux_pllp_pllc_clkm_idx[] = {
876 [0] = 0, [1] = 1, [2] = 3,
877};
878
879static const char *mux_pllp_pllc_clkm_clk32[] = {
880 "pll_p", "pll_c", "clk_m", "clk_32k"
881};
882#define mux_pllp_pllc_clkm_clk32_idx NULL
883
884static const char *mux_plla_clk32_pllp_clkm_plle[] = {
885 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
886};
887#define mux_plla_clk32_pllp_clkm_plle_idx NULL
888
889static const char *mux_clkm_pllp_pllc_pllre[] = {
890 "clk_m", "pll_p", "pll_c", "pll_re_out"
891};
892static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
893 [0] = 0, [1] = 1, [2] = 3, [3] = 5,
894};
895
896static const char *mux_clkm_48M_pllp_480M[] = {
897 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
898};
899#define mux_clkm_48M_pllp_480M_idx NULL
900
901static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
902 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
903};
904static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
905 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
906};
907
908static const char *mux_plld_out0_plld2_out0[] = {
909 "pll_d_out0", "pll_d2_out0",
910};
911#define mux_plld_out0_plld2_out0_idx NULL
912
913static const char *mux_d_audio_clk[] = {
914 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
915 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
916};
917static u32 mux_d_audio_clk_idx[] = {
918 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
919 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
920};
921
922static const char *mux_pllmcp_clkm[] = {
923 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
924};
925
926static const struct clk_div_table pll_re_div_table[] = {
927 { .val = 0, .div = 1 },
928 { .val = 1, .div = 2 },
929 { .val = 2, .div = 3 },
930 { .val = 3, .div = 4 },
931 { .val = 4, .div = 5 },
932 { .val = 5, .div = 6 },
933 { .val = 0, .div = 0 },
934};
935
936static struct clk *clks[clk_max];
937static struct clk_onecell_data clk_data;
938
939static unsigned long osc_freq;
940static unsigned long pll_ref_freq;
941
942static int __init tegra114_osc_clk_init(void __iomem *clk_base)
943{
944 struct clk *clk;
945 u32 val, pll_ref_div;
946
947 val = readl_relaxed(clk_base + OSC_CTRL);
948
949 osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT];
950 if (!osc_freq) {
951 WARN_ON(1);
952 return -EINVAL;
953 }
954
955 /* clk_m */
956 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
957 osc_freq);
958 clk_register_clkdev(clk, "clk_m", NULL);
959 clks[clk_m] = clk;
960
961 /* pll_ref */
962 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
963 pll_ref_div = 1 << val;
964 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
965 CLK_SET_RATE_PARENT, 1, pll_ref_div);
966 clk_register_clkdev(clk, "pll_ref", NULL);
967 clks[pll_ref] = clk;
968
969 pll_ref_freq = osc_freq / pll_ref_div;
970
971 return 0;
972}
973
974static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
975{
976 struct clk *clk;
977
978 /* clk_32k */
979 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
980 32768);
981 clk_register_clkdev(clk, "clk_32k", NULL);
982 clks[clk_32k] = clk;
983
984 /* clk_m_div2 */
985 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
986 CLK_SET_RATE_PARENT, 1, 2);
987 clk_register_clkdev(clk, "clk_m_div2", NULL);
988 clks[clk_m_div2] = clk;
989
990 /* clk_m_div4 */
991 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
992 CLK_SET_RATE_PARENT, 1, 4);
993 clk_register_clkdev(clk, "clk_m_div4", NULL);
994 clks[clk_m_div4] = clk;
995
996}
997
998static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
999{
1000 u32 reg;
1001 int i;
1002
1003 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1004 if (osc_freq == utmi_parameters[i].osc_frequency)
1005 break;
1006 }
1007
1008 if (i >= ARRAY_SIZE(utmi_parameters)) {
1009 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
1010 osc_freq);
1011 return;
1012 }
1013
1014 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1015
1016 /* Program UTMIP PLL stable and active counts */
1017 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1018 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1019 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1020
1021 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1022
1023 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1024 active_delay_count);
1025
1026 /* Remove power downs from UTMIP PLL control bits */
1027 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1028 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1029 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1030
1031 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1032
1033 /* Program UTMIP PLL delay and oscillator frequency counts */
1034 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1035 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1036
1037 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1038 enable_delay_count);
1039
1040 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1041 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1042 xtal_freq_count);
1043
1044 /* Remove power downs from UTMIP PLL control bits */
1045 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1046 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1047 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1048 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1049 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1050
1051 /* Setup HW control of UTMIPLL */
1052 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1053 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1054 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1055 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1056 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1057
1058 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1059 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1060 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1061 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1062
1063 udelay(1);
1064
1065 /* Setup SW override of UTMIPLL assuming USB2.0
1066 ports are assigned to USB2 */
1067 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1068 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1069 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1070 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1071
1072 udelay(1);
1073
1074 /* Enable HW control UTMIPLL */
1075 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1076 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1077 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1078}
1079
1080static void __init _clip_vco_min(struct tegra_clk_pll_params *pll_params)
1081{
1082 pll_params->vco_min =
1083 DIV_ROUND_UP(pll_params->vco_min, pll_ref_freq) * pll_ref_freq;
1084}
1085
1086static int __init _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1087 void __iomem *clk_base)
1088{
1089 u32 val;
1090 u32 step_a, step_b;
1091
1092 switch (pll_ref_freq) {
1093 case 12000000:
1094 case 13000000:
1095 case 26000000:
1096 step_a = 0x2B;
1097 step_b = 0x0B;
1098 break;
1099 case 16800000:
1100 step_a = 0x1A;
1101 step_b = 0x09;
1102 break;
1103 case 19200000:
1104 step_a = 0x12;
1105 step_b = 0x08;
1106 break;
1107 default:
1108 pr_err("%s: Unexpected reference rate %lu\n",
1109 __func__, pll_ref_freq);
1110 WARN_ON(1);
1111 return -EINVAL;
1112 }
1113
1114 val = step_a << pll_params->stepa_shift;
1115 val |= step_b << pll_params->stepb_shift;
1116 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1117
1118 return 0;
1119}
1120
1121static void __init _init_iddq(struct tegra_clk_pll_params *pll_params,
1122 void __iomem *clk_base)
1123{
1124 u32 val, val_iddq;
1125
1126 val = readl_relaxed(clk_base + pll_params->base_reg);
1127 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1128
1129 if (val & BIT(30))
1130 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1131 else {
1132 val_iddq |= BIT(pll_params->iddq_bit_idx);
1133 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1134 }
1135}
1136
1137static void __init tegra114_pll_init(void __iomem *clk_base,
1138 void __iomem *pmc)
1139{
1140 u32 val;
1141 struct clk *clk;
1142
1143 /* PLLC */
1144 _clip_vco_min(&pll_c_params);
1145 if (_setup_dynamic_ramp(&pll_c_params, clk_base) >= 0) {
1146 _init_iddq(&pll_c_params, clk_base);
1147 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1148 pmc, 0, 0, &pll_c_params, TEGRA_PLL_USE_LOCK,
1149 pll_c_freq_table, NULL);
1150 clk_register_clkdev(clk, "pll_c", NULL);
1151 clks[pll_c] = clk;
1152
1153 /* PLLC_OUT1 */
1154 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1155 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1156 8, 8, 1, NULL);
1157 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1158 clk_base + PLLC_OUT, 1, 0,
1159 CLK_SET_RATE_PARENT, 0, NULL);
1160 clk_register_clkdev(clk, "pll_c_out1", NULL);
1161 clks[pll_c_out1] = clk;
1162 }
1163
1164 /* PLLC2 */
1165 _clip_vco_min(&pll_c2_params);
1166 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 0,
1167 &pll_c2_params, TEGRA_PLL_USE_LOCK,
1168 pll_cx_freq_table, NULL);
1169 clk_register_clkdev(clk, "pll_c2", NULL);
1170 clks[pll_c2] = clk;
1171
1172 /* PLLC3 */
1173 _clip_vco_min(&pll_c3_params);
1174 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 0,
1175 &pll_c3_params, TEGRA_PLL_USE_LOCK,
1176 pll_cx_freq_table, NULL);
1177 clk_register_clkdev(clk, "pll_c3", NULL);
1178 clks[pll_c3] = clk;
1179
1180 /* PLLP */
1181 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc, 0,
1182 408000000, &pll_p_params,
1183 TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
1184 pll_p_freq_table, NULL);
1185 clk_register_clkdev(clk, "pll_p", NULL);
1186 clks[pll_p] = clk;
1187
1188 /* PLLP_OUT1 */
1189 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
1190 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
1191 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
1192 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
1193 clk_base + PLLP_OUTA, 1, 0,
1194 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1195 &pll_div_lock);
1196 clk_register_clkdev(clk, "pll_p_out1", NULL);
1197 clks[pll_p_out1] = clk;
1198
1199 /* PLLP_OUT2 */
1200 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
1201 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
1202 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
1203 &pll_div_lock);
1204 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
1205 clk_base + PLLP_OUTA, 17, 16,
1206 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1207 &pll_div_lock);
1208 clk_register_clkdev(clk, "pll_p_out2", NULL);
1209 clks[pll_p_out2] = clk;
1210
1211 /* PLLP_OUT3 */
1212 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
1213 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
1214 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
1215 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
1216 clk_base + PLLP_OUTB, 1, 0,
1217 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1218 &pll_div_lock);
1219 clk_register_clkdev(clk, "pll_p_out3", NULL);
1220 clks[pll_p_out3] = clk;
1221
1222 /* PLLP_OUT4 */
1223 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
1224 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
1225 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
1226 &pll_div_lock);
1227 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
1228 clk_base + PLLP_OUTB, 17, 16,
1229 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1230 &pll_div_lock);
1231 clk_register_clkdev(clk, "pll_p_out4", NULL);
1232 clks[pll_p_out4] = clk;
1233
1234 /* PLLM */
1235 _clip_vco_min(&pll_m_params);
1236 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1237 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
1238 &pll_m_params, TEGRA_PLL_USE_LOCK,
1239 pll_m_freq_table, NULL);
1240 clk_register_clkdev(clk, "pll_m", NULL);
1241 clks[pll_m] = clk;
1242
1243 /* PLLM_OUT1 */
1244 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1245 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1246 8, 8, 1, NULL);
1247 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1248 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1249 CLK_SET_RATE_PARENT, 0, NULL);
1250 clk_register_clkdev(clk, "pll_m_out1", NULL);
1251 clks[pll_m_out1] = clk;
1252
1253 /* PLLM_UD */
1254 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1255 CLK_SET_RATE_PARENT, 1, 1);
1256
1257 /* PLLX */
1258 _clip_vco_min(&pll_x_params);
1259 if (_setup_dynamic_ramp(&pll_x_params, clk_base) >= 0) {
1260 _init_iddq(&pll_x_params, clk_base);
1261 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
1262 pmc, CLK_IGNORE_UNUSED, 0, &pll_x_params,
1263 TEGRA_PLL_USE_LOCK, pll_x_freq_table, NULL);
1264 clk_register_clkdev(clk, "pll_x", NULL);
1265 clks[pll_x] = clk;
1266 }
1267
1268 /* PLLX_OUT0 */
1269 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
1270 CLK_SET_RATE_PARENT, 1, 2);
1271 clk_register_clkdev(clk, "pll_x_out0", NULL);
1272 clks[pll_x_out0] = clk;
1273
1274 /* PLLU */
1275 val = readl(clk_base + pll_u_params.base_reg);
1276 val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1277 writel(val, clk_base + pll_u_params.base_reg);
1278
1279 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1280 0, &pll_u_params, TEGRA_PLLU |
1281 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
1282 TEGRA_PLL_USE_LOCK, pll_u_freq_table, &pll_u_lock);
1283 clk_register_clkdev(clk, "pll_u", NULL);
1284 clks[pll_u] = clk;
1285
1286 tegra114_utmi_param_configure(clk_base);
1287
1288 /* PLLU_480M */
1289 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1290 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1291 22, 0, &pll_u_lock);
1292 clk_register_clkdev(clk, "pll_u_480M", NULL);
1293 clks[pll_u_480M] = clk;
1294
1295 /* PLLU_60M */
1296 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1297 CLK_SET_RATE_PARENT, 1, 8);
1298 clk_register_clkdev(clk, "pll_u_60M", NULL);
1299 clks[pll_u_60M] = clk;
1300
1301 /* PLLU_48M */
1302 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1303 CLK_SET_RATE_PARENT, 1, 10);
1304 clk_register_clkdev(clk, "pll_u_48M", NULL);
1305 clks[pll_u_48M] = clk;
1306
1307 /* PLLU_12M */
1308 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1309 CLK_SET_RATE_PARENT, 1, 40);
1310 clk_register_clkdev(clk, "pll_u_12M", NULL);
1311 clks[pll_u_12M] = clk;
1312
1313 /* PLLD */
1314 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1315 0, &pll_d_params,
1316 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
1317 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d_lock);
1318 clk_register_clkdev(clk, "pll_d", NULL);
1319 clks[pll_d] = clk;
1320
1321 /* PLLD_OUT0 */
1322 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1323 CLK_SET_RATE_PARENT, 1, 2);
1324 clk_register_clkdev(clk, "pll_d_out0", NULL);
1325 clks[pll_d_out0] = clk;
1326
1327 /* PLLD2 */
1328 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
1329 0, &pll_d2_params,
1330 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
1331 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d2_lock);
1332 clk_register_clkdev(clk, "pll_d2", NULL);
1333 clks[pll_d2] = clk;
1334
1335 /* PLLD2_OUT0 */
1336 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1337 CLK_SET_RATE_PARENT, 1, 2);
1338 clk_register_clkdev(clk, "pll_d2_out0", NULL);
1339 clks[pll_d2_out0] = clk;
1340
1341 /* PLLA */
1342 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc, 0,
1343 0, &pll_a_params, TEGRA_PLL_HAS_CPCON |
1344 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL);
1345 clk_register_clkdev(clk, "pll_a", NULL);
1346 clks[pll_a] = clk;
1347
1348 /* PLLA_OUT0 */
1349 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
1350 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1351 8, 8, 1, NULL);
1352 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
1353 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
1354 CLK_SET_RATE_PARENT, 0, NULL);
1355 clk_register_clkdev(clk, "pll_a_out0", NULL);
1356 clks[pll_a_out0] = clk;
1357
1358 /* PLLRE */
1359 _clip_vco_min(&pll_re_vco_params);
1360 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1361 0, 0, &pll_re_vco_params, TEGRA_PLL_USE_LOCK,
1362 NULL, &pll_re_lock, pll_ref_freq);
1363 clk_register_clkdev(clk, "pll_re_vco", NULL);
1364 clks[pll_re_vco] = clk;
1365
1366 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1367 clk_base + PLLRE_BASE, 16, 4, 0,
1368 pll_re_div_table, &pll_re_lock);
1369 clk_register_clkdev(clk, "pll_re_out", NULL);
1370 clks[pll_re_out] = clk;
1371
1372 /* PLLE */
1373 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_re_vco",
1374 clk_base, 0, 100000000, &pll_e_params,
1375 pll_e_freq_table, NULL);
1376 clk_register_clkdev(clk, "pll_e_out0", NULL);
1377 clks[pll_e_out0] = clk;
1378}
1379
1380static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
1381 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
1382};
1383
1384static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
1385 "clk_m_div4", "extern1",
1386};
1387
1388static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
1389 "clk_m_div4", "extern2",
1390};
1391
1392static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
1393 "clk_m_div4", "extern3",
1394};
1395
1396static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1397{
1398 struct clk *clk;
1399
1400 /* spdif_in_sync */
1401 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
1402 24000000);
1403 clk_register_clkdev(clk, "spdif_in_sync", NULL);
1404 clks[spdif_in_sync] = clk;
1405
1406 /* i2s0_sync */
1407 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
1408 clk_register_clkdev(clk, "i2s0_sync", NULL);
1409 clks[i2s0_sync] = clk;
1410
1411 /* i2s1_sync */
1412 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
1413 clk_register_clkdev(clk, "i2s1_sync", NULL);
1414 clks[i2s1_sync] = clk;
1415
1416 /* i2s2_sync */
1417 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
1418 clk_register_clkdev(clk, "i2s2_sync", NULL);
1419 clks[i2s2_sync] = clk;
1420
1421 /* i2s3_sync */
1422 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
1423 clk_register_clkdev(clk, "i2s3_sync", NULL);
1424 clks[i2s3_sync] = clk;
1425
1426 /* i2s4_sync */
1427 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
1428 clk_register_clkdev(clk, "i2s4_sync", NULL);
1429 clks[i2s4_sync] = clk;
1430
1431 /* vimclk_sync */
1432 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
1433 clk_register_clkdev(clk, "vimclk_sync", NULL);
1434 clks[vimclk_sync] = clk;
1435
1436 /* audio0 */
1437 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1438 ARRAY_SIZE(mux_audio_sync_clk), 0,
1439 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0,
1440 NULL);
1441 clks[audio0_mux] = clk;
1442 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1443 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
1444 CLK_GATE_SET_TO_DISABLE, NULL);
1445 clk_register_clkdev(clk, "audio0", NULL);
1446 clks[audio0] = clk;
1447
1448 /* audio1 */
1449 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1450 ARRAY_SIZE(mux_audio_sync_clk), 0,
1451 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0,
1452 NULL);
1453 clks[audio1_mux] = clk;
1454 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1455 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
1456 CLK_GATE_SET_TO_DISABLE, NULL);
1457 clk_register_clkdev(clk, "audio1", NULL);
1458 clks[audio1] = clk;
1459
1460 /* audio2 */
1461 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1462 ARRAY_SIZE(mux_audio_sync_clk), 0,
1463 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0,
1464 NULL);
1465 clks[audio2_mux] = clk;
1466 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1467 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
1468 CLK_GATE_SET_TO_DISABLE, NULL);
1469 clk_register_clkdev(clk, "audio2", NULL);
1470 clks[audio2] = clk;
1471
1472 /* audio3 */
1473 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1474 ARRAY_SIZE(mux_audio_sync_clk), 0,
1475 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0,
1476 NULL);
1477 clks[audio3_mux] = clk;
1478 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1479 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
1480 CLK_GATE_SET_TO_DISABLE, NULL);
1481 clk_register_clkdev(clk, "audio3", NULL);
1482 clks[audio3] = clk;
1483
1484 /* audio4 */
1485 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1486 ARRAY_SIZE(mux_audio_sync_clk), 0,
1487 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0,
1488 NULL);
1489 clks[audio4_mux] = clk;
1490 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1491 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
1492 CLK_GATE_SET_TO_DISABLE, NULL);
1493 clk_register_clkdev(clk, "audio4", NULL);
1494 clks[audio4] = clk;
1495
1496 /* spdif */
1497 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1498 ARRAY_SIZE(mux_audio_sync_clk), 0,
1499 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0,
1500 NULL);
1501 clks[spdif_mux] = clk;
1502 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1503 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
1504 CLK_GATE_SET_TO_DISABLE, NULL);
1505 clk_register_clkdev(clk, "spdif", NULL);
1506 clks[spdif] = clk;
1507
1508 /* audio0_2x */
1509 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
1510 CLK_SET_RATE_PARENT, 2, 1);
1511 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
1512 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1,
1513 0, &clk_doubler_lock);
1514 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1515 TEGRA_PERIPH_NO_RESET, clk_base,
1516 CLK_SET_RATE_PARENT, 113, &periph_v_regs,
1517 periph_clk_enb_refcnt);
1518 clk_register_clkdev(clk, "audio0_2x", NULL);
1519 clks[audio0_2x] = clk;
1520
1521 /* audio1_2x */
1522 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
1523 CLK_SET_RATE_PARENT, 2, 1);
1524 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
1525 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1,
1526 0, &clk_doubler_lock);
1527 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1528 TEGRA_PERIPH_NO_RESET, clk_base,
1529 CLK_SET_RATE_PARENT, 114, &periph_v_regs,
1530 periph_clk_enb_refcnt);
1531 clk_register_clkdev(clk, "audio1_2x", NULL);
1532 clks[audio1_2x] = clk;
1533
1534 /* audio2_2x */
1535 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
1536 CLK_SET_RATE_PARENT, 2, 1);
1537 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
1538 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1,
1539 0, &clk_doubler_lock);
1540 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1541 TEGRA_PERIPH_NO_RESET, clk_base,
1542 CLK_SET_RATE_PARENT, 115, &periph_v_regs,
1543 periph_clk_enb_refcnt);
1544 clk_register_clkdev(clk, "audio2_2x", NULL);
1545 clks[audio2_2x] = clk;
1546
1547 /* audio3_2x */
1548 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
1549 CLK_SET_RATE_PARENT, 2, 1);
1550 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
1551 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1,
1552 0, &clk_doubler_lock);
1553 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1554 TEGRA_PERIPH_NO_RESET, clk_base,
1555 CLK_SET_RATE_PARENT, 116, &periph_v_regs,
1556 periph_clk_enb_refcnt);
1557 clk_register_clkdev(clk, "audio3_2x", NULL);
1558 clks[audio3_2x] = clk;
1559
1560 /* audio4_2x */
1561 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
1562 CLK_SET_RATE_PARENT, 2, 1);
1563 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
1564 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1,
1565 0, &clk_doubler_lock);
1566 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1567 TEGRA_PERIPH_NO_RESET, clk_base,
1568 CLK_SET_RATE_PARENT, 117, &periph_v_regs,
1569 periph_clk_enb_refcnt);
1570 clk_register_clkdev(clk, "audio4_2x", NULL);
1571 clks[audio4_2x] = clk;
1572
1573 /* spdif_2x */
1574 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
1575 CLK_SET_RATE_PARENT, 2, 1);
1576 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
1577 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1,
1578 0, &clk_doubler_lock);
1579 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1580 TEGRA_PERIPH_NO_RESET, clk_base,
1581 CLK_SET_RATE_PARENT, 118,
1582 &periph_v_regs, periph_clk_enb_refcnt);
1583 clk_register_clkdev(clk, "spdif_2x", NULL);
1584 clks[spdif_2x] = clk;
1585}
1586
1587static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1588{
1589 struct clk *clk;
1590
1591 /* clk_out_1 */
1592 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1593 ARRAY_SIZE(clk_out1_parents), 0,
1594 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1595 &clk_out_lock);
1596 clks[clk_out_1_mux] = clk;
1597 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
1598 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
1599 &clk_out_lock);
1600 clk_register_clkdev(clk, "extern1", "clk_out_1");
1601 clks[clk_out_1] = clk;
1602
1603 /* clk_out_2 */
1604 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1605 ARRAY_SIZE(clk_out1_parents), 0,
1606 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1607 &clk_out_lock);
1608 clks[clk_out_2_mux] = clk;
1609 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
1610 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
1611 &clk_out_lock);
1612 clk_register_clkdev(clk, "extern2", "clk_out_2");
1613 clks[clk_out_2] = clk;
1614
1615 /* clk_out_3 */
1616 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1617 ARRAY_SIZE(clk_out1_parents), 0,
1618 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1619 &clk_out_lock);
1620 clks[clk_out_3_mux] = clk;
1621 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
1622 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
1623 &clk_out_lock);
1624 clk_register_clkdev(clk, "extern3", "clk_out_3");
1625 clks[clk_out_3] = clk;
1626
1627 /* blink */
1628 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1629 pmc_base + PMC_DPD_PADS_ORIDE,
1630 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1631 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1632 pmc_base + PMC_CTRL,
1633 PMC_CTRL_BLINK_ENB, 0, NULL);
1634 clk_register_clkdev(clk, "blink", NULL);
1635 clks[blink] = clk;
1636
1637}
1638
1639static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
1640 "pll_p_out3", "pll_p_out2", "unused",
1641 "clk_32k", "pll_m_out1" };
1642
1643static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1644 "pll_p", "pll_p_out4", "unused",
1645 "unused", "pll_x" };
1646
1647static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1648 "pll_p", "pll_p_out4", "unused",
1649 "unused", "pll_x", "pll_x_out0" };
1650
1651static void __init tegra114_super_clk_init(void __iomem *clk_base)
1652{
1653 struct clk *clk;
1654
1655 /* CCLKG */
1656 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
1657 ARRAY_SIZE(cclk_g_parents),
1658 CLK_SET_RATE_PARENT,
1659 clk_base + CCLKG_BURST_POLICY,
1660 0, 4, 0, 0, NULL);
1661 clk_register_clkdev(clk, "cclk_g", NULL);
1662 clks[cclk_g] = clk;
1663
1664 /* CCLKLP */
1665 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1666 ARRAY_SIZE(cclk_lp_parents),
1667 CLK_SET_RATE_PARENT,
1668 clk_base + CCLKLP_BURST_POLICY,
1669 0, 4, 8, 9, NULL);
1670 clk_register_clkdev(clk, "cclk_lp", NULL);
1671 clks[cclk_lp] = clk;
1672
1673 /* SCLK */
1674 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1675 ARRAY_SIZE(sclk_parents),
1676 CLK_SET_RATE_PARENT,
1677 clk_base + SCLK_BURST_POLICY,
1678 0, 4, 0, 0, NULL);
1679 clk_register_clkdev(clk, "sclk", NULL);
1680 clks[sclk] = clk;
1681
1682 /* HCLK */
1683 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
1684 clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
1685 &sysrate_lock);
1686 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT |
1687 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
1688 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1689 clk_register_clkdev(clk, "hclk", NULL);
1690 clks[hclk] = clk;
1691
1692 /* PCLK */
1693 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
1694 clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
1695 &sysrate_lock);
1696 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
1697 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
1698 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1699 clk_register_clkdev(clk, "pclk", NULL);
1700 clks[pclk] = clk;
1701}
1702
1703static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1704 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0),
1705 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
1706 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
1707 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3),
1708 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4),
1709 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
1710 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
1711 TEGRA_INIT_DATA_MUX("pwm", NULL, "pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, &periph_l_regs, TEGRA_PERIPH_ON_APB, pwm),
1712 TEGRA_INIT_DATA_MUX("adx", NULL, "adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, &periph_w_regs, TEGRA_PERIPH_ON_APB, adx),
1713 TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, amx),
1714 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda),
1715 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda2codec_2x),
1716 TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
1717 TEGRA_INIT_DATA_MUX("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
1718 TEGRA_INIT_DATA_MUX("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
1719 TEGRA_INIT_DATA_MUX("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
1720 TEGRA_INIT_DATA_MUX("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
1721 TEGRA_INIT_DATA_MUX("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
1722 TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1723 TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1724 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
1725 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
1726 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
1727 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
1728 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
1729 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
1730 TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite, CLK_IGNORE_UNUSED),
1731 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
1732 TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, trace),
1733 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
1734 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
1735 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
1736 TEGRA_INIT_DATA_I2C("i2c1", "div-clk", "tegra11-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, i2c1),
1737 TEGRA_INIT_DATA_I2C("i2c2", "div-clk", "tegra11-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, i2c2),
1738 TEGRA_INIT_DATA_I2C("i2c3", "div-clk", "tegra11-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, i2c3),
1739 TEGRA_INIT_DATA_I2C("i2c4", "div-clk", "tegra11-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, i2c4),
1740 TEGRA_INIT_DATA_I2C("i2c5", "div-clk", "tegra11-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, i2c5),
1741 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta),
1742 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb),
1743 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc),
1744 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd),
1745 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, gr_3d),
1746 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr_2d),
1747 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
1748 TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
1749 TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
1750 TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_h_regs, TEGRA_PERIPH_WAR_1005168, msenc),
1751 TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, tsec),
1752 TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
1753 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
1754 TEGRA_INIT_DATA_MUX("cilab", "cilab", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, &periph_w_regs, 0, cilab),
1755 TEGRA_INIT_DATA_MUX("cilcd", "cilcd", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, &periph_w_regs, 0, cilcd),
1756 TEGRA_INIT_DATA_MUX("cile", "cile", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, &periph_w_regs, 0, cile),
1757 TEGRA_INIT_DATA_MUX("dsialp", "dsialp", "tegradc.0", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, &periph_w_regs, 0, dsialp),
1758 TEGRA_INIT_DATA_MUX("dsiblp", "dsiblp", "tegradc.1", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, &periph_w_regs, 0, dsiblp),
1759 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor),
1760 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon),
1761 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1),
1762 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2),
1763 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3),
1764 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
1765 TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, TEGRA_PERIPH_ON_APB, se),
1766 TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect, CLK_IGNORE_UNUSED),
1767 TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, &periph_u_regs, TEGRA_PERIPH_ON_APB, soc_therm),
1768 TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, &periph_w_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_host_src),
1769 TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_falcon_src),
1770 TEGRA_INIT_DATA_XUSB("xusb_fs_src", "fs_src", "tegra_xhci", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_fs_src),
1771 TEGRA_INIT_DATA_XUSB("xusb_ss_src", "ss_src", "tegra_xhci", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_ss_src),
1772 TEGRA_INIT_DATA_XUSB("xusb_dev_src", "dev_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, &periph_u_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_dev_src),
1773 TEGRA_INIT_DATA_AUDIO("d_audio", "d_audio", "tegra30-ahub", CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, TEGRA_PERIPH_ON_APB, d_audio),
1774 TEGRA_INIT_DATA_AUDIO("dam0", NULL, "tegra30-dam.0", CLK_SOURCE_DAM0, 108, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam0),
1775 TEGRA_INIT_DATA_AUDIO("dam1", NULL, "tegra30-dam.1", CLK_SOURCE_DAM1, 109, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam1),
1776 TEGRA_INIT_DATA_AUDIO("dam2", NULL, "tegra30-dam.2", CLK_SOURCE_DAM2, 110, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam2),
1777};
1778
1779static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1780 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, &periph_l_regs, 0, disp1),
1781 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, &periph_l_regs, 0, disp2),
1782};
1783
1784static __init void tegra114_periph_clk_init(void __iomem *clk_base)
1785{
1786 struct tegra_periph_init_data *data;
1787 struct clk *clk;
1788 int i;
1789 u32 val;
1790
1791 /* apbdma */
1792 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base,
1793 0, 34, &periph_h_regs,
1794 periph_clk_enb_refcnt);
1795 clks[apbdma] = clk;
1796
1797 /* rtc */
1798 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1799 TEGRA_PERIPH_ON_APB |
1800 TEGRA_PERIPH_NO_RESET, clk_base,
1801 0, 4, &periph_l_regs,
1802 periph_clk_enb_refcnt);
1803 clk_register_clkdev(clk, NULL, "rtc-tegra");
1804 clks[rtc] = clk;
1805
1806 /* kbc */
1807 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1808 TEGRA_PERIPH_ON_APB |
1809 TEGRA_PERIPH_NO_RESET, clk_base,
1810 0, 36, &periph_h_regs,
1811 periph_clk_enb_refcnt);
1812 clks[kbc] = clk;
1813
1814 /* timer */
1815 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
1816 0, 5, &periph_l_regs,
1817 periph_clk_enb_refcnt);
1818 clk_register_clkdev(clk, NULL, "timer");
1819 clks[timer] = clk;
1820
1821 /* kfuse */
1822 clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1823 TEGRA_PERIPH_ON_APB, clk_base, 0, 40,
1824 &periph_h_regs, periph_clk_enb_refcnt);
1825 clks[kfuse] = clk;
1826
1827 /* fuse */
1828 clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1829 TEGRA_PERIPH_ON_APB, clk_base, 0, 39,
1830 &periph_h_regs, periph_clk_enb_refcnt);
1831 clks[fuse] = clk;
1832
1833 /* fuse_burn */
1834 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1835 TEGRA_PERIPH_ON_APB, clk_base, 0, 39,
1836 &periph_h_regs, periph_clk_enb_refcnt);
1837 clks[fuse_burn] = clk;
1838
1839 /* apbif */
1840 clk = tegra_clk_register_periph_gate("apbif", "clk_m",
1841 TEGRA_PERIPH_ON_APB, clk_base, 0, 107,
1842 &periph_v_regs, periph_clk_enb_refcnt);
1843 clks[apbif] = clk;
1844
1845 /* hda2hdmi */
1846 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1847 TEGRA_PERIPH_ON_APB, clk_base, 0, 128,
1848 &periph_w_regs, periph_clk_enb_refcnt);
1849 clks[hda2hdmi] = clk;
1850
1851 /* vcp */
1852 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0,
1853 29, &periph_l_regs,
1854 periph_clk_enb_refcnt);
1855 clks[vcp] = clk;
1856
1857 /* bsea */
1858 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base,
1859 0, 62, &periph_h_regs,
1860 periph_clk_enb_refcnt);
1861 clks[bsea] = clk;
1862
1863 /* bsev */
1864 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base,
1865 0, 63, &periph_h_regs,
1866 periph_clk_enb_refcnt);
1867 clks[bsev] = clk;
1868
1869 /* mipi-cal */
1870 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
1871 0, 56, &periph_h_regs,
1872 periph_clk_enb_refcnt);
1873 clks[mipi_cal] = clk;
1874
1875 /* usbd */
1876 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base,
1877 0, 22, &periph_l_regs,
1878 periph_clk_enb_refcnt);
1879 clks[usbd] = clk;
1880
1881 /* usb2 */
1882 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base,
1883 0, 58, &periph_h_regs,
1884 periph_clk_enb_refcnt);
1885 clks[usb2] = clk;
1886
1887 /* usb3 */
1888 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base,
1889 0, 59, &periph_h_regs,
1890 periph_clk_enb_refcnt);
1891 clks[usb3] = clk;
1892
1893 /* csi */
1894 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
1895 0, 52, &periph_h_regs,
1896 periph_clk_enb_refcnt);
1897 clks[csi] = clk;
1898
1899 /* isp */
1900 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0,
1901 23, &periph_l_regs,
1902 periph_clk_enb_refcnt);
1903 clks[isp] = clk;
1904
1905 /* csus */
1906 clk = tegra_clk_register_periph_gate("csus", "clk_m",
1907 TEGRA_PERIPH_NO_RESET, clk_base, 0, 92,
1908 &periph_u_regs, periph_clk_enb_refcnt);
1909 clks[csus] = clk;
1910
1911 /* dds */
1912 clk = tegra_clk_register_periph_gate("dds", "clk_m",
1913 TEGRA_PERIPH_ON_APB, clk_base, 0, 150,
1914 &periph_w_regs, periph_clk_enb_refcnt);
1915 clks[dds] = clk;
1916
1917 /* dp2 */
1918 clk = tegra_clk_register_periph_gate("dp2", "clk_m",
1919 TEGRA_PERIPH_ON_APB, clk_base, 0, 152,
1920 &periph_w_regs, periph_clk_enb_refcnt);
1921 clks[dp2] = clk;
1922
1923 /* dtv */
1924 clk = tegra_clk_register_periph_gate("dtv", "clk_m",
1925 TEGRA_PERIPH_ON_APB, clk_base, 0, 79,
1926 &periph_u_regs, periph_clk_enb_refcnt);
1927 clks[dtv] = clk;
1928
1929 /* dsia */
1930 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1931 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
1932 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1933 clks[dsia_mux] = clk;
1934 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
1935 0, 48, &periph_h_regs,
1936 periph_clk_enb_refcnt);
1937 clks[dsia] = clk;
1938
1939 /* dsib */
1940 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
1941 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
1942 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1943 clks[dsib_mux] = clk;
1944 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
1945 0, 82, &periph_u_regs,
1946 periph_clk_enb_refcnt);
1947 clks[dsib] = clk;
1948
1949 /* xusb_hs_src */
1950 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
1951 val |= BIT(25); /* always select PLLU_60M */
1952 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
1953
1954 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
1955 1, 1);
1956 clks[xusb_hs_src] = clk;
1957
1958 /* xusb_host */
1959 clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0,
1960 clk_base, 0, 89, &periph_u_regs,
1961 periph_clk_enb_refcnt);
1962 clks[xusb_host] = clk;
1963
1964 /* xusb_ss */
1965 clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0,
1966 clk_base, 0, 156, &periph_w_regs,
1967 periph_clk_enb_refcnt);
1968 clks[xusb_host] = clk;
1969
1970 /* xusb_dev */
1971 clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0,
1972 clk_base, 0, 95, &periph_u_regs,
1973 periph_clk_enb_refcnt);
1974 clks[xusb_dev] = clk;
1975
1976 /* emc */
1977 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1978 ARRAY_SIZE(mux_pllmcp_clkm), 0,
1979 clk_base + CLK_SOURCE_EMC,
1980 29, 3, 0, NULL);
1981 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base,
1982 CLK_IGNORE_UNUSED, 57, &periph_h_regs,
1983 periph_clk_enb_refcnt);
1984 clks[emc] = clk;
1985
1986 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1987 data = &tegra_periph_clk_list[i];
1988 clk = tegra_clk_register_periph(data->name, data->parent_names,
1989 data->num_parents, &data->periph,
1990 clk_base, data->offset, data->flags);
1991 clks[data->clk_id] = clk;
1992 }
1993
1994 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1995 data = &tegra_periph_nodiv_clk_list[i];
1996 clk = tegra_clk_register_periph_nodiv(data->name,
1997 data->parent_names, data->num_parents,
1998 &data->periph, clk_base, data->offset);
1999 clks[data->clk_id] = clk;
2000 }
2001}
2002
2003static struct tegra_cpu_car_ops tegra114_cpu_car_ops;
2004
2005static const struct of_device_id pmc_match[] __initconst = {
2006 { .compatible = "nvidia,tegra114-pmc" },
2007 {},
2008};
2009
2010static __initdata struct tegra_clk_init_table init_table[] = {
2011 {uarta, pll_p, 408000000, 0},
2012 {uartb, pll_p, 408000000, 0},
2013 {uartc, pll_p, 408000000, 0},
2014 {uartd, pll_p, 408000000, 0},
2015 {pll_a, clk_max, 564480000, 1},
2016 {pll_a_out0, clk_max, 11289600, 1},
2017 {extern1, pll_a_out0, 0, 1},
2018 {clk_out_1_mux, extern1, 0, 1},
2019 {clk_out_1, clk_max, 0, 1},
2020 {i2s0, pll_a_out0, 11289600, 0},
2021 {i2s1, pll_a_out0, 11289600, 0},
2022 {i2s2, pll_a_out0, 11289600, 0},
2023 {i2s3, pll_a_out0, 11289600, 0},
2024 {i2s4, pll_a_out0, 11289600, 0},
2025 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
2026};
2027
2028static void __init tegra114_clock_apply_init_table(void)
2029{
2030 tegra_init_from_table(init_table, clks, clk_max);
2031}
2032
2033void __init tegra114_clock_init(struct device_node *np)
2034{
2035 struct device_node *node;
2036 int i;
2037
2038 clk_base = of_iomap(np, 0);
2039 if (!clk_base) {
2040 pr_err("ioremap tegra114 CAR failed\n");
2041 return;
2042 }
2043
2044 node = of_find_matching_node(NULL, pmc_match);
2045 if (!node) {
2046 pr_err("Failed to find pmc node\n");
2047 WARN_ON(1);
2048 return;
2049 }
2050
2051 pmc_base = of_iomap(node, 0);
2052 if (!pmc_base) {
2053 pr_err("Can't map pmc registers\n");
2054 WARN_ON(1);
2055 return;
2056 }
2057
2058 if (tegra114_osc_clk_init(clk_base) < 0)
2059 return;
2060
2061 tegra114_fixed_clk_init(clk_base);
2062 tegra114_pll_init(clk_base, pmc_base);
2063 tegra114_periph_clk_init(clk_base);
2064 tegra114_audio_clk_init(clk_base);
2065 tegra114_pmc_clk_init(pmc_base);
2066 tegra114_super_clk_init(clk_base);
2067
2068 for (i = 0; i < ARRAY_SIZE(clks); i++) {
2069 if (IS_ERR(clks[i])) {
2070 pr_err
2071 ("Tegra114 clk %d: register failed with %ld\n",
2072 i, PTR_ERR(clks[i]));
2073 }
2074 if (!clks[i])
2075 clks[i] = ERR_PTR(-EINVAL);
2076 }
2077
2078 clk_data.clks = clks;
2079 clk_data.clk_num = ARRAY_SIZE(clks);
2080 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
2081
2082 tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
2083
2084 tegra_cpu_car_ops = &tegra114_cpu_car_ops;
2085}
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index bf194009e20f..8292a00c3de9 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -86,8 +86,8 @@
86#define PLLE_BASE 0xe8 86#define PLLE_BASE 0xe8
87#define PLLE_MISC 0xec 87#define PLLE_MISC 0xec
88 88
89#define PLL_BASE_LOCK 27 89#define PLL_BASE_LOCK BIT(27)
90#define PLLE_MISC_LOCK 11 90#define PLLE_MISC_LOCK BIT(11)
91 91
92#define PLL_MISC_LOCK_ENABLE 18 92#define PLL_MISC_LOCK_ENABLE 18
93#define PLLDU_MISC_LOCK_ENABLE 22 93#define PLLDU_MISC_LOCK_ENABLE 22
@@ -236,7 +236,7 @@ enum tegra20_clk {
236 dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2, 236 dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
237 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3, 237 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
238 pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb, 238 pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
239 iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2, 239 iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev2, cdev1,
240 uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve, 240 uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
241 osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0, 241 osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
242 pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1, 242 pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
@@ -248,125 +248,125 @@ static struct clk *clks[clk_max];
248static struct clk_onecell_data clk_data; 248static struct clk_onecell_data clk_data;
249 249
250static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 250static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
251 { 12000000, 600000000, 600, 12, 1, 8 }, 251 { 12000000, 600000000, 600, 12, 0, 8 },
252 { 13000000, 600000000, 600, 13, 1, 8 }, 252 { 13000000, 600000000, 600, 13, 0, 8 },
253 { 19200000, 600000000, 500, 16, 1, 6 }, 253 { 19200000, 600000000, 500, 16, 0, 6 },
254 { 26000000, 600000000, 600, 26, 1, 8 }, 254 { 26000000, 600000000, 600, 26, 0, 8 },
255 { 0, 0, 0, 0, 0, 0 }, 255 { 0, 0, 0, 0, 0, 0 },
256}; 256};
257 257
258static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 258static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
259 { 12000000, 666000000, 666, 12, 1, 8}, 259 { 12000000, 666000000, 666, 12, 0, 8},
260 { 13000000, 666000000, 666, 13, 1, 8}, 260 { 13000000, 666000000, 666, 13, 0, 8},
261 { 19200000, 666000000, 555, 16, 1, 8}, 261 { 19200000, 666000000, 555, 16, 0, 8},
262 { 26000000, 666000000, 666, 26, 1, 8}, 262 { 26000000, 666000000, 666, 26, 0, 8},
263 { 12000000, 600000000, 600, 12, 1, 8}, 263 { 12000000, 600000000, 600, 12, 0, 8},
264 { 13000000, 600000000, 600, 13, 1, 8}, 264 { 13000000, 600000000, 600, 13, 0, 8},
265 { 19200000, 600000000, 375, 12, 1, 6}, 265 { 19200000, 600000000, 375, 12, 0, 6},
266 { 26000000, 600000000, 600, 26, 1, 8}, 266 { 26000000, 600000000, 600, 26, 0, 8},
267 { 0, 0, 0, 0, 0, 0 }, 267 { 0, 0, 0, 0, 0, 0 },
268}; 268};
269 269
270static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 270static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
271 { 12000000, 216000000, 432, 12, 2, 8}, 271 { 12000000, 216000000, 432, 12, 1, 8},
272 { 13000000, 216000000, 432, 13, 2, 8}, 272 { 13000000, 216000000, 432, 13, 1, 8},
273 { 19200000, 216000000, 90, 4, 2, 1}, 273 { 19200000, 216000000, 90, 4, 1, 1},
274 { 26000000, 216000000, 432, 26, 2, 8}, 274 { 26000000, 216000000, 432, 26, 1, 8},
275 { 12000000, 432000000, 432, 12, 1, 8}, 275 { 12000000, 432000000, 432, 12, 0, 8},
276 { 13000000, 432000000, 432, 13, 1, 8}, 276 { 13000000, 432000000, 432, 13, 0, 8},
277 { 19200000, 432000000, 90, 4, 1, 1}, 277 { 19200000, 432000000, 90, 4, 0, 1},
278 { 26000000, 432000000, 432, 26, 1, 8}, 278 { 26000000, 432000000, 432, 26, 0, 8},
279 { 0, 0, 0, 0, 0, 0 }, 279 { 0, 0, 0, 0, 0, 0 },
280}; 280};
281 281
282static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 282static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
283 { 28800000, 56448000, 49, 25, 1, 1}, 283 { 28800000, 56448000, 49, 25, 0, 1},
284 { 28800000, 73728000, 64, 25, 1, 1}, 284 { 28800000, 73728000, 64, 25, 0, 1},
285 { 28800000, 24000000, 5, 6, 1, 1}, 285 { 28800000, 24000000, 5, 6, 0, 1},
286 { 0, 0, 0, 0, 0, 0 }, 286 { 0, 0, 0, 0, 0, 0 },
287}; 287};
288 288
289static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 289static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
290 { 12000000, 216000000, 216, 12, 1, 4}, 290 { 12000000, 216000000, 216, 12, 0, 4},
291 { 13000000, 216000000, 216, 13, 1, 4}, 291 { 13000000, 216000000, 216, 13, 0, 4},
292 { 19200000, 216000000, 135, 12, 1, 3}, 292 { 19200000, 216000000, 135, 12, 0, 3},
293 { 26000000, 216000000, 216, 26, 1, 4}, 293 { 26000000, 216000000, 216, 26, 0, 4},
294 294
295 { 12000000, 594000000, 594, 12, 1, 8}, 295 { 12000000, 594000000, 594, 12, 0, 8},
296 { 13000000, 594000000, 594, 13, 1, 8}, 296 { 13000000, 594000000, 594, 13, 0, 8},
297 { 19200000, 594000000, 495, 16, 1, 8}, 297 { 19200000, 594000000, 495, 16, 0, 8},
298 { 26000000, 594000000, 594, 26, 1, 8}, 298 { 26000000, 594000000, 594, 26, 0, 8},
299 299
300 { 12000000, 1000000000, 1000, 12, 1, 12}, 300 { 12000000, 1000000000, 1000, 12, 0, 12},
301 { 13000000, 1000000000, 1000, 13, 1, 12}, 301 { 13000000, 1000000000, 1000, 13, 0, 12},
302 { 19200000, 1000000000, 625, 12, 1, 8}, 302 { 19200000, 1000000000, 625, 12, 0, 8},
303 { 26000000, 1000000000, 1000, 26, 1, 12}, 303 { 26000000, 1000000000, 1000, 26, 0, 12},
304 304
305 { 0, 0, 0, 0, 0, 0 }, 305 { 0, 0, 0, 0, 0, 0 },
306}; 306};
307 307
308static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 308static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
309 { 12000000, 480000000, 960, 12, 2, 0}, 309 { 12000000, 480000000, 960, 12, 0, 0},
310 { 13000000, 480000000, 960, 13, 2, 0}, 310 { 13000000, 480000000, 960, 13, 0, 0},
311 { 19200000, 480000000, 200, 4, 2, 0}, 311 { 19200000, 480000000, 200, 4, 0, 0},
312 { 26000000, 480000000, 960, 26, 2, 0}, 312 { 26000000, 480000000, 960, 26, 0, 0},
313 { 0, 0, 0, 0, 0, 0 }, 313 { 0, 0, 0, 0, 0, 0 },
314}; 314};
315 315
316static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 316static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
317 /* 1 GHz */ 317 /* 1 GHz */
318 { 12000000, 1000000000, 1000, 12, 1, 12}, 318 { 12000000, 1000000000, 1000, 12, 0, 12},
319 { 13000000, 1000000000, 1000, 13, 1, 12}, 319 { 13000000, 1000000000, 1000, 13, 0, 12},
320 { 19200000, 1000000000, 625, 12, 1, 8}, 320 { 19200000, 1000000000, 625, 12, 0, 8},
321 { 26000000, 1000000000, 1000, 26, 1, 12}, 321 { 26000000, 1000000000, 1000, 26, 0, 12},
322 322
323 /* 912 MHz */ 323 /* 912 MHz */
324 { 12000000, 912000000, 912, 12, 1, 12}, 324 { 12000000, 912000000, 912, 12, 0, 12},
325 { 13000000, 912000000, 912, 13, 1, 12}, 325 { 13000000, 912000000, 912, 13, 0, 12},
326 { 19200000, 912000000, 760, 16, 1, 8}, 326 { 19200000, 912000000, 760, 16, 0, 8},
327 { 26000000, 912000000, 912, 26, 1, 12}, 327 { 26000000, 912000000, 912, 26, 0, 12},
328 328
329 /* 816 MHz */ 329 /* 816 MHz */
330 { 12000000, 816000000, 816, 12, 1, 12}, 330 { 12000000, 816000000, 816, 12, 0, 12},
331 { 13000000, 816000000, 816, 13, 1, 12}, 331 { 13000000, 816000000, 816, 13, 0, 12},
332 { 19200000, 816000000, 680, 16, 1, 8}, 332 { 19200000, 816000000, 680, 16, 0, 8},
333 { 26000000, 816000000, 816, 26, 1, 12}, 333 { 26000000, 816000000, 816, 26, 0, 12},
334 334
335 /* 760 MHz */ 335 /* 760 MHz */
336 { 12000000, 760000000, 760, 12, 1, 12}, 336 { 12000000, 760000000, 760, 12, 0, 12},
337 { 13000000, 760000000, 760, 13, 1, 12}, 337 { 13000000, 760000000, 760, 13, 0, 12},
338 { 19200000, 760000000, 950, 24, 1, 8}, 338 { 19200000, 760000000, 950, 24, 0, 8},
339 { 26000000, 760000000, 760, 26, 1, 12}, 339 { 26000000, 760000000, 760, 26, 0, 12},
340 340
341 /* 750 MHz */ 341 /* 750 MHz */
342 { 12000000, 750000000, 750, 12, 1, 12}, 342 { 12000000, 750000000, 750, 12, 0, 12},
343 { 13000000, 750000000, 750, 13, 1, 12}, 343 { 13000000, 750000000, 750, 13, 0, 12},
344 { 19200000, 750000000, 625, 16, 1, 8}, 344 { 19200000, 750000000, 625, 16, 0, 8},
345 { 26000000, 750000000, 750, 26, 1, 12}, 345 { 26000000, 750000000, 750, 26, 0, 12},
346 346
347 /* 608 MHz */ 347 /* 608 MHz */
348 { 12000000, 608000000, 608, 12, 1, 12}, 348 { 12000000, 608000000, 608, 12, 0, 12},
349 { 13000000, 608000000, 608, 13, 1, 12}, 349 { 13000000, 608000000, 608, 13, 0, 12},
350 { 19200000, 608000000, 380, 12, 1, 8}, 350 { 19200000, 608000000, 380, 12, 0, 8},
351 { 26000000, 608000000, 608, 26, 1, 12}, 351 { 26000000, 608000000, 608, 26, 0, 12},
352 352
353 /* 456 MHz */ 353 /* 456 MHz */
354 { 12000000, 456000000, 456, 12, 1, 12}, 354 { 12000000, 456000000, 456, 12, 0, 12},
355 { 13000000, 456000000, 456, 13, 1, 12}, 355 { 13000000, 456000000, 456, 13, 0, 12},
356 { 19200000, 456000000, 380, 16, 1, 8}, 356 { 19200000, 456000000, 380, 16, 0, 8},
357 { 26000000, 456000000, 456, 26, 1, 12}, 357 { 26000000, 456000000, 456, 26, 0, 12},
358 358
359 /* 312 MHz */ 359 /* 312 MHz */
360 { 12000000, 312000000, 312, 12, 1, 12}, 360 { 12000000, 312000000, 312, 12, 0, 12},
361 { 13000000, 312000000, 312, 13, 1, 12}, 361 { 13000000, 312000000, 312, 13, 0, 12},
362 { 19200000, 312000000, 260, 16, 1, 8}, 362 { 19200000, 312000000, 260, 16, 0, 8},
363 { 26000000, 312000000, 312, 26, 1, 12}, 363 { 26000000, 312000000, 312, 26, 0, 12},
364 364
365 { 0, 0, 0, 0, 0, 0 }, 365 { 0, 0, 0, 0, 0, 0 },
366}; 366};
367 367
368static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 368static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
369 { 12000000, 100000000, 200, 24, 1, 0 }, 369 { 12000000, 100000000, 200, 24, 0, 0 },
370 { 0, 0, 0, 0, 0, 0 }, 370 { 0, 0, 0, 0, 0, 0 },
371}; 371};
372 372
@@ -380,7 +380,7 @@ static struct tegra_clk_pll_params pll_c_params = {
380 .vco_max = 1400000000, 380 .vco_max = 1400000000,
381 .base_reg = PLLC_BASE, 381 .base_reg = PLLC_BASE,
382 .misc_reg = PLLC_MISC, 382 .misc_reg = PLLC_MISC,
383 .lock_bit_idx = PLL_BASE_LOCK, 383 .lock_mask = PLL_BASE_LOCK,
384 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 384 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
385 .lock_delay = 300, 385 .lock_delay = 300,
386}; 386};
@@ -394,7 +394,7 @@ static struct tegra_clk_pll_params pll_m_params = {
394 .vco_max = 1200000000, 394 .vco_max = 1200000000,
395 .base_reg = PLLM_BASE, 395 .base_reg = PLLM_BASE,
396 .misc_reg = PLLM_MISC, 396 .misc_reg = PLLM_MISC,
397 .lock_bit_idx = PLL_BASE_LOCK, 397 .lock_mask = PLL_BASE_LOCK,
398 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 398 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
399 .lock_delay = 300, 399 .lock_delay = 300,
400}; 400};
@@ -408,7 +408,7 @@ static struct tegra_clk_pll_params pll_p_params = {
408 .vco_max = 1400000000, 408 .vco_max = 1400000000,
409 .base_reg = PLLP_BASE, 409 .base_reg = PLLP_BASE,
410 .misc_reg = PLLP_MISC, 410 .misc_reg = PLLP_MISC,
411 .lock_bit_idx = PLL_BASE_LOCK, 411 .lock_mask = PLL_BASE_LOCK,
412 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 412 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
413 .lock_delay = 300, 413 .lock_delay = 300,
414}; 414};
@@ -422,7 +422,7 @@ static struct tegra_clk_pll_params pll_a_params = {
422 .vco_max = 1400000000, 422 .vco_max = 1400000000,
423 .base_reg = PLLA_BASE, 423 .base_reg = PLLA_BASE,
424 .misc_reg = PLLA_MISC, 424 .misc_reg = PLLA_MISC,
425 .lock_bit_idx = PLL_BASE_LOCK, 425 .lock_mask = PLL_BASE_LOCK,
426 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 426 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
427 .lock_delay = 300, 427 .lock_delay = 300,
428}; 428};
@@ -436,11 +436,17 @@ static struct tegra_clk_pll_params pll_d_params = {
436 .vco_max = 1000000000, 436 .vco_max = 1000000000,
437 .base_reg = PLLD_BASE, 437 .base_reg = PLLD_BASE,
438 .misc_reg = PLLD_MISC, 438 .misc_reg = PLLD_MISC,
439 .lock_bit_idx = PLL_BASE_LOCK, 439 .lock_mask = PLL_BASE_LOCK,
440 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 440 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
441 .lock_delay = 1000, 441 .lock_delay = 1000,
442}; 442};
443 443
444static struct pdiv_map pllu_p[] = {
445 { .pdiv = 1, .hw_val = 1 },
446 { .pdiv = 2, .hw_val = 0 },
447 { .pdiv = 0, .hw_val = 0 },
448};
449
444static struct tegra_clk_pll_params pll_u_params = { 450static struct tegra_clk_pll_params pll_u_params = {
445 .input_min = 2000000, 451 .input_min = 2000000,
446 .input_max = 40000000, 452 .input_max = 40000000,
@@ -450,9 +456,10 @@ static struct tegra_clk_pll_params pll_u_params = {
450 .vco_max = 960000000, 456 .vco_max = 960000000,
451 .base_reg = PLLU_BASE, 457 .base_reg = PLLU_BASE,
452 .misc_reg = PLLU_MISC, 458 .misc_reg = PLLU_MISC,
453 .lock_bit_idx = PLL_BASE_LOCK, 459 .lock_mask = PLL_BASE_LOCK,
454 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 460 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
455 .lock_delay = 1000, 461 .lock_delay = 1000,
462 .pdiv_tohw = pllu_p,
456}; 463};
457 464
458static struct tegra_clk_pll_params pll_x_params = { 465static struct tegra_clk_pll_params pll_x_params = {
@@ -464,7 +471,7 @@ static struct tegra_clk_pll_params pll_x_params = {
464 .vco_max = 1200000000, 471 .vco_max = 1200000000,
465 .base_reg = PLLX_BASE, 472 .base_reg = PLLX_BASE,
466 .misc_reg = PLLX_MISC, 473 .misc_reg = PLLX_MISC,
467 .lock_bit_idx = PLL_BASE_LOCK, 474 .lock_mask = PLL_BASE_LOCK,
468 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 475 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
469 .lock_delay = 300, 476 .lock_delay = 300,
470}; 477};
@@ -478,7 +485,7 @@ static struct tegra_clk_pll_params pll_e_params = {
478 .vco_max = 0, 485 .vco_max = 0,
479 .base_reg = PLLE_BASE, 486 .base_reg = PLLE_BASE,
480 .misc_reg = PLLE_MISC, 487 .misc_reg = PLLE_MISC,
481 .lock_bit_idx = PLLE_MISC_LOCK, 488 .lock_mask = PLLE_MISC_LOCK,
482 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 489 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
483 .lock_delay = 0, 490 .lock_delay = 0,
484}; 491};
@@ -1012,7 +1019,7 @@ static void __init tegra20_periph_clk_init(void)
1012 data = &tegra_periph_clk_list[i]; 1019 data = &tegra_periph_clk_list[i];
1013 clk = tegra_clk_register_periph(data->name, data->parent_names, 1020 clk = tegra_clk_register_periph(data->name, data->parent_names,
1014 data->num_parents, &data->periph, 1021 data->num_parents, &data->periph,
1015 clk_base, data->offset); 1022 clk_base, data->offset, data->flags);
1016 clk_register_clkdev(clk, data->con_id, data->dev_id); 1023 clk_register_clkdev(clk, data->con_id, data->dev_id);
1017 clks[data->clk_id] = clk; 1024 clks[data->clk_id] = clk;
1018 } 1025 }
@@ -1247,9 +1254,16 @@ static __initdata struct tegra_clk_init_table init_table[] = {
1247 {host1x, pll_c, 150000000, 0}, 1254 {host1x, pll_c, 150000000, 0},
1248 {disp1, pll_p, 600000000, 0}, 1255 {disp1, pll_p, 600000000, 0},
1249 {disp2, pll_p, 600000000, 0}, 1256 {disp2, pll_p, 600000000, 0},
1257 {gr2d, pll_c, 300000000, 0},
1258 {gr3d, pll_c, 300000000, 0},
1250 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */ 1259 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */
1251}; 1260};
1252 1261
1262static void __init tegra20_clock_apply_init_table(void)
1263{
1264 tegra_init_from_table(init_table, clks, clk_max);
1265}
1266
1253/* 1267/*
1254 * Some clocks may be used by different drivers depending on the board 1268 * Some clocks may be used by different drivers depending on the board
1255 * configuration. List those here to register them twice in the clock lookup 1269 * configuration. List those here to register them twice in the clock lookup
@@ -1316,7 +1330,7 @@ void __init tegra20_clock_init(struct device_node *np)
1316 clk_data.clk_num = ARRAY_SIZE(clks); 1330 clk_data.clk_num = ARRAY_SIZE(clks);
1317 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 1331 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1318 1332
1319 tegra_init_from_table(init_table, clks, clk_max); 1333 tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
1320 1334
1321 tegra_cpu_car_ops = &tegra20_cpu_car_ops; 1335 tegra_cpu_car_ops = &tegra20_cpu_car_ops;
1322} 1336}
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index f15f147d473c..c6921f538e28 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -115,8 +115,8 @@
115#define PLLDU_MISC_LOCK_ENABLE 22 115#define PLLDU_MISC_LOCK_ENABLE 22
116#define PLLE_MISC_LOCK_ENABLE 9 116#define PLLE_MISC_LOCK_ENABLE 9
117 117
118#define PLL_BASE_LOCK 27 118#define PLL_BASE_LOCK BIT(27)
119#define PLLE_MISC_LOCK 11 119#define PLLE_MISC_LOCK BIT(11)
120 120
121#define PLLE_AUX 0x48c 121#define PLLE_AUX 0x48c
122#define PLLC_OUT 0x84 122#define PLLC_OUT 0x84
@@ -329,7 +329,7 @@ enum tegra30_clk {
329 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3, 329 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
330 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow, 330 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow,
331 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92, 331 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
332 cdev1, cdev2, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4, 332 cdev2, cdev1, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
333 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x, 333 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
334 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x, 334 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
335 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda, 335 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda,
@@ -373,164 +373,170 @@ static const struct utmi_clk_param utmi_parameters[] = {
373}; 373};
374 374
375static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 375static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
376 { 12000000, 1040000000, 520, 6, 1, 8}, 376 { 12000000, 1040000000, 520, 6, 0, 8},
377 { 13000000, 1040000000, 480, 6, 1, 8}, 377 { 13000000, 1040000000, 480, 6, 0, 8},
378 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */ 378 { 16800000, 1040000000, 495, 8, 0, 8}, /* actual: 1039.5 MHz */
379 { 19200000, 1040000000, 325, 6, 1, 6}, 379 { 19200000, 1040000000, 325, 6, 0, 6},
380 { 26000000, 1040000000, 520, 13, 1, 8}, 380 { 26000000, 1040000000, 520, 13, 0, 8},
381 381
382 { 12000000, 832000000, 416, 6, 1, 8}, 382 { 12000000, 832000000, 416, 6, 0, 8},
383 { 13000000, 832000000, 832, 13, 1, 8}, 383 { 13000000, 832000000, 832, 13, 0, 8},
384 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */ 384 { 16800000, 832000000, 396, 8, 0, 8}, /* actual: 831.6 MHz */
385 { 19200000, 832000000, 260, 6, 1, 8}, 385 { 19200000, 832000000, 260, 6, 0, 8},
386 { 26000000, 832000000, 416, 13, 1, 8}, 386 { 26000000, 832000000, 416, 13, 0, 8},
387 387
388 { 12000000, 624000000, 624, 12, 1, 8}, 388 { 12000000, 624000000, 624, 12, 0, 8},
389 { 13000000, 624000000, 624, 13, 1, 8}, 389 { 13000000, 624000000, 624, 13, 0, 8},
390 { 16800000, 600000000, 520, 14, 1, 8}, 390 { 16800000, 600000000, 520, 14, 0, 8},
391 { 19200000, 624000000, 520, 16, 1, 8}, 391 { 19200000, 624000000, 520, 16, 0, 8},
392 { 26000000, 624000000, 624, 26, 1, 8}, 392 { 26000000, 624000000, 624, 26, 0, 8},
393 393
394 { 12000000, 600000000, 600, 12, 1, 8}, 394 { 12000000, 600000000, 600, 12, 0, 8},
395 { 13000000, 600000000, 600, 13, 1, 8}, 395 { 13000000, 600000000, 600, 13, 0, 8},
396 { 16800000, 600000000, 500, 14, 1, 8}, 396 { 16800000, 600000000, 500, 14, 0, 8},
397 { 19200000, 600000000, 375, 12, 1, 6}, 397 { 19200000, 600000000, 375, 12, 0, 6},
398 { 26000000, 600000000, 600, 26, 1, 8}, 398 { 26000000, 600000000, 600, 26, 0, 8},
399 399
400 { 12000000, 520000000, 520, 12, 1, 8}, 400 { 12000000, 520000000, 520, 12, 0, 8},
401 { 13000000, 520000000, 520, 13, 1, 8}, 401 { 13000000, 520000000, 520, 13, 0, 8},
402 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */ 402 { 16800000, 520000000, 495, 16, 0, 8}, /* actual: 519.75 MHz */
403 { 19200000, 520000000, 325, 12, 1, 6}, 403 { 19200000, 520000000, 325, 12, 0, 6},
404 { 26000000, 520000000, 520, 26, 1, 8}, 404 { 26000000, 520000000, 520, 26, 0, 8},
405 405
406 { 12000000, 416000000, 416, 12, 1, 8}, 406 { 12000000, 416000000, 416, 12, 0, 8},
407 { 13000000, 416000000, 416, 13, 1, 8}, 407 { 13000000, 416000000, 416, 13, 0, 8},
408 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */ 408 { 16800000, 416000000, 396, 16, 0, 8}, /* actual: 415.8 MHz */
409 { 19200000, 416000000, 260, 12, 1, 6}, 409 { 19200000, 416000000, 260, 12, 0, 6},
410 { 26000000, 416000000, 416, 26, 1, 8}, 410 { 26000000, 416000000, 416, 26, 0, 8},
411 { 0, 0, 0, 0, 0, 0 }, 411 { 0, 0, 0, 0, 0, 0 },
412}; 412};
413 413
414static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 414static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
415 { 12000000, 666000000, 666, 12, 1, 8}, 415 { 12000000, 666000000, 666, 12, 0, 8},
416 { 13000000, 666000000, 666, 13, 1, 8}, 416 { 13000000, 666000000, 666, 13, 0, 8},
417 { 16800000, 666000000, 555, 14, 1, 8}, 417 { 16800000, 666000000, 555, 14, 0, 8},
418 { 19200000, 666000000, 555, 16, 1, 8}, 418 { 19200000, 666000000, 555, 16, 0, 8},
419 { 26000000, 666000000, 666, 26, 1, 8}, 419 { 26000000, 666000000, 666, 26, 0, 8},
420 { 12000000, 600000000, 600, 12, 1, 8}, 420 { 12000000, 600000000, 600, 12, 0, 8},
421 { 13000000, 600000000, 600, 13, 1, 8}, 421 { 13000000, 600000000, 600, 13, 0, 8},
422 { 16800000, 600000000, 500, 14, 1, 8}, 422 { 16800000, 600000000, 500, 14, 0, 8},
423 { 19200000, 600000000, 375, 12, 1, 6}, 423 { 19200000, 600000000, 375, 12, 0, 6},
424 { 26000000, 600000000, 600, 26, 1, 8}, 424 { 26000000, 600000000, 600, 26, 0, 8},
425 { 0, 0, 0, 0, 0, 0 }, 425 { 0, 0, 0, 0, 0, 0 },
426}; 426};
427 427
428static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 428static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
429 { 12000000, 216000000, 432, 12, 2, 8}, 429 { 12000000, 216000000, 432, 12, 1, 8},
430 { 13000000, 216000000, 432, 13, 2, 8}, 430 { 13000000, 216000000, 432, 13, 1, 8},
431 { 16800000, 216000000, 360, 14, 2, 8}, 431 { 16800000, 216000000, 360, 14, 1, 8},
432 { 19200000, 216000000, 360, 16, 2, 8}, 432 { 19200000, 216000000, 360, 16, 1, 8},
433 { 26000000, 216000000, 432, 26, 2, 8}, 433 { 26000000, 216000000, 432, 26, 1, 8},
434 { 0, 0, 0, 0, 0, 0 }, 434 { 0, 0, 0, 0, 0, 0 },
435}; 435};
436 436
437static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 437static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
438 { 9600000, 564480000, 294, 5, 1, 4}, 438 { 9600000, 564480000, 294, 5, 0, 4},
439 { 9600000, 552960000, 288, 5, 1, 4}, 439 { 9600000, 552960000, 288, 5, 0, 4},
440 { 9600000, 24000000, 5, 2, 1, 1}, 440 { 9600000, 24000000, 5, 2, 0, 1},
441 441
442 { 28800000, 56448000, 49, 25, 1, 1}, 442 { 28800000, 56448000, 49, 25, 0, 1},
443 { 28800000, 73728000, 64, 25, 1, 1}, 443 { 28800000, 73728000, 64, 25, 0, 1},
444 { 28800000, 24000000, 5, 6, 1, 1}, 444 { 28800000, 24000000, 5, 6, 0, 1},
445 { 0, 0, 0, 0, 0, 0 }, 445 { 0, 0, 0, 0, 0, 0 },
446}; 446};
447 447
448static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 448static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
449 { 12000000, 216000000, 216, 12, 1, 4}, 449 { 12000000, 216000000, 216, 12, 0, 4},
450 { 13000000, 216000000, 216, 13, 1, 4}, 450 { 13000000, 216000000, 216, 13, 0, 4},
451 { 16800000, 216000000, 180, 14, 1, 4}, 451 { 16800000, 216000000, 180, 14, 0, 4},
452 { 19200000, 216000000, 180, 16, 1, 4}, 452 { 19200000, 216000000, 180, 16, 0, 4},
453 { 26000000, 216000000, 216, 26, 1, 4}, 453 { 26000000, 216000000, 216, 26, 0, 4},
454 454
455 { 12000000, 594000000, 594, 12, 1, 8}, 455 { 12000000, 594000000, 594, 12, 0, 8},
456 { 13000000, 594000000, 594, 13, 1, 8}, 456 { 13000000, 594000000, 594, 13, 0, 8},
457 { 16800000, 594000000, 495, 14, 1, 8}, 457 { 16800000, 594000000, 495, 14, 0, 8},
458 { 19200000, 594000000, 495, 16, 1, 8}, 458 { 19200000, 594000000, 495, 16, 0, 8},
459 { 26000000, 594000000, 594, 26, 1, 8}, 459 { 26000000, 594000000, 594, 26, 0, 8},
460 460
461 { 12000000, 1000000000, 1000, 12, 1, 12}, 461 { 12000000, 1000000000, 1000, 12, 0, 12},
462 { 13000000, 1000000000, 1000, 13, 1, 12}, 462 { 13000000, 1000000000, 1000, 13, 0, 12},
463 { 19200000, 1000000000, 625, 12, 1, 8}, 463 { 19200000, 1000000000, 625, 12, 0, 8},
464 { 26000000, 1000000000, 1000, 26, 1, 12}, 464 { 26000000, 1000000000, 1000, 26, 0, 12},
465 465
466 { 0, 0, 0, 0, 0, 0 }, 466 { 0, 0, 0, 0, 0, 0 },
467}; 467};
468 468
469static struct pdiv_map pllu_p[] = {
470 { .pdiv = 1, .hw_val = 1 },
471 { .pdiv = 2, .hw_val = 0 },
472 { .pdiv = 0, .hw_val = 0 },
473};
474
469static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 475static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
470 { 12000000, 480000000, 960, 12, 2, 12}, 476 { 12000000, 480000000, 960, 12, 0, 12},
471 { 13000000, 480000000, 960, 13, 2, 12}, 477 { 13000000, 480000000, 960, 13, 0, 12},
472 { 16800000, 480000000, 400, 7, 2, 5}, 478 { 16800000, 480000000, 400, 7, 0, 5},
473 { 19200000, 480000000, 200, 4, 2, 3}, 479 { 19200000, 480000000, 200, 4, 0, 3},
474 { 26000000, 480000000, 960, 26, 2, 12}, 480 { 26000000, 480000000, 960, 26, 0, 12},
475 { 0, 0, 0, 0, 0, 0 }, 481 { 0, 0, 0, 0, 0, 0 },
476}; 482};
477 483
478static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 484static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
479 /* 1.7 GHz */ 485 /* 1.7 GHz */
480 { 12000000, 1700000000, 850, 6, 1, 8}, 486 { 12000000, 1700000000, 850, 6, 0, 8},
481 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */ 487 { 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */
482 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */ 488 { 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */
483 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */ 489 { 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */
484 { 26000000, 1700000000, 850, 13, 1, 8}, 490 { 26000000, 1700000000, 850, 13, 0, 8},
485 491
486 /* 1.6 GHz */ 492 /* 1.6 GHz */
487 { 12000000, 1600000000, 800, 6, 1, 8}, 493 { 12000000, 1600000000, 800, 6, 0, 8},
488 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */ 494 { 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */
489 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */ 495 { 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */
490 { 19200000, 1600000000, 500, 6, 1, 8}, 496 { 19200000, 1600000000, 500, 6, 0, 8},
491 { 26000000, 1600000000, 800, 13, 1, 8}, 497 { 26000000, 1600000000, 800, 13, 0, 8},
492 498
493 /* 1.5 GHz */ 499 /* 1.5 GHz */
494 { 12000000, 1500000000, 750, 6, 1, 8}, 500 { 12000000, 1500000000, 750, 6, 0, 8},
495 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */ 501 { 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */
496 { 16800000, 1500000000, 625, 7, 1, 8}, 502 { 16800000, 1500000000, 625, 7, 0, 8},
497 { 19200000, 1500000000, 625, 8, 1, 8}, 503 { 19200000, 1500000000, 625, 8, 0, 8},
498 { 26000000, 1500000000, 750, 13, 1, 8}, 504 { 26000000, 1500000000, 750, 13, 0, 8},
499 505
500 /* 1.4 GHz */ 506 /* 1.4 GHz */
501 { 12000000, 1400000000, 700, 6, 1, 8}, 507 { 12000000, 1400000000, 700, 6, 0, 8},
502 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */ 508 { 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */
503 { 16800000, 1400000000, 1000, 12, 1, 8}, 509 { 16800000, 1400000000, 1000, 12, 0, 8},
504 { 19200000, 1400000000, 875, 12, 1, 8}, 510 { 19200000, 1400000000, 875, 12, 0, 8},
505 { 26000000, 1400000000, 700, 13, 1, 8}, 511 { 26000000, 1400000000, 700, 13, 0, 8},
506 512
507 /* 1.3 GHz */ 513 /* 1.3 GHz */
508 { 12000000, 1300000000, 975, 9, 1, 8}, 514 { 12000000, 1300000000, 975, 9, 0, 8},
509 { 13000000, 1300000000, 1000, 10, 1, 8}, 515 { 13000000, 1300000000, 1000, 10, 0, 8},
510 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */ 516 { 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */
511 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */ 517 { 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */
512 { 26000000, 1300000000, 650, 13, 1, 8}, 518 { 26000000, 1300000000, 650, 13, 0, 8},
513 519
514 /* 1.2 GHz */ 520 /* 1.2 GHz */
515 { 12000000, 1200000000, 1000, 10, 1, 8}, 521 { 12000000, 1200000000, 1000, 10, 0, 8},
516 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */ 522 { 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */
517 { 16800000, 1200000000, 1000, 14, 1, 8}, 523 { 16800000, 1200000000, 1000, 14, 0, 8},
518 { 19200000, 1200000000, 1000, 16, 1, 8}, 524 { 19200000, 1200000000, 1000, 16, 0, 8},
519 { 26000000, 1200000000, 600, 13, 1, 8}, 525 { 26000000, 1200000000, 600, 13, 0, 8},
520 526
521 /* 1.1 GHz */ 527 /* 1.1 GHz */
522 { 12000000, 1100000000, 825, 9, 1, 8}, 528 { 12000000, 1100000000, 825, 9, 0, 8},
523 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */ 529 { 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */
524 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */ 530 { 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */
525 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */ 531 { 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */
526 { 26000000, 1100000000, 550, 13, 1, 8}, 532 { 26000000, 1100000000, 550, 13, 0, 8},
527 533
528 /* 1 GHz */ 534 /* 1 GHz */
529 { 12000000, 1000000000, 1000, 12, 1, 8}, 535 { 12000000, 1000000000, 1000, 12, 0, 8},
530 { 13000000, 1000000000, 1000, 13, 1, 8}, 536 { 13000000, 1000000000, 1000, 13, 0, 8},
531 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */ 537 { 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */
532 { 19200000, 1000000000, 625, 12, 1, 8}, 538 { 19200000, 1000000000, 625, 12, 0, 8},
533 { 26000000, 1000000000, 1000, 26, 1, 8}, 539 { 26000000, 1000000000, 1000, 26, 0, 8},
534 540
535 { 0, 0, 0, 0, 0, 0 }, 541 { 0, 0, 0, 0, 0, 0 },
536}; 542};
@@ -552,7 +558,7 @@ static struct tegra_clk_pll_params pll_c_params = {
552 .vco_max = 1400000000, 558 .vco_max = 1400000000,
553 .base_reg = PLLC_BASE, 559 .base_reg = PLLC_BASE,
554 .misc_reg = PLLC_MISC, 560 .misc_reg = PLLC_MISC,
555 .lock_bit_idx = PLL_BASE_LOCK, 561 .lock_mask = PLL_BASE_LOCK,
556 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 562 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
557 .lock_delay = 300, 563 .lock_delay = 300,
558}; 564};
@@ -566,7 +572,7 @@ static struct tegra_clk_pll_params pll_m_params = {
566 .vco_max = 1200000000, 572 .vco_max = 1200000000,
567 .base_reg = PLLM_BASE, 573 .base_reg = PLLM_BASE,
568 .misc_reg = PLLM_MISC, 574 .misc_reg = PLLM_MISC,
569 .lock_bit_idx = PLL_BASE_LOCK, 575 .lock_mask = PLL_BASE_LOCK,
570 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 576 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
571 .lock_delay = 300, 577 .lock_delay = 300,
572}; 578};
@@ -580,7 +586,7 @@ static struct tegra_clk_pll_params pll_p_params = {
580 .vco_max = 1400000000, 586 .vco_max = 1400000000,
581 .base_reg = PLLP_BASE, 587 .base_reg = PLLP_BASE,
582 .misc_reg = PLLP_MISC, 588 .misc_reg = PLLP_MISC,
583 .lock_bit_idx = PLL_BASE_LOCK, 589 .lock_mask = PLL_BASE_LOCK,
584 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 590 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
585 .lock_delay = 300, 591 .lock_delay = 300,
586}; 592};
@@ -594,7 +600,7 @@ static struct tegra_clk_pll_params pll_a_params = {
594 .vco_max = 1400000000, 600 .vco_max = 1400000000,
595 .base_reg = PLLA_BASE, 601 .base_reg = PLLA_BASE,
596 .misc_reg = PLLA_MISC, 602 .misc_reg = PLLA_MISC,
597 .lock_bit_idx = PLL_BASE_LOCK, 603 .lock_mask = PLL_BASE_LOCK,
598 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 604 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
599 .lock_delay = 300, 605 .lock_delay = 300,
600}; 606};
@@ -608,7 +614,7 @@ static struct tegra_clk_pll_params pll_d_params = {
608 .vco_max = 1000000000, 614 .vco_max = 1000000000,
609 .base_reg = PLLD_BASE, 615 .base_reg = PLLD_BASE,
610 .misc_reg = PLLD_MISC, 616 .misc_reg = PLLD_MISC,
611 .lock_bit_idx = PLL_BASE_LOCK, 617 .lock_mask = PLL_BASE_LOCK,
612 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 618 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
613 .lock_delay = 1000, 619 .lock_delay = 1000,
614}; 620};
@@ -622,7 +628,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
622 .vco_max = 1000000000, 628 .vco_max = 1000000000,
623 .base_reg = PLLD2_BASE, 629 .base_reg = PLLD2_BASE,
624 .misc_reg = PLLD2_MISC, 630 .misc_reg = PLLD2_MISC,
625 .lock_bit_idx = PLL_BASE_LOCK, 631 .lock_mask = PLL_BASE_LOCK,
626 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 632 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
627 .lock_delay = 1000, 633 .lock_delay = 1000,
628}; 634};
@@ -636,9 +642,10 @@ static struct tegra_clk_pll_params pll_u_params = {
636 .vco_max = 960000000, 642 .vco_max = 960000000,
637 .base_reg = PLLU_BASE, 643 .base_reg = PLLU_BASE,
638 .misc_reg = PLLU_MISC, 644 .misc_reg = PLLU_MISC,
639 .lock_bit_idx = PLL_BASE_LOCK, 645 .lock_mask = PLL_BASE_LOCK,
640 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 646 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
641 .lock_delay = 1000, 647 .lock_delay = 1000,
648 .pdiv_tohw = pllu_p,
642}; 649};
643 650
644static struct tegra_clk_pll_params pll_x_params = { 651static struct tegra_clk_pll_params pll_x_params = {
@@ -650,7 +657,7 @@ static struct tegra_clk_pll_params pll_x_params = {
650 .vco_max = 1700000000, 657 .vco_max = 1700000000,
651 .base_reg = PLLX_BASE, 658 .base_reg = PLLX_BASE,
652 .misc_reg = PLLX_MISC, 659 .misc_reg = PLLX_MISC,
653 .lock_bit_idx = PLL_BASE_LOCK, 660 .lock_mask = PLL_BASE_LOCK,
654 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 661 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
655 .lock_delay = 300, 662 .lock_delay = 300,
656}; 663};
@@ -664,7 +671,7 @@ static struct tegra_clk_pll_params pll_e_params = {
664 .vco_max = 2400000000U, 671 .vco_max = 2400000000U,
665 .base_reg = PLLE_BASE, 672 .base_reg = PLLE_BASE,
666 .misc_reg = PLLE_MISC, 673 .misc_reg = PLLE_MISC,
667 .lock_bit_idx = PLLE_MISC_LOCK, 674 .lock_mask = PLLE_MISC_LOCK,
668 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 675 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
669 .lock_delay = 300, 676 .lock_delay = 300,
670}; 677};
@@ -1660,7 +1667,7 @@ static void __init tegra30_periph_clk_init(void)
1660 data = &tegra_periph_clk_list[i]; 1667 data = &tegra_periph_clk_list[i];
1661 clk = tegra_clk_register_periph(data->name, data->parent_names, 1668 clk = tegra_clk_register_periph(data->name, data->parent_names,
1662 data->num_parents, &data->periph, 1669 data->num_parents, &data->periph,
1663 clk_base, data->offset); 1670 clk_base, data->offset, data->flags);
1664 clk_register_clkdev(clk, data->con_id, data->dev_id); 1671 clk_register_clkdev(clk, data->con_id, data->dev_id);
1665 clks[data->clk_id] = clk; 1672 clks[data->clk_id] = clk;
1666 } 1673 }
@@ -1910,9 +1917,16 @@ static __initdata struct tegra_clk_init_table init_table[] = {
1910 {disp1, pll_p, 600000000, 0}, 1917 {disp1, pll_p, 600000000, 0},
1911 {disp2, pll_p, 600000000, 0}, 1918 {disp2, pll_p, 600000000, 0},
1912 {twd, clk_max, 0, 1}, 1919 {twd, clk_max, 0, 1},
1920 {gr2d, pll_c, 300000000, 0},
1921 {gr3d, pll_c, 300000000, 0},
1913 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 1922 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
1914}; 1923};
1915 1924
1925static void __init tegra30_clock_apply_init_table(void)
1926{
1927 tegra_init_from_table(init_table, clks, clk_max);
1928}
1929
1916/* 1930/*
1917 * Some clocks may be used by different drivers depending on the board 1931 * Some clocks may be used by different drivers depending on the board
1918 * configuration. List those here to register them twice in the clock lookup 1932 * configuration. List those here to register them twice in the clock lookup
@@ -1986,7 +2000,7 @@ void __init tegra30_clock_init(struct device_node *np)
1986 clk_data.clk_num = ARRAY_SIZE(clks); 2000 clk_data.clk_num = ARRAY_SIZE(clks);
1987 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 2001 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1988 2002
1989 tegra_init_from_table(init_table, clks, clk_max); 2003 tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
1990 2004
1991 tegra_cpu_car_ops = &tegra30_cpu_car_ops; 2005 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1992} 2006}
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index a603b9af0ad3..923ca7ee4694 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -22,7 +22,8 @@
22#include "clk.h" 22#include "clk.h"
23 23
24/* Global data of Tegra CPU CAR ops */ 24/* Global data of Tegra CPU CAR ops */
25struct tegra_cpu_car_ops *tegra_cpu_car_ops; 25static struct tegra_cpu_car_ops dummy_car_ops;
26struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
26 27
27void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 28void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
28 struct clk *clks[], int clk_max) 29 struct clk *clks[], int clk_max)
@@ -76,6 +77,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
76static const struct of_device_id tegra_dt_clk_match[] = { 77static const struct of_device_id tegra_dt_clk_match[] = {
77 { .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init }, 78 { .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init },
78 { .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init }, 79 { .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init },
80 { .compatible = "nvidia,tegra114-car", .data = tegra114_clock_init },
79 { } 81 { }
80}; 82};
81 83
@@ -83,3 +85,13 @@ void __init tegra_clocks_init(void)
83{ 85{
84 of_clk_init(tegra_dt_clk_match); 86 of_clk_init(tegra_dt_clk_match);
85} 87}
88
89tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
90
91void __init tegra_clocks_apply_init_table(void)
92{
93 if (!tegra_clk_apply_init_table)
94 return;
95
96 tegra_clk_apply_init_table();
97}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index a09d7dcaf183..e0565620d68e 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -1,4 +1,4 @@
1/* 1 /*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
@@ -117,6 +117,17 @@ struct tegra_clk_pll_freq_table {
117}; 117};
118 118
119/** 119/**
120 * struct pdiv_map - map post divider to hw value
121 *
122 * @pdiv: post divider
123 * @hw_val: value to be written to the PLL hw
124 */
125struct pdiv_map {
126 u8 pdiv;
127 u8 hw_val;
128};
129
130/**
120 * struct clk_pll_params - PLL parameters 131 * struct clk_pll_params - PLL parameters
121 * 132 *
122 * @input_min: Minimum input frequency 133 * @input_min: Minimum input frequency
@@ -143,9 +154,18 @@ struct tegra_clk_pll_params {
143 u32 base_reg; 154 u32 base_reg;
144 u32 misc_reg; 155 u32 misc_reg;
145 u32 lock_reg; 156 u32 lock_reg;
146 u32 lock_bit_idx; 157 u32 lock_mask;
147 u32 lock_enable_bit_idx; 158 u32 lock_enable_bit_idx;
159 u32 iddq_reg;
160 u32 iddq_bit_idx;
161 u32 aux_reg;
162 u32 dyn_ramp_reg;
163 u32 ext_misc_reg[3];
164 int stepa_shift;
165 int stepb_shift;
148 int lock_delay; 166 int lock_delay;
167 int max_p;
168 struct pdiv_map *pdiv_tohw;
149}; 169};
150 170
151/** 171/**
@@ -182,12 +202,16 @@ struct tegra_clk_pll_params {
182 * TEGRA_PLL_FIXED - We are not supposed to change output frequency 202 * TEGRA_PLL_FIXED - We are not supposed to change output frequency
183 * of some plls. 203 * of some plls.
184 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling. 204 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
205 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
206 * base register.
207 * TEGRA_PLL_BYPASS - PLL has bypass bit
208 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
185 */ 209 */
186struct tegra_clk_pll { 210struct tegra_clk_pll {
187 struct clk_hw hw; 211 struct clk_hw hw;
188 void __iomem *clk_base; 212 void __iomem *clk_base;
189 void __iomem *pmc; 213 void __iomem *pmc;
190 u8 flags; 214 u32 flags;
191 unsigned long fixed_rate; 215 unsigned long fixed_rate;
192 spinlock_t *lock; 216 spinlock_t *lock;
193 u8 divn_shift; 217 u8 divn_shift;
@@ -210,20 +234,64 @@ struct tegra_clk_pll {
210#define TEGRA_PLLM BIT(5) 234#define TEGRA_PLLM BIT(5)
211#define TEGRA_PLL_FIXED BIT(6) 235#define TEGRA_PLL_FIXED BIT(6)
212#define TEGRA_PLLE_CONFIGURE BIT(7) 236#define TEGRA_PLLE_CONFIGURE BIT(7)
237#define TEGRA_PLL_LOCK_MISC BIT(8)
238#define TEGRA_PLL_BYPASS BIT(9)
239#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
213 240
214extern const struct clk_ops tegra_clk_pll_ops; 241extern const struct clk_ops tegra_clk_pll_ops;
215extern const struct clk_ops tegra_clk_plle_ops; 242extern const struct clk_ops tegra_clk_plle_ops;
216struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 243struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
217 void __iomem *clk_base, void __iomem *pmc, 244 void __iomem *clk_base, void __iomem *pmc,
218 unsigned long flags, unsigned long fixed_rate, 245 unsigned long flags, unsigned long fixed_rate,
219 struct tegra_clk_pll_params *pll_params, u8 pll_flags, 246 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
220 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock); 247 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
248
221struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 249struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
222 void __iomem *clk_base, void __iomem *pmc, 250 void __iomem *clk_base, void __iomem *pmc,
223 unsigned long flags, unsigned long fixed_rate, 251 unsigned long flags, unsigned long fixed_rate,
224 struct tegra_clk_pll_params *pll_params, u8 pll_flags, 252 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
225 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock); 253 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
226 254
255struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
256 void __iomem *clk_base, void __iomem *pmc,
257 unsigned long flags, unsigned long fixed_rate,
258 struct tegra_clk_pll_params *pll_params,
259 u32 pll_flags,
260 struct tegra_clk_pll_freq_table *freq_table,
261 spinlock_t *lock);
262
263struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
264 void __iomem *clk_base, void __iomem *pmc,
265 unsigned long flags, unsigned long fixed_rate,
266 struct tegra_clk_pll_params *pll_params,
267 u32 pll_flags,
268 struct tegra_clk_pll_freq_table *freq_table,
269 spinlock_t *lock);
270
271struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
272 void __iomem *clk_base, void __iomem *pmc,
273 unsigned long flags, unsigned long fixed_rate,
274 struct tegra_clk_pll_params *pll_params,
275 u32 pll_flags,
276 struct tegra_clk_pll_freq_table *freq_table,
277 spinlock_t *lock);
278
279struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
280 void __iomem *clk_base, void __iomem *pmc,
281 unsigned long flags, unsigned long fixed_rate,
282 struct tegra_clk_pll_params *pll_params,
283 u32 pll_flags,
284 struct tegra_clk_pll_freq_table *freq_table,
285 spinlock_t *lock, unsigned long parent_rate);
286
287struct clk *tegra_clk_register_plle_tegra114(const char *name,
288 const char *parent_name,
289 void __iomem *clk_base, unsigned long flags,
290 unsigned long fixed_rate,
291 struct tegra_clk_pll_params *pll_params,
292 struct tegra_clk_pll_freq_table *freq_table,
293 spinlock_t *lock);
294
227/** 295/**
228 * struct tegra_clk_pll_out - PLL divider down clock 296 * struct tegra_clk_pll_out - PLL divider down clock
229 * 297 *
@@ -290,6 +358,7 @@ struct tegra_clk_periph_regs {
290 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the 358 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
291 * bus to flush the write operation in apb bus. This flag indicates 359 * bus to flush the write operation in apb bus. This flag indicates
292 * that this peripheral is in apb bus. 360 * that this peripheral is in apb bus.
361 * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
293 */ 362 */
294struct tegra_clk_periph_gate { 363struct tegra_clk_periph_gate {
295 u32 magic; 364 u32 magic;
@@ -309,6 +378,7 @@ struct tegra_clk_periph_gate {
309#define TEGRA_PERIPH_NO_RESET BIT(0) 378#define TEGRA_PERIPH_NO_RESET BIT(0)
310#define TEGRA_PERIPH_MANUAL_RESET BIT(1) 379#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
311#define TEGRA_PERIPH_ON_APB BIT(2) 380#define TEGRA_PERIPH_ON_APB BIT(2)
381#define TEGRA_PERIPH_WAR_1005168 BIT(3)
312 382
313void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert); 383void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
314extern const struct clk_ops tegra_clk_periph_gate_ops; 384extern const struct clk_ops tegra_clk_periph_gate_ops;
@@ -349,7 +419,7 @@ extern const struct clk_ops tegra_clk_periph_ops;
349struct clk *tegra_clk_register_periph(const char *name, 419struct clk *tegra_clk_register_periph(const char *name,
350 const char **parent_names, int num_parents, 420 const char **parent_names, int num_parents,
351 struct tegra_clk_periph *periph, void __iomem *clk_base, 421 struct tegra_clk_periph *periph, void __iomem *clk_base,
352 u32 offset); 422 u32 offset, unsigned long flags);
353struct clk *tegra_clk_register_periph_nodiv(const char *name, 423struct clk *tegra_clk_register_periph_nodiv(const char *name,
354 const char **parent_names, int num_parents, 424 const char **parent_names, int num_parents,
355 struct tegra_clk_periph *periph, void __iomem *clk_base, 425 struct tegra_clk_periph *periph, void __iomem *clk_base,
@@ -392,12 +462,14 @@ struct tegra_periph_init_data {
392 u32 offset; 462 u32 offset;
393 const char *con_id; 463 const char *con_id;
394 const char *dev_id; 464 const char *dev_id;
465 unsigned long flags;
395}; 466};
396 467
397#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 468#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
398 _mux_shift, _mux_mask, _mux_flags, _div_shift, \ 469 _mux_shift, _mux_mask, _mux_flags, _div_shift, \
399 _div_width, _div_frac_width, _div_flags, _regs, \ 470 _div_width, _div_frac_width, _div_flags, _regs, \
400 _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table) \ 471 _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table,\
472 _flags) \
401 { \ 473 { \
402 .name = _name, \ 474 .name = _name, \
403 .clk_id = _clk_id, \ 475 .clk_id = _clk_id, \
@@ -412,6 +484,7 @@ struct tegra_periph_init_data {
412 .offset = _offset, \ 484 .offset = _offset, \
413 .con_id = _con_id, \ 485 .con_id = _con_id, \
414 .dev_id = _dev_id, \ 486 .dev_id = _dev_id, \
487 .flags = _flags \
415 } 488 }
416 489
417#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ 490#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
@@ -422,7 +495,7 @@ struct tegra_periph_init_data {
422 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ 495 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
423 _div_shift, _div_width, _div_frac_width, _div_flags, \ 496 _div_shift, _div_width, _div_frac_width, _div_flags, \
424 _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\ 497 _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\
425 NULL) 498 NULL, 0)
426 499
427/** 500/**
428 * struct clk_super_mux - super clock 501 * struct clk_super_mux - super clock
@@ -510,4 +583,13 @@ void tegra30_clock_init(struct device_node *np);
510static inline void tegra30_clock_init(struct device_node *np) {} 583static inline void tegra30_clock_init(struct device_node *np) {}
511#endif /* CONFIG_ARCH_TEGRA_3x_SOC */ 584#endif /* CONFIG_ARCH_TEGRA_3x_SOC */
512 585
586#ifdef CONFIG_ARCH_TEGRA_114_SOC
587void tegra114_clock_init(struct device_node *np);
588#else
589static inline void tegra114_clock_init(struct device_node *np) {}
590#endif /* CONFIG_ARCH_TEGRA114_SOC */
591
592typedef void (*tegra_clk_apply_init_table_func)(void);
593extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
594
513#endif /* TEGRA_CLK_H */ 595#endif /* TEGRA_CLK_H */
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 9002185a0a1a..7bc6e51757ee 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -31,6 +31,9 @@ config SUN4I_TIMER
31config VT8500_TIMER 31config VT8500_TIMER
32 bool 32 bool
33 33
34config CADENCE_TTC_TIMER
35 bool
36
34config CLKSRC_NOMADIK_MTU 37config CLKSRC_NOMADIK_MTU
35 bool 38 bool
36 depends on (ARCH_NOMADIK || ARCH_U8500) 39 depends on (ARCH_NOMADIK || ARCH_U8500)
@@ -67,3 +70,8 @@ config CLKSRC_METAG_GENERIC
67 def_bool y if METAG 70 def_bool y if METAG
68 help 71 help
69 This option enables support for the Meta per-thread timers. 72 This option enables support for the Meta per-thread timers.
73
74config CLKSRC_EXYNOS_MCT
75 def_bool y if ARCH_EXYNOS
76 help
77 Support for Multi Core Timer controller on Exynos SoCs.
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 682d48d08164..caacdb63aff9 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -23,6 +23,8 @@ obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o
23obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o 23obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
24obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o 24obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
25obj-$(CONFIG_ARCH_BCM) += bcm_kona_timer.o 25obj-$(CONFIG_ARCH_BCM) += bcm_kona_timer.o
26obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence_ttc_timer.o
27obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o
26 28
27obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o 29obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
28obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o 30obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o
diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/cadence_ttc_timer.c
new file mode 100644
index 000000000000..685bc60e210a
--- /dev/null
+++ b/drivers/clocksource/cadence_ttc_timer.c
@@ -0,0 +1,436 @@
1/*
2 * This file contains driver for the Cadence Triple Timer Counter Rev 06
3 *
4 * Copyright (C) 2011-2013 Xilinx
5 *
6 * based on arch/mips/kernel/time.c timer driver
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/clk.h>
19#include <linux/interrupt.h>
20#include <linux/clockchips.h>
21#include <linux/of_address.h>
22#include <linux/of_irq.h>
23#include <linux/slab.h>
24#include <linux/clk-provider.h>
25
26/*
27 * This driver configures the 2 16-bit count-up timers as follows:
28 *
29 * T1: Timer 1, clocksource for generic timekeeping
30 * T2: Timer 2, clockevent source for hrtimers
31 * T3: Timer 3, <unused>
32 *
33 * The input frequency to the timer module for emulation is 2.5MHz which is
34 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
35 * the timers are clocked at 78.125KHz (12.8 us resolution).
36
37 * The input frequency to the timer module in silicon is configurable and
38 * obtained from device tree. The pre-scaler of 32 is used.
39 */
40
41/*
42 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
43 * and use same offsets for Timer 2
44 */
45#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
46#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
47#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
48#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
49#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
50#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
51
52#define TTC_CNT_CNTRL_DISABLE_MASK 0x1
53
54/*
55 * Setup the timers to use pre-scaling, using a fixed value for now that will
56 * work across most input frequency, but it may need to be more dynamic
57 */
58#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
59#define PRESCALE 2048 /* The exponent must match this */
60#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
61#define CLK_CNTRL_PRESCALE_EN 1
62#define CNT_CNTRL_RESET (1 << 4)
63
64/**
65 * struct ttc_timer - This definition defines local timer structure
66 *
67 * @base_addr: Base address of timer
68 * @clk: Associated clock source
69 * @clk_rate_change_nb Notifier block for clock rate changes
70 */
71struct ttc_timer {
72 void __iomem *base_addr;
73 struct clk *clk;
74 struct notifier_block clk_rate_change_nb;
75};
76
77#define to_ttc_timer(x) \
78 container_of(x, struct ttc_timer, clk_rate_change_nb)
79
80struct ttc_timer_clocksource {
81 struct ttc_timer ttc;
82 struct clocksource cs;
83};
84
85#define to_ttc_timer_clksrc(x) \
86 container_of(x, struct ttc_timer_clocksource, cs)
87
88struct ttc_timer_clockevent {
89 struct ttc_timer ttc;
90 struct clock_event_device ce;
91};
92
93#define to_ttc_timer_clkevent(x) \
94 container_of(x, struct ttc_timer_clockevent, ce)
95
96/**
97 * ttc_set_interval - Set the timer interval value
98 *
99 * @timer: Pointer to the timer instance
100 * @cycles: Timer interval ticks
101 **/
102static void ttc_set_interval(struct ttc_timer *timer,
103 unsigned long cycles)
104{
105 u32 ctrl_reg;
106
107 /* Disable the counter, set the counter value and re-enable counter */
108 ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
109 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
110 __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
111
112 __raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
113
114 /*
115 * Reset the counter (0x10) so that it starts from 0, one-shot
116 * mode makes this needed for timing to be right.
117 */
118 ctrl_reg |= CNT_CNTRL_RESET;
119 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
120 __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
121}
122
123/**
124 * ttc_clock_event_interrupt - Clock event timer interrupt handler
125 *
126 * @irq: IRQ number of the Timer
127 * @dev_id: void pointer to the ttc_timer instance
128 *
129 * returns: Always IRQ_HANDLED - success
130 **/
131static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
132{
133 struct ttc_timer_clockevent *ttce = dev_id;
134 struct ttc_timer *timer = &ttce->ttc;
135
136 /* Acknowledge the interrupt and call event handler */
137 __raw_readl(timer->base_addr + TTC_ISR_OFFSET);
138
139 ttce->ce.event_handler(&ttce->ce);
140
141 return IRQ_HANDLED;
142}
143
144/**
145 * __ttc_clocksource_read - Reads the timer counter register
146 *
147 * returns: Current timer counter register value
148 **/
149static cycle_t __ttc_clocksource_read(struct clocksource *cs)
150{
151 struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
152
153 return (cycle_t)__raw_readl(timer->base_addr +
154 TTC_COUNT_VAL_OFFSET);
155}
156
157/**
158 * ttc_set_next_event - Sets the time interval for next event
159 *
160 * @cycles: Timer interval ticks
161 * @evt: Address of clock event instance
162 *
163 * returns: Always 0 - success
164 **/
165static int ttc_set_next_event(unsigned long cycles,
166 struct clock_event_device *evt)
167{
168 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
169 struct ttc_timer *timer = &ttce->ttc;
170
171 ttc_set_interval(timer, cycles);
172 return 0;
173}
174
175/**
176 * ttc_set_mode - Sets the mode of timer
177 *
178 * @mode: Mode to be set
179 * @evt: Address of clock event instance
180 **/
181static void ttc_set_mode(enum clock_event_mode mode,
182 struct clock_event_device *evt)
183{
184 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
185 struct ttc_timer *timer = &ttce->ttc;
186 u32 ctrl_reg;
187
188 switch (mode) {
189 case CLOCK_EVT_MODE_PERIODIC:
190 ttc_set_interval(timer,
191 DIV_ROUND_CLOSEST(clk_get_rate(ttce->ttc.clk),
192 PRESCALE * HZ));
193 break;
194 case CLOCK_EVT_MODE_ONESHOT:
195 case CLOCK_EVT_MODE_UNUSED:
196 case CLOCK_EVT_MODE_SHUTDOWN:
197 ctrl_reg = __raw_readl(timer->base_addr +
198 TTC_CNT_CNTRL_OFFSET);
199 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
200 __raw_writel(ctrl_reg,
201 timer->base_addr + TTC_CNT_CNTRL_OFFSET);
202 break;
203 case CLOCK_EVT_MODE_RESUME:
204 ctrl_reg = __raw_readl(timer->base_addr +
205 TTC_CNT_CNTRL_OFFSET);
206 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
207 __raw_writel(ctrl_reg,
208 timer->base_addr + TTC_CNT_CNTRL_OFFSET);
209 break;
210 }
211}
212
213static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
214 unsigned long event, void *data)
215{
216 struct clk_notifier_data *ndata = data;
217 struct ttc_timer *ttc = to_ttc_timer(nb);
218 struct ttc_timer_clocksource *ttccs = container_of(ttc,
219 struct ttc_timer_clocksource, ttc);
220
221 switch (event) {
222 case POST_RATE_CHANGE:
223 /*
224 * Do whatever is necessary to maintain a proper time base
225 *
226 * I cannot find a way to adjust the currently used clocksource
227 * to the new frequency. __clocksource_updatefreq_hz() sounds
228 * good, but does not work. Not sure what's that missing.
229 *
230 * This approach works, but triggers two clocksource switches.
231 * The first after unregister to clocksource jiffies. And
232 * another one after the register to the newly registered timer.
233 *
234 * Alternatively we could 'waste' another HW timer to ping pong
235 * between clock sources. That would also use one register and
236 * one unregister call, but only trigger one clocksource switch
237 * for the cost of another HW timer used by the OS.
238 */
239 clocksource_unregister(&ttccs->cs);
240 clocksource_register_hz(&ttccs->cs,
241 ndata->new_rate / PRESCALE);
242 /* fall through */
243 case PRE_RATE_CHANGE:
244 case ABORT_RATE_CHANGE:
245 default:
246 return NOTIFY_DONE;
247 }
248}
249
250static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
251{
252 struct ttc_timer_clocksource *ttccs;
253 int err;
254
255 ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
256 if (WARN_ON(!ttccs))
257 return;
258
259 ttccs->ttc.clk = clk;
260
261 err = clk_prepare_enable(ttccs->ttc.clk);
262 if (WARN_ON(err)) {
263 kfree(ttccs);
264 return;
265 }
266
267 ttccs->ttc.clk_rate_change_nb.notifier_call =
268 ttc_rate_change_clocksource_cb;
269 ttccs->ttc.clk_rate_change_nb.next = NULL;
270 if (clk_notifier_register(ttccs->ttc.clk,
271 &ttccs->ttc.clk_rate_change_nb))
272 pr_warn("Unable to register clock notifier.\n");
273
274 ttccs->ttc.base_addr = base;
275 ttccs->cs.name = "ttc_clocksource";
276 ttccs->cs.rating = 200;
277 ttccs->cs.read = __ttc_clocksource_read;
278 ttccs->cs.mask = CLOCKSOURCE_MASK(16);
279 ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
280
281 /*
282 * Setup the clock source counter to be an incrementing counter
283 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
284 * it by 32 also. Let it start running now.
285 */
286 __raw_writel(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
287 __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
288 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
289 __raw_writel(CNT_CNTRL_RESET,
290 ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
291
292 err = clocksource_register_hz(&ttccs->cs,
293 clk_get_rate(ttccs->ttc.clk) / PRESCALE);
294 if (WARN_ON(err)) {
295 kfree(ttccs);
296 return;
297 }
298}
299
300static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
301 unsigned long event, void *data)
302{
303 struct clk_notifier_data *ndata = data;
304 struct ttc_timer *ttc = to_ttc_timer(nb);
305 struct ttc_timer_clockevent *ttcce = container_of(ttc,
306 struct ttc_timer_clockevent, ttc);
307
308 switch (event) {
309 case POST_RATE_CHANGE:
310 {
311 unsigned long flags;
312
313 /*
314 * clockevents_update_freq should be called with IRQ disabled on
315 * the CPU the timer provides events for. The timer we use is
316 * common to both CPUs, not sure if we need to run on both
317 * cores.
318 */
319 local_irq_save(flags);
320 clockevents_update_freq(&ttcce->ce,
321 ndata->new_rate / PRESCALE);
322 local_irq_restore(flags);
323
324 /* fall through */
325 }
326 case PRE_RATE_CHANGE:
327 case ABORT_RATE_CHANGE:
328 default:
329 return NOTIFY_DONE;
330 }
331}
332
333static void __init ttc_setup_clockevent(struct clk *clk,
334 void __iomem *base, u32 irq)
335{
336 struct ttc_timer_clockevent *ttcce;
337 int err;
338
339 ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
340 if (WARN_ON(!ttcce))
341 return;
342
343 ttcce->ttc.clk = clk;
344
345 err = clk_prepare_enable(ttcce->ttc.clk);
346 if (WARN_ON(err)) {
347 kfree(ttcce);
348 return;
349 }
350
351 ttcce->ttc.clk_rate_change_nb.notifier_call =
352 ttc_rate_change_clockevent_cb;
353 ttcce->ttc.clk_rate_change_nb.next = NULL;
354 if (clk_notifier_register(ttcce->ttc.clk,
355 &ttcce->ttc.clk_rate_change_nb))
356 pr_warn("Unable to register clock notifier.\n");
357
358 ttcce->ttc.base_addr = base;
359 ttcce->ce.name = "ttc_clockevent";
360 ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
361 ttcce->ce.set_next_event = ttc_set_next_event;
362 ttcce->ce.set_mode = ttc_set_mode;
363 ttcce->ce.rating = 200;
364 ttcce->ce.irq = irq;
365 ttcce->ce.cpumask = cpu_possible_mask;
366
367 /*
368 * Setup the clock event timer to be an interval timer which
369 * is prescaled by 32 using the interval interrupt. Leave it
370 * disabled for now.
371 */
372 __raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
373 __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
374 ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
375 __raw_writel(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
376
377 err = request_irq(irq, ttc_clock_event_interrupt,
378 IRQF_DISABLED | IRQF_TIMER,
379 ttcce->ce.name, ttcce);
380 if (WARN_ON(err)) {
381 kfree(ttcce);
382 return;
383 }
384
385 clockevents_config_and_register(&ttcce->ce,
386 clk_get_rate(ttcce->ttc.clk) / PRESCALE, 1, 0xfffe);
387}
388
389/**
390 * ttc_timer_init - Initialize the timer
391 *
392 * Initializes the timer hardware and register the clock source and clock event
393 * timers with Linux kernal timer framework
394 */
395static void __init ttc_timer_init(struct device_node *timer)
396{
397 unsigned int irq;
398 void __iomem *timer_baseaddr;
399 struct clk *clk;
400 static int initialized;
401
402 if (initialized)
403 return;
404
405 initialized = 1;
406
407 /*
408 * Get the 1st Triple Timer Counter (TTC) block from the device tree
409 * and use it. Note that the event timer uses the interrupt and it's the
410 * 2nd TTC hence the irq_of_parse_and_map(,1)
411 */
412 timer_baseaddr = of_iomap(timer, 0);
413 if (!timer_baseaddr) {
414 pr_err("ERROR: invalid timer base address\n");
415 BUG();
416 }
417
418 irq = irq_of_parse_and_map(timer, 1);
419 if (irq <= 0) {
420 pr_err("ERROR: invalid interrupt number\n");
421 BUG();
422 }
423
424 clk = of_clk_get_by_name(timer, "cpu_1x");
425 if (IS_ERR(clk)) {
426 pr_err("ERROR: timer input clock not found\n");
427 BUG();
428 }
429
430 ttc_setup_clocksource(clk, timer_baseaddr);
431 ttc_setup_clockevent(clk, timer_baseaddr + 4, irq);
432
433 pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
434}
435
436CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);
diff --git a/drivers/clocksource/em_sti.c b/drivers/clocksource/em_sti.c
index e6a553cb73e8..4329a29a5310 100644
--- a/drivers/clocksource/em_sti.c
+++ b/drivers/clocksource/em_sti.c
@@ -399,7 +399,18 @@ static struct platform_driver em_sti_device_driver = {
399 } 399 }
400}; 400};
401 401
402module_platform_driver(em_sti_device_driver); 402static int __init em_sti_init(void)
403{
404 return platform_driver_register(&em_sti_device_driver);
405}
406
407static void __exit em_sti_exit(void)
408{
409 platform_driver_unregister(&em_sti_device_driver);
410}
411
412subsys_initcall(em_sti_init);
413module_exit(em_sti_exit);
403 414
404MODULE_AUTHOR("Magnus Damm"); 415MODULE_AUTHOR("Magnus Damm");
405MODULE_DESCRIPTION("Renesas Emma Mobile STI Timer Driver"); 416MODULE_DESCRIPTION("Renesas Emma Mobile STI Timer Driver");
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
new file mode 100644
index 000000000000..661026834b23
--- /dev/null
+++ b/drivers/clocksource/exynos_mct.c
@@ -0,0 +1,568 @@
1/* linux/arch/arm/mach-exynos4/mct.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 MCT(Multi-Core Timer) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/sched.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/clockchips.h>
19#include <linux/platform_device.h>
20#include <linux/delay.h>
21#include <linux/percpu.h>
22#include <linux/of.h>
23#include <linux/of_irq.h>
24#include <linux/of_address.h>
25#include <linux/clocksource.h>
26
27#include <asm/arch_timer.h>
28#include <asm/localtimer.h>
29
30#include <plat/cpu.h>
31
32#include <mach/map.h>
33#include <mach/irqs.h>
34#include <asm/mach/time.h>
35
36#define EXYNOS4_MCTREG(x) (x)
37#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
38#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
39#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
40#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
41#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
42#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
43#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
44#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
45#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
46#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
47#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
48#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
49#define EXYNOS4_MCT_L_MASK (0xffffff00)
50
51#define MCT_L_TCNTB_OFFSET (0x00)
52#define MCT_L_ICNTB_OFFSET (0x08)
53#define MCT_L_TCON_OFFSET (0x20)
54#define MCT_L_INT_CSTAT_OFFSET (0x30)
55#define MCT_L_INT_ENB_OFFSET (0x34)
56#define MCT_L_WSTAT_OFFSET (0x40)
57#define MCT_G_TCON_START (1 << 8)
58#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
59#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
60#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
61#define MCT_L_TCON_INT_START (1 << 1)
62#define MCT_L_TCON_TIMER_START (1 << 0)
63
64#define TICK_BASE_CNT 1
65
66enum {
67 MCT_INT_SPI,
68 MCT_INT_PPI
69};
70
71enum {
72 MCT_G0_IRQ,
73 MCT_G1_IRQ,
74 MCT_G2_IRQ,
75 MCT_G3_IRQ,
76 MCT_L0_IRQ,
77 MCT_L1_IRQ,
78 MCT_L2_IRQ,
79 MCT_L3_IRQ,
80 MCT_NR_IRQS,
81};
82
83static void __iomem *reg_base;
84static unsigned long clk_rate;
85static unsigned int mct_int_type;
86static int mct_irqs[MCT_NR_IRQS];
87
88struct mct_clock_event_device {
89 struct clock_event_device *evt;
90 unsigned long base;
91 char name[10];
92};
93
94static void exynos4_mct_write(unsigned int value, unsigned long offset)
95{
96 unsigned long stat_addr;
97 u32 mask;
98 u32 i;
99
100 __raw_writel(value, reg_base + offset);
101
102 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
103 stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
104 switch (offset & EXYNOS4_MCT_L_MASK) {
105 case MCT_L_TCON_OFFSET:
106 mask = 1 << 3; /* L_TCON write status */
107 break;
108 case MCT_L_ICNTB_OFFSET:
109 mask = 1 << 1; /* L_ICNTB write status */
110 break;
111 case MCT_L_TCNTB_OFFSET:
112 mask = 1 << 0; /* L_TCNTB write status */
113 break;
114 default:
115 return;
116 }
117 } else {
118 switch (offset) {
119 case EXYNOS4_MCT_G_TCON:
120 stat_addr = EXYNOS4_MCT_G_WSTAT;
121 mask = 1 << 16; /* G_TCON write status */
122 break;
123 case EXYNOS4_MCT_G_COMP0_L:
124 stat_addr = EXYNOS4_MCT_G_WSTAT;
125 mask = 1 << 0; /* G_COMP0_L write status */
126 break;
127 case EXYNOS4_MCT_G_COMP0_U:
128 stat_addr = EXYNOS4_MCT_G_WSTAT;
129 mask = 1 << 1; /* G_COMP0_U write status */
130 break;
131 case EXYNOS4_MCT_G_COMP0_ADD_INCR:
132 stat_addr = EXYNOS4_MCT_G_WSTAT;
133 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
134 break;
135 case EXYNOS4_MCT_G_CNT_L:
136 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
137 mask = 1 << 0; /* G_CNT_L write status */
138 break;
139 case EXYNOS4_MCT_G_CNT_U:
140 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
141 mask = 1 << 1; /* G_CNT_U write status */
142 break;
143 default:
144 return;
145 }
146 }
147
148 /* Wait maximum 1 ms until written values are applied */
149 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
150 if (__raw_readl(reg_base + stat_addr) & mask) {
151 __raw_writel(mask, reg_base + stat_addr);
152 return;
153 }
154
155 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
156}
157
158/* Clocksource handling */
159static void exynos4_mct_frc_start(u32 hi, u32 lo)
160{
161 u32 reg;
162
163 exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
164 exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
165
166 reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
167 reg |= MCT_G_TCON_START;
168 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
169}
170
171static cycle_t exynos4_frc_read(struct clocksource *cs)
172{
173 unsigned int lo, hi;
174 u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
175
176 do {
177 hi = hi2;
178 lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
179 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
180 } while (hi != hi2);
181
182 return ((cycle_t)hi << 32) | lo;
183}
184
185static void exynos4_frc_resume(struct clocksource *cs)
186{
187 exynos4_mct_frc_start(0, 0);
188}
189
190struct clocksource mct_frc = {
191 .name = "mct-frc",
192 .rating = 400,
193 .read = exynos4_frc_read,
194 .mask = CLOCKSOURCE_MASK(64),
195 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
196 .resume = exynos4_frc_resume,
197};
198
199static void __init exynos4_clocksource_init(void)
200{
201 exynos4_mct_frc_start(0, 0);
202
203 if (clocksource_register_hz(&mct_frc, clk_rate))
204 panic("%s: can't register clocksource\n", mct_frc.name);
205}
206
207static void exynos4_mct_comp0_stop(void)
208{
209 unsigned int tcon;
210
211 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
212 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
213
214 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
215 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
216}
217
218static void exynos4_mct_comp0_start(enum clock_event_mode mode,
219 unsigned long cycles)
220{
221 unsigned int tcon;
222 cycle_t comp_cycle;
223
224 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
225
226 if (mode == CLOCK_EVT_MODE_PERIODIC) {
227 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
228 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
229 }
230
231 comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
232 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
233 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
234
235 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
236
237 tcon |= MCT_G_TCON_COMP0_ENABLE;
238 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
239}
240
241static int exynos4_comp_set_next_event(unsigned long cycles,
242 struct clock_event_device *evt)
243{
244 exynos4_mct_comp0_start(evt->mode, cycles);
245
246 return 0;
247}
248
249static void exynos4_comp_set_mode(enum clock_event_mode mode,
250 struct clock_event_device *evt)
251{
252 unsigned long cycles_per_jiffy;
253 exynos4_mct_comp0_stop();
254
255 switch (mode) {
256 case CLOCK_EVT_MODE_PERIODIC:
257 cycles_per_jiffy =
258 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
259 exynos4_mct_comp0_start(mode, cycles_per_jiffy);
260 break;
261
262 case CLOCK_EVT_MODE_ONESHOT:
263 case CLOCK_EVT_MODE_UNUSED:
264 case CLOCK_EVT_MODE_SHUTDOWN:
265 case CLOCK_EVT_MODE_RESUME:
266 break;
267 }
268}
269
270static struct clock_event_device mct_comp_device = {
271 .name = "mct-comp",
272 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
273 .rating = 250,
274 .set_next_event = exynos4_comp_set_next_event,
275 .set_mode = exynos4_comp_set_mode,
276};
277
278static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
279{
280 struct clock_event_device *evt = dev_id;
281
282 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
283
284 evt->event_handler(evt);
285
286 return IRQ_HANDLED;
287}
288
289static struct irqaction mct_comp_event_irq = {
290 .name = "mct_comp_irq",
291 .flags = IRQF_TIMER | IRQF_IRQPOLL,
292 .handler = exynos4_mct_comp_isr,
293 .dev_id = &mct_comp_device,
294};
295
296static void exynos4_clockevent_init(void)
297{
298 mct_comp_device.cpumask = cpumask_of(0);
299 clockevents_config_and_register(&mct_comp_device, clk_rate,
300 0xf, 0xffffffff);
301 setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
302}
303
304#ifdef CONFIG_LOCAL_TIMERS
305
306static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
307
308/* Clock event handling */
309static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
310{
311 unsigned long tmp;
312 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
313 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
314
315 tmp = __raw_readl(reg_base + offset);
316 if (tmp & mask) {
317 tmp &= ~mask;
318 exynos4_mct_write(tmp, offset);
319 }
320}
321
322static void exynos4_mct_tick_start(unsigned long cycles,
323 struct mct_clock_event_device *mevt)
324{
325 unsigned long tmp;
326
327 exynos4_mct_tick_stop(mevt);
328
329 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
330
331 /* update interrupt count buffer */
332 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
333
334 /* enable MCT tick interrupt */
335 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
336
337 tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
338 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
339 MCT_L_TCON_INTERVAL_MODE;
340 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
341}
342
343static int exynos4_tick_set_next_event(unsigned long cycles,
344 struct clock_event_device *evt)
345{
346 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
347
348 exynos4_mct_tick_start(cycles, mevt);
349
350 return 0;
351}
352
353static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
354 struct clock_event_device *evt)
355{
356 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
357 unsigned long cycles_per_jiffy;
358
359 exynos4_mct_tick_stop(mevt);
360
361 switch (mode) {
362 case CLOCK_EVT_MODE_PERIODIC:
363 cycles_per_jiffy =
364 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
365 exynos4_mct_tick_start(cycles_per_jiffy, mevt);
366 break;
367
368 case CLOCK_EVT_MODE_ONESHOT:
369 case CLOCK_EVT_MODE_UNUSED:
370 case CLOCK_EVT_MODE_SHUTDOWN:
371 case CLOCK_EVT_MODE_RESUME:
372 break;
373 }
374}
375
376static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
377{
378 struct clock_event_device *evt = mevt->evt;
379
380 /*
381 * This is for supporting oneshot mode.
382 * Mct would generate interrupt periodically
383 * without explicit stopping.
384 */
385 if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
386 exynos4_mct_tick_stop(mevt);
387
388 /* Clear the MCT tick interrupt */
389 if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
390 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
391 return 1;
392 } else {
393 return 0;
394 }
395}
396
397static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
398{
399 struct mct_clock_event_device *mevt = dev_id;
400 struct clock_event_device *evt = mevt->evt;
401
402 exynos4_mct_tick_clear(mevt);
403
404 evt->event_handler(evt);
405
406 return IRQ_HANDLED;
407}
408
409static struct irqaction mct_tick0_event_irq = {
410 .name = "mct_tick0_irq",
411 .flags = IRQF_TIMER | IRQF_NOBALANCING,
412 .handler = exynos4_mct_tick_isr,
413};
414
415static struct irqaction mct_tick1_event_irq = {
416 .name = "mct_tick1_irq",
417 .flags = IRQF_TIMER | IRQF_NOBALANCING,
418 .handler = exynos4_mct_tick_isr,
419};
420
421static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
422{
423 struct mct_clock_event_device *mevt;
424 unsigned int cpu = smp_processor_id();
425
426 mevt = this_cpu_ptr(&percpu_mct_tick);
427 mevt->evt = evt;
428
429 mevt->base = EXYNOS4_MCT_L_BASE(cpu);
430 sprintf(mevt->name, "mct_tick%d", cpu);
431
432 evt->name = mevt->name;
433 evt->cpumask = cpumask_of(cpu);
434 evt->set_next_event = exynos4_tick_set_next_event;
435 evt->set_mode = exynos4_tick_set_mode;
436 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
437 evt->rating = 450;
438 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
439 0xf, 0x7fffffff);
440
441 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
442
443 if (mct_int_type == MCT_INT_SPI) {
444 if (cpu == 0) {
445 mct_tick0_event_irq.dev_id = mevt;
446 evt->irq = mct_irqs[MCT_L0_IRQ];
447 setup_irq(evt->irq, &mct_tick0_event_irq);
448 } else {
449 mct_tick1_event_irq.dev_id = mevt;
450 evt->irq = mct_irqs[MCT_L1_IRQ];
451 setup_irq(evt->irq, &mct_tick1_event_irq);
452 irq_set_affinity(evt->irq, cpumask_of(1));
453 }
454 } else {
455 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
456 }
457
458 return 0;
459}
460
461static void exynos4_local_timer_stop(struct clock_event_device *evt)
462{
463 unsigned int cpu = smp_processor_id();
464 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
465 if (mct_int_type == MCT_INT_SPI)
466 if (cpu == 0)
467 remove_irq(evt->irq, &mct_tick0_event_irq);
468 else
469 remove_irq(evt->irq, &mct_tick1_event_irq);
470 else
471 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
472}
473
474static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
475 .setup = exynos4_local_timer_setup,
476 .stop = exynos4_local_timer_stop,
477};
478#endif /* CONFIG_LOCAL_TIMERS */
479
480static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
481{
482 struct clk *mct_clk, *tick_clk;
483
484 tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
485 clk_get(NULL, "fin_pll");
486 if (IS_ERR(tick_clk))
487 panic("%s: unable to determine tick clock rate\n", __func__);
488 clk_rate = clk_get_rate(tick_clk);
489
490 mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
491 if (IS_ERR(mct_clk))
492 panic("%s: unable to retrieve mct clock instance\n", __func__);
493 clk_prepare_enable(mct_clk);
494
495 reg_base = base;
496 if (!reg_base)
497 panic("%s: unable to ioremap mct address space\n", __func__);
498
499#ifdef CONFIG_LOCAL_TIMERS
500 if (mct_int_type == MCT_INT_PPI) {
501 int err;
502
503 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
504 exynos4_mct_tick_isr, "MCT",
505 &percpu_mct_tick);
506 WARN(err, "MCT: can't request IRQ %d (%d)\n",
507 mct_irqs[MCT_L0_IRQ], err);
508 }
509
510 local_timer_register(&exynos4_mct_tick_ops);
511#endif /* CONFIG_LOCAL_TIMERS */
512}
513
514void __init mct_init(void)
515{
516 if (soc_is_exynos4210()) {
517 mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
518 mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0;
519 mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1;
520 mct_int_type = MCT_INT_SPI;
521 } else {
522 panic("unable to determine mct controller type\n");
523 }
524
525 exynos4_timer_resources(NULL, S5P_VA_SYSTIMER);
526 exynos4_clocksource_init();
527 exynos4_clockevent_init();
528}
529
530static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
531{
532 u32 nr_irqs, i;
533
534 mct_int_type = int_type;
535
536 /* This driver uses only one global timer interrupt */
537 mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
538
539 /*
540 * Find out the number of local irqs specified. The local
541 * timer irqs are specified after the four global timer
542 * irqs are specified.
543 */
544#ifdef CONFIG_OF
545 nr_irqs = of_irq_count(np);
546#else
547 nr_irqs = 0;
548#endif
549 for (i = MCT_L0_IRQ; i < nr_irqs; i++)
550 mct_irqs[i] = irq_of_parse_and_map(np, i);
551
552 exynos4_timer_resources(np, of_iomap(np, 0));
553 exynos4_clocksource_init();
554 exynos4_clockevent_init();
555}
556
557
558static void __init mct_init_spi(struct device_node *np)
559{
560 return mct_init_dt(np, MCT_INT_SPI);
561}
562
563static void __init mct_init_ppi(struct device_node *np)
564{
565 return mct_init_dt(np, MCT_INT_PPI);
566}
567CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
568CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index 488c14cc8dbf..08d0c418c94a 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -54,62 +54,100 @@ struct sh_cmt_priv {
54 struct clocksource cs; 54 struct clocksource cs;
55 unsigned long total_cycles; 55 unsigned long total_cycles;
56 bool cs_enabled; 56 bool cs_enabled;
57
58 /* callbacks for CMSTR and CMCSR access */
59 unsigned long (*read_control)(void __iomem *base, unsigned long offs);
60 void (*write_control)(void __iomem *base, unsigned long offs,
61 unsigned long value);
62
63 /* callbacks for CMCNT and CMCOR access */
64 unsigned long (*read_count)(void __iomem *base, unsigned long offs);
65 void (*write_count)(void __iomem *base, unsigned long offs,
66 unsigned long value);
57}; 67};
58 68
59static DEFINE_RAW_SPINLOCK(sh_cmt_lock); 69/* Examples of supported CMT timer register layouts and I/O access widths:
70 *
71 * "16-bit counter and 16-bit control" as found on sh7263:
72 * CMSTR 0xfffec000 16-bit
73 * CMCSR 0xfffec002 16-bit
74 * CMCNT 0xfffec004 16-bit
75 * CMCOR 0xfffec006 16-bit
76 *
77 * "32-bit counter and 16-bit control" as found on sh7372, sh73a0, r8a7740:
78 * CMSTR 0xffca0000 16-bit
79 * CMCSR 0xffca0060 16-bit
80 * CMCNT 0xffca0064 32-bit
81 * CMCOR 0xffca0068 32-bit
82 */
83
84static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs)
85{
86 return ioread16(base + (offs << 1));
87}
88
89static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs)
90{
91 return ioread32(base + (offs << 2));
92}
93
94static void sh_cmt_write16(void __iomem *base, unsigned long offs,
95 unsigned long value)
96{
97 iowrite16(value, base + (offs << 1));
98}
99
100static void sh_cmt_write32(void __iomem *base, unsigned long offs,
101 unsigned long value)
102{
103 iowrite32(value, base + (offs << 2));
104}
60 105
61#define CMSTR -1 /* shared register */
62#define CMCSR 0 /* channel register */ 106#define CMCSR 0 /* channel register */
63#define CMCNT 1 /* channel register */ 107#define CMCNT 1 /* channel register */
64#define CMCOR 2 /* channel register */ 108#define CMCOR 2 /* channel register */
65 109
66static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr) 110static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_priv *p)
67{ 111{
68 struct sh_timer_config *cfg = p->pdev->dev.platform_data; 112 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
69 void __iomem *base = p->mapbase;
70 unsigned long offs;
71
72 if (reg_nr == CMSTR) {
73 offs = 0;
74 base -= cfg->channel_offset;
75 } else
76 offs = reg_nr;
77
78 if (p->width == 16)
79 offs <<= 1;
80 else {
81 offs <<= 2;
82 if ((reg_nr == CMCNT) || (reg_nr == CMCOR))
83 return ioread32(base + offs);
84 }
85 113
86 return ioread16(base + offs); 114 return p->read_control(p->mapbase - cfg->channel_offset, 0);
87} 115}
88 116
89static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr, 117static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_priv *p)
90 unsigned long value) 118{
119 return p->read_control(p->mapbase, CMCSR);
120}
121
122static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_priv *p)
123{
124 return p->read_count(p->mapbase, CMCNT);
125}
126
127static inline void sh_cmt_write_cmstr(struct sh_cmt_priv *p,
128 unsigned long value)
91{ 129{
92 struct sh_timer_config *cfg = p->pdev->dev.platform_data; 130 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
93 void __iomem *base = p->mapbase;
94 unsigned long offs;
95
96 if (reg_nr == CMSTR) {
97 offs = 0;
98 base -= cfg->channel_offset;
99 } else
100 offs = reg_nr;
101
102 if (p->width == 16)
103 offs <<= 1;
104 else {
105 offs <<= 2;
106 if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) {
107 iowrite32(value, base + offs);
108 return;
109 }
110 }
111 131
112 iowrite16(value, base + offs); 132 p->write_control(p->mapbase - cfg->channel_offset, 0, value);
133}
134
135static inline void sh_cmt_write_cmcsr(struct sh_cmt_priv *p,
136 unsigned long value)
137{
138 p->write_control(p->mapbase, CMCSR, value);
139}
140
141static inline void sh_cmt_write_cmcnt(struct sh_cmt_priv *p,
142 unsigned long value)
143{
144 p->write_count(p->mapbase, CMCNT, value);
145}
146
147static inline void sh_cmt_write_cmcor(struct sh_cmt_priv *p,
148 unsigned long value)
149{
150 p->write_count(p->mapbase, CMCOR, value);
113} 151}
114 152
115static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p, 153static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
@@ -118,15 +156,15 @@ static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
118 unsigned long v1, v2, v3; 156 unsigned long v1, v2, v3;
119 int o1, o2; 157 int o1, o2;
120 158
121 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit; 159 o1 = sh_cmt_read_cmcsr(p) & p->overflow_bit;
122 160
123 /* Make sure the timer value is stable. Stolen from acpi_pm.c */ 161 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
124 do { 162 do {
125 o2 = o1; 163 o2 = o1;
126 v1 = sh_cmt_read(p, CMCNT); 164 v1 = sh_cmt_read_cmcnt(p);
127 v2 = sh_cmt_read(p, CMCNT); 165 v2 = sh_cmt_read_cmcnt(p);
128 v3 = sh_cmt_read(p, CMCNT); 166 v3 = sh_cmt_read_cmcnt(p);
129 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit; 167 o1 = sh_cmt_read_cmcsr(p) & p->overflow_bit;
130 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) 168 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
131 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); 169 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
132 170
@@ -134,6 +172,7 @@ static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
134 return v2; 172 return v2;
135} 173}
136 174
175static DEFINE_RAW_SPINLOCK(sh_cmt_lock);
137 176
138static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start) 177static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
139{ 178{
@@ -142,14 +181,14 @@ static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
142 181
143 /* start stop register shared by multiple timer channels */ 182 /* start stop register shared by multiple timer channels */
144 raw_spin_lock_irqsave(&sh_cmt_lock, flags); 183 raw_spin_lock_irqsave(&sh_cmt_lock, flags);
145 value = sh_cmt_read(p, CMSTR); 184 value = sh_cmt_read_cmstr(p);
146 185
147 if (start) 186 if (start)
148 value |= 1 << cfg->timer_bit; 187 value |= 1 << cfg->timer_bit;
149 else 188 else
150 value &= ~(1 << cfg->timer_bit); 189 value &= ~(1 << cfg->timer_bit);
151 190
152 sh_cmt_write(p, CMSTR, value); 191 sh_cmt_write_cmstr(p, value);
153 raw_spin_unlock_irqrestore(&sh_cmt_lock, flags); 192 raw_spin_unlock_irqrestore(&sh_cmt_lock, flags);
154} 193}
155 194
@@ -173,14 +212,14 @@ static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
173 /* configure channel, periodic mode and maximum timeout */ 212 /* configure channel, periodic mode and maximum timeout */
174 if (p->width == 16) { 213 if (p->width == 16) {
175 *rate = clk_get_rate(p->clk) / 512; 214 *rate = clk_get_rate(p->clk) / 512;
176 sh_cmt_write(p, CMCSR, 0x43); 215 sh_cmt_write_cmcsr(p, 0x43);
177 } else { 216 } else {
178 *rate = clk_get_rate(p->clk) / 8; 217 *rate = clk_get_rate(p->clk) / 8;
179 sh_cmt_write(p, CMCSR, 0x01a4); 218 sh_cmt_write_cmcsr(p, 0x01a4);
180 } 219 }
181 220
182 sh_cmt_write(p, CMCOR, 0xffffffff); 221 sh_cmt_write_cmcor(p, 0xffffffff);
183 sh_cmt_write(p, CMCNT, 0); 222 sh_cmt_write_cmcnt(p, 0);
184 223
185 /* 224 /*
186 * According to the sh73a0 user's manual, as CMCNT can be operated 225 * According to the sh73a0 user's manual, as CMCNT can be operated
@@ -194,12 +233,12 @@ static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
194 * take RCLKx2 at maximum. 233 * take RCLKx2 at maximum.
195 */ 234 */
196 for (k = 0; k < 100; k++) { 235 for (k = 0; k < 100; k++) {
197 if (!sh_cmt_read(p, CMCNT)) 236 if (!sh_cmt_read_cmcnt(p))
198 break; 237 break;
199 udelay(1); 238 udelay(1);
200 } 239 }
201 240
202 if (sh_cmt_read(p, CMCNT)) { 241 if (sh_cmt_read_cmcnt(p)) {
203 dev_err(&p->pdev->dev, "cannot clear CMCNT\n"); 242 dev_err(&p->pdev->dev, "cannot clear CMCNT\n");
204 ret = -ETIMEDOUT; 243 ret = -ETIMEDOUT;
205 goto err1; 244 goto err1;
@@ -222,7 +261,7 @@ static void sh_cmt_disable(struct sh_cmt_priv *p)
222 sh_cmt_start_stop_ch(p, 0); 261 sh_cmt_start_stop_ch(p, 0);
223 262
224 /* disable interrupts in CMT block */ 263 /* disable interrupts in CMT block */
225 sh_cmt_write(p, CMCSR, 0); 264 sh_cmt_write_cmcsr(p, 0);
226 265
227 /* stop clock */ 266 /* stop clock */
228 clk_disable(p->clk); 267 clk_disable(p->clk);
@@ -270,7 +309,7 @@ static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
270 if (new_match > p->max_match_value) 309 if (new_match > p->max_match_value)
271 new_match = p->max_match_value; 310 new_match = p->max_match_value;
272 311
273 sh_cmt_write(p, CMCOR, new_match); 312 sh_cmt_write_cmcor(p, new_match);
274 313
275 now = sh_cmt_get_counter(p, &has_wrapped); 314 now = sh_cmt_get_counter(p, &has_wrapped);
276 if (has_wrapped && (new_match > p->match_value)) { 315 if (has_wrapped && (new_match > p->match_value)) {
@@ -346,7 +385,7 @@ static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
346 struct sh_cmt_priv *p = dev_id; 385 struct sh_cmt_priv *p = dev_id;
347 386
348 /* clear flags */ 387 /* clear flags */
349 sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits); 388 sh_cmt_write_cmcsr(p, sh_cmt_read_cmcsr(p) & p->clear_bits);
350 389
351 /* update clock source counter to begin with if enabled 390 /* update clock source counter to begin with if enabled
352 * the wrap flag should be cleared by the timer specific 391 * the wrap flag should be cleared by the timer specific
@@ -625,14 +664,6 @@ static int sh_cmt_register(struct sh_cmt_priv *p, char *name,
625 unsigned long clockevent_rating, 664 unsigned long clockevent_rating,
626 unsigned long clocksource_rating) 665 unsigned long clocksource_rating)
627{ 666{
628 if (p->width == (sizeof(p->max_match_value) * 8))
629 p->max_match_value = ~0;
630 else
631 p->max_match_value = (1 << p->width) - 1;
632
633 p->match_value = p->max_match_value;
634 raw_spin_lock_init(&p->lock);
635
636 if (clockevent_rating) 667 if (clockevent_rating)
637 sh_cmt_register_clockevent(p, name, clockevent_rating); 668 sh_cmt_register_clockevent(p, name, clockevent_rating);
638 669
@@ -657,8 +688,6 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
657 goto err0; 688 goto err0;
658 } 689 }
659 690
660 platform_set_drvdata(pdev, p);
661
662 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0); 691 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
663 if (!res) { 692 if (!res) {
664 dev_err(&p->pdev->dev, "failed to get I/O memory\n"); 693 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
@@ -693,32 +722,51 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
693 goto err1; 722 goto err1;
694 } 723 }
695 724
725 p->read_control = sh_cmt_read16;
726 p->write_control = sh_cmt_write16;
727
696 if (resource_size(res) == 6) { 728 if (resource_size(res) == 6) {
697 p->width = 16; 729 p->width = 16;
730 p->read_count = sh_cmt_read16;
731 p->write_count = sh_cmt_write16;
698 p->overflow_bit = 0x80; 732 p->overflow_bit = 0x80;
699 p->clear_bits = ~0x80; 733 p->clear_bits = ~0x80;
700 } else { 734 } else {
701 p->width = 32; 735 p->width = 32;
736 p->read_count = sh_cmt_read32;
737 p->write_count = sh_cmt_write32;
702 p->overflow_bit = 0x8000; 738 p->overflow_bit = 0x8000;
703 p->clear_bits = ~0xc000; 739 p->clear_bits = ~0xc000;
704 } 740 }
705 741
742 if (p->width == (sizeof(p->max_match_value) * 8))
743 p->max_match_value = ~0;
744 else
745 p->max_match_value = (1 << p->width) - 1;
746
747 p->match_value = p->max_match_value;
748 raw_spin_lock_init(&p->lock);
749
706 ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev), 750 ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev),
707 cfg->clockevent_rating, 751 cfg->clockevent_rating,
708 cfg->clocksource_rating); 752 cfg->clocksource_rating);
709 if (ret) { 753 if (ret) {
710 dev_err(&p->pdev->dev, "registration failed\n"); 754 dev_err(&p->pdev->dev, "registration failed\n");
711 goto err1; 755 goto err2;
712 } 756 }
713 p->cs_enabled = false; 757 p->cs_enabled = false;
714 758
715 ret = setup_irq(irq, &p->irqaction); 759 ret = setup_irq(irq, &p->irqaction);
716 if (ret) { 760 if (ret) {
717 dev_err(&p->pdev->dev, "failed to request irq %d\n", irq); 761 dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
718 goto err1; 762 goto err2;
719 } 763 }
720 764
765 platform_set_drvdata(pdev, p);
766
721 return 0; 767 return 0;
768err2:
769 clk_put(p->clk);
722 770
723err1: 771err1:
724 iounmap(p->mapbase); 772 iounmap(p->mapbase);
@@ -751,7 +799,6 @@ static int sh_cmt_probe(struct platform_device *pdev)
751 ret = sh_cmt_setup(p, pdev); 799 ret = sh_cmt_setup(p, pdev);
752 if (ret) { 800 if (ret) {
753 kfree(p); 801 kfree(p);
754 platform_set_drvdata(pdev, NULL);
755 pm_runtime_idle(&pdev->dev); 802 pm_runtime_idle(&pdev->dev);
756 return ret; 803 return ret;
757 } 804 }
@@ -791,7 +838,7 @@ static void __exit sh_cmt_exit(void)
791} 838}
792 839
793early_platform_init("earlytimer", &sh_cmt_device_driver); 840early_platform_init("earlytimer", &sh_cmt_device_driver);
794module_init(sh_cmt_init); 841subsys_initcall(sh_cmt_init);
795module_exit(sh_cmt_exit); 842module_exit(sh_cmt_exit);
796 843
797MODULE_AUTHOR("Magnus Damm"); 844MODULE_AUTHOR("Magnus Damm");
diff --git a/drivers/clocksource/sh_mtu2.c b/drivers/clocksource/sh_mtu2.c
index 83943e27cfac..4aac9ee0d0c0 100644
--- a/drivers/clocksource/sh_mtu2.c
+++ b/drivers/clocksource/sh_mtu2.c
@@ -386,7 +386,7 @@ static void __exit sh_mtu2_exit(void)
386} 386}
387 387
388early_platform_init("earlytimer", &sh_mtu2_device_driver); 388early_platform_init("earlytimer", &sh_mtu2_device_driver);
389module_init(sh_mtu2_init); 389subsys_initcall(sh_mtu2_init);
390module_exit(sh_mtu2_exit); 390module_exit(sh_mtu2_exit);
391 391
392MODULE_AUTHOR("Magnus Damm"); 392MODULE_AUTHOR("Magnus Damm");
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index b4502edce2a1..78b8dae49628 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -549,7 +549,7 @@ static void __exit sh_tmu_exit(void)
549} 549}
550 550
551early_platform_init("earlytimer", &sh_tmu_device_driver); 551early_platform_init("earlytimer", &sh_tmu_device_driver);
552module_init(sh_tmu_init); 552subsys_initcall(sh_tmu_init);
553module_exit(sh_tmu_exit); 553module_exit(sh_tmu_exit);
554 554
555MODULE_AUTHOR("Magnus Damm"); 555MODULE_AUTHOR("Magnus Damm");
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 93aaadf99f28..b166e30b3bc4 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -227,12 +227,6 @@ config GPIO_TS5500
227 blocks of the TS-5500: DIO1, DIO2 and the LCD port, and the TS-5600 227 blocks of the TS-5500: DIO1, DIO2 and the LCD port, and the TS-5600
228 LCD port. 228 LCD port.
229 229
230config GPIO_VT8500
231 bool "VIA/Wondermedia SoC GPIO Support"
232 depends on ARCH_VT8500
233 help
234 Say yes here to support the VT8500/WM8505/WM8650 GPIO controller.
235
236config GPIO_XILINX 230config GPIO_XILINX
237 bool "Xilinx GPIO support" 231 bool "Xilinx GPIO support"
238 depends on PPC_OF || MICROBLAZE 232 depends on PPC_OF || MICROBLAZE
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 22e07bc9fcb5..a274d7df3c8c 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -80,7 +80,6 @@ obj-$(CONFIG_GPIO_TWL6040) += gpio-twl6040.o
80obj-$(CONFIG_GPIO_UCB1400) += gpio-ucb1400.o 80obj-$(CONFIG_GPIO_UCB1400) += gpio-ucb1400.o
81obj-$(CONFIG_GPIO_VIPERBOARD) += gpio-viperboard.o 81obj-$(CONFIG_GPIO_VIPERBOARD) += gpio-viperboard.o
82obj-$(CONFIG_GPIO_VR41XX) += gpio-vr41xx.o 82obj-$(CONFIG_GPIO_VR41XX) += gpio-vr41xx.o
83obj-$(CONFIG_GPIO_VT8500) += gpio-vt8500.o
84obj-$(CONFIG_GPIO_VX855) += gpio-vx855.o 83obj-$(CONFIG_GPIO_VX855) += gpio-vx855.o
85obj-$(CONFIG_GPIO_WM831X) += gpio-wm831x.o 84obj-$(CONFIG_GPIO_WM831X) += gpio-wm831x.o
86obj-$(CONFIG_GPIO_WM8350) += gpio-wm8350.o 85obj-$(CONFIG_GPIO_WM8350) += gpio-wm8350.o
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index b3643ff007e4..99e0fa49fcbd 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -1122,8 +1122,12 @@ int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1122#ifdef CONFIG_PLAT_S3C24XX 1122#ifdef CONFIG_PLAT_S3C24XX
1123static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset) 1123static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1124{ 1124{
1125 if (offset < 4) 1125 if (offset < 4) {
1126 return IRQ_EINT0 + offset; 1126 if (soc_is_s3c2412())
1127 return IRQ_EINT0_2412 + offset;
1128 else
1129 return IRQ_EINT0 + offset;
1130 }
1127 1131
1128 if (offset < 8) 1132 if (offset < 8)
1129 return IRQ_EINT4 + offset - 4; 1133 return IRQ_EINT4 + offset - 4;
@@ -3024,6 +3028,7 @@ static __init int samsung_gpiolib_init(void)
3024 static const struct of_device_id exynos_pinctrl_ids[] = { 3028 static const struct of_device_id exynos_pinctrl_ids[] = {
3025 { .compatible = "samsung,exynos4210-pinctrl", }, 3029 { .compatible = "samsung,exynos4210-pinctrl", },
3026 { .compatible = "samsung,exynos4x12-pinctrl", }, 3030 { .compatible = "samsung,exynos4x12-pinctrl", },
3031 { .compatible = "samsung,exynos5250-pinctrl", },
3027 { .compatible = "samsung,exynos5440-pinctrl", }, 3032 { .compatible = "samsung,exynos5440-pinctrl", },
3028 }; 3033 };
3029 for_each_matching_node(pctrl_np, exynos_pinctrl_ids) 3034 for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
diff --git a/drivers/gpio/gpio-vt8500.c b/drivers/gpio/gpio-vt8500.c
deleted file mode 100644
index 81683ca35ac1..000000000000
--- a/drivers/gpio/gpio-vt8500.c
+++ /dev/null
@@ -1,355 +0,0 @@
1/* drivers/gpio/gpio-vt8500.c
2 *
3 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
4 * Based on arch/arm/mach-vt8500/gpio.c:
5 * - Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/module.h>
19#include <linux/err.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <linux/platform_device.h>
23#include <linux/bitops.h>
24#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/of_device.h>
28
29/*
30 We handle GPIOs by bank, each bank containing up to 32 GPIOs covered
31 by one set of registers (although not all may be valid).
32
33 Because different SoC's have different register offsets, we pass the
34 register offsets as data in vt8500_gpio_dt_ids[].
35
36 A value of NO_REG is used to indicate that this register is not
37 supported. Only used for ->en at the moment.
38*/
39
40#define NO_REG 0xFFFF
41
42/*
43 * struct vt8500_gpio_bank_regoffsets
44 * @en: offset to enable register of the bank
45 * @dir: offset to direction register of the bank
46 * @data_out: offset to the data out register of the bank
47 * @data_in: offset to the data in register of the bank
48 * @ngpio: highest valid pin in this bank
49 */
50
51struct vt8500_gpio_bank_regoffsets {
52 unsigned int en;
53 unsigned int dir;
54 unsigned int data_out;
55 unsigned int data_in;
56 unsigned char ngpio;
57};
58
59struct vt8500_gpio_data {
60 unsigned int num_banks;
61 struct vt8500_gpio_bank_regoffsets banks[];
62};
63
64#define VT8500_BANK(__en, __dir, __out, __in, __ngpio) \
65{ \
66 .en = __en, \
67 .dir = __dir, \
68 .data_out = __out, \
69 .data_in = __in, \
70 .ngpio = __ngpio, \
71}
72
73static struct vt8500_gpio_data vt8500_data = {
74 .num_banks = 7,
75 .banks = {
76 VT8500_BANK(NO_REG, 0x3C, 0x5C, 0x7C, 9),
77 VT8500_BANK(0x00, 0x20, 0x40, 0x60, 26),
78 VT8500_BANK(0x04, 0x24, 0x44, 0x64, 28),
79 VT8500_BANK(0x08, 0x28, 0x48, 0x68, 31),
80 VT8500_BANK(0x0C, 0x2C, 0x4C, 0x6C, 19),
81 VT8500_BANK(0x10, 0x30, 0x50, 0x70, 19),
82 VT8500_BANK(0x14, 0x34, 0x54, 0x74, 23),
83 },
84};
85
86static struct vt8500_gpio_data wm8505_data = {
87 .num_banks = 10,
88 .banks = {
89 VT8500_BANK(0x64, 0x8C, 0xB4, 0xDC, 22),
90 VT8500_BANK(0x40, 0x68, 0x90, 0xB8, 8),
91 VT8500_BANK(0x44, 0x6C, 0x94, 0xBC, 32),
92 VT8500_BANK(0x48, 0x70, 0x98, 0xC0, 6),
93 VT8500_BANK(0x4C, 0x74, 0x9C, 0xC4, 16),
94 VT8500_BANK(0x50, 0x78, 0xA0, 0xC8, 25),
95 VT8500_BANK(0x54, 0x7C, 0xA4, 0xCC, 5),
96 VT8500_BANK(0x58, 0x80, 0xA8, 0xD0, 5),
97 VT8500_BANK(0x5C, 0x84, 0xAC, 0xD4, 12),
98 VT8500_BANK(0x60, 0x88, 0xB0, 0xD8, 16),
99 VT8500_BANK(0x500, 0x504, 0x508, 0x50C, 6),
100 },
101};
102
103/*
104 * No information about which bits are valid so we just make
105 * them all available until its figured out.
106 */
107static struct vt8500_gpio_data wm8650_data = {
108 .num_banks = 9,
109 .banks = {
110 VT8500_BANK(0x40, 0x80, 0xC0, 0x00, 32),
111 VT8500_BANK(0x44, 0x84, 0xC4, 0x04, 32),
112 VT8500_BANK(0x48, 0x88, 0xC8, 0x08, 32),
113 VT8500_BANK(0x4C, 0x8C, 0xCC, 0x0C, 32),
114 VT8500_BANK(0x50, 0x90, 0xD0, 0x10, 32),
115 VT8500_BANK(0x54, 0x94, 0xD4, 0x14, 32),
116 VT8500_BANK(0x58, 0x98, 0xD8, 0x18, 32),
117 VT8500_BANK(0x5C, 0x9C, 0xDC, 0x1C, 32),
118 VT8500_BANK(0x7C, 0xBC, 0xFC, 0x3C, 32),
119 VT8500_BANK(0x500, 0x504, 0x508, 0x50C, 6),
120 },
121};
122
123struct vt8500_gpio_chip {
124 struct gpio_chip chip;
125
126 const struct vt8500_gpio_bank_regoffsets *regs;
127 void __iomem *base;
128};
129
130struct vt8500_data {
131 struct vt8500_gpio_chip *chip;
132 void __iomem *iobase;
133 int num_banks;
134};
135
136
137#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip)
138
139static int vt8500_gpio_request(struct gpio_chip *chip, unsigned offset)
140{
141 u32 val;
142 struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
143
144 if (vt8500_chip->regs->en == NO_REG)
145 return 0;
146
147 val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->en);
148 val |= BIT(offset);
149 writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->en);
150
151 return 0;
152}
153
154static void vt8500_gpio_free(struct gpio_chip *chip, unsigned offset)
155{
156 struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
157 u32 val;
158
159 if (vt8500_chip->regs->en == NO_REG)
160 return;
161
162 val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->en);
163 val &= ~BIT(offset);
164 writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->en);
165}
166
167static int vt8500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
168{
169 struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
170
171 u32 val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->dir);
172 val &= ~BIT(offset);
173 writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->dir);
174
175 return 0;
176}
177
178static int vt8500_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
179 int value)
180{
181 struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
182
183 u32 val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->dir);
184 val |= BIT(offset);
185 writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->dir);
186
187 if (value) {
188 val = readl_relaxed(vt8500_chip->base +
189 vt8500_chip->regs->data_out);
190 val |= BIT(offset);
191 writel_relaxed(val, vt8500_chip->base +
192 vt8500_chip->regs->data_out);
193 }
194 return 0;
195}
196
197static int vt8500_gpio_get_value(struct gpio_chip *chip, unsigned offset)
198{
199 struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
200
201 return (readl_relaxed(vt8500_chip->base + vt8500_chip->regs->data_in) >>
202 offset) & 1;
203}
204
205static void vt8500_gpio_set_value(struct gpio_chip *chip, unsigned offset,
206 int value)
207{
208 struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
209
210 u32 val = readl_relaxed(vt8500_chip->base +
211 vt8500_chip->regs->data_out);
212 if (value)
213 val |= BIT(offset);
214 else
215 val &= ~BIT(offset);
216
217 writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->data_out);
218}
219
220static int vt8500_of_xlate(struct gpio_chip *gc,
221 const struct of_phandle_args *gpiospec, u32 *flags)
222{
223 /* bank if specificed in gpiospec->args[0] */
224 if (flags)
225 *flags = gpiospec->args[2];
226
227 return gpiospec->args[1];
228}
229
230static int vt8500_add_chips(struct platform_device *pdev, void __iomem *base,
231 const struct vt8500_gpio_data *data)
232{
233 struct vt8500_data *priv;
234 struct vt8500_gpio_chip *vtchip;
235 struct gpio_chip *chip;
236 int i;
237 int pin_cnt = 0;
238
239 priv = devm_kzalloc(&pdev->dev, sizeof(struct vt8500_data), GFP_KERNEL);
240 if (!priv) {
241 dev_err(&pdev->dev, "failed to allocate memory\n");
242 return -ENOMEM;
243 }
244
245 priv->chip = devm_kzalloc(&pdev->dev,
246 sizeof(struct vt8500_gpio_chip) * data->num_banks,
247 GFP_KERNEL);
248 if (!priv->chip) {
249 dev_err(&pdev->dev, "failed to allocate chip memory\n");
250 return -ENOMEM;
251 }
252
253 priv->iobase = base;
254 priv->num_banks = data->num_banks;
255 platform_set_drvdata(pdev, priv);
256
257 vtchip = priv->chip;
258
259 for (i = 0; i < data->num_banks; i++) {
260 vtchip[i].base = base;
261 vtchip[i].regs = &data->banks[i];
262
263 chip = &vtchip[i].chip;
264
265 chip->of_xlate = vt8500_of_xlate;
266 chip->of_gpio_n_cells = 3;
267 chip->of_node = pdev->dev.of_node;
268
269 chip->request = vt8500_gpio_request;
270 chip->free = vt8500_gpio_free;
271 chip->direction_input = vt8500_gpio_direction_input;
272 chip->direction_output = vt8500_gpio_direction_output;
273 chip->get = vt8500_gpio_get_value;
274 chip->set = vt8500_gpio_set_value;
275 chip->can_sleep = 0;
276 chip->base = pin_cnt;
277 chip->ngpio = data->banks[i].ngpio;
278
279 pin_cnt += data->banks[i].ngpio;
280
281 gpiochip_add(chip);
282 }
283 return 0;
284}
285
286static struct of_device_id vt8500_gpio_dt_ids[] = {
287 { .compatible = "via,vt8500-gpio", .data = &vt8500_data, },
288 { .compatible = "wm,wm8505-gpio", .data = &wm8505_data, },
289 { .compatible = "wm,wm8650-gpio", .data = &wm8650_data, },
290 { /* Sentinel */ },
291};
292
293static int vt8500_gpio_probe(struct platform_device *pdev)
294{
295 int ret;
296 void __iomem *gpio_base;
297 struct resource *res;
298 const struct of_device_id *of_id =
299 of_match_device(vt8500_gpio_dt_ids, &pdev->dev);
300
301 if (!of_id) {
302 dev_err(&pdev->dev, "No matching driver data\n");
303 return -ENODEV;
304 }
305
306 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
307 if (!res) {
308 dev_err(&pdev->dev, "Unable to get IO resource\n");
309 return -ENODEV;
310 }
311
312 gpio_base = devm_request_and_ioremap(&pdev->dev, res);
313 if (!gpio_base) {
314 dev_err(&pdev->dev, "Unable to map GPIO registers\n");
315 return -ENOMEM;
316 }
317
318 ret = vt8500_add_chips(pdev, gpio_base, of_id->data);
319
320 return ret;
321}
322
323static int vt8500_gpio_remove(struct platform_device *pdev)
324{
325 int i;
326 int ret;
327 struct vt8500_data *priv = platform_get_drvdata(pdev);
328 struct vt8500_gpio_chip *vtchip = priv->chip;
329
330 for (i = 0; i < priv->num_banks; i++) {
331 ret = gpiochip_remove(&vtchip[i].chip);
332 if (ret)
333 dev_warn(&pdev->dev, "gpiochip_remove returned %d\n",
334 ret);
335 }
336
337 return 0;
338}
339
340static struct platform_driver vt8500_gpio_driver = {
341 .probe = vt8500_gpio_probe,
342 .remove = vt8500_gpio_remove,
343 .driver = {
344 .name = "vt8500-gpio",
345 .owner = THIS_MODULE,
346 .of_match_table = vt8500_gpio_dt_ids,
347 },
348};
349
350module_platform_driver(vt8500_gpio_driver);
351
352MODULE_DESCRIPTION("VT8500 GPIO Driver");
353MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
354MODULE_LICENSE("GPL v2");
355MODULE_DEVICE_TABLE(of, vt8500_gpio_dt_ids);
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index a350969e5efe..4a33351c25dc 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -25,6 +25,14 @@ config ARM_VIC_NR
25 The maximum number of VICs available in the system, for 25 The maximum number of VICs available in the system, for
26 power management. 26 power management.
27 27
28config RENESAS_INTC_IRQPIN
29 bool
30 select IRQ_DOMAIN
31
32config RENESAS_IRQC
33 bool
34 select IRQ_DOMAIN
35
28config VERSATILE_FPGA_IRQ 36config VERSATILE_FPGA_IRQ
29 bool 37 bool
30 select IRQ_DOMAIN 38 select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 10ef57f35a6e..c28fcccf4a0d 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o
3obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o 3obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
4obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o 4obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
5obj-$(CONFIG_ARCH_MXS) += irq-mxs.o 5obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
6obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
6obj-$(CONFIG_METAG) += irq-metag-ext.o 7obj-$(CONFIG_METAG) += irq-metag-ext.o
7obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o 8obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
8obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o 9obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
@@ -10,4 +11,7 @@ obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
10obj-$(CONFIG_ARM_GIC) += irq-gic.o 11obj-$(CONFIG_ARM_GIC) += irq-gic.o
11obj-$(CONFIG_ARM_VIC) += irq-vic.o 12obj-$(CONFIG_ARM_VIC) += irq-vic.o
12obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o 13obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o
14obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
15obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
13obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o 16obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
17obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
index 6a5201351507..02492ab20d22 100644
--- a/drivers/irqchip/exynos-combiner.c
+++ b/drivers/irqchip/exynos-combiner.c
@@ -32,6 +32,7 @@ struct combiner_chip_data {
32 unsigned int irq_offset; 32 unsigned int irq_offset;
33 unsigned int irq_mask; 33 unsigned int irq_mask;
34 void __iomem *base; 34 void __iomem *base;
35 unsigned int parent_irq;
35}; 36};
36 37
37static struct irq_domain *combiner_irq_domain; 38static struct irq_domain *combiner_irq_domain;
@@ -88,22 +89,46 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
88 chained_irq_exit(chip, desc); 89 chained_irq_exit(chip, desc);
89} 90}
90 91
92#ifdef CONFIG_SMP
93static int combiner_set_affinity(struct irq_data *d,
94 const struct cpumask *mask_val, bool force)
95{
96 struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
97 struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
98 struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);
99
100 if (chip && chip->irq_set_affinity)
101 return chip->irq_set_affinity(data, mask_val, force);
102 else
103 return -EINVAL;
104}
105#endif
106
91static struct irq_chip combiner_chip = { 107static struct irq_chip combiner_chip = {
92 .name = "COMBINER", 108 .name = "COMBINER",
93 .irq_mask = combiner_mask_irq, 109 .irq_mask = combiner_mask_irq,
94 .irq_unmask = combiner_unmask_irq, 110 .irq_unmask = combiner_unmask_irq,
111#ifdef CONFIG_SMP
112 .irq_set_affinity = combiner_set_affinity,
113#endif
95}; 114};
96 115
97static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) 116static unsigned int max_combiner_nr(void)
98{ 117{
99 unsigned int max_nr;
100
101 if (soc_is_exynos5250()) 118 if (soc_is_exynos5250())
102 max_nr = EXYNOS5_MAX_COMBINER_NR; 119 return EXYNOS5_MAX_COMBINER_NR;
120 else if (soc_is_exynos4412())
121 return EXYNOS4412_MAX_COMBINER_NR;
122 else if (soc_is_exynos4212())
123 return EXYNOS4212_MAX_COMBINER_NR;
103 else 124 else
104 max_nr = EXYNOS4_MAX_COMBINER_NR; 125 return EXYNOS4210_MAX_COMBINER_NR;
126}
105 127
106 if (combiner_nr >= max_nr) 128static void __init combiner_cascade_irq(unsigned int combiner_nr,
129 unsigned int irq)
130{
131 if (combiner_nr >= max_combiner_nr())
107 BUG(); 132 BUG();
108 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0) 133 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
109 BUG(); 134 BUG();
@@ -111,12 +136,13 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
111} 136}
112 137
113static void __init combiner_init_one(unsigned int combiner_nr, 138static void __init combiner_init_one(unsigned int combiner_nr,
114 void __iomem *base) 139 void __iomem *base, unsigned int irq)
115{ 140{
116 combiner_data[combiner_nr].base = base; 141 combiner_data[combiner_nr].base = base;
117 combiner_data[combiner_nr].irq_offset = irq_find_mapping( 142 combiner_data[combiner_nr].irq_offset = irq_find_mapping(
118 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER); 143 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
119 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3); 144 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
145 combiner_data[combiner_nr].parent_irq = irq;
120 146
121 /* Disable all interrupts */ 147 /* Disable all interrupts */
122 __raw_writel(combiner_data[combiner_nr].irq_mask, 148 __raw_writel(combiner_data[combiner_nr].irq_mask,
@@ -167,23 +193,38 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
167 .map = combiner_irq_domain_map, 193 .map = combiner_irq_domain_map,
168}; 194};
169 195
196static unsigned int exynos4x12_combiner_extra_irq(int group)
197{
198 switch (group) {
199 case 16:
200 return IRQ_SPI(107);
201 case 17:
202 return IRQ_SPI(108);
203 case 18:
204 return IRQ_SPI(48);
205 case 19:
206 return IRQ_SPI(42);
207 default:
208 return 0;
209 }
210}
211
170void __init combiner_init(void __iomem *combiner_base, 212void __init combiner_init(void __iomem *combiner_base,
171 struct device_node *np) 213 struct device_node *np)
172{ 214{
173 int i, irq, irq_base; 215 int i, irq, irq_base;
174 unsigned int max_nr, nr_irq; 216 unsigned int max_nr, nr_irq;
175 217
218 max_nr = max_combiner_nr();
219
176 if (np) { 220 if (np) {
177 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) { 221 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
178 pr_warning("%s: number of combiners not specified, " 222 pr_info("%s: number of combiners not specified, "
179 "setting default as %d.\n", 223 "setting default as %d.\n",
180 __func__, EXYNOS4_MAX_COMBINER_NR); 224 __func__, max_nr);
181 max_nr = EXYNOS4_MAX_COMBINER_NR;
182 } 225 }
183 } else {
184 max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
185 EXYNOS4_MAX_COMBINER_NR;
186 } 226 }
227
187 nr_irq = max_nr * MAX_IRQ_IN_COMBINER; 228 nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
188 229
189 irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0); 230 irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
@@ -200,12 +241,15 @@ void __init combiner_init(void __iomem *combiner_base,
200 } 241 }
201 242
202 for (i = 0; i < max_nr; i++) { 243 for (i = 0; i < max_nr; i++) {
203 combiner_init_one(i, combiner_base + (i >> 2) * 0x10); 244 if (i < EXYNOS4210_MAX_COMBINER_NR || soc_is_exynos5250())
204 irq = IRQ_SPI(i); 245 irq = IRQ_SPI(i);
246 else
247 irq = exynos4x12_combiner_extra_irq(i);
205#ifdef CONFIG_OF 248#ifdef CONFIG_OF
206 if (np) 249 if (np)
207 irq = irq_of_parse_and_map(np, i); 250 irq = irq_of_parse_and_map(np, i);
208#endif 251#endif
252 combiner_init_one(i, combiner_base + (i >> 2) * 0x10, irq);
209 combiner_cascade_irq(i, irq); 253 combiner_cascade_irq(i, irq);
210 } 254 }
211} 255}
diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c
new file mode 100644
index 000000000000..5a68e5accec1
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-intc-irqpin.c
@@ -0,0 +1,547 @@
1/*
2 * Renesas INTC External IRQ Pin Driver
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/irqdomain.h>
28#include <linux/err.h>
29#include <linux/slab.h>
30#include <linux/module.h>
31#include <linux/platform_data/irq-renesas-intc-irqpin.h>
32
33#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
34
35#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
36#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
37#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
38#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
39#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
40#define INTC_IRQPIN_REG_NR 5
41
42/* INTC external IRQ PIN hardware register access:
43 *
44 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
45 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
46 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
47 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
48 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
49 *
50 * (*) May be accessed by more than one driver instance - lock needed
51 * (**) Read-modify-write access by one driver instance - lock needed
52 * (***) Accessed by one driver instance only - no locking needed
53 */
54
55struct intc_irqpin_iomem {
56 void __iomem *iomem;
57 unsigned long (*read)(void __iomem *iomem);
58 void (*write)(void __iomem *iomem, unsigned long data);
59 int width;
60};
61
62struct intc_irqpin_irq {
63 int hw_irq;
64 int requested_irq;
65 int domain_irq;
66 struct intc_irqpin_priv *p;
67};
68
69struct intc_irqpin_priv {
70 struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
71 struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
72 struct renesas_intc_irqpin_config config;
73 unsigned int number_of_irqs;
74 struct platform_device *pdev;
75 struct irq_chip irq_chip;
76 struct irq_domain *irq_domain;
77 bool shared_irqs;
78 u8 shared_irq_mask;
79};
80
81static unsigned long intc_irqpin_read32(void __iomem *iomem)
82{
83 return ioread32(iomem);
84}
85
86static unsigned long intc_irqpin_read8(void __iomem *iomem)
87{
88 return ioread8(iomem);
89}
90
91static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
92{
93 iowrite32(data, iomem);
94}
95
96static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
97{
98 iowrite8(data, iomem);
99}
100
101static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
102 int reg)
103{
104 struct intc_irqpin_iomem *i = &p->iomem[reg];
105
106 return i->read(i->iomem);
107}
108
109static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
110 int reg, unsigned long data)
111{
112 struct intc_irqpin_iomem *i = &p->iomem[reg];
113
114 i->write(i->iomem, data);
115}
116
117static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
118 int reg, int hw_irq)
119{
120 return BIT((p->iomem[reg].width - 1) - hw_irq);
121}
122
123static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
124 int reg, int hw_irq)
125{
126 intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
127}
128
129static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
130
131static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
132 int reg, int shift,
133 int width, int value)
134{
135 unsigned long flags;
136 unsigned long tmp;
137
138 raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
139
140 tmp = intc_irqpin_read(p, reg);
141 tmp &= ~(((1 << width) - 1) << shift);
142 tmp |= value << shift;
143 intc_irqpin_write(p, reg, tmp);
144
145 raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
146}
147
148static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
149 int irq, int do_mask)
150{
151 int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */
152 int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */
153
154 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
155 shift, bitfield_width,
156 do_mask ? 0 : (1 << bitfield_width) - 1);
157}
158
159static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
160{
161 int bitfield_width = p->config.sense_bitfield_width;
162 int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */
163
164 dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
165
166 if (value >= (1 << bitfield_width))
167 return -EINVAL;
168
169 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
170 bitfield_width, value);
171 return 0;
172}
173
174static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
175{
176 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
177 str, i->requested_irq, i->hw_irq, i->domain_irq);
178}
179
180static void intc_irqpin_irq_enable(struct irq_data *d)
181{
182 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
183 int hw_irq = irqd_to_hwirq(d);
184
185 intc_irqpin_dbg(&p->irq[hw_irq], "enable");
186 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
187}
188
189static void intc_irqpin_irq_disable(struct irq_data *d)
190{
191 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
192 int hw_irq = irqd_to_hwirq(d);
193
194 intc_irqpin_dbg(&p->irq[hw_irq], "disable");
195 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
196}
197
198static void intc_irqpin_shared_irq_enable(struct irq_data *d)
199{
200 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
201 int hw_irq = irqd_to_hwirq(d);
202
203 intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
204 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
205
206 p->shared_irq_mask &= ~BIT(hw_irq);
207}
208
209static void intc_irqpin_shared_irq_disable(struct irq_data *d)
210{
211 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
212 int hw_irq = irqd_to_hwirq(d);
213
214 intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
215 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
216
217 p->shared_irq_mask |= BIT(hw_irq);
218}
219
220static void intc_irqpin_irq_enable_force(struct irq_data *d)
221{
222 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
223 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
224
225 intc_irqpin_irq_enable(d);
226
227 /* enable interrupt through parent interrupt controller,
228 * assumes non-shared interrupt with 1:1 mapping
229 * needed for busted IRQs on some SoCs like sh73a0
230 */
231 irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
232}
233
234static void intc_irqpin_irq_disable_force(struct irq_data *d)
235{
236 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
237 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
238
239 /* disable interrupt through parent interrupt controller,
240 * assumes non-shared interrupt with 1:1 mapping
241 * needed for busted IRQs on some SoCs like sh73a0
242 */
243 irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
244 intc_irqpin_irq_disable(d);
245}
246
247#define INTC_IRQ_SENSE_VALID 0x10
248#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
249
250static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
251 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
252 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
253 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
254 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
255 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
256};
257
258static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
259{
260 unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
261 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
262
263 if (!(value & INTC_IRQ_SENSE_VALID))
264 return -EINVAL;
265
266 return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
267 value ^ INTC_IRQ_SENSE_VALID);
268}
269
270static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
271{
272 struct intc_irqpin_irq *i = dev_id;
273 struct intc_irqpin_priv *p = i->p;
274 unsigned long bit;
275
276 intc_irqpin_dbg(i, "demux1");
277 bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
278
279 if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
280 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
281 intc_irqpin_dbg(i, "demux2");
282 generic_handle_irq(i->domain_irq);
283 return IRQ_HANDLED;
284 }
285 return IRQ_NONE;
286}
287
288static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
289{
290 struct intc_irqpin_priv *p = dev_id;
291 unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
292 irqreturn_t status = IRQ_NONE;
293 int k;
294
295 for (k = 0; k < 8; k++) {
296 if (reg_source & BIT(7 - k)) {
297 if (BIT(k) & p->shared_irq_mask)
298 continue;
299
300 status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
301 }
302 }
303
304 return status;
305}
306
307static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
308 irq_hw_number_t hw)
309{
310 struct intc_irqpin_priv *p = h->host_data;
311
312 p->irq[hw].domain_irq = virq;
313 p->irq[hw].hw_irq = hw;
314
315 intc_irqpin_dbg(&p->irq[hw], "map");
316 irq_set_chip_data(virq, h->host_data);
317 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
318 set_irq_flags(virq, IRQF_VALID); /* kill me now */
319 return 0;
320}
321
322static struct irq_domain_ops intc_irqpin_irq_domain_ops = {
323 .map = intc_irqpin_irq_domain_map,
324 .xlate = irq_domain_xlate_twocell,
325};
326
327static int intc_irqpin_probe(struct platform_device *pdev)
328{
329 struct renesas_intc_irqpin_config *pdata = pdev->dev.platform_data;
330 struct intc_irqpin_priv *p;
331 struct intc_irqpin_iomem *i;
332 struct resource *io[INTC_IRQPIN_REG_NR];
333 struct resource *irq;
334 struct irq_chip *irq_chip;
335 void (*enable_fn)(struct irq_data *d);
336 void (*disable_fn)(struct irq_data *d);
337 const char *name = dev_name(&pdev->dev);
338 int ref_irq;
339 int ret;
340 int k;
341
342 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
343 if (!p) {
344 dev_err(&pdev->dev, "failed to allocate driver data\n");
345 ret = -ENOMEM;
346 goto err0;
347 }
348
349 /* deal with driver instance configuration */
350 if (pdata)
351 memcpy(&p->config, pdata, sizeof(*pdata));
352 if (!p->config.sense_bitfield_width)
353 p->config.sense_bitfield_width = 4; /* default to 4 bits */
354
355 p->pdev = pdev;
356 platform_set_drvdata(pdev, p);
357
358 /* get hold of manadatory IOMEM */
359 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
360 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
361 if (!io[k]) {
362 dev_err(&pdev->dev, "not enough IOMEM resources\n");
363 ret = -EINVAL;
364 goto err0;
365 }
366 }
367
368 /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
369 for (k = 0; k < INTC_IRQPIN_MAX; k++) {
370 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
371 if (!irq)
372 break;
373
374 p->irq[k].p = p;
375 p->irq[k].requested_irq = irq->start;
376 }
377
378 p->number_of_irqs = k;
379 if (p->number_of_irqs < 1) {
380 dev_err(&pdev->dev, "not enough IRQ resources\n");
381 ret = -EINVAL;
382 goto err0;
383 }
384
385 /* ioremap IOMEM and setup read/write callbacks */
386 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
387 i = &p->iomem[k];
388
389 switch (resource_size(io[k])) {
390 case 1:
391 i->width = 8;
392 i->read = intc_irqpin_read8;
393 i->write = intc_irqpin_write8;
394 break;
395 case 4:
396 i->width = 32;
397 i->read = intc_irqpin_read32;
398 i->write = intc_irqpin_write32;
399 break;
400 default:
401 dev_err(&pdev->dev, "IOMEM size mismatch\n");
402 ret = -EINVAL;
403 goto err0;
404 }
405
406 i->iomem = devm_ioremap_nocache(&pdev->dev, io[k]->start,
407 resource_size(io[k]));
408 if (!i->iomem) {
409 dev_err(&pdev->dev, "failed to remap IOMEM\n");
410 ret = -ENXIO;
411 goto err0;
412 }
413 }
414
415 /* mask all interrupts using priority */
416 for (k = 0; k < p->number_of_irqs; k++)
417 intc_irqpin_mask_unmask_prio(p, k, 1);
418
419 /* clear all pending interrupts */
420 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
421
422 /* scan for shared interrupt lines */
423 ref_irq = p->irq[0].requested_irq;
424 p->shared_irqs = true;
425 for (k = 1; k < p->number_of_irqs; k++) {
426 if (ref_irq != p->irq[k].requested_irq) {
427 p->shared_irqs = false;
428 break;
429 }
430 }
431
432 /* use more severe masking method if requested */
433 if (p->config.control_parent) {
434 enable_fn = intc_irqpin_irq_enable_force;
435 disable_fn = intc_irqpin_irq_disable_force;
436 } else if (!p->shared_irqs) {
437 enable_fn = intc_irqpin_irq_enable;
438 disable_fn = intc_irqpin_irq_disable;
439 } else {
440 enable_fn = intc_irqpin_shared_irq_enable;
441 disable_fn = intc_irqpin_shared_irq_disable;
442 }
443
444 irq_chip = &p->irq_chip;
445 irq_chip->name = name;
446 irq_chip->irq_mask = disable_fn;
447 irq_chip->irq_unmask = enable_fn;
448 irq_chip->irq_enable = enable_fn;
449 irq_chip->irq_disable = disable_fn;
450 irq_chip->irq_set_type = intc_irqpin_irq_set_type;
451 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
452
453 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
454 p->number_of_irqs,
455 p->config.irq_base,
456 &intc_irqpin_irq_domain_ops, p);
457 if (!p->irq_domain) {
458 ret = -ENXIO;
459 dev_err(&pdev->dev, "cannot initialize irq domain\n");
460 goto err0;
461 }
462
463 if (p->shared_irqs) {
464 /* request one shared interrupt */
465 if (devm_request_irq(&pdev->dev, p->irq[0].requested_irq,
466 intc_irqpin_shared_irq_handler,
467 IRQF_SHARED, name, p)) {
468 dev_err(&pdev->dev, "failed to request low IRQ\n");
469 ret = -ENOENT;
470 goto err1;
471 }
472 } else {
473 /* request interrupts one by one */
474 for (k = 0; k < p->number_of_irqs; k++) {
475 if (devm_request_irq(&pdev->dev,
476 p->irq[k].requested_irq,
477 intc_irqpin_irq_handler,
478 0, name, &p->irq[k])) {
479 dev_err(&pdev->dev,
480 "failed to request low IRQ\n");
481 ret = -ENOENT;
482 goto err1;
483 }
484 }
485 }
486
487 /* unmask all interrupts on prio level */
488 for (k = 0; k < p->number_of_irqs; k++)
489 intc_irqpin_mask_unmask_prio(p, k, 0);
490
491 dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
492
493 /* warn in case of mismatch if irq base is specified */
494 if (p->config.irq_base) {
495 if (p->config.irq_base != p->irq[0].domain_irq)
496 dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
497 p->config.irq_base, p->irq[0].domain_irq);
498 }
499
500 return 0;
501
502err1:
503 irq_domain_remove(p->irq_domain);
504err0:
505 return ret;
506}
507
508static int intc_irqpin_remove(struct platform_device *pdev)
509{
510 struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
511
512 irq_domain_remove(p->irq_domain);
513
514 return 0;
515}
516
517static const struct of_device_id intc_irqpin_dt_ids[] = {
518 { .compatible = "renesas,intc-irqpin", },
519 {},
520};
521MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
522
523static struct platform_driver intc_irqpin_device_driver = {
524 .probe = intc_irqpin_probe,
525 .remove = intc_irqpin_remove,
526 .driver = {
527 .name = "renesas_intc_irqpin",
528 .of_match_table = intc_irqpin_dt_ids,
529 .owner = THIS_MODULE,
530 }
531};
532
533static int __init intc_irqpin_init(void)
534{
535 return platform_driver_register(&intc_irqpin_device_driver);
536}
537postcore_initcall(intc_irqpin_init);
538
539static void __exit intc_irqpin_exit(void)
540{
541 platform_driver_unregister(&intc_irqpin_device_driver);
542}
543module_exit(intc_irqpin_exit);
544
545MODULE_AUTHOR("Magnus Damm");
546MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
547MODULE_LICENSE("GPL v2");
diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c
new file mode 100644
index 000000000000..927bff373aac
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-irqc.c
@@ -0,0 +1,307 @@
1/*
2 * Renesas IRQC Driver
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/irqdomain.h>
28#include <linux/err.h>
29#include <linux/slab.h>
30#include <linux/module.h>
31#include <linux/platform_data/irq-renesas-irqc.h>
32
33#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
34
35#define IRQC_REQ_STS 0x00
36#define IRQC_EN_STS 0x04
37#define IRQC_EN_SET 0x08
38#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
39#define DETECT_STATUS 0x100
40#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
41
42struct irqc_irq {
43 int hw_irq;
44 int requested_irq;
45 int domain_irq;
46 struct irqc_priv *p;
47};
48
49struct irqc_priv {
50 void __iomem *iomem;
51 void __iomem *cpu_int_base;
52 struct irqc_irq irq[IRQC_IRQ_MAX];
53 struct renesas_irqc_config config;
54 unsigned int number_of_irqs;
55 struct platform_device *pdev;
56 struct irq_chip irq_chip;
57 struct irq_domain *irq_domain;
58};
59
60static void irqc_dbg(struct irqc_irq *i, char *str)
61{
62 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
63 str, i->requested_irq, i->hw_irq, i->domain_irq);
64}
65
66static void irqc_irq_enable(struct irq_data *d)
67{
68 struct irqc_priv *p = irq_data_get_irq_chip_data(d);
69 int hw_irq = irqd_to_hwirq(d);
70
71 irqc_dbg(&p->irq[hw_irq], "enable");
72 iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET);
73}
74
75static void irqc_irq_disable(struct irq_data *d)
76{
77 struct irqc_priv *p = irq_data_get_irq_chip_data(d);
78 int hw_irq = irqd_to_hwirq(d);
79
80 irqc_dbg(&p->irq[hw_irq], "disable");
81 iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS);
82}
83
84#define INTC_IRQ_SENSE_VALID 0x10
85#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
86
87static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
88 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x01),
89 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x02),
90 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x04), /* Synchronous */
91 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x08), /* Synchronous */
92 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x0c), /* Synchronous */
93};
94
95static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
96{
97 struct irqc_priv *p = irq_data_get_irq_chip_data(d);
98 int hw_irq = irqd_to_hwirq(d);
99 unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
100 unsigned long tmp;
101
102 irqc_dbg(&p->irq[hw_irq], "sense");
103
104 if (!(value & INTC_IRQ_SENSE_VALID))
105 return -EINVAL;
106
107 tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
108 tmp &= ~0x3f;
109 tmp |= value ^ INTC_IRQ_SENSE_VALID;
110 iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
111 return 0;
112}
113
114static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
115{
116 struct irqc_irq *i = dev_id;
117 struct irqc_priv *p = i->p;
118 unsigned long bit = BIT(i->hw_irq);
119
120 irqc_dbg(i, "demux1");
121
122 if (ioread32(p->iomem + DETECT_STATUS) & bit) {
123 iowrite32(bit, p->iomem + DETECT_STATUS);
124 irqc_dbg(i, "demux2");
125 generic_handle_irq(i->domain_irq);
126 return IRQ_HANDLED;
127 }
128 return IRQ_NONE;
129}
130
131static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq,
132 irq_hw_number_t hw)
133{
134 struct irqc_priv *p = h->host_data;
135
136 p->irq[hw].domain_irq = virq;
137 p->irq[hw].hw_irq = hw;
138
139 irqc_dbg(&p->irq[hw], "map");
140 irq_set_chip_data(virq, h->host_data);
141 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
142 set_irq_flags(virq, IRQF_VALID); /* kill me now */
143 return 0;
144}
145
146static struct irq_domain_ops irqc_irq_domain_ops = {
147 .map = irqc_irq_domain_map,
148 .xlate = irq_domain_xlate_twocell,
149};
150
151static int irqc_probe(struct platform_device *pdev)
152{
153 struct renesas_irqc_config *pdata = pdev->dev.platform_data;
154 struct irqc_priv *p;
155 struct resource *io;
156 struct resource *irq;
157 struct irq_chip *irq_chip;
158 const char *name = dev_name(&pdev->dev);
159 int ret;
160 int k;
161
162 p = kzalloc(sizeof(*p), GFP_KERNEL);
163 if (!p) {
164 dev_err(&pdev->dev, "failed to allocate driver data\n");
165 ret = -ENOMEM;
166 goto err0;
167 }
168
169 /* deal with driver instance configuration */
170 if (pdata)
171 memcpy(&p->config, pdata, sizeof(*pdata));
172
173 p->pdev = pdev;
174 platform_set_drvdata(pdev, p);
175
176 /* get hold of manadatory IOMEM */
177 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
178 if (!io) {
179 dev_err(&pdev->dev, "not enough IOMEM resources\n");
180 ret = -EINVAL;
181 goto err1;
182 }
183
184 /* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
185 for (k = 0; k < IRQC_IRQ_MAX; k++) {
186 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
187 if (!irq)
188 break;
189
190 p->irq[k].p = p;
191 p->irq[k].requested_irq = irq->start;
192 }
193
194 p->number_of_irqs = k;
195 if (p->number_of_irqs < 1) {
196 dev_err(&pdev->dev, "not enough IRQ resources\n");
197 ret = -EINVAL;
198 goto err1;
199 }
200
201 /* ioremap IOMEM and setup read/write callbacks */
202 p->iomem = ioremap_nocache(io->start, resource_size(io));
203 if (!p->iomem) {
204 dev_err(&pdev->dev, "failed to remap IOMEM\n");
205 ret = -ENXIO;
206 goto err2;
207 }
208
209 p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */
210
211 irq_chip = &p->irq_chip;
212 irq_chip->name = name;
213 irq_chip->irq_mask = irqc_irq_disable;
214 irq_chip->irq_unmask = irqc_irq_enable;
215 irq_chip->irq_enable = irqc_irq_enable;
216 irq_chip->irq_disable = irqc_irq_disable;
217 irq_chip->irq_set_type = irqc_irq_set_type;
218 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
219
220 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
221 p->number_of_irqs,
222 p->config.irq_base,
223 &irqc_irq_domain_ops, p);
224 if (!p->irq_domain) {
225 ret = -ENXIO;
226 dev_err(&pdev->dev, "cannot initialize irq domain\n");
227 goto err2;
228 }
229
230 /* request interrupts one by one */
231 for (k = 0; k < p->number_of_irqs; k++) {
232 if (request_irq(p->irq[k].requested_irq, irqc_irq_handler,
233 0, name, &p->irq[k])) {
234 dev_err(&pdev->dev, "failed to request IRQ\n");
235 ret = -ENOENT;
236 goto err3;
237 }
238 }
239
240 dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
241
242 /* warn in case of mismatch if irq base is specified */
243 if (p->config.irq_base) {
244 if (p->config.irq_base != p->irq[0].domain_irq)
245 dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
246 p->config.irq_base, p->irq[0].domain_irq);
247 }
248
249 return 0;
250err3:
251 for (; k >= 0; k--)
252 free_irq(p->irq[k - 1].requested_irq, &p->irq[k - 1]);
253
254 irq_domain_remove(p->irq_domain);
255err2:
256 iounmap(p->iomem);
257err1:
258 kfree(p);
259err0:
260 return ret;
261}
262
263static int irqc_remove(struct platform_device *pdev)
264{
265 struct irqc_priv *p = platform_get_drvdata(pdev);
266 int k;
267
268 for (k = 0; k < p->number_of_irqs; k++)
269 free_irq(p->irq[k].requested_irq, &p->irq[k]);
270
271 irq_domain_remove(p->irq_domain);
272 iounmap(p->iomem);
273 kfree(p);
274 return 0;
275}
276
277static const struct of_device_id irqc_dt_ids[] = {
278 { .compatible = "renesas,irqc", },
279 {},
280};
281MODULE_DEVICE_TABLE(of, irqc_dt_ids);
282
283static struct platform_driver irqc_device_driver = {
284 .probe = irqc_probe,
285 .remove = irqc_remove,
286 .driver = {
287 .name = "renesas_irqc",
288 .of_match_table = irqc_dt_ids,
289 .owner = THIS_MODULE,
290 }
291};
292
293static int __init irqc_init(void)
294{
295 return platform_driver_register(&irqc_device_driver);
296}
297postcore_initcall(irqc_init);
298
299static void __exit irqc_exit(void)
300{
301 platform_driver_unregister(&irqc_device_driver);
302}
303module_exit(irqc_exit);
304
305MODULE_AUTHOR("Magnus Damm");
306MODULE_DESCRIPTION("Renesas IRQC Driver");
307MODULE_LICENSE("GPL v2");
diff --git a/drivers/irqchip/irq-s3c24xx.c b/drivers/irqchip/irq-s3c24xx.c
new file mode 100644
index 000000000000..bbcc944ed94f
--- /dev/null
+++ b/drivers/irqchip/irq-s3c24xx.c
@@ -0,0 +1,1356 @@
1/*
2 * S3C24XX IRQ handling
3 *
4 * Copyright (c) 2003-2004 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17*/
18
19#include <linux/init.h>
20#include <linux/slab.h>
21#include <linux/module.h>
22#include <linux/io.h>
23#include <linux/err.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/device.h>
27#include <linux/irqdomain.h>
28#include <linux/irqchip/chained_irq.h>
29#include <linux/of.h>
30#include <linux/of_irq.h>
31#include <linux/of_address.h>
32
33#include <asm/exception.h>
34#include <asm/mach/irq.h>
35
36#include <mach/regs-irq.h>
37#include <mach/regs-gpio.h>
38
39#include <plat/cpu.h>
40#include <plat/regs-irqtype.h>
41#include <plat/pm.h>
42
43#include "irqchip.h"
44
45#define S3C_IRQTYPE_NONE 0
46#define S3C_IRQTYPE_EINT 1
47#define S3C_IRQTYPE_EDGE 2
48#define S3C_IRQTYPE_LEVEL 3
49
50struct s3c_irq_data {
51 unsigned int type;
52 unsigned long offset;
53 unsigned long parent_irq;
54
55 /* data gets filled during init */
56 struct s3c_irq_intc *intc;
57 unsigned long sub_bits;
58 struct s3c_irq_intc *sub_intc;
59};
60
61/*
62 * Sructure holding the controller data
63 * @reg_pending register holding pending irqs
64 * @reg_intpnd special register intpnd in main intc
65 * @reg_mask mask register
66 * @domain irq_domain of the controller
67 * @parent parent controller for ext and sub irqs
68 * @irqs irq-data, always s3c_irq_data[32]
69 */
70struct s3c_irq_intc {
71 void __iomem *reg_pending;
72 void __iomem *reg_intpnd;
73 void __iomem *reg_mask;
74 struct irq_domain *domain;
75 struct s3c_irq_intc *parent;
76 struct s3c_irq_data *irqs;
77};
78
79/*
80 * Array holding pointers to the global controller structs
81 * [0] ... main_intc
82 * [1] ... sub_intc
83 * [2] ... main_intc2 on s3c2416
84 */
85static struct s3c_irq_intc *s3c_intc[3];
86
87static void s3c_irq_mask(struct irq_data *data)
88{
89 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
90 struct s3c_irq_intc *intc = irq_data->intc;
91 struct s3c_irq_intc *parent_intc = intc->parent;
92 struct s3c_irq_data *parent_data;
93 unsigned long mask;
94 unsigned int irqno;
95
96 mask = __raw_readl(intc->reg_mask);
97 mask |= (1UL << irq_data->offset);
98 __raw_writel(mask, intc->reg_mask);
99
100 if (parent_intc) {
101 parent_data = &parent_intc->irqs[irq_data->parent_irq];
102
103 /* check to see if we need to mask the parent IRQ
104 * The parent_irq is always in main_intc, so the hwirq
105 * for find_mapping does not need an offset in any case.
106 */
107 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
108 irqno = irq_find_mapping(parent_intc->domain,
109 irq_data->parent_irq);
110 s3c_irq_mask(irq_get_irq_data(irqno));
111 }
112 }
113}
114
115static void s3c_irq_unmask(struct irq_data *data)
116{
117 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
118 struct s3c_irq_intc *intc = irq_data->intc;
119 struct s3c_irq_intc *parent_intc = intc->parent;
120 unsigned long mask;
121 unsigned int irqno;
122
123 mask = __raw_readl(intc->reg_mask);
124 mask &= ~(1UL << irq_data->offset);
125 __raw_writel(mask, intc->reg_mask);
126
127 if (parent_intc) {
128 irqno = irq_find_mapping(parent_intc->domain,
129 irq_data->parent_irq);
130 s3c_irq_unmask(irq_get_irq_data(irqno));
131 }
132}
133
134static inline void s3c_irq_ack(struct irq_data *data)
135{
136 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
137 struct s3c_irq_intc *intc = irq_data->intc;
138 unsigned long bitval = 1UL << irq_data->offset;
139
140 __raw_writel(bitval, intc->reg_pending);
141 if (intc->reg_intpnd)
142 __raw_writel(bitval, intc->reg_intpnd);
143}
144
145static int s3c_irq_type(struct irq_data *data, unsigned int type)
146{
147 switch (type) {
148 case IRQ_TYPE_NONE:
149 break;
150 case IRQ_TYPE_EDGE_RISING:
151 case IRQ_TYPE_EDGE_FALLING:
152 case IRQ_TYPE_EDGE_BOTH:
153 irq_set_handler(data->irq, handle_edge_irq);
154 break;
155 case IRQ_TYPE_LEVEL_LOW:
156 case IRQ_TYPE_LEVEL_HIGH:
157 irq_set_handler(data->irq, handle_level_irq);
158 break;
159 default:
160 pr_err("No such irq type %d", type);
161 return -EINVAL;
162 }
163
164 return 0;
165}
166
167static int s3c_irqext_type_set(void __iomem *gpcon_reg,
168 void __iomem *extint_reg,
169 unsigned long gpcon_offset,
170 unsigned long extint_offset,
171 unsigned int type)
172{
173 unsigned long newvalue = 0, value;
174
175 /* Set the GPIO to external interrupt mode */
176 value = __raw_readl(gpcon_reg);
177 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
178 __raw_writel(value, gpcon_reg);
179
180 /* Set the external interrupt to pointed trigger type */
181 switch (type)
182 {
183 case IRQ_TYPE_NONE:
184 pr_warn("No edge setting!\n");
185 break;
186
187 case IRQ_TYPE_EDGE_RISING:
188 newvalue = S3C2410_EXTINT_RISEEDGE;
189 break;
190
191 case IRQ_TYPE_EDGE_FALLING:
192 newvalue = S3C2410_EXTINT_FALLEDGE;
193 break;
194
195 case IRQ_TYPE_EDGE_BOTH:
196 newvalue = S3C2410_EXTINT_BOTHEDGE;
197 break;
198
199 case IRQ_TYPE_LEVEL_LOW:
200 newvalue = S3C2410_EXTINT_LOWLEV;
201 break;
202
203 case IRQ_TYPE_LEVEL_HIGH:
204 newvalue = S3C2410_EXTINT_HILEV;
205 break;
206
207 default:
208 pr_err("No such irq type %d", type);
209 return -EINVAL;
210 }
211
212 value = __raw_readl(extint_reg);
213 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
214 __raw_writel(value, extint_reg);
215
216 return 0;
217}
218
219static int s3c_irqext_type(struct irq_data *data, unsigned int type)
220{
221 void __iomem *extint_reg;
222 void __iomem *gpcon_reg;
223 unsigned long gpcon_offset, extint_offset;
224
225 if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
226 gpcon_reg = S3C2410_GPFCON;
227 extint_reg = S3C24XX_EXTINT0;
228 gpcon_offset = (data->hwirq) * 2;
229 extint_offset = (data->hwirq) * 4;
230 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
231 gpcon_reg = S3C2410_GPGCON;
232 extint_reg = S3C24XX_EXTINT1;
233 gpcon_offset = (data->hwirq - 8) * 2;
234 extint_offset = (data->hwirq - 8) * 4;
235 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
236 gpcon_reg = S3C2410_GPGCON;
237 extint_reg = S3C24XX_EXTINT2;
238 gpcon_offset = (data->hwirq - 8) * 2;
239 extint_offset = (data->hwirq - 16) * 4;
240 } else {
241 return -EINVAL;
242 }
243
244 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
245 extint_offset, type);
246}
247
248static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
249{
250 void __iomem *extint_reg;
251 void __iomem *gpcon_reg;
252 unsigned long gpcon_offset, extint_offset;
253
254 if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
255 gpcon_reg = S3C2410_GPFCON;
256 extint_reg = S3C24XX_EXTINT0;
257 gpcon_offset = (data->hwirq) * 2;
258 extint_offset = (data->hwirq) * 4;
259 } else {
260 return -EINVAL;
261 }
262
263 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
264 extint_offset, type);
265}
266
267static struct irq_chip s3c_irq_chip = {
268 .name = "s3c",
269 .irq_ack = s3c_irq_ack,
270 .irq_mask = s3c_irq_mask,
271 .irq_unmask = s3c_irq_unmask,
272 .irq_set_type = s3c_irq_type,
273 .irq_set_wake = s3c_irq_wake
274};
275
276static struct irq_chip s3c_irq_level_chip = {
277 .name = "s3c-level",
278 .irq_mask = s3c_irq_mask,
279 .irq_unmask = s3c_irq_unmask,
280 .irq_ack = s3c_irq_ack,
281 .irq_set_type = s3c_irq_type,
282};
283
284static struct irq_chip s3c_irqext_chip = {
285 .name = "s3c-ext",
286 .irq_mask = s3c_irq_mask,
287 .irq_unmask = s3c_irq_unmask,
288 .irq_ack = s3c_irq_ack,
289 .irq_set_type = s3c_irqext_type,
290 .irq_set_wake = s3c_irqext_wake
291};
292
293static struct irq_chip s3c_irq_eint0t4 = {
294 .name = "s3c-ext0",
295 .irq_ack = s3c_irq_ack,
296 .irq_mask = s3c_irq_mask,
297 .irq_unmask = s3c_irq_unmask,
298 .irq_set_wake = s3c_irq_wake,
299 .irq_set_type = s3c_irqext0_type,
300};
301
302static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
303{
304 struct irq_chip *chip = irq_desc_get_chip(desc);
305 struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
306 struct s3c_irq_intc *intc = irq_data->intc;
307 struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
308 unsigned long src;
309 unsigned long msk;
310 unsigned int n;
311 unsigned int offset;
312
313 /* we're using individual domains for the non-dt case
314 * and one big domain for the dt case where the subintc
315 * starts at hwirq number 32.
316 */
317 offset = (intc->domain->of_node) ? 32 : 0;
318
319 chained_irq_enter(chip, desc);
320
321 src = __raw_readl(sub_intc->reg_pending);
322 msk = __raw_readl(sub_intc->reg_mask);
323
324 src &= ~msk;
325 src &= irq_data->sub_bits;
326
327 while (src) {
328 n = __ffs(src);
329 src &= ~(1 << n);
330 irq = irq_find_mapping(sub_intc->domain, offset + n);
331 generic_handle_irq(irq);
332 }
333
334 chained_irq_exit(chip, desc);
335}
336
337static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
338 struct pt_regs *regs, int intc_offset)
339{
340 int pnd;
341 int offset;
342 int irq;
343
344 pnd = __raw_readl(intc->reg_intpnd);
345 if (!pnd)
346 return false;
347
348 /* non-dt machines use individual domains */
349 if (!intc->domain->of_node)
350 intc_offset = 0;
351
352 /* We have a problem that the INTOFFSET register does not always
353 * show one interrupt. Occasionally we get two interrupts through
354 * the prioritiser, and this causes the INTOFFSET register to show
355 * what looks like the logical-or of the two interrupt numbers.
356 *
357 * Thanks to Klaus, Shannon, et al for helping to debug this problem
358 */
359 offset = __raw_readl(intc->reg_intpnd + 4);
360
361 /* Find the bit manually, when the offset is wrong.
362 * The pending register only ever contains the one bit of the next
363 * interrupt to handle.
364 */
365 if (!(pnd & (1 << offset)))
366 offset = __ffs(pnd);
367
368 irq = irq_find_mapping(intc->domain, intc_offset + offset);
369 handle_IRQ(irq, regs);
370 return true;
371}
372
373asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
374{
375 do {
376 if (likely(s3c_intc[0]))
377 if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
378 continue;
379
380 if (s3c_intc[2])
381 if (s3c24xx_handle_intc(s3c_intc[2], regs, 64))
382 continue;
383
384 break;
385 } while (1);
386}
387
388#ifdef CONFIG_FIQ
389/**
390 * s3c24xx_set_fiq - set the FIQ routing
391 * @irq: IRQ number to route to FIQ on processor.
392 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
393 *
394 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
395 * @on is true, the @irq is checked to see if it can be routed and the
396 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
397 * routing is cleared, regardless of which @irq is specified.
398 */
399int s3c24xx_set_fiq(unsigned int irq, bool on)
400{
401 u32 intmod;
402 unsigned offs;
403
404 if (on) {
405 offs = irq - FIQ_START;
406 if (offs > 31)
407 return -EINVAL;
408
409 intmod = 1 << offs;
410 } else {
411 intmod = 0;
412 }
413
414 __raw_writel(intmod, S3C2410_INTMOD);
415 return 0;
416}
417
418EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
419#endif
420
421static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
422 irq_hw_number_t hw)
423{
424 struct s3c_irq_intc *intc = h->host_data;
425 struct s3c_irq_data *irq_data = &intc->irqs[hw];
426 struct s3c_irq_intc *parent_intc;
427 struct s3c_irq_data *parent_irq_data;
428 unsigned int irqno;
429
430 /* attach controller pointer to irq_data */
431 irq_data->intc = intc;
432 irq_data->offset = hw;
433
434 parent_intc = intc->parent;
435
436 /* set handler and flags */
437 switch (irq_data->type) {
438 case S3C_IRQTYPE_NONE:
439 return 0;
440 case S3C_IRQTYPE_EINT:
441 /* On the S3C2412, the EINT0to3 have a parent irq
442 * but need the s3c_irq_eint0t4 chip
443 */
444 if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
445 irq_set_chip_and_handler(virq, &s3c_irqext_chip,
446 handle_edge_irq);
447 else
448 irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
449 handle_edge_irq);
450 break;
451 case S3C_IRQTYPE_EDGE:
452 if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
453 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
454 handle_edge_irq);
455 else
456 irq_set_chip_and_handler(virq, &s3c_irq_chip,
457 handle_edge_irq);
458 break;
459 case S3C_IRQTYPE_LEVEL:
460 if (parent_intc)
461 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
462 handle_level_irq);
463 else
464 irq_set_chip_and_handler(virq, &s3c_irq_chip,
465 handle_level_irq);
466 break;
467 default:
468 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
469 return -EINVAL;
470 }
471
472 irq_set_chip_data(virq, irq_data);
473
474 set_irq_flags(virq, IRQF_VALID);
475
476 if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
477 if (irq_data->parent_irq > 31) {
478 pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
479 irq_data->parent_irq);
480 goto err;
481 }
482
483 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
484 parent_irq_data->sub_intc = intc;
485 parent_irq_data->sub_bits |= (1UL << hw);
486
487 /* attach the demuxer to the parent irq */
488 irqno = irq_find_mapping(parent_intc->domain,
489 irq_data->parent_irq);
490 if (!irqno) {
491 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
492 irq_data->parent_irq);
493 goto err;
494 }
495 irq_set_chained_handler(irqno, s3c_irq_demux);
496 }
497
498 return 0;
499
500err:
501 set_irq_flags(virq, 0);
502
503 /* the only error can result from bad mapping data*/
504 return -EINVAL;
505}
506
507static struct irq_domain_ops s3c24xx_irq_ops = {
508 .map = s3c24xx_irq_map,
509 .xlate = irq_domain_xlate_twocell,
510};
511
512static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
513{
514 void __iomem *reg_source;
515 unsigned long pend;
516 unsigned long last;
517 int i;
518
519 /* if intpnd is set, read the next pending irq from there */
520 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
521
522 last = 0;
523 for (i = 0; i < 4; i++) {
524 pend = __raw_readl(reg_source);
525
526 if (pend == 0 || pend == last)
527 break;
528
529 __raw_writel(pend, intc->reg_pending);
530 if (intc->reg_intpnd)
531 __raw_writel(pend, intc->reg_intpnd);
532
533 pr_info("irq: clearing pending status %08x\n", (int)pend);
534 last = pend;
535 }
536}
537
538static struct s3c_irq_intc * __init s3c24xx_init_intc(struct device_node *np,
539 struct s3c_irq_data *irq_data,
540 struct s3c_irq_intc *parent,
541 unsigned long address)
542{
543 struct s3c_irq_intc *intc;
544 void __iomem *base = (void *)0xf6000000; /* static mapping */
545 int irq_num;
546 int irq_start;
547 int ret;
548
549 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
550 if (!intc)
551 return ERR_PTR(-ENOMEM);
552
553 intc->irqs = irq_data;
554
555 if (parent)
556 intc->parent = parent;
557
558 /* select the correct data for the controller.
559 * Need to hard code the irq num start and offset
560 * to preserve the static mapping for now
561 */
562 switch (address) {
563 case 0x4a000000:
564 pr_debug("irq: found main intc\n");
565 intc->reg_pending = base;
566 intc->reg_mask = base + 0x08;
567 intc->reg_intpnd = base + 0x10;
568 irq_num = 32;
569 irq_start = S3C2410_IRQ(0);
570 break;
571 case 0x4a000018:
572 pr_debug("irq: found subintc\n");
573 intc->reg_pending = base + 0x18;
574 intc->reg_mask = base + 0x1c;
575 irq_num = 29;
576 irq_start = S3C2410_IRQSUB(0);
577 break;
578 case 0x4a000040:
579 pr_debug("irq: found intc2\n");
580 intc->reg_pending = base + 0x40;
581 intc->reg_mask = base + 0x48;
582 intc->reg_intpnd = base + 0x50;
583 irq_num = 8;
584 irq_start = S3C2416_IRQ(0);
585 break;
586 case 0x560000a4:
587 pr_debug("irq: found eintc\n");
588 base = (void *)0xfd000000;
589
590 intc->reg_mask = base + 0xa4;
591 intc->reg_pending = base + 0xa8;
592 irq_num = 24;
593 irq_start = S3C2410_IRQ(32);
594 break;
595 default:
596 pr_err("irq: unsupported controller address\n");
597 ret = -EINVAL;
598 goto err;
599 }
600
601 /* now that all the data is complete, init the irq-domain */
602 s3c24xx_clear_intc(intc);
603 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
604 0, &s3c24xx_irq_ops,
605 intc);
606 if (!intc->domain) {
607 pr_err("irq: could not create irq-domain\n");
608 ret = -EINVAL;
609 goto err;
610 }
611
612 set_handle_irq(s3c24xx_handle_irq);
613
614 return intc;
615
616err:
617 kfree(intc);
618 return ERR_PTR(ret);
619}
620
621static struct s3c_irq_data init_eint[32] = {
622 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
623 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
624 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
625 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
626 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
627 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
628 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
629 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
630 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
631 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
632 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
633 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
634 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
635 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
636 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
637 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
638 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
639 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
640 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
641 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
642 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
643 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
644 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
645 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
646};
647
648#ifdef CONFIG_CPU_S3C2410
649static struct s3c_irq_data init_s3c2410base[32] = {
650 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
651 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
652 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
653 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
654 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
655 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
656 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
657 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
658 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
659 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
660 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
661 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
662 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
663 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
664 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
665 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
666 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
667 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
668 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
669 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
670 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
671 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
672 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
673 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
674 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
675 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
676 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
677 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
678 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
679 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
680 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
681 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
682};
683
684static struct s3c_irq_data init_s3c2410subint[32] = {
685 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
686 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
687 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
688 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
689 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
690 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
691 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
692 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
693 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
694 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
695 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
696};
697
698void __init s3c2410_init_irq(void)
699{
700#ifdef CONFIG_FIQ
701 init_FIQ(FIQ_START);
702#endif
703
704 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL,
705 0x4a000000);
706 if (IS_ERR(s3c_intc[0])) {
707 pr_err("irq: could not create main interrupt controller\n");
708 return;
709 }
710
711 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0],
712 s3c_intc[0], 0x4a000018);
713 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
714}
715#endif
716
717#ifdef CONFIG_CPU_S3C2412
718static struct s3c_irq_data init_s3c2412base[32] = {
719 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
720 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
721 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
722 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
723 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
724 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
725 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
726 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
727 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
728 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
729 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
730 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
731 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
732 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
733 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
734 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
735 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
736 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
737 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
738 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
739 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
740 { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
741 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
742 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
743 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
744 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
745 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
746 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
747 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
748 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
749 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
750 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
751};
752
753static struct s3c_irq_data init_s3c2412eint[32] = {
754 { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
755 { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
756 { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
757 { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
758 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
759 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
760 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
761 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
762 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
763 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
764 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
765 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
766 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
767 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
768 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
769 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
770 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
771 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
772 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
773 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
774 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
775 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
776 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
777 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
778};
779
780static struct s3c_irq_data init_s3c2412subint[32] = {
781 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
782 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
783 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
784 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
785 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
786 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
787 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
788 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
789 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
790 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
791 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
792 { .type = S3C_IRQTYPE_NONE, },
793 { .type = S3C_IRQTYPE_NONE, },
794 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
795 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
796};
797
798void __init s3c2412_init_irq(void)
799{
800 pr_info("S3C2412: IRQ Support\n");
801
802#ifdef CONFIG_FIQ
803 init_FIQ(FIQ_START);
804#endif
805
806 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL,
807 0x4a000000);
808 if (IS_ERR(s3c_intc[0])) {
809 pr_err("irq: could not create main interrupt controller\n");
810 return;
811 }
812
813 s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4);
814 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0],
815 s3c_intc[0], 0x4a000018);
816}
817#endif
818
819#ifdef CONFIG_CPU_S3C2416
820static struct s3c_irq_data init_s3c2416base[32] = {
821 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
822 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
823 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
824 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
825 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
826 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
827 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
828 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
829 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
830 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
831 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
832 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
833 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
834 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
835 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
836 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
837 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
838 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
839 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
840 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
841 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
842 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
843 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
844 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
845 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
846 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
847 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
848 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
849 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
850 { .type = S3C_IRQTYPE_NONE, },
851 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
852 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
853};
854
855static struct s3c_irq_data init_s3c2416subint[32] = {
856 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
857 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
858 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
859 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
860 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
861 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
862 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
863 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
864 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
865 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
866 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
867 { .type = S3C_IRQTYPE_NONE }, /* reserved */
868 { .type = S3C_IRQTYPE_NONE }, /* reserved */
869 { .type = S3C_IRQTYPE_NONE }, /* reserved */
870 { .type = S3C_IRQTYPE_NONE }, /* reserved */
871 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
872 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
873 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
874 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
875 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
876 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
877 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
878 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
879 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
880 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
881 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
882 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
883 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
884 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
885};
886
887static struct s3c_irq_data init_s3c2416_second[32] = {
888 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
889 { .type = S3C_IRQTYPE_NONE }, /* reserved */
890 { .type = S3C_IRQTYPE_NONE }, /* reserved */
891 { .type = S3C_IRQTYPE_NONE }, /* reserved */
892 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
893 { .type = S3C_IRQTYPE_NONE }, /* reserved */
894 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
895};
896
897void __init s3c2416_init_irq(void)
898{
899 pr_info("S3C2416: IRQ Support\n");
900
901#ifdef CONFIG_FIQ
902 init_FIQ(FIQ_START);
903#endif
904
905 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL,
906 0x4a000000);
907 if (IS_ERR(s3c_intc[0])) {
908 pr_err("irq: could not create main interrupt controller\n");
909 return;
910 }
911
912 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
913 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0],
914 s3c_intc[0], 0x4a000018);
915
916 s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0],
917 NULL, 0x4a000040);
918}
919
920#endif
921
922#ifdef CONFIG_CPU_S3C2440
923static struct s3c_irq_data init_s3c2440base[32] = {
924 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
925 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
926 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
927 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
928 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
929 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
930 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
931 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
932 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
933 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
934 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
935 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
936 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
937 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
938 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
939 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
940 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
941 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
942 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
943 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
944 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
945 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
946 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
947 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
948 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
949 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
950 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
951 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
952 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
953 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
954 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
955 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
956};
957
958static struct s3c_irq_data init_s3c2440subint[32] = {
959 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
960 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
961 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
962 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
963 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
964 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
965 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
966 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
967 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
968 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
969 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
970 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
971 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
972 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
973 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
974};
975
976void __init s3c2440_init_irq(void)
977{
978 pr_info("S3C2440: IRQ Support\n");
979
980#ifdef CONFIG_FIQ
981 init_FIQ(FIQ_START);
982#endif
983
984 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL,
985 0x4a000000);
986 if (IS_ERR(s3c_intc[0])) {
987 pr_err("irq: could not create main interrupt controller\n");
988 return;
989 }
990
991 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
992 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0],
993 s3c_intc[0], 0x4a000018);
994}
995#endif
996
997#ifdef CONFIG_CPU_S3C2442
998static struct s3c_irq_data init_s3c2442base[32] = {
999 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
1000 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
1001 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
1002 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
1003 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
1004 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1005 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
1006 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
1007 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1008 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
1009 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1010 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1011 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1012 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1013 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1014 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1015 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
1016 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
1017 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
1018 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
1019 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
1020 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
1021 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1022 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1023 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
1024 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1025 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1026 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1027 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1028 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1029 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1030 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1031};
1032
1033static struct s3c_irq_data init_s3c2442subint[32] = {
1034 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1035 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1036 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1037 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1038 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1039 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1040 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1041 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1042 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1043 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1044 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1045 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1046 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1047};
1048
1049void __init s3c2442_init_irq(void)
1050{
1051 pr_info("S3C2442: IRQ Support\n");
1052
1053#ifdef CONFIG_FIQ
1054 init_FIQ(FIQ_START);
1055#endif
1056
1057 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL,
1058 0x4a000000);
1059 if (IS_ERR(s3c_intc[0])) {
1060 pr_err("irq: could not create main interrupt controller\n");
1061 return;
1062 }
1063
1064 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1065 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0],
1066 s3c_intc[0], 0x4a000018);
1067}
1068#endif
1069
1070#ifdef CONFIG_CPU_S3C2443
1071static struct s3c_irq_data init_s3c2443base[32] = {
1072 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
1073 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
1074 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
1075 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
1076 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
1077 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1078 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
1079 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
1080 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1081 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
1082 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1083 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1084 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1085 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1086 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1087 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1088 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
1089 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
1090 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
1091 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
1092 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
1093 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
1094 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1095 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1096 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
1097 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1098 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1099 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1100 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1101 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1102 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1103 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1104};
1105
1106
1107static struct s3c_irq_data init_s3c2443subint[32] = {
1108 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1109 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1110 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1111 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1112 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1113 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1114 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1115 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1116 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1117 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1118 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1119 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1120 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1121 { .type = S3C_IRQTYPE_NONE }, /* reserved */
1122 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
1123 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
1124 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
1125 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
1126 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
1127 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
1128 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
1129 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
1130 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
1131 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
1132 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1133 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1134 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1135 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
1136 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
1137};
1138
1139void __init s3c2443_init_irq(void)
1140{
1141 pr_info("S3C2443: IRQ Support\n");
1142
1143#ifdef CONFIG_FIQ
1144 init_FIQ(FIQ_START);
1145#endif
1146
1147 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL,
1148 0x4a000000);
1149 if (IS_ERR(s3c_intc[0])) {
1150 pr_err("irq: could not create main interrupt controller\n");
1151 return;
1152 }
1153
1154 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1155 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0],
1156 s3c_intc[0], 0x4a000018);
1157}
1158#endif
1159
1160#ifdef CONFIG_OF
1161static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq,
1162 irq_hw_number_t hw)
1163{
1164 unsigned int ctrl_num = hw / 32;
1165 unsigned int intc_hw = hw % 32;
1166 struct s3c_irq_intc *intc = s3c_intc[ctrl_num];
1167 struct s3c_irq_intc *parent_intc = intc->parent;
1168 struct s3c_irq_data *irq_data = &intc->irqs[intc_hw];
1169
1170 /* attach controller pointer to irq_data */
1171 irq_data->intc = intc;
1172 irq_data->offset = intc_hw;
1173
1174 if (!parent_intc)
1175 irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq);
1176 else
1177 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
1178 handle_edge_irq);
1179
1180 irq_set_chip_data(virq, irq_data);
1181
1182 set_irq_flags(virq, IRQF_VALID);
1183
1184 return 0;
1185}
1186
1187/* Translate our of irq notation
1188 * format: <ctrl_num ctrl_irq parent_irq type>
1189 */
1190static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n,
1191 const u32 *intspec, unsigned int intsize,
1192 irq_hw_number_t *out_hwirq, unsigned int *out_type)
1193{
1194 struct s3c_irq_intc *intc;
1195 struct s3c_irq_intc *parent_intc;
1196 struct s3c_irq_data *irq_data;
1197 struct s3c_irq_data *parent_irq_data;
1198 int irqno;
1199
1200 if (WARN_ON(intsize < 4))
1201 return -EINVAL;
1202
1203 if (intspec[0] > 2 || !s3c_intc[intspec[0]]) {
1204 pr_err("controller number %d invalid\n", intspec[0]);
1205 return -EINVAL;
1206 }
1207 intc = s3c_intc[intspec[0]];
1208
1209 *out_hwirq = intspec[0] * 32 + intspec[2];
1210 *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
1211
1212 parent_intc = intc->parent;
1213 if (parent_intc) {
1214 irq_data = &intc->irqs[intspec[2]];
1215 irq_data->parent_irq = intspec[1];
1216 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
1217 parent_irq_data->sub_intc = intc;
1218 parent_irq_data->sub_bits |= (1UL << intspec[2]);
1219
1220 /* parent_intc is always s3c_intc[0], so no offset */
1221 irqno = irq_create_mapping(parent_intc->domain, intspec[1]);
1222 if (irqno < 0) {
1223 pr_err("irq: could not map parent interrupt\n");
1224 return irqno;
1225 }
1226
1227 irq_set_chained_handler(irqno, s3c_irq_demux);
1228 }
1229
1230 return 0;
1231}
1232
1233static struct irq_domain_ops s3c24xx_irq_ops_of = {
1234 .map = s3c24xx_irq_map_of,
1235 .xlate = s3c24xx_irq_xlate_of,
1236};
1237
1238struct s3c24xx_irq_of_ctrl {
1239 char *name;
1240 unsigned long offset;
1241 struct s3c_irq_intc **handle;
1242 struct s3c_irq_intc **parent;
1243 struct irq_domain_ops *ops;
1244};
1245
1246static int __init s3c_init_intc_of(struct device_node *np,
1247 struct device_node *interrupt_parent,
1248 struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl)
1249{
1250 struct s3c_irq_intc *intc;
1251 struct s3c24xx_irq_of_ctrl *ctrl;
1252 struct irq_domain *domain;
1253 void __iomem *reg_base;
1254 int i;
1255
1256 reg_base = of_iomap(np, 0);
1257 if (!reg_base) {
1258 pr_err("irq-s3c24xx: could not map irq registers\n");
1259 return -EINVAL;
1260 }
1261
1262 domain = irq_domain_add_linear(np, num_ctrl * 32,
1263 &s3c24xx_irq_ops_of, NULL);
1264 if (!domain) {
1265 pr_err("irq: could not create irq-domain\n");
1266 return -EINVAL;
1267 }
1268
1269 for (i = 0; i < num_ctrl; i++) {
1270 ctrl = &s3c_ctrl[i];
1271
1272 pr_debug("irq: found controller %s\n", ctrl->name);
1273
1274 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
1275 if (!intc)
1276 return -ENOMEM;
1277
1278 intc->domain = domain;
1279 intc->irqs = kzalloc(sizeof(struct s3c_irq_data) * 32,
1280 GFP_KERNEL);
1281 if (!intc->irqs) {
1282 kfree(intc);
1283 return -ENOMEM;
1284 }
1285
1286 if (ctrl->parent) {
1287 intc->reg_pending = reg_base + ctrl->offset;
1288 intc->reg_mask = reg_base + ctrl->offset + 0x4;
1289
1290 if (*(ctrl->parent)) {
1291 intc->parent = *(ctrl->parent);
1292 } else {
1293 pr_warn("irq: parent of %s missing\n",
1294 ctrl->name);
1295 kfree(intc->irqs);
1296 kfree(intc);
1297 continue;
1298 }
1299 } else {
1300 intc->reg_pending = reg_base + ctrl->offset;
1301 intc->reg_mask = reg_base + ctrl->offset + 0x08;
1302 intc->reg_intpnd = reg_base + ctrl->offset + 0x10;
1303 }
1304
1305 s3c24xx_clear_intc(intc);
1306 s3c_intc[i] = intc;
1307 }
1308
1309 set_handle_irq(s3c24xx_handle_irq);
1310
1311 return 0;
1312}
1313
1314static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = {
1315 {
1316 .name = "intc",
1317 .offset = 0,
1318 }, {
1319 .name = "subintc",
1320 .offset = 0x18,
1321 .parent = &s3c_intc[0],
1322 }
1323};
1324
1325int __init s3c2410_init_intc_of(struct device_node *np,
1326 struct device_node *interrupt_parent,
1327 struct s3c24xx_irq_of_ctrl *ctrl, int num_ctrl)
1328{
1329 return s3c_init_intc_of(np, interrupt_parent,
1330 s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl));
1331}
1332IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of);
1333
1334static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = {
1335 {
1336 .name = "intc",
1337 .offset = 0,
1338 }, {
1339 .name = "subintc",
1340 .offset = 0x18,
1341 .parent = &s3c_intc[0],
1342 }, {
1343 .name = "intc2",
1344 .offset = 0x40,
1345 }
1346};
1347
1348int __init s3c2416_init_intc_of(struct device_node *np,
1349 struct device_node *interrupt_parent,
1350 struct s3c24xx_irq_of_ctrl *ctrl, int num_ctrl)
1351{
1352 return s3c_init_intc_of(np, interrupt_parent,
1353 s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl));
1354}
1355IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of);
1356#endif
diff --git a/drivers/irqchip/irq-vt8500.c b/drivers/irqchip/irq-vt8500.c
new file mode 100644
index 000000000000..d97059550a2c
--- /dev/null
+++ b/drivers/irqchip/irq-vt8500.c
@@ -0,0 +1,259 @@
1/*
2 * arch/arm/mach-vt8500/irq.c
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
23 * This file is copied and modified from the original irq.c provided by
24 * Alexey Charkov. Minor changes have been made for Device Tree Support.
25 */
26
27#include <linux/slab.h>
28#include <linux/io.h>
29#include <linux/irq.h>
30#include <linux/irqdomain.h>
31#include <linux/interrupt.h>
32#include <linux/bitops.h>
33
34#include <linux/of.h>
35#include <linux/of_irq.h>
36#include <linux/of_address.h>
37
38#include <asm/irq.h>
39#include <asm/exception.h>
40#include <asm/mach/irq.h>
41
42#include "irqchip.h"
43
44#define VT8500_ICPC_IRQ 0x20
45#define VT8500_ICPC_FIQ 0x24
46#define VT8500_ICDC 0x40 /* Destination Control 64*u32 */
47#define VT8500_ICIS 0x80 /* Interrupt status, 16*u32 */
48
49/* ICPC */
50#define ICPC_MASK 0x3F
51#define ICPC_ROTATE BIT(6)
52
53/* IC_DCTR */
54#define ICDC_IRQ 0x00
55#define ICDC_FIQ 0x01
56#define ICDC_DSS0 0x02
57#define ICDC_DSS1 0x03
58#define ICDC_DSS2 0x04
59#define ICDC_DSS3 0x05
60#define ICDC_DSS4 0x06
61#define ICDC_DSS5 0x07
62
63#define VT8500_INT_DISABLE 0
64#define VT8500_INT_ENABLE BIT(3)
65
66#define VT8500_TRIGGER_HIGH 0
67#define VT8500_TRIGGER_RISING BIT(5)
68#define VT8500_TRIGGER_FALLING BIT(6)
69#define VT8500_EDGE ( VT8500_TRIGGER_RISING \
70 | VT8500_TRIGGER_FALLING)
71
72/* vt8500 has 1 intc, wm8505 and wm8650 have 2 */
73#define VT8500_INTC_MAX 2
74
75struct vt8500_irq_data {
76 void __iomem *base; /* IO Memory base address */
77 struct irq_domain *domain; /* Domain for this controller */
78};
79
80/* Global variable for accessing io-mem addresses */
81static struct vt8500_irq_data intc[VT8500_INTC_MAX];
82static u32 active_cnt = 0;
83
84static void vt8500_irq_mask(struct irq_data *d)
85{
86 struct vt8500_irq_data *priv = d->domain->host_data;
87 void __iomem *base = priv->base;
88 void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4);
89 u8 edge, dctr;
90 u32 status;
91
92 edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
93 if (edge) {
94 status = readl(stat_reg);
95
96 status |= (1 << (d->hwirq & 0x1f));
97 writel(status, stat_reg);
98 } else {
99 dctr = readb(base + VT8500_ICDC + d->hwirq);
100 dctr &= ~VT8500_INT_ENABLE;
101 writeb(dctr, base + VT8500_ICDC + d->hwirq);
102 }
103}
104
105static void vt8500_irq_unmask(struct irq_data *d)
106{
107 struct vt8500_irq_data *priv = d->domain->host_data;
108 void __iomem *base = priv->base;
109 u8 dctr;
110
111 dctr = readb(base + VT8500_ICDC + d->hwirq);
112 dctr |= VT8500_INT_ENABLE;
113 writeb(dctr, base + VT8500_ICDC + d->hwirq);
114}
115
116static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
117{
118 struct vt8500_irq_data *priv = d->domain->host_data;
119 void __iomem *base = priv->base;
120 u8 dctr;
121
122 dctr = readb(base + VT8500_ICDC + d->hwirq);
123 dctr &= ~VT8500_EDGE;
124
125 switch (flow_type) {
126 case IRQF_TRIGGER_LOW:
127 return -EINVAL;
128 case IRQF_TRIGGER_HIGH:
129 dctr |= VT8500_TRIGGER_HIGH;
130 __irq_set_handler_locked(d->irq, handle_level_irq);
131 break;
132 case IRQF_TRIGGER_FALLING:
133 dctr |= VT8500_TRIGGER_FALLING;
134 __irq_set_handler_locked(d->irq, handle_edge_irq);
135 break;
136 case IRQF_TRIGGER_RISING:
137 dctr |= VT8500_TRIGGER_RISING;
138 __irq_set_handler_locked(d->irq, handle_edge_irq);
139 break;
140 }
141 writeb(dctr, base + VT8500_ICDC + d->hwirq);
142
143 return 0;
144}
145
146static struct irq_chip vt8500_irq_chip = {
147 .name = "vt8500",
148 .irq_ack = vt8500_irq_mask,
149 .irq_mask = vt8500_irq_mask,
150 .irq_unmask = vt8500_irq_unmask,
151 .irq_set_type = vt8500_irq_set_type,
152};
153
154static void __init vt8500_init_irq_hw(void __iomem *base)
155{
156 u32 i;
157
158 /* Enable rotating priority for IRQ */
159 writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
160 writel(0x00, base + VT8500_ICPC_FIQ);
161
162 /* Disable all interrupts and route them to IRQ */
163 for (i = 0; i < 64; i++)
164 writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i);
165}
166
167static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
168 irq_hw_number_t hw)
169{
170 irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
171 set_irq_flags(virq, IRQF_VALID);
172
173 return 0;
174}
175
176static struct irq_domain_ops vt8500_irq_domain_ops = {
177 .map = vt8500_irq_map,
178 .xlate = irq_domain_xlate_onecell,
179};
180
181asmlinkage void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs)
182{
183 u32 stat, i;
184 int irqnr, virq;
185 void __iomem *base;
186
187 /* Loop through each active controller */
188 for (i=0; i<active_cnt; i++) {
189 base = intc[i].base;
190 irqnr = readl_relaxed(base) & 0x3F;
191 /*
192 Highest Priority register default = 63, so check that this
193 is a real interrupt by checking the status register
194 */
195 if (irqnr == 63) {
196 stat = readl_relaxed(base + VT8500_ICIS + 4);
197 if (!(stat & BIT(31)))
198 continue;
199 }
200
201 virq = irq_find_mapping(intc[i].domain, irqnr);
202 handle_IRQ(virq, regs);
203 }
204}
205
206int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
207{
208 int irq, i;
209 struct device_node *np = node;
210
211 if (active_cnt == VT8500_INTC_MAX) {
212 pr_err("%s: Interrupt controllers > VT8500_INTC_MAX\n",
213 __func__);
214 goto out;
215 }
216
217 intc[active_cnt].base = of_iomap(np, 0);
218 intc[active_cnt].domain = irq_domain_add_linear(node, 64,
219 &vt8500_irq_domain_ops, &intc[active_cnt]);
220
221 if (!intc[active_cnt].base) {
222 pr_err("%s: Unable to map IO memory\n", __func__);
223 goto out;
224 }
225
226 if (!intc[active_cnt].domain) {
227 pr_err("%s: Unable to add irq domain!\n", __func__);
228 goto out;
229 }
230
231 set_handle_irq(vt8500_handle_irq);
232
233 vt8500_init_irq_hw(intc[active_cnt].base);
234
235 pr_info("vt8500-irq: Added interrupt controller\n");
236
237 active_cnt++;
238
239 /* check if this is a slaved controller */
240 if (of_irq_count(np) != 0) {
241 /* check that we have the correct number of interrupts */
242 if (of_irq_count(np) != 8) {
243 pr_err("%s: Incorrect IRQ map for slaved controller\n",
244 __func__);
245 return -EINVAL;
246 }
247
248 for (i = 0; i < 8; i++) {
249 irq = irq_of_parse_and_map(np, i);
250 enable_irq(irq);
251 }
252
253 pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
254 }
255out:
256 return 0;
257}
258
259IRQCHIP_DECLARE(vt8500_irq, "via,vt8500-intc", vt8500_irq_init);
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 0a2bdd106b23..c76d16c972cc 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -747,6 +747,64 @@ struct device_node *of_find_node_by_phandle(phandle handle)
747EXPORT_SYMBOL(of_find_node_by_phandle); 747EXPORT_SYMBOL(of_find_node_by_phandle);
748 748
749/** 749/**
750 * of_find_property_value_of_size
751 *
752 * @np: device node from which the property value is to be read.
753 * @propname: name of the property to be searched.
754 * @len: requested length of property value
755 *
756 * Search for a property in a device node and valid the requested size.
757 * Returns the property value on success, -EINVAL if the property does not
758 * exist, -ENODATA if property does not have a value, and -EOVERFLOW if the
759 * property data isn't large enough.
760 *
761 */
762static void *of_find_property_value_of_size(const struct device_node *np,
763 const char *propname, u32 len)
764{
765 struct property *prop = of_find_property(np, propname, NULL);
766
767 if (!prop)
768 return ERR_PTR(-EINVAL);
769 if (!prop->value)
770 return ERR_PTR(-ENODATA);
771 if (len > prop->length)
772 return ERR_PTR(-EOVERFLOW);
773
774 return prop->value;
775}
776
777/**
778 * of_property_read_u32_index - Find and read a u32 from a multi-value property.
779 *
780 * @np: device node from which the property value is to be read.
781 * @propname: name of the property to be searched.
782 * @index: index of the u32 in the list of values
783 * @out_value: pointer to return value, modified only if no error.
784 *
785 * Search for a property in a device node and read nth 32-bit value from
786 * it. Returns 0 on success, -EINVAL if the property does not exist,
787 * -ENODATA if property does not have a value, and -EOVERFLOW if the
788 * property data isn't large enough.
789 *
790 * The out_value is modified only if a valid u32 value can be decoded.
791 */
792int of_property_read_u32_index(const struct device_node *np,
793 const char *propname,
794 u32 index, u32 *out_value)
795{
796 const u32 *val = of_find_property_value_of_size(np, propname,
797 ((index + 1) * sizeof(*out_value)));
798
799 if (IS_ERR(val))
800 return PTR_ERR(val);
801
802 *out_value = be32_to_cpup(((__be32 *)val) + index);
803 return 0;
804}
805EXPORT_SYMBOL_GPL(of_property_read_u32_index);
806
807/**
750 * of_property_read_u8_array - Find and read an array of u8 from a property. 808 * of_property_read_u8_array - Find and read an array of u8 from a property.
751 * 809 *
752 * @np: device node from which the property value is to be read. 810 * @np: device node from which the property value is to be read.
@@ -767,17 +825,12 @@ EXPORT_SYMBOL(of_find_node_by_phandle);
767int of_property_read_u8_array(const struct device_node *np, 825int of_property_read_u8_array(const struct device_node *np,
768 const char *propname, u8 *out_values, size_t sz) 826 const char *propname, u8 *out_values, size_t sz)
769{ 827{
770 struct property *prop = of_find_property(np, propname, NULL); 828 const u8 *val = of_find_property_value_of_size(np, propname,
771 const u8 *val; 829 (sz * sizeof(*out_values)));
772 830
773 if (!prop) 831 if (IS_ERR(val))
774 return -EINVAL; 832 return PTR_ERR(val);
775 if (!prop->value)
776 return -ENODATA;
777 if ((sz * sizeof(*out_values)) > prop->length)
778 return -EOVERFLOW;
779 833
780 val = prop->value;
781 while (sz--) 834 while (sz--)
782 *out_values++ = *val++; 835 *out_values++ = *val++;
783 return 0; 836 return 0;
@@ -805,17 +858,12 @@ EXPORT_SYMBOL_GPL(of_property_read_u8_array);
805int of_property_read_u16_array(const struct device_node *np, 858int of_property_read_u16_array(const struct device_node *np,
806 const char *propname, u16 *out_values, size_t sz) 859 const char *propname, u16 *out_values, size_t sz)
807{ 860{
808 struct property *prop = of_find_property(np, propname, NULL); 861 const __be16 *val = of_find_property_value_of_size(np, propname,
809 const __be16 *val; 862 (sz * sizeof(*out_values)));
810 863
811 if (!prop) 864 if (IS_ERR(val))
812 return -EINVAL; 865 return PTR_ERR(val);
813 if (!prop->value)
814 return -ENODATA;
815 if ((sz * sizeof(*out_values)) > prop->length)
816 return -EOVERFLOW;
817 866
818 val = prop->value;
819 while (sz--) 867 while (sz--)
820 *out_values++ = be16_to_cpup(val++); 868 *out_values++ = be16_to_cpup(val++);
821 return 0; 869 return 0;
@@ -842,17 +890,12 @@ int of_property_read_u32_array(const struct device_node *np,
842 const char *propname, u32 *out_values, 890 const char *propname, u32 *out_values,
843 size_t sz) 891 size_t sz)
844{ 892{
845 struct property *prop = of_find_property(np, propname, NULL); 893 const __be32 *val = of_find_property_value_of_size(np, propname,
846 const __be32 *val; 894 (sz * sizeof(*out_values)));
847 895
848 if (!prop) 896 if (IS_ERR(val))
849 return -EINVAL; 897 return PTR_ERR(val);
850 if (!prop->value)
851 return -ENODATA;
852 if ((sz * sizeof(*out_values)) > prop->length)
853 return -EOVERFLOW;
854 898
855 val = prop->value;
856 while (sz--) 899 while (sz--)
857 *out_values++ = be32_to_cpup(val++); 900 *out_values++ = be32_to_cpup(val++);
858 return 0; 901 return 0;
@@ -875,15 +918,13 @@ EXPORT_SYMBOL_GPL(of_property_read_u32_array);
875int of_property_read_u64(const struct device_node *np, const char *propname, 918int of_property_read_u64(const struct device_node *np, const char *propname,
876 u64 *out_value) 919 u64 *out_value)
877{ 920{
878 struct property *prop = of_find_property(np, propname, NULL); 921 const __be32 *val = of_find_property_value_of_size(np, propname,
922 sizeof(*out_value));
879 923
880 if (!prop) 924 if (IS_ERR(val))
881 return -EINVAL; 925 return PTR_ERR(val);
882 if (!prop->value) 926
883 return -ENODATA; 927 *out_value = of_read_number(val, 2);
884 if (sizeof(*out_value) > prop->length)
885 return -EOVERFLOW;
886 *out_value = of_read_number(prop->value, 2);
887 return 0; 928 return 0;
888} 929}
889EXPORT_SYMBOL_GPL(of_property_read_u64); 930EXPORT_SYMBOL_GPL(of_property_read_u64);
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 51336b2aedc9..8f6692438149 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -224,6 +224,7 @@ config PINCTRL_S3C64XX
224source "drivers/pinctrl/mvebu/Kconfig" 224source "drivers/pinctrl/mvebu/Kconfig"
225source "drivers/pinctrl/sh-pfc/Kconfig" 225source "drivers/pinctrl/sh-pfc/Kconfig"
226source "drivers/pinctrl/spear/Kconfig" 226source "drivers/pinctrl/spear/Kconfig"
227source "drivers/pinctrl/vt8500/Kconfig"
227 228
228config PINCTRL_XWAY 229config PINCTRL_XWAY
229 bool 230 bool
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index b9aaa61facd1..9bdaeb8785ce 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -50,3 +50,4 @@ obj-$(CONFIG_PLAT_ORION) += mvebu/
50obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/ 50obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
51obj-$(CONFIG_SUPERH) += sh-pfc/ 51obj-$(CONFIG_SUPERH) += sh-pfc/
52obj-$(CONFIG_PLAT_SPEAR) += spear/ 52obj-$(CONFIG_PLAT_SPEAR) += spear/
53obj-$(CONFIG_ARCH_VT8500) += vt8500/
diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c
index f28d4b08771a..c8f20a3d8f88 100644
--- a/drivers/pinctrl/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/pinctrl-bcm2835.c
@@ -699,11 +699,6 @@ static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
699 return 0; 699 return 0;
700} 700}
701 701
702static inline u32 prop_u32(struct property *p, int i)
703{
704 return be32_to_cpup(((__be32 *)p->value) + i);
705}
706
707static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 702static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
708 struct device_node *np, 703 struct device_node *np,
709 struct pinctrl_map **map, unsigned *num_maps) 704 struct pinctrl_map **map, unsigned *num_maps)
@@ -761,7 +756,9 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
761 return -ENOMEM; 756 return -ENOMEM;
762 757
763 for (i = 0; i < num_pins; i++) { 758 for (i = 0; i < num_pins; i++) {
764 pin = prop_u32(pins, i); 759 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
760 if (err)
761 goto out;
765 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) { 762 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
766 dev_err(pc->dev, "%s: invalid brcm,pins value %d\n", 763 dev_err(pc->dev, "%s: invalid brcm,pins value %d\n",
767 of_node_full_name(np), pin); 764 of_node_full_name(np), pin);
@@ -770,14 +767,20 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
770 } 767 }
771 768
772 if (num_funcs) { 769 if (num_funcs) {
773 func = prop_u32(funcs, (num_funcs > 1) ? i : 0); 770 err = of_property_read_u32_index(np, "brcm,function",
771 (num_funcs > 1) ? i : 0, &func);
772 if (err)
773 goto out;
774 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin, 774 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
775 func, &cur_map); 775 func, &cur_map);
776 if (err) 776 if (err)
777 goto out; 777 goto out;
778 } 778 }
779 if (num_pulls) { 779 if (num_pulls) {
780 pull = prop_u32(pulls, (num_pulls > 1) ? i : 0); 780 err = of_property_read_u32_index(np, "brcm,pull",
781 (num_funcs > 1) ? i : 0, &pull);
782 if (err)
783 goto out;
781 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin, 784 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
782 pull, &cur_map); 785 pull, &cur_map);
783 if (err) 786 if (err)
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index ec1567842a7e..ac742817ebce 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -700,3 +700,111 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
700 .label = "exynos4x12-gpio-ctrl3", 700 .label = "exynos4x12-gpio-ctrl3",
701 }, 701 },
702}; 702};
703
704/* pin banks of exynos5250 pin-controller 0 */
705static struct samsung_pin_bank exynos5250_pin_banks0[] = {
706 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
707 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
708 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
709 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
710 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
711 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
712 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
713 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
714 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
715 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
716 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
717 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
718 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
719 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
720 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
721 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
722 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
723 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
724 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
725 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
726 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
727 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
728 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
729 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
730 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
731};
732
733/* pin banks of exynos5250 pin-controller 1 */
734static struct samsung_pin_bank exynos5250_pin_banks1[] = {
735 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
736 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
737 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
738 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
739 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
740 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
741 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
742 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
743 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
744};
745
746/* pin banks of exynos5250 pin-controller 2 */
747static struct samsung_pin_bank exynos5250_pin_banks2[] = {
748 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
749 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
750 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
751 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
752 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
753};
754
755/* pin banks of exynos5250 pin-controller 3 */
756static struct samsung_pin_bank exynos5250_pin_banks3[] = {
757 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
758};
759
760/*
761 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
762 * four gpio/pin-mux/pinconfig controllers.
763 */
764struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
765 {
766 /* pin-controller instance 0 data */
767 .pin_banks = exynos5250_pin_banks0,
768 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
769 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
770 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
771 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
772 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
773 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
774 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
775 .svc = EXYNOS_SVC_OFFSET,
776 .eint_gpio_init = exynos_eint_gpio_init,
777 .eint_wkup_init = exynos_eint_wkup_init,
778 .label = "exynos5250-gpio-ctrl0",
779 }, {
780 /* pin-controller instance 1 data */
781 .pin_banks = exynos5250_pin_banks1,
782 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
783 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
784 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
785 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
786 .svc = EXYNOS_SVC_OFFSET,
787 .eint_gpio_init = exynos_eint_gpio_init,
788 .label = "exynos5250-gpio-ctrl1",
789 }, {
790 /* pin-controller instance 2 data */
791 .pin_banks = exynos5250_pin_banks2,
792 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
793 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
794 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
795 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
796 .svc = EXYNOS_SVC_OFFSET,
797 .eint_gpio_init = exynos_eint_gpio_init,
798 .label = "exynos5250-gpio-ctrl2",
799 }, {
800 /* pin-controller instance 3 data */
801 .pin_banks = exynos5250_pin_banks3,
802 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
803 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
804 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
805 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
806 .svc = EXYNOS_SVC_OFFSET,
807 .eint_gpio_init = exynos_eint_gpio_init,
808 .label = "exynos5250-gpio-ctrl3",
809 },
810};
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 4f54faf2971f..976366899f68 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -970,6 +970,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
970 .data = (void *)exynos4210_pin_ctrl }, 970 .data = (void *)exynos4210_pin_ctrl },
971 { .compatible = "samsung,exynos4x12-pinctrl", 971 { .compatible = "samsung,exynos4x12-pinctrl",
972 .data = (void *)exynos4x12_pin_ctrl }, 972 .data = (void *)exynos4x12_pin_ctrl },
973 { .compatible = "samsung,exynos5250-pinctrl",
974 .data = (void *)exynos5250_pin_ctrl },
973#endif 975#endif
974#ifdef CONFIG_PINCTRL_S3C64XX 976#ifdef CONFIG_PINCTRL_S3C64XX
975 { .compatible = "samsung,s3c64xx-pinctrl", 977 { .compatible = "samsung,s3c64xx-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index 45f27b41e30c..7c7f9ebcd05b 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -244,6 +244,7 @@ struct samsung_pmx_func {
244/* list of all exported SoC specific data */ 244/* list of all exported SoC specific data */
245extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; 245extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
246extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; 246extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
247extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
247extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; 248extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
248 249
249#endif /* __PINCTRL_SAMSUNG_H */ 250#endif /* __PINCTRL_SAMSUNG_H */
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 709008e94124..6f15c03077a0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -2733,9 +2733,9 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2733 { }, 2733 { },
2734}; 2734};
2735 2735
2736/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */ 2736/* External IRQ pins mapped at IRQPIN_BASE */
2737#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5)) 2737#define EXT_IRQ16L(n) irq_pin(n)
2738#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5)) 2738#define EXT_IRQ16H(n) irq_pin(n)
2739 2739
2740static struct pinmux_irq pinmux_irqs[] = { 2740static struct pinmux_irq pinmux_irqs[] = {
2741 PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0), 2741 PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0),
diff --git a/drivers/pinctrl/vt8500/Kconfig b/drivers/pinctrl/vt8500/Kconfig
new file mode 100644
index 000000000000..55724a73d94a
--- /dev/null
+++ b/drivers/pinctrl/vt8500/Kconfig
@@ -0,0 +1,52 @@
1#
2# VIA/Wondermedia PINCTRL drivers
3#
4
5if ARCH_VT8500
6
7config PINCTRL_WMT
8 bool
9 select PINMUX
10 select GENERIC_PINCONF
11
12config PINCTRL_VT8500
13 bool "VIA VT8500 pin controller driver"
14 depends on ARCH_WM8505
15 select PINCTRL_WMT
16 help
17 Say yes here to support the gpio/pin control module on
18 VIA VT8500 SoCs.
19
20config PINCTRL_WM8505
21 bool "Wondermedia WM8505 pin controller driver"
22 depends on ARCH_WM8505
23 select PINCTRL_WMT
24 help
25 Say yes here to support the gpio/pin control module on
26 Wondermedia WM8505 SoCs.
27
28config PINCTRL_WM8650
29 bool "Wondermedia WM8650 pin controller driver"
30 depends on ARCH_WM8505
31 select PINCTRL_WMT
32 help
33 Say yes here to support the gpio/pin control module on
34 Wondermedia WM8650 SoCs.
35
36config PINCTRL_WM8750
37 bool "Wondermedia WM8750 pin controller driver"
38 depends on ARCH_WM8750
39 select PINCTRL_WMT
40 help
41 Say yes here to support the gpio/pin control module on
42 Wondermedia WM8750 SoCs.
43
44config PINCTRL_WM8850
45 bool "Wondermedia WM8850 pin controller driver"
46 depends on ARCH_WM8850
47 select PINCTRL_WMT
48 help
49 Say yes here to support the gpio/pin control module on
50 Wondermedia WM8850 SoCs.
51
52endif
diff --git a/drivers/pinctrl/vt8500/Makefile b/drivers/pinctrl/vt8500/Makefile
new file mode 100644
index 000000000000..24ec45dd0d80
--- /dev/null
+++ b/drivers/pinctrl/vt8500/Makefile
@@ -0,0 +1,8 @@
1# VIA/Wondermedia pinctrl support
2
3obj-$(CONFIG_PINCTRL_WMT) += pinctrl-wmt.o
4obj-$(CONFIG_PINCTRL_VT8500) += pinctrl-vt8500.o
5obj-$(CONFIG_PINCTRL_WM8505) += pinctrl-wm8505.o
6obj-$(CONFIG_PINCTRL_WM8650) += pinctrl-wm8650.o
7obj-$(CONFIG_PINCTRL_WM8750) += pinctrl-wm8750.o
8obj-$(CONFIG_PINCTRL_WM8850) += pinctrl-wm8850.o
diff --git a/drivers/pinctrl/vt8500/pinctrl-vt8500.c b/drivers/pinctrl/vt8500/pinctrl-vt8500.c
new file mode 100644
index 000000000000..f2fe9f85cfa6
--- /dev/null
+++ b/drivers/pinctrl/vt8500/pinctrl-vt8500.c
@@ -0,0 +1,501 @@
1/*
2 * Pinctrl data for VIA VT8500 SoC
3 *
4 * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/pinctrl/pinctrl.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21
22#include "pinctrl-wmt.h"
23
24/*
25 * Describe the register offsets within the GPIO memory space
26 * The dedicated external GPIO's should always be listed in bank 0
27 * so they are exported in the 0..31 range which is what users
28 * expect.
29 *
30 * Do not reorder these banks as it will change the pin numbering
31 */
32static const struct wmt_pinctrl_bank_registers vt8500_banks[] = {
33 WMT_PINCTRL_BANK(NO_REG, 0x3C, 0x5C, 0x7C, NO_REG, NO_REG), /* 0 */
34 WMT_PINCTRL_BANK(0x00, 0x20, 0x40, 0x60, NO_REG, NO_REG), /* 1 */
35 WMT_PINCTRL_BANK(0x04, 0x24, 0x44, 0x64, NO_REG, NO_REG), /* 2 */
36 WMT_PINCTRL_BANK(0x08, 0x28, 0x48, 0x68, NO_REG, NO_REG), /* 3 */
37 WMT_PINCTRL_BANK(0x0C, 0x2C, 0x4C, 0x6C, NO_REG, NO_REG), /* 4 */
38 WMT_PINCTRL_BANK(0x10, 0x30, 0x50, 0x70, NO_REG, NO_REG), /* 5 */
39 WMT_PINCTRL_BANK(0x14, 0x34, 0x54, 0x74, NO_REG, NO_REG), /* 6 */
40};
41
42/* Please keep sorted by bank/bit */
43#define WMT_PIN_EXTGPIO0 WMT_PIN(0, 0)
44#define WMT_PIN_EXTGPIO1 WMT_PIN(0, 1)
45#define WMT_PIN_EXTGPIO2 WMT_PIN(0, 2)
46#define WMT_PIN_EXTGPIO3 WMT_PIN(0, 3)
47#define WMT_PIN_EXTGPIO4 WMT_PIN(0, 4)
48#define WMT_PIN_EXTGPIO5 WMT_PIN(0, 5)
49#define WMT_PIN_EXTGPIO6 WMT_PIN(0, 6)
50#define WMT_PIN_EXTGPIO7 WMT_PIN(0, 7)
51#define WMT_PIN_EXTGPIO8 WMT_PIN(0, 8)
52#define WMT_PIN_UART0RTS WMT_PIN(1, 0)
53#define WMT_PIN_UART0TXD WMT_PIN(1, 1)
54#define WMT_PIN_UART0CTS WMT_PIN(1, 2)
55#define WMT_PIN_UART0RXD WMT_PIN(1, 3)
56#define WMT_PIN_UART1RTS WMT_PIN(1, 4)
57#define WMT_PIN_UART1TXD WMT_PIN(1, 5)
58#define WMT_PIN_UART1CTS WMT_PIN(1, 6)
59#define WMT_PIN_UART1RXD WMT_PIN(1, 7)
60#define WMT_PIN_SPI0CLK WMT_PIN(1, 8)
61#define WMT_PIN_SPI0SS WMT_PIN(1, 9)
62#define WMT_PIN_SPI0MISO WMT_PIN(1, 10)
63#define WMT_PIN_SPI0MOSI WMT_PIN(1, 11)
64#define WMT_PIN_SPI1CLK WMT_PIN(1, 12)
65#define WMT_PIN_SPI1SS WMT_PIN(1, 13)
66#define WMT_PIN_SPI1MISO WMT_PIN(1, 14)
67#define WMT_PIN_SPI1MOSI WMT_PIN(1, 15)
68#define WMT_PIN_SPI2CLK WMT_PIN(1, 16)
69#define WMT_PIN_SPI2SS WMT_PIN(1, 17)
70#define WMT_PIN_SPI2MISO WMT_PIN(1, 18)
71#define WMT_PIN_SPI2MOSI WMT_PIN(1, 19)
72#define WMT_PIN_SDDATA0 WMT_PIN(2, 0)
73#define WMT_PIN_SDDATA1 WMT_PIN(2, 1)
74#define WMT_PIN_SDDATA2 WMT_PIN(2, 2)
75#define WMT_PIN_SDDATA3 WMT_PIN(2, 3)
76#define WMT_PIN_MMCDATA0 WMT_PIN(2, 4)
77#define WMT_PIN_MMCDATA1 WMT_PIN(2, 5)
78#define WMT_PIN_MMCDATA2 WMT_PIN(2, 6)
79#define WMT_PIN_MMCDATA3 WMT_PIN(2, 7)
80#define WMT_PIN_SDCLK WMT_PIN(2, 8)
81#define WMT_PIN_SDWP WMT_PIN(2, 9)
82#define WMT_PIN_SDCMD WMT_PIN(2, 10)
83#define WMT_PIN_MSDATA0 WMT_PIN(2, 16)
84#define WMT_PIN_MSDATA1 WMT_PIN(2, 17)
85#define WMT_PIN_MSDATA2 WMT_PIN(2, 18)
86#define WMT_PIN_MSDATA3 WMT_PIN(2, 19)
87#define WMT_PIN_MSCLK WMT_PIN(2, 20)
88#define WMT_PIN_MSBS WMT_PIN(2, 21)
89#define WMT_PIN_MSINS WMT_PIN(2, 22)
90#define WMT_PIN_I2C0SCL WMT_PIN(2, 24)
91#define WMT_PIN_I2C0SDA WMT_PIN(2, 25)
92#define WMT_PIN_I2C1SCL WMT_PIN(2, 26)
93#define WMT_PIN_I2C1SDA WMT_PIN(2, 27)
94#define WMT_PIN_MII0RXD0 WMT_PIN(3, 0)
95#define WMT_PIN_MII0RXD1 WMT_PIN(3, 1)
96#define WMT_PIN_MII0RXD2 WMT_PIN(3, 2)
97#define WMT_PIN_MII0RXD3 WMT_PIN(3, 3)
98#define WMT_PIN_MII0RXCLK WMT_PIN(3, 4)
99#define WMT_PIN_MII0RXDV WMT_PIN(3, 5)
100#define WMT_PIN_MII0RXERR WMT_PIN(3, 6)
101#define WMT_PIN_MII0PHYRST WMT_PIN(3, 7)
102#define WMT_PIN_MII0TXD0 WMT_PIN(3, 8)
103#define WMT_PIN_MII0TXD1 WMT_PIN(3, 9)
104#define WMT_PIN_MII0TXD2 WMT_PIN(3, 10)
105#define WMT_PIN_MII0TXD3 WMT_PIN(3, 11)
106#define WMT_PIN_MII0TXCLK WMT_PIN(3, 12)
107#define WMT_PIN_MII0TXEN WMT_PIN(3, 13)
108#define WMT_PIN_MII0TXERR WMT_PIN(3, 14)
109#define WMT_PIN_MII0PHYPD WMT_PIN(3, 15)
110#define WMT_PIN_MII0COL WMT_PIN(3, 16)
111#define WMT_PIN_MII0CRS WMT_PIN(3, 17)
112#define WMT_PIN_MII0MDIO WMT_PIN(3, 18)
113#define WMT_PIN_MII0MDC WMT_PIN(3, 19)
114#define WMT_PIN_SEECS WMT_PIN(3, 20)
115#define WMT_PIN_SEECK WMT_PIN(3, 21)
116#define WMT_PIN_SEEDI WMT_PIN(3, 22)
117#define WMT_PIN_SEEDO WMT_PIN(3, 23)
118#define WMT_PIN_IDEDREQ0 WMT_PIN(3, 24)
119#define WMT_PIN_IDEDREQ1 WMT_PIN(3, 25)
120#define WMT_PIN_IDEIOW WMT_PIN(3, 26)
121#define WMT_PIN_IDEIOR WMT_PIN(3, 27)
122#define WMT_PIN_IDEDACK WMT_PIN(3, 28)
123#define WMT_PIN_IDEIORDY WMT_PIN(3, 29)
124#define WMT_PIN_IDEINTRQ WMT_PIN(3, 30)
125#define WMT_PIN_VDIN0 WMT_PIN(4, 0)
126#define WMT_PIN_VDIN1 WMT_PIN(4, 1)
127#define WMT_PIN_VDIN2 WMT_PIN(4, 2)
128#define WMT_PIN_VDIN3 WMT_PIN(4, 3)
129#define WMT_PIN_VDIN4 WMT_PIN(4, 4)
130#define WMT_PIN_VDIN5 WMT_PIN(4, 5)
131#define WMT_PIN_VDIN6 WMT_PIN(4, 6)
132#define WMT_PIN_VDIN7 WMT_PIN(4, 7)
133#define WMT_PIN_VDOUT0 WMT_PIN(4, 8)
134#define WMT_PIN_VDOUT1 WMT_PIN(4, 9)
135#define WMT_PIN_VDOUT2 WMT_PIN(4, 10)
136#define WMT_PIN_VDOUT3 WMT_PIN(4, 11)
137#define WMT_PIN_VDOUT4 WMT_PIN(4, 12)
138#define WMT_PIN_VDOUT5 WMT_PIN(4, 13)
139#define WMT_PIN_NANDCLE0 WMT_PIN(4, 14)
140#define WMT_PIN_NANDCLE1 WMT_PIN(4, 15)
141#define WMT_PIN_VDOUT6_7 WMT_PIN(4, 16)
142#define WMT_PIN_VHSYNC WMT_PIN(4, 17)
143#define WMT_PIN_VVSYNC WMT_PIN(4, 18)
144#define WMT_PIN_TSDIN0 WMT_PIN(5, 8)
145#define WMT_PIN_TSDIN1 WMT_PIN(5, 9)
146#define WMT_PIN_TSDIN2 WMT_PIN(5, 10)
147#define WMT_PIN_TSDIN3 WMT_PIN(5, 11)
148#define WMT_PIN_TSDIN4 WMT_PIN(5, 12)
149#define WMT_PIN_TSDIN5 WMT_PIN(5, 13)
150#define WMT_PIN_TSDIN6 WMT_PIN(5, 14)
151#define WMT_PIN_TSDIN7 WMT_PIN(5, 15)
152#define WMT_PIN_TSSYNC WMT_PIN(5, 16)
153#define WMT_PIN_TSVALID WMT_PIN(5, 17)
154#define WMT_PIN_TSCLK WMT_PIN(5, 18)
155#define WMT_PIN_LCDD0 WMT_PIN(6, 0)
156#define WMT_PIN_LCDD1 WMT_PIN(6, 1)
157#define WMT_PIN_LCDD2 WMT_PIN(6, 2)
158#define WMT_PIN_LCDD3 WMT_PIN(6, 3)
159#define WMT_PIN_LCDD4 WMT_PIN(6, 4)
160#define WMT_PIN_LCDD5 WMT_PIN(6, 5)
161#define WMT_PIN_LCDD6 WMT_PIN(6, 6)
162#define WMT_PIN_LCDD7 WMT_PIN(6, 7)
163#define WMT_PIN_LCDD8 WMT_PIN(6, 8)
164#define WMT_PIN_LCDD9 WMT_PIN(6, 9)
165#define WMT_PIN_LCDD10 WMT_PIN(6, 10)
166#define WMT_PIN_LCDD11 WMT_PIN(6, 11)
167#define WMT_PIN_LCDD12 WMT_PIN(6, 12)
168#define WMT_PIN_LCDD13 WMT_PIN(6, 13)
169#define WMT_PIN_LCDD14 WMT_PIN(6, 14)
170#define WMT_PIN_LCDD15 WMT_PIN(6, 15)
171#define WMT_PIN_LCDD16 WMT_PIN(6, 16)
172#define WMT_PIN_LCDD17 WMT_PIN(6, 17)
173#define WMT_PIN_LCDCLK WMT_PIN(6, 18)
174#define WMT_PIN_LCDDEN WMT_PIN(6, 19)
175#define WMT_PIN_LCDLINE WMT_PIN(6, 20)
176#define WMT_PIN_LCDFRM WMT_PIN(6, 21)
177#define WMT_PIN_LCDBIAS WMT_PIN(6, 22)
178
179static const struct pinctrl_pin_desc vt8500_pins[] = {
180 PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"),
181 PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"),
182 PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"),
183 PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"),
184 PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"),
185 PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"),
186 PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"),
187 PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"),
188 PINCTRL_PIN(WMT_PIN_EXTGPIO8, "extgpio8"),
189 PINCTRL_PIN(WMT_PIN_UART0RTS, "uart0_rts"),
190 PINCTRL_PIN(WMT_PIN_UART0TXD, "uart0_txd"),
191 PINCTRL_PIN(WMT_PIN_UART0CTS, "uart0_cts"),
192 PINCTRL_PIN(WMT_PIN_UART0RXD, "uart0_rxd"),
193 PINCTRL_PIN(WMT_PIN_UART1RTS, "uart1_rts"),
194 PINCTRL_PIN(WMT_PIN_UART1TXD, "uart1_txd"),
195 PINCTRL_PIN(WMT_PIN_UART1CTS, "uart1_cts"),
196 PINCTRL_PIN(WMT_PIN_UART1RXD, "uart1_rxd"),
197 PINCTRL_PIN(WMT_PIN_SPI0CLK, "spi0_clk"),
198 PINCTRL_PIN(WMT_PIN_SPI0SS, "spi0_ss"),
199 PINCTRL_PIN(WMT_PIN_SPI0MISO, "spi0_miso"),
200 PINCTRL_PIN(WMT_PIN_SPI0MOSI, "spi0_mosi"),
201 PINCTRL_PIN(WMT_PIN_SPI1CLK, "spi1_clk"),
202 PINCTRL_PIN(WMT_PIN_SPI1SS, "spi1_ss"),
203 PINCTRL_PIN(WMT_PIN_SPI1MISO, "spi1_miso"),
204 PINCTRL_PIN(WMT_PIN_SPI1MOSI, "spi1_mosi"),
205 PINCTRL_PIN(WMT_PIN_SPI2CLK, "spi2_clk"),
206 PINCTRL_PIN(WMT_PIN_SPI2SS, "spi2_ss"),
207 PINCTRL_PIN(WMT_PIN_SPI2MISO, "spi2_miso"),
208 PINCTRL_PIN(WMT_PIN_SPI2MOSI, "spi2_mosi"),
209 PINCTRL_PIN(WMT_PIN_SDDATA0, "sd_data0"),
210 PINCTRL_PIN(WMT_PIN_SDDATA1, "sd_data1"),
211 PINCTRL_PIN(WMT_PIN_SDDATA2, "sd_data2"),
212 PINCTRL_PIN(WMT_PIN_SDDATA3, "sd_data3"),
213 PINCTRL_PIN(WMT_PIN_MMCDATA0, "mmc_data0"),
214 PINCTRL_PIN(WMT_PIN_MMCDATA1, "mmc_data1"),
215 PINCTRL_PIN(WMT_PIN_MMCDATA2, "mmc_data2"),
216 PINCTRL_PIN(WMT_PIN_MMCDATA3, "mmc_data3"),
217 PINCTRL_PIN(WMT_PIN_SDCLK, "sd_clk"),
218 PINCTRL_PIN(WMT_PIN_SDWP, "sd_wp"),
219 PINCTRL_PIN(WMT_PIN_SDCMD, "sd_cmd"),
220 PINCTRL_PIN(WMT_PIN_MSDATA0, "ms_data0"),
221 PINCTRL_PIN(WMT_PIN_MSDATA1, "ms_data1"),
222 PINCTRL_PIN(WMT_PIN_MSDATA2, "ms_data2"),
223 PINCTRL_PIN(WMT_PIN_MSDATA3, "ms_data3"),
224 PINCTRL_PIN(WMT_PIN_MSCLK, "ms_clk"),
225 PINCTRL_PIN(WMT_PIN_MSBS, "ms_bs"),
226 PINCTRL_PIN(WMT_PIN_MSINS, "ms_ins"),
227 PINCTRL_PIN(WMT_PIN_I2C0SCL, "i2c0_scl"),
228 PINCTRL_PIN(WMT_PIN_I2C0SDA, "i2c0_sda"),
229 PINCTRL_PIN(WMT_PIN_I2C1SCL, "i2c1_scl"),
230 PINCTRL_PIN(WMT_PIN_I2C1SDA, "i2c1_sda"),
231 PINCTRL_PIN(WMT_PIN_MII0RXD0, "mii0_rxd0"),
232 PINCTRL_PIN(WMT_PIN_MII0RXD1, "mii0_rxd1"),
233 PINCTRL_PIN(WMT_PIN_MII0RXD2, "mii0_rxd2"),
234 PINCTRL_PIN(WMT_PIN_MII0RXD3, "mii0_rxd3"),
235 PINCTRL_PIN(WMT_PIN_MII0RXCLK, "mii0_rxclk"),
236 PINCTRL_PIN(WMT_PIN_MII0RXDV, "mii0_rxdv"),
237 PINCTRL_PIN(WMT_PIN_MII0RXERR, "mii0_rxerr"),
238 PINCTRL_PIN(WMT_PIN_MII0PHYRST, "mii0_phyrst"),
239 PINCTRL_PIN(WMT_PIN_MII0TXD0, "mii0_txd0"),
240 PINCTRL_PIN(WMT_PIN_MII0TXD1, "mii0_txd1"),
241 PINCTRL_PIN(WMT_PIN_MII0TXD2, "mii0_txd2"),
242 PINCTRL_PIN(WMT_PIN_MII0TXD3, "mii0_txd3"),
243 PINCTRL_PIN(WMT_PIN_MII0TXCLK, "mii0_txclk"),
244 PINCTRL_PIN(WMT_PIN_MII0TXEN, "mii0_txen"),
245 PINCTRL_PIN(WMT_PIN_MII0TXERR, "mii0_txerr"),
246 PINCTRL_PIN(WMT_PIN_MII0PHYPD, "mii0_phypd"),
247 PINCTRL_PIN(WMT_PIN_MII0COL, "mii0_col"),
248 PINCTRL_PIN(WMT_PIN_MII0CRS, "mii0_crs"),
249 PINCTRL_PIN(WMT_PIN_MII0MDIO, "mii0_mdio"),
250 PINCTRL_PIN(WMT_PIN_MII0MDC, "mii0_mdc"),
251 PINCTRL_PIN(WMT_PIN_SEECS, "see_cs"),
252 PINCTRL_PIN(WMT_PIN_SEECK, "see_ck"),
253 PINCTRL_PIN(WMT_PIN_SEEDI, "see_di"),
254 PINCTRL_PIN(WMT_PIN_SEEDO, "see_do"),
255 PINCTRL_PIN(WMT_PIN_IDEDREQ0, "ide_dreq0"),
256 PINCTRL_PIN(WMT_PIN_IDEDREQ1, "ide_dreq1"),
257 PINCTRL_PIN(WMT_PIN_IDEIOW, "ide_iow"),
258 PINCTRL_PIN(WMT_PIN_IDEIOR, "ide_ior"),
259 PINCTRL_PIN(WMT_PIN_IDEDACK, "ide_dack"),
260 PINCTRL_PIN(WMT_PIN_IDEIORDY, "ide_iordy"),
261 PINCTRL_PIN(WMT_PIN_IDEINTRQ, "ide_intrq"),
262 PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"),
263 PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"),
264 PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"),
265 PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"),
266 PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"),
267 PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"),
268 PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"),
269 PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"),
270 PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"),
271 PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"),
272 PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"),
273 PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"),
274 PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"),
275 PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"),
276 PINCTRL_PIN(WMT_PIN_NANDCLE0, "nand_cle0"),
277 PINCTRL_PIN(WMT_PIN_NANDCLE1, "nand_cle1"),
278 PINCTRL_PIN(WMT_PIN_VDOUT6_7, "vdout6_7"),
279 PINCTRL_PIN(WMT_PIN_VHSYNC, "vhsync"),
280 PINCTRL_PIN(WMT_PIN_VVSYNC, "vvsync"),
281 PINCTRL_PIN(WMT_PIN_TSDIN0, "tsdin0"),
282 PINCTRL_PIN(WMT_PIN_TSDIN1, "tsdin1"),
283 PINCTRL_PIN(WMT_PIN_TSDIN2, "tsdin2"),
284 PINCTRL_PIN(WMT_PIN_TSDIN3, "tsdin3"),
285 PINCTRL_PIN(WMT_PIN_TSDIN4, "tsdin4"),
286 PINCTRL_PIN(WMT_PIN_TSDIN5, "tsdin5"),
287 PINCTRL_PIN(WMT_PIN_TSDIN6, "tsdin6"),
288 PINCTRL_PIN(WMT_PIN_TSDIN7, "tsdin7"),
289 PINCTRL_PIN(WMT_PIN_TSSYNC, "tssync"),
290 PINCTRL_PIN(WMT_PIN_TSVALID, "tsvalid"),
291 PINCTRL_PIN(WMT_PIN_TSCLK, "tsclk"),
292 PINCTRL_PIN(WMT_PIN_LCDD0, "lcd_d0"),
293 PINCTRL_PIN(WMT_PIN_LCDD1, "lcd_d1"),
294 PINCTRL_PIN(WMT_PIN_LCDD2, "lcd_d2"),
295 PINCTRL_PIN(WMT_PIN_LCDD3, "lcd_d3"),
296 PINCTRL_PIN(WMT_PIN_LCDD4, "lcd_d4"),
297 PINCTRL_PIN(WMT_PIN_LCDD5, "lcd_d5"),
298 PINCTRL_PIN(WMT_PIN_LCDD6, "lcd_d6"),
299 PINCTRL_PIN(WMT_PIN_LCDD7, "lcd_d7"),
300 PINCTRL_PIN(WMT_PIN_LCDD8, "lcd_d8"),
301 PINCTRL_PIN(WMT_PIN_LCDD9, "lcd_d9"),
302 PINCTRL_PIN(WMT_PIN_LCDD10, "lcd_d10"),
303 PINCTRL_PIN(WMT_PIN_LCDD11, "lcd_d11"),
304 PINCTRL_PIN(WMT_PIN_LCDD12, "lcd_d12"),
305 PINCTRL_PIN(WMT_PIN_LCDD13, "lcd_d13"),
306 PINCTRL_PIN(WMT_PIN_LCDD14, "lcd_d14"),
307 PINCTRL_PIN(WMT_PIN_LCDD15, "lcd_d15"),
308 PINCTRL_PIN(WMT_PIN_LCDD16, "lcd_d16"),
309 PINCTRL_PIN(WMT_PIN_LCDD17, "lcd_d17"),
310 PINCTRL_PIN(WMT_PIN_LCDCLK, "lcd_clk"),
311 PINCTRL_PIN(WMT_PIN_LCDDEN, "lcd_den"),
312 PINCTRL_PIN(WMT_PIN_LCDLINE, "lcd_line"),
313 PINCTRL_PIN(WMT_PIN_LCDFRM, "lcd_frm"),
314 PINCTRL_PIN(WMT_PIN_LCDBIAS, "lcd_bias"),
315};
316
317/* Order of these names must match the above list */
318static const char * const vt8500_groups[] = {
319 "extgpio0",
320 "extgpio1",
321 "extgpio2",
322 "extgpio3",
323 "extgpio4",
324 "extgpio5",
325 "extgpio6",
326 "extgpio7",
327 "extgpio8",
328 "uart0_rts",
329 "uart0_txd",
330 "uart0_cts",
331 "uart0_rxd",
332 "uart1_rts",
333 "uart1_txd",
334 "uart1_cts",
335 "uart1_rxd",
336 "spi0_clk",
337 "spi0_ss",
338 "spi0_miso",
339 "spi0_mosi",
340 "spi1_clk",
341 "spi1_ss",
342 "spi1_miso",
343 "spi1_mosi",
344 "spi2_clk",
345 "spi2_ss",
346 "spi2_miso",
347 "spi2_mosi",
348 "sd_data0",
349 "sd_data1",
350 "sd_data2",
351 "sd_data3",
352 "mmc_data0",
353 "mmc_data1",
354 "mmc_data2",
355 "mmc_data3",
356 "sd_clk",
357 "sd_wp",
358 "sd_cmd",
359 "ms_data0",
360 "ms_data1",
361 "ms_data2",
362 "ms_data3",
363 "ms_clk",
364 "ms_bs",
365 "ms_ins",
366 "i2c0_scl",
367 "i2c0_sda",
368 "i2c1_scl",
369 "i2c1_sda",
370 "mii0_rxd0",
371 "mii0_rxd1",
372 "mii0_rxd2",
373 "mii0_rxd3",
374 "mii0_rxclk",
375 "mii0_rxdv",
376 "mii0_rxerr",
377 "mii0_phyrst",
378 "mii0_txd0",
379 "mii0_txd1",
380 "mii0_txd2",
381 "mii0_txd3",
382 "mii0_txclk",
383 "mii0_txen",
384 "mii0_txerr",
385 "mii0_phypd",
386 "mii0_col",
387 "mii0_crs",
388 "mii0_mdio",
389 "mii0_mdc",
390 "see_cs",
391 "see_ck",
392 "see_di",
393 "see_do",
394 "ide_dreq0",
395 "ide_dreq1",
396 "ide_iow",
397 "ide_ior",
398 "ide_dack",
399 "ide_iordy",
400 "ide_intrq",
401 "vdin0",
402 "vdin1",
403 "vdin2",
404 "vdin3",
405 "vdin4",
406 "vdin5",
407 "vdin6",
408 "vdin7",
409 "vdout0",
410 "vdout1",
411 "vdout2",
412 "vdout3",
413 "vdout4",
414 "vdout5",
415 "nand_cle0",
416 "nand_cle1",
417 "vdout6_7",
418 "vhsync",
419 "vvsync",
420 "tsdin0",
421 "tsdin1",
422 "tsdin2",
423 "tsdin3",
424 "tsdin4",
425 "tsdin5",
426 "tsdin6",
427 "tsdin7",
428 "tssync",
429 "tsvalid",
430 "tsclk",
431 "lcd_d0",
432 "lcd_d1",
433 "lcd_d2",
434 "lcd_d3",
435 "lcd_d4",
436 "lcd_d5",
437 "lcd_d6",
438 "lcd_d7",
439 "lcd_d8",
440 "lcd_d9",
441 "lcd_d10",
442 "lcd_d11",
443 "lcd_d12",
444 "lcd_d13",
445 "lcd_d14",
446 "lcd_d15",
447 "lcd_d16",
448 "lcd_d17",
449 "lcd_clk",
450 "lcd_den",
451 "lcd_line",
452 "lcd_frm",
453 "lcd_bias",
454};
455
456static int vt8500_pinctrl_probe(struct platform_device *pdev)
457{
458 struct wmt_pinctrl_data *data;
459
460 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
461 if (!data) {
462 dev_err(&pdev->dev, "failed to allocate data\n");
463 return -ENOMEM;
464 }
465
466 data->banks = vt8500_banks;
467 data->nbanks = ARRAY_SIZE(vt8500_banks);
468 data->pins = vt8500_pins;
469 data->npins = ARRAY_SIZE(vt8500_pins);
470 data->groups = vt8500_groups;
471 data->ngroups = ARRAY_SIZE(vt8500_groups);
472
473 return wmt_pinctrl_probe(pdev, data);
474}
475
476static int vt8500_pinctrl_remove(struct platform_device *pdev)
477{
478 return wmt_pinctrl_remove(pdev);
479}
480
481static struct of_device_id wmt_pinctrl_of_match[] = {
482 { .compatible = "via,vt8500-pinctrl" },
483 { /* sentinel */ },
484};
485
486static struct platform_driver wmt_pinctrl_driver = {
487 .probe = vt8500_pinctrl_probe,
488 .remove = vt8500_pinctrl_remove,
489 .driver = {
490 .name = "pinctrl-vt8500",
491 .owner = THIS_MODULE,
492 .of_match_table = wmt_pinctrl_of_match,
493 },
494};
495
496module_platform_driver(wmt_pinctrl_driver);
497
498MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
499MODULE_DESCRIPTION("VIA VT8500 Pincontrol driver");
500MODULE_LICENSE("GPL v2");
501MODULE_DEVICE_TABLE(of, wmt_pinctrl_of_match);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8505.c b/drivers/pinctrl/vt8500/pinctrl-wm8505.c
new file mode 100644
index 000000000000..483ba732694e
--- /dev/null
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8505.c
@@ -0,0 +1,532 @@
1/*
2 * Pinctrl data for Wondermedia WM8505 SoC
3 *
4 * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/pinctrl/pinctrl.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21
22#include "pinctrl-wmt.h"
23
24/*
25 * Describe the register offsets within the GPIO memory space
26 * The dedicated external GPIO's should always be listed in bank 0
27 * so they are exported in the 0..31 range which is what users
28 * expect.
29 *
30 * Do not reorder these banks as it will change the pin numbering
31 */
32static const struct wmt_pinctrl_bank_registers wm8505_banks[] = {
33 WMT_PINCTRL_BANK(0x64, 0x8C, 0xB4, 0xDC, NO_REG, NO_REG), /* 0 */
34 WMT_PINCTRL_BANK(0x40, 0x68, 0x90, 0xB8, NO_REG, NO_REG), /* 1 */
35 WMT_PINCTRL_BANK(0x44, 0x6C, 0x94, 0xBC, NO_REG, NO_REG), /* 2 */
36 WMT_PINCTRL_BANK(0x48, 0x70, 0x98, 0xC0, NO_REG, NO_REG), /* 3 */
37 WMT_PINCTRL_BANK(0x4C, 0x74, 0x9C, 0xC4, NO_REG, NO_REG), /* 4 */
38 WMT_PINCTRL_BANK(0x50, 0x78, 0xA0, 0xC8, NO_REG, NO_REG), /* 5 */
39 WMT_PINCTRL_BANK(0x54, 0x7C, 0xA4, 0xD0, NO_REG, NO_REG), /* 6 */
40 WMT_PINCTRL_BANK(0x58, 0x80, 0xA8, 0xD4, NO_REG, NO_REG), /* 7 */
41 WMT_PINCTRL_BANK(0x5C, 0x84, 0xAC, 0xD8, NO_REG, NO_REG), /* 8 */
42 WMT_PINCTRL_BANK(0x60, 0x88, 0xB0, 0xDC, NO_REG, NO_REG), /* 9 */
43 WMT_PINCTRL_BANK(0x500, 0x504, 0x508, 0x50C, NO_REG, NO_REG), /* 10 */
44};
45
46/* Please keep sorted by bank/bit */
47#define WMT_PIN_EXTGPIO0 WMT_PIN(0, 0)
48#define WMT_PIN_EXTGPIO1 WMT_PIN(0, 1)
49#define WMT_PIN_EXTGPIO2 WMT_PIN(0, 2)
50#define WMT_PIN_EXTGPIO3 WMT_PIN(0, 3)
51#define WMT_PIN_EXTGPIO4 WMT_PIN(0, 4)
52#define WMT_PIN_EXTGPIO5 WMT_PIN(0, 5)
53#define WMT_PIN_EXTGPIO6 WMT_PIN(0, 6)
54#define WMT_PIN_EXTGPIO7 WMT_PIN(0, 7)
55#define WMT_PIN_WAKEUP0 WMT_PIN(0, 16)
56#define WMT_PIN_WAKEUP1 WMT_PIN(0, 17)
57#define WMT_PIN_WAKEUP2 WMT_PIN(0, 18)
58#define WMT_PIN_WAKEUP3 WMT_PIN(0, 19)
59#define WMT_PIN_SUSGPIO0 WMT_PIN(0, 21)
60#define WMT_PIN_SDDATA0 WMT_PIN(1, 0)
61#define WMT_PIN_SDDATA1 WMT_PIN(1, 1)
62#define WMT_PIN_SDDATA2 WMT_PIN(1, 2)
63#define WMT_PIN_SDDATA3 WMT_PIN(1, 3)
64#define WMT_PIN_MMCDATA0 WMT_PIN(1, 4)
65#define WMT_PIN_MMCDATA1 WMT_PIN(1, 5)
66#define WMT_PIN_MMCDATA2 WMT_PIN(1, 6)
67#define WMT_PIN_MMCDATA3 WMT_PIN(1, 7)
68#define WMT_PIN_VDIN0 WMT_PIN(2, 0)
69#define WMT_PIN_VDIN1 WMT_PIN(2, 1)
70#define WMT_PIN_VDIN2 WMT_PIN(2, 2)
71#define WMT_PIN_VDIN3 WMT_PIN(2, 3)
72#define WMT_PIN_VDIN4 WMT_PIN(2, 4)
73#define WMT_PIN_VDIN5 WMT_PIN(2, 5)
74#define WMT_PIN_VDIN6 WMT_PIN(2, 6)
75#define WMT_PIN_VDIN7 WMT_PIN(2, 7)
76#define WMT_PIN_VDOUT0 WMT_PIN(2, 8)
77#define WMT_PIN_VDOUT1 WMT_PIN(2, 9)
78#define WMT_PIN_VDOUT2 WMT_PIN(2, 10)
79#define WMT_PIN_VDOUT3 WMT_PIN(2, 11)
80#define WMT_PIN_VDOUT4 WMT_PIN(2, 12)
81#define WMT_PIN_VDOUT5 WMT_PIN(2, 13)
82#define WMT_PIN_VDOUT6 WMT_PIN(2, 14)
83#define WMT_PIN_VDOUT7 WMT_PIN(2, 15)
84#define WMT_PIN_VDOUT8 WMT_PIN(2, 16)
85#define WMT_PIN_VDOUT9 WMT_PIN(2, 17)
86#define WMT_PIN_VDOUT10 WMT_PIN(2, 18)
87#define WMT_PIN_VDOUT11 WMT_PIN(2, 19)
88#define WMT_PIN_VDOUT12 WMT_PIN(2, 20)
89#define WMT_PIN_VDOUT13 WMT_PIN(2, 21)
90#define WMT_PIN_VDOUT14 WMT_PIN(2, 22)
91#define WMT_PIN_VDOUT15 WMT_PIN(2, 23)
92#define WMT_PIN_VDOUT16 WMT_PIN(2, 24)
93#define WMT_PIN_VDOUT17 WMT_PIN(2, 25)
94#define WMT_PIN_VDOUT18 WMT_PIN(2, 26)
95#define WMT_PIN_VDOUT19 WMT_PIN(2, 27)
96#define WMT_PIN_VDOUT20 WMT_PIN(2, 28)
97#define WMT_PIN_VDOUT21 WMT_PIN(2, 29)
98#define WMT_PIN_VDOUT22 WMT_PIN(2, 30)
99#define WMT_PIN_VDOUT23 WMT_PIN(2, 31)
100#define WMT_PIN_VHSYNC WMT_PIN(3, 0)
101#define WMT_PIN_VVSYNC WMT_PIN(3, 1)
102#define WMT_PIN_VGAHSYNC WMT_PIN(3, 2)
103#define WMT_PIN_VGAVSYNC WMT_PIN(3, 3)
104#define WMT_PIN_VDHSYNC WMT_PIN(3, 4)
105#define WMT_PIN_VDVSYNC WMT_PIN(3, 5)
106#define WMT_PIN_NORD0 WMT_PIN(4, 0)
107#define WMT_PIN_NORD1 WMT_PIN(4, 1)
108#define WMT_PIN_NORD2 WMT_PIN(4, 2)
109#define WMT_PIN_NORD3 WMT_PIN(4, 3)
110#define WMT_PIN_NORD4 WMT_PIN(4, 4)
111#define WMT_PIN_NORD5 WMT_PIN(4, 5)
112#define WMT_PIN_NORD6 WMT_PIN(4, 6)
113#define WMT_PIN_NORD7 WMT_PIN(4, 7)
114#define WMT_PIN_NORD8 WMT_PIN(4, 8)
115#define WMT_PIN_NORD9 WMT_PIN(4, 9)
116#define WMT_PIN_NORD10 WMT_PIN(4, 10)
117#define WMT_PIN_NORD11 WMT_PIN(4, 11)
118#define WMT_PIN_NORD12 WMT_PIN(4, 12)
119#define WMT_PIN_NORD13 WMT_PIN(4, 13)
120#define WMT_PIN_NORD14 WMT_PIN(4, 14)
121#define WMT_PIN_NORD15 WMT_PIN(4, 15)
122#define WMT_PIN_NORA0 WMT_PIN(5, 0)
123#define WMT_PIN_NORA1 WMT_PIN(5, 1)
124#define WMT_PIN_NORA2 WMT_PIN(5, 2)
125#define WMT_PIN_NORA3 WMT_PIN(5, 3)
126#define WMT_PIN_NORA4 WMT_PIN(5, 4)
127#define WMT_PIN_NORA5 WMT_PIN(5, 5)
128#define WMT_PIN_NORA6 WMT_PIN(5, 6)
129#define WMT_PIN_NORA7 WMT_PIN(5, 7)
130#define WMT_PIN_NORA8 WMT_PIN(5, 8)
131#define WMT_PIN_NORA9 WMT_PIN(5, 9)
132#define WMT_PIN_NORA10 WMT_PIN(5, 10)
133#define WMT_PIN_NORA11 WMT_PIN(5, 11)
134#define WMT_PIN_NORA12 WMT_PIN(5, 12)
135#define WMT_PIN_NORA13 WMT_PIN(5, 13)
136#define WMT_PIN_NORA14 WMT_PIN(5, 14)
137#define WMT_PIN_NORA15 WMT_PIN(5, 15)
138#define WMT_PIN_NORA16 WMT_PIN(5, 16)
139#define WMT_PIN_NORA17 WMT_PIN(5, 17)
140#define WMT_PIN_NORA18 WMT_PIN(5, 18)
141#define WMT_PIN_NORA19 WMT_PIN(5, 19)
142#define WMT_PIN_NORA20 WMT_PIN(5, 20)
143#define WMT_PIN_NORA21 WMT_PIN(5, 21)
144#define WMT_PIN_NORA22 WMT_PIN(5, 22)
145#define WMT_PIN_NORA23 WMT_PIN(5, 23)
146#define WMT_PIN_NORA24 WMT_PIN(5, 24)
147#define WMT_PIN_AC97SDI WMT_PIN(6, 0)
148#define WMT_PIN_AC97SYNC WMT_PIN(6, 1)
149#define WMT_PIN_AC97SDO WMT_PIN(6, 2)
150#define WMT_PIN_AC97BCLK WMT_PIN(6, 3)
151#define WMT_PIN_AC97RST WMT_PIN(6, 4)
152#define WMT_PIN_SFDO WMT_PIN(7, 0)
153#define WMT_PIN_SFCS0 WMT_PIN(7, 1)
154#define WMT_PIN_SFCS1 WMT_PIN(7, 2)
155#define WMT_PIN_SFCLK WMT_PIN(7, 3)
156#define WMT_PIN_SFDI WMT_PIN(7, 4)
157#define WMT_PIN_SPI0CLK WMT_PIN(8, 0)
158#define WMT_PIN_SPI0MISO WMT_PIN(8, 1)
159#define WMT_PIN_SPI0MOSI WMT_PIN(8, 2)
160#define WMT_PIN_SPI0SS WMT_PIN(8, 3)
161#define WMT_PIN_SPI1CLK WMT_PIN(8, 4)
162#define WMT_PIN_SPI1MISO WMT_PIN(8, 5)
163#define WMT_PIN_SPI1MOSI WMT_PIN(8, 6)
164#define WMT_PIN_SPI1SS WMT_PIN(8, 7)
165#define WMT_PIN_SPI2CLK WMT_PIN(8, 8)
166#define WMT_PIN_SPI2MISO WMT_PIN(8, 9)
167#define WMT_PIN_SPI2MOSI WMT_PIN(8, 10)
168#define WMT_PIN_SPI2SS WMT_PIN(8, 11)
169#define WMT_PIN_UART0_RTS WMT_PIN(9, 0)
170#define WMT_PIN_UART0_TXD WMT_PIN(9, 1)
171#define WMT_PIN_UART0_CTS WMT_PIN(9, 2)
172#define WMT_PIN_UART0_RXD WMT_PIN(9, 3)
173#define WMT_PIN_UART1_RTS WMT_PIN(9, 4)
174#define WMT_PIN_UART1_TXD WMT_PIN(9, 5)
175#define WMT_PIN_UART1_CTS WMT_PIN(9, 6)
176#define WMT_PIN_UART1_RXD WMT_PIN(9, 7)
177#define WMT_PIN_UART2_RTS WMT_PIN(9, 8)
178#define WMT_PIN_UART2_TXD WMT_PIN(9, 9)
179#define WMT_PIN_UART2_CTS WMT_PIN(9, 10)
180#define WMT_PIN_UART2_RXD WMT_PIN(9, 11)
181#define WMT_PIN_UART3_RTS WMT_PIN(9, 12)
182#define WMT_PIN_UART3_TXD WMT_PIN(9, 13)
183#define WMT_PIN_UART3_CTS WMT_PIN(9, 14)
184#define WMT_PIN_UART3_RXD WMT_PIN(9, 15)
185#define WMT_PIN_I2C0SCL WMT_PIN(10, 0)
186#define WMT_PIN_I2C0SDA WMT_PIN(10, 1)
187#define WMT_PIN_I2C1SCL WMT_PIN(10, 2)
188#define WMT_PIN_I2C1SDA WMT_PIN(10, 3)
189#define WMT_PIN_I2C2SCL WMT_PIN(10, 4)
190#define WMT_PIN_I2C2SDA WMT_PIN(10, 5)
191
192static const struct pinctrl_pin_desc wm8505_pins[] = {
193 PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"),
194 PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"),
195 PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"),
196 PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"),
197 PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"),
198 PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"),
199 PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"),
200 PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"),
201 PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"),
202 PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"),
203 PINCTRL_PIN(WMT_PIN_WAKEUP2, "wakeup2"),
204 PINCTRL_PIN(WMT_PIN_WAKEUP3, "wakeup3"),
205 PINCTRL_PIN(WMT_PIN_SUSGPIO0, "susgpio0"),
206 PINCTRL_PIN(WMT_PIN_SDDATA0, "sd_data0"),
207 PINCTRL_PIN(WMT_PIN_SDDATA1, "sd_data1"),
208 PINCTRL_PIN(WMT_PIN_SDDATA2, "sd_data2"),
209 PINCTRL_PIN(WMT_PIN_SDDATA3, "sd_data3"),
210 PINCTRL_PIN(WMT_PIN_MMCDATA0, "mmc_data0"),
211 PINCTRL_PIN(WMT_PIN_MMCDATA1, "mmc_data1"),
212 PINCTRL_PIN(WMT_PIN_MMCDATA2, "mmc_data2"),
213 PINCTRL_PIN(WMT_PIN_MMCDATA3, "mmc_data3"),
214 PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"),
215 PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"),
216 PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"),
217 PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"),
218 PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"),
219 PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"),
220 PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"),
221 PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"),
222 PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"),
223 PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"),
224 PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"),
225 PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"),
226 PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"),
227 PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"),
228 PINCTRL_PIN(WMT_PIN_VDOUT6, "vdout6"),
229 PINCTRL_PIN(WMT_PIN_VDOUT7, "vdout7"),
230 PINCTRL_PIN(WMT_PIN_VDOUT8, "vdout8"),
231 PINCTRL_PIN(WMT_PIN_VDOUT9, "vdout9"),
232 PINCTRL_PIN(WMT_PIN_VDOUT10, "vdout10"),
233 PINCTRL_PIN(WMT_PIN_VDOUT11, "vdout11"),
234 PINCTRL_PIN(WMT_PIN_VDOUT12, "vdout12"),
235 PINCTRL_PIN(WMT_PIN_VDOUT13, "vdout13"),
236 PINCTRL_PIN(WMT_PIN_VDOUT14, "vdout14"),
237 PINCTRL_PIN(WMT_PIN_VDOUT15, "vdout15"),
238 PINCTRL_PIN(WMT_PIN_VDOUT16, "vdout16"),
239 PINCTRL_PIN(WMT_PIN_VDOUT17, "vdout17"),
240 PINCTRL_PIN(WMT_PIN_VDOUT18, "vdout18"),
241 PINCTRL_PIN(WMT_PIN_VDOUT19, "vdout19"),
242 PINCTRL_PIN(WMT_PIN_VDOUT20, "vdout20"),
243 PINCTRL_PIN(WMT_PIN_VDOUT21, "vdout21"),
244 PINCTRL_PIN(WMT_PIN_VDOUT22, "vdout22"),
245 PINCTRL_PIN(WMT_PIN_VDOUT23, "vdout23"),
246 PINCTRL_PIN(WMT_PIN_VHSYNC, "v_hsync"),
247 PINCTRL_PIN(WMT_PIN_VVSYNC, "v_vsync"),
248 PINCTRL_PIN(WMT_PIN_VGAHSYNC, "vga_hsync"),
249 PINCTRL_PIN(WMT_PIN_VGAVSYNC, "vga_vsync"),
250 PINCTRL_PIN(WMT_PIN_VDHSYNC, "vd_hsync"),
251 PINCTRL_PIN(WMT_PIN_VDVSYNC, "vd_vsync"),
252 PINCTRL_PIN(WMT_PIN_NORD0, "nor_d0"),
253 PINCTRL_PIN(WMT_PIN_NORD1, "nor_d1"),
254 PINCTRL_PIN(WMT_PIN_NORD2, "nor_d2"),
255 PINCTRL_PIN(WMT_PIN_NORD3, "nor_d3"),
256 PINCTRL_PIN(WMT_PIN_NORD4, "nor_d4"),
257 PINCTRL_PIN(WMT_PIN_NORD5, "nor_d5"),
258 PINCTRL_PIN(WMT_PIN_NORD6, "nor_d6"),
259 PINCTRL_PIN(WMT_PIN_NORD7, "nor_d7"),
260 PINCTRL_PIN(WMT_PIN_NORD8, "nor_d8"),
261 PINCTRL_PIN(WMT_PIN_NORD9, "nor_d9"),
262 PINCTRL_PIN(WMT_PIN_NORD10, "nor_d10"),
263 PINCTRL_PIN(WMT_PIN_NORD11, "nor_d11"),
264 PINCTRL_PIN(WMT_PIN_NORD12, "nor_d12"),
265 PINCTRL_PIN(WMT_PIN_NORD13, "nor_d13"),
266 PINCTRL_PIN(WMT_PIN_NORD14, "nor_d14"),
267 PINCTRL_PIN(WMT_PIN_NORD15, "nor_d15"),
268 PINCTRL_PIN(WMT_PIN_NORA0, "nor_a0"),
269 PINCTRL_PIN(WMT_PIN_NORA1, "nor_a1"),
270 PINCTRL_PIN(WMT_PIN_NORA2, "nor_a2"),
271 PINCTRL_PIN(WMT_PIN_NORA3, "nor_a3"),
272 PINCTRL_PIN(WMT_PIN_NORA4, "nor_a4"),
273 PINCTRL_PIN(WMT_PIN_NORA5, "nor_a5"),
274 PINCTRL_PIN(WMT_PIN_NORA6, "nor_a6"),
275 PINCTRL_PIN(WMT_PIN_NORA7, "nor_a7"),
276 PINCTRL_PIN(WMT_PIN_NORA8, "nor_a8"),
277 PINCTRL_PIN(WMT_PIN_NORA9, "nor_a9"),
278 PINCTRL_PIN(WMT_PIN_NORA10, "nor_a10"),
279 PINCTRL_PIN(WMT_PIN_NORA11, "nor_a11"),
280 PINCTRL_PIN(WMT_PIN_NORA12, "nor_a12"),
281 PINCTRL_PIN(WMT_PIN_NORA13, "nor_a13"),
282 PINCTRL_PIN(WMT_PIN_NORA14, "nor_a14"),
283 PINCTRL_PIN(WMT_PIN_NORA15, "nor_a15"),
284 PINCTRL_PIN(WMT_PIN_NORA16, "nor_a16"),
285 PINCTRL_PIN(WMT_PIN_NORA17, "nor_a17"),
286 PINCTRL_PIN(WMT_PIN_NORA18, "nor_a18"),
287 PINCTRL_PIN(WMT_PIN_NORA19, "nor_a19"),
288 PINCTRL_PIN(WMT_PIN_NORA20, "nor_a20"),
289 PINCTRL_PIN(WMT_PIN_NORA21, "nor_a21"),
290 PINCTRL_PIN(WMT_PIN_NORA22, "nor_a22"),
291 PINCTRL_PIN(WMT_PIN_NORA23, "nor_a23"),
292 PINCTRL_PIN(WMT_PIN_NORA24, "nor_a24"),
293 PINCTRL_PIN(WMT_PIN_AC97SDI, "ac97_sdi"),
294 PINCTRL_PIN(WMT_PIN_AC97SYNC, "ac97_sync"),
295 PINCTRL_PIN(WMT_PIN_AC97SDO, "ac97_sdo"),
296 PINCTRL_PIN(WMT_PIN_AC97BCLK, "ac97_bclk"),
297 PINCTRL_PIN(WMT_PIN_AC97RST, "ac97_rst"),
298 PINCTRL_PIN(WMT_PIN_SFDO, "sf_do"),
299 PINCTRL_PIN(WMT_PIN_SFCS0, "sf_cs0"),
300 PINCTRL_PIN(WMT_PIN_SFCS1, "sf_cs1"),
301 PINCTRL_PIN(WMT_PIN_SFCLK, "sf_clk"),
302 PINCTRL_PIN(WMT_PIN_SFDI, "sf_di"),
303 PINCTRL_PIN(WMT_PIN_SPI0CLK, "spi0_clk"),
304 PINCTRL_PIN(WMT_PIN_SPI0MISO, "spi0_miso"),
305 PINCTRL_PIN(WMT_PIN_SPI0MOSI, "spi0_mosi"),
306 PINCTRL_PIN(WMT_PIN_SPI0SS, "spi0_ss"),
307 PINCTRL_PIN(WMT_PIN_SPI1CLK, "spi1_clk"),
308 PINCTRL_PIN(WMT_PIN_SPI1MISO, "spi1_miso"),
309 PINCTRL_PIN(WMT_PIN_SPI1MOSI, "spi1_mosi"),
310 PINCTRL_PIN(WMT_PIN_SPI1SS, "spi1_ss"),
311 PINCTRL_PIN(WMT_PIN_SPI2CLK, "spi2_clk"),
312 PINCTRL_PIN(WMT_PIN_SPI2MISO, "spi2_miso"),
313 PINCTRL_PIN(WMT_PIN_SPI2MOSI, "spi2_mosi"),
314 PINCTRL_PIN(WMT_PIN_SPI2SS, "spi2_ss"),
315 PINCTRL_PIN(WMT_PIN_UART0_RTS, "uart0_rts"),
316 PINCTRL_PIN(WMT_PIN_UART0_TXD, "uart0_txd"),
317 PINCTRL_PIN(WMT_PIN_UART0_CTS, "uart0_cts"),
318 PINCTRL_PIN(WMT_PIN_UART0_RXD, "uart0_rxd"),
319 PINCTRL_PIN(WMT_PIN_UART1_RTS, "uart1_rts"),
320 PINCTRL_PIN(WMT_PIN_UART1_TXD, "uart1_txd"),
321 PINCTRL_PIN(WMT_PIN_UART1_CTS, "uart1_cts"),
322 PINCTRL_PIN(WMT_PIN_UART1_RXD, "uart1_rxd"),
323 PINCTRL_PIN(WMT_PIN_UART2_RTS, "uart2_rts"),
324 PINCTRL_PIN(WMT_PIN_UART2_TXD, "uart2_txd"),
325 PINCTRL_PIN(WMT_PIN_UART2_CTS, "uart2_cts"),
326 PINCTRL_PIN(WMT_PIN_UART2_RXD, "uart2_rxd"),
327 PINCTRL_PIN(WMT_PIN_UART3_RTS, "uart3_rts"),
328 PINCTRL_PIN(WMT_PIN_UART3_TXD, "uart3_txd"),
329 PINCTRL_PIN(WMT_PIN_UART3_CTS, "uart3_cts"),
330 PINCTRL_PIN(WMT_PIN_UART3_RXD, "uart3_rxd"),
331 PINCTRL_PIN(WMT_PIN_I2C0SCL, "i2c0_scl"),
332 PINCTRL_PIN(WMT_PIN_I2C0SDA, "i2c0_sda"),
333 PINCTRL_PIN(WMT_PIN_I2C1SCL, "i2c1_scl"),
334 PINCTRL_PIN(WMT_PIN_I2C1SDA, "i2c1_sda"),
335 PINCTRL_PIN(WMT_PIN_I2C2SCL, "i2c2_scl"),
336 PINCTRL_PIN(WMT_PIN_I2C2SDA, "i2c2_sda"),
337};
338
339/* Order of these names must match the above list */
340static const char * const wm8505_groups[] = {
341 "extgpio0",
342 "extgpio1",
343 "extgpio2",
344 "extgpio3",
345 "extgpio4",
346 "extgpio5",
347 "extgpio6",
348 "extgpio7",
349 "wakeup0",
350 "wakeup1",
351 "wakeup2",
352 "wakeup3",
353 "susgpio0",
354 "sd_data0",
355 "sd_data1",
356 "sd_data2",
357 "sd_data3",
358 "mmc_data0",
359 "mmc_data1",
360 "mmc_data2",
361 "mmc_data3",
362 "vdin0",
363 "vdin1",
364 "vdin2",
365 "vdin3",
366 "vdin4",
367 "vdin5",
368 "vdin6",
369 "vdin7",
370 "vdout0",
371 "vdout1",
372 "vdout2",
373 "vdout3",
374 "vdout4",
375 "vdout5",
376 "vdout6",
377 "vdout7",
378 "vdout8",
379 "vdout9",
380 "vdout10",
381 "vdout11",
382 "vdout12",
383 "vdout13",
384 "vdout14",
385 "vdout15",
386 "vdout16",
387 "vdout17",
388 "vdout18",
389 "vdout19",
390 "vdout20",
391 "vdout21",
392 "vdout22",
393 "vdout23",
394 "v_hsync",
395 "v_vsync",
396 "vga_hsync",
397 "vga_vsync",
398 "vd_hsync",
399 "vd_vsync",
400 "nor_d0",
401 "nor_d1",
402 "nor_d2",
403 "nor_d3",
404 "nor_d4",
405 "nor_d5",
406 "nor_d6",
407 "nor_d7",
408 "nor_d8",
409 "nor_d9",
410 "nor_d10",
411 "nor_d11",
412 "nor_d12",
413 "nor_d13",
414 "nor_d14",
415 "nor_d15",
416 "nor_a0",
417 "nor_a1",
418 "nor_a2",
419 "nor_a3",
420 "nor_a4",
421 "nor_a5",
422 "nor_a6",
423 "nor_a7",
424 "nor_a8",
425 "nor_a9",
426 "nor_a10",
427 "nor_a11",
428 "nor_a12",
429 "nor_a13",
430 "nor_a14",
431 "nor_a15",
432 "nor_a16",
433 "nor_a17",
434 "nor_a18",
435 "nor_a19",
436 "nor_a20",
437 "nor_a21",
438 "nor_a22",
439 "nor_a23",
440 "nor_a24",
441 "ac97_sdi",
442 "ac97_sync",
443 "ac97_sdo",
444 "ac97_bclk",
445 "ac97_rst",
446 "sf_do",
447 "sf_cs0",
448 "sf_cs1",
449 "sf_clk",
450 "sf_di",
451 "spi0_clk",
452 "spi0_miso",
453 "spi0_mosi",
454 "spi0_ss",
455 "spi1_clk",
456 "spi1_miso",
457 "spi1_mosi",
458 "spi1_ss",
459 "spi2_clk",
460 "spi2_miso",
461 "spi2_mosi",
462 "spi2_ss",
463 "uart0_rts",
464 "uart0_txd",
465 "uart0_cts",
466 "uart0_rxd",
467 "uart1_rts",
468 "uart1_txd",
469 "uart1_cts",
470 "uart1_rxd",
471 "uart2_rts",
472 "uart2_txd",
473 "uart2_cts",
474 "uart2_rxd",
475 "uart3_rts",
476 "uart3_txd",
477 "uart3_cts",
478 "uart3_rxd",
479 "i2c0_scl",
480 "i2c0_sda",
481 "i2c1_scl",
482 "i2c1_sda",
483 "i2c2_scl",
484 "i2c2_sda",
485};
486
487static int wm8505_pinctrl_probe(struct platform_device *pdev)
488{
489 struct wmt_pinctrl_data *data;
490
491 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
492 if (!data) {
493 dev_err(&pdev->dev, "failed to allocate data\n");
494 return -ENOMEM;
495 }
496
497 data->banks = wm8505_banks;
498 data->nbanks = ARRAY_SIZE(wm8505_banks);
499 data->pins = wm8505_pins;
500 data->npins = ARRAY_SIZE(wm8505_pins);
501 data->groups = wm8505_groups;
502 data->ngroups = ARRAY_SIZE(wm8505_groups);
503
504 return wmt_pinctrl_probe(pdev, data);
505}
506
507static int wm8505_pinctrl_remove(struct platform_device *pdev)
508{
509 return wmt_pinctrl_remove(pdev);
510}
511
512static struct of_device_id wmt_pinctrl_of_match[] = {
513 { .compatible = "wm,wm8505-pinctrl" },
514 { /* sentinel */ },
515};
516
517static struct platform_driver wmt_pinctrl_driver = {
518 .probe = wm8505_pinctrl_probe,
519 .remove = wm8505_pinctrl_remove,
520 .driver = {
521 .name = "pinctrl-wm8505",
522 .owner = THIS_MODULE,
523 .of_match_table = wmt_pinctrl_of_match,
524 },
525};
526
527module_platform_driver(wmt_pinctrl_driver);
528
529MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
530MODULE_DESCRIPTION("Wondermedia WM8505 Pincontrol driver");
531MODULE_LICENSE("GPL v2");
532MODULE_DEVICE_TABLE(of, wmt_pinctrl_of_match);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8650.c b/drivers/pinctrl/vt8500/pinctrl-wm8650.c
new file mode 100644
index 000000000000..7de57f063153
--- /dev/null
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8650.c
@@ -0,0 +1,370 @@
1/*
2 * Pinctrl data for Wondermedia WM8650 SoC
3 *
4 * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/pinctrl/pinctrl.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21
22#include "pinctrl-wmt.h"
23
24/*
25 * Describe the register offsets within the GPIO memory space
26 * The dedicated external GPIO's should always be listed in bank 0
27 * so they are exported in the 0..31 range which is what users
28 * expect.
29 *
30 * Do not reorder these banks as it will change the pin numbering
31 */
32static const struct wmt_pinctrl_bank_registers wm8650_banks[] = {
33 WMT_PINCTRL_BANK(0x40, 0x80, 0xC0, 0x00, 0x480, 0x4C0), /* 0 */
34 WMT_PINCTRL_BANK(0x44, 0x84, 0xC4, 0x04, 0x484, 0x4C4), /* 1 */
35 WMT_PINCTRL_BANK(0x48, 0x88, 0xC8, 0x08, 0x488, 0x4C8), /* 2 */
36 WMT_PINCTRL_BANK(0x4C, 0x8C, 0xCC, 0x0C, 0x48C, 0x4CC), /* 3 */
37 WMT_PINCTRL_BANK(0x50, 0x90, 0xD0, 0x10, 0x490, 0x4D0), /* 4 */
38 WMT_PINCTRL_BANK(0x54, 0x94, 0xD4, 0x14, 0x494, 0x4D4), /* 5 */
39 WMT_PINCTRL_BANK(0x58, 0x98, 0xD8, 0x18, 0x498, 0x4D8), /* 6 */
40 WMT_PINCTRL_BANK(0x5C, 0x9C, 0xDC, 0x1C, 0x49C, 0x4DC), /* 7 */
41};
42
43/* Please keep sorted by bank/bit */
44#define WMT_PIN_EXTGPIO0 WMT_PIN(0, 0)
45#define WMT_PIN_EXTGPIO1 WMT_PIN(0, 1)
46#define WMT_PIN_EXTGPIO2 WMT_PIN(0, 2)
47#define WMT_PIN_EXTGPIO3 WMT_PIN(0, 3)
48#define WMT_PIN_EXTGPIO4 WMT_PIN(0, 4)
49#define WMT_PIN_EXTGPIO5 WMT_PIN(0, 5)
50#define WMT_PIN_EXTGPIO6 WMT_PIN(0, 6)
51#define WMT_PIN_EXTGPIO7 WMT_PIN(0, 7)
52#define WMT_PIN_WAKEUP0 WMT_PIN(0, 16)
53#define WMT_PIN_WAKEUP1 WMT_PIN(0, 17)
54#define WMT_PIN_SUSGPIO0 WMT_PIN(0, 21)
55#define WMT_PIN_SD0CD WMT_PIN(0, 28)
56#define WMT_PIN_SD1CD WMT_PIN(0, 29)
57#define WMT_PIN_VDOUT0 WMT_PIN(1, 0)
58#define WMT_PIN_VDOUT1 WMT_PIN(1, 1)
59#define WMT_PIN_VDOUT2 WMT_PIN(1, 2)
60#define WMT_PIN_VDOUT3 WMT_PIN(1, 3)
61#define WMT_PIN_VDOUT4 WMT_PIN(1, 4)
62#define WMT_PIN_VDOUT5 WMT_PIN(1, 5)
63#define WMT_PIN_VDOUT6 WMT_PIN(1, 6)
64#define WMT_PIN_VDOUT7 WMT_PIN(1, 7)
65#define WMT_PIN_VDOUT8 WMT_PIN(1, 8)
66#define WMT_PIN_VDOUT9 WMT_PIN(1, 9)
67#define WMT_PIN_VDOUT10 WMT_PIN(1, 10)
68#define WMT_PIN_VDOUT11 WMT_PIN(1, 11)
69#define WMT_PIN_VDOUT12 WMT_PIN(1, 12)
70#define WMT_PIN_VDOUT13 WMT_PIN(1, 13)
71#define WMT_PIN_VDOUT14 WMT_PIN(1, 14)
72#define WMT_PIN_VDOUT15 WMT_PIN(1, 15)
73#define WMT_PIN_VDOUT16 WMT_PIN(1, 16)
74#define WMT_PIN_VDOUT17 WMT_PIN(1, 17)
75#define WMT_PIN_VDOUT18 WMT_PIN(1, 18)
76#define WMT_PIN_VDOUT19 WMT_PIN(1, 19)
77#define WMT_PIN_VDOUT20 WMT_PIN(1, 20)
78#define WMT_PIN_VDOUT21 WMT_PIN(1, 21)
79#define WMT_PIN_VDOUT22 WMT_PIN(1, 22)
80#define WMT_PIN_VDOUT23 WMT_PIN(1, 23)
81#define WMT_PIN_VDIN0 WMT_PIN(2, 0)
82#define WMT_PIN_VDIN1 WMT_PIN(2, 1)
83#define WMT_PIN_VDIN2 WMT_PIN(2, 2)
84#define WMT_PIN_VDIN3 WMT_PIN(2, 3)
85#define WMT_PIN_VDIN4 WMT_PIN(2, 4)
86#define WMT_PIN_VDIN5 WMT_PIN(2, 5)
87#define WMT_PIN_VDIN6 WMT_PIN(2, 6)
88#define WMT_PIN_VDIN7 WMT_PIN(2, 7)
89#define WMT_PIN_I2C1SCL WMT_PIN(2, 12)
90#define WMT_PIN_I2C1SDA WMT_PIN(2, 13)
91#define WMT_PIN_SPI0MOSI WMT_PIN(2, 24)
92#define WMT_PIN_SPI0MISO WMT_PIN(2, 25)
93#define WMT_PIN_SPI0SS0 WMT_PIN(2, 26)
94#define WMT_PIN_SPI0CLK WMT_PIN(2, 27)
95#define WMT_PIN_SD0DATA0 WMT_PIN(3, 8)
96#define WMT_PIN_SD0DATA1 WMT_PIN(3, 9)
97#define WMT_PIN_SD0DATA2 WMT_PIN(3, 10)
98#define WMT_PIN_SD0DATA3 WMT_PIN(3, 11)
99#define WMT_PIN_SD0CLK WMT_PIN(3, 12)
100#define WMT_PIN_SD0WP WMT_PIN(3, 13)
101#define WMT_PIN_SD0CMD WMT_PIN(3, 14)
102#define WMT_PIN_SD1DATA0 WMT_PIN(3, 24)
103#define WMT_PIN_SD1DATA1 WMT_PIN(3, 25)
104#define WMT_PIN_SD1DATA2 WMT_PIN(3, 26)
105#define WMT_PIN_SD1DATA3 WMT_PIN(3, 27)
106#define WMT_PIN_SD1DATA4 WMT_PIN(3, 28)
107#define WMT_PIN_SD1DATA5 WMT_PIN(3, 29)
108#define WMT_PIN_SD1DATA6 WMT_PIN(3, 30)
109#define WMT_PIN_SD1DATA7 WMT_PIN(3, 31)
110#define WMT_PIN_I2C0SCL WMT_PIN(5, 8)
111#define WMT_PIN_I2C0SDA WMT_PIN(5, 9)
112#define WMT_PIN_UART0RTS WMT_PIN(5, 16)
113#define WMT_PIN_UART0TXD WMT_PIN(5, 17)
114#define WMT_PIN_UART0CTS WMT_PIN(5, 18)
115#define WMT_PIN_UART0RXD WMT_PIN(5, 19)
116#define WMT_PIN_UART1RTS WMT_PIN(5, 20)
117#define WMT_PIN_UART1TXD WMT_PIN(5, 21)
118#define WMT_PIN_UART1CTS WMT_PIN(5, 22)
119#define WMT_PIN_UART1RXD WMT_PIN(5, 23)
120#define WMT_PIN_UART2RTS WMT_PIN(5, 24)
121#define WMT_PIN_UART2TXD WMT_PIN(5, 25)
122#define WMT_PIN_UART2CTS WMT_PIN(5, 26)
123#define WMT_PIN_UART2RXD WMT_PIN(5, 27)
124#define WMT_PIN_UART3RTS WMT_PIN(5, 28)
125#define WMT_PIN_UART3TXD WMT_PIN(5, 29)
126#define WMT_PIN_UART3CTS WMT_PIN(5, 30)
127#define WMT_PIN_UART3RXD WMT_PIN(5, 31)
128#define WMT_PIN_KPADROW0 WMT_PIN(6, 16)
129#define WMT_PIN_KPADROW1 WMT_PIN(6, 17)
130#define WMT_PIN_KPADCOL0 WMT_PIN(6, 18)
131#define WMT_PIN_KPADCOL1 WMT_PIN(6, 19)
132#define WMT_PIN_SD1CLK WMT_PIN(7, 0)
133#define WMT_PIN_SD1CMD WMT_PIN(7, 1)
134#define WMT_PIN_SD1WP WMT_PIN(7, 13)
135
136static const struct pinctrl_pin_desc wm8650_pins[] = {
137 PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"),
138 PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"),
139 PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"),
140 PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"),
141 PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"),
142 PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"),
143 PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"),
144 PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"),
145 PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"),
146 PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"),
147 PINCTRL_PIN(WMT_PIN_SUSGPIO0, "susgpio0"),
148 PINCTRL_PIN(WMT_PIN_SD0CD, "sd0_cd"),
149 PINCTRL_PIN(WMT_PIN_SD1CD, "sd1_cd"),
150 PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"),
151 PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"),
152 PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"),
153 PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"),
154 PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"),
155 PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"),
156 PINCTRL_PIN(WMT_PIN_VDOUT6, "vdout6"),
157 PINCTRL_PIN(WMT_PIN_VDOUT7, "vdout7"),
158 PINCTRL_PIN(WMT_PIN_VDOUT8, "vdout8"),
159 PINCTRL_PIN(WMT_PIN_VDOUT9, "vdout9"),
160 PINCTRL_PIN(WMT_PIN_VDOUT10, "vdout10"),
161 PINCTRL_PIN(WMT_PIN_VDOUT11, "vdout11"),
162 PINCTRL_PIN(WMT_PIN_VDOUT12, "vdout12"),
163 PINCTRL_PIN(WMT_PIN_VDOUT13, "vdout13"),
164 PINCTRL_PIN(WMT_PIN_VDOUT14, "vdout14"),
165 PINCTRL_PIN(WMT_PIN_VDOUT15, "vdout15"),
166 PINCTRL_PIN(WMT_PIN_VDOUT16, "vdout16"),
167 PINCTRL_PIN(WMT_PIN_VDOUT17, "vdout17"),
168 PINCTRL_PIN(WMT_PIN_VDOUT18, "vdout18"),
169 PINCTRL_PIN(WMT_PIN_VDOUT19, "vdout19"),
170 PINCTRL_PIN(WMT_PIN_VDOUT20, "vdout20"),
171 PINCTRL_PIN(WMT_PIN_VDOUT21, "vdout21"),
172 PINCTRL_PIN(WMT_PIN_VDOUT22, "vdout22"),
173 PINCTRL_PIN(WMT_PIN_VDOUT23, "vdout23"),
174 PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"),
175 PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"),
176 PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"),
177 PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"),
178 PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"),
179 PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"),
180 PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"),
181 PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"),
182 PINCTRL_PIN(WMT_PIN_I2C1SCL, "i2c1_scl"),
183 PINCTRL_PIN(WMT_PIN_I2C1SDA, "i2c1_sda"),
184 PINCTRL_PIN(WMT_PIN_SPI0MOSI, "spi0_mosi"),
185 PINCTRL_PIN(WMT_PIN_SPI0MISO, "spi0_miso"),
186 PINCTRL_PIN(WMT_PIN_SPI0SS0, "spi0_ss0"),
187 PINCTRL_PIN(WMT_PIN_SPI0CLK, "spi0_clk"),
188 PINCTRL_PIN(WMT_PIN_SD0DATA0, "sd0_data0"),
189 PINCTRL_PIN(WMT_PIN_SD0DATA1, "sd0_data1"),
190 PINCTRL_PIN(WMT_PIN_SD0DATA2, "sd0_data2"),
191 PINCTRL_PIN(WMT_PIN_SD0DATA3, "sd0_data3"),
192 PINCTRL_PIN(WMT_PIN_SD0CLK, "sd0_clk"),
193 PINCTRL_PIN(WMT_PIN_SD0WP, "sd0_wp"),
194 PINCTRL_PIN(WMT_PIN_SD0CMD, "sd0_cmd"),
195 PINCTRL_PIN(WMT_PIN_SD1DATA0, "sd1_data0"),
196 PINCTRL_PIN(WMT_PIN_SD1DATA1, "sd1_data1"),
197 PINCTRL_PIN(WMT_PIN_SD1DATA2, "sd1_data2"),
198 PINCTRL_PIN(WMT_PIN_SD1DATA3, "sd1_data3"),
199 PINCTRL_PIN(WMT_PIN_SD1DATA4, "sd1_data4"),
200 PINCTRL_PIN(WMT_PIN_SD1DATA5, "sd1_data5"),
201 PINCTRL_PIN(WMT_PIN_SD1DATA6, "sd1_data6"),
202 PINCTRL_PIN(WMT_PIN_SD1DATA7, "sd1_data7"),
203 PINCTRL_PIN(WMT_PIN_I2C0SCL, "i2c0_scl"),
204 PINCTRL_PIN(WMT_PIN_I2C0SDA, "i2c0_sda"),
205 PINCTRL_PIN(WMT_PIN_UART0RTS, "uart0_rts"),
206 PINCTRL_PIN(WMT_PIN_UART0TXD, "uart0_txd"),
207 PINCTRL_PIN(WMT_PIN_UART0CTS, "uart0_cts"),
208 PINCTRL_PIN(WMT_PIN_UART0RXD, "uart0_rxd"),
209 PINCTRL_PIN(WMT_PIN_UART1RTS, "uart1_rts"),
210 PINCTRL_PIN(WMT_PIN_UART1TXD, "uart1_txd"),
211 PINCTRL_PIN(WMT_PIN_UART1CTS, "uart1_cts"),
212 PINCTRL_PIN(WMT_PIN_UART1RXD, "uart1_rxd"),
213 PINCTRL_PIN(WMT_PIN_UART2RTS, "uart2_rts"),
214 PINCTRL_PIN(WMT_PIN_UART2TXD, "uart2_txd"),
215 PINCTRL_PIN(WMT_PIN_UART2CTS, "uart2_cts"),
216 PINCTRL_PIN(WMT_PIN_UART2RXD, "uart2_rxd"),
217 PINCTRL_PIN(WMT_PIN_UART3RTS, "uart3_rts"),
218 PINCTRL_PIN(WMT_PIN_UART3TXD, "uart3_txd"),
219 PINCTRL_PIN(WMT_PIN_UART3CTS, "uart3_cts"),
220 PINCTRL_PIN(WMT_PIN_UART3RXD, "uart3_rxd"),
221 PINCTRL_PIN(WMT_PIN_KPADROW0, "kpadrow0"),
222 PINCTRL_PIN(WMT_PIN_KPADROW1, "kpadrow1"),
223 PINCTRL_PIN(WMT_PIN_KPADCOL0, "kpadcol0"),
224 PINCTRL_PIN(WMT_PIN_KPADCOL1, "kpadcol1"),
225 PINCTRL_PIN(WMT_PIN_SD1CLK, "sd1_clk"),
226 PINCTRL_PIN(WMT_PIN_SD1CMD, "sd1_cmd"),
227 PINCTRL_PIN(WMT_PIN_SD1WP, "sd1_wp"),
228};
229
230/* Order of these names must match the above list */
231static const char * const wm8650_groups[] = {
232 "extgpio0",
233 "extgpio1",
234 "extgpio2",
235 "extgpio3",
236 "extgpio4",
237 "extgpio5",
238 "extgpio6",
239 "extgpio7",
240 "wakeup0",
241 "wakeup1",
242 "susgpio0",
243 "sd0_cd",
244 "sd1_cd",
245 "vdout0",
246 "vdout1",
247 "vdout2",
248 "vdout3",
249 "vdout4",
250 "vdout5",
251 "vdout6",
252 "vdout7",
253 "vdout8",
254 "vdout9",
255 "vdout10",
256 "vdout11",
257 "vdout12",
258 "vdout13",
259 "vdout14",
260 "vdout15",
261 "vdout16",
262 "vdout17",
263 "vdout18",
264 "vdout19",
265 "vdout20",
266 "vdout21",
267 "vdout22",
268 "vdout23",
269 "vdin0",
270 "vdin1",
271 "vdin2",
272 "vdin3",
273 "vdin4",
274 "vdin5",
275 "vdin6",
276 "vdin7",
277 "i2c1_scl",
278 "i2c1_sda",
279 "spi0_mosi",
280 "spi0_miso",
281 "spi0_ss0",
282 "spi0_clk",
283 "sd0_data0",
284 "sd0_data1",
285 "sd0_data2",
286 "sd0_data3",
287 "sd0_clk",
288 "sd0_wp",
289 "sd0_cmd",
290 "sd1_data0",
291 "sd1_data1",
292 "sd1_data2",
293 "sd1_data3",
294 "sd1_data4",
295 "sd1_data5",
296 "sd1_data6",
297 "sd1_data7",
298 "i2c0_scl",
299 "i2c0_sda",
300 "uart0_rts",
301 "uart0_txd",
302 "uart0_cts",
303 "uart0_rxd",
304 "uart1_rts",
305 "uart1_txd",
306 "uart1_cts",
307 "uart1_rxd",
308 "uart2_rts",
309 "uart2_txd",
310 "uart2_cts",
311 "uart2_rxd",
312 "uart3_rts",
313 "uart3_txd",
314 "uart3_cts",
315 "uart3_rxd",
316 "kpadrow0",
317 "kpadrow1",
318 "kpadcol0",
319 "kpadcol1",
320 "sd1_clk",
321 "sd1_cmd",
322 "sd1_wp",
323};
324
325static int wm8650_pinctrl_probe(struct platform_device *pdev)
326{
327 struct wmt_pinctrl_data *data;
328
329 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
330 if (!data) {
331 dev_err(&pdev->dev, "failed to allocate data\n");
332 return -ENOMEM;
333 }
334
335 data->banks = wm8650_banks;
336 data->nbanks = ARRAY_SIZE(wm8650_banks);
337 data->pins = wm8650_pins;
338 data->npins = ARRAY_SIZE(wm8650_pins);
339 data->groups = wm8650_groups;
340 data->ngroups = ARRAY_SIZE(wm8650_groups);
341
342 return wmt_pinctrl_probe(pdev, data);
343}
344
345static int wm8650_pinctrl_remove(struct platform_device *pdev)
346{
347 return wmt_pinctrl_remove(pdev);
348}
349
350static struct of_device_id wmt_pinctrl_of_match[] = {
351 { .compatible = "wm,wm8650-pinctrl" },
352 { /* sentinel */ },
353};
354
355static struct platform_driver wmt_pinctrl_driver = {
356 .probe = wm8650_pinctrl_probe,
357 .remove = wm8650_pinctrl_remove,
358 .driver = {
359 .name = "pinctrl-wm8650",
360 .owner = THIS_MODULE,
361 .of_match_table = wmt_pinctrl_of_match,
362 },
363};
364
365module_platform_driver(wmt_pinctrl_driver);
366
367MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
368MODULE_DESCRIPTION("Wondermedia WM8650 Pincontrol driver");
369MODULE_LICENSE("GPL v2");
370MODULE_DEVICE_TABLE(of, wmt_pinctrl_of_match);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8750.c b/drivers/pinctrl/vt8500/pinctrl-wm8750.c
new file mode 100644
index 000000000000..b964cc550568
--- /dev/null
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8750.c
@@ -0,0 +1,409 @@
1/*
2 * Pinctrl data for Wondermedia WM8750 SoC
3 *
4 * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/pinctrl/pinctrl.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21
22#include "pinctrl-wmt.h"
23
24/*
25 * Describe the register offsets within the GPIO memory space
26 * The dedicated external GPIO's should always be listed in bank 0
27 * so they are exported in the 0..31 range which is what users
28 * expect.
29 *
30 * Do not reorder these banks as it will change the pin numbering
31 */
32static const struct wmt_pinctrl_bank_registers wm8750_banks[] = {
33 WMT_PINCTRL_BANK(0x40, 0x80, 0xC0, 0x00, 0x480, 0x4C0), /* 0 */
34 WMT_PINCTRL_BANK(0x44, 0x84, 0xC4, 0x04, 0x484, 0x4C4), /* 1 */
35 WMT_PINCTRL_BANK(0x48, 0x88, 0xC8, 0x08, 0x488, 0x4C8), /* 2 */
36 WMT_PINCTRL_BANK(0x4C, 0x8C, 0xCC, 0x0C, 0x48C, 0x4CC), /* 3 */
37 WMT_PINCTRL_BANK(0x50, 0x90, 0xD0, 0x10, 0x490, 0x4D0), /* 4 */
38 WMT_PINCTRL_BANK(0x54, 0x94, 0xD4, 0x14, 0x494, 0x4D4), /* 5 */
39 WMT_PINCTRL_BANK(0x58, 0x98, 0xD8, 0x18, 0x498, 0x4D8), /* 6 */
40 WMT_PINCTRL_BANK(0x5C, 0x9C, 0xDC, 0x1C, 0x49C, 0x4DC), /* 7 */
41 WMT_PINCTRL_BANK(0x60, 0xA0, 0xE0, 0x20, 0x4A0, 0x4E0), /* 8 */
42 WMT_PINCTRL_BANK(0x70, 0xB0, 0xF0, 0x30, 0x4B0, 0x4F0), /* 9 */
43 WMT_PINCTRL_BANK(0x7C, 0xBC, 0xDC, 0x3C, 0x4BC, 0x4FC), /* 10 */
44};
45
46/* Please keep sorted by bank/bit */
47#define WMT_PIN_EXTGPIO0 WMT_PIN(0, 0)
48#define WMT_PIN_EXTGPIO1 WMT_PIN(0, 1)
49#define WMT_PIN_EXTGPIO2 WMT_PIN(0, 2)
50#define WMT_PIN_EXTGPIO3 WMT_PIN(0, 3)
51#define WMT_PIN_EXTGPIO4 WMT_PIN(0, 4)
52#define WMT_PIN_EXTGPIO5 WMT_PIN(0, 5)
53#define WMT_PIN_EXTGPIO6 WMT_PIN(0, 6)
54#define WMT_PIN_EXTGPIO7 WMT_PIN(0, 7)
55#define WMT_PIN_WAKEUP0 WMT_PIN(0, 16)
56#define WMT_PIN_WAKEUP1 WMT_PIN(0, 16)
57#define WMT_PIN_SD0CD WMT_PIN(0, 28)
58#define WMT_PIN_VDOUT0 WMT_PIN(1, 0)
59#define WMT_PIN_VDOUT1 WMT_PIN(1, 1)
60#define WMT_PIN_VDOUT2 WMT_PIN(1, 2)
61#define WMT_PIN_VDOUT3 WMT_PIN(1, 3)
62#define WMT_PIN_VDOUT4 WMT_PIN(1, 4)
63#define WMT_PIN_VDOUT5 WMT_PIN(1, 5)
64#define WMT_PIN_VDOUT6 WMT_PIN(1, 6)
65#define WMT_PIN_VDOUT7 WMT_PIN(1, 7)
66#define WMT_PIN_VDOUT8 WMT_PIN(1, 8)
67#define WMT_PIN_VDOUT9 WMT_PIN(1, 9)
68#define WMT_PIN_VDOUT10 WMT_PIN(1, 10)
69#define WMT_PIN_VDOUT11 WMT_PIN(1, 11)
70#define WMT_PIN_VDOUT12 WMT_PIN(1, 12)
71#define WMT_PIN_VDOUT13 WMT_PIN(1, 13)
72#define WMT_PIN_VDOUT14 WMT_PIN(1, 14)
73#define WMT_PIN_VDOUT15 WMT_PIN(1, 15)
74#define WMT_PIN_VDOUT16 WMT_PIN(1, 16)
75#define WMT_PIN_VDOUT17 WMT_PIN(1, 17)
76#define WMT_PIN_VDOUT18 WMT_PIN(1, 18)
77#define WMT_PIN_VDOUT19 WMT_PIN(1, 19)
78#define WMT_PIN_VDOUT20 WMT_PIN(1, 20)
79#define WMT_PIN_VDOUT21 WMT_PIN(1, 21)
80#define WMT_PIN_VDOUT22 WMT_PIN(1, 22)
81#define WMT_PIN_VDOUT23 WMT_PIN(1, 23)
82#define WMT_PIN_VDIN0 WMT_PIN(2, 0)
83#define WMT_PIN_VDIN1 WMT_PIN(2, 1)
84#define WMT_PIN_VDIN2 WMT_PIN(2, 2)
85#define WMT_PIN_VDIN3 WMT_PIN(2, 3)
86#define WMT_PIN_VDIN4 WMT_PIN(2, 4)
87#define WMT_PIN_VDIN5 WMT_PIN(2, 5)
88#define WMT_PIN_VDIN6 WMT_PIN(2, 6)
89#define WMT_PIN_VDIN7 WMT_PIN(2, 7)
90#define WMT_PIN_SPI0_MOSI WMT_PIN(2, 24)
91#define WMT_PIN_SPI0_MISO WMT_PIN(2, 25)
92#define WMT_PIN_SPI0_SS WMT_PIN(2, 26)
93#define WMT_PIN_SPI0_CLK WMT_PIN(2, 27)
94#define WMT_PIN_SPI0_SSB WMT_PIN(2, 28)
95#define WMT_PIN_SD0CLK WMT_PIN(3, 17)
96#define WMT_PIN_SD0CMD WMT_PIN(3, 18)
97#define WMT_PIN_SD0WP WMT_PIN(3, 19)
98#define WMT_PIN_SD0DATA0 WMT_PIN(3, 20)
99#define WMT_PIN_SD0DATA1 WMT_PIN(3, 21)
100#define WMT_PIN_SD0DATA2 WMT_PIN(3, 22)
101#define WMT_PIN_SD0DATA3 WMT_PIN(3, 23)
102#define WMT_PIN_SD1DATA0 WMT_PIN(3, 24)
103#define WMT_PIN_SD1DATA1 WMT_PIN(3, 25)
104#define WMT_PIN_SD1DATA2 WMT_PIN(3, 26)
105#define WMT_PIN_SD1DATA3 WMT_PIN(3, 27)
106#define WMT_PIN_SD1DATA4 WMT_PIN(3, 28)
107#define WMT_PIN_SD1DATA5 WMT_PIN(3, 29)
108#define WMT_PIN_SD1DATA6 WMT_PIN(3, 30)
109#define WMT_PIN_SD1DATA7 WMT_PIN(3, 31)
110#define WMT_PIN_I2C0_SCL WMT_PIN(5, 8)
111#define WMT_PIN_I2C0_SDA WMT_PIN(5, 9)
112#define WMT_PIN_I2C1_SCL WMT_PIN(5, 10)
113#define WMT_PIN_I2C1_SDA WMT_PIN(5, 11)
114#define WMT_PIN_I2C2_SCL WMT_PIN(5, 12)
115#define WMT_PIN_I2C2_SDA WMT_PIN(5, 13)
116#define WMT_PIN_UART0_RTS WMT_PIN(5, 16)
117#define WMT_PIN_UART0_TXD WMT_PIN(5, 17)
118#define WMT_PIN_UART0_CTS WMT_PIN(5, 18)
119#define WMT_PIN_UART0_RXD WMT_PIN(5, 19)
120#define WMT_PIN_UART1_RTS WMT_PIN(5, 20)
121#define WMT_PIN_UART1_TXD WMT_PIN(5, 21)
122#define WMT_PIN_UART1_CTS WMT_PIN(5, 22)
123#define WMT_PIN_UART1_RXD WMT_PIN(5, 23)
124#define WMT_PIN_UART2_RTS WMT_PIN(5, 24)
125#define WMT_PIN_UART2_TXD WMT_PIN(5, 25)
126#define WMT_PIN_UART2_CTS WMT_PIN(5, 26)
127#define WMT_PIN_UART2_RXD WMT_PIN(5, 27)
128#define WMT_PIN_UART3_RTS WMT_PIN(5, 28)
129#define WMT_PIN_UART3_TXD WMT_PIN(5, 29)
130#define WMT_PIN_UART3_CTS WMT_PIN(5, 30)
131#define WMT_PIN_UART3_RXD WMT_PIN(5, 31)
132#define WMT_PIN_SD2CD WMT_PIN(6, 0)
133#define WMT_PIN_SD2DATA3 WMT_PIN(6, 1)
134#define WMT_PIN_SD2DATA0 WMT_PIN(6, 2)
135#define WMT_PIN_SD2WP WMT_PIN(6, 3)
136#define WMT_PIN_SD2DATA1 WMT_PIN(6, 4)
137#define WMT_PIN_SD2DATA2 WMT_PIN(6, 5)
138#define WMT_PIN_SD2CMD WMT_PIN(6, 6)
139#define WMT_PIN_SD2CLK WMT_PIN(6, 7)
140#define WMT_PIN_SD2PWR WMT_PIN(6, 9)
141#define WMT_PIN_SD1CLK WMT_PIN(7, 0)
142#define WMT_PIN_SD1CMD WMT_PIN(7, 1)
143#define WMT_PIN_SD1PWR WMT_PIN(7, 10)
144#define WMT_PIN_SD1WP WMT_PIN(7, 11)
145#define WMT_PIN_SD1CD WMT_PIN(7, 12)
146#define WMT_PIN_SPI0SS3 WMT_PIN(7, 24)
147#define WMT_PIN_SPI0SS2 WMT_PIN(7, 25)
148#define WMT_PIN_PWMOUT1 WMT_PIN(7, 26)
149#define WMT_PIN_PWMOUT0 WMT_PIN(7, 27)
150
151static const struct pinctrl_pin_desc wm8750_pins[] = {
152 PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"),
153 PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"),
154 PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"),
155 PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"),
156 PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"),
157 PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"),
158 PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"),
159 PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"),
160 PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"),
161 PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"),
162 PINCTRL_PIN(WMT_PIN_SD0CD, "sd0_cd"),
163 PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"),
164 PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"),
165 PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"),
166 PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"),
167 PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"),
168 PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"),
169 PINCTRL_PIN(WMT_PIN_VDOUT6, "vdout6"),
170 PINCTRL_PIN(WMT_PIN_VDOUT7, "vdout7"),
171 PINCTRL_PIN(WMT_PIN_VDOUT8, "vdout8"),
172 PINCTRL_PIN(WMT_PIN_VDOUT9, "vdout9"),
173 PINCTRL_PIN(WMT_PIN_VDOUT10, "vdout10"),
174 PINCTRL_PIN(WMT_PIN_VDOUT11, "vdout11"),
175 PINCTRL_PIN(WMT_PIN_VDOUT12, "vdout12"),
176 PINCTRL_PIN(WMT_PIN_VDOUT13, "vdout13"),
177 PINCTRL_PIN(WMT_PIN_VDOUT14, "vdout14"),
178 PINCTRL_PIN(WMT_PIN_VDOUT15, "vdout15"),
179 PINCTRL_PIN(WMT_PIN_VDOUT16, "vdout16"),
180 PINCTRL_PIN(WMT_PIN_VDOUT17, "vdout17"),
181 PINCTRL_PIN(WMT_PIN_VDOUT18, "vdout18"),
182 PINCTRL_PIN(WMT_PIN_VDOUT19, "vdout19"),
183 PINCTRL_PIN(WMT_PIN_VDOUT20, "vdout20"),
184 PINCTRL_PIN(WMT_PIN_VDOUT21, "vdout21"),
185 PINCTRL_PIN(WMT_PIN_VDOUT22, "vdout22"),
186 PINCTRL_PIN(WMT_PIN_VDOUT23, "vdout23"),
187 PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"),
188 PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"),
189 PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"),
190 PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"),
191 PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"),
192 PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"),
193 PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"),
194 PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"),
195 PINCTRL_PIN(WMT_PIN_SPI0_MOSI, "spi0_mosi"),
196 PINCTRL_PIN(WMT_PIN_SPI0_MISO, "spi0_miso"),
197 PINCTRL_PIN(WMT_PIN_SPI0_SS, "spi0_ss"),
198 PINCTRL_PIN(WMT_PIN_SPI0_CLK, "spi0_clk"),
199 PINCTRL_PIN(WMT_PIN_SPI0_SSB, "spi0_ssb"),
200 PINCTRL_PIN(WMT_PIN_SD0CLK, "sd0_clk"),
201 PINCTRL_PIN(WMT_PIN_SD0CMD, "sd0_cmd"),
202 PINCTRL_PIN(WMT_PIN_SD0WP, "sd0_wp"),
203 PINCTRL_PIN(WMT_PIN_SD0DATA0, "sd0_data0"),
204 PINCTRL_PIN(WMT_PIN_SD0DATA1, "sd0_data1"),
205 PINCTRL_PIN(WMT_PIN_SD0DATA2, "sd0_data2"),
206 PINCTRL_PIN(WMT_PIN_SD0DATA3, "sd0_data3"),
207 PINCTRL_PIN(WMT_PIN_SD1DATA0, "sd1_data0"),
208 PINCTRL_PIN(WMT_PIN_SD1DATA1, "sd1_data1"),
209 PINCTRL_PIN(WMT_PIN_SD1DATA2, "sd1_data2"),
210 PINCTRL_PIN(WMT_PIN_SD1DATA3, "sd1_data3"),
211 PINCTRL_PIN(WMT_PIN_SD1DATA4, "sd1_data4"),
212 PINCTRL_PIN(WMT_PIN_SD1DATA5, "sd1_data5"),
213 PINCTRL_PIN(WMT_PIN_SD1DATA6, "sd1_data6"),
214 PINCTRL_PIN(WMT_PIN_SD1DATA7, "sd1_data7"),
215 PINCTRL_PIN(WMT_PIN_I2C0_SCL, "i2c0_scl"),
216 PINCTRL_PIN(WMT_PIN_I2C0_SDA, "i2c0_sda"),
217 PINCTRL_PIN(WMT_PIN_I2C1_SCL, "i2c1_scl"),
218 PINCTRL_PIN(WMT_PIN_I2C1_SDA, "i2c1_sda"),
219 PINCTRL_PIN(WMT_PIN_I2C2_SCL, "i2c2_scl"),
220 PINCTRL_PIN(WMT_PIN_I2C2_SDA, "i2c2_sda"),
221 PINCTRL_PIN(WMT_PIN_UART0_RTS, "uart0_rts"),
222 PINCTRL_PIN(WMT_PIN_UART0_TXD, "uart0_txd"),
223 PINCTRL_PIN(WMT_PIN_UART0_CTS, "uart0_cts"),
224 PINCTRL_PIN(WMT_PIN_UART0_RXD, "uart0_rxd"),
225 PINCTRL_PIN(WMT_PIN_UART1_RTS, "uart1_rts"),
226 PINCTRL_PIN(WMT_PIN_UART1_TXD, "uart1_txd"),
227 PINCTRL_PIN(WMT_PIN_UART1_CTS, "uart1_cts"),
228 PINCTRL_PIN(WMT_PIN_UART1_RXD, "uart1_rxd"),
229 PINCTRL_PIN(WMT_PIN_UART2_RTS, "uart2_rts"),
230 PINCTRL_PIN(WMT_PIN_UART2_TXD, "uart2_txd"),
231 PINCTRL_PIN(WMT_PIN_UART2_CTS, "uart2_cts"),
232 PINCTRL_PIN(WMT_PIN_UART2_RXD, "uart2_rxd"),
233 PINCTRL_PIN(WMT_PIN_UART3_RTS, "uart3_rts"),
234 PINCTRL_PIN(WMT_PIN_UART3_TXD, "uart3_txd"),
235 PINCTRL_PIN(WMT_PIN_UART3_CTS, "uart3_cts"),
236 PINCTRL_PIN(WMT_PIN_UART3_RXD, "uart3_rxd"),
237 PINCTRL_PIN(WMT_PIN_SD2CD, "sd2_cd"),
238 PINCTRL_PIN(WMT_PIN_SD2DATA3, "sd2_data3"),
239 PINCTRL_PIN(WMT_PIN_SD2DATA0, "sd2_data0"),
240 PINCTRL_PIN(WMT_PIN_SD2WP, "sd2_wp"),
241 PINCTRL_PIN(WMT_PIN_SD2DATA1, "sd2_data1"),
242 PINCTRL_PIN(WMT_PIN_SD2DATA2, "sd2_data2"),
243 PINCTRL_PIN(WMT_PIN_SD2CMD, "sd2_cmd"),
244 PINCTRL_PIN(WMT_PIN_SD2CLK, "sd2_clk"),
245 PINCTRL_PIN(WMT_PIN_SD2PWR, "sd2_pwr"),
246 PINCTRL_PIN(WMT_PIN_SD1CLK, "sd1_clk"),
247 PINCTRL_PIN(WMT_PIN_SD1CMD, "sd1_cmd"),
248 PINCTRL_PIN(WMT_PIN_SD1PWR, "sd1_pwr"),
249 PINCTRL_PIN(WMT_PIN_SD1WP, "sd1_wp"),
250 PINCTRL_PIN(WMT_PIN_SD1CD, "sd1_cd"),
251 PINCTRL_PIN(WMT_PIN_SPI0SS3, "spi0_ss3"),
252 PINCTRL_PIN(WMT_PIN_SPI0SS2, "spi0_ss2"),
253 PINCTRL_PIN(WMT_PIN_PWMOUT1, "pwmout1"),
254 PINCTRL_PIN(WMT_PIN_PWMOUT0, "pwmout0"),
255};
256
257/* Order of these names must match the above list */
258static const char * const wm8750_groups[] = {
259 "extgpio0",
260 "extgpio1",
261 "extgpio2",
262 "extgpio3",
263 "extgpio4",
264 "extgpio5",
265 "extgpio6",
266 "extgpio7",
267 "wakeup0",
268 "wakeup1",
269 "sd0_cd",
270 "vdout0",
271 "vdout1",
272 "vdout2",
273 "vdout3",
274 "vdout4",
275 "vdout5",
276 "vdout6",
277 "vdout7",
278 "vdout8",
279 "vdout9",
280 "vdout10",
281 "vdout11",
282 "vdout12",
283 "vdout13",
284 "vdout14",
285 "vdout15",
286 "vdout16",
287 "vdout17",
288 "vdout18",
289 "vdout19",
290 "vdout20",
291 "vdout21",
292 "vdout22",
293 "vdout23",
294 "vdin0",
295 "vdin1",
296 "vdin2",
297 "vdin3",
298 "vdin4",
299 "vdin5",
300 "vdin6",
301 "vdin7",
302 "spi0_mosi",
303 "spi0_miso",
304 "spi0_ss",
305 "spi0_clk",
306 "spi0_ssb",
307 "sd0_clk",
308 "sd0_cmd",
309 "sd0_wp",
310 "sd0_data0",
311 "sd0_data1",
312 "sd0_data2",
313 "sd0_data3",
314 "sd1_data0",
315 "sd1_data1",
316 "sd1_data2",
317 "sd1_data3",
318 "sd1_data4",
319 "sd1_data5",
320 "sd1_data6",
321 "sd1_data7",
322 "i2c0_scl",
323 "i2c0_sda",
324 "i2c1_scl",
325 "i2c1_sda",
326 "i2c2_scl",
327 "i2c2_sda",
328 "uart0_rts",
329 "uart0_txd",
330 "uart0_cts",
331 "uart0_rxd",
332 "uart1_rts",
333 "uart1_txd",
334 "uart1_cts",
335 "uart1_rxd",
336 "uart2_rts",
337 "uart2_txd",
338 "uart2_cts",
339 "uart2_rxd",
340 "uart3_rts",
341 "uart3_txd",
342 "uart3_cts",
343 "uart3_rxd",
344 "sd2_cd",
345 "sd2_data3",
346 "sd2_data0",
347 "sd2_wp",
348 "sd2_data1",
349 "sd2_data2",
350 "sd2_cmd",
351 "sd2_clk",
352 "sd2_pwr",
353 "sd1_clk",
354 "sd1_cmd",
355 "sd1_pwr",
356 "sd1_wp",
357 "sd1_cd",
358 "spi0_ss3",
359 "spi0_ss2",
360 "pwmout1",
361 "pwmout0",
362};
363
364static int wm8750_pinctrl_probe(struct platform_device *pdev)
365{
366 struct wmt_pinctrl_data *data;
367
368 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
369 if (!data) {
370 dev_err(&pdev->dev, "failed to allocate data\n");
371 return -ENOMEM;
372 }
373
374 data->banks = wm8750_banks;
375 data->nbanks = ARRAY_SIZE(wm8750_banks);
376 data->pins = wm8750_pins;
377 data->npins = ARRAY_SIZE(wm8750_pins);
378 data->groups = wm8750_groups;
379 data->ngroups = ARRAY_SIZE(wm8750_groups);
380
381 return wmt_pinctrl_probe(pdev, data);
382}
383
384static int wm8750_pinctrl_remove(struct platform_device *pdev)
385{
386 return wmt_pinctrl_remove(pdev);
387}
388
389static struct of_device_id wmt_pinctrl_of_match[] = {
390 { .compatible = "wm,wm8750-pinctrl" },
391 { /* sentinel */ },
392};
393
394static struct platform_driver wmt_pinctrl_driver = {
395 .probe = wm8750_pinctrl_probe,
396 .remove = wm8750_pinctrl_remove,
397 .driver = {
398 .name = "pinctrl-wm8750",
399 .owner = THIS_MODULE,
400 .of_match_table = wmt_pinctrl_of_match,
401 },
402};
403
404module_platform_driver(wmt_pinctrl_driver);
405
406MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
407MODULE_DESCRIPTION("Wondermedia WM8750 Pincontrol driver");
408MODULE_LICENSE("GPL v2");
409MODULE_DEVICE_TABLE(of, wmt_pinctrl_of_match);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8850.c b/drivers/pinctrl/vt8500/pinctrl-wm8850.c
new file mode 100644
index 000000000000..ecadce9c91d5
--- /dev/null
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8850.c
@@ -0,0 +1,388 @@
1/*
2 * Pinctrl data for Wondermedia WM8850 SoC
3 *
4 * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/pinctrl/pinctrl.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21
22#include "pinctrl-wmt.h"
23
24/*
25 * Describe the register offsets within the GPIO memory space
26 * The dedicated external GPIO's should always be listed in bank 0
27 * so they are exported in the 0..31 range which is what users
28 * expect.
29 *
30 * Do not reorder these banks as it will change the pin numbering
31 */
32static const struct wmt_pinctrl_bank_registers wm8850_banks[] = {
33 WMT_PINCTRL_BANK(0x40, 0x80, 0xC0, 0x00, 0x480, 0x4C0), /* 0 */
34 WMT_PINCTRL_BANK(0x44, 0x84, 0xC4, 0x04, 0x484, 0x4C4), /* 1 */
35 WMT_PINCTRL_BANK(0x48, 0x88, 0xC8, 0x08, 0x488, 0x4C8), /* 2 */
36 WMT_PINCTRL_BANK(0x4C, 0x8C, 0xCC, 0x0C, 0x48C, 0x4CC), /* 3 */
37 WMT_PINCTRL_BANK(0x50, 0x90, 0xD0, 0x10, 0x490, 0x4D0), /* 4 */
38 WMT_PINCTRL_BANK(0x54, 0x94, 0xD4, 0x14, 0x494, 0x4D4), /* 5 */
39 WMT_PINCTRL_BANK(0x58, 0x98, 0xD8, 0x18, 0x498, 0x4D8), /* 6 */
40 WMT_PINCTRL_BANK(0x5C, 0x9C, 0xDC, 0x1C, 0x49C, 0x4DC), /* 7 */
41 WMT_PINCTRL_BANK(0x60, 0xA0, 0xE0, 0x20, 0x4A0, 0x4E0), /* 8 */
42 WMT_PINCTRL_BANK(0x70, 0xB0, 0xF0, 0x30, 0x4B0, 0x4F0), /* 9 */
43 WMT_PINCTRL_BANK(0x7C, 0xBC, 0xDC, 0x3C, 0x4BC, 0x4FC), /* 10 */
44};
45
46/* Please keep sorted by bank/bit */
47#define WMT_PIN_EXTGPIO0 WMT_PIN(0, 0)
48#define WMT_PIN_EXTGPIO1 WMT_PIN(0, 1)
49#define WMT_PIN_EXTGPIO2 WMT_PIN(0, 2)
50#define WMT_PIN_EXTGPIO3 WMT_PIN(0, 3)
51#define WMT_PIN_EXTGPIO4 WMT_PIN(0, 4)
52#define WMT_PIN_EXTGPIO5 WMT_PIN(0, 5)
53#define WMT_PIN_EXTGPIO6 WMT_PIN(0, 6)
54#define WMT_PIN_EXTGPIO7 WMT_PIN(0, 7)
55#define WMT_PIN_WAKEUP0 WMT_PIN(0, 16)
56#define WMT_PIN_WAKEUP1 WMT_PIN(0, 17)
57#define WMT_PIN_WAKEUP2 WMT_PIN(0, 18)
58#define WMT_PIN_WAKEUP3 WMT_PIN(0, 19)
59#define WMT_PIN_SUSGPIO0 WMT_PIN(0, 21)
60#define WMT_PIN_SUSGPIO1 WMT_PIN(0, 22)
61#define WMT_PIN_SD0CD WMT_PIN(0, 28)
62#define WMT_PIN_VDOUT0 WMT_PIN(1, 0)
63#define WMT_PIN_VDOUT1 WMT_PIN(1, 1)
64#define WMT_PIN_VDOUT2 WMT_PIN(1, 2)
65#define WMT_PIN_VDOUT3 WMT_PIN(1, 3)
66#define WMT_PIN_VDOUT4 WMT_PIN(1, 4)
67#define WMT_PIN_VDOUT5 WMT_PIN(1, 5)
68#define WMT_PIN_VDOUT6 WMT_PIN(1, 6)
69#define WMT_PIN_VDOUT7 WMT_PIN(1, 7)
70#define WMT_PIN_VDOUT8 WMT_PIN(1, 8)
71#define WMT_PIN_VDOUT9 WMT_PIN(1, 9)
72#define WMT_PIN_VDOUT10 WMT_PIN(1, 10)
73#define WMT_PIN_VDOUT11 WMT_PIN(1, 11)
74#define WMT_PIN_VDOUT12 WMT_PIN(1, 12)
75#define WMT_PIN_VDOUT13 WMT_PIN(1, 13)
76#define WMT_PIN_VDOUT14 WMT_PIN(1, 14)
77#define WMT_PIN_VDOUT15 WMT_PIN(1, 15)
78#define WMT_PIN_VDOUT16 WMT_PIN(1, 16)
79#define WMT_PIN_VDOUT17 WMT_PIN(1, 17)
80#define WMT_PIN_VDOUT18 WMT_PIN(1, 18)
81#define WMT_PIN_VDOUT19 WMT_PIN(1, 19)
82#define WMT_PIN_VDOUT20 WMT_PIN(1, 20)
83#define WMT_PIN_VDOUT21 WMT_PIN(1, 21)
84#define WMT_PIN_VDOUT22 WMT_PIN(1, 22)
85#define WMT_PIN_VDOUT23 WMT_PIN(1, 23)
86#define WMT_PIN_VDIN0 WMT_PIN(2, 0)
87#define WMT_PIN_VDIN1 WMT_PIN(2, 1)
88#define WMT_PIN_VDIN2 WMT_PIN(2, 2)
89#define WMT_PIN_VDIN3 WMT_PIN(2, 3)
90#define WMT_PIN_VDIN4 WMT_PIN(2, 4)
91#define WMT_PIN_VDIN5 WMT_PIN(2, 5)
92#define WMT_PIN_VDIN6 WMT_PIN(2, 6)
93#define WMT_PIN_VDIN7 WMT_PIN(2, 7)
94#define WMT_PIN_SPI0_MOSI WMT_PIN(2, 24)
95#define WMT_PIN_SPI0_MISO WMT_PIN(2, 25)
96#define WMT_PIN_SPI0_SS WMT_PIN(2, 26)
97#define WMT_PIN_SPI0_CLK WMT_PIN(2, 27)
98#define WMT_PIN_SPI0_SSB WMT_PIN(2, 28)
99#define WMT_PIN_SD0CLK WMT_PIN(3, 17)
100#define WMT_PIN_SD0CMD WMT_PIN(3, 18)
101#define WMT_PIN_SD0WP WMT_PIN(3, 19)
102#define WMT_PIN_SD0DATA0 WMT_PIN(3, 20)
103#define WMT_PIN_SD0DATA1 WMT_PIN(3, 21)
104#define WMT_PIN_SD0DATA2 WMT_PIN(3, 22)
105#define WMT_PIN_SD0DATA3 WMT_PIN(3, 23)
106#define WMT_PIN_SD1DATA0 WMT_PIN(3, 24)
107#define WMT_PIN_SD1DATA1 WMT_PIN(3, 25)
108#define WMT_PIN_SD1DATA2 WMT_PIN(3, 26)
109#define WMT_PIN_SD1DATA3 WMT_PIN(3, 27)
110#define WMT_PIN_SD1DATA4 WMT_PIN(3, 28)
111#define WMT_PIN_SD1DATA5 WMT_PIN(3, 29)
112#define WMT_PIN_SD1DATA6 WMT_PIN(3, 30)
113#define WMT_PIN_SD1DATA7 WMT_PIN(3, 31)
114#define WMT_PIN_I2C0_SCL WMT_PIN(5, 8)
115#define WMT_PIN_I2C0_SDA WMT_PIN(5, 9)
116#define WMT_PIN_I2C1_SCL WMT_PIN(5, 10)
117#define WMT_PIN_I2C1_SDA WMT_PIN(5, 11)
118#define WMT_PIN_I2C2_SCL WMT_PIN(5, 12)
119#define WMT_PIN_I2C2_SDA WMT_PIN(5, 13)
120#define WMT_PIN_UART0_RTS WMT_PIN(5, 16)
121#define WMT_PIN_UART0_TXD WMT_PIN(5, 17)
122#define WMT_PIN_UART0_CTS WMT_PIN(5, 18)
123#define WMT_PIN_UART0_RXD WMT_PIN(5, 19)
124#define WMT_PIN_UART1_RTS WMT_PIN(5, 20)
125#define WMT_PIN_UART1_TXD WMT_PIN(5, 21)
126#define WMT_PIN_UART1_CTS WMT_PIN(5, 22)
127#define WMT_PIN_UART1_RXD WMT_PIN(5, 23)
128#define WMT_PIN_UART2_RTS WMT_PIN(5, 24)
129#define WMT_PIN_UART2_TXD WMT_PIN(5, 25)
130#define WMT_PIN_UART2_CTS WMT_PIN(5, 26)
131#define WMT_PIN_UART2_RXD WMT_PIN(5, 27)
132#define WMT_PIN_SD2WP WMT_PIN(6, 3)
133#define WMT_PIN_SD2CMD WMT_PIN(6, 6)
134#define WMT_PIN_SD2CLK WMT_PIN(6, 7)
135#define WMT_PIN_SD2PWR WMT_PIN(6, 9)
136#define WMT_PIN_SD1CLK WMT_PIN(7, 0)
137#define WMT_PIN_SD1CMD WMT_PIN(7, 1)
138#define WMT_PIN_SD1PWR WMT_PIN(7, 10)
139#define WMT_PIN_SD1WP WMT_PIN(7, 11)
140#define WMT_PIN_SD1CD WMT_PIN(7, 12)
141#define WMT_PIN_PWMOUT1 WMT_PIN(7, 26)
142#define WMT_PIN_PWMOUT0 WMT_PIN(7, 27)
143
144static const struct pinctrl_pin_desc wm8850_pins[] = {
145 PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"),
146 PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"),
147 PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"),
148 PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"),
149 PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"),
150 PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"),
151 PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"),
152 PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"),
153 PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"),
154 PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"),
155 PINCTRL_PIN(WMT_PIN_WAKEUP2, "wakeup2"),
156 PINCTRL_PIN(WMT_PIN_WAKEUP3, "wakeup3"),
157 PINCTRL_PIN(WMT_PIN_SUSGPIO0, "susgpio0"),
158 PINCTRL_PIN(WMT_PIN_SUSGPIO1, "susgpio1"),
159 PINCTRL_PIN(WMT_PIN_SD0CD, "sd0_cd"),
160 PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"),
161 PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"),
162 PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"),
163 PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"),
164 PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"),
165 PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"),
166 PINCTRL_PIN(WMT_PIN_VDOUT6, "vdout6"),
167 PINCTRL_PIN(WMT_PIN_VDOUT7, "vdout7"),
168 PINCTRL_PIN(WMT_PIN_VDOUT8, "vdout8"),
169 PINCTRL_PIN(WMT_PIN_VDOUT9, "vdout9"),
170 PINCTRL_PIN(WMT_PIN_VDOUT10, "vdout10"),
171 PINCTRL_PIN(WMT_PIN_VDOUT11, "vdout11"),
172 PINCTRL_PIN(WMT_PIN_VDOUT12, "vdout12"),
173 PINCTRL_PIN(WMT_PIN_VDOUT13, "vdout13"),
174 PINCTRL_PIN(WMT_PIN_VDOUT14, "vdout14"),
175 PINCTRL_PIN(WMT_PIN_VDOUT15, "vdout15"),
176 PINCTRL_PIN(WMT_PIN_VDOUT16, "vdout16"),
177 PINCTRL_PIN(WMT_PIN_VDOUT17, "vdout17"),
178 PINCTRL_PIN(WMT_PIN_VDOUT18, "vdout18"),
179 PINCTRL_PIN(WMT_PIN_VDOUT19, "vdout19"),
180 PINCTRL_PIN(WMT_PIN_VDOUT20, "vdout20"),
181 PINCTRL_PIN(WMT_PIN_VDOUT21, "vdout21"),
182 PINCTRL_PIN(WMT_PIN_VDOUT22, "vdout22"),
183 PINCTRL_PIN(WMT_PIN_VDOUT23, "vdout23"),
184 PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"),
185 PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"),
186 PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"),
187 PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"),
188 PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"),
189 PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"),
190 PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"),
191 PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"),
192 PINCTRL_PIN(WMT_PIN_SPI0_MOSI, "spi0_mosi"),
193 PINCTRL_PIN(WMT_PIN_SPI0_MISO, "spi0_miso"),
194 PINCTRL_PIN(WMT_PIN_SPI0_SS, "spi0_ss"),
195 PINCTRL_PIN(WMT_PIN_SPI0_CLK, "spi0_clk"),
196 PINCTRL_PIN(WMT_PIN_SPI0_SSB, "spi0_ssb"),
197 PINCTRL_PIN(WMT_PIN_SD0CLK, "sd0_clk"),
198 PINCTRL_PIN(WMT_PIN_SD0CMD, "sd0_cmd"),
199 PINCTRL_PIN(WMT_PIN_SD0WP, "sd0_wp"),
200 PINCTRL_PIN(WMT_PIN_SD0DATA0, "sd0_data0"),
201 PINCTRL_PIN(WMT_PIN_SD0DATA1, "sd0_data1"),
202 PINCTRL_PIN(WMT_PIN_SD0DATA2, "sd0_data2"),
203 PINCTRL_PIN(WMT_PIN_SD0DATA3, "sd0_data3"),
204 PINCTRL_PIN(WMT_PIN_SD1DATA0, "sd1_data0"),
205 PINCTRL_PIN(WMT_PIN_SD1DATA1, "sd1_data1"),
206 PINCTRL_PIN(WMT_PIN_SD1DATA2, "sd1_data2"),
207 PINCTRL_PIN(WMT_PIN_SD1DATA3, "sd1_data3"),
208 PINCTRL_PIN(WMT_PIN_SD1DATA4, "sd1_data4"),
209 PINCTRL_PIN(WMT_PIN_SD1DATA5, "sd1_data5"),
210 PINCTRL_PIN(WMT_PIN_SD1DATA6, "sd1_data6"),
211 PINCTRL_PIN(WMT_PIN_SD1DATA7, "sd1_data7"),
212 PINCTRL_PIN(WMT_PIN_I2C0_SCL, "i2c0_scl"),
213 PINCTRL_PIN(WMT_PIN_I2C0_SDA, "i2c0_sda"),
214 PINCTRL_PIN(WMT_PIN_I2C1_SCL, "i2c1_scl"),
215 PINCTRL_PIN(WMT_PIN_I2C1_SDA, "i2c1_sda"),
216 PINCTRL_PIN(WMT_PIN_I2C2_SCL, "i2c2_scl"),
217 PINCTRL_PIN(WMT_PIN_I2C2_SDA, "i2c2_sda"),
218 PINCTRL_PIN(WMT_PIN_UART0_RTS, "uart0_rts"),
219 PINCTRL_PIN(WMT_PIN_UART0_TXD, "uart0_txd"),
220 PINCTRL_PIN(WMT_PIN_UART0_CTS, "uart0_cts"),
221 PINCTRL_PIN(WMT_PIN_UART0_RXD, "uart0_rxd"),
222 PINCTRL_PIN(WMT_PIN_UART1_RTS, "uart1_rts"),
223 PINCTRL_PIN(WMT_PIN_UART1_TXD, "uart1_txd"),
224 PINCTRL_PIN(WMT_PIN_UART1_CTS, "uart1_cts"),
225 PINCTRL_PIN(WMT_PIN_UART1_RXD, "uart1_rxd"),
226 PINCTRL_PIN(WMT_PIN_UART2_RTS, "uart2_rts"),
227 PINCTRL_PIN(WMT_PIN_UART2_TXD, "uart2_txd"),
228 PINCTRL_PIN(WMT_PIN_UART2_CTS, "uart2_cts"),
229 PINCTRL_PIN(WMT_PIN_UART2_RXD, "uart2_rxd"),
230 PINCTRL_PIN(WMT_PIN_SD2WP, "sd2_wp"),
231 PINCTRL_PIN(WMT_PIN_SD2CMD, "sd2_cmd"),
232 PINCTRL_PIN(WMT_PIN_SD2CLK, "sd2_clk"),
233 PINCTRL_PIN(WMT_PIN_SD2PWR, "sd2_pwr"),
234 PINCTRL_PIN(WMT_PIN_SD1CLK, "sd1_clk"),
235 PINCTRL_PIN(WMT_PIN_SD1CMD, "sd1_cmd"),
236 PINCTRL_PIN(WMT_PIN_SD1PWR, "sd1_pwr"),
237 PINCTRL_PIN(WMT_PIN_SD1WP, "sd1_wp"),
238 PINCTRL_PIN(WMT_PIN_SD1CD, "sd1_cd"),
239 PINCTRL_PIN(WMT_PIN_PWMOUT1, "pwmout1"),
240 PINCTRL_PIN(WMT_PIN_PWMOUT0, "pwmout0"),
241};
242
243/* Order of these names must match the above list */
244static const char * const wm8850_groups[] = {
245 "extgpio0",
246 "extgpio1",
247 "extgpio2",
248 "extgpio3",
249 "extgpio4",
250 "extgpio5",
251 "extgpio6",
252 "extgpio7",
253 "wakeup0",
254 "wakeup1",
255 "wakeup2",
256 "wakeup3",
257 "susgpio0",
258 "susgpio1",
259 "sd0_cd",
260 "vdout0",
261 "vdout1",
262 "vdout2",
263 "vdout3",
264 "vdout4",
265 "vdout5",
266 "vdout6",
267 "vdout7",
268 "vdout8",
269 "vdout9",
270 "vdout10",
271 "vdout11",
272 "vdout12",
273 "vdout13",
274 "vdout14",
275 "vdout15",
276 "vdout16",
277 "vdout17",
278 "vdout18",
279 "vdout19",
280 "vdout20",
281 "vdout21",
282 "vdout22",
283 "vdout23",
284 "vdin0",
285 "vdin1",
286 "vdin2",
287 "vdin3",
288 "vdin4",
289 "vdin5",
290 "vdin6",
291 "vdin7",
292 "spi0_mosi",
293 "spi0_miso",
294 "spi0_ss",
295 "spi0_clk",
296 "spi0_ssb",
297 "sd0_clk",
298 "sd0_cmd",
299 "sd0_wp",
300 "sd0_data0",
301 "sd0_data1",
302 "sd0_data2",
303 "sd0_data3",
304 "sd1_data0",
305 "sd1_data1",
306 "sd1_data2",
307 "sd1_data3",
308 "sd1_data4",
309 "sd1_data5",
310 "sd1_data6",
311 "sd1_data7",
312 "i2c0_scl",
313 "i2c0_sda",
314 "i2c1_scl",
315 "i2c1_sda",
316 "i2c2_scl",
317 "i2c2_sda",
318 "uart0_rts",
319 "uart0_txd",
320 "uart0_cts",
321 "uart0_rxd",
322 "uart1_rts",
323 "uart1_txd",
324 "uart1_cts",
325 "uart1_rxd",
326 "uart2_rts",
327 "uart2_txd",
328 "uart2_cts",
329 "uart2_rxd",
330 "sd2_wp",
331 "sd2_cmd",
332 "sd2_clk",
333 "sd2_pwr",
334 "sd1_clk",
335 "sd1_cmd",
336 "sd1_pwr",
337 "sd1_wp",
338 "sd1_cd",
339 "pwmout1",
340 "pwmout0",
341};
342
343static int wm8850_pinctrl_probe(struct platform_device *pdev)
344{
345 struct wmt_pinctrl_data *data;
346
347 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
348 if (!data) {
349 dev_err(&pdev->dev, "failed to allocate data\n");
350 return -ENOMEM;
351 }
352
353 data->banks = wm8850_banks;
354 data->nbanks = ARRAY_SIZE(wm8850_banks);
355 data->pins = wm8850_pins;
356 data->npins = ARRAY_SIZE(wm8850_pins);
357 data->groups = wm8850_groups;
358 data->ngroups = ARRAY_SIZE(wm8850_groups);
359
360 return wmt_pinctrl_probe(pdev, data);
361}
362
363static int wm8850_pinctrl_remove(struct platform_device *pdev)
364{
365 return wmt_pinctrl_remove(pdev);
366}
367
368static struct of_device_id wmt_pinctrl_of_match[] = {
369 { .compatible = "wm,wm8850-pinctrl" },
370 { /* sentinel */ },
371};
372
373static struct platform_driver wmt_pinctrl_driver = {
374 .probe = wm8850_pinctrl_probe,
375 .remove = wm8850_pinctrl_remove,
376 .driver = {
377 .name = "pinctrl-wm8850",
378 .owner = THIS_MODULE,
379 .of_match_table = wmt_pinctrl_of_match,
380 },
381};
382
383module_platform_driver(wmt_pinctrl_driver);
384
385MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
386MODULE_DESCRIPTION("Wondermedia WM8850 Pincontrol driver");
387MODULE_LICENSE("GPL v2");
388MODULE_DEVICE_TABLE(of, wmt_pinctrl_of_match);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c
new file mode 100644
index 000000000000..ab63104e8dc9
--- /dev/null
+++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c
@@ -0,0 +1,632 @@
1/*
2 * Pinctrl driver for the Wondermedia SoC's
3 *
4 * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/err.h>
17#include <linux/gpio.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_irq.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/pinctrl/machine.h>
26#include <linux/pinctrl/pinconf.h>
27#include <linux/pinctrl/pinconf-generic.h>
28#include <linux/pinctrl/pinctrl.h>
29#include <linux/pinctrl/pinmux.h>
30#include <linux/platform_device.h>
31#include <linux/slab.h>
32
33#include "pinctrl-wmt.h"
34
35static inline void wmt_setbits(struct wmt_pinctrl_data *data, u32 reg,
36 u32 mask)
37{
38 u32 val;
39
40 val = readl_relaxed(data->base + reg);
41 val |= mask;
42 writel_relaxed(val, data->base + reg);
43}
44
45static inline void wmt_clearbits(struct wmt_pinctrl_data *data, u32 reg,
46 u32 mask)
47{
48 u32 val;
49
50 val = readl_relaxed(data->base + reg);
51 val &= ~mask;
52 writel_relaxed(val, data->base + reg);
53}
54
55enum wmt_func_sel {
56 WMT_FSEL_GPIO_IN = 0,
57 WMT_FSEL_GPIO_OUT = 1,
58 WMT_FSEL_ALT = 2,
59 WMT_FSEL_COUNT = 3,
60};
61
62static const char * const wmt_functions[WMT_FSEL_COUNT] = {
63 [WMT_FSEL_GPIO_IN] = "gpio_in",
64 [WMT_FSEL_GPIO_OUT] = "gpio_out",
65 [WMT_FSEL_ALT] = "alt",
66};
67
68static int wmt_pmx_get_functions_count(struct pinctrl_dev *pctldev)
69{
70 return WMT_FSEL_COUNT;
71}
72
73static const char *wmt_pmx_get_function_name(struct pinctrl_dev *pctldev,
74 unsigned selector)
75{
76 return wmt_functions[selector];
77}
78
79static int wmt_pmx_get_function_groups(struct pinctrl_dev *pctldev,
80 unsigned selector,
81 const char * const **groups,
82 unsigned * const num_groups)
83{
84 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
85
86 /* every pin does every function */
87 *groups = data->groups;
88 *num_groups = data->ngroups;
89
90 return 0;
91}
92
93static int wmt_set_pinmux(struct wmt_pinctrl_data *data, unsigned func,
94 unsigned pin)
95{
96 u32 bank = WMT_BANK_FROM_PIN(pin);
97 u32 bit = WMT_BIT_FROM_PIN(pin);
98 u32 reg_en = data->banks[bank].reg_en;
99 u32 reg_dir = data->banks[bank].reg_dir;
100
101 if (reg_dir == NO_REG) {
102 dev_err(data->dev, "pin:%d no direction register defined\n",
103 pin);
104 return -EINVAL;
105 }
106
107 /*
108 * If reg_en == NO_REG, we assume it is a dedicated GPIO and cannot be
109 * disabled (as on VT8500) and that no alternate function is available.
110 */
111 switch (func) {
112 case WMT_FSEL_GPIO_IN:
113 if (reg_en != NO_REG)
114 wmt_setbits(data, reg_en, BIT(bit));
115 wmt_clearbits(data, reg_dir, BIT(bit));
116 break;
117 case WMT_FSEL_GPIO_OUT:
118 if (reg_en != NO_REG)
119 wmt_setbits(data, reg_en, BIT(bit));
120 wmt_setbits(data, reg_dir, BIT(bit));
121 break;
122 case WMT_FSEL_ALT:
123 if (reg_en == NO_REG) {
124 dev_err(data->dev, "pin:%d no alt function available\n",
125 pin);
126 return -EINVAL;
127 }
128 wmt_clearbits(data, reg_en, BIT(bit));
129 }
130
131 return 0;
132}
133
134static int wmt_pmx_enable(struct pinctrl_dev *pctldev,
135 unsigned func_selector,
136 unsigned group_selector)
137{
138 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
139 u32 pinnum = data->pins[group_selector].number;
140
141 return wmt_set_pinmux(data, func_selector, pinnum);
142}
143
144static void wmt_pmx_disable(struct pinctrl_dev *pctldev,
145 unsigned func_selector,
146 unsigned group_selector)
147{
148 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
149 u32 pinnum = data->pins[group_selector].number;
150
151 /* disable by setting GPIO_IN */
152 wmt_set_pinmux(data, WMT_FSEL_GPIO_IN, pinnum);
153}
154
155static void wmt_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
156 struct pinctrl_gpio_range *range,
157 unsigned offset)
158{
159 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
160
161 /* disable by setting GPIO_IN */
162 wmt_set_pinmux(data, WMT_FSEL_GPIO_IN, offset);
163}
164
165static int wmt_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
166 struct pinctrl_gpio_range *range,
167 unsigned offset,
168 bool input)
169{
170 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
171
172 wmt_set_pinmux(data, (input ? WMT_FSEL_GPIO_IN : WMT_FSEL_GPIO_OUT),
173 offset);
174
175 return 0;
176}
177
178static struct pinmux_ops wmt_pinmux_ops = {
179 .get_functions_count = wmt_pmx_get_functions_count,
180 .get_function_name = wmt_pmx_get_function_name,
181 .get_function_groups = wmt_pmx_get_function_groups,
182 .enable = wmt_pmx_enable,
183 .disable = wmt_pmx_disable,
184 .gpio_disable_free = wmt_pmx_gpio_disable_free,
185 .gpio_set_direction = wmt_pmx_gpio_set_direction,
186};
187
188static int wmt_get_groups_count(struct pinctrl_dev *pctldev)
189{
190 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
191
192 return data->ngroups;
193}
194
195static const char *wmt_get_group_name(struct pinctrl_dev *pctldev,
196 unsigned selector)
197{
198 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
199
200 return data->groups[selector];
201}
202
203static int wmt_get_group_pins(struct pinctrl_dev *pctldev,
204 unsigned selector,
205 const unsigned **pins,
206 unsigned *num_pins)
207{
208 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
209
210 *pins = &data->pins[selector].number;
211 *num_pins = 1;
212
213 return 0;
214}
215
216static int wmt_pctl_find_group_by_pin(struct wmt_pinctrl_data *data, u32 pin)
217{
218 int i;
219
220 for (i = 0; i < data->npins; i++) {
221 if (data->pins[i].number == pin)
222 return i;
223 }
224
225 return -EINVAL;
226}
227
228static int wmt_pctl_dt_node_to_map_func(struct wmt_pinctrl_data *data,
229 struct device_node *np,
230 u32 pin, u32 fnum,
231 struct pinctrl_map **maps)
232{
233 int group;
234 struct pinctrl_map *map = *maps;
235
236 if (fnum >= ARRAY_SIZE(wmt_functions)) {
237 dev_err(data->dev, "invalid wm,function %d\n", fnum);
238 return -EINVAL;
239 }
240
241 group = wmt_pctl_find_group_by_pin(data, pin);
242 if (group < 0) {
243 dev_err(data->dev, "unable to match pin %d to group\n", pin);
244 return group;
245 }
246
247 map->type = PIN_MAP_TYPE_MUX_GROUP;
248 map->data.mux.group = data->groups[group];
249 map->data.mux.function = wmt_functions[fnum];
250 (*maps)++;
251
252 return 0;
253}
254
255static int wmt_pctl_dt_node_to_map_pull(struct wmt_pinctrl_data *data,
256 struct device_node *np,
257 u32 pin, u32 pull,
258 struct pinctrl_map **maps)
259{
260 int group;
261 unsigned long *configs;
262 struct pinctrl_map *map = *maps;
263
264 if (pull > 2) {
265 dev_err(data->dev, "invalid wm,pull %d\n", pull);
266 return -EINVAL;
267 }
268
269 group = wmt_pctl_find_group_by_pin(data, pin);
270 if (group < 0) {
271 dev_err(data->dev, "unable to match pin %d to group\n", pin);
272 return group;
273 }
274
275 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
276 if (!configs)
277 return -ENOMEM;
278
279 configs[0] = pull;
280
281 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
282 map->data.configs.group_or_pin = data->groups[group];
283 map->data.configs.configs = configs;
284 map->data.configs.num_configs = 1;
285 (*maps)++;
286
287 return 0;
288}
289
290static void wmt_pctl_dt_free_map(struct pinctrl_dev *pctldev,
291 struct pinctrl_map *maps,
292 unsigned num_maps)
293{
294 int i;
295
296 for (i = 0; i < num_maps; i++)
297 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
298 kfree(maps[i].data.configs.configs);
299
300 kfree(maps);
301}
302
303static int wmt_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
304 struct device_node *np,
305 struct pinctrl_map **map,
306 unsigned *num_maps)
307{
308 struct pinctrl_map *maps, *cur_map;
309 struct property *pins, *funcs, *pulls;
310 u32 pin, func, pull;
311 int num_pins, num_funcs, num_pulls, maps_per_pin;
312 int i, err;
313 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
314
315 pins = of_find_property(np, "wm,pins", NULL);
316 if (!pins) {
317 dev_err(data->dev, "missing wmt,pins property\n");
318 return -EINVAL;
319 }
320
321 funcs = of_find_property(np, "wm,function", NULL);
322 pulls = of_find_property(np, "wm,pull", NULL);
323
324 if (!funcs && !pulls) {
325 dev_err(data->dev, "neither wm,function nor wm,pull specified\n");
326 return -EINVAL;
327 }
328
329 /*
330 * The following lines calculate how many values are defined for each
331 * of the properties.
332 */
333 num_pins = pins->length / sizeof(u32);
334 num_funcs = funcs ? (funcs->length / sizeof(u32)) : 0;
335 num_pulls = pulls ? (pulls->length / sizeof(u32)) : 0;
336
337 if (num_funcs > 1 && num_funcs != num_pins) {
338 dev_err(data->dev, "wm,function must have 1 or %d entries\n",
339 num_pins);
340 return -EINVAL;
341 }
342
343 if (num_pulls > 1 && num_pulls != num_pins) {
344 dev_err(data->dev, "wm,pull must have 1 or %d entries\n",
345 num_pins);
346 return -EINVAL;
347 }
348
349 maps_per_pin = 0;
350 if (num_funcs)
351 maps_per_pin++;
352 if (num_pulls)
353 maps_per_pin++;
354
355 cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps),
356 GFP_KERNEL);
357 if (!maps)
358 return -ENOMEM;
359
360 for (i = 0; i < num_pins; i++) {
361 err = of_property_read_u32_index(np, "wm,pins", i, &pin);
362 if (err)
363 goto fail;
364
365 if (pin >= (data->nbanks * 32)) {
366 dev_err(data->dev, "invalid wm,pins value\n");
367 err = -EINVAL;
368 goto fail;
369 }
370
371 if (num_funcs) {
372 err = of_property_read_u32_index(np, "wm,function",
373 (num_funcs > 1 ? i : 0), &func);
374 if (err)
375 goto fail;
376
377 err = wmt_pctl_dt_node_to_map_func(data, np, pin, func,
378 &cur_map);
379 if (err)
380 goto fail;
381 }
382
383 if (num_pulls) {
384 err = of_property_read_u32_index(np, "wm,pull",
385 (num_pulls > 1 ? i : 0), &pull);
386 if (err)
387 goto fail;
388
389 err = wmt_pctl_dt_node_to_map_pull(data, np, pin, pull,
390 &cur_map);
391 if (err)
392 goto fail;
393 }
394 }
395 *map = maps;
396 *num_maps = num_pins * maps_per_pin;
397 return 0;
398
399/*
400 * The fail path removes any maps that have been allocated. The fail path is
401 * only called from code after maps has been kzalloc'd. It is also safe to
402 * pass 'num_pins * maps_per_pin' as the map count even though we probably
403 * failed before all the mappings were read as all maps are allocated at once,
404 * and configs are only allocated for .type = PIN_MAP_TYPE_CONFIGS_PIN - there
405 * is no failpath where a config can be allocated without .type being set.
406 */
407fail:
408 wmt_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
409 return err;
410}
411
412static struct pinctrl_ops wmt_pctl_ops = {
413 .get_groups_count = wmt_get_groups_count,
414 .get_group_name = wmt_get_group_name,
415 .get_group_pins = wmt_get_group_pins,
416 .dt_node_to_map = wmt_pctl_dt_node_to_map,
417 .dt_free_map = wmt_pctl_dt_free_map,
418};
419
420static int wmt_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
421 unsigned long *config)
422{
423 return -ENOTSUPP;
424}
425
426static int wmt_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
427 unsigned long config)
428{
429 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
430 enum pin_config_param param = pinconf_to_config_param(config);
431 u16 arg = pinconf_to_config_argument(config);
432 u32 bank = WMT_BANK_FROM_PIN(pin);
433 u32 bit = WMT_BIT_FROM_PIN(pin);
434 u32 reg_pull_en = data->banks[bank].reg_pull_en;
435 u32 reg_pull_cfg = data->banks[bank].reg_pull_cfg;
436
437 if ((reg_pull_en == NO_REG) || (reg_pull_cfg == NO_REG)) {
438 dev_err(data->dev, "bias functions not supported on pin %d\n",
439 pin);
440 return -EINVAL;
441 }
442
443 if ((param == PIN_CONFIG_BIAS_PULL_DOWN) ||
444 (param == PIN_CONFIG_BIAS_PULL_UP)) {
445 if (arg == 0)
446 param = PIN_CONFIG_BIAS_DISABLE;
447 }
448
449 switch (param) {
450 case PIN_CONFIG_BIAS_DISABLE:
451 wmt_clearbits(data, reg_pull_en, BIT(bit));
452 break;
453 case PIN_CONFIG_BIAS_PULL_DOWN:
454 wmt_clearbits(data, reg_pull_cfg, BIT(bit));
455 wmt_setbits(data, reg_pull_en, BIT(bit));
456 break;
457 case PIN_CONFIG_BIAS_PULL_UP:
458 wmt_setbits(data, reg_pull_cfg, BIT(bit));
459 wmt_setbits(data, reg_pull_en, BIT(bit));
460 break;
461 default:
462 dev_err(data->dev, "unknown pinconf param\n");
463 return -EINVAL;
464 }
465
466 return 0;
467}
468
469static struct pinconf_ops wmt_pinconf_ops = {
470 .pin_config_get = wmt_pinconf_get,
471 .pin_config_set = wmt_pinconf_set,
472};
473
474static struct pinctrl_desc wmt_desc = {
475 .owner = THIS_MODULE,
476 .name = "pinctrl-wmt",
477 .pctlops = &wmt_pctl_ops,
478 .pmxops = &wmt_pinmux_ops,
479 .confops = &wmt_pinconf_ops,
480};
481
482static int wmt_gpio_request(struct gpio_chip *chip, unsigned offset)
483{
484 return pinctrl_request_gpio(chip->base + offset);
485}
486
487static void wmt_gpio_free(struct gpio_chip *chip, unsigned offset)
488{
489 pinctrl_free_gpio(chip->base + offset);
490}
491
492static int wmt_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
493{
494 struct wmt_pinctrl_data *data = dev_get_drvdata(chip->dev);
495 u32 bank = WMT_BANK_FROM_PIN(offset);
496 u32 bit = WMT_BIT_FROM_PIN(offset);
497 u32 reg_dir = data->banks[bank].reg_dir;
498 u32 val;
499
500 val = readl_relaxed(data->base + reg_dir);
501 if (val & BIT(bit))
502 return GPIOF_DIR_OUT;
503 else
504 return GPIOF_DIR_IN;
505}
506
507static int wmt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
508{
509 return pinctrl_gpio_direction_input(chip->base + offset);
510}
511
512static int wmt_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
513 int value)
514{
515 return pinctrl_gpio_direction_output(chip->base + offset);
516}
517
518static int wmt_gpio_get_value(struct gpio_chip *chip, unsigned offset)
519{
520 struct wmt_pinctrl_data *data = dev_get_drvdata(chip->dev);
521 u32 bank = WMT_BANK_FROM_PIN(offset);
522 u32 bit = WMT_BIT_FROM_PIN(offset);
523 u32 reg_data_in = data->banks[bank].reg_data_in;
524
525 if (reg_data_in == NO_REG) {
526 dev_err(data->dev, "no data in register defined\n");
527 return -EINVAL;
528 }
529
530 return !!(readl_relaxed(data->base + reg_data_in) & BIT(bit));
531}
532
533static void wmt_gpio_set_value(struct gpio_chip *chip, unsigned offset,
534 int val)
535{
536 struct wmt_pinctrl_data *data = dev_get_drvdata(chip->dev);
537 u32 bank = WMT_BANK_FROM_PIN(offset);
538 u32 bit = WMT_BIT_FROM_PIN(offset);
539 u32 reg_data_out = data->banks[bank].reg_data_out;
540
541 if (reg_data_out == NO_REG) {
542 dev_err(data->dev, "no data out register defined\n");
543 return;
544 }
545
546 if (val)
547 wmt_setbits(data, reg_data_out, BIT(bit));
548 else
549 wmt_clearbits(data, reg_data_out, BIT(bit));
550}
551
552static struct gpio_chip wmt_gpio_chip = {
553 .label = "gpio-wmt",
554 .owner = THIS_MODULE,
555 .request = wmt_gpio_request,
556 .free = wmt_gpio_free,
557 .get_direction = wmt_gpio_get_direction,
558 .direction_input = wmt_gpio_direction_input,
559 .direction_output = wmt_gpio_direction_output,
560 .get = wmt_gpio_get_value,
561 .set = wmt_gpio_set_value,
562 .can_sleep = 0,
563};
564
565int wmt_pinctrl_probe(struct platform_device *pdev,
566 struct wmt_pinctrl_data *data)
567{
568 int err;
569 struct resource *res;
570
571 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
572 data->base = devm_request_and_ioremap(&pdev->dev, res);
573 if (!data->base) {
574 dev_err(&pdev->dev, "failed to map memory resource\n");
575 return -EBUSY;
576 }
577
578 wmt_desc.pins = data->pins;
579 wmt_desc.npins = data->npins;
580
581 data->gpio_chip = wmt_gpio_chip;
582 data->gpio_chip.dev = &pdev->dev;
583 data->gpio_chip.of_node = pdev->dev.of_node;
584 data->gpio_chip.ngpio = data->nbanks * 32;
585
586 platform_set_drvdata(pdev, data);
587
588 data->dev = &pdev->dev;
589
590 data->pctl_dev = pinctrl_register(&wmt_desc, &pdev->dev, data);
591 if (!data->pctl_dev) {
592 dev_err(&pdev->dev, "Failed to register pinctrl\n");
593 return -EINVAL;
594 }
595
596 err = gpiochip_add(&data->gpio_chip);
597 if (err) {
598 dev_err(&pdev->dev, "could not add GPIO chip\n");
599 goto fail_gpio;
600 }
601
602 err = gpiochip_add_pin_range(&data->gpio_chip, dev_name(data->dev),
603 0, 0, data->nbanks * 32);
604 if (err)
605 goto fail_range;
606
607 dev_info(&pdev->dev, "Pin controller initialized\n");
608
609 return 0;
610
611fail_range:
612 err = gpiochip_remove(&data->gpio_chip);
613 if (err)
614 dev_err(&pdev->dev, "failed to remove gpio chip\n");
615fail_gpio:
616 pinctrl_unregister(data->pctl_dev);
617 return err;
618}
619
620int wmt_pinctrl_remove(struct platform_device *pdev)
621{
622 struct wmt_pinctrl_data *data = platform_get_drvdata(pdev);
623 int err;
624
625 err = gpiochip_remove(&data->gpio_chip);
626 if (err)
627 dev_err(&pdev->dev, "failed to remove gpio chip\n");
628
629 pinctrl_unregister(data->pctl_dev);
630
631 return 0;
632}
diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.h b/drivers/pinctrl/vt8500/pinctrl-wmt.h
new file mode 100644
index 000000000000..41f5f2deb5d6
--- /dev/null
+++ b/drivers/pinctrl/vt8500/pinctrl-wmt.h
@@ -0,0 +1,79 @@
1/*
2 * Pinctrl driver for the Wondermedia SoC's
3 *
4 * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/gpio.h>
17
18/* VT8500 has no enable register in the extgpio bank. */
19#define NO_REG 0xFFFF
20
21#define WMT_PINCTRL_BANK(__en, __dir, __dout, __din, __pen, __pcfg) \
22{ \
23 .reg_en = __en, \
24 .reg_dir = __dir, \
25 .reg_data_out = __dout, \
26 .reg_data_in = __din, \
27 .reg_pull_en = __pen, \
28 .reg_pull_cfg = __pcfg, \
29}
30
31/* Encode/decode the bank/bit pairs into a pin value */
32#define WMT_PIN(__bank, __offset) ((__bank << 5) | __offset)
33#define WMT_BANK_FROM_PIN(__pin) (__pin >> 5)
34#define WMT_BIT_FROM_PIN(__pin) (__pin & 0x1f)
35
36#define WMT_GROUP(__name, __data) \
37{ \
38 .name = __name, \
39 .pins = __data, \
40 .npins = ARRAY_SIZE(__data), \
41}
42
43struct wmt_pinctrl_bank_registers {
44 u32 reg_en;
45 u32 reg_dir;
46 u32 reg_data_out;
47 u32 reg_data_in;
48
49 u32 reg_pull_en;
50 u32 reg_pull_cfg;
51};
52
53struct wmt_pinctrl_group {
54 const char *name;
55 const unsigned int *pins;
56 const unsigned npins;
57};
58
59struct wmt_pinctrl_data {
60 struct device *dev;
61 struct pinctrl_dev *pctl_dev;
62
63 /* must be initialized before calling wmt_pinctrl_probe */
64 void __iomem *base;
65 const struct wmt_pinctrl_bank_registers *banks;
66 const struct pinctrl_pin_desc *pins;
67 const char * const *groups;
68
69 u32 nbanks;
70 u32 npins;
71 u32 ngroups;
72
73 struct gpio_chip gpio_chip;
74 struct pinctrl_gpio_range gpio_range;
75};
76
77int wmt_pinctrl_probe(struct platform_device *pdev,
78 struct wmt_pinctrl_data *data);
79int wmt_pinctrl_remove(struct platform_device *pdev);
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
new file mode 100644
index 000000000000..c9d04f797862
--- /dev/null
+++ b/drivers/reset/Kconfig
@@ -0,0 +1,13 @@
1config ARCH_HAS_RESET_CONTROLLER
2 bool
3
4menuconfig RESET_CONTROLLER
5 bool "Reset Controller Support"
6 default y if ARCH_HAS_RESET_CONTROLLER
7 help
8 Generic Reset Controller support.
9
10 This framework is designed to abstract reset handling of devices
11 via GPIOs or SoC-internal reset controller modules.
12
13 If unsure, say no.
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
new file mode 100644
index 000000000000..1e2d83f2b995
--- /dev/null
+++ b/drivers/reset/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_RESET_CONTROLLER) += core.o
diff --git a/drivers/reset/core.c b/drivers/reset/core.c
new file mode 100644
index 000000000000..d1b6089a0ef8
--- /dev/null
+++ b/drivers/reset/core.c
@@ -0,0 +1,297 @@
1/*
2 * Reset Controller framework
3 *
4 * Copyright 2013 Philipp Zabel, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#include <linux/device.h>
12#include <linux/err.h>
13#include <linux/export.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/reset.h>
18#include <linux/reset-controller.h>
19#include <linux/slab.h>
20
21static DEFINE_MUTEX(reset_controller_list_mutex);
22static LIST_HEAD(reset_controller_list);
23
24/**
25 * struct reset_control - a reset control
26 * @rcdev: a pointer to the reset controller device
27 * this reset control belongs to
28 * @id: ID of the reset controller in the reset
29 * controller device
30 */
31struct reset_control {
32 struct reset_controller_dev *rcdev;
33 struct device *dev;
34 unsigned int id;
35};
36
37/**
38 * of_reset_simple_xlate - translate reset_spec to the reset line number
39 * @rcdev: a pointer to the reset controller device
40 * @reset_spec: reset line specifier as found in the device tree
41 * @flags: a flags pointer to fill in (optional)
42 *
43 * This simple translation function should be used for reset controllers
44 * with 1:1 mapping, where reset lines can be indexed by number without gaps.
45 */
46int of_reset_simple_xlate(struct reset_controller_dev *rcdev,
47 const struct of_phandle_args *reset_spec)
48{
49 if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
50 return -EINVAL;
51
52 if (reset_spec->args[0] >= rcdev->nr_resets)
53 return -EINVAL;
54
55 return reset_spec->args[0];
56}
57EXPORT_SYMBOL_GPL(of_reset_simple_xlate);
58
59/**
60 * reset_controller_register - register a reset controller device
61 * @rcdev: a pointer to the initialized reset controller device
62 */
63int reset_controller_register(struct reset_controller_dev *rcdev)
64{
65 if (!rcdev->of_xlate) {
66 rcdev->of_reset_n_cells = 1;
67 rcdev->of_xlate = of_reset_simple_xlate;
68 }
69
70 mutex_lock(&reset_controller_list_mutex);
71 list_add(&rcdev->list, &reset_controller_list);
72 mutex_unlock(&reset_controller_list_mutex);
73
74 return 0;
75}
76EXPORT_SYMBOL_GPL(reset_controller_register);
77
78/**
79 * reset_controller_unregister - unregister a reset controller device
80 * @rcdev: a pointer to the reset controller device
81 */
82void reset_controller_unregister(struct reset_controller_dev *rcdev)
83{
84 mutex_lock(&reset_controller_list_mutex);
85 list_del(&rcdev->list);
86 mutex_unlock(&reset_controller_list_mutex);
87}
88EXPORT_SYMBOL_GPL(reset_controller_unregister);
89
90/**
91 * reset_control_reset - reset the controlled device
92 * @rstc: reset controller
93 */
94int reset_control_reset(struct reset_control *rstc)
95{
96 if (rstc->rcdev->ops->reset)
97 return rstc->rcdev->ops->reset(rstc->rcdev, rstc->id);
98
99 return -ENOSYS;
100}
101EXPORT_SYMBOL_GPL(reset_control_reset);
102
103/**
104 * reset_control_assert - asserts the reset line
105 * @rstc: reset controller
106 */
107int reset_control_assert(struct reset_control *rstc)
108{
109 if (rstc->rcdev->ops->assert)
110 return rstc->rcdev->ops->assert(rstc->rcdev, rstc->id);
111
112 return -ENOSYS;
113}
114EXPORT_SYMBOL_GPL(reset_control_assert);
115
116/**
117 * reset_control_deassert - deasserts the reset line
118 * @rstc: reset controller
119 */
120int reset_control_deassert(struct reset_control *rstc)
121{
122 if (rstc->rcdev->ops->deassert)
123 return rstc->rcdev->ops->deassert(rstc->rcdev, rstc->id);
124
125 return -ENOSYS;
126}
127EXPORT_SYMBOL_GPL(reset_control_deassert);
128
129/**
130 * reset_control_get - Lookup and obtain a reference to a reset controller.
131 * @dev: device to be reset by the controller
132 * @id: reset line name
133 *
134 * Returns a struct reset_control or IS_ERR() condition containing errno.
135 *
136 * Use of id names is optional.
137 */
138struct reset_control *reset_control_get(struct device *dev, const char *id)
139{
140 struct reset_control *rstc = ERR_PTR(-EPROBE_DEFER);
141 struct reset_controller_dev *r, *rcdev;
142 struct of_phandle_args args;
143 int index = 0;
144 int rstc_id;
145 int ret;
146
147 if (!dev)
148 return ERR_PTR(-EINVAL);
149
150 if (id)
151 index = of_property_match_string(dev->of_node,
152 "reset-names", id);
153 ret = of_parse_phandle_with_args(dev->of_node, "resets", "#reset-cells",
154 index, &args);
155 if (ret)
156 return ERR_PTR(ret);
157
158 mutex_lock(&reset_controller_list_mutex);
159 rcdev = NULL;
160 list_for_each_entry(r, &reset_controller_list, list) {
161 if (args.np == r->of_node) {
162 rcdev = r;
163 break;
164 }
165 }
166 of_node_put(args.np);
167
168 if (!rcdev) {
169 mutex_unlock(&reset_controller_list_mutex);
170 return ERR_PTR(-ENODEV);
171 }
172
173 rstc_id = rcdev->of_xlate(rcdev, &args);
174 if (rstc_id < 0) {
175 mutex_unlock(&reset_controller_list_mutex);
176 return ERR_PTR(rstc_id);
177 }
178
179 try_module_get(rcdev->owner);
180 mutex_unlock(&reset_controller_list_mutex);
181
182 rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
183 if (!rstc) {
184 module_put(rcdev->owner);
185 return ERR_PTR(-ENOMEM);
186 }
187
188 rstc->dev = dev;
189 rstc->rcdev = rcdev;
190 rstc->id = rstc_id;
191
192 return rstc;
193}
194EXPORT_SYMBOL_GPL(reset_control_get);
195
196/**
197 * reset_control_put - free the reset controller
198 * @rstc: reset controller
199 */
200
201void reset_control_put(struct reset_control *rstc)
202{
203 if (IS_ERR(rstc))
204 return;
205
206 module_put(rstc->rcdev->owner);
207 kfree(rstc);
208}
209EXPORT_SYMBOL_GPL(reset_control_put);
210
211static void devm_reset_control_release(struct device *dev, void *res)
212{
213 reset_control_put(*(struct reset_control **)res);
214}
215
216/**
217 * devm_reset_control_get - resource managed reset_control_get()
218 * @dev: device to be reset by the controller
219 * @id: reset line name
220 *
221 * Managed reset_control_get(). For reset controllers returned from this
222 * function, reset_control_put() is called automatically on driver detach.
223 * See reset_control_get() for more information.
224 */
225struct reset_control *devm_reset_control_get(struct device *dev, const char *id)
226{
227 struct reset_control **ptr, *rstc;
228
229 ptr = devres_alloc(devm_reset_control_release, sizeof(*ptr),
230 GFP_KERNEL);
231 if (!ptr)
232 return ERR_PTR(-ENOMEM);
233
234 rstc = reset_control_get(dev, id);
235 if (!IS_ERR(rstc)) {
236 *ptr = rstc;
237 devres_add(dev, ptr);
238 } else {
239 devres_free(ptr);
240 }
241
242 return rstc;
243}
244EXPORT_SYMBOL_GPL(devm_reset_control_get);
245
246static int devm_reset_control_match(struct device *dev, void *res, void *data)
247{
248 struct reset_control **rstc = res;
249 if (WARN_ON(!rstc || !*rstc))
250 return 0;
251 return *rstc == data;
252}
253
254/**
255 * devm_reset_control_put - resource managed reset_control_put()
256 * @rstc: reset controller to free
257 *
258 * Deallocate a reset control allocated withd devm_reset_control_get().
259 * This function will not need to be called normally, as devres will take
260 * care of freeing the resource.
261 */
262void devm_reset_control_put(struct reset_control *rstc)
263{
264 int ret;
265
266 ret = devres_release(rstc->dev, devm_reset_control_release,
267 devm_reset_control_match, rstc);
268 if (ret)
269 WARN_ON(ret);
270}
271EXPORT_SYMBOL_GPL(devm_reset_control_put);
272
273/**
274 * device_reset - find reset controller associated with the device
275 * and perform reset
276 * @dev: device to be reset by the controller
277 *
278 * Convenience wrapper for reset_control_get() and reset_control_reset().
279 * This is useful for the common case of devices with single, dedicated reset
280 * lines.
281 */
282int device_reset(struct device *dev)
283{
284 struct reset_control *rstc;
285 int ret;
286
287 rstc = reset_control_get(dev, NULL);
288 if (IS_ERR(rstc))
289 return PTR_ERR(rstc);
290
291 ret = reset_control_reset(rstc);
292
293 reset_control_put(rstc);
294
295 return ret;
296}
297EXPORT_SYMBOL_GPL(device_reset);
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 98348ec0b3ce..540909de6247 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -34,6 +34,77 @@
34#define ATMEL_LCDC_DMA_BURST_LEN 8 /* words */ 34#define ATMEL_LCDC_DMA_BURST_LEN 8 /* words */
35#define ATMEL_LCDC_FIFO_SIZE 512 /* words */ 35#define ATMEL_LCDC_FIFO_SIZE 512 /* words */
36 36
37struct atmel_lcdfb_config {
38 bool have_alt_pixclock;
39 bool have_hozval;
40 bool have_intensity_bit;
41};
42
43static struct atmel_lcdfb_config at91sam9261_config = {
44 .have_hozval = true,
45 .have_intensity_bit = true,
46};
47
48static struct atmel_lcdfb_config at91sam9263_config = {
49 .have_intensity_bit = true,
50};
51
52static struct atmel_lcdfb_config at91sam9g10_config = {
53 .have_hozval = true,
54};
55
56static struct atmel_lcdfb_config at91sam9g45_config = {
57 .have_alt_pixclock = true,
58};
59
60static struct atmel_lcdfb_config at91sam9g45es_config = {
61};
62
63static struct atmel_lcdfb_config at91sam9rl_config = {
64 .have_intensity_bit = true,
65};
66
67static struct atmel_lcdfb_config at32ap_config = {
68 .have_hozval = true,
69};
70
71static const struct platform_device_id atmel_lcdfb_devtypes[] = {
72 {
73 .name = "at91sam9261-lcdfb",
74 .driver_data = (unsigned long)&at91sam9261_config,
75 }, {
76 .name = "at91sam9263-lcdfb",
77 .driver_data = (unsigned long)&at91sam9263_config,
78 }, {
79 .name = "at91sam9g10-lcdfb",
80 .driver_data = (unsigned long)&at91sam9g10_config,
81 }, {
82 .name = "at91sam9g45-lcdfb",
83 .driver_data = (unsigned long)&at91sam9g45_config,
84 }, {
85 .name = "at91sam9g45es-lcdfb",
86 .driver_data = (unsigned long)&at91sam9g45es_config,
87 }, {
88 .name = "at91sam9rl-lcdfb",
89 .driver_data = (unsigned long)&at91sam9rl_config,
90 }, {
91 .name = "at32ap-lcdfb",
92 .driver_data = (unsigned long)&at32ap_config,
93 }, {
94 /* terminator */
95 }
96};
97
98static struct atmel_lcdfb_config *
99atmel_lcdfb_get_config(struct platform_device *pdev)
100{
101 unsigned long data;
102
103 data = platform_get_device_id(pdev)->driver_data;
104
105 return (struct atmel_lcdfb_config *)data;
106}
107
37#if defined(CONFIG_ARCH_AT91) 108#if defined(CONFIG_ARCH_AT91)
38#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \ 109#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
39 | FBINFO_PARTIAL_PAN_OK \ 110 | FBINFO_PARTIAL_PAN_OK \
@@ -193,14 +264,16 @@ static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
193 .accel = FB_ACCEL_NONE, 264 .accel = FB_ACCEL_NONE,
194}; 265};
195 266
196static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2) 267static unsigned long compute_hozval(struct atmel_lcdfb_info *sinfo,
268 unsigned long xres)
197{ 269{
270 unsigned long lcdcon2;
198 unsigned long value; 271 unsigned long value;
199 272
200 if (!(cpu_is_at91sam9261() || cpu_is_at91sam9g10() 273 if (!sinfo->config->have_hozval)
201 || cpu_is_at32ap7000()))
202 return xres; 274 return xres;
203 275
276 lcdcon2 = lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2);
204 value = xres; 277 value = xres;
205 if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) { 278 if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
206 /* STN display */ 279 /* STN display */
@@ -423,7 +496,7 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
423 break; 496 break;
424 case 16: 497 case 16:
425 /* Older SOCs use IBGR:555 rather than BGR:565. */ 498 /* Older SOCs use IBGR:555 rather than BGR:565. */
426 if (sinfo->have_intensity_bit) 499 if (sinfo->config->have_intensity_bit)
427 var->green.length = 5; 500 var->green.length = 5;
428 else 501 else
429 var->green.length = 6; 502 var->green.length = 6;
@@ -531,7 +604,7 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
531 /* Now, the LCDC core... */ 604 /* Now, the LCDC core... */
532 605
533 /* Set pixel clock */ 606 /* Set pixel clock */
534 if (cpu_is_at91sam9g45() && !cpu_is_at91sam9g45es()) 607 if (sinfo->config->have_alt_pixclock)
535 pix_factor = 1; 608 pix_factor = 1;
536 609
537 clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000; 610 clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
@@ -591,8 +664,7 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
591 lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value); 664 lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
592 665
593 /* Horizontal value (aka line size) */ 666 /* Horizontal value (aka line size) */
594 hozval_linesz = compute_hozval(info->var.xres, 667 hozval_linesz = compute_hozval(sinfo, info->var.xres);
595 lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
596 668
597 /* Display size */ 669 /* Display size */
598 value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET; 670 value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
@@ -684,7 +756,7 @@ static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
684 756
685 case FB_VISUAL_PSEUDOCOLOR: 757 case FB_VISUAL_PSEUDOCOLOR:
686 if (regno < 256) { 758 if (regno < 256) {
687 if (sinfo->have_intensity_bit) { 759 if (sinfo->config->have_intensity_bit) {
688 /* old style I+BGR:555 */ 760 /* old style I+BGR:555 */
689 val = ((red >> 11) & 0x001f); 761 val = ((red >> 11) & 0x001f);
690 val |= ((green >> 6) & 0x03e0); 762 val |= ((green >> 6) & 0x03e0);
@@ -821,15 +893,13 @@ static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo)
821 893
822static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo) 894static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
823{ 895{
824 if (sinfo->bus_clk) 896 clk_enable(sinfo->bus_clk);
825 clk_enable(sinfo->bus_clk);
826 clk_enable(sinfo->lcdc_clk); 897 clk_enable(sinfo->lcdc_clk);
827} 898}
828 899
829static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo) 900static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
830{ 901{
831 if (sinfo->bus_clk) 902 clk_disable(sinfo->bus_clk);
832 clk_disable(sinfo->bus_clk);
833 clk_disable(sinfo->lcdc_clk); 903 clk_disable(sinfo->lcdc_clk);
834} 904}
835 905
@@ -874,10 +944,9 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
874 } 944 }
875 sinfo->info = info; 945 sinfo->info = info;
876 sinfo->pdev = pdev; 946 sinfo->pdev = pdev;
877 if (cpu_is_at91sam9261() || cpu_is_at91sam9263() || 947 sinfo->config = atmel_lcdfb_get_config(pdev);
878 cpu_is_at91sam9rl()) { 948 if (!sinfo->config)
879 sinfo->have_intensity_bit = true; 949 goto free_info;
880 }
881 950
882 strcpy(info->fix.id, sinfo->pdev->name); 951 strcpy(info->fix.id, sinfo->pdev->name);
883 info->flags = ATMEL_LCDFB_FBINFO_DEFAULT; 952 info->flags = ATMEL_LCDFB_FBINFO_DEFAULT;
@@ -888,13 +957,10 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
888 info->fix = atmel_lcdfb_fix; 957 info->fix = atmel_lcdfb_fix;
889 958
890 /* Enable LCDC Clocks */ 959 /* Enable LCDC Clocks */
891 if (cpu_is_at91sam9261() || cpu_is_at91sam9g10() 960 sinfo->bus_clk = clk_get(dev, "hclk");
892 || cpu_is_at32ap7000()) { 961 if (IS_ERR(sinfo->bus_clk)) {
893 sinfo->bus_clk = clk_get(dev, "hck1"); 962 ret = PTR_ERR(sinfo->bus_clk);
894 if (IS_ERR(sinfo->bus_clk)) { 963 goto free_info;
895 ret = PTR_ERR(sinfo->bus_clk);
896 goto free_info;
897 }
898 } 964 }
899 sinfo->lcdc_clk = clk_get(dev, "lcdc_clk"); 965 sinfo->lcdc_clk = clk_get(dev, "lcdc_clk");
900 if (IS_ERR(sinfo->lcdc_clk)) { 966 if (IS_ERR(sinfo->lcdc_clk)) {
@@ -1055,8 +1121,7 @@ stop_clk:
1055 atmel_lcdfb_stop_clock(sinfo); 1121 atmel_lcdfb_stop_clock(sinfo);
1056 clk_put(sinfo->lcdc_clk); 1122 clk_put(sinfo->lcdc_clk);
1057put_bus_clk: 1123put_bus_clk:
1058 if (sinfo->bus_clk) 1124 clk_put(sinfo->bus_clk);
1059 clk_put(sinfo->bus_clk);
1060free_info: 1125free_info:
1061 framebuffer_release(info); 1126 framebuffer_release(info);
1062out: 1127out:
@@ -1081,8 +1146,7 @@ static int __exit atmel_lcdfb_remove(struct platform_device *pdev)
1081 unregister_framebuffer(info); 1146 unregister_framebuffer(info);
1082 atmel_lcdfb_stop_clock(sinfo); 1147 atmel_lcdfb_stop_clock(sinfo);
1083 clk_put(sinfo->lcdc_clk); 1148 clk_put(sinfo->lcdc_clk);
1084 if (sinfo->bus_clk) 1149 clk_put(sinfo->bus_clk);
1085 clk_put(sinfo->bus_clk);
1086 fb_dealloc_cmap(&info->cmap); 1150 fb_dealloc_cmap(&info->cmap);
1087 free_irq(sinfo->irq_base, info); 1151 free_irq(sinfo->irq_base, info);
1088 iounmap(sinfo->mmio); 1152 iounmap(sinfo->mmio);
@@ -1151,7 +1215,7 @@ static struct platform_driver atmel_lcdfb_driver = {
1151 .remove = __exit_p(atmel_lcdfb_remove), 1215 .remove = __exit_p(atmel_lcdfb_remove),
1152 .suspend = atmel_lcdfb_suspend, 1216 .suspend = atmel_lcdfb_suspend,
1153 .resume = atmel_lcdfb_resume, 1217 .resume = atmel_lcdfb_resume,
1154 1218 .id_table = atmel_lcdfb_devtypes,
1155 .driver = { 1219 .driver = {
1156 .name = "atmel_lcdfb", 1220 .name = "atmel_lcdfb",
1157 .owner = THIS_MODULE, 1221 .owner = THIS_MODULE,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-24 13:02:24 -0500