diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/stmmac/dwmac1000_dma.c | 10 | ||||
-rw-r--r-- | drivers/net/stmmac/dwmac100_dma.c | 10 |
2 files changed, 18 insertions, 2 deletions
diff --git a/drivers/net/stmmac/dwmac1000_dma.c b/drivers/net/stmmac/dwmac1000_dma.c index 2ef5a56370e9..ce6163e39cd5 100644 --- a/drivers/net/stmmac/dwmac1000_dma.c +++ b/drivers/net/stmmac/dwmac1000_dma.c | |||
@@ -33,10 +33,18 @@ static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx, | |||
33 | u32 dma_rx) | 33 | u32 dma_rx) |
34 | { | 34 | { |
35 | u32 value = readl(ioaddr + DMA_BUS_MODE); | 35 | u32 value = readl(ioaddr + DMA_BUS_MODE); |
36 | int limit; | ||
37 | |||
36 | /* DMA SW reset */ | 38 | /* DMA SW reset */ |
37 | value |= DMA_BUS_MODE_SFT_RESET; | 39 | value |= DMA_BUS_MODE_SFT_RESET; |
38 | writel(value, ioaddr + DMA_BUS_MODE); | 40 | writel(value, ioaddr + DMA_BUS_MODE); |
39 | do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)); | 41 | limit = 15000; |
42 | while (limit--) { | ||
43 | if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) | ||
44 | break; | ||
45 | } | ||
46 | if (limit < 0) | ||
47 | return -EBUSY; | ||
40 | 48 | ||
41 | value = /* DMA_BUS_MODE_FB | */ DMA_BUS_MODE_4PBL | | 49 | value = /* DMA_BUS_MODE_FB | */ DMA_BUS_MODE_4PBL | |
42 | ((pbl << DMA_BUS_MODE_PBL_SHIFT) | | 50 | ((pbl << DMA_BUS_MODE_PBL_SHIFT) | |
diff --git a/drivers/net/stmmac/dwmac100_dma.c b/drivers/net/stmmac/dwmac100_dma.c index c7279d2b946b..96aac93b789b 100644 --- a/drivers/net/stmmac/dwmac100_dma.c +++ b/drivers/net/stmmac/dwmac100_dma.c | |||
@@ -35,10 +35,18 @@ static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx, | |||
35 | u32 dma_rx) | 35 | u32 dma_rx) |
36 | { | 36 | { |
37 | u32 value = readl(ioaddr + DMA_BUS_MODE); | 37 | u32 value = readl(ioaddr + DMA_BUS_MODE); |
38 | int limit; | ||
39 | |||
38 | /* DMA SW reset */ | 40 | /* DMA SW reset */ |
39 | value |= DMA_BUS_MODE_SFT_RESET; | 41 | value |= DMA_BUS_MODE_SFT_RESET; |
40 | writel(value, ioaddr + DMA_BUS_MODE); | 42 | writel(value, ioaddr + DMA_BUS_MODE); |
41 | do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)); | 43 | limit = 15000; |
44 | while (limit--) { | ||
45 | if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) | ||
46 | break; | ||
47 | } | ||
48 | if (limit < 0) | ||
49 | return -EBUSY; | ||
42 | 50 | ||
43 | /* Enable Application Access by writing to DMA CSR0 */ | 51 | /* Enable Application Access by writing to DMA CSR0 */ |
44 | writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT), | 52 | writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT), |