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-rw-r--r--drivers/video/geode/lxfb.h377
-rw-r--r--drivers/video/geode/lxfb_core.c6
-rw-r--r--drivers/video/geode/lxfb_ops.c162
3 files changed, 353 insertions, 192 deletions
diff --git a/drivers/video/geode/lxfb.h b/drivers/video/geode/lxfb.h
index 60579f4d004a..6eac13d0ffb4 100644
--- a/drivers/video/geode/lxfb.h
+++ b/drivers/video/geode/lxfb.h
@@ -54,181 +54,342 @@ void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
54#define DC_SPARE_PIX8_PAN_FIX 0x00000010 54#define DC_SPARE_PIX8_PAN_FIX 0x00000010
55#define DC_SPARE_FIRST_REQ_MASK 0x00000002 55#define DC_SPARE_FIRST_REQ_MASK 0x00000002
56 56
57/* Registers */
58 57
59#define DC_UNLOCK 0x00 58/* Graphics Processor registers (table 6-29 from the data book) */
60#define DC_UNLOCK_CODE 0x4758 59enum gp_registers {
60 GP_DST_OFFSET = 0,
61 GP_SRC_OFFSET,
62 GP_STRIDE,
63 GP_WID_HEIGHT,
64
65 GP_SRC_COLOR_FG,
66 GP_SRC_COLOR_BG,
67 GP_PAT_COLOR_0,
68 GP_PAT_COLOR_1,
69
70 GP_PAT_COLOR_2,
71 GP_PAT_COLOR_3,
72 GP_PAT_COLOR_4,
73 GP_PAT_COLOR_5,
74
75 GP_PAT_DATA_0,
76 GP_PAT_DATA_1,
77 GP_RASTER_MODE,
78 GP_VECTOR_MODE,
79
80 GP_BLT_MODE,
81 GP_BLT_STATUS,
82 GP_HST_SRC,
83 GP_BASE_OFFSET,
84
85 GP_CMD_TOP,
86 GP_CMD_BOT,
87 GP_CMD_READ,
88 GP_CMD_WRITE,
89
90 GP_CH3_OFFSET,
91 GP_CH3_MODE_STR,
92 GP_CH3_WIDHI,
93 GP_CH3_HSRC,
94
95 GP_LUT_INDEX,
96 GP_LUT_DATA,
97 GP_INT_CNTRL, /* 0x78 */
98};
99
100#define GP_BLT_STATUS_CE (1 << 4) /* cmd buf empty */
101#define GP_BLT_STATUS_PB (1 << 0) /* primative busy */
102
103
104/* Display Controller registers (table 6-47 from the data book) */
105enum dc_registers {
106 DC_UNLOCK = 0,
107 DC_GENERAL_CFG,
108 DC_DISPLAY_CFG,
109 DC_ARB_CFG,
110
111 DC_FB_ST_OFFSET,
112 DC_CB_ST_OFFSET,
113 DC_CURS_ST_OFFSET,
114 DC_RSVD_0,
115
116 DC_VID_Y_ST_OFFSET,
117 DC_VID_U_ST_OFFSET,
118 DC_VID_V_ST_OFFSET,
119 DC_DV_TOP,
120
121 DC_LINE_SIZE,
122 DC_GFX_PITCH,
123 DC_VID_YUV_PITCH,
124 DC_RSVD_1,
125
126 DC_H_ACTIVE_TIMING,
127 DC_H_BLANK_TIMING,
128 DC_H_SYNC_TIMING,
129 DC_RSVD_2,
130
131 DC_V_ACTIVE_TIMING,
132 DC_V_BLANK_TIMING,
133 DC_V_SYNC_TIMING,
134 DC_FB_ACTIVE,
135
136 DC_CURSOR_X,
137 DC_CURSOR_Y,
138 DC_RSVD_3,
139 DC_LINE_CNT,
140
141 DC_PAL_ADDRESS,
142 DC_PAL_DATA,
143 DC_DFIFO_DIAG,
144 DC_CFIFO_DIAG,
145
146 DC_VID_DS_DELTA,
147 DC_GLIU0_MEM_OFFSET,
148 DC_DV_CTL,
149 DC_DV_ACCESS,
150
151 DC_GFX_SCALE,
152 DC_IRQ_FILT_CTL,
153 DC_FILT_COEFF1,
154 DC_FILT_COEFF2,
155
156 DC_VBI_EVEN_CTL,
157 DC_VBI_ODD_CTL,
158 DC_VBI_HOR,
159 DC_VBI_LN_ODD,
160
161 DC_VBI_LN_EVEN,
162 DC_VBI_PITCH,
163 DC_CLR_KEY,
164 DC_CLR_KEY_MASK,
165
166 DC_CLR_KEY_X,
167 DC_CLR_KEY_Y,
168 DC_IRQ,
169 DC_RSVD_4,
170
171 DC_RSVD_5,
172 DC_GENLK_CTL,
173 DC_VID_EVEN_Y_ST_OFFSET,
174 DC_VID_EVEN_U_ST_OFFSET,
175
176 DC_VID_EVEN_V_ST_OFFSET,
177 DC_V_ACTIVE_EVEN_TIMING,
178 DC_V_BLANK_EVEN_TIMING,
179 DC_V_SYNC_EVEN_TIMING, /* 0xec */
180};
181
182#define DC_UNLOCK_LOCK 0x00000000
183#define DC_UNLOCK_UNLOCK 0x00004758 /* magic value */
184
185#define DC_GENERAL_CFG_FDTY (1 << 17)
186#define DC_GENERAL_CFG_DFHPEL_SHIFT (12)
187#define DC_GENERAL_CFG_DFHPSL_SHIFT (8)
188#define DC_GENERAL_CFG_VGAE (1 << 7)
189#define DC_GENERAL_CFG_DECE (1 << 6)
190#define DC_GENERAL_CFG_CMPE (1 << 5)
191#define DC_GENERAL_CFG_VIDE (1 << 3)
192#define DC_GENERAL_CFG_DFLE (1 << 0)
61 193
62#define DC_GENERAL_CFG 0x04 194#define DC_DISPLAY_CFG_VISL (1 << 27)
63#define DC_GCFG_DFLE (1 << 0) 195#define DC_DISPLAY_CFG_PALB (1 << 25)
64#define DC_GCFG_VIDE (1 << 3) 196#define DC_DISPLAY_CFG_DCEN (1 << 24)
65#define DC_GCFG_VGAE (1 << 7) 197#define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9)
66#define DC_GCFG_CMPE (1 << 5) 198#define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8)
67#define DC_GCFG_DECE (1 << 6) 199#define DC_DISPLAY_CFG_DISP_MODE_8BPP (0)
68#define DC_GCFG_FDTY (1 << 17) 200#define DC_DISPLAY_CFG_TRUP (1 << 6)
201#define DC_DISPLAY_CFG_VDEN (1 << 4)
202#define DC_DISPLAY_CFG_GDEN (1 << 3)
203#define DC_DISPLAY_CFG_TGEN (1 << 0)
69 204
70#define DC_DISPLAY_CFG 0x08 205#define DC_DV_TOP_DV_TOP_EN (1 << 0)
71#define DC_DCFG_TGEN (1 << 0)
72#define DC_DCFG_GDEN (1 << 3)
73#define DC_DCFG_VDEN (1 << 4)
74#define DC_DCFG_TRUP (1 << 6)
75#define DC_DCFG_DCEN (1 << 24)
76#define DC_DCFG_PALB (1 << 25)
77#define DC_DCFG_VISL (1 << 27)
78 206
79#define DC_DCFG_16BPP 0x0 207#define DC_DV_CTL_DV_LINE_SIZE ((1 << 10) | (1 << 11))
208#define DC_DV_CTL_DV_LINE_SIZE_1K (0)
209#define DC_DV_CTL_DV_LINE_SIZE_2K (1 << 10)
210#define DC_DV_CTL_DV_LINE_SIZE_4K (1 << 11)
211#define DC_DV_CTL_DV_LINE_SIZE_8K ((1 << 10) | (1 << 11))
80 212
81#define DC_DCFG_DISP_MODE_MASK 0x00000300 213#define DC_CLR_KEY_CLR_KEY_EN (1 << 24)
82#define DC_DCFG_DISP_MODE_8BPP 0x00000000
83#define DC_DCFG_DISP_MODE_16BPP 0x00000100
84#define DC_DCFG_DISP_MODE_24BPP 0x00000200
85#define DC_DCFG_DISP_MODE_32BPP 0x00000300
86 214
215#define DC_IRQ_VIP_VSYNC_IRQ_STATUS (1 << 21) /* undocumented? */
216#define DC_IRQ_STATUS (1 << 20) /* undocumented? */
217#define DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK (1 << 1)
218#define DC_IRQ_MASK (1 << 0)
87 219
88#define DC_ARB_CFG 0x0C 220#define DC_GENLK_CTL_FLICK_SEL_MASK (0x0F << 28)
221#define DC_GENLK_CTL_ALPHA_FLICK_EN (1 << 25)
222#define DC_GENLK_CTL_FLICK_EN (1 << 24)
223#define DC_GENLK_CTL_GENLK_EN (1 << 18)
89 224
90#define DC_FB_START 0x10
91#define DC_CB_START 0x14
92#define DC_CURSOR_START 0x18
93 225
94#define DC_DV_TOP 0x2C 226/*
95#define DC_DV_TOP_ENABLE (1 << 0) 227 * Video Processor registers (table 6-71).
228 * There is space for 64 bit values, but we never use more than the
229 * lower 32 bits. The actual register save/restore code only bothers
230 * to restore those 32 bits.
231 */
232enum vp_registers {
233 VP_VCFG = 0,
234 VP_DCFG,
96 235
97#define DC_LINE_SIZE 0x30 236 VP_VX,
98#define DC_GRAPHICS_PITCH 0x34 237 VP_VY,
99#define DC_H_ACTIVE_TIMING 0x40
100#define DC_H_BLANK_TIMING 0x44
101#define DC_H_SYNC_TIMING 0x48
102#define DC_V_ACTIVE_TIMING 0x50
103#define DC_V_BLANK_TIMING 0x54
104#define DC_V_SYNC_TIMING 0x58
105#define DC_FB_ACTIVE 0x5C
106 238
107#define DC_PAL_ADDRESS 0x70 239 VP_SCL,
108#define DC_PAL_DATA 0x74 240 VP_VCK,
109 241
110#define DC_PHY_MEM_OFFSET 0x84 242 VP_VCM,
243 VP_PAR,
111 244
112#define DC_DV_CTL 0x88 245 VP_PDR,
113#define DC_DV_LINE_SIZE_MASK 0x00000C00 246 VP_SLR,
114#define DC_DV_LINE_SIZE_1024 0x00000000
115#define DC_DV_LINE_SIZE_2048 0x00000400
116#define DC_DV_LINE_SIZE_4096 0x00000800
117#define DC_DV_LINE_SIZE_8192 0x00000C00
118 247
248 VP_MISC,
249 VP_CCS,
119 250
120#define DC_GFX_SCALE 0x90 251 VP_VYS,
121#define DC_IRQ_FILT_CTL 0x94 252 VP_VXS,
122 253
254 VP_RSVD_0,
255 VP_VDC,
123 256
124#define DC_IRQ 0xC8 257 VP_RSVD_1,
125#define DC_IRQ_MASK (1 << 0) 258 VP_CRC,
126#define DC_VSYNC_IRQ_MASK (1 << 1)
127#define DC_IRQ_STATUS (1 << 20)
128#define DC_VSYNC_IRQ_STATUS (1 << 21)
129 259
130#define DC_GENLCK_CTRL 0xD4 260 VP_CRC32,
131#define DC_GENLCK_ENABLE (1 << 18) 261 VP_VDE,
132#define DC_GC_ALPHA_FLICK_ENABLE (1 << 25)
133#define DC_GC_FLICKER_FILTER_ENABLE (1 << 24)
134#define DC_GC_FLICKER_FILTER_MASK (0x0F << 28)
135 262
136#define DC_COLOR_KEY 0xB8 263 VP_CCK,
137#define DC_CLR_KEY_ENABLE (1 << 24) 264 VP_CCM,
138 265
266 VP_CC1,
267 VP_CC2,
139 268
140#define DC3_DV_LINE_SIZE_MASK 0x00000C00 269 VP_A1X,
141#define DC3_DV_LINE_SIZE_1024 0x00000000 270 VP_A1Y,
142#define DC3_DV_LINE_SIZE_2048 0x00000400
143#define DC3_DV_LINE_SIZE_4096 0x00000800
144#define DC3_DV_LINE_SIZE_8192 0x00000C00
145 271
146#define DF_VIDEO_CFG 0x0 272 VP_A1C,
147#define DF_VCFG_VID_EN (1 << 0) 273 VP_A1T,
148 274
149#define DF_DISPLAY_CFG 0x08 275 VP_A2X,
276 VP_A2Y,
150 277
151#define DF_DCFG_CRT_EN (1 << 0) 278 VP_A2C,
152#define DF_DCFG_HSYNC_EN (1 << 1) 279 VP_A2T,
153#define DF_DCFG_VSYNC_EN (1 << 2)
154#define DF_DCFG_DAC_BL_EN (1 << 3)
155#define DF_DCFG_CRT_HSYNC_POL (1 << 8)
156#define DF_DCFG_CRT_VSYNC_POL (1 << 9)
157#define DF_DCFG_GV_PAL_BYP (1 << 21)
158 280
159#define DF_DCFG_CRT_SYNC_SKW_INIT 0x10000 281 VP_A3X,
160#define DF_DCFG_CRT_SYNC_SKW_MASK 0x1c000 282 VP_A3Y,
161 283
162#define DF_DCFG_PWR_SEQ_DLY_INIT 0x80000 284 VP_A3C,
163#define DF_DCFG_PWR_SEQ_DLY_MASK 0xe0000 285 VP_A3T,
286
287 VP_VRR,
288 VP_AWT,
289
290 VP_VTM,
291 VP_VYE,
292
293 VP_A1YE,
294 VP_A2YE,
295
296 VP_A3YE, /* 0x150 */
297};
164 298
165#define DF_MISC 0x50 299#define VP_VCFG_VID_EN (1 << 0)
166 300
167#define DF_MISC_GAM_BYPASS (1 << 0) 301#define VP_DCFG_GV_GAM (1 << 21)
168#define DF_MISC_DAC_PWRDN (1 << 10) 302#define VP_DCFG_PWR_SEQ_DELAY ((1 << 17) | (1 << 18) | (1 << 19))
169#define DF_MISC_A_PWRDN (1 << 11) 303#define VP_DCFG_PWR_SEQ_DELAY_DEFAULT (1 << 19) /* undocumented */
304#define VP_DCFG_CRT_SYNC_SKW ((1 << 14) | (1 << 15) | (1 << 16))
305#define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16)
306#define VP_DCFG_CRT_VSYNC_POL (1 << 9)
307#define VP_DCFG_CRT_HSYNC_POL (1 << 8)
308#define VP_DCFG_DAC_BL_EN (1 << 3)
309#define VP_DCFG_VSYNC_EN (1 << 2)
310#define VP_DCFG_HSYNC_EN (1 << 1)
311#define VP_DCFG_CRT_EN (1 << 0)
170 312
171#define DF_PAR 0x38 313#define VP_MISC_APWRDN (1 << 11)
172#define DF_PDR 0x40 314#define VP_MISC_DACPWRDN (1 << 10)
173#define DF_ALPHA_CONTROL_1 0xD8 315#define VP_MISC_BYP_BOTH (1 << 0)
174#define DF_VIDEO_REQUEST 0x120
175 316
176#define DF_PANEL_TIM1 0x400
177#define DF_DEFAULT_TFT_PMTIM1 0x0
178 317
179#define DF_PANEL_TIM2 0x408 318/*
180#define DF_DEFAULT_TFT_PMTIM2 0x08000000 319 * Flat Panel registers (table 6-71).
320 * Also 64 bit registers; see above note about 32-bit handling.
321 */
322
323/* we're actually in the VP register space, starting at address 0x400 */
324#define VP_FP_START 0x400
325
326enum fp_registers {
327 FP_PT1 = 0,
328 FP_PT2,
329
330 FP_PM,
331 FP_DFC,
332
333 FP_RSVD_0,
334 FP_RSVD_1,
335
336 FP_RSVD_2,
337 FP_RSVD_3,
338
339 FP_RSVD_4,
340 FP_DCA,
341
342 FP_DMD,
343 FP_CRC, /* 0x458 */
344};
345
346#define FP_PT2_SCRC (1 << 27) /* shfclk free */
181 347
182#define DF_FP_PM 0x410 348#define FP_PM_P (1 << 24) /* panel power ctl */
183#define DF_FP_PM_P (1 << 24)
184 349
185#define DF_DITHER_CONTROL 0x418 350#define FP_DFC_BC ((1 << 4) | (1 << 5) | (1 << 6))
186#define DF_DEFAULT_TFT_DITHCTL 0x00000070
187#define GP_BLT_STATUS 0x44
188#define GP_BS_BLT_BUSY (1 << 0)
189#define GP_BS_CB_EMPTY (1 << 4)
190 351
191 352
192/* register access functions */ 353/* register access functions */
193 354
194static inline uint32_t read_gp(struct lxfb_par *par, int reg) 355static inline uint32_t read_gp(struct lxfb_par *par, int reg)
195{ 356{
196 return readl(par->gp_regs + reg); 357 return readl(par->gp_regs + 4*reg);
197} 358}
198 359
199static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val) 360static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val)
200{ 361{
201 writel(val, par->gp_regs + reg); 362 writel(val, par->gp_regs + 4*reg);
202} 363}
203 364
204static inline uint32_t read_dc(struct lxfb_par *par, int reg) 365static inline uint32_t read_dc(struct lxfb_par *par, int reg)
205{ 366{
206 return readl(par->dc_regs + reg); 367 return readl(par->dc_regs + 4*reg);
207} 368}
208 369
209static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val) 370static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val)
210{ 371{
211 writel(val, par->dc_regs + reg); 372 writel(val, par->dc_regs + 4*reg);
212} 373}
213 374
214static inline uint32_t read_vp(struct lxfb_par *par, int reg) 375static inline uint32_t read_vp(struct lxfb_par *par, int reg)
215{ 376{
216 return readl(par->df_regs + reg); 377 return readl(par->df_regs + 8*reg);
217} 378}
218 379
219static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val) 380static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val)
220{ 381{
221 writel(val, par->df_regs + reg); 382 writel(val, par->df_regs + 8*reg);
222} 383}
223 384
224static inline uint32_t read_fp(struct lxfb_par *par, int reg) 385static inline uint32_t read_fp(struct lxfb_par *par, int reg)
225{ 386{
226 return readl(par->df_regs + reg); 387 return readl(par->df_regs + 8*reg + VP_FP_START);
227} 388}
228 389
229static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val) 390static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
230{ 391{
231 writel(val, par->df_regs + reg); 392 writel(val, par->df_regs + 8*reg + VP_FP_START);
232} 393}
233 394
234#endif 395#endif
diff --git a/drivers/video/geode/lxfb_core.c b/drivers/video/geode/lxfb_core.c
index a1d14e0c3aa9..acf1bf64e782 100644
--- a/drivers/video/geode/lxfb_core.c
+++ b/drivers/video/geode/lxfb_core.c
@@ -366,9 +366,9 @@ static int __init lxfb_map_video_memory(struct fb_info *info,
366 if (par->df_regs == NULL) 366 if (par->df_regs == NULL)
367 return ret; 367 return ret;
368 368
369 write_dc(par, DC_UNLOCK, DC_UNLOCK_CODE); 369 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
370 write_dc(par, DC_PHY_MEM_OFFSET, info->fix.smem_start & 0xFF000000); 370 write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000);
371 write_dc(par, DC_UNLOCK, 0); 371 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
372 372
373 dev_info(&dev->dev, "%d KB of video memory at 0x%lx\n", 373 dev_info(&dev->dev, "%d KB of video memory at 0x%lx\n",
374 info->fix.smem_len / 1024, info->fix.smem_start); 374 info->fix.smem_len / 1024, info->fix.smem_start);
diff --git a/drivers/video/geode/lxfb_ops.c b/drivers/video/geode/lxfb_ops.c
index d1210e2d3894..7be6f578e87e 100644
--- a/drivers/video/geode/lxfb_ops.c
+++ b/drivers/video/geode/lxfb_ops.c
@@ -210,47 +210,47 @@ static void lx_graphics_disable(struct fb_info *info)
210 210
211 /* Note: This assumes that the video is in a quitet state */ 211 /* Note: This assumes that the video is in a quitet state */
212 212
213 write_vp(par, DF_ALPHA_CONTROL_1, 0); 213 write_vp(par, VP_A1T, 0);
214 write_vp(par, DF_ALPHA_CONTROL_1 + 32, 0); 214 write_vp(par, VP_A2T, 0);
215 write_vp(par, DF_ALPHA_CONTROL_1 + 64, 0); 215 write_vp(par, VP_A3T, 0);
216 216
217 /* Turn off the VGA and video enable */ 217 /* Turn off the VGA and video enable */
218 val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GCFG_VGAE | DC_GCFG_VIDE); 218 val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GENERAL_CFG_VGAE |
219 DC_GENERAL_CFG_VIDE);
219 220
220 write_dc(par, DC_GENERAL_CFG, val); 221 write_dc(par, DC_GENERAL_CFG, val);
221 222
222 val = read_vp(par, DF_VIDEO_CFG) & ~DF_VCFG_VID_EN; 223 val = read_vp(par, VP_VCFG) & ~VP_VCFG_VID_EN;
223 write_vp(par, DF_VIDEO_CFG, val); 224 write_vp(par, VP_VCFG, val);
224 225
225 write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_VSYNC_IRQ_MASK | DC_IRQ_STATUS | 226 write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK |
226 DC_VSYNC_IRQ_STATUS); 227 DC_IRQ_STATUS | DC_IRQ_VIP_VSYNC_IRQ_STATUS);
227 228
228 val = read_dc(par, DC_GENLCK_CTRL) & ~DC_GENLCK_ENABLE; 229 val = read_dc(par, DC_GENLK_CTL) & ~DC_GENLK_CTL_GENLK_EN;
229 write_dc(par, DC_GENLCK_CTRL, val); 230 write_dc(par, DC_GENLK_CTL, val);
230 231
231 val = read_dc(par, DC_COLOR_KEY) & ~DC_CLR_KEY_ENABLE; 232 val = read_dc(par, DC_CLR_KEY);
232 write_dc(par, DC_COLOR_KEY, val & ~DC_CLR_KEY_ENABLE); 233 write_dc(par, DC_CLR_KEY, val & ~DC_CLR_KEY_CLR_KEY_EN);
233 234
234 /* We don't actually blank the panel, due to the long latency 235 /* We don't actually blank the panel, due to the long latency
235 involved with bringing it back */ 236 involved with bringing it back */
236 237
237 val = read_vp(par, DF_MISC) | DF_MISC_DAC_PWRDN; 238 val = read_vp(par, VP_MISC) | VP_MISC_DACPWRDN;
238 write_vp(par, DF_MISC, val); 239 write_vp(par, VP_MISC, val);
239 240
240 /* Turn off the display */ 241 /* Turn off the display */
241 242
242 val = read_vp(par, DF_DISPLAY_CFG); 243 val = read_vp(par, VP_DCFG);
243 write_vp(par, DF_DISPLAY_CFG, val & 244 write_vp(par, VP_DCFG, val & ~(VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN |
244 ~(DF_DCFG_CRT_EN | DF_DCFG_HSYNC_EN | 245 VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN));
245 DF_DCFG_VSYNC_EN | DF_DCFG_DAC_BL_EN));
246 246
247 gcfg = read_dc(par, DC_GENERAL_CFG); 247 gcfg = read_dc(par, DC_GENERAL_CFG);
248 gcfg &= ~(DC_GCFG_CMPE | DC_GCFG_DECE); 248 gcfg &= ~(DC_GENERAL_CFG_CMPE | DC_GENERAL_CFG_DECE);
249 write_dc(par, DC_GENERAL_CFG, gcfg); 249 write_dc(par, DC_GENERAL_CFG, gcfg);
250 250
251 /* Turn off the TGEN */ 251 /* Turn off the TGEN */
252 val = read_dc(par, DC_DISPLAY_CFG); 252 val = read_dc(par, DC_DISPLAY_CFG);
253 val &= ~DC_DCFG_TGEN; 253 val &= ~DC_DISPLAY_CFG_TGEN;
254 write_dc(par, DC_DISPLAY_CFG, val); 254 write_dc(par, DC_DISPLAY_CFG, val);
255 255
256 /* Wait 1000 usecs to ensure that the TGEN is clear */ 256 /* Wait 1000 usecs to ensure that the TGEN is clear */
@@ -258,14 +258,14 @@ static void lx_graphics_disable(struct fb_info *info)
258 258
259 /* Turn off the FIFO loader */ 259 /* Turn off the FIFO loader */
260 260
261 gcfg &= ~DC_GCFG_DFLE; 261 gcfg &= ~DC_GENERAL_CFG_DFLE;
262 write_dc(par, DC_GENERAL_CFG, gcfg); 262 write_dc(par, DC_GENERAL_CFG, gcfg);
263 263
264 /* Lastly, wait for the GP to go idle */ 264 /* Lastly, wait for the GP to go idle */
265 265
266 do { 266 do {
267 val = read_gp(par, GP_BLT_STATUS); 267 val = read_gp(par, GP_BLT_STATUS);
268 } while ((val & GP_BS_BLT_BUSY) || !(val & GP_BS_CB_EMPTY)); 268 } while ((val & GP_BLT_STATUS_PB) || !(val & GP_BLT_STATUS_CE));
269} 269}
270 270
271static void lx_graphics_enable(struct fb_info *info) 271static void lx_graphics_enable(struct fb_info *info)
@@ -274,30 +274,30 @@ static void lx_graphics_enable(struct fb_info *info)
274 u32 temp, config; 274 u32 temp, config;
275 275
276 /* Set the video request register */ 276 /* Set the video request register */
277 write_vp(par, DF_VIDEO_REQUEST, 0); 277 write_vp(par, VP_VRR, 0);
278 278
279 /* Set up the polarities */ 279 /* Set up the polarities */
280 280
281 config = read_vp(par, DF_DISPLAY_CFG); 281 config = read_vp(par, VP_DCFG);
282 282
283 config &= ~(DF_DCFG_CRT_SYNC_SKW_MASK | DF_DCFG_PWR_SEQ_DLY_MASK | 283 config &= ~(VP_DCFG_CRT_SYNC_SKW | VP_DCFG_PWR_SEQ_DELAY |
284 DF_DCFG_CRT_HSYNC_POL | DF_DCFG_CRT_VSYNC_POL); 284 VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL);
285 285
286 config |= (DF_DCFG_CRT_SYNC_SKW_INIT | DF_DCFG_PWR_SEQ_DLY_INIT | 286 config |= (VP_DCFG_CRT_SYNC_SKW_DEFAULT | VP_DCFG_PWR_SEQ_DELAY_DEFAULT
287 DF_DCFG_GV_PAL_BYP); 287 | VP_DCFG_GV_GAM);
288 288
289 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 289 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
290 config |= DF_DCFG_CRT_HSYNC_POL; 290 config |= VP_DCFG_CRT_HSYNC_POL;
291 291
292 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 292 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
293 config |= DF_DCFG_CRT_VSYNC_POL; 293 config |= VP_DCFG_CRT_VSYNC_POL;
294 294
295 if (par->output & OUTPUT_PANEL) { 295 if (par->output & OUTPUT_PANEL) {
296 u32 msrlo, msrhi; 296 u32 msrlo, msrhi;
297 297
298 write_fp(par, DF_PANEL_TIM1, DF_DEFAULT_TFT_PMTIM1); 298 write_fp(par, FP_PT1, 0);
299 write_fp(par, DF_PANEL_TIM2, DF_DEFAULT_TFT_PMTIM2); 299 write_fp(par, FP_PT2, FP_PT2_SCRC);
300 write_fp(par, DF_DITHER_CONTROL, DF_DEFAULT_TFT_DITHCTL); 300 write_fp(par, FP_DFC, FP_DFC_BC);
301 301
302 msrlo = DF_DEFAULT_TFT_PAD_SEL_LOW; 302 msrlo = DF_DEFAULT_TFT_PAD_SEL_LOW;
303 msrhi = DF_DEFAULT_TFT_PAD_SEL_HIGH; 303 msrhi = DF_DEFAULT_TFT_PAD_SEL_HIGH;
@@ -306,27 +306,27 @@ static void lx_graphics_enable(struct fb_info *info)
306 } 306 }
307 307
308 if (par->output & OUTPUT_CRT) { 308 if (par->output & OUTPUT_CRT) {
309 config |= DF_DCFG_CRT_EN | DF_DCFG_HSYNC_EN | 309 config |= VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN |
310 DF_DCFG_VSYNC_EN | DF_DCFG_DAC_BL_EN; 310 VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN;
311 } 311 }
312 312
313 write_vp(par, DF_DISPLAY_CFG, config); 313 write_vp(par, VP_DCFG, config);
314 314
315 /* Turn the CRT dacs back on */ 315 /* Turn the CRT dacs back on */
316 316
317 if (par->output & OUTPUT_CRT) { 317 if (par->output & OUTPUT_CRT) {
318 temp = read_vp(par, DF_MISC); 318 temp = read_vp(par, VP_MISC);
319 temp &= ~(DF_MISC_DAC_PWRDN | DF_MISC_A_PWRDN); 319 temp &= ~(VP_MISC_DACPWRDN | VP_MISC_APWRDN);
320 write_vp(par, DF_MISC, temp); 320 write_vp(par, VP_MISC, temp);
321 } 321 }
322 322
323 /* Turn the panel on (if it isn't already) */ 323 /* Turn the panel on (if it isn't already) */
324 324
325 if (par->output & OUTPUT_PANEL) { 325 if (par->output & OUTPUT_PANEL) {
326 temp = read_fp(par, DF_FP_PM); 326 temp = read_fp(par, FP_PM);
327 327
328 if (!(temp & 0x09)) 328 if (!(temp & 0x09))
329 write_fp(par, DF_FP_PM, temp | DF_FP_PM_P); 329 write_fp(par, FP_PM, temp | FP_PM_P);
330 } 330 }
331} 331}
332 332
@@ -357,7 +357,7 @@ void lx_set_mode(struct fb_info *info)
357 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; 357 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
358 358
359 /* Unlock the DC registers */ 359 /* Unlock the DC registers */
360 write_dc(par, DC_UNLOCK, DC_UNLOCK_CODE); 360 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
361 361
362 lx_graphics_disable(info); 362 lx_graphics_disable(info);
363 363
@@ -384,45 +384,45 @@ void lx_set_mode(struct fb_info *info)
384 /* Clear the various buffers */ 384 /* Clear the various buffers */
385 /* FIXME: Adjust for panning here */ 385 /* FIXME: Adjust for panning here */
386 386
387 write_dc(par, DC_FB_START, 0); 387 write_dc(par, DC_FB_ST_OFFSET, 0);
388 write_dc(par, DC_CB_START, 0); 388 write_dc(par, DC_CB_ST_OFFSET, 0);
389 write_dc(par, DC_CURSOR_START, 0); 389 write_dc(par, DC_CURS_ST_OFFSET, 0);
390 390
391 /* FIXME: Add support for interlacing */ 391 /* FIXME: Add support for interlacing */
392 /* FIXME: Add support for scaling */ 392 /* FIXME: Add support for scaling */
393 393
394 val = read_dc(par, DC_GENLCK_CTRL); 394 val = read_dc(par, DC_GENLK_CTL);
395 val &= ~(DC_GC_ALPHA_FLICK_ENABLE | 395 val &= ~(DC_GENLK_CTL_ALPHA_FLICK_EN | DC_GENLK_CTL_FLICK_EN |
396 DC_GC_FLICKER_FILTER_ENABLE | DC_GC_FLICKER_FILTER_MASK); 396 DC_GENLK_CTL_FLICK_SEL_MASK);
397 397
398 /* Default scaling params */ 398 /* Default scaling params */
399 399
400 write_dc(par, DC_GFX_SCALE, (0x4000 << 16) | 0x4000); 400 write_dc(par, DC_GFX_SCALE, (0x4000 << 16) | 0x4000);
401 write_dc(par, DC_IRQ_FILT_CTL, 0); 401 write_dc(par, DC_IRQ_FILT_CTL, 0);
402 write_dc(par, DC_GENLCK_CTRL, val); 402 write_dc(par, DC_GENLK_CTL, val);
403 403
404 /* FIXME: Support compression */ 404 /* FIXME: Support compression */
405 405
406 if (info->fix.line_length > 4096) 406 if (info->fix.line_length > 4096)
407 dv = DC_DV_LINE_SIZE_8192; 407 dv = DC_DV_CTL_DV_LINE_SIZE_8K;
408 else if (info->fix.line_length > 2048) 408 else if (info->fix.line_length > 2048)
409 dv = DC_DV_LINE_SIZE_4096; 409 dv = DC_DV_CTL_DV_LINE_SIZE_4K;
410 else if (info->fix.line_length > 1024) 410 else if (info->fix.line_length > 1024)
411 dv = DC_DV_LINE_SIZE_2048; 411 dv = DC_DV_CTL_DV_LINE_SIZE_2K;
412 else 412 else
413 dv = DC_DV_LINE_SIZE_1024; 413 dv = DC_DV_CTL_DV_LINE_SIZE_1K;
414 414
415 max = info->fix.line_length * info->var.yres; 415 max = info->fix.line_length * info->var.yres;
416 max = (max + 0x3FF) & 0xFFFFFC00; 416 max = (max + 0x3FF) & 0xFFFFFC00;
417 417
418 write_dc(par, DC_DV_TOP, max | DC_DV_TOP_ENABLE); 418 write_dc(par, DC_DV_TOP, max | DC_DV_TOP_DV_TOP_EN);
419 419
420 val = read_dc(par, DC_DV_CTL) & ~DC_DV_LINE_SIZE_MASK; 420 val = read_dc(par, DC_DV_CTL) & ~DC_DV_CTL_DV_LINE_SIZE;
421 write_dc(par, DC_DV_CTL, val | dv); 421 write_dc(par, DC_DV_CTL, val | dv);
422 422
423 size = info->var.xres * (info->var.bits_per_pixel >> 3); 423 size = info->var.xres * (info->var.bits_per_pixel >> 3);
424 424
425 write_dc(par, DC_GRAPHICS_PITCH, info->fix.line_length >> 3); 425 write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
426 write_dc(par, DC_LINE_SIZE, (size + 7) >> 3); 426 write_dc(par, DC_LINE_SIZE, (size + 7) >> 3);
427 427
428 /* Set default watermark values */ 428 /* Set default watermark values */
@@ -435,32 +435,33 @@ void lx_set_mode(struct fb_info *info)
435 msrval |= DC_SPARE_DISABLE_VFIFO_WM | DC_SPARE_DISABLE_INIT_VID_PRI; 435 msrval |= DC_SPARE_DISABLE_VFIFO_WM | DC_SPARE_DISABLE_INIT_VID_PRI;
436 wrmsrl(MSR_LX_SPARE_MSR, msrval); 436 wrmsrl(MSR_LX_SPARE_MSR, msrval);
437 437
438 gcfg = DC_GCFG_DFLE; /* Display fifo enable */ 438 gcfg = DC_GENERAL_CFG_DFLE; /* Display fifo enable */
439 gcfg |= 0xB600; /* Set default priority */ 439 gcfg |= (0x6 << DC_GENERAL_CFG_DFHPSL_SHIFT) | /* default priority */
440 gcfg |= DC_GCFG_FDTY; /* Set the frame dirty mode */ 440 (0xb << DC_GENERAL_CFG_DFHPEL_SHIFT);
441 gcfg |= DC_GENERAL_CFG_FDTY; /* Set the frame dirty mode */
441 442
442 dcfg = DC_DCFG_VDEN; /* Enable video data */ 443 dcfg = DC_DISPLAY_CFG_VDEN; /* Enable video data */
443 dcfg |= DC_DCFG_GDEN; /* Enable graphics */ 444 dcfg |= DC_DISPLAY_CFG_GDEN; /* Enable graphics */
444 dcfg |= DC_DCFG_TGEN; /* Turn on the timing generator */ 445 dcfg |= DC_DISPLAY_CFG_TGEN; /* Turn on the timing generator */
445 dcfg |= DC_DCFG_TRUP; /* Update timings immediately */ 446 dcfg |= DC_DISPLAY_CFG_TRUP; /* Update timings immediately */
446 dcfg |= DC_DCFG_PALB; /* Palette bypass in > 8 bpp modes */ 447 dcfg |= DC_DISPLAY_CFG_PALB; /* Palette bypass in > 8 bpp modes */
447 dcfg |= DC_DCFG_VISL; 448 dcfg |= DC_DISPLAY_CFG_VISL;
448 dcfg |= DC_DCFG_DCEN; /* Always center the display */ 449 dcfg |= DC_DISPLAY_CFG_DCEN; /* Always center the display */
449 450
450 /* Set the current BPP mode */ 451 /* Set the current BPP mode */
451 452
452 switch (info->var.bits_per_pixel) { 453 switch (info->var.bits_per_pixel) {
453 case 8: 454 case 8:
454 dcfg |= DC_DCFG_DISP_MODE_8BPP; 455 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
455 break; 456 break;
456 457
457 case 16: 458 case 16:
458 dcfg |= DC_DCFG_DISP_MODE_16BPP | DC_DCFG_16BPP; 459 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
459 break; 460 break;
460 461
461 case 32: 462 case 32:
462 case 24: 463 case 24:
463 dcfg |= DC_DCFG_DISP_MODE_24BPP; 464 dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
464 break; 465 break;
465 } 466 }
466 467
@@ -504,7 +505,7 @@ void lx_set_mode(struct fb_info *info)
504 write_dc(par, DC_GENERAL_CFG, gcfg); 505 write_dc(par, DC_GENERAL_CFG, gcfg);
505 506
506 /* Lock the DC registers */ 507 /* Lock the DC registers */
507 write_dc(par, DC_UNLOCK, 0); 508 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
508} 509}
509 510
510void lx_set_palette_reg(struct fb_info *info, unsigned regno, 511void lx_set_palette_reg(struct fb_info *info, unsigned regno,
@@ -550,26 +551,25 @@ int lx_blank_display(struct fb_info *info, int blank_mode)
550 return -EINVAL; 551 return -EINVAL;
551 } 552 }
552 553
553 dcfg = read_vp(par, DF_DISPLAY_CFG); 554 dcfg = read_vp(par, VP_DCFG);
554 dcfg &= ~(DF_DCFG_DAC_BL_EN 555 dcfg &= ~(VP_DCFG_DAC_BL_EN | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN);
555 | DF_DCFG_HSYNC_EN | DF_DCFG_VSYNC_EN);
556 if (!blank) 556 if (!blank)
557 dcfg |= DF_DCFG_DAC_BL_EN; 557 dcfg |= VP_DCFG_DAC_BL_EN;
558 if (hsync) 558 if (hsync)
559 dcfg |= DF_DCFG_HSYNC_EN; 559 dcfg |= VP_DCFG_HSYNC_EN;
560 if (vsync) 560 if (vsync)
561 dcfg |= DF_DCFG_VSYNC_EN; 561 dcfg |= VP_DCFG_VSYNC_EN;
562 write_vp(par, DF_DISPLAY_CFG, dcfg); 562 write_vp(par, VP_DCFG, dcfg);
563 563
564 /* Power on/off flat panel */ 564 /* Power on/off flat panel */
565 565
566 if (par->output & OUTPUT_PANEL) { 566 if (par->output & OUTPUT_PANEL) {
567 fp_pm = read_fp(par, DF_FP_PM); 567 fp_pm = read_fp(par, FP_PM);
568 if (blank_mode == FB_BLANK_POWERDOWN) 568 if (blank_mode == FB_BLANK_POWERDOWN)
569 fp_pm &= ~DF_FP_PM_P; 569 fp_pm &= ~FP_PM_P;
570 else 570 else
571 fp_pm |= DF_FP_PM_P; 571 fp_pm |= FP_PM_P;
572 write_fp(par, DF_FP_PM, fp_pm); 572 write_fp(par, FP_PM, fp_pm);
573 } 573 }
574 574
575 return 0; 575 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 10:24:39 -0500