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-rw-r--r--drivers/net/tg3.c17
-rw-r--r--drivers/net/tg3.h1
2 files changed, 17 insertions, 1 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 501ea6da03cc..27c73b9ec2d0 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -959,6 +959,13 @@ static int tg3_phy_reset(struct tg3 *tp)
959 u32 phy_status; 959 u32 phy_status;
960 int err; 960 int err;
961 961
962 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
963 u32 val;
964
965 val = tr32(GRC_MISC_CFG);
966 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
967 udelay(40);
968 }
962 err = tg3_readphy(tp, MII_BMSR, &phy_status); 969 err = tg3_readphy(tp, MII_BMSR, &phy_status);
963 err |= tg3_readphy(tp, MII_BMSR, &phy_status); 970 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
964 if (err != 0) 971 if (err != 0)
@@ -1170,7 +1177,15 @@ static void tg3_power_down_phy(struct tg3 *tp)
1170 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) 1177 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
1171 return; 1178 return;
1172 1179
1173 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) { 1180 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1181 u32 val;
1182
1183 tg3_bmcr_reset(tp);
1184 val = tr32(GRC_MISC_CFG);
1185 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1186 udelay(40);
1187 return;
1188 } else {
1174 tg3_writephy(tp, MII_TG3_EXT_CTRL, 1189 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1175 MII_TG3_EXT_CTRL_FORCE_LED_OFF); 1190 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1176 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2); 1191 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index dfaf4ed127bd..cf78a7e5997b 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1350,6 +1350,7 @@
1350#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000 1350#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1351#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000 1351#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1352#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 1352#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1353#define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
1353#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000 1354#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1354#define GRC_LOCAL_CTRL 0x00006808 1355#define GRC_LOCAL_CTRL 0x00006808
1355#define GRC_LCLCTRL_INT_ACTIVE 0x00000001 1356#define GRC_LCLCTRL_INT_ACTIVE 0x00000001