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-rw-r--r--drivers/gpu/drm/Kconfig18
-rw-r--r--drivers/gpu/drm/Makefile8
-rw-r--r--drivers/gpu/drm/drm_bufs.c4
-rw-r--r--drivers/gpu/drm/drm_cache.c46
-rw-r--r--drivers/gpu/drm/drm_crtc.c77
-rw-r--r--drivers/gpu/drm/drm_crtc_helper.c223
-rw-r--r--drivers/gpu/drm/drm_drv.c4
-rw-r--r--drivers/gpu/drm/drm_edid.c504
-rw-r--r--drivers/gpu/drm/drm_encoder_slave.c116
-rw-r--r--drivers/gpu/drm/drm_fb_helper.c707
-rw-r--r--drivers/gpu/drm/drm_gem.c11
-rw-r--r--drivers/gpu/drm/drm_irq.c27
-rw-r--r--drivers/gpu/drm/drm_mm.c21
-rw-r--r--drivers/gpu/drm/drm_modes.c435
-rw-r--r--drivers/gpu/drm/drm_proc.c17
-rw-r--r--drivers/gpu/drm/drm_sysfs.c28
-rw-r--r--drivers/gpu/drm/i915/Makefile2
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c (renamed from drivers/gpu/drm/i915/i915_gem_debugfs.c)91
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c120
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c9
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h63
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c14
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c80
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c21
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h144
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c4
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c8
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c28
-rw-r--r--drivers/gpu/drm/i915/intel_display.c624
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h8
-rw-r--r--drivers/gpu/drm/i915/intel_fb.c737
-rw-r--r--drivers/gpu/drm/i915/intel_i2c.c8
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c22
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c331
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c30
-rw-r--r--drivers/gpu/drm/mga/mga_dma.c4
-rw-r--r--drivers/gpu/drm/mga/mga_drv.h1
-rw-r--r--drivers/gpu/drm/mga/mga_ucode.h11645
-rw-r--r--drivers/gpu/drm/mga/mga_warp.c180
-rw-r--r--drivers/gpu/drm/r128/r128_cce.c116
-rw-r--r--drivers/gpu/drm/r128/r128_drv.h8
-rw-r--r--drivers/gpu/drm/r128/r128_state.c36
-rw-r--r--drivers/gpu/drm/radeon/Kconfig1
-rw-r--r--drivers/gpu/drm/radeon/Makefile43
-rw-r--r--drivers/gpu/drm/radeon/atombios.h11
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c105
-rw-r--r--drivers/gpu/drm/radeon/avivod.h69
-rw-r--r--drivers/gpu/drm/radeon/mkregtable.c720
-rw-r--r--drivers/gpu/drm/radeon/r100.c1232
-rw-r--r--drivers/gpu/drm/radeon/r100_track.h124
-rw-r--r--drivers/gpu/drm/radeon/r100d.h607
-rw-r--r--drivers/gpu/drm/radeon/r200.c456
-rw-r--r--drivers/gpu/drm/radeon/r300.c556
-rw-r--r--drivers/gpu/drm/radeon/r300.h36
-rw-r--r--drivers/gpu/drm/radeon/r300d.h101
-rw-r--r--drivers/gpu/drm/radeon/r420.c301
-rw-r--r--drivers/gpu/drm/radeon/r420d.h249
-rw-r--r--drivers/gpu/drm/radeon/r520.c6
-rw-r--r--drivers/gpu/drm/radeon/r600.c1802
-rw-r--r--drivers/gpu/drm/radeon/r600_blit.c850
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_kms.c805
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_shaders.c1072
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_shaders.h14
-rw-r--r--drivers/gpu/drm/radeon/r600_cp.c541
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c657
-rw-r--r--drivers/gpu/drm/radeon/r600_microcode.h23297
-rw-r--r--drivers/gpu/drm/radeon/r600d.h662
-rw-r--r--drivers/gpu/drm/radeon/radeon.h269
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h240
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c171
-rw-r--r--drivers/gpu/drm/radeon/radeon_clocks.c10
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c58
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c480
-rw-r--r--drivers/gpu/drm/radeon/radeon_cp.c151
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c423
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c101
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c23
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h151
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c137
-rw-r--r--drivers/gpu/drm/radeon/radeon_fb.c674
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c49
-rw-r--r--drivers/gpu/drm/radeon/radeon_gart.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_ioc32.c15
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq.c18
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq_kms.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c25
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c85
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c368
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_tv.c904
-rw-r--r--drivers/gpu/drm/radeon/radeon_microcode.h1844
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h74
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c10
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_reg.h79
-rw-r--r--drivers/gpu/drm/radeon/radeon_ring.c143
-rw-r--r--drivers/gpu/drm/radeon/radeon_share.h39
-rw-r--r--drivers/gpu/drm/radeon/radeon_state.c23
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c96
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r100105
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r200184
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r300729
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rn5030
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rs600729
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rv515486
-rw-r--r--drivers/gpu/drm/radeon/rs400.c56
-rw-r--r--drivers/gpu/drm/radeon/rs600.c106
-rw-r--r--drivers/gpu/drm/radeon/rs690.c4
-rw-r--r--drivers/gpu/drm/radeon/rs780.c102
-rw-r--r--drivers/gpu/drm/radeon/rv515.c524
-rw-r--r--drivers/gpu/drm/radeon/rv515d.h (renamed from drivers/gpu/drm/radeon/rv515r.h)56
-rw-r--r--drivers/gpu/drm/radeon/rv770.c1050
-rw-r--r--drivers/gpu/drm/radeon/rv770d.h341
-rw-r--r--drivers/gpu/drm/ttm/ttm_bo.c295
-rw-r--r--drivers/gpu/drm/ttm/ttm_bo_util.c4
-rw-r--r--drivers/gpu/drm/ttm/ttm_global.c4
-rw-r--r--drivers/gpu/drm/ttm/ttm_memory.c508
-rw-r--r--drivers/gpu/drm/ttm/ttm_module.c58
-rw-r--r--drivers/gpu/drm/ttm/ttm_tt.c104
119 files changed, 21760 insertions, 41286 deletions
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 39b393d38bb3..e4d971c8b9d0 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -18,6 +18,14 @@ menuconfig DRM
18 details. You should also select and configure AGP 18 details. You should also select and configure AGP
19 (/dev/agpgart) support. 19 (/dev/agpgart) support.
20 20
21config DRM_KMS_HELPER
22 tristate
23 depends on DRM
24 select FB
25 select FRAMEBUFFER_CONSOLE if !EMBEDDED
26 help
27 FB and CRTC helpers for KMS drivers.
28
21config DRM_TTM 29config DRM_TTM
22 tristate 30 tristate
23 depends on DRM 31 depends on DRM
@@ -36,6 +44,7 @@ config DRM_TDFX
36config DRM_R128 44config DRM_R128
37 tristate "ATI Rage 128" 45 tristate "ATI Rage 128"
38 depends on DRM && PCI 46 depends on DRM && PCI
47 select FW_LOADER
39 help 48 help
40 Choose this option if you have an ATI Rage 128 graphics card. If M 49 Choose this option if you have an ATI Rage 128 graphics card. If M
41 is selected, the module will be called r128. AGP support for 50 is selected, the module will be called r128. AGP support for
@@ -47,8 +56,9 @@ config DRM_RADEON
47 select FB_CFB_FILLRECT 56 select FB_CFB_FILLRECT
48 select FB_CFB_COPYAREA 57 select FB_CFB_COPYAREA
49 select FB_CFB_IMAGEBLIT 58 select FB_CFB_IMAGEBLIT
50 select FB 59 select FW_LOADER
51 select FRAMEBUFFER_CONSOLE if !EMBEDDED 60 select DRM_KMS_HELPER
61 select DRM_TTM
52 help 62 help
53 Choose this option if you have an ATI Radeon graphics card. There 63 Choose this option if you have an ATI Radeon graphics card. There
54 are both PCI and AGP versions. You don't need to choose this to 64 are both PCI and AGP versions. You don't need to choose this to
@@ -82,11 +92,10 @@ config DRM_I830
82config DRM_I915 92config DRM_I915
83 tristate "i915 driver" 93 tristate "i915 driver"
84 depends on AGP_INTEL 94 depends on AGP_INTEL
95 select DRM_KMS_HELPER
85 select FB_CFB_FILLRECT 96 select FB_CFB_FILLRECT
86 select FB_CFB_COPYAREA 97 select FB_CFB_COPYAREA
87 select FB_CFB_IMAGEBLIT 98 select FB_CFB_IMAGEBLIT
88 select FB
89 select FRAMEBUFFER_CONSOLE if !EMBEDDED
90 # i915 depends on ACPI_VIDEO when ACPI is enabled 99 # i915 depends on ACPI_VIDEO when ACPI is enabled
91 # but for select to work, need to select ACPI_VIDEO's dependencies, ick 100 # but for select to work, need to select ACPI_VIDEO's dependencies, ick
92 select VIDEO_OUTPUT_CONTROL if ACPI 101 select VIDEO_OUTPUT_CONTROL if ACPI
@@ -116,6 +125,7 @@ endchoice
116config DRM_MGA 125config DRM_MGA
117 tristate "Matrox g200/g400" 126 tristate "Matrox g200/g400"
118 depends on DRM 127 depends on DRM
128 select FW_LOADER
119 help 129 help
120 Choose this option if you have a Matrox G200, G400 or G450 graphics 130 Choose this option if you have a Matrox G200, G400 or G450 graphics
121 card. If M is selected, the module will be called mga. AGP 131 card. If M is selected, the module will be called mga. AGP
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index fe23f29f7cba..3c8827a7aabd 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -10,11 +10,15 @@ drm-y := drm_auth.o drm_bufs.o drm_cache.o \
10 drm_lock.o drm_memory.o drm_proc.o drm_stub.o drm_vm.o \ 10 drm_lock.o drm_memory.o drm_proc.o drm_stub.o drm_vm.o \
11 drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \ 11 drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \
12 drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \ 12 drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \
13 drm_crtc.o drm_crtc_helper.o drm_modes.o drm_edid.o \ 13 drm_crtc.o drm_modes.o drm_edid.o \
14 drm_info.o drm_debugfs.o 14 drm_info.o drm_debugfs.o drm_encoder_slave.o
15 15
16drm-$(CONFIG_COMPAT) += drm_ioc32.o 16drm-$(CONFIG_COMPAT) += drm_ioc32.o
17 17
18drm_kms_helper-y := drm_fb_helper.o drm_crtc_helper.o
19
20obj-$(CONFIG_DRM_KMS_HELPER) += drm_kms_helper.o
21
18obj-$(CONFIG_DRM) += drm.o 22obj-$(CONFIG_DRM) += drm.o
19obj-$(CONFIG_DRM_TTM) += ttm/ 23obj-$(CONFIG_DRM_TTM) += ttm/
20obj-$(CONFIG_DRM_TDFX) += tdfx/ 24obj-$(CONFIG_DRM_TDFX) += tdfx/
diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index 6246e3f3dad7..3d09e304f6f4 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -310,10 +310,10 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset,
310 (unsigned long long)map->offset, map->size); 310 (unsigned long long)map->offset, map->size);
311 311
312 break; 312 break;
313 }
313 case _DRM_GEM: 314 case _DRM_GEM:
314 DRM_ERROR("tried to rmmap GEM object\n"); 315 DRM_ERROR("tried to addmap GEM object\n");
315 break; 316 break;
316 }
317 case _DRM_SCATTER_GATHER: 317 case _DRM_SCATTER_GATHER:
318 if (!dev->sg) { 318 if (!dev->sg) {
319 kfree(map); 319 kfree(map);
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 0e994a0e46d4..0e3bd5b54b78 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -45,6 +45,23 @@ drm_clflush_page(struct page *page)
45 clflush(page_virtual + i); 45 clflush(page_virtual + i);
46 kunmap_atomic(page_virtual, KM_USER0); 46 kunmap_atomic(page_virtual, KM_USER0);
47} 47}
48
49static void drm_cache_flush_clflush(struct page *pages[],
50 unsigned long num_pages)
51{
52 unsigned long i;
53
54 mb();
55 for (i = 0; i < num_pages; i++)
56 drm_clflush_page(*pages++);
57 mb();
58}
59
60static void
61drm_clflush_ipi_handler(void *null)
62{
63 wbinvd();
64}
48#endif 65#endif
49 66
50void 67void
@@ -53,17 +70,30 @@ drm_clflush_pages(struct page *pages[], unsigned long num_pages)
53 70
54#if defined(CONFIG_X86) 71#if defined(CONFIG_X86)
55 if (cpu_has_clflush) { 72 if (cpu_has_clflush) {
56 unsigned long i; 73 drm_cache_flush_clflush(pages, num_pages);
57
58 mb();
59 for (i = 0; i < num_pages; ++i)
60 drm_clflush_page(*pages++);
61 mb();
62
63 return; 74 return;
64 } 75 }
65 76
66 wbinvd(); 77 if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0)
78 printk(KERN_ERR "Timed out waiting for cache flush.\n");
79
80#elif defined(__powerpc__)
81 unsigned long i;
82 for (i = 0; i < num_pages; i++) {
83 struct page *page = pages[i];
84 void *page_virtual;
85
86 if (unlikely(page == NULL))
87 continue;
88
89 page_virtual = kmap_atomic(page, KM_USER0);
90 flush_dcache_range((unsigned long)page_virtual,
91 (unsigned long)page_virtual + PAGE_SIZE);
92 kunmap_atomic(page_virtual, KM_USER0);
93 }
94#else
95 printk(KERN_ERR "Architecture has no drm_cache.c support\n");
96 WARN_ON_ONCE(1);
67#endif 97#endif
68} 98}
69EXPORT_SYMBOL(drm_clflush_pages); 99EXPORT_SYMBOL(drm_clflush_pages);
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 2f631c75f704..ba728ad77f2a 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -68,10 +68,10 @@ DRM_ENUM_NAME_FN(drm_get_dpms_name, drm_dpms_enum_list)
68 */ 68 */
69static struct drm_prop_enum_list drm_scaling_mode_enum_list[] = 69static struct drm_prop_enum_list drm_scaling_mode_enum_list[] =
70{ 70{
71 { DRM_MODE_SCALE_NON_GPU, "Non-GPU" }, 71 { DRM_MODE_SCALE_NONE, "None" },
72 { DRM_MODE_SCALE_FULLSCREEN, "Fullscreen" }, 72 { DRM_MODE_SCALE_FULLSCREEN, "Full" },
73 { DRM_MODE_SCALE_NO_SCALE, "No scale" }, 73 { DRM_MODE_SCALE_CENTER, "Center" },
74 { DRM_MODE_SCALE_ASPECT, "Aspect" }, 74 { DRM_MODE_SCALE_ASPECT, "Full aspect" },
75}; 75};
76 76
77static struct drm_prop_enum_list drm_dithering_mode_enum_list[] = 77static struct drm_prop_enum_list drm_dithering_mode_enum_list[] =
@@ -108,6 +108,7 @@ static struct drm_prop_enum_list drm_tv_select_enum_list[] =
108 { DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */ 108 { DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */
109 { DRM_MODE_SUBCONNECTOR_SVIDEO, "SVIDEO" }, /* TV-out */ 109 { DRM_MODE_SUBCONNECTOR_SVIDEO, "SVIDEO" }, /* TV-out */
110 { DRM_MODE_SUBCONNECTOR_Component, "Component" }, /* TV-out */ 110 { DRM_MODE_SUBCONNECTOR_Component, "Component" }, /* TV-out */
111 { DRM_MODE_SUBCONNECTOR_SCART, "SCART" }, /* TV-out */
111}; 112};
112 113
113DRM_ENUM_NAME_FN(drm_get_tv_select_name, drm_tv_select_enum_list) 114DRM_ENUM_NAME_FN(drm_get_tv_select_name, drm_tv_select_enum_list)
@@ -118,6 +119,7 @@ static struct drm_prop_enum_list drm_tv_subconnector_enum_list[] =
118 { DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */ 119 { DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */
119 { DRM_MODE_SUBCONNECTOR_SVIDEO, "SVIDEO" }, /* TV-out */ 120 { DRM_MODE_SUBCONNECTOR_SVIDEO, "SVIDEO" }, /* TV-out */
120 { DRM_MODE_SUBCONNECTOR_Component, "Component" }, /* TV-out */ 121 { DRM_MODE_SUBCONNECTOR_Component, "Component" }, /* TV-out */
122 { DRM_MODE_SUBCONNECTOR_SCART, "SCART" }, /* TV-out */
121}; 123};
122 124
123DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name, 125DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name,
@@ -146,6 +148,7 @@ static struct drm_conn_prop_enum_list drm_connector_enum_list[] =
146 { DRM_MODE_CONNECTOR_DisplayPort, "DisplayPort", 0 }, 148 { DRM_MODE_CONNECTOR_DisplayPort, "DisplayPort", 0 },
147 { DRM_MODE_CONNECTOR_HDMIA, "HDMI Type A", 0 }, 149 { DRM_MODE_CONNECTOR_HDMIA, "HDMI Type A", 0 },
148 { DRM_MODE_CONNECTOR_HDMIB, "HDMI Type B", 0 }, 150 { DRM_MODE_CONNECTOR_HDMIB, "HDMI Type B", 0 },
151 { DRM_MODE_CONNECTOR_TV, "TV", 0 },
149}; 152};
150 153
151static struct drm_prop_enum_list drm_encoder_enum_list[] = 154static struct drm_prop_enum_list drm_encoder_enum_list[] =
@@ -165,6 +168,7 @@ char *drm_get_encoder_name(struct drm_encoder *encoder)
165 encoder->base.id); 168 encoder->base.id);
166 return buf; 169 return buf;
167} 170}
171EXPORT_SYMBOL(drm_get_encoder_name);
168 172
169char *drm_get_connector_name(struct drm_connector *connector) 173char *drm_get_connector_name(struct drm_connector *connector)
170{ 174{
@@ -699,6 +703,42 @@ int drm_mode_create_tv_properties(struct drm_device *dev, int num_modes,
699 drm_property_add_enum(dev->mode_config.tv_mode_property, i, 703 drm_property_add_enum(dev->mode_config.tv_mode_property, i,
700 i, modes[i]); 704 i, modes[i]);
701 705
706 dev->mode_config.tv_brightness_property =
707 drm_property_create(dev, DRM_MODE_PROP_RANGE,
708 "brightness", 2);
709 dev->mode_config.tv_brightness_property->values[0] = 0;
710 dev->mode_config.tv_brightness_property->values[1] = 100;
711
712 dev->mode_config.tv_contrast_property =
713 drm_property_create(dev, DRM_MODE_PROP_RANGE,
714 "contrast", 2);
715 dev->mode_config.tv_contrast_property->values[0] = 0;
716 dev->mode_config.tv_contrast_property->values[1] = 100;
717
718 dev->mode_config.tv_flicker_reduction_property =
719 drm_property_create(dev, DRM_MODE_PROP_RANGE,
720 "flicker reduction", 2);
721 dev->mode_config.tv_flicker_reduction_property->values[0] = 0;
722 dev->mode_config.tv_flicker_reduction_property->values[1] = 100;
723
724 dev->mode_config.tv_overscan_property =
725 drm_property_create(dev, DRM_MODE_PROP_RANGE,
726 "overscan", 2);
727 dev->mode_config.tv_overscan_property->values[0] = 0;
728 dev->mode_config.tv_overscan_property->values[1] = 100;
729
730 dev->mode_config.tv_saturation_property =
731 drm_property_create(dev, DRM_MODE_PROP_RANGE,
732 "saturation", 2);
733 dev->mode_config.tv_saturation_property->values[0] = 0;
734 dev->mode_config.tv_saturation_property->values[1] = 100;
735
736 dev->mode_config.tv_hue_property =
737 drm_property_create(dev, DRM_MODE_PROP_RANGE,
738 "hue", 2);
739 dev->mode_config.tv_hue_property->values[0] = 0;
740 dev->mode_config.tv_hue_property->values[1] = 100;
741
702 return 0; 742 return 0;
703} 743}
704EXPORT_SYMBOL(drm_mode_create_tv_properties); 744EXPORT_SYMBOL(drm_mode_create_tv_properties);
@@ -1044,7 +1084,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data,
1044 if (file_priv->master->minor->type == DRM_MINOR_CONTROL) { 1084 if (file_priv->master->minor->type == DRM_MINOR_CONTROL) {
1045 list_for_each_entry(crtc, &dev->mode_config.crtc_list, 1085 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
1046 head) { 1086 head) {
1047 DRM_DEBUG("CRTC ID is %d\n", crtc->base.id); 1087 DRM_DEBUG_KMS("CRTC ID is %d\n", crtc->base.id);
1048 if (put_user(crtc->base.id, crtc_id + copied)) { 1088 if (put_user(crtc->base.id, crtc_id + copied)) {
1049 ret = -EFAULT; 1089 ret = -EFAULT;
1050 goto out; 1090 goto out;
@@ -1072,7 +1112,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data,
1072 list_for_each_entry(encoder, 1112 list_for_each_entry(encoder,
1073 &dev->mode_config.encoder_list, 1113 &dev->mode_config.encoder_list,
1074 head) { 1114 head) {
1075 DRM_DEBUG("ENCODER ID is %d\n", 1115 DRM_DEBUG_KMS("ENCODER ID is %d\n",
1076 encoder->base.id); 1116 encoder->base.id);
1077 if (put_user(encoder->base.id, encoder_id + 1117 if (put_user(encoder->base.id, encoder_id +
1078 copied)) { 1118 copied)) {
@@ -1103,7 +1143,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data,
1103 list_for_each_entry(connector, 1143 list_for_each_entry(connector,
1104 &dev->mode_config.connector_list, 1144 &dev->mode_config.connector_list,
1105 head) { 1145 head) {
1106 DRM_DEBUG("CONNECTOR ID is %d\n", 1146 DRM_DEBUG_KMS("CONNECTOR ID is %d\n",
1107 connector->base.id); 1147 connector->base.id);
1108 if (put_user(connector->base.id, 1148 if (put_user(connector->base.id,
1109 connector_id + copied)) { 1149 connector_id + copied)) {
@@ -1127,7 +1167,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data,
1127 } 1167 }
1128 card_res->count_connectors = connector_count; 1168 card_res->count_connectors = connector_count;
1129 1169
1130 DRM_DEBUG("Counted %d %d %d\n", card_res->count_crtcs, 1170 DRM_DEBUG_KMS("Counted %d %d %d\n", card_res->count_crtcs,
1131 card_res->count_connectors, card_res->count_encoders); 1171 card_res->count_connectors, card_res->count_encoders);
1132 1172
1133out: 1173out:
@@ -1230,7 +1270,7 @@ int drm_mode_getconnector(struct drm_device *dev, void *data,
1230 1270
1231 memset(&u_mode, 0, sizeof(struct drm_mode_modeinfo)); 1271 memset(&u_mode, 0, sizeof(struct drm_mode_modeinfo));
1232 1272
1233 DRM_DEBUG("connector id %d:\n", out_resp->connector_id); 1273 DRM_DEBUG_KMS("connector id %d:\n", out_resp->connector_id);
1234 1274
1235 mutex_lock(&dev->mode_config.mutex); 1275 mutex_lock(&dev->mode_config.mutex);
1236 1276
@@ -1406,7 +1446,7 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
1406 obj = drm_mode_object_find(dev, crtc_req->crtc_id, 1446 obj = drm_mode_object_find(dev, crtc_req->crtc_id,
1407 DRM_MODE_OBJECT_CRTC); 1447 DRM_MODE_OBJECT_CRTC);
1408 if (!obj) { 1448 if (!obj) {
1409 DRM_DEBUG("Unknown CRTC ID %d\n", crtc_req->crtc_id); 1449 DRM_DEBUG_KMS("Unknown CRTC ID %d\n", crtc_req->crtc_id);
1410 ret = -EINVAL; 1450 ret = -EINVAL;
1411 goto out; 1451 goto out;
1412 } 1452 }
@@ -1419,7 +1459,8 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
1419 list_for_each_entry(crtcfb, 1459 list_for_each_entry(crtcfb,
1420 &dev->mode_config.crtc_list, head) { 1460 &dev->mode_config.crtc_list, head) {
1421 if (crtcfb == crtc) { 1461 if (crtcfb == crtc) {
1422 DRM_DEBUG("Using current fb for setmode\n"); 1462 DRM_DEBUG_KMS("Using current fb for "
1463 "setmode\n");
1423 fb = crtc->fb; 1464 fb = crtc->fb;
1424 } 1465 }
1425 } 1466 }
@@ -1427,7 +1468,8 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
1427 obj = drm_mode_object_find(dev, crtc_req->fb_id, 1468 obj = drm_mode_object_find(dev, crtc_req->fb_id,
1428 DRM_MODE_OBJECT_FB); 1469 DRM_MODE_OBJECT_FB);
1429 if (!obj) { 1470 if (!obj) {
1430 DRM_DEBUG("Unknown FB ID%d\n", crtc_req->fb_id); 1471 DRM_DEBUG_KMS("Unknown FB ID%d\n",
1472 crtc_req->fb_id);
1431 ret = -EINVAL; 1473 ret = -EINVAL;
1432 goto out; 1474 goto out;
1433 } 1475 }
@@ -1440,13 +1482,13 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
1440 } 1482 }
1441 1483
1442 if (crtc_req->count_connectors == 0 && mode) { 1484 if (crtc_req->count_connectors == 0 && mode) {
1443 DRM_DEBUG("Count connectors is 0 but mode set\n"); 1485 DRM_DEBUG_KMS("Count connectors is 0 but mode set\n");
1444 ret = -EINVAL; 1486 ret = -EINVAL;
1445 goto out; 1487 goto out;
1446 } 1488 }
1447 1489
1448 if (crtc_req->count_connectors > 0 && (!mode || !fb)) { 1490 if (crtc_req->count_connectors > 0 && (!mode || !fb)) {
1449 DRM_DEBUG("Count connectors is %d but no mode or fb set\n", 1491 DRM_DEBUG_KMS("Count connectors is %d but no mode or fb set\n",
1450 crtc_req->count_connectors); 1492 crtc_req->count_connectors);
1451 ret = -EINVAL; 1493 ret = -EINVAL;
1452 goto out; 1494 goto out;
@@ -1479,7 +1521,8 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
1479 obj = drm_mode_object_find(dev, out_id, 1521 obj = drm_mode_object_find(dev, out_id,
1480 DRM_MODE_OBJECT_CONNECTOR); 1522 DRM_MODE_OBJECT_CONNECTOR);
1481 if (!obj) { 1523 if (!obj) {
1482 DRM_DEBUG("Connector id %d unknown\n", out_id); 1524 DRM_DEBUG_KMS("Connector id %d unknown\n",
1525 out_id);
1483 ret = -EINVAL; 1526 ret = -EINVAL;
1484 goto out; 1527 goto out;
1485 } 1528 }
@@ -1512,7 +1555,7 @@ int drm_mode_cursor_ioctl(struct drm_device *dev,
1512 struct drm_crtc *crtc; 1555 struct drm_crtc *crtc;
1513 int ret = 0; 1556 int ret = 0;
1514 1557
1515 DRM_DEBUG("\n"); 1558 DRM_DEBUG_KMS("\n");
1516 1559
1517 if (!req->flags) { 1560 if (!req->flags) {
1518 DRM_ERROR("no operation set\n"); 1561 DRM_ERROR("no operation set\n");
@@ -1522,7 +1565,7 @@ int drm_mode_cursor_ioctl(struct drm_device *dev,
1522 mutex_lock(&dev->mode_config.mutex); 1565 mutex_lock(&dev->mode_config.mutex);
1523 obj = drm_mode_object_find(dev, req->crtc_id, DRM_MODE_OBJECT_CRTC); 1566 obj = drm_mode_object_find(dev, req->crtc_id, DRM_MODE_OBJECT_CRTC);
1524 if (!obj) { 1567 if (!obj) {
1525 DRM_DEBUG("Unknown CRTC ID %d\n", req->crtc_id); 1568 DRM_DEBUG_KMS("Unknown CRTC ID %d\n", req->crtc_id);
1526 ret = -EINVAL; 1569 ret = -EINVAL;
1527 goto out; 1570 goto out;
1528 } 1571 }
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index 6aaa2cb23365..fe8697447f32 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -33,15 +33,6 @@
33#include "drm_crtc.h" 33#include "drm_crtc.h"
34#include "drm_crtc_helper.h" 34#include "drm_crtc_helper.h"
35 35
36/*
37 * Detailed mode info for 800x600@60Hz
38 */
39static struct drm_display_mode std_modes[] = {
40 { DRM_MODE("800x600", DRM_MODE_TYPE_DEFAULT, 40000, 800, 840,
41 968, 1056, 0, 600, 601, 605, 628, 0,
42 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
43};
44
45static void drm_mode_validate_flag(struct drm_connector *connector, 36static void drm_mode_validate_flag(struct drm_connector *connector,
46 int flags) 37 int flags)
47{ 38{
@@ -94,7 +85,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
94 int count = 0; 85 int count = 0;
95 int mode_flags = 0; 86 int mode_flags = 0;
96 87
97 DRM_DEBUG("%s\n", drm_get_connector_name(connector)); 88 DRM_DEBUG_KMS("%s\n", drm_get_connector_name(connector));
98 /* set all modes to the unverified state */ 89 /* set all modes to the unverified state */
99 list_for_each_entry_safe(mode, t, &connector->modes, head) 90 list_for_each_entry_safe(mode, t, &connector->modes, head)
100 mode->status = MODE_UNVERIFIED; 91 mode->status = MODE_UNVERIFIED;
@@ -102,15 +93,17 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
102 connector->status = connector->funcs->detect(connector); 93 connector->status = connector->funcs->detect(connector);
103 94
104 if (connector->status == connector_status_disconnected) { 95 if (connector->status == connector_status_disconnected) {
105 DRM_DEBUG("%s is disconnected\n", 96 DRM_DEBUG_KMS("%s is disconnected\n",
106 drm_get_connector_name(connector)); 97 drm_get_connector_name(connector));
107 /* TODO set EDID to NULL */ 98 goto prune;
108 return 0;
109 } 99 }
110 100
111 count = (*connector_funcs->get_modes)(connector); 101 count = (*connector_funcs->get_modes)(connector);
112 if (!count) 102 if (!count) {
113 return 0; 103 count = drm_add_modes_noedid(connector, 800, 600);
104 if (!count)
105 return 0;
106 }
114 107
115 drm_mode_connector_list_update(connector); 108 drm_mode_connector_list_update(connector);
116 109
@@ -130,7 +123,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
130 mode); 123 mode);
131 } 124 }
132 125
133 126prune:
134 drm_mode_prune_invalid(dev, &connector->modes, true); 127 drm_mode_prune_invalid(dev, &connector->modes, true);
135 128
136 if (list_empty(&connector->modes)) 129 if (list_empty(&connector->modes))
@@ -138,7 +131,8 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
138 131
139 drm_mode_sort(&connector->modes); 132 drm_mode_sort(&connector->modes);
140 133
141 DRM_DEBUG("Probed modes for %s\n", drm_get_connector_name(connector)); 134 DRM_DEBUG_KMS("Probed modes for %s\n",
135 drm_get_connector_name(connector));
142 list_for_each_entry_safe(mode, t, &connector->modes, head) { 136 list_for_each_entry_safe(mode, t, &connector->modes, head) {
143 mode->vrefresh = drm_mode_vrefresh(mode); 137 mode->vrefresh = drm_mode_vrefresh(mode);
144 138
@@ -165,39 +159,6 @@ int drm_helper_probe_connector_modes(struct drm_device *dev, uint32_t maxX,
165} 159}
166EXPORT_SYMBOL(drm_helper_probe_connector_modes); 160EXPORT_SYMBOL(drm_helper_probe_connector_modes);
167 161
168static void drm_helper_add_std_modes(struct drm_device *dev,
169 struct drm_connector *connector)
170{
171 struct drm_display_mode *mode, *t;
172 int i;
173
174 for (i = 0; i < ARRAY_SIZE(std_modes); i++) {
175 struct drm_display_mode *stdmode;
176
177 /*
178 * When no valid EDID modes are available we end up
179 * here and bailed in the past, now we add some standard
180 * modes and move on.
181 */
182 stdmode = drm_mode_duplicate(dev, &std_modes[i]);
183 drm_mode_probed_add(connector, stdmode);
184 drm_mode_list_concat(&connector->probed_modes,
185 &connector->modes);
186
187 DRM_DEBUG("Adding mode %s to %s\n", stdmode->name,
188 drm_get_connector_name(connector));
189 }
190 drm_mode_sort(&connector->modes);
191
192 DRM_DEBUG("Added std modes on %s\n", drm_get_connector_name(connector));
193 list_for_each_entry_safe(mode, t, &connector->modes, head) {
194 mode->vrefresh = drm_mode_vrefresh(mode);
195
196 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
197 drm_mode_debug_printmodeline(mode);
198 }
199}
200
201/** 162/**
202 * drm_helper_encoder_in_use - check if a given encoder is in use 163 * drm_helper_encoder_in_use - check if a given encoder is in use
203 * @encoder: encoder to check 164 * @encoder: encoder to check
@@ -258,13 +219,27 @@ EXPORT_SYMBOL(drm_helper_crtc_in_use);
258void drm_helper_disable_unused_functions(struct drm_device *dev) 219void drm_helper_disable_unused_functions(struct drm_device *dev)
259{ 220{
260 struct drm_encoder *encoder; 221 struct drm_encoder *encoder;
222 struct drm_connector *connector;
261 struct drm_encoder_helper_funcs *encoder_funcs; 223 struct drm_encoder_helper_funcs *encoder_funcs;
262 struct drm_crtc *crtc; 224 struct drm_crtc *crtc;
263 225
226 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
227 if (!connector->encoder)
228 continue;
229 if (connector->status == connector_status_disconnected)
230 connector->encoder = NULL;
231 }
232
264 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 233 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
265 encoder_funcs = encoder->helper_private; 234 encoder_funcs = encoder->helper_private;
266 if (!drm_helper_encoder_in_use(encoder)) 235 if (!drm_helper_encoder_in_use(encoder)) {
267 (*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF); 236 if (encoder_funcs->disable)
237 (*encoder_funcs->disable)(encoder);
238 else
239 (*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF);
240 /* disconnector encoder from any connector */
241 encoder->crtc = NULL;
242 }
268 } 243 }
269 244
270 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 245 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
@@ -312,7 +287,7 @@ static void drm_enable_connectors(struct drm_device *dev, bool *enabled)
312 287
313 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 288 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
314 enabled[i] = drm_connector_enabled(connector, true); 289 enabled[i] = drm_connector_enabled(connector, true);
315 DRM_DEBUG("connector %d enabled? %s\n", connector->base.id, 290 DRM_DEBUG_KMS("connector %d enabled? %s\n", connector->base.id,
316 enabled[i] ? "yes" : "no"); 291 enabled[i] ? "yes" : "no");
317 any_enabled |= enabled[i]; 292 any_enabled |= enabled[i];
318 i++; 293 i++;
@@ -342,7 +317,7 @@ static bool drm_target_preferred(struct drm_device *dev,
342 continue; 317 continue;
343 } 318 }
344 319
345 DRM_DEBUG("looking for preferred mode on connector %d\n", 320 DRM_DEBUG_KMS("looking for preferred mode on connector %d\n",
346 connector->base.id); 321 connector->base.id);
347 322
348 modes[i] = drm_has_preferred_mode(connector, width, height); 323 modes[i] = drm_has_preferred_mode(connector, width, height);
@@ -351,7 +326,7 @@ static bool drm_target_preferred(struct drm_device *dev,
351 list_for_each_entry(modes[i], &connector->modes, head) 326 list_for_each_entry(modes[i], &connector->modes, head)
352 break; 327 break;
353 } 328 }
354 DRM_DEBUG("found mode %s\n", modes[i] ? modes[i]->name : 329 DRM_DEBUG_KMS("found mode %s\n", modes[i] ? modes[i]->name :
355 "none"); 330 "none");
356 i++; 331 i++;
357 } 332 }
@@ -409,7 +384,7 @@ static int drm_pick_crtcs(struct drm_device *dev,
409 c = 0; 384 c = 0;
410 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 385 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
411 386
412 if ((connector->encoder->possible_crtcs & (1 << c)) == 0) { 387 if ((encoder->possible_crtcs & (1 << c)) == 0) {
413 c++; 388 c++;
414 continue; 389 continue;
415 } 390 }
@@ -452,7 +427,7 @@ static void drm_setup_crtcs(struct drm_device *dev)
452 int width, height; 427 int width, height;
453 int i, ret; 428 int i, ret;
454 429
455 DRM_DEBUG("\n"); 430 DRM_DEBUG_KMS("\n");
456 431
457 width = dev->mode_config.max_width; 432 width = dev->mode_config.max_width;
458 height = dev->mode_config.max_height; 433 height = dev->mode_config.max_height;
@@ -475,7 +450,7 @@ static void drm_setup_crtcs(struct drm_device *dev)
475 if (!ret) 450 if (!ret)
476 DRM_ERROR("Unable to find initial modes\n"); 451 DRM_ERROR("Unable to find initial modes\n");
477 452
478 DRM_DEBUG("picking CRTCs for %dx%d config\n", width, height); 453 DRM_DEBUG_KMS("picking CRTCs for %dx%d config\n", width, height);
479 454
480 drm_pick_crtcs(dev, crtcs, modes, 0, width, height); 455 drm_pick_crtcs(dev, crtcs, modes, 0, width, height);
481 456
@@ -490,12 +465,14 @@ static void drm_setup_crtcs(struct drm_device *dev)
490 } 465 }
491 466
492 if (mode && crtc) { 467 if (mode && crtc) {
493 DRM_DEBUG("desired mode %s set on crtc %d\n", 468 DRM_DEBUG_KMS("desired mode %s set on crtc %d\n",
494 mode->name, crtc->base.id); 469 mode->name, crtc->base.id);
495 crtc->desired_mode = mode; 470 crtc->desired_mode = mode;
496 connector->encoder->crtc = crtc; 471 connector->encoder->crtc = crtc;
497 } else 472 } else {
498 connector->encoder->crtc = NULL; 473 connector->encoder->crtc = NULL;
474 connector->encoder = NULL;
475 }
499 i++; 476 i++;
500 } 477 }
501 478
@@ -702,18 +679,17 @@ EXPORT_SYMBOL(drm_crtc_helper_set_mode);
702int drm_crtc_helper_set_config(struct drm_mode_set *set) 679int drm_crtc_helper_set_config(struct drm_mode_set *set)
703{ 680{
704 struct drm_device *dev; 681 struct drm_device *dev;
705 struct drm_crtc **save_crtcs, *new_crtc; 682 struct drm_crtc *save_crtcs, *new_crtc, *crtc;
706 struct drm_encoder **save_encoders, *new_encoder; 683 struct drm_encoder *save_encoders, *new_encoder, *encoder;
707 struct drm_framebuffer *old_fb = NULL; 684 struct drm_framebuffer *old_fb = NULL;
708 bool save_enabled;
709 bool mode_changed = false; /* if true do a full mode set */ 685 bool mode_changed = false; /* if true do a full mode set */
710 bool fb_changed = false; /* if true and !mode_changed just do a flip */ 686 bool fb_changed = false; /* if true and !mode_changed just do a flip */
711 struct drm_connector *connector; 687 struct drm_connector *save_connectors, *connector;
712 int count = 0, ro, fail = 0; 688 int count = 0, ro, fail = 0;
713 struct drm_crtc_helper_funcs *crtc_funcs; 689 struct drm_crtc_helper_funcs *crtc_funcs;
714 int ret = 0; 690 int ret = 0;
715 691
716 DRM_DEBUG("\n"); 692 DRM_DEBUG_KMS("\n");
717 693
718 if (!set) 694 if (!set)
719 return -EINVAL; 695 return -EINVAL;
@@ -726,37 +702,60 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
726 702
727 crtc_funcs = set->crtc->helper_private; 703 crtc_funcs = set->crtc->helper_private;
728 704
729 DRM_DEBUG("crtc: %p %d fb: %p connectors: %p num_connectors: %d (x, y) (%i, %i)\n", 705 DRM_DEBUG_KMS("crtc: %p %d fb: %p connectors: %p num_connectors:"
706 " %d (x, y) (%i, %i)\n",
730 set->crtc, set->crtc->base.id, set->fb, set->connectors, 707 set->crtc, set->crtc->base.id, set->fb, set->connectors,
731 (int)set->num_connectors, set->x, set->y); 708 (int)set->num_connectors, set->x, set->y);
732 709
733 dev = set->crtc->dev; 710 dev = set->crtc->dev;
734 711
735 /* save previous config */ 712 /* Allocate space for the backup of all (non-pointer) crtc, encoder and
736 save_enabled = set->crtc->enabled; 713 * connector data. */
737 714 save_crtcs = kzalloc(dev->mode_config.num_crtc *
738 /* 715 sizeof(struct drm_crtc), GFP_KERNEL);
739 * We do mode_config.num_connectors here since we'll look at the
740 * CRTC and encoder associated with each connector later.
741 */
742 save_crtcs = kzalloc(dev->mode_config.num_connector *
743 sizeof(struct drm_crtc *), GFP_KERNEL);
744 if (!save_crtcs) 716 if (!save_crtcs)
745 return -ENOMEM; 717 return -ENOMEM;
746 718
747 save_encoders = kzalloc(dev->mode_config.num_connector * 719 save_encoders = kzalloc(dev->mode_config.num_encoder *
748 sizeof(struct drm_encoders *), GFP_KERNEL); 720 sizeof(struct drm_encoder), GFP_KERNEL);
749 if (!save_encoders) { 721 if (!save_encoders) {
750 kfree(save_crtcs); 722 kfree(save_crtcs);
751 return -ENOMEM; 723 return -ENOMEM;
752 } 724 }
753 725
726 save_connectors = kzalloc(dev->mode_config.num_connector *
727 sizeof(struct drm_connector), GFP_KERNEL);
728 if (!save_connectors) {
729 kfree(save_crtcs);
730 kfree(save_encoders);
731 return -ENOMEM;
732 }
733
734 /* Copy data. Note that driver private data is not affected.
735 * Should anything bad happen only the expected state is
736 * restored, not the drivers personal bookkeeping.
737 */
738 count = 0;
739 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
740 save_crtcs[count++] = *crtc;
741 }
742
743 count = 0;
744 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
745 save_encoders[count++] = *encoder;
746 }
747
748 count = 0;
749 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
750 save_connectors[count++] = *connector;
751 }
752
754 /* We should be able to check here if the fb has the same properties 753 /* We should be able to check here if the fb has the same properties
755 * and then just flip_or_move it */ 754 * and then just flip_or_move it */
756 if (set->crtc->fb != set->fb) { 755 if (set->crtc->fb != set->fb) {
757 /* If we have no fb then treat it as a full mode set */ 756 /* If we have no fb then treat it as a full mode set */
758 if (set->crtc->fb == NULL) { 757 if (set->crtc->fb == NULL) {
759 DRM_DEBUG("crtc has no fb, full mode set\n"); 758 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
760 mode_changed = true; 759 mode_changed = true;
761 } else if (set->fb == NULL) { 760 } else if (set->fb == NULL) {
762 mode_changed = true; 761 mode_changed = true;
@@ -772,7 +771,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
772 fb_changed = true; 771 fb_changed = true;
773 772
774 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { 773 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
775 DRM_DEBUG("modes are different, full mode set\n"); 774 DRM_DEBUG_KMS("modes are different, full mode set\n");
776 drm_mode_debug_printmodeline(&set->crtc->mode); 775 drm_mode_debug_printmodeline(&set->crtc->mode);
777 drm_mode_debug_printmodeline(set->mode); 776 drm_mode_debug_printmodeline(set->mode);
778 mode_changed = true; 777 mode_changed = true;
@@ -783,7 +782,6 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
783 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 782 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
784 struct drm_connector_helper_funcs *connector_funcs = 783 struct drm_connector_helper_funcs *connector_funcs =
785 connector->helper_private; 784 connector->helper_private;
786 save_encoders[count++] = connector->encoder;
787 new_encoder = connector->encoder; 785 new_encoder = connector->encoder;
788 for (ro = 0; ro < set->num_connectors; ro++) { 786 for (ro = 0; ro < set->num_connectors; ro++) {
789 if (set->connectors[ro] == connector) { 787 if (set->connectors[ro] == connector) {
@@ -798,15 +796,20 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
798 } 796 }
799 797
800 if (new_encoder != connector->encoder) { 798 if (new_encoder != connector->encoder) {
801 DRM_DEBUG("encoder changed, full mode switch\n"); 799 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
802 mode_changed = true; 800 mode_changed = true;
801 /* If the encoder is reused for another connector, then
802 * the appropriate crtc will be set later.
803 */
804 if (connector->encoder)
805 connector->encoder->crtc = NULL;
803 connector->encoder = new_encoder; 806 connector->encoder = new_encoder;
804 } 807 }
805 } 808 }
806 809
807 if (fail) { 810 if (fail) {
808 ret = -EINVAL; 811 ret = -EINVAL;
809 goto fail_no_encoder; 812 goto fail;
810 } 813 }
811 814
812 count = 0; 815 count = 0;
@@ -814,8 +817,6 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
814 if (!connector->encoder) 817 if (!connector->encoder)
815 continue; 818 continue;
816 819
817 save_crtcs[count++] = connector->encoder->crtc;
818
819 if (connector->encoder->crtc == set->crtc) 820 if (connector->encoder->crtc == set->crtc)
820 new_crtc = NULL; 821 new_crtc = NULL;
821 else 822 else
@@ -830,14 +831,14 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
830 if (new_crtc && 831 if (new_crtc &&
831 !drm_encoder_crtc_ok(connector->encoder, new_crtc)) { 832 !drm_encoder_crtc_ok(connector->encoder, new_crtc)) {
832 ret = -EINVAL; 833 ret = -EINVAL;
833 goto fail_set_mode; 834 goto fail;
834 } 835 }
835 if (new_crtc != connector->encoder->crtc) { 836 if (new_crtc != connector->encoder->crtc) {
836 DRM_DEBUG("crtc changed, full mode switch\n"); 837 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
837 mode_changed = true; 838 mode_changed = true;
838 connector->encoder->crtc = new_crtc; 839 connector->encoder->crtc = new_crtc;
839 } 840 }
840 DRM_DEBUG("setting connector %d crtc to %p\n", 841 DRM_DEBUG_KMS("setting connector %d crtc to %p\n",
841 connector->base.id, new_crtc); 842 connector->base.id, new_crtc);
842 } 843 }
843 844
@@ -850,7 +851,8 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
850 set->crtc->fb = set->fb; 851 set->crtc->fb = set->fb;
851 set->crtc->enabled = (set->mode != NULL); 852 set->crtc->enabled = (set->mode != NULL);
852 if (set->mode != NULL) { 853 if (set->mode != NULL) {
853 DRM_DEBUG("attempting to set mode from userspace\n"); 854 DRM_DEBUG_KMS("attempting to set mode from"
855 " userspace\n");
854 drm_mode_debug_printmodeline(set->mode); 856 drm_mode_debug_printmodeline(set->mode);
855 if (!drm_crtc_helper_set_mode(set->crtc, set->mode, 857 if (!drm_crtc_helper_set_mode(set->crtc, set->mode,
856 set->x, set->y, 858 set->x, set->y,
@@ -858,7 +860,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
858 DRM_ERROR("failed to set mode on crtc %p\n", 860 DRM_ERROR("failed to set mode on crtc %p\n",
859 set->crtc); 861 set->crtc);
860 ret = -EINVAL; 862 ret = -EINVAL;
861 goto fail_set_mode; 863 goto fail;
862 } 864 }
863 /* TODO are these needed? */ 865 /* TODO are these needed? */
864 set->crtc->desired_x = set->x; 866 set->crtc->desired_x = set->x;
@@ -867,43 +869,50 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
867 } 869 }
868 drm_helper_disable_unused_functions(dev); 870 drm_helper_disable_unused_functions(dev);
869 } else if (fb_changed) { 871 } else if (fb_changed) {
872 set->crtc->x = set->x;
873 set->crtc->y = set->y;
874
870 old_fb = set->crtc->fb; 875 old_fb = set->crtc->fb;
871 if (set->crtc->fb != set->fb) 876 if (set->crtc->fb != set->fb)
872 set->crtc->fb = set->fb; 877 set->crtc->fb = set->fb;
873 ret = crtc_funcs->mode_set_base(set->crtc, 878 ret = crtc_funcs->mode_set_base(set->crtc,
874 set->x, set->y, old_fb); 879 set->x, set->y, old_fb);
875 if (ret != 0) 880 if (ret != 0)
876 goto fail_set_mode; 881 goto fail;
877 } 882 }
878 883
884 kfree(save_connectors);
879 kfree(save_encoders); 885 kfree(save_encoders);
880 kfree(save_crtcs); 886 kfree(save_crtcs);
881 return 0; 887 return 0;
882 888
883fail_set_mode: 889fail:
884 set->crtc->enabled = save_enabled; 890 /* Restore all previous data. */
885 set->crtc->fb = old_fb;
886 count = 0; 891 count = 0;
887 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 892 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
888 if (!connector->encoder) 893 *crtc = save_crtcs[count++];
889 continue; 894 }
890 895
891 connector->encoder->crtc = save_crtcs[count++]; 896 count = 0;
897 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
898 *encoder = save_encoders[count++];
892 } 899 }
893fail_no_encoder: 900
894 kfree(save_crtcs);
895 count = 0; 901 count = 0;
896 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 902 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
897 connector->encoder = save_encoders[count++]; 903 *connector = save_connectors[count++];
898 } 904 }
905
906 kfree(save_connectors);
899 kfree(save_encoders); 907 kfree(save_encoders);
908 kfree(save_crtcs);
900 return ret; 909 return ret;
901} 910}
902EXPORT_SYMBOL(drm_crtc_helper_set_config); 911EXPORT_SYMBOL(drm_crtc_helper_set_config);
903 912
904bool drm_helper_plugged_event(struct drm_device *dev) 913bool drm_helper_plugged_event(struct drm_device *dev)
905{ 914{
906 DRM_DEBUG("\n"); 915 DRM_DEBUG_KMS("\n");
907 916
908 drm_helper_probe_connector_modes(dev, dev->mode_config.max_width, 917 drm_helper_probe_connector_modes(dev, dev->mode_config.max_width,
909 dev->mode_config.max_height); 918 dev->mode_config.max_height);
@@ -932,7 +941,6 @@ bool drm_helper_plugged_event(struct drm_device *dev)
932 */ 941 */
933bool drm_helper_initial_config(struct drm_device *dev) 942bool drm_helper_initial_config(struct drm_device *dev)
934{ 943{
935 struct drm_connector *connector;
936 int count = 0; 944 int count = 0;
937 945
938 count = drm_helper_probe_connector_modes(dev, 946 count = drm_helper_probe_connector_modes(dev,
@@ -940,16 +948,9 @@ bool drm_helper_initial_config(struct drm_device *dev)
940 dev->mode_config.max_height); 948 dev->mode_config.max_height);
941 949
942 /* 950 /*
943 * None of the available connectors had any modes, so add some 951 * we shouldn't end up with no modes here.
944 * and try to light them up anyway
945 */ 952 */
946 if (!count) { 953 WARN(!count, "Connected connector with 0 modes\n");
947 DRM_ERROR("connectors have no modes, using standard modes\n");
948 list_for_each_entry(connector,
949 &dev->mode_config.connector_list,
950 head)
951 drm_helper_add_std_modes(dev, connector);
952 }
953 954
954 drm_setup_crtcs(dev); 955 drm_setup_crtcs(dev);
955 956
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index b39d7bfc0c9c..a75ca63deea6 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -63,12 +63,12 @@ static struct drm_ioctl_desc drm_ioctls[] = {
63 DRM_IOCTL_DEF(DRM_IOCTL_GET_MAP, drm_getmap, 0), 63 DRM_IOCTL_DEF(DRM_IOCTL_GET_MAP, drm_getmap, 0),
64 DRM_IOCTL_DEF(DRM_IOCTL_GET_CLIENT, drm_getclient, 0), 64 DRM_IOCTL_DEF(DRM_IOCTL_GET_CLIENT, drm_getclient, 0),
65 DRM_IOCTL_DEF(DRM_IOCTL_GET_STATS, drm_getstats, 0), 65 DRM_IOCTL_DEF(DRM_IOCTL_GET_STATS, drm_getstats, 0),
66 DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER|DRM_ROOT_ONLY), 66 DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER),
67 67
68 DRM_IOCTL_DEF(DRM_IOCTL_SET_UNIQUE, drm_setunique, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 68 DRM_IOCTL_DEF(DRM_IOCTL_SET_UNIQUE, drm_setunique, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
69 DRM_IOCTL_DEF(DRM_IOCTL_BLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 69 DRM_IOCTL_DEF(DRM_IOCTL_BLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
70 DRM_IOCTL_DEF(DRM_IOCTL_UNBLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 70 DRM_IOCTL_DEF(DRM_IOCTL_UNBLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
71 DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 71 DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_AUTH|DRM_MASTER),
72 72
73 DRM_IOCTL_DEF(DRM_IOCTL_ADD_MAP, drm_addmap_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 73 DRM_IOCTL_DEF(DRM_IOCTL_ADD_MAP, drm_addmap_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
74 DRM_IOCTL_DEF(DRM_IOCTL_RM_MAP, drm_rmmap_ioctl, DRM_AUTH), 74 DRM_IOCTL_DEF(DRM_IOCTL_RM_MAP, drm_rmmap_ioctl, DRM_AUTH),
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 7f2728bbc16c..90d76bacff17 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -60,6 +60,12 @@
60#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 60#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
61/* use +hsync +vsync for detailed mode */ 61/* use +hsync +vsync for detailed mode */
62#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 62#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
63/* define the number of Extension EDID block */
64#define MAX_EDID_EXT_NUM 4
65
66#define LEVEL_DMT 0
67#define LEVEL_GTF 1
68#define LEVEL_CVT 2
63 69
64static struct edid_quirk { 70static struct edid_quirk {
65 char *vendor; 71 char *vendor;
@@ -237,28 +243,291 @@ static void edid_fixup_preferred(struct drm_connector *connector,
237 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 243 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
238} 244}
239 245
246/*
247 * Add the Autogenerated from the DMT spec.
248 * This table is copied from xfree86/modes/xf86EdidModes.c.
249 * But the mode with Reduced blank feature is deleted.
250 */
251static struct drm_display_mode drm_dmt_modes[] = {
252 /* 640x350@85Hz */
253 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
254 736, 832, 0, 350, 382, 385, 445, 0,
255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
256 /* 640x400@85Hz */
257 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
258 736, 832, 0, 400, 401, 404, 445, 0,
259 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
260 /* 720x400@85Hz */
261 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
262 828, 936, 0, 400, 401, 404, 446, 0,
263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
264 /* 640x480@60Hz */
265 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
266 752, 800, 0, 480, 489, 492, 525, 0,
267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
268 /* 640x480@72Hz */
269 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
270 704, 832, 0, 480, 489, 492, 520, 0,
271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
272 /* 640x480@75Hz */
273 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
274 720, 840, 0, 480, 481, 484, 500, 0,
275 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
276 /* 640x480@85Hz */
277 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
278 752, 832, 0, 480, 481, 484, 509, 0,
279 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
280 /* 800x600@56Hz */
281 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
282 896, 1024, 0, 600, 601, 603, 625, 0,
283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
284 /* 800x600@60Hz */
285 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
286 968, 1056, 0, 600, 601, 605, 628, 0,
287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
288 /* 800x600@72Hz */
289 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
290 976, 1040, 0, 600, 637, 643, 666, 0,
291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
292 /* 800x600@75Hz */
293 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
294 896, 1056, 0, 600, 601, 604, 625, 0,
295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
296 /* 800x600@85Hz */
297 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
298 896, 1048, 0, 600, 601, 604, 631, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
300 /* 848x480@60Hz */
301 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
302 976, 1088, 0, 480, 486, 494, 517, 0,
303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
304 /* 1024x768@43Hz, interlace */
305 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
306 1208, 1264, 0, 768, 768, 772, 817, 0,
307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
308 DRM_MODE_FLAG_INTERLACE) },
309 /* 1024x768@60Hz */
310 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
311 1184, 1344, 0, 768, 771, 777, 806, 0,
312 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
313 /* 1024x768@70Hz */
314 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
315 1184, 1328, 0, 768, 771, 777, 806, 0,
316 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
317 /* 1024x768@75Hz */
318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
319 1136, 1312, 0, 768, 769, 772, 800, 0,
320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
321 /* 1024x768@85Hz */
322 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
323 1072, 1376, 0, 768, 769, 772, 808, 0,
324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
325 /* 1152x864@75Hz */
326 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
327 1344, 1600, 0, 864, 865, 868, 900, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
329 /* 1280x768@60Hz */
330 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
331 1472, 1664, 0, 768, 771, 778, 798, 0,
332 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
333 /* 1280x768@75Hz */
334 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
335 1488, 1696, 0, 768, 771, 778, 805, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
337 /* 1280x768@85Hz */
338 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
339 1496, 1712, 0, 768, 771, 778, 809, 0,
340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 1280x800@60Hz */
342 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
343 1480, 1680, 0, 800, 803, 809, 831, 0,
344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
345 /* 1280x800@75Hz */
346 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
347 1488, 1696, 0, 800, 803, 809, 838, 0,
348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
349 /* 1280x800@85Hz */
350 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
351 1496, 1712, 0, 800, 803, 809, 843, 0,
352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
353 /* 1280x960@60Hz */
354 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
355 1488, 1800, 0, 960, 961, 964, 1000, 0,
356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
357 /* 1280x960@85Hz */
358 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
359 1504, 1728, 0, 960, 961, 964, 1011, 0,
360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 1280x1024@60Hz */
362 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
363 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
365 /* 1280x1024@75Hz */
366 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
367 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
369 /* 1280x1024@85Hz */
370 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
371 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
373 /* 1360x768@60Hz */
374 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
375 1536, 1792, 0, 768, 771, 777, 795, 0,
376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
377 /* 1440x1050@60Hz */
378 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
379 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
380 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
381 /* 1440x1050@75Hz */
382 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
383 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
384 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
385 /* 1440x1050@85Hz */
386 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
387 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
388 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
389 /* 1440x900@60Hz */
390 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
391 1672, 1904, 0, 900, 903, 909, 934, 0,
392 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
393 /* 1440x900@75Hz */
394 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
395 1688, 1936, 0, 900, 903, 909, 942, 0,
396 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
397 /* 1440x900@85Hz */
398 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
399 1696, 1952, 0, 900, 903, 909, 948, 0,
400 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
401 /* 1600x1200@60Hz */
402 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
403 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
405 /* 1600x1200@65Hz */
406 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
407 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
409 /* 1600x1200@70Hz */
410 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
411 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
413 /* 1600x1200@75Hz */
414 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 2025000, 1600, 1664,
415 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
417 /* 1600x1200@85Hz */
418 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
419 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
421 /* 1680x1050@60Hz */
422 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
423 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
425 /* 1680x1050@75Hz */
426 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
427 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
429 /* 1680x1050@85Hz */
430 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
431 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
433 /* 1792x1344@60Hz */
434 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
435 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
437 /* 1729x1344@75Hz */
438 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
439 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
441 /* 1853x1392@60Hz */
442 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
443 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
445 /* 1856x1392@75Hz */
446 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
447 2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
449 /* 1920x1200@60Hz */
450 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
451 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
453 /* 1920x1200@75Hz */
454 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
455 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
457 /* 1920x1200@85Hz */
458 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
459 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
461 /* 1920x1440@60Hz */
462 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
463 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
465 /* 1920x1440@75Hz */
466 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
467 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
468 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
469 /* 2560x1600@60Hz */
470 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
471 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
473 /* 2560x1600@75HZ */
474 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
475 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
477 /* 2560x1600@85HZ */
478 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
479 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
480 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
481};
482
483static struct drm_display_mode *drm_find_dmt(struct drm_device *dev,
484 int hsize, int vsize, int fresh)
485{
486 int i, count;
487 struct drm_display_mode *ptr, *mode;
488
489 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
490 mode = NULL;
491 for (i = 0; i < count; i++) {
492 ptr = &drm_dmt_modes[i];
493 if (hsize == ptr->hdisplay &&
494 vsize == ptr->vdisplay &&
495 fresh == drm_mode_vrefresh(ptr)) {
496 /* get the expected default mode */
497 mode = drm_mode_duplicate(dev, ptr);
498 break;
499 }
500 }
501 return mode;
502}
240/** 503/**
241 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 504 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
242 * @t: standard timing params 505 * @t: standard timing params
506 * @timing_level: standard timing level
243 * 507 *
244 * Take the standard timing params (in this case width, aspect, and refresh) 508 * Take the standard timing params (in this case width, aspect, and refresh)
245 * and convert them into a real mode using CVT. 509 * and convert them into a real mode using CVT/GTF/DMT.
246 * 510 *
247 * Punts for now, but should eventually use the FB layer's CVT based mode 511 * Punts for now, but should eventually use the FB layer's CVT based mode
248 * generation code. 512 * generation code.
249 */ 513 */
250struct drm_display_mode *drm_mode_std(struct drm_device *dev, 514struct drm_display_mode *drm_mode_std(struct drm_device *dev,
251 struct std_timing *t) 515 struct std_timing *t,
516 int timing_level)
252{ 517{
253 struct drm_display_mode *mode; 518 struct drm_display_mode *mode;
254 int hsize = t->hsize * 8 + 248, vsize; 519 int hsize, vsize;
520 int vrefresh_rate;
255 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 521 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
256 >> EDID_TIMING_ASPECT_SHIFT; 522 >> EDID_TIMING_ASPECT_SHIFT;
257 523 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
258 mode = drm_mode_create(dev); 524 >> EDID_TIMING_VFREQ_SHIFT;
259 if (!mode) 525
260 return NULL; 526 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
261 527 hsize = t->hsize * 8 + 248;
528 /* vrefresh_rate = vfreq + 60 */
529 vrefresh_rate = vfreq + 60;
530 /* the vdisplay is calculated based on the aspect ratio */
262 if (aspect_ratio == 0) 531 if (aspect_ratio == 0)
263 vsize = (hsize * 10) / 16; 532 vsize = (hsize * 10) / 16;
264 else if (aspect_ratio == 1) 533 else if (aspect_ratio == 1)
@@ -267,9 +536,30 @@ struct drm_display_mode *drm_mode_std(struct drm_device *dev,
267 vsize = (hsize * 4) / 5; 536 vsize = (hsize * 4) / 5;
268 else 537 else
269 vsize = (hsize * 9) / 16; 538 vsize = (hsize * 9) / 16;
270 539 /* HDTV hack */
271 drm_mode_set_name(mode); 540 if (hsize == 1360 && vsize == 765 && vrefresh_rate == 60) {
272 541 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
542 mode->hdisplay = 1366;
543 mode->vsync_start = mode->vsync_start - 1;
544 mode->vsync_end = mode->vsync_end - 1;
545 return mode;
546 }
547 mode = NULL;
548 /* check whether it can be found in default mode table */
549 mode = drm_find_dmt(dev, hsize, vsize, vrefresh_rate);
550 if (mode)
551 return mode;
552
553 switch (timing_level) {
554 case LEVEL_DMT:
555 break;
556 case LEVEL_GTF:
557 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
558 break;
559 case LEVEL_CVT:
560 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
561 break;
562 }
273 return mode; 563 return mode;
274} 564}
275 565
@@ -451,6 +741,19 @@ static int add_established_modes(struct drm_connector *connector, struct edid *e
451 741
452 return modes; 742 return modes;
453} 743}
744/**
745 * stanard_timing_level - get std. timing level(CVT/GTF/DMT)
746 * @edid: EDID block to scan
747 */
748static int standard_timing_level(struct edid *edid)
749{
750 if (edid->revision >= 2) {
751 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
752 return LEVEL_CVT;
753 return LEVEL_GTF;
754 }
755 return LEVEL_DMT;
756}
454 757
455/** 758/**
456 * add_standard_modes - get std. modes from EDID and add them 759 * add_standard_modes - get std. modes from EDID and add them
@@ -463,6 +766,9 @@ static int add_standard_modes(struct drm_connector *connector, struct edid *edid
463{ 766{
464 struct drm_device *dev = connector->dev; 767 struct drm_device *dev = connector->dev;
465 int i, modes = 0; 768 int i, modes = 0;
769 int timing_level;
770
771 timing_level = standard_timing_level(edid);
466 772
467 for (i = 0; i < EDID_STD_TIMINGS; i++) { 773 for (i = 0; i < EDID_STD_TIMINGS; i++) {
468 struct std_timing *t = &edid->standard_timings[i]; 774 struct std_timing *t = &edid->standard_timings[i];
@@ -472,7 +778,8 @@ static int add_standard_modes(struct drm_connector *connector, struct edid *edid
472 if (t->hsize == 1 && t->vfreq_aspect == 1) 778 if (t->hsize == 1 && t->vfreq_aspect == 1)
473 continue; 779 continue;
474 780
475 newmode = drm_mode_std(dev, &edid->standard_timings[i]); 781 newmode = drm_mode_std(dev, &edid->standard_timings[i],
782 timing_level);
476 if (newmode) { 783 if (newmode) {
477 drm_mode_probed_add(connector, newmode); 784 drm_mode_probed_add(connector, newmode);
478 modes++; 785 modes++;
@@ -496,6 +803,9 @@ static int add_detailed_info(struct drm_connector *connector,
496{ 803{
497 struct drm_device *dev = connector->dev; 804 struct drm_device *dev = connector->dev;
498 int i, j, modes = 0; 805 int i, j, modes = 0;
806 int timing_level;
807
808 timing_level = standard_timing_level(edid);
499 809
500 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) { 810 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) {
501 struct detailed_timing *timing = &edid->detailed_timings[i]; 811 struct detailed_timing *timing = &edid->detailed_timings[i];
@@ -525,7 +835,8 @@ static int add_detailed_info(struct drm_connector *connector,
525 struct drm_display_mode *newmode; 835 struct drm_display_mode *newmode;
526 836
527 std = &data->data.timings[j]; 837 std = &data->data.timings[j];
528 newmode = drm_mode_std(dev, std); 838 newmode = drm_mode_std(dev, std,
839 timing_level);
529 if (newmode) { 840 if (newmode) {
530 drm_mode_probed_add(connector, newmode); 841 drm_mode_probed_add(connector, newmode);
531 modes++; 842 modes++;
@@ -551,6 +862,122 @@ static int add_detailed_info(struct drm_connector *connector,
551 862
552 return modes; 863 return modes;
553} 864}
865/**
866 * add_detailed_mode_eedid - get detailed mode info from addtional timing
867 * EDID block
868 * @connector: attached connector
869 * @edid: EDID block to scan(It is only to get addtional timing EDID block)
870 * @quirks: quirks to apply
871 *
872 * Some of the detailed timing sections may contain mode information. Grab
873 * it and add it to the list.
874 */
875static int add_detailed_info_eedid(struct drm_connector *connector,
876 struct edid *edid, u32 quirks)
877{
878 struct drm_device *dev = connector->dev;
879 int i, j, modes = 0;
880 char *edid_ext = NULL;
881 struct detailed_timing *timing;
882 struct detailed_non_pixel *data;
883 struct drm_display_mode *newmode;
884 int edid_ext_num;
885 int start_offset, end_offset;
886 int timing_level;
887
888 if (edid->version == 1 && edid->revision < 3) {
889 /* If the EDID version is less than 1.3, there is no
890 * extension EDID.
891 */
892 return 0;
893 }
894 if (!edid->extensions) {
895 /* if there is no extension EDID, it is unnecessary to
896 * parse the E-EDID to get detailed info
897 */
898 return 0;
899 }
900
901 /* Chose real EDID extension number */
902 edid_ext_num = edid->extensions > MAX_EDID_EXT_NUM ?
903 MAX_EDID_EXT_NUM : edid->extensions;
904
905 /* Find CEA extension */
906 for (i = 0; i < edid_ext_num; i++) {
907 edid_ext = (char *)edid + EDID_LENGTH * (i + 1);
908 /* This block is CEA extension */
909 if (edid_ext[0] == 0x02)
910 break;
911 }
912
913 if (i == edid_ext_num) {
914 /* if there is no additional timing EDID block, return */
915 return 0;
916 }
917
918 /* Get the start offset of detailed timing block */
919 start_offset = edid_ext[2];
920 if (start_offset == 0) {
921 /* If the start_offset is zero, it means that neither detailed
922 * info nor data block exist. In such case it is also
923 * unnecessary to parse the detailed timing info.
924 */
925 return 0;
926 }
927
928 timing_level = standard_timing_level(edid);
929 end_offset = EDID_LENGTH;
930 end_offset -= sizeof(struct detailed_timing);
931 for (i = start_offset; i < end_offset;
932 i += sizeof(struct detailed_timing)) {
933 timing = (struct detailed_timing *)(edid_ext + i);
934 data = &timing->data.other_data;
935 /* Detailed mode timing */
936 if (timing->pixel_clock) {
937 newmode = drm_mode_detailed(dev, edid, timing, quirks);
938 if (!newmode)
939 continue;
940
941 drm_mode_probed_add(connector, newmode);
942
943 modes++;
944 continue;
945 }
946
947 /* Other timing or info */
948 switch (data->type) {
949 case EDID_DETAIL_MONITOR_SERIAL:
950 break;
951 case EDID_DETAIL_MONITOR_STRING:
952 break;
953 case EDID_DETAIL_MONITOR_RANGE:
954 /* Get monitor range data */
955 break;
956 case EDID_DETAIL_MONITOR_NAME:
957 break;
958 case EDID_DETAIL_MONITOR_CPDATA:
959 break;
960 case EDID_DETAIL_STD_MODES:
961 /* Five modes per detailed section */
962 for (j = 0; j < 5; i++) {
963 struct std_timing *std;
964 struct drm_display_mode *newmode;
965
966 std = &data->data.timings[j];
967 newmode = drm_mode_std(dev, std, timing_level);
968 if (newmode) {
969 drm_mode_probed_add(connector, newmode);
970 modes++;
971 }
972 }
973 break;
974 default:
975 break;
976 }
977 }
978
979 return modes;
980}
554 981
555#define DDC_ADDR 0x50 982#define DDC_ADDR 0x50
556/** 983/**
@@ -584,7 +1011,6 @@ int drm_do_probe_ddc_edid(struct i2c_adapter *adapter,
584 if (i2c_transfer(adapter, msgs, 2) == 2) 1011 if (i2c_transfer(adapter, msgs, 2) == 2)
585 return 0; 1012 return 0;
586 1013
587 dev_info(&adapter->dev, "unable to read EDID block.\n");
588 return -1; 1014 return -1;
589} 1015}
590EXPORT_SYMBOL(drm_do_probe_ddc_edid); 1016EXPORT_SYMBOL(drm_do_probe_ddc_edid);
@@ -597,8 +1023,6 @@ static int drm_ddc_read_edid(struct drm_connector *connector,
597 1023
598 ret = drm_do_probe_ddc_edid(adapter, buf, len); 1024 ret = drm_do_probe_ddc_edid(adapter, buf, len);
599 if (ret != 0) { 1025 if (ret != 0) {
600 dev_info(&connector->dev->pdev->dev, "%s: no EDID data\n",
601 drm_get_connector_name(connector));
602 goto end; 1026 goto end;
603 } 1027 }
604 if (!edid_is_valid((struct edid *)buf)) { 1028 if (!edid_is_valid((struct edid *)buf)) {
@@ -610,7 +1034,6 @@ end:
610 return ret; 1034 return ret;
611} 1035}
612 1036
613#define MAX_EDID_EXT_NUM 4
614/** 1037/**
615 * drm_get_edid - get EDID data, if available 1038 * drm_get_edid - get EDID data, if available
616 * @connector: connector we're probing 1039 * @connector: connector we're probing
@@ -763,6 +1186,7 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
763 num_modes += add_established_modes(connector, edid); 1186 num_modes += add_established_modes(connector, edid);
764 num_modes += add_standard_modes(connector, edid); 1187 num_modes += add_standard_modes(connector, edid);
765 num_modes += add_detailed_info(connector, edid, quirks); 1188 num_modes += add_detailed_info(connector, edid, quirks);
1189 num_modes += add_detailed_info_eedid(connector, edid, quirks);
766 1190
767 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 1191 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
768 edid_fixup_preferred(connector, quirks); 1192 edid_fixup_preferred(connector, quirks);
@@ -788,3 +1212,49 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
788 return num_modes; 1212 return num_modes;
789} 1213}
790EXPORT_SYMBOL(drm_add_edid_modes); 1214EXPORT_SYMBOL(drm_add_edid_modes);
1215
1216/**
1217 * drm_add_modes_noedid - add modes for the connectors without EDID
1218 * @connector: connector we're probing
1219 * @hdisplay: the horizontal display limit
1220 * @vdisplay: the vertical display limit
1221 *
1222 * Add the specified modes to the connector's mode list. Only when the
1223 * hdisplay/vdisplay is not beyond the given limit, it will be added.
1224 *
1225 * Return number of modes added or 0 if we couldn't find any.
1226 */
1227int drm_add_modes_noedid(struct drm_connector *connector,
1228 int hdisplay, int vdisplay)
1229{
1230 int i, count, num_modes = 0;
1231 struct drm_display_mode *mode, *ptr;
1232 struct drm_device *dev = connector->dev;
1233
1234 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
1235 if (hdisplay < 0)
1236 hdisplay = 0;
1237 if (vdisplay < 0)
1238 vdisplay = 0;
1239
1240 for (i = 0; i < count; i++) {
1241 ptr = &drm_dmt_modes[i];
1242 if (hdisplay && vdisplay) {
1243 /*
1244 * Only when two are valid, they will be used to check
1245 * whether the mode should be added to the mode list of
1246 * the connector.
1247 */
1248 if (ptr->hdisplay > hdisplay ||
1249 ptr->vdisplay > vdisplay)
1250 continue;
1251 }
1252 mode = drm_mode_duplicate(dev, ptr);
1253 if (mode) {
1254 drm_mode_probed_add(connector, mode);
1255 num_modes++;
1256 }
1257 }
1258 return num_modes;
1259}
1260EXPORT_SYMBOL(drm_add_modes_noedid);
diff --git a/drivers/gpu/drm/drm_encoder_slave.c b/drivers/gpu/drm/drm_encoder_slave.c
new file mode 100644
index 000000000000..f0184696edf3
--- /dev/null
+++ b/drivers/gpu/drm/drm_encoder_slave.c
@@ -0,0 +1,116 @@
1/*
2 * Copyright (C) 2009 Francisco Jerez.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include "drm_encoder_slave.h"
28
29/**
30 * drm_i2c_encoder_init - Initialize an I2C slave encoder
31 * @dev: DRM device.
32 * @encoder: Encoder to be attached to the I2C device. You aren't
33 * required to have called drm_encoder_init() before.
34 * @adap: I2C adapter that will be used to communicate with
35 * the device.
36 * @info: Information that will be used to create the I2C device.
37 * Required fields are @addr and @type.
38 *
39 * Create an I2C device on the specified bus (the module containing its
40 * driver is transparently loaded) and attach it to the specified
41 * &drm_encoder_slave. The @slave_funcs field will be initialized with
42 * the hooks provided by the slave driver.
43 *
44 * Returns 0 on success or a negative errno on failure, in particular,
45 * -ENODEV is returned when no matching driver is found.
46 */
47int drm_i2c_encoder_init(struct drm_device *dev,
48 struct drm_encoder_slave *encoder,
49 struct i2c_adapter *adap,
50 const struct i2c_board_info *info)
51{
52 char modalias[sizeof(I2C_MODULE_PREFIX)
53 + I2C_NAME_SIZE];
54 struct module *module = NULL;
55 struct i2c_client *client;
56 struct drm_i2c_encoder_driver *encoder_drv;
57 int err = 0;
58
59 snprintf(modalias, sizeof(modalias),
60 "%s%s", I2C_MODULE_PREFIX, info->type);
61 request_module(modalias);
62
63 client = i2c_new_device(adap, info);
64 if (!client) {
65 err = -ENOMEM;
66 goto fail;
67 }
68
69 if (!client->driver) {
70 err = -ENODEV;
71 goto fail_unregister;
72 }
73
74 module = client->driver->driver.owner;
75 if (!try_module_get(module)) {
76 err = -ENODEV;
77 goto fail_unregister;
78 }
79
80 encoder->bus_priv = client;
81
82 encoder_drv = to_drm_i2c_encoder_driver(client->driver);
83
84 err = encoder_drv->encoder_init(client, dev, encoder);
85 if (err)
86 goto fail_unregister;
87
88 return 0;
89
90fail_unregister:
91 i2c_unregister_device(client);
92 module_put(module);
93fail:
94 return err;
95}
96EXPORT_SYMBOL(drm_i2c_encoder_init);
97
98/**
99 * drm_i2c_encoder_destroy - Unregister the I2C device backing an encoder
100 * @drm_encoder: Encoder to be unregistered.
101 *
102 * This should be called from the @destroy method of an I2C slave
103 * encoder driver once I2C access is no longer needed.
104 */
105void drm_i2c_encoder_destroy(struct drm_encoder *drm_encoder)
106{
107 struct drm_encoder_slave *encoder = to_encoder_slave(drm_encoder);
108 struct i2c_client *client = drm_i2c_encoder_get_client(drm_encoder);
109 struct module *module = client->driver->driver.owner;
110
111 i2c_unregister_device(client);
112 encoder->bus_priv = NULL;
113
114 module_put(module);
115}
116EXPORT_SYMBOL(drm_i2c_encoder_destroy);
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
new file mode 100644
index 000000000000..2c4671314884
--- /dev/null
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -0,0 +1,707 @@
1/*
2 * Copyright (c) 2006-2009 Red Hat Inc.
3 * Copyright (c) 2006-2008 Intel Corporation
4 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
5 *
6 * DRM framebuffer helper functions
7 *
8 * Permission to use, copy, modify, distribute, and sell this software and its
9 * documentation for any purpose is hereby granted without fee, provided that
10 * the above copyright notice appear in all copies and that both that copyright
11 * notice and this permission notice appear in supporting documentation, and
12 * that the name of the copyright holders not be used in advertising or
13 * publicity pertaining to distribution of the software without specific,
14 * written prior permission. The copyright holders make no representations
15 * about the suitability of this software for any purpose. It is provided "as
16 * is" without express or implied warranty.
17 *
18 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
19 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
20 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
21 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
22 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
23 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
24 * OF THIS SOFTWARE.
25 *
26 * Authors:
27 * Dave Airlie <airlied@linux.ie>
28 * Jesse Barnes <jesse.barnes@intel.com>
29 */
30#include <linux/sysrq.h>
31#include <linux/fb.h>
32#include "drmP.h"
33#include "drm_crtc.h"
34#include "drm_fb_helper.h"
35#include "drm_crtc_helper.h"
36
37MODULE_AUTHOR("David Airlie, Jesse Barnes");
38MODULE_DESCRIPTION("DRM KMS helper");
39MODULE_LICENSE("GPL and additional rights");
40
41static LIST_HEAD(kernel_fb_helper_list);
42
43bool drm_fb_helper_force_kernel_mode(void)
44{
45 int i = 0;
46 bool ret, error = false;
47 struct drm_fb_helper *helper;
48
49 if (list_empty(&kernel_fb_helper_list))
50 return false;
51
52 list_for_each_entry(helper, &kernel_fb_helper_list, kernel_fb_list) {
53 for (i = 0; i < helper->crtc_count; i++) {
54 struct drm_mode_set *mode_set = &helper->crtc_info[i].mode_set;
55 ret = drm_crtc_helper_set_config(mode_set);
56 if (ret)
57 error = true;
58 }
59 }
60 return error;
61}
62
63int drm_fb_helper_panic(struct notifier_block *n, unsigned long ununsed,
64 void *panic_str)
65{
66 DRM_ERROR("panic occurred, switching back to text console\n");
67 return drm_fb_helper_force_kernel_mode();
68 return 0;
69}
70EXPORT_SYMBOL(drm_fb_helper_panic);
71
72static struct notifier_block paniced = {
73 .notifier_call = drm_fb_helper_panic,
74};
75
76/**
77 * drm_fb_helper_restore - restore the framebuffer console (kernel) config
78 *
79 * Restore's the kernel's fbcon mode, used for lastclose & panic paths.
80 */
81void drm_fb_helper_restore(void)
82{
83 bool ret;
84 ret = drm_fb_helper_force_kernel_mode();
85 if (ret == true)
86 DRM_ERROR("Failed to restore crtc configuration\n");
87}
88EXPORT_SYMBOL(drm_fb_helper_restore);
89
90static void drm_fb_helper_restore_work_fn(struct work_struct *ignored)
91{
92 drm_fb_helper_restore();
93}
94static DECLARE_WORK(drm_fb_helper_restore_work, drm_fb_helper_restore_work_fn);
95
96static void drm_fb_helper_sysrq(int dummy1, struct tty_struct *dummy3)
97{
98 schedule_work(&drm_fb_helper_restore_work);
99}
100
101static struct sysrq_key_op sysrq_drm_fb_helper_restore_op = {
102 .handler = drm_fb_helper_sysrq,
103 .help_msg = "force-fb(V)",
104 .action_msg = "Restore framebuffer console",
105};
106
107static void drm_fb_helper_on(struct fb_info *info)
108{
109 struct drm_fb_helper *fb_helper = info->par;
110 struct drm_device *dev = fb_helper->dev;
111 struct drm_crtc *crtc;
112 struct drm_encoder *encoder;
113 int i;
114
115 /*
116 * For each CRTC in this fb, turn the crtc on then,
117 * find all associated encoders and turn them on.
118 */
119 for (i = 0; i < fb_helper->crtc_count; i++) {
120 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
121 struct drm_crtc_helper_funcs *crtc_funcs =
122 crtc->helper_private;
123
124 /* Only mess with CRTCs in this fb */
125 if (crtc->base.id != fb_helper->crtc_info[i].crtc_id ||
126 !crtc->enabled)
127 continue;
128
129 mutex_lock(&dev->mode_config.mutex);
130 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
131 mutex_unlock(&dev->mode_config.mutex);
132
133 /* Found a CRTC on this fb, now find encoders */
134 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
135 if (encoder->crtc == crtc) {
136 struct drm_encoder_helper_funcs *encoder_funcs;
137
138 encoder_funcs = encoder->helper_private;
139 mutex_lock(&dev->mode_config.mutex);
140 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
141 mutex_unlock(&dev->mode_config.mutex);
142 }
143 }
144 }
145 }
146}
147
148static void drm_fb_helper_off(struct fb_info *info, int dpms_mode)
149{
150 struct drm_fb_helper *fb_helper = info->par;
151 struct drm_device *dev = fb_helper->dev;
152 struct drm_crtc *crtc;
153 struct drm_encoder *encoder;
154 int i;
155
156 /*
157 * For each CRTC in this fb, find all associated encoders
158 * and turn them off, then turn off the CRTC.
159 */
160 for (i = 0; i < fb_helper->crtc_count; i++) {
161 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
162 struct drm_crtc_helper_funcs *crtc_funcs =
163 crtc->helper_private;
164
165 /* Only mess with CRTCs in this fb */
166 if (crtc->base.id != fb_helper->crtc_info[i].crtc_id ||
167 !crtc->enabled)
168 continue;
169
170 /* Found a CRTC on this fb, now find encoders */
171 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
172 if (encoder->crtc == crtc) {
173 struct drm_encoder_helper_funcs *encoder_funcs;
174
175 encoder_funcs = encoder->helper_private;
176 mutex_lock(&dev->mode_config.mutex);
177 encoder_funcs->dpms(encoder, dpms_mode);
178 mutex_unlock(&dev->mode_config.mutex);
179 }
180 }
181 if (dpms_mode == DRM_MODE_DPMS_OFF) {
182 mutex_lock(&dev->mode_config.mutex);
183 crtc_funcs->dpms(crtc, dpms_mode);
184 mutex_unlock(&dev->mode_config.mutex);
185 }
186 }
187 }
188}
189
190int drm_fb_helper_blank(int blank, struct fb_info *info)
191{
192 switch (blank) {
193 case FB_BLANK_UNBLANK:
194 drm_fb_helper_on(info);
195 break;
196 case FB_BLANK_NORMAL:
197 drm_fb_helper_off(info, DRM_MODE_DPMS_STANDBY);
198 break;
199 case FB_BLANK_HSYNC_SUSPEND:
200 drm_fb_helper_off(info, DRM_MODE_DPMS_STANDBY);
201 break;
202 case FB_BLANK_VSYNC_SUSPEND:
203 drm_fb_helper_off(info, DRM_MODE_DPMS_SUSPEND);
204 break;
205 case FB_BLANK_POWERDOWN:
206 drm_fb_helper_off(info, DRM_MODE_DPMS_OFF);
207 break;
208 }
209 return 0;
210}
211EXPORT_SYMBOL(drm_fb_helper_blank);
212
213static void drm_fb_helper_crtc_free(struct drm_fb_helper *helper)
214{
215 int i;
216
217 for (i = 0; i < helper->crtc_count; i++)
218 kfree(helper->crtc_info[i].mode_set.connectors);
219 kfree(helper->crtc_info);
220}
221
222int drm_fb_helper_init_crtc_count(struct drm_fb_helper *helper, int crtc_count, int max_conn_count)
223{
224 struct drm_device *dev = helper->dev;
225 struct drm_crtc *crtc;
226 int ret = 0;
227 int i;
228
229 helper->crtc_info = kcalloc(crtc_count, sizeof(struct drm_fb_helper_crtc), GFP_KERNEL);
230 if (!helper->crtc_info)
231 return -ENOMEM;
232
233 helper->crtc_count = crtc_count;
234
235 for (i = 0; i < crtc_count; i++) {
236 helper->crtc_info[i].mode_set.connectors =
237 kcalloc(max_conn_count,
238 sizeof(struct drm_connector *),
239 GFP_KERNEL);
240
241 if (!helper->crtc_info[i].mode_set.connectors) {
242 ret = -ENOMEM;
243 goto out_free;
244 }
245 helper->crtc_info[i].mode_set.num_connectors = 0;
246 }
247
248 i = 0;
249 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
250 helper->crtc_info[i].crtc_id = crtc->base.id;
251 helper->crtc_info[i].mode_set.crtc = crtc;
252 i++;
253 }
254 helper->conn_limit = max_conn_count;
255 return 0;
256out_free:
257 drm_fb_helper_crtc_free(helper);
258 return -ENOMEM;
259}
260EXPORT_SYMBOL(drm_fb_helper_init_crtc_count);
261
262int drm_fb_helper_setcolreg(unsigned regno,
263 unsigned red,
264 unsigned green,
265 unsigned blue,
266 unsigned transp,
267 struct fb_info *info)
268{
269 struct drm_fb_helper *fb_helper = info->par;
270 struct drm_device *dev = fb_helper->dev;
271 struct drm_crtc *crtc;
272 int i;
273
274 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
275 struct drm_framebuffer *fb = fb_helper->fb;
276
277 for (i = 0; i < fb_helper->crtc_count; i++) {
278 if (crtc->base.id == fb_helper->crtc_info[i].crtc_id)
279 break;
280 }
281 if (i == fb_helper->crtc_count)
282 continue;
283
284 if (regno > 255)
285 return 1;
286
287 if (fb->depth == 8) {
288 fb_helper->funcs->gamma_set(crtc, red, green, blue, regno);
289 return 0;
290 }
291
292 if (regno < 16) {
293 switch (fb->depth) {
294 case 15:
295 fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) |
296 ((green & 0xf800) >> 6) |
297 ((blue & 0xf800) >> 11);
298 break;
299 case 16:
300 fb->pseudo_palette[regno] = (red & 0xf800) |
301 ((green & 0xfc00) >> 5) |
302 ((blue & 0xf800) >> 11);
303 break;
304 case 24:
305 case 32:
306 fb->pseudo_palette[regno] =
307 (((red >> 8) & 0xff) << info->var.red.offset) |
308 (((green >> 8) & 0xff) << info->var.green.offset) |
309 (((blue >> 8) & 0xff) << info->var.blue.offset);
310 break;
311 }
312 }
313 }
314 return 0;
315}
316EXPORT_SYMBOL(drm_fb_helper_setcolreg);
317
318int drm_fb_helper_check_var(struct fb_var_screeninfo *var,
319 struct fb_info *info)
320{
321 struct drm_fb_helper *fb_helper = info->par;
322 struct drm_framebuffer *fb = fb_helper->fb;
323 int depth;
324
325 if (var->pixclock == -1 || !var->pixclock)
326 return -EINVAL;
327
328 /* Need to resize the fb object !!! */
329 if (var->xres > fb->width || var->yres > fb->height) {
330 DRM_ERROR("Requested width/height is greater than current fb "
331 "object %dx%d > %dx%d\n", var->xres, var->yres,
332 fb->width, fb->height);
333 DRM_ERROR("Need resizing code.\n");
334 return -EINVAL;
335 }
336
337 switch (var->bits_per_pixel) {
338 case 16:
339 depth = (var->green.length == 6) ? 16 : 15;
340 break;
341 case 32:
342 depth = (var->transp.length > 0) ? 32 : 24;
343 break;
344 default:
345 depth = var->bits_per_pixel;
346 break;
347 }
348
349 switch (depth) {
350 case 8:
351 var->red.offset = 0;
352 var->green.offset = 0;
353 var->blue.offset = 0;
354 var->red.length = 8;
355 var->green.length = 8;
356 var->blue.length = 8;
357 var->transp.length = 0;
358 var->transp.offset = 0;
359 break;
360 case 15:
361 var->red.offset = 10;
362 var->green.offset = 5;
363 var->blue.offset = 0;
364 var->red.length = 5;
365 var->green.length = 5;
366 var->blue.length = 5;
367 var->transp.length = 1;
368 var->transp.offset = 15;
369 break;
370 case 16:
371 var->red.offset = 11;
372 var->green.offset = 5;
373 var->blue.offset = 0;
374 var->red.length = 5;
375 var->green.length = 6;
376 var->blue.length = 5;
377 var->transp.length = 0;
378 var->transp.offset = 0;
379 break;
380 case 24:
381 var->red.offset = 16;
382 var->green.offset = 8;
383 var->blue.offset = 0;
384 var->red.length = 8;
385 var->green.length = 8;
386 var->blue.length = 8;
387 var->transp.length = 0;
388 var->transp.offset = 0;
389 break;
390 case 32:
391 var->red.offset = 16;
392 var->green.offset = 8;
393 var->blue.offset = 0;
394 var->red.length = 8;
395 var->green.length = 8;
396 var->blue.length = 8;
397 var->transp.length = 8;
398 var->transp.offset = 24;
399 break;
400 default:
401 return -EINVAL;
402 }
403 return 0;
404}
405EXPORT_SYMBOL(drm_fb_helper_check_var);
406
407/* this will let fbcon do the mode init */
408int drm_fb_helper_set_par(struct fb_info *info)
409{
410 struct drm_fb_helper *fb_helper = info->par;
411 struct drm_device *dev = fb_helper->dev;
412 struct fb_var_screeninfo *var = &info->var;
413 struct drm_crtc *crtc;
414 int ret;
415 int i;
416
417 if (var->pixclock != -1) {
418 DRM_ERROR("PIXEL CLCOK SET\n");
419 return -EINVAL;
420 }
421
422 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
423
424 for (i = 0; i < fb_helper->crtc_count; i++) {
425 if (crtc->base.id == fb_helper->crtc_info[i].crtc_id)
426 break;
427 }
428 if (i == fb_helper->crtc_count)
429 continue;
430
431 if (crtc->fb == fb_helper->crtc_info[i].mode_set.fb) {
432 mutex_lock(&dev->mode_config.mutex);
433 ret = crtc->funcs->set_config(&fb_helper->crtc_info->mode_set);
434 mutex_unlock(&dev->mode_config.mutex);
435 if (ret)
436 return ret;
437 }
438 }
439 return 0;
440}
441EXPORT_SYMBOL(drm_fb_helper_set_par);
442
443int drm_fb_helper_pan_display(struct fb_var_screeninfo *var,
444 struct fb_info *info)
445{
446 struct drm_fb_helper *fb_helper = info->par;
447 struct drm_device *dev = fb_helper->dev;
448 struct drm_mode_set *modeset;
449 struct drm_crtc *crtc;
450 int ret = 0;
451 int i;
452
453 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
454 for (i = 0; i < fb_helper->crtc_count; i++) {
455 if (crtc->base.id == fb_helper->crtc_info[i].crtc_id)
456 break;
457 }
458
459 if (i == fb_helper->crtc_count)
460 continue;
461
462 modeset = &fb_helper->crtc_info[i].mode_set;
463
464 modeset->x = var->xoffset;
465 modeset->y = var->yoffset;
466
467 if (modeset->num_connectors) {
468 mutex_lock(&dev->mode_config.mutex);
469 ret = crtc->funcs->set_config(modeset);
470 mutex_unlock(&dev->mode_config.mutex);
471 if (!ret) {
472 info->var.xoffset = var->xoffset;
473 info->var.yoffset = var->yoffset;
474 }
475 }
476 }
477 return ret;
478}
479EXPORT_SYMBOL(drm_fb_helper_pan_display);
480
481int drm_fb_helper_single_fb_probe(struct drm_device *dev,
482 int (*fb_create)(struct drm_device *dev,
483 uint32_t fb_width,
484 uint32_t fb_height,
485 uint32_t surface_width,
486 uint32_t surface_height,
487 struct drm_framebuffer **fb_ptr))
488{
489 struct drm_crtc *crtc;
490 struct drm_connector *connector;
491 unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1;
492 unsigned int surface_width = 0, surface_height = 0;
493 int new_fb = 0;
494 int crtc_count = 0;
495 int ret, i, conn_count = 0;
496 struct fb_info *info;
497 struct drm_framebuffer *fb;
498 struct drm_mode_set *modeset = NULL;
499 struct drm_fb_helper *fb_helper;
500
501 /* first up get a count of crtcs now in use and new min/maxes width/heights */
502 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
503 if (drm_helper_crtc_in_use(crtc)) {
504 if (crtc->desired_mode) {
505 if (crtc->desired_mode->hdisplay < fb_width)
506 fb_width = crtc->desired_mode->hdisplay;
507
508 if (crtc->desired_mode->vdisplay < fb_height)
509 fb_height = crtc->desired_mode->vdisplay;
510
511 if (crtc->desired_mode->hdisplay > surface_width)
512 surface_width = crtc->desired_mode->hdisplay;
513
514 if (crtc->desired_mode->vdisplay > surface_height)
515 surface_height = crtc->desired_mode->vdisplay;
516 }
517 crtc_count++;
518 }
519 }
520
521 if (crtc_count == 0 || fb_width == -1 || fb_height == -1) {
522 /* hmm everyone went away - assume VGA cable just fell out
523 and will come back later. */
524 return 0;
525 }
526
527 /* do we have an fb already? */
528 if (list_empty(&dev->mode_config.fb_kernel_list)) {
529 ret = (*fb_create)(dev, fb_width, fb_height, surface_width,
530 surface_height, &fb);
531 if (ret)
532 return -EINVAL;
533 new_fb = 1;
534 } else {
535 fb = list_first_entry(&dev->mode_config.fb_kernel_list,
536 struct drm_framebuffer, filp_head);
537
538 /* if someone hotplugs something bigger than we have already allocated, we are pwned.
539 As really we can't resize an fbdev that is in the wild currently due to fbdev
540 not really being designed for the lower layers moving stuff around under it.
541 - so in the grand style of things - punt. */
542 if ((fb->width < surface_width) ||
543 (fb->height < surface_height)) {
544 DRM_ERROR("Framebuffer not large enough to scale console onto.\n");
545 return -EINVAL;
546 }
547 }
548
549 info = fb->fbdev;
550 fb_helper = info->par;
551
552 crtc_count = 0;
553 /* okay we need to setup new connector sets in the crtcs */
554 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
555 modeset = &fb_helper->crtc_info[crtc_count].mode_set;
556 modeset->fb = fb;
557 conn_count = 0;
558 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
559 if (connector->encoder)
560 if (connector->encoder->crtc == modeset->crtc) {
561 modeset->connectors[conn_count] = connector;
562 conn_count++;
563 if (conn_count > fb_helper->conn_limit)
564 BUG();
565 }
566 }
567
568 for (i = conn_count; i < fb_helper->conn_limit; i++)
569 modeset->connectors[i] = NULL;
570
571 modeset->crtc = crtc;
572 crtc_count++;
573
574 modeset->num_connectors = conn_count;
575 if (modeset->crtc->desired_mode) {
576 if (modeset->mode)
577 drm_mode_destroy(dev, modeset->mode);
578 modeset->mode = drm_mode_duplicate(dev,
579 modeset->crtc->desired_mode);
580 }
581 }
582 fb_helper->crtc_count = crtc_count;
583 fb_helper->fb = fb;
584
585 if (new_fb) {
586 info->var.pixclock = -1;
587 if (register_framebuffer(info) < 0)
588 return -EINVAL;
589 } else {
590 drm_fb_helper_set_par(info);
591 }
592 printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
593 info->fix.id);
594
595 /* Switch back to kernel console on panic */
596 /* multi card linked list maybe */
597 if (list_empty(&kernel_fb_helper_list)) {
598 printk(KERN_INFO "registered panic notifier\n");
599 atomic_notifier_chain_register(&panic_notifier_list,
600 &paniced);
601 register_sysrq_key('v', &sysrq_drm_fb_helper_restore_op);
602 }
603 list_add(&fb_helper->kernel_fb_list, &kernel_fb_helper_list);
604 return 0;
605}
606EXPORT_SYMBOL(drm_fb_helper_single_fb_probe);
607
608void drm_fb_helper_free(struct drm_fb_helper *helper)
609{
610 list_del(&helper->kernel_fb_list);
611 if (list_empty(&kernel_fb_helper_list)) {
612 printk(KERN_INFO "unregistered panic notifier\n");
613 atomic_notifier_chain_unregister(&panic_notifier_list,
614 &paniced);
615 unregister_sysrq_key('v', &sysrq_drm_fb_helper_restore_op);
616 }
617 drm_fb_helper_crtc_free(helper);
618}
619EXPORT_SYMBOL(drm_fb_helper_free);
620
621void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch)
622{
623 info->fix.type = FB_TYPE_PACKED_PIXELS;
624 info->fix.visual = FB_VISUAL_TRUECOLOR;
625 info->fix.type_aux = 0;
626 info->fix.xpanstep = 1; /* doing it in hw */
627 info->fix.ypanstep = 1; /* doing it in hw */
628 info->fix.ywrapstep = 0;
629 info->fix.accel = FB_ACCEL_NONE;
630 info->fix.type_aux = 0;
631
632 info->fix.line_length = pitch;
633 return;
634}
635EXPORT_SYMBOL(drm_fb_helper_fill_fix);
636
637void drm_fb_helper_fill_var(struct fb_info *info, struct drm_framebuffer *fb,
638 uint32_t fb_width, uint32_t fb_height)
639{
640 info->pseudo_palette = fb->pseudo_palette;
641 info->var.xres_virtual = fb->width;
642 info->var.yres_virtual = fb->height;
643 info->var.bits_per_pixel = fb->bits_per_pixel;
644 info->var.xoffset = 0;
645 info->var.yoffset = 0;
646 info->var.activate = FB_ACTIVATE_NOW;
647 info->var.height = -1;
648 info->var.width = -1;
649
650 switch (fb->depth) {
651 case 8:
652 info->var.red.offset = 0;
653 info->var.green.offset = 0;
654 info->var.blue.offset = 0;
655 info->var.red.length = 8; /* 8bit DAC */
656 info->var.green.length = 8;
657 info->var.blue.length = 8;
658 info->var.transp.offset = 0;
659 info->var.transp.length = 0;
660 break;
661 case 15:
662 info->var.red.offset = 10;
663 info->var.green.offset = 5;
664 info->var.blue.offset = 0;
665 info->var.red.length = 5;
666 info->var.green.length = 5;
667 info->var.blue.length = 5;
668 info->var.transp.offset = 15;
669 info->var.transp.length = 1;
670 break;
671 case 16:
672 info->var.red.offset = 11;
673 info->var.green.offset = 5;
674 info->var.blue.offset = 0;
675 info->var.red.length = 5;
676 info->var.green.length = 6;
677 info->var.blue.length = 5;
678 info->var.transp.offset = 0;
679 break;
680 case 24:
681 info->var.red.offset = 16;
682 info->var.green.offset = 8;
683 info->var.blue.offset = 0;
684 info->var.red.length = 8;
685 info->var.green.length = 8;
686 info->var.blue.length = 8;
687 info->var.transp.offset = 0;
688 info->var.transp.length = 0;
689 break;
690 case 32:
691 info->var.red.offset = 16;
692 info->var.green.offset = 8;
693 info->var.blue.offset = 0;
694 info->var.red.length = 8;
695 info->var.green.length = 8;
696 info->var.blue.length = 8;
697 info->var.transp.offset = 24;
698 info->var.transp.length = 8;
699 break;
700 default:
701 break;
702 }
703
704 info->var.xres = fb_width;
705 info->var.yres = fb_height;
706}
707EXPORT_SYMBOL(drm_fb_helper_fill_var);
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index ffe8f4394d50..230c9ffdd5e9 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -164,7 +164,7 @@ EXPORT_SYMBOL(drm_gem_object_alloc);
164 * Removes the mapping from handle to filp for this object. 164 * Removes the mapping from handle to filp for this object.
165 */ 165 */
166static int 166static int
167drm_gem_handle_delete(struct drm_file *filp, int handle) 167drm_gem_handle_delete(struct drm_file *filp, u32 handle)
168{ 168{
169 struct drm_device *dev; 169 struct drm_device *dev;
170 struct drm_gem_object *obj; 170 struct drm_gem_object *obj;
@@ -207,7 +207,7 @@ drm_gem_handle_delete(struct drm_file *filp, int handle)
207int 207int
208drm_gem_handle_create(struct drm_file *file_priv, 208drm_gem_handle_create(struct drm_file *file_priv,
209 struct drm_gem_object *obj, 209 struct drm_gem_object *obj,
210 int *handlep) 210 u32 *handlep)
211{ 211{
212 int ret; 212 int ret;
213 213
@@ -221,7 +221,7 @@ again:
221 221
222 /* do the allocation under our spinlock */ 222 /* do the allocation under our spinlock */
223 spin_lock(&file_priv->table_lock); 223 spin_lock(&file_priv->table_lock);
224 ret = idr_get_new_above(&file_priv->object_idr, obj, 1, handlep); 224 ret = idr_get_new_above(&file_priv->object_idr, obj, 1, (int *)handlep);
225 spin_unlock(&file_priv->table_lock); 225 spin_unlock(&file_priv->table_lock);
226 if (ret == -EAGAIN) 226 if (ret == -EAGAIN)
227 goto again; 227 goto again;
@@ -237,7 +237,7 @@ EXPORT_SYMBOL(drm_gem_handle_create);
237/** Returns a reference to the object named by the handle. */ 237/** Returns a reference to the object named by the handle. */
238struct drm_gem_object * 238struct drm_gem_object *
239drm_gem_object_lookup(struct drm_device *dev, struct drm_file *filp, 239drm_gem_object_lookup(struct drm_device *dev, struct drm_file *filp,
240 int handle) 240 u32 handle)
241{ 241{
242 struct drm_gem_object *obj; 242 struct drm_gem_object *obj;
243 243
@@ -344,7 +344,7 @@ drm_gem_open_ioctl(struct drm_device *dev, void *data,
344 struct drm_gem_open *args = data; 344 struct drm_gem_open *args = data;
345 struct drm_gem_object *obj; 345 struct drm_gem_object *obj;
346 int ret; 346 int ret;
347 int handle; 347 u32 handle;
348 348
349 if (!(dev->driver->driver_features & DRIVER_GEM)) 349 if (!(dev->driver->driver_features & DRIVER_GEM))
350 return -ENODEV; 350 return -ENODEV;
@@ -539,7 +539,6 @@ int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma)
539 vma->vm_flags |= VM_RESERVED | VM_IO | VM_PFNMAP | VM_DONTEXPAND; 539 vma->vm_flags |= VM_RESERVED | VM_IO | VM_PFNMAP | VM_DONTEXPAND;
540 vma->vm_ops = obj->dev->driver->gem_vm_ops; 540 vma->vm_ops = obj->dev->driver->gem_vm_ops;
541 vma->vm_private_data = map->handle; 541 vma->vm_private_data = map->handle;
542 /* FIXME: use pgprot_writecombine when available */
543 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); 542 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
544 543
545 /* Take a ref for this mapping of the object, so that the fault 544 /* Take a ref for this mapping of the object, so that the fault
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index f85aaf21e783..0a6f0b3bdc78 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -37,6 +37,7 @@
37 37
38#include <linux/interrupt.h> /* For task queue support */ 38#include <linux/interrupt.h> /* For task queue support */
39 39
40#include <linux/vgaarb.h>
40/** 41/**
41 * Get interrupt from bus id. 42 * Get interrupt from bus id.
42 * 43 *
@@ -171,6 +172,26 @@ err:
171} 172}
172EXPORT_SYMBOL(drm_vblank_init); 173EXPORT_SYMBOL(drm_vblank_init);
173 174
175static void drm_irq_vgaarb_nokms(void *cookie, bool state)
176{
177 struct drm_device *dev = cookie;
178
179 if (dev->driver->vgaarb_irq) {
180 dev->driver->vgaarb_irq(dev, state);
181 return;
182 }
183
184 if (!dev->irq_enabled)
185 return;
186
187 if (state)
188 dev->driver->irq_uninstall(dev);
189 else {
190 dev->driver->irq_preinstall(dev);
191 dev->driver->irq_postinstall(dev);
192 }
193}
194
174/** 195/**
175 * Install IRQ handler. 196 * Install IRQ handler.
176 * 197 *
@@ -231,6 +252,9 @@ int drm_irq_install(struct drm_device *dev)
231 return ret; 252 return ret;
232 } 253 }
233 254
255 if (!drm_core_check_feature(dev, DRIVER_MODESET))
256 vga_client_register(dev->pdev, (void *)dev, drm_irq_vgaarb_nokms, NULL);
257
234 /* After installing handler */ 258 /* After installing handler */
235 ret = dev->driver->irq_postinstall(dev); 259 ret = dev->driver->irq_postinstall(dev);
236 if (ret < 0) { 260 if (ret < 0) {
@@ -279,6 +303,9 @@ int drm_irq_uninstall(struct drm_device * dev)
279 303
280 DRM_DEBUG("irq=%d\n", dev->pdev->irq); 304 DRM_DEBUG("irq=%d\n", dev->pdev->irq);
281 305
306 if (!drm_core_check_feature(dev, DRIVER_MODESET))
307 vga_client_register(dev->pdev, NULL, NULL, NULL);
308
282 dev->driver->irq_uninstall(dev); 309 dev->driver->irq_uninstall(dev);
283 310
284 free_irq(dev->pdev->irq, dev); 311 free_irq(dev->pdev->irq, dev);
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index 3e47869d6dae..c861d80fd779 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -44,6 +44,7 @@
44#include "drmP.h" 44#include "drmP.h"
45#include "drm_mm.h" 45#include "drm_mm.h"
46#include <linux/slab.h> 46#include <linux/slab.h>
47#include <linux/seq_file.h>
47 48
48#define MM_UNUSED_TARGET 4 49#define MM_UNUSED_TARGET 4
49 50
@@ -370,3 +371,23 @@ void drm_mm_takedown(struct drm_mm * mm)
370 BUG_ON(mm->num_unused != 0); 371 BUG_ON(mm->num_unused != 0);
371} 372}
372EXPORT_SYMBOL(drm_mm_takedown); 373EXPORT_SYMBOL(drm_mm_takedown);
374
375#if defined(CONFIG_DEBUG_FS)
376int drm_mm_dump_table(struct seq_file *m, struct drm_mm *mm)
377{
378 struct drm_mm_node *entry;
379 int total_used = 0, total_free = 0, total = 0;
380
381 list_for_each_entry(entry, &mm->ml_entry, ml_entry) {
382 seq_printf(m, "0x%08lx-0x%08lx: 0x%08lx: %s\n", entry->start, entry->start + entry->size, entry->size, entry->free ? "free" : "used");
383 total += entry->size;
384 if (entry->free)
385 total_free += entry->size;
386 else
387 total_used += entry->size;
388 }
389 seq_printf(m, "total: %d, used %d free %d\n", total, total_free, total_used);
390 return 0;
391}
392EXPORT_SYMBOL(drm_mm_dump_table);
393#endif
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 7914097b09c6..49404ce1666e 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -8,6 +8,8 @@
8 * Copyright © 2007 Dave Airlie 8 * Copyright © 2007 Dave Airlie
9 * Copyright © 2007-2008 Intel Corporation 9 * Copyright © 2007-2008 Intel Corporation
10 * Jesse Barnes <jesse.barnes@intel.com> 10 * Jesse Barnes <jesse.barnes@intel.com>
11 * Copyright 2005-2006 Luc Verhaegen
12 * Copyright (c) 2001, Andy Ritger aritger@nvidia.com
11 * 13 *
12 * Permission is hereby granted, free of charge, to any person obtaining a 14 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"), 15 * copy of this software and associated documentation files (the "Software"),
@@ -38,7 +40,6 @@
38#include "drm.h" 40#include "drm.h"
39#include "drm_crtc.h" 41#include "drm_crtc.h"
40 42
41#define DRM_MODESET_DEBUG "drm_mode"
42/** 43/**
43 * drm_mode_debug_printmodeline - debug print a mode 44 * drm_mode_debug_printmodeline - debug print a mode
44 * @dev: DRM device 45 * @dev: DRM device
@@ -51,8 +52,8 @@
51 */ 52 */
52void drm_mode_debug_printmodeline(struct drm_display_mode *mode) 53void drm_mode_debug_printmodeline(struct drm_display_mode *mode)
53{ 54{
54 DRM_DEBUG_MODE(DRM_MODESET_DEBUG, 55 DRM_DEBUG_KMS("Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d "
55 "Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x\n", 56 "0x%x 0x%x\n",
56 mode->base.id, mode->name, mode->vrefresh, mode->clock, 57 mode->base.id, mode->name, mode->vrefresh, mode->clock,
57 mode->hdisplay, mode->hsync_start, 58 mode->hdisplay, mode->hsync_start,
58 mode->hsync_end, mode->htotal, 59 mode->hsync_end, mode->htotal,
@@ -62,6 +63,420 @@ void drm_mode_debug_printmodeline(struct drm_display_mode *mode)
62EXPORT_SYMBOL(drm_mode_debug_printmodeline); 63EXPORT_SYMBOL(drm_mode_debug_printmodeline);
63 64
64/** 65/**
66 * drm_cvt_mode -create a modeline based on CVT algorithm
67 * @dev: DRM device
68 * @hdisplay: hdisplay size
69 * @vdisplay: vdisplay size
70 * @vrefresh : vrefresh rate
71 * @reduced : Whether the GTF calculation is simplified
72 * @interlaced:Whether the interlace is supported
73 *
74 * LOCKING:
75 * none.
76 *
77 * return the modeline based on CVT algorithm
78 *
79 * This function is called to generate the modeline based on CVT algorithm
80 * according to the hdisplay, vdisplay, vrefresh.
81 * It is based from the VESA(TM) Coordinated Video Timing Generator by
82 * Graham Loveridge April 9, 2003 available at
83 * http://www.vesa.org/public/CVT/CVTd6r1.xls
84 *
85 * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c.
86 * What I have done is to translate it by using integer calculation.
87 */
88#define HV_FACTOR 1000
89struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay,
90 int vdisplay, int vrefresh,
91 bool reduced, bool interlaced)
92{
93 /* 1) top/bottom margin size (% of height) - default: 1.8, */
94#define CVT_MARGIN_PERCENTAGE 18
95 /* 2) character cell horizontal granularity (pixels) - default 8 */
96#define CVT_H_GRANULARITY 8
97 /* 3) Minimum vertical porch (lines) - default 3 */
98#define CVT_MIN_V_PORCH 3
99 /* 4) Minimum number of vertical back porch lines - default 6 */
100#define CVT_MIN_V_BPORCH 6
101 /* Pixel Clock step (kHz) */
102#define CVT_CLOCK_STEP 250
103 struct drm_display_mode *drm_mode;
104 bool margins = false;
105 unsigned int vfieldrate, hperiod;
106 int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync;
107 int interlace;
108
109 /* allocate the drm_display_mode structure. If failure, we will
110 * return directly
111 */
112 drm_mode = drm_mode_create(dev);
113 if (!drm_mode)
114 return NULL;
115
116 /* the CVT default refresh rate is 60Hz */
117 if (!vrefresh)
118 vrefresh = 60;
119
120 /* the required field fresh rate */
121 if (interlaced)
122 vfieldrate = vrefresh * 2;
123 else
124 vfieldrate = vrefresh;
125
126 /* horizontal pixels */
127 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY);
128
129 /* determine the left&right borders */
130 hmargin = 0;
131 if (margins) {
132 hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000;
133 hmargin -= hmargin % CVT_H_GRANULARITY;
134 }
135 /* find the total active pixels */
136 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin;
137
138 /* find the number of lines per field */
139 if (interlaced)
140 vdisplay_rnd = vdisplay / 2;
141 else
142 vdisplay_rnd = vdisplay;
143
144 /* find the top & bottom borders */
145 vmargin = 0;
146 if (margins)
147 vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000;
148
149 drm_mode->vdisplay = vdisplay + 2 * vmargin;
150
151 /* Interlaced */
152 if (interlaced)
153 interlace = 1;
154 else
155 interlace = 0;
156
157 /* Determine VSync Width from aspect ratio */
158 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay))
159 vsync = 4;
160 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay))
161 vsync = 5;
162 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay))
163 vsync = 6;
164 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay))
165 vsync = 7;
166 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay))
167 vsync = 7;
168 else /* custom */
169 vsync = 10;
170
171 if (!reduced) {
172 /* simplify the GTF calculation */
173 /* 4) Minimum time of vertical sync + back porch interval (µs)
174 * default 550.0
175 */
176 int tmp1, tmp2;
177#define CVT_MIN_VSYNC_BP 550
178 /* 3) Nominal HSync width (% of line period) - default 8 */
179#define CVT_HSYNC_PERCENTAGE 8
180 unsigned int hblank_percentage;
181 int vsyncandback_porch, vback_porch, hblank;
182
183 /* estimated the horizontal period */
184 tmp1 = HV_FACTOR * 1000000 -
185 CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate;
186 tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 +
187 interlace;
188 hperiod = tmp1 * 2 / (tmp2 * vfieldrate);
189
190 tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1;
191 /* 9. Find number of lines in sync + backporch */
192 if (tmp1 < (vsync + CVT_MIN_V_PORCH))
193 vsyncandback_porch = vsync + CVT_MIN_V_PORCH;
194 else
195 vsyncandback_porch = tmp1;
196 /* 10. Find number of lines in back porch */
197 vback_porch = vsyncandback_porch - vsync;
198 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin +
199 vsyncandback_porch + CVT_MIN_V_PORCH;
200 /* 5) Definition of Horizontal blanking time limitation */
201 /* Gradient (%/kHz) - default 600 */
202#define CVT_M_FACTOR 600
203 /* Offset (%) - default 40 */
204#define CVT_C_FACTOR 40
205 /* Blanking time scaling factor - default 128 */
206#define CVT_K_FACTOR 128
207 /* Scaling factor weighting - default 20 */
208#define CVT_J_FACTOR 20
209#define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256)
210#define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \
211 CVT_J_FACTOR)
212 /* 12. Find ideal blanking duty cycle from formula */
213 hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME *
214 hperiod / 1000;
215 /* 13. Blanking time */
216 if (hblank_percentage < 20 * HV_FACTOR)
217 hblank_percentage = 20 * HV_FACTOR;
218 hblank = drm_mode->hdisplay * hblank_percentage /
219 (100 * HV_FACTOR - hblank_percentage);
220 hblank -= hblank % (2 * CVT_H_GRANULARITY);
221 /* 14. find the total pixes per line */
222 drm_mode->htotal = drm_mode->hdisplay + hblank;
223 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2;
224 drm_mode->hsync_start = drm_mode->hsync_end -
225 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100;
226 drm_mode->hsync_start += CVT_H_GRANULARITY -
227 drm_mode->hsync_start % CVT_H_GRANULARITY;
228 /* fill the Vsync values */
229 drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH;
230 drm_mode->vsync_end = drm_mode->vsync_start + vsync;
231 } else {
232 /* Reduced blanking */
233 /* Minimum vertical blanking interval time (µs)- default 460 */
234#define CVT_RB_MIN_VBLANK 460
235 /* Fixed number of clocks for horizontal sync */
236#define CVT_RB_H_SYNC 32
237 /* Fixed number of clocks for horizontal blanking */
238#define CVT_RB_H_BLANK 160
239 /* Fixed number of lines for vertical front porch - default 3*/
240#define CVT_RB_VFPORCH 3
241 int vbilines;
242 int tmp1, tmp2;
243 /* 8. Estimate Horizontal period. */
244 tmp1 = HV_FACTOR * 1000000 -
245 CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate;
246 tmp2 = vdisplay_rnd + 2 * vmargin;
247 hperiod = tmp1 / (tmp2 * vfieldrate);
248 /* 9. Find number of lines in vertical blanking */
249 vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1;
250 /* 10. Check if vertical blanking is sufficient */
251 if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH))
252 vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH;
253 /* 11. Find total number of lines in vertical field */
254 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines;
255 /* 12. Find total number of pixels in a line */
256 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK;
257 /* Fill in HSync values */
258 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2;
259 drm_mode->hsync_start = drm_mode->hsync_end = CVT_RB_H_SYNC;
260 }
261 /* 15/13. Find pixel clock frequency (kHz for xf86) */
262 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod;
263 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP;
264 /* 18/16. Find actual vertical frame frequency */
265 /* ignore - just set the mode flag for interlaced */
266 if (interlaced)
267 drm_mode->vtotal *= 2;
268 /* Fill the mode line name */
269 drm_mode_set_name(drm_mode);
270 if (reduced)
271 drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC |
272 DRM_MODE_FLAG_NVSYNC);
273 else
274 drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC |
275 DRM_MODE_FLAG_NHSYNC);
276 if (interlaced)
277 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE;
278
279 return drm_mode;
280}
281EXPORT_SYMBOL(drm_cvt_mode);
282
283/**
284 * drm_gtf_mode - create the modeline based on GTF algorithm
285 *
286 * @dev :drm device
287 * @hdisplay :hdisplay size
288 * @vdisplay :vdisplay size
289 * @vrefresh :vrefresh rate.
290 * @interlaced :whether the interlace is supported
291 * @margins :whether the margin is supported
292 *
293 * LOCKING.
294 * none.
295 *
296 * return the modeline based on GTF algorithm
297 *
298 * This function is to create the modeline based on the GTF algorithm.
299 * Generalized Timing Formula is derived from:
300 * GTF Spreadsheet by Andy Morrish (1/5/97)
301 * available at http://www.vesa.org
302 *
303 * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c.
304 * What I have done is to translate it by using integer calculation.
305 * I also refer to the function of fb_get_mode in the file of
306 * drivers/video/fbmon.c
307 */
308struct drm_display_mode *drm_gtf_mode(struct drm_device *dev, int hdisplay,
309 int vdisplay, int vrefresh,
310 bool interlaced, int margins)
311{
312 /* 1) top/bottom margin size (% of height) - default: 1.8, */
313#define GTF_MARGIN_PERCENTAGE 18
314 /* 2) character cell horizontal granularity (pixels) - default 8 */
315#define GTF_CELL_GRAN 8
316 /* 3) Minimum vertical porch (lines) - default 3 */
317#define GTF_MIN_V_PORCH 1
318 /* width of vsync in lines */
319#define V_SYNC_RQD 3
320 /* width of hsync as % of total line */
321#define H_SYNC_PERCENT 8
322 /* min time of vsync + back porch (microsec) */
323#define MIN_VSYNC_PLUS_BP 550
324 /* blanking formula gradient */
325#define GTF_M 600
326 /* blanking formula offset */
327#define GTF_C 40
328 /* blanking formula scaling factor */
329#define GTF_K 128
330 /* blanking formula scaling factor */
331#define GTF_J 20
332 /* C' and M' are part of the Blanking Duty Cycle computation */
333#define GTF_C_PRIME (((GTF_C - GTF_J) * GTF_K / 256) + GTF_J)
334#define GTF_M_PRIME (GTF_K * GTF_M / 256)
335 struct drm_display_mode *drm_mode;
336 unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd;
337 int top_margin, bottom_margin;
338 int interlace;
339 unsigned int hfreq_est;
340 int vsync_plus_bp, vback_porch;
341 unsigned int vtotal_lines, vfieldrate_est, hperiod;
342 unsigned int vfield_rate, vframe_rate;
343 int left_margin, right_margin;
344 unsigned int total_active_pixels, ideal_duty_cycle;
345 unsigned int hblank, total_pixels, pixel_freq;
346 int hsync, hfront_porch, vodd_front_porch_lines;
347 unsigned int tmp1, tmp2;
348
349 drm_mode = drm_mode_create(dev);
350 if (!drm_mode)
351 return NULL;
352
353 /* 1. In order to give correct results, the number of horizontal
354 * pixels requested is first processed to ensure that it is divisible
355 * by the character size, by rounding it to the nearest character
356 * cell boundary:
357 */
358 hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN;
359 hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN;
360
361 /* 2. If interlace is requested, the number of vertical lines assumed
362 * by the calculation must be halved, as the computation calculates
363 * the number of vertical lines per field.
364 */
365 if (interlaced)
366 vdisplay_rnd = vdisplay / 2;
367 else
368 vdisplay_rnd = vdisplay;
369
370 /* 3. Find the frame rate required: */
371 if (interlaced)
372 vfieldrate_rqd = vrefresh * 2;
373 else
374 vfieldrate_rqd = vrefresh;
375
376 /* 4. Find number of lines in Top margin: */
377 top_margin = 0;
378 if (margins)
379 top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) /
380 1000;
381 /* 5. Find number of lines in bottom margin: */
382 bottom_margin = top_margin;
383
384 /* 6. If interlace is required, then set variable interlace: */
385 if (interlaced)
386 interlace = 1;
387 else
388 interlace = 0;
389
390 /* 7. Estimate the Horizontal frequency */
391 {
392 tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500;
393 tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) *
394 2 + interlace;
395 hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1;
396 }
397
398 /* 8. Find the number of lines in V sync + back porch */
399 /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */
400 vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000;
401 vsync_plus_bp = (vsync_plus_bp + 500) / 1000;
402 /* 9. Find the number of lines in V back porch alone: */
403 vback_porch = vsync_plus_bp - V_SYNC_RQD;
404 /* 10. Find the total number of lines in Vertical field period: */
405 vtotal_lines = vdisplay_rnd + top_margin + bottom_margin +
406 vsync_plus_bp + GTF_MIN_V_PORCH;
407 /* 11. Estimate the Vertical field frequency: */
408 vfieldrate_est = hfreq_est / vtotal_lines;
409 /* 12. Find the actual horizontal period: */
410 hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines);
411
412 /* 13. Find the actual Vertical field frequency: */
413 vfield_rate = hfreq_est / vtotal_lines;
414 /* 14. Find the Vertical frame frequency: */
415 if (interlaced)
416 vframe_rate = vfield_rate / 2;
417 else
418 vframe_rate = vfield_rate;
419 /* 15. Find number of pixels in left margin: */
420 if (margins)
421 left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) /
422 1000;
423 else
424 left_margin = 0;
425
426 /* 16.Find number of pixels in right margin: */
427 right_margin = left_margin;
428 /* 17.Find total number of active pixels in image and left and right */
429 total_active_pixels = hdisplay_rnd + left_margin + right_margin;
430 /* 18.Find the ideal blanking duty cycle from blanking duty cycle */
431 ideal_duty_cycle = GTF_C_PRIME * 1000 -
432 (GTF_M_PRIME * 1000000 / hfreq_est);
433 /* 19.Find the number of pixels in the blanking time to the nearest
434 * double character cell: */
435 hblank = total_active_pixels * ideal_duty_cycle /
436 (100000 - ideal_duty_cycle);
437 hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN);
438 hblank = hblank * 2 * GTF_CELL_GRAN;
439 /* 20.Find total number of pixels: */
440 total_pixels = total_active_pixels + hblank;
441 /* 21.Find pixel clock frequency: */
442 pixel_freq = total_pixels * hfreq_est / 1000;
443 /* Stage 1 computations are now complete; I should really pass
444 * the results to another function and do the Stage 2 computations,
445 * but I only need a few more values so I'll just append the
446 * computations here for now */
447 /* 17. Find the number of pixels in the horizontal sync period: */
448 hsync = H_SYNC_PERCENT * total_pixels / 100;
449 hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN;
450 hsync = hsync * GTF_CELL_GRAN;
451 /* 18. Find the number of pixels in horizontal front porch period */
452 hfront_porch = hblank / 2 - hsync;
453 /* 36. Find the number of lines in the odd front porch period: */
454 vodd_front_porch_lines = GTF_MIN_V_PORCH ;
455
456 /* finally, pack the results in the mode struct */
457 drm_mode->hdisplay = hdisplay_rnd;
458 drm_mode->hsync_start = hdisplay_rnd + hfront_porch;
459 drm_mode->hsync_end = drm_mode->hsync_start + hsync;
460 drm_mode->htotal = total_pixels;
461 drm_mode->vdisplay = vdisplay_rnd;
462 drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines;
463 drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD;
464 drm_mode->vtotal = vtotal_lines;
465
466 drm_mode->clock = pixel_freq;
467
468 drm_mode_set_name(drm_mode);
469 drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC;
470
471 if (interlaced) {
472 drm_mode->vtotal *= 2;
473 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE;
474 }
475
476 return drm_mode;
477}
478EXPORT_SYMBOL(drm_gtf_mode);
479/**
65 * drm_mode_set_name - set the name on a mode 480 * drm_mode_set_name - set the name on a mode
66 * @mode: name will be set in this mode 481 * @mode: name will be set in this mode
67 * 482 *
@@ -151,7 +566,9 @@ EXPORT_SYMBOL(drm_mode_height);
151 * FIXME: why is this needed? shouldn't vrefresh be set already? 566 * FIXME: why is this needed? shouldn't vrefresh be set already?
152 * 567 *
153 * RETURNS: 568 * RETURNS:
154 * Vertical refresh rate of @mode x 1000. For precision reasons. 569 * Vertical refresh rate. It will be the result of actual value plus 0.5.
570 * If it is 70.288, it will return 70Hz.
571 * If it is 59.6, it will return 60Hz.
155 */ 572 */
156int drm_mode_vrefresh(struct drm_display_mode *mode) 573int drm_mode_vrefresh(struct drm_display_mode *mode)
157{ 574{
@@ -161,14 +578,13 @@ int drm_mode_vrefresh(struct drm_display_mode *mode)
161 if (mode->vrefresh > 0) 578 if (mode->vrefresh > 0)
162 refresh = mode->vrefresh; 579 refresh = mode->vrefresh;
163 else if (mode->htotal > 0 && mode->vtotal > 0) { 580 else if (mode->htotal > 0 && mode->vtotal > 0) {
581 int vtotal;
582 vtotal = mode->vtotal;
164 /* work out vrefresh the value will be x1000 */ 583 /* work out vrefresh the value will be x1000 */
165 calc_val = (mode->clock * 1000); 584 calc_val = (mode->clock * 1000);
166
167 calc_val /= mode->htotal; 585 calc_val /= mode->htotal;
168 calc_val *= 1000; 586 refresh = (calc_val + vtotal / 2) / vtotal;
169 calc_val /= mode->vtotal;
170 587
171 refresh = calc_val;
172 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 588 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
173 refresh *= 2; 589 refresh *= 2;
174 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 590 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -403,8 +819,7 @@ void drm_mode_prune_invalid(struct drm_device *dev,
403 list_del(&mode->head); 819 list_del(&mode->head);
404 if (verbose) { 820 if (verbose) {
405 drm_mode_debug_printmodeline(mode); 821 drm_mode_debug_printmodeline(mode);
406 DRM_DEBUG_MODE(DRM_MODESET_DEBUG, 822 DRM_DEBUG_KMS("Not using %s mode %d\n",
407 "Not using %s mode %d\n",
408 mode->name, mode->status); 823 mode->name, mode->status);
409 } 824 }
410 drm_mode_destroy(dev, mode); 825 drm_mode_destroy(dev, mode);
diff --git a/drivers/gpu/drm/drm_proc.c b/drivers/gpu/drm/drm_proc.c
index bbd4b3d1074a..d379c4f2892f 100644
--- a/drivers/gpu/drm/drm_proc.c
+++ b/drivers/gpu/drm/drm_proc.c
@@ -106,20 +106,25 @@ int drm_proc_create_files(struct drm_info_list *files, int count,
106 continue; 106 continue;
107 107
108 tmp = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); 108 tmp = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
109 ent = create_proc_entry(files[i].name, S_IFREG | S_IRUGO, root); 109 if (tmp == NULL) {
110 ret = -1;
111 goto fail;
112 }
113 tmp->minor = minor;
114 tmp->info_ent = &files[i];
115 list_add(&tmp->list, &minor->proc_nodes.list);
116
117 ent = proc_create_data(files[i].name, S_IRUGO, root,
118 &drm_proc_fops, tmp);
110 if (!ent) { 119 if (!ent) {
111 DRM_ERROR("Cannot create /proc/dri/%s/%s\n", 120 DRM_ERROR("Cannot create /proc/dri/%s/%s\n",
112 name, files[i].name); 121 name, files[i].name);
122 list_del(&tmp->list);
113 kfree(tmp); 123 kfree(tmp);
114 ret = -1; 124 ret = -1;
115 goto fail; 125 goto fail;
116 } 126 }
117 127
118 ent->proc_fops = &drm_proc_fops;
119 ent->data = tmp;
120 tmp->minor = minor;
121 tmp->info_ent = &files[i];
122 list_add(&(tmp->list), &(minor->proc_nodes.list));
123 } 128 }
124 return 0; 129 return 0;
125 130
diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
index 5301f226cb1c..7e42b7e9d43a 100644
--- a/drivers/gpu/drm/drm_sysfs.c
+++ b/drivers/gpu/drm/drm_sysfs.c
@@ -16,6 +16,7 @@
16#include <linux/kdev_t.h> 16#include <linux/kdev_t.h>
17#include <linux/err.h> 17#include <linux/err.h>
18 18
19#include "drm_sysfs.h"
19#include "drm_core.h" 20#include "drm_core.h"
20#include "drmP.h" 21#include "drmP.h"
21 22
@@ -253,6 +254,7 @@ static ssize_t subconnector_show(struct device *device,
253 case DRM_MODE_CONNECTOR_Composite: 254 case DRM_MODE_CONNECTOR_Composite:
254 case DRM_MODE_CONNECTOR_SVIDEO: 255 case DRM_MODE_CONNECTOR_SVIDEO:
255 case DRM_MODE_CONNECTOR_Component: 256 case DRM_MODE_CONNECTOR_Component:
257 case DRM_MODE_CONNECTOR_TV:
256 prop = dev->mode_config.tv_subconnector_property; 258 prop = dev->mode_config.tv_subconnector_property;
257 is_tv = 1; 259 is_tv = 1;
258 break; 260 break;
@@ -293,6 +295,7 @@ static ssize_t select_subconnector_show(struct device *device,
293 case DRM_MODE_CONNECTOR_Composite: 295 case DRM_MODE_CONNECTOR_Composite:
294 case DRM_MODE_CONNECTOR_SVIDEO: 296 case DRM_MODE_CONNECTOR_SVIDEO:
295 case DRM_MODE_CONNECTOR_Component: 297 case DRM_MODE_CONNECTOR_Component:
298 case DRM_MODE_CONNECTOR_TV:
296 prop = dev->mode_config.tv_select_subconnector_property; 299 prop = dev->mode_config.tv_select_subconnector_property;
297 is_tv = 1; 300 is_tv = 1;
298 break; 301 break;
@@ -391,6 +394,7 @@ int drm_sysfs_connector_add(struct drm_connector *connector)
391 case DRM_MODE_CONNECTOR_Composite: 394 case DRM_MODE_CONNECTOR_Composite:
392 case DRM_MODE_CONNECTOR_SVIDEO: 395 case DRM_MODE_CONNECTOR_SVIDEO:
393 case DRM_MODE_CONNECTOR_Component: 396 case DRM_MODE_CONNECTOR_Component:
397 case DRM_MODE_CONNECTOR_TV:
394 for (i = 0; i < ARRAY_SIZE(connector_attrs_opt1); i++) { 398 for (i = 0; i < ARRAY_SIZE(connector_attrs_opt1); i++) {
395 ret = device_create_file(&connector->kdev, &connector_attrs_opt1[i]); 399 ret = device_create_file(&connector->kdev, &connector_attrs_opt1[i]);
396 if (ret) 400 if (ret)
@@ -519,3 +523,27 @@ void drm_sysfs_device_remove(struct drm_minor *minor)
519{ 523{
520 device_unregister(&minor->kdev); 524 device_unregister(&minor->kdev);
521} 525}
526
527
528/**
529 * drm_class_device_register - Register a struct device in the drm class.
530 *
531 * @dev: pointer to struct device to register.
532 *
533 * @dev should have all relevant members pre-filled with the exception
534 * of the class member. In particular, the device_type member must
535 * be set.
536 */
537
538int drm_class_device_register(struct device *dev)
539{
540 dev->class = drm_class;
541 return device_register(dev);
542}
543EXPORT_SYMBOL_GPL(drm_class_device_register);
544
545void drm_class_device_unregister(struct device *dev)
546{
547 return device_unregister(dev);
548}
549EXPORT_SYMBOL_GPL(drm_class_device_unregister);
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 30d6b99fb302..5269dfa5f620 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -4,10 +4,10 @@
4 4
5ccflags-y := -Iinclude/drm 5ccflags-y := -Iinclude/drm
6i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \ 6i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \
7 i915_debugfs.o \
7 i915_suspend.o \ 8 i915_suspend.o \
8 i915_gem.o \ 9 i915_gem.o \
9 i915_gem_debug.o \ 10 i915_gem_debug.o \
10 i915_gem_debugfs.o \
11 i915_gem_tiling.o \ 11 i915_gem_tiling.o \
12 intel_display.o \ 12 intel_display.o \
13 intel_crt.o \ 13 intel_crt.o \
diff --git a/drivers/gpu/drm/i915/i915_gem_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index cb3b97405fbf..1e3bdcee863c 100644
--- a/drivers/gpu/drm/i915/i915_gem_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -158,16 +158,37 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
158 struct drm_device *dev = node->minor->dev; 158 struct drm_device *dev = node->minor->dev;
159 drm_i915_private_t *dev_priv = dev->dev_private; 159 drm_i915_private_t *dev_priv = dev->dev_private;
160 160
161 seq_printf(m, "Interrupt enable: %08x\n", 161 if (!IS_IGDNG(dev)) {
162 I915_READ(IER)); 162 seq_printf(m, "Interrupt enable: %08x\n",
163 seq_printf(m, "Interrupt identity: %08x\n", 163 I915_READ(IER));
164 I915_READ(IIR)); 164 seq_printf(m, "Interrupt identity: %08x\n",
165 seq_printf(m, "Interrupt mask: %08x\n", 165 I915_READ(IIR));
166 I915_READ(IMR)); 166 seq_printf(m, "Interrupt mask: %08x\n",
167 seq_printf(m, "Pipe A stat: %08x\n", 167 I915_READ(IMR));
168 I915_READ(PIPEASTAT)); 168 seq_printf(m, "Pipe A stat: %08x\n",
169 seq_printf(m, "Pipe B stat: %08x\n", 169 I915_READ(PIPEASTAT));
170 I915_READ(PIPEBSTAT)); 170 seq_printf(m, "Pipe B stat: %08x\n",
171 I915_READ(PIPEBSTAT));
172 } else {
173 seq_printf(m, "North Display Interrupt enable: %08x\n",
174 I915_READ(DEIER));
175 seq_printf(m, "North Display Interrupt identity: %08x\n",
176 I915_READ(DEIIR));
177 seq_printf(m, "North Display Interrupt mask: %08x\n",
178 I915_READ(DEIMR));
179 seq_printf(m, "South Display Interrupt enable: %08x\n",
180 I915_READ(SDEIER));
181 seq_printf(m, "South Display Interrupt identity: %08x\n",
182 I915_READ(SDEIIR));
183 seq_printf(m, "South Display Interrupt mask: %08x\n",
184 I915_READ(SDEIMR));
185 seq_printf(m, "Graphics Interrupt enable: %08x\n",
186 I915_READ(GTIER));
187 seq_printf(m, "Graphics Interrupt identity: %08x\n",
188 I915_READ(GTIIR));
189 seq_printf(m, "Graphics Interrupt mask: %08x\n",
190 I915_READ(GTIMR));
191 }
171 seq_printf(m, "Interrupts received: %d\n", 192 seq_printf(m, "Interrupts received: %d\n",
172 atomic_read(&dev_priv->irq_received)); 193 atomic_read(&dev_priv->irq_received));
173 if (dev_priv->hw_status_page != NULL) { 194 if (dev_priv->hw_status_page != NULL) {
@@ -312,15 +333,13 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data)
312 struct drm_info_node *node = (struct drm_info_node *) m->private; 333 struct drm_info_node *node = (struct drm_info_node *) m->private;
313 struct drm_device *dev = node->minor->dev; 334 struct drm_device *dev = node->minor->dev;
314 drm_i915_private_t *dev_priv = dev->dev_private; 335 drm_i915_private_t *dev_priv = dev->dev_private;
315 unsigned int head, tail, mask; 336 unsigned int head, tail;
316 337
317 head = I915_READ(PRB0_HEAD) & HEAD_ADDR; 338 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
318 tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; 339 tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
319 mask = dev_priv->ring.tail_mask;
320 340
321 seq_printf(m, "RingHead : %08x\n", head); 341 seq_printf(m, "RingHead : %08x\n", head);
322 seq_printf(m, "RingTail : %08x\n", tail); 342 seq_printf(m, "RingTail : %08x\n", tail);
323 seq_printf(m, "RingMask : %08x\n", mask);
324 seq_printf(m, "RingSize : %08lx\n", dev_priv->ring.Size); 343 seq_printf(m, "RingSize : %08lx\n", dev_priv->ring.Size);
325 seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD)); 344 seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD));
326 345
@@ -363,7 +382,37 @@ out:
363 return 0; 382 return 0;
364} 383}
365 384
366static struct drm_info_list i915_gem_debugfs_list[] = { 385static int i915_registers_info(struct seq_file *m, void *data) {
386 struct drm_info_node *node = (struct drm_info_node *) m->private;
387 struct drm_device *dev = node->minor->dev;
388 drm_i915_private_t *dev_priv = dev->dev_private;
389 uint32_t reg;
390
391#define DUMP_RANGE(start, end) \
392 for (reg=start; reg < end; reg += 4) \
393 seq_printf(m, "%08x\t%08x\n", reg, I915_READ(reg));
394
395 DUMP_RANGE(0x00000, 0x00fff); /* VGA registers */
396 DUMP_RANGE(0x02000, 0x02fff); /* instruction, memory, interrupt control registers */
397 DUMP_RANGE(0x03000, 0x031ff); /* FENCE and PPGTT control registers */
398 DUMP_RANGE(0x03200, 0x03fff); /* frame buffer compression registers */
399 DUMP_RANGE(0x05000, 0x05fff); /* I/O control registers */
400 DUMP_RANGE(0x06000, 0x06fff); /* clock control registers */
401 DUMP_RANGE(0x07000, 0x07fff); /* 3D internal debug registers */
402 DUMP_RANGE(0x07400, 0x088ff); /* GPE debug registers */
403 DUMP_RANGE(0x0a000, 0x0afff); /* display palette registers */
404 DUMP_RANGE(0x10000, 0x13fff); /* MMIO MCHBAR */
405 DUMP_RANGE(0x30000, 0x3ffff); /* overlay registers */
406 DUMP_RANGE(0x60000, 0x6ffff); /* display engine pipeline registers */
407 DUMP_RANGE(0x70000, 0x72fff); /* display and cursor registers */
408 DUMP_RANGE(0x73000, 0x73fff); /* performance counters */
409
410 return 0;
411}
412
413
414static struct drm_info_list i915_debugfs_list[] = {
415 {"i915_regs", i915_registers_info, 0},
367 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, 416 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
368 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, 417 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
369 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, 418 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
@@ -377,19 +426,19 @@ static struct drm_info_list i915_gem_debugfs_list[] = {
377 {"i915_batchbuffers", i915_batchbuffer_info, 0}, 426 {"i915_batchbuffers", i915_batchbuffer_info, 0},
378 {"i915_error_state", i915_error_state, 0}, 427 {"i915_error_state", i915_error_state, 0},
379}; 428};
380#define I915_GEM_DEBUGFS_ENTRIES ARRAY_SIZE(i915_gem_debugfs_list) 429#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
381 430
382int i915_gem_debugfs_init(struct drm_minor *minor) 431int i915_debugfs_init(struct drm_minor *minor)
383{ 432{
384 return drm_debugfs_create_files(i915_gem_debugfs_list, 433 return drm_debugfs_create_files(i915_debugfs_list,
385 I915_GEM_DEBUGFS_ENTRIES, 434 I915_DEBUGFS_ENTRIES,
386 minor->debugfs_root, minor); 435 minor->debugfs_root, minor);
387} 436}
388 437
389void i915_gem_debugfs_cleanup(struct drm_minor *minor) 438void i915_debugfs_cleanup(struct drm_minor *minor)
390{ 439{
391 drm_debugfs_remove_files(i915_gem_debugfs_list, 440 drm_debugfs_remove_files(i915_debugfs_list,
392 I915_GEM_DEBUGFS_ENTRIES, minor); 441 I915_DEBUGFS_ENTRIES, minor);
393} 442}
394 443
395#endif /* CONFIG_DEBUG_FS */ 444#endif /* CONFIG_DEBUG_FS */
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 50d1f782768c..5a49a1867b35 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -29,11 +29,11 @@
29#include "drmP.h" 29#include "drmP.h"
30#include "drm.h" 30#include "drm.h"
31#include "drm_crtc_helper.h" 31#include "drm_crtc_helper.h"
32#include "drm_fb_helper.h"
32#include "intel_drv.h" 33#include "intel_drv.h"
33#include "i915_drm.h" 34#include "i915_drm.h"
34#include "i915_drv.h" 35#include "i915_drv.h"
35 36#include <linux/vgaarb.h>
36#define I915_DRV "i915_drv"
37 37
38/* Really want an OS-independent resettable timer. Would like to have 38/* Really want an OS-independent resettable timer. Would like to have
39 * this loop run for (eg) 3 sec, but have the timer reset every time 39 * this loop run for (eg) 3 sec, but have the timer reset every time
@@ -80,6 +80,34 @@ int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
80 return -EBUSY; 80 return -EBUSY;
81} 81}
82 82
83/* As a ringbuffer is only allowed to wrap between instructions, fill
84 * the tail with NOOPs.
85 */
86int i915_wrap_ring(struct drm_device *dev)
87{
88 drm_i915_private_t *dev_priv = dev->dev_private;
89 volatile unsigned int *virt;
90 int rem;
91
92 rem = dev_priv->ring.Size - dev_priv->ring.tail;
93 if (dev_priv->ring.space < rem) {
94 int ret = i915_wait_ring(dev, rem, __func__);
95 if (ret)
96 return ret;
97 }
98 dev_priv->ring.space -= rem;
99
100 virt = (unsigned int *)
101 (dev_priv->ring.virtual_start + dev_priv->ring.tail);
102 rem /= 4;
103 while (rem--)
104 *virt++ = MI_NOOP;
105
106 dev_priv->ring.tail = 0;
107
108 return 0;
109}
110
83/** 111/**
84 * Sets up the hardware status page for devices that need a physical address 112 * Sets up the hardware status page for devices that need a physical address
85 * in the register. 113 * in the register.
@@ -101,7 +129,7 @@ static int i915_init_phys_hws(struct drm_device *dev)
101 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 129 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
102 130
103 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); 131 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
104 DRM_DEBUG_DRIVER(I915_DRV, "Enabled hardware status page\n"); 132 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
105 return 0; 133 return 0;
106} 134}
107 135
@@ -187,8 +215,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
187 master_priv->sarea_priv = (drm_i915_sarea_t *) 215 master_priv->sarea_priv = (drm_i915_sarea_t *)
188 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); 216 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
189 } else { 217 } else {
190 DRM_DEBUG_DRIVER(I915_DRV, 218 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
191 "sarea not found assuming DRI2 userspace\n");
192 } 219 }
193 220
194 if (init->ring_size != 0) { 221 if (init->ring_size != 0) {
@@ -200,7 +227,6 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
200 } 227 }
201 228
202 dev_priv->ring.Size = init->ring_size; 229 dev_priv->ring.Size = init->ring_size;
203 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
204 230
205 dev_priv->ring.map.offset = init->ring_start; 231 dev_priv->ring.map.offset = init->ring_start;
206 dev_priv->ring.map.size = init->ring_size; 232 dev_priv->ring.map.size = init->ring_size;
@@ -238,7 +264,7 @@ static int i915_dma_resume(struct drm_device * dev)
238{ 264{
239 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 265 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
240 266
241 DRM_DEBUG_DRIVER(I915_DRV, "%s\n", __func__); 267 DRM_DEBUG_DRIVER("%s\n", __func__);
242 268
243 if (dev_priv->ring.map.handle == NULL) { 269 if (dev_priv->ring.map.handle == NULL) {
244 DRM_ERROR("can not ioremap virtual address for" 270 DRM_ERROR("can not ioremap virtual address for"
@@ -251,14 +277,14 @@ static int i915_dma_resume(struct drm_device * dev)
251 DRM_ERROR("Can not find hardware status page\n"); 277 DRM_ERROR("Can not find hardware status page\n");
252 return -EINVAL; 278 return -EINVAL;
253 } 279 }
254 DRM_DEBUG_DRIVER(I915_DRV, "hw status page @ %p\n", 280 DRM_DEBUG_DRIVER("hw status page @ %p\n",
255 dev_priv->hw_status_page); 281 dev_priv->hw_status_page);
256 282
257 if (dev_priv->status_gfx_addr != 0) 283 if (dev_priv->status_gfx_addr != 0)
258 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); 284 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
259 else 285 else
260 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); 286 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
261 DRM_DEBUG_DRIVER(I915_DRV, "Enabled hardware status page\n"); 287 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
262 288
263 return 0; 289 return 0;
264} 290}
@@ -552,7 +578,7 @@ static int i915_dispatch_flip(struct drm_device * dev)
552 if (!master_priv->sarea_priv) 578 if (!master_priv->sarea_priv)
553 return -EINVAL; 579 return -EINVAL;
554 580
555 DRM_DEBUG_DRIVER(I915_DRV, "%s: page=%d pfCurrentPage=%d\n", 581 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
556 __func__, 582 __func__,
557 dev_priv->current_page, 583 dev_priv->current_page,
558 master_priv->sarea_priv->pf_current_page); 584 master_priv->sarea_priv->pf_current_page);
@@ -633,8 +659,7 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
633 return -EINVAL; 659 return -EINVAL;
634 } 660 }
635 661
636 DRM_DEBUG_DRIVER(I915_DRV, 662 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
637 "i915 batchbuffer, start %x used %d cliprects %d\n",
638 batch->start, batch->used, batch->num_cliprects); 663 batch->start, batch->used, batch->num_cliprects);
639 664
640 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 665 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
@@ -681,8 +706,7 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
681 void *batch_data; 706 void *batch_data;
682 int ret; 707 int ret;
683 708
684 DRM_DEBUG_DRIVER(I915_DRV, 709 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
685 "i915 cmdbuffer, buf %p sz %d cliprects %d\n",
686 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); 710 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
687 711
688 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 712 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
@@ -735,7 +759,7 @@ static int i915_flip_bufs(struct drm_device *dev, void *data,
735{ 759{
736 int ret; 760 int ret;
737 761
738 DRM_DEBUG_DRIVER(I915_DRV, "%s\n", __func__); 762 DRM_DEBUG_DRIVER("%s\n", __func__);
739 763
740 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 764 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
741 765
@@ -778,7 +802,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
778 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; 802 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
779 break; 803 break;
780 default: 804 default:
781 DRM_DEBUG_DRIVER(I915_DRV, "Unknown parameter %d\n", 805 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
782 param->param); 806 param->param);
783 return -EINVAL; 807 return -EINVAL;
784 } 808 }
@@ -819,7 +843,7 @@ static int i915_setparam(struct drm_device *dev, void *data,
819 dev_priv->fence_reg_start = param->value; 843 dev_priv->fence_reg_start = param->value;
820 break; 844 break;
821 default: 845 default:
822 DRM_DEBUG_DRIVER(I915_DRV, "unknown parameter %d\n", 846 DRM_DEBUG_DRIVER("unknown parameter %d\n",
823 param->param); 847 param->param);
824 return -EINVAL; 848 return -EINVAL;
825 } 849 }
@@ -846,7 +870,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
846 return 0; 870 return 0;
847 } 871 }
848 872
849 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr); 873 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
850 874
851 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); 875 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
852 876
@@ -868,13 +892,25 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
868 892
869 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 893 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
870 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); 894 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
871 DRM_DEBUG_DRIVER(I915_DRV, "load hws HWS_PGA with gfx mem 0x%x\n", 895 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
872 dev_priv->status_gfx_addr); 896 dev_priv->status_gfx_addr);
873 DRM_DEBUG_DRIVER(I915_DRV, "load hws at %p\n", 897 DRM_DEBUG_DRIVER("load hws at %p\n",
874 dev_priv->hw_status_page); 898 dev_priv->hw_status_page);
875 return 0; 899 return 0;
876} 900}
877 901
902static int i915_get_bridge_dev(struct drm_device *dev)
903{
904 struct drm_i915_private *dev_priv = dev->dev_private;
905
906 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
907 if (!dev_priv->bridge_dev) {
908 DRM_ERROR("bridge device not found\n");
909 return -1;
910 }
911 return 0;
912}
913
878/** 914/**
879 * i915_probe_agp - get AGP bootup configuration 915 * i915_probe_agp - get AGP bootup configuration
880 * @pdev: PCI device 916 * @pdev: PCI device
@@ -888,20 +924,13 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
888static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size, 924static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
889 uint32_t *preallocated_size) 925 uint32_t *preallocated_size)
890{ 926{
891 struct pci_dev *bridge_dev; 927 struct drm_i915_private *dev_priv = dev->dev_private;
892 u16 tmp = 0; 928 u16 tmp = 0;
893 unsigned long overhead; 929 unsigned long overhead;
894 unsigned long stolen; 930 unsigned long stolen;
895 931
896 bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
897 if (!bridge_dev) {
898 DRM_ERROR("bridge device not found\n");
899 return -1;
900 }
901
902 /* Get the fb aperture size and "stolen" memory amount. */ 932 /* Get the fb aperture size and "stolen" memory amount. */
903 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp); 933 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
904 pci_dev_put(bridge_dev);
905 934
906 *aperture_size = 1024 * 1024; 935 *aperture_size = 1024 * 1024;
907 *preallocated_size = 1024 * 1024; 936 *preallocated_size = 1024 * 1024;
@@ -984,6 +1013,19 @@ static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
984 return 0; 1013 return 0;
985} 1014}
986 1015
1016/* true = enable decode, false = disable decoder */
1017static unsigned int i915_vga_set_decode(void *cookie, bool state)
1018{
1019 struct drm_device *dev = cookie;
1020
1021 intel_modeset_vga_set_state(dev, state);
1022 if (state)
1023 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1024 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1025 else
1026 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1027}
1028
987static int i915_load_modeset_init(struct drm_device *dev, 1029static int i915_load_modeset_init(struct drm_device *dev,
988 unsigned long prealloc_size, 1030 unsigned long prealloc_size,
989 unsigned long agp_size) 1031 unsigned long agp_size)
@@ -1029,6 +1071,11 @@ static int i915_load_modeset_init(struct drm_device *dev,
1029 if (ret) 1071 if (ret)
1030 DRM_INFO("failed to find VBIOS tables\n"); 1072 DRM_INFO("failed to find VBIOS tables\n");
1031 1073
1074 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1075 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1076 if (ret)
1077 goto destroy_ringbuffer;
1078
1032 ret = drm_irq_install(dev); 1079 ret = drm_irq_install(dev);
1033 if (ret) 1080 if (ret)
1034 goto destroy_ringbuffer; 1081 goto destroy_ringbuffer;
@@ -1153,11 +1200,16 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1153 base = drm_get_resource_start(dev, mmio_bar); 1200 base = drm_get_resource_start(dev, mmio_bar);
1154 size = drm_get_resource_len(dev, mmio_bar); 1201 size = drm_get_resource_len(dev, mmio_bar);
1155 1202
1203 if (i915_get_bridge_dev(dev)) {
1204 ret = -EIO;
1205 goto free_priv;
1206 }
1207
1156 dev_priv->regs = ioremap(base, size); 1208 dev_priv->regs = ioremap(base, size);
1157 if (!dev_priv->regs) { 1209 if (!dev_priv->regs) {
1158 DRM_ERROR("failed to map registers\n"); 1210 DRM_ERROR("failed to map registers\n");
1159 ret = -EIO; 1211 ret = -EIO;
1160 goto free_priv; 1212 goto put_bridge;
1161 } 1213 }
1162 1214
1163 dev_priv->mm.gtt_mapping = 1215 dev_priv->mm.gtt_mapping =
@@ -1269,6 +1321,8 @@ out_iomapfree:
1269 io_mapping_free(dev_priv->mm.gtt_mapping); 1321 io_mapping_free(dev_priv->mm.gtt_mapping);
1270out_rmmap: 1322out_rmmap:
1271 iounmap(dev_priv->regs); 1323 iounmap(dev_priv->regs);
1324put_bridge:
1325 pci_dev_put(dev_priv->bridge_dev);
1272free_priv: 1326free_priv:
1273 kfree(dev_priv); 1327 kfree(dev_priv);
1274 return ret; 1328 return ret;
@@ -1289,6 +1343,7 @@ int i915_driver_unload(struct drm_device *dev)
1289 1343
1290 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1344 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1291 drm_irq_uninstall(dev); 1345 drm_irq_uninstall(dev);
1346 vga_client_register(dev->pdev, NULL, NULL, NULL);
1292 } 1347 }
1293 1348
1294 if (dev->pdev->msi_enabled) 1349 if (dev->pdev->msi_enabled)
@@ -1312,6 +1367,7 @@ int i915_driver_unload(struct drm_device *dev)
1312 i915_gem_lastclose(dev); 1367 i915_gem_lastclose(dev);
1313 } 1368 }
1314 1369
1370 pci_dev_put(dev_priv->bridge_dev);
1315 kfree(dev->dev_private); 1371 kfree(dev->dev_private);
1316 1372
1317 return 0; 1373 return 0;
@@ -1321,7 +1377,7 @@ int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1321{ 1377{
1322 struct drm_i915_file_private *i915_file_priv; 1378 struct drm_i915_file_private *i915_file_priv;
1323 1379
1324 DRM_DEBUG_DRIVER(I915_DRV, "\n"); 1380 DRM_DEBUG_DRIVER("\n");
1325 i915_file_priv = (struct drm_i915_file_private *) 1381 i915_file_priv = (struct drm_i915_file_private *)
1326 kmalloc(sizeof(*i915_file_priv), GFP_KERNEL); 1382 kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
1327 1383
@@ -1352,7 +1408,7 @@ void i915_driver_lastclose(struct drm_device * dev)
1352 drm_i915_private_t *dev_priv = dev->dev_private; 1408 drm_i915_private_t *dev_priv = dev->dev_private;
1353 1409
1354 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { 1410 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1355 intelfb_restore(); 1411 drm_fb_helper_restore();
1356 return; 1412 return;
1357 } 1413 }
1358 1414
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fc4b68aa2d05..dbe568c9327b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -37,12 +37,15 @@
37#include <linux/console.h> 37#include <linux/console.h>
38#include "drm_crtc_helper.h" 38#include "drm_crtc_helper.h"
39 39
40static unsigned int i915_modeset = -1; 40static int i915_modeset = -1;
41module_param_named(modeset, i915_modeset, int, 0400); 41module_param_named(modeset, i915_modeset, int, 0400);
42 42
43unsigned int i915_fbpercrtc = 0; 43unsigned int i915_fbpercrtc = 0;
44module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); 44module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
45 45
46unsigned int i915_powersave = 1;
47module_param_named(powersave, i915_powersave, int, 0400);
48
46static struct drm_driver driver; 49static struct drm_driver driver;
47 50
48static struct pci_device_id pciidlist[] = { 51static struct pci_device_id pciidlist[] = {
@@ -188,8 +191,8 @@ static struct drm_driver driver = {
188 .master_create = i915_master_create, 191 .master_create = i915_master_create,
189 .master_destroy = i915_master_destroy, 192 .master_destroy = i915_master_destroy,
190#if defined(CONFIG_DEBUG_FS) 193#if defined(CONFIG_DEBUG_FS)
191 .debugfs_init = i915_gem_debugfs_init, 194 .debugfs_init = i915_debugfs_init,
192 .debugfs_cleanup = i915_gem_debugfs_cleanup, 195 .debugfs_cleanup = i915_debugfs_cleanup,
193#endif 196#endif
194 .gem_init_object = i915_gem_init_object, 197 .gem_init_object = i915_gem_init_object,
195 .gem_free_object = i915_gem_free_object, 198 .gem_free_object = i915_gem_free_object,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5b4f87e55621..a0632f8e76ac 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -85,7 +85,6 @@ struct drm_i915_gem_phys_object {
85}; 85};
86 86
87typedef struct _drm_i915_ring_buffer { 87typedef struct _drm_i915_ring_buffer {
88 int tail_mask;
89 unsigned long Size; 88 unsigned long Size;
90 u8 *virtual_start; 89 u8 *virtual_start;
91 int head; 90 int head;
@@ -156,6 +155,7 @@ typedef struct drm_i915_private {
156 155
157 void __iomem *regs; 156 void __iomem *regs;
158 157
158 struct pci_dev *bridge_dev;
159 drm_i915_ring_buffer_t ring; 159 drm_i915_ring_buffer_t ring;
160 160
161 drm_dma_handle_t *status_page_dmah; 161 drm_dma_handle_t *status_page_dmah;
@@ -311,7 +311,7 @@ typedef struct drm_i915_private {
311 u32 saveIMR; 311 u32 saveIMR;
312 u32 saveCACHE_MODE_0; 312 u32 saveCACHE_MODE_0;
313 u32 saveD_STATE; 313 u32 saveD_STATE;
314 u32 saveCG_2D_DIS; 314 u32 saveDSPCLK_GATE_D;
315 u32 saveMI_ARB_STATE; 315 u32 saveMI_ARB_STATE;
316 u32 saveSWF0[16]; 316 u32 saveSWF0[16];
317 u32 saveSWF1[16]; 317 u32 saveSWF1[16];
@@ -443,6 +443,14 @@ typedef struct drm_i915_private {
443 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 443 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
444 } mm; 444 } mm;
445 struct sdvo_device_mapping sdvo_mappings[2]; 445 struct sdvo_device_mapping sdvo_mappings[2];
446
447 /* Reclocking support */
448 bool render_reclock_avail;
449 bool lvds_downclock_avail;
450 struct work_struct idle_work;
451 struct timer_list idle_timer;
452 bool busy;
453 u16 orig_clock;
446} drm_i915_private_t; 454} drm_i915_private_t;
447 455
448/** driver private structure attached to each drm_gem_object */ 456/** driver private structure attached to each drm_gem_object */
@@ -575,6 +583,7 @@ enum intel_chip_family {
575extern struct drm_ioctl_desc i915_ioctls[]; 583extern struct drm_ioctl_desc i915_ioctls[];
576extern int i915_max_ioctl; 584extern int i915_max_ioctl;
577extern unsigned int i915_fbpercrtc; 585extern unsigned int i915_fbpercrtc;
586extern unsigned int i915_powersave;
578 587
579extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 588extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
580extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 589extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
@@ -730,8 +739,8 @@ void i915_gem_dump_object(struct drm_gem_object *obj, int len,
730void i915_dump_lru(struct drm_device *dev, const char *where); 739void i915_dump_lru(struct drm_device *dev, const char *where);
731 740
732/* i915_debugfs.c */ 741/* i915_debugfs.c */
733int i915_gem_debugfs_init(struct drm_minor *minor); 742int i915_debugfs_init(struct drm_minor *minor);
734void i915_gem_debugfs_cleanup(struct drm_minor *minor); 743void i915_debugfs_cleanup(struct drm_minor *minor);
735 744
736/* i915_suspend.c */ 745/* i915_suspend.c */
737extern int i915_save_state(struct drm_device *dev); 746extern int i915_save_state(struct drm_device *dev);
@@ -757,6 +766,7 @@ static inline void opregion_enable_asle(struct drm_device *dev) { return; }
757/* modesetting */ 766/* modesetting */
758extern void intel_modeset_init(struct drm_device *dev); 767extern void intel_modeset_init(struct drm_device *dev);
759extern void intel_modeset_cleanup(struct drm_device *dev); 768extern void intel_modeset_cleanup(struct drm_device *dev);
769extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
760 770
761/** 771/**
762 * Lock test for when it's just for synchronization of ring access. 772 * Lock test for when it's just for synchronization of ring access.
@@ -781,33 +791,32 @@ extern void intel_modeset_cleanup(struct drm_device *dev);
781 791
782#define I915_VERBOSE 0 792#define I915_VERBOSE 0
783 793
784#define RING_LOCALS unsigned int outring, ringmask, outcount; \ 794#define RING_LOCALS volatile unsigned int *ring_virt__;
785 volatile char *virt; 795
786 796#define BEGIN_LP_RING(n) do { \
787#define BEGIN_LP_RING(n) do { \ 797 int bytes__ = 4*(n); \
788 if (I915_VERBOSE) \ 798 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
789 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ 799 /* a wrap must occur between instructions so pad beforehand */ \
790 if (dev_priv->ring.space < (n)*4) \ 800 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
791 i915_wait_ring(dev, (n)*4, __func__); \ 801 i915_wrap_ring(dev); \
792 outcount = 0; \ 802 if (unlikely (dev_priv->ring.space < bytes__)) \
793 outring = dev_priv->ring.tail; \ 803 i915_wait_ring(dev, bytes__, __func__); \
794 ringmask = dev_priv->ring.tail_mask; \ 804 ring_virt__ = (unsigned int *) \
795 virt = dev_priv->ring.virtual_start; \ 805 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
806 dev_priv->ring.tail += bytes__; \
807 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
808 dev_priv->ring.space -= bytes__; \
796} while (0) 809} while (0)
797 810
798#define OUT_RING(n) do { \ 811#define OUT_RING(n) do { \
799 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 812 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
800 *(volatile unsigned int *)(virt + outring) = (n); \ 813 *ring_virt__++ = (n); \
801 outcount++; \
802 outring += 4; \
803 outring &= ringmask; \
804} while (0) 814} while (0)
805 815
806#define ADVANCE_LP_RING() do { \ 816#define ADVANCE_LP_RING() do { \
807 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 817 if (I915_VERBOSE) \
808 dev_priv->ring.tail = outring; \ 818 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
809 dev_priv->ring.space -= outcount * 4; \ 819 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
810 I915_WRITE(PRB0_TAIL, outring); \
811} while(0) 820} while(0)
812 821
813/** 822/**
@@ -830,6 +839,7 @@ extern void intel_modeset_cleanup(struct drm_device *dev);
830#define I915_GEM_HWS_INDEX 0x20 839#define I915_GEM_HWS_INDEX 0x20
831#define I915_BREADCRUMB_INDEX 0x21 840#define I915_BREADCRUMB_INDEX 0x21
832 841
842extern int i915_wrap_ring(struct drm_device * dev);
833extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 843extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
834 844
835#define IS_I830(dev) ((dev)->pci_device == 0x3577) 845#define IS_I830(dev) ((dev)->pci_device == 0x3577)
@@ -903,6 +913,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
903/* dsparb controlled by hw only */ 913/* dsparb controlled by hw only */
904#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev)) 914#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
905 915
916#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
917#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
918
906#define PRIMARY_RINGBUFFER_SIZE (128*1024) 919#define PRIMARY_RINGBUFFER_SIZE (128*1024)
907 920
908#endif 921#endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 80e5ba490dc2..c67317112f4a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -29,6 +29,7 @@
29#include "drm.h" 29#include "drm.h"
30#include "i915_drm.h" 30#include "i915_drm.h"
31#include "i915_drv.h" 31#include "i915_drv.h"
32#include "intel_drv.h"
32#include <linux/swap.h> 33#include <linux/swap.h>
33#include <linux/pci.h> 34#include <linux/pci.h>
34 35
@@ -111,7 +112,8 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
111{ 112{
112 struct drm_i915_gem_create *args = data; 113 struct drm_i915_gem_create *args = data;
113 struct drm_gem_object *obj; 114 struct drm_gem_object *obj;
114 int handle, ret; 115 int ret;
116 u32 handle;
115 117
116 args->size = roundup(args->size, PAGE_SIZE); 118 args->size = roundup(args->size, PAGE_SIZE);
117 119
@@ -981,6 +983,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
981 struct drm_i915_private *dev_priv = dev->dev_private; 983 struct drm_i915_private *dev_priv = dev->dev_private;
982 struct drm_i915_gem_set_domain *args = data; 984 struct drm_i915_gem_set_domain *args = data;
983 struct drm_gem_object *obj; 985 struct drm_gem_object *obj;
986 struct drm_i915_gem_object *obj_priv;
984 uint32_t read_domains = args->read_domains; 987 uint32_t read_domains = args->read_domains;
985 uint32_t write_domain = args->write_domain; 988 uint32_t write_domain = args->write_domain;
986 int ret; 989 int ret;
@@ -1004,15 +1007,17 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1004 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 1007 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1005 if (obj == NULL) 1008 if (obj == NULL)
1006 return -EBADF; 1009 return -EBADF;
1010 obj_priv = obj->driver_private;
1007 1011
1008 mutex_lock(&dev->struct_mutex); 1012 mutex_lock(&dev->struct_mutex);
1013
1014 intel_mark_busy(dev, obj);
1015
1009#if WATCH_BUF 1016#if WATCH_BUF
1010 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n", 1017 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1011 obj, obj->size, read_domains, write_domain); 1018 obj, obj->size, read_domains, write_domain);
1012#endif 1019#endif
1013 if (read_domains & I915_GEM_DOMAIN_GTT) { 1020 if (read_domains & I915_GEM_DOMAIN_GTT) {
1014 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1015
1016 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); 1021 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1017 1022
1018 /* Update the LRU on the fence for the CPU access that's 1023 /* Update the LRU on the fence for the CPU access that's
@@ -2776,6 +2781,8 @@ i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2776 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); 2781 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2777 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); 2782 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2778 2783
2784 intel_mark_busy(dev, obj);
2785
2779#if WATCH_BUF 2786#if WATCH_BUF
2780 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", 2787 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2781 __func__, obj, 2788 __func__, obj,
@@ -4093,7 +4100,6 @@ i915_gem_init_ringbuffer(struct drm_device *dev)
4093 4100
4094 /* Set up the kernel mapping for the ring. */ 4101 /* Set up the kernel mapping for the ring. */
4095 ring->Size = obj->size; 4102 ring->Size = obj->size;
4096 ring->tail_mask = obj->size - 1;
4097 4103
4098 ring->map.offset = dev->agp->base + obj_priv->gtt_offset; 4104 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4099 ring->map.size = obj->size; 4105 ring->map.size = obj->size;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index a2d527b22ec4..200e398453ca 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -94,23 +94,15 @@
94static int 94static int
95intel_alloc_mchbar_resource(struct drm_device *dev) 95intel_alloc_mchbar_resource(struct drm_device *dev)
96{ 96{
97 struct pci_dev *bridge_dev;
98 drm_i915_private_t *dev_priv = dev->dev_private; 97 drm_i915_private_t *dev_priv = dev->dev_private;
99 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; 98 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
100 u32 temp_lo, temp_hi = 0; 99 u32 temp_lo, temp_hi = 0;
101 u64 mchbar_addr; 100 u64 mchbar_addr;
102 int ret = 0; 101 int ret = 0;
103 102
104 bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
105 if (!bridge_dev) {
106 DRM_DEBUG("no bridge dev?!\n");
107 ret = -ENODEV;
108 goto out;
109 }
110
111 if (IS_I965G(dev)) 103 if (IS_I965G(dev))
112 pci_read_config_dword(bridge_dev, reg + 4, &temp_hi); 104 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
113 pci_read_config_dword(bridge_dev, reg, &temp_lo); 105 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
114 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 106 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
115 107
116 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 108 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
@@ -118,30 +110,28 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
118 if (mchbar_addr && 110 if (mchbar_addr &&
119 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) { 111 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
120 ret = 0; 112 ret = 0;
121 goto out_put; 113 goto out;
122 } 114 }
123#endif 115#endif
124 116
125 /* Get some space for it */ 117 /* Get some space for it */
126 ret = pci_bus_alloc_resource(bridge_dev->bus, &dev_priv->mch_res, 118 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
127 MCHBAR_SIZE, MCHBAR_SIZE, 119 MCHBAR_SIZE, MCHBAR_SIZE,
128 PCIBIOS_MIN_MEM, 120 PCIBIOS_MIN_MEM,
129 0, pcibios_align_resource, 121 0, pcibios_align_resource,
130 bridge_dev); 122 dev_priv->bridge_dev);
131 if (ret) { 123 if (ret) {
132 DRM_DEBUG("failed bus alloc: %d\n", ret); 124 DRM_DEBUG("failed bus alloc: %d\n", ret);
133 dev_priv->mch_res.start = 0; 125 dev_priv->mch_res.start = 0;
134 goto out_put; 126 goto out;
135 } 127 }
136 128
137 if (IS_I965G(dev)) 129 if (IS_I965G(dev))
138 pci_write_config_dword(bridge_dev, reg + 4, 130 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
139 upper_32_bits(dev_priv->mch_res.start)); 131 upper_32_bits(dev_priv->mch_res.start));
140 132
141 pci_write_config_dword(bridge_dev, reg, 133 pci_write_config_dword(dev_priv->bridge_dev, reg,
142 lower_32_bits(dev_priv->mch_res.start)); 134 lower_32_bits(dev_priv->mch_res.start));
143out_put:
144 pci_dev_put(bridge_dev);
145out: 135out:
146 return ret; 136 return ret;
147} 137}
@@ -150,44 +140,36 @@ out:
150static bool 140static bool
151intel_setup_mchbar(struct drm_device *dev) 141intel_setup_mchbar(struct drm_device *dev)
152{ 142{
153 struct pci_dev *bridge_dev; 143 drm_i915_private_t *dev_priv = dev->dev_private;
154 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; 144 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
155 u32 temp; 145 u32 temp;
156 bool need_disable = false, enabled; 146 bool need_disable = false, enabled;
157 147
158 bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
159 if (!bridge_dev) {
160 DRM_DEBUG("no bridge dev?!\n");
161 goto out;
162 }
163
164 if (IS_I915G(dev) || IS_I915GM(dev)) { 148 if (IS_I915G(dev) || IS_I915GM(dev)) {
165 pci_read_config_dword(bridge_dev, DEVEN_REG, &temp); 149 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
166 enabled = !!(temp & DEVEN_MCHBAR_EN); 150 enabled = !!(temp & DEVEN_MCHBAR_EN);
167 } else { 151 } else {
168 pci_read_config_dword(bridge_dev, mchbar_reg, &temp); 152 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
169 enabled = temp & 1; 153 enabled = temp & 1;
170 } 154 }
171 155
172 /* If it's already enabled, don't have to do anything */ 156 /* If it's already enabled, don't have to do anything */
173 if (enabled) 157 if (enabled)
174 goto out_put; 158 goto out;
175 159
176 if (intel_alloc_mchbar_resource(dev)) 160 if (intel_alloc_mchbar_resource(dev))
177 goto out_put; 161 goto out;
178 162
179 need_disable = true; 163 need_disable = true;
180 164
181 /* Space is allocated or reserved, so enable it. */ 165 /* Space is allocated or reserved, so enable it. */
182 if (IS_I915G(dev) || IS_I915GM(dev)) { 166 if (IS_I915G(dev) || IS_I915GM(dev)) {
183 pci_write_config_dword(bridge_dev, DEVEN_REG, 167 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
184 temp | DEVEN_MCHBAR_EN); 168 temp | DEVEN_MCHBAR_EN);
185 } else { 169 } else {
186 pci_read_config_dword(bridge_dev, mchbar_reg, &temp); 170 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
187 pci_write_config_dword(bridge_dev, mchbar_reg, temp | 1); 171 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
188 } 172 }
189out_put:
190 pci_dev_put(bridge_dev);
191out: 173out:
192 return need_disable; 174 return need_disable;
193} 175}
@@ -196,25 +178,18 @@ static void
196intel_teardown_mchbar(struct drm_device *dev, bool disable) 178intel_teardown_mchbar(struct drm_device *dev, bool disable)
197{ 179{
198 drm_i915_private_t *dev_priv = dev->dev_private; 180 drm_i915_private_t *dev_priv = dev->dev_private;
199 struct pci_dev *bridge_dev;
200 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; 181 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
201 u32 temp; 182 u32 temp;
202 183
203 bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
204 if (!bridge_dev) {
205 DRM_DEBUG("no bridge dev?!\n");
206 return;
207 }
208
209 if (disable) { 184 if (disable) {
210 if (IS_I915G(dev) || IS_I915GM(dev)) { 185 if (IS_I915G(dev) || IS_I915GM(dev)) {
211 pci_read_config_dword(bridge_dev, DEVEN_REG, &temp); 186 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
212 temp &= ~DEVEN_MCHBAR_EN; 187 temp &= ~DEVEN_MCHBAR_EN;
213 pci_write_config_dword(bridge_dev, DEVEN_REG, temp); 188 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
214 } else { 189 } else {
215 pci_read_config_dword(bridge_dev, mchbar_reg, &temp); 190 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
216 temp &= ~1; 191 temp &= ~1;
217 pci_write_config_dword(bridge_dev, mchbar_reg, temp); 192 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
218 } 193 }
219 } 194 }
220 195
@@ -234,7 +209,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
234 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; 209 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
235 bool need_disable; 210 bool need_disable;
236 211
237 if (!IS_I9XX(dev)) { 212 if (IS_IGDNG(dev)) {
213 /* On IGDNG whatever DRAM config, GPU always do
214 * same swizzling setup.
215 */
216 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
217 swizzle_y = I915_BIT_6_SWIZZLE_9;
218 } else if (!IS_I9XX(dev)) {
238 /* As far as we know, the 865 doesn't have these bit 6 219 /* As far as we know, the 865 doesn't have these bit 6
239 * swizzling issues. 220 * swizzling issues.
240 */ 221 */
@@ -317,13 +298,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
317 } 298 }
318 } 299 }
319 300
320 /* FIXME: check with memory config on IGDNG */
321 if (IS_IGDNG(dev)) {
322 DRM_ERROR("disable tiling on IGDNG...\n");
323 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
324 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
325 }
326
327 dev_priv->mm.bit_6_swizzle_x = swizzle_x; 301 dev_priv->mm.bit_6_swizzle_x = swizzle_x;
328 dev_priv->mm.bit_6_swizzle_y = swizzle_y; 302 dev_priv->mm.bit_6_swizzle_y = swizzle_y;
329} 303}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7ebc84c2881e..6c89f2ff2495 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -565,6 +565,27 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
565 565
566 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 566 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
567 I915_READ(PORT_HOTPLUG_STAT); 567 I915_READ(PORT_HOTPLUG_STAT);
568
569 /* EOS interrupts occurs */
570 if (IS_IGD(dev) &&
571 (hotplug_status & CRT_EOS_INT_STATUS)) {
572 u32 temp;
573
574 DRM_DEBUG("EOS interrupt occurs\n");
575 /* status is already cleared */
576 temp = I915_READ(ADPA);
577 temp &= ~ADPA_DAC_ENABLE;
578 I915_WRITE(ADPA, temp);
579
580 temp = I915_READ(PORT_HOTPLUG_EN);
581 temp &= ~CRT_EOS_INT_EN;
582 I915_WRITE(PORT_HOTPLUG_EN, temp);
583
584 temp = I915_READ(PORT_HOTPLUG_STAT);
585 if (temp & CRT_EOS_INT_STATUS)
586 I915_WRITE(PORT_HOTPLUG_STAT,
587 CRT_EOS_INT_STATUS);
588 }
568 } 589 }
569 590
570 I915_WRITE(IIR, iir); 591 I915_WRITE(IIR, iir);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2955083aa471..3f7963553464 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -30,6 +30,7 @@
30 * fb aperture size and the amount of pre-reserved memory. 30 * fb aperture size and the amount of pre-reserved memory.
31 */ 31 */
32#define INTEL_GMCH_CTRL 0x52 32#define INTEL_GMCH_CTRL 0x52
33#define INTEL_GMCH_VGA_DISABLE (1 << 1)
33#define INTEL_GMCH_ENABLED 0x4 34#define INTEL_GMCH_ENABLED 0x4
34#define INTEL_GMCH_MEM_MASK 0x1 35#define INTEL_GMCH_MEM_MASK 0x1
35#define INTEL_GMCH_MEM_64M 0x1 36#define INTEL_GMCH_MEM_64M 0x1
@@ -55,7 +56,7 @@
55/* PCI config space */ 56/* PCI config space */
56 57
57#define HPLLCC 0xc0 /* 855 only */ 58#define HPLLCC 0xc0 /* 855 only */
58#define GC_CLOCK_CONTROL_MASK (3 << 0) 59#define GC_CLOCK_CONTROL_MASK (0xf << 0)
59#define GC_CLOCK_133_200 (0 << 0) 60#define GC_CLOCK_133_200 (0 << 0)
60#define GC_CLOCK_100_200 (1 << 0) 61#define GC_CLOCK_100_200 (1 << 0)
61#define GC_CLOCK_100_133 (2 << 0) 62#define GC_CLOCK_100_133 (2 << 0)
@@ -65,6 +66,25 @@
65#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 66#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
66#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 67#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
67#define GC_DISPLAY_CLOCK_MASK (7 << 4) 68#define GC_DISPLAY_CLOCK_MASK (7 << 4)
69#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
70#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
71#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
72#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
73#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
74#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
75#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
76#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
77#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
78#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
79#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
80#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
81#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
82#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
83#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
84#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
85#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
86#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
87#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
68#define LBB 0xf4 88#define LBB 0xf4
69 89
70/* VGA stuff */ 90/* VGA stuff */
@@ -553,9 +573,118 @@
553#define DPLLA_TEST_M_BYPASS (1 << 2) 573#define DPLLA_TEST_M_BYPASS (1 << 2)
554#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 574#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
555#define D_STATE 0x6104 575#define D_STATE 0x6104
556#define CG_2D_DIS 0x6200 576#define DSTATE_PLL_D3_OFF (1<<3)
557#define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) 577#define DSTATE_GFX_CLOCK_GATING (1<<1)
558#define CG_3D_DIS 0x6204 578#define DSTATE_DOT_CLOCK_GATING (1<<0)
579#define DSPCLK_GATE_D 0x6200
580# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
581# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
582# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
583# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
584# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
585# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
586# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
587# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
588# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
589# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
590# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
591# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
592# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
593# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
594# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
595# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
596# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
597# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
598# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
599# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
600# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
601# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
602# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
603# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
604# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
605# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
606# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
607# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
608/**
609 * This bit must be set on the 830 to prevent hangs when turning off the
610 * overlay scaler.
611 */
612# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
613# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
614# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
615# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
616# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
617
618#define RENCLK_GATE_D1 0x6204
619# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
620# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
621# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
622# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
623# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
624# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
625# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
626# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
627# define MAG_CLOCK_GATE_DISABLE (1 << 5)
628/** This bit must be unset on 855,865 */
629# define MECI_CLOCK_GATE_DISABLE (1 << 4)
630# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
631# define MEC_CLOCK_GATE_DISABLE (1 << 2)
632# define MECO_CLOCK_GATE_DISABLE (1 << 1)
633/** This bit must be set on 855,865. */
634# define SV_CLOCK_GATE_DISABLE (1 << 0)
635# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
636# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
637# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
638# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
639# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
640# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
641# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
642# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
643# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
644# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
645# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
646# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
647# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
648# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
649# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
650# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
651# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
652
653# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
654/** This bit must always be set on 965G/965GM */
655# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
656# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
657# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
658# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
659# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
660# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
661/** This bit must always be set on 965G */
662# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
663# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
664# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
665# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
666# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
667# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
668# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
669# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
670# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
671# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
672# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
673# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
674# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
675# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
676# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
677# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
678# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
679# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
680# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
681
682#define RENCLK_GATE_D2 0x6208
683#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
684#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
685#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
686#define RAMCLK_GATE_D 0x6210 /* CRL only */
687#define DEUC 0x6214 /* CRL only */
559 688
560/* 689/*
561 * Palette regs 690 * Palette regs
@@ -683,6 +812,7 @@
683#define SDVOB_HOTPLUG_INT_EN (1 << 26) 812#define SDVOB_HOTPLUG_INT_EN (1 << 26)
684#define SDVOC_HOTPLUG_INT_EN (1 << 25) 813#define SDVOC_HOTPLUG_INT_EN (1 << 25)
685#define TV_HOTPLUG_INT_EN (1 << 18) 814#define TV_HOTPLUG_INT_EN (1 << 18)
815#define CRT_EOS_INT_EN (1 << 10)
686#define CRT_HOTPLUG_INT_EN (1 << 9) 816#define CRT_HOTPLUG_INT_EN (1 << 9)
687#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 817#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
688#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 818#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
@@ -717,6 +847,7 @@
717#define DPC_HOTPLUG_INT_STATUS (1 << 28) 847#define DPC_HOTPLUG_INT_STATUS (1 << 28)
718#define HDMID_HOTPLUG_INT_STATUS (1 << 27) 848#define HDMID_HOTPLUG_INT_STATUS (1 << 27)
719#define DPD_HOTPLUG_INT_STATUS (1 << 27) 849#define DPD_HOTPLUG_INT_STATUS (1 << 27)
850#define CRT_EOS_INT_STATUS (1 << 12)
720#define CRT_HOTPLUG_INT_STATUS (1 << 11) 851#define CRT_HOTPLUG_INT_STATUS (1 << 11)
721#define TV_HOTPLUG_INT_STATUS (1 << 10) 852#define TV_HOTPLUG_INT_STATUS (1 << 10)
722#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 853#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
@@ -1586,6 +1717,7 @@
1586#define PIPECONF_PROGRESSIVE (0 << 21) 1717#define PIPECONF_PROGRESSIVE (0 << 21)
1587#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 1718#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1588#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 1719#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1720#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
1589#define PIPEASTAT 0x70024 1721#define PIPEASTAT 0x70024
1590#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 1722#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
1591#define PIPE_CRC_ERROR_ENABLE (1UL<<29) 1723#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
@@ -1733,6 +1865,7 @@
1733#define DISPPLANE_NO_LINE_DOUBLE 0 1865#define DISPPLANE_NO_LINE_DOUBLE 0
1734#define DISPPLANE_STEREO_POLARITY_FIRST 0 1866#define DISPPLANE_STEREO_POLARITY_FIRST 0
1735#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 1867#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1868#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* IGDNG */
1736#define DISPPLANE_TILED (1<<10) 1869#define DISPPLANE_TILED (1<<10)
1737#define DSPAADDR 0x70184 1870#define DSPAADDR 0x70184
1738#define DSPASTRIDE 0x70188 1871#define DSPASTRIDE 0x70188
@@ -1913,6 +2046,9 @@
1913#define GTIIR 0x44018 2046#define GTIIR 0x44018
1914#define GTIER 0x4401c 2047#define GTIER 0x4401c
1915 2048
2049#define DISP_ARB_CTL 0x45000
2050#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
2051
1916/* PCH */ 2052/* PCH */
1917 2053
1918/* south display engine interrupt */ 2054/* south display engine interrupt */
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 1d04e1904ac6..20d4d19f5568 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -461,7 +461,7 @@ int i915_save_state(struct drm_device *dev)
461 461
462 /* Clock gating state */ 462 /* Clock gating state */
463 dev_priv->saveD_STATE = I915_READ(D_STATE); 463 dev_priv->saveD_STATE = I915_READ(D_STATE);
464 dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS); 464 dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
465 465
466 /* Cache mode state */ 466 /* Cache mode state */
467 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); 467 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
@@ -588,7 +588,7 @@ int i915_restore_state(struct drm_device *dev)
588 588
589 /* Clock gating state */ 589 /* Clock gating state */
590 I915_WRITE (D_STATE, dev_priv->saveD_STATE); 590 I915_WRITE (D_STATE, dev_priv->saveD_STATE);
591 I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS); 591 I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
592 592
593 /* Cache mode state */ 593 /* Cache mode state */
594 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); 594 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index f806fcc54e09..1e28c1652fd0 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -355,8 +355,14 @@ parse_driver_features(struct drm_i915_private *dev_priv,
355 } 355 }
356 356
357 driver = find_section(bdb, BDB_DRIVER_FEATURES); 357 driver = find_section(bdb, BDB_DRIVER_FEATURES);
358 if (driver && driver->lvds_config == BDB_DRIVER_FEATURE_EDP) 358 if (!driver)
359 return;
360
361 if (driver->lvds_config == BDB_DRIVER_FEATURE_EDP)
359 dev_priv->edp_support = 1; 362 dev_priv->edp_support = 1;
363
364 if (driver->dual_frequency)
365 dev_priv->render_reclock_avail = true;
360} 366}
361 367
362/** 368/**
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 590f81c8f594..88814fa2dfd2 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -64,6 +64,34 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
64 } 64 }
65 65
66 I915_WRITE(reg, temp); 66 I915_WRITE(reg, temp);
67
68 if (IS_IGD(dev)) {
69 if (mode == DRM_MODE_DPMS_OFF) {
70 /* turn off DAC */
71 temp = I915_READ(PORT_HOTPLUG_EN);
72 temp &= ~CRT_EOS_INT_EN;
73 I915_WRITE(PORT_HOTPLUG_EN, temp);
74
75 temp = I915_READ(PORT_HOTPLUG_STAT);
76 if (temp & CRT_EOS_INT_STATUS)
77 I915_WRITE(PORT_HOTPLUG_STAT,
78 CRT_EOS_INT_STATUS);
79 } else {
80 /* turn on DAC. EOS interrupt must be enabled after DAC
81 * is enabled, so it sounds not good to enable it in
82 * i915_driver_irq_postinstall()
83 * wait 12.5ms after DAC is enabled
84 */
85 msleep(13);
86 temp = I915_READ(PORT_HOTPLUG_STAT);
87 if (temp & CRT_EOS_INT_STATUS)
88 I915_WRITE(PORT_HOTPLUG_STAT,
89 CRT_EOS_INT_STATUS);
90 temp = I915_READ(PORT_HOTPLUG_EN);
91 temp |= CRT_EOS_INT_EN;
92 I915_WRITE(PORT_HOTPLUG_EN, temp);
93 }
94 }
67} 95}
68 96
69static int intel_crt_mode_valid(struct drm_connector *connector, 97static int intel_crt_mode_valid(struct drm_connector *connector,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 748ed50c55ca..0227b1652906 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -38,6 +38,7 @@
38 38
39bool intel_pipe_has_type (struct drm_crtc *crtc, int type); 39bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
40static void intel_update_watermarks(struct drm_device *dev); 40static void intel_update_watermarks(struct drm_device *dev);
41static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
41 42
42typedef struct { 43typedef struct {
43 /* given values */ 44 /* given values */
@@ -67,6 +68,8 @@ struct intel_limit {
67 intel_p2_t p2; 68 intel_p2_t p2;
68 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, 69 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
69 int, int, intel_clock_t *); 70 int, int, intel_clock_t *);
71 bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
72 int, int, intel_clock_t *);
70}; 73};
71 74
72#define I8XX_DOT_MIN 25000 75#define I8XX_DOT_MIN 25000
@@ -261,6 +264,9 @@ static bool
261intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 264intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
262 int target, int refclk, intel_clock_t *best_clock); 265 int target, int refclk, intel_clock_t *best_clock);
263static bool 266static bool
267intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
268 int target, int refclk, intel_clock_t *best_clock);
269static bool
264intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 270intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
265 int target, int refclk, intel_clock_t *best_clock); 271 int target, int refclk, intel_clock_t *best_clock);
266static bool 272static bool
@@ -286,6 +292,7 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
286 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, 292 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
287 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, 293 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
288 .find_pll = intel_find_best_PLL, 294 .find_pll = intel_find_best_PLL,
295 .find_reduced_pll = intel_find_best_reduced_PLL,
289}; 296};
290 297
291static const intel_limit_t intel_limits_i8xx_lvds = { 298static const intel_limit_t intel_limits_i8xx_lvds = {
@@ -300,6 +307,7 @@ static const intel_limit_t intel_limits_i8xx_lvds = {
300 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, 307 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
301 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, 308 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
302 .find_pll = intel_find_best_PLL, 309 .find_pll = intel_find_best_PLL,
310 .find_reduced_pll = intel_find_best_reduced_PLL,
303}; 311};
304 312
305static const intel_limit_t intel_limits_i9xx_sdvo = { 313static const intel_limit_t intel_limits_i9xx_sdvo = {
@@ -314,6 +322,7 @@ static const intel_limit_t intel_limits_i9xx_sdvo = {
314 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, 322 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
315 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, 323 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
316 .find_pll = intel_find_best_PLL, 324 .find_pll = intel_find_best_PLL,
325 .find_reduced_pll = intel_find_best_reduced_PLL,
317}; 326};
318 327
319static const intel_limit_t intel_limits_i9xx_lvds = { 328static const intel_limit_t intel_limits_i9xx_lvds = {
@@ -331,6 +340,7 @@ static const intel_limit_t intel_limits_i9xx_lvds = {
331 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, 340 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
332 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, 341 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
333 .find_pll = intel_find_best_PLL, 342 .find_pll = intel_find_best_PLL,
343 .find_reduced_pll = intel_find_best_reduced_PLL,
334}; 344};
335 345
336 /* below parameter and function is for G4X Chipset Family*/ 346 /* below parameter and function is for G4X Chipset Family*/
@@ -348,6 +358,7 @@ static const intel_limit_t intel_limits_g4x_sdvo = {
348 .p2_fast = G4X_P2_SDVO_FAST 358 .p2_fast = G4X_P2_SDVO_FAST
349 }, 359 },
350 .find_pll = intel_g4x_find_best_PLL, 360 .find_pll = intel_g4x_find_best_PLL,
361 .find_reduced_pll = intel_g4x_find_best_PLL,
351}; 362};
352 363
353static const intel_limit_t intel_limits_g4x_hdmi = { 364static const intel_limit_t intel_limits_g4x_hdmi = {
@@ -364,6 +375,7 @@ static const intel_limit_t intel_limits_g4x_hdmi = {
364 .p2_fast = G4X_P2_HDMI_DAC_FAST 375 .p2_fast = G4X_P2_HDMI_DAC_FAST
365 }, 376 },
366 .find_pll = intel_g4x_find_best_PLL, 377 .find_pll = intel_g4x_find_best_PLL,
378 .find_reduced_pll = intel_g4x_find_best_PLL,
367}; 379};
368 380
369static const intel_limit_t intel_limits_g4x_single_channel_lvds = { 381static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
@@ -388,6 +400,7 @@ static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
388 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST 400 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
389 }, 401 },
390 .find_pll = intel_g4x_find_best_PLL, 402 .find_pll = intel_g4x_find_best_PLL,
403 .find_reduced_pll = intel_g4x_find_best_PLL,
391}; 404};
392 405
393static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { 406static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
@@ -412,6 +425,7 @@ static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
412 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST 425 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
413 }, 426 },
414 .find_pll = intel_g4x_find_best_PLL, 427 .find_pll = intel_g4x_find_best_PLL,
428 .find_reduced_pll = intel_g4x_find_best_PLL,
415}; 429};
416 430
417static const intel_limit_t intel_limits_g4x_display_port = { 431static const intel_limit_t intel_limits_g4x_display_port = {
@@ -449,6 +463,7 @@ static const intel_limit_t intel_limits_igd_sdvo = {
449 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, 463 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
450 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, 464 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
451 .find_pll = intel_find_best_PLL, 465 .find_pll = intel_find_best_PLL,
466 .find_reduced_pll = intel_find_best_reduced_PLL,
452}; 467};
453 468
454static const intel_limit_t intel_limits_igd_lvds = { 469static const intel_limit_t intel_limits_igd_lvds = {
@@ -464,6 +479,7 @@ static const intel_limit_t intel_limits_igd_lvds = {
464 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, 479 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
465 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, 480 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
466 .find_pll = intel_find_best_PLL, 481 .find_pll = intel_find_best_PLL,
482 .find_reduced_pll = intel_find_best_reduced_PLL,
467}; 483};
468 484
469static const intel_limit_t intel_limits_igdng_sdvo = { 485static const intel_limit_t intel_limits_igdng_sdvo = {
@@ -688,15 +704,16 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
688 704
689 memset (best_clock, 0, sizeof (*best_clock)); 705 memset (best_clock, 0, sizeof (*best_clock));
690 706
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 707 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
692 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) { 708 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
693 /* m1 is always 0 in IGD */ 709 clock.m1++) {
694 if (clock.m2 >= clock.m1 && !IS_IGD(dev)) 710 for (clock.m2 = limit->m2.min;
695 break; 711 clock.m2 <= limit->m2.max; clock.m2++) {
696 for (clock.n = limit->n.min; clock.n <= limit->n.max; 712 /* m1 is always 0 in IGD */
697 clock.n++) { 713 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
698 for (clock.p1 = limit->p1.min; 714 break;
699 clock.p1 <= limit->p1.max; clock.p1++) { 715 for (clock.n = limit->n.min;
716 clock.n <= limit->n.max; clock.n++) {
700 int this_err; 717 int this_err;
701 718
702 intel_clock(dev, refclk, &clock); 719 intel_clock(dev, refclk, &clock);
@@ -717,6 +734,46 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
717 return (err != target); 734 return (err != target);
718} 735}
719 736
737
738static bool
739intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
740 int target, int refclk, intel_clock_t *best_clock)
741
742{
743 struct drm_device *dev = crtc->dev;
744 intel_clock_t clock;
745 int err = target;
746 bool found = false;
747
748 memcpy(&clock, best_clock, sizeof(intel_clock_t));
749
750 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
751 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
752 /* m1 is always 0 in IGD */
753 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
754 break;
755 for (clock.n = limit->n.min; clock.n <= limit->n.max;
756 clock.n++) {
757 int this_err;
758
759 intel_clock(dev, refclk, &clock);
760
761 if (!intel_PLL_is_valid(crtc, &clock))
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err) {
766 *best_clock = clock;
767 err = this_err;
768 found = true;
769 }
770 }
771 }
772 }
773
774 return found;
775}
776
720static bool 777static bool
721intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 778intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
722 int target, int refclk, intel_clock_t *best_clock) 779 int target, int refclk, intel_clock_t *best_clock)
@@ -747,7 +804,7 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
747 max_n = limit->n.max; 804 max_n = limit->n.max;
748 /* based on hardware requriment prefer smaller n to precision */ 805 /* based on hardware requriment prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 806 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirment prefere larger m1,m2, p1 */ 807 /* based on hardware requirment prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max; 808 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) { 809 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max; 810 for (clock.m2 = limit->m2.max;
@@ -832,15 +889,14 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
832 889
833 memset(best_clock, 0, sizeof(*best_clock)); 890 memset(best_clock, 0, sizeof(*best_clock));
834 max_n = limit->n.max; 891 max_n = limit->n.max;
835 /* based on hardware requriment prefer smaller n to precision */ 892 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
836 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 893 /* based on hardware requriment prefer smaller n to precision */
837 /* based on hardware requirment prefere larger m1,m2, p1 */ 894 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
838 for (clock.m1 = limit->m1.max; 895 /* based on hardware requirment prefere larger m1,m2 */
839 clock.m1 >= limit->m1.min; clock.m1--) { 896 for (clock.m1 = limit->m1.max;
840 for (clock.m2 = limit->m2.max; 897 clock.m1 >= limit->m1.min; clock.m1--) {
841 clock.m2 >= limit->m2.min; clock.m2--) { 898 for (clock.m2 = limit->m2.max;
842 for (clock.p1 = limit->p1.max; 899 clock.m2 >= limit->m2.min; clock.m2--) {
843 clock.p1 >= limit->p1.min; clock.p1--) {
844 int this_err; 900 int this_err;
845 901
846 intel_clock(dev, refclk, &clock); 902 intel_clock(dev, refclk, &clock);
@@ -1008,6 +1064,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1008 dspcntr &= ~DISPPLANE_TILED; 1064 dspcntr &= ~DISPPLANE_TILED;
1009 } 1065 }
1010 1066
1067 if (IS_IGDNG(dev))
1068 /* must disable */
1069 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1070
1011 I915_WRITE(dspcntr_reg, dspcntr); 1071 I915_WRITE(dspcntr_reg, dspcntr);
1012 1072
1013 Start = obj_priv->gtt_offset; 1073 Start = obj_priv->gtt_offset;
@@ -1030,8 +1090,11 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1030 1090
1031 if (old_fb) { 1091 if (old_fb) {
1032 intel_fb = to_intel_framebuffer(old_fb); 1092 intel_fb = to_intel_framebuffer(old_fb);
1093 obj_priv = intel_fb->obj->driver_private;
1033 i915_gem_object_unpin(intel_fb->obj); 1094 i915_gem_object_unpin(intel_fb->obj);
1034 } 1095 }
1096 intel_increase_pllclock(crtc, true);
1097
1035 mutex_unlock(&dev->struct_mutex); 1098 mutex_unlock(&dev->struct_mutex);
1036 1099
1037 if (!dev->primary->master) 1100 if (!dev->primary->master)
@@ -1581,6 +1644,8 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1581 else 1644 else
1582 i9xx_crtc_dpms(crtc, mode); 1645 i9xx_crtc_dpms(crtc, mode);
1583 1646
1647 intel_crtc->dpms_mode = mode;
1648
1584 if (!dev->primary->master) 1649 if (!dev->primary->master)
1585 return; 1650 return;
1586 1651
@@ -1603,8 +1668,6 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1603 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); 1668 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1604 break; 1669 break;
1605 } 1670 }
1606
1607 intel_crtc->dpms_mode = mode;
1608} 1671}
1609 1672
1610static void intel_crtc_prepare (struct drm_crtc *crtc) 1673static void intel_crtc_prepare (struct drm_crtc *crtc)
@@ -2054,6 +2117,18 @@ static int intel_get_fifo_size(struct drm_device *dev, int plane)
2054 return size; 2117 return size;
2055} 2118}
2056 2119
2120static void g4x_update_wm(struct drm_device *dev)
2121{
2122 struct drm_i915_private *dev_priv = dev->dev_private;
2123 u32 fw_blc_self = I915_READ(FW_BLC_SELF);
2124
2125 if (i915_powersave)
2126 fw_blc_self |= FW_BLC_SELF_EN;
2127 else
2128 fw_blc_self &= ~FW_BLC_SELF_EN;
2129 I915_WRITE(FW_BLC_SELF, fw_blc_self);
2130}
2131
2057static void i965_update_wm(struct drm_device *dev) 2132static void i965_update_wm(struct drm_device *dev)
2058{ 2133{
2059 struct drm_i915_private *dev_priv = dev->dev_private; 2134 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2105,7 +2180,8 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2105 cwm = 2; 2180 cwm = 2;
2106 2181
2107 /* Calc sr entries for one plane configs */ 2182 /* Calc sr entries for one plane configs */
2108 if (sr_hdisplay && (!planea_clock || !planeb_clock)) { 2183 if (HAS_FW_BLC(dev) && sr_hdisplay &&
2184 (!planea_clock || !planeb_clock)) {
2109 /* self-refresh has much higher latency */ 2185 /* self-refresh has much higher latency */
2110 const static int sr_latency_ns = 6000; 2186 const static int sr_latency_ns = 6000;
2111 2187
@@ -2120,8 +2196,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2120 srwm = total_size - sr_entries; 2196 srwm = total_size - sr_entries;
2121 if (srwm < 0) 2197 if (srwm < 0)
2122 srwm = 1; 2198 srwm = 1;
2123 if (IS_I9XX(dev)) 2199 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2124 I915_WRITE(FW_BLC_SELF, (srwm & 0x3f));
2125 } 2200 }
2126 2201
2127 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 2202 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
@@ -2195,9 +2270,6 @@ static void intel_update_watermarks(struct drm_device *dev)
2195 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; 2270 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2196 int enabled = 0, pixel_size = 0; 2271 int enabled = 0, pixel_size = 0;
2197 2272
2198 if (DSPARB_HWCONTROL(dev))
2199 return;
2200
2201 /* Get the clock config from both planes */ 2273 /* Get the clock config from both planes */
2202 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 2274 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2203 intel_crtc = to_intel_crtc(crtc); 2275 intel_crtc = to_intel_crtc(crtc);
@@ -2230,7 +2302,9 @@ static void intel_update_watermarks(struct drm_device *dev)
2230 else if (IS_IGD(dev)) 2302 else if (IS_IGD(dev))
2231 igd_disable_cxsr(dev); 2303 igd_disable_cxsr(dev);
2232 2304
2233 if (IS_I965G(dev)) 2305 if (IS_G4X(dev))
2306 g4x_update_wm(dev);
2307 else if (IS_I965G(dev))
2234 i965_update_wm(dev); 2308 i965_update_wm(dev);
2235 else if (IS_I9XX(dev) || IS_MOBILE(dev)) 2309 else if (IS_I9XX(dev) || IS_MOBILE(dev))
2236 i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay, 2310 i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay,
@@ -2264,9 +2338,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2264 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; 2338 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
2265 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; 2339 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2266 int refclk, num_outputs = 0; 2340 int refclk, num_outputs = 0;
2267 intel_clock_t clock; 2341 intel_clock_t clock, reduced_clock;
2268 u32 dpll = 0, fp = 0, dspcntr, pipeconf; 2342 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2269 bool ok, is_sdvo = false, is_dvo = false; 2343 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2270 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 2344 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2271 bool is_edp = false; 2345 bool is_edp = false;
2272 struct drm_mode_config *mode_config = &dev->mode_config; 2346 struct drm_mode_config *mode_config = &dev->mode_config;
@@ -2349,6 +2423,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2349 return -EINVAL; 2423 return -EINVAL;
2350 } 2424 }
2351 2425
2426 if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
2427 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2428 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2429 (adjusted_mode->clock*3/4),
2430 refclk,
2431 &reduced_clock);
2432 }
2433
2352 /* SDVO TV has fixed PLL values depend on its clock range, 2434 /* SDVO TV has fixed PLL values depend on its clock range,
2353 this mirrors vbios setting. */ 2435 this mirrors vbios setting. */
2354 if (is_sdvo && is_tv) { 2436 if (is_sdvo && is_tv) {
@@ -2394,10 +2476,17 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2394 link_bw, &m_n); 2476 link_bw, &m_n);
2395 } 2477 }
2396 2478
2397 if (IS_IGD(dev)) 2479 if (IS_IGD(dev)) {
2398 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; 2480 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2399 else 2481 if (has_reduced_clock)
2482 fp2 = (1 << reduced_clock.n) << 16 |
2483 reduced_clock.m1 << 8 | reduced_clock.m2;
2484 } else {
2400 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 2485 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2486 if (has_reduced_clock)
2487 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
2488 reduced_clock.m2;
2489 }
2401 2490
2402 if (!IS_IGDNG(dev)) 2491 if (!IS_IGDNG(dev))
2403 dpll = DPLL_VGA_MODE_DIS; 2492 dpll = DPLL_VGA_MODE_DIS;
@@ -2426,6 +2515,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2426 /* also FPA1 */ 2515 /* also FPA1 */
2427 if (IS_IGDNG(dev)) 2516 if (IS_IGDNG(dev))
2428 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 2517 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2518 if (IS_G4X(dev) && has_reduced_clock)
2519 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2429 } 2520 }
2430 switch (clock.p2) { 2521 switch (clock.p2) {
2431 case 5: 2522 case 5:
@@ -2573,6 +2664,22 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2573 udelay(150); 2664 udelay(150);
2574 } 2665 }
2575 2666
2667 if (is_lvds && has_reduced_clock && i915_powersave) {
2668 I915_WRITE(fp_reg + 4, fp2);
2669 intel_crtc->lowfreq_avail = true;
2670 if (HAS_PIPE_CXSR(dev)) {
2671 DRM_DEBUG("enabling CxSR downclocking\n");
2672 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
2673 }
2674 } else {
2675 I915_WRITE(fp_reg + 4, fp);
2676 intel_crtc->lowfreq_avail = false;
2677 if (HAS_PIPE_CXSR(dev)) {
2678 DRM_DEBUG("disabling CxSR downclocking\n");
2679 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
2680 }
2681 }
2682
2576 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | 2683 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
2577 ((adjusted_mode->crtc_htotal - 1) << 16)); 2684 ((adjusted_mode->crtc_htotal - 1) << 16));
2578 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | 2685 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
@@ -2616,6 +2723,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2616 2723
2617 intel_wait_for_vblank(dev); 2724 intel_wait_for_vblank(dev);
2618 2725
2726 if (IS_IGDNG(dev)) {
2727 /* enable address swizzle for tiling buffer */
2728 temp = I915_READ(DISP_ARB_CTL);
2729 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
2730 }
2731
2619 I915_WRITE(dspcntr_reg, dspcntr); 2732 I915_WRITE(dspcntr_reg, dspcntr);
2620 2733
2621 /* Flush the plane changes */ 2734 /* Flush the plane changes */
@@ -2769,10 +2882,16 @@ static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
2769 struct drm_device *dev = crtc->dev; 2882 struct drm_device *dev = crtc->dev;
2770 struct drm_i915_private *dev_priv = dev->dev_private; 2883 struct drm_i915_private *dev_priv = dev->dev_private;
2771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2885 struct intel_framebuffer *intel_fb;
2772 int pipe = intel_crtc->pipe; 2886 int pipe = intel_crtc->pipe;
2773 uint32_t temp = 0; 2887 uint32_t temp = 0;
2774 uint32_t adder; 2888 uint32_t adder;
2775 2889
2890 if (crtc->fb) {
2891 intel_fb = to_intel_framebuffer(crtc->fb);
2892 intel_mark_busy(dev, intel_fb->obj);
2893 }
2894
2776 if (x < 0) { 2895 if (x < 0) {
2777 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; 2896 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
2778 x = -x; 2897 x = -x;
@@ -3070,12 +3189,319 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3070 return mode; 3189 return mode;
3071} 3190}
3072 3191
3192#define GPU_IDLE_TIMEOUT 500 /* ms */
3193
3194/* When this timer fires, we've been idle for awhile */
3195static void intel_gpu_idle_timer(unsigned long arg)
3196{
3197 struct drm_device *dev = (struct drm_device *)arg;
3198 drm_i915_private_t *dev_priv = dev->dev_private;
3199
3200 DRM_DEBUG("idle timer fired, downclocking\n");
3201
3202 dev_priv->busy = false;
3203
3204 queue_work(dev_priv->wq, &dev_priv->idle_work);
3205}
3206
3207void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3208{
3209 drm_i915_private_t *dev_priv = dev->dev_private;
3210
3211 if (IS_IGDNG(dev))
3212 return;
3213
3214 if (!dev_priv->render_reclock_avail) {
3215 DRM_DEBUG("not reclocking render clock\n");
3216 return;
3217 }
3218
3219 /* Restore render clock frequency to original value */
3220 if (IS_G4X(dev) || IS_I9XX(dev))
3221 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3222 else if (IS_I85X(dev))
3223 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3224 DRM_DEBUG("increasing render clock frequency\n");
3225
3226 /* Schedule downclock */
3227 if (schedule)
3228 mod_timer(&dev_priv->idle_timer, jiffies +
3229 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3230}
3231
3232void intel_decrease_renderclock(struct drm_device *dev)
3233{
3234 drm_i915_private_t *dev_priv = dev->dev_private;
3235
3236 if (IS_IGDNG(dev))
3237 return;
3238
3239 if (!dev_priv->render_reclock_avail) {
3240 DRM_DEBUG("not reclocking render clock\n");
3241 return;
3242 }
3243
3244 if (IS_G4X(dev)) {
3245 u16 gcfgc;
3246
3247 /* Adjust render clock... */
3248 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3249
3250 /* Down to minimum... */
3251 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3252 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3253
3254 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3255 } else if (IS_I965G(dev)) {
3256 u16 gcfgc;
3257
3258 /* Adjust render clock... */
3259 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3260
3261 /* Down to minimum... */
3262 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3263 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3264
3265 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3266 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3267 u16 gcfgc;
3268
3269 /* Adjust render clock... */
3270 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3271
3272 /* Down to minimum... */
3273 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3274 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3275
3276 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3277 } else if (IS_I915G(dev)) {
3278 u16 gcfgc;
3279
3280 /* Adjust render clock... */
3281 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3282
3283 /* Down to minimum... */
3284 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3285 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3286
3287 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3288 } else if (IS_I85X(dev)) {
3289 u16 hpllcc;
3290
3291 /* Adjust render clock... */
3292 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3293
3294 /* Up to maximum... */
3295 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3296 hpllcc |= GC_CLOCK_133_200;
3297
3298 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3299 }
3300 DRM_DEBUG("decreasing render clock frequency\n");
3301}
3302
3303/* Note that no increase function is needed for this - increase_renderclock()
3304 * will also rewrite these bits
3305 */
3306void intel_decrease_displayclock(struct drm_device *dev)
3307{
3308 if (IS_IGDNG(dev))
3309 return;
3310
3311 if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3312 IS_I915GM(dev)) {
3313 u16 gcfgc;
3314
3315 /* Adjust render clock... */
3316 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3317
3318 /* Down to minimum... */
3319 gcfgc &= ~0xf0;
3320 gcfgc |= 0x80;
3321
3322 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3323 }
3324}
3325
3326#define CRTC_IDLE_TIMEOUT 1000 /* ms */
3327
3328static void intel_crtc_idle_timer(unsigned long arg)
3329{
3330 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3331 struct drm_crtc *crtc = &intel_crtc->base;
3332 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3333
3334 DRM_DEBUG("idle timer fired, downclocking\n");
3335
3336 intel_crtc->busy = false;
3337
3338 queue_work(dev_priv->wq, &dev_priv->idle_work);
3339}
3340
3341static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3342{
3343 struct drm_device *dev = crtc->dev;
3344 drm_i915_private_t *dev_priv = dev->dev_private;
3345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3346 int pipe = intel_crtc->pipe;
3347 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3348 int dpll = I915_READ(dpll_reg);
3349
3350 if (IS_IGDNG(dev))
3351 return;
3352
3353 if (!dev_priv->lvds_downclock_avail)
3354 return;
3355
3356 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3357 DRM_DEBUG("upclocking LVDS\n");
3358
3359 /* Unlock panel regs */
3360 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3361
3362 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3363 I915_WRITE(dpll_reg, dpll);
3364 dpll = I915_READ(dpll_reg);
3365 intel_wait_for_vblank(dev);
3366 dpll = I915_READ(dpll_reg);
3367 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3368 DRM_DEBUG("failed to upclock LVDS!\n");
3369
3370 /* ...and lock them again */
3371 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3372 }
3373
3374 /* Schedule downclock */
3375 if (schedule)
3376 mod_timer(&intel_crtc->idle_timer, jiffies +
3377 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3378}
3379
3380static void intel_decrease_pllclock(struct drm_crtc *crtc)
3381{
3382 struct drm_device *dev = crtc->dev;
3383 drm_i915_private_t *dev_priv = dev->dev_private;
3384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3385 int pipe = intel_crtc->pipe;
3386 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3387 int dpll = I915_READ(dpll_reg);
3388
3389 if (IS_IGDNG(dev))
3390 return;
3391
3392 if (!dev_priv->lvds_downclock_avail)
3393 return;
3394
3395 /*
3396 * Since this is called by a timer, we should never get here in
3397 * the manual case.
3398 */
3399 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3400 DRM_DEBUG("downclocking LVDS\n");
3401
3402 /* Unlock panel regs */
3403 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3404
3405 dpll |= DISPLAY_RATE_SELECT_FPA1;
3406 I915_WRITE(dpll_reg, dpll);
3407 dpll = I915_READ(dpll_reg);
3408 intel_wait_for_vblank(dev);
3409 dpll = I915_READ(dpll_reg);
3410 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3411 DRM_DEBUG("failed to downclock LVDS!\n");
3412
3413 /* ...and lock them again */
3414 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3415 }
3416
3417}
3418
3419/**
3420 * intel_idle_update - adjust clocks for idleness
3421 * @work: work struct
3422 *
3423 * Either the GPU or display (or both) went idle. Check the busy status
3424 * here and adjust the CRTC and GPU clocks as necessary.
3425 */
3426static void intel_idle_update(struct work_struct *work)
3427{
3428 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3429 idle_work);
3430 struct drm_device *dev = dev_priv->dev;
3431 struct drm_crtc *crtc;
3432 struct intel_crtc *intel_crtc;
3433
3434 if (!i915_powersave)
3435 return;
3436
3437 mutex_lock(&dev->struct_mutex);
3438
3439 /* GPU isn't processing, downclock it. */
3440 if (!dev_priv->busy) {
3441 intel_decrease_renderclock(dev);
3442 intel_decrease_displayclock(dev);
3443 }
3444
3445 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3446 /* Skip inactive CRTCs */
3447 if (!crtc->fb)
3448 continue;
3449
3450 intel_crtc = to_intel_crtc(crtc);
3451 if (!intel_crtc->busy)
3452 intel_decrease_pllclock(crtc);
3453 }
3454
3455 mutex_unlock(&dev->struct_mutex);
3456}
3457
3458/**
3459 * intel_mark_busy - mark the GPU and possibly the display busy
3460 * @dev: drm device
3461 * @obj: object we're operating on
3462 *
3463 * Callers can use this function to indicate that the GPU is busy processing
3464 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
3465 * buffer), we'll also mark the display as busy, so we know to increase its
3466 * clock frequency.
3467 */
3468void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3469{
3470 drm_i915_private_t *dev_priv = dev->dev_private;
3471 struct drm_crtc *crtc = NULL;
3472 struct intel_framebuffer *intel_fb;
3473 struct intel_crtc *intel_crtc;
3474
3475 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3476 return;
3477
3478 dev_priv->busy = true;
3479 intel_increase_renderclock(dev, true);
3480
3481 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3482 if (!crtc->fb)
3483 continue;
3484
3485 intel_crtc = to_intel_crtc(crtc);
3486 intel_fb = to_intel_framebuffer(crtc->fb);
3487 if (intel_fb->obj == obj) {
3488 if (!intel_crtc->busy) {
3489 /* Non-busy -> busy, upclock */
3490 intel_increase_pllclock(crtc, true);
3491 intel_crtc->busy = true;
3492 } else {
3493 /* Busy -> busy, put off timer */
3494 mod_timer(&intel_crtc->idle_timer, jiffies +
3495 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3496 }
3497 }
3498 }
3499}
3500
3073static void intel_crtc_destroy(struct drm_crtc *crtc) 3501static void intel_crtc_destroy(struct drm_crtc *crtc)
3074{ 3502{
3075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3076 3504
3077 if (intel_crtc->mode_set.mode)
3078 drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode);
3079 drm_crtc_cleanup(crtc); 3505 drm_crtc_cleanup(crtc);
3080 kfree(intel_crtc); 3506 kfree(intel_crtc);
3081} 3507}
@@ -3122,15 +3548,10 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
3122 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; 3548 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
3123 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); 3549 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
3124 3550
3125 intel_crtc->mode_set.crtc = &intel_crtc->base; 3551 intel_crtc->busy = false;
3126 intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
3127 intel_crtc->mode_set.num_connectors = 0;
3128
3129 if (i915_fbpercrtc) {
3130 3552
3131 3553 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
3132 3554 (unsigned long)intel_crtc);
3133 }
3134} 3555}
3135 3556
3136int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 3557int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
@@ -3138,30 +3559,26 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
3138{ 3559{
3139 drm_i915_private_t *dev_priv = dev->dev_private; 3560 drm_i915_private_t *dev_priv = dev->dev_private;
3140 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 3561 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
3141 struct drm_crtc *crtc = NULL; 3562 struct drm_mode_object *drmmode_obj;
3142 int pipe = -1; 3563 struct intel_crtc *crtc;
3143 3564
3144 if (!dev_priv) { 3565 if (!dev_priv) {
3145 DRM_ERROR("called with no initialization\n"); 3566 DRM_ERROR("called with no initialization\n");
3146 return -EINVAL; 3567 return -EINVAL;
3147 } 3568 }
3148 3569
3149 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 3570 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
3150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3571 DRM_MODE_OBJECT_CRTC);
3151 if (crtc->base.id == pipe_from_crtc_id->crtc_id) {
3152 pipe = intel_crtc->pipe;
3153 break;
3154 }
3155 }
3156 3572
3157 if (pipe == -1) { 3573 if (!drmmode_obj) {
3158 DRM_ERROR("no such CRTC id\n"); 3574 DRM_ERROR("no such CRTC id\n");
3159 return -EINVAL; 3575 return -EINVAL;
3160 } 3576 }
3161 3577
3162 pipe_from_crtc_id->pipe = pipe; 3578 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
3579 pipe_from_crtc_id->pipe = crtc->pipe;
3163 3580
3164 return 0; 3581 return 0;
3165} 3582}
3166 3583
3167struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) 3584struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
@@ -3362,8 +3779,56 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
3362 .fb_changed = intelfb_probe, 3779 .fb_changed = intelfb_probe,
3363}; 3780};
3364 3781
3782void intel_init_clock_gating(struct drm_device *dev)
3783{
3784 struct drm_i915_private *dev_priv = dev->dev_private;
3785
3786 /*
3787 * Disable clock gating reported to work incorrectly according to the
3788 * specs, but enable as much else as we can.
3789 */
3790 if (IS_G4X(dev)) {
3791 uint32_t dspclk_gate;
3792 I915_WRITE(RENCLK_GATE_D1, 0);
3793 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3794 GS_UNIT_CLOCK_GATE_DISABLE |
3795 CL_UNIT_CLOCK_GATE_DISABLE);
3796 I915_WRITE(RAMCLK_GATE_D, 0);
3797 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
3798 OVRUNIT_CLOCK_GATE_DISABLE |
3799 OVCUNIT_CLOCK_GATE_DISABLE;
3800 if (IS_GM45(dev))
3801 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
3802 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
3803 } else if (IS_I965GM(dev)) {
3804 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
3805 I915_WRITE(RENCLK_GATE_D2, 0);
3806 I915_WRITE(DSPCLK_GATE_D, 0);
3807 I915_WRITE(RAMCLK_GATE_D, 0);
3808 I915_WRITE16(DEUC, 0);
3809 } else if (IS_I965G(dev)) {
3810 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
3811 I965_RCC_CLOCK_GATE_DISABLE |
3812 I965_RCPB_CLOCK_GATE_DISABLE |
3813 I965_ISC_CLOCK_GATE_DISABLE |
3814 I965_FBC_CLOCK_GATE_DISABLE);
3815 I915_WRITE(RENCLK_GATE_D2, 0);
3816 } else if (IS_I9XX(dev)) {
3817 u32 dstate = I915_READ(D_STATE);
3818
3819 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
3820 DSTATE_DOT_CLOCK_GATING;
3821 I915_WRITE(D_STATE, dstate);
3822 } else if (IS_I855(dev) || IS_I865G(dev)) {
3823 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
3824 } else if (IS_I830(dev)) {
3825 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
3826 }
3827}
3828
3365void intel_modeset_init(struct drm_device *dev) 3829void intel_modeset_init(struct drm_device *dev)
3366{ 3830{
3831 struct drm_i915_private *dev_priv = dev->dev_private;
3367 int num_pipe; 3832 int num_pipe;
3368 int i; 3833 int i;
3369 3834
@@ -3398,15 +3863,47 @@ void intel_modeset_init(struct drm_device *dev)
3398 DRM_DEBUG("%d display pipe%s available.\n", 3863 DRM_DEBUG("%d display pipe%s available.\n",
3399 num_pipe, num_pipe > 1 ? "s" : ""); 3864 num_pipe, num_pipe > 1 ? "s" : "");
3400 3865
3866 if (IS_I85X(dev))
3867 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
3868 else if (IS_I9XX(dev) || IS_G4X(dev))
3869 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
3870
3401 for (i = 0; i < num_pipe; i++) { 3871 for (i = 0; i < num_pipe; i++) {
3402 intel_crtc_init(dev, i); 3872 intel_crtc_init(dev, i);
3403 } 3873 }
3404 3874
3405 intel_setup_outputs(dev); 3875 intel_setup_outputs(dev);
3876
3877 intel_init_clock_gating(dev);
3878
3879 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
3880 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
3881 (unsigned long)dev);
3406} 3882}
3407 3883
3408void intel_modeset_cleanup(struct drm_device *dev) 3884void intel_modeset_cleanup(struct drm_device *dev)
3409{ 3885{
3886 struct drm_i915_private *dev_priv = dev->dev_private;
3887 struct drm_crtc *crtc;
3888 struct intel_crtc *intel_crtc;
3889
3890 mutex_lock(&dev->struct_mutex);
3891
3892 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3893 /* Skip inactive CRTCs */
3894 if (!crtc->fb)
3895 continue;
3896
3897 intel_crtc = to_intel_crtc(crtc);
3898 intel_increase_pllclock(crtc, false);
3899 del_timer_sync(&intel_crtc->idle_timer);
3900 }
3901
3902 intel_increase_renderclock(dev, false);
3903 del_timer_sync(&dev_priv->idle_timer);
3904
3905 mutex_unlock(&dev->struct_mutex);
3906
3410 drm_mode_config_cleanup(dev); 3907 drm_mode_config_cleanup(dev);
3411} 3908}
3412 3909
@@ -3420,3 +3917,20 @@ struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
3420 3917
3421 return &intel_output->enc; 3918 return &intel_output->enc;
3422} 3919}
3920
3921/*
3922 * set vga decode state - true == enable VGA decode
3923 */
3924int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
3925{
3926 struct drm_i915_private *dev_priv = dev->dev_private;
3927 u16 gmch_ctrl;
3928
3929 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
3930 if (state)
3931 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
3932 else
3933 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
3934 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
3935 return 0;
3936}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 26a6227c15fe..3ebbbabfe59b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -117,9 +117,9 @@ struct intel_crtc {
117 uint32_t cursor_addr; 117 uint32_t cursor_addr;
118 u8 lut_r[256], lut_g[256], lut_b[256]; 118 u8 lut_r[256], lut_g[256], lut_b[256];
119 int dpms_mode; 119 int dpms_mode;
120 struct intel_framebuffer *fbdev_fb; 120 bool busy; /* is scanout buffer being updated frequently? */
121 /* a mode_set for fbdev users on this crtc */ 121 struct timer_list idle_timer;
122 struct drm_mode_set mode_set; 122 bool lowfreq_avail;
123}; 123};
124 124
125#define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 125#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
@@ -138,6 +138,7 @@ extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
138extern bool intel_sdvo_init(struct drm_device *dev, int output_device); 138extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
139extern void intel_dvo_init(struct drm_device *dev); 139extern void intel_dvo_init(struct drm_device *dev);
140extern void intel_tv_init(struct drm_device *dev); 140extern void intel_tv_init(struct drm_device *dev);
141extern void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj);
141extern void intel_lvds_init(struct drm_device *dev); 142extern void intel_lvds_init(struct drm_device *dev);
142extern void intel_dp_init(struct drm_device *dev, int dp_reg); 143extern void intel_dp_init(struct drm_device *dev, int dp_reg);
143void 144void
@@ -178,4 +179,5 @@ extern int intel_framebuffer_create(struct drm_device *dev,
178 struct drm_mode_fb_cmd *mode_cmd, 179 struct drm_mode_fb_cmd *mode_cmd,
179 struct drm_framebuffer **fb, 180 struct drm_framebuffer **fb,
180 struct drm_gem_object *obj); 181 struct drm_gem_object *obj);
182
181#endif /* __INTEL_DRV_H__ */ 183#endif /* __INTEL_DRV_H__ */
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 1d30802e773e..7ba4a232a97f 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -39,339 +39,34 @@
39#include "drmP.h" 39#include "drmP.h"
40#include "drm.h" 40#include "drm.h"
41#include "drm_crtc.h" 41#include "drm_crtc.h"
42#include "drm_fb_helper.h"
42#include "intel_drv.h" 43#include "intel_drv.h"
43#include "i915_drm.h" 44#include "i915_drm.h"
44#include "i915_drv.h" 45#include "i915_drv.h"
45 46
46struct intelfb_par { 47struct intelfb_par {
47 struct drm_device *dev; 48 struct drm_fb_helper helper;
48 struct drm_display_mode *our_mode;
49 struct intel_framebuffer *intel_fb; 49 struct intel_framebuffer *intel_fb;
50 int crtc_count; 50 struct drm_display_mode *our_mode;
51 /* crtc currently bound to this */
52 uint32_t crtc_ids[2];
53}; 51};
54 52
55static int intelfb_setcolreg(unsigned regno, unsigned red, unsigned green,
56 unsigned blue, unsigned transp,
57 struct fb_info *info)
58{
59 struct intelfb_par *par = info->par;
60 struct drm_device *dev = par->dev;
61 struct drm_crtc *crtc;
62 int i;
63
64 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
65 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
66 struct drm_mode_set *modeset = &intel_crtc->mode_set;
67 struct drm_framebuffer *fb = modeset->fb;
68
69 for (i = 0; i < par->crtc_count; i++)
70 if (crtc->base.id == par->crtc_ids[i])
71 break;
72
73 if (i == par->crtc_count)
74 continue;
75
76
77 if (regno > 255)
78 return 1;
79
80 if (fb->depth == 8) {
81 intel_crtc_fb_gamma_set(crtc, red, green, blue, regno);
82 return 0;
83 }
84
85 if (regno < 16) {
86 switch (fb->depth) {
87 case 15:
88 fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) |
89 ((green & 0xf800) >> 6) |
90 ((blue & 0xf800) >> 11);
91 break;
92 case 16:
93 fb->pseudo_palette[regno] = (red & 0xf800) |
94 ((green & 0xfc00) >> 5) |
95 ((blue & 0xf800) >> 11);
96 break;
97 case 24:
98 case 32:
99 fb->pseudo_palette[regno] = ((red & 0xff00) << 8) |
100 (green & 0xff00) |
101 ((blue & 0xff00) >> 8);
102 break;
103 }
104 }
105 }
106 return 0;
107}
108
109static int intelfb_check_var(struct fb_var_screeninfo *var,
110 struct fb_info *info)
111{
112 struct intelfb_par *par = info->par;
113 struct intel_framebuffer *intel_fb = par->intel_fb;
114 struct drm_framebuffer *fb = &intel_fb->base;
115 int depth;
116
117 if (var->pixclock == -1 || !var->pixclock)
118 return -EINVAL;
119
120 /* Need to resize the fb object !!! */
121 if (var->xres > fb->width || var->yres > fb->height) {
122 DRM_ERROR("Requested width/height is greater than current fb object %dx%d > %dx%d\n",var->xres,var->yres,fb->width,fb->height);
123 DRM_ERROR("Need resizing code.\n");
124 return -EINVAL;
125 }
126
127 switch (var->bits_per_pixel) {
128 case 16:
129 depth = (var->green.length == 6) ? 16 : 15;
130 break;
131 case 32:
132 depth = (var->transp.length > 0) ? 32 : 24;
133 break;
134 default:
135 depth = var->bits_per_pixel;
136 break;
137 }
138
139 switch (depth) {
140 case 8:
141 var->red.offset = 0;
142 var->green.offset = 0;
143 var->blue.offset = 0;
144 var->red.length = 8;
145 var->green.length = 8;
146 var->blue.length = 8;
147 var->transp.length = 0;
148 var->transp.offset = 0;
149 break;
150 case 15:
151 var->red.offset = 10;
152 var->green.offset = 5;
153 var->blue.offset = 0;
154 var->red.length = 5;
155 var->green.length = 5;
156 var->blue.length = 5;
157 var->transp.length = 1;
158 var->transp.offset = 15;
159 break;
160 case 16:
161 var->red.offset = 11;
162 var->green.offset = 5;
163 var->blue.offset = 0;
164 var->red.length = 5;
165 var->green.length = 6;
166 var->blue.length = 5;
167 var->transp.length = 0;
168 var->transp.offset = 0;
169 break;
170 case 24:
171 var->red.offset = 16;
172 var->green.offset = 8;
173 var->blue.offset = 0;
174 var->red.length = 8;
175 var->green.length = 8;
176 var->blue.length = 8;
177 var->transp.length = 0;
178 var->transp.offset = 0;
179 break;
180 case 32:
181 var->red.offset = 16;
182 var->green.offset = 8;
183 var->blue.offset = 0;
184 var->red.length = 8;
185 var->green.length = 8;
186 var->blue.length = 8;
187 var->transp.length = 8;
188 var->transp.offset = 24;
189 break;
190 default:
191 return -EINVAL;
192 }
193
194 return 0;
195}
196
197/* this will let fbcon do the mode init */
198/* FIXME: take mode config lock? */
199static int intelfb_set_par(struct fb_info *info)
200{
201 struct intelfb_par *par = info->par;
202 struct drm_device *dev = par->dev;
203 struct fb_var_screeninfo *var = &info->var;
204 int i;
205
206 DRM_DEBUG("%d %d\n", var->xres, var->pixclock);
207
208 if (var->pixclock != -1) {
209
210 DRM_ERROR("PIXEL CLOCK SET\n");
211 return -EINVAL;
212 } else {
213 struct drm_crtc *crtc;
214 int ret;
215
216 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
218
219 for (i = 0; i < par->crtc_count; i++)
220 if (crtc->base.id == par->crtc_ids[i])
221 break;
222
223 if (i == par->crtc_count)
224 continue;
225
226 if (crtc->fb == intel_crtc->mode_set.fb) {
227 mutex_lock(&dev->mode_config.mutex);
228 ret = crtc->funcs->set_config(&intel_crtc->mode_set);
229 mutex_unlock(&dev->mode_config.mutex);
230 if (ret)
231 return ret;
232 }
233 }
234 return 0;
235 }
236}
237
238static int intelfb_pan_display(struct fb_var_screeninfo *var,
239 struct fb_info *info)
240{
241 struct intelfb_par *par = info->par;
242 struct drm_device *dev = par->dev;
243 struct drm_mode_set *modeset;
244 struct drm_crtc *crtc;
245 struct intel_crtc *intel_crtc;
246 int ret = 0;
247 int i;
248
249 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
250 for (i = 0; i < par->crtc_count; i++)
251 if (crtc->base.id == par->crtc_ids[i])
252 break;
253
254 if (i == par->crtc_count)
255 continue;
256
257 intel_crtc = to_intel_crtc(crtc);
258 modeset = &intel_crtc->mode_set;
259
260 modeset->x = var->xoffset;
261 modeset->y = var->yoffset;
262
263 if (modeset->num_connectors) {
264 mutex_lock(&dev->mode_config.mutex);
265 ret = crtc->funcs->set_config(modeset);
266 mutex_unlock(&dev->mode_config.mutex);
267 if (!ret) {
268 info->var.xoffset = var->xoffset;
269 info->var.yoffset = var->yoffset;
270 }
271 }
272 }
273
274 return ret;
275}
276
277static void intelfb_on(struct fb_info *info)
278{
279 struct intelfb_par *par = info->par;
280 struct drm_device *dev = par->dev;
281 struct drm_crtc *crtc;
282 struct drm_encoder *encoder;
283 int i;
284
285 /*
286 * For each CRTC in this fb, find all associated encoders
287 * and turn them off, then turn off the CRTC.
288 */
289 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
290 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
291
292 for (i = 0; i < par->crtc_count; i++)
293 if (crtc->base.id == par->crtc_ids[i])
294 break;
295
296 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
297
298 /* Found a CRTC on this fb, now find encoders */
299 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
300 if (encoder->crtc == crtc) {
301 struct drm_encoder_helper_funcs *encoder_funcs;
302 encoder_funcs = encoder->helper_private;
303 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
304 }
305 }
306 }
307}
308
309static void intelfb_off(struct fb_info *info, int dpms_mode)
310{
311 struct intelfb_par *par = info->par;
312 struct drm_device *dev = par->dev;
313 struct drm_crtc *crtc;
314 struct drm_encoder *encoder;
315 int i;
316
317 /*
318 * For each CRTC in this fb, find all associated encoders
319 * and turn them off, then turn off the CRTC.
320 */
321 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
322 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
323
324 for (i = 0; i < par->crtc_count; i++)
325 if (crtc->base.id == par->crtc_ids[i])
326 break;
327
328 /* Found a CRTC on this fb, now find encoders */
329 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
330 if (encoder->crtc == crtc) {
331 struct drm_encoder_helper_funcs *encoder_funcs;
332 encoder_funcs = encoder->helper_private;
333 encoder_funcs->dpms(encoder, dpms_mode);
334 }
335 }
336 if (dpms_mode == DRM_MODE_DPMS_OFF)
337 crtc_funcs->dpms(crtc, dpms_mode);
338 }
339}
340
341static int intelfb_blank(int blank, struct fb_info *info)
342{
343 switch (blank) {
344 case FB_BLANK_UNBLANK:
345 intelfb_on(info);
346 break;
347 case FB_BLANK_NORMAL:
348 intelfb_off(info, DRM_MODE_DPMS_STANDBY);
349 break;
350 case FB_BLANK_HSYNC_SUSPEND:
351 intelfb_off(info, DRM_MODE_DPMS_STANDBY);
352 break;
353 case FB_BLANK_VSYNC_SUSPEND:
354 intelfb_off(info, DRM_MODE_DPMS_SUSPEND);
355 break;
356 case FB_BLANK_POWERDOWN:
357 intelfb_off(info, DRM_MODE_DPMS_OFF);
358 break;
359 }
360 return 0;
361}
362
363static struct fb_ops intelfb_ops = { 53static struct fb_ops intelfb_ops = {
364 .owner = THIS_MODULE, 54 .owner = THIS_MODULE,
365 .fb_check_var = intelfb_check_var, 55 .fb_check_var = drm_fb_helper_check_var,
366 .fb_set_par = intelfb_set_par, 56 .fb_set_par = drm_fb_helper_set_par,
367 .fb_setcolreg = intelfb_setcolreg, 57 .fb_setcolreg = drm_fb_helper_setcolreg,
368 .fb_fillrect = cfb_fillrect, 58 .fb_fillrect = cfb_fillrect,
369 .fb_copyarea = cfb_copyarea, 59 .fb_copyarea = cfb_copyarea,
370 .fb_imageblit = cfb_imageblit, 60 .fb_imageblit = cfb_imageblit,
371 .fb_pan_display = intelfb_pan_display, 61 .fb_pan_display = drm_fb_helper_pan_display,
372 .fb_blank = intelfb_blank, 62 .fb_blank = drm_fb_helper_blank,
373}; 63};
374 64
65static struct drm_fb_helper_funcs intel_fb_helper_funcs = {
66 .gamma_set = intel_crtc_fb_gamma_set,
67};
68
69
375/** 70/**
376 * Curretly it is assumed that the old framebuffer is reused. 71 * Curretly it is assumed that the old framebuffer is reused.
377 * 72 *
@@ -412,25 +107,10 @@ int intelfb_resize(struct drm_device *dev, struct drm_crtc *crtc)
412} 107}
413EXPORT_SYMBOL(intelfb_resize); 108EXPORT_SYMBOL(intelfb_resize);
414 109
415static struct drm_mode_set kernelfb_mode;
416
417static int intelfb_panic(struct notifier_block *n, unsigned long ununsed,
418 void *panic_str)
419{
420 DRM_ERROR("panic occurred, switching back to text console\n");
421
422 intelfb_restore();
423 return 0;
424}
425
426static struct notifier_block paniced = {
427 .notifier_call = intelfb_panic,
428};
429
430static int intelfb_create(struct drm_device *dev, uint32_t fb_width, 110static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
431 uint32_t fb_height, uint32_t surface_width, 111 uint32_t fb_height, uint32_t surface_width,
432 uint32_t surface_height, 112 uint32_t surface_height,
433 struct intel_framebuffer **intel_fb_p) 113 struct drm_framebuffer **fb_p)
434{ 114{
435 struct fb_info *info; 115 struct fb_info *info;
436 struct intelfb_par *par; 116 struct intelfb_par *par;
@@ -479,7 +159,7 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
479 list_add(&fb->filp_head, &dev->mode_config.fb_kernel_list); 159 list_add(&fb->filp_head, &dev->mode_config.fb_kernel_list);
480 160
481 intel_fb = to_intel_framebuffer(fb); 161 intel_fb = to_intel_framebuffer(fb);
482 *intel_fb_p = intel_fb; 162 *fb_p = fb;
483 163
484 info = framebuffer_alloc(sizeof(struct intelfb_par), device); 164 info = framebuffer_alloc(sizeof(struct intelfb_par), device);
485 if (!info) { 165 if (!info) {
@@ -489,21 +169,19 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
489 169
490 par = info->par; 170 par = info->par;
491 171
172 par->helper.funcs = &intel_fb_helper_funcs;
173 par->helper.dev = dev;
174 ret = drm_fb_helper_init_crtc_count(&par->helper, 2,
175 INTELFB_CONN_LIMIT);
176 if (ret)
177 goto out_unref;
178
492 strcpy(info->fix.id, "inteldrmfb"); 179 strcpy(info->fix.id, "inteldrmfb");
493 info->fix.type = FB_TYPE_PACKED_PIXELS;
494 info->fix.visual = FB_VISUAL_TRUECOLOR;
495 info->fix.type_aux = 0;
496 info->fix.xpanstep = 1; /* doing it in hw */
497 info->fix.ypanstep = 1; /* doing it in hw */
498 info->fix.ywrapstep = 0;
499 info->fix.accel = FB_ACCEL_I830;
500 info->fix.type_aux = 0;
501 180
502 info->flags = FBINFO_DEFAULT; 181 info->flags = FBINFO_DEFAULT;
503 182
504 info->fbops = &intelfb_ops; 183 info->fbops = &intelfb_ops;
505 184
506 info->fix.line_length = fb->pitch;
507 185
508 /* setup aperture base/size for vesafb takeover */ 186 /* setup aperture base/size for vesafb takeover */
509 info->aperture_base = dev->mode_config.fb_base; 187 info->aperture_base = dev->mode_config.fb_base;
@@ -527,18 +205,8 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
527 205
528// memset(info->screen_base, 0, size); 206// memset(info->screen_base, 0, size);
529 207
530 info->pseudo_palette = fb->pseudo_palette; 208 drm_fb_helper_fill_fix(info, fb->pitch);
531 info->var.xres_virtual = fb->width; 209 drm_fb_helper_fill_var(info, fb, fb_width, fb_height);
532 info->var.yres_virtual = fb->height;
533 info->var.bits_per_pixel = fb->bits_per_pixel;
534 info->var.xoffset = 0;
535 info->var.yoffset = 0;
536 info->var.activate = FB_ACTIVATE_NOW;
537 info->var.height = -1;
538 info->var.width = -1;
539
540 info->var.xres = fb_width;
541 info->var.yres = fb_height;
542 210
543 /* FIXME: we really shouldn't expose mmio space at all */ 211 /* FIXME: we really shouldn't expose mmio space at all */
544 info->fix.mmio_start = pci_resource_start(dev->pdev, mmio_bar); 212 info->fix.mmio_start = pci_resource_start(dev->pdev, mmio_bar);
@@ -550,64 +218,9 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
550 info->pixmap.flags = FB_PIXMAP_SYSTEM; 218 info->pixmap.flags = FB_PIXMAP_SYSTEM;
551 info->pixmap.scan_align = 1; 219 info->pixmap.scan_align = 1;
552 220
553 switch(fb->depth) {
554 case 8:
555 info->var.red.offset = 0;
556 info->var.green.offset = 0;
557 info->var.blue.offset = 0;
558 info->var.red.length = 8; /* 8bit DAC */
559 info->var.green.length = 8;
560 info->var.blue.length = 8;
561 info->var.transp.offset = 0;
562 info->var.transp.length = 0;
563 break;
564 case 15:
565 info->var.red.offset = 10;
566 info->var.green.offset = 5;
567 info->var.blue.offset = 0;
568 info->var.red.length = 5;
569 info->var.green.length = 5;
570 info->var.blue.length = 5;
571 info->var.transp.offset = 15;
572 info->var.transp.length = 1;
573 break;
574 case 16:
575 info->var.red.offset = 11;
576 info->var.green.offset = 5;
577 info->var.blue.offset = 0;
578 info->var.red.length = 5;
579 info->var.green.length = 6;
580 info->var.blue.length = 5;
581 info->var.transp.offset = 0;
582 break;
583 case 24:
584 info->var.red.offset = 16;
585 info->var.green.offset = 8;
586 info->var.blue.offset = 0;
587 info->var.red.length = 8;
588 info->var.green.length = 8;
589 info->var.blue.length = 8;
590 info->var.transp.offset = 0;
591 info->var.transp.length = 0;
592 break;
593 case 32:
594 info->var.red.offset = 16;
595 info->var.green.offset = 8;
596 info->var.blue.offset = 0;
597 info->var.red.length = 8;
598 info->var.green.length = 8;
599 info->var.blue.length = 8;
600 info->var.transp.offset = 24;
601 info->var.transp.length = 8;
602 break;
603 default:
604 break;
605 }
606
607 fb->fbdev = info; 221 fb->fbdev = info;
608 222
609 par->intel_fb = intel_fb; 223 par->intel_fb = intel_fb;
610 par->dev = dev;
611 224
612 /* To allow resizeing without swapping buffers */ 225 /* To allow resizeing without swapping buffers */
613 DRM_DEBUG("allocated %dx%d fb: 0x%08x, bo %p\n", intel_fb->base.width, 226 DRM_DEBUG("allocated %dx%d fb: 0x%08x, bo %p\n", intel_fb->base.width,
@@ -625,307 +238,12 @@ out:
625 return ret; 238 return ret;
626} 239}
627 240
628static int intelfb_multi_fb_probe_crtc(struct drm_device *dev, struct drm_crtc *crtc)
629{
630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
631 struct intel_framebuffer *intel_fb;
632 struct drm_framebuffer *fb;
633 struct drm_connector *connector;
634 struct fb_info *info;
635 struct intelfb_par *par;
636 struct drm_mode_set *modeset;
637 unsigned int width, height;
638 int new_fb = 0;
639 int ret, i, conn_count;
640
641 if (!drm_helper_crtc_in_use(crtc))
642 return 0;
643
644 if (!crtc->desired_mode)
645 return 0;
646
647 width = crtc->desired_mode->hdisplay;
648 height = crtc->desired_mode->vdisplay;
649
650 /* is there an fb bound to this crtc already */
651 if (!intel_crtc->mode_set.fb) {
652 ret = intelfb_create(dev, width, height, width, height, &intel_fb);
653 if (ret)
654 return -EINVAL;
655 new_fb = 1;
656 } else {
657 fb = intel_crtc->mode_set.fb;
658 intel_fb = to_intel_framebuffer(fb);
659 if ((intel_fb->base.width < width) || (intel_fb->base.height < height))
660 return -EINVAL;
661 }
662
663 info = intel_fb->base.fbdev;
664 par = info->par;
665
666 modeset = &intel_crtc->mode_set;
667 modeset->fb = &intel_fb->base;
668 conn_count = 0;
669 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
670 if (connector->encoder)
671 if (connector->encoder->crtc == modeset->crtc) {
672 modeset->connectors[conn_count] = connector;
673 conn_count++;
674 if (conn_count > INTELFB_CONN_LIMIT)
675 BUG();
676 }
677 }
678
679 for (i = conn_count; i < INTELFB_CONN_LIMIT; i++)
680 modeset->connectors[i] = NULL;
681
682 par->crtc_ids[0] = crtc->base.id;
683
684 modeset->num_connectors = conn_count;
685 if (modeset->crtc->desired_mode) {
686 if (modeset->mode)
687 drm_mode_destroy(dev, modeset->mode);
688 modeset->mode = drm_mode_duplicate(dev,
689 modeset->crtc->desired_mode);
690 }
691
692 par->crtc_count = 1;
693
694 if (new_fb) {
695 info->var.pixclock = -1;
696 if (register_framebuffer(info) < 0)
697 return -EINVAL;
698 } else
699 intelfb_set_par(info);
700
701 DRM_INFO("fb%d: %s frame buffer device\n", info->node,
702 info->fix.id);
703
704 /* Switch back to kernel console on panic */
705 kernelfb_mode = *modeset;
706 atomic_notifier_chain_register(&panic_notifier_list, &paniced);
707 DRM_DEBUG("registered panic notifier\n");
708
709 return 0;
710}
711
712static int intelfb_multi_fb_probe(struct drm_device *dev)
713{
714
715 struct drm_crtc *crtc;
716 int ret = 0;
717
718 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
719 ret = intelfb_multi_fb_probe_crtc(dev, crtc);
720 if (ret)
721 return ret;
722 }
723 return ret;
724}
725
726static int intelfb_single_fb_probe(struct drm_device *dev)
727{
728 struct drm_crtc *crtc;
729 struct drm_connector *connector;
730 unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1;
731 unsigned int surface_width = 0, surface_height = 0;
732 int new_fb = 0;
733 int crtc_count = 0;
734 int ret, i, conn_count = 0;
735 struct intel_framebuffer *intel_fb;
736 struct fb_info *info;
737 struct intelfb_par *par;
738 struct drm_mode_set *modeset = NULL;
739
740 DRM_DEBUG("\n");
741
742 /* Get a count of crtcs now in use and new min/maxes width/heights */
743 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
744 if (!drm_helper_crtc_in_use(crtc))
745 continue;
746
747 crtc_count++;
748 if (!crtc->desired_mode)
749 continue;
750
751 /* Smallest mode determines console size... */
752 if (crtc->desired_mode->hdisplay < fb_width)
753 fb_width = crtc->desired_mode->hdisplay;
754
755 if (crtc->desired_mode->vdisplay < fb_height)
756 fb_height = crtc->desired_mode->vdisplay;
757
758 /* ... but largest for memory allocation dimensions */
759 if (crtc->desired_mode->hdisplay > surface_width)
760 surface_width = crtc->desired_mode->hdisplay;
761
762 if (crtc->desired_mode->vdisplay > surface_height)
763 surface_height = crtc->desired_mode->vdisplay;
764 }
765
766 if (crtc_count == 0 || fb_width == -1 || fb_height == -1) {
767 /* hmm everyone went away - assume VGA cable just fell out
768 and will come back later. */
769 DRM_DEBUG("no CRTCs available?\n");
770 return 0;
771 }
772
773//fail
774 /* Find the fb for our new config */
775 if (list_empty(&dev->mode_config.fb_kernel_list)) {
776 DRM_DEBUG("creating new fb (console size %dx%d, "
777 "buffer size %dx%d)\n", fb_width, fb_height,
778 surface_width, surface_height);
779 ret = intelfb_create(dev, fb_width, fb_height, surface_width,
780 surface_height, &intel_fb);
781 if (ret)
782 return -EINVAL;
783 new_fb = 1;
784 } else {
785 struct drm_framebuffer *fb;
786
787 fb = list_first_entry(&dev->mode_config.fb_kernel_list,
788 struct drm_framebuffer, filp_head);
789 intel_fb = to_intel_framebuffer(fb);
790
791 /* if someone hotplugs something bigger than we have already
792 * allocated, we are pwned. As really we can't resize an
793 * fbdev that is in the wild currently due to fbdev not really
794 * being designed for the lower layers moving stuff around
795 * under it.
796 * - so in the grand style of things - punt.
797 */
798 if ((fb->width < surface_width) ||
799 (fb->height < surface_height)) {
800 DRM_ERROR("fb not large enough for console\n");
801 return -EINVAL;
802 }
803 }
804// fail
805
806 info = intel_fb->base.fbdev;
807 par = info->par;
808
809 crtc_count = 0;
810 /*
811 * For each CRTC, set up the connector list for the CRTC's mode
812 * set configuration.
813 */
814 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
816
817 modeset = &intel_crtc->mode_set;
818 modeset->fb = &intel_fb->base;
819 conn_count = 0;
820 list_for_each_entry(connector, &dev->mode_config.connector_list,
821 head) {
822 if (!connector->encoder)
823 continue;
824
825 if(connector->encoder->crtc == modeset->crtc) {
826 modeset->connectors[conn_count++] = connector;
827 if (conn_count > INTELFB_CONN_LIMIT)
828 BUG();
829 }
830 }
831
832 /* Zero out remaining connector pointers */
833 for (i = conn_count; i < INTELFB_CONN_LIMIT; i++)
834 modeset->connectors[i] = NULL;
835
836 par->crtc_ids[crtc_count++] = crtc->base.id;
837
838 modeset->num_connectors = conn_count;
839 if (modeset->crtc->desired_mode) {
840 if (modeset->mode)
841 drm_mode_destroy(dev, modeset->mode);
842 modeset->mode = drm_mode_duplicate(dev,
843 modeset->crtc->desired_mode);
844 }
845 }
846 par->crtc_count = crtc_count;
847
848 if (new_fb) {
849 info->var.pixclock = -1;
850 if (register_framebuffer(info) < 0)
851 return -EINVAL;
852 } else
853 intelfb_set_par(info);
854
855 DRM_INFO("fb%d: %s frame buffer device\n", info->node,
856 info->fix.id);
857
858 /* Switch back to kernel console on panic */
859 kernelfb_mode = *modeset;
860 atomic_notifier_chain_register(&panic_notifier_list, &paniced);
861 DRM_DEBUG("registered panic notifier\n");
862
863 return 0;
864}
865
866/**
867 * intelfb_restore - restore the framebuffer console (kernel) config
868 *
869 * Restore's the kernel's fbcon mode, used for lastclose & panic paths.
870 */
871void intelfb_restore(void)
872{
873 int ret;
874 if ((ret = drm_crtc_helper_set_config(&kernelfb_mode)) != 0) {
875 DRM_ERROR("Failed to restore crtc configuration: %d\n",
876 ret);
877 }
878}
879
880static void intelfb_restore_work_fn(struct work_struct *ignored)
881{
882 intelfb_restore();
883}
884static DECLARE_WORK(intelfb_restore_work, intelfb_restore_work_fn);
885
886static void intelfb_sysrq(int dummy1, struct tty_struct *dummy3)
887{
888 schedule_work(&intelfb_restore_work);
889}
890
891static struct sysrq_key_op sysrq_intelfb_restore_op = {
892 .handler = intelfb_sysrq,
893 .help_msg = "force-fb(V)",
894 .action_msg = "Restore framebuffer console",
895};
896
897int intelfb_probe(struct drm_device *dev) 241int intelfb_probe(struct drm_device *dev)
898{ 242{
899 int ret; 243 int ret;
900 244
901 DRM_DEBUG("\n"); 245 DRM_DEBUG("\n");
902 246 ret = drm_fb_helper_single_fb_probe(dev, intelfb_create);
903 /* something has changed in the lower levels of hell - deal with it
904 here */
905
906 /* two modes : a) 1 fb to rule all crtcs.
907 b) one fb per crtc.
908 two actions 1) new connected device
909 2) device removed.
910 case a/1 : if the fb surface isn't big enough - resize the surface fb.
911 if the fb size isn't big enough - resize fb into surface.
912 if everything big enough configure the new crtc/etc.
913 case a/2 : undo the configuration
914 possibly resize down the fb to fit the new configuration.
915 case b/1 : see if it is on a new crtc - setup a new fb and add it.
916 case b/2 : teardown the new fb.
917 */
918
919 /* mode a first */
920 /* search for an fb */
921 if (i915_fbpercrtc == 1) {
922 ret = intelfb_multi_fb_probe(dev);
923 } else {
924 ret = intelfb_single_fb_probe(dev);
925 }
926
927 register_sysrq_key('v', &sysrq_intelfb_restore_op);
928
929 return ret; 247 return ret;
930} 248}
931EXPORT_SYMBOL(intelfb_probe); 249EXPORT_SYMBOL(intelfb_probe);
@@ -940,13 +258,14 @@ int intelfb_remove(struct drm_device *dev, struct drm_framebuffer *fb)
940 info = fb->fbdev; 258 info = fb->fbdev;
941 259
942 if (info) { 260 if (info) {
261 struct intelfb_par *par = info->par;
943 unregister_framebuffer(info); 262 unregister_framebuffer(info);
944 iounmap(info->screen_base); 263 iounmap(info->screen_base);
264 if (info->par)
265 drm_fb_helper_free(&par->helper);
945 framebuffer_release(info); 266 framebuffer_release(info);
946 } 267 }
947 268
948 atomic_notifier_chain_unregister(&panic_notifier_list, &paniced);
949 memset(&kernelfb_mode, 0, sizeof(struct drm_mode_set));
950 return 0; 269 return 0;
951} 270}
952EXPORT_SYMBOL(intelfb_remove); 271EXPORT_SYMBOL(intelfb_remove);
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 62b8bead7652..c7eab724c418 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -42,11 +42,11 @@ void intel_i2c_quirk_set(struct drm_device *dev, bool enable)
42 if (!IS_IGD(dev)) 42 if (!IS_IGD(dev))
43 return; 43 return;
44 if (enable) 44 if (enable)
45 I915_WRITE(CG_2D_DIS, 45 I915_WRITE(DSPCLK_GATE_D,
46 I915_READ(CG_2D_DIS) | DPCUNIT_CLOCK_GATE_DISABLE); 46 I915_READ(DSPCLK_GATE_D) | DPCUNIT_CLOCK_GATE_DISABLE);
47 else 47 else
48 I915_WRITE(CG_2D_DIS, 48 I915_WRITE(DSPCLK_GATE_D,
49 I915_READ(CG_2D_DIS) & (~DPCUNIT_CLOCK_GATE_DISABLE)); 49 I915_READ(DSPCLK_GATE_D) & (~DPCUNIT_CLOCK_GATE_DISABLE));
50} 50}
51 51
52/* 52/*
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 8df02ef89261..dafc0da1c256 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -38,16 +38,6 @@
38#include "i915_drv.h" 38#include "i915_drv.h"
39#include <linux/acpi.h> 39#include <linux/acpi.h>
40 40
41#define I915_LVDS "i915_lvds"
42
43/*
44 * the following four scaling options are defined.
45 * #define DRM_MODE_SCALE_NON_GPU 0
46 * #define DRM_MODE_SCALE_FULLSCREEN 1
47 * #define DRM_MODE_SCALE_NO_SCALE 2
48 * #define DRM_MODE_SCALE_ASPECT 3
49 */
50
51/* Private structure for the integrated LVDS support */ 41/* Private structure for the integrated LVDS support */
52struct intel_lvds_priv { 42struct intel_lvds_priv {
53 int fitting_mode; 43 int fitting_mode;
@@ -336,7 +326,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
336 I915_WRITE(BCLRPAT_B, 0); 326 I915_WRITE(BCLRPAT_B, 0);
337 327
338 switch (lvds_priv->fitting_mode) { 328 switch (lvds_priv->fitting_mode) {
339 case DRM_MODE_SCALE_NO_SCALE: 329 case DRM_MODE_SCALE_CENTER:
340 /* 330 /*
341 * For centered modes, we have to calculate border widths & 331 * For centered modes, we have to calculate border widths &
342 * heights and modify the values programmed into the CRTC. 332 * heights and modify the values programmed into the CRTC.
@@ -672,9 +662,8 @@ static int intel_lvds_set_property(struct drm_connector *connector,
672 connector->encoder) { 662 connector->encoder) {
673 struct drm_crtc *crtc = connector->encoder->crtc; 663 struct drm_crtc *crtc = connector->encoder->crtc;
674 struct intel_lvds_priv *lvds_priv = intel_output->dev_priv; 664 struct intel_lvds_priv *lvds_priv = intel_output->dev_priv;
675 if (value == DRM_MODE_SCALE_NON_GPU) { 665 if (value == DRM_MODE_SCALE_NONE) {
676 DRM_DEBUG_KMS(I915_LVDS, 666 DRM_DEBUG_KMS("no scaling not supported\n");
677 "non_GPU property is unsupported\n");
678 return 0; 667 return 0;
679 } 668 }
680 if (lvds_priv->fitting_mode == value) { 669 if (lvds_priv->fitting_mode == value) {
@@ -731,8 +720,7 @@ static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
731 720
732static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 721static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
733{ 722{
734 DRM_DEBUG_KMS(I915_LVDS, 723 DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident);
735 "Skipping LVDS initialization for %s\n", id->ident);
736 return 1; 724 return 1;
737} 725}
738 726
@@ -1027,7 +1015,7 @@ out:
1027 return; 1015 return;
1028 1016
1029failed: 1017failed:
1030 DRM_DEBUG_KMS(I915_LVDS, "No LVDS modes found, disabling.\n"); 1018 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1031 if (intel_output->ddc_bus) 1019 if (intel_output->ddc_bus)
1032 intel_i2c_destroy(intel_output->ddc_bus); 1020 intel_i2c_destroy(intel_output->ddc_bus);
1033 drm_connector_cleanup(connector); 1021 drm_connector_cleanup(connector);
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index d3b74ba62b4a..0bf28efcf2c1 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -37,7 +37,19 @@
37#include "intel_sdvo_regs.h" 37#include "intel_sdvo_regs.h"
38 38
39#undef SDVO_DEBUG 39#undef SDVO_DEBUG
40#define I915_SDVO "i915_sdvo" 40
41static char *tv_format_names[] = {
42 "NTSC_M" , "NTSC_J" , "NTSC_443",
43 "PAL_B" , "PAL_D" , "PAL_G" ,
44 "PAL_H" , "PAL_I" , "PAL_M" ,
45 "PAL_N" , "PAL_NC" , "PAL_60" ,
46 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
47 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
48 "SECAM_60"
49};
50
51#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
52
41struct intel_sdvo_priv { 53struct intel_sdvo_priv {
42 u8 slave_addr; 54 u8 slave_addr;
43 55
@@ -71,6 +83,15 @@ struct intel_sdvo_priv {
71 */ 83 */
72 bool is_tv; 84 bool is_tv;
73 85
86 /* This is for current tv format name */
87 char *tv_format_name;
88
89 /* This contains all current supported TV format */
90 char *tv_format_supported[TV_FORMAT_NUM];
91 int format_supported_num;
92 struct drm_property *tv_format_property;
93 struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
94
74 /** 95 /**
75 * This is set if we treat the device as HDMI, instead of DVI. 96 * This is set if we treat the device as HDMI, instead of DVI.
76 */ 97 */
@@ -97,14 +118,6 @@ struct intel_sdvo_priv {
97 */ 118 */
98 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions; 119 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
99 120
100 /**
101 * Current selected TV format.
102 *
103 * This is stored in the same structure that's passed to the device, for
104 * convenience.
105 */
106 struct intel_sdvo_tv_format tv_format;
107
108 /* 121 /*
109 * supported encoding mode, used to determine whether HDMI is 122 * supported encoding mode, used to determine whether HDMI is
110 * supported 123 * supported
@@ -114,6 +127,9 @@ struct intel_sdvo_priv {
114 /* DDC bus used by this SDVO output */ 127 /* DDC bus used by this SDVO output */
115 uint8_t ddc_bus; 128 uint8_t ddc_bus;
116 129
130 /* Mac mini hack -- use the same DDC as the analog connector */
131 struct i2c_adapter *analog_ddc_bus;
132
117 int save_sdvo_mult; 133 int save_sdvo_mult;
118 u16 save_active_outputs; 134 u16 save_active_outputs;
119 struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2; 135 struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
@@ -188,7 +204,7 @@ static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
188 return true; 204 return true;
189 } 205 }
190 206
191 DRM_DEBUG("i2c transfer returned %d\n", ret); 207 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
192 return false; 208 return false;
193} 209}
194 210
@@ -298,7 +314,7 @@ static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
298 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 314 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
299 int i; 315 int i;
300 316
301 DRM_DEBUG_KMS(I915_SDVO, "%s: W: %02X ", 317 DRM_DEBUG_KMS("%s: W: %02X ",
302 SDVO_NAME(sdvo_priv), cmd); 318 SDVO_NAME(sdvo_priv), cmd);
303 for (i = 0; i < args_len; i++) 319 for (i = 0; i < args_len; i++)
304 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); 320 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
@@ -351,7 +367,7 @@ static void intel_sdvo_debug_response(struct intel_output *intel_output,
351 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 367 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
352 int i; 368 int i;
353 369
354 DRM_DEBUG_KMS(I915_SDVO, "%s: R: ", SDVO_NAME(sdvo_priv)); 370 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv));
355 for (i = 0; i < response_len; i++) 371 for (i = 0; i < response_len; i++)
356 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]); 372 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
357 for (; i < 8; i++) 373 for (; i < 8; i++)
@@ -668,10 +684,10 @@ static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
668 status = intel_sdvo_read_response(intel_output, &response, 1); 684 status = intel_sdvo_read_response(intel_output, &response, 1);
669 685
670 if (status != SDVO_CMD_STATUS_SUCCESS) { 686 if (status != SDVO_CMD_STATUS_SUCCESS) {
671 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n"); 687 DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n");
672 return SDVO_CLOCK_RATE_MULT_1X; 688 return SDVO_CLOCK_RATE_MULT_1X;
673 } else { 689 } else {
674 DRM_DEBUG("Current clock rate multiplier: %d\n", response); 690 DRM_DEBUG_KMS("Current clock rate multiplier: %d\n", response);
675 } 691 }
676 692
677 return response; 693 return response;
@@ -945,23 +961,28 @@ static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
945 961
946static void intel_sdvo_set_tv_format(struct intel_output *output) 962static void intel_sdvo_set_tv_format(struct intel_output *output)
947{ 963{
964
965 struct intel_sdvo_tv_format format;
948 struct intel_sdvo_priv *sdvo_priv = output->dev_priv; 966 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
949 struct intel_sdvo_tv_format *format, unset; 967 uint32_t format_map, i;
950 u8 status; 968 uint8_t status;
951 969
952 format = &sdvo_priv->tv_format; 970 for (i = 0; i < TV_FORMAT_NUM; i++)
953 memset(&unset, 0, sizeof(unset)); 971 if (tv_format_names[i] == sdvo_priv->tv_format_name)
954 if (memcmp(format, &unset, sizeof(*format))) { 972 break;
955 DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n", 973
956 SDVO_NAME(sdvo_priv)); 974 format_map = 1 << i;
957 format->ntsc_m = 1; 975 memset(&format, 0, sizeof(format));
958 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format, 976 memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?
959 sizeof(*format)); 977 sizeof(format) : sizeof(format_map));
960 status = intel_sdvo_read_response(output, NULL, 0); 978
961 if (status != SDVO_CMD_STATUS_SUCCESS) 979 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, &format_map,
962 DRM_DEBUG("%s: Failed to set TV format\n", 980 sizeof(format));
963 SDVO_NAME(sdvo_priv)); 981
964 } 982 status = intel_sdvo_read_response(output, NULL, 0);
983 if (status != SDVO_CMD_STATUS_SUCCESS)
984 DRM_DEBUG("%s: Failed to set TV format\n",
985 SDVO_NAME(sdvo_priv));
965} 986}
966 987
967static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, 988static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
@@ -1230,8 +1251,8 @@ static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1230 * a given it the status is a success, we succeeded. 1251 * a given it the status is a success, we succeeded.
1231 */ 1252 */
1232 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { 1253 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1233 DRM_DEBUG("First %s output reported failure to sync\n", 1254 DRM_DEBUG_KMS("First %s output reported failure to "
1234 SDVO_NAME(sdvo_priv)); 1255 "sync\n", SDVO_NAME(sdvo_priv));
1235 } 1256 }
1236 1257
1237 if (0) 1258 if (0)
@@ -1326,8 +1347,8 @@ static void intel_sdvo_restore(struct drm_connector *connector)
1326 intel_wait_for_vblank(dev); 1347 intel_wait_for_vblank(dev);
1327 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2); 1348 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
1328 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) 1349 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1329 DRM_DEBUG("First %s output reported failure to sync\n", 1350 DRM_DEBUG_KMS("First %s output reported failure to "
1330 SDVO_NAME(sdvo_priv)); 1351 "sync\n", SDVO_NAME(sdvo_priv));
1331 } 1352 }
1332 1353
1333 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs); 1354 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
@@ -1405,7 +1426,7 @@ int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1405 u8 response[2]; 1426 u8 response[2];
1406 u8 status; 1427 u8 status;
1407 struct intel_output *intel_output; 1428 struct intel_output *intel_output;
1408 DRM_DEBUG("\n"); 1429 DRM_DEBUG_KMS("\n");
1409 1430
1410 if (!connector) 1431 if (!connector)
1411 return 0; 1432 return 0;
@@ -1478,6 +1499,36 @@ intel_sdvo_multifunc_encoder(struct intel_output *intel_output)
1478 return (caps > 1); 1499 return (caps > 1);
1479} 1500}
1480 1501
1502static struct drm_connector *
1503intel_find_analog_connector(struct drm_device *dev)
1504{
1505 struct drm_connector *connector;
1506 struct intel_output *intel_output;
1507
1508 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1509 intel_output = to_intel_output(connector);
1510 if (intel_output->type == INTEL_OUTPUT_ANALOG)
1511 return connector;
1512 }
1513 return NULL;
1514}
1515
1516static int
1517intel_analog_is_connected(struct drm_device *dev)
1518{
1519 struct drm_connector *analog_connector;
1520 analog_connector = intel_find_analog_connector(dev);
1521
1522 if (!analog_connector)
1523 return false;
1524
1525 if (analog_connector->funcs->detect(analog_connector) ==
1526 connector_status_disconnected)
1527 return false;
1528
1529 return true;
1530}
1531
1481enum drm_connector_status 1532enum drm_connector_status
1482intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response) 1533intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
1483{ 1534{
@@ -1488,6 +1539,15 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
1488 1539
1489 edid = drm_get_edid(&intel_output->base, 1540 edid = drm_get_edid(&intel_output->base,
1490 intel_output->ddc_bus); 1541 intel_output->ddc_bus);
1542
1543 /* when there is no edid and no monitor is connected with VGA
1544 * port, try to use the CRT ddc to read the EDID for DVI-connector
1545 */
1546 if (edid == NULL &&
1547 sdvo_priv->analog_ddc_bus &&
1548 !intel_analog_is_connected(intel_output->base.dev))
1549 edid = drm_get_edid(&intel_output->base,
1550 sdvo_priv->analog_ddc_bus);
1491 if (edid != NULL) { 1551 if (edid != NULL) {
1492 /* Don't report the output as connected if it's a DVI-I 1552 /* Don't report the output as connected if it's a DVI-I
1493 * connector with a non-digital EDID coming out. 1553 * connector with a non-digital EDID coming out.
@@ -1516,10 +1576,11 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect
1516 struct intel_output *intel_output = to_intel_output(connector); 1576 struct intel_output *intel_output = to_intel_output(connector);
1517 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 1577 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1518 1578
1519 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0); 1579 intel_sdvo_write_cmd(intel_output,
1580 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1520 status = intel_sdvo_read_response(intel_output, &response, 2); 1581 status = intel_sdvo_read_response(intel_output, &response, 2);
1521 1582
1522 DRM_DEBUG("SDVO response %d %d\n", response & 0xff, response >> 8); 1583 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
1523 1584
1524 if (status != SDVO_CMD_STATUS_SUCCESS) 1585 if (status != SDVO_CMD_STATUS_SUCCESS)
1525 return connector_status_unknown; 1586 return connector_status_unknown;
@@ -1540,50 +1601,32 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect
1540static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1601static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1541{ 1602{
1542 struct intel_output *intel_output = to_intel_output(connector); 1603 struct intel_output *intel_output = to_intel_output(connector);
1604 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1605 int num_modes;
1543 1606
1544 /* set the bus switch and get the modes */ 1607 /* set the bus switch and get the modes */
1545 intel_ddc_get_modes(intel_output); 1608 num_modes = intel_ddc_get_modes(intel_output);
1546 1609
1547#if 0 1610 /*
1548 struct drm_device *dev = encoder->dev; 1611 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1549 struct drm_i915_private *dev_priv = dev->dev_private; 1612 * link between analog and digital outputs. So, if the regular SDVO
1550 /* Mac mini hack. On this device, I get DDC through the analog, which 1613 * DDC fails, check to see if the analog output is disconnected, in
1551 * load-detects as disconnected. I fail to DDC through the SDVO DDC, 1614 * which case we'll look there for the digital DDC data.
1552 * but it does load-detect as connected. So, just steal the DDC bits
1553 * from analog when we fail at finding it the right way.
1554 */ 1615 */
1555 crt = xf86_config->output[0]; 1616 if (num_modes == 0 &&
1556 intel_output = crt->driver_private; 1617 sdvo_priv->analog_ddc_bus &&
1557 if (intel_output->type == I830_OUTPUT_ANALOG && 1618 !intel_analog_is_connected(intel_output->base.dev)) {
1558 crt->funcs->detect(crt) == XF86OutputStatusDisconnected) { 1619 struct i2c_adapter *digital_ddc_bus;
1559 I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A");
1560 edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus);
1561 xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true);
1562 }
1563 if (edid_mon) {
1564 xf86OutputSetEDID(output, edid_mon);
1565 modes = xf86OutputGetEDIDModes(output);
1566 }
1567#endif
1568}
1569 1620
1570/** 1621 /* Switch to the analog ddc bus and try that
1571 * This function checks the current TV format, and chooses a default if 1622 */
1572 * it hasn't been set. 1623 digital_ddc_bus = intel_output->ddc_bus;
1573 */ 1624 intel_output->ddc_bus = sdvo_priv->analog_ddc_bus;
1574static void
1575intel_sdvo_check_tv_format(struct intel_output *output)
1576{
1577 struct intel_sdvo_priv *dev_priv = output->dev_priv;
1578 struct intel_sdvo_tv_format format;
1579 uint8_t status;
1580 1625
1581 intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0); 1626 (void) intel_ddc_get_modes(intel_output);
1582 status = intel_sdvo_read_response(output, &format, sizeof(format));
1583 if (status != SDVO_CMD_STATUS_SUCCESS)
1584 return;
1585 1627
1586 memcpy(&dev_priv->tv_format, &format, sizeof(format)); 1628 intel_output->ddc_bus = digital_ddc_bus;
1629 }
1587} 1630}
1588 1631
1589/* 1632/*
@@ -1656,17 +1699,26 @@ static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1656 struct intel_output *output = to_intel_output(connector); 1699 struct intel_output *output = to_intel_output(connector);
1657 struct intel_sdvo_priv *sdvo_priv = output->dev_priv; 1700 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1658 struct intel_sdvo_sdtv_resolution_request tv_res; 1701 struct intel_sdvo_sdtv_resolution_request tv_res;
1659 uint32_t reply = 0; 1702 uint32_t reply = 0, format_map = 0;
1703 int i;
1660 uint8_t status; 1704 uint8_t status;
1661 int i = 0;
1662 1705
1663 intel_sdvo_check_tv_format(output);
1664 1706
1665 /* Read the list of supported input resolutions for the selected TV 1707 /* Read the list of supported input resolutions for the selected TV
1666 * format. 1708 * format.
1667 */ 1709 */
1668 memset(&tv_res, 0, sizeof(tv_res)); 1710 for (i = 0; i < TV_FORMAT_NUM; i++)
1669 memcpy(&tv_res, &sdvo_priv->tv_format, sizeof(tv_res)); 1711 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1712 break;
1713
1714 format_map = (1 << i);
1715 memcpy(&tv_res, &format_map,
1716 sizeof(struct intel_sdvo_sdtv_resolution_request) >
1717 sizeof(format_map) ? sizeof(format_map) :
1718 sizeof(struct intel_sdvo_sdtv_resolution_request));
1719
1720 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1721
1670 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 1722 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1671 &tv_res, sizeof(tv_res)); 1723 &tv_res, sizeof(tv_res));
1672 status = intel_sdvo_read_response(output, &reply, 3); 1724 status = intel_sdvo_read_response(output, &reply, 3);
@@ -1681,6 +1733,7 @@ static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1681 if (nmode) 1733 if (nmode)
1682 drm_mode_probed_add(connector, nmode); 1734 drm_mode_probed_add(connector, nmode);
1683 } 1735 }
1736
1684} 1737}
1685 1738
1686static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 1739static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
@@ -1748,17 +1801,62 @@ static void intel_sdvo_destroy(struct drm_connector *connector)
1748 intel_i2c_destroy(intel_output->i2c_bus); 1801 intel_i2c_destroy(intel_output->i2c_bus);
1749 if (intel_output->ddc_bus) 1802 if (intel_output->ddc_bus)
1750 intel_i2c_destroy(intel_output->ddc_bus); 1803 intel_i2c_destroy(intel_output->ddc_bus);
1804 if (sdvo_priv->analog_ddc_bus)
1805 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
1751 1806
1752 if (sdvo_priv->sdvo_lvds_fixed_mode != NULL) 1807 if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
1753 drm_mode_destroy(connector->dev, 1808 drm_mode_destroy(connector->dev,
1754 sdvo_priv->sdvo_lvds_fixed_mode); 1809 sdvo_priv->sdvo_lvds_fixed_mode);
1755 1810
1811 if (sdvo_priv->tv_format_property)
1812 drm_property_destroy(connector->dev,
1813 sdvo_priv->tv_format_property);
1814
1756 drm_sysfs_connector_remove(connector); 1815 drm_sysfs_connector_remove(connector);
1757 drm_connector_cleanup(connector); 1816 drm_connector_cleanup(connector);
1758 1817
1759 kfree(intel_output); 1818 kfree(intel_output);
1760} 1819}
1761 1820
1821static int
1822intel_sdvo_set_property(struct drm_connector *connector,
1823 struct drm_property *property,
1824 uint64_t val)
1825{
1826 struct intel_output *intel_output = to_intel_output(connector);
1827 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1828 struct drm_encoder *encoder = &intel_output->enc;
1829 struct drm_crtc *crtc = encoder->crtc;
1830 int ret = 0;
1831 bool changed = false;
1832
1833 ret = drm_connector_property_set_value(connector, property, val);
1834 if (ret < 0)
1835 goto out;
1836
1837 if (property == sdvo_priv->tv_format_property) {
1838 if (val >= TV_FORMAT_NUM) {
1839 ret = -EINVAL;
1840 goto out;
1841 }
1842 if (sdvo_priv->tv_format_name ==
1843 sdvo_priv->tv_format_supported[val])
1844 goto out;
1845
1846 sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[val];
1847 changed = true;
1848 } else {
1849 ret = -EINVAL;
1850 goto out;
1851 }
1852
1853 if (changed && crtc)
1854 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
1855 crtc->y, crtc->fb);
1856out:
1857 return ret;
1858}
1859
1762static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { 1860static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1763 .dpms = intel_sdvo_dpms, 1861 .dpms = intel_sdvo_dpms,
1764 .mode_fixup = intel_sdvo_mode_fixup, 1862 .mode_fixup = intel_sdvo_mode_fixup,
@@ -1773,6 +1871,7 @@ static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
1773 .restore = intel_sdvo_restore, 1871 .restore = intel_sdvo_restore,
1774 .detect = intel_sdvo_detect, 1872 .detect = intel_sdvo_detect,
1775 .fill_modes = drm_helper_probe_single_connector_modes, 1873 .fill_modes = drm_helper_probe_single_connector_modes,
1874 .set_property = intel_sdvo_set_property,
1776 .destroy = intel_sdvo_destroy, 1875 .destroy = intel_sdvo_destroy,
1777}; 1876};
1778 1877
@@ -2013,10 +2112,9 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
2013 2112
2014 sdvo_priv->controlled_output = 0; 2113 sdvo_priv->controlled_output = 0;
2015 memcpy(bytes, &sdvo_priv->caps.output_flags, 2); 2114 memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
2016 DRM_DEBUG_KMS(I915_SDVO, 2115 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2017 "%s: Unknown SDVO output type (0x%02x%02x)\n", 2116 SDVO_NAME(sdvo_priv),
2018 SDVO_NAME(sdvo_priv), 2117 bytes[0], bytes[1]);
2019 bytes[0], bytes[1]);
2020 ret = false; 2118 ret = false;
2021 } 2119 }
2022 intel_output->crtc_mask = (1 << 0) | (1 << 1); 2120 intel_output->crtc_mask = (1 << 0) | (1 << 1);
@@ -2029,6 +2127,55 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
2029 2127
2030} 2128}
2031 2129
2130static void intel_sdvo_tv_create_property(struct drm_connector *connector)
2131{
2132 struct intel_output *intel_output = to_intel_output(connector);
2133 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
2134 struct intel_sdvo_tv_format format;
2135 uint32_t format_map, i;
2136 uint8_t status;
2137
2138 intel_sdvo_set_target_output(intel_output,
2139 sdvo_priv->controlled_output);
2140
2141 intel_sdvo_write_cmd(intel_output,
2142 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0);
2143 status = intel_sdvo_read_response(intel_output,
2144 &format, sizeof(format));
2145 if (status != SDVO_CMD_STATUS_SUCCESS)
2146 return;
2147
2148 memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ?
2149 sizeof(format_map) : sizeof(format));
2150
2151 if (format_map == 0)
2152 return;
2153
2154 sdvo_priv->format_supported_num = 0;
2155 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2156 if (format_map & (1 << i)) {
2157 sdvo_priv->tv_format_supported
2158 [sdvo_priv->format_supported_num++] =
2159 tv_format_names[i];
2160 }
2161
2162
2163 sdvo_priv->tv_format_property =
2164 drm_property_create(
2165 connector->dev, DRM_MODE_PROP_ENUM,
2166 "mode", sdvo_priv->format_supported_num);
2167
2168 for (i = 0; i < sdvo_priv->format_supported_num; i++)
2169 drm_property_add_enum(
2170 sdvo_priv->tv_format_property, i,
2171 i, sdvo_priv->tv_format_supported[i]);
2172
2173 sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[0];
2174 drm_connector_attach_property(
2175 connector, sdvo_priv->tv_format_property, 0);
2176
2177}
2178
2032bool intel_sdvo_init(struct drm_device *dev, int output_device) 2179bool intel_sdvo_init(struct drm_device *dev, int output_device)
2033{ 2180{
2034 struct drm_connector *connector; 2181 struct drm_connector *connector;
@@ -2066,18 +2213,22 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
2066 /* Read the regs to test if we can talk to the device */ 2213 /* Read the regs to test if we can talk to the device */
2067 for (i = 0; i < 0x40; i++) { 2214 for (i = 0; i < 0x40; i++) {
2068 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) { 2215 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
2069 DRM_DEBUG_KMS(I915_SDVO, 2216 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
2070 "No SDVO device found on SDVO%c\n",
2071 output_device == SDVOB ? 'B' : 'C'); 2217 output_device == SDVOB ? 'B' : 'C');
2072 goto err_i2c; 2218 goto err_i2c;
2073 } 2219 }
2074 } 2220 }
2075 2221
2076 /* setup the DDC bus. */ 2222 /* setup the DDC bus. */
2077 if (output_device == SDVOB) 2223 if (output_device == SDVOB) {
2078 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS"); 2224 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
2079 else 2225 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2226 "SDVOB/VGA DDC BUS");
2227 } else {
2080 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS"); 2228 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
2229 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2230 "SDVOC/VGA DDC BUS");
2231 }
2081 2232
2082 if (intel_output->ddc_bus == NULL) 2233 if (intel_output->ddc_bus == NULL)
2083 goto err_i2c; 2234 goto err_i2c;
@@ -2090,7 +2241,7 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
2090 2241
2091 if (intel_sdvo_output_setup(intel_output, 2242 if (intel_sdvo_output_setup(intel_output,
2092 sdvo_priv->caps.output_flags) != true) { 2243 sdvo_priv->caps.output_flags) != true) {
2093 DRM_DEBUG("SDVO output failed to setup on SDVO%c\n", 2244 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
2094 output_device == SDVOB ? 'B' : 'C'); 2245 output_device == SDVOB ? 'B' : 'C');
2095 goto err_i2c; 2246 goto err_i2c;
2096 } 2247 }
@@ -2111,6 +2262,8 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
2111 drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs); 2262 drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
2112 2263
2113 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc); 2264 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
2265 if (sdvo_priv->is_tv)
2266 intel_sdvo_tv_create_property(connector);
2114 drm_sysfs_connector_add(connector); 2267 drm_sysfs_connector_add(connector);
2115 2268
2116 intel_sdvo_select_ddc_bus(sdvo_priv); 2269 intel_sdvo_select_ddc_bus(sdvo_priv);
@@ -2123,7 +2276,7 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
2123 &sdvo_priv->pixel_clock_max); 2276 &sdvo_priv->pixel_clock_max);
2124 2277
2125 2278
2126 DRM_DEBUG_KMS(I915_SDVO, "%s device VID/DID: %02X:%02X.%02X, " 2279 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2127 "clock range %dMHz - %dMHz, " 2280 "clock range %dMHz - %dMHz, "
2128 "input 1: %c, input 2: %c, " 2281 "input 1: %c, input 2: %c, "
2129 "output 1: %c, output 2: %c\n", 2282 "output 1: %c, output 2: %c\n",
@@ -2143,6 +2296,8 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
2143 return true; 2296 return true;
2144 2297
2145err_i2c: 2298err_i2c:
2299 if (sdvo_priv->analog_ddc_bus != NULL)
2300 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
2146 if (intel_output->ddc_bus != NULL) 2301 if (intel_output->ddc_bus != NULL)
2147 intel_i2c_destroy(intel_output->ddc_bus); 2302 intel_i2c_destroy(intel_output->ddc_bus);
2148 if (intel_output->i2c_bus != NULL) 2303 if (intel_output->i2c_bus != NULL)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 5b1c9e9fdba0..c64eab493fb0 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1437,6 +1437,35 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct intel_output *intel_output)
1437 return type; 1437 return type;
1438} 1438}
1439 1439
1440/*
1441 * Here we set accurate tv format according to connector type
1442 * i.e Component TV should not be assigned by NTSC or PAL
1443 */
1444static void intel_tv_find_better_format(struct drm_connector *connector)
1445{
1446 struct intel_output *intel_output = to_intel_output(connector);
1447 struct intel_tv_priv *tv_priv = intel_output->dev_priv;
1448 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_output);
1449 int i;
1450
1451 if ((tv_priv->type == DRM_MODE_CONNECTOR_Component) ==
1452 tv_mode->component_only)
1453 return;
1454
1455
1456 for (i = 0; i < sizeof(tv_modes) / sizeof(*tv_modes); i++) {
1457 tv_mode = tv_modes + i;
1458
1459 if ((tv_priv->type == DRM_MODE_CONNECTOR_Component) ==
1460 tv_mode->component_only)
1461 break;
1462 }
1463
1464 tv_priv->tv_format = tv_mode->name;
1465 drm_connector_property_set_value(connector,
1466 connector->dev->mode_config.tv_mode_property, i);
1467}
1468
1440/** 1469/**
1441 * Detect the TV connection. 1470 * Detect the TV connection.
1442 * 1471 *
@@ -1473,6 +1502,7 @@ intel_tv_detect(struct drm_connector *connector)
1473 if (type < 0) 1502 if (type < 0)
1474 return connector_status_disconnected; 1503 return connector_status_disconnected;
1475 1504
1505 intel_tv_find_better_format(connector);
1476 return connector_status_connected; 1506 return connector_status_connected;
1477} 1507}
1478 1508
diff --git a/drivers/gpu/drm/mga/mga_dma.c b/drivers/gpu/drm/mga/mga_dma.c
index 6c67a02910c8..3c917fb3a60b 100644
--- a/drivers/gpu/drm/mga/mga_dma.c
+++ b/drivers/gpu/drm/mga/mga_dma.c
@@ -444,7 +444,7 @@ static int mga_do_agp_dma_bootstrap(struct drm_device * dev,
444{ 444{
445 drm_mga_private_t *const dev_priv = 445 drm_mga_private_t *const dev_priv =
446 (drm_mga_private_t *) dev->dev_private; 446 (drm_mga_private_t *) dev->dev_private;
447 unsigned int warp_size = mga_warp_microcode_size(dev_priv); 447 unsigned int warp_size = MGA_WARP_UCODE_SIZE;
448 int err; 448 int err;
449 unsigned offset; 449 unsigned offset;
450 const unsigned secondary_size = dma_bs->secondary_bin_count 450 const unsigned secondary_size = dma_bs->secondary_bin_count
@@ -619,7 +619,7 @@ static int mga_do_pci_dma_bootstrap(struct drm_device * dev,
619{ 619{
620 drm_mga_private_t *const dev_priv = 620 drm_mga_private_t *const dev_priv =
621 (drm_mga_private_t *) dev->dev_private; 621 (drm_mga_private_t *) dev->dev_private;
622 unsigned int warp_size = mga_warp_microcode_size(dev_priv); 622 unsigned int warp_size = MGA_WARP_UCODE_SIZE;
623 unsigned int primary_size; 623 unsigned int primary_size;
624 unsigned int bin_count; 624 unsigned int bin_count;
625 int err; 625 int err;
diff --git a/drivers/gpu/drm/mga/mga_drv.h b/drivers/gpu/drm/mga/mga_drv.h
index 3d264f288237..be6c6b9b0e89 100644
--- a/drivers/gpu/drm/mga/mga_drv.h
+++ b/drivers/gpu/drm/mga/mga_drv.h
@@ -177,7 +177,6 @@ extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv);
177extern int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf); 177extern int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf);
178 178
179 /* mga_warp.c */ 179 /* mga_warp.c */
180extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv);
181extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv); 180extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv);
182extern int mga_warp_init(drm_mga_private_t * dev_priv); 181extern int mga_warp_init(drm_mga_private_t * dev_priv);
183 182
diff --git a/drivers/gpu/drm/mga/mga_ucode.h b/drivers/gpu/drm/mga/mga_ucode.h
deleted file mode 100644
index b611e27470e1..000000000000
--- a/drivers/gpu/drm/mga/mga_ucode.h
+++ /dev/null
@@ -1,11645 +0,0 @@
1/* mga_ucode.h -- Matrox G200/G400 WARP engine microcode -*- linux-c -*-
2 * Created: Thu Jan 11 21:20:43 2001 by gareth@valinux.com
3 *
4 * Copyright 1999 Matrox Graphics Inc.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included
15 * in all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * MATROX GRAPHICS INC., OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
23 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * Kernel-based WARP engine management:
26 * Gareth Hughes <gareth@valinux.com>
27 */
28
29/*
30 * WARP pipes are named according to the functions they perform, where:
31 *
32 * - T stands for computation of texture stage 0
33 * - T2 stands for computation of both texture stage 0 and texture stage 1
34 * - G stands for computation of triangle intensity (Gouraud interpolation)
35 * - Z stands for computation of Z buffer interpolation
36 * - S stands for computation of specular highlight
37 * - A stands for computation of the alpha channel
38 * - F stands for computation of vertex fog interpolation
39 */
40
41static unsigned char warp_g200_tgz[] = {
42
43 0x00, 0x80, 0x00, 0xE8,
44 0x00, 0x80, 0x00, 0xE8,
45
46 0x00, 0x80, 0x00, 0xE8,
47 0x00, 0x80, 0x00, 0xE8,
48
49 0x00, 0x80, 0x00, 0xE8,
50 0x00, 0x80, 0x00, 0xE8,
51
52 0x00, 0x80, 0x00, 0xE8,
53 0x00, 0x80, 0x00, 0xE8,
54
55 0x00, 0x80, 0x00, 0xE8,
56 0x00, 0x80, 0x00, 0xE8,
57
58 0x00, 0x98, 0xA0, 0xE9,
59 0x40, 0x40, 0xD8, 0xEC,
60
61 0xFF, 0x80, 0xC0, 0xE9,
62 0x00, 0x80, 0x00, 0xE8,
63
64 0x1F, 0xD7, 0x18, 0xBD,
65 0x3F, 0xD7, 0x22, 0xBD,
66
67 0x81, 0x04,
68 0x89, 0x04,
69 0x01, 0x04,
70 0x09, 0x04,
71
72 0xC9, 0x41, 0xC0, 0xEC,
73 0x11, 0x04,
74 0x00, 0xE0,
75
76 0x41, 0xCC, 0x41, 0xCD,
77 0x49, 0xCC, 0x49, 0xCD,
78
79 0xD1, 0x41, 0xC0, 0xEC,
80 0x51, 0xCC, 0x51, 0xCD,
81
82 0x80, 0x04,
83 0x10, 0x04,
84 0x08, 0x04,
85 0x00, 0xE0,
86
87 0x00, 0xCC, 0xC0, 0xCD,
88 0xD1, 0x49, 0xC0, 0xEC,
89
90 0x8A, 0x1F, 0x20, 0xE9,
91 0x8B, 0x3F, 0x20, 0xE9,
92
93 0x41, 0x3C, 0x41, 0xAD,
94 0x49, 0x3C, 0x49, 0xAD,
95
96 0x10, 0xCC, 0x10, 0xCD,
97 0x08, 0xCC, 0x08, 0xCD,
98
99 0xB9, 0x41, 0x49, 0xBB,
100 0x1F, 0xF0, 0x41, 0xCD,
101
102 0x51, 0x3C, 0x51, 0xAD,
103 0x00, 0x98, 0x80, 0xE9,
104
105 0x72, 0x80, 0x07, 0xEA,
106 0x24, 0x1F, 0x20, 0xE9,
107
108 0x15, 0x41, 0x49, 0xBD,
109 0x1D, 0x41, 0x51, 0xBD,
110
111 0x2E, 0x41, 0x2A, 0xB8,
112 0x34, 0x53, 0xA0, 0xE8,
113
114 0x15, 0x30,
115 0x1D, 0x30,
116 0x58, 0xE3,
117 0x00, 0xE0,
118
119 0xB5, 0x40, 0x48, 0xBD,
120 0x3D, 0x40, 0x50, 0xBD,
121
122 0x24, 0x43, 0xA0, 0xE8,
123 0x2C, 0x4B, 0xA0, 0xE8,
124
125 0x15, 0x72,
126 0x09, 0xE3,
127 0x00, 0xE0,
128 0x1D, 0x72,
129
130 0x35, 0x30,
131 0xB5, 0x30,
132 0xBD, 0x30,
133 0x3D, 0x30,
134
135 0x9C, 0x97, 0x57, 0x9F,
136 0x00, 0x80, 0x00, 0xE8,
137
138 0x6C, 0x64, 0xC8, 0xEC,
139 0x98, 0xE1,
140 0xB5, 0x05,
141
142 0xBD, 0x05,
143 0x2E, 0x30,
144 0x32, 0xC0, 0xA0, 0xE8,
145
146 0x33, 0xC0, 0xA0, 0xE8,
147 0x74, 0x64, 0xC8, 0xEC,
148
149 0x40, 0x3C, 0x40, 0xAD,
150 0x32, 0x6A,
151 0x2A, 0x30,
152
153 0x20, 0x73,
154 0x33, 0x6A,
155 0x00, 0xE0,
156 0x28, 0x73,
157
158 0x1C, 0x72,
159 0x83, 0xE2,
160 0x60, 0x80, 0x15, 0xEA,
161
162 0xB8, 0x3D, 0x28, 0xDF,
163 0x30, 0x35, 0x20, 0xDF,
164
165 0x40, 0x30,
166 0x00, 0xE0,
167 0xCC, 0xE2,
168 0x64, 0x72,
169
170 0x25, 0x42, 0x52, 0xBF,
171 0x2D, 0x42, 0x4A, 0xBF,
172
173 0x30, 0x2E, 0x30, 0xDF,
174 0x38, 0x2E, 0x38, 0xDF,
175
176 0x18, 0x1D, 0x45, 0xE9,
177 0x1E, 0x15, 0x45, 0xE9,
178
179 0x2B, 0x49, 0x51, 0xBD,
180 0x00, 0xE0,
181 0x1F, 0x73,
182
183 0x38, 0x38, 0x40, 0xAF,
184 0x30, 0x30, 0x40, 0xAF,
185
186 0x24, 0x1F, 0x24, 0xDF,
187 0x1D, 0x32, 0x20, 0xE9,
188
189 0x2C, 0x1F, 0x2C, 0xDF,
190 0x1A, 0x33, 0x20, 0xE9,
191
192 0xB0, 0x10,
193 0x08, 0xE3,
194 0x40, 0x10,
195 0xB8, 0x10,
196
197 0x26, 0xF0, 0x30, 0xCD,
198 0x2F, 0xF0, 0x38, 0xCD,
199
200 0x2B, 0x80, 0x20, 0xE9,
201 0x2A, 0x80, 0x20, 0xE9,
202
203 0xA6, 0x20,
204 0x88, 0xE2,
205 0x00, 0xE0,
206 0xAF, 0x20,
207
208 0x28, 0x2A, 0x26, 0xAF,
209 0x20, 0x2A, 0xC0, 0xAF,
210
211 0x34, 0x1F, 0x34, 0xDF,
212 0x46, 0x24, 0x46, 0xDF,
213
214 0x28, 0x30, 0x80, 0xBF,
215 0x20, 0x38, 0x80, 0xBF,
216
217 0x47, 0x24, 0x47, 0xDF,
218 0x4E, 0x2C, 0x4E, 0xDF,
219
220 0x4F, 0x2C, 0x4F, 0xDF,
221 0x56, 0x34, 0x56, 0xDF,
222
223 0x28, 0x15, 0x28, 0xDF,
224 0x20, 0x1D, 0x20, 0xDF,
225
226 0x57, 0x34, 0x57, 0xDF,
227 0x00, 0xE0,
228 0x1D, 0x05,
229
230 0x04, 0x80, 0x10, 0xEA,
231 0x89, 0xE2,
232 0x2B, 0x30,
233
234 0x3F, 0xC1, 0x1D, 0xBD,
235 0x00, 0x80, 0x00, 0xE8,
236
237 0x00, 0x80, 0x00, 0xE8,
238 0x00, 0x80, 0x00, 0xE8,
239
240 0xA0, 0x68,
241 0xBF, 0x25,
242 0x00, 0x80, 0x00, 0xE8,
243
244 0x20, 0xC0, 0x20, 0xAF,
245 0x28, 0x05,
246 0x97, 0x74,
247
248 0x00, 0xE0,
249 0x2A, 0x10,
250 0x16, 0xC0, 0x20, 0xE9,
251
252 0x04, 0x80, 0x10, 0xEA,
253 0x8C, 0xE2,
254 0x95, 0x05,
255
256 0x28, 0xC1, 0x28, 0xAD,
257 0x1F, 0xC1, 0x15, 0xBD,
258
259 0x00, 0x80, 0x00, 0xE8,
260 0x00, 0x80, 0x00, 0xE8,
261
262 0xA8, 0x67,
263 0x9F, 0x6B,
264 0x00, 0x80, 0x00, 0xE8,
265
266 0x28, 0xC0, 0x28, 0xAD,
267 0x1D, 0x25,
268 0x20, 0x05,
269
270 0x28, 0x32, 0x80, 0xAD,
271 0x40, 0x2A, 0x40, 0xBD,
272
273 0x1C, 0x80, 0x20, 0xE9,
274 0x20, 0x33, 0x20, 0xAD,
275
276 0x20, 0x73,
277 0x00, 0xE0,
278 0xB6, 0x49, 0x51, 0xBB,
279
280 0x26, 0x2F, 0xB0, 0xE8,
281 0x19, 0x20, 0x20, 0xE9,
282
283 0x35, 0x20, 0x35, 0xDF,
284 0x3D, 0x20, 0x3D, 0xDF,
285
286 0x15, 0x20, 0x15, 0xDF,
287 0x1D, 0x20, 0x1D, 0xDF,
288
289 0x26, 0xD0, 0x26, 0xCD,
290 0x29, 0x49, 0x2A, 0xB8,
291
292 0x26, 0x40, 0x80, 0xBD,
293 0x3B, 0x48, 0x50, 0xBD,
294
295 0x3E, 0x54, 0x57, 0x9F,
296 0x00, 0xE0,
297 0x82, 0xE1,
298
299 0x1E, 0xAF, 0x59, 0x9F,
300 0x00, 0x80, 0x00, 0xE8,
301
302 0x26, 0x30,
303 0x29, 0x30,
304 0x48, 0x3C, 0x48, 0xAD,
305
306 0x2B, 0x72,
307 0xC2, 0xE1,
308 0x2C, 0xC0, 0x44, 0xC2,
309
310 0x05, 0x24, 0x34, 0xBF,
311 0x0D, 0x24, 0x2C, 0xBF,
312
313 0x2D, 0x46, 0x4E, 0xBF,
314 0x25, 0x46, 0x56, 0xBF,
315
316 0x20, 0x1D, 0x6F, 0x8F,
317 0x32, 0x3E, 0x5F, 0xE9,
318
319 0x3E, 0x50, 0x56, 0x9F,
320 0x00, 0xE0,
321 0x3B, 0x30,
322
323 0x1E, 0x8F, 0x51, 0x9F,
324 0x33, 0x1E, 0x5F, 0xE9,
325
326 0x05, 0x44, 0x54, 0xB2,
327 0x0D, 0x44, 0x4C, 0xB2,
328
329 0x19, 0xC0, 0xB0, 0xE8,
330 0x34, 0xC0, 0x44, 0xC4,
331
332 0x33, 0x73,
333 0x00, 0xE0,
334 0x3E, 0x62, 0x57, 0x9F,
335
336 0x1E, 0xAF, 0x59, 0x9F,
337 0x00, 0xE0,
338 0x0D, 0x20,
339
340 0x84, 0x3E, 0x58, 0xE9,
341 0x28, 0x1D, 0x6F, 0x8F,
342
343 0x05, 0x20,
344 0x00, 0xE0,
345 0x85, 0x1E, 0x58, 0xE9,
346
347 0x9B, 0x3B, 0x33, 0xDF,
348 0x20, 0x20, 0x42, 0xAF,
349
350 0x30, 0x42, 0x56, 0x9F,
351 0x80, 0x3E, 0x57, 0xE9,
352
353 0x3F, 0x8F, 0x51, 0x9F,
354 0x30, 0x80, 0x5F, 0xE9,
355
356 0x28, 0x28, 0x24, 0xAF,
357 0x81, 0x1E, 0x57, 0xE9,
358
359 0x05, 0x47, 0x57, 0xBF,
360 0x0D, 0x47, 0x4F, 0xBF,
361
362 0x88, 0x80, 0x58, 0xE9,
363 0x1B, 0x29, 0x1B, 0xDF,
364
365 0x30, 0x1D, 0x6F, 0x8F,
366 0x3A, 0x30, 0x4F, 0xE9,
367
368 0x1C, 0x30, 0x26, 0xDF,
369 0x09, 0xE3,
370 0x3B, 0x05,
371
372 0x3E, 0x50, 0x56, 0x9F,
373 0x3B, 0x3F, 0x4F, 0xE9,
374
375 0x1E, 0x8F, 0x51, 0x9F,
376 0x00, 0xE0,
377 0xAC, 0x20,
378
379 0x2D, 0x44, 0x4C, 0xB4,
380 0x2C, 0x1C, 0xC0, 0xAF,
381
382 0x25, 0x44, 0x54, 0xB4,
383 0x00, 0xE0,
384 0xC8, 0x30,
385
386 0x30, 0x46, 0x30, 0xAF,
387 0x1B, 0x1B, 0x48, 0xAF,
388
389 0x00, 0xE0,
390 0x25, 0x20,
391 0x38, 0x2C, 0x4F, 0xE9,
392
393 0x86, 0x80, 0x57, 0xE9,
394 0x38, 0x1D, 0x6F, 0x8F,
395
396 0x28, 0x74,
397 0x00, 0xE0,
398 0x0D, 0x44, 0x4C, 0xB0,
399
400 0x05, 0x44, 0x54, 0xB0,
401 0x2D, 0x20,
402 0x9B, 0x10,
403
404 0x82, 0x3E, 0x57, 0xE9,
405 0x32, 0xF0, 0x1B, 0xCD,
406
407 0x1E, 0xBD, 0x59, 0x9F,
408 0x83, 0x1E, 0x57, 0xE9,
409
410 0x38, 0x47, 0x38, 0xAF,
411 0x34, 0x20,
412 0x2A, 0x30,
413
414 0x00, 0xE0,
415 0x0D, 0x20,
416 0x32, 0x20,
417 0x05, 0x20,
418
419 0x87, 0x80, 0x57, 0xE9,
420 0x1F, 0x54, 0x57, 0x9F,
421
422 0x17, 0x42, 0x56, 0x9F,
423 0x00, 0xE0,
424 0x3B, 0x6A,
425
426 0x3F, 0x8F, 0x51, 0x9F,
427 0x37, 0x1E, 0x4F, 0xE9,
428
429 0x37, 0x32, 0x2A, 0xAF,
430 0x00, 0xE0,
431 0x32, 0x00,
432
433 0x00, 0x80, 0x00, 0xE8,
434 0x27, 0xC0, 0x44, 0xC0,
435
436 0x36, 0x1F, 0x4F, 0xE9,
437 0x1F, 0x1F, 0x26, 0xDF,
438
439 0x37, 0x1B, 0x37, 0xBF,
440 0x17, 0x26, 0x17, 0xDF,
441
442 0x3E, 0x17, 0x4F, 0xE9,
443 0x3F, 0x3F, 0x4F, 0xE9,
444
445 0x34, 0x1F, 0x34, 0xAF,
446 0x2B, 0x05,
447 0xA7, 0x20,
448
449 0x33, 0x2B, 0x37, 0xDF,
450 0x27, 0x17, 0xC0, 0xAF,
451
452 0x34, 0x80, 0x4F, 0xE9,
453 0x00, 0x80, 0x00, 0xE8,
454
455 0x03, 0x80, 0x0A, 0xEA,
456 0x17, 0xC1, 0x2B, 0xBD,
457
458 0x00, 0x80, 0x00, 0xE8,
459 0x00, 0x80, 0x00, 0xE8,
460
461 0xB3, 0x68,
462 0x97, 0x25,
463 0x00, 0x80, 0x00, 0xE8,
464
465 0x33, 0xC0, 0x33, 0xAF,
466 0x3C, 0x27, 0x4F, 0xE9,
467
468 0x57, 0x39, 0x20, 0xE9,
469 0x28, 0x19, 0x60, 0xEC,
470
471 0x2B, 0x32, 0x20, 0xE9,
472 0x1D, 0x3B, 0x20, 0xE9,
473
474 0xB3, 0x05,
475 0x00, 0xE0,
476 0x16, 0x28, 0x20, 0xE9,
477
478 0x23, 0x3B, 0x33, 0xAD,
479 0x1E, 0x2B, 0x20, 0xE9,
480
481 0x1C, 0x80, 0x20, 0xE9,
482 0x57, 0x36, 0x20, 0xE9,
483
484 0x00, 0x80, 0xA0, 0xE9,
485 0x40, 0x40, 0xD8, 0xEC,
486
487 0xFF, 0x80, 0xC0, 0xE9,
488 0x90, 0xE2,
489 0x00, 0xE0,
490
491 0x85, 0xFF, 0x20, 0xEA,
492 0x19, 0xC8, 0xC1, 0xCD,
493
494 0x1F, 0xD7, 0x18, 0xBD,
495 0x3F, 0xD7, 0x22, 0xBD,
496
497 0x9F, 0x41, 0x49, 0xBD,
498 0x00, 0x80, 0x00, 0xE8,
499
500 0x25, 0x41, 0x49, 0xBD,
501 0x2D, 0x41, 0x51, 0xBD,
502
503 0x0D, 0x80, 0x07, 0xEA,
504 0x00, 0x80, 0x00, 0xE8,
505
506 0x35, 0x40, 0x48, 0xBD,
507 0x3D, 0x40, 0x50, 0xBD,
508
509 0x00, 0x80, 0x00, 0xE8,
510 0x25, 0x30,
511 0x2D, 0x30,
512
513 0x35, 0x30,
514 0xB5, 0x30,
515 0xBD, 0x30,
516 0x3D, 0x30,
517
518 0x9C, 0xA7, 0x5B, 0x9F,
519 0x00, 0x80, 0x00, 0xE8,
520
521 0x00, 0x80, 0x00, 0xE8,
522 0x00, 0x80, 0x00, 0xE8,
523
524 0x00, 0x80, 0x00, 0xE8,
525 0x00, 0x80, 0x00, 0xE8,
526
527 0x00, 0x80, 0x00, 0xE8,
528 0x00, 0x80, 0x00, 0xE8,
529
530 0x00, 0x80, 0x00, 0xE8,
531 0x00, 0x80, 0x00, 0xE8,
532
533 0x84, 0xFF, 0x0A, 0xEA,
534 0x00, 0x80, 0x00, 0xE8,
535
536 0xC9, 0x41, 0xC8, 0xEC,
537 0x42, 0xE1,
538 0x00, 0xE0,
539
540 0x82, 0xFF, 0x20, 0xEA,
541 0x00, 0x80, 0x00, 0xE8,
542
543 0x00, 0x80, 0x00, 0xE8,
544 0x00, 0x80, 0x00, 0xE8,
545
546 0xC8, 0x40, 0xC0, 0xEC,
547 0x00, 0x80, 0x00, 0xE8,
548
549 0x7F, 0xFF, 0x20, 0xEA,
550 0x00, 0x80, 0x00, 0xE8,
551
552 0x00, 0x80, 0x00, 0xE8,
553 0x00, 0x80, 0x00, 0xE8,
554
555};
556
557static unsigned char warp_g200_tgza[] = {
558
559 0x00, 0x98, 0xA0, 0xE9,
560 0x40, 0x40, 0xD8, 0xEC,
561
562 0xFF, 0x80, 0xC0, 0xE9,
563 0x00, 0x80, 0x00, 0xE8,
564
565 0x1F, 0xD7, 0x18, 0xBD,
566 0x3F, 0xD7, 0x22, 0xBD,
567
568 0x81, 0x04,
569 0x89, 0x04,
570 0x01, 0x04,
571 0x09, 0x04,
572
573 0xC9, 0x41, 0xC0, 0xEC,
574 0x11, 0x04,
575 0x00, 0xE0,
576
577 0x41, 0xCC, 0x41, 0xCD,
578 0x49, 0xCC, 0x49, 0xCD,
579
580 0xD1, 0x41, 0xC0, 0xEC,
581 0x51, 0xCC, 0x51, 0xCD,
582
583 0x80, 0x04,
584 0x10, 0x04,
585 0x08, 0x04,
586 0x00, 0xE0,
587
588 0x00, 0xCC, 0xC0, 0xCD,
589 0xD1, 0x49, 0xC0, 0xEC,
590
591 0x8A, 0x1F, 0x20, 0xE9,
592 0x8B, 0x3F, 0x20, 0xE9,
593
594 0x41, 0x3C, 0x41, 0xAD,
595 0x49, 0x3C, 0x49, 0xAD,
596
597 0x10, 0xCC, 0x10, 0xCD,
598 0x08, 0xCC, 0x08, 0xCD,
599
600 0xB9, 0x41, 0x49, 0xBB,
601 0x1F, 0xF0, 0x41, 0xCD,
602
603 0x51, 0x3C, 0x51, 0xAD,
604 0x00, 0x98, 0x80, 0xE9,
605
606 0x7D, 0x80, 0x07, 0xEA,
607 0x24, 0x1F, 0x20, 0xE9,
608
609 0x15, 0x41, 0x49, 0xBD,
610 0x1D, 0x41, 0x51, 0xBD,
611
612 0x2E, 0x41, 0x2A, 0xB8,
613 0x34, 0x53, 0xA0, 0xE8,
614
615 0x15, 0x30,
616 0x1D, 0x30,
617 0x58, 0xE3,
618 0x00, 0xE0,
619
620 0xB5, 0x40, 0x48, 0xBD,
621 0x3D, 0x40, 0x50, 0xBD,
622
623 0x24, 0x43, 0xA0, 0xE8,
624 0x2C, 0x4B, 0xA0, 0xE8,
625
626 0x15, 0x72,
627 0x09, 0xE3,
628 0x00, 0xE0,
629 0x1D, 0x72,
630
631 0x35, 0x30,
632 0xB5, 0x30,
633 0xBD, 0x30,
634 0x3D, 0x30,
635
636 0x9C, 0x97, 0x57, 0x9F,
637 0x00, 0x80, 0x00, 0xE8,
638
639 0x6C, 0x64, 0xC8, 0xEC,
640 0x98, 0xE1,
641 0xB5, 0x05,
642
643 0xBD, 0x05,
644 0x2E, 0x30,
645 0x32, 0xC0, 0xA0, 0xE8,
646
647 0x33, 0xC0, 0xA0, 0xE8,
648 0x74, 0x64, 0xC8, 0xEC,
649
650 0x40, 0x3C, 0x40, 0xAD,
651 0x32, 0x6A,
652 0x2A, 0x30,
653
654 0x20, 0x73,
655 0x33, 0x6A,
656 0x00, 0xE0,
657 0x28, 0x73,
658
659 0x1C, 0x72,
660 0x83, 0xE2,
661 0x6B, 0x80, 0x15, 0xEA,
662
663 0xB8, 0x3D, 0x28, 0xDF,
664 0x30, 0x35, 0x20, 0xDF,
665
666 0x40, 0x30,
667 0x00, 0xE0,
668 0xCC, 0xE2,
669 0x64, 0x72,
670
671 0x25, 0x42, 0x52, 0xBF,
672 0x2D, 0x42, 0x4A, 0xBF,
673
674 0x30, 0x2E, 0x30, 0xDF,
675 0x38, 0x2E, 0x38, 0xDF,
676
677 0x18, 0x1D, 0x45, 0xE9,
678 0x1E, 0x15, 0x45, 0xE9,
679
680 0x2B, 0x49, 0x51, 0xBD,
681 0x00, 0xE0,
682 0x1F, 0x73,
683
684 0x38, 0x38, 0x40, 0xAF,
685 0x30, 0x30, 0x40, 0xAF,
686
687 0x24, 0x1F, 0x24, 0xDF,
688 0x1D, 0x32, 0x20, 0xE9,
689
690 0x2C, 0x1F, 0x2C, 0xDF,
691 0x1A, 0x33, 0x20, 0xE9,
692
693 0xB0, 0x10,
694 0x08, 0xE3,
695 0x40, 0x10,
696 0xB8, 0x10,
697
698 0x26, 0xF0, 0x30, 0xCD,
699 0x2F, 0xF0, 0x38, 0xCD,
700
701 0x2B, 0x80, 0x20, 0xE9,
702 0x2A, 0x80, 0x20, 0xE9,
703
704 0xA6, 0x20,
705 0x88, 0xE2,
706 0x00, 0xE0,
707 0xAF, 0x20,
708
709 0x28, 0x2A, 0x26, 0xAF,
710 0x20, 0x2A, 0xC0, 0xAF,
711
712 0x34, 0x1F, 0x34, 0xDF,
713 0x46, 0x24, 0x46, 0xDF,
714
715 0x28, 0x30, 0x80, 0xBF,
716 0x20, 0x38, 0x80, 0xBF,
717
718 0x47, 0x24, 0x47, 0xDF,
719 0x4E, 0x2C, 0x4E, 0xDF,
720
721 0x4F, 0x2C, 0x4F, 0xDF,
722 0x56, 0x34, 0x56, 0xDF,
723
724 0x28, 0x15, 0x28, 0xDF,
725 0x20, 0x1D, 0x20, 0xDF,
726
727 0x57, 0x34, 0x57, 0xDF,
728 0x00, 0xE0,
729 0x1D, 0x05,
730
731 0x04, 0x80, 0x10, 0xEA,
732 0x89, 0xE2,
733 0x2B, 0x30,
734
735 0x3F, 0xC1, 0x1D, 0xBD,
736 0x00, 0x80, 0x00, 0xE8,
737
738 0x00, 0x80, 0x00, 0xE8,
739 0x00, 0x80, 0x00, 0xE8,
740
741 0xA0, 0x68,
742 0xBF, 0x25,
743 0x00, 0x80, 0x00, 0xE8,
744
745 0x20, 0xC0, 0x20, 0xAF,
746 0x28, 0x05,
747 0x97, 0x74,
748
749 0x00, 0xE0,
750 0x2A, 0x10,
751 0x16, 0xC0, 0x20, 0xE9,
752
753 0x04, 0x80, 0x10, 0xEA,
754 0x8C, 0xE2,
755 0x95, 0x05,
756
757 0x28, 0xC1, 0x28, 0xAD,
758 0x1F, 0xC1, 0x15, 0xBD,
759
760 0x00, 0x80, 0x00, 0xE8,
761 0x00, 0x80, 0x00, 0xE8,
762
763 0xA8, 0x67,
764 0x9F, 0x6B,
765 0x00, 0x80, 0x00, 0xE8,
766
767 0x28, 0xC0, 0x28, 0xAD,
768 0x1D, 0x25,
769 0x20, 0x05,
770
771 0x28, 0x32, 0x80, 0xAD,
772 0x40, 0x2A, 0x40, 0xBD,
773
774 0x1C, 0x80, 0x20, 0xE9,
775 0x20, 0x33, 0x20, 0xAD,
776
777 0x20, 0x73,
778 0x00, 0xE0,
779 0xB6, 0x49, 0x51, 0xBB,
780
781 0x26, 0x2F, 0xB0, 0xE8,
782 0x19, 0x20, 0x20, 0xE9,
783
784 0x35, 0x20, 0x35, 0xDF,
785 0x3D, 0x20, 0x3D, 0xDF,
786
787 0x15, 0x20, 0x15, 0xDF,
788 0x1D, 0x20, 0x1D, 0xDF,
789
790 0x26, 0xD0, 0x26, 0xCD,
791 0x29, 0x49, 0x2A, 0xB8,
792
793 0x26, 0x40, 0x80, 0xBD,
794 0x3B, 0x48, 0x50, 0xBD,
795
796 0x3E, 0x54, 0x57, 0x9F,
797 0x00, 0xE0,
798 0x82, 0xE1,
799
800 0x1E, 0xAF, 0x59, 0x9F,
801 0x00, 0x80, 0x00, 0xE8,
802
803 0x26, 0x30,
804 0x29, 0x30,
805 0x48, 0x3C, 0x48, 0xAD,
806
807 0x2B, 0x72,
808 0xC2, 0xE1,
809 0x2C, 0xC0, 0x44, 0xC2,
810
811 0x05, 0x24, 0x34, 0xBF,
812 0x0D, 0x24, 0x2C, 0xBF,
813
814 0x2D, 0x46, 0x4E, 0xBF,
815 0x25, 0x46, 0x56, 0xBF,
816
817 0x20, 0x1D, 0x6F, 0x8F,
818 0x32, 0x3E, 0x5F, 0xE9,
819
820 0x3E, 0x50, 0x56, 0x9F,
821 0x00, 0xE0,
822 0x3B, 0x30,
823
824 0x1E, 0x8F, 0x51, 0x9F,
825 0x33, 0x1E, 0x5F, 0xE9,
826
827 0x05, 0x44, 0x54, 0xB2,
828 0x0D, 0x44, 0x4C, 0xB2,
829
830 0x19, 0xC0, 0xB0, 0xE8,
831 0x34, 0xC0, 0x44, 0xC4,
832
833 0x33, 0x73,
834 0x00, 0xE0,
835 0x3E, 0x62, 0x57, 0x9F,
836
837 0x1E, 0xAF, 0x59, 0x9F,
838 0x00, 0xE0,
839 0x0D, 0x20,
840
841 0x84, 0x3E, 0x58, 0xE9,
842 0x28, 0x1D, 0x6F, 0x8F,
843
844 0x05, 0x20,
845 0x00, 0xE0,
846 0x85, 0x1E, 0x58, 0xE9,
847
848 0x9B, 0x3B, 0x33, 0xDF,
849 0x20, 0x20, 0x42, 0xAF,
850
851 0x30, 0x42, 0x56, 0x9F,
852 0x80, 0x3E, 0x57, 0xE9,
853
854 0x3F, 0x8F, 0x51, 0x9F,
855 0x30, 0x80, 0x5F, 0xE9,
856
857 0x28, 0x28, 0x24, 0xAF,
858 0x81, 0x1E, 0x57, 0xE9,
859
860 0x05, 0x47, 0x57, 0xBF,
861 0x0D, 0x47, 0x4F, 0xBF,
862
863 0x88, 0x80, 0x58, 0xE9,
864 0x1B, 0x29, 0x1B, 0xDF,
865
866 0x30, 0x1D, 0x6F, 0x8F,
867 0x3A, 0x30, 0x4F, 0xE9,
868
869 0x1C, 0x30, 0x26, 0xDF,
870 0x09, 0xE3,
871 0x3B, 0x05,
872
873 0x3E, 0x50, 0x56, 0x9F,
874 0x3B, 0x3F, 0x4F, 0xE9,
875
876 0x1E, 0x8F, 0x51, 0x9F,
877 0x00, 0xE0,
878 0xAC, 0x20,
879
880 0x2D, 0x44, 0x4C, 0xB4,
881 0x2C, 0x1C, 0xC0, 0xAF,
882
883 0x25, 0x44, 0x54, 0xB4,
884 0x00, 0xE0,
885 0xC8, 0x30,
886
887 0x30, 0x46, 0x30, 0xAF,
888 0x1B, 0x1B, 0x48, 0xAF,
889
890 0x00, 0xE0,
891 0x25, 0x20,
892 0x38, 0x2C, 0x4F, 0xE9,
893
894 0x86, 0x80, 0x57, 0xE9,
895 0x38, 0x1D, 0x6F, 0x8F,
896
897 0x28, 0x74,
898 0x00, 0xE0,
899 0x0D, 0x44, 0x4C, 0xB0,
900
901 0x05, 0x44, 0x54, 0xB0,
902 0x2D, 0x20,
903 0x9B, 0x10,
904
905 0x82, 0x3E, 0x57, 0xE9,
906 0x32, 0xF0, 0x1B, 0xCD,
907
908 0x1E, 0xBD, 0x59, 0x9F,
909 0x83, 0x1E, 0x57, 0xE9,
910
911 0x38, 0x47, 0x38, 0xAF,
912 0x34, 0x20,
913 0x2A, 0x30,
914
915 0x00, 0xE0,
916 0x0D, 0x20,
917 0x32, 0x20,
918 0x05, 0x20,
919
920 0x87, 0x80, 0x57, 0xE9,
921 0x1F, 0x54, 0x57, 0x9F,
922
923 0x17, 0x42, 0x56, 0x9F,
924 0x00, 0xE0,
925 0x3B, 0x6A,
926
927 0x3F, 0x8F, 0x51, 0x9F,
928 0x37, 0x1E, 0x4F, 0xE9,
929
930 0x37, 0x32, 0x2A, 0xAF,
931 0x00, 0xE0,
932 0x32, 0x00,
933
934 0x00, 0x80, 0x00, 0xE8,
935 0x27, 0xC0, 0x44, 0xC0,
936
937 0x36, 0x1F, 0x4F, 0xE9,
938 0x1F, 0x1F, 0x26, 0xDF,
939
940 0x37, 0x1B, 0x37, 0xBF,
941 0x17, 0x26, 0x17, 0xDF,
942
943 0x3E, 0x17, 0x4F, 0xE9,
944 0x3F, 0x3F, 0x4F, 0xE9,
945
946 0x34, 0x1F, 0x34, 0xAF,
947 0x2B, 0x05,
948 0xA7, 0x20,
949
950 0x33, 0x2B, 0x37, 0xDF,
951 0x27, 0x17, 0xC0, 0xAF,
952
953 0x34, 0x80, 0x4F, 0xE9,
954 0x00, 0x80, 0x00, 0xE8,
955
956 0x2D, 0x44, 0x4C, 0xB6,
957 0x25, 0x44, 0x54, 0xB6,
958
959 0x03, 0x80, 0x2A, 0xEA,
960 0x17, 0xC1, 0x2B, 0xBD,
961
962 0x2D, 0x20,
963 0x25, 0x20,
964 0x07, 0xC0, 0x44, 0xC6,
965
966 0xB3, 0x68,
967 0x97, 0x25,
968 0x00, 0x80, 0x00, 0xE8,
969
970 0x33, 0xC0, 0x33, 0xAF,
971 0x3C, 0x27, 0x4F, 0xE9,
972
973 0x1F, 0x62, 0x57, 0x9F,
974 0x00, 0x80, 0x00, 0xE8,
975
976 0x3F, 0x3D, 0x5D, 0x9F,
977 0x00, 0xE0,
978 0x07, 0x20,
979
980 0x00, 0x80, 0x00, 0xE8,
981 0x28, 0x19, 0x60, 0xEC,
982
983 0xB3, 0x05,
984 0x00, 0xE0,
985 0x00, 0x80, 0x00, 0xE8,
986
987 0x23, 0x3B, 0x33, 0xAD,
988 0x00, 0x80, 0x00, 0xE8,
989
990 0x1F, 0x26, 0x1F, 0xDF,
991 0x9D, 0x1F, 0x4F, 0xE9,
992
993 0x00, 0x80, 0x00, 0xE8,
994 0x00, 0x80, 0x00, 0xE8,
995
996 0x00, 0x80, 0x00, 0xE8,
997 0x9E, 0x3F, 0x4F, 0xE9,
998
999 0x07, 0x07, 0x1F, 0xAF,
1000 0x00, 0x80, 0x00, 0xE8,
1001
1002 0x00, 0x80, 0x00, 0xE8,
1003 0x00, 0x80, 0x00, 0xE8,
1004
1005 0x9C, 0x80, 0x4F, 0xE9,
1006 0x00, 0x80, 0x00, 0xE8,
1007
1008 0x00, 0x80, 0x00, 0xE8,
1009 0x57, 0x39, 0x20, 0xE9,
1010
1011 0x16, 0x28, 0x20, 0xE9,
1012 0x1D, 0x3B, 0x20, 0xE9,
1013
1014 0x1E, 0x2B, 0x20, 0xE9,
1015 0x2B, 0x32, 0x20, 0xE9,
1016
1017 0x1C, 0x23, 0x20, 0xE9,
1018 0x57, 0x36, 0x20, 0xE9,
1019
1020 0x00, 0x80, 0xA0, 0xE9,
1021 0x40, 0x40, 0xD8, 0xEC,
1022
1023 0xFF, 0x80, 0xC0, 0xE9,
1024 0x90, 0xE2,
1025 0x00, 0xE0,
1026
1027 0x7A, 0xFF, 0x20, 0xEA,
1028 0x19, 0xC8, 0xC1, 0xCD,
1029
1030 0x1F, 0xD7, 0x18, 0xBD,
1031 0x3F, 0xD7, 0x22, 0xBD,
1032
1033 0x9F, 0x41, 0x49, 0xBD,
1034 0x00, 0x80, 0x00, 0xE8,
1035
1036 0x25, 0x41, 0x49, 0xBD,
1037 0x2D, 0x41, 0x51, 0xBD,
1038
1039 0x0D, 0x80, 0x07, 0xEA,
1040 0x00, 0x80, 0x00, 0xE8,
1041
1042 0x35, 0x40, 0x48, 0xBD,
1043 0x3D, 0x40, 0x50, 0xBD,
1044
1045 0x00, 0x80, 0x00, 0xE8,
1046 0x25, 0x30,
1047 0x2D, 0x30,
1048
1049 0x35, 0x30,
1050 0xB5, 0x30,
1051 0xBD, 0x30,
1052 0x3D, 0x30,
1053
1054 0x9C, 0xA7, 0x5B, 0x9F,
1055 0x00, 0x80, 0x00, 0xE8,
1056
1057 0x00, 0x80, 0x00, 0xE8,
1058 0x00, 0x80, 0x00, 0xE8,
1059
1060 0x00, 0x80, 0x00, 0xE8,
1061 0x00, 0x80, 0x00, 0xE8,
1062
1063 0x00, 0x80, 0x00, 0xE8,
1064 0x00, 0x80, 0x00, 0xE8,
1065
1066 0x00, 0x80, 0x00, 0xE8,
1067 0x00, 0x80, 0x00, 0xE8,
1068
1069 0x79, 0xFF, 0x0A, 0xEA,
1070 0x00, 0x80, 0x00, 0xE8,
1071
1072 0xC9, 0x41, 0xC8, 0xEC,
1073 0x42, 0xE1,
1074 0x00, 0xE0,
1075
1076 0x77, 0xFF, 0x20, 0xEA,
1077 0x00, 0x80, 0x00, 0xE8,
1078
1079 0x00, 0x80, 0x00, 0xE8,
1080 0x00, 0x80, 0x00, 0xE8,
1081
1082 0xC8, 0x40, 0xC0, 0xEC,
1083 0x00, 0x80, 0x00, 0xE8,
1084
1085 0x74, 0xFF, 0x20, 0xEA,
1086 0x00, 0x80, 0x00, 0xE8,
1087
1088 0x00, 0x80, 0x00, 0xE8,
1089 0x00, 0x80, 0x00, 0xE8,
1090
1091};
1092
1093static unsigned char warp_g200_tgzaf[] = {
1094
1095 0x00, 0x80, 0x00, 0xE8,
1096 0x00, 0x80, 0x00, 0xE8,
1097
1098 0x00, 0x80, 0x00, 0xE8,
1099 0x00, 0x80, 0x00, 0xE8,
1100
1101 0x00, 0x80, 0x00, 0xE8,
1102 0x00, 0x80, 0x00, 0xE8,
1103
1104 0x00, 0x80, 0x00, 0xE8,
1105 0x00, 0x80, 0x00, 0xE8,
1106
1107 0x00, 0x80, 0x00, 0xE8,
1108 0x00, 0x80, 0x00, 0xE8,
1109
1110 0x00, 0x80, 0x00, 0xE8,
1111 0x00, 0x80, 0x00, 0xE8,
1112
1113 0x00, 0x80, 0x00, 0xE8,
1114 0x00, 0x80, 0x00, 0xE8,
1115
1116 0x00, 0x80, 0x00, 0xE8,
1117 0x00, 0x80, 0x00, 0xE8,
1118
1119 0x00, 0x80, 0x00, 0xE8,
1120 0x00, 0x80, 0x00, 0xE8,
1121
1122 0x00, 0x80, 0x00, 0xE8,
1123 0x00, 0x80, 0x00, 0xE8,
1124
1125 0x00, 0x98, 0xA0, 0xE9,
1126 0x40, 0x40, 0xD8, 0xEC,
1127
1128 0xFF, 0x80, 0xC0, 0xE9,
1129 0x00, 0x80, 0x00, 0xE8,
1130
1131 0x1F, 0xD7, 0x18, 0xBD,
1132 0x3F, 0xD7, 0x22, 0xBD,
1133
1134 0x81, 0x04,
1135 0x89, 0x04,
1136 0x01, 0x04,
1137 0x09, 0x04,
1138
1139 0xC9, 0x41, 0xC0, 0xEC,
1140 0x11, 0x04,
1141 0x00, 0xE0,
1142
1143 0x41, 0xCC, 0x41, 0xCD,
1144 0x49, 0xCC, 0x49, 0xCD,
1145
1146 0xD1, 0x41, 0xC0, 0xEC,
1147 0x51, 0xCC, 0x51, 0xCD,
1148
1149 0x80, 0x04,
1150 0x10, 0x04,
1151 0x08, 0x04,
1152 0x00, 0xE0,
1153
1154 0x00, 0xCC, 0xC0, 0xCD,
1155 0xD1, 0x49, 0xC0, 0xEC,
1156
1157 0x8A, 0x1F, 0x20, 0xE9,
1158 0x8B, 0x3F, 0x20, 0xE9,
1159
1160 0x41, 0x3C, 0x41, 0xAD,
1161 0x49, 0x3C, 0x49, 0xAD,
1162
1163 0x10, 0xCC, 0x10, 0xCD,
1164 0x08, 0xCC, 0x08, 0xCD,
1165
1166 0xB9, 0x41, 0x49, 0xBB,
1167 0x1F, 0xF0, 0x41, 0xCD,
1168
1169 0x51, 0x3C, 0x51, 0xAD,
1170 0x00, 0x98, 0x80, 0xE9,
1171
1172 0x83, 0x80, 0x07, 0xEA,
1173 0x24, 0x1F, 0x20, 0xE9,
1174
1175 0x21, 0x45, 0x80, 0xE8,
1176 0x1A, 0x4D, 0x80, 0xE8,
1177
1178 0x31, 0x55, 0x80, 0xE8,
1179 0x00, 0x80, 0x00, 0xE8,
1180
1181 0x15, 0x41, 0x49, 0xBD,
1182 0x1D, 0x41, 0x51, 0xBD,
1183
1184 0x2E, 0x41, 0x2A, 0xB8,
1185 0x34, 0x53, 0xA0, 0xE8,
1186
1187 0x15, 0x30,
1188 0x1D, 0x30,
1189 0x58, 0xE3,
1190 0x00, 0xE0,
1191
1192 0xB5, 0x40, 0x48, 0xBD,
1193 0x3D, 0x40, 0x50, 0xBD,
1194
1195 0x24, 0x43, 0xA0, 0xE8,
1196 0x2C, 0x4B, 0xA0, 0xE8,
1197
1198 0x15, 0x72,
1199 0x09, 0xE3,
1200 0x00, 0xE0,
1201 0x1D, 0x72,
1202
1203 0x35, 0x30,
1204 0xB5, 0x30,
1205 0xBD, 0x30,
1206 0x3D, 0x30,
1207
1208 0x9C, 0x97, 0x57, 0x9F,
1209 0x00, 0x80, 0x00, 0xE8,
1210
1211 0x6C, 0x64, 0xC8, 0xEC,
1212 0x98, 0xE1,
1213 0xB5, 0x05,
1214
1215 0xBD, 0x05,
1216 0x2E, 0x30,
1217 0x32, 0xC0, 0xA0, 0xE8,
1218
1219 0x33, 0xC0, 0xA0, 0xE8,
1220 0x74, 0x64, 0xC8, 0xEC,
1221
1222 0x40, 0x3C, 0x40, 0xAD,
1223 0x32, 0x6A,
1224 0x2A, 0x30,
1225
1226 0x20, 0x73,
1227 0x33, 0x6A,
1228 0x00, 0xE0,
1229 0x28, 0x73,
1230
1231 0x1C, 0x72,
1232 0x83, 0xE2,
1233 0x6F, 0x80, 0x15, 0xEA,
1234
1235 0xB8, 0x3D, 0x28, 0xDF,
1236 0x30, 0x35, 0x20, 0xDF,
1237
1238 0x40, 0x30,
1239 0x00, 0xE0,
1240 0xCC, 0xE2,
1241 0x64, 0x72,
1242
1243 0x25, 0x42, 0x52, 0xBF,
1244 0x2D, 0x42, 0x4A, 0xBF,
1245
1246 0x30, 0x2E, 0x30, 0xDF,
1247 0x38, 0x2E, 0x38, 0xDF,
1248
1249 0x18, 0x1D, 0x45, 0xE9,
1250 0x1E, 0x15, 0x45, 0xE9,
1251
1252 0x2B, 0x49, 0x51, 0xBD,
1253 0x00, 0xE0,
1254 0x1F, 0x73,
1255
1256 0x38, 0x38, 0x40, 0xAF,
1257 0x30, 0x30, 0x40, 0xAF,
1258
1259 0x24, 0x1F, 0x24, 0xDF,
1260 0x1D, 0x32, 0x20, 0xE9,
1261
1262 0x2C, 0x1F, 0x2C, 0xDF,
1263 0x1A, 0x33, 0x20, 0xE9,
1264
1265 0xB0, 0x10,
1266 0x08, 0xE3,
1267 0x40, 0x10,
1268 0xB8, 0x10,
1269
1270 0x26, 0xF0, 0x30, 0xCD,
1271 0x2F, 0xF0, 0x38, 0xCD,
1272
1273 0x2B, 0x80, 0x20, 0xE9,
1274 0x2A, 0x80, 0x20, 0xE9,
1275
1276 0xA6, 0x20,
1277 0x88, 0xE2,
1278 0x00, 0xE0,
1279 0xAF, 0x20,
1280
1281 0x28, 0x2A, 0x26, 0xAF,
1282 0x20, 0x2A, 0xC0, 0xAF,
1283
1284 0x34, 0x1F, 0x34, 0xDF,
1285 0x46, 0x24, 0x46, 0xDF,
1286
1287 0x28, 0x30, 0x80, 0xBF,
1288 0x20, 0x38, 0x80, 0xBF,
1289
1290 0x47, 0x24, 0x47, 0xDF,
1291 0x4E, 0x2C, 0x4E, 0xDF,
1292
1293 0x4F, 0x2C, 0x4F, 0xDF,
1294 0x56, 0x34, 0x56, 0xDF,
1295
1296 0x28, 0x15, 0x28, 0xDF,
1297 0x20, 0x1D, 0x20, 0xDF,
1298
1299 0x57, 0x34, 0x57, 0xDF,
1300 0x00, 0xE0,
1301 0x1D, 0x05,
1302
1303 0x04, 0x80, 0x10, 0xEA,
1304 0x89, 0xE2,
1305 0x2B, 0x30,
1306
1307 0x3F, 0xC1, 0x1D, 0xBD,
1308 0x00, 0x80, 0x00, 0xE8,
1309
1310 0x00, 0x80, 0x00, 0xE8,
1311 0x00, 0x80, 0x00, 0xE8,
1312
1313 0xA0, 0x68,
1314 0xBF, 0x25,
1315 0x00, 0x80, 0x00, 0xE8,
1316
1317 0x20, 0xC0, 0x20, 0xAF,
1318 0x28, 0x05,
1319 0x97, 0x74,
1320
1321 0x00, 0xE0,
1322 0x2A, 0x10,
1323 0x16, 0xC0, 0x20, 0xE9,
1324
1325 0x04, 0x80, 0x10, 0xEA,
1326 0x8C, 0xE2,
1327 0x95, 0x05,
1328
1329 0x28, 0xC1, 0x28, 0xAD,
1330 0x1F, 0xC1, 0x15, 0xBD,
1331
1332 0x00, 0x80, 0x00, 0xE8,
1333 0x00, 0x80, 0x00, 0xE8,
1334
1335 0xA8, 0x67,
1336 0x9F, 0x6B,
1337 0x00, 0x80, 0x00, 0xE8,
1338
1339 0x28, 0xC0, 0x28, 0xAD,
1340 0x1D, 0x25,
1341 0x20, 0x05,
1342
1343 0x28, 0x32, 0x80, 0xAD,
1344 0x40, 0x2A, 0x40, 0xBD,
1345
1346 0x1C, 0x80, 0x20, 0xE9,
1347 0x20, 0x33, 0x20, 0xAD,
1348
1349 0x20, 0x73,
1350 0x00, 0xE0,
1351 0xB6, 0x49, 0x51, 0xBB,
1352
1353 0x26, 0x2F, 0xB0, 0xE8,
1354 0x19, 0x20, 0x20, 0xE9,
1355
1356 0x35, 0x20, 0x35, 0xDF,
1357 0x3D, 0x20, 0x3D, 0xDF,
1358
1359 0x15, 0x20, 0x15, 0xDF,
1360 0x1D, 0x20, 0x1D, 0xDF,
1361
1362 0x26, 0xD0, 0x26, 0xCD,
1363 0x29, 0x49, 0x2A, 0xB8,
1364
1365 0x26, 0x40, 0x80, 0xBD,
1366 0x3B, 0x48, 0x50, 0xBD,
1367
1368 0x3E, 0x54, 0x57, 0x9F,
1369 0x00, 0xE0,
1370 0x82, 0xE1,
1371
1372 0x1E, 0xAF, 0x59, 0x9F,
1373 0x00, 0x80, 0x00, 0xE8,
1374
1375 0x26, 0x30,
1376 0x29, 0x30,
1377 0x48, 0x3C, 0x48, 0xAD,
1378
1379 0x2B, 0x72,
1380 0xC2, 0xE1,
1381 0x2C, 0xC0, 0x44, 0xC2,
1382
1383 0x05, 0x24, 0x34, 0xBF,
1384 0x0D, 0x24, 0x2C, 0xBF,
1385
1386 0x2D, 0x46, 0x4E, 0xBF,
1387 0x25, 0x46, 0x56, 0xBF,
1388
1389 0x20, 0x1D, 0x6F, 0x8F,
1390 0x32, 0x3E, 0x5F, 0xE9,
1391
1392 0x3E, 0x50, 0x56, 0x9F,
1393 0x00, 0xE0,
1394 0x3B, 0x30,
1395
1396 0x1E, 0x8F, 0x51, 0x9F,
1397 0x33, 0x1E, 0x5F, 0xE9,
1398
1399 0x05, 0x44, 0x54, 0xB2,
1400 0x0D, 0x44, 0x4C, 0xB2,
1401
1402 0x19, 0xC0, 0xB0, 0xE8,
1403 0x34, 0xC0, 0x44, 0xC4,
1404
1405 0x33, 0x73,
1406 0x00, 0xE0,
1407 0x3E, 0x62, 0x57, 0x9F,
1408
1409 0x1E, 0xAF, 0x59, 0x9F,
1410 0x00, 0xE0,
1411 0x0D, 0x20,
1412
1413 0x84, 0x3E, 0x58, 0xE9,
1414 0x28, 0x1D, 0x6F, 0x8F,
1415
1416 0x05, 0x20,
1417 0x00, 0xE0,
1418 0x85, 0x1E, 0x58, 0xE9,
1419
1420 0x9B, 0x3B, 0x33, 0xDF,
1421 0x20, 0x20, 0x42, 0xAF,
1422
1423 0x30, 0x42, 0x56, 0x9F,
1424 0x80, 0x3E, 0x57, 0xE9,
1425
1426 0x3F, 0x8F, 0x51, 0x9F,
1427 0x30, 0x80, 0x5F, 0xE9,
1428
1429 0x28, 0x28, 0x24, 0xAF,
1430 0x81, 0x1E, 0x57, 0xE9,
1431
1432 0x05, 0x47, 0x57, 0xBF,
1433 0x0D, 0x47, 0x4F, 0xBF,
1434
1435 0x88, 0x80, 0x58, 0xE9,
1436 0x1B, 0x29, 0x1B, 0xDF,
1437
1438 0x30, 0x1D, 0x6F, 0x8F,
1439 0x3A, 0x30, 0x4F, 0xE9,
1440
1441 0x1C, 0x30, 0x26, 0xDF,
1442 0x09, 0xE3,
1443 0x3B, 0x05,
1444
1445 0x3E, 0x50, 0x56, 0x9F,
1446 0x3B, 0x3F, 0x4F, 0xE9,
1447
1448 0x1E, 0x8F, 0x51, 0x9F,
1449 0x00, 0xE0,
1450 0xAC, 0x20,
1451
1452 0x2D, 0x44, 0x4C, 0xB4,
1453 0x2C, 0x1C, 0xC0, 0xAF,
1454
1455 0x25, 0x44, 0x54, 0xB4,
1456 0x00, 0xE0,
1457 0xC8, 0x30,
1458
1459 0x30, 0x46, 0x30, 0xAF,
1460 0x1B, 0x1B, 0x48, 0xAF,
1461
1462 0x00, 0xE0,
1463 0x25, 0x20,
1464 0x38, 0x2C, 0x4F, 0xE9,
1465
1466 0x86, 0x80, 0x57, 0xE9,
1467 0x38, 0x1D, 0x6F, 0x8F,
1468
1469 0x28, 0x74,
1470 0x00, 0xE0,
1471 0x0D, 0x44, 0x4C, 0xB0,
1472
1473 0x05, 0x44, 0x54, 0xB0,
1474 0x2D, 0x20,
1475 0x9B, 0x10,
1476
1477 0x82, 0x3E, 0x57, 0xE9,
1478 0x32, 0xF0, 0x1B, 0xCD,
1479
1480 0x1E, 0xBD, 0x59, 0x9F,
1481 0x83, 0x1E, 0x57, 0xE9,
1482
1483 0x38, 0x47, 0x38, 0xAF,
1484 0x34, 0x20,
1485 0x2A, 0x30,
1486
1487 0x00, 0xE0,
1488 0x0D, 0x20,
1489 0x32, 0x20,
1490 0x05, 0x20,
1491
1492 0x87, 0x80, 0x57, 0xE9,
1493 0x1F, 0x54, 0x57, 0x9F,
1494
1495 0x17, 0x42, 0x56, 0x9F,
1496 0x00, 0xE0,
1497 0x3B, 0x6A,
1498
1499 0x3F, 0x8F, 0x51, 0x9F,
1500 0x37, 0x1E, 0x4F, 0xE9,
1501
1502 0x37, 0x32, 0x2A, 0xAF,
1503 0x00, 0xE0,
1504 0x32, 0x00,
1505
1506 0x00, 0x80, 0x00, 0xE8,
1507 0x27, 0xC0, 0x44, 0xC0,
1508
1509 0x36, 0x1F, 0x4F, 0xE9,
1510 0x1F, 0x1F, 0x26, 0xDF,
1511
1512 0x37, 0x1B, 0x37, 0xBF,
1513 0x17, 0x26, 0x17, 0xDF,
1514
1515 0x3E, 0x17, 0x4F, 0xE9,
1516 0x3F, 0x3F, 0x4F, 0xE9,
1517
1518 0x34, 0x1F, 0x34, 0xAF,
1519 0x2B, 0x05,
1520 0xA7, 0x20,
1521
1522 0x33, 0x2B, 0x37, 0xDF,
1523 0x27, 0x17, 0xC0, 0xAF,
1524
1525 0x34, 0x80, 0x4F, 0xE9,
1526 0x00, 0x80, 0x00, 0xE8,
1527
1528 0x0D, 0x21, 0x1A, 0xB6,
1529 0x05, 0x21, 0x31, 0xB6,
1530
1531 0x2D, 0x44, 0x4C, 0xB6,
1532 0x25, 0x44, 0x54, 0xB6,
1533
1534 0x03, 0x80, 0x2A, 0xEA,
1535 0x17, 0xC1, 0x2B, 0xBD,
1536
1537 0x0D, 0x20,
1538 0x05, 0x20,
1539 0x2F, 0xC0, 0x21, 0xC6,
1540
1541 0xB3, 0x68,
1542 0x97, 0x25,
1543 0x00, 0x80, 0x00, 0xE8,
1544
1545 0x33, 0xC0, 0x33, 0xAF,
1546 0x3C, 0x27, 0x4F, 0xE9,
1547
1548 0x00, 0xE0,
1549 0x25, 0x20,
1550 0x07, 0xC0, 0x44, 0xC6,
1551
1552 0x17, 0x50, 0x56, 0x9F,
1553 0x00, 0xE0,
1554 0x2D, 0x20,
1555
1556 0x37, 0x0F, 0x5C, 0x9F,
1557 0x00, 0xE0,
1558 0x2F, 0x20,
1559
1560 0x1F, 0x62, 0x57, 0x9F,
1561 0x00, 0xE0,
1562 0x07, 0x20,
1563
1564 0x3F, 0x3D, 0x5D, 0x9F,
1565 0x00, 0x80, 0x00, 0xE8,
1566
1567 0x00, 0x80, 0x00, 0xE8,
1568 0x28, 0x19, 0x60, 0xEC,
1569
1570 0xB3, 0x05,
1571 0x00, 0xE0,
1572 0x17, 0x26, 0x17, 0xDF,
1573
1574 0x23, 0x3B, 0x33, 0xAD,
1575 0x35, 0x17, 0x4F, 0xE9,
1576
1577 0x1F, 0x26, 0x1F, 0xDF,
1578 0x9D, 0x1F, 0x4F, 0xE9,
1579
1580 0x9E, 0x3F, 0x4F, 0xE9,
1581 0x39, 0x37, 0x4F, 0xE9,
1582
1583 0x2F, 0x2F, 0x17, 0xAF,
1584 0x00, 0x80, 0x00, 0xE8,
1585
1586 0x07, 0x07, 0x1F, 0xAF,
1587 0x00, 0x80, 0x00, 0xE8,
1588
1589 0x31, 0x80, 0x4F, 0xE9,
1590 0x00, 0x80, 0x00, 0xE8,
1591
1592 0x9C, 0x80, 0x4F, 0xE9,
1593 0x00, 0x80, 0x00, 0xE8,
1594
1595 0x00, 0x80, 0x00, 0xE8,
1596 0x57, 0x39, 0x20, 0xE9,
1597
1598 0x16, 0x28, 0x20, 0xE9,
1599 0x1D, 0x3B, 0x20, 0xE9,
1600
1601 0x1E, 0x2B, 0x20, 0xE9,
1602 0x2B, 0x32, 0x20, 0xE9,
1603
1604 0x1C, 0x23, 0x20, 0xE9,
1605 0x57, 0x36, 0x20, 0xE9,
1606
1607 0x00, 0x80, 0xA0, 0xE9,
1608 0x40, 0x40, 0xD8, 0xEC,
1609
1610 0xFF, 0x80, 0xC0, 0xE9,
1611 0x90, 0xE2,
1612 0x00, 0xE0,
1613
1614 0x74, 0xFF, 0x20, 0xEA,
1615 0x19, 0xC8, 0xC1, 0xCD,
1616
1617 0x1F, 0xD7, 0x18, 0xBD,
1618 0x3F, 0xD7, 0x22, 0xBD,
1619
1620 0x9F, 0x41, 0x49, 0xBD,
1621 0x00, 0x80, 0x00, 0xE8,
1622
1623 0x25, 0x41, 0x49, 0xBD,
1624 0x2D, 0x41, 0x51, 0xBD,
1625
1626 0x0D, 0x80, 0x07, 0xEA,
1627 0x00, 0x80, 0x00, 0xE8,
1628
1629 0x35, 0x40, 0x48, 0xBD,
1630 0x3D, 0x40, 0x50, 0xBD,
1631
1632 0x00, 0x80, 0x00, 0xE8,
1633 0x25, 0x30,
1634 0x2D, 0x30,
1635
1636 0x35, 0x30,
1637 0xB5, 0x30,
1638 0xBD, 0x30,
1639 0x3D, 0x30,
1640
1641 0x9C, 0xA7, 0x5B, 0x9F,
1642 0x00, 0x80, 0x00, 0xE8,
1643
1644 0x00, 0x80, 0x00, 0xE8,
1645 0x00, 0x80, 0x00, 0xE8,
1646
1647 0x00, 0x80, 0x00, 0xE8,
1648 0x00, 0x80, 0x00, 0xE8,
1649
1650 0x00, 0x80, 0x00, 0xE8,
1651 0x00, 0x80, 0x00, 0xE8,
1652
1653 0x00, 0x80, 0x00, 0xE8,
1654 0x00, 0x80, 0x00, 0xE8,
1655
1656 0x73, 0xFF, 0x0A, 0xEA,
1657 0x00, 0x80, 0x00, 0xE8,
1658
1659 0xC9, 0x41, 0xC8, 0xEC,
1660 0x42, 0xE1,
1661 0x00, 0xE0,
1662
1663 0x71, 0xFF, 0x20, 0xEA,
1664 0x00, 0x80, 0x00, 0xE8,
1665
1666 0x00, 0x80, 0x00, 0xE8,
1667 0x00, 0x80, 0x00, 0xE8,
1668
1669 0xC8, 0x40, 0xC0, 0xEC,
1670 0x00, 0x80, 0x00, 0xE8,
1671
1672 0x6E, 0xFF, 0x20, 0xEA,
1673 0x00, 0x80, 0x00, 0xE8,
1674
1675 0x00, 0x80, 0x00, 0xE8,
1676 0x00, 0x80, 0x00, 0xE8,
1677
1678};
1679
1680static unsigned char warp_g200_tgzf[] = {
1681
1682 0x00, 0x80, 0x00, 0xE8,
1683 0x00, 0x80, 0x00, 0xE8,
1684
1685 0x00, 0x80, 0x00, 0xE8,
1686 0x00, 0x80, 0x00, 0xE8,
1687
1688 0x00, 0x80, 0x00, 0xE8,
1689 0x00, 0x80, 0x00, 0xE8,
1690
1691 0x00, 0x80, 0x00, 0xE8,
1692 0x00, 0x80, 0x00, 0xE8,
1693
1694 0x00, 0x80, 0x00, 0xE8,
1695 0x00, 0x80, 0x00, 0xE8,
1696
1697 0x00, 0x80, 0x00, 0xE8,
1698 0x00, 0x80, 0x00, 0xE8,
1699
1700 0x00, 0x80, 0x00, 0xE8,
1701 0x00, 0x80, 0x00, 0xE8,
1702
1703 0x00, 0x80, 0x00, 0xE8,
1704 0x00, 0x80, 0x00, 0xE8,
1705
1706 0x00, 0x80, 0x00, 0xE8,
1707 0x00, 0x80, 0x00, 0xE8,
1708
1709 0x00, 0x80, 0x00, 0xE8,
1710 0x00, 0x80, 0x00, 0xE8,
1711
1712 0x00, 0x98, 0xA0, 0xE9,
1713 0x40, 0x40, 0xD8, 0xEC,
1714
1715 0xFF, 0x80, 0xC0, 0xE9,
1716 0x00, 0x80, 0x00, 0xE8,
1717
1718 0x1F, 0xD7, 0x18, 0xBD,
1719 0x3F, 0xD7, 0x22, 0xBD,
1720
1721 0x81, 0x04,
1722 0x89, 0x04,
1723 0x01, 0x04,
1724 0x09, 0x04,
1725
1726 0xC9, 0x41, 0xC0, 0xEC,
1727 0x11, 0x04,
1728 0x00, 0xE0,
1729
1730 0x41, 0xCC, 0x41, 0xCD,
1731 0x49, 0xCC, 0x49, 0xCD,
1732
1733 0xD1, 0x41, 0xC0, 0xEC,
1734 0x51, 0xCC, 0x51, 0xCD,
1735
1736 0x80, 0x04,
1737 0x10, 0x04,
1738 0x08, 0x04,
1739 0x00, 0xE0,
1740
1741 0x00, 0xCC, 0xC0, 0xCD,
1742 0xD1, 0x49, 0xC0, 0xEC,
1743
1744 0x8A, 0x1F, 0x20, 0xE9,
1745 0x8B, 0x3F, 0x20, 0xE9,
1746
1747 0x41, 0x3C, 0x41, 0xAD,
1748 0x49, 0x3C, 0x49, 0xAD,
1749
1750 0x10, 0xCC, 0x10, 0xCD,
1751 0x08, 0xCC, 0x08, 0xCD,
1752
1753 0xB9, 0x41, 0x49, 0xBB,
1754 0x1F, 0xF0, 0x41, 0xCD,
1755
1756 0x51, 0x3C, 0x51, 0xAD,
1757 0x00, 0x98, 0x80, 0xE9,
1758
1759 0x7F, 0x80, 0x07, 0xEA,
1760 0x24, 0x1F, 0x20, 0xE9,
1761
1762 0x21, 0x45, 0x80, 0xE8,
1763 0x1A, 0x4D, 0x80, 0xE8,
1764
1765 0x31, 0x55, 0x80, 0xE8,
1766 0x00, 0x80, 0x00, 0xE8,
1767
1768 0x15, 0x41, 0x49, 0xBD,
1769 0x1D, 0x41, 0x51, 0xBD,
1770
1771 0x2E, 0x41, 0x2A, 0xB8,
1772 0x34, 0x53, 0xA0, 0xE8,
1773
1774 0x15, 0x30,
1775 0x1D, 0x30,
1776 0x58, 0xE3,
1777 0x00, 0xE0,
1778
1779 0xB5, 0x40, 0x48, 0xBD,
1780 0x3D, 0x40, 0x50, 0xBD,
1781
1782 0x24, 0x43, 0xA0, 0xE8,
1783 0x2C, 0x4B, 0xA0, 0xE8,
1784
1785 0x15, 0x72,
1786 0x09, 0xE3,
1787 0x00, 0xE0,
1788 0x1D, 0x72,
1789
1790 0x35, 0x30,
1791 0xB5, 0x30,
1792 0xBD, 0x30,
1793 0x3D, 0x30,
1794
1795 0x9C, 0x97, 0x57, 0x9F,
1796 0x00, 0x80, 0x00, 0xE8,
1797
1798 0x6C, 0x64, 0xC8, 0xEC,
1799 0x98, 0xE1,
1800 0xB5, 0x05,
1801
1802 0xBD, 0x05,
1803 0x2E, 0x30,
1804 0x32, 0xC0, 0xA0, 0xE8,
1805
1806 0x33, 0xC0, 0xA0, 0xE8,
1807 0x74, 0x64, 0xC8, 0xEC,
1808
1809 0x40, 0x3C, 0x40, 0xAD,
1810 0x32, 0x6A,
1811 0x2A, 0x30,
1812
1813 0x20, 0x73,
1814 0x33, 0x6A,
1815 0x00, 0xE0,
1816 0x28, 0x73,
1817
1818 0x1C, 0x72,
1819 0x83, 0xE2,
1820 0x6B, 0x80, 0x15, 0xEA,
1821
1822 0xB8, 0x3D, 0x28, 0xDF,
1823 0x30, 0x35, 0x20, 0xDF,
1824
1825 0x40, 0x30,
1826 0x00, 0xE0,
1827 0xCC, 0xE2,
1828 0x64, 0x72,
1829
1830 0x25, 0x42, 0x52, 0xBF,
1831 0x2D, 0x42, 0x4A, 0xBF,
1832
1833 0x30, 0x2E, 0x30, 0xDF,
1834 0x38, 0x2E, 0x38, 0xDF,
1835
1836 0x18, 0x1D, 0x45, 0xE9,
1837 0x1E, 0x15, 0x45, 0xE9,
1838
1839 0x2B, 0x49, 0x51, 0xBD,
1840 0x00, 0xE0,
1841 0x1F, 0x73,
1842
1843 0x38, 0x38, 0x40, 0xAF,
1844 0x30, 0x30, 0x40, 0xAF,
1845
1846 0x24, 0x1F, 0x24, 0xDF,
1847 0x1D, 0x32, 0x20, 0xE9,
1848
1849 0x2C, 0x1F, 0x2C, 0xDF,
1850 0x1A, 0x33, 0x20, 0xE9,
1851
1852 0xB0, 0x10,
1853 0x08, 0xE3,
1854 0x40, 0x10,
1855 0xB8, 0x10,
1856
1857 0x26, 0xF0, 0x30, 0xCD,
1858 0x2F, 0xF0, 0x38, 0xCD,
1859
1860 0x2B, 0x80, 0x20, 0xE9,
1861 0x2A, 0x80, 0x20, 0xE9,
1862
1863 0xA6, 0x20,
1864 0x88, 0xE2,
1865 0x00, 0xE0,
1866 0xAF, 0x20,
1867
1868 0x28, 0x2A, 0x26, 0xAF,
1869 0x20, 0x2A, 0xC0, 0xAF,
1870
1871 0x34, 0x1F, 0x34, 0xDF,
1872 0x46, 0x24, 0x46, 0xDF,
1873
1874 0x28, 0x30, 0x80, 0xBF,
1875 0x20, 0x38, 0x80, 0xBF,
1876
1877 0x47, 0x24, 0x47, 0xDF,
1878 0x4E, 0x2C, 0x4E, 0xDF,
1879
1880 0x4F, 0x2C, 0x4F, 0xDF,
1881 0x56, 0x34, 0x56, 0xDF,
1882
1883 0x28, 0x15, 0x28, 0xDF,
1884 0x20, 0x1D, 0x20, 0xDF,
1885
1886 0x57, 0x34, 0x57, 0xDF,
1887 0x00, 0xE0,
1888 0x1D, 0x05,
1889
1890 0x04, 0x80, 0x10, 0xEA,
1891 0x89, 0xE2,
1892 0x2B, 0x30,
1893
1894 0x3F, 0xC1, 0x1D, 0xBD,
1895 0x00, 0x80, 0x00, 0xE8,
1896
1897 0x00, 0x80, 0x00, 0xE8,
1898 0x00, 0x80, 0x00, 0xE8,
1899
1900 0xA0, 0x68,
1901 0xBF, 0x25,
1902 0x00, 0x80, 0x00, 0xE8,
1903
1904 0x20, 0xC0, 0x20, 0xAF,
1905 0x28, 0x05,
1906 0x97, 0x74,
1907
1908 0x00, 0xE0,
1909 0x2A, 0x10,
1910 0x16, 0xC0, 0x20, 0xE9,
1911
1912 0x04, 0x80, 0x10, 0xEA,
1913 0x8C, 0xE2,
1914 0x95, 0x05,
1915
1916 0x28, 0xC1, 0x28, 0xAD,
1917 0x1F, 0xC1, 0x15, 0xBD,
1918
1919 0x00, 0x80, 0x00, 0xE8,
1920 0x00, 0x80, 0x00, 0xE8,
1921
1922 0xA8, 0x67,
1923 0x9F, 0x6B,
1924 0x00, 0x80, 0x00, 0xE8,
1925
1926 0x28, 0xC0, 0x28, 0xAD,
1927 0x1D, 0x25,
1928 0x20, 0x05,
1929
1930 0x28, 0x32, 0x80, 0xAD,
1931 0x40, 0x2A, 0x40, 0xBD,
1932
1933 0x1C, 0x80, 0x20, 0xE9,
1934 0x20, 0x33, 0x20, 0xAD,
1935
1936 0x20, 0x73,
1937 0x00, 0xE0,
1938 0xB6, 0x49, 0x51, 0xBB,
1939
1940 0x26, 0x2F, 0xB0, 0xE8,
1941 0x19, 0x20, 0x20, 0xE9,
1942
1943 0x35, 0x20, 0x35, 0xDF,
1944 0x3D, 0x20, 0x3D, 0xDF,
1945
1946 0x15, 0x20, 0x15, 0xDF,
1947 0x1D, 0x20, 0x1D, 0xDF,
1948
1949 0x26, 0xD0, 0x26, 0xCD,
1950 0x29, 0x49, 0x2A, 0xB8,
1951
1952 0x26, 0x40, 0x80, 0xBD,
1953 0x3B, 0x48, 0x50, 0xBD,
1954
1955 0x3E, 0x54, 0x57, 0x9F,
1956 0x00, 0xE0,
1957 0x82, 0xE1,
1958
1959 0x1E, 0xAF, 0x59, 0x9F,
1960 0x00, 0x80, 0x00, 0xE8,
1961
1962 0x26, 0x30,
1963 0x29, 0x30,
1964 0x48, 0x3C, 0x48, 0xAD,
1965
1966 0x2B, 0x72,
1967 0xC2, 0xE1,
1968 0x2C, 0xC0, 0x44, 0xC2,
1969
1970 0x05, 0x24, 0x34, 0xBF,
1971 0x0D, 0x24, 0x2C, 0xBF,
1972
1973 0x2D, 0x46, 0x4E, 0xBF,
1974 0x25, 0x46, 0x56, 0xBF,
1975
1976 0x20, 0x1D, 0x6F, 0x8F,
1977 0x32, 0x3E, 0x5F, 0xE9,
1978
1979 0x3E, 0x50, 0x56, 0x9F,
1980 0x00, 0xE0,
1981 0x3B, 0x30,
1982
1983 0x1E, 0x8F, 0x51, 0x9F,
1984 0x33, 0x1E, 0x5F, 0xE9,
1985
1986 0x05, 0x44, 0x54, 0xB2,
1987 0x0D, 0x44, 0x4C, 0xB2,
1988
1989 0x19, 0xC0, 0xB0, 0xE8,
1990 0x34, 0xC0, 0x44, 0xC4,
1991
1992 0x33, 0x73,
1993 0x00, 0xE0,
1994 0x3E, 0x62, 0x57, 0x9F,
1995
1996 0x1E, 0xAF, 0x59, 0x9F,
1997 0x00, 0xE0,
1998 0x0D, 0x20,
1999
2000 0x84, 0x3E, 0x58, 0xE9,
2001 0x28, 0x1D, 0x6F, 0x8F,
2002
2003 0x05, 0x20,
2004 0x00, 0xE0,
2005 0x85, 0x1E, 0x58, 0xE9,
2006
2007 0x9B, 0x3B, 0x33, 0xDF,
2008 0x20, 0x20, 0x42, 0xAF,
2009
2010 0x30, 0x42, 0x56, 0x9F,
2011 0x80, 0x3E, 0x57, 0xE9,
2012
2013 0x3F, 0x8F, 0x51, 0x9F,
2014 0x30, 0x80, 0x5F, 0xE9,
2015
2016 0x28, 0x28, 0x24, 0xAF,
2017 0x81, 0x1E, 0x57, 0xE9,
2018
2019 0x05, 0x47, 0x57, 0xBF,
2020 0x0D, 0x47, 0x4F, 0xBF,
2021
2022 0x88, 0x80, 0x58, 0xE9,
2023 0x1B, 0x29, 0x1B, 0xDF,
2024
2025 0x30, 0x1D, 0x6F, 0x8F,
2026 0x3A, 0x30, 0x4F, 0xE9,
2027
2028 0x1C, 0x30, 0x26, 0xDF,
2029 0x09, 0xE3,
2030 0x3B, 0x05,
2031
2032 0x3E, 0x50, 0x56, 0x9F,
2033 0x3B, 0x3F, 0x4F, 0xE9,
2034
2035 0x1E, 0x8F, 0x51, 0x9F,
2036 0x00, 0xE0,
2037 0xAC, 0x20,
2038
2039 0x2D, 0x44, 0x4C, 0xB4,
2040 0x2C, 0x1C, 0xC0, 0xAF,
2041
2042 0x25, 0x44, 0x54, 0xB4,
2043 0x00, 0xE0,
2044 0xC8, 0x30,
2045
2046 0x30, 0x46, 0x30, 0xAF,
2047 0x1B, 0x1B, 0x48, 0xAF,
2048
2049 0x00, 0xE0,
2050 0x25, 0x20,
2051 0x38, 0x2C, 0x4F, 0xE9,
2052
2053 0x86, 0x80, 0x57, 0xE9,
2054 0x38, 0x1D, 0x6F, 0x8F,
2055
2056 0x28, 0x74,
2057 0x00, 0xE0,
2058 0x0D, 0x44, 0x4C, 0xB0,
2059
2060 0x05, 0x44, 0x54, 0xB0,
2061 0x2D, 0x20,
2062 0x9B, 0x10,
2063
2064 0x82, 0x3E, 0x57, 0xE9,
2065 0x32, 0xF0, 0x1B, 0xCD,
2066
2067 0x1E, 0xBD, 0x59, 0x9F,
2068 0x83, 0x1E, 0x57, 0xE9,
2069
2070 0x38, 0x47, 0x38, 0xAF,
2071 0x34, 0x20,
2072 0x2A, 0x30,
2073
2074 0x00, 0xE0,
2075 0x0D, 0x20,
2076 0x32, 0x20,
2077 0x05, 0x20,
2078
2079 0x87, 0x80, 0x57, 0xE9,
2080 0x1F, 0x54, 0x57, 0x9F,
2081
2082 0x17, 0x42, 0x56, 0x9F,
2083 0x00, 0xE0,
2084 0x3B, 0x6A,
2085
2086 0x3F, 0x8F, 0x51, 0x9F,
2087 0x37, 0x1E, 0x4F, 0xE9,
2088
2089 0x37, 0x32, 0x2A, 0xAF,
2090 0x00, 0xE0,
2091 0x32, 0x00,
2092
2093 0x00, 0x80, 0x00, 0xE8,
2094 0x27, 0xC0, 0x44, 0xC0,
2095
2096 0x36, 0x1F, 0x4F, 0xE9,
2097 0x1F, 0x1F, 0x26, 0xDF,
2098
2099 0x37, 0x1B, 0x37, 0xBF,
2100 0x17, 0x26, 0x17, 0xDF,
2101
2102 0x3E, 0x17, 0x4F, 0xE9,
2103 0x3F, 0x3F, 0x4F, 0xE9,
2104
2105 0x34, 0x1F, 0x34, 0xAF,
2106 0x2B, 0x05,
2107 0xA7, 0x20,
2108
2109 0x33, 0x2B, 0x37, 0xDF,
2110 0x27, 0x17, 0xC0, 0xAF,
2111
2112 0x34, 0x80, 0x4F, 0xE9,
2113 0x00, 0x80, 0x00, 0xE8,
2114
2115 0x0D, 0x21, 0x1A, 0xB6,
2116 0x05, 0x21, 0x31, 0xB6,
2117
2118 0x03, 0x80, 0x2A, 0xEA,
2119 0x17, 0xC1, 0x2B, 0xBD,
2120
2121 0x0D, 0x20,
2122 0x05, 0x20,
2123 0x2F, 0xC0, 0x21, 0xC6,
2124
2125 0xB3, 0x68,
2126 0x97, 0x25,
2127 0x00, 0x80, 0x00, 0xE8,
2128
2129 0x33, 0xC0, 0x33, 0xAF,
2130 0x3C, 0x27, 0x4F, 0xE9,
2131
2132 0x17, 0x50, 0x56, 0x9F,
2133 0x00, 0x80, 0x00, 0xE8,
2134
2135 0x37, 0x0F, 0x5C, 0x9F,
2136 0x00, 0xE0,
2137 0x2F, 0x20,
2138
2139 0x00, 0x80, 0x00, 0xE8,
2140 0x28, 0x19, 0x60, 0xEC,
2141
2142 0xB3, 0x05,
2143 0x00, 0xE0,
2144 0x00, 0x80, 0x00, 0xE8,
2145
2146 0x23, 0x3B, 0x33, 0xAD,
2147 0x00, 0x80, 0x00, 0xE8,
2148
2149 0x17, 0x26, 0x17, 0xDF,
2150 0x35, 0x17, 0x4F, 0xE9,
2151
2152 0x00, 0x80, 0x00, 0xE8,
2153 0x00, 0x80, 0x00, 0xE8,
2154
2155 0x00, 0x80, 0x00, 0xE8,
2156 0x39, 0x37, 0x4F, 0xE9,
2157
2158 0x2F, 0x2F, 0x17, 0xAF,
2159 0x00, 0x80, 0x00, 0xE8,
2160
2161 0x00, 0x80, 0x00, 0xE8,
2162 0x00, 0x80, 0x00, 0xE8,
2163
2164 0x31, 0x80, 0x4F, 0xE9,
2165 0x00, 0x80, 0x00, 0xE8,
2166
2167 0x00, 0x80, 0x00, 0xE8,
2168 0x57, 0x39, 0x20, 0xE9,
2169
2170 0x16, 0x28, 0x20, 0xE9,
2171 0x1D, 0x3B, 0x20, 0xE9,
2172
2173 0x1E, 0x2B, 0x20, 0xE9,
2174 0x2B, 0x32, 0x20, 0xE9,
2175
2176 0x1C, 0x23, 0x20, 0xE9,
2177 0x57, 0x36, 0x20, 0xE9,
2178
2179 0x00, 0x80, 0xA0, 0xE9,
2180 0x40, 0x40, 0xD8, 0xEC,
2181
2182 0xFF, 0x80, 0xC0, 0xE9,
2183 0x90, 0xE2,
2184 0x00, 0xE0,
2185
2186 0x78, 0xFF, 0x20, 0xEA,
2187 0x19, 0xC8, 0xC1, 0xCD,
2188
2189 0x1F, 0xD7, 0x18, 0xBD,
2190 0x3F, 0xD7, 0x22, 0xBD,
2191
2192 0x9F, 0x41, 0x49, 0xBD,
2193 0x00, 0x80, 0x00, 0xE8,
2194
2195 0x25, 0x41, 0x49, 0xBD,
2196 0x2D, 0x41, 0x51, 0xBD,
2197
2198 0x0D, 0x80, 0x07, 0xEA,
2199 0x00, 0x80, 0x00, 0xE8,
2200
2201 0x35, 0x40, 0x48, 0xBD,
2202 0x3D, 0x40, 0x50, 0xBD,
2203
2204 0x00, 0x80, 0x00, 0xE8,
2205 0x25, 0x30,
2206 0x2D, 0x30,
2207
2208 0x35, 0x30,
2209 0xB5, 0x30,
2210 0xBD, 0x30,
2211 0x3D, 0x30,
2212
2213 0x9C, 0xA7, 0x5B, 0x9F,
2214 0x00, 0x80, 0x00, 0xE8,
2215
2216 0x00, 0x80, 0x00, 0xE8,
2217 0x00, 0x80, 0x00, 0xE8,
2218
2219 0x00, 0x80, 0x00, 0xE8,
2220 0x00, 0x80, 0x00, 0xE8,
2221
2222 0x00, 0x80, 0x00, 0xE8,
2223 0x00, 0x80, 0x00, 0xE8,
2224
2225 0x00, 0x80, 0x00, 0xE8,
2226 0x00, 0x80, 0x00, 0xE8,
2227
2228 0x77, 0xFF, 0x0A, 0xEA,
2229 0x00, 0x80, 0x00, 0xE8,
2230
2231 0xC9, 0x41, 0xC8, 0xEC,
2232 0x42, 0xE1,
2233 0x00, 0xE0,
2234
2235 0x75, 0xFF, 0x20, 0xEA,
2236 0x00, 0x80, 0x00, 0xE8,
2237
2238 0x00, 0x80, 0x00, 0xE8,
2239 0x00, 0x80, 0x00, 0xE8,
2240
2241 0xC8, 0x40, 0xC0, 0xEC,
2242 0x00, 0x80, 0x00, 0xE8,
2243
2244 0x72, 0xFF, 0x20, 0xEA,
2245 0x00, 0x80, 0x00, 0xE8,
2246
2247 0x00, 0x80, 0x00, 0xE8,
2248 0x00, 0x80, 0x00, 0xE8,
2249
2250};
2251
2252static unsigned char warp_g200_tgzs[] = {
2253
2254 0x00, 0x80, 0x00, 0xE8,
2255 0x00, 0x80, 0x00, 0xE8,
2256
2257 0x00, 0x80, 0x00, 0xE8,
2258 0x00, 0x80, 0x00, 0xE8,
2259
2260 0x00, 0x80, 0x00, 0xE8,
2261 0x00, 0x80, 0x00, 0xE8,
2262
2263 0x00, 0x80, 0x00, 0xE8,
2264 0x00, 0x80, 0x00, 0xE8,
2265
2266 0x00, 0x80, 0x00, 0xE8,
2267 0x00, 0x80, 0x00, 0xE8,
2268
2269 0x00, 0x80, 0x00, 0xE8,
2270 0x00, 0x80, 0x00, 0xE8,
2271
2272 0x00, 0x80, 0x00, 0xE8,
2273 0x00, 0x80, 0x00, 0xE8,
2274
2275 0x00, 0x80, 0x00, 0xE8,
2276 0x00, 0x80, 0x00, 0xE8,
2277
2278 0x00, 0x80, 0x00, 0xE8,
2279 0x00, 0x80, 0x00, 0xE8,
2280
2281 0x00, 0x80, 0x00, 0xE8,
2282 0x00, 0x80, 0x00, 0xE8,
2283
2284 0x00, 0x80, 0x00, 0xE8,
2285 0x00, 0x80, 0x00, 0xE8,
2286
2287 0x00, 0x80, 0x00, 0xE8,
2288 0x00, 0x80, 0x00, 0xE8,
2289
2290 0x00, 0x80, 0x00, 0xE8,
2291 0x00, 0x80, 0x00, 0xE8,
2292
2293 0x00, 0x98, 0xA0, 0xE9,
2294 0x40, 0x40, 0xD8, 0xEC,
2295
2296 0xFF, 0x80, 0xC0, 0xE9,
2297 0x00, 0x80, 0x00, 0xE8,
2298
2299 0x1F, 0xD7, 0x18, 0xBD,
2300 0x3F, 0xD7, 0x22, 0xBD,
2301
2302 0x81, 0x04,
2303 0x89, 0x04,
2304 0x01, 0x04,
2305 0x09, 0x04,
2306
2307 0xC9, 0x41, 0xC0, 0xEC,
2308 0x11, 0x04,
2309 0x00, 0xE0,
2310
2311 0x41, 0xCC, 0x41, 0xCD,
2312 0x49, 0xCC, 0x49, 0xCD,
2313
2314 0xD1, 0x41, 0xC0, 0xEC,
2315 0x51, 0xCC, 0x51, 0xCD,
2316
2317 0x80, 0x04,
2318 0x10, 0x04,
2319 0x08, 0x04,
2320 0x00, 0xE0,
2321
2322 0x00, 0xCC, 0xC0, 0xCD,
2323 0xD1, 0x49, 0xC0, 0xEC,
2324
2325 0x8A, 0x1F, 0x20, 0xE9,
2326 0x8B, 0x3F, 0x20, 0xE9,
2327
2328 0x41, 0x3C, 0x41, 0xAD,
2329 0x49, 0x3C, 0x49, 0xAD,
2330
2331 0x10, 0xCC, 0x10, 0xCD,
2332 0x08, 0xCC, 0x08, 0xCD,
2333
2334 0xB9, 0x41, 0x49, 0xBB,
2335 0x1F, 0xF0, 0x41, 0xCD,
2336
2337 0x51, 0x3C, 0x51, 0xAD,
2338 0x00, 0x98, 0x80, 0xE9,
2339
2340 0x8B, 0x80, 0x07, 0xEA,
2341 0x24, 0x1F, 0x20, 0xE9,
2342
2343 0x21, 0x45, 0x80, 0xE8,
2344 0x1A, 0x4D, 0x80, 0xE8,
2345
2346 0x31, 0x55, 0x80, 0xE8,
2347 0x00, 0x80, 0x00, 0xE8,
2348
2349 0x15, 0x41, 0x49, 0xBD,
2350 0x1D, 0x41, 0x51, 0xBD,
2351
2352 0x2E, 0x41, 0x2A, 0xB8,
2353 0x34, 0x53, 0xA0, 0xE8,
2354
2355 0x15, 0x30,
2356 0x1D, 0x30,
2357 0x58, 0xE3,
2358 0x00, 0xE0,
2359
2360 0xB5, 0x40, 0x48, 0xBD,
2361 0x3D, 0x40, 0x50, 0xBD,
2362
2363 0x24, 0x43, 0xA0, 0xE8,
2364 0x2C, 0x4B, 0xA0, 0xE8,
2365
2366 0x15, 0x72,
2367 0x09, 0xE3,
2368 0x00, 0xE0,
2369 0x1D, 0x72,
2370
2371 0x35, 0x30,
2372 0xB5, 0x30,
2373 0xBD, 0x30,
2374 0x3D, 0x30,
2375
2376 0x9C, 0x97, 0x57, 0x9F,
2377 0x00, 0x80, 0x00, 0xE8,
2378
2379 0x6C, 0x64, 0xC8, 0xEC,
2380 0x98, 0xE1,
2381 0xB5, 0x05,
2382
2383 0xBD, 0x05,
2384 0x2E, 0x30,
2385 0x32, 0xC0, 0xA0, 0xE8,
2386
2387 0x33, 0xC0, 0xA0, 0xE8,
2388 0x74, 0x64, 0xC8, 0xEC,
2389
2390 0x40, 0x3C, 0x40, 0xAD,
2391 0x32, 0x6A,
2392 0x2A, 0x30,
2393
2394 0x20, 0x73,
2395 0x33, 0x6A,
2396 0x00, 0xE0,
2397 0x28, 0x73,
2398
2399 0x1C, 0x72,
2400 0x83, 0xE2,
2401 0x77, 0x80, 0x15, 0xEA,
2402
2403 0xB8, 0x3D, 0x28, 0xDF,
2404 0x30, 0x35, 0x20, 0xDF,
2405
2406 0x40, 0x30,
2407 0x00, 0xE0,
2408 0xCC, 0xE2,
2409 0x64, 0x72,
2410
2411 0x25, 0x42, 0x52, 0xBF,
2412 0x2D, 0x42, 0x4A, 0xBF,
2413
2414 0x30, 0x2E, 0x30, 0xDF,
2415 0x38, 0x2E, 0x38, 0xDF,
2416
2417 0x18, 0x1D, 0x45, 0xE9,
2418 0x1E, 0x15, 0x45, 0xE9,
2419
2420 0x2B, 0x49, 0x51, 0xBD,
2421 0x00, 0xE0,
2422 0x1F, 0x73,
2423
2424 0x38, 0x38, 0x40, 0xAF,
2425 0x30, 0x30, 0x40, 0xAF,
2426
2427 0x24, 0x1F, 0x24, 0xDF,
2428 0x1D, 0x32, 0x20, 0xE9,
2429
2430 0x2C, 0x1F, 0x2C, 0xDF,
2431 0x1A, 0x33, 0x20, 0xE9,
2432
2433 0xB0, 0x10,
2434 0x08, 0xE3,
2435 0x40, 0x10,
2436 0xB8, 0x10,
2437
2438 0x26, 0xF0, 0x30, 0xCD,
2439 0x2F, 0xF0, 0x38, 0xCD,
2440
2441 0x2B, 0x80, 0x20, 0xE9,
2442 0x2A, 0x80, 0x20, 0xE9,
2443
2444 0xA6, 0x20,
2445 0x88, 0xE2,
2446 0x00, 0xE0,
2447 0xAF, 0x20,
2448
2449 0x28, 0x2A, 0x26, 0xAF,
2450 0x20, 0x2A, 0xC0, 0xAF,
2451
2452 0x34, 0x1F, 0x34, 0xDF,
2453 0x46, 0x24, 0x46, 0xDF,
2454
2455 0x28, 0x30, 0x80, 0xBF,
2456 0x20, 0x38, 0x80, 0xBF,
2457
2458 0x47, 0x24, 0x47, 0xDF,
2459 0x4E, 0x2C, 0x4E, 0xDF,
2460
2461 0x4F, 0x2C, 0x4F, 0xDF,
2462 0x56, 0x34, 0x56, 0xDF,
2463
2464 0x28, 0x15, 0x28, 0xDF,
2465 0x20, 0x1D, 0x20, 0xDF,
2466
2467 0x57, 0x34, 0x57, 0xDF,
2468 0x00, 0xE0,
2469 0x1D, 0x05,
2470
2471 0x04, 0x80, 0x10, 0xEA,
2472 0x89, 0xE2,
2473 0x2B, 0x30,
2474
2475 0x3F, 0xC1, 0x1D, 0xBD,
2476 0x00, 0x80, 0x00, 0xE8,
2477
2478 0x00, 0x80, 0x00, 0xE8,
2479 0x00, 0x80, 0x00, 0xE8,
2480
2481 0xA0, 0x68,
2482 0xBF, 0x25,
2483 0x00, 0x80, 0x00, 0xE8,
2484
2485 0x20, 0xC0, 0x20, 0xAF,
2486 0x28, 0x05,
2487 0x97, 0x74,
2488
2489 0x00, 0xE0,
2490 0x2A, 0x10,
2491 0x16, 0xC0, 0x20, 0xE9,
2492
2493 0x04, 0x80, 0x10, 0xEA,
2494 0x8C, 0xE2,
2495 0x95, 0x05,
2496
2497 0x28, 0xC1, 0x28, 0xAD,
2498 0x1F, 0xC1, 0x15, 0xBD,
2499
2500 0x00, 0x80, 0x00, 0xE8,
2501 0x00, 0x80, 0x00, 0xE8,
2502
2503 0xA8, 0x67,
2504 0x9F, 0x6B,
2505 0x00, 0x80, 0x00, 0xE8,
2506
2507 0x28, 0xC0, 0x28, 0xAD,
2508 0x1D, 0x25,
2509 0x20, 0x05,
2510
2511 0x28, 0x32, 0x80, 0xAD,
2512 0x40, 0x2A, 0x40, 0xBD,
2513
2514 0x1C, 0x80, 0x20, 0xE9,
2515 0x20, 0x33, 0x20, 0xAD,
2516
2517 0x20, 0x73,
2518 0x00, 0xE0,
2519 0xB6, 0x49, 0x51, 0xBB,
2520
2521 0x26, 0x2F, 0xB0, 0xE8,
2522 0x19, 0x20, 0x20, 0xE9,
2523
2524 0x35, 0x20, 0x35, 0xDF,
2525 0x3D, 0x20, 0x3D, 0xDF,
2526
2527 0x15, 0x20, 0x15, 0xDF,
2528 0x1D, 0x20, 0x1D, 0xDF,
2529
2530 0x26, 0xD0, 0x26, 0xCD,
2531 0x29, 0x49, 0x2A, 0xB8,
2532
2533 0x26, 0x40, 0x80, 0xBD,
2534 0x3B, 0x48, 0x50, 0xBD,
2535
2536 0x3E, 0x54, 0x57, 0x9F,
2537 0x00, 0xE0,
2538 0x82, 0xE1,
2539
2540 0x1E, 0xAF, 0x59, 0x9F,
2541 0x00, 0x80, 0x00, 0xE8,
2542
2543 0x26, 0x30,
2544 0x29, 0x30,
2545 0x48, 0x3C, 0x48, 0xAD,
2546
2547 0x2B, 0x72,
2548 0xC2, 0xE1,
2549 0x2C, 0xC0, 0x44, 0xC2,
2550
2551 0x05, 0x24, 0x34, 0xBF,
2552 0x0D, 0x24, 0x2C, 0xBF,
2553
2554 0x2D, 0x46, 0x4E, 0xBF,
2555 0x25, 0x46, 0x56, 0xBF,
2556
2557 0x20, 0x1D, 0x6F, 0x8F,
2558 0x32, 0x3E, 0x5F, 0xE9,
2559
2560 0x3E, 0x50, 0x56, 0x9F,
2561 0x00, 0xE0,
2562 0x3B, 0x30,
2563
2564 0x1E, 0x8F, 0x51, 0x9F,
2565 0x33, 0x1E, 0x5F, 0xE9,
2566
2567 0x05, 0x44, 0x54, 0xB2,
2568 0x0D, 0x44, 0x4C, 0xB2,
2569
2570 0x19, 0xC0, 0xB0, 0xE8,
2571 0x34, 0xC0, 0x44, 0xC4,
2572
2573 0x33, 0x73,
2574 0x00, 0xE0,
2575 0x3E, 0x62, 0x57, 0x9F,
2576
2577 0x1E, 0xAF, 0x59, 0x9F,
2578 0x00, 0xE0,
2579 0x0D, 0x20,
2580
2581 0x84, 0x3E, 0x58, 0xE9,
2582 0x28, 0x1D, 0x6F, 0x8F,
2583
2584 0x05, 0x20,
2585 0x00, 0xE0,
2586 0x85, 0x1E, 0x58, 0xE9,
2587
2588 0x9B, 0x3B, 0x33, 0xDF,
2589 0x20, 0x20, 0x42, 0xAF,
2590
2591 0x30, 0x42, 0x56, 0x9F,
2592 0x80, 0x3E, 0x57, 0xE9,
2593
2594 0x3F, 0x8F, 0x51, 0x9F,
2595 0x30, 0x80, 0x5F, 0xE9,
2596
2597 0x28, 0x28, 0x24, 0xAF,
2598 0x81, 0x1E, 0x57, 0xE9,
2599
2600 0x05, 0x47, 0x57, 0xBF,
2601 0x0D, 0x47, 0x4F, 0xBF,
2602
2603 0x88, 0x80, 0x58, 0xE9,
2604 0x1B, 0x29, 0x1B, 0xDF,
2605
2606 0x30, 0x1D, 0x6F, 0x8F,
2607 0x3A, 0x30, 0x4F, 0xE9,
2608
2609 0x1C, 0x30, 0x26, 0xDF,
2610 0x09, 0xE3,
2611 0x3B, 0x05,
2612
2613 0x3E, 0x50, 0x56, 0x9F,
2614 0x3B, 0x3F, 0x4F, 0xE9,
2615
2616 0x1E, 0x8F, 0x51, 0x9F,
2617 0x00, 0xE0,
2618 0xAC, 0x20,
2619
2620 0x2D, 0x44, 0x4C, 0xB4,
2621 0x2C, 0x1C, 0xC0, 0xAF,
2622
2623 0x25, 0x44, 0x54, 0xB4,
2624 0x00, 0xE0,
2625 0xC8, 0x30,
2626
2627 0x30, 0x46, 0x30, 0xAF,
2628 0x1B, 0x1B, 0x48, 0xAF,
2629
2630 0x00, 0xE0,
2631 0x25, 0x20,
2632 0x38, 0x2C, 0x4F, 0xE9,
2633
2634 0x86, 0x80, 0x57, 0xE9,
2635 0x38, 0x1D, 0x6F, 0x8F,
2636
2637 0x28, 0x74,
2638 0x00, 0xE0,
2639 0x0D, 0x44, 0x4C, 0xB0,
2640
2641 0x05, 0x44, 0x54, 0xB0,
2642 0x2D, 0x20,
2643 0x9B, 0x10,
2644
2645 0x82, 0x3E, 0x57, 0xE9,
2646 0x32, 0xF0, 0x1B, 0xCD,
2647
2648 0x1E, 0xBD, 0x59, 0x9F,
2649 0x83, 0x1E, 0x57, 0xE9,
2650
2651 0x38, 0x47, 0x38, 0xAF,
2652 0x34, 0x20,
2653 0x2A, 0x30,
2654
2655 0x00, 0xE0,
2656 0x0D, 0x20,
2657 0x32, 0x20,
2658 0x05, 0x20,
2659
2660 0x87, 0x80, 0x57, 0xE9,
2661 0x1F, 0x54, 0x57, 0x9F,
2662
2663 0x17, 0x42, 0x56, 0x9F,
2664 0x00, 0xE0,
2665 0x3B, 0x6A,
2666
2667 0x3F, 0x8F, 0x51, 0x9F,
2668 0x37, 0x1E, 0x4F, 0xE9,
2669
2670 0x37, 0x32, 0x2A, 0xAF,
2671 0x00, 0xE0,
2672 0x32, 0x00,
2673
2674 0x00, 0x80, 0x00, 0xE8,
2675 0x27, 0xC0, 0x44, 0xC0,
2676
2677 0x36, 0x1F, 0x4F, 0xE9,
2678 0x1F, 0x1F, 0x26, 0xDF,
2679
2680 0x37, 0x1B, 0x37, 0xBF,
2681 0x17, 0x26, 0x17, 0xDF,
2682
2683 0x3E, 0x17, 0x4F, 0xE9,
2684 0x3F, 0x3F, 0x4F, 0xE9,
2685
2686 0x34, 0x1F, 0x34, 0xAF,
2687 0x2B, 0x05,
2688 0xA7, 0x20,
2689
2690 0x33, 0x2B, 0x37, 0xDF,
2691 0x27, 0x17, 0xC0, 0xAF,
2692
2693 0x34, 0x80, 0x4F, 0xE9,
2694 0x00, 0x80, 0x00, 0xE8,
2695
2696 0x2D, 0x21, 0x1A, 0xB0,
2697 0x25, 0x21, 0x31, 0xB0,
2698
2699 0x0D, 0x21, 0x1A, 0xB2,
2700 0x05, 0x21, 0x31, 0xB2,
2701
2702 0x03, 0x80, 0x2A, 0xEA,
2703 0x17, 0xC1, 0x2B, 0xBD,
2704
2705 0x2D, 0x20,
2706 0x25, 0x20,
2707 0x05, 0x20,
2708 0x0D, 0x20,
2709
2710 0xB3, 0x68,
2711 0x97, 0x25,
2712 0x00, 0x80, 0x00, 0xE8,
2713
2714 0x33, 0xC0, 0x33, 0xAF,
2715 0x2F, 0xC0, 0x21, 0xC0,
2716
2717 0x16, 0x42, 0x56, 0x9F,
2718 0x3C, 0x27, 0x4F, 0xE9,
2719
2720 0x1E, 0x62, 0x57, 0x9F,
2721 0x00, 0x80, 0x00, 0xE8,
2722
2723 0x25, 0x21, 0x31, 0xB4,
2724 0x2D, 0x21, 0x1A, 0xB4,
2725
2726 0x3F, 0x2F, 0x5D, 0x9F,
2727 0x00, 0x80, 0x00, 0xE8,
2728
2729 0x33, 0x05,
2730 0x00, 0xE0,
2731 0x28, 0x19, 0x60, 0xEC,
2732
2733 0x37, 0x0F, 0x5C, 0x9F,
2734 0x00, 0xE0,
2735 0x2F, 0x20,
2736
2737 0x23, 0x3B, 0x33, 0xAD,
2738 0x1E, 0x26, 0x1E, 0xDF,
2739
2740 0xA7, 0x1E, 0x4F, 0xE9,
2741 0x17, 0x26, 0x16, 0xDF,
2742
2743 0x2D, 0x20,
2744 0x00, 0xE0,
2745 0xA8, 0x3F, 0x4F, 0xE9,
2746
2747 0x2F, 0x2F, 0x1E, 0xAF,
2748 0x25, 0x20,
2749 0x00, 0xE0,
2750
2751 0xA4, 0x16, 0x4F, 0xE9,
2752 0x0F, 0xC0, 0x21, 0xC2,
2753
2754 0xA6, 0x80, 0x4F, 0xE9,
2755 0x1F, 0x62, 0x57, 0x9F,
2756
2757 0x3F, 0x2F, 0x5D, 0x9F,
2758 0x00, 0xE0,
2759 0x8F, 0x20,
2760
2761 0xA5, 0x37, 0x4F, 0xE9,
2762 0x0F, 0x17, 0x0F, 0xAF,
2763
2764 0x06, 0xC0, 0x21, 0xC4,
2765 0x00, 0x80, 0x00, 0xE8,
2766
2767 0x00, 0x80, 0x00, 0xE8,
2768 0xA3, 0x80, 0x4F, 0xE9,
2769
2770 0x06, 0x20,
2771 0x00, 0xE0,
2772 0x1F, 0x26, 0x1F, 0xDF,
2773
2774 0xA1, 0x1F, 0x4F, 0xE9,
2775 0xA2, 0x3F, 0x4F, 0xE9,
2776
2777 0x00, 0x80, 0x00, 0xE8,
2778 0x00, 0x80, 0x00, 0xE8,
2779
2780 0x06, 0x06, 0x1F, 0xAF,
2781 0x00, 0x80, 0x00, 0xE8,
2782
2783 0x00, 0x80, 0x00, 0xE8,
2784 0x00, 0x80, 0x00, 0xE8,
2785
2786 0xA0, 0x80, 0x4F, 0xE9,
2787 0x00, 0x80, 0x00, 0xE8,
2788
2789 0x00, 0x80, 0x00, 0xE8,
2790 0x57, 0x39, 0x20, 0xE9,
2791
2792 0x16, 0x28, 0x20, 0xE9,
2793 0x1D, 0x3B, 0x20, 0xE9,
2794
2795 0x1E, 0x2B, 0x20, 0xE9,
2796 0x2B, 0x32, 0x20, 0xE9,
2797
2798 0x1C, 0x23, 0x20, 0xE9,
2799 0x57, 0x36, 0x20, 0xE9,
2800
2801 0x00, 0x80, 0xA0, 0xE9,
2802 0x40, 0x40, 0xD8, 0xEC,
2803
2804 0xFF, 0x80, 0xC0, 0xE9,
2805 0x90, 0xE2,
2806 0x00, 0xE0,
2807
2808 0x6C, 0xFF, 0x20, 0xEA,
2809 0x19, 0xC8, 0xC1, 0xCD,
2810
2811 0x1F, 0xD7, 0x18, 0xBD,
2812 0x3F, 0xD7, 0x22, 0xBD,
2813
2814 0x9F, 0x41, 0x49, 0xBD,
2815 0x00, 0x80, 0x00, 0xE8,
2816
2817 0x25, 0x41, 0x49, 0xBD,
2818 0x2D, 0x41, 0x51, 0xBD,
2819
2820 0x0D, 0x80, 0x07, 0xEA,
2821 0x00, 0x80, 0x00, 0xE8,
2822
2823 0x35, 0x40, 0x48, 0xBD,
2824 0x3D, 0x40, 0x50, 0xBD,
2825
2826 0x00, 0x80, 0x00, 0xE8,
2827 0x25, 0x30,
2828 0x2D, 0x30,
2829
2830 0x35, 0x30,
2831 0xB5, 0x30,
2832 0xBD, 0x30,
2833 0x3D, 0x30,
2834
2835 0x9C, 0xA7, 0x5B, 0x9F,
2836 0x00, 0x80, 0x00, 0xE8,
2837
2838 0x00, 0x80, 0x00, 0xE8,
2839 0x00, 0x80, 0x00, 0xE8,
2840
2841 0x00, 0x80, 0x00, 0xE8,
2842 0x00, 0x80, 0x00, 0xE8,
2843
2844 0x00, 0x80, 0x00, 0xE8,
2845 0x00, 0x80, 0x00, 0xE8,
2846
2847 0x00, 0x80, 0x00, 0xE8,
2848 0x00, 0x80, 0x00, 0xE8,
2849
2850 0x6B, 0xFF, 0x0A, 0xEA,
2851 0x00, 0x80, 0x00, 0xE8,
2852
2853 0xC9, 0x41, 0xC8, 0xEC,
2854 0x42, 0xE1,
2855 0x00, 0xE0,
2856
2857 0x69, 0xFF, 0x20, 0xEA,
2858 0x00, 0x80, 0x00, 0xE8,
2859
2860 0x00, 0x80, 0x00, 0xE8,
2861 0x00, 0x80, 0x00, 0xE8,
2862
2863 0xC8, 0x40, 0xC0, 0xEC,
2864 0x00, 0x80, 0x00, 0xE8,
2865
2866 0x66, 0xFF, 0x20, 0xEA,
2867 0x00, 0x80, 0x00, 0xE8,
2868
2869 0x00, 0x80, 0x00, 0xE8,
2870 0x00, 0x80, 0x00, 0xE8,
2871
2872};
2873
2874static unsigned char warp_g200_tgzsa[] = {
2875
2876 0x00, 0x80, 0x00, 0xE8,
2877 0x00, 0x80, 0x00, 0xE8,
2878
2879 0x00, 0x80, 0x00, 0xE8,
2880 0x00, 0x80, 0x00, 0xE8,
2881
2882 0x00, 0x80, 0x00, 0xE8,
2883 0x00, 0x80, 0x00, 0xE8,
2884
2885 0x00, 0x80, 0x00, 0xE8,
2886 0x00, 0x80, 0x00, 0xE8,
2887
2888 0x00, 0x80, 0x00, 0xE8,
2889 0x00, 0x80, 0x00, 0xE8,
2890
2891 0x00, 0x80, 0x00, 0xE8,
2892 0x00, 0x80, 0x00, 0xE8,
2893
2894 0x00, 0x80, 0x00, 0xE8,
2895 0x00, 0x80, 0x00, 0xE8,
2896
2897 0x00, 0x80, 0x00, 0xE8,
2898 0x00, 0x80, 0x00, 0xE8,
2899
2900 0x00, 0x80, 0x00, 0xE8,
2901 0x00, 0x80, 0x00, 0xE8,
2902
2903 0x00, 0x80, 0x00, 0xE8,
2904 0x00, 0x80, 0x00, 0xE8,
2905
2906 0x00, 0x80, 0x00, 0xE8,
2907 0x00, 0x80, 0x00, 0xE8,
2908
2909 0x00, 0x80, 0x00, 0xE8,
2910 0x00, 0x80, 0x00, 0xE8,
2911
2912 0x00, 0x80, 0x00, 0xE8,
2913 0x00, 0x80, 0x00, 0xE8,
2914
2915 0x00, 0x98, 0xA0, 0xE9,
2916 0x40, 0x40, 0xD8, 0xEC,
2917
2918 0xFF, 0x80, 0xC0, 0xE9,
2919 0x00, 0x80, 0x00, 0xE8,
2920
2921 0x1F, 0xD7, 0x18, 0xBD,
2922 0x3F, 0xD7, 0x22, 0xBD,
2923
2924 0x81, 0x04,
2925 0x89, 0x04,
2926 0x01, 0x04,
2927 0x09, 0x04,
2928
2929 0xC9, 0x41, 0xC0, 0xEC,
2930 0x11, 0x04,
2931 0x00, 0xE0,
2932
2933 0x41, 0xCC, 0x41, 0xCD,
2934 0x49, 0xCC, 0x49, 0xCD,
2935
2936 0xD1, 0x41, 0xC0, 0xEC,
2937 0x51, 0xCC, 0x51, 0xCD,
2938
2939 0x80, 0x04,
2940 0x10, 0x04,
2941 0x08, 0x04,
2942 0x00, 0xE0,
2943
2944 0x00, 0xCC, 0xC0, 0xCD,
2945 0xD1, 0x49, 0xC0, 0xEC,
2946
2947 0x8A, 0x1F, 0x20, 0xE9,
2948 0x8B, 0x3F, 0x20, 0xE9,
2949
2950 0x41, 0x3C, 0x41, 0xAD,
2951 0x49, 0x3C, 0x49, 0xAD,
2952
2953 0x10, 0xCC, 0x10, 0xCD,
2954 0x08, 0xCC, 0x08, 0xCD,
2955
2956 0xB9, 0x41, 0x49, 0xBB,
2957 0x1F, 0xF0, 0x41, 0xCD,
2958
2959 0x51, 0x3C, 0x51, 0xAD,
2960 0x00, 0x98, 0x80, 0xE9,
2961
2962 0x8F, 0x80, 0x07, 0xEA,
2963 0x24, 0x1F, 0x20, 0xE9,
2964
2965 0x21, 0x45, 0x80, 0xE8,
2966 0x1A, 0x4D, 0x80, 0xE8,
2967
2968 0x31, 0x55, 0x80, 0xE8,
2969 0x00, 0x80, 0x00, 0xE8,
2970
2971 0x15, 0x41, 0x49, 0xBD,
2972 0x1D, 0x41, 0x51, 0xBD,
2973
2974 0x2E, 0x41, 0x2A, 0xB8,
2975 0x34, 0x53, 0xA0, 0xE8,
2976
2977 0x15, 0x30,
2978 0x1D, 0x30,
2979 0x58, 0xE3,
2980 0x00, 0xE0,
2981
2982 0xB5, 0x40, 0x48, 0xBD,
2983 0x3D, 0x40, 0x50, 0xBD,
2984
2985 0x24, 0x43, 0xA0, 0xE8,
2986 0x2C, 0x4B, 0xA0, 0xE8,
2987
2988 0x15, 0x72,
2989 0x09, 0xE3,
2990 0x00, 0xE0,
2991 0x1D, 0x72,
2992
2993 0x35, 0x30,
2994 0xB5, 0x30,
2995 0xBD, 0x30,
2996 0x3D, 0x30,
2997
2998 0x9C, 0x97, 0x57, 0x9F,
2999 0x00, 0x80, 0x00, 0xE8,
3000
3001 0x6C, 0x64, 0xC8, 0xEC,
3002 0x98, 0xE1,
3003 0xB5, 0x05,
3004
3005 0xBD, 0x05,
3006 0x2E, 0x30,
3007 0x32, 0xC0, 0xA0, 0xE8,
3008
3009 0x33, 0xC0, 0xA0, 0xE8,
3010 0x74, 0x64, 0xC8, 0xEC,
3011
3012 0x40, 0x3C, 0x40, 0xAD,
3013 0x32, 0x6A,
3014 0x2A, 0x30,
3015
3016 0x20, 0x73,
3017 0x33, 0x6A,
3018 0x00, 0xE0,
3019 0x28, 0x73,
3020
3021 0x1C, 0x72,
3022 0x83, 0xE2,
3023 0x7B, 0x80, 0x15, 0xEA,
3024
3025 0xB8, 0x3D, 0x28, 0xDF,
3026 0x30, 0x35, 0x20, 0xDF,
3027
3028 0x40, 0x30,
3029 0x00, 0xE0,
3030 0xCC, 0xE2,
3031 0x64, 0x72,
3032
3033 0x25, 0x42, 0x52, 0xBF,
3034 0x2D, 0x42, 0x4A, 0xBF,
3035
3036 0x30, 0x2E, 0x30, 0xDF,
3037 0x38, 0x2E, 0x38, 0xDF,
3038
3039 0x18, 0x1D, 0x45, 0xE9,
3040 0x1E, 0x15, 0x45, 0xE9,
3041
3042 0x2B, 0x49, 0x51, 0xBD,
3043 0x00, 0xE0,
3044 0x1F, 0x73,
3045
3046 0x38, 0x38, 0x40, 0xAF,
3047 0x30, 0x30, 0x40, 0xAF,
3048
3049 0x24, 0x1F, 0x24, 0xDF,
3050 0x1D, 0x32, 0x20, 0xE9,
3051
3052 0x2C, 0x1F, 0x2C, 0xDF,
3053 0x1A, 0x33, 0x20, 0xE9,
3054
3055 0xB0, 0x10,
3056 0x08, 0xE3,
3057 0x40, 0x10,
3058 0xB8, 0x10,
3059
3060 0x26, 0xF0, 0x30, 0xCD,
3061 0x2F, 0xF0, 0x38, 0xCD,
3062
3063 0x2B, 0x80, 0x20, 0xE9,
3064 0x2A, 0x80, 0x20, 0xE9,
3065
3066 0xA6, 0x20,
3067 0x88, 0xE2,
3068 0x00, 0xE0,
3069 0xAF, 0x20,
3070
3071 0x28, 0x2A, 0x26, 0xAF,
3072 0x20, 0x2A, 0xC0, 0xAF,
3073
3074 0x34, 0x1F, 0x34, 0xDF,
3075 0x46, 0x24, 0x46, 0xDF,
3076
3077 0x28, 0x30, 0x80, 0xBF,
3078 0x20, 0x38, 0x80, 0xBF,
3079
3080 0x47, 0x24, 0x47, 0xDF,
3081 0x4E, 0x2C, 0x4E, 0xDF,
3082
3083 0x4F, 0x2C, 0x4F, 0xDF,
3084 0x56, 0x34, 0x56, 0xDF,
3085
3086 0x28, 0x15, 0x28, 0xDF,
3087 0x20, 0x1D, 0x20, 0xDF,
3088
3089 0x57, 0x34, 0x57, 0xDF,
3090 0x00, 0xE0,
3091 0x1D, 0x05,
3092
3093 0x04, 0x80, 0x10, 0xEA,
3094 0x89, 0xE2,
3095 0x2B, 0x30,
3096
3097 0x3F, 0xC1, 0x1D, 0xBD,
3098 0x00, 0x80, 0x00, 0xE8,
3099
3100 0x00, 0x80, 0x00, 0xE8,
3101 0x00, 0x80, 0x00, 0xE8,
3102
3103 0xA0, 0x68,
3104 0xBF, 0x25,
3105 0x00, 0x80, 0x00, 0xE8,
3106
3107 0x20, 0xC0, 0x20, 0xAF,
3108 0x28, 0x05,
3109 0x97, 0x74,
3110
3111 0x00, 0xE0,
3112 0x2A, 0x10,
3113 0x16, 0xC0, 0x20, 0xE9,
3114
3115 0x04, 0x80, 0x10, 0xEA,
3116 0x8C, 0xE2,
3117 0x95, 0x05,
3118
3119 0x28, 0xC1, 0x28, 0xAD,
3120 0x1F, 0xC1, 0x15, 0xBD,
3121
3122 0x00, 0x80, 0x00, 0xE8,
3123 0x00, 0x80, 0x00, 0xE8,
3124
3125 0xA8, 0x67,
3126 0x9F, 0x6B,
3127 0x00, 0x80, 0x00, 0xE8,
3128
3129 0x28, 0xC0, 0x28, 0xAD,
3130 0x1D, 0x25,
3131 0x20, 0x05,
3132
3133 0x28, 0x32, 0x80, 0xAD,
3134 0x40, 0x2A, 0x40, 0xBD,
3135
3136 0x1C, 0x80, 0x20, 0xE9,
3137 0x20, 0x33, 0x20, 0xAD,
3138
3139 0x20, 0x73,
3140 0x00, 0xE0,
3141 0xB6, 0x49, 0x51, 0xBB,
3142
3143 0x26, 0x2F, 0xB0, 0xE8,
3144 0x19, 0x20, 0x20, 0xE9,
3145
3146 0x35, 0x20, 0x35, 0xDF,
3147 0x3D, 0x20, 0x3D, 0xDF,
3148
3149 0x15, 0x20, 0x15, 0xDF,
3150 0x1D, 0x20, 0x1D, 0xDF,
3151
3152 0x26, 0xD0, 0x26, 0xCD,
3153 0x29, 0x49, 0x2A, 0xB8,
3154
3155 0x26, 0x40, 0x80, 0xBD,
3156 0x3B, 0x48, 0x50, 0xBD,
3157
3158 0x3E, 0x54, 0x57, 0x9F,
3159 0x00, 0xE0,
3160 0x82, 0xE1,
3161
3162 0x1E, 0xAF, 0x59, 0x9F,
3163 0x00, 0x80, 0x00, 0xE8,
3164
3165 0x26, 0x30,
3166 0x29, 0x30,
3167 0x48, 0x3C, 0x48, 0xAD,
3168
3169 0x2B, 0x72,
3170 0xC2, 0xE1,
3171 0x2C, 0xC0, 0x44, 0xC2,
3172
3173 0x05, 0x24, 0x34, 0xBF,
3174 0x0D, 0x24, 0x2C, 0xBF,
3175
3176 0x2D, 0x46, 0x4E, 0xBF,
3177 0x25, 0x46, 0x56, 0xBF,
3178
3179 0x20, 0x1D, 0x6F, 0x8F,
3180 0x32, 0x3E, 0x5F, 0xE9,
3181
3182 0x3E, 0x50, 0x56, 0x9F,
3183 0x00, 0xE0,
3184 0x3B, 0x30,
3185
3186 0x1E, 0x8F, 0x51, 0x9F,
3187 0x33, 0x1E, 0x5F, 0xE9,
3188
3189 0x05, 0x44, 0x54, 0xB2,
3190 0x0D, 0x44, 0x4C, 0xB2,
3191
3192 0x19, 0xC0, 0xB0, 0xE8,
3193 0x34, 0xC0, 0x44, 0xC4,
3194
3195 0x33, 0x73,
3196 0x00, 0xE0,
3197 0x3E, 0x62, 0x57, 0x9F,
3198
3199 0x1E, 0xAF, 0x59, 0x9F,
3200 0x00, 0xE0,
3201 0x0D, 0x20,
3202
3203 0x84, 0x3E, 0x58, 0xE9,
3204 0x28, 0x1D, 0x6F, 0x8F,
3205
3206 0x05, 0x20,
3207 0x00, 0xE0,
3208 0x85, 0x1E, 0x58, 0xE9,
3209
3210 0x9B, 0x3B, 0x33, 0xDF,
3211 0x20, 0x20, 0x42, 0xAF,
3212
3213 0x30, 0x42, 0x56, 0x9F,
3214 0x80, 0x3E, 0x57, 0xE9,
3215
3216 0x3F, 0x8F, 0x51, 0x9F,
3217 0x30, 0x80, 0x5F, 0xE9,
3218
3219 0x28, 0x28, 0x24, 0xAF,
3220 0x81, 0x1E, 0x57, 0xE9,
3221
3222 0x05, 0x47, 0x57, 0xBF,
3223 0x0D, 0x47, 0x4F, 0xBF,
3224
3225 0x88, 0x80, 0x58, 0xE9,
3226 0x1B, 0x29, 0x1B, 0xDF,
3227
3228 0x30, 0x1D, 0x6F, 0x8F,
3229 0x3A, 0x30, 0x4F, 0xE9,
3230
3231 0x1C, 0x30, 0x26, 0xDF,
3232 0x09, 0xE3,
3233 0x3B, 0x05,
3234
3235 0x3E, 0x50, 0x56, 0x9F,
3236 0x3B, 0x3F, 0x4F, 0xE9,
3237
3238 0x1E, 0x8F, 0x51, 0x9F,
3239 0x00, 0xE0,
3240 0xAC, 0x20,
3241
3242 0x2D, 0x44, 0x4C, 0xB4,
3243 0x2C, 0x1C, 0xC0, 0xAF,
3244
3245 0x25, 0x44, 0x54, 0xB4,
3246 0x00, 0xE0,
3247 0xC8, 0x30,
3248
3249 0x30, 0x46, 0x30, 0xAF,
3250 0x1B, 0x1B, 0x48, 0xAF,
3251
3252 0x00, 0xE0,
3253 0x25, 0x20,
3254 0x38, 0x2C, 0x4F, 0xE9,
3255
3256 0x86, 0x80, 0x57, 0xE9,
3257 0x38, 0x1D, 0x6F, 0x8F,
3258
3259 0x28, 0x74,
3260 0x00, 0xE0,
3261 0x0D, 0x44, 0x4C, 0xB0,
3262
3263 0x05, 0x44, 0x54, 0xB0,
3264 0x2D, 0x20,
3265 0x9B, 0x10,
3266
3267 0x82, 0x3E, 0x57, 0xE9,
3268 0x32, 0xF0, 0x1B, 0xCD,
3269
3270 0x1E, 0xBD, 0x59, 0x9F,
3271 0x83, 0x1E, 0x57, 0xE9,
3272
3273 0x38, 0x47, 0x38, 0xAF,
3274 0x34, 0x20,
3275 0x2A, 0x30,
3276
3277 0x00, 0xE0,
3278 0x0D, 0x20,
3279 0x32, 0x20,
3280 0x05, 0x20,
3281
3282 0x87, 0x80, 0x57, 0xE9,
3283 0x1F, 0x54, 0x57, 0x9F,
3284
3285 0x17, 0x42, 0x56, 0x9F,
3286 0x00, 0xE0,
3287 0x3B, 0x6A,
3288
3289 0x3F, 0x8F, 0x51, 0x9F,
3290 0x37, 0x1E, 0x4F, 0xE9,
3291
3292 0x37, 0x32, 0x2A, 0xAF,
3293 0x00, 0xE0,
3294 0x32, 0x00,
3295
3296 0x00, 0x80, 0x00, 0xE8,
3297 0x27, 0xC0, 0x44, 0xC0,
3298
3299 0x36, 0x1F, 0x4F, 0xE9,
3300 0x1F, 0x1F, 0x26, 0xDF,
3301
3302 0x37, 0x1B, 0x37, 0xBF,
3303 0x17, 0x26, 0x17, 0xDF,
3304
3305 0x3E, 0x17, 0x4F, 0xE9,
3306 0x3F, 0x3F, 0x4F, 0xE9,
3307
3308 0x34, 0x1F, 0x34, 0xAF,
3309 0x2B, 0x05,
3310 0xA7, 0x20,
3311
3312 0x33, 0x2B, 0x37, 0xDF,
3313 0x27, 0x17, 0xC0, 0xAF,
3314
3315 0x34, 0x80, 0x4F, 0xE9,
3316 0x00, 0x80, 0x00, 0xE8,
3317
3318 0x2D, 0x21, 0x1A, 0xB0,
3319 0x25, 0x21, 0x31, 0xB0,
3320
3321 0x0D, 0x21, 0x1A, 0xB2,
3322 0x05, 0x21, 0x31, 0xB2,
3323
3324 0x03, 0x80, 0x2A, 0xEA,
3325 0x17, 0xC1, 0x2B, 0xBD,
3326
3327 0x2D, 0x20,
3328 0x25, 0x20,
3329 0x05, 0x20,
3330 0x0D, 0x20,
3331
3332 0xB3, 0x68,
3333 0x97, 0x25,
3334 0x00, 0x80, 0x00, 0xE8,
3335
3336 0x33, 0xC0, 0x33, 0xAF,
3337 0x2F, 0xC0, 0x21, 0xC0,
3338
3339 0x16, 0x42, 0x56, 0x9F,
3340 0x3C, 0x27, 0x4F, 0xE9,
3341
3342 0x1E, 0x62, 0x57, 0x9F,
3343 0x00, 0x80, 0x00, 0xE8,
3344
3345 0x25, 0x21, 0x31, 0xB4,
3346 0x2D, 0x21, 0x1A, 0xB4,
3347
3348 0x3F, 0x2F, 0x5D, 0x9F,
3349 0x00, 0x80, 0x00, 0xE8,
3350
3351 0x33, 0x05,
3352 0x00, 0xE0,
3353 0x28, 0x19, 0x60, 0xEC,
3354
3355 0x0D, 0x44, 0x4C, 0xB6,
3356 0x05, 0x44, 0x54, 0xB6,
3357
3358 0x37, 0x0F, 0x5C, 0x9F,
3359 0x00, 0xE0,
3360 0x2F, 0x20,
3361
3362 0x23, 0x3B, 0x33, 0xAD,
3363 0x1E, 0x26, 0x1E, 0xDF,
3364
3365 0xA7, 0x1E, 0x4F, 0xE9,
3366 0x17, 0x26, 0x16, 0xDF,
3367
3368 0x2D, 0x20,
3369 0x00, 0xE0,
3370 0xA8, 0x3F, 0x4F, 0xE9,
3371
3372 0x2F, 0x2F, 0x1E, 0xAF,
3373 0x25, 0x20,
3374 0x00, 0xE0,
3375
3376 0xA4, 0x16, 0x4F, 0xE9,
3377 0x0F, 0xC0, 0x21, 0xC2,
3378
3379 0xA6, 0x80, 0x4F, 0xE9,
3380 0x1F, 0x62, 0x57, 0x9F,
3381
3382 0x0D, 0x20,
3383 0x05, 0x20,
3384 0x00, 0x80, 0x00, 0xE8,
3385
3386 0x3F, 0x2F, 0x5D, 0x9F,
3387 0x00, 0xE0,
3388 0x0F, 0x20,
3389
3390 0x17, 0x50, 0x56, 0x9F,
3391 0xA5, 0x37, 0x4F, 0xE9,
3392
3393 0x06, 0xC0, 0x21, 0xC4,
3394 0x0F, 0x17, 0x0F, 0xAF,
3395
3396 0x37, 0x0F, 0x5C, 0x9F,
3397 0x00, 0x80, 0x00, 0xE8,
3398
3399 0x2F, 0xC0, 0x44, 0xC6,
3400 0xA3, 0x80, 0x4F, 0xE9,
3401
3402 0x06, 0x20,
3403 0x00, 0xE0,
3404 0x1F, 0x26, 0x1F, 0xDF,
3405
3406 0x17, 0x26, 0x17, 0xDF,
3407 0x9D, 0x17, 0x4F, 0xE9,
3408
3409 0xA1, 0x1F, 0x4F, 0xE9,
3410 0xA2, 0x3F, 0x4F, 0xE9,
3411
3412 0x06, 0x06, 0x1F, 0xAF,
3413 0x00, 0xE0,
3414 0xAF, 0x20,
3415
3416 0x9E, 0x37, 0x4F, 0xE9,
3417 0x2F, 0x17, 0x2F, 0xAF,
3418
3419 0xA0, 0x80, 0x4F, 0xE9,
3420 0x00, 0x80, 0x00, 0xE8,
3421
3422 0x00, 0x80, 0x00, 0xE8,
3423 0x9C, 0x80, 0x4F, 0xE9,
3424
3425 0x00, 0x80, 0x00, 0xE8,
3426 0x57, 0x39, 0x20, 0xE9,
3427
3428 0x16, 0x28, 0x20, 0xE9,
3429 0x1D, 0x3B, 0x20, 0xE9,
3430
3431 0x1E, 0x2B, 0x20, 0xE9,
3432 0x2B, 0x32, 0x20, 0xE9,
3433
3434 0x1C, 0x23, 0x20, 0xE9,
3435 0x57, 0x36, 0x20, 0xE9,
3436
3437 0x00, 0x80, 0xA0, 0xE9,
3438 0x40, 0x40, 0xD8, 0xEC,
3439
3440 0xFF, 0x80, 0xC0, 0xE9,
3441 0x90, 0xE2,
3442 0x00, 0xE0,
3443
3444 0x68, 0xFF, 0x20, 0xEA,
3445 0x19, 0xC8, 0xC1, 0xCD,
3446
3447 0x1F, 0xD7, 0x18, 0xBD,
3448 0x3F, 0xD7, 0x22, 0xBD,
3449
3450 0x9F, 0x41, 0x49, 0xBD,
3451 0x00, 0x80, 0x00, 0xE8,
3452
3453 0x25, 0x41, 0x49, 0xBD,
3454 0x2D, 0x41, 0x51, 0xBD,
3455
3456 0x0D, 0x80, 0x07, 0xEA,
3457 0x00, 0x80, 0x00, 0xE8,
3458
3459 0x35, 0x40, 0x48, 0xBD,
3460 0x3D, 0x40, 0x50, 0xBD,
3461
3462 0x00, 0x80, 0x00, 0xE8,
3463 0x25, 0x30,
3464 0x2D, 0x30,
3465
3466 0x35, 0x30,
3467 0xB5, 0x30,
3468 0xBD, 0x30,
3469 0x3D, 0x30,
3470
3471 0x9C, 0xA7, 0x5B, 0x9F,
3472 0x00, 0x80, 0x00, 0xE8,
3473
3474 0x00, 0x80, 0x00, 0xE8,
3475 0x00, 0x80, 0x00, 0xE8,
3476
3477 0x00, 0x80, 0x00, 0xE8,
3478 0x00, 0x80, 0x00, 0xE8,
3479
3480 0x00, 0x80, 0x00, 0xE8,
3481 0x00, 0x80, 0x00, 0xE8,
3482
3483 0x00, 0x80, 0x00, 0xE8,
3484 0x00, 0x80, 0x00, 0xE8,
3485
3486 0x67, 0xFF, 0x0A, 0xEA,
3487 0x00, 0x80, 0x00, 0xE8,
3488
3489 0xC9, 0x41, 0xC8, 0xEC,
3490 0x42, 0xE1,
3491 0x00, 0xE0,
3492
3493 0x65, 0xFF, 0x20, 0xEA,
3494 0x00, 0x80, 0x00, 0xE8,
3495
3496 0x00, 0x80, 0x00, 0xE8,
3497 0x00, 0x80, 0x00, 0xE8,
3498
3499 0xC8, 0x40, 0xC0, 0xEC,
3500 0x00, 0x80, 0x00, 0xE8,
3501
3502 0x62, 0xFF, 0x20, 0xEA,
3503 0x00, 0x80, 0x00, 0xE8,
3504
3505 0x00, 0x80, 0x00, 0xE8,
3506 0x00, 0x80, 0x00, 0xE8,
3507
3508};
3509
3510static unsigned char warp_g200_tgzsaf[] = {
3511
3512 0x00, 0x80, 0x00, 0xE8,
3513 0x00, 0x80, 0x00, 0xE8,
3514
3515 0x00, 0x80, 0x00, 0xE8,
3516 0x00, 0x80, 0x00, 0xE8,
3517
3518 0x00, 0x80, 0x00, 0xE8,
3519 0x00, 0x80, 0x00, 0xE8,
3520
3521 0x00, 0x98, 0xA0, 0xE9,
3522 0x40, 0x40, 0xD8, 0xEC,
3523
3524 0xFF, 0x80, 0xC0, 0xE9,
3525 0x00, 0x80, 0x00, 0xE8,
3526
3527 0x1F, 0xD7, 0x18, 0xBD,
3528 0x3F, 0xD7, 0x22, 0xBD,
3529
3530 0x81, 0x04,
3531 0x89, 0x04,
3532 0x01, 0x04,
3533 0x09, 0x04,
3534
3535 0xC9, 0x41, 0xC0, 0xEC,
3536 0x11, 0x04,
3537 0x00, 0xE0,
3538
3539 0x41, 0xCC, 0x41, 0xCD,
3540 0x49, 0xCC, 0x49, 0xCD,
3541
3542 0xD1, 0x41, 0xC0, 0xEC,
3543 0x51, 0xCC, 0x51, 0xCD,
3544
3545 0x80, 0x04,
3546 0x10, 0x04,
3547 0x08, 0x04,
3548 0x00, 0xE0,
3549
3550 0x00, 0xCC, 0xC0, 0xCD,
3551 0xD1, 0x49, 0xC0, 0xEC,
3552
3553 0x8A, 0x1F, 0x20, 0xE9,
3554 0x8B, 0x3F, 0x20, 0xE9,
3555
3556 0x41, 0x3C, 0x41, 0xAD,
3557 0x49, 0x3C, 0x49, 0xAD,
3558
3559 0x10, 0xCC, 0x10, 0xCD,
3560 0x08, 0xCC, 0x08, 0xCD,
3561
3562 0xB9, 0x41, 0x49, 0xBB,
3563 0x1F, 0xF0, 0x41, 0xCD,
3564
3565 0x51, 0x3C, 0x51, 0xAD,
3566 0x00, 0x98, 0x80, 0xE9,
3567
3568 0x94, 0x80, 0x07, 0xEA,
3569 0x24, 0x1F, 0x20, 0xE9,
3570
3571 0x21, 0x45, 0x80, 0xE8,
3572 0x1A, 0x4D, 0x80, 0xE8,
3573
3574 0x31, 0x55, 0x80, 0xE8,
3575 0x00, 0x80, 0x00, 0xE8,
3576
3577 0x15, 0x41, 0x49, 0xBD,
3578 0x1D, 0x41, 0x51, 0xBD,
3579
3580 0x2E, 0x41, 0x2A, 0xB8,
3581 0x34, 0x53, 0xA0, 0xE8,
3582
3583 0x15, 0x30,
3584 0x1D, 0x30,
3585 0x58, 0xE3,
3586 0x00, 0xE0,
3587
3588 0xB5, 0x40, 0x48, 0xBD,
3589 0x3D, 0x40, 0x50, 0xBD,
3590
3591 0x24, 0x43, 0xA0, 0xE8,
3592 0x2C, 0x4B, 0xA0, 0xE8,
3593
3594 0x15, 0x72,
3595 0x09, 0xE3,
3596 0x00, 0xE0,
3597 0x1D, 0x72,
3598
3599 0x35, 0x30,
3600 0xB5, 0x30,
3601 0xBD, 0x30,
3602 0x3D, 0x30,
3603
3604 0x9C, 0x97, 0x57, 0x9F,
3605 0x00, 0x80, 0x00, 0xE8,
3606
3607 0x6C, 0x64, 0xC8, 0xEC,
3608 0x98, 0xE1,
3609 0xB5, 0x05,
3610
3611 0xBD, 0x05,
3612 0x2E, 0x30,
3613 0x32, 0xC0, 0xA0, 0xE8,
3614
3615 0x33, 0xC0, 0xA0, 0xE8,
3616 0x74, 0x64, 0xC8, 0xEC,
3617
3618 0x40, 0x3C, 0x40, 0xAD,
3619 0x32, 0x6A,
3620 0x2A, 0x30,
3621
3622 0x20, 0x73,
3623 0x33, 0x6A,
3624 0x00, 0xE0,
3625 0x28, 0x73,
3626
3627 0x1C, 0x72,
3628 0x83, 0xE2,
3629 0x80, 0x80, 0x15, 0xEA,
3630
3631 0xB8, 0x3D, 0x28, 0xDF,
3632 0x30, 0x35, 0x20, 0xDF,
3633
3634 0x40, 0x30,
3635 0x00, 0xE0,
3636 0xCC, 0xE2,
3637 0x64, 0x72,
3638
3639 0x25, 0x42, 0x52, 0xBF,
3640 0x2D, 0x42, 0x4A, 0xBF,
3641
3642 0x30, 0x2E, 0x30, 0xDF,
3643 0x38, 0x2E, 0x38, 0xDF,
3644
3645 0x18, 0x1D, 0x45, 0xE9,
3646 0x1E, 0x15, 0x45, 0xE9,
3647
3648 0x2B, 0x49, 0x51, 0xBD,
3649 0x00, 0xE0,
3650 0x1F, 0x73,
3651
3652 0x38, 0x38, 0x40, 0xAF,
3653 0x30, 0x30, 0x40, 0xAF,
3654
3655 0x24, 0x1F, 0x24, 0xDF,
3656 0x1D, 0x32, 0x20, 0xE9,
3657
3658 0x2C, 0x1F, 0x2C, 0xDF,
3659 0x1A, 0x33, 0x20, 0xE9,
3660
3661 0xB0, 0x10,
3662 0x08, 0xE3,
3663 0x40, 0x10,
3664 0xB8, 0x10,
3665
3666 0x26, 0xF0, 0x30, 0xCD,
3667 0x2F, 0xF0, 0x38, 0xCD,
3668
3669 0x2B, 0x80, 0x20, 0xE9,
3670 0x2A, 0x80, 0x20, 0xE9,
3671
3672 0xA6, 0x20,
3673 0x88, 0xE2,
3674 0x00, 0xE0,
3675 0xAF, 0x20,
3676
3677 0x28, 0x2A, 0x26, 0xAF,
3678 0x20, 0x2A, 0xC0, 0xAF,
3679
3680 0x34, 0x1F, 0x34, 0xDF,
3681 0x46, 0x24, 0x46, 0xDF,
3682
3683 0x28, 0x30, 0x80, 0xBF,
3684 0x20, 0x38, 0x80, 0xBF,
3685
3686 0x47, 0x24, 0x47, 0xDF,
3687 0x4E, 0x2C, 0x4E, 0xDF,
3688
3689 0x4F, 0x2C, 0x4F, 0xDF,
3690 0x56, 0x34, 0x56, 0xDF,
3691
3692 0x28, 0x15, 0x28, 0xDF,
3693 0x20, 0x1D, 0x20, 0xDF,
3694
3695 0x57, 0x34, 0x57, 0xDF,
3696 0x00, 0xE0,
3697 0x1D, 0x05,
3698
3699 0x04, 0x80, 0x10, 0xEA,
3700 0x89, 0xE2,
3701 0x2B, 0x30,
3702
3703 0x3F, 0xC1, 0x1D, 0xBD,
3704 0x00, 0x80, 0x00, 0xE8,
3705
3706 0x00, 0x80, 0x00, 0xE8,
3707 0x00, 0x80, 0x00, 0xE8,
3708
3709 0xA0, 0x68,
3710 0xBF, 0x25,
3711 0x00, 0x80, 0x00, 0xE8,
3712
3713 0x20, 0xC0, 0x20, 0xAF,
3714 0x28, 0x05,
3715 0x97, 0x74,
3716
3717 0x00, 0xE0,
3718 0x2A, 0x10,
3719 0x16, 0xC0, 0x20, 0xE9,
3720
3721 0x04, 0x80, 0x10, 0xEA,
3722 0x8C, 0xE2,
3723 0x95, 0x05,
3724
3725 0x28, 0xC1, 0x28, 0xAD,
3726 0x1F, 0xC1, 0x15, 0xBD,
3727
3728 0x00, 0x80, 0x00, 0xE8,
3729 0x00, 0x80, 0x00, 0xE8,
3730
3731 0xA8, 0x67,
3732 0x9F, 0x6B,
3733 0x00, 0x80, 0x00, 0xE8,
3734
3735 0x28, 0xC0, 0x28, 0xAD,
3736 0x1D, 0x25,
3737 0x20, 0x05,
3738
3739 0x28, 0x32, 0x80, 0xAD,
3740 0x40, 0x2A, 0x40, 0xBD,
3741
3742 0x1C, 0x80, 0x20, 0xE9,
3743 0x20, 0x33, 0x20, 0xAD,
3744
3745 0x20, 0x73,
3746 0x00, 0xE0,
3747 0xB6, 0x49, 0x51, 0xBB,
3748
3749 0x26, 0x2F, 0xB0, 0xE8,
3750 0x19, 0x20, 0x20, 0xE9,
3751
3752 0x35, 0x20, 0x35, 0xDF,
3753 0x3D, 0x20, 0x3D, 0xDF,
3754
3755 0x15, 0x20, 0x15, 0xDF,
3756 0x1D, 0x20, 0x1D, 0xDF,
3757
3758 0x26, 0xD0, 0x26, 0xCD,
3759 0x29, 0x49, 0x2A, 0xB8,
3760
3761 0x26, 0x40, 0x80, 0xBD,
3762 0x3B, 0x48, 0x50, 0xBD,
3763
3764 0x3E, 0x54, 0x57, 0x9F,
3765 0x00, 0xE0,
3766 0x82, 0xE1,
3767
3768 0x1E, 0xAF, 0x59, 0x9F,
3769 0x00, 0x80, 0x00, 0xE8,
3770
3771 0x26, 0x30,
3772 0x29, 0x30,
3773 0x48, 0x3C, 0x48, 0xAD,
3774
3775 0x2B, 0x72,
3776 0xC2, 0xE1,
3777 0x2C, 0xC0, 0x44, 0xC2,
3778
3779 0x05, 0x24, 0x34, 0xBF,
3780 0x0D, 0x24, 0x2C, 0xBF,
3781
3782 0x2D, 0x46, 0x4E, 0xBF,
3783 0x25, 0x46, 0x56, 0xBF,
3784
3785 0x20, 0x1D, 0x6F, 0x8F,
3786 0x32, 0x3E, 0x5F, 0xE9,
3787
3788 0x3E, 0x50, 0x56, 0x9F,
3789 0x00, 0xE0,
3790 0x3B, 0x30,
3791
3792 0x1E, 0x8F, 0x51, 0x9F,
3793 0x33, 0x1E, 0x5F, 0xE9,
3794
3795 0x05, 0x44, 0x54, 0xB2,
3796 0x0D, 0x44, 0x4C, 0xB2,
3797
3798 0x19, 0xC0, 0xB0, 0xE8,
3799 0x34, 0xC0, 0x44, 0xC4,
3800
3801 0x33, 0x73,
3802 0x00, 0xE0,
3803 0x3E, 0x62, 0x57, 0x9F,
3804
3805 0x1E, 0xAF, 0x59, 0x9F,
3806 0x00, 0xE0,
3807 0x0D, 0x20,
3808
3809 0x84, 0x3E, 0x58, 0xE9,
3810 0x28, 0x1D, 0x6F, 0x8F,
3811
3812 0x05, 0x20,
3813 0x00, 0xE0,
3814 0x85, 0x1E, 0x58, 0xE9,
3815
3816 0x9B, 0x3B, 0x33, 0xDF,
3817 0x20, 0x20, 0x42, 0xAF,
3818
3819 0x30, 0x42, 0x56, 0x9F,
3820 0x80, 0x3E, 0x57, 0xE9,
3821
3822 0x3F, 0x8F, 0x51, 0x9F,
3823 0x30, 0x80, 0x5F, 0xE9,
3824
3825 0x28, 0x28, 0x24, 0xAF,
3826 0x81, 0x1E, 0x57, 0xE9,
3827
3828 0x05, 0x47, 0x57, 0xBF,
3829 0x0D, 0x47, 0x4F, 0xBF,
3830
3831 0x88, 0x80, 0x58, 0xE9,
3832 0x1B, 0x29, 0x1B, 0xDF,
3833
3834 0x30, 0x1D, 0x6F, 0x8F,
3835 0x3A, 0x30, 0x4F, 0xE9,
3836
3837 0x1C, 0x30, 0x26, 0xDF,
3838 0x09, 0xE3,
3839 0x3B, 0x05,
3840
3841 0x3E, 0x50, 0x56, 0x9F,
3842 0x3B, 0x3F, 0x4F, 0xE9,
3843
3844 0x1E, 0x8F, 0x51, 0x9F,
3845 0x00, 0xE0,
3846 0xAC, 0x20,
3847
3848 0x2D, 0x44, 0x4C, 0xB4,
3849 0x2C, 0x1C, 0xC0, 0xAF,
3850
3851 0x25, 0x44, 0x54, 0xB4,
3852 0x00, 0xE0,
3853 0xC8, 0x30,
3854
3855 0x30, 0x46, 0x30, 0xAF,
3856 0x1B, 0x1B, 0x48, 0xAF,
3857
3858 0x00, 0xE0,
3859 0x25, 0x20,
3860 0x38, 0x2C, 0x4F, 0xE9,
3861
3862 0x86, 0x80, 0x57, 0xE9,
3863 0x38, 0x1D, 0x6F, 0x8F,
3864
3865 0x28, 0x74,
3866 0x00, 0xE0,
3867 0x0D, 0x44, 0x4C, 0xB0,
3868
3869 0x05, 0x44, 0x54, 0xB0,
3870 0x2D, 0x20,
3871 0x9B, 0x10,
3872
3873 0x82, 0x3E, 0x57, 0xE9,
3874 0x32, 0xF0, 0x1B, 0xCD,
3875
3876 0x1E, 0xBD, 0x59, 0x9F,
3877 0x83, 0x1E, 0x57, 0xE9,
3878
3879 0x38, 0x47, 0x38, 0xAF,
3880 0x34, 0x20,
3881 0x2A, 0x30,
3882
3883 0x00, 0xE0,
3884 0x0D, 0x20,
3885 0x32, 0x20,
3886 0x05, 0x20,
3887
3888 0x87, 0x80, 0x57, 0xE9,
3889 0x1F, 0x54, 0x57, 0x9F,
3890
3891 0x17, 0x42, 0x56, 0x9F,
3892 0x00, 0xE0,
3893 0x3B, 0x6A,
3894
3895 0x3F, 0x8F, 0x51, 0x9F,
3896 0x37, 0x1E, 0x4F, 0xE9,
3897
3898 0x37, 0x32, 0x2A, 0xAF,
3899 0x00, 0xE0,
3900 0x32, 0x00,
3901
3902 0x00, 0x80, 0x00, 0xE8,
3903 0x27, 0xC0, 0x44, 0xC0,
3904
3905 0x36, 0x1F, 0x4F, 0xE9,
3906 0x1F, 0x1F, 0x26, 0xDF,
3907
3908 0x37, 0x1B, 0x37, 0xBF,
3909 0x17, 0x26, 0x17, 0xDF,
3910
3911 0x3E, 0x17, 0x4F, 0xE9,
3912 0x3F, 0x3F, 0x4F, 0xE9,
3913
3914 0x34, 0x1F, 0x34, 0xAF,
3915 0x2B, 0x05,
3916 0xA7, 0x20,
3917
3918 0x33, 0x2B, 0x37, 0xDF,
3919 0x27, 0x17, 0xC0, 0xAF,
3920
3921 0x34, 0x80, 0x4F, 0xE9,
3922 0x00, 0x80, 0x00, 0xE8,
3923
3924 0x2D, 0x21, 0x1A, 0xB0,
3925 0x25, 0x21, 0x31, 0xB0,
3926
3927 0x0D, 0x21, 0x1A, 0xB2,
3928 0x05, 0x21, 0x31, 0xB2,
3929
3930 0x03, 0x80, 0x2A, 0xEA,
3931 0x17, 0xC1, 0x2B, 0xBD,
3932
3933 0x2D, 0x20,
3934 0x25, 0x20,
3935 0x05, 0x20,
3936 0x0D, 0x20,
3937
3938 0xB3, 0x68,
3939 0x97, 0x25,
3940 0x00, 0x80, 0x00, 0xE8,
3941
3942 0x33, 0xC0, 0x33, 0xAF,
3943 0x2F, 0xC0, 0x21, 0xC0,
3944
3945 0x16, 0x42, 0x56, 0x9F,
3946 0x3C, 0x27, 0x4F, 0xE9,
3947
3948 0x1E, 0x62, 0x57, 0x9F,
3949 0x00, 0x80, 0x00, 0xE8,
3950
3951 0x25, 0x21, 0x31, 0xB4,
3952 0x2D, 0x21, 0x1A, 0xB4,
3953
3954 0x3F, 0x2F, 0x5D, 0x9F,
3955 0x00, 0x80, 0x00, 0xE8,
3956
3957 0x33, 0x05,
3958 0x00, 0xE0,
3959 0x28, 0x19, 0x60, 0xEC,
3960
3961 0x0D, 0x21, 0x1A, 0xB6,
3962 0x05, 0x21, 0x31, 0xB6,
3963
3964 0x37, 0x0F, 0x5C, 0x9F,
3965 0x00, 0xE0,
3966 0x2F, 0x20,
3967
3968 0x23, 0x3B, 0x33, 0xAD,
3969 0x1E, 0x26, 0x1E, 0xDF,
3970
3971 0xA7, 0x1E, 0x4F, 0xE9,
3972 0x17, 0x26, 0x16, 0xDF,
3973
3974 0x2D, 0x20,
3975 0x00, 0xE0,
3976 0xA8, 0x3F, 0x4F, 0xE9,
3977
3978 0x2F, 0x2F, 0x1E, 0xAF,
3979 0x25, 0x20,
3980 0x00, 0xE0,
3981
3982 0xA4, 0x16, 0x4F, 0xE9,
3983 0x0F, 0xC0, 0x21, 0xC2,
3984
3985 0xA6, 0x80, 0x4F, 0xE9,
3986 0x1F, 0x62, 0x57, 0x9F,
3987
3988 0x0D, 0x20,
3989 0x05, 0x20,
3990 0x2F, 0xC0, 0x21, 0xC6,
3991
3992 0x2D, 0x44, 0x4C, 0xB6,
3993 0x25, 0x44, 0x54, 0xB6,
3994
3995 0x3F, 0x2F, 0x5D, 0x9F,
3996 0x00, 0xE0,
3997 0x0F, 0x20,
3998
3999 0x2D, 0x20,
4000 0x25, 0x20,
4001 0x07, 0xC0, 0x44, 0xC6,
4002
4003 0x17, 0x50, 0x56, 0x9F,
4004 0xA5, 0x37, 0x4F, 0xE9,
4005
4006 0x06, 0xC0, 0x21, 0xC4,
4007 0x0F, 0x17, 0x0F, 0xAF,
4008
4009 0x37, 0x0F, 0x5C, 0x9F,
4010 0x00, 0x80, 0x00, 0xE8,
4011
4012 0x1E, 0x62, 0x57, 0x9F,
4013 0x00, 0x80, 0x00, 0xE8,
4014
4015 0x3E, 0x3D, 0x5D, 0x9F,
4016 0x00, 0xE0,
4017 0x07, 0x20,
4018
4019 0x2F, 0x20,
4020 0x00, 0xE0,
4021 0xA3, 0x0F, 0x4F, 0xE9,
4022
4023 0x06, 0x20,
4024 0x00, 0xE0,
4025 0x1F, 0x26, 0x1F, 0xDF,
4026
4027 0x17, 0x26, 0x17, 0xDF,
4028 0xA1, 0x1F, 0x4F, 0xE9,
4029
4030 0x1E, 0x26, 0x1E, 0xDF,
4031 0x9D, 0x1E, 0x4F, 0xE9,
4032
4033 0x35, 0x17, 0x4F, 0xE9,
4034 0xA2, 0x3F, 0x4F, 0xE9,
4035
4036 0x06, 0x06, 0x1F, 0xAF,
4037 0x39, 0x37, 0x4F, 0xE9,
4038
4039 0x2F, 0x2F, 0x17, 0xAF,
4040 0x07, 0x07, 0x1E, 0xAF,
4041
4042 0xA0, 0x80, 0x4F, 0xE9,
4043 0x9E, 0x3E, 0x4F, 0xE9,
4044
4045 0x31, 0x80, 0x4F, 0xE9,
4046 0x9C, 0x80, 0x4F, 0xE9,
4047
4048 0x00, 0x80, 0x00, 0xE8,
4049 0x57, 0x39, 0x20, 0xE9,
4050
4051 0x16, 0x28, 0x20, 0xE9,
4052 0x1D, 0x3B, 0x20, 0xE9,
4053
4054 0x1E, 0x2B, 0x20, 0xE9,
4055 0x2B, 0x32, 0x20, 0xE9,
4056
4057 0x1C, 0x23, 0x20, 0xE9,
4058 0x57, 0x36, 0x20, 0xE9,
4059
4060 0x00, 0x80, 0xA0, 0xE9,
4061 0x40, 0x40, 0xD8, 0xEC,
4062
4063 0xFF, 0x80, 0xC0, 0xE9,
4064 0x90, 0xE2,
4065 0x00, 0xE0,
4066
4067 0x63, 0xFF, 0x20, 0xEA,
4068 0x19, 0xC8, 0xC1, 0xCD,
4069
4070 0x1F, 0xD7, 0x18, 0xBD,
4071 0x3F, 0xD7, 0x22, 0xBD,
4072
4073 0x9F, 0x41, 0x49, 0xBD,
4074 0x00, 0x80, 0x00, 0xE8,
4075
4076 0x25, 0x41, 0x49, 0xBD,
4077 0x2D, 0x41, 0x51, 0xBD,
4078
4079 0x0D, 0x80, 0x07, 0xEA,
4080 0x00, 0x80, 0x00, 0xE8,
4081
4082 0x35, 0x40, 0x48, 0xBD,
4083 0x3D, 0x40, 0x50, 0xBD,
4084
4085 0x00, 0x80, 0x00, 0xE8,
4086 0x25, 0x30,
4087 0x2D, 0x30,
4088
4089 0x35, 0x30,
4090 0xB5, 0x30,
4091 0xBD, 0x30,
4092 0x3D, 0x30,
4093
4094 0x9C, 0xA7, 0x5B, 0x9F,
4095 0x00, 0x80, 0x00, 0xE8,
4096
4097 0x00, 0x80, 0x00, 0xE8,
4098 0x00, 0x80, 0x00, 0xE8,
4099
4100 0x00, 0x80, 0x00, 0xE8,
4101 0x00, 0x80, 0x00, 0xE8,
4102
4103 0x00, 0x80, 0x00, 0xE8,
4104 0x00, 0x80, 0x00, 0xE8,
4105
4106 0x00, 0x80, 0x00, 0xE8,
4107 0x00, 0x80, 0x00, 0xE8,
4108
4109 0x62, 0xFF, 0x0A, 0xEA,
4110 0x00, 0x80, 0x00, 0xE8,
4111
4112 0xC9, 0x41, 0xC8, 0xEC,
4113 0x42, 0xE1,
4114 0x00, 0xE0,
4115
4116 0x60, 0xFF, 0x20, 0xEA,
4117 0x00, 0x80, 0x00, 0xE8,
4118
4119 0x00, 0x80, 0x00, 0xE8,
4120 0x00, 0x80, 0x00, 0xE8,
4121
4122 0xC8, 0x40, 0xC0, 0xEC,
4123 0x00, 0x80, 0x00, 0xE8,
4124
4125 0x5D, 0xFF, 0x20, 0xEA,
4126 0x00, 0x80, 0x00, 0xE8,
4127
4128 0x00, 0x80, 0x00, 0xE8,
4129 0x00, 0x80, 0x00, 0xE8,
4130
4131};
4132
4133static unsigned char warp_g200_tgzsf[] = {
4134
4135 0x00, 0x80, 0x00, 0xE8,
4136 0x00, 0x80, 0x00, 0xE8,
4137
4138 0x00, 0x80, 0x00, 0xE8,
4139 0x00, 0x80, 0x00, 0xE8,
4140
4141 0x00, 0x80, 0x00, 0xE8,
4142 0x00, 0x80, 0x00, 0xE8,
4143
4144 0x00, 0x80, 0x00, 0xE8,
4145 0x00, 0x80, 0x00, 0xE8,
4146
4147 0x00, 0x80, 0x00, 0xE8,
4148 0x00, 0x80, 0x00, 0xE8,
4149
4150 0x00, 0x80, 0x00, 0xE8,
4151 0x00, 0x80, 0x00, 0xE8,
4152
4153 0x00, 0x80, 0x00, 0xE8,
4154 0x00, 0x80, 0x00, 0xE8,
4155
4156 0x00, 0x80, 0x00, 0xE8,
4157 0x00, 0x80, 0x00, 0xE8,
4158
4159 0x00, 0x80, 0x00, 0xE8,
4160 0x00, 0x80, 0x00, 0xE8,
4161
4162 0x00, 0x80, 0x00, 0xE8,
4163 0x00, 0x80, 0x00, 0xE8,
4164
4165 0x00, 0x80, 0x00, 0xE8,
4166 0x00, 0x80, 0x00, 0xE8,
4167
4168 0x00, 0x80, 0x00, 0xE8,
4169 0x00, 0x80, 0x00, 0xE8,
4170
4171 0x00, 0x80, 0x00, 0xE8,
4172 0x00, 0x80, 0x00, 0xE8,
4173
4174 0x00, 0x98, 0xA0, 0xE9,
4175 0x40, 0x40, 0xD8, 0xEC,
4176
4177 0xFF, 0x80, 0xC0, 0xE9,
4178 0x00, 0x80, 0x00, 0xE8,
4179
4180 0x1F, 0xD7, 0x18, 0xBD,
4181 0x3F, 0xD7, 0x22, 0xBD,
4182
4183 0x81, 0x04,
4184 0x89, 0x04,
4185 0x01, 0x04,
4186 0x09, 0x04,
4187
4188 0xC9, 0x41, 0xC0, 0xEC,
4189 0x11, 0x04,
4190 0x00, 0xE0,
4191
4192 0x41, 0xCC, 0x41, 0xCD,
4193 0x49, 0xCC, 0x49, 0xCD,
4194
4195 0xD1, 0x41, 0xC0, 0xEC,
4196 0x51, 0xCC, 0x51, 0xCD,
4197
4198 0x80, 0x04,
4199 0x10, 0x04,
4200 0x08, 0x04,
4201 0x00, 0xE0,
4202
4203 0x00, 0xCC, 0xC0, 0xCD,
4204 0xD1, 0x49, 0xC0, 0xEC,
4205
4206 0x8A, 0x1F, 0x20, 0xE9,
4207 0x8B, 0x3F, 0x20, 0xE9,
4208
4209 0x41, 0x3C, 0x41, 0xAD,
4210 0x49, 0x3C, 0x49, 0xAD,
4211
4212 0x10, 0xCC, 0x10, 0xCD,
4213 0x08, 0xCC, 0x08, 0xCD,
4214
4215 0xB9, 0x41, 0x49, 0xBB,
4216 0x1F, 0xF0, 0x41, 0xCD,
4217
4218 0x51, 0x3C, 0x51, 0xAD,
4219 0x00, 0x98, 0x80, 0xE9,
4220
4221 0x8F, 0x80, 0x07, 0xEA,
4222 0x24, 0x1F, 0x20, 0xE9,
4223
4224 0x21, 0x45, 0x80, 0xE8,
4225 0x1A, 0x4D, 0x80, 0xE8,
4226
4227 0x31, 0x55, 0x80, 0xE8,
4228 0x00, 0x80, 0x00, 0xE8,
4229
4230 0x15, 0x41, 0x49, 0xBD,
4231 0x1D, 0x41, 0x51, 0xBD,
4232
4233 0x2E, 0x41, 0x2A, 0xB8,
4234 0x34, 0x53, 0xA0, 0xE8,
4235
4236 0x15, 0x30,
4237 0x1D, 0x30,
4238 0x58, 0xE3,
4239 0x00, 0xE0,
4240
4241 0xB5, 0x40, 0x48, 0xBD,
4242 0x3D, 0x40, 0x50, 0xBD,
4243
4244 0x24, 0x43, 0xA0, 0xE8,
4245 0x2C, 0x4B, 0xA0, 0xE8,
4246
4247 0x15, 0x72,
4248 0x09, 0xE3,
4249 0x00, 0xE0,
4250 0x1D, 0x72,
4251
4252 0x35, 0x30,
4253 0xB5, 0x30,
4254 0xBD, 0x30,
4255 0x3D, 0x30,
4256
4257 0x9C, 0x97, 0x57, 0x9F,
4258 0x00, 0x80, 0x00, 0xE8,
4259
4260 0x6C, 0x64, 0xC8, 0xEC,
4261 0x98, 0xE1,
4262 0xB5, 0x05,
4263
4264 0xBD, 0x05,
4265 0x2E, 0x30,
4266 0x32, 0xC0, 0xA0, 0xE8,
4267
4268 0x33, 0xC0, 0xA0, 0xE8,
4269 0x74, 0x64, 0xC8, 0xEC,
4270
4271 0x40, 0x3C, 0x40, 0xAD,
4272 0x32, 0x6A,
4273 0x2A, 0x30,
4274
4275 0x20, 0x73,
4276 0x33, 0x6A,
4277 0x00, 0xE0,
4278 0x28, 0x73,
4279
4280 0x1C, 0x72,
4281 0x83, 0xE2,
4282 0x7B, 0x80, 0x15, 0xEA,
4283
4284 0xB8, 0x3D, 0x28, 0xDF,
4285 0x30, 0x35, 0x20, 0xDF,
4286
4287 0x40, 0x30,
4288 0x00, 0xE0,
4289 0xCC, 0xE2,
4290 0x64, 0x72,
4291
4292 0x25, 0x42, 0x52, 0xBF,
4293 0x2D, 0x42, 0x4A, 0xBF,
4294
4295 0x30, 0x2E, 0x30, 0xDF,
4296 0x38, 0x2E, 0x38, 0xDF,
4297
4298 0x18, 0x1D, 0x45, 0xE9,
4299 0x1E, 0x15, 0x45, 0xE9,
4300
4301 0x2B, 0x49, 0x51, 0xBD,
4302 0x00, 0xE0,
4303 0x1F, 0x73,
4304
4305 0x38, 0x38, 0x40, 0xAF,
4306 0x30, 0x30, 0x40, 0xAF,
4307
4308 0x24, 0x1F, 0x24, 0xDF,
4309 0x1D, 0x32, 0x20, 0xE9,
4310
4311 0x2C, 0x1F, 0x2C, 0xDF,
4312 0x1A, 0x33, 0x20, 0xE9,
4313
4314 0xB0, 0x10,
4315 0x08, 0xE3,
4316 0x40, 0x10,
4317 0xB8, 0x10,
4318
4319 0x26, 0xF0, 0x30, 0xCD,
4320 0x2F, 0xF0, 0x38, 0xCD,
4321
4322 0x2B, 0x80, 0x20, 0xE9,
4323 0x2A, 0x80, 0x20, 0xE9,
4324
4325 0xA6, 0x20,
4326 0x88, 0xE2,
4327 0x00, 0xE0,
4328 0xAF, 0x20,
4329
4330 0x28, 0x2A, 0x26, 0xAF,
4331 0x20, 0x2A, 0xC0, 0xAF,
4332
4333 0x34, 0x1F, 0x34, 0xDF,
4334 0x46, 0x24, 0x46, 0xDF,
4335
4336 0x28, 0x30, 0x80, 0xBF,
4337 0x20, 0x38, 0x80, 0xBF,
4338
4339 0x47, 0x24, 0x47, 0xDF,
4340 0x4E, 0x2C, 0x4E, 0xDF,
4341
4342 0x4F, 0x2C, 0x4F, 0xDF,
4343 0x56, 0x34, 0x56, 0xDF,
4344
4345 0x28, 0x15, 0x28, 0xDF,
4346 0x20, 0x1D, 0x20, 0xDF,
4347
4348 0x57, 0x34, 0x57, 0xDF,
4349 0x00, 0xE0,
4350 0x1D, 0x05,
4351
4352 0x04, 0x80, 0x10, 0xEA,
4353 0x89, 0xE2,
4354 0x2B, 0x30,
4355
4356 0x3F, 0xC1, 0x1D, 0xBD,
4357 0x00, 0x80, 0x00, 0xE8,
4358
4359 0x00, 0x80, 0x00, 0xE8,
4360 0x00, 0x80, 0x00, 0xE8,
4361
4362 0xA0, 0x68,
4363 0xBF, 0x25,
4364 0x00, 0x80, 0x00, 0xE8,
4365
4366 0x20, 0xC0, 0x20, 0xAF,
4367 0x28, 0x05,
4368 0x97, 0x74,
4369
4370 0x00, 0xE0,
4371 0x2A, 0x10,
4372 0x16, 0xC0, 0x20, 0xE9,
4373
4374 0x04, 0x80, 0x10, 0xEA,
4375 0x8C, 0xE2,
4376 0x95, 0x05,
4377
4378 0x28, 0xC1, 0x28, 0xAD,
4379 0x1F, 0xC1, 0x15, 0xBD,
4380
4381 0x00, 0x80, 0x00, 0xE8,
4382 0x00, 0x80, 0x00, 0xE8,
4383
4384 0xA8, 0x67,
4385 0x9F, 0x6B,
4386 0x00, 0x80, 0x00, 0xE8,
4387
4388 0x28, 0xC0, 0x28, 0xAD,
4389 0x1D, 0x25,
4390 0x20, 0x05,
4391
4392 0x28, 0x32, 0x80, 0xAD,
4393 0x40, 0x2A, 0x40, 0xBD,
4394
4395 0x1C, 0x80, 0x20, 0xE9,
4396 0x20, 0x33, 0x20, 0xAD,
4397
4398 0x20, 0x73,
4399 0x00, 0xE0,
4400 0xB6, 0x49, 0x51, 0xBB,
4401
4402 0x26, 0x2F, 0xB0, 0xE8,
4403 0x19, 0x20, 0x20, 0xE9,
4404
4405 0x35, 0x20, 0x35, 0xDF,
4406 0x3D, 0x20, 0x3D, 0xDF,
4407
4408 0x15, 0x20, 0x15, 0xDF,
4409 0x1D, 0x20, 0x1D, 0xDF,
4410
4411 0x26, 0xD0, 0x26, 0xCD,
4412 0x29, 0x49, 0x2A, 0xB8,
4413
4414 0x26, 0x40, 0x80, 0xBD,
4415 0x3B, 0x48, 0x50, 0xBD,
4416
4417 0x3E, 0x54, 0x57, 0x9F,
4418 0x00, 0xE0,
4419 0x82, 0xE1,
4420
4421 0x1E, 0xAF, 0x59, 0x9F,
4422 0x00, 0x80, 0x00, 0xE8,
4423
4424 0x26, 0x30,
4425 0x29, 0x30,
4426 0x48, 0x3C, 0x48, 0xAD,
4427
4428 0x2B, 0x72,
4429 0xC2, 0xE1,
4430 0x2C, 0xC0, 0x44, 0xC2,
4431
4432 0x05, 0x24, 0x34, 0xBF,
4433 0x0D, 0x24, 0x2C, 0xBF,
4434
4435 0x2D, 0x46, 0x4E, 0xBF,
4436 0x25, 0x46, 0x56, 0xBF,
4437
4438 0x20, 0x1D, 0x6F, 0x8F,
4439 0x32, 0x3E, 0x5F, 0xE9,
4440
4441 0x3E, 0x50, 0x56, 0x9F,
4442 0x00, 0xE0,
4443 0x3B, 0x30,
4444
4445 0x1E, 0x8F, 0x51, 0x9F,
4446 0x33, 0x1E, 0x5F, 0xE9,
4447
4448 0x05, 0x44, 0x54, 0xB2,
4449 0x0D, 0x44, 0x4C, 0xB2,
4450
4451 0x19, 0xC0, 0xB0, 0xE8,
4452 0x34, 0xC0, 0x44, 0xC4,
4453
4454 0x33, 0x73,
4455 0x00, 0xE0,
4456 0x3E, 0x62, 0x57, 0x9F,
4457
4458 0x1E, 0xAF, 0x59, 0x9F,
4459 0x00, 0xE0,
4460 0x0D, 0x20,
4461
4462 0x84, 0x3E, 0x58, 0xE9,
4463 0x28, 0x1D, 0x6F, 0x8F,
4464
4465 0x05, 0x20,
4466 0x00, 0xE0,
4467 0x85, 0x1E, 0x58, 0xE9,
4468
4469 0x9B, 0x3B, 0x33, 0xDF,
4470 0x20, 0x20, 0x42, 0xAF,
4471
4472 0x30, 0x42, 0x56, 0x9F,
4473 0x80, 0x3E, 0x57, 0xE9,
4474
4475 0x3F, 0x8F, 0x51, 0x9F,
4476 0x30, 0x80, 0x5F, 0xE9,
4477
4478 0x28, 0x28, 0x24, 0xAF,
4479 0x81, 0x1E, 0x57, 0xE9,
4480
4481 0x05, 0x47, 0x57, 0xBF,
4482 0x0D, 0x47, 0x4F, 0xBF,
4483
4484 0x88, 0x80, 0x58, 0xE9,
4485 0x1B, 0x29, 0x1B, 0xDF,
4486
4487 0x30, 0x1D, 0x6F, 0x8F,
4488 0x3A, 0x30, 0x4F, 0xE9,
4489
4490 0x1C, 0x30, 0x26, 0xDF,
4491 0x09, 0xE3,
4492 0x3B, 0x05,
4493
4494 0x3E, 0x50, 0x56, 0x9F,
4495 0x3B, 0x3F, 0x4F, 0xE9,
4496
4497 0x1E, 0x8F, 0x51, 0x9F,
4498 0x00, 0xE0,
4499 0xAC, 0x20,
4500
4501 0x2D, 0x44, 0x4C, 0xB4,
4502 0x2C, 0x1C, 0xC0, 0xAF,
4503
4504 0x25, 0x44, 0x54, 0xB4,
4505 0x00, 0xE0,
4506 0xC8, 0x30,
4507
4508 0x30, 0x46, 0x30, 0xAF,
4509 0x1B, 0x1B, 0x48, 0xAF,
4510
4511 0x00, 0xE0,
4512 0x25, 0x20,
4513 0x38, 0x2C, 0x4F, 0xE9,
4514
4515 0x86, 0x80, 0x57, 0xE9,
4516 0x38, 0x1D, 0x6F, 0x8F,
4517
4518 0x28, 0x74,
4519 0x00, 0xE0,
4520 0x0D, 0x44, 0x4C, 0xB0,
4521
4522 0x05, 0x44, 0x54, 0xB0,
4523 0x2D, 0x20,
4524 0x9B, 0x10,
4525
4526 0x82, 0x3E, 0x57, 0xE9,
4527 0x32, 0xF0, 0x1B, 0xCD,
4528
4529 0x1E, 0xBD, 0x59, 0x9F,
4530 0x83, 0x1E, 0x57, 0xE9,
4531
4532 0x38, 0x47, 0x38, 0xAF,
4533 0x34, 0x20,
4534 0x2A, 0x30,
4535
4536 0x00, 0xE0,
4537 0x0D, 0x20,
4538 0x32, 0x20,
4539 0x05, 0x20,
4540
4541 0x87, 0x80, 0x57, 0xE9,
4542 0x1F, 0x54, 0x57, 0x9F,
4543
4544 0x17, 0x42, 0x56, 0x9F,
4545 0x00, 0xE0,
4546 0x3B, 0x6A,
4547
4548 0x3F, 0x8F, 0x51, 0x9F,
4549 0x37, 0x1E, 0x4F, 0xE9,
4550
4551 0x37, 0x32, 0x2A, 0xAF,
4552 0x00, 0xE0,
4553 0x32, 0x00,
4554
4555 0x00, 0x80, 0x00, 0xE8,
4556 0x27, 0xC0, 0x44, 0xC0,
4557
4558 0x36, 0x1F, 0x4F, 0xE9,
4559 0x1F, 0x1F, 0x26, 0xDF,
4560
4561 0x37, 0x1B, 0x37, 0xBF,
4562 0x17, 0x26, 0x17, 0xDF,
4563
4564 0x3E, 0x17, 0x4F, 0xE9,
4565 0x3F, 0x3F, 0x4F, 0xE9,
4566
4567 0x34, 0x1F, 0x34, 0xAF,
4568 0x2B, 0x05,
4569 0xA7, 0x20,
4570
4571 0x33, 0x2B, 0x37, 0xDF,
4572 0x27, 0x17, 0xC0, 0xAF,
4573
4574 0x34, 0x80, 0x4F, 0xE9,
4575 0x00, 0x80, 0x00, 0xE8,
4576
4577 0x2D, 0x21, 0x1A, 0xB0,
4578 0x25, 0x21, 0x31, 0xB0,
4579
4580 0x0D, 0x21, 0x1A, 0xB2,
4581 0x05, 0x21, 0x31, 0xB2,
4582
4583 0x03, 0x80, 0x2A, 0xEA,
4584 0x17, 0xC1, 0x2B, 0xBD,
4585
4586 0x2D, 0x20,
4587 0x25, 0x20,
4588 0x05, 0x20,
4589 0x0D, 0x20,
4590
4591 0xB3, 0x68,
4592 0x97, 0x25,
4593 0x00, 0x80, 0x00, 0xE8,
4594
4595 0x33, 0xC0, 0x33, 0xAF,
4596 0x2F, 0xC0, 0x21, 0xC0,
4597
4598 0x16, 0x42, 0x56, 0x9F,
4599 0x3C, 0x27, 0x4F, 0xE9,
4600
4601 0x1E, 0x62, 0x57, 0x9F,
4602 0x00, 0x80, 0x00, 0xE8,
4603
4604 0x25, 0x21, 0x31, 0xB4,
4605 0x2D, 0x21, 0x1A, 0xB4,
4606
4607 0x3F, 0x2F, 0x5D, 0x9F,
4608 0x00, 0x80, 0x00, 0xE8,
4609
4610 0x33, 0x05,
4611 0x00, 0xE0,
4612 0x28, 0x19, 0x60, 0xEC,
4613
4614 0x0D, 0x21, 0x1A, 0xB6,
4615 0x05, 0x21, 0x31, 0xB6,
4616
4617 0x37, 0x0F, 0x5C, 0x9F,
4618 0x00, 0xE0,
4619 0x2F, 0x20,
4620
4621 0x23, 0x3B, 0x33, 0xAD,
4622 0x1E, 0x26, 0x1E, 0xDF,
4623
4624 0xA7, 0x1E, 0x4F, 0xE9,
4625 0x17, 0x26, 0x16, 0xDF,
4626
4627 0x2D, 0x20,
4628 0x00, 0xE0,
4629 0xA8, 0x3F, 0x4F, 0xE9,
4630
4631 0x2F, 0x2F, 0x1E, 0xAF,
4632 0x25, 0x20,
4633 0x00, 0xE0,
4634
4635 0xA4, 0x16, 0x4F, 0xE9,
4636 0x0F, 0xC0, 0x21, 0xC2,
4637
4638 0xA6, 0x80, 0x4F, 0xE9,
4639 0x1F, 0x62, 0x57, 0x9F,
4640
4641 0x0D, 0x20,
4642 0x05, 0x20,
4643 0x2F, 0xC0, 0x21, 0xC6,
4644
4645 0x3F, 0x2F, 0x5D, 0x9F,
4646 0x00, 0xE0,
4647 0x0F, 0x20,
4648
4649 0x17, 0x50, 0x56, 0x9F,
4650 0xA5, 0x37, 0x4F, 0xE9,
4651
4652 0x06, 0xC0, 0x21, 0xC4,
4653 0x0F, 0x17, 0x0F, 0xAF,
4654
4655 0x37, 0x0F, 0x5C, 0x9F,
4656 0x00, 0x80, 0x00, 0xE8,
4657
4658 0x2F, 0x20,
4659 0x00, 0xE0,
4660 0xA3, 0x80, 0x4F, 0xE9,
4661
4662 0x06, 0x20,
4663 0x00, 0xE0,
4664 0x1F, 0x26, 0x1F, 0xDF,
4665
4666 0x17, 0x26, 0x17, 0xDF,
4667 0x35, 0x17, 0x4F, 0xE9,
4668
4669 0xA1, 0x1F, 0x4F, 0xE9,
4670 0xA2, 0x3F, 0x4F, 0xE9,
4671
4672 0x06, 0x06, 0x1F, 0xAF,
4673 0x39, 0x37, 0x4F, 0xE9,
4674
4675 0x2F, 0x2F, 0x17, 0xAF,
4676 0x00, 0x80, 0x00, 0xE8,
4677
4678 0xA0, 0x80, 0x4F, 0xE9,
4679 0x00, 0x80, 0x00, 0xE8,
4680
4681 0x31, 0x80, 0x4F, 0xE9,
4682 0x00, 0x80, 0x00, 0xE8,
4683
4684 0x00, 0x80, 0x00, 0xE8,
4685 0x57, 0x39, 0x20, 0xE9,
4686
4687 0x16, 0x28, 0x20, 0xE9,
4688 0x1D, 0x3B, 0x20, 0xE9,
4689
4690 0x1E, 0x2B, 0x20, 0xE9,
4691 0x2B, 0x32, 0x20, 0xE9,
4692
4693 0x1C, 0x23, 0x20, 0xE9,
4694 0x57, 0x36, 0x20, 0xE9,
4695
4696 0x00, 0x80, 0xA0, 0xE9,
4697 0x40, 0x40, 0xD8, 0xEC,
4698
4699 0xFF, 0x80, 0xC0, 0xE9,
4700 0x90, 0xE2,
4701 0x00, 0xE0,
4702
4703 0x68, 0xFF, 0x20, 0xEA,
4704 0x19, 0xC8, 0xC1, 0xCD,
4705
4706 0x1F, 0xD7, 0x18, 0xBD,
4707 0x3F, 0xD7, 0x22, 0xBD,
4708
4709 0x9F, 0x41, 0x49, 0xBD,
4710 0x00, 0x80, 0x00, 0xE8,
4711
4712 0x25, 0x41, 0x49, 0xBD,
4713 0x2D, 0x41, 0x51, 0xBD,
4714
4715 0x0D, 0x80, 0x07, 0xEA,
4716 0x00, 0x80, 0x00, 0xE8,
4717
4718 0x35, 0x40, 0x48, 0xBD,
4719 0x3D, 0x40, 0x50, 0xBD,
4720
4721 0x00, 0x80, 0x00, 0xE8,
4722 0x25, 0x30,
4723 0x2D, 0x30,
4724
4725 0x35, 0x30,
4726 0xB5, 0x30,
4727 0xBD, 0x30,
4728 0x3D, 0x30,
4729
4730 0x9C, 0xA7, 0x5B, 0x9F,
4731 0x00, 0x80, 0x00, 0xE8,
4732
4733 0x00, 0x80, 0x00, 0xE8,
4734 0x00, 0x80, 0x00, 0xE8,
4735
4736 0x00, 0x80, 0x00, 0xE8,
4737 0x00, 0x80, 0x00, 0xE8,
4738
4739 0x00, 0x80, 0x00, 0xE8,
4740 0x00, 0x80, 0x00, 0xE8,
4741
4742 0x00, 0x80, 0x00, 0xE8,
4743 0x00, 0x80, 0x00, 0xE8,
4744
4745 0x67, 0xFF, 0x0A, 0xEA,
4746 0x00, 0x80, 0x00, 0xE8,
4747
4748 0xC9, 0x41, 0xC8, 0xEC,
4749 0x42, 0xE1,
4750 0x00, 0xE0,
4751
4752 0x65, 0xFF, 0x20, 0xEA,
4753 0x00, 0x80, 0x00, 0xE8,
4754
4755 0x00, 0x80, 0x00, 0xE8,
4756 0x00, 0x80, 0x00, 0xE8,
4757
4758 0xC8, 0x40, 0xC0, 0xEC,
4759 0x00, 0x80, 0x00, 0xE8,
4760
4761 0x62, 0xFF, 0x20, 0xEA,
4762 0x00, 0x80, 0x00, 0xE8,
4763
4764 0x00, 0x80, 0x00, 0xE8,
4765 0x00, 0x80, 0x00, 0xE8,
4766
4767};
4768
4769static unsigned char warp_g400_t2gz[] = {
4770
4771 0x00, 0x8A, 0x98, 0xE9,
4772 0x00, 0x80, 0x00, 0xE8,
4773
4774 0x00, 0x80, 0xA0, 0xE9,
4775 0x00, 0x00, 0xD8, 0xEC,
4776
4777 0xFF, 0x80, 0xC0, 0xE9,
4778 0x00, 0x80, 0x00, 0xE8,
4779
4780 0x0A, 0x40, 0x50, 0xBF,
4781 0x2A, 0x40, 0x60, 0xBF,
4782
4783 0x32, 0x41, 0x51, 0xBF,
4784 0x3A, 0x41, 0x61, 0xBF,
4785
4786 0xC3, 0x6B,
4787 0xD3, 0x6B,
4788 0x00, 0x8A, 0x98, 0xE9,
4789
4790 0x73, 0x7B, 0xC8, 0xEC,
4791 0x96, 0xE2,
4792 0x41, 0x04,
4793
4794 0x7B, 0x43, 0xA0, 0xE8,
4795 0x73, 0x53, 0xA0, 0xE8,
4796
4797 0xAD, 0xEE, 0x23, 0x9F,
4798 0x00, 0xE0,
4799 0x51, 0x04,
4800
4801 0x90, 0xE2,
4802 0x61, 0x04,
4803 0x31, 0x46, 0xB1, 0xE8,
4804
4805 0x51, 0x41, 0xE0, 0xEC,
4806 0x39, 0x67, 0xB1, 0xE8,
4807
4808 0x00, 0x04,
4809 0x46, 0xE2,
4810 0x73, 0x63, 0xA0, 0xE8,
4811
4812 0x61, 0x41, 0xE0, 0xEC,
4813 0x31, 0x00,
4814 0x39, 0x00,
4815
4816 0x78, 0x80, 0x15, 0xEA,
4817 0x10, 0x04,
4818 0x20, 0x04,
4819
4820 0x61, 0x51, 0xE0, 0xEC,
4821 0x2F, 0x41, 0x60, 0xEA,
4822
4823 0x31, 0x20,
4824 0x39, 0x20,
4825 0x1F, 0x42, 0xA0, 0xE8,
4826
4827 0x2A, 0x42, 0x52, 0xBF,
4828 0x0F, 0x52, 0xA0, 0xE8,
4829
4830 0x1A, 0x42, 0x62, 0xBF,
4831 0x1E, 0x51, 0x60, 0xEA,
4832
4833 0x73, 0x7B, 0xC8, 0xEC,
4834 0x0E, 0x61, 0x60, 0xEA,
4835
4836 0x32, 0x40, 0x50, 0xBD,
4837 0x22, 0x40, 0x60, 0xBD,
4838
4839 0x12, 0x41, 0x51, 0xBD,
4840 0x3A, 0x41, 0x61, 0xBD,
4841
4842 0xBF, 0x2F, 0x0E, 0xBD,
4843 0x97, 0xE2,
4844 0x7B, 0x72,
4845
4846 0x32, 0x20,
4847 0x22, 0x20,
4848 0x12, 0x20,
4849 0x3A, 0x20,
4850
4851 0x35, 0x48, 0xB1, 0xE8,
4852 0x3D, 0x59, 0xB1, 0xE8,
4853
4854 0x46, 0x31, 0x46, 0xBF,
4855 0x56, 0x31, 0x56, 0xBF,
4856
4857 0xB3, 0xE2, 0x2D, 0x9F,
4858 0x00, 0x80, 0x00, 0xE8,
4859
4860 0x66, 0x31, 0x66, 0xBF,
4861 0x47, 0x39, 0x47, 0xBF,
4862
4863 0x57, 0x39, 0x57, 0xBF,
4864 0x67, 0x39, 0x67, 0xBF,
4865
4866 0x69, 0x80, 0x07, 0xEA,
4867 0x24, 0x41, 0x20, 0xE9,
4868
4869 0x35, 0x00,
4870 0x3D, 0x00,
4871 0x00, 0xE0,
4872 0x2D, 0x73,
4873
4874 0x33, 0x72,
4875 0x0C, 0xE3,
4876 0x8D, 0x2F, 0x1E, 0xBD,
4877
4878 0x43, 0x75, 0xF8, 0xEC,
4879 0x35, 0x20,
4880 0x3D, 0x20,
4881
4882 0x43, 0x43, 0x2D, 0xDF,
4883 0x53, 0x53, 0x2D, 0xDF,
4884
4885 0xAE, 0x1E, 0x0E, 0xBD,
4886 0x58, 0xE3,
4887 0x33, 0x66,
4888
4889 0x48, 0x35, 0x48, 0xBF,
4890 0x58, 0x35, 0x58, 0xBF,
4891
4892 0x68, 0x35, 0x68, 0xBF,
4893 0x49, 0x3D, 0x49, 0xBF,
4894
4895 0x59, 0x3D, 0x59, 0xBF,
4896 0x69, 0x3D, 0x69, 0xBF,
4897
4898 0x63, 0x63, 0x2D, 0xDF,
4899 0x4D, 0x7D, 0xF8, 0xEC,
4900
4901 0x59, 0xE3,
4902 0x00, 0xE0,
4903 0xB8, 0x38, 0x33, 0xBF,
4904
4905 0x2D, 0x73,
4906 0x30, 0x76,
4907 0x18, 0x3A, 0x41, 0xE9,
4908
4909 0x3F, 0x53, 0xA0, 0xE8,
4910 0x05, 0x80, 0x3D, 0xEA,
4911
4912 0x37, 0x43, 0xA0, 0xE8,
4913 0x3D, 0x63, 0xA0, 0xE8,
4914
4915 0x50, 0x70, 0xF8, 0xEC,
4916 0x2B, 0x50, 0x3C, 0xE9,
4917
4918 0x1F, 0x0F, 0xBC, 0xE8,
4919 0x00, 0x80, 0x00, 0xE8,
4920
4921 0x59, 0x78, 0xF8, 0xEC,
4922 0x00, 0x80, 0x00, 0xE8,
4923
4924 0x15, 0xC0, 0x20, 0xE9,
4925 0x15, 0xC0, 0x20, 0xE9,
4926
4927 0x15, 0xC0, 0x20, 0xE9,
4928 0x15, 0xC0, 0x20, 0xE9,
4929
4930 0x1E, 0x12, 0x41, 0xE9,
4931 0x1A, 0x22, 0x41, 0xE9,
4932
4933 0x46, 0x37, 0x46, 0xDF,
4934 0x56, 0x3F, 0x56, 0xDF,
4935
4936 0x2B, 0x40, 0x3D, 0xE9,
4937 0x66, 0x3D, 0x66, 0xDF,
4938
4939 0x1D, 0x32, 0x41, 0xE9,
4940 0x67, 0x3D, 0x67, 0xDF,
4941
4942 0x47, 0x37, 0x47, 0xDF,
4943 0x57, 0x3F, 0x57, 0xDF,
4944
4945 0x2A, 0x40, 0x20, 0xE9,
4946 0x59, 0x3F, 0x59, 0xDF,
4947
4948 0x16, 0x30, 0x20, 0xE9,
4949 0x69, 0x3D, 0x69, 0xDF,
4950
4951 0x48, 0x37, 0x48, 0xDF,
4952 0x58, 0x3F, 0x58, 0xDF,
4953
4954 0x12, 0x12, 0x2D, 0xDF,
4955 0x22, 0x22, 0x2D, 0xDF,
4956
4957 0x32, 0x32, 0x2D, 0xDF,
4958 0x3A, 0x3A, 0x2D, 0xDF,
4959
4960 0x68, 0x3D, 0x68, 0xDF,
4961 0x49, 0x37, 0x49, 0xDF,
4962
4963 0x3D, 0xCF, 0x74, 0xC0,
4964 0x37, 0xCF, 0x74, 0xC4,
4965
4966 0x31, 0x53, 0x2F, 0x9F,
4967 0x34, 0x80, 0x20, 0xE9,
4968
4969 0x39, 0xE5, 0x2C, 0x9F,
4970 0x3C, 0x3D, 0x20, 0xE9,
4971
4972 0x0A, 0x44, 0x54, 0xB0,
4973 0x02, 0x44, 0x64, 0xB0,
4974
4975 0x2A, 0x44, 0x54, 0xB2,
4976 0x1A, 0x44, 0x64, 0xB2,
4977
4978 0x25, 0x80, 0x3A, 0xEA,
4979 0x0A, 0x20,
4980 0x02, 0x20,
4981
4982 0x3D, 0xCF, 0x74, 0xC2,
4983 0x2A, 0x20,
4984 0x1A, 0x20,
4985
4986 0x30, 0x50, 0x2E, 0x9F,
4987 0x32, 0x31, 0x5F, 0xE9,
4988
4989 0x38, 0x21, 0x2C, 0x9F,
4990 0x33, 0x39, 0x5F, 0xE9,
4991
4992 0x31, 0x53, 0x2F, 0x9F,
4993 0x00, 0x80, 0x00, 0xE8,
4994
4995 0x2A, 0x44, 0x54, 0xB4,
4996 0x1A, 0x44, 0x64, 0xB4,
4997
4998 0x39, 0xE5, 0x2C, 0x9F,
4999 0x38, 0x3D, 0x20, 0xE9,
5000
5001 0x88, 0x73, 0x5E, 0xE9,
5002 0x2A, 0x20,
5003 0x1A, 0x20,
5004
5005 0x2A, 0x46, 0x56, 0xBF,
5006 0x1A, 0x46, 0x66, 0xBF,
5007
5008 0x31, 0x53, 0x2F, 0x9F,
5009 0x3E, 0x30, 0x4F, 0xE9,
5010
5011 0x39, 0xE5, 0x2C, 0x9F,
5012 0x3F, 0x38, 0x4F, 0xE9,
5013
5014 0x0A, 0x47, 0x57, 0xBF,
5015 0x02, 0x47, 0x67, 0xBF,
5016
5017 0x31, 0x53, 0x2F, 0x9F,
5018 0x3A, 0x31, 0x4F, 0xE9,
5019
5020 0x39, 0xE5, 0x2C, 0x9F,
5021 0x3B, 0x39, 0x4F, 0xE9,
5022
5023 0x2A, 0x43, 0x53, 0xBF,
5024 0x1A, 0x43, 0x63, 0xBF,
5025
5026 0x30, 0x50, 0x2E, 0x9F,
5027 0x36, 0x31, 0x4F, 0xE9,
5028
5029 0x38, 0x21, 0x2C, 0x9F,
5030 0x37, 0x39, 0x4F, 0xE9,
5031
5032 0x0A, 0x48, 0x58, 0xBF,
5033 0x02, 0x48, 0x68, 0xBF,
5034
5035 0x31, 0x53, 0x2F, 0x9F,
5036 0x80, 0x31, 0x57, 0xE9,
5037
5038 0x39, 0xE5, 0x2C, 0x9F,
5039 0x81, 0x39, 0x57, 0xE9,
5040
5041 0x2A, 0x49, 0x59, 0xBF,
5042 0x1A, 0x49, 0x69, 0xBF,
5043
5044 0x30, 0x50, 0x2E, 0x9F,
5045 0x82, 0x30, 0x57, 0xE9,
5046
5047 0x38, 0x21, 0x2C, 0x9F,
5048 0x83, 0x38, 0x57, 0xE9,
5049
5050 0x31, 0x53, 0x2F, 0x9F,
5051 0x84, 0x31, 0x5E, 0xE9,
5052
5053 0x39, 0xE5, 0x2C, 0x9F,
5054 0x85, 0x39, 0x5E, 0xE9,
5055
5056 0x86, 0x76, 0x57, 0xE9,
5057 0x8A, 0x36, 0x20, 0xE9,
5058
5059 0x87, 0x77, 0x57, 0xE9,
5060 0x8B, 0x3E, 0xBF, 0xEA,
5061
5062 0x80, 0x30, 0x57, 0xE9,
5063 0x81, 0x38, 0x57, 0xE9,
5064
5065 0x82, 0x31, 0x57, 0xE9,
5066 0x86, 0x78, 0x57, 0xE9,
5067
5068 0x83, 0x39, 0x57, 0xE9,
5069 0x87, 0x79, 0x57, 0xE9,
5070
5071 0x30, 0x1F, 0x5F, 0xE9,
5072 0x8A, 0x34, 0x20, 0xE9,
5073
5074 0x8B, 0x3C, 0x20, 0xE9,
5075 0x37, 0x50, 0x60, 0xBD,
5076
5077 0x57, 0x0D, 0x20, 0xE9,
5078 0x35, 0x51, 0x61, 0xBD,
5079
5080 0x2B, 0x50, 0x20, 0xE9,
5081 0x1D, 0x37, 0xE1, 0xEA,
5082
5083 0x1E, 0x35, 0xE1, 0xEA,
5084 0x00, 0xE0,
5085 0x0E, 0x77,
5086
5087 0x24, 0x51, 0x20, 0xE9,
5088 0x9F, 0xFF, 0x20, 0xEA,
5089
5090 0x16, 0x0E, 0x20, 0xE9,
5091 0x57, 0x2E, 0xBF, 0xEA,
5092
5093 0x0B, 0x46, 0xA0, 0xE8,
5094 0x1B, 0x56, 0xA0, 0xE8,
5095
5096 0x2B, 0x66, 0xA0, 0xE8,
5097 0x0C, 0x47, 0xA0, 0xE8,
5098
5099 0x1C, 0x57, 0xA0, 0xE8,
5100 0x2C, 0x67, 0xA0, 0xE8,
5101
5102 0x0B, 0x00,
5103 0x1B, 0x00,
5104 0x2B, 0x00,
5105 0x00, 0xE0,
5106
5107 0x0C, 0x00,
5108 0x1C, 0x00,
5109 0x2C, 0x00,
5110 0x00, 0xE0,
5111
5112 0x0B, 0x65,
5113 0x1B, 0x65,
5114 0x2B, 0x65,
5115 0x00, 0xE0,
5116
5117 0x0C, 0x65,
5118 0x1C, 0x65,
5119 0x2C, 0x65,
5120 0x00, 0xE0,
5121
5122 0x0B, 0x1B, 0x60, 0xEC,
5123 0x36, 0xD7, 0x36, 0xAD,
5124
5125 0x2B, 0x80, 0x60, 0xEC,
5126 0x0C, 0x1C, 0x60, 0xEC,
5127
5128 0x3E, 0xD7, 0x3E, 0xAD,
5129 0x2C, 0x80, 0x60, 0xEC,
5130
5131 0x0B, 0x2B, 0xDE, 0xE8,
5132 0x1B, 0x80, 0xDE, 0xE8,
5133
5134 0x36, 0x80, 0x36, 0xBD,
5135 0x3E, 0x80, 0x3E, 0xBD,
5136
5137 0x33, 0xD7, 0x0B, 0xBD,
5138 0x3B, 0xD7, 0x1B, 0xBD,
5139
5140 0x46, 0x80, 0x46, 0xCF,
5141 0x57, 0x80, 0x57, 0xCF,
5142
5143 0x66, 0x33, 0x66, 0xCF,
5144 0x47, 0x3B, 0x47, 0xCF,
5145
5146 0x56, 0x33, 0x56, 0xCF,
5147 0x67, 0x3B, 0x67, 0xCF,
5148
5149 0x0B, 0x48, 0xA0, 0xE8,
5150 0x1B, 0x58, 0xA0, 0xE8,
5151
5152 0x2B, 0x68, 0xA0, 0xE8,
5153 0x0C, 0x49, 0xA0, 0xE8,
5154
5155 0x1C, 0x59, 0xA0, 0xE8,
5156 0x2C, 0x69, 0xA0, 0xE8,
5157
5158 0x0B, 0x00,
5159 0x1B, 0x00,
5160 0x2B, 0x00,
5161 0x00, 0xE0,
5162
5163 0x0C, 0x00,
5164 0x1C, 0x00,
5165 0x2C, 0x00,
5166 0x00, 0xE0,
5167
5168 0x0B, 0x65,
5169 0x1B, 0x65,
5170 0x2B, 0x65,
5171 0x00, 0xE0,
5172
5173 0x0C, 0x65,
5174 0x1C, 0x65,
5175 0x2C, 0x65,
5176 0x00, 0xE0,
5177
5178 0x0B, 0x1B, 0x60, 0xEC,
5179 0x34, 0xD7, 0x34, 0xAD,
5180
5181 0x2B, 0x80, 0x60, 0xEC,
5182 0x0C, 0x1C, 0x60, 0xEC,
5183
5184 0x3C, 0xD7, 0x3C, 0xAD,
5185 0x2C, 0x80, 0x60, 0xEC,
5186
5187 0x0B, 0x2B, 0xDE, 0xE8,
5188 0x1B, 0x80, 0xDE, 0xE8,
5189
5190 0x34, 0x80, 0x34, 0xBD,
5191 0x3C, 0x80, 0x3C, 0xBD,
5192
5193 0x33, 0xD7, 0x0B, 0xBD,
5194 0x3B, 0xD7, 0x1B, 0xBD,
5195
5196 0x48, 0x80, 0x48, 0xCF,
5197 0x59, 0x80, 0x59, 0xCF,
5198
5199 0x68, 0x33, 0x68, 0xCF,
5200 0x49, 0x3B, 0x49, 0xCF,
5201
5202 0xBE, 0xFF, 0x20, 0xEA,
5203 0x00, 0x80, 0x00, 0xE8,
5204
5205 0x58, 0x33, 0x58, 0xCF,
5206 0x69, 0x3B, 0x69, 0xCF,
5207
5208 0x7D, 0xFF, 0x20, 0xEA,
5209 0x57, 0xC0, 0xBF, 0xEA,
5210
5211 0x00, 0x80, 0xA0, 0xE9,
5212 0x00, 0x00, 0xD8, 0xEC,
5213
5214};
5215
5216static unsigned char warp_g400_t2gza[] = {
5217
5218 0x00, 0x8A, 0x98, 0xE9,
5219 0x00, 0x80, 0x00, 0xE8,
5220
5221 0x00, 0x80, 0xA0, 0xE9,
5222 0x00, 0x00, 0xD8, 0xEC,
5223
5224 0xFF, 0x80, 0xC0, 0xE9,
5225 0x00, 0x80, 0x00, 0xE8,
5226
5227 0x0A, 0x40, 0x50, 0xBF,
5228 0x2A, 0x40, 0x60, 0xBF,
5229
5230 0x32, 0x41, 0x51, 0xBF,
5231 0x3A, 0x41, 0x61, 0xBF,
5232
5233 0xC3, 0x6B,
5234 0xD3, 0x6B,
5235 0x00, 0x8A, 0x98, 0xE9,
5236
5237 0x73, 0x7B, 0xC8, 0xEC,
5238 0x96, 0xE2,
5239 0x41, 0x04,
5240
5241 0x7B, 0x43, 0xA0, 0xE8,
5242 0x73, 0x53, 0xA0, 0xE8,
5243
5244 0xAD, 0xEE, 0x23, 0x9F,
5245 0x00, 0xE0,
5246 0x51, 0x04,
5247
5248 0x90, 0xE2,
5249 0x61, 0x04,
5250 0x31, 0x46, 0xB1, 0xE8,
5251
5252 0x51, 0x41, 0xE0, 0xEC,
5253 0x39, 0x67, 0xB1, 0xE8,
5254
5255 0x00, 0x04,
5256 0x46, 0xE2,
5257 0x73, 0x63, 0xA0, 0xE8,
5258
5259 0x61, 0x41, 0xE0, 0xEC,
5260 0x31, 0x00,
5261 0x39, 0x00,
5262
5263 0x7C, 0x80, 0x15, 0xEA,
5264 0x10, 0x04,
5265 0x20, 0x04,
5266
5267 0x61, 0x51, 0xE0, 0xEC,
5268 0x2F, 0x41, 0x60, 0xEA,
5269
5270 0x31, 0x20,
5271 0x39, 0x20,
5272 0x1F, 0x42, 0xA0, 0xE8,
5273
5274 0x2A, 0x42, 0x52, 0xBF,
5275 0x0F, 0x52, 0xA0, 0xE8,
5276
5277 0x1A, 0x42, 0x62, 0xBF,
5278 0x1E, 0x51, 0x60, 0xEA,
5279
5280 0x73, 0x7B, 0xC8, 0xEC,
5281 0x0E, 0x61, 0x60, 0xEA,
5282
5283 0x32, 0x40, 0x50, 0xBD,
5284 0x22, 0x40, 0x60, 0xBD,
5285
5286 0x12, 0x41, 0x51, 0xBD,
5287 0x3A, 0x41, 0x61, 0xBD,
5288
5289 0xBF, 0x2F, 0x0E, 0xBD,
5290 0x97, 0xE2,
5291 0x7B, 0x72,
5292
5293 0x32, 0x20,
5294 0x22, 0x20,
5295 0x12, 0x20,
5296 0x3A, 0x20,
5297
5298 0x35, 0x48, 0xB1, 0xE8,
5299 0x3D, 0x59, 0xB1, 0xE8,
5300
5301 0x46, 0x31, 0x46, 0xBF,
5302 0x56, 0x31, 0x56, 0xBF,
5303
5304 0xB3, 0xE2, 0x2D, 0x9F,
5305 0x00, 0x80, 0x00, 0xE8,
5306
5307 0x66, 0x31, 0x66, 0xBF,
5308 0x47, 0x39, 0x47, 0xBF,
5309
5310 0x57, 0x39, 0x57, 0xBF,
5311 0x67, 0x39, 0x67, 0xBF,
5312
5313 0x6D, 0x80, 0x07, 0xEA,
5314 0x24, 0x41, 0x20, 0xE9,
5315
5316 0x35, 0x00,
5317 0x3D, 0x00,
5318 0x00, 0xE0,
5319 0x2D, 0x73,
5320
5321 0x33, 0x72,
5322 0x0C, 0xE3,
5323 0x8D, 0x2F, 0x1E, 0xBD,
5324
5325 0x43, 0x75, 0xF8, 0xEC,
5326 0x35, 0x20,
5327 0x3D, 0x20,
5328
5329 0x43, 0x43, 0x2D, 0xDF,
5330 0x53, 0x53, 0x2D, 0xDF,
5331
5332 0xAE, 0x1E, 0x0E, 0xBD,
5333 0x58, 0xE3,
5334 0x33, 0x66,
5335
5336 0x48, 0x35, 0x48, 0xBF,
5337 0x58, 0x35, 0x58, 0xBF,
5338
5339 0x68, 0x35, 0x68, 0xBF,
5340 0x49, 0x3D, 0x49, 0xBF,
5341
5342 0x59, 0x3D, 0x59, 0xBF,
5343 0x69, 0x3D, 0x69, 0xBF,
5344
5345 0x63, 0x63, 0x2D, 0xDF,
5346 0x4D, 0x7D, 0xF8, 0xEC,
5347
5348 0x59, 0xE3,
5349 0x00, 0xE0,
5350 0xB8, 0x38, 0x33, 0xBF,
5351
5352 0x2D, 0x73,
5353 0x30, 0x76,
5354 0x18, 0x3A, 0x41, 0xE9,
5355
5356 0x3F, 0x53, 0xA0, 0xE8,
5357 0x05, 0x80, 0x3D, 0xEA,
5358
5359 0x37, 0x43, 0xA0, 0xE8,
5360 0x3D, 0x63, 0xA0, 0xE8,
5361
5362 0x50, 0x70, 0xF8, 0xEC,
5363 0x2B, 0x50, 0x3C, 0xE9,
5364
5365 0x1F, 0x0F, 0xBC, 0xE8,
5366 0x00, 0x80, 0x00, 0xE8,
5367
5368 0x59, 0x78, 0xF8, 0xEC,
5369 0x00, 0x80, 0x00, 0xE8,
5370
5371 0x15, 0xC0, 0x20, 0xE9,
5372 0x15, 0xC0, 0x20, 0xE9,
5373
5374 0x15, 0xC0, 0x20, 0xE9,
5375 0x15, 0xC0, 0x20, 0xE9,
5376
5377 0x1E, 0x12, 0x41, 0xE9,
5378 0x1A, 0x22, 0x41, 0xE9,
5379
5380 0x46, 0x37, 0x46, 0xDF,
5381 0x56, 0x3F, 0x56, 0xDF,
5382
5383 0x2B, 0x40, 0x3D, 0xE9,
5384 0x66, 0x3D, 0x66, 0xDF,
5385
5386 0x1D, 0x32, 0x41, 0xE9,
5387 0x67, 0x3D, 0x67, 0xDF,
5388
5389 0x47, 0x37, 0x47, 0xDF,
5390 0x57, 0x3F, 0x57, 0xDF,
5391
5392 0x2A, 0x40, 0x20, 0xE9,
5393 0x59, 0x3F, 0x59, 0xDF,
5394
5395 0x16, 0x30, 0x20, 0xE9,
5396 0x69, 0x3D, 0x69, 0xDF,
5397
5398 0x48, 0x37, 0x48, 0xDF,
5399 0x58, 0x3F, 0x58, 0xDF,
5400
5401 0x12, 0x12, 0x2D, 0xDF,
5402 0x22, 0x22, 0x2D, 0xDF,
5403
5404 0x32, 0x32, 0x2D, 0xDF,
5405 0x3A, 0x3A, 0x2D, 0xDF,
5406
5407 0x68, 0x3D, 0x68, 0xDF,
5408 0x49, 0x37, 0x49, 0xDF,
5409
5410 0x3D, 0xCF, 0x74, 0xC0,
5411 0x37, 0xCF, 0x74, 0xC4,
5412
5413 0x31, 0x53, 0x2F, 0x9F,
5414 0x34, 0x80, 0x20, 0xE9,
5415
5416 0x39, 0xE5, 0x2C, 0x9F,
5417 0x3C, 0x3D, 0x20, 0xE9,
5418
5419 0x0A, 0x44, 0x54, 0xB0,
5420 0x02, 0x44, 0x64, 0xB0,
5421
5422 0x2A, 0x44, 0x54, 0xB2,
5423 0x1A, 0x44, 0x64, 0xB2,
5424
5425 0x29, 0x80, 0x3A, 0xEA,
5426 0x0A, 0x20,
5427 0x02, 0x20,
5428
5429 0x0F, 0xCF, 0x74, 0xC6,
5430 0x3D, 0xCF, 0x74, 0xC2,
5431
5432 0x88, 0x73, 0x5E, 0xE9,
5433 0x2A, 0x20,
5434 0x1A, 0x20,
5435
5436 0x30, 0x50, 0x2E, 0x9F,
5437 0x32, 0x31, 0x5F, 0xE9,
5438
5439 0x38, 0x21, 0x2C, 0x9F,
5440 0x33, 0x39, 0x5F, 0xE9,
5441
5442 0x31, 0x53, 0x2F, 0x9F,
5443 0x9C, 0x0F, 0x20, 0xE9,
5444
5445 0x0A, 0x44, 0x54, 0xB4,
5446 0x02, 0x44, 0x64, 0xB4,
5447
5448 0x2A, 0x44, 0x54, 0xB6,
5449 0x1A, 0x44, 0x64, 0xB6,
5450
5451 0x39, 0xE5, 0x2C, 0x9F,
5452 0x38, 0x3D, 0x20, 0xE9,
5453
5454 0x0A, 0x20,
5455 0x02, 0x20,
5456 0x2A, 0x20,
5457 0x1A, 0x20,
5458
5459 0x0A, 0x47, 0x57, 0xBF,
5460 0x02, 0x47, 0x67, 0xBF,
5461
5462 0x30, 0x50, 0x2E, 0x9F,
5463 0x3E, 0x30, 0x4F, 0xE9,
5464
5465 0x38, 0x21, 0x2C, 0x9F,
5466 0x3F, 0x38, 0x4F, 0xE9,
5467
5468 0x2A, 0x46, 0x56, 0xBF,
5469 0x1A, 0x46, 0x66, 0xBF,
5470
5471 0x31, 0x53, 0x2F, 0x9F,
5472 0x3A, 0x31, 0x4F, 0xE9,
5473
5474 0x39, 0xE5, 0x2C, 0x9F,
5475 0x3B, 0x39, 0x4F, 0xE9,
5476
5477 0x31, 0x53, 0x2F, 0x9F,
5478 0x36, 0x30, 0x4F, 0xE9,
5479
5480 0x39, 0xE5, 0x2C, 0x9F,
5481 0x37, 0x38, 0x4F, 0xE9,
5482
5483 0x2A, 0x43, 0x53, 0xBF,
5484 0x1A, 0x43, 0x63, 0xBF,
5485
5486 0x30, 0x50, 0x2E, 0x9F,
5487 0x9D, 0x31, 0x4F, 0xE9,
5488
5489 0x38, 0x21, 0x2C, 0x9F,
5490 0x9E, 0x39, 0x4F, 0xE9,
5491
5492 0x0A, 0x48, 0x58, 0xBF,
5493 0x02, 0x48, 0x68, 0xBF,
5494
5495 0x31, 0x53, 0x2F, 0x9F,
5496 0x80, 0x31, 0x57, 0xE9,
5497
5498 0x39, 0xE5, 0x2C, 0x9F,
5499 0x81, 0x39, 0x57, 0xE9,
5500
5501 0x2A, 0x49, 0x59, 0xBF,
5502 0x1A, 0x49, 0x69, 0xBF,
5503
5504 0x30, 0x50, 0x2E, 0x9F,
5505 0x82, 0x30, 0x57, 0xE9,
5506
5507 0x38, 0x21, 0x2C, 0x9F,
5508 0x83, 0x38, 0x57, 0xE9,
5509
5510 0x31, 0x53, 0x2F, 0x9F,
5511 0x84, 0x31, 0x5E, 0xE9,
5512
5513 0x39, 0xE5, 0x2C, 0x9F,
5514 0x85, 0x39, 0x5E, 0xE9,
5515
5516 0x86, 0x76, 0x57, 0xE9,
5517 0x8A, 0x36, 0x20, 0xE9,
5518
5519 0x87, 0x77, 0x57, 0xE9,
5520 0x8B, 0x3E, 0xBF, 0xEA,
5521
5522 0x80, 0x30, 0x57, 0xE9,
5523 0x81, 0x38, 0x57, 0xE9,
5524
5525 0x82, 0x31, 0x57, 0xE9,
5526 0x86, 0x78, 0x57, 0xE9,
5527
5528 0x83, 0x39, 0x57, 0xE9,
5529 0x87, 0x79, 0x57, 0xE9,
5530
5531 0x30, 0x1F, 0x5F, 0xE9,
5532 0x8A, 0x34, 0x20, 0xE9,
5533
5534 0x8B, 0x3C, 0x20, 0xE9,
5535 0x37, 0x50, 0x60, 0xBD,
5536
5537 0x57, 0x0D, 0x20, 0xE9,
5538 0x35, 0x51, 0x61, 0xBD,
5539
5540 0x2B, 0x50, 0x20, 0xE9,
5541 0x1D, 0x37, 0xE1, 0xEA,
5542
5543 0x1E, 0x35, 0xE1, 0xEA,
5544 0x00, 0xE0,
5545 0x0E, 0x77,
5546
5547 0x24, 0x51, 0x20, 0xE9,
5548 0x9B, 0xFF, 0x20, 0xEA,
5549
5550 0x16, 0x0E, 0x20, 0xE9,
5551 0x57, 0x2E, 0xBF, 0xEA,
5552
5553 0x0B, 0x46, 0xA0, 0xE8,
5554 0x1B, 0x56, 0xA0, 0xE8,
5555
5556 0x2B, 0x66, 0xA0, 0xE8,
5557 0x0C, 0x47, 0xA0, 0xE8,
5558
5559 0x1C, 0x57, 0xA0, 0xE8,
5560 0x2C, 0x67, 0xA0, 0xE8,
5561
5562 0x0B, 0x00,
5563 0x1B, 0x00,
5564 0x2B, 0x00,
5565 0x00, 0xE0,
5566
5567 0x0C, 0x00,
5568 0x1C, 0x00,
5569 0x2C, 0x00,
5570 0x00, 0xE0,
5571
5572 0x0B, 0x65,
5573 0x1B, 0x65,
5574 0x2B, 0x65,
5575 0x00, 0xE0,
5576
5577 0x0C, 0x65,
5578 0x1C, 0x65,
5579 0x2C, 0x65,
5580 0x00, 0xE0,
5581
5582 0x0B, 0x1B, 0x60, 0xEC,
5583 0x36, 0xD7, 0x36, 0xAD,
5584
5585 0x2B, 0x80, 0x60, 0xEC,
5586 0x0C, 0x1C, 0x60, 0xEC,
5587
5588 0x3E, 0xD7, 0x3E, 0xAD,
5589 0x2C, 0x80, 0x60, 0xEC,
5590
5591 0x0B, 0x2B, 0xDE, 0xE8,
5592 0x1B, 0x80, 0xDE, 0xE8,
5593
5594 0x36, 0x80, 0x36, 0xBD,
5595 0x3E, 0x80, 0x3E, 0xBD,
5596
5597 0x33, 0xD7, 0x0B, 0xBD,
5598 0x3B, 0xD7, 0x1B, 0xBD,
5599
5600 0x46, 0x80, 0x46, 0xCF,
5601 0x57, 0x80, 0x57, 0xCF,
5602
5603 0x66, 0x33, 0x66, 0xCF,
5604 0x47, 0x3B, 0x47, 0xCF,
5605
5606 0x56, 0x33, 0x56, 0xCF,
5607 0x67, 0x3B, 0x67, 0xCF,
5608
5609 0x0B, 0x48, 0xA0, 0xE8,
5610 0x1B, 0x58, 0xA0, 0xE8,
5611
5612 0x2B, 0x68, 0xA0, 0xE8,
5613 0x0C, 0x49, 0xA0, 0xE8,
5614
5615 0x1C, 0x59, 0xA0, 0xE8,
5616 0x2C, 0x69, 0xA0, 0xE8,
5617
5618 0x0B, 0x00,
5619 0x1B, 0x00,
5620 0x2B, 0x00,
5621 0x00, 0xE0,
5622
5623 0x0C, 0x00,
5624 0x1C, 0x00,
5625 0x2C, 0x00,
5626 0x00, 0xE0,
5627
5628 0x0B, 0x65,
5629 0x1B, 0x65,
5630 0x2B, 0x65,
5631 0x00, 0xE0,
5632
5633 0x0C, 0x65,
5634 0x1C, 0x65,
5635 0x2C, 0x65,
5636 0x00, 0xE0,
5637
5638 0x0B, 0x1B, 0x60, 0xEC,
5639 0x34, 0xD7, 0x34, 0xAD,
5640
5641 0x2B, 0x80, 0x60, 0xEC,
5642 0x0C, 0x1C, 0x60, 0xEC,
5643
5644 0x3C, 0xD7, 0x3C, 0xAD,
5645 0x2C, 0x80, 0x60, 0xEC,
5646
5647 0x0B, 0x2B, 0xDE, 0xE8,
5648 0x1B, 0x80, 0xDE, 0xE8,
5649
5650 0x34, 0x80, 0x34, 0xBD,
5651 0x3C, 0x80, 0x3C, 0xBD,
5652
5653 0x33, 0xD7, 0x0B, 0xBD,
5654 0x3B, 0xD7, 0x1B, 0xBD,
5655
5656 0x48, 0x80, 0x48, 0xCF,
5657 0x59, 0x80, 0x59, 0xCF,
5658
5659 0x68, 0x33, 0x68, 0xCF,
5660 0x49, 0x3B, 0x49, 0xCF,
5661
5662 0xBA, 0xFF, 0x20, 0xEA,
5663 0x00, 0x80, 0x00, 0xE8,
5664
5665 0x58, 0x33, 0x58, 0xCF,
5666 0x69, 0x3B, 0x69, 0xCF,
5667
5668 0x79, 0xFF, 0x20, 0xEA,
5669 0x57, 0xC0, 0xBF, 0xEA,
5670
5671 0x00, 0x80, 0xA0, 0xE9,
5672 0x00, 0x00, 0xD8, 0xEC,
5673
5674};
5675
5676static unsigned char warp_g400_t2gzaf[] = {
5677
5678 0x00, 0x8A, 0x98, 0xE9,
5679 0x00, 0x80, 0x00, 0xE8,
5680
5681 0x00, 0x80, 0xA0, 0xE9,
5682 0x00, 0x00, 0xD8, 0xEC,
5683
5684 0xFF, 0x80, 0xC0, 0xE9,
5685 0x00, 0x80, 0x00, 0xE8,
5686
5687 0x0A, 0x40, 0x50, 0xBF,
5688 0x2A, 0x40, 0x60, 0xBF,
5689
5690 0x32, 0x41, 0x51, 0xBF,
5691 0x3A, 0x41, 0x61, 0xBF,
5692
5693 0xC3, 0x6B,
5694 0xD3, 0x6B,
5695 0x00, 0x8A, 0x98, 0xE9,
5696
5697 0x73, 0x7B, 0xC8, 0xEC,
5698 0x96, 0xE2,
5699 0x41, 0x04,
5700
5701 0x7B, 0x43, 0xA0, 0xE8,
5702 0x73, 0x53, 0xA0, 0xE8,
5703
5704 0xAD, 0xEE, 0x23, 0x9F,
5705 0x00, 0xE0,
5706 0x51, 0x04,
5707
5708 0x90, 0xE2,
5709 0x61, 0x04,
5710 0x31, 0x46, 0xB1, 0xE8,
5711
5712 0x51, 0x41, 0xE0, 0xEC,
5713 0x39, 0x67, 0xB1, 0xE8,
5714
5715 0x00, 0x04,
5716 0x46, 0xE2,
5717 0x73, 0x63, 0xA0, 0xE8,
5718
5719 0x61, 0x41, 0xE0, 0xEC,
5720 0x31, 0x00,
5721 0x39, 0x00,
5722
5723 0x81, 0x80, 0x15, 0xEA,
5724 0x10, 0x04,
5725 0x20, 0x04,
5726
5727 0x61, 0x51, 0xE0, 0xEC,
5728 0x2F, 0x41, 0x60, 0xEA,
5729
5730 0x31, 0x20,
5731 0x39, 0x20,
5732 0x1F, 0x42, 0xA0, 0xE8,
5733
5734 0x2A, 0x42, 0x52, 0xBF,
5735 0x0F, 0x52, 0xA0, 0xE8,
5736
5737 0x1A, 0x42, 0x62, 0xBF,
5738 0x1E, 0x51, 0x60, 0xEA,
5739
5740 0x73, 0x7B, 0xC8, 0xEC,
5741 0x0E, 0x61, 0x60, 0xEA,
5742
5743 0x32, 0x40, 0x50, 0xBD,
5744 0x22, 0x40, 0x60, 0xBD,
5745
5746 0x12, 0x41, 0x51, 0xBD,
5747 0x3A, 0x41, 0x61, 0xBD,
5748
5749 0xBF, 0x2F, 0x0E, 0xBD,
5750 0x97, 0xE2,
5751 0x7B, 0x72,
5752
5753 0x32, 0x20,
5754 0x22, 0x20,
5755 0x12, 0x20,
5756 0x3A, 0x20,
5757
5758 0x35, 0x48, 0xB1, 0xE8,
5759 0x3D, 0x59, 0xB1, 0xE8,
5760
5761 0x46, 0x31, 0x46, 0xBF,
5762 0x56, 0x31, 0x56, 0xBF,
5763
5764 0xB3, 0xE2, 0x2D, 0x9F,
5765 0x00, 0x80, 0x00, 0xE8,
5766
5767 0x66, 0x31, 0x66, 0xBF,
5768 0x47, 0x39, 0x47, 0xBF,
5769
5770 0x57, 0x39, 0x57, 0xBF,
5771 0x67, 0x39, 0x67, 0xBF,
5772
5773 0x72, 0x80, 0x07, 0xEA,
5774 0x24, 0x41, 0x20, 0xE9,
5775
5776 0x35, 0x00,
5777 0x3D, 0x00,
5778 0x00, 0xE0,
5779 0x2D, 0x73,
5780
5781 0x33, 0x72,
5782 0x0C, 0xE3,
5783 0x8D, 0x2F, 0x1E, 0xBD,
5784
5785 0x43, 0x75, 0xF8, 0xEC,
5786 0x35, 0x20,
5787 0x3D, 0x20,
5788
5789 0x43, 0x43, 0x2D, 0xDF,
5790 0x53, 0x53, 0x2D, 0xDF,
5791
5792 0xAE, 0x1E, 0x0E, 0xBD,
5793 0x58, 0xE3,
5794 0x33, 0x66,
5795
5796 0x48, 0x35, 0x48, 0xBF,
5797 0x58, 0x35, 0x58, 0xBF,
5798
5799 0x68, 0x35, 0x68, 0xBF,
5800 0x49, 0x3D, 0x49, 0xBF,
5801
5802 0x59, 0x3D, 0x59, 0xBF,
5803 0x69, 0x3D, 0x69, 0xBF,
5804
5805 0x63, 0x63, 0x2D, 0xDF,
5806 0x4D, 0x7D, 0xF8, 0xEC,
5807
5808 0x59, 0xE3,
5809 0x00, 0xE0,
5810 0xB8, 0x38, 0x33, 0xBF,
5811
5812 0x2D, 0x73,
5813 0x30, 0x76,
5814 0x18, 0x3A, 0x41, 0xE9,
5815
5816 0x3F, 0x53, 0xA0, 0xE8,
5817 0x05, 0x80, 0x3D, 0xEA,
5818
5819 0x37, 0x43, 0xA0, 0xE8,
5820 0x3D, 0x63, 0xA0, 0xE8,
5821
5822 0x50, 0x70, 0xF8, 0xEC,
5823 0x2B, 0x50, 0x3C, 0xE9,
5824
5825 0x1F, 0x0F, 0xBC, 0xE8,
5826 0x00, 0x80, 0x00, 0xE8,
5827
5828 0x59, 0x78, 0xF8, 0xEC,
5829 0x00, 0x80, 0x00, 0xE8,
5830
5831 0x15, 0xC0, 0x20, 0xE9,
5832 0x15, 0xC0, 0x20, 0xE9,
5833
5834 0x15, 0xC0, 0x20, 0xE9,
5835 0x15, 0xC0, 0x20, 0xE9,
5836
5837 0x1E, 0x12, 0x41, 0xE9,
5838 0x1A, 0x22, 0x41, 0xE9,
5839
5840 0x46, 0x37, 0x46, 0xDF,
5841 0x56, 0x3F, 0x56, 0xDF,
5842
5843 0x2B, 0x40, 0x3D, 0xE9,
5844 0x66, 0x3D, 0x66, 0xDF,
5845
5846 0x1D, 0x32, 0x41, 0xE9,
5847 0x67, 0x3D, 0x67, 0xDF,
5848
5849 0x47, 0x37, 0x47, 0xDF,
5850 0x57, 0x3F, 0x57, 0xDF,
5851
5852 0x2A, 0x40, 0x20, 0xE9,
5853 0x59, 0x3F, 0x59, 0xDF,
5854
5855 0x16, 0x30, 0x20, 0xE9,
5856 0x69, 0x3D, 0x69, 0xDF,
5857
5858 0x48, 0x37, 0x48, 0xDF,
5859 0x58, 0x3F, 0x58, 0xDF,
5860
5861 0x12, 0x12, 0x2D, 0xDF,
5862 0x22, 0x22, 0x2D, 0xDF,
5863
5864 0x32, 0x32, 0x2D, 0xDF,
5865 0x3A, 0x3A, 0x2D, 0xDF,
5866
5867 0x68, 0x3D, 0x68, 0xDF,
5868 0x49, 0x37, 0x49, 0xDF,
5869
5870 0x3D, 0xCF, 0x74, 0xC0,
5871 0x37, 0xCF, 0x74, 0xC4,
5872
5873 0x0A, 0x44, 0x54, 0xB0,
5874 0x02, 0x44, 0x64, 0xB0,
5875
5876 0x31, 0x53, 0x2F, 0x9F,
5877 0x34, 0x37, 0x20, 0xE9,
5878
5879 0x39, 0xE5, 0x2C, 0x9F,
5880 0x3C, 0x3D, 0x20, 0xE9,
5881
5882 0x2A, 0x44, 0x54, 0xB2,
5883 0x1A, 0x44, 0x64, 0xB2,
5884
5885 0x2E, 0x80, 0x3A, 0xEA,
5886 0x0A, 0x20,
5887 0x02, 0x20,
5888
5889 0x88, 0x73, 0x5E, 0xE9,
5890 0x2A, 0x20,
5891 0x1A, 0x20,
5892
5893 0x3D, 0xCF, 0x74, 0xC2,
5894 0x0F, 0xCF, 0x74, 0xC6,
5895
5896 0x30, 0x50, 0x2E, 0x9F,
5897 0x32, 0x31, 0x5F, 0xE9,
5898
5899 0x38, 0x21, 0x2C, 0x9F,
5900 0x33, 0x39, 0x5F, 0xE9,
5901
5902 0x31, 0x53, 0x2F, 0x9F,
5903 0x9C, 0x0F, 0x20, 0xE9,
5904
5905 0x0A, 0x44, 0x54, 0xB4,
5906 0x02, 0x44, 0x64, 0xB4,
5907
5908 0x2A, 0x44, 0x54, 0xB6,
5909 0x1A, 0x44, 0x64, 0xB6,
5910
5911 0x39, 0xE5, 0x2C, 0x9F,
5912 0x38, 0x3D, 0x20, 0xE9,
5913
5914 0x0A, 0x20,
5915 0x02, 0x20,
5916 0x2A, 0x20,
5917 0x1A, 0x20,
5918
5919 0x3D, 0xCF, 0x75, 0xC6,
5920 0x00, 0x80, 0x00, 0xE8,
5921
5922 0x30, 0x50, 0x2E, 0x9F,
5923 0x3E, 0x30, 0x4F, 0xE9,
5924
5925 0x38, 0x21, 0x2C, 0x9F,
5926 0x3F, 0x38, 0x4F, 0xE9,
5927
5928 0x0A, 0x45, 0x55, 0xB6,
5929 0x02, 0x45, 0x65, 0xB6,
5930
5931 0x31, 0x53, 0x2F, 0x9F,
5932 0x3A, 0x31, 0x4F, 0xE9,
5933
5934 0x39, 0xE5, 0x2C, 0x9F,
5935 0x3B, 0x39, 0x4F, 0xE9,
5936
5937 0x31, 0x3D, 0x20, 0xE9,
5938 0x0A, 0x20,
5939 0x02, 0x20,
5940
5941 0x2A, 0x46, 0x56, 0xBF,
5942 0x1A, 0x46, 0x66, 0xBF,
5943
5944 0x0A, 0x47, 0x57, 0xBF,
5945 0x02, 0x47, 0x67, 0xBF,
5946
5947 0x30, 0x50, 0x2E, 0x9F,
5948 0x36, 0x30, 0x4F, 0xE9,
5949
5950 0x38, 0x21, 0x2C, 0x9F,
5951 0x37, 0x38, 0x4F, 0xE9,
5952
5953 0x31, 0x53, 0x2F, 0x9F,
5954 0x9D, 0x31, 0x4F, 0xE9,
5955
5956 0x39, 0xE5, 0x2C, 0x9F,
5957 0x9E, 0x39, 0x4F, 0xE9,
5958
5959 0x2A, 0x43, 0x53, 0xBF,
5960 0x1A, 0x43, 0x63, 0xBF,
5961
5962 0x30, 0x50, 0x2E, 0x9F,
5963 0x35, 0x30, 0x4F, 0xE9,
5964
5965 0x38, 0x21, 0x2C, 0x9F,
5966 0x39, 0x38, 0x4F, 0xE9,
5967
5968 0x0A, 0x48, 0x58, 0xBF,
5969 0x02, 0x48, 0x68, 0xBF,
5970
5971 0x31, 0x53, 0x2F, 0x9F,
5972 0x80, 0x31, 0x57, 0xE9,
5973
5974 0x39, 0xE5, 0x2C, 0x9F,
5975 0x81, 0x39, 0x57, 0xE9,
5976
5977 0x2A, 0x49, 0x59, 0xBF,
5978 0x1A, 0x49, 0x69, 0xBF,
5979
5980 0x30, 0x50, 0x2E, 0x9F,
5981 0x82, 0x30, 0x57, 0xE9,
5982
5983 0x38, 0x21, 0x2C, 0x9F,
5984 0x83, 0x38, 0x57, 0xE9,
5985
5986 0x31, 0x53, 0x2F, 0x9F,
5987 0x84, 0x31, 0x5E, 0xE9,
5988
5989 0x39, 0xE5, 0x2C, 0x9F,
5990 0x85, 0x39, 0x5E, 0xE9,
5991
5992 0x86, 0x76, 0x57, 0xE9,
5993 0x8A, 0x36, 0x20, 0xE9,
5994
5995 0x87, 0x77, 0x57, 0xE9,
5996 0x8B, 0x3E, 0xBF, 0xEA,
5997
5998 0x80, 0x30, 0x57, 0xE9,
5999 0x81, 0x38, 0x57, 0xE9,
6000
6001 0x82, 0x31, 0x57, 0xE9,
6002 0x86, 0x78, 0x57, 0xE9,
6003
6004 0x83, 0x39, 0x57, 0xE9,
6005 0x87, 0x79, 0x57, 0xE9,
6006
6007 0x30, 0x1F, 0x5F, 0xE9,
6008 0x8A, 0x34, 0x20, 0xE9,
6009
6010 0x8B, 0x3C, 0x20, 0xE9,
6011 0x37, 0x50, 0x60, 0xBD,
6012
6013 0x57, 0x0D, 0x20, 0xE9,
6014 0x35, 0x51, 0x61, 0xBD,
6015
6016 0x2B, 0x50, 0x20, 0xE9,
6017 0x1D, 0x37, 0xE1, 0xEA,
6018
6019 0x1E, 0x35, 0xE1, 0xEA,
6020 0x00, 0xE0,
6021 0x0E, 0x77,
6022
6023 0x24, 0x51, 0x20, 0xE9,
6024 0x96, 0xFF, 0x20, 0xEA,
6025
6026 0x16, 0x0E, 0x20, 0xE9,
6027 0x57, 0x2E, 0xBF, 0xEA,
6028
6029 0x0B, 0x46, 0xA0, 0xE8,
6030 0x1B, 0x56, 0xA0, 0xE8,
6031
6032 0x2B, 0x66, 0xA0, 0xE8,
6033 0x0C, 0x47, 0xA0, 0xE8,
6034
6035 0x1C, 0x57, 0xA0, 0xE8,
6036 0x2C, 0x67, 0xA0, 0xE8,
6037
6038 0x0B, 0x00,
6039 0x1B, 0x00,
6040 0x2B, 0x00,
6041 0x00, 0xE0,
6042
6043 0x0C, 0x00,
6044 0x1C, 0x00,
6045 0x2C, 0x00,
6046 0x00, 0xE0,
6047
6048 0x0B, 0x65,
6049 0x1B, 0x65,
6050 0x2B, 0x65,
6051 0x00, 0xE0,
6052
6053 0x0C, 0x65,
6054 0x1C, 0x65,
6055 0x2C, 0x65,
6056 0x00, 0xE0,
6057
6058 0x0B, 0x1B, 0x60, 0xEC,
6059 0x36, 0xD7, 0x36, 0xAD,
6060
6061 0x2B, 0x80, 0x60, 0xEC,
6062 0x0C, 0x1C, 0x60, 0xEC,
6063
6064 0x3E, 0xD7, 0x3E, 0xAD,
6065 0x2C, 0x80, 0x60, 0xEC,
6066
6067 0x0B, 0x2B, 0xDE, 0xE8,
6068 0x1B, 0x80, 0xDE, 0xE8,
6069
6070 0x36, 0x80, 0x36, 0xBD,
6071 0x3E, 0x80, 0x3E, 0xBD,
6072
6073 0x33, 0xD7, 0x0B, 0xBD,
6074 0x3B, 0xD7, 0x1B, 0xBD,
6075
6076 0x46, 0x80, 0x46, 0xCF,
6077 0x57, 0x80, 0x57, 0xCF,
6078
6079 0x66, 0x33, 0x66, 0xCF,
6080 0x47, 0x3B, 0x47, 0xCF,
6081
6082 0x56, 0x33, 0x56, 0xCF,
6083 0x67, 0x3B, 0x67, 0xCF,
6084
6085 0x0B, 0x48, 0xA0, 0xE8,
6086 0x1B, 0x58, 0xA0, 0xE8,
6087
6088 0x2B, 0x68, 0xA0, 0xE8,
6089 0x0C, 0x49, 0xA0, 0xE8,
6090
6091 0x1C, 0x59, 0xA0, 0xE8,
6092 0x2C, 0x69, 0xA0, 0xE8,
6093
6094 0x0B, 0x00,
6095 0x1B, 0x00,
6096 0x2B, 0x00,
6097 0x00, 0xE0,
6098
6099 0x0C, 0x00,
6100 0x1C, 0x00,
6101 0x2C, 0x00,
6102 0x00, 0xE0,
6103
6104 0x0B, 0x65,
6105 0x1B, 0x65,
6106 0x2B, 0x65,
6107 0x00, 0xE0,
6108
6109 0x0C, 0x65,
6110 0x1C, 0x65,
6111 0x2C, 0x65,
6112 0x00, 0xE0,
6113
6114 0x0B, 0x1B, 0x60, 0xEC,
6115 0x34, 0xD7, 0x34, 0xAD,
6116
6117 0x2B, 0x80, 0x60, 0xEC,
6118 0x0C, 0x1C, 0x60, 0xEC,
6119
6120 0x3C, 0xD7, 0x3C, 0xAD,
6121 0x2C, 0x80, 0x60, 0xEC,
6122
6123 0x0B, 0x2B, 0xDE, 0xE8,
6124 0x1B, 0x80, 0xDE, 0xE8,
6125
6126 0x34, 0x80, 0x34, 0xBD,
6127 0x3C, 0x80, 0x3C, 0xBD,
6128
6129 0x33, 0xD7, 0x0B, 0xBD,
6130 0x3B, 0xD7, 0x1B, 0xBD,
6131
6132 0x48, 0x80, 0x48, 0xCF,
6133 0x59, 0x80, 0x59, 0xCF,
6134
6135 0x68, 0x33, 0x68, 0xCF,
6136 0x49, 0x3B, 0x49, 0xCF,
6137
6138 0xB5, 0xFF, 0x20, 0xEA,
6139 0x00, 0x80, 0x00, 0xE8,
6140
6141 0x58, 0x33, 0x58, 0xCF,
6142 0x69, 0x3B, 0x69, 0xCF,
6143
6144 0x74, 0xFF, 0x20, 0xEA,
6145 0x57, 0xC0, 0xBF, 0xEA,
6146
6147 0x00, 0x80, 0xA0, 0xE9,
6148 0x00, 0x00, 0xD8, 0xEC,
6149
6150};
6151
6152static unsigned char warp_g400_t2gzf[] = {
6153
6154 0x00, 0x8A, 0x98, 0xE9,
6155 0x00, 0x80, 0x00, 0xE8,
6156
6157 0x00, 0x80, 0xA0, 0xE9,
6158 0x00, 0x00, 0xD8, 0xEC,
6159
6160 0xFF, 0x80, 0xC0, 0xE9,
6161 0x00, 0x80, 0x00, 0xE8,
6162
6163 0x0A, 0x40, 0x50, 0xBF,
6164 0x2A, 0x40, 0x60, 0xBF,
6165
6166 0x32, 0x41, 0x51, 0xBF,
6167 0x3A, 0x41, 0x61, 0xBF,
6168
6169 0xC3, 0x6B,
6170 0xD3, 0x6B,
6171 0x00, 0x8A, 0x98, 0xE9,
6172
6173 0x73, 0x7B, 0xC8, 0xEC,
6174 0x96, 0xE2,
6175 0x41, 0x04,
6176
6177 0x7B, 0x43, 0xA0, 0xE8,
6178 0x73, 0x53, 0xA0, 0xE8,
6179
6180 0xAD, 0xEE, 0x23, 0x9F,
6181 0x00, 0xE0,
6182 0x51, 0x04,
6183
6184 0x90, 0xE2,
6185 0x61, 0x04,
6186 0x31, 0x46, 0xB1, 0xE8,
6187
6188 0x51, 0x41, 0xE0, 0xEC,
6189 0x39, 0x67, 0xB1, 0xE8,
6190
6191 0x00, 0x04,
6192 0x46, 0xE2,
6193 0x73, 0x63, 0xA0, 0xE8,
6194
6195 0x61, 0x41, 0xE0, 0xEC,
6196 0x31, 0x00,
6197 0x39, 0x00,
6198
6199 0x7D, 0x80, 0x15, 0xEA,
6200 0x10, 0x04,
6201 0x20, 0x04,
6202
6203 0x61, 0x51, 0xE0, 0xEC,
6204 0x2F, 0x41, 0x60, 0xEA,
6205
6206 0x31, 0x20,
6207 0x39, 0x20,
6208 0x1F, 0x42, 0xA0, 0xE8,
6209
6210 0x2A, 0x42, 0x52, 0xBF,
6211 0x0F, 0x52, 0xA0, 0xE8,
6212
6213 0x1A, 0x42, 0x62, 0xBF,
6214 0x1E, 0x51, 0x60, 0xEA,
6215
6216 0x73, 0x7B, 0xC8, 0xEC,
6217 0x0E, 0x61, 0x60, 0xEA,
6218
6219 0x32, 0x40, 0x50, 0xBD,
6220 0x22, 0x40, 0x60, 0xBD,
6221
6222 0x12, 0x41, 0x51, 0xBD,
6223 0x3A, 0x41, 0x61, 0xBD,
6224
6225 0xBF, 0x2F, 0x0E, 0xBD,
6226 0x97, 0xE2,
6227 0x7B, 0x72,
6228
6229 0x32, 0x20,
6230 0x22, 0x20,
6231 0x12, 0x20,
6232 0x3A, 0x20,
6233
6234 0x35, 0x48, 0xB1, 0xE8,
6235 0x3D, 0x59, 0xB1, 0xE8,
6236
6237 0x46, 0x31, 0x46, 0xBF,
6238 0x56, 0x31, 0x56, 0xBF,
6239
6240 0xB3, 0xE2, 0x2D, 0x9F,
6241 0x00, 0x80, 0x00, 0xE8,
6242
6243 0x66, 0x31, 0x66, 0xBF,
6244 0x47, 0x39, 0x47, 0xBF,
6245
6246 0x57, 0x39, 0x57, 0xBF,
6247 0x67, 0x39, 0x67, 0xBF,
6248
6249 0x6E, 0x80, 0x07, 0xEA,
6250 0x24, 0x41, 0x20, 0xE9,
6251
6252 0x35, 0x00,
6253 0x3D, 0x00,
6254 0x00, 0xE0,
6255 0x2D, 0x73,
6256
6257 0x33, 0x72,
6258 0x0C, 0xE3,
6259 0x8D, 0x2F, 0x1E, 0xBD,
6260
6261 0x43, 0x75, 0xF8, 0xEC,
6262 0x35, 0x20,
6263 0x3D, 0x20,
6264
6265 0x43, 0x43, 0x2D, 0xDF,
6266 0x53, 0x53, 0x2D, 0xDF,
6267
6268 0xAE, 0x1E, 0x0E, 0xBD,
6269 0x58, 0xE3,
6270 0x33, 0x66,
6271
6272 0x48, 0x35, 0x48, 0xBF,
6273 0x58, 0x35, 0x58, 0xBF,
6274
6275 0x68, 0x35, 0x68, 0xBF,
6276 0x49, 0x3D, 0x49, 0xBF,
6277
6278 0x59, 0x3D, 0x59, 0xBF,
6279 0x69, 0x3D, 0x69, 0xBF,
6280
6281 0x63, 0x63, 0x2D, 0xDF,
6282 0x4D, 0x7D, 0xF8, 0xEC,
6283
6284 0x59, 0xE3,
6285 0x00, 0xE0,
6286 0xB8, 0x38, 0x33, 0xBF,
6287
6288 0x2D, 0x73,
6289 0x30, 0x76,
6290 0x18, 0x3A, 0x41, 0xE9,
6291
6292 0x3F, 0x53, 0xA0, 0xE8,
6293 0x05, 0x80, 0x3D, 0xEA,
6294
6295 0x37, 0x43, 0xA0, 0xE8,
6296 0x3D, 0x63, 0xA0, 0xE8,
6297
6298 0x50, 0x70, 0xF8, 0xEC,
6299 0x2B, 0x50, 0x3C, 0xE9,
6300
6301 0x1F, 0x0F, 0xBC, 0xE8,
6302 0x00, 0x80, 0x00, 0xE8,
6303
6304 0x59, 0x78, 0xF8, 0xEC,
6305 0x00, 0x80, 0x00, 0xE8,
6306
6307 0x15, 0xC0, 0x20, 0xE9,
6308 0x15, 0xC0, 0x20, 0xE9,
6309
6310 0x15, 0xC0, 0x20, 0xE9,
6311 0x15, 0xC0, 0x20, 0xE9,
6312
6313 0x1E, 0x12, 0x41, 0xE9,
6314 0x1A, 0x22, 0x41, 0xE9,
6315
6316 0x46, 0x37, 0x46, 0xDF,
6317 0x56, 0x3F, 0x56, 0xDF,
6318
6319 0x2B, 0x40, 0x3D, 0xE9,
6320 0x66, 0x3D, 0x66, 0xDF,
6321
6322 0x1D, 0x32, 0x41, 0xE9,
6323 0x67, 0x3D, 0x67, 0xDF,
6324
6325 0x47, 0x37, 0x47, 0xDF,
6326 0x57, 0x3F, 0x57, 0xDF,
6327
6328 0x2A, 0x40, 0x20, 0xE9,
6329 0x59, 0x3F, 0x59, 0xDF,
6330
6331 0x16, 0x30, 0x20, 0xE9,
6332 0x69, 0x3D, 0x69, 0xDF,
6333
6334 0x48, 0x37, 0x48, 0xDF,
6335 0x58, 0x3F, 0x58, 0xDF,
6336
6337 0x12, 0x12, 0x2D, 0xDF,
6338 0x22, 0x22, 0x2D, 0xDF,
6339
6340 0x32, 0x32, 0x2D, 0xDF,
6341 0x3A, 0x3A, 0x2D, 0xDF,
6342
6343 0x68, 0x3D, 0x68, 0xDF,
6344 0x49, 0x37, 0x49, 0xDF,
6345
6346 0x3D, 0xCF, 0x74, 0xC0,
6347 0x37, 0xCF, 0x74, 0xC4,
6348
6349 0x39, 0xE5, 0x2C, 0x9F,
6350 0x34, 0x80, 0x20, 0xE9,
6351
6352 0x31, 0x53, 0x2F, 0x9F,
6353 0x00, 0x80, 0x00, 0xE8,
6354
6355 0x88, 0x73, 0x5E, 0xE9,
6356 0x00, 0x80, 0x00, 0xE8,
6357
6358 0x0F, 0xCF, 0x75, 0xC6,
6359 0x3C, 0x3D, 0x20, 0xE9,
6360
6361 0x0A, 0x44, 0x54, 0xB0,
6362 0x02, 0x44, 0x64, 0xB0,
6363
6364 0x2A, 0x44, 0x54, 0xB2,
6365 0x1A, 0x44, 0x64, 0xB2,
6366
6367 0x28, 0x80, 0x3A, 0xEA,
6368 0x0A, 0x20,
6369 0x02, 0x20,
6370
6371 0x3D, 0xCF, 0x74, 0xC2,
6372 0x2A, 0x20,
6373 0x1A, 0x20,
6374
6375 0x30, 0x50, 0x2E, 0x9F,
6376 0x32, 0x31, 0x5F, 0xE9,
6377
6378 0x38, 0x21, 0x2C, 0x9F,
6379 0x33, 0x39, 0x5F, 0xE9,
6380
6381 0x31, 0x53, 0x2F, 0x9F,
6382 0x31, 0x0F, 0x20, 0xE9,
6383
6384 0x0A, 0x44, 0x54, 0xB4,
6385 0x02, 0x44, 0x64, 0xB4,
6386
6387 0x2A, 0x45, 0x55, 0xB6,
6388 0x1A, 0x45, 0x65, 0xB6,
6389
6390 0x39, 0xE5, 0x2C, 0x9F,
6391 0x38, 0x3D, 0x20, 0xE9,
6392
6393 0x0A, 0x20,
6394 0x02, 0x20,
6395 0x2A, 0x20,
6396 0x1A, 0x20,
6397
6398 0x0A, 0x47, 0x57, 0xBF,
6399 0x02, 0x47, 0x67, 0xBF,
6400
6401 0x30, 0x50, 0x2E, 0x9F,
6402 0x3E, 0x30, 0x4F, 0xE9,
6403
6404 0x38, 0x21, 0x2C, 0x9F,
6405 0x3F, 0x38, 0x4F, 0xE9,
6406
6407 0x2A, 0x46, 0x56, 0xBF,
6408 0x1A, 0x46, 0x66, 0xBF,
6409
6410 0x31, 0x53, 0x2F, 0x9F,
6411 0x3A, 0x31, 0x4F, 0xE9,
6412
6413 0x39, 0xE5, 0x2C, 0x9F,
6414 0x3B, 0x39, 0x4F, 0xE9,
6415
6416 0x31, 0x53, 0x2F, 0x9F,
6417 0x36, 0x30, 0x4F, 0xE9,
6418
6419 0x39, 0xE5, 0x2C, 0x9F,
6420 0x37, 0x38, 0x4F, 0xE9,
6421
6422 0x2A, 0x43, 0x53, 0xBF,
6423 0x1A, 0x43, 0x63, 0xBF,
6424
6425 0x30, 0x50, 0x2E, 0x9F,
6426 0x35, 0x31, 0x4F, 0xE9,
6427
6428 0x38, 0x21, 0x2C, 0x9F,
6429 0x39, 0x39, 0x4F, 0xE9,
6430
6431 0x0A, 0x48, 0x58, 0xBF,
6432 0x02, 0x48, 0x68, 0xBF,
6433
6434 0x31, 0x53, 0x2F, 0x9F,
6435 0x80, 0x31, 0x57, 0xE9,
6436
6437 0x39, 0xE5, 0x2C, 0x9F,
6438 0x81, 0x39, 0x57, 0xE9,
6439
6440 0x2A, 0x49, 0x59, 0xBF,
6441 0x1A, 0x49, 0x69, 0xBF,
6442
6443 0x30, 0x50, 0x2E, 0x9F,
6444 0x82, 0x30, 0x57, 0xE9,
6445
6446 0x38, 0x21, 0x2C, 0x9F,
6447 0x83, 0x38, 0x57, 0xE9,
6448
6449 0x31, 0x53, 0x2F, 0x9F,
6450 0x84, 0x31, 0x5E, 0xE9,
6451
6452 0x39, 0xE5, 0x2C, 0x9F,
6453 0x85, 0x39, 0x5E, 0xE9,
6454
6455 0x86, 0x76, 0x57, 0xE9,
6456 0x8A, 0x36, 0x20, 0xE9,
6457
6458 0x87, 0x77, 0x57, 0xE9,
6459 0x8B, 0x3E, 0xBF, 0xEA,
6460
6461 0x80, 0x30, 0x57, 0xE9,
6462 0x81, 0x38, 0x57, 0xE9,
6463
6464 0x82, 0x31, 0x57, 0xE9,
6465 0x86, 0x78, 0x57, 0xE9,
6466
6467 0x83, 0x39, 0x57, 0xE9,
6468 0x87, 0x79, 0x57, 0xE9,
6469
6470 0x30, 0x1F, 0x5F, 0xE9,
6471 0x8A, 0x34, 0x20, 0xE9,
6472
6473 0x8B, 0x3C, 0x20, 0xE9,
6474 0x37, 0x50, 0x60, 0xBD,
6475
6476 0x57, 0x0D, 0x20, 0xE9,
6477 0x35, 0x51, 0x61, 0xBD,
6478
6479 0x2B, 0x50, 0x20, 0xE9,
6480 0x1D, 0x37, 0xE1, 0xEA,
6481
6482 0x1E, 0x35, 0xE1, 0xEA,
6483 0x00, 0xE0,
6484 0x0E, 0x77,
6485
6486 0x24, 0x51, 0x20, 0xE9,
6487 0x9A, 0xFF, 0x20, 0xEA,
6488
6489 0x16, 0x0E, 0x20, 0xE9,
6490 0x57, 0x2E, 0xBF, 0xEA,
6491
6492 0x0B, 0x46, 0xA0, 0xE8,
6493 0x1B, 0x56, 0xA0, 0xE8,
6494
6495 0x2B, 0x66, 0xA0, 0xE8,
6496 0x0C, 0x47, 0xA0, 0xE8,
6497
6498 0x1C, 0x57, 0xA0, 0xE8,
6499 0x2C, 0x67, 0xA0, 0xE8,
6500
6501 0x0B, 0x00,
6502 0x1B, 0x00,
6503 0x2B, 0x00,
6504 0x00, 0xE0,
6505
6506 0x0C, 0x00,
6507 0x1C, 0x00,
6508 0x2C, 0x00,
6509 0x00, 0xE0,
6510
6511 0x0B, 0x65,
6512 0x1B, 0x65,
6513 0x2B, 0x65,
6514 0x00, 0xE0,
6515
6516 0x0C, 0x65,
6517 0x1C, 0x65,
6518 0x2C, 0x65,
6519 0x00, 0xE0,
6520
6521 0x0B, 0x1B, 0x60, 0xEC,
6522 0x36, 0xD7, 0x36, 0xAD,
6523
6524 0x2B, 0x80, 0x60, 0xEC,
6525 0x0C, 0x1C, 0x60, 0xEC,
6526
6527 0x3E, 0xD7, 0x3E, 0xAD,
6528 0x2C, 0x80, 0x60, 0xEC,
6529
6530 0x0B, 0x2B, 0xDE, 0xE8,
6531 0x1B, 0x80, 0xDE, 0xE8,
6532
6533 0x36, 0x80, 0x36, 0xBD,
6534 0x3E, 0x80, 0x3E, 0xBD,
6535
6536 0x33, 0xD7, 0x0B, 0xBD,
6537 0x3B, 0xD7, 0x1B, 0xBD,
6538
6539 0x46, 0x80, 0x46, 0xCF,
6540 0x57, 0x80, 0x57, 0xCF,
6541
6542 0x66, 0x33, 0x66, 0xCF,
6543 0x47, 0x3B, 0x47, 0xCF,
6544
6545 0x56, 0x33, 0x56, 0xCF,
6546 0x67, 0x3B, 0x67, 0xCF,
6547
6548 0x0B, 0x48, 0xA0, 0xE8,
6549 0x1B, 0x58, 0xA0, 0xE8,
6550
6551 0x2B, 0x68, 0xA0, 0xE8,
6552 0x0C, 0x49, 0xA0, 0xE8,
6553
6554 0x1C, 0x59, 0xA0, 0xE8,
6555 0x2C, 0x69, 0xA0, 0xE8,
6556
6557 0x0B, 0x00,
6558 0x1B, 0x00,
6559 0x2B, 0x00,
6560 0x00, 0xE0,
6561
6562 0x0C, 0x00,
6563 0x1C, 0x00,
6564 0x2C, 0x00,
6565 0x00, 0xE0,
6566
6567 0x0B, 0x65,
6568 0x1B, 0x65,
6569 0x2B, 0x65,
6570 0x00, 0xE0,
6571
6572 0x0C, 0x65,
6573 0x1C, 0x65,
6574 0x2C, 0x65,
6575 0x00, 0xE0,
6576
6577 0x0B, 0x1B, 0x60, 0xEC,
6578 0x34, 0xD7, 0x34, 0xAD,
6579
6580 0x2B, 0x80, 0x60, 0xEC,
6581 0x0C, 0x1C, 0x60, 0xEC,
6582
6583 0x3C, 0xD7, 0x3C, 0xAD,
6584 0x2C, 0x80, 0x60, 0xEC,
6585
6586 0x0B, 0x2B, 0xDE, 0xE8,
6587 0x1B, 0x80, 0xDE, 0xE8,
6588
6589 0x34, 0x80, 0x34, 0xBD,
6590 0x3C, 0x80, 0x3C, 0xBD,
6591
6592 0x33, 0xD7, 0x0B, 0xBD,
6593 0x3B, 0xD7, 0x1B, 0xBD,
6594
6595 0x48, 0x80, 0x48, 0xCF,
6596 0x59, 0x80, 0x59, 0xCF,
6597
6598 0x68, 0x33, 0x68, 0xCF,
6599 0x49, 0x3B, 0x49, 0xCF,
6600
6601 0xBB, 0xFF, 0x20, 0xEA,
6602 0x00, 0x80, 0x00, 0xE8,
6603
6604 0x58, 0x33, 0x58, 0xCF,
6605 0x69, 0x3B, 0x69, 0xCF,
6606
6607 0x78, 0xFF, 0x20, 0xEA,
6608 0x57, 0xC0, 0xBF, 0xEA,
6609
6610 0x00, 0x80, 0xA0, 0xE9,
6611 0x00, 0x00, 0xD8, 0xEC,
6612
6613};
6614
6615static unsigned char warp_g400_t2gzs[] = {
6616
6617 0x00, 0x8A, 0x98, 0xE9,
6618 0x00, 0x80, 0x00, 0xE8,
6619
6620 0x00, 0x80, 0xA0, 0xE9,
6621 0x00, 0x00, 0xD8, 0xEC,
6622
6623 0xFF, 0x80, 0xC0, 0xE9,
6624 0x00, 0x80, 0x00, 0xE8,
6625
6626 0x0A, 0x40, 0x50, 0xBF,
6627 0x2A, 0x40, 0x60, 0xBF,
6628
6629 0x32, 0x41, 0x51, 0xBF,
6630 0x3A, 0x41, 0x61, 0xBF,
6631
6632 0xC3, 0x6B,
6633 0xD3, 0x6B,
6634 0x00, 0x8A, 0x98, 0xE9,
6635
6636 0x73, 0x7B, 0xC8, 0xEC,
6637 0x96, 0xE2,
6638 0x41, 0x04,
6639
6640 0x7B, 0x43, 0xA0, 0xE8,
6641 0x73, 0x53, 0xA0, 0xE8,
6642
6643 0xAD, 0xEE, 0x23, 0x9F,
6644 0x00, 0xE0,
6645 0x51, 0x04,
6646
6647 0x90, 0xE2,
6648 0x61, 0x04,
6649 0x31, 0x46, 0xB1, 0xE8,
6650
6651 0x51, 0x41, 0xE0, 0xEC,
6652 0x39, 0x67, 0xB1, 0xE8,
6653
6654 0x00, 0x04,
6655 0x46, 0xE2,
6656 0x73, 0x63, 0xA0, 0xE8,
6657
6658 0x61, 0x41, 0xE0, 0xEC,
6659 0x31, 0x00,
6660 0x39, 0x00,
6661
6662 0x85, 0x80, 0x15, 0xEA,
6663 0x10, 0x04,
6664 0x20, 0x04,
6665
6666 0x61, 0x51, 0xE0, 0xEC,
6667 0x2F, 0x41, 0x60, 0xEA,
6668
6669 0x31, 0x20,
6670 0x39, 0x20,
6671 0x1F, 0x42, 0xA0, 0xE8,
6672
6673 0x2A, 0x42, 0x52, 0xBF,
6674 0x0F, 0x52, 0xA0, 0xE8,
6675
6676 0x1A, 0x42, 0x62, 0xBF,
6677 0x1E, 0x51, 0x60, 0xEA,
6678
6679 0x73, 0x7B, 0xC8, 0xEC,
6680 0x0E, 0x61, 0x60, 0xEA,
6681
6682 0x32, 0x40, 0x50, 0xBD,
6683 0x22, 0x40, 0x60, 0xBD,
6684
6685 0x12, 0x41, 0x51, 0xBD,
6686 0x3A, 0x41, 0x61, 0xBD,
6687
6688 0xBF, 0x2F, 0x0E, 0xBD,
6689 0x97, 0xE2,
6690 0x7B, 0x72,
6691
6692 0x32, 0x20,
6693 0x22, 0x20,
6694 0x12, 0x20,
6695 0x3A, 0x20,
6696
6697 0x35, 0x48, 0xB1, 0xE8,
6698 0x3D, 0x59, 0xB1, 0xE8,
6699
6700 0x46, 0x31, 0x46, 0xBF,
6701 0x56, 0x31, 0x56, 0xBF,
6702
6703 0xB3, 0xE2, 0x2D, 0x9F,
6704 0x00, 0x80, 0x00, 0xE8,
6705
6706 0x66, 0x31, 0x66, 0xBF,
6707 0x47, 0x39, 0x47, 0xBF,
6708
6709 0x57, 0x39, 0x57, 0xBF,
6710 0x67, 0x39, 0x67, 0xBF,
6711
6712 0x76, 0x80, 0x07, 0xEA,
6713 0x24, 0x41, 0x20, 0xE9,
6714
6715 0x35, 0x00,
6716 0x3D, 0x00,
6717 0x00, 0xE0,
6718 0x2D, 0x73,
6719
6720 0x33, 0x72,
6721 0x0C, 0xE3,
6722 0x8D, 0x2F, 0x1E, 0xBD,
6723
6724 0x43, 0x75, 0xF8, 0xEC,
6725 0x35, 0x20,
6726 0x3D, 0x20,
6727
6728 0x43, 0x43, 0x2D, 0xDF,
6729 0x53, 0x53, 0x2D, 0xDF,
6730
6731 0xAE, 0x1E, 0x0E, 0xBD,
6732 0x58, 0xE3,
6733 0x33, 0x66,
6734
6735 0x48, 0x35, 0x48, 0xBF,
6736 0x58, 0x35, 0x58, 0xBF,
6737
6738 0x68, 0x35, 0x68, 0xBF,
6739 0x49, 0x3D, 0x49, 0xBF,
6740
6741 0x59, 0x3D, 0x59, 0xBF,
6742 0x69, 0x3D, 0x69, 0xBF,
6743
6744 0x63, 0x63, 0x2D, 0xDF,
6745 0x4D, 0x7D, 0xF8, 0xEC,
6746
6747 0x59, 0xE3,
6748 0x00, 0xE0,
6749 0xB8, 0x38, 0x33, 0xBF,
6750
6751 0x2D, 0x73,
6752 0x30, 0x76,
6753 0x18, 0x3A, 0x41, 0xE9,
6754
6755 0x3F, 0x53, 0xA0, 0xE8,
6756 0x05, 0x80, 0x3D, 0xEA,
6757
6758 0x37, 0x43, 0xA0, 0xE8,
6759 0x3D, 0x63, 0xA0, 0xE8,
6760
6761 0x50, 0x70, 0xF8, 0xEC,
6762 0x2B, 0x50, 0x3C, 0xE9,
6763
6764 0x1F, 0x0F, 0xBC, 0xE8,
6765 0x00, 0x80, 0x00, 0xE8,
6766
6767 0x59, 0x78, 0xF8, 0xEC,
6768 0x00, 0x80, 0x00, 0xE8,
6769
6770 0x15, 0xC0, 0x20, 0xE9,
6771 0x15, 0xC0, 0x20, 0xE9,
6772
6773 0x15, 0xC0, 0x20, 0xE9,
6774 0x15, 0xC0, 0x20, 0xE9,
6775
6776 0x1E, 0x12, 0x41, 0xE9,
6777 0x1A, 0x22, 0x41, 0xE9,
6778
6779 0x46, 0x37, 0x46, 0xDF,
6780 0x56, 0x3F, 0x56, 0xDF,
6781
6782 0x2B, 0x40, 0x3D, 0xE9,
6783 0x66, 0x3D, 0x66, 0xDF,
6784
6785 0x1D, 0x32, 0x41, 0xE9,
6786 0x67, 0x3D, 0x67, 0xDF,
6787
6788 0x47, 0x37, 0x47, 0xDF,
6789 0x57, 0x3F, 0x57, 0xDF,
6790
6791 0x2A, 0x40, 0x20, 0xE9,
6792 0x59, 0x3F, 0x59, 0xDF,
6793
6794 0x16, 0x30, 0x20, 0xE9,
6795 0x69, 0x3D, 0x69, 0xDF,
6796
6797 0x48, 0x37, 0x48, 0xDF,
6798 0x58, 0x3F, 0x58, 0xDF,
6799
6800 0x68, 0x3D, 0x68, 0xDF,
6801 0x49, 0x37, 0x49, 0xDF,
6802
6803 0x32, 0x32, 0x2D, 0xDF,
6804 0x22, 0x22, 0x2D, 0xDF,
6805
6806 0x12, 0x12, 0x2D, 0xDF,
6807 0x3A, 0x3A, 0x2D, 0xDF,
6808
6809 0x0F, 0xCF, 0x74, 0xC2,
6810 0x37, 0xCF, 0x74, 0xC4,
6811
6812 0x0A, 0x44, 0x54, 0xB0,
6813 0x02, 0x44, 0x64, 0xB0,
6814
6815 0x3D, 0xCF, 0x74, 0xC0,
6816 0x34, 0x37, 0x20, 0xE9,
6817
6818 0x31, 0x53, 0x2F, 0x9F,
6819 0x38, 0x0F, 0x20, 0xE9,
6820
6821 0x39, 0xE5, 0x2C, 0x9F,
6822 0x3C, 0x3D, 0x20, 0xE9,
6823
6824 0x2A, 0x44, 0x54, 0xB2,
6825 0x1A, 0x44, 0x64, 0xB2,
6826
6827 0x31, 0x80, 0x3A, 0xEA,
6828 0x0A, 0x20,
6829 0x02, 0x20,
6830
6831 0x0F, 0xCF, 0x75, 0xC0,
6832 0x2A, 0x20,
6833 0x1A, 0x20,
6834
6835 0x30, 0x50, 0x2E, 0x9F,
6836 0x32, 0x31, 0x5F, 0xE9,
6837
6838 0x38, 0x21, 0x2C, 0x9F,
6839 0x33, 0x39, 0x5F, 0xE9,
6840
6841 0x3D, 0xCF, 0x75, 0xC2,
6842 0x37, 0xCF, 0x75, 0xC4,
6843
6844 0x31, 0x53, 0x2F, 0x9F,
6845 0xA6, 0x0F, 0x20, 0xE9,
6846
6847 0x39, 0xE5, 0x2C, 0x9F,
6848 0xA3, 0x3D, 0x20, 0xE9,
6849
6850 0x2A, 0x44, 0x54, 0xB4,
6851 0x1A, 0x44, 0x64, 0xB4,
6852
6853 0x0A, 0x45, 0x55, 0xB0,
6854 0x02, 0x45, 0x65, 0xB0,
6855
6856 0x88, 0x73, 0x5E, 0xE9,
6857 0x2A, 0x20,
6858 0x1A, 0x20,
6859
6860 0xA0, 0x37, 0x20, 0xE9,
6861 0x0A, 0x20,
6862 0x02, 0x20,
6863
6864 0x31, 0x53, 0x2F, 0x9F,
6865 0x3E, 0x30, 0x4F, 0xE9,
6866
6867 0x39, 0xE5, 0x2C, 0x9F,
6868 0x3F, 0x38, 0x4F, 0xE9,
6869
6870 0x30, 0x50, 0x2E, 0x9F,
6871 0x3A, 0x31, 0x4F, 0xE9,
6872
6873 0x2A, 0x45, 0x55, 0xB2,
6874 0x1A, 0x45, 0x65, 0xB2,
6875
6876 0x0A, 0x45, 0x55, 0xB4,
6877 0x02, 0x45, 0x65, 0xB4,
6878
6879 0x38, 0x21, 0x2C, 0x9F,
6880 0x3B, 0x39, 0x4F, 0xE9,
6881
6882 0x2A, 0x20,
6883 0x1A, 0x20,
6884 0x0A, 0x20,
6885 0x02, 0x20,
6886
6887 0x2A, 0x46, 0x56, 0xBF,
6888 0x1A, 0x46, 0x66, 0xBF,
6889
6890 0x31, 0x53, 0x2F, 0x9F,
6891 0x36, 0x31, 0x4F, 0xE9,
6892
6893 0x39, 0xE5, 0x2C, 0x9F,
6894 0x37, 0x39, 0x4F, 0xE9,
6895
6896 0x30, 0x50, 0x2E, 0x9F,
6897 0xA7, 0x30, 0x4F, 0xE9,
6898
6899 0x38, 0x21, 0x2C, 0x9F,
6900 0xA8, 0x38, 0x4F, 0xE9,
6901
6902 0x0A, 0x47, 0x57, 0xBF,
6903 0x02, 0x47, 0x67, 0xBF,
6904
6905 0x31, 0x53, 0x2F, 0x9F,
6906 0xA4, 0x31, 0x4F, 0xE9,
6907
6908 0x39, 0xE5, 0x2C, 0x9F,
6909 0xA5, 0x39, 0x4F, 0xE9,
6910
6911 0x2A, 0x43, 0x53, 0xBF,
6912 0x1A, 0x43, 0x63, 0xBF,
6913
6914 0x30, 0x50, 0x2E, 0x9F,
6915 0xA1, 0x30, 0x4F, 0xE9,
6916
6917 0x38, 0x21, 0x2C, 0x9F,
6918 0xA2, 0x38, 0x4F, 0xE9,
6919
6920 0x0A, 0x48, 0x58, 0xBF,
6921 0x02, 0x48, 0x68, 0xBF,
6922
6923 0x31, 0x53, 0x2F, 0x9F,
6924 0x80, 0x31, 0x57, 0xE9,
6925
6926 0x39, 0xE5, 0x2C, 0x9F,
6927 0x81, 0x39, 0x57, 0xE9,
6928
6929 0x2A, 0x49, 0x59, 0xBF,
6930 0x1A, 0x49, 0x69, 0xBF,
6931
6932 0x30, 0x50, 0x2E, 0x9F,
6933 0x82, 0x30, 0x57, 0xE9,
6934
6935 0x38, 0x21, 0x2C, 0x9F,
6936 0x83, 0x38, 0x57, 0xE9,
6937
6938 0x31, 0x53, 0x2F, 0x9F,
6939 0x84, 0x31, 0x5E, 0xE9,
6940
6941 0x39, 0xE5, 0x2C, 0x9F,
6942 0x85, 0x39, 0x5E, 0xE9,
6943
6944 0x86, 0x76, 0x57, 0xE9,
6945 0x8A, 0x36, 0x20, 0xE9,
6946
6947 0x87, 0x77, 0x57, 0xE9,
6948 0x8B, 0x3E, 0xBF, 0xEA,
6949
6950 0x80, 0x30, 0x57, 0xE9,
6951 0x81, 0x38, 0x57, 0xE9,
6952
6953 0x82, 0x31, 0x57, 0xE9,
6954 0x86, 0x78, 0x57, 0xE9,
6955
6956 0x83, 0x39, 0x57, 0xE9,
6957 0x87, 0x79, 0x57, 0xE9,
6958
6959 0x30, 0x1F, 0x5F, 0xE9,
6960 0x8A, 0x34, 0x20, 0xE9,
6961
6962 0x8B, 0x3C, 0x20, 0xE9,
6963 0x37, 0x50, 0x60, 0xBD,
6964
6965 0x57, 0x0D, 0x20, 0xE9,
6966 0x35, 0x51, 0x61, 0xBD,
6967
6968 0x2B, 0x50, 0x20, 0xE9,
6969 0x1D, 0x37, 0xE1, 0xEA,
6970
6971 0x1E, 0x35, 0xE1, 0xEA,
6972 0x00, 0xE0,
6973 0x0E, 0x77,
6974
6975 0x24, 0x51, 0x20, 0xE9,
6976 0x92, 0xFF, 0x20, 0xEA,
6977
6978 0x16, 0x0E, 0x20, 0xE9,
6979 0x57, 0x2E, 0xBF, 0xEA,
6980
6981 0x0B, 0x46, 0xA0, 0xE8,
6982 0x1B, 0x56, 0xA0, 0xE8,
6983
6984 0x2B, 0x66, 0xA0, 0xE8,
6985 0x0C, 0x47, 0xA0, 0xE8,
6986
6987 0x1C, 0x57, 0xA0, 0xE8,
6988 0x2C, 0x67, 0xA0, 0xE8,
6989
6990 0x0B, 0x00,
6991 0x1B, 0x00,
6992 0x2B, 0x00,
6993 0x00, 0xE0,
6994
6995 0x0C, 0x00,
6996 0x1C, 0x00,
6997 0x2C, 0x00,
6998 0x00, 0xE0,
6999
7000 0x0B, 0x65,
7001 0x1B, 0x65,
7002 0x2B, 0x65,
7003 0x00, 0xE0,
7004
7005 0x0C, 0x65,
7006 0x1C, 0x65,
7007 0x2C, 0x65,
7008 0x00, 0xE0,
7009
7010 0x0B, 0x1B, 0x60, 0xEC,
7011 0x36, 0xD7, 0x36, 0xAD,
7012
7013 0x2B, 0x80, 0x60, 0xEC,
7014 0x0C, 0x1C, 0x60, 0xEC,
7015
7016 0x3E, 0xD7, 0x3E, 0xAD,
7017 0x2C, 0x80, 0x60, 0xEC,
7018
7019 0x0B, 0x2B, 0xDE, 0xE8,
7020 0x1B, 0x80, 0xDE, 0xE8,
7021
7022 0x36, 0x80, 0x36, 0xBD,
7023 0x3E, 0x80, 0x3E, 0xBD,
7024
7025 0x33, 0xD7, 0x0B, 0xBD,
7026 0x3B, 0xD7, 0x1B, 0xBD,
7027
7028 0x46, 0x80, 0x46, 0xCF,
7029 0x57, 0x80, 0x57, 0xCF,
7030
7031 0x66, 0x33, 0x66, 0xCF,
7032 0x47, 0x3B, 0x47, 0xCF,
7033
7034 0x56, 0x33, 0x56, 0xCF,
7035 0x67, 0x3B, 0x67, 0xCF,
7036
7037 0x0B, 0x48, 0xA0, 0xE8,
7038 0x1B, 0x58, 0xA0, 0xE8,
7039
7040 0x2B, 0x68, 0xA0, 0xE8,
7041 0x0C, 0x49, 0xA0, 0xE8,
7042
7043 0x1C, 0x59, 0xA0, 0xE8,
7044 0x2C, 0x69, 0xA0, 0xE8,
7045
7046 0x0B, 0x00,
7047 0x1B, 0x00,
7048 0x2B, 0x00,
7049 0x00, 0xE0,
7050
7051 0x0C, 0x00,
7052 0x1C, 0x00,
7053 0x2C, 0x00,
7054 0x00, 0xE0,
7055
7056 0x0B, 0x65,
7057 0x1B, 0x65,
7058 0x2B, 0x65,
7059 0x00, 0xE0,
7060
7061 0x0C, 0x65,
7062 0x1C, 0x65,
7063 0x2C, 0x65,
7064 0x00, 0xE0,
7065
7066 0x0B, 0x1B, 0x60, 0xEC,
7067 0x34, 0xD7, 0x34, 0xAD,
7068
7069 0x2B, 0x80, 0x60, 0xEC,
7070 0x0C, 0x1C, 0x60, 0xEC,
7071
7072 0x3C, 0xD7, 0x3C, 0xAD,
7073 0x2C, 0x80, 0x60, 0xEC,
7074
7075 0x0B, 0x2B, 0xDE, 0xE8,
7076 0x1B, 0x80, 0xDE, 0xE8,
7077
7078 0x34, 0x80, 0x34, 0xBD,
7079 0x3C, 0x80, 0x3C, 0xBD,
7080
7081 0x33, 0xD7, 0x0B, 0xBD,
7082 0x3B, 0xD7, 0x1B, 0xBD,
7083
7084 0x48, 0x80, 0x48, 0xCF,
7085 0x59, 0x80, 0x59, 0xCF,
7086
7087 0x68, 0x33, 0x68, 0xCF,
7088 0x49, 0x3B, 0x49, 0xCF,
7089
7090 0xB2, 0xFF, 0x20, 0xEA,
7091 0x00, 0x80, 0x00, 0xE8,
7092
7093 0x58, 0x33, 0x58, 0xCF,
7094 0x69, 0x3B, 0x69, 0xCF,
7095
7096 0x70, 0xFF, 0x20, 0xEA,
7097 0x57, 0xC0, 0xBF, 0xEA,
7098
7099 0x00, 0x80, 0xA0, 0xE9,
7100 0x00, 0x00, 0xD8, 0xEC,
7101
7102};
7103
7104static unsigned char warp_g400_t2gzsa[] = {
7105
7106 0x00, 0x8A, 0x98, 0xE9,
7107 0x00, 0x80, 0x00, 0xE8,
7108
7109 0x00, 0x80, 0xA0, 0xE9,
7110 0x00, 0x00, 0xD8, 0xEC,
7111
7112 0xFF, 0x80, 0xC0, 0xE9,
7113 0x00, 0x80, 0x00, 0xE8,
7114
7115 0x0A, 0x40, 0x50, 0xBF,
7116 0x2A, 0x40, 0x60, 0xBF,
7117
7118 0x32, 0x41, 0x51, 0xBF,
7119 0x3A, 0x41, 0x61, 0xBF,
7120
7121 0xC3, 0x6B,
7122 0xD3, 0x6B,
7123 0x00, 0x8A, 0x98, 0xE9,
7124
7125 0x73, 0x7B, 0xC8, 0xEC,
7126 0x96, 0xE2,
7127 0x41, 0x04,
7128
7129 0x7B, 0x43, 0xA0, 0xE8,
7130 0x73, 0x53, 0xA0, 0xE8,
7131
7132 0xAD, 0xEE, 0x23, 0x9F,
7133 0x00, 0xE0,
7134 0x51, 0x04,
7135
7136 0x90, 0xE2,
7137 0x61, 0x04,
7138 0x31, 0x46, 0xB1, 0xE8,
7139
7140 0x51, 0x41, 0xE0, 0xEC,
7141 0x39, 0x67, 0xB1, 0xE8,
7142
7143 0x00, 0x04,
7144 0x46, 0xE2,
7145 0x73, 0x63, 0xA0, 0xE8,
7146
7147 0x61, 0x41, 0xE0, 0xEC,
7148 0x31, 0x00,
7149 0x39, 0x00,
7150
7151 0x8A, 0x80, 0x15, 0xEA,
7152 0x10, 0x04,
7153 0x20, 0x04,
7154
7155 0x61, 0x51, 0xE0, 0xEC,
7156 0x2F, 0x41, 0x60, 0xEA,
7157
7158 0x31, 0x20,
7159 0x39, 0x20,
7160 0x1F, 0x42, 0xA0, 0xE8,
7161
7162 0x2A, 0x42, 0x52, 0xBF,
7163 0x0F, 0x52, 0xA0, 0xE8,
7164
7165 0x1A, 0x42, 0x62, 0xBF,
7166 0x1E, 0x51, 0x60, 0xEA,
7167
7168 0x73, 0x7B, 0xC8, 0xEC,
7169 0x0E, 0x61, 0x60, 0xEA,
7170
7171 0x32, 0x40, 0x50, 0xBD,
7172 0x22, 0x40, 0x60, 0xBD,
7173
7174 0x12, 0x41, 0x51, 0xBD,
7175 0x3A, 0x41, 0x61, 0xBD,
7176
7177 0xBF, 0x2F, 0x0E, 0xBD,
7178 0x97, 0xE2,
7179 0x7B, 0x72,
7180
7181 0x32, 0x20,
7182 0x22, 0x20,
7183 0x12, 0x20,
7184 0x3A, 0x20,
7185
7186 0x35, 0x48, 0xB1, 0xE8,
7187 0x3D, 0x59, 0xB1, 0xE8,
7188
7189 0x46, 0x31, 0x46, 0xBF,
7190 0x56, 0x31, 0x56, 0xBF,
7191
7192 0xB3, 0xE2, 0x2D, 0x9F,
7193 0x00, 0x80, 0x00, 0xE8,
7194
7195 0x66, 0x31, 0x66, 0xBF,
7196 0x47, 0x39, 0x47, 0xBF,
7197
7198 0x57, 0x39, 0x57, 0xBF,
7199 0x67, 0x39, 0x67, 0xBF,
7200
7201 0x7B, 0x80, 0x07, 0xEA,
7202 0x24, 0x41, 0x20, 0xE9,
7203
7204 0x35, 0x00,
7205 0x3D, 0x00,
7206 0x00, 0xE0,
7207 0x2D, 0x73,
7208
7209 0x33, 0x72,
7210 0x0C, 0xE3,
7211 0x8D, 0x2F, 0x1E, 0xBD,
7212
7213 0x43, 0x75, 0xF8, 0xEC,
7214 0x35, 0x20,
7215 0x3D, 0x20,
7216
7217 0x43, 0x43, 0x2D, 0xDF,
7218 0x53, 0x53, 0x2D, 0xDF,
7219
7220 0xAE, 0x1E, 0x0E, 0xBD,
7221 0x58, 0xE3,
7222 0x33, 0x66,
7223
7224 0x48, 0x35, 0x48, 0xBF,
7225 0x58, 0x35, 0x58, 0xBF,
7226
7227 0x68, 0x35, 0x68, 0xBF,
7228 0x49, 0x3D, 0x49, 0xBF,
7229
7230 0x59, 0x3D, 0x59, 0xBF,
7231 0x69, 0x3D, 0x69, 0xBF,
7232
7233 0x63, 0x63, 0x2D, 0xDF,
7234 0x4D, 0x7D, 0xF8, 0xEC,
7235
7236 0x59, 0xE3,
7237 0x00, 0xE0,
7238 0xB8, 0x38, 0x33, 0xBF,
7239
7240 0x2D, 0x73,
7241 0x30, 0x76,
7242 0x18, 0x3A, 0x41, 0xE9,
7243
7244 0x3F, 0x53, 0xA0, 0xE8,
7245 0x05, 0x80, 0x3D, 0xEA,
7246
7247 0x37, 0x43, 0xA0, 0xE8,
7248 0x3D, 0x63, 0xA0, 0xE8,
7249
7250 0x50, 0x70, 0xF8, 0xEC,
7251 0x2B, 0x50, 0x3C, 0xE9,
7252
7253 0x1F, 0x0F, 0xBC, 0xE8,
7254 0x00, 0x80, 0x00, 0xE8,
7255
7256 0x59, 0x78, 0xF8, 0xEC,
7257 0x00, 0x80, 0x00, 0xE8,
7258
7259 0x15, 0xC0, 0x20, 0xE9,
7260 0x15, 0xC0, 0x20, 0xE9,
7261
7262 0x15, 0xC0, 0x20, 0xE9,
7263 0x15, 0xC0, 0x20, 0xE9,
7264
7265 0x1E, 0x12, 0x41, 0xE9,
7266 0x1A, 0x22, 0x41, 0xE9,
7267
7268 0x46, 0x37, 0x46, 0xDF,
7269 0x56, 0x3F, 0x56, 0xDF,
7270
7271 0x2B, 0x40, 0x3D, 0xE9,
7272 0x66, 0x3D, 0x66, 0xDF,
7273
7274 0x1D, 0x32, 0x41, 0xE9,
7275 0x67, 0x3D, 0x67, 0xDF,
7276
7277 0x47, 0x37, 0x47, 0xDF,
7278 0x57, 0x3F, 0x57, 0xDF,
7279
7280 0x2A, 0x40, 0x20, 0xE9,
7281 0x59, 0x3F, 0x59, 0xDF,
7282
7283 0x16, 0x30, 0x20, 0xE9,
7284 0x69, 0x3D, 0x69, 0xDF,
7285
7286 0x48, 0x37, 0x48, 0xDF,
7287 0x58, 0x3F, 0x58, 0xDF,
7288
7289 0x68, 0x3D, 0x68, 0xDF,
7290 0x49, 0x37, 0x49, 0xDF,
7291
7292 0x32, 0x32, 0x2D, 0xDF,
7293 0x22, 0x22, 0x2D, 0xDF,
7294
7295 0x12, 0x12, 0x2D, 0xDF,
7296 0x3A, 0x3A, 0x2D, 0xDF,
7297
7298 0x0F, 0xCF, 0x74, 0xC2,
7299 0x37, 0xCF, 0x74, 0xC4,
7300
7301 0x0A, 0x44, 0x54, 0xB0,
7302 0x02, 0x44, 0x64, 0xB0,
7303
7304 0x3D, 0xCF, 0x74, 0xC0,
7305 0x34, 0x37, 0x20, 0xE9,
7306
7307 0x31, 0x53, 0x2F, 0x9F,
7308 0x38, 0x0F, 0x20, 0xE9,
7309
7310 0x39, 0xE5, 0x2C, 0x9F,
7311 0x3C, 0x3D, 0x20, 0xE9,
7312
7313 0x2A, 0x44, 0x54, 0xB2,
7314 0x1A, 0x44, 0x64, 0xB2,
7315
7316 0x36, 0x80, 0x3A, 0xEA,
7317 0x0A, 0x20,
7318 0x02, 0x20,
7319
7320 0x0F, 0xCF, 0x75, 0xC0,
7321 0x2A, 0x20,
7322 0x1A, 0x20,
7323
7324 0x30, 0x50, 0x2E, 0x9F,
7325 0x32, 0x31, 0x5F, 0xE9,
7326
7327 0x38, 0x21, 0x2C, 0x9F,
7328 0x33, 0x39, 0x5F, 0xE9,
7329
7330 0x3D, 0xCF, 0x75, 0xC2,
7331 0x37, 0xCF, 0x75, 0xC4,
7332
7333 0x31, 0x53, 0x2F, 0x9F,
7334 0xA6, 0x0F, 0x20, 0xE9,
7335
7336 0x39, 0xE5, 0x2C, 0x9F,
7337 0xA3, 0x3D, 0x20, 0xE9,
7338
7339 0x2A, 0x44, 0x54, 0xB4,
7340 0x1A, 0x44, 0x64, 0xB4,
7341
7342 0x0A, 0x45, 0x55, 0xB0,
7343 0x02, 0x45, 0x65, 0xB0,
7344
7345 0x88, 0x73, 0x5E, 0xE9,
7346 0x2A, 0x20,
7347 0x1A, 0x20,
7348
7349 0xA0, 0x37, 0x20, 0xE9,
7350 0x0A, 0x20,
7351 0x02, 0x20,
7352
7353 0x31, 0x53, 0x2F, 0x9F,
7354 0x3E, 0x30, 0x4F, 0xE9,
7355
7356 0x39, 0xE5, 0x2C, 0x9F,
7357 0x3F, 0x38, 0x4F, 0xE9,
7358
7359 0x30, 0x50, 0x2E, 0x9F,
7360 0x3A, 0x31, 0x4F, 0xE9,
7361
7362 0x38, 0x21, 0x2C, 0x9F,
7363 0x3B, 0x39, 0x4F, 0xE9,
7364
7365 0x2A, 0x45, 0x55, 0xB2,
7366 0x1A, 0x45, 0x65, 0xB2,
7367
7368 0x0A, 0x45, 0x55, 0xB4,
7369 0x02, 0x45, 0x65, 0xB4,
7370
7371 0x0F, 0xCF, 0x74, 0xC6,
7372 0x2A, 0x20,
7373 0x1A, 0x20,
7374
7375 0xA7, 0x30, 0x4F, 0xE9,
7376 0x0A, 0x20,
7377 0x02, 0x20,
7378
7379 0x31, 0x53, 0x2F, 0x9F,
7380 0x9C, 0x0F, 0x20, 0xE9,
7381
7382 0x39, 0xE5, 0x2C, 0x9F,
7383 0xA8, 0x38, 0x4F, 0xE9,
7384
7385 0x2A, 0x44, 0x54, 0xB6,
7386 0x1A, 0x44, 0x64, 0xB6,
7387
7388 0x30, 0x50, 0x2E, 0x9F,
7389 0x36, 0x31, 0x4F, 0xE9,
7390
7391 0x38, 0x21, 0x2C, 0x9F,
7392 0x37, 0x39, 0x4F, 0xE9,
7393
7394 0x00, 0x80, 0x00, 0xE8,
7395 0x2A, 0x20,
7396 0x1A, 0x20,
7397
7398 0x2A, 0x46, 0x56, 0xBF,
7399 0x1A, 0x46, 0x66, 0xBF,
7400
7401 0x31, 0x53, 0x2F, 0x9F,
7402 0xA4, 0x31, 0x4F, 0xE9,
7403
7404 0x39, 0xE5, 0x2C, 0x9F,
7405 0xA5, 0x39, 0x4F, 0xE9,
7406
7407 0x0A, 0x47, 0x57, 0xBF,
7408 0x02, 0x47, 0x67, 0xBF,
7409
7410 0x31, 0x53, 0x2F, 0x9F,
7411 0xA1, 0x30, 0x4F, 0xE9,
7412
7413 0x39, 0xE5, 0x2C, 0x9F,
7414 0xA2, 0x38, 0x4F, 0xE9,
7415
7416 0x2A, 0x43, 0x53, 0xBF,
7417 0x1A, 0x43, 0x63, 0xBF,
7418
7419 0x30, 0x50, 0x2E, 0x9F,
7420 0x9D, 0x31, 0x4F, 0xE9,
7421
7422 0x38, 0x21, 0x2C, 0x9F,
7423 0x9E, 0x39, 0x4F, 0xE9,
7424
7425 0x0A, 0x48, 0x58, 0xBF,
7426 0x02, 0x48, 0x68, 0xBF,
7427
7428 0x31, 0x53, 0x2F, 0x9F,
7429 0x80, 0x31, 0x57, 0xE9,
7430
7431 0x39, 0xE5, 0x2C, 0x9F,
7432 0x81, 0x39, 0x57, 0xE9,
7433
7434 0x2A, 0x49, 0x59, 0xBF,
7435 0x1A, 0x49, 0x69, 0xBF,
7436
7437 0x30, 0x50, 0x2E, 0x9F,
7438 0x82, 0x30, 0x57, 0xE9,
7439
7440 0x38, 0x21, 0x2C, 0x9F,
7441 0x83, 0x38, 0x57, 0xE9,
7442
7443 0x31, 0x53, 0x2F, 0x9F,
7444 0x84, 0x31, 0x5E, 0xE9,
7445
7446 0x39, 0xE5, 0x2C, 0x9F,
7447 0x85, 0x39, 0x5E, 0xE9,
7448
7449 0x86, 0x76, 0x57, 0xE9,
7450 0x8A, 0x36, 0x20, 0xE9,
7451
7452 0x87, 0x77, 0x57, 0xE9,
7453 0x8B, 0x3E, 0xBF, 0xEA,
7454
7455 0x80, 0x30, 0x57, 0xE9,
7456 0x81, 0x38, 0x57, 0xE9,
7457
7458 0x82, 0x31, 0x57, 0xE9,
7459 0x86, 0x78, 0x57, 0xE9,
7460
7461 0x83, 0x39, 0x57, 0xE9,
7462 0x87, 0x79, 0x57, 0xE9,
7463
7464 0x30, 0x1F, 0x5F, 0xE9,
7465 0x8A, 0x34, 0x20, 0xE9,
7466
7467 0x8B, 0x3C, 0x20, 0xE9,
7468 0x37, 0x50, 0x60, 0xBD,
7469
7470 0x57, 0x0D, 0x20, 0xE9,
7471 0x35, 0x51, 0x61, 0xBD,
7472
7473 0x2B, 0x50, 0x20, 0xE9,
7474 0x1D, 0x37, 0xE1, 0xEA,
7475
7476 0x1E, 0x35, 0xE1, 0xEA,
7477 0x00, 0xE0,
7478 0x0E, 0x77,
7479
7480 0x24, 0x51, 0x20, 0xE9,
7481 0x8D, 0xFF, 0x20, 0xEA,
7482
7483 0x16, 0x0E, 0x20, 0xE9,
7484 0x57, 0x2E, 0xBF, 0xEA,
7485
7486 0x0B, 0x46, 0xA0, 0xE8,
7487 0x1B, 0x56, 0xA0, 0xE8,
7488
7489 0x2B, 0x66, 0xA0, 0xE8,
7490 0x0C, 0x47, 0xA0, 0xE8,
7491
7492 0x1C, 0x57, 0xA0, 0xE8,
7493 0x2C, 0x67, 0xA0, 0xE8,
7494
7495 0x0B, 0x00,
7496 0x1B, 0x00,
7497 0x2B, 0x00,
7498 0x00, 0xE0,
7499
7500 0x0C, 0x00,
7501 0x1C, 0x00,
7502 0x2C, 0x00,
7503 0x00, 0xE0,
7504
7505 0x0B, 0x65,
7506 0x1B, 0x65,
7507 0x2B, 0x65,
7508 0x00, 0xE0,
7509
7510 0x0C, 0x65,
7511 0x1C, 0x65,
7512 0x2C, 0x65,
7513 0x00, 0xE0,
7514
7515 0x0B, 0x1B, 0x60, 0xEC,
7516 0x36, 0xD7, 0x36, 0xAD,
7517
7518 0x2B, 0x80, 0x60, 0xEC,
7519 0x0C, 0x1C, 0x60, 0xEC,
7520
7521 0x3E, 0xD7, 0x3E, 0xAD,
7522 0x2C, 0x80, 0x60, 0xEC,
7523
7524 0x0B, 0x2B, 0xDE, 0xE8,
7525 0x1B, 0x80, 0xDE, 0xE8,
7526
7527 0x36, 0x80, 0x36, 0xBD,
7528 0x3E, 0x80, 0x3E, 0xBD,
7529
7530 0x33, 0xD7, 0x0B, 0xBD,
7531 0x3B, 0xD7, 0x1B, 0xBD,
7532
7533 0x46, 0x80, 0x46, 0xCF,
7534 0x57, 0x80, 0x57, 0xCF,
7535
7536 0x66, 0x33, 0x66, 0xCF,
7537 0x47, 0x3B, 0x47, 0xCF,
7538
7539 0x56, 0x33, 0x56, 0xCF,
7540 0x67, 0x3B, 0x67, 0xCF,
7541
7542 0x0B, 0x48, 0xA0, 0xE8,
7543 0x1B, 0x58, 0xA0, 0xE8,
7544
7545 0x2B, 0x68, 0xA0, 0xE8,
7546 0x0C, 0x49, 0xA0, 0xE8,
7547
7548 0x1C, 0x59, 0xA0, 0xE8,
7549 0x2C, 0x69, 0xA0, 0xE8,
7550
7551 0x0B, 0x00,
7552 0x1B, 0x00,
7553 0x2B, 0x00,
7554 0x00, 0xE0,
7555
7556 0x0C, 0x00,
7557 0x1C, 0x00,
7558 0x2C, 0x00,
7559 0x00, 0xE0,
7560
7561 0x0B, 0x65,
7562 0x1B, 0x65,
7563 0x2B, 0x65,
7564 0x00, 0xE0,
7565
7566 0x0C, 0x65,
7567 0x1C, 0x65,
7568 0x2C, 0x65,
7569 0x00, 0xE0,
7570
7571 0x0B, 0x1B, 0x60, 0xEC,
7572 0x34, 0xD7, 0x34, 0xAD,
7573
7574 0x2B, 0x80, 0x60, 0xEC,
7575 0x0C, 0x1C, 0x60, 0xEC,
7576
7577 0x3C, 0xD7, 0x3C, 0xAD,
7578 0x2C, 0x80, 0x60, 0xEC,
7579
7580 0x0B, 0x2B, 0xDE, 0xE8,
7581 0x1B, 0x80, 0xDE, 0xE8,
7582
7583 0x34, 0x80, 0x34, 0xBD,
7584 0x3C, 0x80, 0x3C, 0xBD,
7585
7586 0x33, 0xD7, 0x0B, 0xBD,
7587 0x3B, 0xD7, 0x1B, 0xBD,
7588
7589 0x48, 0x80, 0x48, 0xCF,
7590 0x59, 0x80, 0x59, 0xCF,
7591
7592 0x68, 0x33, 0x68, 0xCF,
7593 0x49, 0x3B, 0x49, 0xCF,
7594
7595 0xAD, 0xFF, 0x20, 0xEA,
7596 0x00, 0x80, 0x00, 0xE8,
7597
7598 0x58, 0x33, 0x58, 0xCF,
7599 0x69, 0x3B, 0x69, 0xCF,
7600
7601 0x6B, 0xFF, 0x20, 0xEA,
7602 0x57, 0xC0, 0xBF, 0xEA,
7603
7604 0x00, 0x80, 0xA0, 0xE9,
7605 0x00, 0x00, 0xD8, 0xEC,
7606
7607};
7608
7609static unsigned char warp_g400_t2gzsaf[] = {
7610
7611 0x00, 0x8A, 0x98, 0xE9,
7612 0x00, 0x80, 0x00, 0xE8,
7613
7614 0x00, 0x80, 0xA0, 0xE9,
7615 0x00, 0x00, 0xD8, 0xEC,
7616
7617 0xFF, 0x80, 0xC0, 0xE9,
7618 0x00, 0x80, 0x00, 0xE8,
7619
7620 0x0A, 0x40, 0x50, 0xBF,
7621 0x2A, 0x40, 0x60, 0xBF,
7622
7623 0x32, 0x41, 0x51, 0xBF,
7624 0x3A, 0x41, 0x61, 0xBF,
7625
7626 0xC3, 0x6B,
7627 0xD3, 0x6B,
7628 0x00, 0x8A, 0x98, 0xE9,
7629
7630 0x73, 0x7B, 0xC8, 0xEC,
7631 0x96, 0xE2,
7632 0x41, 0x04,
7633
7634 0x7B, 0x43, 0xA0, 0xE8,
7635 0x73, 0x53, 0xA0, 0xE8,
7636
7637 0xAD, 0xEE, 0x23, 0x9F,
7638 0x00, 0xE0,
7639 0x51, 0x04,
7640
7641 0x90, 0xE2,
7642 0x61, 0x04,
7643 0x31, 0x46, 0xB1, 0xE8,
7644
7645 0x51, 0x41, 0xE0, 0xEC,
7646 0x39, 0x67, 0xB1, 0xE8,
7647
7648 0x00, 0x04,
7649 0x46, 0xE2,
7650 0x73, 0x63, 0xA0, 0xE8,
7651
7652 0x61, 0x41, 0xE0, 0xEC,
7653 0x31, 0x00,
7654 0x39, 0x00,
7655
7656 0x8E, 0x80, 0x15, 0xEA,
7657 0x10, 0x04,
7658 0x20, 0x04,
7659
7660 0x61, 0x51, 0xE0, 0xEC,
7661 0x2F, 0x41, 0x60, 0xEA,
7662
7663 0x31, 0x20,
7664 0x39, 0x20,
7665 0x1F, 0x42, 0xA0, 0xE8,
7666
7667 0x2A, 0x42, 0x52, 0xBF,
7668 0x0F, 0x52, 0xA0, 0xE8,
7669
7670 0x1A, 0x42, 0x62, 0xBF,
7671 0x1E, 0x51, 0x60, 0xEA,
7672
7673 0x73, 0x7B, 0xC8, 0xEC,
7674 0x0E, 0x61, 0x60, 0xEA,
7675
7676 0x32, 0x40, 0x50, 0xBD,
7677 0x22, 0x40, 0x60, 0xBD,
7678
7679 0x12, 0x41, 0x51, 0xBD,
7680 0x3A, 0x41, 0x61, 0xBD,
7681
7682 0xBF, 0x2F, 0x0E, 0xBD,
7683 0x97, 0xE2,
7684 0x7B, 0x72,
7685
7686 0x32, 0x20,
7687 0x22, 0x20,
7688 0x12, 0x20,
7689 0x3A, 0x20,
7690
7691 0x35, 0x48, 0xB1, 0xE8,
7692 0x3D, 0x59, 0xB1, 0xE8,
7693
7694 0x46, 0x31, 0x46, 0xBF,
7695 0x56, 0x31, 0x56, 0xBF,
7696
7697 0xB3, 0xE2, 0x2D, 0x9F,
7698 0x00, 0x80, 0x00, 0xE8,
7699
7700 0x66, 0x31, 0x66, 0xBF,
7701 0x47, 0x39, 0x47, 0xBF,
7702
7703 0x57, 0x39, 0x57, 0xBF,
7704 0x67, 0x39, 0x67, 0xBF,
7705
7706 0x7F, 0x80, 0x07, 0xEA,
7707 0x24, 0x41, 0x20, 0xE9,
7708
7709 0x35, 0x00,
7710 0x3D, 0x00,
7711 0x00, 0xE0,
7712 0x2D, 0x73,
7713
7714 0x33, 0x72,
7715 0x0C, 0xE3,
7716 0x8D, 0x2F, 0x1E, 0xBD,
7717
7718 0x43, 0x75, 0xF8, 0xEC,
7719 0x35, 0x20,
7720 0x3D, 0x20,
7721
7722 0x43, 0x43, 0x2D, 0xDF,
7723 0x53, 0x53, 0x2D, 0xDF,
7724
7725 0xAE, 0x1E, 0x0E, 0xBD,
7726 0x58, 0xE3,
7727 0x33, 0x66,
7728
7729 0x48, 0x35, 0x48, 0xBF,
7730 0x58, 0x35, 0x58, 0xBF,
7731
7732 0x68, 0x35, 0x68, 0xBF,
7733 0x49, 0x3D, 0x49, 0xBF,
7734
7735 0x59, 0x3D, 0x59, 0xBF,
7736 0x69, 0x3D, 0x69, 0xBF,
7737
7738 0x63, 0x63, 0x2D, 0xDF,
7739 0x4D, 0x7D, 0xF8, 0xEC,
7740
7741 0x59, 0xE3,
7742 0x00, 0xE0,
7743 0xB8, 0x38, 0x33, 0xBF,
7744
7745 0x2D, 0x73,
7746 0x30, 0x76,
7747 0x18, 0x3A, 0x41, 0xE9,
7748
7749 0x3F, 0x53, 0xA0, 0xE8,
7750 0x05, 0x80, 0x3D, 0xEA,
7751
7752 0x37, 0x43, 0xA0, 0xE8,
7753 0x3D, 0x63, 0xA0, 0xE8,
7754
7755 0x50, 0x70, 0xF8, 0xEC,
7756 0x2B, 0x50, 0x3C, 0xE9,
7757
7758 0x1F, 0x0F, 0xBC, 0xE8,
7759 0x00, 0x80, 0x00, 0xE8,
7760
7761 0x59, 0x78, 0xF8, 0xEC,
7762 0x00, 0x80, 0x00, 0xE8,
7763
7764 0x15, 0xC0, 0x20, 0xE9,
7765 0x15, 0xC0, 0x20, 0xE9,
7766
7767 0x15, 0xC0, 0x20, 0xE9,
7768 0x15, 0xC0, 0x20, 0xE9,
7769
7770 0x1E, 0x12, 0x41, 0xE9,
7771 0x1A, 0x22, 0x41, 0xE9,
7772
7773 0x46, 0x37, 0x46, 0xDF,
7774 0x56, 0x3F, 0x56, 0xDF,
7775
7776 0x2B, 0x40, 0x3D, 0xE9,
7777 0x66, 0x3D, 0x66, 0xDF,
7778
7779 0x1D, 0x32, 0x41, 0xE9,
7780 0x67, 0x3D, 0x67, 0xDF,
7781
7782 0x47, 0x37, 0x47, 0xDF,
7783 0x57, 0x3F, 0x57, 0xDF,
7784
7785 0x2A, 0x40, 0x20, 0xE9,
7786 0x59, 0x3F, 0x59, 0xDF,
7787
7788 0x16, 0x30, 0x20, 0xE9,
7789 0x69, 0x3D, 0x69, 0xDF,
7790
7791 0x48, 0x37, 0x48, 0xDF,
7792 0x58, 0x3F, 0x58, 0xDF,
7793
7794 0x68, 0x3D, 0x68, 0xDF,
7795 0x49, 0x37, 0x49, 0xDF,
7796
7797 0x32, 0x32, 0x2D, 0xDF,
7798 0x22, 0x22, 0x2D, 0xDF,
7799
7800 0x12, 0x12, 0x2D, 0xDF,
7801 0x3A, 0x3A, 0x2D, 0xDF,
7802
7803 0x0F, 0xCF, 0x74, 0xC2,
7804 0x37, 0xCF, 0x74, 0xC4,
7805
7806 0x0A, 0x44, 0x54, 0xB0,
7807 0x02, 0x44, 0x64, 0xB0,
7808
7809 0x3D, 0xCF, 0x74, 0xC0,
7810 0x34, 0x37, 0x20, 0xE9,
7811
7812 0x31, 0x53, 0x2F, 0x9F,
7813 0x38, 0x0F, 0x20, 0xE9,
7814
7815 0x39, 0xE5, 0x2C, 0x9F,
7816 0x3C, 0x3D, 0x20, 0xE9,
7817
7818 0x2A, 0x44, 0x54, 0xB2,
7819 0x1A, 0x44, 0x64, 0xB2,
7820
7821 0x3A, 0x80, 0x3A, 0xEA,
7822 0x0A, 0x20,
7823 0x02, 0x20,
7824
7825 0x0F, 0xCF, 0x75, 0xC0,
7826 0x2A, 0x20,
7827 0x1A, 0x20,
7828
7829 0x30, 0x50, 0x2E, 0x9F,
7830 0x32, 0x31, 0x5F, 0xE9,
7831
7832 0x38, 0x21, 0x2C, 0x9F,
7833 0x33, 0x39, 0x5F, 0xE9,
7834
7835 0x3D, 0xCF, 0x75, 0xC2,
7836 0x37, 0xCF, 0x75, 0xC4,
7837
7838 0x31, 0x53, 0x2F, 0x9F,
7839 0xA6, 0x0F, 0x20, 0xE9,
7840
7841 0x39, 0xE5, 0x2C, 0x9F,
7842 0xA3, 0x3D, 0x20, 0xE9,
7843
7844 0x2A, 0x44, 0x54, 0xB4,
7845 0x1A, 0x44, 0x64, 0xB4,
7846
7847 0x0A, 0x45, 0x55, 0xB0,
7848 0x02, 0x45, 0x65, 0xB0,
7849
7850 0x88, 0x73, 0x5E, 0xE9,
7851 0x2A, 0x20,
7852 0x1A, 0x20,
7853
7854 0xA0, 0x37, 0x20, 0xE9,
7855 0x0A, 0x20,
7856 0x02, 0x20,
7857
7858 0x31, 0x53, 0x2F, 0x9F,
7859 0x3E, 0x30, 0x4F, 0xE9,
7860
7861 0x39, 0xE5, 0x2C, 0x9F,
7862 0x3F, 0x38, 0x4F, 0xE9,
7863
7864 0x30, 0x50, 0x2E, 0x9F,
7865 0x3A, 0x31, 0x4F, 0xE9,
7866
7867 0x38, 0x21, 0x2C, 0x9F,
7868 0x3B, 0x39, 0x4F, 0xE9,
7869
7870 0x2A, 0x45, 0x55, 0xB2,
7871 0x1A, 0x45, 0x65, 0xB2,
7872
7873 0x0A, 0x45, 0x55, 0xB4,
7874 0x02, 0x45, 0x65, 0xB4,
7875
7876 0x0F, 0xCF, 0x74, 0xC6,
7877 0x2A, 0x20,
7878 0x1A, 0x20,
7879
7880 0xA7, 0x30, 0x4F, 0xE9,
7881 0x0A, 0x20,
7882 0x02, 0x20,
7883
7884 0x31, 0x53, 0x2F, 0x9F,
7885 0x9C, 0x0F, 0x20, 0xE9,
7886
7887 0x39, 0xE5, 0x2C, 0x9F,
7888 0xA8, 0x38, 0x4F, 0xE9,
7889
7890 0x2A, 0x44, 0x54, 0xB6,
7891 0x1A, 0x44, 0x64, 0xB6,
7892
7893 0x30, 0x50, 0x2E, 0x9F,
7894 0x36, 0x31, 0x4F, 0xE9,
7895
7896 0x38, 0x21, 0x2C, 0x9F,
7897 0x37, 0x39, 0x4F, 0xE9,
7898
7899 0x0A, 0x45, 0x55, 0xB6,
7900 0x02, 0x45, 0x65, 0xB6,
7901
7902 0x3D, 0xCF, 0x75, 0xC6,
7903 0x2A, 0x20,
7904 0x1A, 0x20,
7905
7906 0x2A, 0x46, 0x56, 0xBF,
7907 0x1A, 0x46, 0x66, 0xBF,
7908
7909 0x31, 0x53, 0x2F, 0x9F,
7910 0xA4, 0x31, 0x4F, 0xE9,
7911
7912 0x39, 0xE5, 0x2C, 0x9F,
7913 0xA5, 0x39, 0x4F, 0xE9,
7914
7915 0x31, 0x3D, 0x20, 0xE9,
7916 0x0A, 0x20,
7917 0x02, 0x20,
7918
7919 0x0A, 0x47, 0x57, 0xBF,
7920 0x02, 0x47, 0x67, 0xBF,
7921
7922 0x30, 0x50, 0x2E, 0x9F,
7923 0xA1, 0x30, 0x4F, 0xE9,
7924
7925 0x38, 0x21, 0x2C, 0x9F,
7926 0xA2, 0x38, 0x4F, 0xE9,
7927
7928 0x31, 0x53, 0x2F, 0x9F,
7929 0x9D, 0x31, 0x4F, 0xE9,
7930
7931 0x39, 0xE5, 0x2C, 0x9F,
7932 0x9E, 0x39, 0x4F, 0xE9,
7933
7934 0x2A, 0x43, 0x53, 0xBF,
7935 0x1A, 0x43, 0x63, 0xBF,
7936
7937 0x30, 0x50, 0x2E, 0x9F,
7938 0x35, 0x30, 0x4F, 0xE9,
7939
7940 0x38, 0x21, 0x2C, 0x9F,
7941 0x39, 0x38, 0x4F, 0xE9,
7942
7943 0x0A, 0x48, 0x58, 0xBF,
7944 0x02, 0x48, 0x68, 0xBF,
7945
7946 0x31, 0x53, 0x2F, 0x9F,
7947 0x80, 0x31, 0x57, 0xE9,
7948
7949 0x39, 0xE5, 0x2C, 0x9F,
7950 0x81, 0x39, 0x57, 0xE9,
7951
7952 0x2A, 0x49, 0x59, 0xBF,
7953 0x1A, 0x49, 0x69, 0xBF,
7954
7955 0x30, 0x50, 0x2E, 0x9F,
7956 0x82, 0x30, 0x57, 0xE9,
7957
7958 0x38, 0x21, 0x2C, 0x9F,
7959 0x83, 0x38, 0x57, 0xE9,
7960
7961 0x31, 0x53, 0x2F, 0x9F,
7962 0x84, 0x31, 0x5E, 0xE9,
7963
7964 0x39, 0xE5, 0x2C, 0x9F,
7965 0x85, 0x39, 0x5E, 0xE9,
7966
7967 0x86, 0x76, 0x57, 0xE9,
7968 0x8A, 0x36, 0x20, 0xE9,
7969
7970 0x87, 0x77, 0x57, 0xE9,
7971 0x8B, 0x3E, 0xBF, 0xEA,
7972
7973 0x80, 0x30, 0x57, 0xE9,
7974 0x81, 0x38, 0x57, 0xE9,
7975
7976 0x82, 0x31, 0x57, 0xE9,
7977 0x86, 0x78, 0x57, 0xE9,
7978
7979 0x83, 0x39, 0x57, 0xE9,
7980 0x87, 0x79, 0x57, 0xE9,
7981
7982 0x30, 0x1F, 0x5F, 0xE9,
7983 0x8A, 0x34, 0x20, 0xE9,
7984
7985 0x8B, 0x3C, 0x20, 0xE9,
7986 0x37, 0x50, 0x60, 0xBD,
7987
7988 0x57, 0x0D, 0x20, 0xE9,
7989 0x35, 0x51, 0x61, 0xBD,
7990
7991 0x2B, 0x50, 0x20, 0xE9,
7992 0x1D, 0x37, 0xE1, 0xEA,
7993
7994 0x1E, 0x35, 0xE1, 0xEA,
7995 0x00, 0xE0,
7996 0x0E, 0x77,
7997
7998 0x24, 0x51, 0x20, 0xE9,
7999 0x89, 0xFF, 0x20, 0xEA,
8000
8001 0x16, 0x0E, 0x20, 0xE9,
8002 0x57, 0x2E, 0xBF, 0xEA,
8003
8004 0x0B, 0x46, 0xA0, 0xE8,
8005 0x1B, 0x56, 0xA0, 0xE8,
8006
8007 0x2B, 0x66, 0xA0, 0xE8,
8008 0x0C, 0x47, 0xA0, 0xE8,
8009
8010 0x1C, 0x57, 0xA0, 0xE8,
8011 0x2C, 0x67, 0xA0, 0xE8,
8012
8013 0x0B, 0x00,
8014 0x1B, 0x00,
8015 0x2B, 0x00,
8016 0x00, 0xE0,
8017
8018 0x0C, 0x00,
8019 0x1C, 0x00,
8020 0x2C, 0x00,
8021 0x00, 0xE0,
8022
8023 0x0B, 0x65,
8024 0x1B, 0x65,
8025 0x2B, 0x65,
8026 0x00, 0xE0,
8027
8028 0x0C, 0x65,
8029 0x1C, 0x65,
8030 0x2C, 0x65,
8031 0x00, 0xE0,
8032
8033 0x0B, 0x1B, 0x60, 0xEC,
8034 0x36, 0xD7, 0x36, 0xAD,
8035
8036 0x2B, 0x80, 0x60, 0xEC,
8037 0x0C, 0x1C, 0x60, 0xEC,
8038
8039 0x3E, 0xD7, 0x3E, 0xAD,
8040 0x2C, 0x80, 0x60, 0xEC,
8041
8042 0x0B, 0x2B, 0xDE, 0xE8,
8043 0x1B, 0x80, 0xDE, 0xE8,
8044
8045 0x36, 0x80, 0x36, 0xBD,
8046 0x3E, 0x80, 0x3E, 0xBD,
8047
8048 0x33, 0xD7, 0x0B, 0xBD,
8049 0x3B, 0xD7, 0x1B, 0xBD,
8050
8051 0x46, 0x80, 0x46, 0xCF,
8052 0x57, 0x80, 0x57, 0xCF,
8053
8054 0x66, 0x33, 0x66, 0xCF,
8055 0x47, 0x3B, 0x47, 0xCF,
8056
8057 0x56, 0x33, 0x56, 0xCF,
8058 0x67, 0x3B, 0x67, 0xCF,
8059
8060 0x0B, 0x48, 0xA0, 0xE8,
8061 0x1B, 0x58, 0xA0, 0xE8,
8062
8063 0x2B, 0x68, 0xA0, 0xE8,
8064 0x0C, 0x49, 0xA0, 0xE8,
8065
8066 0x1C, 0x59, 0xA0, 0xE8,
8067 0x2C, 0x69, 0xA0, 0xE8,
8068
8069 0x0B, 0x00,
8070 0x1B, 0x00,
8071 0x2B, 0x00,
8072 0x00, 0xE0,
8073
8074 0x0C, 0x00,
8075 0x1C, 0x00,
8076 0x2C, 0x00,
8077 0x00, 0xE0,
8078
8079 0x0B, 0x65,
8080 0x1B, 0x65,
8081 0x2B, 0x65,
8082 0x00, 0xE0,
8083
8084 0x0C, 0x65,
8085 0x1C, 0x65,
8086 0x2C, 0x65,
8087 0x00, 0xE0,
8088
8089 0x0B, 0x1B, 0x60, 0xEC,
8090 0x34, 0xD7, 0x34, 0xAD,
8091
8092 0x2B, 0x80, 0x60, 0xEC,
8093 0x0C, 0x1C, 0x60, 0xEC,
8094
8095 0x3C, 0xD7, 0x3C, 0xAD,
8096 0x2C, 0x80, 0x60, 0xEC,
8097
8098 0x0B, 0x2B, 0xDE, 0xE8,
8099 0x1B, 0x80, 0xDE, 0xE8,
8100
8101 0x34, 0x80, 0x34, 0xBD,
8102 0x3C, 0x80, 0x3C, 0xBD,
8103
8104 0x33, 0xD7, 0x0B, 0xBD,
8105 0x3B, 0xD7, 0x1B, 0xBD,
8106
8107 0x48, 0x80, 0x48, 0xCF,
8108 0x59, 0x80, 0x59, 0xCF,
8109
8110 0x68, 0x33, 0x68, 0xCF,
8111 0x49, 0x3B, 0x49, 0xCF,
8112
8113 0xA9, 0xFF, 0x20, 0xEA,
8114 0x00, 0x80, 0x00, 0xE8,
8115
8116 0x58, 0x33, 0x58, 0xCF,
8117 0x69, 0x3B, 0x69, 0xCF,
8118
8119 0x67, 0xFF, 0x20, 0xEA,
8120 0x57, 0xC0, 0xBF, 0xEA,
8121
8122 0x00, 0x80, 0xA0, 0xE9,
8123 0x00, 0x00, 0xD8, 0xEC,
8124
8125};
8126
8127static unsigned char warp_g400_t2gzsf[] = {
8128
8129 0x00, 0x8A, 0x98, 0xE9,
8130 0x00, 0x80, 0x00, 0xE8,
8131
8132 0x00, 0x80, 0xA0, 0xE9,
8133 0x00, 0x00, 0xD8, 0xEC,
8134
8135 0xFF, 0x80, 0xC0, 0xE9,
8136 0x00, 0x80, 0x00, 0xE8,
8137
8138 0x0A, 0x40, 0x50, 0xBF,
8139 0x2A, 0x40, 0x60, 0xBF,
8140
8141 0x32, 0x41, 0x51, 0xBF,
8142 0x3A, 0x41, 0x61, 0xBF,
8143
8144 0xC3, 0x6B,
8145 0xD3, 0x6B,
8146 0x00, 0x8A, 0x98, 0xE9,
8147
8148 0x73, 0x7B, 0xC8, 0xEC,
8149 0x96, 0xE2,
8150 0x41, 0x04,
8151
8152 0x7B, 0x43, 0xA0, 0xE8,
8153 0x73, 0x53, 0xA0, 0xE8,
8154
8155 0xAD, 0xEE, 0x23, 0x9F,
8156 0x00, 0xE0,
8157 0x51, 0x04,
8158
8159 0x90, 0xE2,
8160 0x61, 0x04,
8161 0x31, 0x46, 0xB1, 0xE8,
8162
8163 0x51, 0x41, 0xE0, 0xEC,
8164 0x39, 0x67, 0xB1, 0xE8,
8165
8166 0x00, 0x04,
8167 0x46, 0xE2,
8168 0x73, 0x63, 0xA0, 0xE8,
8169
8170 0x61, 0x41, 0xE0, 0xEC,
8171 0x31, 0x00,
8172 0x39, 0x00,
8173
8174 0x8A, 0x80, 0x15, 0xEA,
8175 0x10, 0x04,
8176 0x20, 0x04,
8177
8178 0x61, 0x51, 0xE0, 0xEC,
8179 0x2F, 0x41, 0x60, 0xEA,
8180
8181 0x31, 0x20,
8182 0x39, 0x20,
8183 0x1F, 0x42, 0xA0, 0xE8,
8184
8185 0x2A, 0x42, 0x52, 0xBF,
8186 0x0F, 0x52, 0xA0, 0xE8,
8187
8188 0x1A, 0x42, 0x62, 0xBF,
8189 0x1E, 0x51, 0x60, 0xEA,
8190
8191 0x73, 0x7B, 0xC8, 0xEC,
8192 0x0E, 0x61, 0x60, 0xEA,
8193
8194 0x32, 0x40, 0x50, 0xBD,
8195 0x22, 0x40, 0x60, 0xBD,
8196
8197 0x12, 0x41, 0x51, 0xBD,
8198 0x3A, 0x41, 0x61, 0xBD,
8199
8200 0xBF, 0x2F, 0x0E, 0xBD,
8201 0x97, 0xE2,
8202 0x7B, 0x72,
8203
8204 0x32, 0x20,
8205 0x22, 0x20,
8206 0x12, 0x20,
8207 0x3A, 0x20,
8208
8209 0x35, 0x48, 0xB1, 0xE8,
8210 0x3D, 0x59, 0xB1, 0xE8,
8211
8212 0x46, 0x31, 0x46, 0xBF,
8213 0x56, 0x31, 0x56, 0xBF,
8214
8215 0xB3, 0xE2, 0x2D, 0x9F,
8216 0x00, 0x80, 0x00, 0xE8,
8217
8218 0x66, 0x31, 0x66, 0xBF,
8219 0x47, 0x39, 0x47, 0xBF,
8220
8221 0x57, 0x39, 0x57, 0xBF,
8222 0x67, 0x39, 0x67, 0xBF,
8223
8224 0x7B, 0x80, 0x07, 0xEA,
8225 0x24, 0x41, 0x20, 0xE9,
8226
8227 0x35, 0x00,
8228 0x3D, 0x00,
8229 0x00, 0xE0,
8230 0x2D, 0x73,
8231
8232 0x33, 0x72,
8233 0x0C, 0xE3,
8234 0x8D, 0x2F, 0x1E, 0xBD,
8235
8236 0x43, 0x75, 0xF8, 0xEC,
8237 0x35, 0x20,
8238 0x3D, 0x20,
8239
8240 0x43, 0x43, 0x2D, 0xDF,
8241 0x53, 0x53, 0x2D, 0xDF,
8242
8243 0xAE, 0x1E, 0x0E, 0xBD,
8244 0x58, 0xE3,
8245 0x33, 0x66,
8246
8247 0x48, 0x35, 0x48, 0xBF,
8248 0x58, 0x35, 0x58, 0xBF,
8249
8250 0x68, 0x35, 0x68, 0xBF,
8251 0x49, 0x3D, 0x49, 0xBF,
8252
8253 0x59, 0x3D, 0x59, 0xBF,
8254 0x69, 0x3D, 0x69, 0xBF,
8255
8256 0x63, 0x63, 0x2D, 0xDF,
8257 0x4D, 0x7D, 0xF8, 0xEC,
8258
8259 0x59, 0xE3,
8260 0x00, 0xE0,
8261 0xB8, 0x38, 0x33, 0xBF,
8262
8263 0x2D, 0x73,
8264 0x30, 0x76,
8265 0x18, 0x3A, 0x41, 0xE9,
8266
8267 0x3F, 0x53, 0xA0, 0xE8,
8268 0x05, 0x80, 0x3D, 0xEA,
8269
8270 0x37, 0x43, 0xA0, 0xE8,
8271 0x3D, 0x63, 0xA0, 0xE8,
8272
8273 0x50, 0x70, 0xF8, 0xEC,
8274 0x2B, 0x50, 0x3C, 0xE9,
8275
8276 0x1F, 0x0F, 0xBC, 0xE8,
8277 0x00, 0x80, 0x00, 0xE8,
8278
8279 0x59, 0x78, 0xF8, 0xEC,
8280 0x00, 0x80, 0x00, 0xE8,
8281
8282 0x15, 0xC0, 0x20, 0xE9,
8283 0x15, 0xC0, 0x20, 0xE9,
8284
8285 0x15, 0xC0, 0x20, 0xE9,
8286 0x15, 0xC0, 0x20, 0xE9,
8287
8288 0x1E, 0x12, 0x41, 0xE9,
8289 0x1A, 0x22, 0x41, 0xE9,
8290
8291 0x46, 0x37, 0x46, 0xDF,
8292 0x56, 0x3F, 0x56, 0xDF,
8293
8294 0x2B, 0x40, 0x3D, 0xE9,
8295 0x66, 0x3D, 0x66, 0xDF,
8296
8297 0x1D, 0x32, 0x41, 0xE9,
8298 0x67, 0x3D, 0x67, 0xDF,
8299
8300 0x47, 0x37, 0x47, 0xDF,
8301 0x57, 0x3F, 0x57, 0xDF,
8302
8303 0x2A, 0x40, 0x20, 0xE9,
8304 0x59, 0x3F, 0x59, 0xDF,
8305
8306 0x16, 0x30, 0x20, 0xE9,
8307 0x69, 0x3D, 0x69, 0xDF,
8308
8309 0x48, 0x37, 0x48, 0xDF,
8310 0x58, 0x3F, 0x58, 0xDF,
8311
8312 0x68, 0x3D, 0x68, 0xDF,
8313 0x49, 0x37, 0x49, 0xDF,
8314
8315 0x32, 0x32, 0x2D, 0xDF,
8316 0x22, 0x22, 0x2D, 0xDF,
8317
8318 0x12, 0x12, 0x2D, 0xDF,
8319 0x3A, 0x3A, 0x2D, 0xDF,
8320
8321 0x0F, 0xCF, 0x74, 0xC2,
8322 0x37, 0xCF, 0x74, 0xC4,
8323
8324 0x0A, 0x44, 0x54, 0xB0,
8325 0x02, 0x44, 0x64, 0xB0,
8326
8327 0x3D, 0xCF, 0x74, 0xC0,
8328 0x34, 0x37, 0x20, 0xE9,
8329
8330 0x31, 0x53, 0x2F, 0x9F,
8331 0x38, 0x0F, 0x20, 0xE9,
8332
8333 0x39, 0xE5, 0x2C, 0x9F,
8334 0x3C, 0x3D, 0x20, 0xE9,
8335
8336 0x2A, 0x44, 0x54, 0xB2,
8337 0x1A, 0x44, 0x64, 0xB2,
8338
8339 0x36, 0x80, 0x3A, 0xEA,
8340 0x0A, 0x20,
8341 0x02, 0x20,
8342
8343 0x0F, 0xCF, 0x75, 0xC0,
8344 0x2A, 0x20,
8345 0x1A, 0x20,
8346
8347 0x30, 0x50, 0x2E, 0x9F,
8348 0x32, 0x31, 0x5F, 0xE9,
8349
8350 0x38, 0x21, 0x2C, 0x9F,
8351 0x33, 0x39, 0x5F, 0xE9,
8352
8353 0x3D, 0xCF, 0x75, 0xC2,
8354 0x37, 0xCF, 0x75, 0xC4,
8355
8356 0x31, 0x53, 0x2F, 0x9F,
8357 0xA6, 0x0F, 0x20, 0xE9,
8358
8359 0x39, 0xE5, 0x2C, 0x9F,
8360 0xA3, 0x3D, 0x20, 0xE9,
8361
8362 0x2A, 0x44, 0x54, 0xB4,
8363 0x1A, 0x44, 0x64, 0xB4,
8364
8365 0x0A, 0x45, 0x55, 0xB0,
8366 0x02, 0x45, 0x65, 0xB0,
8367
8368 0x88, 0x73, 0x5E, 0xE9,
8369 0x2A, 0x20,
8370 0x1A, 0x20,
8371
8372 0xA0, 0x37, 0x20, 0xE9,
8373 0x0A, 0x20,
8374 0x02, 0x20,
8375
8376 0x31, 0x53, 0x2F, 0x9F,
8377 0x3E, 0x30, 0x4F, 0xE9,
8378
8379 0x39, 0xE5, 0x2C, 0x9F,
8380 0x3F, 0x38, 0x4F, 0xE9,
8381
8382 0x30, 0x50, 0x2E, 0x9F,
8383 0x3A, 0x31, 0x4F, 0xE9,
8384
8385 0x38, 0x21, 0x2C, 0x9F,
8386 0x3B, 0x39, 0x4F, 0xE9,
8387
8388 0x2A, 0x45, 0x55, 0xB2,
8389 0x1A, 0x45, 0x65, 0xB2,
8390
8391 0x0A, 0x45, 0x55, 0xB4,
8392 0x02, 0x45, 0x65, 0xB4,
8393
8394 0x0F, 0xCF, 0x75, 0xC6,
8395 0x2A, 0x20,
8396 0x1A, 0x20,
8397
8398 0xA7, 0x30, 0x4F, 0xE9,
8399 0x0A, 0x20,
8400 0x02, 0x20,
8401
8402 0x31, 0x53, 0x2F, 0x9F,
8403 0x31, 0x0F, 0x20, 0xE9,
8404
8405 0x39, 0xE5, 0x2C, 0x9F,
8406 0xA8, 0x38, 0x4F, 0xE9,
8407
8408 0x2A, 0x45, 0x55, 0xB6,
8409 0x1A, 0x45, 0x65, 0xB6,
8410
8411 0x30, 0x50, 0x2E, 0x9F,
8412 0x36, 0x31, 0x4F, 0xE9,
8413
8414 0x38, 0x21, 0x2C, 0x9F,
8415 0x37, 0x39, 0x4F, 0xE9,
8416
8417 0x00, 0x80, 0x00, 0xE8,
8418 0x2A, 0x20,
8419 0x1A, 0x20,
8420
8421 0x2A, 0x46, 0x56, 0xBF,
8422 0x1A, 0x46, 0x66, 0xBF,
8423
8424 0x31, 0x53, 0x2F, 0x9F,
8425 0xA4, 0x31, 0x4F, 0xE9,
8426
8427 0x39, 0xE5, 0x2C, 0x9F,
8428 0xA5, 0x39, 0x4F, 0xE9,
8429
8430 0x0A, 0x47, 0x57, 0xBF,
8431 0x02, 0x47, 0x67, 0xBF,
8432
8433 0x31, 0x53, 0x2F, 0x9F,
8434 0xA1, 0x30, 0x4F, 0xE9,
8435
8436 0x39, 0xE5, 0x2C, 0x9F,
8437 0xA2, 0x38, 0x4F, 0xE9,
8438
8439 0x2A, 0x43, 0x53, 0xBF,
8440 0x1A, 0x43, 0x63, 0xBF,
8441
8442 0x30, 0x50, 0x2E, 0x9F,
8443 0x35, 0x31, 0x4F, 0xE9,
8444
8445 0x38, 0x21, 0x2C, 0x9F,
8446 0x39, 0x39, 0x4F, 0xE9,
8447
8448 0x0A, 0x48, 0x58, 0xBF,
8449 0x02, 0x48, 0x68, 0xBF,
8450
8451 0x31, 0x53, 0x2F, 0x9F,
8452 0x80, 0x31, 0x57, 0xE9,
8453
8454 0x39, 0xE5, 0x2C, 0x9F,
8455 0x81, 0x39, 0x57, 0xE9,
8456
8457 0x2A, 0x49, 0x59, 0xBF,
8458 0x1A, 0x49, 0x69, 0xBF,
8459
8460 0x30, 0x50, 0x2E, 0x9F,
8461 0x82, 0x30, 0x57, 0xE9,
8462
8463 0x38, 0x21, 0x2C, 0x9F,
8464 0x83, 0x38, 0x57, 0xE9,
8465
8466 0x31, 0x53, 0x2F, 0x9F,
8467 0x84, 0x31, 0x5E, 0xE9,
8468
8469 0x39, 0xE5, 0x2C, 0x9F,
8470 0x85, 0x39, 0x5E, 0xE9,
8471
8472 0x86, 0x76, 0x57, 0xE9,
8473 0x8A, 0x36, 0x20, 0xE9,
8474
8475 0x87, 0x77, 0x57, 0xE9,
8476 0x8B, 0x3E, 0xBF, 0xEA,
8477
8478 0x80, 0x30, 0x57, 0xE9,
8479 0x81, 0x38, 0x57, 0xE9,
8480
8481 0x82, 0x31, 0x57, 0xE9,
8482 0x86, 0x78, 0x57, 0xE9,
8483
8484 0x83, 0x39, 0x57, 0xE9,
8485 0x87, 0x79, 0x57, 0xE9,
8486
8487 0x30, 0x1F, 0x5F, 0xE9,
8488 0x8A, 0x34, 0x20, 0xE9,
8489
8490 0x8B, 0x3C, 0x20, 0xE9,
8491 0x37, 0x50, 0x60, 0xBD,
8492
8493 0x57, 0x0D, 0x20, 0xE9,
8494 0x35, 0x51, 0x61, 0xBD,
8495
8496 0x2B, 0x50, 0x20, 0xE9,
8497 0x1D, 0x37, 0xE1, 0xEA,
8498
8499 0x1E, 0x35, 0xE1, 0xEA,
8500 0x00, 0xE0,
8501 0x0E, 0x77,
8502
8503 0x24, 0x51, 0x20, 0xE9,
8504 0x8D, 0xFF, 0x20, 0xEA,
8505
8506 0x16, 0x0E, 0x20, 0xE9,
8507 0x57, 0x2E, 0xBF, 0xEA,
8508
8509 0x0B, 0x46, 0xA0, 0xE8,
8510 0x1B, 0x56, 0xA0, 0xE8,
8511
8512 0x2B, 0x66, 0xA0, 0xE8,
8513 0x0C, 0x47, 0xA0, 0xE8,
8514
8515 0x1C, 0x57, 0xA0, 0xE8,
8516 0x2C, 0x67, 0xA0, 0xE8,
8517
8518 0x0B, 0x00,
8519 0x1B, 0x00,
8520 0x2B, 0x00,
8521 0x00, 0xE0,
8522
8523 0x0C, 0x00,
8524 0x1C, 0x00,
8525 0x2C, 0x00,
8526 0x00, 0xE0,
8527
8528 0x0B, 0x65,
8529 0x1B, 0x65,
8530 0x2B, 0x65,
8531 0x00, 0xE0,
8532
8533 0x0C, 0x65,
8534 0x1C, 0x65,
8535 0x2C, 0x65,
8536 0x00, 0xE0,
8537
8538 0x0B, 0x1B, 0x60, 0xEC,
8539 0x36, 0xD7, 0x36, 0xAD,
8540
8541 0x2B, 0x80, 0x60, 0xEC,
8542 0x0C, 0x1C, 0x60, 0xEC,
8543
8544 0x3E, 0xD7, 0x3E, 0xAD,
8545 0x2C, 0x80, 0x60, 0xEC,
8546
8547 0x0B, 0x2B, 0xDE, 0xE8,
8548 0x1B, 0x80, 0xDE, 0xE8,
8549
8550 0x36, 0x80, 0x36, 0xBD,
8551 0x3E, 0x80, 0x3E, 0xBD,
8552
8553 0x33, 0xD7, 0x0B, 0xBD,
8554 0x3B, 0xD7, 0x1B, 0xBD,
8555
8556 0x46, 0x80, 0x46, 0xCF,
8557 0x57, 0x80, 0x57, 0xCF,
8558
8559 0x66, 0x33, 0x66, 0xCF,
8560 0x47, 0x3B, 0x47, 0xCF,
8561
8562 0x56, 0x33, 0x56, 0xCF,
8563 0x67, 0x3B, 0x67, 0xCF,
8564
8565 0x0B, 0x48, 0xA0, 0xE8,
8566 0x1B, 0x58, 0xA0, 0xE8,
8567
8568 0x2B, 0x68, 0xA0, 0xE8,
8569 0x0C, 0x49, 0xA0, 0xE8,
8570
8571 0x1C, 0x59, 0xA0, 0xE8,
8572 0x2C, 0x69, 0xA0, 0xE8,
8573
8574 0x0B, 0x00,
8575 0x1B, 0x00,
8576 0x2B, 0x00,
8577 0x00, 0xE0,
8578
8579 0x0C, 0x00,
8580 0x1C, 0x00,
8581 0x2C, 0x00,
8582 0x00, 0xE0,
8583
8584 0x0B, 0x65,
8585 0x1B, 0x65,
8586 0x2B, 0x65,
8587 0x00, 0xE0,
8588
8589 0x0C, 0x65,
8590 0x1C, 0x65,
8591 0x2C, 0x65,
8592 0x00, 0xE0,
8593
8594 0x0B, 0x1B, 0x60, 0xEC,
8595 0x34, 0xD7, 0x34, 0xAD,
8596
8597 0x2B, 0x80, 0x60, 0xEC,
8598 0x0C, 0x1C, 0x60, 0xEC,
8599
8600 0x3C, 0xD7, 0x3C, 0xAD,
8601 0x2C, 0x80, 0x60, 0xEC,
8602
8603 0x0B, 0x2B, 0xDE, 0xE8,
8604 0x1B, 0x80, 0xDE, 0xE8,
8605
8606 0x34, 0x80, 0x34, 0xBD,
8607 0x3C, 0x80, 0x3C, 0xBD,
8608
8609 0x33, 0xD7, 0x0B, 0xBD,
8610 0x3B, 0xD7, 0x1B, 0xBD,
8611
8612 0x48, 0x80, 0x48, 0xCF,
8613 0x59, 0x80, 0x59, 0xCF,
8614
8615 0x68, 0x33, 0x68, 0xCF,
8616 0x49, 0x3B, 0x49, 0xCF,
8617
8618 0xAD, 0xFF, 0x20, 0xEA,
8619 0x00, 0x80, 0x00, 0xE8,
8620
8621 0x58, 0x33, 0x58, 0xCF,
8622 0x69, 0x3B, 0x69, 0xCF,
8623
8624 0x6B, 0xFF, 0x20, 0xEA,
8625 0x57, 0xC0, 0xBF, 0xEA,
8626
8627 0x00, 0x80, 0xA0, 0xE9,
8628 0x00, 0x00, 0xD8, 0xEC,
8629
8630};
8631
8632static unsigned char warp_g400_tgz[] = {
8633
8634 0x00, 0x88, 0x98, 0xE9,
8635 0x00, 0x80, 0x00, 0xE8,
8636
8637 0x00, 0x80, 0xA0, 0xE9,
8638 0x00, 0x00, 0xD8, 0xEC,
8639
8640 0xFF, 0x80, 0xC0, 0xE9,
8641 0x00, 0x80, 0x00, 0xE8,
8642
8643 0x22, 0x40, 0x48, 0xBF,
8644 0x2A, 0x40, 0x50, 0xBF,
8645
8646 0x32, 0x41, 0x49, 0xBF,
8647 0x3A, 0x41, 0x51, 0xBF,
8648
8649 0xC3, 0x6B,
8650 0xCB, 0x6B,
8651 0x00, 0x88, 0x98, 0xE9,
8652
8653 0x73, 0x7B, 0xC8, 0xEC,
8654 0x96, 0xE2,
8655 0x41, 0x04,
8656
8657 0x7B, 0x43, 0xA0, 0xE8,
8658 0x73, 0x4B, 0xA0, 0xE8,
8659
8660 0xAD, 0xEE, 0x29, 0x9F,
8661 0x00, 0xE0,
8662 0x49, 0x04,
8663
8664 0x90, 0xE2,
8665 0x51, 0x04,
8666 0x31, 0x46, 0xB1, 0xE8,
8667
8668 0x49, 0x41, 0xC0, 0xEC,
8669 0x39, 0x57, 0xB1, 0xE8,
8670
8671 0x00, 0x04,
8672 0x46, 0xE2,
8673 0x73, 0x53, 0xA0, 0xE8,
8674
8675 0x51, 0x41, 0xC0, 0xEC,
8676 0x31, 0x00,
8677 0x39, 0x00,
8678
8679 0x58, 0x80, 0x15, 0xEA,
8680 0x08, 0x04,
8681 0x10, 0x04,
8682
8683 0x51, 0x49, 0xC0, 0xEC,
8684 0x2F, 0x41, 0x60, 0xEA,
8685
8686 0x31, 0x20,
8687 0x39, 0x20,
8688 0x1F, 0x42, 0xA0, 0xE8,
8689
8690 0x2A, 0x42, 0x4A, 0xBF,
8691 0x27, 0x4A, 0xA0, 0xE8,
8692
8693 0x1A, 0x42, 0x52, 0xBF,
8694 0x1E, 0x49, 0x60, 0xEA,
8695
8696 0x73, 0x7B, 0xC8, 0xEC,
8697 0x26, 0x51, 0x60, 0xEA,
8698
8699 0x32, 0x40, 0x48, 0xBD,
8700 0x22, 0x40, 0x50, 0xBD,
8701
8702 0x12, 0x41, 0x49, 0xBD,
8703 0x3A, 0x41, 0x51, 0xBD,
8704
8705 0xBF, 0x2F, 0x26, 0xBD,
8706 0x00, 0xE0,
8707 0x7B, 0x72,
8708
8709 0x32, 0x20,
8710 0x22, 0x20,
8711 0x12, 0x20,
8712 0x3A, 0x20,
8713
8714 0x46, 0x31, 0x46, 0xBF,
8715 0x4E, 0x31, 0x4E, 0xBF,
8716
8717 0xB3, 0xE2, 0x2D, 0x9F,
8718 0x00, 0x80, 0x00, 0xE8,
8719
8720 0x56, 0x31, 0x56, 0xBF,
8721 0x47, 0x39, 0x47, 0xBF,
8722
8723 0x4F, 0x39, 0x4F, 0xBF,
8724 0x57, 0x39, 0x57, 0xBF,
8725
8726 0x4A, 0x80, 0x07, 0xEA,
8727 0x24, 0x41, 0x20, 0xE9,
8728
8729 0x42, 0x73, 0xF8, 0xEC,
8730 0x00, 0xE0,
8731 0x2D, 0x73,
8732
8733 0x33, 0x72,
8734 0x0C, 0xE3,
8735 0xA5, 0x2F, 0x1E, 0xBD,
8736
8737 0x43, 0x43, 0x2D, 0xDF,
8738 0x4B, 0x4B, 0x2D, 0xDF,
8739
8740 0xAE, 0x1E, 0x26, 0xBD,
8741 0x58, 0xE3,
8742 0x33, 0x66,
8743
8744 0x53, 0x53, 0x2D, 0xDF,
8745 0x00, 0x80, 0x00, 0xE8,
8746
8747 0xB8, 0x38, 0x33, 0xBF,
8748 0x00, 0xE0,
8749 0x59, 0xE3,
8750
8751 0x1E, 0x12, 0x41, 0xE9,
8752 0x1A, 0x22, 0x41, 0xE9,
8753
8754 0x2B, 0x40, 0x3D, 0xE9,
8755 0x3F, 0x4B, 0xA0, 0xE8,
8756
8757 0x2D, 0x73,
8758 0x30, 0x76,
8759 0x05, 0x80, 0x3D, 0xEA,
8760
8761 0x37, 0x43, 0xA0, 0xE8,
8762 0x3D, 0x53, 0xA0, 0xE8,
8763
8764 0x48, 0x70, 0xF8, 0xEC,
8765 0x2B, 0x48, 0x3C, 0xE9,
8766
8767 0x1F, 0x27, 0xBC, 0xE8,
8768 0x00, 0x80, 0x00, 0xE8,
8769
8770 0x00, 0x80, 0x00, 0xE8,
8771 0x00, 0x80, 0x00, 0xE8,
8772
8773 0x15, 0xC0, 0x20, 0xE9,
8774 0x15, 0xC0, 0x20, 0xE9,
8775
8776 0x15, 0xC0, 0x20, 0xE9,
8777 0x15, 0xC0, 0x20, 0xE9,
8778
8779 0x18, 0x3A, 0x41, 0xE9,
8780 0x1D, 0x32, 0x41, 0xE9,
8781
8782 0x2A, 0x40, 0x20, 0xE9,
8783 0x56, 0x3D, 0x56, 0xDF,
8784
8785 0x46, 0x37, 0x46, 0xDF,
8786 0x4E, 0x3F, 0x4E, 0xDF,
8787
8788 0x16, 0x30, 0x20, 0xE9,
8789 0x4F, 0x3F, 0x4F, 0xDF,
8790
8791 0x32, 0x32, 0x2D, 0xDF,
8792 0x22, 0x22, 0x2D, 0xDF,
8793
8794 0x12, 0x12, 0x2D, 0xDF,
8795 0x3A, 0x3A, 0x2D, 0xDF,
8796
8797 0x47, 0x37, 0x47, 0xDF,
8798 0x57, 0x3D, 0x57, 0xDF,
8799
8800 0x3D, 0xCF, 0x74, 0xC0,
8801 0x37, 0xCF, 0x74, 0xC4,
8802
8803 0x31, 0x53, 0x2F, 0x9F,
8804 0x34, 0x80, 0x20, 0xE9,
8805
8806 0x39, 0xE5, 0x2C, 0x9F,
8807 0x3C, 0x3D, 0x20, 0xE9,
8808
8809 0x0A, 0x44, 0x4C, 0xB0,
8810 0x02, 0x44, 0x54, 0xB0,
8811
8812 0x2A, 0x44, 0x4C, 0xB2,
8813 0x1A, 0x44, 0x54, 0xB2,
8814
8815 0x1D, 0x80, 0x3A, 0xEA,
8816 0x0A, 0x20,
8817 0x02, 0x20,
8818
8819 0x3D, 0xCF, 0x74, 0xC2,
8820 0x2A, 0x20,
8821 0x1A, 0x20,
8822
8823 0x30, 0x50, 0x2E, 0x9F,
8824 0x32, 0x31, 0x5F, 0xE9,
8825
8826 0x38, 0x21, 0x2C, 0x9F,
8827 0x33, 0x39, 0x5F, 0xE9,
8828
8829 0x31, 0x53, 0x2F, 0x9F,
8830 0x00, 0x80, 0x00, 0xE8,
8831
8832 0x2A, 0x44, 0x4C, 0xB4,
8833 0x1A, 0x44, 0x54, 0xB4,
8834
8835 0x39, 0xE5, 0x2C, 0x9F,
8836 0x38, 0x3D, 0x20, 0xE9,
8837
8838 0x88, 0x73, 0x5E, 0xE9,
8839 0x2A, 0x20,
8840 0x1A, 0x20,
8841
8842 0x2A, 0x46, 0x4E, 0xBF,
8843 0x1A, 0x46, 0x56, 0xBF,
8844
8845 0x31, 0x53, 0x2F, 0x9F,
8846 0x3E, 0x30, 0x4F, 0xE9,
8847
8848 0x39, 0xE5, 0x2C, 0x9F,
8849 0x3F, 0x38, 0x4F, 0xE9,
8850
8851 0x0A, 0x47, 0x4F, 0xBF,
8852 0x02, 0x47, 0x57, 0xBF,
8853
8854 0x31, 0x53, 0x2F, 0x9F,
8855 0x3A, 0x31, 0x4F, 0xE9,
8856
8857 0x39, 0xE5, 0x2C, 0x9F,
8858 0x3B, 0x39, 0x4F, 0xE9,
8859
8860 0x2A, 0x43, 0x4B, 0xBF,
8861 0x1A, 0x43, 0x53, 0xBF,
8862
8863 0x30, 0x50, 0x2E, 0x9F,
8864 0x36, 0x31, 0x4F, 0xE9,
8865
8866 0x38, 0x21, 0x2C, 0x9F,
8867 0x37, 0x39, 0x4F, 0xE9,
8868
8869 0x31, 0x53, 0x2F, 0x9F,
8870 0x80, 0x31, 0x57, 0xE9,
8871
8872 0x39, 0xE5, 0x2C, 0x9F,
8873 0x81, 0x39, 0x57, 0xE9,
8874
8875 0x37, 0x48, 0x50, 0xBD,
8876 0x8A, 0x36, 0x20, 0xE9,
8877
8878 0x86, 0x76, 0x57, 0xE9,
8879 0x8B, 0x3E, 0x20, 0xE9,
8880
8881 0x82, 0x30, 0x57, 0xE9,
8882 0x87, 0x77, 0x57, 0xE9,
8883
8884 0x83, 0x38, 0x57, 0xE9,
8885 0x35, 0x49, 0x51, 0xBD,
8886
8887 0x84, 0x31, 0x5E, 0xE9,
8888 0x30, 0x1F, 0x5F, 0xE9,
8889
8890 0x85, 0x39, 0x5E, 0xE9,
8891 0x57, 0x25, 0x20, 0xE9,
8892
8893 0x2B, 0x48, 0x20, 0xE9,
8894 0x1D, 0x37, 0xE1, 0xEA,
8895
8896 0x1E, 0x35, 0xE1, 0xEA,
8897 0x00, 0xE0,
8898 0x26, 0x77,
8899
8900 0x24, 0x49, 0x20, 0xE9,
8901 0xAF, 0xFF, 0x20, 0xEA,
8902
8903 0x16, 0x26, 0x20, 0xE9,
8904 0x57, 0x2E, 0xBF, 0xEA,
8905
8906 0x1C, 0x46, 0xA0, 0xE8,
8907 0x23, 0x4E, 0xA0, 0xE8,
8908
8909 0x2B, 0x56, 0xA0, 0xE8,
8910 0x1D, 0x47, 0xA0, 0xE8,
8911
8912 0x24, 0x4F, 0xA0, 0xE8,
8913 0x2C, 0x57, 0xA0, 0xE8,
8914
8915 0x1C, 0x00,
8916 0x23, 0x00,
8917 0x2B, 0x00,
8918 0x00, 0xE0,
8919
8920 0x1D, 0x00,
8921 0x24, 0x00,
8922 0x2C, 0x00,
8923 0x00, 0xE0,
8924
8925 0x1C, 0x65,
8926 0x23, 0x65,
8927 0x2B, 0x65,
8928 0x00, 0xE0,
8929
8930 0x1D, 0x65,
8931 0x24, 0x65,
8932 0x2C, 0x65,
8933 0x00, 0xE0,
8934
8935 0x1C, 0x23, 0x60, 0xEC,
8936 0x36, 0xD7, 0x36, 0xAD,
8937
8938 0x2B, 0x80, 0x60, 0xEC,
8939 0x1D, 0x24, 0x60, 0xEC,
8940
8941 0x3E, 0xD7, 0x3E, 0xAD,
8942 0x2C, 0x80, 0x60, 0xEC,
8943
8944 0x1C, 0x2B, 0xDE, 0xE8,
8945 0x23, 0x80, 0xDE, 0xE8,
8946
8947 0x36, 0x80, 0x36, 0xBD,
8948 0x3E, 0x80, 0x3E, 0xBD,
8949
8950 0x33, 0xD7, 0x1C, 0xBD,
8951 0x3B, 0xD7, 0x23, 0xBD,
8952
8953 0x46, 0x80, 0x46, 0xCF,
8954 0x4F, 0x80, 0x4F, 0xCF,
8955
8956 0x56, 0x33, 0x56, 0xCF,
8957 0x47, 0x3B, 0x47, 0xCF,
8958
8959 0xD6, 0xFF, 0x20, 0xEA,
8960 0x00, 0x80, 0x00, 0xE8,
8961
8962 0x4E, 0x33, 0x4E, 0xCF,
8963 0x57, 0x3B, 0x57, 0xCF,
8964
8965 0x9D, 0xFF, 0x20, 0xEA,
8966 0x57, 0xC0, 0xBF, 0xEA,
8967
8968 0x00, 0x80, 0xA0, 0xE9,
8969 0x00, 0x00, 0xD8, 0xEC,
8970
8971};
8972
8973static unsigned char warp_g400_tgza[] = {
8974
8975 0x00, 0x88, 0x98, 0xE9,
8976 0x00, 0x80, 0x00, 0xE8,
8977
8978 0x00, 0x80, 0xA0, 0xE9,
8979 0x00, 0x00, 0xD8, 0xEC,
8980
8981 0xFF, 0x80, 0xC0, 0xE9,
8982 0x00, 0x80, 0x00, 0xE8,
8983
8984 0x22, 0x40, 0x48, 0xBF,
8985 0x2A, 0x40, 0x50, 0xBF,
8986
8987 0x32, 0x41, 0x49, 0xBF,
8988 0x3A, 0x41, 0x51, 0xBF,
8989
8990 0xC3, 0x6B,
8991 0xCB, 0x6B,
8992 0x00, 0x88, 0x98, 0xE9,
8993
8994 0x73, 0x7B, 0xC8, 0xEC,
8995 0x96, 0xE2,
8996 0x41, 0x04,
8997
8998 0x7B, 0x43, 0xA0, 0xE8,
8999 0x73, 0x4B, 0xA0, 0xE8,
9000
9001 0xAD, 0xEE, 0x29, 0x9F,
9002 0x00, 0xE0,
9003 0x49, 0x04,
9004
9005 0x90, 0xE2,
9006 0x51, 0x04,
9007 0x31, 0x46, 0xB1, 0xE8,
9008
9009 0x49, 0x41, 0xC0, 0xEC,
9010 0x39, 0x57, 0xB1, 0xE8,
9011
9012 0x00, 0x04,
9013 0x46, 0xE2,
9014 0x73, 0x53, 0xA0, 0xE8,
9015
9016 0x51, 0x41, 0xC0, 0xEC,
9017 0x31, 0x00,
9018 0x39, 0x00,
9019
9020 0x5C, 0x80, 0x15, 0xEA,
9021 0x08, 0x04,
9022 0x10, 0x04,
9023
9024 0x51, 0x49, 0xC0, 0xEC,
9025 0x2F, 0x41, 0x60, 0xEA,
9026
9027 0x31, 0x20,
9028 0x39, 0x20,
9029 0x1F, 0x42, 0xA0, 0xE8,
9030
9031 0x2A, 0x42, 0x4A, 0xBF,
9032 0x27, 0x4A, 0xA0, 0xE8,
9033
9034 0x1A, 0x42, 0x52, 0xBF,
9035 0x1E, 0x49, 0x60, 0xEA,
9036
9037 0x73, 0x7B, 0xC8, 0xEC,
9038 0x26, 0x51, 0x60, 0xEA,
9039
9040 0x32, 0x40, 0x48, 0xBD,
9041 0x22, 0x40, 0x50, 0xBD,
9042
9043 0x12, 0x41, 0x49, 0xBD,
9044 0x3A, 0x41, 0x51, 0xBD,
9045
9046 0xBF, 0x2F, 0x26, 0xBD,
9047 0x00, 0xE0,
9048 0x7B, 0x72,
9049
9050 0x32, 0x20,
9051 0x22, 0x20,
9052 0x12, 0x20,
9053 0x3A, 0x20,
9054
9055 0x46, 0x31, 0x46, 0xBF,
9056 0x4E, 0x31, 0x4E, 0xBF,
9057
9058 0xB3, 0xE2, 0x2D, 0x9F,
9059 0x00, 0x80, 0x00, 0xE8,
9060
9061 0x56, 0x31, 0x56, 0xBF,
9062 0x47, 0x39, 0x47, 0xBF,
9063
9064 0x4F, 0x39, 0x4F, 0xBF,
9065 0x57, 0x39, 0x57, 0xBF,
9066
9067 0x4E, 0x80, 0x07, 0xEA,
9068 0x24, 0x41, 0x20, 0xE9,
9069
9070 0x42, 0x73, 0xF8, 0xEC,
9071 0x00, 0xE0,
9072 0x2D, 0x73,
9073
9074 0x33, 0x72,
9075 0x0C, 0xE3,
9076 0xA5, 0x2F, 0x1E, 0xBD,
9077
9078 0x43, 0x43, 0x2D, 0xDF,
9079 0x4B, 0x4B, 0x2D, 0xDF,
9080
9081 0xAE, 0x1E, 0x26, 0xBD,
9082 0x58, 0xE3,
9083 0x33, 0x66,
9084
9085 0x53, 0x53, 0x2D, 0xDF,
9086 0x00, 0x80, 0x00, 0xE8,
9087
9088 0xB8, 0x38, 0x33, 0xBF,
9089 0x00, 0xE0,
9090 0x59, 0xE3,
9091
9092 0x1E, 0x12, 0x41, 0xE9,
9093 0x1A, 0x22, 0x41, 0xE9,
9094
9095 0x2B, 0x40, 0x3D, 0xE9,
9096 0x3F, 0x4B, 0xA0, 0xE8,
9097
9098 0x2D, 0x73,
9099 0x30, 0x76,
9100 0x05, 0x80, 0x3D, 0xEA,
9101
9102 0x37, 0x43, 0xA0, 0xE8,
9103 0x3D, 0x53, 0xA0, 0xE8,
9104
9105 0x48, 0x70, 0xF8, 0xEC,
9106 0x2B, 0x48, 0x3C, 0xE9,
9107
9108 0x1F, 0x27, 0xBC, 0xE8,
9109 0x00, 0x80, 0x00, 0xE8,
9110
9111 0x00, 0x80, 0x00, 0xE8,
9112 0x00, 0x80, 0x00, 0xE8,
9113
9114 0x15, 0xC0, 0x20, 0xE9,
9115 0x15, 0xC0, 0x20, 0xE9,
9116
9117 0x15, 0xC0, 0x20, 0xE9,
9118 0x15, 0xC0, 0x20, 0xE9,
9119
9120 0x18, 0x3A, 0x41, 0xE9,
9121 0x1D, 0x32, 0x41, 0xE9,
9122
9123 0x2A, 0x40, 0x20, 0xE9,
9124 0x56, 0x3D, 0x56, 0xDF,
9125
9126 0x46, 0x37, 0x46, 0xDF,
9127 0x4E, 0x3F, 0x4E, 0xDF,
9128
9129 0x16, 0x30, 0x20, 0xE9,
9130 0x4F, 0x3F, 0x4F, 0xDF,
9131
9132 0x32, 0x32, 0x2D, 0xDF,
9133 0x22, 0x22, 0x2D, 0xDF,
9134
9135 0x12, 0x12, 0x2D, 0xDF,
9136 0x3A, 0x3A, 0x2D, 0xDF,
9137
9138 0x47, 0x37, 0x47, 0xDF,
9139 0x57, 0x3D, 0x57, 0xDF,
9140
9141 0x3D, 0xCF, 0x74, 0xC0,
9142 0x37, 0xCF, 0x74, 0xC4,
9143
9144 0x31, 0x53, 0x2F, 0x9F,
9145 0x34, 0x80, 0x20, 0xE9,
9146
9147 0x39, 0xE5, 0x2C, 0x9F,
9148 0x3C, 0x3D, 0x20, 0xE9,
9149
9150 0x27, 0xCF, 0x74, 0xC6,
9151 0x3D, 0xCF, 0x74, 0xC2,
9152
9153 0x0A, 0x44, 0x4C, 0xB0,
9154 0x02, 0x44, 0x54, 0xB0,
9155
9156 0x2A, 0x44, 0x4C, 0xB2,
9157 0x1A, 0x44, 0x54, 0xB2,
9158
9159 0x20, 0x80, 0x3A, 0xEA,
9160 0x0A, 0x20,
9161 0x02, 0x20,
9162
9163 0x88, 0x73, 0x5E, 0xE9,
9164 0x2A, 0x20,
9165 0x1A, 0x20,
9166
9167 0x30, 0x50, 0x2E, 0x9F,
9168 0x32, 0x31, 0x5F, 0xE9,
9169
9170 0x38, 0x21, 0x2C, 0x9F,
9171 0x33, 0x39, 0x5F, 0xE9,
9172
9173 0x31, 0x53, 0x2F, 0x9F,
9174 0x9C, 0x27, 0x20, 0xE9,
9175
9176 0x0A, 0x44, 0x4C, 0xB4,
9177 0x02, 0x44, 0x54, 0xB4,
9178
9179 0x2A, 0x44, 0x4C, 0xB6,
9180 0x1A, 0x44, 0x54, 0xB6,
9181
9182 0x39, 0xE5, 0x2C, 0x9F,
9183 0x38, 0x3D, 0x20, 0xE9,
9184
9185 0x0A, 0x20,
9186 0x02, 0x20,
9187 0x2A, 0x20,
9188 0x1A, 0x20,
9189
9190 0x0A, 0x47, 0x4F, 0xBF,
9191 0x02, 0x47, 0x57, 0xBF,
9192
9193 0x30, 0x50, 0x2E, 0x9F,
9194 0x3E, 0x30, 0x4F, 0xE9,
9195
9196 0x38, 0x21, 0x2C, 0x9F,
9197 0x3F, 0x38, 0x4F, 0xE9,
9198
9199 0x2A, 0x46, 0x4E, 0xBF,
9200 0x1A, 0x46, 0x56, 0xBF,
9201
9202 0x31, 0x53, 0x2F, 0x9F,
9203 0x3A, 0x31, 0x4F, 0xE9,
9204
9205 0x39, 0xE5, 0x2C, 0x9F,
9206 0x3B, 0x39, 0x4F, 0xE9,
9207
9208 0x31, 0x53, 0x2F, 0x9F,
9209 0x36, 0x30, 0x4F, 0xE9,
9210
9211 0x39, 0xE5, 0x2C, 0x9F,
9212 0x37, 0x38, 0x4F, 0xE9,
9213
9214 0x2A, 0x43, 0x4B, 0xBF,
9215 0x1A, 0x43, 0x53, 0xBF,
9216
9217 0x30, 0x50, 0x2E, 0x9F,
9218 0x9D, 0x31, 0x4F, 0xE9,
9219
9220 0x38, 0x21, 0x2C, 0x9F,
9221 0x9E, 0x39, 0x4F, 0xE9,
9222
9223 0x31, 0x53, 0x2F, 0x9F,
9224 0x80, 0x31, 0x57, 0xE9,
9225
9226 0x39, 0xE5, 0x2C, 0x9F,
9227 0x81, 0x39, 0x57, 0xE9,
9228
9229 0x37, 0x48, 0x50, 0xBD,
9230 0x8A, 0x36, 0x20, 0xE9,
9231
9232 0x86, 0x76, 0x57, 0xE9,
9233 0x8B, 0x3E, 0x20, 0xE9,
9234
9235 0x82, 0x30, 0x57, 0xE9,
9236 0x87, 0x77, 0x57, 0xE9,
9237
9238 0x83, 0x38, 0x57, 0xE9,
9239 0x35, 0x49, 0x51, 0xBD,
9240
9241 0x84, 0x31, 0x5E, 0xE9,
9242 0x30, 0x1F, 0x5F, 0xE9,
9243
9244 0x85, 0x39, 0x5E, 0xE9,
9245 0x57, 0x25, 0x20, 0xE9,
9246
9247 0x2B, 0x48, 0x20, 0xE9,
9248 0x1D, 0x37, 0xE1, 0xEA,
9249
9250 0x1E, 0x35, 0xE1, 0xEA,
9251 0x00, 0xE0,
9252 0x26, 0x77,
9253
9254 0x24, 0x49, 0x20, 0xE9,
9255 0xAB, 0xFF, 0x20, 0xEA,
9256
9257 0x16, 0x26, 0x20, 0xE9,
9258 0x57, 0x2E, 0xBF, 0xEA,
9259
9260 0x1C, 0x46, 0xA0, 0xE8,
9261 0x23, 0x4E, 0xA0, 0xE8,
9262
9263 0x2B, 0x56, 0xA0, 0xE8,
9264 0x1D, 0x47, 0xA0, 0xE8,
9265
9266 0x24, 0x4F, 0xA0, 0xE8,
9267 0x2C, 0x57, 0xA0, 0xE8,
9268
9269 0x1C, 0x00,
9270 0x23, 0x00,
9271 0x2B, 0x00,
9272 0x00, 0xE0,
9273
9274 0x1D, 0x00,
9275 0x24, 0x00,
9276 0x2C, 0x00,
9277 0x00, 0xE0,
9278
9279 0x1C, 0x65,
9280 0x23, 0x65,
9281 0x2B, 0x65,
9282 0x00, 0xE0,
9283
9284 0x1D, 0x65,
9285 0x24, 0x65,
9286 0x2C, 0x65,
9287 0x00, 0xE0,
9288
9289 0x1C, 0x23, 0x60, 0xEC,
9290 0x36, 0xD7, 0x36, 0xAD,
9291
9292 0x2B, 0x80, 0x60, 0xEC,
9293 0x1D, 0x24, 0x60, 0xEC,
9294
9295 0x3E, 0xD7, 0x3E, 0xAD,
9296 0x2C, 0x80, 0x60, 0xEC,
9297
9298 0x1C, 0x2B, 0xDE, 0xE8,
9299 0x23, 0x80, 0xDE, 0xE8,
9300
9301 0x36, 0x80, 0x36, 0xBD,
9302 0x3E, 0x80, 0x3E, 0xBD,
9303
9304 0x33, 0xD7, 0x1C, 0xBD,
9305 0x3B, 0xD7, 0x23, 0xBD,
9306
9307 0x46, 0x80, 0x46, 0xCF,
9308 0x4F, 0x80, 0x4F, 0xCF,
9309
9310 0x56, 0x33, 0x56, 0xCF,
9311 0x47, 0x3B, 0x47, 0xCF,
9312
9313 0xD3, 0xFF, 0x20, 0xEA,
9314 0x00, 0x80, 0x00, 0xE8,
9315
9316 0x4E, 0x33, 0x4E, 0xCF,
9317 0x57, 0x3B, 0x57, 0xCF,
9318
9319 0x99, 0xFF, 0x20, 0xEA,
9320 0x57, 0xC0, 0xBF, 0xEA,
9321
9322 0x00, 0x80, 0xA0, 0xE9,
9323 0x00, 0x00, 0xD8, 0xEC,
9324
9325};
9326
9327static unsigned char warp_g400_tgzaf[] = {
9328
9329 0x00, 0x88, 0x98, 0xE9,
9330 0x00, 0x80, 0x00, 0xE8,
9331
9332 0x00, 0x80, 0xA0, 0xE9,
9333 0x00, 0x00, 0xD8, 0xEC,
9334
9335 0xFF, 0x80, 0xC0, 0xE9,
9336 0x00, 0x80, 0x00, 0xE8,
9337
9338 0x22, 0x40, 0x48, 0xBF,
9339 0x2A, 0x40, 0x50, 0xBF,
9340
9341 0x32, 0x41, 0x49, 0xBF,
9342 0x3A, 0x41, 0x51, 0xBF,
9343
9344 0xC3, 0x6B,
9345 0xCB, 0x6B,
9346 0x00, 0x88, 0x98, 0xE9,
9347
9348 0x73, 0x7B, 0xC8, 0xEC,
9349 0x96, 0xE2,
9350 0x41, 0x04,
9351
9352 0x7B, 0x43, 0xA0, 0xE8,
9353 0x73, 0x4B, 0xA0, 0xE8,
9354
9355 0xAD, 0xEE, 0x29, 0x9F,
9356 0x00, 0xE0,
9357 0x49, 0x04,
9358
9359 0x90, 0xE2,
9360 0x51, 0x04,
9361 0x31, 0x46, 0xB1, 0xE8,
9362
9363 0x49, 0x41, 0xC0, 0xEC,
9364 0x39, 0x57, 0xB1, 0xE8,
9365
9366 0x00, 0x04,
9367 0x46, 0xE2,
9368 0x73, 0x53, 0xA0, 0xE8,
9369
9370 0x51, 0x41, 0xC0, 0xEC,
9371 0x31, 0x00,
9372 0x39, 0x00,
9373
9374 0x61, 0x80, 0x15, 0xEA,
9375 0x08, 0x04,
9376 0x10, 0x04,
9377
9378 0x51, 0x49, 0xC0, 0xEC,
9379 0x2F, 0x41, 0x60, 0xEA,
9380
9381 0x31, 0x20,
9382 0x39, 0x20,
9383 0x1F, 0x42, 0xA0, 0xE8,
9384
9385 0x2A, 0x42, 0x4A, 0xBF,
9386 0x27, 0x4A, 0xA0, 0xE8,
9387
9388 0x1A, 0x42, 0x52, 0xBF,
9389 0x1E, 0x49, 0x60, 0xEA,
9390
9391 0x73, 0x7B, 0xC8, 0xEC,
9392 0x26, 0x51, 0x60, 0xEA,
9393
9394 0x32, 0x40, 0x48, 0xBD,
9395 0x22, 0x40, 0x50, 0xBD,
9396
9397 0x12, 0x41, 0x49, 0xBD,
9398 0x3A, 0x41, 0x51, 0xBD,
9399
9400 0xBF, 0x2F, 0x26, 0xBD,
9401 0x00, 0xE0,
9402 0x7B, 0x72,
9403
9404 0x32, 0x20,
9405 0x22, 0x20,
9406 0x12, 0x20,
9407 0x3A, 0x20,
9408
9409 0x46, 0x31, 0x46, 0xBF,
9410 0x4E, 0x31, 0x4E, 0xBF,
9411
9412 0xB3, 0xE2, 0x2D, 0x9F,
9413 0x00, 0x80, 0x00, 0xE8,
9414
9415 0x56, 0x31, 0x56, 0xBF,
9416 0x47, 0x39, 0x47, 0xBF,
9417
9418 0x4F, 0x39, 0x4F, 0xBF,
9419 0x57, 0x39, 0x57, 0xBF,
9420
9421 0x53, 0x80, 0x07, 0xEA,
9422 0x24, 0x41, 0x20, 0xE9,
9423
9424 0x42, 0x73, 0xF8, 0xEC,
9425 0x00, 0xE0,
9426 0x2D, 0x73,
9427
9428 0x33, 0x72,
9429 0x0C, 0xE3,
9430 0xA5, 0x2F, 0x1E, 0xBD,
9431
9432 0x43, 0x43, 0x2D, 0xDF,
9433 0x4B, 0x4B, 0x2D, 0xDF,
9434
9435 0xAE, 0x1E, 0x26, 0xBD,
9436 0x58, 0xE3,
9437 0x33, 0x66,
9438
9439 0x53, 0x53, 0x2D, 0xDF,
9440 0x00, 0x80, 0x00, 0xE8,
9441
9442 0xB8, 0x38, 0x33, 0xBF,
9443 0x00, 0xE0,
9444 0x59, 0xE3,
9445
9446 0x1E, 0x12, 0x41, 0xE9,
9447 0x1A, 0x22, 0x41, 0xE9,
9448
9449 0x2B, 0x40, 0x3D, 0xE9,
9450 0x3F, 0x4B, 0xA0, 0xE8,
9451
9452 0x2D, 0x73,
9453 0x30, 0x76,
9454 0x05, 0x80, 0x3D, 0xEA,
9455
9456 0x37, 0x43, 0xA0, 0xE8,
9457 0x3D, 0x53, 0xA0, 0xE8,
9458
9459 0x48, 0x70, 0xF8, 0xEC,
9460 0x2B, 0x48, 0x3C, 0xE9,
9461
9462 0x1F, 0x27, 0xBC, 0xE8,
9463 0x00, 0x80, 0x00, 0xE8,
9464
9465 0x00, 0x80, 0x00, 0xE8,
9466 0x00, 0x80, 0x00, 0xE8,
9467
9468 0x15, 0xC0, 0x20, 0xE9,
9469 0x15, 0xC0, 0x20, 0xE9,
9470
9471 0x15, 0xC0, 0x20, 0xE9,
9472 0x15, 0xC0, 0x20, 0xE9,
9473
9474 0x18, 0x3A, 0x41, 0xE9,
9475 0x1D, 0x32, 0x41, 0xE9,
9476
9477 0x2A, 0x40, 0x20, 0xE9,
9478 0x56, 0x3D, 0x56, 0xDF,
9479
9480 0x46, 0x37, 0x46, 0xDF,
9481 0x4E, 0x3F, 0x4E, 0xDF,
9482
9483 0x16, 0x30, 0x20, 0xE9,
9484 0x4F, 0x3F, 0x4F, 0xDF,
9485
9486 0x32, 0x32, 0x2D, 0xDF,
9487 0x22, 0x22, 0x2D, 0xDF,
9488
9489 0x12, 0x12, 0x2D, 0xDF,
9490 0x3A, 0x3A, 0x2D, 0xDF,
9491
9492 0x47, 0x37, 0x47, 0xDF,
9493 0x57, 0x3D, 0x57, 0xDF,
9494
9495 0x3D, 0xCF, 0x74, 0xC0,
9496 0x37, 0xCF, 0x74, 0xC4,
9497
9498 0x0A, 0x44, 0x4C, 0xB0,
9499 0x02, 0x44, 0x54, 0xB0,
9500
9501 0x31, 0x53, 0x2F, 0x9F,
9502 0x34, 0x37, 0x20, 0xE9,
9503
9504 0x39, 0xE5, 0x2C, 0x9F,
9505 0x3C, 0x3D, 0x20, 0xE9,
9506
9507 0x2A, 0x44, 0x4C, 0xB2,
9508 0x1A, 0x44, 0x54, 0xB2,
9509
9510 0x26, 0x80, 0x3A, 0xEA,
9511 0x0A, 0x20,
9512 0x02, 0x20,
9513
9514 0x88, 0x73, 0x5E, 0xE9,
9515 0x2A, 0x20,
9516 0x1A, 0x20,
9517
9518 0x3D, 0xCF, 0x74, 0xC2,
9519 0x27, 0xCF, 0x74, 0xC6,
9520
9521 0x30, 0x50, 0x2E, 0x9F,
9522 0x32, 0x31, 0x5F, 0xE9,
9523
9524 0x38, 0x21, 0x2C, 0x9F,
9525 0x33, 0x39, 0x5F, 0xE9,
9526
9527 0x31, 0x53, 0x2F, 0x9F,
9528 0x9C, 0x27, 0x20, 0xE9,
9529
9530 0x0A, 0x44, 0x4C, 0xB4,
9531 0x02, 0x44, 0x54, 0xB4,
9532
9533 0x2A, 0x44, 0x4C, 0xB6,
9534 0x1A, 0x44, 0x54, 0xB6,
9535
9536 0x39, 0xE5, 0x2C, 0x9F,
9537 0x38, 0x3D, 0x20, 0xE9,
9538
9539 0x0A, 0x20,
9540 0x02, 0x20,
9541 0x2A, 0x20,
9542 0x1A, 0x20,
9543
9544 0x3D, 0xCF, 0x75, 0xC6,
9545 0x00, 0x80, 0x00, 0xE8,
9546
9547 0x30, 0x50, 0x2E, 0x9F,
9548 0x3E, 0x30, 0x4F, 0xE9,
9549
9550 0x38, 0x21, 0x2C, 0x9F,
9551 0x3F, 0x38, 0x4F, 0xE9,
9552
9553 0x0A, 0x45, 0x4D, 0xB6,
9554 0x02, 0x45, 0x55, 0xB6,
9555
9556 0x31, 0x53, 0x2F, 0x9F,
9557 0x3A, 0x31, 0x4F, 0xE9,
9558
9559 0x39, 0xE5, 0x2C, 0x9F,
9560 0x3B, 0x39, 0x4F, 0xE9,
9561
9562 0x31, 0x3D, 0x20, 0xE9,
9563 0x0A, 0x20,
9564 0x02, 0x20,
9565
9566 0x2A, 0x46, 0x4E, 0xBF,
9567 0x1A, 0x46, 0x56, 0xBF,
9568
9569 0x0A, 0x47, 0x4F, 0xBF,
9570 0x02, 0x47, 0x57, 0xBF,
9571
9572 0x30, 0x50, 0x2E, 0x9F,
9573 0x36, 0x30, 0x4F, 0xE9,
9574
9575 0x38, 0x21, 0x2C, 0x9F,
9576 0x37, 0x38, 0x4F, 0xE9,
9577
9578 0x31, 0x53, 0x2F, 0x9F,
9579 0x9D, 0x31, 0x4F, 0xE9,
9580
9581 0x39, 0xE5, 0x2C, 0x9F,
9582 0x9E, 0x39, 0x4F, 0xE9,
9583
9584 0x2A, 0x43, 0x4B, 0xBF,
9585 0x1A, 0x43, 0x53, 0xBF,
9586
9587 0x30, 0x50, 0x2E, 0x9F,
9588 0x35, 0x30, 0x4F, 0xE9,
9589
9590 0x38, 0x21, 0x2C, 0x9F,
9591 0x39, 0x38, 0x4F, 0xE9,
9592
9593 0x31, 0x53, 0x2F, 0x9F,
9594 0x80, 0x31, 0x57, 0xE9,
9595
9596 0x39, 0xE5, 0x2C, 0x9F,
9597 0x81, 0x39, 0x57, 0xE9,
9598
9599 0x37, 0x48, 0x50, 0xBD,
9600 0x8A, 0x36, 0x20, 0xE9,
9601
9602 0x86, 0x76, 0x57, 0xE9,
9603 0x8B, 0x3E, 0x20, 0xE9,
9604
9605 0x82, 0x30, 0x57, 0xE9,
9606 0x87, 0x77, 0x57, 0xE9,
9607
9608 0x83, 0x38, 0x57, 0xE9,
9609 0x35, 0x49, 0x51, 0xBD,
9610
9611 0x84, 0x31, 0x5E, 0xE9,
9612 0x30, 0x1F, 0x5F, 0xE9,
9613
9614 0x85, 0x39, 0x5E, 0xE9,
9615 0x57, 0x25, 0x20, 0xE9,
9616
9617 0x2B, 0x48, 0x20, 0xE9,
9618 0x1D, 0x37, 0xE1, 0xEA,
9619
9620 0x1E, 0x35, 0xE1, 0xEA,
9621 0x00, 0xE0,
9622 0x26, 0x77,
9623
9624 0x24, 0x49, 0x20, 0xE9,
9625 0xA6, 0xFF, 0x20, 0xEA,
9626
9627 0x16, 0x26, 0x20, 0xE9,
9628 0x57, 0x2E, 0xBF, 0xEA,
9629
9630 0x1C, 0x46, 0xA0, 0xE8,
9631 0x23, 0x4E, 0xA0, 0xE8,
9632
9633 0x2B, 0x56, 0xA0, 0xE8,
9634 0x1D, 0x47, 0xA0, 0xE8,
9635
9636 0x24, 0x4F, 0xA0, 0xE8,
9637 0x2C, 0x57, 0xA0, 0xE8,
9638
9639 0x1C, 0x00,
9640 0x23, 0x00,
9641 0x2B, 0x00,
9642 0x00, 0xE0,
9643
9644 0x1D, 0x00,
9645 0x24, 0x00,
9646 0x2C, 0x00,
9647 0x00, 0xE0,
9648
9649 0x1C, 0x65,
9650 0x23, 0x65,
9651 0x2B, 0x65,
9652 0x00, 0xE0,
9653
9654 0x1D, 0x65,
9655 0x24, 0x65,
9656 0x2C, 0x65,
9657 0x00, 0xE0,
9658
9659 0x1C, 0x23, 0x60, 0xEC,
9660 0x36, 0xD7, 0x36, 0xAD,
9661
9662 0x2B, 0x80, 0x60, 0xEC,
9663 0x1D, 0x24, 0x60, 0xEC,
9664
9665 0x3E, 0xD7, 0x3E, 0xAD,
9666 0x2C, 0x80, 0x60, 0xEC,
9667
9668 0x1C, 0x2B, 0xDE, 0xE8,
9669 0x23, 0x80, 0xDE, 0xE8,
9670
9671 0x36, 0x80, 0x36, 0xBD,
9672 0x3E, 0x80, 0x3E, 0xBD,
9673
9674 0x33, 0xD7, 0x1C, 0xBD,
9675 0x3B, 0xD7, 0x23, 0xBD,
9676
9677 0x46, 0x80, 0x46, 0xCF,
9678 0x4F, 0x80, 0x4F, 0xCF,
9679
9680 0x56, 0x33, 0x56, 0xCF,
9681 0x47, 0x3B, 0x47, 0xCF,
9682
9683 0xCD, 0xFF, 0x20, 0xEA,
9684 0x00, 0x80, 0x00, 0xE8,
9685
9686 0x4E, 0x33, 0x4E, 0xCF,
9687 0x57, 0x3B, 0x57, 0xCF,
9688
9689 0x94, 0xFF, 0x20, 0xEA,
9690 0x57, 0xC0, 0xBF, 0xEA,
9691
9692 0x00, 0x80, 0xA0, 0xE9,
9693 0x00, 0x00, 0xD8, 0xEC,
9694
9695};
9696
9697static unsigned char warp_g400_tgzf[] = {
9698
9699 0x00, 0x88, 0x98, 0xE9,
9700 0x00, 0x80, 0x00, 0xE8,
9701
9702 0x00, 0x80, 0xA0, 0xE9,
9703 0x00, 0x00, 0xD8, 0xEC,
9704
9705 0xFF, 0x80, 0xC0, 0xE9,
9706 0x00, 0x80, 0x00, 0xE8,
9707
9708 0x22, 0x40, 0x48, 0xBF,
9709 0x2A, 0x40, 0x50, 0xBF,
9710
9711 0x32, 0x41, 0x49, 0xBF,
9712 0x3A, 0x41, 0x51, 0xBF,
9713
9714 0xC3, 0x6B,
9715 0xCB, 0x6B,
9716 0x00, 0x88, 0x98, 0xE9,
9717
9718 0x73, 0x7B, 0xC8, 0xEC,
9719 0x96, 0xE2,
9720 0x41, 0x04,
9721
9722 0x7B, 0x43, 0xA0, 0xE8,
9723 0x73, 0x4B, 0xA0, 0xE8,
9724
9725 0xAD, 0xEE, 0x29, 0x9F,
9726 0x00, 0xE0,
9727 0x49, 0x04,
9728
9729 0x90, 0xE2,
9730 0x51, 0x04,
9731 0x31, 0x46, 0xB1, 0xE8,
9732
9733 0x49, 0x41, 0xC0, 0xEC,
9734 0x39, 0x57, 0xB1, 0xE8,
9735
9736 0x00, 0x04,
9737 0x46, 0xE2,
9738 0x73, 0x53, 0xA0, 0xE8,
9739
9740 0x51, 0x41, 0xC0, 0xEC,
9741 0x31, 0x00,
9742 0x39, 0x00,
9743
9744 0x5D, 0x80, 0x15, 0xEA,
9745 0x08, 0x04,
9746 0x10, 0x04,
9747
9748 0x51, 0x49, 0xC0, 0xEC,
9749 0x2F, 0x41, 0x60, 0xEA,
9750
9751 0x31, 0x20,
9752 0x39, 0x20,
9753 0x1F, 0x42, 0xA0, 0xE8,
9754
9755 0x2A, 0x42, 0x4A, 0xBF,
9756 0x27, 0x4A, 0xA0, 0xE8,
9757
9758 0x1A, 0x42, 0x52, 0xBF,
9759 0x1E, 0x49, 0x60, 0xEA,
9760
9761 0x73, 0x7B, 0xC8, 0xEC,
9762 0x26, 0x51, 0x60, 0xEA,
9763
9764 0x32, 0x40, 0x48, 0xBD,
9765 0x22, 0x40, 0x50, 0xBD,
9766
9767 0x12, 0x41, 0x49, 0xBD,
9768 0x3A, 0x41, 0x51, 0xBD,
9769
9770 0xBF, 0x2F, 0x26, 0xBD,
9771 0x00, 0xE0,
9772 0x7B, 0x72,
9773
9774 0x32, 0x20,
9775 0x22, 0x20,
9776 0x12, 0x20,
9777 0x3A, 0x20,
9778
9779 0x46, 0x31, 0x46, 0xBF,
9780 0x4E, 0x31, 0x4E, 0xBF,
9781
9782 0xB3, 0xE2, 0x2D, 0x9F,
9783 0x00, 0x80, 0x00, 0xE8,
9784
9785 0x56, 0x31, 0x56, 0xBF,
9786 0x47, 0x39, 0x47, 0xBF,
9787
9788 0x4F, 0x39, 0x4F, 0xBF,
9789 0x57, 0x39, 0x57, 0xBF,
9790
9791 0x4F, 0x80, 0x07, 0xEA,
9792 0x24, 0x41, 0x20, 0xE9,
9793
9794 0x42, 0x73, 0xF8, 0xEC,
9795 0x00, 0xE0,
9796 0x2D, 0x73,
9797
9798 0x33, 0x72,
9799 0x0C, 0xE3,
9800 0xA5, 0x2F, 0x1E, 0xBD,
9801
9802 0x43, 0x43, 0x2D, 0xDF,
9803 0x4B, 0x4B, 0x2D, 0xDF,
9804
9805 0xAE, 0x1E, 0x26, 0xBD,
9806 0x58, 0xE3,
9807 0x33, 0x66,
9808
9809 0x53, 0x53, 0x2D, 0xDF,
9810 0x00, 0x80, 0x00, 0xE8,
9811
9812 0xB8, 0x38, 0x33, 0xBF,
9813 0x00, 0xE0,
9814 0x59, 0xE3,
9815
9816 0x1E, 0x12, 0x41, 0xE9,
9817 0x1A, 0x22, 0x41, 0xE9,
9818
9819 0x2B, 0x40, 0x3D, 0xE9,
9820 0x3F, 0x4B, 0xA0, 0xE8,
9821
9822 0x2D, 0x73,
9823 0x30, 0x76,
9824 0x05, 0x80, 0x3D, 0xEA,
9825
9826 0x37, 0x43, 0xA0, 0xE8,
9827 0x3D, 0x53, 0xA0, 0xE8,
9828
9829 0x48, 0x70, 0xF8, 0xEC,
9830 0x2B, 0x48, 0x3C, 0xE9,
9831
9832 0x1F, 0x27, 0xBC, 0xE8,
9833 0x00, 0x80, 0x00, 0xE8,
9834
9835 0x00, 0x80, 0x00, 0xE8,
9836 0x00, 0x80, 0x00, 0xE8,
9837
9838 0x15, 0xC0, 0x20, 0xE9,
9839 0x15, 0xC0, 0x20, 0xE9,
9840
9841 0x15, 0xC0, 0x20, 0xE9,
9842 0x15, 0xC0, 0x20, 0xE9,
9843
9844 0x18, 0x3A, 0x41, 0xE9,
9845 0x1D, 0x32, 0x41, 0xE9,
9846
9847 0x2A, 0x40, 0x20, 0xE9,
9848 0x56, 0x3D, 0x56, 0xDF,
9849
9850 0x46, 0x37, 0x46, 0xDF,
9851 0x4E, 0x3F, 0x4E, 0xDF,
9852
9853 0x16, 0x30, 0x20, 0xE9,
9854 0x4F, 0x3F, 0x4F, 0xDF,
9855
9856 0x32, 0x32, 0x2D, 0xDF,
9857 0x22, 0x22, 0x2D, 0xDF,
9858
9859 0x12, 0x12, 0x2D, 0xDF,
9860 0x3A, 0x3A, 0x2D, 0xDF,
9861
9862 0x47, 0x37, 0x47, 0xDF,
9863 0x57, 0x3D, 0x57, 0xDF,
9864
9865 0x3D, 0xCF, 0x74, 0xC0,
9866 0x37, 0xCF, 0x74, 0xC4,
9867
9868 0x39, 0xE5, 0x2C, 0x9F,
9869 0x34, 0x80, 0x20, 0xE9,
9870
9871 0x31, 0x53, 0x2F, 0x9F,
9872 0x00, 0x80, 0x00, 0xE8,
9873
9874 0x88, 0x73, 0x5E, 0xE9,
9875 0x00, 0x80, 0x00, 0xE8,
9876
9877 0x27, 0xCF, 0x75, 0xC6,
9878 0x3C, 0x3D, 0x20, 0xE9,
9879
9880 0x0A, 0x44, 0x4C, 0xB0,
9881 0x02, 0x44, 0x54, 0xB0,
9882
9883 0x2A, 0x44, 0x4C, 0xB2,
9884 0x1A, 0x44, 0x54, 0xB2,
9885
9886 0x20, 0x80, 0x3A, 0xEA,
9887 0x0A, 0x20,
9888 0x02, 0x20,
9889
9890 0x3D, 0xCF, 0x74, 0xC2,
9891 0x2A, 0x20,
9892 0x1A, 0x20,
9893
9894 0x30, 0x50, 0x2E, 0x9F,
9895 0x32, 0x31, 0x5F, 0xE9,
9896
9897 0x38, 0x21, 0x2C, 0x9F,
9898 0x33, 0x39, 0x5F, 0xE9,
9899
9900 0x31, 0x53, 0x2F, 0x9F,
9901 0x31, 0x27, 0x20, 0xE9,
9902
9903 0x0A, 0x44, 0x4C, 0xB4,
9904 0x02, 0x44, 0x54, 0xB4,
9905
9906 0x2A, 0x45, 0x4D, 0xB6,
9907 0x1A, 0x45, 0x55, 0xB6,
9908
9909 0x39, 0xE5, 0x2C, 0x9F,
9910 0x38, 0x3D, 0x20, 0xE9,
9911
9912 0x0A, 0x20,
9913 0x02, 0x20,
9914 0x2A, 0x20,
9915 0x1A, 0x20,
9916
9917 0x0A, 0x47, 0x4F, 0xBF,
9918 0x02, 0x47, 0x57, 0xBF,
9919
9920 0x30, 0x50, 0x2E, 0x9F,
9921 0x3E, 0x30, 0x4F, 0xE9,
9922
9923 0x38, 0x21, 0x2C, 0x9F,
9924 0x3F, 0x38, 0x4F, 0xE9,
9925
9926 0x2A, 0x46, 0x4E, 0xBF,
9927 0x1A, 0x46, 0x56, 0xBF,
9928
9929 0x31, 0x53, 0x2F, 0x9F,
9930 0x3A, 0x31, 0x4F, 0xE9,
9931
9932 0x39, 0xE5, 0x2C, 0x9F,
9933 0x3B, 0x39, 0x4F, 0xE9,
9934
9935 0x31, 0x53, 0x2F, 0x9F,
9936 0x36, 0x30, 0x4F, 0xE9,
9937
9938 0x39, 0xE5, 0x2C, 0x9F,
9939 0x37, 0x38, 0x4F, 0xE9,
9940
9941 0x2A, 0x43, 0x4B, 0xBF,
9942 0x1A, 0x43, 0x53, 0xBF,
9943
9944 0x30, 0x50, 0x2E, 0x9F,
9945 0x35, 0x31, 0x4F, 0xE9,
9946
9947 0x38, 0x21, 0x2C, 0x9F,
9948 0x39, 0x39, 0x4F, 0xE9,
9949
9950 0x31, 0x53, 0x2F, 0x9F,
9951 0x80, 0x31, 0x57, 0xE9,
9952
9953 0x39, 0xE5, 0x2C, 0x9F,
9954 0x81, 0x39, 0x57, 0xE9,
9955
9956 0x37, 0x48, 0x50, 0xBD,
9957 0x8A, 0x36, 0x20, 0xE9,
9958
9959 0x86, 0x76, 0x57, 0xE9,
9960 0x8B, 0x3E, 0x20, 0xE9,
9961
9962 0x82, 0x30, 0x57, 0xE9,
9963 0x87, 0x77, 0x57, 0xE9,
9964
9965 0x83, 0x38, 0x57, 0xE9,
9966 0x35, 0x49, 0x51, 0xBD,
9967
9968 0x84, 0x31, 0x5E, 0xE9,
9969 0x30, 0x1F, 0x5F, 0xE9,
9970
9971 0x85, 0x39, 0x5E, 0xE9,
9972 0x57, 0x25, 0x20, 0xE9,
9973
9974 0x2B, 0x48, 0x20, 0xE9,
9975 0x1D, 0x37, 0xE1, 0xEA,
9976
9977 0x1E, 0x35, 0xE1, 0xEA,
9978 0x00, 0xE0,
9979 0x26, 0x77,
9980
9981 0x24, 0x49, 0x20, 0xE9,
9982 0xAA, 0xFF, 0x20, 0xEA,
9983
9984 0x16, 0x26, 0x20, 0xE9,
9985 0x57, 0x2E, 0xBF, 0xEA,
9986
9987 0x1C, 0x46, 0xA0, 0xE8,
9988 0x23, 0x4E, 0xA0, 0xE8,
9989
9990 0x2B, 0x56, 0xA0, 0xE8,
9991 0x1D, 0x47, 0xA0, 0xE8,
9992
9993 0x24, 0x4F, 0xA0, 0xE8,
9994 0x2C, 0x57, 0xA0, 0xE8,
9995
9996 0x1C, 0x00,
9997 0x23, 0x00,
9998 0x2B, 0x00,
9999 0x00, 0xE0,
10000
10001 0x1D, 0x00,
10002 0x24, 0x00,
10003 0x2C, 0x00,
10004 0x00, 0xE0,
10005
10006 0x1C, 0x65,
10007 0x23, 0x65,
10008 0x2B, 0x65,
10009 0x00, 0xE0,
10010
10011 0x1D, 0x65,
10012 0x24, 0x65,
10013 0x2C, 0x65,
10014 0x00, 0xE0,
10015
10016 0x1C, 0x23, 0x60, 0xEC,
10017 0x36, 0xD7, 0x36, 0xAD,
10018
10019 0x2B, 0x80, 0x60, 0xEC,
10020 0x1D, 0x24, 0x60, 0xEC,
10021
10022 0x3E, 0xD7, 0x3E, 0xAD,
10023 0x2C, 0x80, 0x60, 0xEC,
10024
10025 0x1C, 0x2B, 0xDE, 0xE8,
10026 0x23, 0x80, 0xDE, 0xE8,
10027
10028 0x36, 0x80, 0x36, 0xBD,
10029 0x3E, 0x80, 0x3E, 0xBD,
10030
10031 0x33, 0xD7, 0x1C, 0xBD,
10032 0x3B, 0xD7, 0x23, 0xBD,
10033
10034 0x46, 0x80, 0x46, 0xCF,
10035 0x4F, 0x80, 0x4F, 0xCF,
10036
10037 0x56, 0x33, 0x56, 0xCF,
10038 0x47, 0x3B, 0x47, 0xCF,
10039
10040 0xD3, 0xFF, 0x20, 0xEA,
10041 0x00, 0x80, 0x00, 0xE8,
10042
10043 0x4E, 0x33, 0x4E, 0xCF,
10044 0x57, 0x3B, 0x57, 0xCF,
10045
10046 0x98, 0xFF, 0x20, 0xEA,
10047 0x57, 0xC0, 0xBF, 0xEA,
10048
10049 0x00, 0x80, 0xA0, 0xE9,
10050 0x00, 0x00, 0xD8, 0xEC,
10051
10052};
10053
10054static unsigned char warp_g400_tgzs[] = {
10055
10056 0x00, 0x88, 0x98, 0xE9,
10057 0x00, 0x80, 0x00, 0xE8,
10058
10059 0x00, 0x80, 0xA0, 0xE9,
10060 0x00, 0x00, 0xD8, 0xEC,
10061
10062 0xFF, 0x80, 0xC0, 0xE9,
10063 0x00, 0x80, 0x00, 0xE8,
10064
10065 0x22, 0x40, 0x48, 0xBF,
10066 0x2A, 0x40, 0x50, 0xBF,
10067
10068 0x32, 0x41, 0x49, 0xBF,
10069 0x3A, 0x41, 0x51, 0xBF,
10070
10071 0xC3, 0x6B,
10072 0xCB, 0x6B,
10073 0x00, 0x88, 0x98, 0xE9,
10074
10075 0x73, 0x7B, 0xC8, 0xEC,
10076 0x96, 0xE2,
10077 0x41, 0x04,
10078
10079 0x7B, 0x43, 0xA0, 0xE8,
10080 0x73, 0x4B, 0xA0, 0xE8,
10081
10082 0xAD, 0xEE, 0x29, 0x9F,
10083 0x00, 0xE0,
10084 0x49, 0x04,
10085
10086 0x90, 0xE2,
10087 0x51, 0x04,
10088 0x31, 0x46, 0xB1, 0xE8,
10089
10090 0x49, 0x41, 0xC0, 0xEC,
10091 0x39, 0x57, 0xB1, 0xE8,
10092
10093 0x00, 0x04,
10094 0x46, 0xE2,
10095 0x73, 0x53, 0xA0, 0xE8,
10096
10097 0x51, 0x41, 0xC0, 0xEC,
10098 0x31, 0x00,
10099 0x39, 0x00,
10100
10101 0x65, 0x80, 0x15, 0xEA,
10102 0x08, 0x04,
10103 0x10, 0x04,
10104
10105 0x51, 0x49, 0xC0, 0xEC,
10106 0x2F, 0x41, 0x60, 0xEA,
10107
10108 0x31, 0x20,
10109 0x39, 0x20,
10110 0x1F, 0x42, 0xA0, 0xE8,
10111
10112 0x2A, 0x42, 0x4A, 0xBF,
10113 0x27, 0x4A, 0xA0, 0xE8,
10114
10115 0x1A, 0x42, 0x52, 0xBF,
10116 0x1E, 0x49, 0x60, 0xEA,
10117
10118 0x73, 0x7B, 0xC8, 0xEC,
10119 0x26, 0x51, 0x60, 0xEA,
10120
10121 0x32, 0x40, 0x48, 0xBD,
10122 0x22, 0x40, 0x50, 0xBD,
10123
10124 0x12, 0x41, 0x49, 0xBD,
10125 0x3A, 0x41, 0x51, 0xBD,
10126
10127 0xBF, 0x2F, 0x26, 0xBD,
10128 0x00, 0xE0,
10129 0x7B, 0x72,
10130
10131 0x32, 0x20,
10132 0x22, 0x20,
10133 0x12, 0x20,
10134 0x3A, 0x20,
10135
10136 0x46, 0x31, 0x46, 0xBF,
10137 0x4E, 0x31, 0x4E, 0xBF,
10138
10139 0xB3, 0xE2, 0x2D, 0x9F,
10140 0x00, 0x80, 0x00, 0xE8,
10141
10142 0x56, 0x31, 0x56, 0xBF,
10143 0x47, 0x39, 0x47, 0xBF,
10144
10145 0x4F, 0x39, 0x4F, 0xBF,
10146 0x57, 0x39, 0x57, 0xBF,
10147
10148 0x57, 0x80, 0x07, 0xEA,
10149 0x24, 0x41, 0x20, 0xE9,
10150
10151 0x42, 0x73, 0xF8, 0xEC,
10152 0x00, 0xE0,
10153 0x2D, 0x73,
10154
10155 0x33, 0x72,
10156 0x0C, 0xE3,
10157 0xA5, 0x2F, 0x1E, 0xBD,
10158
10159 0x43, 0x43, 0x2D, 0xDF,
10160 0x4B, 0x4B, 0x2D, 0xDF,
10161
10162 0xAE, 0x1E, 0x26, 0xBD,
10163 0x58, 0xE3,
10164 0x33, 0x66,
10165
10166 0x53, 0x53, 0x2D, 0xDF,
10167 0x00, 0x80, 0x00, 0xE8,
10168
10169 0xB8, 0x38, 0x33, 0xBF,
10170 0x00, 0xE0,
10171 0x59, 0xE3,
10172
10173 0x1E, 0x12, 0x41, 0xE9,
10174 0x1A, 0x22, 0x41, 0xE9,
10175
10176 0x2B, 0x40, 0x3D, 0xE9,
10177 0x3F, 0x4B, 0xA0, 0xE8,
10178
10179 0x2D, 0x73,
10180 0x30, 0x76,
10181 0x05, 0x80, 0x3D, 0xEA,
10182
10183 0x37, 0x43, 0xA0, 0xE8,
10184 0x3D, 0x53, 0xA0, 0xE8,
10185
10186 0x48, 0x70, 0xF8, 0xEC,
10187 0x2B, 0x48, 0x3C, 0xE9,
10188
10189 0x1F, 0x27, 0xBC, 0xE8,
10190 0x00, 0x80, 0x00, 0xE8,
10191
10192 0x00, 0x80, 0x00, 0xE8,
10193 0x00, 0x80, 0x00, 0xE8,
10194
10195 0x15, 0xC0, 0x20, 0xE9,
10196 0x15, 0xC0, 0x20, 0xE9,
10197
10198 0x15, 0xC0, 0x20, 0xE9,
10199 0x15, 0xC0, 0x20, 0xE9,
10200
10201 0x18, 0x3A, 0x41, 0xE9,
10202 0x1D, 0x32, 0x41, 0xE9,
10203
10204 0x2A, 0x40, 0x20, 0xE9,
10205 0x56, 0x3D, 0x56, 0xDF,
10206
10207 0x46, 0x37, 0x46, 0xDF,
10208 0x4E, 0x3F, 0x4E, 0xDF,
10209
10210 0x16, 0x30, 0x20, 0xE9,
10211 0x4F, 0x3F, 0x4F, 0xDF,
10212
10213 0x47, 0x37, 0x47, 0xDF,
10214 0x57, 0x3D, 0x57, 0xDF,
10215
10216 0x32, 0x32, 0x2D, 0xDF,
10217 0x22, 0x22, 0x2D, 0xDF,
10218
10219 0x12, 0x12, 0x2D, 0xDF,
10220 0x3A, 0x3A, 0x2D, 0xDF,
10221
10222 0x27, 0xCF, 0x74, 0xC2,
10223 0x37, 0xCF, 0x74, 0xC4,
10224
10225 0x0A, 0x44, 0x4C, 0xB0,
10226 0x02, 0x44, 0x54, 0xB0,
10227
10228 0x3D, 0xCF, 0x74, 0xC0,
10229 0x34, 0x37, 0x20, 0xE9,
10230
10231 0x31, 0x53, 0x2F, 0x9F,
10232 0x38, 0x27, 0x20, 0xE9,
10233
10234 0x39, 0xE5, 0x2C, 0x9F,
10235 0x3C, 0x3D, 0x20, 0xE9,
10236
10237 0x2A, 0x44, 0x4C, 0xB2,
10238 0x1A, 0x44, 0x54, 0xB2,
10239
10240 0x29, 0x80, 0x3A, 0xEA,
10241 0x0A, 0x20,
10242 0x02, 0x20,
10243
10244 0x27, 0xCF, 0x75, 0xC0,
10245 0x2A, 0x20,
10246 0x1A, 0x20,
10247
10248 0x30, 0x50, 0x2E, 0x9F,
10249 0x32, 0x31, 0x5F, 0xE9,
10250
10251 0x38, 0x21, 0x2C, 0x9F,
10252 0x33, 0x39, 0x5F, 0xE9,
10253
10254 0x3D, 0xCF, 0x75, 0xC2,
10255 0x37, 0xCF, 0x75, 0xC4,
10256
10257 0x31, 0x53, 0x2F, 0x9F,
10258 0xA6, 0x27, 0x20, 0xE9,
10259
10260 0x39, 0xE5, 0x2C, 0x9F,
10261 0xA3, 0x3D, 0x20, 0xE9,
10262
10263 0x2A, 0x44, 0x4C, 0xB4,
10264 0x1A, 0x44, 0x54, 0xB4,
10265
10266 0x0A, 0x45, 0x4D, 0xB0,
10267 0x02, 0x45, 0x55, 0xB0,
10268
10269 0x88, 0x73, 0x5E, 0xE9,
10270 0x2A, 0x20,
10271 0x1A, 0x20,
10272
10273 0xA0, 0x37, 0x20, 0xE9,
10274 0x0A, 0x20,
10275 0x02, 0x20,
10276
10277 0x31, 0x53, 0x2F, 0x9F,
10278 0x3E, 0x30, 0x4F, 0xE9,
10279
10280 0x39, 0xE5, 0x2C, 0x9F,
10281 0x3F, 0x38, 0x4F, 0xE9,
10282
10283 0x30, 0x50, 0x2E, 0x9F,
10284 0x3A, 0x31, 0x4F, 0xE9,
10285
10286 0x2A, 0x45, 0x4D, 0xB2,
10287 0x1A, 0x45, 0x55, 0xB2,
10288
10289 0x0A, 0x45, 0x4D, 0xB4,
10290 0x02, 0x45, 0x55, 0xB4,
10291
10292 0x38, 0x21, 0x2C, 0x9F,
10293 0x3B, 0x39, 0x4F, 0xE9,
10294
10295 0x0A, 0x20,
10296 0x02, 0x20,
10297 0x2A, 0x20,
10298 0x1A, 0x20,
10299
10300 0x2A, 0x46, 0x4E, 0xBF,
10301 0x1A, 0x46, 0x56, 0xBF,
10302
10303 0x31, 0x53, 0x2F, 0x9F,
10304 0x36, 0x31, 0x4F, 0xE9,
10305
10306 0x39, 0xE5, 0x2C, 0x9F,
10307 0x37, 0x39, 0x4F, 0xE9,
10308
10309 0x30, 0x50, 0x2E, 0x9F,
10310 0xA7, 0x30, 0x4F, 0xE9,
10311
10312 0x38, 0x21, 0x2C, 0x9F,
10313 0xA8, 0x38, 0x4F, 0xE9,
10314
10315 0x0A, 0x47, 0x4F, 0xBF,
10316 0x02, 0x47, 0x57, 0xBF,
10317
10318 0x31, 0x53, 0x2F, 0x9F,
10319 0xA4, 0x31, 0x4F, 0xE9,
10320
10321 0x39, 0xE5, 0x2C, 0x9F,
10322 0xA5, 0x39, 0x4F, 0xE9,
10323
10324 0x2A, 0x43, 0x4B, 0xBF,
10325 0x1A, 0x43, 0x53, 0xBF,
10326
10327 0x30, 0x50, 0x2E, 0x9F,
10328 0xA1, 0x30, 0x4F, 0xE9,
10329
10330 0x38, 0x21, 0x2C, 0x9F,
10331 0xA2, 0x38, 0x4F, 0xE9,
10332
10333 0x31, 0x53, 0x2F, 0x9F,
10334 0x80, 0x31, 0x57, 0xE9,
10335
10336 0x39, 0xE5, 0x2C, 0x9F,
10337 0x81, 0x39, 0x57, 0xE9,
10338
10339 0x37, 0x48, 0x50, 0xBD,
10340 0x8A, 0x36, 0x20, 0xE9,
10341
10342 0x86, 0x76, 0x57, 0xE9,
10343 0x8B, 0x3E, 0x20, 0xE9,
10344
10345 0x82, 0x30, 0x57, 0xE9,
10346 0x87, 0x77, 0x57, 0xE9,
10347
10348 0x83, 0x38, 0x57, 0xE9,
10349 0x35, 0x49, 0x51, 0xBD,
10350
10351 0x84, 0x31, 0x5E, 0xE9,
10352 0x30, 0x1F, 0x5F, 0xE9,
10353
10354 0x85, 0x39, 0x5E, 0xE9,
10355 0x57, 0x25, 0x20, 0xE9,
10356
10357 0x2B, 0x48, 0x20, 0xE9,
10358 0x1D, 0x37, 0xE1, 0xEA,
10359
10360 0x1E, 0x35, 0xE1, 0xEA,
10361 0x00, 0xE0,
10362 0x26, 0x77,
10363
10364 0x24, 0x49, 0x20, 0xE9,
10365 0xA2, 0xFF, 0x20, 0xEA,
10366
10367 0x16, 0x26, 0x20, 0xE9,
10368 0x57, 0x2E, 0xBF, 0xEA,
10369
10370 0x1C, 0x46, 0xA0, 0xE8,
10371 0x23, 0x4E, 0xA0, 0xE8,
10372
10373 0x2B, 0x56, 0xA0, 0xE8,
10374 0x1D, 0x47, 0xA0, 0xE8,
10375
10376 0x24, 0x4F, 0xA0, 0xE8,
10377 0x2C, 0x57, 0xA0, 0xE8,
10378
10379 0x1C, 0x00,
10380 0x23, 0x00,
10381 0x2B, 0x00,
10382 0x00, 0xE0,
10383
10384 0x1D, 0x00,
10385 0x24, 0x00,
10386 0x2C, 0x00,
10387 0x00, 0xE0,
10388
10389 0x1C, 0x65,
10390 0x23, 0x65,
10391 0x2B, 0x65,
10392 0x00, 0xE0,
10393
10394 0x1D, 0x65,
10395 0x24, 0x65,
10396 0x2C, 0x65,
10397 0x00, 0xE0,
10398
10399 0x1C, 0x23, 0x60, 0xEC,
10400 0x36, 0xD7, 0x36, 0xAD,
10401
10402 0x2B, 0x80, 0x60, 0xEC,
10403 0x1D, 0x24, 0x60, 0xEC,
10404
10405 0x3E, 0xD7, 0x3E, 0xAD,
10406 0x2C, 0x80, 0x60, 0xEC,
10407
10408 0x1C, 0x2B, 0xDE, 0xE8,
10409 0x23, 0x80, 0xDE, 0xE8,
10410
10411 0x36, 0x80, 0x36, 0xBD,
10412 0x3E, 0x80, 0x3E, 0xBD,
10413
10414 0x33, 0xD7, 0x1C, 0xBD,
10415 0x3B, 0xD7, 0x23, 0xBD,
10416
10417 0x46, 0x80, 0x46, 0xCF,
10418 0x4F, 0x80, 0x4F, 0xCF,
10419
10420 0x56, 0x33, 0x56, 0xCF,
10421 0x47, 0x3B, 0x47, 0xCF,
10422
10423 0xCA, 0xFF, 0x20, 0xEA,
10424 0x00, 0x80, 0x00, 0xE8,
10425
10426 0x4E, 0x33, 0x4E, 0xCF,
10427 0x57, 0x3B, 0x57, 0xCF,
10428
10429 0x90, 0xFF, 0x20, 0xEA,
10430 0x57, 0xC0, 0xBF, 0xEA,
10431
10432 0x00, 0x80, 0xA0, 0xE9,
10433 0x00, 0x00, 0xD8, 0xEC,
10434
10435};
10436
10437static unsigned char warp_g400_tgzsa[] = {
10438
10439 0x00, 0x88, 0x98, 0xE9,
10440 0x00, 0x80, 0x00, 0xE8,
10441
10442 0x00, 0x80, 0xA0, 0xE9,
10443 0x00, 0x00, 0xD8, 0xEC,
10444
10445 0xFF, 0x80, 0xC0, 0xE9,
10446 0x00, 0x80, 0x00, 0xE8,
10447
10448 0x22, 0x40, 0x48, 0xBF,
10449 0x2A, 0x40, 0x50, 0xBF,
10450
10451 0x32, 0x41, 0x49, 0xBF,
10452 0x3A, 0x41, 0x51, 0xBF,
10453
10454 0xC3, 0x6B,
10455 0xCB, 0x6B,
10456 0x00, 0x88, 0x98, 0xE9,
10457
10458 0x73, 0x7B, 0xC8, 0xEC,
10459 0x96, 0xE2,
10460 0x41, 0x04,
10461
10462 0x7B, 0x43, 0xA0, 0xE8,
10463 0x73, 0x4B, 0xA0, 0xE8,
10464
10465 0xAD, 0xEE, 0x29, 0x9F,
10466 0x00, 0xE0,
10467 0x49, 0x04,
10468
10469 0x90, 0xE2,
10470 0x51, 0x04,
10471 0x31, 0x46, 0xB1, 0xE8,
10472
10473 0x49, 0x41, 0xC0, 0xEC,
10474 0x39, 0x57, 0xB1, 0xE8,
10475
10476 0x00, 0x04,
10477 0x46, 0xE2,
10478 0x73, 0x53, 0xA0, 0xE8,
10479
10480 0x51, 0x41, 0xC0, 0xEC,
10481 0x31, 0x00,
10482 0x39, 0x00,
10483
10484 0x6A, 0x80, 0x15, 0xEA,
10485 0x08, 0x04,
10486 0x10, 0x04,
10487
10488 0x51, 0x49, 0xC0, 0xEC,
10489 0x2F, 0x41, 0x60, 0xEA,
10490
10491 0x31, 0x20,
10492 0x39, 0x20,
10493 0x1F, 0x42, 0xA0, 0xE8,
10494
10495 0x2A, 0x42, 0x4A, 0xBF,
10496 0x27, 0x4A, 0xA0, 0xE8,
10497
10498 0x1A, 0x42, 0x52, 0xBF,
10499 0x1E, 0x49, 0x60, 0xEA,
10500
10501 0x73, 0x7B, 0xC8, 0xEC,
10502 0x26, 0x51, 0x60, 0xEA,
10503
10504 0x32, 0x40, 0x48, 0xBD,
10505 0x22, 0x40, 0x50, 0xBD,
10506
10507 0x12, 0x41, 0x49, 0xBD,
10508 0x3A, 0x41, 0x51, 0xBD,
10509
10510 0xBF, 0x2F, 0x26, 0xBD,
10511 0x00, 0xE0,
10512 0x7B, 0x72,
10513
10514 0x32, 0x20,
10515 0x22, 0x20,
10516 0x12, 0x20,
10517 0x3A, 0x20,
10518
10519 0x46, 0x31, 0x46, 0xBF,
10520 0x4E, 0x31, 0x4E, 0xBF,
10521
10522 0xB3, 0xE2, 0x2D, 0x9F,
10523 0x00, 0x80, 0x00, 0xE8,
10524
10525 0x56, 0x31, 0x56, 0xBF,
10526 0x47, 0x39, 0x47, 0xBF,
10527
10528 0x4F, 0x39, 0x4F, 0xBF,
10529 0x57, 0x39, 0x57, 0xBF,
10530
10531 0x5C, 0x80, 0x07, 0xEA,
10532 0x24, 0x41, 0x20, 0xE9,
10533
10534 0x42, 0x73, 0xF8, 0xEC,
10535 0x00, 0xE0,
10536 0x2D, 0x73,
10537
10538 0x33, 0x72,
10539 0x0C, 0xE3,
10540 0xA5, 0x2F, 0x1E, 0xBD,
10541
10542 0x43, 0x43, 0x2D, 0xDF,
10543 0x4B, 0x4B, 0x2D, 0xDF,
10544
10545 0xAE, 0x1E, 0x26, 0xBD,
10546 0x58, 0xE3,
10547 0x33, 0x66,
10548
10549 0x53, 0x53, 0x2D, 0xDF,
10550 0x00, 0x80, 0x00, 0xE8,
10551
10552 0xB8, 0x38, 0x33, 0xBF,
10553 0x00, 0xE0,
10554 0x59, 0xE3,
10555
10556 0x1E, 0x12, 0x41, 0xE9,
10557 0x1A, 0x22, 0x41, 0xE9,
10558
10559 0x2B, 0x40, 0x3D, 0xE9,
10560 0x3F, 0x4B, 0xA0, 0xE8,
10561
10562 0x2D, 0x73,
10563 0x30, 0x76,
10564 0x05, 0x80, 0x3D, 0xEA,
10565
10566 0x37, 0x43, 0xA0, 0xE8,
10567 0x3D, 0x53, 0xA0, 0xE8,
10568
10569 0x48, 0x70, 0xF8, 0xEC,
10570 0x2B, 0x48, 0x3C, 0xE9,
10571
10572 0x1F, 0x27, 0xBC, 0xE8,
10573 0x00, 0x80, 0x00, 0xE8,
10574
10575 0x00, 0x80, 0x00, 0xE8,
10576 0x00, 0x80, 0x00, 0xE8,
10577
10578 0x15, 0xC0, 0x20, 0xE9,
10579 0x15, 0xC0, 0x20, 0xE9,
10580
10581 0x15, 0xC0, 0x20, 0xE9,
10582 0x15, 0xC0, 0x20, 0xE9,
10583
10584 0x18, 0x3A, 0x41, 0xE9,
10585 0x1D, 0x32, 0x41, 0xE9,
10586
10587 0x2A, 0x40, 0x20, 0xE9,
10588 0x56, 0x3D, 0x56, 0xDF,
10589
10590 0x46, 0x37, 0x46, 0xDF,
10591 0x4E, 0x3F, 0x4E, 0xDF,
10592
10593 0x16, 0x30, 0x20, 0xE9,
10594 0x4F, 0x3F, 0x4F, 0xDF,
10595
10596 0x47, 0x37, 0x47, 0xDF,
10597 0x57, 0x3D, 0x57, 0xDF,
10598
10599 0x32, 0x32, 0x2D, 0xDF,
10600 0x22, 0x22, 0x2D, 0xDF,
10601
10602 0x12, 0x12, 0x2D, 0xDF,
10603 0x3A, 0x3A, 0x2D, 0xDF,
10604
10605 0x27, 0xCF, 0x74, 0xC2,
10606 0x37, 0xCF, 0x74, 0xC4,
10607
10608 0x0A, 0x44, 0x4C, 0xB0,
10609 0x02, 0x44, 0x54, 0xB0,
10610
10611 0x3D, 0xCF, 0x74, 0xC0,
10612 0x34, 0x37, 0x20, 0xE9,
10613
10614 0x31, 0x53, 0x2F, 0x9F,
10615 0x38, 0x27, 0x20, 0xE9,
10616
10617 0x39, 0xE5, 0x2C, 0x9F,
10618 0x3C, 0x3D, 0x20, 0xE9,
10619
10620 0x2A, 0x44, 0x4C, 0xB2,
10621 0x1A, 0x44, 0x54, 0xB2,
10622
10623 0x2E, 0x80, 0x3A, 0xEA,
10624 0x0A, 0x20,
10625 0x02, 0x20,
10626
10627 0x27, 0xCF, 0x75, 0xC0,
10628 0x2A, 0x20,
10629 0x1A, 0x20,
10630
10631 0x30, 0x50, 0x2E, 0x9F,
10632 0x32, 0x31, 0x5F, 0xE9,
10633
10634 0x38, 0x21, 0x2C, 0x9F,
10635 0x33, 0x39, 0x5F, 0xE9,
10636
10637 0x3D, 0xCF, 0x75, 0xC2,
10638 0x37, 0xCF, 0x75, 0xC4,
10639
10640 0x31, 0x53, 0x2F, 0x9F,
10641 0xA6, 0x27, 0x20, 0xE9,
10642
10643 0x39, 0xE5, 0x2C, 0x9F,
10644 0xA3, 0x3D, 0x20, 0xE9,
10645
10646 0x2A, 0x44, 0x4C, 0xB4,
10647 0x1A, 0x44, 0x54, 0xB4,
10648
10649 0x0A, 0x45, 0x4D, 0xB0,
10650 0x02, 0x45, 0x55, 0xB0,
10651
10652 0x88, 0x73, 0x5E, 0xE9,
10653 0x2A, 0x20,
10654 0x1A, 0x20,
10655
10656 0xA0, 0x37, 0x20, 0xE9,
10657 0x0A, 0x20,
10658 0x02, 0x20,
10659
10660 0x31, 0x53, 0x2F, 0x9F,
10661 0x3E, 0x30, 0x4F, 0xE9,
10662
10663 0x39, 0xE5, 0x2C, 0x9F,
10664 0x3F, 0x38, 0x4F, 0xE9,
10665
10666 0x30, 0x50, 0x2E, 0x9F,
10667 0x3A, 0x31, 0x4F, 0xE9,
10668
10669 0x38, 0x21, 0x2C, 0x9F,
10670 0x3B, 0x39, 0x4F, 0xE9,
10671
10672 0x2A, 0x45, 0x4D, 0xB2,
10673 0x1A, 0x45, 0x55, 0xB2,
10674
10675 0x0A, 0x45, 0x4D, 0xB4,
10676 0x02, 0x45, 0x55, 0xB4,
10677
10678 0x27, 0xCF, 0x74, 0xC6,
10679 0x2A, 0x20,
10680 0x1A, 0x20,
10681
10682 0xA7, 0x30, 0x4F, 0xE9,
10683 0x0A, 0x20,
10684 0x02, 0x20,
10685
10686 0x31, 0x53, 0x2F, 0x9F,
10687 0x9C, 0x27, 0x20, 0xE9,
10688
10689 0x39, 0xE5, 0x2C, 0x9F,
10690 0xA8, 0x38, 0x4F, 0xE9,
10691
10692 0x2A, 0x44, 0x4C, 0xB6,
10693 0x1A, 0x44, 0x54, 0xB6,
10694
10695 0x30, 0x50, 0x2E, 0x9F,
10696 0x36, 0x31, 0x4F, 0xE9,
10697
10698 0x38, 0x21, 0x2C, 0x9F,
10699 0x37, 0x39, 0x4F, 0xE9,
10700
10701 0x00, 0x80, 0x00, 0xE8,
10702 0x2A, 0x20,
10703 0x1A, 0x20,
10704
10705 0x2A, 0x46, 0x4E, 0xBF,
10706 0x1A, 0x46, 0x56, 0xBF,
10707
10708 0x31, 0x53, 0x2F, 0x9F,
10709 0xA4, 0x31, 0x4F, 0xE9,
10710
10711 0x39, 0xE5, 0x2C, 0x9F,
10712 0xA5, 0x39, 0x4F, 0xE9,
10713
10714 0x0A, 0x47, 0x4F, 0xBF,
10715 0x02, 0x47, 0x57, 0xBF,
10716
10717 0x31, 0x53, 0x2F, 0x9F,
10718 0xA1, 0x30, 0x4F, 0xE9,
10719
10720 0x39, 0xE5, 0x2C, 0x9F,
10721 0xA2, 0x38, 0x4F, 0xE9,
10722
10723 0x2A, 0x43, 0x4B, 0xBF,
10724 0x1A, 0x43, 0x53, 0xBF,
10725
10726 0x30, 0x50, 0x2E, 0x9F,
10727 0x9D, 0x31, 0x4F, 0xE9,
10728
10729 0x38, 0x21, 0x2C, 0x9F,
10730 0x9E, 0x39, 0x4F, 0xE9,
10731
10732 0x31, 0x53, 0x2F, 0x9F,
10733 0x80, 0x31, 0x57, 0xE9,
10734
10735 0x39, 0xE5, 0x2C, 0x9F,
10736 0x81, 0x39, 0x57, 0xE9,
10737
10738 0x37, 0x48, 0x50, 0xBD,
10739 0x8A, 0x36, 0x20, 0xE9,
10740
10741 0x86, 0x76, 0x57, 0xE9,
10742 0x8B, 0x3E, 0x20, 0xE9,
10743
10744 0x82, 0x30, 0x57, 0xE9,
10745 0x87, 0x77, 0x57, 0xE9,
10746
10747 0x83, 0x38, 0x57, 0xE9,
10748 0x35, 0x49, 0x51, 0xBD,
10749
10750 0x84, 0x31, 0x5E, 0xE9,
10751 0x30, 0x1F, 0x5F, 0xE9,
10752
10753 0x85, 0x39, 0x5E, 0xE9,
10754 0x57, 0x25, 0x20, 0xE9,
10755
10756 0x2B, 0x48, 0x20, 0xE9,
10757 0x1D, 0x37, 0xE1, 0xEA,
10758
10759 0x1E, 0x35, 0xE1, 0xEA,
10760 0x00, 0xE0,
10761 0x26, 0x77,
10762
10763 0x24, 0x49, 0x20, 0xE9,
10764 0x9D, 0xFF, 0x20, 0xEA,
10765
10766 0x16, 0x26, 0x20, 0xE9,
10767 0x57, 0x2E, 0xBF, 0xEA,
10768
10769 0x1C, 0x46, 0xA0, 0xE8,
10770 0x23, 0x4E, 0xA0, 0xE8,
10771
10772 0x2B, 0x56, 0xA0, 0xE8,
10773 0x1D, 0x47, 0xA0, 0xE8,
10774
10775 0x24, 0x4F, 0xA0, 0xE8,
10776 0x2C, 0x57, 0xA0, 0xE8,
10777
10778 0x1C, 0x00,
10779 0x23, 0x00,
10780 0x2B, 0x00,
10781 0x00, 0xE0,
10782
10783 0x1D, 0x00,
10784 0x24, 0x00,
10785 0x2C, 0x00,
10786 0x00, 0xE0,
10787
10788 0x1C, 0x65,
10789 0x23, 0x65,
10790 0x2B, 0x65,
10791 0x00, 0xE0,
10792
10793 0x1D, 0x65,
10794 0x24, 0x65,
10795 0x2C, 0x65,
10796 0x00, 0xE0,
10797
10798 0x1C, 0x23, 0x60, 0xEC,
10799 0x36, 0xD7, 0x36, 0xAD,
10800
10801 0x2B, 0x80, 0x60, 0xEC,
10802 0x1D, 0x24, 0x60, 0xEC,
10803
10804 0x3E, 0xD7, 0x3E, 0xAD,
10805 0x2C, 0x80, 0x60, 0xEC,
10806
10807 0x1C, 0x2B, 0xDE, 0xE8,
10808 0x23, 0x80, 0xDE, 0xE8,
10809
10810 0x36, 0x80, 0x36, 0xBD,
10811 0x3E, 0x80, 0x3E, 0xBD,
10812
10813 0x33, 0xD7, 0x1C, 0xBD,
10814 0x3B, 0xD7, 0x23, 0xBD,
10815
10816 0x46, 0x80, 0x46, 0xCF,
10817 0x4F, 0x80, 0x4F, 0xCF,
10818
10819 0x56, 0x33, 0x56, 0xCF,
10820 0x47, 0x3B, 0x47, 0xCF,
10821
10822 0xC5, 0xFF, 0x20, 0xEA,
10823 0x00, 0x80, 0x00, 0xE8,
10824
10825 0x4E, 0x33, 0x4E, 0xCF,
10826 0x57, 0x3B, 0x57, 0xCF,
10827
10828 0x8B, 0xFF, 0x20, 0xEA,
10829 0x57, 0xC0, 0xBF, 0xEA,
10830
10831 0x00, 0x80, 0xA0, 0xE9,
10832 0x00, 0x00, 0xD8, 0xEC,
10833
10834};
10835
10836static unsigned char warp_g400_tgzsaf[] = {
10837
10838 0x00, 0x88, 0x98, 0xE9,
10839 0x00, 0x80, 0x00, 0xE8,
10840
10841 0x00, 0x80, 0xA0, 0xE9,
10842 0x00, 0x00, 0xD8, 0xEC,
10843
10844 0xFF, 0x80, 0xC0, 0xE9,
10845 0x00, 0x80, 0x00, 0xE8,
10846
10847 0x22, 0x40, 0x48, 0xBF,
10848 0x2A, 0x40, 0x50, 0xBF,
10849
10850 0x32, 0x41, 0x49, 0xBF,
10851 0x3A, 0x41, 0x51, 0xBF,
10852
10853 0xC3, 0x6B,
10854 0xCB, 0x6B,
10855 0x00, 0x88, 0x98, 0xE9,
10856
10857 0x73, 0x7B, 0xC8, 0xEC,
10858 0x96, 0xE2,
10859 0x41, 0x04,
10860
10861 0x7B, 0x43, 0xA0, 0xE8,
10862 0x73, 0x4B, 0xA0, 0xE8,
10863
10864 0xAD, 0xEE, 0x29, 0x9F,
10865 0x00, 0xE0,
10866 0x49, 0x04,
10867
10868 0x90, 0xE2,
10869 0x51, 0x04,
10870 0x31, 0x46, 0xB1, 0xE8,
10871
10872 0x49, 0x41, 0xC0, 0xEC,
10873 0x39, 0x57, 0xB1, 0xE8,
10874
10875 0x00, 0x04,
10876 0x46, 0xE2,
10877 0x73, 0x53, 0xA0, 0xE8,
10878
10879 0x51, 0x41, 0xC0, 0xEC,
10880 0x31, 0x00,
10881 0x39, 0x00,
10882
10883 0x6E, 0x80, 0x15, 0xEA,
10884 0x08, 0x04,
10885 0x10, 0x04,
10886
10887 0x51, 0x49, 0xC0, 0xEC,
10888 0x2F, 0x41, 0x60, 0xEA,
10889
10890 0x31, 0x20,
10891 0x39, 0x20,
10892 0x1F, 0x42, 0xA0, 0xE8,
10893
10894 0x2A, 0x42, 0x4A, 0xBF,
10895 0x27, 0x4A, 0xA0, 0xE8,
10896
10897 0x1A, 0x42, 0x52, 0xBF,
10898 0x1E, 0x49, 0x60, 0xEA,
10899
10900 0x73, 0x7B, 0xC8, 0xEC,
10901 0x26, 0x51, 0x60, 0xEA,
10902
10903 0x32, 0x40, 0x48, 0xBD,
10904 0x22, 0x40, 0x50, 0xBD,
10905
10906 0x12, 0x41, 0x49, 0xBD,
10907 0x3A, 0x41, 0x51, 0xBD,
10908
10909 0xBF, 0x2F, 0x26, 0xBD,
10910 0x00, 0xE0,
10911 0x7B, 0x72,
10912
10913 0x32, 0x20,
10914 0x22, 0x20,
10915 0x12, 0x20,
10916 0x3A, 0x20,
10917
10918 0x46, 0x31, 0x46, 0xBF,
10919 0x4E, 0x31, 0x4E, 0xBF,
10920
10921 0xB3, 0xE2, 0x2D, 0x9F,
10922 0x00, 0x80, 0x00, 0xE8,
10923
10924 0x56, 0x31, 0x56, 0xBF,
10925 0x47, 0x39, 0x47, 0xBF,
10926
10927 0x4F, 0x39, 0x4F, 0xBF,
10928 0x57, 0x39, 0x57, 0xBF,
10929
10930 0x60, 0x80, 0x07, 0xEA,
10931 0x24, 0x41, 0x20, 0xE9,
10932
10933 0x42, 0x73, 0xF8, 0xEC,
10934 0x00, 0xE0,
10935 0x2D, 0x73,
10936
10937 0x33, 0x72,
10938 0x0C, 0xE3,
10939 0xA5, 0x2F, 0x1E, 0xBD,
10940
10941 0x43, 0x43, 0x2D, 0xDF,
10942 0x4B, 0x4B, 0x2D, 0xDF,
10943
10944 0xAE, 0x1E, 0x26, 0xBD,
10945 0x58, 0xE3,
10946 0x33, 0x66,
10947
10948 0x53, 0x53, 0x2D, 0xDF,
10949 0x00, 0x80, 0x00, 0xE8,
10950
10951 0xB8, 0x38, 0x33, 0xBF,
10952 0x00, 0xE0,
10953 0x59, 0xE3,
10954
10955 0x1E, 0x12, 0x41, 0xE9,
10956 0x1A, 0x22, 0x41, 0xE9,
10957
10958 0x2B, 0x40, 0x3D, 0xE9,
10959 0x3F, 0x4B, 0xA0, 0xE8,
10960
10961 0x2D, 0x73,
10962 0x30, 0x76,
10963 0x05, 0x80, 0x3D, 0xEA,
10964
10965 0x37, 0x43, 0xA0, 0xE8,
10966 0x3D, 0x53, 0xA0, 0xE8,
10967
10968 0x48, 0x70, 0xF8, 0xEC,
10969 0x2B, 0x48, 0x3C, 0xE9,
10970
10971 0x1F, 0x27, 0xBC, 0xE8,
10972 0x00, 0x80, 0x00, 0xE8,
10973
10974 0x00, 0x80, 0x00, 0xE8,
10975 0x00, 0x80, 0x00, 0xE8,
10976
10977 0x15, 0xC0, 0x20, 0xE9,
10978 0x15, 0xC0, 0x20, 0xE9,
10979
10980 0x15, 0xC0, 0x20, 0xE9,
10981 0x15, 0xC0, 0x20, 0xE9,
10982
10983 0x18, 0x3A, 0x41, 0xE9,
10984 0x1D, 0x32, 0x41, 0xE9,
10985
10986 0x2A, 0x40, 0x20, 0xE9,
10987 0x56, 0x3D, 0x56, 0xDF,
10988
10989 0x46, 0x37, 0x46, 0xDF,
10990 0x4E, 0x3F, 0x4E, 0xDF,
10991
10992 0x16, 0x30, 0x20, 0xE9,
10993 0x4F, 0x3F, 0x4F, 0xDF,
10994
10995 0x47, 0x37, 0x47, 0xDF,
10996 0x57, 0x3D, 0x57, 0xDF,
10997
10998 0x32, 0x32, 0x2D, 0xDF,
10999 0x22, 0x22, 0x2D, 0xDF,
11000
11001 0x12, 0x12, 0x2D, 0xDF,
11002 0x3A, 0x3A, 0x2D, 0xDF,
11003
11004 0x27, 0xCF, 0x74, 0xC2,
11005 0x37, 0xCF, 0x74, 0xC4,
11006
11007 0x0A, 0x44, 0x4C, 0xB0,
11008 0x02, 0x44, 0x54, 0xB0,
11009
11010 0x3D, 0xCF, 0x74, 0xC0,
11011 0x34, 0x37, 0x20, 0xE9,
11012
11013 0x31, 0x53, 0x2F, 0x9F,
11014 0x38, 0x27, 0x20, 0xE9,
11015
11016 0x39, 0xE5, 0x2C, 0x9F,
11017 0x3C, 0x3D, 0x20, 0xE9,
11018
11019 0x2A, 0x44, 0x4C, 0xB2,
11020 0x1A, 0x44, 0x54, 0xB2,
11021
11022 0x32, 0x80, 0x3A, 0xEA,
11023 0x0A, 0x20,
11024 0x02, 0x20,
11025
11026 0x27, 0xCF, 0x75, 0xC0,
11027 0x2A, 0x20,
11028 0x1A, 0x20,
11029
11030 0x30, 0x50, 0x2E, 0x9F,
11031 0x32, 0x31, 0x5F, 0xE9,
11032
11033 0x38, 0x21, 0x2C, 0x9F,
11034 0x33, 0x39, 0x5F, 0xE9,
11035
11036 0x3D, 0xCF, 0x75, 0xC2,
11037 0x37, 0xCF, 0x75, 0xC4,
11038
11039 0x31, 0x53, 0x2F, 0x9F,
11040 0xA6, 0x27, 0x20, 0xE9,
11041
11042 0x39, 0xE5, 0x2C, 0x9F,
11043 0xA3, 0x3D, 0x20, 0xE9,
11044
11045 0x2A, 0x44, 0x4C, 0xB4,
11046 0x1A, 0x44, 0x54, 0xB4,
11047
11048 0x0A, 0x45, 0x4D, 0xB0,
11049 0x02, 0x45, 0x55, 0xB0,
11050
11051 0x88, 0x73, 0x5E, 0xE9,
11052 0x2A, 0x20,
11053 0x1A, 0x20,
11054
11055 0xA0, 0x37, 0x20, 0xE9,
11056 0x0A, 0x20,
11057 0x02, 0x20,
11058
11059 0x31, 0x53, 0x2F, 0x9F,
11060 0x3E, 0x30, 0x4F, 0xE9,
11061
11062 0x39, 0xE5, 0x2C, 0x9F,
11063 0x3F, 0x38, 0x4F, 0xE9,
11064
11065 0x30, 0x50, 0x2E, 0x9F,
11066 0x3A, 0x31, 0x4F, 0xE9,
11067
11068 0x38, 0x21, 0x2C, 0x9F,
11069 0x3B, 0x39, 0x4F, 0xE9,
11070
11071 0x2A, 0x45, 0x4D, 0xB2,
11072 0x1A, 0x45, 0x55, 0xB2,
11073
11074 0x0A, 0x45, 0x4D, 0xB4,
11075 0x02, 0x45, 0x55, 0xB4,
11076
11077 0x27, 0xCF, 0x74, 0xC6,
11078 0x2A, 0x20,
11079 0x1A, 0x20,
11080
11081 0xA7, 0x30, 0x4F, 0xE9,
11082 0x0A, 0x20,
11083 0x02, 0x20,
11084
11085 0x31, 0x53, 0x2F, 0x9F,
11086 0x9C, 0x27, 0x20, 0xE9,
11087
11088 0x39, 0xE5, 0x2C, 0x9F,
11089 0xA8, 0x38, 0x4F, 0xE9,
11090
11091 0x2A, 0x44, 0x4C, 0xB6,
11092 0x1A, 0x44, 0x54, 0xB6,
11093
11094 0x30, 0x50, 0x2E, 0x9F,
11095 0x36, 0x31, 0x4F, 0xE9,
11096
11097 0x38, 0x21, 0x2C, 0x9F,
11098 0x37, 0x39, 0x4F, 0xE9,
11099
11100 0x0A, 0x45, 0x4D, 0xB6,
11101 0x02, 0x45, 0x55, 0xB6,
11102
11103 0x3D, 0xCF, 0x75, 0xC6,
11104 0x2A, 0x20,
11105 0x1A, 0x20,
11106
11107 0x2A, 0x46, 0x4E, 0xBF,
11108 0x1A, 0x46, 0x56, 0xBF,
11109
11110 0x31, 0x53, 0x2F, 0x9F,
11111 0xA4, 0x31, 0x4F, 0xE9,
11112
11113 0x39, 0xE5, 0x2C, 0x9F,
11114 0xA5, 0x39, 0x4F, 0xE9,
11115
11116 0x31, 0x3D, 0x20, 0xE9,
11117 0x0A, 0x20,
11118 0x02, 0x20,
11119
11120 0x0A, 0x47, 0x4F, 0xBF,
11121 0x02, 0x47, 0x57, 0xBF,
11122
11123 0x30, 0x50, 0x2E, 0x9F,
11124 0xA1, 0x30, 0x4F, 0xE9,
11125
11126 0x38, 0x21, 0x2C, 0x9F,
11127 0xA2, 0x38, 0x4F, 0xE9,
11128
11129 0x31, 0x53, 0x2F, 0x9F,
11130 0x9D, 0x31, 0x4F, 0xE9,
11131
11132 0x39, 0xE5, 0x2C, 0x9F,
11133 0x9E, 0x39, 0x4F, 0xE9,
11134
11135 0x2A, 0x43, 0x4B, 0xBF,
11136 0x1A, 0x43, 0x53, 0xBF,
11137
11138 0x30, 0x50, 0x2E, 0x9F,
11139 0x35, 0x30, 0x4F, 0xE9,
11140
11141 0x38, 0x21, 0x2C, 0x9F,
11142 0x39, 0x38, 0x4F, 0xE9,
11143
11144 0x31, 0x53, 0x2F, 0x9F,
11145 0x80, 0x31, 0x57, 0xE9,
11146
11147 0x39, 0xE5, 0x2C, 0x9F,
11148 0x81, 0x39, 0x57, 0xE9,
11149
11150 0x37, 0x48, 0x50, 0xBD,
11151 0x8A, 0x36, 0x20, 0xE9,
11152
11153 0x86, 0x76, 0x57, 0xE9,
11154 0x8B, 0x3E, 0x20, 0xE9,
11155
11156 0x82, 0x30, 0x57, 0xE9,
11157 0x87, 0x77, 0x57, 0xE9,
11158
11159 0x83, 0x38, 0x57, 0xE9,
11160 0x35, 0x49, 0x51, 0xBD,
11161
11162 0x84, 0x31, 0x5E, 0xE9,
11163 0x30, 0x1F, 0x5F, 0xE9,
11164
11165 0x85, 0x39, 0x5E, 0xE9,
11166 0x57, 0x25, 0x20, 0xE9,
11167
11168 0x2B, 0x48, 0x20, 0xE9,
11169 0x1D, 0x37, 0xE1, 0xEA,
11170
11171 0x1E, 0x35, 0xE1, 0xEA,
11172 0x00, 0xE0,
11173 0x26, 0x77,
11174
11175 0x24, 0x49, 0x20, 0xE9,
11176 0x99, 0xFF, 0x20, 0xEA,
11177
11178 0x16, 0x26, 0x20, 0xE9,
11179 0x57, 0x2E, 0xBF, 0xEA,
11180
11181 0x1C, 0x46, 0xA0, 0xE8,
11182 0x23, 0x4E, 0xA0, 0xE8,
11183
11184 0x2B, 0x56, 0xA0, 0xE8,
11185 0x1D, 0x47, 0xA0, 0xE8,
11186
11187 0x24, 0x4F, 0xA0, 0xE8,
11188 0x2C, 0x57, 0xA0, 0xE8,
11189
11190 0x1C, 0x00,
11191 0x23, 0x00,
11192 0x2B, 0x00,
11193 0x00, 0xE0,
11194
11195 0x1D, 0x00,
11196 0x24, 0x00,
11197 0x2C, 0x00,
11198 0x00, 0xE0,
11199
11200 0x1C, 0x65,
11201 0x23, 0x65,
11202 0x2B, 0x65,
11203 0x00, 0xE0,
11204
11205 0x1D, 0x65,
11206 0x24, 0x65,
11207 0x2C, 0x65,
11208 0x00, 0xE0,
11209
11210 0x1C, 0x23, 0x60, 0xEC,
11211 0x36, 0xD7, 0x36, 0xAD,
11212
11213 0x2B, 0x80, 0x60, 0xEC,
11214 0x1D, 0x24, 0x60, 0xEC,
11215
11216 0x3E, 0xD7, 0x3E, 0xAD,
11217 0x2C, 0x80, 0x60, 0xEC,
11218
11219 0x1C, 0x2B, 0xDE, 0xE8,
11220 0x23, 0x80, 0xDE, 0xE8,
11221
11222 0x36, 0x80, 0x36, 0xBD,
11223 0x3E, 0x80, 0x3E, 0xBD,
11224
11225 0x33, 0xD7, 0x1C, 0xBD,
11226 0x3B, 0xD7, 0x23, 0xBD,
11227
11228 0x46, 0x80, 0x46, 0xCF,
11229 0x4F, 0x80, 0x4F, 0xCF,
11230
11231 0x56, 0x33, 0x56, 0xCF,
11232 0x47, 0x3B, 0x47, 0xCF,
11233
11234 0xC1, 0xFF, 0x20, 0xEA,
11235 0x00, 0x80, 0x00, 0xE8,
11236
11237 0x4E, 0x33, 0x4E, 0xCF,
11238 0x57, 0x3B, 0x57, 0xCF,
11239
11240 0x87, 0xFF, 0x20, 0xEA,
11241 0x57, 0xC0, 0xBF, 0xEA,
11242
11243 0x00, 0x80, 0xA0, 0xE9,
11244 0x00, 0x00, 0xD8, 0xEC,
11245
11246};
11247
11248static unsigned char warp_g400_tgzsf[] = {
11249
11250 0x00, 0x88, 0x98, 0xE9,
11251 0x00, 0x80, 0x00, 0xE8,
11252
11253 0x00, 0x80, 0xA0, 0xE9,
11254 0x00, 0x00, 0xD8, 0xEC,
11255
11256 0xFF, 0x80, 0xC0, 0xE9,
11257 0x00, 0x80, 0x00, 0xE8,
11258
11259 0x22, 0x40, 0x48, 0xBF,
11260 0x2A, 0x40, 0x50, 0xBF,
11261
11262 0x32, 0x41, 0x49, 0xBF,
11263 0x3A, 0x41, 0x51, 0xBF,
11264
11265 0xC3, 0x6B,
11266 0xCB, 0x6B,
11267 0x00, 0x88, 0x98, 0xE9,
11268
11269 0x73, 0x7B, 0xC8, 0xEC,
11270 0x96, 0xE2,
11271 0x41, 0x04,
11272
11273 0x7B, 0x43, 0xA0, 0xE8,
11274 0x73, 0x4B, 0xA0, 0xE8,
11275
11276 0xAD, 0xEE, 0x29, 0x9F,
11277 0x00, 0xE0,
11278 0x49, 0x04,
11279
11280 0x90, 0xE2,
11281 0x51, 0x04,
11282 0x31, 0x46, 0xB1, 0xE8,
11283
11284 0x49, 0x41, 0xC0, 0xEC,
11285 0x39, 0x57, 0xB1, 0xE8,
11286
11287 0x00, 0x04,
11288 0x46, 0xE2,
11289 0x73, 0x53, 0xA0, 0xE8,
11290
11291 0x51, 0x41, 0xC0, 0xEC,
11292 0x31, 0x00,
11293 0x39, 0x00,
11294
11295 0x6A, 0x80, 0x15, 0xEA,
11296 0x08, 0x04,
11297 0x10, 0x04,
11298
11299 0x51, 0x49, 0xC0, 0xEC,
11300 0x2F, 0x41, 0x60, 0xEA,
11301
11302 0x31, 0x20,
11303 0x39, 0x20,
11304 0x1F, 0x42, 0xA0, 0xE8,
11305
11306 0x2A, 0x42, 0x4A, 0xBF,
11307 0x27, 0x4A, 0xA0, 0xE8,
11308
11309 0x1A, 0x42, 0x52, 0xBF,
11310 0x1E, 0x49, 0x60, 0xEA,
11311
11312 0x73, 0x7B, 0xC8, 0xEC,
11313 0x26, 0x51, 0x60, 0xEA,
11314
11315 0x32, 0x40, 0x48, 0xBD,
11316 0x22, 0x40, 0x50, 0xBD,
11317
11318 0x12, 0x41, 0x49, 0xBD,
11319 0x3A, 0x41, 0x51, 0xBD,
11320
11321 0xBF, 0x2F, 0x26, 0xBD,
11322 0x00, 0xE0,
11323 0x7B, 0x72,
11324
11325 0x32, 0x20,
11326 0x22, 0x20,
11327 0x12, 0x20,
11328 0x3A, 0x20,
11329
11330 0x46, 0x31, 0x46, 0xBF,
11331 0x4E, 0x31, 0x4E, 0xBF,
11332
11333 0xB3, 0xE2, 0x2D, 0x9F,
11334 0x00, 0x80, 0x00, 0xE8,
11335
11336 0x56, 0x31, 0x56, 0xBF,
11337 0x47, 0x39, 0x47, 0xBF,
11338
11339 0x4F, 0x39, 0x4F, 0xBF,
11340 0x57, 0x39, 0x57, 0xBF,
11341
11342 0x5C, 0x80, 0x07, 0xEA,
11343 0x24, 0x41, 0x20, 0xE9,
11344
11345 0x42, 0x73, 0xF8, 0xEC,
11346 0x00, 0xE0,
11347 0x2D, 0x73,
11348
11349 0x33, 0x72,
11350 0x0C, 0xE3,
11351 0xA5, 0x2F, 0x1E, 0xBD,
11352
11353 0x43, 0x43, 0x2D, 0xDF,
11354 0x4B, 0x4B, 0x2D, 0xDF,
11355
11356 0xAE, 0x1E, 0x26, 0xBD,
11357 0x58, 0xE3,
11358 0x33, 0x66,
11359
11360 0x53, 0x53, 0x2D, 0xDF,
11361 0x00, 0x80, 0x00, 0xE8,
11362
11363 0xB8, 0x38, 0x33, 0xBF,
11364 0x00, 0xE0,
11365 0x59, 0xE3,
11366
11367 0x1E, 0x12, 0x41, 0xE9,
11368 0x1A, 0x22, 0x41, 0xE9,
11369
11370 0x2B, 0x40, 0x3D, 0xE9,
11371 0x3F, 0x4B, 0xA0, 0xE8,
11372
11373 0x2D, 0x73,
11374 0x30, 0x76,
11375 0x05, 0x80, 0x3D, 0xEA,
11376
11377 0x37, 0x43, 0xA0, 0xE8,
11378 0x3D, 0x53, 0xA0, 0xE8,
11379
11380 0x48, 0x70, 0xF8, 0xEC,
11381 0x2B, 0x48, 0x3C, 0xE9,
11382
11383 0x1F, 0x27, 0xBC, 0xE8,
11384 0x00, 0x80, 0x00, 0xE8,
11385
11386 0x00, 0x80, 0x00, 0xE8,
11387 0x00, 0x80, 0x00, 0xE8,
11388
11389 0x15, 0xC0, 0x20, 0xE9,
11390 0x15, 0xC0, 0x20, 0xE9,
11391
11392 0x15, 0xC0, 0x20, 0xE9,
11393 0x15, 0xC0, 0x20, 0xE9,
11394
11395 0x18, 0x3A, 0x41, 0xE9,
11396 0x1D, 0x32, 0x41, 0xE9,
11397
11398 0x2A, 0x40, 0x20, 0xE9,
11399 0x56, 0x3D, 0x56, 0xDF,
11400
11401 0x46, 0x37, 0x46, 0xDF,
11402 0x4E, 0x3F, 0x4E, 0xDF,
11403
11404 0x16, 0x30, 0x20, 0xE9,
11405 0x4F, 0x3F, 0x4F, 0xDF,
11406
11407 0x47, 0x37, 0x47, 0xDF,
11408 0x57, 0x3D, 0x57, 0xDF,
11409
11410 0x32, 0x32, 0x2D, 0xDF,
11411 0x22, 0x22, 0x2D, 0xDF,
11412
11413 0x12, 0x12, 0x2D, 0xDF,
11414 0x3A, 0x3A, 0x2D, 0xDF,
11415
11416 0x27, 0xCF, 0x74, 0xC2,
11417 0x37, 0xCF, 0x74, 0xC4,
11418
11419 0x0A, 0x44, 0x4C, 0xB0,
11420 0x02, 0x44, 0x54, 0xB0,
11421
11422 0x3D, 0xCF, 0x74, 0xC0,
11423 0x34, 0x37, 0x20, 0xE9,
11424
11425 0x31, 0x53, 0x2F, 0x9F,
11426 0x38, 0x27, 0x20, 0xE9,
11427
11428 0x39, 0xE5, 0x2C, 0x9F,
11429 0x3C, 0x3D, 0x20, 0xE9,
11430
11431 0x2A, 0x44, 0x4C, 0xB2,
11432 0x1A, 0x44, 0x54, 0xB2,
11433
11434 0x2E, 0x80, 0x3A, 0xEA,
11435 0x0A, 0x20,
11436 0x02, 0x20,
11437
11438 0x27, 0xCF, 0x75, 0xC0,
11439 0x2A, 0x20,
11440 0x1A, 0x20,
11441
11442 0x30, 0x50, 0x2E, 0x9F,
11443 0x32, 0x31, 0x5F, 0xE9,
11444
11445 0x38, 0x21, 0x2C, 0x9F,
11446 0x33, 0x39, 0x5F, 0xE9,
11447
11448 0x3D, 0xCF, 0x75, 0xC2,
11449 0x37, 0xCF, 0x75, 0xC4,
11450
11451 0x31, 0x53, 0x2F, 0x9F,
11452 0xA6, 0x27, 0x20, 0xE9,
11453
11454 0x39, 0xE5, 0x2C, 0x9F,
11455 0xA3, 0x3D, 0x20, 0xE9,
11456
11457 0x2A, 0x44, 0x4C, 0xB4,
11458 0x1A, 0x44, 0x54, 0xB4,
11459
11460 0x0A, 0x45, 0x4D, 0xB0,
11461 0x02, 0x45, 0x55, 0xB0,
11462
11463 0x88, 0x73, 0x5E, 0xE9,
11464 0x2A, 0x20,
11465 0x1A, 0x20,
11466
11467 0xA0, 0x37, 0x20, 0xE9,
11468 0x0A, 0x20,
11469 0x02, 0x20,
11470
11471 0x31, 0x53, 0x2F, 0x9F,
11472 0x3E, 0x30, 0x4F, 0xE9,
11473
11474 0x39, 0xE5, 0x2C, 0x9F,
11475 0x3F, 0x38, 0x4F, 0xE9,
11476
11477 0x30, 0x50, 0x2E, 0x9F,
11478 0x3A, 0x31, 0x4F, 0xE9,
11479
11480 0x38, 0x21, 0x2C, 0x9F,
11481 0x3B, 0x39, 0x4F, 0xE9,
11482
11483 0x2A, 0x45, 0x4D, 0xB2,
11484 0x1A, 0x45, 0x55, 0xB2,
11485
11486 0x0A, 0x45, 0x4D, 0xB4,
11487 0x02, 0x45, 0x55, 0xB4,
11488
11489 0x27, 0xCF, 0x75, 0xC6,
11490 0x2A, 0x20,
11491 0x1A, 0x20,
11492
11493 0xA7, 0x30, 0x4F, 0xE9,
11494 0x0A, 0x20,
11495 0x02, 0x20,
11496
11497 0x31, 0x53, 0x2F, 0x9F,
11498 0x31, 0x27, 0x20, 0xE9,
11499
11500 0x39, 0xE5, 0x2C, 0x9F,
11501 0xA8, 0x38, 0x4F, 0xE9,
11502
11503 0x2A, 0x45, 0x4D, 0xB6,
11504 0x1A, 0x45, 0x55, 0xB6,
11505
11506 0x30, 0x50, 0x2E, 0x9F,
11507 0x36, 0x31, 0x4F, 0xE9,
11508
11509 0x38, 0x21, 0x2C, 0x9F,
11510 0x37, 0x39, 0x4F, 0xE9,
11511
11512 0x00, 0x80, 0x00, 0xE8,
11513 0x2A, 0x20,
11514 0x1A, 0x20,
11515
11516 0x2A, 0x46, 0x4E, 0xBF,
11517 0x1A, 0x46, 0x56, 0xBF,
11518
11519 0x31, 0x53, 0x2F, 0x9F,
11520 0xA4, 0x31, 0x4F, 0xE9,
11521
11522 0x39, 0xE5, 0x2C, 0x9F,
11523 0xA5, 0x39, 0x4F, 0xE9,
11524
11525 0x0A, 0x47, 0x4F, 0xBF,
11526 0x02, 0x47, 0x57, 0xBF,
11527
11528 0x31, 0x53, 0x2F, 0x9F,
11529 0xA1, 0x30, 0x4F, 0xE9,
11530
11531 0x39, 0xE5, 0x2C, 0x9F,
11532 0xA2, 0x38, 0x4F, 0xE9,
11533
11534 0x2A, 0x43, 0x4B, 0xBF,
11535 0x1A, 0x43, 0x53, 0xBF,
11536
11537 0x30, 0x50, 0x2E, 0x9F,
11538 0x35, 0x31, 0x4F, 0xE9,
11539
11540 0x38, 0x21, 0x2C, 0x9F,
11541 0x39, 0x39, 0x4F, 0xE9,
11542
11543 0x31, 0x53, 0x2F, 0x9F,
11544 0x80, 0x31, 0x57, 0xE9,
11545
11546 0x39, 0xE5, 0x2C, 0x9F,
11547 0x81, 0x39, 0x57, 0xE9,
11548
11549 0x37, 0x48, 0x50, 0xBD,
11550 0x8A, 0x36, 0x20, 0xE9,
11551
11552 0x86, 0x76, 0x57, 0xE9,
11553 0x8B, 0x3E, 0x20, 0xE9,
11554
11555 0x82, 0x30, 0x57, 0xE9,
11556 0x87, 0x77, 0x57, 0xE9,
11557
11558 0x83, 0x38, 0x57, 0xE9,
11559 0x35, 0x49, 0x51, 0xBD,
11560
11561 0x84, 0x31, 0x5E, 0xE9,
11562 0x30, 0x1F, 0x5F, 0xE9,
11563
11564 0x85, 0x39, 0x5E, 0xE9,
11565 0x57, 0x25, 0x20, 0xE9,
11566
11567 0x2B, 0x48, 0x20, 0xE9,
11568 0x1D, 0x37, 0xE1, 0xEA,
11569
11570 0x1E, 0x35, 0xE1, 0xEA,
11571 0x00, 0xE0,
11572 0x26, 0x77,
11573
11574 0x24, 0x49, 0x20, 0xE9,
11575 0x9D, 0xFF, 0x20, 0xEA,
11576
11577 0x16, 0x26, 0x20, 0xE9,
11578 0x57, 0x2E, 0xBF, 0xEA,
11579
11580 0x1C, 0x46, 0xA0, 0xE8,
11581 0x23, 0x4E, 0xA0, 0xE8,
11582
11583 0x2B, 0x56, 0xA0, 0xE8,
11584 0x1D, 0x47, 0xA0, 0xE8,
11585
11586 0x24, 0x4F, 0xA0, 0xE8,
11587 0x2C, 0x57, 0xA0, 0xE8,
11588
11589 0x1C, 0x00,
11590 0x23, 0x00,
11591 0x2B, 0x00,
11592 0x00, 0xE0,
11593
11594 0x1D, 0x00,
11595 0x24, 0x00,
11596 0x2C, 0x00,
11597 0x00, 0xE0,
11598
11599 0x1C, 0x65,
11600 0x23, 0x65,
11601 0x2B, 0x65,
11602 0x00, 0xE0,
11603
11604 0x1D, 0x65,
11605 0x24, 0x65,
11606 0x2C, 0x65,
11607 0x00, 0xE0,
11608
11609 0x1C, 0x23, 0x60, 0xEC,
11610 0x36, 0xD7, 0x36, 0xAD,
11611
11612 0x2B, 0x80, 0x60, 0xEC,
11613 0x1D, 0x24, 0x60, 0xEC,
11614
11615 0x3E, 0xD7, 0x3E, 0xAD,
11616 0x2C, 0x80, 0x60, 0xEC,
11617
11618 0x1C, 0x2B, 0xDE, 0xE8,
11619 0x23, 0x80, 0xDE, 0xE8,
11620
11621 0x36, 0x80, 0x36, 0xBD,
11622 0x3E, 0x80, 0x3E, 0xBD,
11623
11624 0x33, 0xD7, 0x1C, 0xBD,
11625 0x3B, 0xD7, 0x23, 0xBD,
11626
11627 0x46, 0x80, 0x46, 0xCF,
11628 0x4F, 0x80, 0x4F, 0xCF,
11629
11630 0x56, 0x33, 0x56, 0xCF,
11631 0x47, 0x3B, 0x47, 0xCF,
11632
11633 0xC5, 0xFF, 0x20, 0xEA,
11634 0x00, 0x80, 0x00, 0xE8,
11635
11636 0x4E, 0x33, 0x4E, 0xCF,
11637 0x57, 0x3B, 0x57, 0xCF,
11638
11639 0x8B, 0xFF, 0x20, 0xEA,
11640 0x57, 0xC0, 0xBF, 0xEA,
11641
11642 0x00, 0x80, 0xA0, 0xE9,
11643 0x00, 0x00, 0xD8, 0xEC,
11644
11645};
diff --git a/drivers/gpu/drm/mga/mga_warp.c b/drivers/gpu/drm/mga/mga_warp.c
index 651b93c8ab5d..9aad4847afdf 100644
--- a/drivers/gpu/drm/mga/mga_warp.c
+++ b/drivers/gpu/drm/mga/mga_warp.c
@@ -27,132 +27,108 @@
27 * Gareth Hughes <gareth@valinux.com> 27 * Gareth Hughes <gareth@valinux.com>
28 */ 28 */
29 29
30#include <linux/firmware.h>
31#include <linux/ihex.h>
32#include <linux/platform_device.h>
33
30#include "drmP.h" 34#include "drmP.h"
31#include "drm.h" 35#include "drm.h"
32#include "mga_drm.h" 36#include "mga_drm.h"
33#include "mga_drv.h" 37#include "mga_drv.h"
34#include "mga_ucode.h" 38
39#define FIRMWARE_G200 "matrox/g200_warp.fw"
40#define FIRMWARE_G400 "matrox/g400_warp.fw"
41
42MODULE_FIRMWARE(FIRMWARE_G200);
43MODULE_FIRMWARE(FIRMWARE_G400);
35 44
36#define MGA_WARP_CODE_ALIGN 256 /* in bytes */ 45#define MGA_WARP_CODE_ALIGN 256 /* in bytes */
37 46
38#define WARP_UCODE_SIZE( which ) \ 47#define WARP_UCODE_SIZE(size) ALIGN(size, MGA_WARP_CODE_ALIGN)
39 ((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN) 48
40 49int mga_warp_install_microcode(drm_mga_private_t * dev_priv)
41#define WARP_UCODE_INSTALL( which, where ) \
42do { \
43 DRM_DEBUG( " pcbase = 0x%08lx vcbase = %p\n", pcbase, vcbase );\
44 dev_priv->warp_pipe_phys[where] = pcbase; \
45 memcpy( vcbase, which, sizeof(which) ); \
46 pcbase += WARP_UCODE_SIZE( which ); \
47 vcbase += WARP_UCODE_SIZE( which ); \
48} while (0)
49
50static const unsigned int mga_warp_g400_microcode_size =
51 (WARP_UCODE_SIZE(warp_g400_tgz) +
52 WARP_UCODE_SIZE(warp_g400_tgza) +
53 WARP_UCODE_SIZE(warp_g400_tgzaf) +
54 WARP_UCODE_SIZE(warp_g400_tgzf) +
55 WARP_UCODE_SIZE(warp_g400_tgzs) +
56 WARP_UCODE_SIZE(warp_g400_tgzsa) +
57 WARP_UCODE_SIZE(warp_g400_tgzsaf) +
58 WARP_UCODE_SIZE(warp_g400_tgzsf) +
59 WARP_UCODE_SIZE(warp_g400_t2gz) +
60 WARP_UCODE_SIZE(warp_g400_t2gza) +
61 WARP_UCODE_SIZE(warp_g400_t2gzaf) +
62 WARP_UCODE_SIZE(warp_g400_t2gzf) +
63 WARP_UCODE_SIZE(warp_g400_t2gzs) +
64 WARP_UCODE_SIZE(warp_g400_t2gzsa) +
65 WARP_UCODE_SIZE(warp_g400_t2gzsaf) + WARP_UCODE_SIZE(warp_g400_t2gzsf));
66
67static const unsigned int mga_warp_g200_microcode_size =
68 (WARP_UCODE_SIZE(warp_g200_tgz) +
69 WARP_UCODE_SIZE(warp_g200_tgza) +
70 WARP_UCODE_SIZE(warp_g200_tgzaf) +
71 WARP_UCODE_SIZE(warp_g200_tgzf) +
72 WARP_UCODE_SIZE(warp_g200_tgzs) +
73 WARP_UCODE_SIZE(warp_g200_tgzsa) +
74 WARP_UCODE_SIZE(warp_g200_tgzsaf) + WARP_UCODE_SIZE(warp_g200_tgzsf));
75
76unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv)
77{ 50{
51 unsigned char *vcbase = dev_priv->warp->handle;
52 unsigned long pcbase = dev_priv->warp->offset;
53 const char *firmware_name;
54 struct platform_device *pdev;
55 const struct firmware *fw = NULL;
56 const struct ihex_binrec *rec;
57 unsigned int size;
58 int n_pipes, where;
59 int rc = 0;
60
78 switch (dev_priv->chipset) { 61 switch (dev_priv->chipset) {
79 case MGA_CARD_TYPE_G400: 62 case MGA_CARD_TYPE_G400:
80 case MGA_CARD_TYPE_G550: 63 case MGA_CARD_TYPE_G550:
81 return PAGE_ALIGN(mga_warp_g400_microcode_size); 64 firmware_name = FIRMWARE_G400;
65 n_pipes = MGA_MAX_G400_PIPES;
66 break;
82 case MGA_CARD_TYPE_G200: 67 case MGA_CARD_TYPE_G200:
83 return PAGE_ALIGN(mga_warp_g200_microcode_size); 68 firmware_name = FIRMWARE_G200;
69 n_pipes = MGA_MAX_G200_PIPES;
70 break;
84 default: 71 default:
85 return 0; 72 return -EINVAL;
86 } 73 }
87}
88
89static int mga_warp_install_g400_microcode(drm_mga_private_t * dev_priv)
90{
91 unsigned char *vcbase = dev_priv->warp->handle;
92 unsigned long pcbase = dev_priv->warp->offset;
93
94 memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
95
96 WARP_UCODE_INSTALL(warp_g400_tgz, MGA_WARP_TGZ);
97 WARP_UCODE_INSTALL(warp_g400_tgzf, MGA_WARP_TGZF);
98 WARP_UCODE_INSTALL(warp_g400_tgza, MGA_WARP_TGZA);
99 WARP_UCODE_INSTALL(warp_g400_tgzaf, MGA_WARP_TGZAF);
100 WARP_UCODE_INSTALL(warp_g400_tgzs, MGA_WARP_TGZS);
101 WARP_UCODE_INSTALL(warp_g400_tgzsf, MGA_WARP_TGZSF);
102 WARP_UCODE_INSTALL(warp_g400_tgzsa, MGA_WARP_TGZSA);
103 WARP_UCODE_INSTALL(warp_g400_tgzsaf, MGA_WARP_TGZSAF);
104
105 WARP_UCODE_INSTALL(warp_g400_t2gz, MGA_WARP_T2GZ);
106 WARP_UCODE_INSTALL(warp_g400_t2gzf, MGA_WARP_T2GZF);
107 WARP_UCODE_INSTALL(warp_g400_t2gza, MGA_WARP_T2GZA);
108 WARP_UCODE_INSTALL(warp_g400_t2gzaf, MGA_WARP_T2GZAF);
109 WARP_UCODE_INSTALL(warp_g400_t2gzs, MGA_WARP_T2GZS);
110 WARP_UCODE_INSTALL(warp_g400_t2gzsf, MGA_WARP_T2GZSF);
111 WARP_UCODE_INSTALL(warp_g400_t2gzsa, MGA_WARP_T2GZSA);
112 WARP_UCODE_INSTALL(warp_g400_t2gzsaf, MGA_WARP_T2GZSAF);
113
114 return 0;
115}
116
117static int mga_warp_install_g200_microcode(drm_mga_private_t * dev_priv)
118{
119 unsigned char *vcbase = dev_priv->warp->handle;
120 unsigned long pcbase = dev_priv->warp->offset;
121
122 memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
123
124 WARP_UCODE_INSTALL(warp_g200_tgz, MGA_WARP_TGZ);
125 WARP_UCODE_INSTALL(warp_g200_tgzf, MGA_WARP_TGZF);
126 WARP_UCODE_INSTALL(warp_g200_tgza, MGA_WARP_TGZA);
127 WARP_UCODE_INSTALL(warp_g200_tgzaf, MGA_WARP_TGZAF);
128 WARP_UCODE_INSTALL(warp_g200_tgzs, MGA_WARP_TGZS);
129 WARP_UCODE_INSTALL(warp_g200_tgzsf, MGA_WARP_TGZSF);
130 WARP_UCODE_INSTALL(warp_g200_tgzsa, MGA_WARP_TGZSA);
131 WARP_UCODE_INSTALL(warp_g200_tgzsaf, MGA_WARP_TGZSAF);
132 74
133 return 0; 75 pdev = platform_device_register_simple("mga_warp", 0, NULL, 0);
134} 76 if (IS_ERR(pdev)) {
77 DRM_ERROR("mga: Failed to register microcode\n");
78 return PTR_ERR(pdev);
79 }
80 rc = request_ihex_firmware(&fw, firmware_name, &pdev->dev);
81 platform_device_unregister(pdev);
82 if (rc) {
83 DRM_ERROR("mga: Failed to load microcode \"%s\"\n",
84 firmware_name);
85 return rc;
86 }
135 87
136int mga_warp_install_microcode(drm_mga_private_t * dev_priv) 88 size = 0;
137{ 89 where = 0;
138 const unsigned int size = mga_warp_microcode_size(dev_priv); 90 for (rec = (const struct ihex_binrec *)fw->data;
91 rec;
92 rec = ihex_next_binrec(rec)) {
93 size += WARP_UCODE_SIZE(be16_to_cpu(rec->len));
94 where++;
95 }
139 96
97 if (where != n_pipes) {
98 DRM_ERROR("mga: Invalid microcode \"%s\"\n", firmware_name);
99 rc = -EINVAL;
100 goto out;
101 }
102 size = PAGE_ALIGN(size);
140 DRM_DEBUG("MGA ucode size = %d bytes\n", size); 103 DRM_DEBUG("MGA ucode size = %d bytes\n", size);
141 if (size > dev_priv->warp->size) { 104 if (size > dev_priv->warp->size) {
142 DRM_ERROR("microcode too large! (%u > %lu)\n", 105 DRM_ERROR("microcode too large! (%u > %lu)\n",
143 size, dev_priv->warp->size); 106 size, dev_priv->warp->size);
144 return -ENOMEM; 107 rc = -ENOMEM;
108 goto out;
145 } 109 }
146 110
147 switch (dev_priv->chipset) { 111 memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
148 case MGA_CARD_TYPE_G400: 112
149 case MGA_CARD_TYPE_G550: 113 where = 0;
150 return mga_warp_install_g400_microcode(dev_priv); 114 for (rec = (const struct ihex_binrec *)fw->data;
151 case MGA_CARD_TYPE_G200: 115 rec;
152 return mga_warp_install_g200_microcode(dev_priv); 116 rec = ihex_next_binrec(rec)) {
153 default: 117 unsigned int src_size, dst_size;
154 return -EINVAL; 118
119 DRM_DEBUG(" pcbase = 0x%08lx vcbase = %p\n", pcbase, vcbase);
120 dev_priv->warp_pipe_phys[where] = pcbase;
121 src_size = be16_to_cpu(rec->len);
122 dst_size = WARP_UCODE_SIZE(src_size);
123 memcpy(vcbase, rec->data, src_size);
124 pcbase += dst_size;
125 vcbase += dst_size;
126 where++;
155 } 127 }
128
129out:
130 release_firmware(fw);
131 return rc;
156} 132}
157 133
158#define WMISC_EXPECTED (MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE) 134#define WMISC_EXPECTED (MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE)
diff --git a/drivers/gpu/drm/r128/r128_cce.c b/drivers/gpu/drm/r128/r128_cce.c
index c75fd3564040..4c39a407aa4a 100644
--- a/drivers/gpu/drm/r128/r128_cce.c
+++ b/drivers/gpu/drm/r128/r128_cce.c
@@ -29,6 +29,9 @@
29 * Gareth Hughes <gareth@valinux.com> 29 * Gareth Hughes <gareth@valinux.com>
30 */ 30 */
31 31
32#include <linux/firmware.h>
33#include <linux/platform_device.h>
34
32#include "drmP.h" 35#include "drmP.h"
33#include "drm.h" 36#include "drm.h"
34#include "r128_drm.h" 37#include "r128_drm.h"
@@ -36,50 +39,9 @@
36 39
37#define R128_FIFO_DEBUG 0 40#define R128_FIFO_DEBUG 0
38 41
39/* CCE microcode (from ATI) */ 42#define FIRMWARE_NAME "r128/r128_cce.bin"
40static u32 r128_cce_microcode[] = { 43
41 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0, 44MODULE_FIRMWARE(FIRMWARE_NAME);
42 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
43 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
44 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
45 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
46 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
47 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
48 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
49 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
50 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
51 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
52 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
53 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
54 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
55 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
56 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
57 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
58 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
59 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
60 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
61 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
62 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
63 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
64 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
65 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
66 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
67 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
68 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
69 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
70 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
71 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
72 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
73 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
74 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
75 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
76 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
77 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
78 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
81 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
82};
83 45
84static int R128_READ_PLL(struct drm_device * dev, int addr) 46static int R128_READ_PLL(struct drm_device * dev, int addr)
85{ 47{
@@ -176,20 +138,50 @@ static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)
176 */ 138 */
177 139
178/* Load the microcode for the CCE */ 140/* Load the microcode for the CCE */
179static void r128_cce_load_microcode(drm_r128_private_t * dev_priv) 141static int r128_cce_load_microcode(drm_r128_private_t *dev_priv)
180{ 142{
181 int i; 143 struct platform_device *pdev;
144 const struct firmware *fw;
145 const __be32 *fw_data;
146 int rc, i;
182 147
183 DRM_DEBUG("\n"); 148 DRM_DEBUG("\n");
184 149
150 pdev = platform_device_register_simple("r128_cce", 0, NULL, 0);
151 if (IS_ERR(pdev)) {
152 printk(KERN_ERR "r128_cce: Failed to register firmware\n");
153 return PTR_ERR(pdev);
154 }
155 rc = request_firmware(&fw, FIRMWARE_NAME, &pdev->dev);
156 platform_device_unregister(pdev);
157 if (rc) {
158 printk(KERN_ERR "r128_cce: Failed to load firmware \"%s\"\n",
159 FIRMWARE_NAME);
160 return rc;
161 }
162
163 if (fw->size != 256 * 8) {
164 printk(KERN_ERR
165 "r128_cce: Bogus length %zu in firmware \"%s\"\n",
166 fw->size, FIRMWARE_NAME);
167 rc = -EINVAL;
168 goto out_release;
169 }
170
185 r128_do_wait_for_idle(dev_priv); 171 r128_do_wait_for_idle(dev_priv);
186 172
173 fw_data = (const __be32 *)fw->data;
187 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0); 174 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
188 for (i = 0; i < 256; i++) { 175 for (i = 0; i < 256; i++) {
189 R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]); 176 R128_WRITE(R128_PM4_MICROCODE_DATAH,
177 be32_to_cpup(&fw_data[i * 2]));
190 R128_WRITE(R128_PM4_MICROCODE_DATAL, 178 R128_WRITE(R128_PM4_MICROCODE_DATAL,
191 r128_cce_microcode[i * 2 + 1]); 179 be32_to_cpup(&fw_data[i * 2 + 1]));
192 } 180 }
181
182out_release:
183 release_firmware(fw);
184 return rc;
193} 185}
194 186
195/* Flush any pending commands to the CCE. This should only be used just 187/* Flush any pending commands to the CCE. This should only be used just
@@ -350,9 +342,15 @@ static void r128_cce_init_ring_buffer(struct drm_device * dev,
350static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) 342static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init)
351{ 343{
352 drm_r128_private_t *dev_priv; 344 drm_r128_private_t *dev_priv;
345 int rc;
353 346
354 DRM_DEBUG("\n"); 347 DRM_DEBUG("\n");
355 348
349 if (dev->dev_private) {
350 DRM_DEBUG("called when already initialized\n");
351 return -EINVAL;
352 }
353
356 dev_priv = kzalloc(sizeof(drm_r128_private_t), GFP_KERNEL); 354 dev_priv = kzalloc(sizeof(drm_r128_private_t), GFP_KERNEL);
357 if (dev_priv == NULL) 355 if (dev_priv == NULL)
358 return -ENOMEM; 356 return -ENOMEM;
@@ -575,13 +573,18 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init)
575#endif 573#endif
576 574
577 r128_cce_init_ring_buffer(dev, dev_priv); 575 r128_cce_init_ring_buffer(dev, dev_priv);
578 r128_cce_load_microcode(dev_priv); 576 rc = r128_cce_load_microcode(dev_priv);
579 577
580 dev->dev_private = (void *)dev_priv; 578 dev->dev_private = (void *)dev_priv;
581 579
582 r128_do_engine_reset(dev); 580 r128_do_engine_reset(dev);
583 581
584 return 0; 582 if (rc) {
583 DRM_ERROR("Failed to load firmware!\n");
584 r128_do_cleanup_cce(dev);
585 }
586
587 return rc;
585} 588}
586 589
587int r128_do_cleanup_cce(struct drm_device * dev) 590int r128_do_cleanup_cce(struct drm_device * dev)
@@ -649,6 +652,8 @@ int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_pri
649 652
650 LOCK_TEST_WITH_RETURN(dev, file_priv); 653 LOCK_TEST_WITH_RETURN(dev, file_priv);
651 654
655 DEV_INIT_TEST_WITH_RETURN(dev_priv);
656
652 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) { 657 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
653 DRM_DEBUG("while CCE running\n"); 658 DRM_DEBUG("while CCE running\n");
654 return 0; 659 return 0;
@@ -671,6 +676,8 @@ int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv
671 676
672 LOCK_TEST_WITH_RETURN(dev, file_priv); 677 LOCK_TEST_WITH_RETURN(dev, file_priv);
673 678
679 DEV_INIT_TEST_WITH_RETURN(dev_priv);
680
674 /* Flush any pending CCE commands. This ensures any outstanding 681 /* Flush any pending CCE commands. This ensures any outstanding
675 * commands are exectuted by the engine before we turn it off. 682 * commands are exectuted by the engine before we turn it off.
676 */ 683 */
@@ -708,10 +715,7 @@ int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_pri
708 715
709 LOCK_TEST_WITH_RETURN(dev, file_priv); 716 LOCK_TEST_WITH_RETURN(dev, file_priv);
710 717
711 if (!dev_priv) { 718 DEV_INIT_TEST_WITH_RETURN(dev_priv);
712 DRM_DEBUG("called before init done\n");
713 return -EINVAL;
714 }
715 719
716 r128_do_cce_reset(dev_priv); 720 r128_do_cce_reset(dev_priv);
717 721
@@ -728,6 +732,8 @@ int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv
728 732
729 LOCK_TEST_WITH_RETURN(dev, file_priv); 733 LOCK_TEST_WITH_RETURN(dev, file_priv);
730 734
735 DEV_INIT_TEST_WITH_RETURN(dev_priv);
736
731 if (dev_priv->cce_running) { 737 if (dev_priv->cce_running) {
732 r128_do_cce_flush(dev_priv); 738 r128_do_cce_flush(dev_priv);
733 } 739 }
@@ -741,6 +747,8 @@ int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_
741 747
742 LOCK_TEST_WITH_RETURN(dev, file_priv); 748 LOCK_TEST_WITH_RETURN(dev, file_priv);
743 749
750 DEV_INIT_TEST_WITH_RETURN(dev->dev_private);
751
744 return r128_do_engine_reset(dev); 752 return r128_do_engine_reset(dev);
745} 753}
746 754
diff --git a/drivers/gpu/drm/r128/r128_drv.h b/drivers/gpu/drm/r128/r128_drv.h
index 797a26c42dab..3c60829d82e9 100644
--- a/drivers/gpu/drm/r128/r128_drv.h
+++ b/drivers/gpu/drm/r128/r128_drv.h
@@ -422,6 +422,14 @@ static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv)
422 * Misc helper macros 422 * Misc helper macros
423 */ 423 */
424 424
425#define DEV_INIT_TEST_WITH_RETURN(_dev_priv) \
426do { \
427 if (!_dev_priv) { \
428 DRM_ERROR("called with no initialization\n"); \
429 return -EINVAL; \
430 } \
431} while (0)
432
425#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 433#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
426do { \ 434do { \
427 drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \ 435 drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \
diff --git a/drivers/gpu/drm/r128/r128_state.c b/drivers/gpu/drm/r128/r128_state.c
index 026a48c95c8f..af2665cf4718 100644
--- a/drivers/gpu/drm/r128/r128_state.c
+++ b/drivers/gpu/drm/r128/r128_state.c
@@ -1244,14 +1244,18 @@ static void r128_cce_dispatch_stipple(struct drm_device * dev, u32 * stipple)
1244static int r128_cce_clear(struct drm_device *dev, void *data, struct drm_file *file_priv) 1244static int r128_cce_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
1245{ 1245{
1246 drm_r128_private_t *dev_priv = dev->dev_private; 1246 drm_r128_private_t *dev_priv = dev->dev_private;
1247 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 1247 drm_r128_sarea_t *sarea_priv;
1248 drm_r128_clear_t *clear = data; 1248 drm_r128_clear_t *clear = data;
1249 DRM_DEBUG("\n"); 1249 DRM_DEBUG("\n");
1250 1250
1251 LOCK_TEST_WITH_RETURN(dev, file_priv); 1251 LOCK_TEST_WITH_RETURN(dev, file_priv);
1252 1252
1253 DEV_INIT_TEST_WITH_RETURN(dev_priv);
1254
1253 RING_SPACE_TEST_WITH_RETURN(dev_priv); 1255 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1254 1256
1257 sarea_priv = dev_priv->sarea_priv;
1258
1255 if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) 1259 if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
1256 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; 1260 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
1257 1261
@@ -1312,6 +1316,8 @@ static int r128_cce_flip(struct drm_device *dev, void *data, struct drm_file *fi
1312 1316
1313 LOCK_TEST_WITH_RETURN(dev, file_priv); 1317 LOCK_TEST_WITH_RETURN(dev, file_priv);
1314 1318
1319 DEV_INIT_TEST_WITH_RETURN(dev_priv);
1320
1315 RING_SPACE_TEST_WITH_RETURN(dev_priv); 1321 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1316 1322
1317 if (!dev_priv->page_flipping) 1323 if (!dev_priv->page_flipping)
@@ -1331,6 +1337,8 @@ static int r128_cce_swap(struct drm_device *dev, void *data, struct drm_file *fi
1331 1337
1332 LOCK_TEST_WITH_RETURN(dev, file_priv); 1338 LOCK_TEST_WITH_RETURN(dev, file_priv);
1333 1339
1340 DEV_INIT_TEST_WITH_RETURN(dev_priv);
1341
1334 RING_SPACE_TEST_WITH_RETURN(dev_priv); 1342 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1335 1343
1336 if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) 1344 if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
@@ -1354,10 +1362,7 @@ static int r128_cce_vertex(struct drm_device *dev, void *data, struct drm_file *
1354 1362
1355 LOCK_TEST_WITH_RETURN(dev, file_priv); 1363 LOCK_TEST_WITH_RETURN(dev, file_priv);
1356 1364
1357 if (!dev_priv) { 1365 DEV_INIT_TEST_WITH_RETURN(dev_priv);
1358 DRM_ERROR("called with no initialization\n");
1359 return -EINVAL;
1360 }
1361 1366
1362 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", 1367 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
1363 DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard); 1368 DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard);
@@ -1410,10 +1415,7 @@ static int r128_cce_indices(struct drm_device *dev, void *data, struct drm_file
1410 1415
1411 LOCK_TEST_WITH_RETURN(dev, file_priv); 1416 LOCK_TEST_WITH_RETURN(dev, file_priv);
1412 1417
1413 if (!dev_priv) { 1418 DEV_INIT_TEST_WITH_RETURN(dev_priv);
1414 DRM_ERROR("called with no initialization\n");
1415 return -EINVAL;
1416 }
1417 1419
1418 DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, 1420 DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID,
1419 elts->idx, elts->start, elts->end, elts->discard); 1421 elts->idx, elts->start, elts->end, elts->discard);
@@ -1476,6 +1478,8 @@ static int r128_cce_blit(struct drm_device *dev, void *data, struct drm_file *fi
1476 1478
1477 LOCK_TEST_WITH_RETURN(dev, file_priv); 1479 LOCK_TEST_WITH_RETURN(dev, file_priv);
1478 1480
1481 DEV_INIT_TEST_WITH_RETURN(dev_priv);
1482
1479 DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit->idx); 1483 DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit->idx);
1480 1484
1481 if (blit->idx < 0 || blit->idx >= dma->buf_count) { 1485 if (blit->idx < 0 || blit->idx >= dma->buf_count) {
@@ -1501,6 +1505,8 @@ static int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *f
1501 1505
1502 LOCK_TEST_WITH_RETURN(dev, file_priv); 1506 LOCK_TEST_WITH_RETURN(dev, file_priv);
1503 1507
1508 DEV_INIT_TEST_WITH_RETURN(dev_priv);
1509
1504 RING_SPACE_TEST_WITH_RETURN(dev_priv); 1510 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1505 1511
1506 ret = -EINVAL; 1512 ret = -EINVAL;
@@ -1531,6 +1537,8 @@ static int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file
1531 1537
1532 LOCK_TEST_WITH_RETURN(dev, file_priv); 1538 LOCK_TEST_WITH_RETURN(dev, file_priv);
1533 1539
1540 DEV_INIT_TEST_WITH_RETURN(dev_priv);
1541
1534 if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32))) 1542 if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32)))
1535 return -EFAULT; 1543 return -EFAULT;
1536 1544
@@ -1555,10 +1563,7 @@ static int r128_cce_indirect(struct drm_device *dev, void *data, struct drm_file
1555 1563
1556 LOCK_TEST_WITH_RETURN(dev, file_priv); 1564 LOCK_TEST_WITH_RETURN(dev, file_priv);
1557 1565
1558 if (!dev_priv) { 1566 DEV_INIT_TEST_WITH_RETURN(dev_priv);
1559 DRM_ERROR("called with no initialization\n");
1560 return -EINVAL;
1561 }
1562 1567
1563 DRM_DEBUG("idx=%d s=%d e=%d d=%d\n", 1568 DRM_DEBUG("idx=%d s=%d e=%d d=%d\n",
1564 indirect->idx, indirect->start, indirect->end, 1569 indirect->idx, indirect->start, indirect->end,
@@ -1620,10 +1625,7 @@ static int r128_getparam(struct drm_device *dev, void *data, struct drm_file *fi
1620 drm_r128_getparam_t *param = data; 1625 drm_r128_getparam_t *param = data;
1621 int value; 1626 int value;
1622 1627
1623 if (!dev_priv) { 1628 DEV_INIT_TEST_WITH_RETURN(dev_priv);
1624 DRM_ERROR("called with no initialization\n");
1625 return -EINVAL;
1626 }
1627 1629
1628 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); 1630 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1629 1631
diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig
index 2168d67f09a6..5982321be4d5 100644
--- a/drivers/gpu/drm/radeon/Kconfig
+++ b/drivers/gpu/drm/radeon/Kconfig
@@ -1,7 +1,6 @@
1config DRM_RADEON_KMS 1config DRM_RADEON_KMS
2 bool "Enable modesetting on radeon by default" 2 bool "Enable modesetting on radeon by default"
3 depends on DRM_RADEON 3 depends on DRM_RADEON
4 select DRM_TTM
5 help 4 help
6 Choose this option if you want kernel modesetting enabled by default, 5 Choose this option if you want kernel modesetting enabled by default,
7 and you have a new enough userspace to support this. Running old 6 and you have a new enough userspace to support this. Running old
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 013d38059943..09a28923f46e 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -3,18 +3,53 @@
3# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. 3# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
4 4
5ccflags-y := -Iinclude/drm 5ccflags-y := -Iinclude/drm
6
7hostprogs-y := mkregtable
8
9quiet_cmd_mkregtable = MKREGTABLE $@
10 cmd_mkregtable = $(obj)/mkregtable $< > $@
11
12$(obj)/rn50_reg_safe.h: $(src)/reg_srcs/rn50 $(obj)/mkregtable
13 $(call if_changed,mkregtable)
14
15$(obj)/r100_reg_safe.h: $(src)/reg_srcs/r100 $(obj)/mkregtable
16 $(call if_changed,mkregtable)
17
18$(obj)/r200_reg_safe.h: $(src)/reg_srcs/r200 $(obj)/mkregtable
19 $(call if_changed,mkregtable)
20
21$(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable
22 $(call if_changed,mkregtable)
23
24$(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable
25 $(call if_changed,mkregtable)
26
27$(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable
28 $(call if_changed,mkregtable)
29
30$(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h
31
32$(obj)/r200.o: $(obj)/r200_reg_safe.h
33
34$(obj)/rv515.o: $(obj)/rv515_reg_safe.h
35
36$(obj)/r300.o: $(obj)/r300_reg_safe.h
37
38$(obj)/rs600.o: $(obj)/rs600_reg_safe.h
39
6radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \ 40radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
7 radeon_irq.o r300_cmdbuf.o r600_cp.o 41 radeon_irq.o r300_cmdbuf.o r600_cp.o
8 42# add KMS driver
9radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \ 43radeon-y += radeon_device.o radeon_kms.o \
10 radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \ 44 radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \
11 atom.o radeon_fence.o radeon_ttm.o radeon_object.o radeon_gart.o \ 45 atom.o radeon_fence.o radeon_ttm.o radeon_object.o radeon_gart.o \
12 radeon_legacy_crtc.o radeon_legacy_encoders.o radeon_connectors.o \ 46 radeon_legacy_crtc.o radeon_legacy_encoders.o radeon_connectors.o \
13 radeon_encoders.o radeon_display.o radeon_cursor.o radeon_i2c.o \ 47 radeon_encoders.o radeon_display.o radeon_cursor.o radeon_i2c.o \
14 radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \ 48 radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \
15 radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ 49 radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \
16 rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o \ 50 rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \
17 radeon_test.o 51 r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
52 r600_blit_kms.o
18 53
19radeon-$(CONFIG_COMPAT) += radeon_ioc32.o 54radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
20 55
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index cf67928abbc8..5d402086bc47 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -2374,6 +2374,17 @@ typedef struct _ATOM_ANALOG_TV_INFO {
2374 ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; 2374 ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING];
2375} ATOM_ANALOG_TV_INFO; 2375} ATOM_ANALOG_TV_INFO;
2376 2376
2377#define MAX_SUPPORTED_TV_TIMING_V1_2 3
2378
2379typedef struct _ATOM_ANALOG_TV_INFO_V1_2 {
2380 ATOM_COMMON_TABLE_HEADER sHeader;
2381 UCHAR ucTV_SupportedStandard;
2382 UCHAR ucTV_BootUpDefaultStandard;
2383 UCHAR ucExt_TV_ASIC_ID;
2384 UCHAR ucExt_TV_ASIC_SlaveAddr;
2385 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];
2386} ATOM_ANALOG_TV_INFO_V1_2;
2387
2377/**************************************************************************/ 2388/**************************************************************************/
2378/* VRAM usage and their defintions */ 2389/* VRAM usage and their defintions */
2379 2390
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 74d034f77c6b..6a015929deee 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -31,6 +31,10 @@
31#include "atom.h" 31#include "atom.h"
32#include "atom-bits.h" 32#include "atom-bits.h"
33 33
34/* evil but including atombios.h is much worse */
35bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
37 int32_t *pixel_clock);
34static void atombios_overscan_setup(struct drm_crtc *crtc, 38static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode, 39 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode) 40 struct drm_display_mode *adjusted_mode)
@@ -89,17 +93,32 @@ static void atombios_scaler_setup(struct drm_crtc *crtc)
89 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 93 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
90 ENABLE_SCALER_PS_ALLOCATION args; 94 ENABLE_SCALER_PS_ALLOCATION args;
91 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 95 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
96
92 /* fixme - fill in enc_priv for atom dac */ 97 /* fixme - fill in enc_priv for atom dac */
93 enum radeon_tv_std tv_std = TV_STD_NTSC; 98 enum radeon_tv_std tv_std = TV_STD_NTSC;
99 bool is_tv = false, is_cv = false;
100 struct drm_encoder *encoder;
94 101
95 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 102 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
96 return; 103 return;
97 104
105 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
106 /* find tv std */
107 if (encoder->crtc == crtc) {
108 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
109 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
110 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
111 tv_std = tv_dac->tv_std;
112 is_tv = true;
113 }
114 }
115 }
116
98 memset(&args, 0, sizeof(args)); 117 memset(&args, 0, sizeof(args));
99 118
100 args.ucScaler = radeon_crtc->crtc_id; 119 args.ucScaler = radeon_crtc->crtc_id;
101 120
102 if (radeon_crtc->devices & (ATOM_DEVICE_TV_SUPPORT)) { 121 if (is_tv) {
103 switch (tv_std) { 122 switch (tv_std) {
104 case TV_STD_NTSC: 123 case TV_STD_NTSC:
105 default: 124 default:
@@ -128,7 +147,7 @@ static void atombios_scaler_setup(struct drm_crtc *crtc)
128 break; 147 break;
129 } 148 }
130 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 149 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
131 } else if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT)) { 150 } else if (is_cv) {
132 args.ucTVStandard = ATOM_TV_CV; 151 args.ucTVStandard = ATOM_TV_CV;
133 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 152 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
134 } else { 153 } else {
@@ -151,9 +170,9 @@ static void atombios_scaler_setup(struct drm_crtc *crtc)
151 } 170 }
152 } 171 }
153 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 172 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
154 if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT) 173 if ((is_tv || is_cv)
155 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_RV570) { 174 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
156 atom_rv515_force_tv_scaler(rdev); 175 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
157 } 176 }
158} 177}
159 178
@@ -370,6 +389,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
370 pll_flags |= RADEON_PLL_USE_REF_DIV; 389 pll_flags |= RADEON_PLL_USE_REF_DIV;
371 } 390 }
372 radeon_encoder = to_radeon_encoder(encoder); 391 radeon_encoder = to_radeon_encoder(encoder);
392 break;
373 } 393 }
374 } 394 }
375 395
@@ -468,6 +488,11 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
468 } 488 }
469 489
470 switch (crtc->fb->bits_per_pixel) { 490 switch (crtc->fb->bits_per_pixel) {
491 case 8:
492 fb_format =
493 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
494 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
495 break;
471 case 15: 496 case 15:
472 fb_format = 497 fb_format =
473 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 498 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
@@ -551,42 +576,68 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
551 struct radeon_device *rdev = dev->dev_private; 576 struct radeon_device *rdev = dev->dev_private;
552 struct drm_encoder *encoder; 577 struct drm_encoder *encoder;
553 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing; 578 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
579 int need_tv_timings = 0;
580 bool ret;
554 581
555 /* TODO color tiling */ 582 /* TODO color tiling */
556 memset(&crtc_timing, 0, sizeof(crtc_timing)); 583 memset(&crtc_timing, 0, sizeof(crtc_timing));
557 584
558 /* TODO tv */
559 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 585 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
560 586 /* find tv std */
587 if (encoder->crtc == crtc) {
588 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
589
590 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
591 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
592 if (tv_dac) {
593 if (tv_dac->tv_std == TV_STD_NTSC ||
594 tv_dac->tv_std == TV_STD_NTSC_J ||
595 tv_dac->tv_std == TV_STD_PAL_M)
596 need_tv_timings = 1;
597 else
598 need_tv_timings = 2;
599 break;
600 }
601 }
602 }
561 } 603 }
562 604
563 crtc_timing.ucCRTC = radeon_crtc->crtc_id; 605 crtc_timing.ucCRTC = radeon_crtc->crtc_id;
564 crtc_timing.usH_Total = adjusted_mode->crtc_htotal; 606 if (need_tv_timings) {
565 crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay; 607 ret = radeon_atom_get_tv_timings(rdev, need_tv_timings - 1,
566 crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start; 608 &crtc_timing, &adjusted_mode->clock);
567 crtc_timing.usH_SyncWidth = 609 if (ret == false)
568 adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 610 need_tv_timings = 0;
611 }
569 612
570 crtc_timing.usV_Total = adjusted_mode->crtc_vtotal; 613 if (!need_tv_timings) {
571 crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay; 614 crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
572 crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start; 615 crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
573 crtc_timing.usV_SyncWidth = 616 crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
574 adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; 617 crtc_timing.usH_SyncWidth =
618 adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
575 619
576 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 620 crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
577 crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY; 621 crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
622 crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
623 crtc_timing.usV_SyncWidth =
624 adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
578 625
579 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 626 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
580 crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY; 627 crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
581 628
582 if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) 629 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
583 crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC; 630 crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
584 631
585 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 632 if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
586 crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE; 633 crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
587 634
588 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 635 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
589 crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE; 636 crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
637
638 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
639 crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
640 }
590 641
591 atombios_crtc_set_pll(crtc, adjusted_mode); 642 atombios_crtc_set_pll(crtc, adjusted_mode);
592 atombios_crtc_set_timing(crtc, &crtc_timing); 643 atombios_crtc_set_timing(crtc, &crtc_timing);
diff --git a/drivers/gpu/drm/radeon/avivod.h b/drivers/gpu/drm/radeon/avivod.h
new file mode 100644
index 000000000000..e2b92c445bab
--- /dev/null
+++ b/drivers/gpu/drm/radeon/avivod.h
@@ -0,0 +1,69 @@
1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 * Jerome Glisse
26 */
27#ifndef AVIVOD_H
28#define AVIVOD_H
29
30
31#define D1CRTC_CONTROL 0x6080
32#define CRTC_EN (1 << 0)
33#define D1CRTC_UPDATE_LOCK 0x60E8
34#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
35#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
36
37#define D2CRTC_CONTROL 0x6880
38#define D2CRTC_UPDATE_LOCK 0x68E8
39#define D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
40#define D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
41
42#define D1VGA_CONTROL 0x0330
43#define DVGA_CONTROL_MODE_ENABLE (1 << 0)
44#define DVGA_CONTROL_TIMING_SELECT (1 << 8)
45#define DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9)
46#define DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10)
47#define DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16)
48#define DVGA_CONTROL_ROTATE (1 << 24)
49#define D2VGA_CONTROL 0x0338
50
51#define VGA_HDP_CONTROL 0x328
52#define VGA_MEM_PAGE_SELECT_EN (1 << 0)
53#define VGA_MEMORY_DISABLE (1 << 4)
54#define VGA_RBBM_LOCK_DISABLE (1 << 8)
55#define VGA_SOFT_RESET (1 << 16)
56#define VGA_MEMORY_BASE_ADDRESS 0x0310
57#define VGA_RENDER_CONTROL 0x0300
58#define VGA_VSTATUS_CNTL_MASK 0x00030000
59
60/* AVIVO disable VGA rendering */
61static inline void radeon_avivo_vga_render_disable(struct radeon_device *rdev)
62{
63 u32 vga_render;
64 vga_render = RREG32(VGA_RENDER_CONTROL);
65 vga_render &= ~VGA_VSTATUS_CNTL_MASK;
66 WREG32(VGA_RENDER_CONTROL, vga_render);
67}
68
69#endif
diff --git a/drivers/gpu/drm/radeon/mkregtable.c b/drivers/gpu/drm/radeon/mkregtable.c
new file mode 100644
index 000000000000..fb211e585dea
--- /dev/null
+++ b/drivers/gpu/drm/radeon/mkregtable.c
@@ -0,0 +1,720 @@
1/* utility to create the register check tables
2 * this includes inlined list.h safe for userspace.
3 *
4 * Copyright 2009 Jerome Glisse
5 * Copyright 2009 Red Hat Inc.
6 *
7 * Authors:
8 * Jerome Glisse
9 * Dave Airlie
10 */
11
12#include <sys/types.h>
13#include <stdlib.h>
14#include <string.h>
15#include <stdio.h>
16#include <regex.h>
17#include <libgen.h>
18
19#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
20/**
21 * container_of - cast a member of a structure out to the containing structure
22 * @ptr: the pointer to the member.
23 * @type: the type of the container struct this is embedded in.
24 * @member: the name of the member within the struct.
25 *
26 */
27#define container_of(ptr, type, member) ({ \
28 const typeof(((type *)0)->member)*__mptr = (ptr); \
29 (type *)((char *)__mptr - offsetof(type, member)); })
30
31/*
32 * Simple doubly linked list implementation.
33 *
34 * Some of the internal functions ("__xxx") are useful when
35 * manipulating whole lists rather than single entries, as
36 * sometimes we already know the next/prev entries and we can
37 * generate better code by using them directly rather than
38 * using the generic single-entry routines.
39 */
40
41struct list_head {
42 struct list_head *next, *prev;
43};
44
45#define LIST_HEAD_INIT(name) { &(name), &(name) }
46
47#define LIST_HEAD(name) \
48 struct list_head name = LIST_HEAD_INIT(name)
49
50static inline void INIT_LIST_HEAD(struct list_head *list)
51{
52 list->next = list;
53 list->prev = list;
54}
55
56/*
57 * Insert a new entry between two known consecutive entries.
58 *
59 * This is only for internal list manipulation where we know
60 * the prev/next entries already!
61 */
62#ifndef CONFIG_DEBUG_LIST
63static inline void __list_add(struct list_head *new,
64 struct list_head *prev, struct list_head *next)
65{
66 next->prev = new;
67 new->next = next;
68 new->prev = prev;
69 prev->next = new;
70}
71#else
72extern void __list_add(struct list_head *new,
73 struct list_head *prev, struct list_head *next);
74#endif
75
76/**
77 * list_add - add a new entry
78 * @new: new entry to be added
79 * @head: list head to add it after
80 *
81 * Insert a new entry after the specified head.
82 * This is good for implementing stacks.
83 */
84static inline void list_add(struct list_head *new, struct list_head *head)
85{
86 __list_add(new, head, head->next);
87}
88
89/**
90 * list_add_tail - add a new entry
91 * @new: new entry to be added
92 * @head: list head to add it before
93 *
94 * Insert a new entry before the specified head.
95 * This is useful for implementing queues.
96 */
97static inline void list_add_tail(struct list_head *new, struct list_head *head)
98{
99 __list_add(new, head->prev, head);
100}
101
102/*
103 * Delete a list entry by making the prev/next entries
104 * point to each other.
105 *
106 * This is only for internal list manipulation where we know
107 * the prev/next entries already!
108 */
109static inline void __list_del(struct list_head *prev, struct list_head *next)
110{
111 next->prev = prev;
112 prev->next = next;
113}
114
115/**
116 * list_del - deletes entry from list.
117 * @entry: the element to delete from the list.
118 * Note: list_empty() on entry does not return true after this, the entry is
119 * in an undefined state.
120 */
121#ifndef CONFIG_DEBUG_LIST
122static inline void list_del(struct list_head *entry)
123{
124 __list_del(entry->prev, entry->next);
125 entry->next = (void *)0xDEADBEEF;
126 entry->prev = (void *)0xBEEFDEAD;
127}
128#else
129extern void list_del(struct list_head *entry);
130#endif
131
132/**
133 * list_replace - replace old entry by new one
134 * @old : the element to be replaced
135 * @new : the new element to insert
136 *
137 * If @old was empty, it will be overwritten.
138 */
139static inline void list_replace(struct list_head *old, struct list_head *new)
140{
141 new->next = old->next;
142 new->next->prev = new;
143 new->prev = old->prev;
144 new->prev->next = new;
145}
146
147static inline void list_replace_init(struct list_head *old,
148 struct list_head *new)
149{
150 list_replace(old, new);
151 INIT_LIST_HEAD(old);
152}
153
154/**
155 * list_del_init - deletes entry from list and reinitialize it.
156 * @entry: the element to delete from the list.
157 */
158static inline void list_del_init(struct list_head *entry)
159{
160 __list_del(entry->prev, entry->next);
161 INIT_LIST_HEAD(entry);
162}
163
164/**
165 * list_move - delete from one list and add as another's head
166 * @list: the entry to move
167 * @head: the head that will precede our entry
168 */
169static inline void list_move(struct list_head *list, struct list_head *head)
170{
171 __list_del(list->prev, list->next);
172 list_add(list, head);
173}
174
175/**
176 * list_move_tail - delete from one list and add as another's tail
177 * @list: the entry to move
178 * @head: the head that will follow our entry
179 */
180static inline void list_move_tail(struct list_head *list,
181 struct list_head *head)
182{
183 __list_del(list->prev, list->next);
184 list_add_tail(list, head);
185}
186
187/**
188 * list_is_last - tests whether @list is the last entry in list @head
189 * @list: the entry to test
190 * @head: the head of the list
191 */
192static inline int list_is_last(const struct list_head *list,
193 const struct list_head *head)
194{
195 return list->next == head;
196}
197
198/**
199 * list_empty - tests whether a list is empty
200 * @head: the list to test.
201 */
202static inline int list_empty(const struct list_head *head)
203{
204 return head->next == head;
205}
206
207/**
208 * list_empty_careful - tests whether a list is empty and not being modified
209 * @head: the list to test
210 *
211 * Description:
212 * tests whether a list is empty _and_ checks that no other CPU might be
213 * in the process of modifying either member (next or prev)
214 *
215 * NOTE: using list_empty_careful() without synchronization
216 * can only be safe if the only activity that can happen
217 * to the list entry is list_del_init(). Eg. it cannot be used
218 * if another CPU could re-list_add() it.
219 */
220static inline int list_empty_careful(const struct list_head *head)
221{
222 struct list_head *next = head->next;
223 return (next == head) && (next == head->prev);
224}
225
226/**
227 * list_is_singular - tests whether a list has just one entry.
228 * @head: the list to test.
229 */
230static inline int list_is_singular(const struct list_head *head)
231{
232 return !list_empty(head) && (head->next == head->prev);
233}
234
235static inline void __list_cut_position(struct list_head *list,
236 struct list_head *head,
237 struct list_head *entry)
238{
239 struct list_head *new_first = entry->next;
240 list->next = head->next;
241 list->next->prev = list;
242 list->prev = entry;
243 entry->next = list;
244 head->next = new_first;
245 new_first->prev = head;
246}
247
248/**
249 * list_cut_position - cut a list into two
250 * @list: a new list to add all removed entries
251 * @head: a list with entries
252 * @entry: an entry within head, could be the head itself
253 * and if so we won't cut the list
254 *
255 * This helper moves the initial part of @head, up to and
256 * including @entry, from @head to @list. You should
257 * pass on @entry an element you know is on @head. @list
258 * should be an empty list or a list you do not care about
259 * losing its data.
260 *
261 */
262static inline void list_cut_position(struct list_head *list,
263 struct list_head *head,
264 struct list_head *entry)
265{
266 if (list_empty(head))
267 return;
268 if (list_is_singular(head) && (head->next != entry && head != entry))
269 return;
270 if (entry == head)
271 INIT_LIST_HEAD(list);
272 else
273 __list_cut_position(list, head, entry);
274}
275
276static inline void __list_splice(const struct list_head *list,
277 struct list_head *prev, struct list_head *next)
278{
279 struct list_head *first = list->next;
280 struct list_head *last = list->prev;
281
282 first->prev = prev;
283 prev->next = first;
284
285 last->next = next;
286 next->prev = last;
287}
288
289/**
290 * list_splice - join two lists, this is designed for stacks
291 * @list: the new list to add.
292 * @head: the place to add it in the first list.
293 */
294static inline void list_splice(const struct list_head *list,
295 struct list_head *head)
296{
297 if (!list_empty(list))
298 __list_splice(list, head, head->next);
299}
300
301/**
302 * list_splice_tail - join two lists, each list being a queue
303 * @list: the new list to add.
304 * @head: the place to add it in the first list.
305 */
306static inline void list_splice_tail(struct list_head *list,
307 struct list_head *head)
308{
309 if (!list_empty(list))
310 __list_splice(list, head->prev, head);
311}
312
313/**
314 * list_splice_init - join two lists and reinitialise the emptied list.
315 * @list: the new list to add.
316 * @head: the place to add it in the first list.
317 *
318 * The list at @list is reinitialised
319 */
320static inline void list_splice_init(struct list_head *list,
321 struct list_head *head)
322{
323 if (!list_empty(list)) {
324 __list_splice(list, head, head->next);
325 INIT_LIST_HEAD(list);
326 }
327}
328
329/**
330 * list_splice_tail_init - join two lists and reinitialise the emptied list
331 * @list: the new list to add.
332 * @head: the place to add it in the first list.
333 *
334 * Each of the lists is a queue.
335 * The list at @list is reinitialised
336 */
337static inline void list_splice_tail_init(struct list_head *list,
338 struct list_head *head)
339{
340 if (!list_empty(list)) {
341 __list_splice(list, head->prev, head);
342 INIT_LIST_HEAD(list);
343 }
344}
345
346/**
347 * list_entry - get the struct for this entry
348 * @ptr: the &struct list_head pointer.
349 * @type: the type of the struct this is embedded in.
350 * @member: the name of the list_struct within the struct.
351 */
352#define list_entry(ptr, type, member) \
353 container_of(ptr, type, member)
354
355/**
356 * list_first_entry - get the first element from a list
357 * @ptr: the list head to take the element from.
358 * @type: the type of the struct this is embedded in.
359 * @member: the name of the list_struct within the struct.
360 *
361 * Note, that list is expected to be not empty.
362 */
363#define list_first_entry(ptr, type, member) \
364 list_entry((ptr)->next, type, member)
365
366/**
367 * list_for_each - iterate over a list
368 * @pos: the &struct list_head to use as a loop cursor.
369 * @head: the head for your list.
370 */
371#define list_for_each(pos, head) \
372 for (pos = (head)->next; prefetch(pos->next), pos != (head); \
373 pos = pos->next)
374
375/**
376 * __list_for_each - iterate over a list
377 * @pos: the &struct list_head to use as a loop cursor.
378 * @head: the head for your list.
379 *
380 * This variant differs from list_for_each() in that it's the
381 * simplest possible list iteration code, no prefetching is done.
382 * Use this for code that knows the list to be very short (empty
383 * or 1 entry) most of the time.
384 */
385#define __list_for_each(pos, head) \
386 for (pos = (head)->next; pos != (head); pos = pos->next)
387
388/**
389 * list_for_each_prev - iterate over a list backwards
390 * @pos: the &struct list_head to use as a loop cursor.
391 * @head: the head for your list.
392 */
393#define list_for_each_prev(pos, head) \
394 for (pos = (head)->prev; prefetch(pos->prev), pos != (head); \
395 pos = pos->prev)
396
397/**
398 * list_for_each_safe - iterate over a list safe against removal of list entry
399 * @pos: the &struct list_head to use as a loop cursor.
400 * @n: another &struct list_head to use as temporary storage
401 * @head: the head for your list.
402 */
403#define list_for_each_safe(pos, n, head) \
404 for (pos = (head)->next, n = pos->next; pos != (head); \
405 pos = n, n = pos->next)
406
407/**
408 * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry
409 * @pos: the &struct list_head to use as a loop cursor.
410 * @n: another &struct list_head to use as temporary storage
411 * @head: the head for your list.
412 */
413#define list_for_each_prev_safe(pos, n, head) \
414 for (pos = (head)->prev, n = pos->prev; \
415 prefetch(pos->prev), pos != (head); \
416 pos = n, n = pos->prev)
417
418/**
419 * list_for_each_entry - iterate over list of given type
420 * @pos: the type * to use as a loop cursor.
421 * @head: the head for your list.
422 * @member: the name of the list_struct within the struct.
423 */
424#define list_for_each_entry(pos, head, member) \
425 for (pos = list_entry((head)->next, typeof(*pos), member); \
426 &pos->member != (head); \
427 pos = list_entry(pos->member.next, typeof(*pos), member))
428
429/**
430 * list_for_each_entry_reverse - iterate backwards over list of given type.
431 * @pos: the type * to use as a loop cursor.
432 * @head: the head for your list.
433 * @member: the name of the list_struct within the struct.
434 */
435#define list_for_each_entry_reverse(pos, head, member) \
436 for (pos = list_entry((head)->prev, typeof(*pos), member); \
437 prefetch(pos->member.prev), &pos->member != (head); \
438 pos = list_entry(pos->member.prev, typeof(*pos), member))
439
440/**
441 * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue()
442 * @pos: the type * to use as a start point
443 * @head: the head of the list
444 * @member: the name of the list_struct within the struct.
445 *
446 * Prepares a pos entry for use as a start point in list_for_each_entry_continue().
447 */
448#define list_prepare_entry(pos, head, member) \
449 ((pos) ? : list_entry(head, typeof(*pos), member))
450
451/**
452 * list_for_each_entry_continue - continue iteration over list of given type
453 * @pos: the type * to use as a loop cursor.
454 * @head: the head for your list.
455 * @member: the name of the list_struct within the struct.
456 *
457 * Continue to iterate over list of given type, continuing after
458 * the current position.
459 */
460#define list_for_each_entry_continue(pos, head, member) \
461 for (pos = list_entry(pos->member.next, typeof(*pos), member); \
462 prefetch(pos->member.next), &pos->member != (head); \
463 pos = list_entry(pos->member.next, typeof(*pos), member))
464
465/**
466 * list_for_each_entry_continue_reverse - iterate backwards from the given point
467 * @pos: the type * to use as a loop cursor.
468 * @head: the head for your list.
469 * @member: the name of the list_struct within the struct.
470 *
471 * Start to iterate over list of given type backwards, continuing after
472 * the current position.
473 */
474#define list_for_each_entry_continue_reverse(pos, head, member) \
475 for (pos = list_entry(pos->member.prev, typeof(*pos), member); \
476 prefetch(pos->member.prev), &pos->member != (head); \
477 pos = list_entry(pos->member.prev, typeof(*pos), member))
478
479/**
480 * list_for_each_entry_from - iterate over list of given type from the current point
481 * @pos: the type * to use as a loop cursor.
482 * @head: the head for your list.
483 * @member: the name of the list_struct within the struct.
484 *
485 * Iterate over list of given type, continuing from current position.
486 */
487#define list_for_each_entry_from(pos, head, member) \
488 for (; prefetch(pos->member.next), &pos->member != (head); \
489 pos = list_entry(pos->member.next, typeof(*pos), member))
490
491/**
492 * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry
493 * @pos: the type * to use as a loop cursor.
494 * @n: another type * to use as temporary storage
495 * @head: the head for your list.
496 * @member: the name of the list_struct within the struct.
497 */
498#define list_for_each_entry_safe(pos, n, head, member) \
499 for (pos = list_entry((head)->next, typeof(*pos), member), \
500 n = list_entry(pos->member.next, typeof(*pos), member); \
501 &pos->member != (head); \
502 pos = n, n = list_entry(n->member.next, typeof(*n), member))
503
504/**
505 * list_for_each_entry_safe_continue
506 * @pos: the type * to use as a loop cursor.
507 * @n: another type * to use as temporary storage
508 * @head: the head for your list.
509 * @member: the name of the list_struct within the struct.
510 *
511 * Iterate over list of given type, continuing after current point,
512 * safe against removal of list entry.
513 */
514#define list_for_each_entry_safe_continue(pos, n, head, member) \
515 for (pos = list_entry(pos->member.next, typeof(*pos), member), \
516 n = list_entry(pos->member.next, typeof(*pos), member); \
517 &pos->member != (head); \
518 pos = n, n = list_entry(n->member.next, typeof(*n), member))
519
520/**
521 * list_for_each_entry_safe_from
522 * @pos: the type * to use as a loop cursor.
523 * @n: another type * to use as temporary storage
524 * @head: the head for your list.
525 * @member: the name of the list_struct within the struct.
526 *
527 * Iterate over list of given type from current point, safe against
528 * removal of list entry.
529 */
530#define list_for_each_entry_safe_from(pos, n, head, member) \
531 for (n = list_entry(pos->member.next, typeof(*pos), member); \
532 &pos->member != (head); \
533 pos = n, n = list_entry(n->member.next, typeof(*n), member))
534
535/**
536 * list_for_each_entry_safe_reverse
537 * @pos: the type * to use as a loop cursor.
538 * @n: another type * to use as temporary storage
539 * @head: the head for your list.
540 * @member: the name of the list_struct within the struct.
541 *
542 * Iterate backwards over list of given type, safe against removal
543 * of list entry.
544 */
545#define list_for_each_entry_safe_reverse(pos, n, head, member) \
546 for (pos = list_entry((head)->prev, typeof(*pos), member), \
547 n = list_entry(pos->member.prev, typeof(*pos), member); \
548 &pos->member != (head); \
549 pos = n, n = list_entry(n->member.prev, typeof(*n), member))
550
551struct offset {
552 struct list_head list;
553 unsigned offset;
554};
555
556struct table {
557 struct list_head offsets;
558 unsigned offset_max;
559 unsigned nentry;
560 unsigned *table;
561 char *gpu_prefix;
562};
563
564struct offset *offset_new(unsigned o)
565{
566 struct offset *offset;
567
568 offset = (struct offset *)malloc(sizeof(struct offset));
569 if (offset) {
570 INIT_LIST_HEAD(&offset->list);
571 offset->offset = o;
572 }
573 return offset;
574}
575
576void table_offset_add(struct table *t, struct offset *offset)
577{
578 list_add_tail(&offset->list, &t->offsets);
579}
580
581void table_init(struct table *t)
582{
583 INIT_LIST_HEAD(&t->offsets);
584 t->offset_max = 0;
585 t->nentry = 0;
586 t->table = NULL;
587}
588
589void table_print(struct table *t)
590{
591 unsigned nlloop, i, j, n, c, id;
592
593 nlloop = (t->nentry + 3) / 4;
594 c = t->nentry;
595 printf("static const unsigned %s_reg_safe_bm[%d] = {\n", t->gpu_prefix,
596 t->nentry);
597 for (i = 0, id = 0; i < nlloop; i++) {
598 n = 4;
599 if (n > c)
600 n = c;
601 c -= n;
602 for (j = 0; j < n; j++) {
603 if (j == 0)
604 printf("\t");
605 else
606 printf(" ");
607 printf("0x%08X,", t->table[id++]);
608 }
609 printf("\n");
610 }
611 printf("};\n");
612}
613
614int table_build(struct table *t)
615{
616 struct offset *offset;
617 unsigned i, m;
618
619 t->nentry = ((t->offset_max >> 2) + 31) / 32;
620 t->table = (unsigned *)malloc(sizeof(unsigned) * t->nentry);
621 if (t->table == NULL)
622 return -1;
623 memset(t->table, 0xff, sizeof(unsigned) * t->nentry);
624 list_for_each_entry(offset, &t->offsets, list) {
625 i = (offset->offset >> 2) / 32;
626 m = (offset->offset >> 2) & 31;
627 m = 1 << m;
628 t->table[i] ^= m;
629 }
630 return 0;
631}
632
633static char gpu_name[10];
634int parser_auth(struct table *t, const char *filename)
635{
636 FILE *file;
637 regex_t mask_rex;
638 regmatch_t match[4];
639 char buf[1024];
640 size_t end;
641 int len;
642 int done = 0;
643 int r;
644 unsigned o;
645 struct offset *offset;
646 char last_reg_s[10];
647 int last_reg;
648
649 if (regcomp
650 (&mask_rex, "(0x[0-9a-fA-F]*) *([_a-zA-Z0-9]*)", REG_EXTENDED)) {
651 fprintf(stderr, "Failed to compile regular expression\n");
652 return -1;
653 }
654 file = fopen(filename, "r");
655 if (file == NULL) {
656 fprintf(stderr, "Failed to open: %s\n", filename);
657 return -1;
658 }
659 fseek(file, 0, SEEK_END);
660 end = ftell(file);
661 fseek(file, 0, SEEK_SET);
662
663 /* get header */
664 if (fgets(buf, 1024, file) == NULL)
665 return -1;
666
667 /* first line will contain the last register
668 * and gpu name */
669 sscanf(buf, "%s %s", gpu_name, last_reg_s);
670 t->gpu_prefix = gpu_name;
671 last_reg = strtol(last_reg_s, NULL, 16);
672
673 do {
674 if (fgets(buf, 1024, file) == NULL)
675 return -1;
676 len = strlen(buf);
677 if (ftell(file) == end)
678 done = 1;
679 if (len) {
680 r = regexec(&mask_rex, buf, 4, match, 0);
681 if (r == REG_NOMATCH) {
682 } else if (r) {
683 fprintf(stderr,
684 "Error matching regular expression %d in %s\n",
685 r, filename);
686 return -1;
687 } else {
688 buf[match[0].rm_eo] = 0;
689 buf[match[1].rm_eo] = 0;
690 buf[match[2].rm_eo] = 0;
691 o = strtol(&buf[match[1].rm_so], NULL, 16);
692 offset = offset_new(o);
693 table_offset_add(t, offset);
694 if (o > t->offset_max)
695 t->offset_max = o;
696 }
697 }
698 } while (!done);
699 fclose(file);
700 if (t->offset_max < last_reg)
701 t->offset_max = last_reg;
702 return table_build(t);
703}
704
705int main(int argc, char *argv[])
706{
707 struct table t;
708
709 if (argc != 2) {
710 fprintf(stderr, "Usage: %s <authfile>\n", argv[0]);
711 exit(1);
712 }
713 table_init(&t);
714 if (parser_auth(&t, argv[1])) {
715 fprintf(stderr, "Failed to parse file %s\n", argv[1]);
716 return -1;
717 }
718 table_print(&t);
719 return 0;
720}
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 68e728e8be4d..be51c5f7d0f6 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -29,15 +29,41 @@
29#include "drmP.h" 29#include "drmP.h"
30#include "drm.h" 30#include "drm.h"
31#include "radeon_drm.h" 31#include "radeon_drm.h"
32#include "radeon_microcode.h"
33#include "radeon_reg.h" 32#include "radeon_reg.h"
34#include "radeon.h" 33#include "radeon.h"
34#include "r100d.h"
35
36#include <linux/firmware.h>
37#include <linux/platform_device.h>
38
39#include "r100_reg_safe.h"
40#include "rn50_reg_safe.h"
41
42/* Firmware Names */
43#define FIRMWARE_R100 "radeon/R100_cp.bin"
44#define FIRMWARE_R200 "radeon/R200_cp.bin"
45#define FIRMWARE_R300 "radeon/R300_cp.bin"
46#define FIRMWARE_R420 "radeon/R420_cp.bin"
47#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
48#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
49#define FIRMWARE_R520 "radeon/R520_cp.bin"
50
51MODULE_FIRMWARE(FIRMWARE_R100);
52MODULE_FIRMWARE(FIRMWARE_R200);
53MODULE_FIRMWARE(FIRMWARE_R300);
54MODULE_FIRMWARE(FIRMWARE_R420);
55MODULE_FIRMWARE(FIRMWARE_RS690);
56MODULE_FIRMWARE(FIRMWARE_RS600);
57MODULE_FIRMWARE(FIRMWARE_R520);
58
59#include "r100_track.h"
35 60
36/* This files gather functions specifics to: 61/* This files gather functions specifics to:
37 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 62 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
38 * 63 *
39 * Some of these functions might be used by newer ASICs. 64 * Some of these functions might be used by newer ASICs.
40 */ 65 */
66int r200_init(struct radeon_device *rdev);
41void r100_hdp_reset(struct radeon_device *rdev); 67void r100_hdp_reset(struct radeon_device *rdev);
42void r100_gpu_init(struct radeon_device *rdev); 68void r100_gpu_init(struct radeon_device *rdev);
43int r100_gui_wait_for_idle(struct radeon_device *rdev); 69int r100_gui_wait_for_idle(struct radeon_device *rdev);
@@ -58,23 +84,28 @@ void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
58 * could end up in wrong address. */ 84 * could end up in wrong address. */
59} 85}
60 86
61int r100_pci_gart_enable(struct radeon_device *rdev) 87int r100_pci_gart_init(struct radeon_device *rdev)
62{ 88{
63 uint32_t tmp;
64 int r; 89 int r;
65 90
91 if (rdev->gart.table.ram.ptr) {
92 WARN(1, "R100 PCI GART already initialized.\n");
93 return 0;
94 }
66 /* Initialize common gart structure */ 95 /* Initialize common gart structure */
67 r = radeon_gart_init(rdev); 96 r = radeon_gart_init(rdev);
68 if (r) { 97 if (r)
69 return r; 98 return r;
70 } 99 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
71 if (rdev->gart.table.ram.ptr == NULL) { 100 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
72 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 101 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
73 r = radeon_gart_table_ram_alloc(rdev); 102 return radeon_gart_table_ram_alloc(rdev);
74 if (r) { 103}
75 return r; 104
76 } 105int r100_pci_gart_enable(struct radeon_device *rdev)
77 } 106{
107 uint32_t tmp;
108
78 /* discard memory request outside of configured range */ 109 /* discard memory request outside of configured range */
79 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 110 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
80 WREG32(RADEON_AIC_CNTL, tmp); 111 WREG32(RADEON_AIC_CNTL, tmp);
@@ -114,13 +145,11 @@ int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
114 return 0; 145 return 0;
115} 146}
116 147
117int r100_gart_enable(struct radeon_device *rdev) 148void r100_pci_gart_fini(struct radeon_device *rdev)
118{ 149{
119 if (rdev->flags & RADEON_IS_AGP) { 150 r100_pci_gart_disable(rdev);
120 r100_pci_gart_disable(rdev); 151 radeon_gart_table_ram_free(rdev);
121 return 0; 152 radeon_gart_fini(rdev);
122 }
123 return r100_pci_gart_enable(rdev);
124} 153}
125 154
126 155
@@ -247,9 +276,6 @@ int r100_mc_init(struct radeon_device *rdev)
247 276
248void r100_mc_fini(struct radeon_device *rdev) 277void r100_mc_fini(struct radeon_device *rdev)
249{ 278{
250 r100_pci_gart_disable(rdev);
251 radeon_gart_table_ram_free(rdev);
252 radeon_gart_fini(rdev);
253} 279}
254 280
255 281
@@ -273,6 +299,17 @@ int r100_irq_set(struct radeon_device *rdev)
273 return 0; 299 return 0;
274} 300}
275 301
302void r100_irq_disable(struct radeon_device *rdev)
303{
304 u32 tmp;
305
306 WREG32(R_000040_GEN_INT_CNTL, 0);
307 /* Wait and acknowledge irq */
308 mdelay(1);
309 tmp = RREG32(R_000044_GEN_INT_STATUS);
310 WREG32(R_000044_GEN_INT_STATUS, tmp);
311}
312
276static inline uint32_t r100_irq_ack(struct radeon_device *rdev) 313static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
277{ 314{
278 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 315 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
@@ -293,6 +330,9 @@ int r100_irq_process(struct radeon_device *rdev)
293 if (!status) { 330 if (!status) {
294 return IRQ_NONE; 331 return IRQ_NONE;
295 } 332 }
333 if (rdev->shutdown) {
334 return IRQ_NONE;
335 }
296 while (status) { 336 while (status) {
297 /* SW interrupt */ 337 /* SW interrupt */
298 if (status & RADEON_SW_INT_TEST) { 338 if (status & RADEON_SW_INT_TEST) {
@@ -367,14 +407,21 @@ int r100_wb_init(struct radeon_device *rdev)
367 return r; 407 return r;
368 } 408 }
369 } 409 }
370 WREG32(0x774, rdev->wb.gpu_addr); 410 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
371 WREG32(0x70C, rdev->wb.gpu_addr + 1024); 411 WREG32(R_00070C_CP_RB_RPTR_ADDR,
372 WREG32(0x770, 0xff); 412 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
413 WREG32(R_000770_SCRATCH_UMSK, 0xff);
373 return 0; 414 return 0;
374} 415}
375 416
417void r100_wb_disable(struct radeon_device *rdev)
418{
419 WREG32(R_000770_SCRATCH_UMSK, 0);
420}
421
376void r100_wb_fini(struct radeon_device *rdev) 422void r100_wb_fini(struct radeon_device *rdev)
377{ 423{
424 r100_wb_disable(rdev);
378 if (rdev->wb.wb_obj) { 425 if (rdev->wb.wb_obj) {
379 radeon_object_kunmap(rdev->wb.wb_obj); 426 radeon_object_kunmap(rdev->wb.wb_obj);
380 radeon_object_unpin(rdev->wb.wb_obj); 427 radeon_object_unpin(rdev->wb.wb_obj);
@@ -461,6 +508,21 @@ int r100_copy_blit(struct radeon_device *rdev,
461/* 508/*
462 * CP 509 * CP
463 */ 510 */
511static int r100_cp_wait_for_idle(struct radeon_device *rdev)
512{
513 unsigned i;
514 u32 tmp;
515
516 for (i = 0; i < rdev->usec_timeout; i++) {
517 tmp = RREG32(R_000E40_RBBM_STATUS);
518 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
519 return 0;
520 }
521 udelay(1);
522 }
523 return -1;
524}
525
464void r100_ring_start(struct radeon_device *rdev) 526void r100_ring_start(struct radeon_device *rdev)
465{ 527{
466 int r; 528 int r;
@@ -478,33 +540,33 @@ void r100_ring_start(struct radeon_device *rdev)
478 radeon_ring_unlock_commit(rdev); 540 radeon_ring_unlock_commit(rdev);
479} 541}
480 542
481static void r100_cp_load_microcode(struct radeon_device *rdev) 543
544/* Load the microcode for the CP */
545static int r100_cp_init_microcode(struct radeon_device *rdev)
482{ 546{
483 int i; 547 struct platform_device *pdev;
548 const char *fw_name = NULL;
549 int err;
484 550
485 if (r100_gui_wait_for_idle(rdev)) { 551 DRM_DEBUG("\n");
486 printk(KERN_WARNING "Failed to wait GUI idle while "
487 "programming pipes. Bad things might happen.\n");
488 }
489 552
490 WREG32(RADEON_CP_ME_RAM_ADDR, 0); 553 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
554 err = IS_ERR(pdev);
555 if (err) {
556 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
557 return -EINVAL;
558 }
491 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 559 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
492 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 560 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
493 (rdev->family == CHIP_RS200)) { 561 (rdev->family == CHIP_RS200)) {
494 DRM_INFO("Loading R100 Microcode\n"); 562 DRM_INFO("Loading R100 Microcode\n");
495 for (i = 0; i < 256; i++) { 563 fw_name = FIRMWARE_R100;
496 WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]);
497 WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]);
498 }
499 } else if ((rdev->family == CHIP_R200) || 564 } else if ((rdev->family == CHIP_R200) ||
500 (rdev->family == CHIP_RV250) || 565 (rdev->family == CHIP_RV250) ||
501 (rdev->family == CHIP_RV280) || 566 (rdev->family == CHIP_RV280) ||
502 (rdev->family == CHIP_RS300)) { 567 (rdev->family == CHIP_RS300)) {
503 DRM_INFO("Loading R200 Microcode\n"); 568 DRM_INFO("Loading R200 Microcode\n");
504 for (i = 0; i < 256; i++) { 569 fw_name = FIRMWARE_R200;
505 WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]);
506 WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]);
507 }
508 } else if ((rdev->family == CHIP_R300) || 570 } else if ((rdev->family == CHIP_R300) ||
509 (rdev->family == CHIP_R350) || 571 (rdev->family == CHIP_R350) ||
510 (rdev->family == CHIP_RV350) || 572 (rdev->family == CHIP_RV350) ||
@@ -512,31 +574,19 @@ static void r100_cp_load_microcode(struct radeon_device *rdev)
512 (rdev->family == CHIP_RS400) || 574 (rdev->family == CHIP_RS400) ||
513 (rdev->family == CHIP_RS480)) { 575 (rdev->family == CHIP_RS480)) {
514 DRM_INFO("Loading R300 Microcode\n"); 576 DRM_INFO("Loading R300 Microcode\n");
515 for (i = 0; i < 256; i++) { 577 fw_name = FIRMWARE_R300;
516 WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]);
517 WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]);
518 }
519 } else if ((rdev->family == CHIP_R420) || 578 } else if ((rdev->family == CHIP_R420) ||
520 (rdev->family == CHIP_R423) || 579 (rdev->family == CHIP_R423) ||
521 (rdev->family == CHIP_RV410)) { 580 (rdev->family == CHIP_RV410)) {
522 DRM_INFO("Loading R400 Microcode\n"); 581 DRM_INFO("Loading R400 Microcode\n");
523 for (i = 0; i < 256; i++) { 582 fw_name = FIRMWARE_R420;
524 WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]);
525 WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]);
526 }
527 } else if ((rdev->family == CHIP_RS690) || 583 } else if ((rdev->family == CHIP_RS690) ||
528 (rdev->family == CHIP_RS740)) { 584 (rdev->family == CHIP_RS740)) {
529 DRM_INFO("Loading RS690/RS740 Microcode\n"); 585 DRM_INFO("Loading RS690/RS740 Microcode\n");
530 for (i = 0; i < 256; i++) { 586 fw_name = FIRMWARE_RS690;
531 WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]);
532 WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]);
533 }
534 } else if (rdev->family == CHIP_RS600) { 587 } else if (rdev->family == CHIP_RS600) {
535 DRM_INFO("Loading RS600 Microcode\n"); 588 DRM_INFO("Loading RS600 Microcode\n");
536 for (i = 0; i < 256; i++) { 589 fw_name = FIRMWARE_RS600;
537 WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]);
538 WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]);
539 }
540 } else if ((rdev->family == CHIP_RV515) || 590 } else if ((rdev->family == CHIP_RV515) ||
541 (rdev->family == CHIP_R520) || 591 (rdev->family == CHIP_R520) ||
542 (rdev->family == CHIP_RV530) || 592 (rdev->family == CHIP_RV530) ||
@@ -544,9 +594,43 @@ static void r100_cp_load_microcode(struct radeon_device *rdev)
544 (rdev->family == CHIP_RV560) || 594 (rdev->family == CHIP_RV560) ||
545 (rdev->family == CHIP_RV570)) { 595 (rdev->family == CHIP_RV570)) {
546 DRM_INFO("Loading R500 Microcode\n"); 596 DRM_INFO("Loading R500 Microcode\n");
547 for (i = 0; i < 256; i++) { 597 fw_name = FIRMWARE_R520;
548 WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]); 598 }
549 WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]); 599
600 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
601 platform_device_unregister(pdev);
602 if (err) {
603 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
604 fw_name);
605 } else if (rdev->me_fw->size % 8) {
606 printk(KERN_ERR
607 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
608 rdev->me_fw->size, fw_name);
609 err = -EINVAL;
610 release_firmware(rdev->me_fw);
611 rdev->me_fw = NULL;
612 }
613 return err;
614}
615static void r100_cp_load_microcode(struct radeon_device *rdev)
616{
617 const __be32 *fw_data;
618 int i, size;
619
620 if (r100_gui_wait_for_idle(rdev)) {
621 printk(KERN_WARNING "Failed to wait GUI idle while "
622 "programming pipes. Bad things might happen.\n");
623 }
624
625 if (rdev->me_fw) {
626 size = rdev->me_fw->size / 4;
627 fw_data = (const __be32 *)&rdev->me_fw->data[0];
628 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
629 for (i = 0; i < size; i += 2) {
630 WREG32(RADEON_CP_ME_RAM_DATAH,
631 be32_to_cpup(&fw_data[i]));
632 WREG32(RADEON_CP_ME_RAM_DATAL,
633 be32_to_cpup(&fw_data[i + 1]));
550 } 634 }
551 } 635 }
552} 636}
@@ -585,6 +669,15 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
585 } else { 669 } else {
586 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp); 670 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
587 } 671 }
672
673 if (!rdev->me_fw) {
674 r = r100_cp_init_microcode(rdev);
675 if (r) {
676 DRM_ERROR("Failed to load firmware!\n");
677 return r;
678 }
679 }
680
588 /* Align ring size */ 681 /* Align ring size */
589 rb_bufsz = drm_order(ring_size / 8); 682 rb_bufsz = drm_order(ring_size / 8);
590 ring_size = (1 << (rb_bufsz + 1)) * 4; 683 ring_size = (1 << (rb_bufsz + 1)) * 4;
@@ -658,9 +751,11 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
658 751
659void r100_cp_fini(struct radeon_device *rdev) 752void r100_cp_fini(struct radeon_device *rdev)
660{ 753{
754 if (r100_cp_wait_for_idle(rdev)) {
755 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
756 }
661 /* Disable ring */ 757 /* Disable ring */
662 rdev->cp.ready = false; 758 r100_cp_disable(rdev);
663 WREG32(RADEON_CP_CSQ_CNTL, 0);
664 radeon_ring_fini(rdev); 759 radeon_ring_fini(rdev);
665 DRM_INFO("radeon: cp finalized\n"); 760 DRM_INFO("radeon: cp finalized\n");
666} 761}
@@ -710,6 +805,12 @@ int r100_cp_reset(struct radeon_device *rdev)
710 return -1; 805 return -1;
711} 806}
712 807
808void r100_cp_commit(struct radeon_device *rdev)
809{
810 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
811 (void)RREG32(RADEON_CP_RB_WPTR);
812}
813
713 814
714/* 815/*
715 * CS functions 816 * CS functions
@@ -968,147 +1069,356 @@ int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
968 return 0; 1069 return 0;
969} 1070}
970 1071
1072static int r100_get_vtx_size(uint32_t vtx_fmt)
1073{
1074 int vtx_size;
1075 vtx_size = 2;
1076 /* ordered according to bits in spec */
1077 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1078 vtx_size++;
1079 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1080 vtx_size += 3;
1081 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1082 vtx_size++;
1083 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1084 vtx_size++;
1085 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1086 vtx_size += 3;
1087 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1088 vtx_size++;
1089 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1090 vtx_size++;
1091 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1092 vtx_size += 2;
1093 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1094 vtx_size += 2;
1095 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1096 vtx_size++;
1097 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1098 vtx_size += 2;
1099 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1100 vtx_size++;
1101 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1102 vtx_size += 2;
1103 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1104 vtx_size++;
1105 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1106 vtx_size++;
1107 /* blend weight */
1108 if (vtx_fmt & (0x7 << 15))
1109 vtx_size += (vtx_fmt >> 15) & 0x7;
1110 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1111 vtx_size += 3;
1112 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1113 vtx_size += 2;
1114 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1115 vtx_size++;
1116 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1117 vtx_size++;
1118 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1119 vtx_size++;
1120 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1121 vtx_size++;
1122 return vtx_size;
1123}
1124
971static int r100_packet0_check(struct radeon_cs_parser *p, 1125static int r100_packet0_check(struct radeon_cs_parser *p,
972 struct radeon_cs_packet *pkt) 1126 struct radeon_cs_packet *pkt,
1127 unsigned idx, unsigned reg)
973{ 1128{
974 struct radeon_cs_chunk *ib_chunk; 1129 struct radeon_cs_chunk *ib_chunk;
975 struct radeon_cs_reloc *reloc; 1130 struct radeon_cs_reloc *reloc;
1131 struct r100_cs_track *track;
976 volatile uint32_t *ib; 1132 volatile uint32_t *ib;
977 uint32_t tmp; 1133 uint32_t tmp;
978 unsigned reg;
979 unsigned i;
980 unsigned idx;
981 bool onereg;
982 int r; 1134 int r;
1135 int i, face;
983 u32 tile_flags = 0; 1136 u32 tile_flags = 0;
984 1137
985 ib = p->ib->ptr; 1138 ib = p->ib->ptr;
986 ib_chunk = &p->chunks[p->chunk_ib_idx]; 1139 ib_chunk = &p->chunks[p->chunk_ib_idx];
987 idx = pkt->idx + 1; 1140 track = (struct r100_cs_track *)p->track;
988 reg = pkt->reg; 1141
989 onereg = false; 1142 switch (reg) {
990 if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) { 1143 case RADEON_CRTC_GUI_TRIG_VLINE:
991 onereg = true; 1144 r = r100_cs_packet_parse_vline(p);
992 } 1145 if (r) {
993 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { 1146 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
994 switch (reg) { 1147 idx, reg);
995 case RADEON_CRTC_GUI_TRIG_VLINE: 1148 r100_cs_dump_packet(p, pkt);
996 r = r100_cs_packet_parse_vline(p); 1149 return r;
997 if (r) { 1150 }
998 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1151 break;
999 idx, reg);
1000 r100_cs_dump_packet(p, pkt);
1001 return r;
1002 }
1003 break;
1004 /* FIXME: only allow PACKET3 blit? easier to check for out of 1152 /* FIXME: only allow PACKET3 blit? easier to check for out of
1005 * range access */ 1153 * range access */
1006 case RADEON_DST_PITCH_OFFSET: 1154 case RADEON_DST_PITCH_OFFSET:
1007 case RADEON_SRC_PITCH_OFFSET: 1155 case RADEON_SRC_PITCH_OFFSET:
1008 r = r100_cs_packet_next_reloc(p, &reloc); 1156 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1009 if (r) { 1157 if (r)
1010 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1158 return r;
1011 idx, reg); 1159 break;
1012 r100_cs_dump_packet(p, pkt); 1160 case RADEON_RB3D_DEPTHOFFSET:
1013 return r; 1161 r = r100_cs_packet_next_reloc(p, &reloc);
1014 } 1162 if (r) {
1015 tmp = ib_chunk->kdata[idx] & 0x003fffff; 1163 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1016 tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 1164 idx, reg);
1017 1165 r100_cs_dump_packet(p, pkt);
1018 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1166 return r;
1019 tile_flags |= RADEON_DST_TILE_MACRO; 1167 }
1020 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 1168 track->zb.robj = reloc->robj;
1021 if (reg == RADEON_SRC_PITCH_OFFSET) { 1169 track->zb.offset = ib_chunk->kdata[idx];
1022 DRM_ERROR("Cannot src blit from microtiled surface\n"); 1170 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1023 r100_cs_dump_packet(p, pkt); 1171 break;
1024 return -EINVAL; 1172 case RADEON_RB3D_COLOROFFSET:
1025 } 1173 r = r100_cs_packet_next_reloc(p, &reloc);
1026 tile_flags |= RADEON_DST_TILE_MICRO; 1174 if (r) {
1027 } 1175 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1176 idx, reg);
1177 r100_cs_dump_packet(p, pkt);
1178 return r;
1179 }
1180 track->cb[0].robj = reloc->robj;
1181 track->cb[0].offset = ib_chunk->kdata[idx];
1182 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1183 break;
1184 case RADEON_PP_TXOFFSET_0:
1185 case RADEON_PP_TXOFFSET_1:
1186 case RADEON_PP_TXOFFSET_2:
1187 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1188 r = r100_cs_packet_next_reloc(p, &reloc);
1189 if (r) {
1190 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1191 idx, reg);
1192 r100_cs_dump_packet(p, pkt);
1193 return r;
1194 }
1195 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1196 track->textures[i].robj = reloc->robj;
1197 break;
1198 case RADEON_PP_CUBIC_OFFSET_T0_0:
1199 case RADEON_PP_CUBIC_OFFSET_T0_1:
1200 case RADEON_PP_CUBIC_OFFSET_T0_2:
1201 case RADEON_PP_CUBIC_OFFSET_T0_3:
1202 case RADEON_PP_CUBIC_OFFSET_T0_4:
1203 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1204 r = r100_cs_packet_next_reloc(p, &reloc);
1205 if (r) {
1206 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1207 idx, reg);
1208 r100_cs_dump_packet(p, pkt);
1209 return r;
1210 }
1211 track->textures[0].cube_info[i].offset = ib_chunk->kdata[idx];
1212 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1213 track->textures[0].cube_info[i].robj = reloc->robj;
1214 break;
1215 case RADEON_PP_CUBIC_OFFSET_T1_0:
1216 case RADEON_PP_CUBIC_OFFSET_T1_1:
1217 case RADEON_PP_CUBIC_OFFSET_T1_2:
1218 case RADEON_PP_CUBIC_OFFSET_T1_3:
1219 case RADEON_PP_CUBIC_OFFSET_T1_4:
1220 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1221 r = r100_cs_packet_next_reloc(p, &reloc);
1222 if (r) {
1223 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1224 idx, reg);
1225 r100_cs_dump_packet(p, pkt);
1226 return r;
1227 }
1228 track->textures[1].cube_info[i].offset = ib_chunk->kdata[idx];
1229 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1230 track->textures[1].cube_info[i].robj = reloc->robj;
1231 break;
1232 case RADEON_PP_CUBIC_OFFSET_T2_0:
1233 case RADEON_PP_CUBIC_OFFSET_T2_1:
1234 case RADEON_PP_CUBIC_OFFSET_T2_2:
1235 case RADEON_PP_CUBIC_OFFSET_T2_3:
1236 case RADEON_PP_CUBIC_OFFSET_T2_4:
1237 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1238 r = r100_cs_packet_next_reloc(p, &reloc);
1239 if (r) {
1240 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1241 idx, reg);
1242 r100_cs_dump_packet(p, pkt);
1243 return r;
1244 }
1245 track->textures[2].cube_info[i].offset = ib_chunk->kdata[idx];
1246 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1247 track->textures[2].cube_info[i].robj = reloc->robj;
1248 break;
1249 case RADEON_RE_WIDTH_HEIGHT:
1250 track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF);
1251 break;
1252 case RADEON_RB3D_COLORPITCH:
1253 r = r100_cs_packet_next_reloc(p, &reloc);
1254 if (r) {
1255 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1256 idx, reg);
1257 r100_cs_dump_packet(p, pkt);
1258 return r;
1259 }
1028 1260
1029 tmp |= tile_flags; 1261 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1030 ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; 1262 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1031 break; 1263 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1032 case RADEON_RB3D_DEPTHOFFSET: 1264 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1033 case RADEON_RB3D_COLOROFFSET:
1034 case R300_RB3D_COLOROFFSET0:
1035 case R300_ZB_DEPTHOFFSET:
1036 case R200_PP_TXOFFSET_0:
1037 case R200_PP_TXOFFSET_1:
1038 case R200_PP_TXOFFSET_2:
1039 case R200_PP_TXOFFSET_3:
1040 case R200_PP_TXOFFSET_4:
1041 case R200_PP_TXOFFSET_5:
1042 case RADEON_PP_TXOFFSET_0:
1043 case RADEON_PP_TXOFFSET_1:
1044 case RADEON_PP_TXOFFSET_2:
1045 case R300_TX_OFFSET_0:
1046 case R300_TX_OFFSET_0+4:
1047 case R300_TX_OFFSET_0+8:
1048 case R300_TX_OFFSET_0+12:
1049 case R300_TX_OFFSET_0+16:
1050 case R300_TX_OFFSET_0+20:
1051 case R300_TX_OFFSET_0+24:
1052 case R300_TX_OFFSET_0+28:
1053 case R300_TX_OFFSET_0+32:
1054 case R300_TX_OFFSET_0+36:
1055 case R300_TX_OFFSET_0+40:
1056 case R300_TX_OFFSET_0+44:
1057 case R300_TX_OFFSET_0+48:
1058 case R300_TX_OFFSET_0+52:
1059 case R300_TX_OFFSET_0+56:
1060 case R300_TX_OFFSET_0+60:
1061 /* rn50 has no 3D engine so fail on any 3d setup */
1062 if (ASIC_IS_RN50(p->rdev)) {
1063 DRM_ERROR("attempt to use RN50 3D engine failed\n");
1064 return -EINVAL;
1065 }
1066 r = r100_cs_packet_next_reloc(p, &reloc);
1067 if (r) {
1068 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1069 idx, reg);
1070 r100_cs_dump_packet(p, pkt);
1071 return r;
1072 }
1073 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1074 break;
1075 case R300_RB3D_COLORPITCH0:
1076 case RADEON_RB3D_COLORPITCH:
1077 r = r100_cs_packet_next_reloc(p, &reloc);
1078 if (r) {
1079 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1080 idx, reg);
1081 r100_cs_dump_packet(p, pkt);
1082 return r;
1083 }
1084 1265
1085 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1266 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
1086 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1267 tmp |= tile_flags;
1087 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1268 ib[idx] = tmp;
1088 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1089 1269
1090 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); 1270 track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK;
1091 tmp |= tile_flags; 1271 break;
1092 ib[idx] = tmp; 1272 case RADEON_RB3D_DEPTHPITCH:
1273 track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK;
1274 break;
1275 case RADEON_RB3D_CNTL:
1276 switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1277 case 7:
1278 case 8:
1279 case 9:
1280 case 11:
1281 case 12:
1282 track->cb[0].cpp = 1;
1093 break; 1283 break;
1094 case RADEON_RB3D_ZPASS_ADDR: 1284 case 3:
1095 r = r100_cs_packet_next_reloc(p, &reloc); 1285 case 4:
1096 if (r) { 1286 case 15:
1097 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1287 track->cb[0].cpp = 2;
1098 idx, reg); 1288 break;
1099 r100_cs_dump_packet(p, pkt); 1289 case 6:
1100 return r; 1290 track->cb[0].cpp = 4;
1101 }
1102 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1103 break; 1291 break;
1104 default: 1292 default:
1105 /* FIXME: we don't want to allow anyothers packet */ 1293 DRM_ERROR("Invalid color buffer format (%d) !\n",
1294 ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1295 return -EINVAL;
1296 }
1297 track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE);
1298 break;
1299 case RADEON_RB3D_ZSTENCILCNTL:
1300 switch (ib_chunk->kdata[idx] & 0xf) {
1301 case 0:
1302 track->zb.cpp = 2;
1303 break;
1304 case 2:
1305 case 3:
1306 case 4:
1307 case 5:
1308 case 9:
1309 case 11:
1310 track->zb.cpp = 4;
1106 break; 1311 break;
1312 default:
1313 break;
1314 }
1315 break;
1316 case RADEON_RB3D_ZPASS_ADDR:
1317 r = r100_cs_packet_next_reloc(p, &reloc);
1318 if (r) {
1319 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1320 idx, reg);
1321 r100_cs_dump_packet(p, pkt);
1322 return r;
1323 }
1324 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1325 break;
1326 case RADEON_PP_CNTL:
1327 {
1328 uint32_t temp = ib_chunk->kdata[idx] >> 4;
1329 for (i = 0; i < track->num_texture; i++)
1330 track->textures[i].enabled = !!(temp & (1 << i));
1107 } 1331 }
1108 if (onereg) { 1332 break;
1109 /* FIXME: forbid onereg write to register on relocate */ 1333 case RADEON_SE_VF_CNTL:
1334 track->vap_vf_cntl = ib_chunk->kdata[idx];
1335 break;
1336 case RADEON_SE_VTX_FMT:
1337 track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx]);
1338 break;
1339 case RADEON_PP_TEX_SIZE_0:
1340 case RADEON_PP_TEX_SIZE_1:
1341 case RADEON_PP_TEX_SIZE_2:
1342 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1343 track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1;
1344 track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1345 break;
1346 case RADEON_PP_TEX_PITCH_0:
1347 case RADEON_PP_TEX_PITCH_1:
1348 case RADEON_PP_TEX_PITCH_2:
1349 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1350 track->textures[i].pitch = ib_chunk->kdata[idx] + 32;
1351 break;
1352 case RADEON_PP_TXFILTER_0:
1353 case RADEON_PP_TXFILTER_1:
1354 case RADEON_PP_TXFILTER_2:
1355 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1356 track->textures[i].num_levels = ((ib_chunk->kdata[idx] & RADEON_MAX_MIP_LEVEL_MASK)
1357 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1358 tmp = (ib_chunk->kdata[idx] >> 23) & 0x7;
1359 if (tmp == 2 || tmp == 6)
1360 track->textures[i].roundup_w = false;
1361 tmp = (ib_chunk->kdata[idx] >> 27) & 0x7;
1362 if (tmp == 2 || tmp == 6)
1363 track->textures[i].roundup_h = false;
1364 break;
1365 case RADEON_PP_TXFORMAT_0:
1366 case RADEON_PP_TXFORMAT_1:
1367 case RADEON_PP_TXFORMAT_2:
1368 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1369 if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_NON_POWER2) {
1370 track->textures[i].use_pitch = 1;
1371 } else {
1372 track->textures[i].use_pitch = 0;
1373 track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1374 track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1375 }
1376 if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1377 track->textures[i].tex_coord_type = 2;
1378 switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) {
1379 case RADEON_TXFORMAT_I8:
1380 case RADEON_TXFORMAT_RGB332:
1381 case RADEON_TXFORMAT_Y8:
1382 track->textures[i].cpp = 1;
1110 break; 1383 break;
1384 case RADEON_TXFORMAT_AI88:
1385 case RADEON_TXFORMAT_ARGB1555:
1386 case RADEON_TXFORMAT_RGB565:
1387 case RADEON_TXFORMAT_ARGB4444:
1388 case RADEON_TXFORMAT_VYUY422:
1389 case RADEON_TXFORMAT_YVYU422:
1390 case RADEON_TXFORMAT_DXT1:
1391 case RADEON_TXFORMAT_SHADOW16:
1392 case RADEON_TXFORMAT_LDUDV655:
1393 case RADEON_TXFORMAT_DUDV88:
1394 track->textures[i].cpp = 2;
1395 break;
1396 case RADEON_TXFORMAT_ARGB8888:
1397 case RADEON_TXFORMAT_RGBA8888:
1398 case RADEON_TXFORMAT_DXT23:
1399 case RADEON_TXFORMAT_DXT45:
1400 case RADEON_TXFORMAT_SHADOW32:
1401 case RADEON_TXFORMAT_LDUDUV8888:
1402 track->textures[i].cpp = 4;
1403 break;
1404 }
1405 track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf);
1406 track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf);
1407 break;
1408 case RADEON_PP_CUBIC_FACES_0:
1409 case RADEON_PP_CUBIC_FACES_1:
1410 case RADEON_PP_CUBIC_FACES_2:
1411 tmp = ib_chunk->kdata[idx];
1412 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1413 for (face = 0; face < 4; face++) {
1414 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1415 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1111 } 1416 }
1417 break;
1418 default:
1419 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1420 reg, idx);
1421 return -EINVAL;
1112 } 1422 }
1113 return 0; 1423 return 0;
1114} 1424}
@@ -1137,6 +1447,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1137{ 1447{
1138 struct radeon_cs_chunk *ib_chunk; 1448 struct radeon_cs_chunk *ib_chunk;
1139 struct radeon_cs_reloc *reloc; 1449 struct radeon_cs_reloc *reloc;
1450 struct r100_cs_track *track;
1140 unsigned idx; 1451 unsigned idx;
1141 unsigned i, c; 1452 unsigned i, c;
1142 volatile uint32_t *ib; 1453 volatile uint32_t *ib;
@@ -1145,9 +1456,11 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1145 ib = p->ib->ptr; 1456 ib = p->ib->ptr;
1146 ib_chunk = &p->chunks[p->chunk_ib_idx]; 1457 ib_chunk = &p->chunks[p->chunk_ib_idx];
1147 idx = pkt->idx + 1; 1458 idx = pkt->idx + 1;
1459 track = (struct r100_cs_track *)p->track;
1148 switch (pkt->opcode) { 1460 switch (pkt->opcode) {
1149 case PACKET3_3D_LOAD_VBPNTR: 1461 case PACKET3_3D_LOAD_VBPNTR:
1150 c = ib_chunk->kdata[idx++]; 1462 c = ib_chunk->kdata[idx++];
1463 track->num_arrays = c;
1151 for (i = 0; i < (c - 1); i += 2, idx += 3) { 1464 for (i = 0; i < (c - 1); i += 2, idx += 3) {
1152 r = r100_cs_packet_next_reloc(p, &reloc); 1465 r = r100_cs_packet_next_reloc(p, &reloc);
1153 if (r) { 1466 if (r) {
@@ -1157,6 +1470,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1157 return r; 1470 return r;
1158 } 1471 }
1159 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); 1472 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1473 track->arrays[i + 0].robj = reloc->robj;
1474 track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
1475 track->arrays[i + 0].esize &= 0x7F;
1160 r = r100_cs_packet_next_reloc(p, &reloc); 1476 r = r100_cs_packet_next_reloc(p, &reloc);
1161 if (r) { 1477 if (r) {
1162 DRM_ERROR("No reloc for packet3 %d\n", 1478 DRM_ERROR("No reloc for packet3 %d\n",
@@ -1165,6 +1481,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1165 return r; 1481 return r;
1166 } 1482 }
1167 ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset); 1483 ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
1484 track->arrays[i + 1].robj = reloc->robj;
1485 track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24;
1486 track->arrays[i + 1].esize &= 0x7F;
1168 } 1487 }
1169 if (c & 1) { 1488 if (c & 1) {
1170 r = r100_cs_packet_next_reloc(p, &reloc); 1489 r = r100_cs_packet_next_reloc(p, &reloc);
@@ -1175,6 +1494,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1175 return r; 1494 return r;
1176 } 1495 }
1177 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); 1496 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1497 track->arrays[i + 0].robj = reloc->robj;
1498 track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
1499 track->arrays[i + 0].esize &= 0x7F;
1178 } 1500 }
1179 break; 1501 break;
1180 case PACKET3_INDX_BUFFER: 1502 case PACKET3_INDX_BUFFER:
@@ -1191,7 +1513,6 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1191 } 1513 }
1192 break; 1514 break;
1193 case 0x23: 1515 case 0x23:
1194 /* FIXME: cleanup */
1195 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1516 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1196 r = r100_cs_packet_next_reloc(p, &reloc); 1517 r = r100_cs_packet_next_reloc(p, &reloc);
1197 if (r) { 1518 if (r) {
@@ -1200,18 +1521,71 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1200 return r; 1521 return r;
1201 } 1522 }
1202 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 1523 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1524 track->num_arrays = 1;
1525 track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx+2]);
1526
1527 track->arrays[0].robj = reloc->robj;
1528 track->arrays[0].esize = track->vtx_size;
1529
1530 track->max_indx = ib_chunk->kdata[idx+1];
1531
1532 track->vap_vf_cntl = ib_chunk->kdata[idx+3];
1533 track->immd_dwords = pkt->count - 1;
1534 r = r100_cs_track_check(p->rdev, track);
1535 if (r)
1536 return r;
1203 break; 1537 break;
1204 case PACKET3_3D_DRAW_IMMD: 1538 case PACKET3_3D_DRAW_IMMD:
1539 if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) {
1540 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1541 return -EINVAL;
1542 }
1543 track->vap_vf_cntl = ib_chunk->kdata[idx+1];
1544 track->immd_dwords = pkt->count - 1;
1545 r = r100_cs_track_check(p->rdev, track);
1546 if (r)
1547 return r;
1548 break;
1205 /* triggers drawing using in-packet vertex data */ 1549 /* triggers drawing using in-packet vertex data */
1206 case PACKET3_3D_DRAW_IMMD_2: 1550 case PACKET3_3D_DRAW_IMMD_2:
1551 if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) {
1552 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1553 return -EINVAL;
1554 }
1555 track->vap_vf_cntl = ib_chunk->kdata[idx];
1556 track->immd_dwords = pkt->count;
1557 r = r100_cs_track_check(p->rdev, track);
1558 if (r)
1559 return r;
1560 break;
1207 /* triggers drawing using in-packet vertex data */ 1561 /* triggers drawing using in-packet vertex data */
1208 case PACKET3_3D_DRAW_VBUF_2: 1562 case PACKET3_3D_DRAW_VBUF_2:
1563 track->vap_vf_cntl = ib_chunk->kdata[idx];
1564 r = r100_cs_track_check(p->rdev, track);
1565 if (r)
1566 return r;
1567 break;
1209 /* triggers drawing of vertex buffers setup elsewhere */ 1568 /* triggers drawing of vertex buffers setup elsewhere */
1210 case PACKET3_3D_DRAW_INDX_2: 1569 case PACKET3_3D_DRAW_INDX_2:
1570 track->vap_vf_cntl = ib_chunk->kdata[idx];
1571 r = r100_cs_track_check(p->rdev, track);
1572 if (r)
1573 return r;
1574 break;
1211 /* triggers drawing using indices to vertex buffer */ 1575 /* triggers drawing using indices to vertex buffer */
1212 case PACKET3_3D_DRAW_VBUF: 1576 case PACKET3_3D_DRAW_VBUF:
1577 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1578 r = r100_cs_track_check(p->rdev, track);
1579 if (r)
1580 return r;
1581 break;
1213 /* triggers drawing of vertex buffers setup elsewhere */ 1582 /* triggers drawing of vertex buffers setup elsewhere */
1214 case PACKET3_3D_DRAW_INDX: 1583 case PACKET3_3D_DRAW_INDX:
1584 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1585 r = r100_cs_track_check(p->rdev, track);
1586 if (r)
1587 return r;
1588 break;
1215 /* triggers drawing using indices to vertex buffer */ 1589 /* triggers drawing using indices to vertex buffer */
1216 case PACKET3_NOP: 1590 case PACKET3_NOP:
1217 break; 1591 break;
@@ -1225,8 +1599,12 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1225int r100_cs_parse(struct radeon_cs_parser *p) 1599int r100_cs_parse(struct radeon_cs_parser *p)
1226{ 1600{
1227 struct radeon_cs_packet pkt; 1601 struct radeon_cs_packet pkt;
1602 struct r100_cs_track *track;
1228 int r; 1603 int r;
1229 1604
1605 track = kzalloc(sizeof(*track), GFP_KERNEL);
1606 r100_cs_track_clear(p->rdev, track);
1607 p->track = track;
1230 do { 1608 do {
1231 r = r100_cs_packet_parse(p, &pkt, p->idx); 1609 r = r100_cs_packet_parse(p, &pkt, p->idx);
1232 if (r) { 1610 if (r) {
@@ -1235,7 +1613,16 @@ int r100_cs_parse(struct radeon_cs_parser *p)
1235 p->idx += pkt.count + 2; 1613 p->idx += pkt.count + 2;
1236 switch (pkt.type) { 1614 switch (pkt.type) {
1237 case PACKET_TYPE0: 1615 case PACKET_TYPE0:
1238 r = r100_packet0_check(p, &pkt); 1616 if (p->rdev->family >= CHIP_R200)
1617 r = r100_cs_parse_packet0(p, &pkt,
1618 p->rdev->config.r100.reg_safe_bm,
1619 p->rdev->config.r100.reg_safe_bm_size,
1620 &r200_packet0_check);
1621 else
1622 r = r100_cs_parse_packet0(p, &pkt,
1623 p->rdev->config.r100.reg_safe_bm,
1624 p->rdev->config.r100.reg_safe_bm_size,
1625 &r100_packet0_check);
1239 break; 1626 break;
1240 case PACKET_TYPE2: 1627 case PACKET_TYPE2:
1241 break; 1628 break;
@@ -1568,6 +1955,20 @@ void r100_vram_init_sizes(struct radeon_device *rdev)
1568 rdev->mc.real_vram_size = rdev->mc.aper_size; 1955 rdev->mc.real_vram_size = rdev->mc.aper_size;
1569} 1956}
1570 1957
1958void r100_vga_set_state(struct radeon_device *rdev, bool state)
1959{
1960 uint32_t temp;
1961
1962 temp = RREG32(RADEON_CONFIG_CNTL);
1963 if (state == false) {
1964 temp &= ~(1<<8);
1965 temp |= (1<<9);
1966 } else {
1967 temp &= ~(1<<9);
1968 }
1969 WREG32(RADEON_CONFIG_CNTL, temp);
1970}
1971
1571void r100_vram_info(struct radeon_device *rdev) 1972void r100_vram_info(struct radeon_device *rdev)
1572{ 1973{
1573 r100_vram_get_type(rdev); 1974 r100_vram_get_type(rdev);
@@ -1634,6 +2035,15 @@ void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1634 2035
1635int r100_init(struct radeon_device *rdev) 2036int r100_init(struct radeon_device *rdev)
1636{ 2037{
2038 if (ASIC_IS_RN50(rdev)) {
2039 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2040 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2041 } else if (rdev->family < CHIP_R200) {
2042 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2043 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2044 } else {
2045 return r200_init(rdev);
2046 }
1637 return 0; 2047 return 0;
1638} 2048}
1639 2049
@@ -1839,6 +2249,11 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
1839 flags |= R300_SURF_TILE_MICRO; 2249 flags |= R300_SURF_TILE_MICRO;
1840 } 2250 }
1841 2251
2252 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2253 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2254 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2255 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2256
1842 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 2257 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
1843 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 2258 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
1844 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 2259 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
@@ -2334,3 +2749,460 @@ void r100_bandwidth_update(struct radeon_device *rdev)
2334 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 2749 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2335 } 2750 }
2336} 2751}
2752
2753static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2754{
2755 DRM_ERROR("pitch %d\n", t->pitch);
2756 DRM_ERROR("width %d\n", t->width);
2757 DRM_ERROR("height %d\n", t->height);
2758 DRM_ERROR("num levels %d\n", t->num_levels);
2759 DRM_ERROR("depth %d\n", t->txdepth);
2760 DRM_ERROR("bpp %d\n", t->cpp);
2761 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2762 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2763 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2764}
2765
2766static int r100_cs_track_cube(struct radeon_device *rdev,
2767 struct r100_cs_track *track, unsigned idx)
2768{
2769 unsigned face, w, h;
2770 struct radeon_object *cube_robj;
2771 unsigned long size;
2772
2773 for (face = 0; face < 5; face++) {
2774 cube_robj = track->textures[idx].cube_info[face].robj;
2775 w = track->textures[idx].cube_info[face].width;
2776 h = track->textures[idx].cube_info[face].height;
2777
2778 size = w * h;
2779 size *= track->textures[idx].cpp;
2780
2781 size += track->textures[idx].cube_info[face].offset;
2782
2783 if (size > radeon_object_size(cube_robj)) {
2784 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2785 size, radeon_object_size(cube_robj));
2786 r100_cs_track_texture_print(&track->textures[idx]);
2787 return -1;
2788 }
2789 }
2790 return 0;
2791}
2792
2793static int r100_cs_track_texture_check(struct radeon_device *rdev,
2794 struct r100_cs_track *track)
2795{
2796 struct radeon_object *robj;
2797 unsigned long size;
2798 unsigned u, i, w, h;
2799 int ret;
2800
2801 for (u = 0; u < track->num_texture; u++) {
2802 if (!track->textures[u].enabled)
2803 continue;
2804 robj = track->textures[u].robj;
2805 if (robj == NULL) {
2806 DRM_ERROR("No texture bound to unit %u\n", u);
2807 return -EINVAL;
2808 }
2809 size = 0;
2810 for (i = 0; i <= track->textures[u].num_levels; i++) {
2811 if (track->textures[u].use_pitch) {
2812 if (rdev->family < CHIP_R300)
2813 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2814 else
2815 w = track->textures[u].pitch / (1 << i);
2816 } else {
2817 w = track->textures[u].width / (1 << i);
2818 if (rdev->family >= CHIP_RV515)
2819 w |= track->textures[u].width_11;
2820 if (track->textures[u].roundup_w)
2821 w = roundup_pow_of_two(w);
2822 }
2823 h = track->textures[u].height / (1 << i);
2824 if (rdev->family >= CHIP_RV515)
2825 h |= track->textures[u].height_11;
2826 if (track->textures[u].roundup_h)
2827 h = roundup_pow_of_two(h);
2828 size += w * h;
2829 }
2830 size *= track->textures[u].cpp;
2831 switch (track->textures[u].tex_coord_type) {
2832 case 0:
2833 break;
2834 case 1:
2835 size *= (1 << track->textures[u].txdepth);
2836 break;
2837 case 2:
2838 if (track->separate_cube) {
2839 ret = r100_cs_track_cube(rdev, track, u);
2840 if (ret)
2841 return ret;
2842 } else
2843 size *= 6;
2844 break;
2845 default:
2846 DRM_ERROR("Invalid texture coordinate type %u for unit "
2847 "%u\n", track->textures[u].tex_coord_type, u);
2848 return -EINVAL;
2849 }
2850 if (size > radeon_object_size(robj)) {
2851 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2852 "%lu\n", u, size, radeon_object_size(robj));
2853 r100_cs_track_texture_print(&track->textures[u]);
2854 return -EINVAL;
2855 }
2856 }
2857 return 0;
2858}
2859
2860int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2861{
2862 unsigned i;
2863 unsigned long size;
2864 unsigned prim_walk;
2865 unsigned nverts;
2866
2867 for (i = 0; i < track->num_cb; i++) {
2868 if (track->cb[i].robj == NULL) {
2869 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2870 return -EINVAL;
2871 }
2872 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2873 size += track->cb[i].offset;
2874 if (size > radeon_object_size(track->cb[i].robj)) {
2875 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2876 "(need %lu have %lu) !\n", i, size,
2877 radeon_object_size(track->cb[i].robj));
2878 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2879 i, track->cb[i].pitch, track->cb[i].cpp,
2880 track->cb[i].offset, track->maxy);
2881 return -EINVAL;
2882 }
2883 }
2884 if (track->z_enabled) {
2885 if (track->zb.robj == NULL) {
2886 DRM_ERROR("[drm] No buffer for z buffer !\n");
2887 return -EINVAL;
2888 }
2889 size = track->zb.pitch * track->zb.cpp * track->maxy;
2890 size += track->zb.offset;
2891 if (size > radeon_object_size(track->zb.robj)) {
2892 DRM_ERROR("[drm] Buffer too small for z buffer "
2893 "(need %lu have %lu) !\n", size,
2894 radeon_object_size(track->zb.robj));
2895 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2896 track->zb.pitch, track->zb.cpp,
2897 track->zb.offset, track->maxy);
2898 return -EINVAL;
2899 }
2900 }
2901 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2902 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2903 switch (prim_walk) {
2904 case 1:
2905 for (i = 0; i < track->num_arrays; i++) {
2906 size = track->arrays[i].esize * track->max_indx * 4;
2907 if (track->arrays[i].robj == NULL) {
2908 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2909 "bound\n", prim_walk, i);
2910 return -EINVAL;
2911 }
2912 if (size > radeon_object_size(track->arrays[i].robj)) {
2913 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2914 "have %lu dwords\n", prim_walk, i,
2915 size >> 2,
2916 radeon_object_size(track->arrays[i].robj) >> 2);
2917 DRM_ERROR("Max indices %u\n", track->max_indx);
2918 return -EINVAL;
2919 }
2920 }
2921 break;
2922 case 2:
2923 for (i = 0; i < track->num_arrays; i++) {
2924 size = track->arrays[i].esize * (nverts - 1) * 4;
2925 if (track->arrays[i].robj == NULL) {
2926 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2927 "bound\n", prim_walk, i);
2928 return -EINVAL;
2929 }
2930 if (size > radeon_object_size(track->arrays[i].robj)) {
2931 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2932 "have %lu dwords\n", prim_walk, i, size >> 2,
2933 radeon_object_size(track->arrays[i].robj) >> 2);
2934 return -EINVAL;
2935 }
2936 }
2937 break;
2938 case 3:
2939 size = track->vtx_size * nverts;
2940 if (size != track->immd_dwords) {
2941 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2942 track->immd_dwords, size);
2943 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2944 nverts, track->vtx_size);
2945 return -EINVAL;
2946 }
2947 break;
2948 default:
2949 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2950 prim_walk);
2951 return -EINVAL;
2952 }
2953 return r100_cs_track_texture_check(rdev, track);
2954}
2955
2956void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2957{
2958 unsigned i, face;
2959
2960 if (rdev->family < CHIP_R300) {
2961 track->num_cb = 1;
2962 if (rdev->family <= CHIP_RS200)
2963 track->num_texture = 3;
2964 else
2965 track->num_texture = 6;
2966 track->maxy = 2048;
2967 track->separate_cube = 1;
2968 } else {
2969 track->num_cb = 4;
2970 track->num_texture = 16;
2971 track->maxy = 4096;
2972 track->separate_cube = 0;
2973 }
2974
2975 for (i = 0; i < track->num_cb; i++) {
2976 track->cb[i].robj = NULL;
2977 track->cb[i].pitch = 8192;
2978 track->cb[i].cpp = 16;
2979 track->cb[i].offset = 0;
2980 }
2981 track->z_enabled = true;
2982 track->zb.robj = NULL;
2983 track->zb.pitch = 8192;
2984 track->zb.cpp = 4;
2985 track->zb.offset = 0;
2986 track->vtx_size = 0x7F;
2987 track->immd_dwords = 0xFFFFFFFFUL;
2988 track->num_arrays = 11;
2989 track->max_indx = 0x00FFFFFFUL;
2990 for (i = 0; i < track->num_arrays; i++) {
2991 track->arrays[i].robj = NULL;
2992 track->arrays[i].esize = 0x7F;
2993 }
2994 for (i = 0; i < track->num_texture; i++) {
2995 track->textures[i].pitch = 16536;
2996 track->textures[i].width = 16536;
2997 track->textures[i].height = 16536;
2998 track->textures[i].width_11 = 1 << 11;
2999 track->textures[i].height_11 = 1 << 11;
3000 track->textures[i].num_levels = 12;
3001 if (rdev->family <= CHIP_RS200) {
3002 track->textures[i].tex_coord_type = 0;
3003 track->textures[i].txdepth = 0;
3004 } else {
3005 track->textures[i].txdepth = 16;
3006 track->textures[i].tex_coord_type = 1;
3007 }
3008 track->textures[i].cpp = 64;
3009 track->textures[i].robj = NULL;
3010 /* CS IB emission code makes sure texture unit are disabled */
3011 track->textures[i].enabled = false;
3012 track->textures[i].roundup_w = true;
3013 track->textures[i].roundup_h = true;
3014 if (track->separate_cube)
3015 for (face = 0; face < 5; face++) {
3016 track->textures[i].cube_info[face].robj = NULL;
3017 track->textures[i].cube_info[face].width = 16536;
3018 track->textures[i].cube_info[face].height = 16536;
3019 track->textures[i].cube_info[face].offset = 0;
3020 }
3021 }
3022}
3023
3024int r100_ring_test(struct radeon_device *rdev)
3025{
3026 uint32_t scratch;
3027 uint32_t tmp = 0;
3028 unsigned i;
3029 int r;
3030
3031 r = radeon_scratch_get(rdev, &scratch);
3032 if (r) {
3033 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3034 return r;
3035 }
3036 WREG32(scratch, 0xCAFEDEAD);
3037 r = radeon_ring_lock(rdev, 2);
3038 if (r) {
3039 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3040 radeon_scratch_free(rdev, scratch);
3041 return r;
3042 }
3043 radeon_ring_write(rdev, PACKET0(scratch, 0));
3044 radeon_ring_write(rdev, 0xDEADBEEF);
3045 radeon_ring_unlock_commit(rdev);
3046 for (i = 0; i < rdev->usec_timeout; i++) {
3047 tmp = RREG32(scratch);
3048 if (tmp == 0xDEADBEEF) {
3049 break;
3050 }
3051 DRM_UDELAY(1);
3052 }
3053 if (i < rdev->usec_timeout) {
3054 DRM_INFO("ring test succeeded in %d usecs\n", i);
3055 } else {
3056 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3057 scratch, tmp);
3058 r = -EINVAL;
3059 }
3060 radeon_scratch_free(rdev, scratch);
3061 return r;
3062}
3063
3064void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3065{
3066 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3067 radeon_ring_write(rdev, ib->gpu_addr);
3068 radeon_ring_write(rdev, ib->length_dw);
3069}
3070
3071int r100_ib_test(struct radeon_device *rdev)
3072{
3073 struct radeon_ib *ib;
3074 uint32_t scratch;
3075 uint32_t tmp = 0;
3076 unsigned i;
3077 int r;
3078
3079 r = radeon_scratch_get(rdev, &scratch);
3080 if (r) {
3081 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3082 return r;
3083 }
3084 WREG32(scratch, 0xCAFEDEAD);
3085 r = radeon_ib_get(rdev, &ib);
3086 if (r) {
3087 return r;
3088 }
3089 ib->ptr[0] = PACKET0(scratch, 0);
3090 ib->ptr[1] = 0xDEADBEEF;
3091 ib->ptr[2] = PACKET2(0);
3092 ib->ptr[3] = PACKET2(0);
3093 ib->ptr[4] = PACKET2(0);
3094 ib->ptr[5] = PACKET2(0);
3095 ib->ptr[6] = PACKET2(0);
3096 ib->ptr[7] = PACKET2(0);
3097 ib->length_dw = 8;
3098 r = radeon_ib_schedule(rdev, ib);
3099 if (r) {
3100 radeon_scratch_free(rdev, scratch);
3101 radeon_ib_free(rdev, &ib);
3102 return r;
3103 }
3104 r = radeon_fence_wait(ib->fence, false);
3105 if (r) {
3106 return r;
3107 }
3108 for (i = 0; i < rdev->usec_timeout; i++) {
3109 tmp = RREG32(scratch);
3110 if (tmp == 0xDEADBEEF) {
3111 break;
3112 }
3113 DRM_UDELAY(1);
3114 }
3115 if (i < rdev->usec_timeout) {
3116 DRM_INFO("ib test succeeded in %u usecs\n", i);
3117 } else {
3118 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3119 scratch, tmp);
3120 r = -EINVAL;
3121 }
3122 radeon_scratch_free(rdev, scratch);
3123 radeon_ib_free(rdev, &ib);
3124 return r;
3125}
3126
3127void r100_ib_fini(struct radeon_device *rdev)
3128{
3129 radeon_ib_pool_fini(rdev);
3130}
3131
3132int r100_ib_init(struct radeon_device *rdev)
3133{
3134 int r;
3135
3136 r = radeon_ib_pool_init(rdev);
3137 if (r) {
3138 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3139 r100_ib_fini(rdev);
3140 return r;
3141 }
3142 r = r100_ib_test(rdev);
3143 if (r) {
3144 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3145 r100_ib_fini(rdev);
3146 return r;
3147 }
3148 return 0;
3149}
3150
3151void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3152{
3153 /* Shutdown CP we shouldn't need to do that but better be safe than
3154 * sorry
3155 */
3156 rdev->cp.ready = false;
3157 WREG32(R_000740_CP_CSQ_CNTL, 0);
3158
3159 /* Save few CRTC registers */
3160 save->GENMO_WT = RREG32(R_0003C0_GENMO_WT);
3161 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3162 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3163 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3164 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3165 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3166 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3167 }
3168
3169 /* Disable VGA aperture access */
3170 WREG32(R_0003C0_GENMO_WT, C_0003C0_VGA_RAM_EN & save->GENMO_WT);
3171 /* Disable cursor, overlay, crtc */
3172 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3173 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3174 S_000054_CRTC_DISPLAY_DIS(1));
3175 WREG32(R_000050_CRTC_GEN_CNTL,
3176 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3177 S_000050_CRTC_DISP_REQ_EN_B(1));
3178 WREG32(R_000420_OV0_SCALE_CNTL,
3179 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3180 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3181 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3182 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3183 S_000360_CUR2_LOCK(1));
3184 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3185 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3186 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3187 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3188 WREG32(R_000360_CUR2_OFFSET,
3189 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3190 }
3191}
3192
3193void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3194{
3195 /* Update base address for crtc */
3196 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
3197 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3198 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
3199 rdev->mc.vram_location);
3200 }
3201 /* Restore CRTC registers */
3202 WREG32(R_0003C0_GENMO_WT, save->GENMO_WT);
3203 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3204 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3205 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3206 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3207 }
3208}
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
new file mode 100644
index 000000000000..70a82eda394a
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -0,0 +1,124 @@
1
2#define R100_TRACK_MAX_TEXTURE 3
3#define R200_TRACK_MAX_TEXTURE 6
4#define R300_TRACK_MAX_TEXTURE 16
5
6#define R100_MAX_CB 1
7#define R300_MAX_CB 4
8
9/*
10 * CS functions
11 */
12struct r100_cs_track_cb {
13 struct radeon_object *robj;
14 unsigned pitch;
15 unsigned cpp;
16 unsigned offset;
17};
18
19struct r100_cs_track_array {
20 struct radeon_object *robj;
21 unsigned esize;
22};
23
24struct r100_cs_cube_info {
25 struct radeon_object *robj;
26 unsigned offset;
27 unsigned width;
28 unsigned height;
29};
30
31struct r100_cs_track_texture {
32 struct radeon_object *robj;
33 struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
34 unsigned pitch;
35 unsigned width;
36 unsigned height;
37 unsigned num_levels;
38 unsigned cpp;
39 unsigned tex_coord_type;
40 unsigned txdepth;
41 unsigned width_11;
42 unsigned height_11;
43 bool use_pitch;
44 bool enabled;
45 bool roundup_w;
46 bool roundup_h;
47};
48
49struct r100_cs_track_limits {
50 unsigned num_cb;
51 unsigned num_texture;
52 unsigned max_levels;
53};
54
55struct r100_cs_track {
56 struct radeon_device *rdev;
57 unsigned num_cb;
58 unsigned num_texture;
59 unsigned maxy;
60 unsigned vtx_size;
61 unsigned vap_vf_cntl;
62 unsigned immd_dwords;
63 unsigned num_arrays;
64 unsigned max_indx;
65 struct r100_cs_track_array arrays[11];
66 struct r100_cs_track_cb cb[R300_MAX_CB];
67 struct r100_cs_track_cb zb;
68 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
69 bool z_enabled;
70 bool separate_cube;
71
72};
73
74int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
75void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
76int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
77 struct radeon_cs_reloc **cs_reloc);
78void r100_cs_dump_packet(struct radeon_cs_parser *p,
79 struct radeon_cs_packet *pkt);
80
81int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
82
83int r200_packet0_check(struct radeon_cs_parser *p,
84 struct radeon_cs_packet *pkt,
85 unsigned idx, unsigned reg);
86
87static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
88 struct radeon_cs_packet *pkt,
89 unsigned idx,
90 unsigned reg)
91{
92 int r;
93 u32 tile_flags = 0;
94 u32 tmp;
95 struct radeon_cs_reloc *reloc;
96 struct radeon_cs_chunk *ib_chunk;
97
98 ib_chunk = &p->chunks[p->chunk_ib_idx];
99
100 r = r100_cs_packet_next_reloc(p, &reloc);
101 if (r) {
102 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
103 idx, reg);
104 r100_cs_dump_packet(p, pkt);
105 return r;
106 }
107 tmp = ib_chunk->kdata[idx] & 0x003fffff;
108 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
109
110 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
111 tile_flags |= RADEON_DST_TILE_MACRO;
112 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
113 if (reg == RADEON_SRC_PITCH_OFFSET) {
114 DRM_ERROR("Cannot src blit from microtiled surface\n");
115 r100_cs_dump_packet(p, pkt);
116 return -EINVAL;
117 }
118 tile_flags |= RADEON_DST_TILE_MICRO;
119 }
120
121 tmp |= tile_flags;
122 p->ib->ptr[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
123 return 0;
124}
diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h
new file mode 100644
index 000000000000..c4b257ec920e
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r100d.h
@@ -0,0 +1,607 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __R100D_H__
29#define __R100D_H__
30
31#define CP_PACKET0 0x00000000
32#define PACKET0_BASE_INDEX_SHIFT 0
33#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
34#define PACKET0_COUNT_SHIFT 16
35#define PACKET0_COUNT_MASK (0x3fff << 16)
36#define CP_PACKET1 0x40000000
37#define CP_PACKET2 0x80000000
38#define PACKET2_PAD_SHIFT 0
39#define PACKET2_PAD_MASK (0x3fffffff << 0)
40#define CP_PACKET3 0xC0000000
41#define PACKET3_IT_OPCODE_SHIFT 8
42#define PACKET3_IT_OPCODE_MASK (0xff << 8)
43#define PACKET3_COUNT_SHIFT 16
44#define PACKET3_COUNT_MASK (0x3fff << 16)
45/* PACKET3 op code */
46#define PACKET3_NOP 0x10
47#define PACKET3_3D_DRAW_VBUF 0x28
48#define PACKET3_3D_DRAW_IMMD 0x29
49#define PACKET3_3D_DRAW_INDX 0x2A
50#define PACKET3_3D_LOAD_VBPNTR 0x2F
51#define PACKET3_INDX_BUFFER 0x33
52#define PACKET3_3D_DRAW_VBUF_2 0x34
53#define PACKET3_3D_DRAW_IMMD_2 0x35
54#define PACKET3_3D_DRAW_INDX_2 0x36
55#define PACKET3_BITBLT_MULTI 0x9B
56
57#define PACKET0(reg, n) (CP_PACKET0 | \
58 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
59 REG_SET(PACKET0_COUNT, (n)))
60#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
61#define PACKET3(op, n) (CP_PACKET3 | \
62 REG_SET(PACKET3_IT_OPCODE, (op)) | \
63 REG_SET(PACKET3_COUNT, (n)))
64
65#define PACKET_TYPE0 0
66#define PACKET_TYPE1 1
67#define PACKET_TYPE2 2
68#define PACKET_TYPE3 3
69
70#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
71#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
72#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
73#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
74#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
75
76/* Registers */
77#define R_000040_GEN_INT_CNTL 0x000040
78#define S_000040_CRTC_VBLANK(x) (((x) & 0x1) << 0)
79#define G_000040_CRTC_VBLANK(x) (((x) >> 0) & 0x1)
80#define C_000040_CRTC_VBLANK 0xFFFFFFFE
81#define S_000040_CRTC_VLINE(x) (((x) & 0x1) << 1)
82#define G_000040_CRTC_VLINE(x) (((x) >> 1) & 0x1)
83#define C_000040_CRTC_VLINE 0xFFFFFFFD
84#define S_000040_CRTC_VSYNC(x) (((x) & 0x1) << 2)
85#define G_000040_CRTC_VSYNC(x) (((x) >> 2) & 0x1)
86#define C_000040_CRTC_VSYNC 0xFFFFFFFB
87#define S_000040_SNAPSHOT(x) (((x) & 0x1) << 3)
88#define G_000040_SNAPSHOT(x) (((x) >> 3) & 0x1)
89#define C_000040_SNAPSHOT 0xFFFFFFF7
90#define S_000040_FP_DETECT(x) (((x) & 0x1) << 4)
91#define G_000040_FP_DETECT(x) (((x) >> 4) & 0x1)
92#define C_000040_FP_DETECT 0xFFFFFFEF
93#define S_000040_CRTC2_VLINE(x) (((x) & 0x1) << 5)
94#define G_000040_CRTC2_VLINE(x) (((x) >> 5) & 0x1)
95#define C_000040_CRTC2_VLINE 0xFFFFFFDF
96#define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12)
97#define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1)
98#define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF
99#define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6)
100#define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1)
101#define C_000040_CRTC2_VSYNC 0xFFFFFFBF
102#define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7)
103#define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1)
104#define C_000040_SNAPSHOT2 0xFFFFFF7F
105#define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9)
106#define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1)
107#define C_000040_CRTC2_VBLANK 0xFFFFFDFF
108#define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10)
109#define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1)
110#define C_000040_FP2_DETECT 0xFFFFFBFF
111#define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11)
112#define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1)
113#define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF
114#define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13)
115#define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1)
116#define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF
117#define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14)
118#define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1)
119#define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF
120#define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15)
121#define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1)
122#define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF
123#define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17)
124#define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1)
125#define C_000040_I2C_INT_EN 0xFFFDFFFF
126#define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19)
127#define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1)
128#define C_000040_GUI_IDLE 0xFFF7FFFF
129#define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24)
130#define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1)
131#define C_000040_VIPH_INT_EN 0xFEFFFFFF
132#define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25)
133#define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1)
134#define C_000040_SW_INT_EN 0xFDFFFFFF
135#define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27)
136#define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1)
137#define C_000040_GEYSERVILLE 0xF7FFFFFF
138#define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28)
139#define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1)
140#define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF
141#define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29)
142#define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1)
143#define C_000040_DVI_I2C_INT 0xDFFFFFFF
144#define S_000040_GUIDMA(x) (((x) & 0x1) << 30)
145#define G_000040_GUIDMA(x) (((x) >> 30) & 0x1)
146#define C_000040_GUIDMA 0xBFFFFFFF
147#define S_000040_VIDDMA(x) (((x) & 0x1) << 31)
148#define G_000040_VIDDMA(x) (((x) >> 31) & 0x1)
149#define C_000040_VIDDMA 0x7FFFFFFF
150#define R_000044_GEN_INT_STATUS 0x000044
151#define S_000044_CRTC_VBLANK_STAT(x) (((x) & 0x1) << 0)
152#define G_000044_CRTC_VBLANK_STAT(x) (((x) >> 0) & 0x1)
153#define C_000044_CRTC_VBLANK_STAT 0xFFFFFFFE
154#define S_000044_CRTC_VBLANK_STAT_AK(x) (((x) & 0x1) << 0)
155#define G_000044_CRTC_VBLANK_STAT_AK(x) (((x) >> 0) & 0x1)
156#define C_000044_CRTC_VBLANK_STAT_AK 0xFFFFFFFE
157#define S_000044_CRTC_VLINE_STAT(x) (((x) & 0x1) << 1)
158#define G_000044_CRTC_VLINE_STAT(x) (((x) >> 1) & 0x1)
159#define C_000044_CRTC_VLINE_STAT 0xFFFFFFFD
160#define S_000044_CRTC_VLINE_STAT_AK(x) (((x) & 0x1) << 1)
161#define G_000044_CRTC_VLINE_STAT_AK(x) (((x) >> 1) & 0x1)
162#define C_000044_CRTC_VLINE_STAT_AK 0xFFFFFFFD
163#define S_000044_CRTC_VSYNC_STAT(x) (((x) & 0x1) << 2)
164#define G_000044_CRTC_VSYNC_STAT(x) (((x) >> 2) & 0x1)
165#define C_000044_CRTC_VSYNC_STAT 0xFFFFFFFB
166#define S_000044_CRTC_VSYNC_STAT_AK(x) (((x) & 0x1) << 2)
167#define G_000044_CRTC_VSYNC_STAT_AK(x) (((x) >> 2) & 0x1)
168#define C_000044_CRTC_VSYNC_STAT_AK 0xFFFFFFFB
169#define S_000044_SNAPSHOT_STAT(x) (((x) & 0x1) << 3)
170#define G_000044_SNAPSHOT_STAT(x) (((x) >> 3) & 0x1)
171#define C_000044_SNAPSHOT_STAT 0xFFFFFFF7
172#define S_000044_SNAPSHOT_STAT_AK(x) (((x) & 0x1) << 3)
173#define G_000044_SNAPSHOT_STAT_AK(x) (((x) >> 3) & 0x1)
174#define C_000044_SNAPSHOT_STAT_AK 0xFFFFFFF7
175#define S_000044_FP_DETECT_STAT(x) (((x) & 0x1) << 4)
176#define G_000044_FP_DETECT_STAT(x) (((x) >> 4) & 0x1)
177#define C_000044_FP_DETECT_STAT 0xFFFFFFEF
178#define S_000044_FP_DETECT_STAT_AK(x) (((x) & 0x1) << 4)
179#define G_000044_FP_DETECT_STAT_AK(x) (((x) >> 4) & 0x1)
180#define C_000044_FP_DETECT_STAT_AK 0xFFFFFFEF
181#define S_000044_CRTC2_VLINE_STAT(x) (((x) & 0x1) << 5)
182#define G_000044_CRTC2_VLINE_STAT(x) (((x) >> 5) & 0x1)
183#define C_000044_CRTC2_VLINE_STAT 0xFFFFFFDF
184#define S_000044_CRTC2_VLINE_STAT_AK(x) (((x) & 0x1) << 5)
185#define G_000044_CRTC2_VLINE_STAT_AK(x) (((x) >> 5) & 0x1)
186#define C_000044_CRTC2_VLINE_STAT_AK 0xFFFFFFDF
187#define S_000044_CRTC2_VSYNC_STAT(x) (((x) & 0x1) << 6)
188#define G_000044_CRTC2_VSYNC_STAT(x) (((x) >> 6) & 0x1)
189#define C_000044_CRTC2_VSYNC_STAT 0xFFFFFFBF
190#define S_000044_CRTC2_VSYNC_STAT_AK(x) (((x) & 0x1) << 6)
191#define G_000044_CRTC2_VSYNC_STAT_AK(x) (((x) >> 6) & 0x1)
192#define C_000044_CRTC2_VSYNC_STAT_AK 0xFFFFFFBF
193#define S_000044_SNAPSHOT2_STAT(x) (((x) & 0x1) << 7)
194#define G_000044_SNAPSHOT2_STAT(x) (((x) >> 7) & 0x1)
195#define C_000044_SNAPSHOT2_STAT 0xFFFFFF7F
196#define S_000044_SNAPSHOT2_STAT_AK(x) (((x) & 0x1) << 7)
197#define G_000044_SNAPSHOT2_STAT_AK(x) (((x) >> 7) & 0x1)
198#define C_000044_SNAPSHOT2_STAT_AK 0xFFFFFF7F
199#define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8)
200#define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1)
201#define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF
202#define S_000044_CRTC2_VBLANK_STAT(x) (((x) & 0x1) << 9)
203#define G_000044_CRTC2_VBLANK_STAT(x) (((x) >> 9) & 0x1)
204#define C_000044_CRTC2_VBLANK_STAT 0xFFFFFDFF
205#define S_000044_CRTC2_VBLANK_STAT_AK(x) (((x) & 0x1) << 9)
206#define G_000044_CRTC2_VBLANK_STAT_AK(x) (((x) >> 9) & 0x1)
207#define C_000044_CRTC2_VBLANK_STAT_AK 0xFFFFFDFF
208#define S_000044_FP2_DETECT_STAT(x) (((x) & 0x1) << 10)
209#define G_000044_FP2_DETECT_STAT(x) (((x) >> 10) & 0x1)
210#define C_000044_FP2_DETECT_STAT 0xFFFFFBFF
211#define S_000044_FP2_DETECT_STAT_AK(x) (((x) & 0x1) << 10)
212#define G_000044_FP2_DETECT_STAT_AK(x) (((x) >> 10) & 0x1)
213#define C_000044_FP2_DETECT_STAT_AK 0xFFFFFBFF
214#define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) & 0x1) << 11)
215#define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) >> 11) & 0x1)
216#define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT 0xFFFFF7FF
217#define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) & 0x1) << 11)
218#define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) >> 11) & 0x1)
219#define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK 0xFFFFF7FF
220#define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12)
221#define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1)
222#define C_000044_DMA_VIPH0_INT 0xFFFFEFFF
223#define S_000044_DMA_VIPH0_INT_AK(x) (((x) & 0x1) << 12)
224#define G_000044_DMA_VIPH0_INT_AK(x) (((x) >> 12) & 0x1)
225#define C_000044_DMA_VIPH0_INT_AK 0xFFFFEFFF
226#define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13)
227#define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1)
228#define C_000044_DMA_VIPH1_INT 0xFFFFDFFF
229#define S_000044_DMA_VIPH1_INT_AK(x) (((x) & 0x1) << 13)
230#define G_000044_DMA_VIPH1_INT_AK(x) (((x) >> 13) & 0x1)
231#define C_000044_DMA_VIPH1_INT_AK 0xFFFFDFFF
232#define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14)
233#define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1)
234#define C_000044_DMA_VIPH2_INT 0xFFFFBFFF
235#define S_000044_DMA_VIPH2_INT_AK(x) (((x) & 0x1) << 14)
236#define G_000044_DMA_VIPH2_INT_AK(x) (((x) >> 14) & 0x1)
237#define C_000044_DMA_VIPH2_INT_AK 0xFFFFBFFF
238#define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15)
239#define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1)
240#define C_000044_DMA_VIPH3_INT 0xFFFF7FFF
241#define S_000044_DMA_VIPH3_INT_AK(x) (((x) & 0x1) << 15)
242#define G_000044_DMA_VIPH3_INT_AK(x) (((x) >> 15) & 0x1)
243#define C_000044_DMA_VIPH3_INT_AK 0xFFFF7FFF
244#define S_000044_I2C_INT(x) (((x) & 0x1) << 17)
245#define G_000044_I2C_INT(x) (((x) >> 17) & 0x1)
246#define C_000044_I2C_INT 0xFFFDFFFF
247#define S_000044_I2C_INT_AK(x) (((x) & 0x1) << 17)
248#define G_000044_I2C_INT_AK(x) (((x) >> 17) & 0x1)
249#define C_000044_I2C_INT_AK 0xFFFDFFFF
250#define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19)
251#define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1)
252#define C_000044_GUI_IDLE_STAT 0xFFF7FFFF
253#define S_000044_GUI_IDLE_STAT_AK(x) (((x) & 0x1) << 19)
254#define G_000044_GUI_IDLE_STAT_AK(x) (((x) >> 19) & 0x1)
255#define C_000044_GUI_IDLE_STAT_AK 0xFFF7FFFF
256#define S_000044_VIPH_INT(x) (((x) & 0x1) << 24)
257#define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1)
258#define C_000044_VIPH_INT 0xFEFFFFFF
259#define S_000044_SW_INT(x) (((x) & 0x1) << 25)
260#define G_000044_SW_INT(x) (((x) >> 25) & 0x1)
261#define C_000044_SW_INT 0xFDFFFFFF
262#define S_000044_SW_INT_AK(x) (((x) & 0x1) << 25)
263#define G_000044_SW_INT_AK(x) (((x) >> 25) & 0x1)
264#define C_000044_SW_INT_AK 0xFDFFFFFF
265#define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26)
266#define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1)
267#define C_000044_SW_INT_SET 0xFBFFFFFF
268#define S_000044_GEYSERVILLE_STAT(x) (((x) & 0x1) << 27)
269#define G_000044_GEYSERVILLE_STAT(x) (((x) >> 27) & 0x1)
270#define C_000044_GEYSERVILLE_STAT 0xF7FFFFFF
271#define S_000044_GEYSERVILLE_STAT_AK(x) (((x) & 0x1) << 27)
272#define G_000044_GEYSERVILLE_STAT_AK(x) (((x) >> 27) & 0x1)
273#define C_000044_GEYSERVILLE_STAT_AK 0xF7FFFFFF
274#define S_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) & 0x1) << 28)
275#define G_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) >> 28) & 0x1)
276#define C_000044_HDCP_AUTHORIZED_INT_STAT 0xEFFFFFFF
277#define S_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) & 0x1) << 28)
278#define G_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) >> 28) & 0x1)
279#define C_000044_HDCP_AUTHORIZED_INT_AK 0xEFFFFFFF
280#define S_000044_DVI_I2C_INT_STAT(x) (((x) & 0x1) << 29)
281#define G_000044_DVI_I2C_INT_STAT(x) (((x) >> 29) & 0x1)
282#define C_000044_DVI_I2C_INT_STAT 0xDFFFFFFF
283#define S_000044_DVI_I2C_INT_AK(x) (((x) & 0x1) << 29)
284#define G_000044_DVI_I2C_INT_AK(x) (((x) >> 29) & 0x1)
285#define C_000044_DVI_I2C_INT_AK 0xDFFFFFFF
286#define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30)
287#define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1)
288#define C_000044_GUIDMA_STAT 0xBFFFFFFF
289#define S_000044_GUIDMA_AK(x) (((x) & 0x1) << 30)
290#define G_000044_GUIDMA_AK(x) (((x) >> 30) & 0x1)
291#define C_000044_GUIDMA_AK 0xBFFFFFFF
292#define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31)
293#define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1)
294#define C_000044_VIDDMA_STAT 0x7FFFFFFF
295#define S_000044_VIDDMA_AK(x) (((x) & 0x1) << 31)
296#define G_000044_VIDDMA_AK(x) (((x) >> 31) & 0x1)
297#define C_000044_VIDDMA_AK 0x7FFFFFFF
298#define R_000050_CRTC_GEN_CNTL 0x000050
299#define S_000050_CRTC_DBL_SCAN_EN(x) (((x) & 0x1) << 0)
300#define G_000050_CRTC_DBL_SCAN_EN(x) (((x) >> 0) & 0x1)
301#define C_000050_CRTC_DBL_SCAN_EN 0xFFFFFFFE
302#define S_000050_CRTC_INTERLACE_EN(x) (((x) & 0x1) << 1)
303#define G_000050_CRTC_INTERLACE_EN(x) (((x) >> 1) & 0x1)
304#define C_000050_CRTC_INTERLACE_EN 0xFFFFFFFD
305#define S_000050_CRTC_C_SYNC_EN(x) (((x) & 0x1) << 4)
306#define G_000050_CRTC_C_SYNC_EN(x) (((x) >> 4) & 0x1)
307#define C_000050_CRTC_C_SYNC_EN 0xFFFFFFEF
308#define S_000050_CRTC_PIX_WIDTH(x) (((x) & 0xF) << 8)
309#define G_000050_CRTC_PIX_WIDTH(x) (((x) >> 8) & 0xF)
310#define C_000050_CRTC_PIX_WIDTH 0xFFFFF0FF
311#define S_000050_CRTC_ICON_EN(x) (((x) & 0x1) << 15)
312#define G_000050_CRTC_ICON_EN(x) (((x) >> 15) & 0x1)
313#define C_000050_CRTC_ICON_EN 0xFFFF7FFF
314#define S_000050_CRTC_CUR_EN(x) (((x) & 0x1) << 16)
315#define G_000050_CRTC_CUR_EN(x) (((x) >> 16) & 0x1)
316#define C_000050_CRTC_CUR_EN 0xFFFEFFFF
317#define S_000050_CRTC_VSTAT_MODE(x) (((x) & 0x3) << 17)
318#define G_000050_CRTC_VSTAT_MODE(x) (((x) >> 17) & 0x3)
319#define C_000050_CRTC_VSTAT_MODE 0xFFF9FFFF
320#define S_000050_CRTC_CUR_MODE(x) (((x) & 0x7) << 20)
321#define G_000050_CRTC_CUR_MODE(x) (((x) >> 20) & 0x7)
322#define C_000050_CRTC_CUR_MODE 0xFF8FFFFF
323#define S_000050_CRTC_EXT_DISP_EN(x) (((x) & 0x1) << 24)
324#define G_000050_CRTC_EXT_DISP_EN(x) (((x) >> 24) & 0x1)
325#define C_000050_CRTC_EXT_DISP_EN 0xFEFFFFFF
326#define S_000050_CRTC_EN(x) (((x) & 0x1) << 25)
327#define G_000050_CRTC_EN(x) (((x) >> 25) & 0x1)
328#define C_000050_CRTC_EN 0xFDFFFFFF
329#define S_000050_CRTC_DISP_REQ_EN_B(x) (((x) & 0x1) << 26)
330#define G_000050_CRTC_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1)
331#define C_000050_CRTC_DISP_REQ_EN_B 0xFBFFFFFF
332#define R_000054_CRTC_EXT_CNTL 0x000054
333#define S_000054_CRTC_VGA_XOVERSCAN(x) (((x) & 0x1) << 0)
334#define G_000054_CRTC_VGA_XOVERSCAN(x) (((x) >> 0) & 0x1)
335#define C_000054_CRTC_VGA_XOVERSCAN 0xFFFFFFFE
336#define S_000054_VGA_BLINK_RATE(x) (((x) & 0x3) << 1)
337#define G_000054_VGA_BLINK_RATE(x) (((x) >> 1) & 0x3)
338#define C_000054_VGA_BLINK_RATE 0xFFFFFFF9
339#define S_000054_VGA_ATI_LINEAR(x) (((x) & 0x1) << 3)
340#define G_000054_VGA_ATI_LINEAR(x) (((x) >> 3) & 0x1)
341#define C_000054_VGA_ATI_LINEAR 0xFFFFFFF7
342#define S_000054_VGA_128KAP_PAGING(x) (((x) & 0x1) << 4)
343#define G_000054_VGA_128KAP_PAGING(x) (((x) >> 4) & 0x1)
344#define C_000054_VGA_128KAP_PAGING 0xFFFFFFEF
345#define S_000054_VGA_TEXT_132(x) (((x) & 0x1) << 5)
346#define G_000054_VGA_TEXT_132(x) (((x) >> 5) & 0x1)
347#define C_000054_VGA_TEXT_132 0xFFFFFFDF
348#define S_000054_VGA_XCRT_CNT_EN(x) (((x) & 0x1) << 6)
349#define G_000054_VGA_XCRT_CNT_EN(x) (((x) >> 6) & 0x1)
350#define C_000054_VGA_XCRT_CNT_EN 0xFFFFFFBF
351#define S_000054_CRTC_HSYNC_DIS(x) (((x) & 0x1) << 8)
352#define G_000054_CRTC_HSYNC_DIS(x) (((x) >> 8) & 0x1)
353#define C_000054_CRTC_HSYNC_DIS 0xFFFFFEFF
354#define S_000054_CRTC_VSYNC_DIS(x) (((x) & 0x1) << 9)
355#define G_000054_CRTC_VSYNC_DIS(x) (((x) >> 9) & 0x1)
356#define C_000054_CRTC_VSYNC_DIS 0xFFFFFDFF
357#define S_000054_CRTC_DISPLAY_DIS(x) (((x) & 0x1) << 10)
358#define G_000054_CRTC_DISPLAY_DIS(x) (((x) >> 10) & 0x1)
359#define C_000054_CRTC_DISPLAY_DIS 0xFFFFFBFF
360#define S_000054_CRTC_SYNC_TRISTATE(x) (((x) & 0x1) << 11)
361#define G_000054_CRTC_SYNC_TRISTATE(x) (((x) >> 11) & 0x1)
362#define C_000054_CRTC_SYNC_TRISTATE 0xFFFFF7FF
363#define S_000054_CRTC_HSYNC_TRISTATE(x) (((x) & 0x1) << 12)
364#define G_000054_CRTC_HSYNC_TRISTATE(x) (((x) >> 12) & 0x1)
365#define C_000054_CRTC_HSYNC_TRISTATE 0xFFFFEFFF
366#define S_000054_CRTC_VSYNC_TRISTATE(x) (((x) & 0x1) << 13)
367#define G_000054_CRTC_VSYNC_TRISTATE(x) (((x) >> 13) & 0x1)
368#define C_000054_CRTC_VSYNC_TRISTATE 0xFFFFDFFF
369#define S_000054_CRT_ON(x) (((x) & 0x1) << 15)
370#define G_000054_CRT_ON(x) (((x) >> 15) & 0x1)
371#define C_000054_CRT_ON 0xFFFF7FFF
372#define S_000054_VGA_CUR_B_TEST(x) (((x) & 0x1) << 17)
373#define G_000054_VGA_CUR_B_TEST(x) (((x) >> 17) & 0x1)
374#define C_000054_VGA_CUR_B_TEST 0xFFFDFFFF
375#define S_000054_VGA_PACK_DIS(x) (((x) & 0x1) << 18)
376#define G_000054_VGA_PACK_DIS(x) (((x) >> 18) & 0x1)
377#define C_000054_VGA_PACK_DIS 0xFFFBFFFF
378#define S_000054_VGA_MEM_PS_EN(x) (((x) & 0x1) << 19)
379#define G_000054_VGA_MEM_PS_EN(x) (((x) >> 19) & 0x1)
380#define C_000054_VGA_MEM_PS_EN 0xFFF7FFFF
381#define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24)
382#define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F)
383#define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF
384#define R_00023C_DISPLAY_BASE_ADDR 0x00023C
385#define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
386#define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
387#define C_00023C_DISPLAY_BASE_ADDR 0x00000000
388#define R_000260_CUR_OFFSET 0x000260
389#define S_000260_CUR_OFFSET(x) (((x) & 0x7FFFFFF) << 0)
390#define G_000260_CUR_OFFSET(x) (((x) >> 0) & 0x7FFFFFF)
391#define C_000260_CUR_OFFSET 0xF8000000
392#define S_000260_CUR_LOCK(x) (((x) & 0x1) << 31)
393#define G_000260_CUR_LOCK(x) (((x) >> 31) & 0x1)
394#define C_000260_CUR_LOCK 0x7FFFFFFF
395#define R_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00033C
396#define S_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
397#define G_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
398#define C_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00000000
399#define R_000360_CUR2_OFFSET 0x000360
400#define S_000360_CUR2_OFFSET(x) (((x) & 0x7FFFFFF) << 0)
401#define G_000360_CUR2_OFFSET(x) (((x) >> 0) & 0x7FFFFFF)
402#define C_000360_CUR2_OFFSET 0xF8000000
403#define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31)
404#define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1)
405#define C_000360_CUR2_LOCK 0x7FFFFFFF
406#define R_0003C0_GENMO_WT 0x0003C0
407#define S_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0)
408#define G_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1)
409#define C_0003C0_GENMO_MONO_ADDRESS_B 0xFFFFFFFE
410#define S_0003C0_VGA_RAM_EN(x) (((x) & 0x1) << 1)
411#define G_0003C0_VGA_RAM_EN(x) (((x) >> 1) & 0x1)
412#define C_0003C0_VGA_RAM_EN 0xFFFFFFFD
413#define S_0003C0_VGA_CKSEL(x) (((x) & 0x3) << 2)
414#define G_0003C0_VGA_CKSEL(x) (((x) >> 2) & 0x3)
415#define C_0003C0_VGA_CKSEL 0xFFFFFFF3
416#define S_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5)
417#define G_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1)
418#define C_0003C0_ODD_EVEN_MD_PGSEL 0xFFFFFFDF
419#define S_0003C0_VGA_HSYNC_POL(x) (((x) & 0x1) << 6)
420#define G_0003C0_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1)
421#define C_0003C0_VGA_HSYNC_POL 0xFFFFFFBF
422#define S_0003C0_VGA_VSYNC_POL(x) (((x) & 0x1) << 7)
423#define G_0003C0_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1)
424#define C_0003C0_VGA_VSYNC_POL 0xFFFFFF7F
425#define R_0003F8_CRTC2_GEN_CNTL 0x0003F8
426#define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0)
427#define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1)
428#define C_0003F8_CRTC2_DBL_SCAN_EN 0xFFFFFFFE
429#define S_0003F8_CRTC2_INTERLACE_EN(x) (((x) & 0x1) << 1)
430#define G_0003F8_CRTC2_INTERLACE_EN(x) (((x) >> 1) & 0x1)
431#define C_0003F8_CRTC2_INTERLACE_EN 0xFFFFFFFD
432#define S_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) & 0x1) << 4)
433#define G_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) >> 4) & 0x1)
434#define C_0003F8_CRTC2_SYNC_TRISTATE 0xFFFFFFEF
435#define S_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) & 0x1) << 5)
436#define G_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) >> 5) & 0x1)
437#define C_0003F8_CRTC2_HSYNC_TRISTATE 0xFFFFFFDF
438#define S_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) & 0x1) << 6)
439#define G_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) >> 6) & 0x1)
440#define C_0003F8_CRTC2_VSYNC_TRISTATE 0xFFFFFFBF
441#define S_0003F8_CRT2_ON(x) (((x) & 0x1) << 7)
442#define G_0003F8_CRT2_ON(x) (((x) >> 7) & 0x1)
443#define C_0003F8_CRT2_ON 0xFFFFFF7F
444#define S_0003F8_CRTC2_PIX_WIDTH(x) (((x) & 0xF) << 8)
445#define G_0003F8_CRTC2_PIX_WIDTH(x) (((x) >> 8) & 0xF)
446#define C_0003F8_CRTC2_PIX_WIDTH 0xFFFFF0FF
447#define S_0003F8_CRTC2_ICON_EN(x) (((x) & 0x1) << 15)
448#define G_0003F8_CRTC2_ICON_EN(x) (((x) >> 15) & 0x1)
449#define C_0003F8_CRTC2_ICON_EN 0xFFFF7FFF
450#define S_0003F8_CRTC2_CUR_EN(x) (((x) & 0x1) << 16)
451#define G_0003F8_CRTC2_CUR_EN(x) (((x) >> 16) & 0x1)
452#define C_0003F8_CRTC2_CUR_EN 0xFFFEFFFF
453#define S_0003F8_CRTC2_CUR_MODE(x) (((x) & 0x7) << 20)
454#define G_0003F8_CRTC2_CUR_MODE(x) (((x) >> 20) & 0x7)
455#define C_0003F8_CRTC2_CUR_MODE 0xFF8FFFFF
456#define S_0003F8_CRTC2_DISPLAY_DIS(x) (((x) & 0x1) << 23)
457#define G_0003F8_CRTC2_DISPLAY_DIS(x) (((x) >> 23) & 0x1)
458#define C_0003F8_CRTC2_DISPLAY_DIS 0xFF7FFFFF
459#define S_0003F8_CRTC2_EN(x) (((x) & 0x1) << 25)
460#define G_0003F8_CRTC2_EN(x) (((x) >> 25) & 0x1)
461#define C_0003F8_CRTC2_EN 0xFDFFFFFF
462#define S_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) & 0x1) << 26)
463#define G_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1)
464#define C_0003F8_CRTC2_DISP_REQ_EN_B 0xFBFFFFFF
465#define S_0003F8_CRTC2_C_SYNC_EN(x) (((x) & 0x1) << 27)
466#define G_0003F8_CRTC2_C_SYNC_EN(x) (((x) >> 27) & 0x1)
467#define C_0003F8_CRTC2_C_SYNC_EN 0xF7FFFFFF
468#define S_0003F8_CRTC2_HSYNC_DIS(x) (((x) & 0x1) << 28)
469#define G_0003F8_CRTC2_HSYNC_DIS(x) (((x) >> 28) & 0x1)
470#define C_0003F8_CRTC2_HSYNC_DIS 0xEFFFFFFF
471#define S_0003F8_CRTC2_VSYNC_DIS(x) (((x) & 0x1) << 29)
472#define G_0003F8_CRTC2_VSYNC_DIS(x) (((x) >> 29) & 0x1)
473#define C_0003F8_CRTC2_VSYNC_DIS 0xDFFFFFFF
474#define R_000420_OV0_SCALE_CNTL 0x000420
475#define S_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) & 0x1) << 1)
476#define G_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) >> 1) & 0x1)
477#define C_000420_OV0_NO_READ_BEHIND_SCAN 0xFFFFFFFD
478#define S_000420_OV0_HORZ_PICK_NEAREST(x) (((x) & 0x1) << 2)
479#define G_000420_OV0_HORZ_PICK_NEAREST(x) (((x) >> 2) & 0x1)
480#define C_000420_OV0_HORZ_PICK_NEAREST 0xFFFFFFFB
481#define S_000420_OV0_VERT_PICK_NEAREST(x) (((x) & 0x1) << 3)
482#define G_000420_OV0_VERT_PICK_NEAREST(x) (((x) >> 3) & 0x1)
483#define C_000420_OV0_VERT_PICK_NEAREST 0xFFFFFFF7
484#define S_000420_OV0_SIGNED_UV(x) (((x) & 0x1) << 4)
485#define G_000420_OV0_SIGNED_UV(x) (((x) >> 4) & 0x1)
486#define C_000420_OV0_SIGNED_UV 0xFFFFFFEF
487#define S_000420_OV0_GAMMA_SEL(x) (((x) & 0x7) << 5)
488#define G_000420_OV0_GAMMA_SEL(x) (((x) >> 5) & 0x7)
489#define C_000420_OV0_GAMMA_SEL 0xFFFFFF1F
490#define S_000420_OV0_SURFACE_FORMAT(x) (((x) & 0xF) << 8)
491#define G_000420_OV0_SURFACE_FORMAT(x) (((x) >> 8) & 0xF)
492#define C_000420_OV0_SURFACE_FORMAT 0xFFFFF0FF
493#define S_000420_OV0_ADAPTIVE_DEINT(x) (((x) & 0x1) << 12)
494#define G_000420_OV0_ADAPTIVE_DEINT(x) (((x) >> 12) & 0x1)
495#define C_000420_OV0_ADAPTIVE_DEINT 0xFFFFEFFF
496#define S_000420_OV0_CRTC_SEL(x) (((x) & 0x1) << 14)
497#define G_000420_OV0_CRTC_SEL(x) (((x) >> 14) & 0x1)
498#define C_000420_OV0_CRTC_SEL 0xFFFFBFFF
499#define S_000420_OV0_BURST_PER_PLANE(x) (((x) & 0x7F) << 16)
500#define G_000420_OV0_BURST_PER_PLANE(x) (((x) >> 16) & 0x7F)
501#define C_000420_OV0_BURST_PER_PLANE 0xFF80FFFF
502#define S_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) & 0x1) << 24)
503#define G_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) >> 24) & 0x1)
504#define C_000420_OV0_DOUBLE_BUFFER_REGS 0xFEFFFFFF
505#define S_000420_OV0_BANDWIDTH(x) (((x) & 0x1) << 26)
506#define G_000420_OV0_BANDWIDTH(x) (((x) >> 26) & 0x1)
507#define C_000420_OV0_BANDWIDTH 0xFBFFFFFF
508#define S_000420_OV0_LIN_TRANS_BYPASS(x) (((x) & 0x1) << 28)
509#define G_000420_OV0_LIN_TRANS_BYPASS(x) (((x) >> 28) & 0x1)
510#define C_000420_OV0_LIN_TRANS_BYPASS 0xEFFFFFFF
511#define S_000420_OV0_INT_EMU(x) (((x) & 0x1) << 29)
512#define G_000420_OV0_INT_EMU(x) (((x) >> 29) & 0x1)
513#define C_000420_OV0_INT_EMU 0xDFFFFFFF
514#define S_000420_OV0_OVERLAY_EN(x) (((x) & 0x1) << 30)
515#define G_000420_OV0_OVERLAY_EN(x) (((x) >> 30) & 0x1)
516#define C_000420_OV0_OVERLAY_EN 0xBFFFFFFF
517#define S_000420_OV0_SOFT_RESET(x) (((x) & 0x1) << 31)
518#define G_000420_OV0_SOFT_RESET(x) (((x) >> 31) & 0x1)
519#define C_000420_OV0_SOFT_RESET 0x7FFFFFFF
520#define R_00070C_CP_RB_RPTR_ADDR 0x00070C
521#define S_00070C_RB_RPTR_SWAP(x) (((x) & 0x3) << 0)
522#define G_00070C_RB_RPTR_SWAP(x) (((x) >> 0) & 0x3)
523#define C_00070C_RB_RPTR_SWAP 0xFFFFFFFC
524#define S_00070C_RB_RPTR_ADDR(x) (((x) & 0x3FFFFFFF) << 2)
525#define G_00070C_RB_RPTR_ADDR(x) (((x) >> 2) & 0x3FFFFFFF)
526#define C_00070C_RB_RPTR_ADDR 0x00000003
527#define R_000740_CP_CSQ_CNTL 0x000740
528#define S_000740_CSQ_CNT_PRIMARY(x) (((x) & 0xFF) << 0)
529#define G_000740_CSQ_CNT_PRIMARY(x) (((x) >> 0) & 0xFF)
530#define C_000740_CSQ_CNT_PRIMARY 0xFFFFFF00
531#define S_000740_CSQ_CNT_INDIRECT(x) (((x) & 0xFF) << 8)
532#define G_000740_CSQ_CNT_INDIRECT(x) (((x) >> 8) & 0xFF)
533#define C_000740_CSQ_CNT_INDIRECT 0xFFFF00FF
534#define S_000740_CSQ_MODE(x) (((x) & 0xF) << 28)
535#define G_000740_CSQ_MODE(x) (((x) >> 28) & 0xF)
536#define C_000740_CSQ_MODE 0x0FFFFFFF
537#define R_000770_SCRATCH_UMSK 0x000770
538#define S_000770_SCRATCH_UMSK(x) (((x) & 0x3F) << 0)
539#define G_000770_SCRATCH_UMSK(x) (((x) >> 0) & 0x3F)
540#define C_000770_SCRATCH_UMSK 0xFFFFFFC0
541#define S_000770_SCRATCH_SWAP(x) (((x) & 0x3) << 16)
542#define G_000770_SCRATCH_SWAP(x) (((x) >> 16) & 0x3)
543#define C_000770_SCRATCH_SWAP 0xFFFCFFFF
544#define R_000774_SCRATCH_ADDR 0x000774
545#define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5)
546#define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF)
547#define C_000774_SCRATCH_ADDR 0x0000001F
548#define R_000E40_RBBM_STATUS 0x000E40
549#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
550#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
551#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80
552#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)
553#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)
554#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF
555#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)
556#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)
557#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF
558#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)
559#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)
560#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF
561#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)
562#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)
563#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF
564#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)
565#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)
566#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF
567#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)
568#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)
569#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF
570#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)
571#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)
572#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF
573#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)
574#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)
575#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF
576#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)
577#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)
578#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF
579#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)
580#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)
581#define C_000E40_E2_BUSY 0xFFFDFFFF
582#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)
583#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)
584#define C_000E40_RB2D_BUSY 0xFFFBFFFF
585#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)
586#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)
587#define C_000E40_RB3D_BUSY 0xFFF7FFFF
588#define S_000E40_SE_BUSY(x) (((x) & 0x1) << 20)
589#define G_000E40_SE_BUSY(x) (((x) >> 20) & 0x1)
590#define C_000E40_SE_BUSY 0xFFEFFFFF
591#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)
592#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)
593#define C_000E40_RE_BUSY 0xFFDFFFFF
594#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)
595#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)
596#define C_000E40_TAM_BUSY 0xFFBFFFFF
597#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)
598#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)
599#define C_000E40_TDM_BUSY 0xFF7FFFFF
600#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)
601#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)
602#define C_000E40_PB_BUSY 0xFEFFFFFF
603#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)
604#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
605#define C_000E40_GUI_ACTIVE 0x7FFFFFFF
606
607#endif
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
new file mode 100644
index 000000000000..568c74bfba3d
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -0,0 +1,456 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "drm.h"
30#include "radeon_drm.h"
31#include "radeon_reg.h"
32#include "radeon.h"
33
34#include "r200_reg_safe.h"
35
36#include "r100_track.h"
37
38static int r200_get_vtx_size_0(uint32_t vtx_fmt_0)
39{
40 int vtx_size, i;
41 vtx_size = 2;
42
43 if (vtx_fmt_0 & R200_VTX_Z0)
44 vtx_size++;
45 if (vtx_fmt_0 & R200_VTX_W0)
46 vtx_size++;
47 /* blend weight */
48 if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT))
49 vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7;
50 if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL)
51 vtx_size++;
52 if (vtx_fmt_0 & R200_VTX_N0)
53 vtx_size += 3;
54 if (vtx_fmt_0 & R200_VTX_POINT_SIZE)
55 vtx_size++;
56 if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG)
57 vtx_size++;
58 if (vtx_fmt_0 & R200_VTX_SHININESS_0)
59 vtx_size++;
60 if (vtx_fmt_0 & R200_VTX_SHININESS_1)
61 vtx_size++;
62 for (i = 0; i < 8; i++) {
63 int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3;
64 switch (color_size) {
65 case 0: break;
66 case 1: vtx_size++; break;
67 case 2: vtx_size += 3; break;
68 case 3: vtx_size += 4; break;
69 }
70 }
71 if (vtx_fmt_0 & R200_VTX_XY1)
72 vtx_size += 2;
73 if (vtx_fmt_0 & R200_VTX_Z1)
74 vtx_size++;
75 if (vtx_fmt_0 & R200_VTX_W1)
76 vtx_size++;
77 if (vtx_fmt_0 & R200_VTX_N1)
78 vtx_size += 3;
79 return vtx_size;
80}
81
82static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)
83{
84 int vtx_size, i, tex_size;
85 vtx_size = 0;
86 for (i = 0; i < 6; i++) {
87 tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7;
88 if (tex_size > 4)
89 continue;
90 vtx_size += tex_size;
91 }
92 return vtx_size;
93}
94
95int r200_packet0_check(struct radeon_cs_parser *p,
96 struct radeon_cs_packet *pkt,
97 unsigned idx, unsigned reg)
98{
99 struct radeon_cs_chunk *ib_chunk;
100 struct radeon_cs_reloc *reloc;
101 struct r100_cs_track *track;
102 volatile uint32_t *ib;
103 uint32_t tmp;
104 int r;
105 int i;
106 int face;
107 u32 tile_flags = 0;
108
109 ib = p->ib->ptr;
110 ib_chunk = &p->chunks[p->chunk_ib_idx];
111 track = (struct r100_cs_track *)p->track;
112
113 switch (reg) {
114 case RADEON_CRTC_GUI_TRIG_VLINE:
115 r = r100_cs_packet_parse_vline(p);
116 if (r) {
117 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
118 idx, reg);
119 r100_cs_dump_packet(p, pkt);
120 return r;
121 }
122 break;
123 /* FIXME: only allow PACKET3 blit? easier to check for out of
124 * range access */
125 case RADEON_DST_PITCH_OFFSET:
126 case RADEON_SRC_PITCH_OFFSET:
127 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
128 if (r)
129 return r;
130 break;
131 case RADEON_RB3D_DEPTHOFFSET:
132 r = r100_cs_packet_next_reloc(p, &reloc);
133 if (r) {
134 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
135 idx, reg);
136 r100_cs_dump_packet(p, pkt);
137 return r;
138 }
139 track->zb.robj = reloc->robj;
140 track->zb.offset = ib_chunk->kdata[idx];
141 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
142 break;
143 case RADEON_RB3D_COLOROFFSET:
144 r = r100_cs_packet_next_reloc(p, &reloc);
145 if (r) {
146 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
147 idx, reg);
148 r100_cs_dump_packet(p, pkt);
149 return r;
150 }
151 track->cb[0].robj = reloc->robj;
152 track->cb[0].offset = ib_chunk->kdata[idx];
153 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
154 break;
155 case R200_PP_TXOFFSET_0:
156 case R200_PP_TXOFFSET_1:
157 case R200_PP_TXOFFSET_2:
158 case R200_PP_TXOFFSET_3:
159 case R200_PP_TXOFFSET_4:
160 case R200_PP_TXOFFSET_5:
161 i = (reg - R200_PP_TXOFFSET_0) / 24;
162 r = r100_cs_packet_next_reloc(p, &reloc);
163 if (r) {
164 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
165 idx, reg);
166 r100_cs_dump_packet(p, pkt);
167 return r;
168 }
169 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
170 track->textures[i].robj = reloc->robj;
171 break;
172 case R200_PP_CUBIC_OFFSET_F1_0:
173 case R200_PP_CUBIC_OFFSET_F2_0:
174 case R200_PP_CUBIC_OFFSET_F3_0:
175 case R200_PP_CUBIC_OFFSET_F4_0:
176 case R200_PP_CUBIC_OFFSET_F5_0:
177 case R200_PP_CUBIC_OFFSET_F1_1:
178 case R200_PP_CUBIC_OFFSET_F2_1:
179 case R200_PP_CUBIC_OFFSET_F3_1:
180 case R200_PP_CUBIC_OFFSET_F4_1:
181 case R200_PP_CUBIC_OFFSET_F5_1:
182 case R200_PP_CUBIC_OFFSET_F1_2:
183 case R200_PP_CUBIC_OFFSET_F2_2:
184 case R200_PP_CUBIC_OFFSET_F3_2:
185 case R200_PP_CUBIC_OFFSET_F4_2:
186 case R200_PP_CUBIC_OFFSET_F5_2:
187 case R200_PP_CUBIC_OFFSET_F1_3:
188 case R200_PP_CUBIC_OFFSET_F2_3:
189 case R200_PP_CUBIC_OFFSET_F3_3:
190 case R200_PP_CUBIC_OFFSET_F4_3:
191 case R200_PP_CUBIC_OFFSET_F5_3:
192 case R200_PP_CUBIC_OFFSET_F1_4:
193 case R200_PP_CUBIC_OFFSET_F2_4:
194 case R200_PP_CUBIC_OFFSET_F3_4:
195 case R200_PP_CUBIC_OFFSET_F4_4:
196 case R200_PP_CUBIC_OFFSET_F5_4:
197 case R200_PP_CUBIC_OFFSET_F1_5:
198 case R200_PP_CUBIC_OFFSET_F2_5:
199 case R200_PP_CUBIC_OFFSET_F3_5:
200 case R200_PP_CUBIC_OFFSET_F4_5:
201 case R200_PP_CUBIC_OFFSET_F5_5:
202 i = (reg - R200_PP_TXOFFSET_0) / 24;
203 face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
204 r = r100_cs_packet_next_reloc(p, &reloc);
205 if (r) {
206 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
207 idx, reg);
208 r100_cs_dump_packet(p, pkt);
209 return r;
210 }
211 track->textures[i].cube_info[face - 1].offset = ib_chunk->kdata[idx];
212 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
213 track->textures[i].cube_info[face - 1].robj = reloc->robj;
214 break;
215 case RADEON_RE_WIDTH_HEIGHT:
216 track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF);
217 break;
218 case RADEON_RB3D_COLORPITCH:
219 r = r100_cs_packet_next_reloc(p, &reloc);
220 if (r) {
221 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
222 idx, reg);
223 r100_cs_dump_packet(p, pkt);
224 return r;
225 }
226
227 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
228 tile_flags |= RADEON_COLOR_TILE_ENABLE;
229 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
230 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
231
232 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
233 tmp |= tile_flags;
234 ib[idx] = tmp;
235
236 track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK;
237 break;
238 case RADEON_RB3D_DEPTHPITCH:
239 track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK;
240 break;
241 case RADEON_RB3D_CNTL:
242 switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
243 case 7:
244 case 8:
245 case 9:
246 case 11:
247 case 12:
248 track->cb[0].cpp = 1;
249 break;
250 case 3:
251 case 4:
252 case 15:
253 track->cb[0].cpp = 2;
254 break;
255 case 6:
256 track->cb[0].cpp = 4;
257 break;
258 default:
259 DRM_ERROR("Invalid color buffer format (%d) !\n",
260 ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
261 return -EINVAL;
262 }
263 if (ib_chunk->kdata[idx] & RADEON_DEPTHXY_OFFSET_ENABLE) {
264 DRM_ERROR("No support for depth xy offset in kms\n");
265 return -EINVAL;
266 }
267
268 track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE);
269 break;
270 case RADEON_RB3D_ZSTENCILCNTL:
271 switch (ib_chunk->kdata[idx] & 0xf) {
272 case 0:
273 track->zb.cpp = 2;
274 break;
275 case 2:
276 case 3:
277 case 4:
278 case 5:
279 case 9:
280 case 11:
281 track->zb.cpp = 4;
282 break;
283 default:
284 break;
285 }
286 break;
287 case RADEON_RB3D_ZPASS_ADDR:
288 r = r100_cs_packet_next_reloc(p, &reloc);
289 if (r) {
290 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
291 idx, reg);
292 r100_cs_dump_packet(p, pkt);
293 return r;
294 }
295 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
296 break;
297 case RADEON_PP_CNTL:
298 {
299 uint32_t temp = ib_chunk->kdata[idx] >> 4;
300 for (i = 0; i < track->num_texture; i++)
301 track->textures[i].enabled = !!(temp & (1 << i));
302 }
303 break;
304 case RADEON_SE_VF_CNTL:
305 track->vap_vf_cntl = ib_chunk->kdata[idx];
306 break;
307 case 0x210c:
308 /* VAP_VF_MAX_VTX_INDX */
309 track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL;
310 break;
311 case R200_SE_VTX_FMT_0:
312 track->vtx_size = r200_get_vtx_size_0(ib_chunk->kdata[idx]);
313 break;
314 case R200_SE_VTX_FMT_1:
315 track->vtx_size += r200_get_vtx_size_1(ib_chunk->kdata[idx]);
316 break;
317 case R200_PP_TXSIZE_0:
318 case R200_PP_TXSIZE_1:
319 case R200_PP_TXSIZE_2:
320 case R200_PP_TXSIZE_3:
321 case R200_PP_TXSIZE_4:
322 case R200_PP_TXSIZE_5:
323 i = (reg - R200_PP_TXSIZE_0) / 32;
324 track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1;
325 track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
326 break;
327 case R200_PP_TXPITCH_0:
328 case R200_PP_TXPITCH_1:
329 case R200_PP_TXPITCH_2:
330 case R200_PP_TXPITCH_3:
331 case R200_PP_TXPITCH_4:
332 case R200_PP_TXPITCH_5:
333 i = (reg - R200_PP_TXPITCH_0) / 32;
334 track->textures[i].pitch = ib_chunk->kdata[idx] + 32;
335 break;
336 case R200_PP_TXFILTER_0:
337 case R200_PP_TXFILTER_1:
338 case R200_PP_TXFILTER_2:
339 case R200_PP_TXFILTER_3:
340 case R200_PP_TXFILTER_4:
341 case R200_PP_TXFILTER_5:
342 i = (reg - R200_PP_TXFILTER_0) / 32;
343 track->textures[i].num_levels = ((ib_chunk->kdata[idx] & R200_MAX_MIP_LEVEL_MASK)
344 >> R200_MAX_MIP_LEVEL_SHIFT);
345 tmp = (ib_chunk->kdata[idx] >> 23) & 0x7;
346 if (tmp == 2 || tmp == 6)
347 track->textures[i].roundup_w = false;
348 tmp = (ib_chunk->kdata[idx] >> 27) & 0x7;
349 if (tmp == 2 || tmp == 6)
350 track->textures[i].roundup_h = false;
351 break;
352 case R200_PP_TXMULTI_CTL_0:
353 case R200_PP_TXMULTI_CTL_1:
354 case R200_PP_TXMULTI_CTL_2:
355 case R200_PP_TXMULTI_CTL_3:
356 case R200_PP_TXMULTI_CTL_4:
357 case R200_PP_TXMULTI_CTL_5:
358 i = (reg - R200_PP_TXMULTI_CTL_0) / 32;
359 break;
360 case R200_PP_TXFORMAT_X_0:
361 case R200_PP_TXFORMAT_X_1:
362 case R200_PP_TXFORMAT_X_2:
363 case R200_PP_TXFORMAT_X_3:
364 case R200_PP_TXFORMAT_X_4:
365 case R200_PP_TXFORMAT_X_5:
366 i = (reg - R200_PP_TXFORMAT_X_0) / 32;
367 track->textures[i].txdepth = ib_chunk->kdata[idx] & 0x7;
368 tmp = (ib_chunk->kdata[idx] >> 16) & 0x3;
369 /* 2D, 3D, CUBE */
370 switch (tmp) {
371 case 0:
372 case 5:
373 case 6:
374 case 7:
375 track->textures[i].tex_coord_type = 0;
376 break;
377 case 1:
378 track->textures[i].tex_coord_type = 1;
379 break;
380 case 2:
381 track->textures[i].tex_coord_type = 2;
382 break;
383 }
384 break;
385 case R200_PP_TXFORMAT_0:
386 case R200_PP_TXFORMAT_1:
387 case R200_PP_TXFORMAT_2:
388 case R200_PP_TXFORMAT_3:
389 case R200_PP_TXFORMAT_4:
390 case R200_PP_TXFORMAT_5:
391 i = (reg - R200_PP_TXFORMAT_0) / 32;
392 if (ib_chunk->kdata[idx] & R200_TXFORMAT_NON_POWER2) {
393 track->textures[i].use_pitch = 1;
394 } else {
395 track->textures[i].use_pitch = 0;
396 track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
397 track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
398 }
399 switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) {
400 case R200_TXFORMAT_I8:
401 case R200_TXFORMAT_RGB332:
402 case R200_TXFORMAT_Y8:
403 track->textures[i].cpp = 1;
404 break;
405 case R200_TXFORMAT_DXT1:
406 case R200_TXFORMAT_AI88:
407 case R200_TXFORMAT_ARGB1555:
408 case R200_TXFORMAT_RGB565:
409 case R200_TXFORMAT_ARGB4444:
410 case R200_TXFORMAT_VYUY422:
411 case R200_TXFORMAT_YVYU422:
412 case R200_TXFORMAT_LDVDU655:
413 case R200_TXFORMAT_DVDU88:
414 case R200_TXFORMAT_AVYU4444:
415 track->textures[i].cpp = 2;
416 break;
417 case R200_TXFORMAT_ARGB8888:
418 case R200_TXFORMAT_RGBA8888:
419 case R200_TXFORMAT_ABGR8888:
420 case R200_TXFORMAT_BGR111110:
421 case R200_TXFORMAT_LDVDU8888:
422 case R200_TXFORMAT_DXT23:
423 case R200_TXFORMAT_DXT45:
424 track->textures[i].cpp = 4;
425 break;
426 }
427 track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf);
428 track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf);
429 break;
430 case R200_PP_CUBIC_FACES_0:
431 case R200_PP_CUBIC_FACES_1:
432 case R200_PP_CUBIC_FACES_2:
433 case R200_PP_CUBIC_FACES_3:
434 case R200_PP_CUBIC_FACES_4:
435 case R200_PP_CUBIC_FACES_5:
436 tmp = ib_chunk->kdata[idx];
437 i = (reg - R200_PP_CUBIC_FACES_0) / 32;
438 for (face = 0; face < 4; face++) {
439 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
440 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
441 }
442 break;
443 default:
444 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
445 reg, idx);
446 return -EINVAL;
447 }
448 return 0;
449}
450
451int r200_init(struct radeon_device *rdev)
452{
453 rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;
454 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);
455 return 0;
456}
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 051bca6e3a4f..bb151ecdf8fc 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -31,7 +31,10 @@
31#include "radeon_reg.h" 31#include "radeon_reg.h"
32#include "radeon.h" 32#include "radeon.h"
33#include "radeon_drm.h" 33#include "radeon_drm.h"
34#include "radeon_share.h" 34#include "r100_track.h"
35#include "r300d.h"
36
37#include "r300_reg_safe.h"
35 38
36/* r300,r350,rv350,rv370,rv380 depends on : */ 39/* r300,r350,rv350,rv370,rv380 depends on : */
37void r100_hdp_reset(struct radeon_device *rdev); 40void r100_hdp_reset(struct radeon_device *rdev);
@@ -39,7 +42,6 @@ int r100_cp_reset(struct radeon_device *rdev);
39int r100_rb2d_reset(struct radeon_device *rdev); 42int r100_rb2d_reset(struct radeon_device *rdev);
40int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 43int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
41int r100_pci_gart_enable(struct radeon_device *rdev); 44int r100_pci_gart_enable(struct radeon_device *rdev);
42void r100_pci_gart_disable(struct radeon_device *rdev);
43void r100_mc_setup(struct radeon_device *rdev); 45void r100_mc_setup(struct radeon_device *rdev);
44void r100_mc_disable_clients(struct radeon_device *rdev); 46void r100_mc_disable_clients(struct radeon_device *rdev);
45int r100_gui_wait_for_idle(struct radeon_device *rdev); 47int r100_gui_wait_for_idle(struct radeon_device *rdev);
@@ -47,14 +49,10 @@ int r100_cs_packet_parse(struct radeon_cs_parser *p,
47 struct radeon_cs_packet *pkt, 49 struct radeon_cs_packet *pkt,
48 unsigned idx); 50 unsigned idx);
49int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); 51int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
50int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
51 struct radeon_cs_reloc **cs_reloc);
52int r100_cs_parse_packet0(struct radeon_cs_parser *p, 52int r100_cs_parse_packet0(struct radeon_cs_parser *p,
53 struct radeon_cs_packet *pkt, 53 struct radeon_cs_packet *pkt,
54 const unsigned *auth, unsigned n, 54 const unsigned *auth, unsigned n,
55 radeon_packet0_check_t check); 55 radeon_packet0_check_t check);
56void r100_cs_dump_packet(struct radeon_cs_parser *p,
57 struct radeon_cs_packet *pkt);
58int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 56int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
59 struct radeon_cs_packet *pkt, 57 struct radeon_cs_packet *pkt,
60 struct radeon_object *robj); 58 struct radeon_object *robj);
@@ -87,26 +85,57 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
87 mb(); 85 mb();
88} 86}
89 87
90int rv370_pcie_gart_enable(struct radeon_device *rdev) 88int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
89{
90 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
91
92 if (i < 0 || i > rdev->gart.num_gpu_pages) {
93 return -EINVAL;
94 }
95 addr = (lower_32_bits(addr) >> 8) |
96 ((upper_32_bits(addr) & 0xff) << 24) |
97 0xc;
98 /* on x86 we want this to be CPU endian, on powerpc
99 * on powerpc without HW swappers, it'll get swapped on way
100 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
101 writel(addr, ((void __iomem *)ptr) + (i * 4));
102 return 0;
103}
104
105int rv370_pcie_gart_init(struct radeon_device *rdev)
91{ 106{
92 uint32_t table_addr;
93 uint32_t tmp;
94 int r; 107 int r;
95 108
109 if (rdev->gart.table.vram.robj) {
110 WARN(1, "RV370 PCIE GART already initialized.\n");
111 return 0;
112 }
96 /* Initialize common gart structure */ 113 /* Initialize common gart structure */
97 r = radeon_gart_init(rdev); 114 r = radeon_gart_init(rdev);
98 if (r) { 115 if (r)
99 return r; 116 return r;
100 }
101 r = rv370_debugfs_pcie_gart_info_init(rdev); 117 r = rv370_debugfs_pcie_gart_info_init(rdev);
102 if (r) { 118 if (r)
103 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); 119 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
104 }
105 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 120 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
106 r = radeon_gart_table_vram_alloc(rdev); 121 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
107 if (r) { 122 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
108 return r; 123 return radeon_gart_table_vram_alloc(rdev);
124}
125
126int rv370_pcie_gart_enable(struct radeon_device *rdev)
127{
128 uint32_t table_addr;
129 uint32_t tmp;
130 int r;
131
132 if (rdev->gart.table.vram.robj == NULL) {
133 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
134 return -EINVAL;
109 } 135 }
136 r = radeon_gart_table_vram_pin(rdev);
137 if (r)
138 return r;
110 /* discard memory request outside of configured range */ 139 /* discard memory request outside of configured range */
111 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 140 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
112 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 141 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
@@ -128,7 +157,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
128 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 157 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
129 rv370_pcie_gart_tlb_flush(rdev); 158 rv370_pcie_gart_tlb_flush(rdev);
130 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n", 159 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
131 rdev->mc.gtt_size >> 20, table_addr); 160 (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
132 rdev->gart.ready = true; 161 rdev->gart.ready = true;
133 return 0; 162 return 0;
134} 163}
@@ -146,45 +175,13 @@ void rv370_pcie_gart_disable(struct radeon_device *rdev)
146 } 175 }
147} 176}
148 177
149int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 178void rv370_pcie_gart_fini(struct radeon_device *rdev)
150{ 179{
151 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; 180 rv370_pcie_gart_disable(rdev);
152 181 radeon_gart_table_vram_free(rdev);
153 if (i < 0 || i > rdev->gart.num_gpu_pages) { 182 radeon_gart_fini(rdev);
154 return -EINVAL;
155 }
156 addr = (lower_32_bits(addr) >> 8) |
157 ((upper_32_bits(addr) & 0xff) << 24) |
158 0xc;
159 /* on x86 we want this to be CPU endian, on powerpc
160 * on powerpc without HW swappers, it'll get swapped on way
161 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
162 writel(addr, ((void __iomem *)ptr) + (i * 4));
163 return 0;
164}
165
166int r300_gart_enable(struct radeon_device *rdev)
167{
168#if __OS_HAS_AGP
169 if (rdev->flags & RADEON_IS_AGP) {
170 if (rdev->family > CHIP_RV350) {
171 rv370_pcie_gart_disable(rdev);
172 } else {
173 r100_pci_gart_disable(rdev);
174 }
175 return 0;
176 }
177#endif
178 if (rdev->flags & RADEON_IS_PCIE) {
179 rdev->asic->gart_disable = &rv370_pcie_gart_disable;
180 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
181 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
182 return rv370_pcie_gart_enable(rdev);
183 }
184 return r100_pci_gart_enable(rdev);
185} 183}
186 184
187
188/* 185/*
189 * MC 186 * MC
190 */ 187 */
@@ -232,14 +229,6 @@ int r300_mc_init(struct radeon_device *rdev)
232 229
233void r300_mc_fini(struct radeon_device *rdev) 230void r300_mc_fini(struct radeon_device *rdev)
234{ 231{
235 if (rdev->flags & RADEON_IS_PCIE) {
236 rv370_pcie_gart_disable(rdev);
237 radeon_gart_table_vram_free(rdev);
238 } else {
239 r100_pci_gart_disable(rdev);
240 radeon_gart_table_ram_free(rdev);
241 }
242 radeon_gart_fini(rdev);
243} 232}
244 233
245 234
@@ -704,307 +693,13 @@ int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
704/* 693/*
705 * CS functions 694 * CS functions
706 */ 695 */
707struct r300_cs_track_cb {
708 struct radeon_object *robj;
709 unsigned pitch;
710 unsigned cpp;
711 unsigned offset;
712};
713
714struct r300_cs_track_array {
715 struct radeon_object *robj;
716 unsigned esize;
717};
718
719struct r300_cs_track_texture {
720 struct radeon_object *robj;
721 unsigned pitch;
722 unsigned width;
723 unsigned height;
724 unsigned num_levels;
725 unsigned cpp;
726 unsigned tex_coord_type;
727 unsigned txdepth;
728 unsigned width_11;
729 unsigned height_11;
730 bool use_pitch;
731 bool enabled;
732 bool roundup_w;
733 bool roundup_h;
734};
735
736struct r300_cs_track {
737 unsigned num_cb;
738 unsigned maxy;
739 unsigned vtx_size;
740 unsigned vap_vf_cntl;
741 unsigned immd_dwords;
742 unsigned num_arrays;
743 unsigned max_indx;
744 struct r300_cs_track_array arrays[11];
745 struct r300_cs_track_cb cb[4];
746 struct r300_cs_track_cb zb;
747 struct r300_cs_track_texture textures[16];
748 bool z_enabled;
749};
750
751static inline void r300_cs_track_texture_print(struct r300_cs_track_texture *t)
752{
753 DRM_ERROR("pitch %d\n", t->pitch);
754 DRM_ERROR("width %d\n", t->width);
755 DRM_ERROR("height %d\n", t->height);
756 DRM_ERROR("num levels %d\n", t->num_levels);
757 DRM_ERROR("depth %d\n", t->txdepth);
758 DRM_ERROR("bpp %d\n", t->cpp);
759 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
760 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
761 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
762}
763
764static inline int r300_cs_track_texture_check(struct radeon_device *rdev,
765 struct r300_cs_track *track)
766{
767 struct radeon_object *robj;
768 unsigned long size;
769 unsigned u, i, w, h;
770
771 for (u = 0; u < 16; u++) {
772 if (!track->textures[u].enabled)
773 continue;
774 robj = track->textures[u].robj;
775 if (robj == NULL) {
776 DRM_ERROR("No texture bound to unit %u\n", u);
777 return -EINVAL;
778 }
779 size = 0;
780 for (i = 0; i <= track->textures[u].num_levels; i++) {
781 if (track->textures[u].use_pitch) {
782 w = track->textures[u].pitch / (1 << i);
783 } else {
784 w = track->textures[u].width / (1 << i);
785 if (rdev->family >= CHIP_RV515)
786 w |= track->textures[u].width_11;
787 if (track->textures[u].roundup_w)
788 w = roundup_pow_of_two(w);
789 }
790 h = track->textures[u].height / (1 << i);
791 if (rdev->family >= CHIP_RV515)
792 h |= track->textures[u].height_11;
793 if (track->textures[u].roundup_h)
794 h = roundup_pow_of_two(h);
795 size += w * h;
796 }
797 size *= track->textures[u].cpp;
798 switch (track->textures[u].tex_coord_type) {
799 case 0:
800 break;
801 case 1:
802 size *= (1 << track->textures[u].txdepth);
803 break;
804 case 2:
805 size *= 6;
806 break;
807 default:
808 DRM_ERROR("Invalid texture coordinate type %u for unit "
809 "%u\n", track->textures[u].tex_coord_type, u);
810 return -EINVAL;
811 }
812 if (size > radeon_object_size(robj)) {
813 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
814 "%lu\n", u, size, radeon_object_size(robj));
815 r300_cs_track_texture_print(&track->textures[u]);
816 return -EINVAL;
817 }
818 }
819 return 0;
820}
821
822int r300_cs_track_check(struct radeon_device *rdev, struct r300_cs_track *track)
823{
824 unsigned i;
825 unsigned long size;
826 unsigned prim_walk;
827 unsigned nverts;
828
829 for (i = 0; i < track->num_cb; i++) {
830 if (track->cb[i].robj == NULL) {
831 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
832 return -EINVAL;
833 }
834 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
835 size += track->cb[i].offset;
836 if (size > radeon_object_size(track->cb[i].robj)) {
837 DRM_ERROR("[drm] Buffer too small for color buffer %d "
838 "(need %lu have %lu) !\n", i, size,
839 radeon_object_size(track->cb[i].robj));
840 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
841 i, track->cb[i].pitch, track->cb[i].cpp,
842 track->cb[i].offset, track->maxy);
843 return -EINVAL;
844 }
845 }
846 if (track->z_enabled) {
847 if (track->zb.robj == NULL) {
848 DRM_ERROR("[drm] No buffer for z buffer !\n");
849 return -EINVAL;
850 }
851 size = track->zb.pitch * track->zb.cpp * track->maxy;
852 size += track->zb.offset;
853 if (size > radeon_object_size(track->zb.robj)) {
854 DRM_ERROR("[drm] Buffer too small for z buffer "
855 "(need %lu have %lu) !\n", size,
856 radeon_object_size(track->zb.robj));
857 return -EINVAL;
858 }
859 }
860 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
861 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
862 switch (prim_walk) {
863 case 1:
864 for (i = 0; i < track->num_arrays; i++) {
865 size = track->arrays[i].esize * track->max_indx * 4;
866 if (track->arrays[i].robj == NULL) {
867 DRM_ERROR("(PW %u) Vertex array %u no buffer "
868 "bound\n", prim_walk, i);
869 return -EINVAL;
870 }
871 if (size > radeon_object_size(track->arrays[i].robj)) {
872 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
873 "have %lu dwords\n", prim_walk, i,
874 size >> 2,
875 radeon_object_size(track->arrays[i].robj) >> 2);
876 DRM_ERROR("Max indices %u\n", track->max_indx);
877 return -EINVAL;
878 }
879 }
880 break;
881 case 2:
882 for (i = 0; i < track->num_arrays; i++) {
883 size = track->arrays[i].esize * (nverts - 1) * 4;
884 if (track->arrays[i].robj == NULL) {
885 DRM_ERROR("(PW %u) Vertex array %u no buffer "
886 "bound\n", prim_walk, i);
887 return -EINVAL;
888 }
889 if (size > radeon_object_size(track->arrays[i].robj)) {
890 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
891 "have %lu dwords\n", prim_walk, i, size >> 2,
892 radeon_object_size(track->arrays[i].robj) >> 2);
893 return -EINVAL;
894 }
895 }
896 break;
897 case 3:
898 size = track->vtx_size * nverts;
899 if (size != track->immd_dwords) {
900 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
901 track->immd_dwords, size);
902 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
903 nverts, track->vtx_size);
904 return -EINVAL;
905 }
906 break;
907 default:
908 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
909 prim_walk);
910 return -EINVAL;
911 }
912 return r300_cs_track_texture_check(rdev, track);
913}
914
915static inline void r300_cs_track_clear(struct r300_cs_track *track)
916{
917 unsigned i;
918
919 track->num_cb = 4;
920 track->maxy = 4096;
921 for (i = 0; i < track->num_cb; i++) {
922 track->cb[i].robj = NULL;
923 track->cb[i].pitch = 8192;
924 track->cb[i].cpp = 16;
925 track->cb[i].offset = 0;
926 }
927 track->z_enabled = true;
928 track->zb.robj = NULL;
929 track->zb.pitch = 8192;
930 track->zb.cpp = 4;
931 track->zb.offset = 0;
932 track->vtx_size = 0x7F;
933 track->immd_dwords = 0xFFFFFFFFUL;
934 track->num_arrays = 11;
935 track->max_indx = 0x00FFFFFFUL;
936 for (i = 0; i < track->num_arrays; i++) {
937 track->arrays[i].robj = NULL;
938 track->arrays[i].esize = 0x7F;
939 }
940 for (i = 0; i < 16; i++) {
941 track->textures[i].pitch = 16536;
942 track->textures[i].width = 16536;
943 track->textures[i].height = 16536;
944 track->textures[i].width_11 = 1 << 11;
945 track->textures[i].height_11 = 1 << 11;
946 track->textures[i].num_levels = 12;
947 track->textures[i].txdepth = 16;
948 track->textures[i].cpp = 64;
949 track->textures[i].tex_coord_type = 1;
950 track->textures[i].robj = NULL;
951 /* CS IB emission code makes sure texture unit are disabled */
952 track->textures[i].enabled = false;
953 track->textures[i].roundup_w = true;
954 track->textures[i].roundup_h = true;
955 }
956}
957
958static const unsigned r300_reg_safe_bm[159] = {
959 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
960 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
961 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
962 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
963 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
964 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
965 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
966 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
967 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
968 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
969 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
970 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
971 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
972 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
973 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
974 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
975 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
976 0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
977 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
978 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
979 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
980 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
981 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
982 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
983 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
984 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
985 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
986 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
987 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
988 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
989 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
990 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
991 0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFF,
992 0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF,
993 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
994 0x00000000, 0x0000C100, 0x00000000, 0x00000000,
995 0x00000000, 0x00000000, 0x00000000, 0x00000000,
996 0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF,
997 0x00000000, 0x00000000, 0x00000000, 0x00000000,
998 0x0003FC01, 0xFFFFFCF8, 0xFF800B19,
999};
1000
1001static int r300_packet0_check(struct radeon_cs_parser *p, 696static int r300_packet0_check(struct radeon_cs_parser *p,
1002 struct radeon_cs_packet *pkt, 697 struct radeon_cs_packet *pkt,
1003 unsigned idx, unsigned reg) 698 unsigned idx, unsigned reg)
1004{ 699{
1005 struct radeon_cs_chunk *ib_chunk; 700 struct radeon_cs_chunk *ib_chunk;
1006 struct radeon_cs_reloc *reloc; 701 struct radeon_cs_reloc *reloc;
1007 struct r300_cs_track *track; 702 struct r100_cs_track *track;
1008 volatile uint32_t *ib; 703 volatile uint32_t *ib;
1009 uint32_t tmp, tile_flags = 0; 704 uint32_t tmp, tile_flags = 0;
1010 unsigned i; 705 unsigned i;
@@ -1012,7 +707,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1012 707
1013 ib = p->ib->ptr; 708 ib = p->ib->ptr;
1014 ib_chunk = &p->chunks[p->chunk_ib_idx]; 709 ib_chunk = &p->chunks[p->chunk_ib_idx];
1015 track = (struct r300_cs_track*)p->track; 710 track = (struct r100_cs_track *)p->track;
1016 switch(reg) { 711 switch(reg) {
1017 case AVIVO_D1MODE_VLINE_START_END: 712 case AVIVO_D1MODE_VLINE_START_END:
1018 case RADEON_CRTC_GUI_TRIG_VLINE: 713 case RADEON_CRTC_GUI_TRIG_VLINE:
@@ -1026,28 +721,9 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1026 break; 721 break;
1027 case RADEON_DST_PITCH_OFFSET: 722 case RADEON_DST_PITCH_OFFSET:
1028 case RADEON_SRC_PITCH_OFFSET: 723 case RADEON_SRC_PITCH_OFFSET:
1029 r = r100_cs_packet_next_reloc(p, &reloc); 724 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1030 if (r) { 725 if (r)
1031 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1032 idx, reg);
1033 r100_cs_dump_packet(p, pkt);
1034 return r; 726 return r;
1035 }
1036 tmp = ib_chunk->kdata[idx] & 0x003fffff;
1037 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
1038
1039 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1040 tile_flags |= RADEON_DST_TILE_MACRO;
1041 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1042 if (reg == RADEON_SRC_PITCH_OFFSET) {
1043 DRM_ERROR("Cannot src blit from microtiled surface\n");
1044 r100_cs_dump_packet(p, pkt);
1045 return -EINVAL;
1046 }
1047 tile_flags |= RADEON_DST_TILE_MICRO;
1048 }
1049 tmp |= tile_flags;
1050 ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
1051 break; 727 break;
1052 case R300_RB3D_COLOROFFSET0: 728 case R300_RB3D_COLOROFFSET0:
1053 case R300_RB3D_COLOROFFSET1: 729 case R300_RB3D_COLOROFFSET1:
@@ -1256,42 +932,41 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1256 tmp = (ib_chunk->kdata[idx] >> 25) & 0x3; 932 tmp = (ib_chunk->kdata[idx] >> 25) & 0x3;
1257 track->textures[i].tex_coord_type = tmp; 933 track->textures[i].tex_coord_type = tmp;
1258 switch ((ib_chunk->kdata[idx] & 0x1F)) { 934 switch ((ib_chunk->kdata[idx] & 0x1F)) {
1259 case 0: 935 case R300_TX_FORMAT_X8:
1260 case 2: 936 case R300_TX_FORMAT_Y4X4:
1261 case 5: 937 case R300_TX_FORMAT_Z3Y3X2:
1262 case 18:
1263 case 20:
1264 case 21:
1265 track->textures[i].cpp = 1; 938 track->textures[i].cpp = 1;
1266 break; 939 break;
1267 case 1: 940 case R300_TX_FORMAT_X16:
1268 case 3: 941 case R300_TX_FORMAT_Y8X8:
1269 case 6: 942 case R300_TX_FORMAT_Z5Y6X5:
1270 case 7: 943 case R300_TX_FORMAT_Z6Y5X5:
1271 case 10: 944 case R300_TX_FORMAT_W4Z4Y4X4:
1272 case 11: 945 case R300_TX_FORMAT_W1Z5Y5X5:
1273 case 19: 946 case R300_TX_FORMAT_DXT1:
1274 case 22: 947 case R300_TX_FORMAT_D3DMFT_CxV8U8:
1275 case 24: 948 case R300_TX_FORMAT_B8G8_B8G8:
949 case R300_TX_FORMAT_G8R8_G8B8:
1276 track->textures[i].cpp = 2; 950 track->textures[i].cpp = 2;
1277 break; 951 break;
1278 case 4: 952 case R300_TX_FORMAT_Y16X16:
1279 case 8: 953 case R300_TX_FORMAT_Z11Y11X10:
1280 case 9: 954 case R300_TX_FORMAT_Z10Y11X11:
1281 case 12: 955 case R300_TX_FORMAT_W8Z8Y8X8:
1282 case 13: 956 case R300_TX_FORMAT_W2Z10Y10X10:
1283 case 23: 957 case 0x17:
1284 case 25: 958 case R300_TX_FORMAT_FL_I32:
1285 case 27: 959 case 0x1e:
1286 case 30: 960 case R300_TX_FORMAT_DXT3:
961 case R300_TX_FORMAT_DXT5:
1287 track->textures[i].cpp = 4; 962 track->textures[i].cpp = 4;
1288 break; 963 break;
1289 case 14: 964 case R300_TX_FORMAT_W16Z16Y16X16:
1290 case 26: 965 case R300_TX_FORMAT_FL_R16G16B16A16:
1291 case 28: 966 case R300_TX_FORMAT_FL_I32A32:
1292 track->textures[i].cpp = 8; 967 track->textures[i].cpp = 8;
1293 break; 968 break;
1294 case 29: 969 case R300_TX_FORMAT_FL_R32G32B32A32:
1295 track->textures[i].cpp = 16; 970 track->textures[i].cpp = 16;
1296 break; 971 break;
1297 default: 972 default:
@@ -1319,11 +994,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1319 case 0x443C: 994 case 0x443C:
1320 /* TX_FILTER0_[0-15] */ 995 /* TX_FILTER0_[0-15] */
1321 i = (reg - 0x4400) >> 2; 996 i = (reg - 0x4400) >> 2;
1322 tmp = ib_chunk->kdata[idx] & 0x7;; 997 tmp = ib_chunk->kdata[idx] & 0x7;
1323 if (tmp == 2 || tmp == 4 || tmp == 6) { 998 if (tmp == 2 || tmp == 4 || tmp == 6) {
1324 track->textures[i].roundup_w = false; 999 track->textures[i].roundup_w = false;
1325 } 1000 }
1326 tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;; 1001 tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;
1327 if (tmp == 2 || tmp == 4 || tmp == 6) { 1002 if (tmp == 2 || tmp == 4 || tmp == 6) {
1328 track->textures[i].roundup_h = false; 1003 track->textures[i].roundup_h = false;
1329 } 1004 }
@@ -1411,8 +1086,9 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1411 struct radeon_cs_packet *pkt) 1086 struct radeon_cs_packet *pkt)
1412{ 1087{
1413 struct radeon_cs_chunk *ib_chunk; 1088 struct radeon_cs_chunk *ib_chunk;
1089
1414 struct radeon_cs_reloc *reloc; 1090 struct radeon_cs_reloc *reloc;
1415 struct r300_cs_track *track; 1091 struct r100_cs_track *track;
1416 volatile uint32_t *ib; 1092 volatile uint32_t *ib;
1417 unsigned idx; 1093 unsigned idx;
1418 unsigned i, c; 1094 unsigned i, c;
@@ -1421,7 +1097,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1421 ib = p->ib->ptr; 1097 ib = p->ib->ptr;
1422 ib_chunk = &p->chunks[p->chunk_ib_idx]; 1098 ib_chunk = &p->chunks[p->chunk_ib_idx];
1423 idx = pkt->idx + 1; 1099 idx = pkt->idx + 1;
1424 track = (struct r300_cs_track*)p->track; 1100 track = (struct r100_cs_track *)p->track;
1425 switch(pkt->opcode) { 1101 switch(pkt->opcode) {
1426 case PACKET3_3D_LOAD_VBPNTR: 1102 case PACKET3_3D_LOAD_VBPNTR:
1427 c = ib_chunk->kdata[idx++] & 0x1F; 1103 c = ib_chunk->kdata[idx++] & 0x1F;
@@ -1488,7 +1164,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1488 } 1164 }
1489 track->vap_vf_cntl = ib_chunk->kdata[idx+1]; 1165 track->vap_vf_cntl = ib_chunk->kdata[idx+1];
1490 track->immd_dwords = pkt->count - 1; 1166 track->immd_dwords = pkt->count - 1;
1491 r = r300_cs_track_check(p->rdev, track); 1167 r = r100_cs_track_check(p->rdev, track);
1492 if (r) { 1168 if (r) {
1493 return r; 1169 return r;
1494 } 1170 }
@@ -1503,35 +1179,35 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1503 } 1179 }
1504 track->vap_vf_cntl = ib_chunk->kdata[idx]; 1180 track->vap_vf_cntl = ib_chunk->kdata[idx];
1505 track->immd_dwords = pkt->count; 1181 track->immd_dwords = pkt->count;
1506 r = r300_cs_track_check(p->rdev, track); 1182 r = r100_cs_track_check(p->rdev, track);
1507 if (r) { 1183 if (r) {
1508 return r; 1184 return r;
1509 } 1185 }
1510 break; 1186 break;
1511 case PACKET3_3D_DRAW_VBUF: 1187 case PACKET3_3D_DRAW_VBUF:
1512 track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; 1188 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1513 r = r300_cs_track_check(p->rdev, track); 1189 r = r100_cs_track_check(p->rdev, track);
1514 if (r) { 1190 if (r) {
1515 return r; 1191 return r;
1516 } 1192 }
1517 break; 1193 break;
1518 case PACKET3_3D_DRAW_VBUF_2: 1194 case PACKET3_3D_DRAW_VBUF_2:
1519 track->vap_vf_cntl = ib_chunk->kdata[idx]; 1195 track->vap_vf_cntl = ib_chunk->kdata[idx];
1520 r = r300_cs_track_check(p->rdev, track); 1196 r = r100_cs_track_check(p->rdev, track);
1521 if (r) { 1197 if (r) {
1522 return r; 1198 return r;
1523 } 1199 }
1524 break; 1200 break;
1525 case PACKET3_3D_DRAW_INDX: 1201 case PACKET3_3D_DRAW_INDX:
1526 track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; 1202 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1527 r = r300_cs_track_check(p->rdev, track); 1203 r = r100_cs_track_check(p->rdev, track);
1528 if (r) { 1204 if (r) {
1529 return r; 1205 return r;
1530 } 1206 }
1531 break; 1207 break;
1532 case PACKET3_3D_DRAW_INDX_2: 1208 case PACKET3_3D_DRAW_INDX_2:
1533 track->vap_vf_cntl = ib_chunk->kdata[idx]; 1209 track->vap_vf_cntl = ib_chunk->kdata[idx];
1534 r = r300_cs_track_check(p->rdev, track); 1210 r = r100_cs_track_check(p->rdev, track);
1535 if (r) { 1211 if (r) {
1536 return r; 1212 return r;
1537 } 1213 }
@@ -1548,11 +1224,12 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1548int r300_cs_parse(struct radeon_cs_parser *p) 1224int r300_cs_parse(struct radeon_cs_parser *p)
1549{ 1225{
1550 struct radeon_cs_packet pkt; 1226 struct radeon_cs_packet pkt;
1551 struct r300_cs_track track; 1227 struct r100_cs_track *track;
1552 int r; 1228 int r;
1553 1229
1554 r300_cs_track_clear(&track); 1230 track = kzalloc(sizeof(*track), GFP_KERNEL);
1555 p->track = &track; 1231 r100_cs_track_clear(p->rdev, track);
1232 p->track = track;
1556 do { 1233 do {
1557 r = r100_cs_packet_parse(p, &pkt, p->idx); 1234 r = r100_cs_packet_parse(p, &pkt, p->idx);
1558 if (r) { 1235 if (r) {
@@ -1582,9 +1259,48 @@ int r300_cs_parse(struct radeon_cs_parser *p)
1582 return 0; 1259 return 0;
1583} 1260}
1584 1261
1585int r300_init(struct radeon_device *rdev) 1262void r300_set_reg_safe(struct radeon_device *rdev)
1586{ 1263{
1587 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; 1264 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1588 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); 1265 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1266}
1267
1268int r300_init(struct radeon_device *rdev)
1269{
1270 r300_set_reg_safe(rdev);
1589 return 0; 1271 return 0;
1590} 1272}
1273
1274void r300_mc_program(struct radeon_device *rdev)
1275{
1276 struct r100_mc_save save;
1277 int r;
1278
1279 r = r100_debugfs_mc_info_init(rdev);
1280 if (r) {
1281 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1282 }
1283
1284 /* Stops all mc clients */
1285 r100_mc_stop(rdev, &save);
1286 if (rdev->flags & RADEON_IS_AGP) {
1287 WREG32(R_00014C_MC_AGP_LOCATION,
1288 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1289 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1290 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1291 WREG32(R_00015C_AGP_BASE_2,
1292 upper_32_bits(rdev->mc.agp_base) & 0xff);
1293 } else {
1294 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1295 WREG32(R_000170_AGP_BASE, 0);
1296 WREG32(R_00015C_AGP_BASE_2, 0);
1297 }
1298 /* Wait for mc idle */
1299 if (r300_mc_wait_for_idle(rdev))
1300 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1301 /* Program MC, should be a 32bits limited address space */
1302 WREG32(R_000148_MC_FB_LOCATION,
1303 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1304 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1305 r100_mc_resume(rdev, &save);
1306}
diff --git a/drivers/gpu/drm/radeon/r300.h b/drivers/gpu/drm/radeon/r300.h
deleted file mode 100644
index 8486b4da9d69..000000000000
--- a/drivers/gpu/drm/radeon/r300.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef R300_H
29#define R300_H
30
31struct r300_asic {
32 const unsigned *reg_safe_bm;
33 unsigned reg_safe_bm_size;
34};
35
36#endif
diff --git a/drivers/gpu/drm/radeon/r300d.h b/drivers/gpu/drm/radeon/r300d.h
new file mode 100644
index 000000000000..d4fa3eb1074f
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r300d.h
@@ -0,0 +1,101 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __R300D_H__
29#define __R300D_H__
30
31#define CP_PACKET0 0x00000000
32#define PACKET0_BASE_INDEX_SHIFT 0
33#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
34#define PACKET0_COUNT_SHIFT 16
35#define PACKET0_COUNT_MASK (0x3fff << 16)
36#define CP_PACKET1 0x40000000
37#define CP_PACKET2 0x80000000
38#define PACKET2_PAD_SHIFT 0
39#define PACKET2_PAD_MASK (0x3fffffff << 0)
40#define CP_PACKET3 0xC0000000
41#define PACKET3_IT_OPCODE_SHIFT 8
42#define PACKET3_IT_OPCODE_MASK (0xff << 8)
43#define PACKET3_COUNT_SHIFT 16
44#define PACKET3_COUNT_MASK (0x3fff << 16)
45/* PACKET3 op code */
46#define PACKET3_NOP 0x10
47#define PACKET3_3D_DRAW_VBUF 0x28
48#define PACKET3_3D_DRAW_IMMD 0x29
49#define PACKET3_3D_DRAW_INDX 0x2A
50#define PACKET3_3D_LOAD_VBPNTR 0x2F
51#define PACKET3_INDX_BUFFER 0x33
52#define PACKET3_3D_DRAW_VBUF_2 0x34
53#define PACKET3_3D_DRAW_IMMD_2 0x35
54#define PACKET3_3D_DRAW_INDX_2 0x36
55#define PACKET3_BITBLT_MULTI 0x9B
56
57#define PACKET0(reg, n) (CP_PACKET0 | \
58 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
59 REG_SET(PACKET0_COUNT, (n)))
60#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
61#define PACKET3(op, n) (CP_PACKET3 | \
62 REG_SET(PACKET3_IT_OPCODE, (op)) | \
63 REG_SET(PACKET3_COUNT, (n)))
64
65#define PACKET_TYPE0 0
66#define PACKET_TYPE1 1
67#define PACKET_TYPE2 2
68#define PACKET_TYPE3 3
69
70#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
71#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
72#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
73#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
74#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
75
76/* Registers */
77#define R_000148_MC_FB_LOCATION 0x000148
78#define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0)
79#define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
80#define C_000148_MC_FB_START 0xFFFF0000
81#define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
82#define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
83#define C_000148_MC_FB_TOP 0x0000FFFF
84#define R_00014C_MC_AGP_LOCATION 0x00014C
85#define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0)
86#define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF)
87#define C_00014C_MC_AGP_START 0xFFFF0000
88#define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16)
89#define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF)
90#define C_00014C_MC_AGP_TOP 0x0000FFFF
91#define R_00015C_AGP_BASE_2 0x00015C
92#define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0)
93#define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF)
94#define C_00015C_AGP_BASE_ADDR_2 0xFFFFFFF0
95#define R_000170_AGP_BASE 0x000170
96#define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
97#define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
98#define C_000170_AGP_BASE_ADDR 0x00000000
99
100
101#endif
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 97426a6f370f..49a2fdc57d27 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -29,47 +29,13 @@
29#include "drmP.h" 29#include "drmP.h"
30#include "radeon_reg.h" 30#include "radeon_reg.h"
31#include "radeon.h" 31#include "radeon.h"
32#include "atom.h"
33#include "r420d.h"
32 34
33/* r420,r423,rv410 depends on : */
34void r100_pci_gart_disable(struct radeon_device *rdev);
35void r100_hdp_reset(struct radeon_device *rdev);
36void r100_mc_setup(struct radeon_device *rdev);
37int r100_gui_wait_for_idle(struct radeon_device *rdev);
38void r100_mc_disable_clients(struct radeon_device *rdev);
39void r300_vram_info(struct radeon_device *rdev);
40int r300_mc_wait_for_idle(struct radeon_device *rdev);
41int rv370_pcie_gart_enable(struct radeon_device *rdev);
42void rv370_pcie_gart_disable(struct radeon_device *rdev);
43
44/* This files gather functions specifics to :
45 * r420,r423,rv410
46 *
47 * Some of these functions might be used by newer ASICs.
48 */
49void r420_gpu_init(struct radeon_device *rdev);
50int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
51
52
53/*
54 * MC
55 */
56int r420_mc_init(struct radeon_device *rdev) 35int r420_mc_init(struct radeon_device *rdev)
57{ 36{
58 int r; 37 int r;
59 38
60 if (r100_debugfs_rbbm_init(rdev)) {
61 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
62 }
63 if (r420_debugfs_pipes_info_init(rdev)) {
64 DRM_ERROR("Failed to register debugfs file for pipes !\n");
65 }
66
67 r420_gpu_init(rdev);
68 r100_pci_gart_disable(rdev);
69 if (rdev->flags & RADEON_IS_PCIE) {
70 rv370_pcie_gart_disable(rdev);
71 }
72
73 /* Setup GPU memory space */ 39 /* Setup GPU memory space */
74 rdev->mc.vram_location = 0xFFFFFFFFUL; 40 rdev->mc.vram_location = 0xFFFFFFFFUL;
75 rdev->mc.gtt_location = 0xFFFFFFFFUL; 41 rdev->mc.gtt_location = 0xFFFFFFFFUL;
@@ -87,33 +53,9 @@ int r420_mc_init(struct radeon_device *rdev)
87 if (r) { 53 if (r) {
88 return r; 54 return r;
89 } 55 }
90
91 /* Program GPU memory space */
92 r100_mc_disable_clients(rdev);
93 if (r300_mc_wait_for_idle(rdev)) {
94 printk(KERN_WARNING "Failed to wait MC idle while "
95 "programming pipes. Bad things might happen.\n");
96 }
97 r100_mc_setup(rdev);
98 return 0; 56 return 0;
99} 57}
100 58
101void r420_mc_fini(struct radeon_device *rdev)
102{
103 rv370_pcie_gart_disable(rdev);
104 radeon_gart_table_vram_free(rdev);
105 radeon_gart_fini(rdev);
106}
107
108
109/*
110 * Global GPU functions
111 */
112void r420_errata(struct radeon_device *rdev)
113{
114 rdev->pll_errata = 0;
115}
116
117void r420_pipes_init(struct radeon_device *rdev) 59void r420_pipes_init(struct radeon_device *rdev)
118{ 60{
119 unsigned tmp; 61 unsigned tmp;
@@ -122,6 +64,11 @@ void r420_pipes_init(struct radeon_device *rdev)
122 64
123 /* GA_ENHANCE workaround TCL deadlock issue */ 65 /* GA_ENHANCE workaround TCL deadlock issue */
124 WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)); 66 WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
67 /* add idle wait as per freedesktop.org bug 24041 */
68 if (r100_gui_wait_for_idle(rdev)) {
69 printk(KERN_WARNING "Failed to wait GUI idle while "
70 "programming pipes. Bad things might happen.\n");
71 }
125 /* get max number of pipes */ 72 /* get max number of pipes */
126 gb_pipe_select = RREG32(0x402C); 73 gb_pipe_select = RREG32(0x402C);
127 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; 74 num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
@@ -179,25 +126,239 @@ void r420_pipes_init(struct radeon_device *rdev)
179 rdev->num_gb_pipes, rdev->num_z_pipes); 126 rdev->num_gb_pipes, rdev->num_z_pipes);
180} 127}
181 128
182void r420_gpu_init(struct radeon_device *rdev) 129u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
130{
131 u32 r;
132
133 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
134 r = RREG32(R_0001FC_MC_IND_DATA);
135 return r;
136}
137
138void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
139{
140 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
141 S_0001F8_MC_IND_WR_EN(1));
142 WREG32(R_0001FC_MC_IND_DATA, v);
143}
144
145static void r420_debugfs(struct radeon_device *rdev)
146{
147 if (r100_debugfs_rbbm_init(rdev)) {
148 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
149 }
150 if (r420_debugfs_pipes_info_init(rdev)) {
151 DRM_ERROR("Failed to register debugfs file for pipes !\n");
152 }
153}
154
155static void r420_clock_resume(struct radeon_device *rdev)
156{
157 u32 sclk_cntl;
158 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
159 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
160 if (rdev->family == CHIP_R420)
161 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
162 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
163}
164
165static int r420_startup(struct radeon_device *rdev)
183{ 166{
184 r100_hdp_reset(rdev); 167 int r;
168
169 r300_mc_program(rdev);
170 /* Initialize GART (initialize after TTM so we can allocate
171 * memory through TTM but finalize after TTM) */
172 if (rdev->flags & RADEON_IS_PCIE) {
173 r = rv370_pcie_gart_enable(rdev);
174 if (r)
175 return r;
176 }
177 if (rdev->flags & RADEON_IS_PCI) {
178 r = r100_pci_gart_enable(rdev);
179 if (r)
180 return r;
181 }
185 r420_pipes_init(rdev); 182 r420_pipes_init(rdev);
186 if (r300_mc_wait_for_idle(rdev)) { 183 /* Enable IRQ */
187 printk(KERN_WARNING "Failed to wait MC idle while " 184 rdev->irq.sw_int = true;
188 "programming pipes. Bad things might happen.\n"); 185 r100_irq_set(rdev);
186 /* 1M ring buffer */
187 r = r100_cp_init(rdev, 1024 * 1024);
188 if (r) {
189 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
190 return r;
191 }
192 r = r100_wb_init(rdev);
193 if (r) {
194 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
195 }
196 r = r100_ib_init(rdev);
197 if (r) {
198 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
199 return r;
189 } 200 }
201 return 0;
190} 202}
191 203
204int r420_resume(struct radeon_device *rdev)
205{
206 /* Make sur GART are not working */
207 if (rdev->flags & RADEON_IS_PCIE)
208 rv370_pcie_gart_disable(rdev);
209 if (rdev->flags & RADEON_IS_PCI)
210 r100_pci_gart_disable(rdev);
211 /* Resume clock before doing reset */
212 r420_clock_resume(rdev);
213 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
214 if (radeon_gpu_reset(rdev)) {
215 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
216 RREG32(R_000E40_RBBM_STATUS),
217 RREG32(R_0007C0_CP_STAT));
218 }
219 /* check if cards are posted or not */
220 if (rdev->is_atom_bios) {
221 atom_asic_init(rdev->mode_info.atom_context);
222 } else {
223 radeon_combios_asic_init(rdev->ddev);
224 }
225 /* Resume clock after posting */
226 r420_clock_resume(rdev);
192 227
193/* 228 return r420_startup(rdev);
194 * r420,r423,rv410 VRAM info 229}
195 */ 230
196void r420_vram_info(struct radeon_device *rdev) 231int r420_suspend(struct radeon_device *rdev)
197{ 232{
198 r300_vram_info(rdev); 233 r100_cp_disable(rdev);
234 r100_wb_disable(rdev);
235 r100_irq_disable(rdev);
236 if (rdev->flags & RADEON_IS_PCIE)
237 rv370_pcie_gart_disable(rdev);
238 if (rdev->flags & RADEON_IS_PCI)
239 r100_pci_gart_disable(rdev);
240 return 0;
241}
242
243void r420_fini(struct radeon_device *rdev)
244{
245 r100_cp_fini(rdev);
246 r100_wb_fini(rdev);
247 r100_ib_fini(rdev);
248 radeon_gem_fini(rdev);
249 if (rdev->flags & RADEON_IS_PCIE)
250 rv370_pcie_gart_fini(rdev);
251 if (rdev->flags & RADEON_IS_PCI)
252 r100_pci_gart_fini(rdev);
253 radeon_agp_fini(rdev);
254 radeon_irq_kms_fini(rdev);
255 radeon_fence_driver_fini(rdev);
256 radeon_object_fini(rdev);
257 if (rdev->is_atom_bios) {
258 radeon_atombios_fini(rdev);
259 } else {
260 radeon_combios_fini(rdev);
261 }
262 kfree(rdev->bios);
263 rdev->bios = NULL;
199} 264}
200 265
266int r420_init(struct radeon_device *rdev)
267{
268 int r;
269
270 rdev->new_init_path = true;
271 /* Initialize scratch registers */
272 radeon_scratch_init(rdev);
273 /* Initialize surface registers */
274 radeon_surface_init(rdev);
275 /* TODO: disable VGA need to use VGA request */
276 /* BIOS*/
277 if (!radeon_get_bios(rdev)) {
278 if (ASIC_IS_AVIVO(rdev))
279 return -EINVAL;
280 }
281 if (rdev->is_atom_bios) {
282 r = radeon_atombios_init(rdev);
283 if (r) {
284 return r;
285 }
286 } else {
287 r = radeon_combios_init(rdev);
288 if (r) {
289 return r;
290 }
291 }
292 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
293 if (radeon_gpu_reset(rdev)) {
294 dev_warn(rdev->dev,
295 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
296 RREG32(R_000E40_RBBM_STATUS),
297 RREG32(R_0007C0_CP_STAT));
298 }
299 /* check if cards are posted or not */
300 if (!radeon_card_posted(rdev) && rdev->bios) {
301 DRM_INFO("GPU not posted. posting now...\n");
302 if (rdev->is_atom_bios) {
303 atom_asic_init(rdev->mode_info.atom_context);
304 } else {
305 radeon_combios_asic_init(rdev->ddev);
306 }
307 }
308 /* Initialize clocks */
309 radeon_get_clock_info(rdev->ddev);
310 /* Get vram informations */
311 r300_vram_info(rdev);
312 /* Initialize memory controller (also test AGP) */
313 r = r420_mc_init(rdev);
314 if (r) {
315 return r;
316 }
317 r420_debugfs(rdev);
318 /* Fence driver */
319 r = radeon_fence_driver_init(rdev);
320 if (r) {
321 return r;
322 }
323 r = radeon_irq_kms_init(rdev);
324 if (r) {
325 return r;
326 }
327 /* Memory manager */
328 r = radeon_object_init(rdev);
329 if (r) {
330 return r;
331 }
332 if (rdev->flags & RADEON_IS_PCIE) {
333 r = rv370_pcie_gart_init(rdev);
334 if (r)
335 return r;
336 }
337 if (rdev->flags & RADEON_IS_PCI) {
338 r = r100_pci_gart_init(rdev);
339 if (r)
340 return r;
341 }
342 r300_set_reg_safe(rdev);
343 rdev->accel_working = true;
344 r = r420_startup(rdev);
345 if (r) {
346 /* Somethings want wront with the accel init stop accel */
347 dev_err(rdev->dev, "Disabling GPU acceleration\n");
348 r420_suspend(rdev);
349 r100_cp_fini(rdev);
350 r100_wb_fini(rdev);
351 r100_ib_fini(rdev);
352 if (rdev->flags & RADEON_IS_PCIE)
353 rv370_pcie_gart_fini(rdev);
354 if (rdev->flags & RADEON_IS_PCI)
355 r100_pci_gart_fini(rdev);
356 radeon_agp_fini(rdev);
357 radeon_irq_kms_fini(rdev);
358 rdev->accel_working = false;
359 }
360 return 0;
361}
201 362
202/* 363/*
203 * Debugfs info 364 * Debugfs info
diff --git a/drivers/gpu/drm/radeon/r420d.h b/drivers/gpu/drm/radeon/r420d.h
new file mode 100644
index 000000000000..a48a7db1e2aa
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r420d.h
@@ -0,0 +1,249 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef R420D_H
29#define R420D_H
30
31#define R_0001F8_MC_IND_INDEX 0x0001F8
32#define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0)
33#define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F)
34#define C_0001F8_MC_IND_ADDR 0xFFFFFF80
35#define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8)
36#define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1)
37#define C_0001F8_MC_IND_WR_EN 0xFFFFFEFF
38#define R_0001FC_MC_IND_DATA 0x0001FC
39#define S_0001FC_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0)
40#define G_0001FC_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF)
41#define C_0001FC_MC_IND_DATA 0x00000000
42#define R_0007C0_CP_STAT 0x0007C0
43#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
44#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
45#define C_0007C0_MRU_BUSY 0xFFFFFFFE
46#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
47#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
48#define C_0007C0_MWU_BUSY 0xFFFFFFFD
49#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
50#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
51#define C_0007C0_RSIU_BUSY 0xFFFFFFFB
52#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
53#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
54#define C_0007C0_RCIU_BUSY 0xFFFFFFF7
55#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
56#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
57#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF
58#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)
59#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)
60#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF
61#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)
62#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)
63#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF
64#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)
65#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)
66#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF
67#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)
68#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)
69#define C_0007C0_CSI_BUSY 0xFFFFDFFF
70#define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14)
71#define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1)
72#define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF
73#define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15)
74#define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1)
75#define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF
76#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)
77#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)
78#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF
79#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)
80#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)
81#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF
82#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)
83#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)
84#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF
85#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)
86#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)
87#define C_0007C0_CP_BUSY 0x7FFFFFFF
88#define R_000E40_RBBM_STATUS 0x000E40
89#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
90#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
91#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80
92#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)
93#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)
94#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF
95#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)
96#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)
97#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF
98#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)
99#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)
100#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF
101#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)
102#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)
103#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF
104#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)
105#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)
106#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF
107#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)
108#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)
109#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF
110#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)
111#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)
112#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF
113#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)
114#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)
115#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF
116#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)
117#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)
118#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF
119#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)
120#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)
121#define C_000E40_E2_BUSY 0xFFFDFFFF
122#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)
123#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)
124#define C_000E40_RB2D_BUSY 0xFFFBFFFF
125#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)
126#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)
127#define C_000E40_RB3D_BUSY 0xFFF7FFFF
128#define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20)
129#define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1)
130#define C_000E40_VAP_BUSY 0xFFEFFFFF
131#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)
132#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)
133#define C_000E40_RE_BUSY 0xFFDFFFFF
134#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)
135#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)
136#define C_000E40_TAM_BUSY 0xFFBFFFFF
137#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)
138#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)
139#define C_000E40_TDM_BUSY 0xFF7FFFFF
140#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)
141#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)
142#define C_000E40_PB_BUSY 0xFEFFFFFF
143#define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25)
144#define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1)
145#define C_000E40_TIM_BUSY 0xFDFFFFFF
146#define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26)
147#define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1)
148#define C_000E40_GA_BUSY 0xFBFFFFFF
149#define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27)
150#define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1)
151#define C_000E40_CBA2D_BUSY 0xF7FFFFFF
152#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)
153#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
154#define C_000E40_GUI_ACTIVE 0x7FFFFFFF
155
156/* CLK registers */
157#define R_00000D_SCLK_CNTL 0x00000D
158#define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0)
159#define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7)
160#define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8
161#define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3)
162#define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1)
163#define C_00000D_CP_MAX_DYN_STOP_LAT 0xFFFFFFF7
164#define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4)
165#define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1)
166#define C_00000D_HDP_MAX_DYN_STOP_LAT 0xFFFFFFEF
167#define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5)
168#define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1)
169#define C_00000D_TV_MAX_DYN_STOP_LAT 0xFFFFFFDF
170#define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6)
171#define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1)
172#define C_00000D_E2_MAX_DYN_STOP_LAT 0xFFFFFFBF
173#define S_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 7)
174#define G_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) >> 7) & 0x1)
175#define C_00000D_SE_MAX_DYN_STOP_LAT 0xFFFFFF7F
176#define S_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 8)
177#define G_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 8) & 0x1)
178#define C_00000D_IDCT_MAX_DYN_STOP_LAT 0xFFFFFEFF
179#define S_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 9)
180#define G_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) >> 9) & 0x1)
181#define C_00000D_VIP_MAX_DYN_STOP_LAT 0xFFFFFDFF
182#define S_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 10)
183#define G_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) >> 10) & 0x1)
184#define C_00000D_RE_MAX_DYN_STOP_LAT 0xFFFFFBFF
185#define S_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 11)
186#define G_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) >> 11) & 0x1)
187#define C_00000D_PB_MAX_DYN_STOP_LAT 0xFFFFF7FF
188#define S_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 12)
189#define G_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) >> 12) & 0x1)
190#define C_00000D_TAM_MAX_DYN_STOP_LAT 0xFFFFEFFF
191#define S_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 13)
192#define G_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) >> 13) & 0x1)
193#define C_00000D_TDM_MAX_DYN_STOP_LAT 0xFFFFDFFF
194#define S_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 14)
195#define G_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) >> 14) & 0x1)
196#define C_00000D_RB_MAX_DYN_STOP_LAT 0xFFFFBFFF
197#define S_00000D_FORCE_DISP2(x) (((x) & 0x1) << 15)
198#define G_00000D_FORCE_DISP2(x) (((x) >> 15) & 0x1)
199#define C_00000D_FORCE_DISP2 0xFFFF7FFF
200#define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16)
201#define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1)
202#define C_00000D_FORCE_CP 0xFFFEFFFF
203#define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17)
204#define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1)
205#define C_00000D_FORCE_HDP 0xFFFDFFFF
206#define S_00000D_FORCE_DISP1(x) (((x) & 0x1) << 18)
207#define G_00000D_FORCE_DISP1(x) (((x) >> 18) & 0x1)
208#define C_00000D_FORCE_DISP1 0xFFFBFFFF
209#define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19)
210#define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1)
211#define C_00000D_FORCE_TOP 0xFFF7FFFF
212#define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20)
213#define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1)
214#define C_00000D_FORCE_E2 0xFFEFFFFF
215#define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21)
216#define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1)
217#define C_00000D_FORCE_SE 0xFFDFFFFF
218#define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22)
219#define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1)
220#define C_00000D_FORCE_IDCT 0xFFBFFFFF
221#define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23)
222#define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1)
223#define C_00000D_FORCE_VIP 0xFF7FFFFF
224#define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24)
225#define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1)
226#define C_00000D_FORCE_RE 0xFEFFFFFF
227#define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25)
228#define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1)
229#define C_00000D_FORCE_PB 0xFDFFFFFF
230#define S_00000D_FORCE_PX(x) (((x) & 0x1) << 26)
231#define G_00000D_FORCE_PX(x) (((x) >> 26) & 0x1)
232#define C_00000D_FORCE_PX 0xFBFFFFFF
233#define S_00000D_FORCE_TX(x) (((x) & 0x1) << 27)
234#define G_00000D_FORCE_TX(x) (((x) >> 27) & 0x1)
235#define C_00000D_FORCE_TX 0xF7FFFFFF
236#define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28)
237#define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1)
238#define C_00000D_FORCE_RB 0xEFFFFFFF
239#define S_00000D_FORCE_TV_SCLK(x) (((x) & 0x1) << 29)
240#define G_00000D_FORCE_TV_SCLK(x) (((x) >> 29) & 0x1)
241#define C_00000D_FORCE_TV_SCLK 0xDFFFFFFF
242#define S_00000D_FORCE_SUBPIC(x) (((x) & 0x1) << 30)
243#define G_00000D_FORCE_SUBPIC(x) (((x) >> 30) & 0x1)
244#define C_00000D_FORCE_SUBPIC 0xBFFFFFFF
245#define S_00000D_FORCE_OV0(x) (((x) & 0x1) << 31)
246#define G_00000D_FORCE_OV0(x) (((x) >> 31) & 0x1)
247#define C_00000D_FORCE_OV0 0x7FFFFFFF
248
249#endif
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index ebd6b0f7bdff..d4b0b9d2e39b 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -28,12 +28,9 @@
28#include "drmP.h" 28#include "drmP.h"
29#include "radeon_reg.h" 29#include "radeon_reg.h"
30#include "radeon.h" 30#include "radeon.h"
31#include "radeon_share.h"
32 31
33/* r520,rv530,rv560,rv570,r580 depends on : */ 32/* r520,rv530,rv560,rv570,r580 depends on : */
34void r100_hdp_reset(struct radeon_device *rdev); 33void r100_hdp_reset(struct radeon_device *rdev);
35int rv370_pcie_gart_enable(struct radeon_device *rdev);
36void rv370_pcie_gart_disable(struct radeon_device *rdev);
37void r420_pipes_init(struct radeon_device *rdev); 34void r420_pipes_init(struct radeon_device *rdev);
38void rs600_mc_disable_clients(struct radeon_device *rdev); 35void rs600_mc_disable_clients(struct radeon_device *rdev);
39void rs600_disable_vga(struct radeon_device *rdev); 36void rs600_disable_vga(struct radeon_device *rdev);
@@ -119,9 +116,6 @@ int r520_mc_init(struct radeon_device *rdev)
119 116
120void r520_mc_fini(struct radeon_device *rdev) 117void r520_mc_fini(struct radeon_device *rdev)
121{ 118{
122 rv370_pcie_gart_disable(rdev);
123 radeon_gart_table_vram_free(rdev);
124 radeon_gart_fini(rdev);
125} 119}
126 120
127 121
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 538cd907df69..eab31c1d6df1 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -25,12 +25,45 @@
25 * Alex Deucher 25 * Alex Deucher
26 * Jerome Glisse 26 * Jerome Glisse
27 */ 27 */
28#include <linux/seq_file.h>
29#include <linux/firmware.h>
30#include <linux/platform_device.h>
28#include "drmP.h" 31#include "drmP.h"
29#include "radeon_reg.h" 32#include "radeon_drm.h"
30#include "radeon.h" 33#include "radeon.h"
34#include "radeon_mode.h"
35#include "r600d.h"
36#include "avivod.h"
37#include "atom.h"
31 38
32/* r600,rv610,rv630,rv620,rv635,rv670 depends on : */ 39#define PFP_UCODE_SIZE 576
33void rs600_mc_disable_clients(struct radeon_device *rdev); 40#define PM4_UCODE_SIZE 1792
41#define R700_PFP_UCODE_SIZE 848
42#define R700_PM4_UCODE_SIZE 1360
43
44/* Firmware Names */
45MODULE_FIRMWARE("radeon/R600_pfp.bin");
46MODULE_FIRMWARE("radeon/R600_me.bin");
47MODULE_FIRMWARE("radeon/RV610_pfp.bin");
48MODULE_FIRMWARE("radeon/RV610_me.bin");
49MODULE_FIRMWARE("radeon/RV630_pfp.bin");
50MODULE_FIRMWARE("radeon/RV630_me.bin");
51MODULE_FIRMWARE("radeon/RV620_pfp.bin");
52MODULE_FIRMWARE("radeon/RV620_me.bin");
53MODULE_FIRMWARE("radeon/RV635_pfp.bin");
54MODULE_FIRMWARE("radeon/RV635_me.bin");
55MODULE_FIRMWARE("radeon/RV670_pfp.bin");
56MODULE_FIRMWARE("radeon/RV670_me.bin");
57MODULE_FIRMWARE("radeon/RS780_pfp.bin");
58MODULE_FIRMWARE("radeon/RS780_me.bin");
59MODULE_FIRMWARE("radeon/RV770_pfp.bin");
60MODULE_FIRMWARE("radeon/RV770_me.bin");
61MODULE_FIRMWARE("radeon/RV730_pfp.bin");
62MODULE_FIRMWARE("radeon/RV730_me.bin");
63MODULE_FIRMWARE("radeon/RV710_pfp.bin");
64MODULE_FIRMWARE("radeon/RV710_me.bin");
65
66int r600_debugfs_mc_info_init(struct radeon_device *rdev);
34 67
35/* This files gather functions specifics to: 68/* This files gather functions specifics to:
36 * r600,rv610,rv630,rv620,rv635,rv670 69 * r600,rv610,rv630,rv620,rv635,rv670
@@ -39,87 +72,293 @@ void rs600_mc_disable_clients(struct radeon_device *rdev);
39 */ 72 */
40int r600_mc_wait_for_idle(struct radeon_device *rdev); 73int r600_mc_wait_for_idle(struct radeon_device *rdev);
41void r600_gpu_init(struct radeon_device *rdev); 74void r600_gpu_init(struct radeon_device *rdev);
75void r600_fini(struct radeon_device *rdev);
42 76
43 77
44/* 78/*
45 * MC 79 * R600 PCIE GART
46 */ 80 */
47int r600_mc_init(struct radeon_device *rdev) 81int r600_gart_clear_page(struct radeon_device *rdev, int i)
48{ 82{
49 uint32_t tmp; 83 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
84 u64 pte;
50 85
51 r600_gpu_init(rdev); 86 if (i < 0 || i > rdev->gart.num_gpu_pages)
87 return -EINVAL;
88 pte = 0;
89 writeq(pte, ((void __iomem *)ptr) + (i * 8));
90 return 0;
91}
52 92
53 /* setup the gart before changing location so we can ask to 93void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
54 * discard unmapped mc request 94{
55 */ 95 unsigned i;
56 /* FIXME: disable out of gart access */ 96 u32 tmp;
57 tmp = rdev->mc.gtt_location / 4096; 97
58 tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp); 98 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
59 WREG32(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp); 99 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
60 tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096; 100 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
61 tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp); 101 for (i = 0; i < rdev->usec_timeout; i++) {
62 WREG32(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp); 102 /* read MC_STATUS */
63 103 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
64 rs600_mc_disable_clients(rdev); 104 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
65 if (r600_mc_wait_for_idle(rdev)) { 105 if (tmp == 2) {
66 printk(KERN_WARNING "Failed to wait MC idle while " 106 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
67 "programming pipes. Bad things might happen.\n"); 107 return;
108 }
109 if (tmp) {
110 return;
111 }
112 udelay(1);
68 } 113 }
114}
69 115
70 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; 116int r600_pcie_gart_init(struct radeon_device *rdev)
71 tmp = REG_SET(R600_MC_FB_TOP, tmp >> 24); 117{
72 tmp |= REG_SET(R600_MC_FB_BASE, rdev->mc.vram_location >> 24); 118 int r;
73 WREG32(R600_MC_VM_FB_LOCATION, tmp); 119
74 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; 120 if (rdev->gart.table.vram.robj) {
75 tmp = REG_SET(R600_MC_AGP_TOP, tmp >> 22); 121 WARN(1, "R600 PCIE GART already initialized.\n");
76 WREG32(R600_MC_VM_AGP_TOP, tmp); 122 return 0;
77 tmp = REG_SET(R600_MC_AGP_BOT, rdev->mc.gtt_location >> 22); 123 }
78 WREG32(R600_MC_VM_AGP_BOT, tmp); 124 /* Initialize common gart structure */
79 return 0; 125 r = radeon_gart_init(rdev);
126 if (r)
127 return r;
128 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
129 return radeon_gart_table_vram_alloc(rdev);
80} 130}
81 131
82void r600_mc_fini(struct radeon_device *rdev) 132int r600_pcie_gart_enable(struct radeon_device *rdev)
83{ 133{
84 /* FIXME: implement */ 134 u32 tmp;
135 int r, i;
136
137 if (rdev->gart.table.vram.robj == NULL) {
138 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
139 return -EINVAL;
140 }
141 r = radeon_gart_table_vram_pin(rdev);
142 if (r)
143 return r;
144
145 /* Setup L2 cache */
146 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
147 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
148 EFFECTIVE_L2_QUEUE_SIZE(7));
149 WREG32(VM_L2_CNTL2, 0);
150 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
151 /* Setup TLB control */
152 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
153 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
154 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
155 ENABLE_WAIT_L2_QUERY;
156 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
157 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
158 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
159 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
160 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
161 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
162 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
163 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
164 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
165 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
166 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
167 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
168 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
169 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
170 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
171 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
172 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
173 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
174 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
175 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
176 (u32)(rdev->dummy_page.addr >> 12));
177 for (i = 1; i < 7; i++)
178 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
179
180 r600_pcie_gart_tlb_flush(rdev);
181 rdev->gart.ready = true;
182 return 0;
85} 183}
86 184
185void r600_pcie_gart_disable(struct radeon_device *rdev)
186{
187 u32 tmp;
188 int i;
87 189
88/* 190 /* Disable all tables */
89 * Global GPU functions 191 for (i = 0; i < 7; i++)
90 */ 192 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
91void r600_errata(struct radeon_device *rdev) 193
194 /* Disable L2 cache */
195 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
196 EFFECTIVE_L2_QUEUE_SIZE(7));
197 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
198 /* Setup L1 TLB control */
199 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
200 ENABLE_WAIT_L2_QUERY;
201 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
202 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
203 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
204 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
205 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
206 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
207 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
208 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
209 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
210 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
211 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
212 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
213 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
214 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
215 if (rdev->gart.table.vram.robj) {
216 radeon_object_kunmap(rdev->gart.table.vram.robj);
217 radeon_object_unpin(rdev->gart.table.vram.robj);
218 }
219}
220
221void r600_pcie_gart_fini(struct radeon_device *rdev)
92{ 222{
93 rdev->pll_errata = 0; 223 r600_pcie_gart_disable(rdev);
224 radeon_gart_table_vram_free(rdev);
225 radeon_gart_fini(rdev);
94} 226}
95 227
96int r600_mc_wait_for_idle(struct radeon_device *rdev) 228int r600_mc_wait_for_idle(struct radeon_device *rdev)
97{ 229{
98 /* FIXME: implement */ 230 unsigned i;
99 return 0; 231 u32 tmp;
232
233 for (i = 0; i < rdev->usec_timeout; i++) {
234 /* read MC_STATUS */
235 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
236 if (!tmp)
237 return 0;
238 udelay(1);
239 }
240 return -1;
100} 241}
101 242
102void r600_gpu_init(struct radeon_device *rdev) 243static void r600_mc_resume(struct radeon_device *rdev)
103{ 244{
104 /* FIXME: implement */ 245 u32 d1vga_control, d2vga_control;
105} 246 u32 vga_render_control, vga_hdp_control;
247 u32 d1crtc_control, d2crtc_control;
248 u32 new_d1grph_primary, new_d1grph_secondary;
249 u32 new_d2grph_primary, new_d2grph_secondary;
250 u64 old_vram_start;
251 u32 tmp;
252 int i, j;
106 253
254 /* Initialize HDP */
255 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
256 WREG32((0x2c14 + j), 0x00000000);
257 WREG32((0x2c18 + j), 0x00000000);
258 WREG32((0x2c1c + j), 0x00000000);
259 WREG32((0x2c20 + j), 0x00000000);
260 WREG32((0x2c24 + j), 0x00000000);
261 }
262 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
107 263
108/* 264 d1vga_control = RREG32(D1VGA_CONTROL);
109 * VRAM info 265 d2vga_control = RREG32(D2VGA_CONTROL);
110 */ 266 vga_render_control = RREG32(VGA_RENDER_CONTROL);
111void r600_vram_get_type(struct radeon_device *rdev) 267 vga_hdp_control = RREG32(VGA_HDP_CONTROL);
268 d1crtc_control = RREG32(D1CRTC_CONTROL);
269 d2crtc_control = RREG32(D2CRTC_CONTROL);
270 old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
271 new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
272 new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
273 new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
274 new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
275 new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
276 new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
277 new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
278 new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
279
280 /* Stop all video */
281 WREG32(D1VGA_CONTROL, 0);
282 WREG32(D2VGA_CONTROL, 0);
283 WREG32(VGA_RENDER_CONTROL, 0);
284 WREG32(D1CRTC_UPDATE_LOCK, 1);
285 WREG32(D2CRTC_UPDATE_LOCK, 1);
286 WREG32(D1CRTC_CONTROL, 0);
287 WREG32(D2CRTC_CONTROL, 0);
288 WREG32(D1CRTC_UPDATE_LOCK, 0);
289 WREG32(D2CRTC_UPDATE_LOCK, 0);
290
291 mdelay(1);
292 if (r600_mc_wait_for_idle(rdev)) {
293 printk(KERN_WARNING "[drm] MC not idle !\n");
294 }
295
296 /* Lockout access through VGA aperture*/
297 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
298
299 /* Update configuration */
300 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
301 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
302 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
303 tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
304 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
305 WREG32(MC_VM_FB_LOCATION, tmp);
306 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
307 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
308 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
309 if (rdev->flags & RADEON_IS_AGP) {
310 WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
311 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
312 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
313 } else {
314 WREG32(MC_VM_AGP_BASE, 0);
315 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
316 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
317 }
318 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
319 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
320 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
321 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
322 WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
323
324 /* Unlock host access */
325 WREG32(VGA_HDP_CONTROL, vga_hdp_control);
326
327 mdelay(1);
328 if (r600_mc_wait_for_idle(rdev)) {
329 printk(KERN_WARNING "[drm] MC not idle !\n");
330 }
331
332 /* Restore video state */
333 WREG32(D1CRTC_UPDATE_LOCK, 1);
334 WREG32(D2CRTC_UPDATE_LOCK, 1);
335 WREG32(D1CRTC_CONTROL, d1crtc_control);
336 WREG32(D2CRTC_CONTROL, d2crtc_control);
337 WREG32(D1CRTC_UPDATE_LOCK, 0);
338 WREG32(D2CRTC_UPDATE_LOCK, 0);
339 WREG32(D1VGA_CONTROL, d1vga_control);
340 WREG32(D2VGA_CONTROL, d2vga_control);
341 WREG32(VGA_RENDER_CONTROL, vga_render_control);
342
343 /* we need to own VRAM, so turn off the VGA renderer here
344 * to stop it overwriting our objects */
345 radeon_avivo_vga_render_disable(rdev);
346}
347
348int r600_mc_init(struct radeon_device *rdev)
112{ 349{
113 uint32_t tmp; 350 fixed20_12 a;
351 u32 tmp;
114 int chansize; 352 int chansize;
353 int r;
115 354
355 /* Get VRAM informations */
116 rdev->mc.vram_width = 128; 356 rdev->mc.vram_width = 128;
117 rdev->mc.vram_is_ddr = true; 357 rdev->mc.vram_is_ddr = true;
118 358 tmp = RREG32(RAMCFG);
119 tmp = RREG32(R600_RAMCFG); 359 if (tmp & CHANSIZE_OVERRIDE) {
120 if (tmp & R600_CHANSIZE_OVERRIDE) {
121 chansize = 16; 360 chansize = 16;
122 } else if (tmp & R600_CHANSIZE) { 361 } else if (tmp & CHANSIZE_MASK) {
123 chansize = 64; 362 chansize = 64;
124 } else { 363 } else {
125 chansize = 32; 364 chansize = 32;
@@ -135,36 +374,1459 @@ void r600_vram_get_type(struct radeon_device *rdev)
135 (rdev->family == CHIP_RV635)) { 374 (rdev->family == CHIP_RV635)) {
136 rdev->mc.vram_width = 2 * chansize; 375 rdev->mc.vram_width = 2 * chansize;
137 } 376 }
377 /* Could aper size report 0 ? */
378 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
379 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
380 /* Setup GPU memory space */
381 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
382 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
383 if (rdev->flags & RADEON_IS_AGP) {
384 r = radeon_agp_init(rdev);
385 if (r)
386 return r;
387 /* gtt_size is setup by radeon_agp_init */
388 rdev->mc.gtt_location = rdev->mc.agp_base;
389 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
390 /* Try to put vram before or after AGP because we
391 * we want SYSTEM_APERTURE to cover both VRAM and
392 * AGP so that GPU can catch out of VRAM/AGP access
393 */
394 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
395 /* Enought place before */
396 rdev->mc.vram_location = rdev->mc.gtt_location -
397 rdev->mc.mc_vram_size;
398 } else if (tmp > rdev->mc.mc_vram_size) {
399 /* Enought place after */
400 rdev->mc.vram_location = rdev->mc.gtt_location +
401 rdev->mc.gtt_size;
402 } else {
403 /* Try to setup VRAM then AGP might not
404 * not work on some card
405 */
406 rdev->mc.vram_location = 0x00000000UL;
407 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
408 }
409 } else {
410 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
411 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
412 0xFFFF) << 24;
413 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
414 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
415 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
416 /* Enough place after vram */
417 rdev->mc.gtt_location = tmp;
418 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
419 /* Enough place before vram */
420 rdev->mc.gtt_location = 0;
421 } else {
422 /* Not enough place after or before shrink
423 * gart size
424 */
425 if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
426 rdev->mc.gtt_location = 0;
427 rdev->mc.gtt_size = rdev->mc.vram_location;
428 } else {
429 rdev->mc.gtt_location = tmp;
430 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
431 }
432 }
433 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
434 } else {
435 rdev->mc.vram_location = 0x00000000UL;
436 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
437 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
438 }
439 }
440 rdev->mc.vram_start = rdev->mc.vram_location;
441 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
442 rdev->mc.gtt_start = rdev->mc.gtt_location;
443 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
444 /* FIXME: we should enforce default clock in case GPU is not in
445 * default setup
446 */
447 a.full = rfixed_const(100);
448 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
449 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
450 return 0;
138} 451}
139 452
140void r600_vram_info(struct radeon_device *rdev) 453/* We doesn't check that the GPU really needs a reset we simply do the
454 * reset, it's up to the caller to determine if the GPU needs one. We
455 * might add an helper function to check that.
456 */
457int r600_gpu_soft_reset(struct radeon_device *rdev)
141{ 458{
142 r600_vram_get_type(rdev); 459 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
143 rdev->mc.real_vram_size = RREG32(R600_CONFIG_MEMSIZE); 460 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
144 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 461 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
462 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
463 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
464 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
465 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
466 S_008010_GUI_ACTIVE(1);
467 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
468 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
469 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
470 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
471 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
472 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
473 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
474 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
475 u32 srbm_reset = 0;
145 476
146 /* Could aper size report 0 ? */ 477 /* Disable CP parsing/prefetching */
147 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 478 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
148 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 479 /* Check if any of the rendering block is busy and reset it */
480 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
481 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
482 WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CR(1) |
483 S_008020_SOFT_RESET_DB(1) |
484 S_008020_SOFT_RESET_CB(1) |
485 S_008020_SOFT_RESET_PA(1) |
486 S_008020_SOFT_RESET_SC(1) |
487 S_008020_SOFT_RESET_SMX(1) |
488 S_008020_SOFT_RESET_SPI(1) |
489 S_008020_SOFT_RESET_SX(1) |
490 S_008020_SOFT_RESET_SH(1) |
491 S_008020_SOFT_RESET_TC(1) |
492 S_008020_SOFT_RESET_TA(1) |
493 S_008020_SOFT_RESET_VC(1) |
494 S_008020_SOFT_RESET_VGT(1));
495 (void)RREG32(R_008020_GRBM_SOFT_RESET);
496 udelay(50);
497 WREG32(R_008020_GRBM_SOFT_RESET, 0);
498 (void)RREG32(R_008020_GRBM_SOFT_RESET);
499 }
500 /* Reset CP (we always reset CP) */
501 WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CP(1));
502 (void)RREG32(R_008020_GRBM_SOFT_RESET);
503 udelay(50);
504 WREG32(R_008020_GRBM_SOFT_RESET, 0);
505 (void)RREG32(R_008020_GRBM_SOFT_RESET);
506 /* Reset others GPU block if necessary */
507 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
508 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
509 if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
510 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
511 if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
512 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
513 if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
514 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
515 if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
516 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
517 if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
518 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
519 if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
520 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
521 if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
522 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
523 if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
524 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
525 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
526 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
527 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
528 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
529 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
530 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
531 udelay(50);
532 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
533 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
534 /* Wait a little for things to settle down */
535 udelay(50);
536 return 0;
149} 537}
150 538
539int r600_gpu_reset(struct radeon_device *rdev)
540{
541 return r600_gpu_soft_reset(rdev);
542}
543
544static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
545 u32 num_backends,
546 u32 backend_disable_mask)
547{
548 u32 backend_map = 0;
549 u32 enabled_backends_mask;
550 u32 enabled_backends_count;
551 u32 cur_pipe;
552 u32 swizzle_pipe[R6XX_MAX_PIPES];
553 u32 cur_backend;
554 u32 i;
555
556 if (num_tile_pipes > R6XX_MAX_PIPES)
557 num_tile_pipes = R6XX_MAX_PIPES;
558 if (num_tile_pipes < 1)
559 num_tile_pipes = 1;
560 if (num_backends > R6XX_MAX_BACKENDS)
561 num_backends = R6XX_MAX_BACKENDS;
562 if (num_backends < 1)
563 num_backends = 1;
564
565 enabled_backends_mask = 0;
566 enabled_backends_count = 0;
567 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
568 if (((backend_disable_mask >> i) & 1) == 0) {
569 enabled_backends_mask |= (1 << i);
570 ++enabled_backends_count;
571 }
572 if (enabled_backends_count == num_backends)
573 break;
574 }
575
576 if (enabled_backends_count == 0) {
577 enabled_backends_mask = 1;
578 enabled_backends_count = 1;
579 }
580
581 if (enabled_backends_count != num_backends)
582 num_backends = enabled_backends_count;
583
584 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
585 switch (num_tile_pipes) {
586 case 1:
587 swizzle_pipe[0] = 0;
588 break;
589 case 2:
590 swizzle_pipe[0] = 0;
591 swizzle_pipe[1] = 1;
592 break;
593 case 3:
594 swizzle_pipe[0] = 0;
595 swizzle_pipe[1] = 1;
596 swizzle_pipe[2] = 2;
597 break;
598 case 4:
599 swizzle_pipe[0] = 0;
600 swizzle_pipe[1] = 1;
601 swizzle_pipe[2] = 2;
602 swizzle_pipe[3] = 3;
603 break;
604 case 5:
605 swizzle_pipe[0] = 0;
606 swizzle_pipe[1] = 1;
607 swizzle_pipe[2] = 2;
608 swizzle_pipe[3] = 3;
609 swizzle_pipe[4] = 4;
610 break;
611 case 6:
612 swizzle_pipe[0] = 0;
613 swizzle_pipe[1] = 2;
614 swizzle_pipe[2] = 4;
615 swizzle_pipe[3] = 5;
616 swizzle_pipe[4] = 1;
617 swizzle_pipe[5] = 3;
618 break;
619 case 7:
620 swizzle_pipe[0] = 0;
621 swizzle_pipe[1] = 2;
622 swizzle_pipe[2] = 4;
623 swizzle_pipe[3] = 6;
624 swizzle_pipe[4] = 1;
625 swizzle_pipe[5] = 3;
626 swizzle_pipe[6] = 5;
627 break;
628 case 8:
629 swizzle_pipe[0] = 0;
630 swizzle_pipe[1] = 2;
631 swizzle_pipe[2] = 4;
632 swizzle_pipe[3] = 6;
633 swizzle_pipe[4] = 1;
634 swizzle_pipe[5] = 3;
635 swizzle_pipe[6] = 5;
636 swizzle_pipe[7] = 7;
637 break;
638 }
639
640 cur_backend = 0;
641 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
642 while (((1 << cur_backend) & enabled_backends_mask) == 0)
643 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
644
645 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
646
647 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
648 }
649
650 return backend_map;
651}
652
653int r600_count_pipe_bits(uint32_t val)
654{
655 int i, ret = 0;
656
657 for (i = 0; i < 32; i++) {
658 ret += val & 1;
659 val >>= 1;
660 }
661 return ret;
662}
663
664void r600_gpu_init(struct radeon_device *rdev)
665{
666 u32 tiling_config;
667 u32 ramcfg;
668 u32 tmp;
669 int i, j;
670 u32 sq_config;
671 u32 sq_gpr_resource_mgmt_1 = 0;
672 u32 sq_gpr_resource_mgmt_2 = 0;
673 u32 sq_thread_resource_mgmt = 0;
674 u32 sq_stack_resource_mgmt_1 = 0;
675 u32 sq_stack_resource_mgmt_2 = 0;
676
677 /* FIXME: implement */
678 switch (rdev->family) {
679 case CHIP_R600:
680 rdev->config.r600.max_pipes = 4;
681 rdev->config.r600.max_tile_pipes = 8;
682 rdev->config.r600.max_simds = 4;
683 rdev->config.r600.max_backends = 4;
684 rdev->config.r600.max_gprs = 256;
685 rdev->config.r600.max_threads = 192;
686 rdev->config.r600.max_stack_entries = 256;
687 rdev->config.r600.max_hw_contexts = 8;
688 rdev->config.r600.max_gs_threads = 16;
689 rdev->config.r600.sx_max_export_size = 128;
690 rdev->config.r600.sx_max_export_pos_size = 16;
691 rdev->config.r600.sx_max_export_smx_size = 128;
692 rdev->config.r600.sq_num_cf_insts = 2;
693 break;
694 case CHIP_RV630:
695 case CHIP_RV635:
696 rdev->config.r600.max_pipes = 2;
697 rdev->config.r600.max_tile_pipes = 2;
698 rdev->config.r600.max_simds = 3;
699 rdev->config.r600.max_backends = 1;
700 rdev->config.r600.max_gprs = 128;
701 rdev->config.r600.max_threads = 192;
702 rdev->config.r600.max_stack_entries = 128;
703 rdev->config.r600.max_hw_contexts = 8;
704 rdev->config.r600.max_gs_threads = 4;
705 rdev->config.r600.sx_max_export_size = 128;
706 rdev->config.r600.sx_max_export_pos_size = 16;
707 rdev->config.r600.sx_max_export_smx_size = 128;
708 rdev->config.r600.sq_num_cf_insts = 2;
709 break;
710 case CHIP_RV610:
711 case CHIP_RV620:
712 case CHIP_RS780:
713 case CHIP_RS880:
714 rdev->config.r600.max_pipes = 1;
715 rdev->config.r600.max_tile_pipes = 1;
716 rdev->config.r600.max_simds = 2;
717 rdev->config.r600.max_backends = 1;
718 rdev->config.r600.max_gprs = 128;
719 rdev->config.r600.max_threads = 192;
720 rdev->config.r600.max_stack_entries = 128;
721 rdev->config.r600.max_hw_contexts = 4;
722 rdev->config.r600.max_gs_threads = 4;
723 rdev->config.r600.sx_max_export_size = 128;
724 rdev->config.r600.sx_max_export_pos_size = 16;
725 rdev->config.r600.sx_max_export_smx_size = 128;
726 rdev->config.r600.sq_num_cf_insts = 1;
727 break;
728 case CHIP_RV670:
729 rdev->config.r600.max_pipes = 4;
730 rdev->config.r600.max_tile_pipes = 4;
731 rdev->config.r600.max_simds = 4;
732 rdev->config.r600.max_backends = 4;
733 rdev->config.r600.max_gprs = 192;
734 rdev->config.r600.max_threads = 192;
735 rdev->config.r600.max_stack_entries = 256;
736 rdev->config.r600.max_hw_contexts = 8;
737 rdev->config.r600.max_gs_threads = 16;
738 rdev->config.r600.sx_max_export_size = 128;
739 rdev->config.r600.sx_max_export_pos_size = 16;
740 rdev->config.r600.sx_max_export_smx_size = 128;
741 rdev->config.r600.sq_num_cf_insts = 2;
742 break;
743 default:
744 break;
745 }
746
747 /* Initialize HDP */
748 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
749 WREG32((0x2c14 + j), 0x00000000);
750 WREG32((0x2c18 + j), 0x00000000);
751 WREG32((0x2c1c + j), 0x00000000);
752 WREG32((0x2c20 + j), 0x00000000);
753 WREG32((0x2c24 + j), 0x00000000);
754 }
755
756 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
757
758 /* Setup tiling */
759 tiling_config = 0;
760 ramcfg = RREG32(RAMCFG);
761 switch (rdev->config.r600.max_tile_pipes) {
762 case 1:
763 tiling_config |= PIPE_TILING(0);
764 break;
765 case 2:
766 tiling_config |= PIPE_TILING(1);
767 break;
768 case 4:
769 tiling_config |= PIPE_TILING(2);
770 break;
771 case 8:
772 tiling_config |= PIPE_TILING(3);
773 break;
774 default:
775 break;
776 }
777 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
778 tiling_config |= GROUP_SIZE(0);
779 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
780 if (tmp > 3) {
781 tiling_config |= ROW_TILING(3);
782 tiling_config |= SAMPLE_SPLIT(3);
783 } else {
784 tiling_config |= ROW_TILING(tmp);
785 tiling_config |= SAMPLE_SPLIT(tmp);
786 }
787 tiling_config |= BANK_SWAPS(1);
788 tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
789 rdev->config.r600.max_backends,
790 (0xff << rdev->config.r600.max_backends) & 0xff);
791 tiling_config |= BACKEND_MAP(tmp);
792 WREG32(GB_TILING_CONFIG, tiling_config);
793 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
794 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
795
796 tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
797 WREG32(CC_RB_BACKEND_DISABLE, tmp);
798
799 /* Setup pipes */
800 tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
801 tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
802 WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
803 WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
804
805 tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
806 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
807 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
808
809 /* Setup some CP states */
810 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
811 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
812
813 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
814 SYNC_WALKER | SYNC_ALIGNER));
815 /* Setup various GPU states */
816 if (rdev->family == CHIP_RV670)
817 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
818
819 tmp = RREG32(SX_DEBUG_1);
820 tmp |= SMX_EVENT_RELEASE;
821 if ((rdev->family > CHIP_R600))
822 tmp |= ENABLE_NEW_SMX_ADDRESS;
823 WREG32(SX_DEBUG_1, tmp);
824
825 if (((rdev->family) == CHIP_R600) ||
826 ((rdev->family) == CHIP_RV630) ||
827 ((rdev->family) == CHIP_RV610) ||
828 ((rdev->family) == CHIP_RV620) ||
829 ((rdev->family) == CHIP_RS780)) {
830 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
831 } else {
832 WREG32(DB_DEBUG, 0);
833 }
834 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
835 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
836
837 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
838 WREG32(VGT_NUM_INSTANCES, 0);
839
840 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
841 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
842
843 tmp = RREG32(SQ_MS_FIFO_SIZES);
844 if (((rdev->family) == CHIP_RV610) ||
845 ((rdev->family) == CHIP_RV620) ||
846 ((rdev->family) == CHIP_RS780)) {
847 tmp = (CACHE_FIFO_SIZE(0xa) |
848 FETCH_FIFO_HIWATER(0xa) |
849 DONE_FIFO_HIWATER(0xe0) |
850 ALU_UPDATE_FIFO_HIWATER(0x8));
851 } else if (((rdev->family) == CHIP_R600) ||
852 ((rdev->family) == CHIP_RV630)) {
853 tmp &= ~DONE_FIFO_HIWATER(0xff);
854 tmp |= DONE_FIFO_HIWATER(0x4);
855 }
856 WREG32(SQ_MS_FIFO_SIZES, tmp);
857
858 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
859 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
860 */
861 sq_config = RREG32(SQ_CONFIG);
862 sq_config &= ~(PS_PRIO(3) |
863 VS_PRIO(3) |
864 GS_PRIO(3) |
865 ES_PRIO(3));
866 sq_config |= (DX9_CONSTS |
867 VC_ENABLE |
868 PS_PRIO(0) |
869 VS_PRIO(1) |
870 GS_PRIO(2) |
871 ES_PRIO(3));
872
873 if ((rdev->family) == CHIP_R600) {
874 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
875 NUM_VS_GPRS(124) |
876 NUM_CLAUSE_TEMP_GPRS(4));
877 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
878 NUM_ES_GPRS(0));
879 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
880 NUM_VS_THREADS(48) |
881 NUM_GS_THREADS(4) |
882 NUM_ES_THREADS(4));
883 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
884 NUM_VS_STACK_ENTRIES(128));
885 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
886 NUM_ES_STACK_ENTRIES(0));
887 } else if (((rdev->family) == CHIP_RV610) ||
888 ((rdev->family) == CHIP_RV620) ||
889 ((rdev->family) == CHIP_RS780)) {
890 /* no vertex cache */
891 sq_config &= ~VC_ENABLE;
892
893 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
894 NUM_VS_GPRS(44) |
895 NUM_CLAUSE_TEMP_GPRS(2));
896 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
897 NUM_ES_GPRS(17));
898 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
899 NUM_VS_THREADS(78) |
900 NUM_GS_THREADS(4) |
901 NUM_ES_THREADS(31));
902 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
903 NUM_VS_STACK_ENTRIES(40));
904 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
905 NUM_ES_STACK_ENTRIES(16));
906 } else if (((rdev->family) == CHIP_RV630) ||
907 ((rdev->family) == CHIP_RV635)) {
908 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
909 NUM_VS_GPRS(44) |
910 NUM_CLAUSE_TEMP_GPRS(2));
911 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
912 NUM_ES_GPRS(18));
913 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
914 NUM_VS_THREADS(78) |
915 NUM_GS_THREADS(4) |
916 NUM_ES_THREADS(31));
917 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
918 NUM_VS_STACK_ENTRIES(40));
919 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
920 NUM_ES_STACK_ENTRIES(16));
921 } else if ((rdev->family) == CHIP_RV670) {
922 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
923 NUM_VS_GPRS(44) |
924 NUM_CLAUSE_TEMP_GPRS(2));
925 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
926 NUM_ES_GPRS(17));
927 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
928 NUM_VS_THREADS(78) |
929 NUM_GS_THREADS(4) |
930 NUM_ES_THREADS(31));
931 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
932 NUM_VS_STACK_ENTRIES(64));
933 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
934 NUM_ES_STACK_ENTRIES(64));
935 }
936
937 WREG32(SQ_CONFIG, sq_config);
938 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
939 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
940 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
941 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
942 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
943
944 if (((rdev->family) == CHIP_RV610) ||
945 ((rdev->family) == CHIP_RV620) ||
946 ((rdev->family) == CHIP_RS780)) {
947 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
948 } else {
949 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
950 }
951
952 /* More default values. 2D/3D driver should adjust as needed */
953 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
954 S1_X(0x4) | S1_Y(0xc)));
955 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
956 S1_X(0x2) | S1_Y(0x2) |
957 S2_X(0xa) | S2_Y(0x6) |
958 S3_X(0x6) | S3_Y(0xa)));
959 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
960 S1_X(0x4) | S1_Y(0xc) |
961 S2_X(0x1) | S2_Y(0x6) |
962 S3_X(0xa) | S3_Y(0xe)));
963 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
964 S5_X(0x0) | S5_Y(0x0) |
965 S6_X(0xb) | S6_Y(0x4) |
966 S7_X(0x7) | S7_Y(0x8)));
967
968 WREG32(VGT_STRMOUT_EN, 0);
969 tmp = rdev->config.r600.max_pipes * 16;
970 switch (rdev->family) {
971 case CHIP_RV610:
972 case CHIP_RS780:
973 case CHIP_RV620:
974 tmp += 32;
975 break;
976 case CHIP_RV670:
977 tmp += 128;
978 break;
979 default:
980 break;
981 }
982 if (tmp > 256) {
983 tmp = 256;
984 }
985 WREG32(VGT_ES_PER_GS, 128);
986 WREG32(VGT_GS_PER_ES, tmp);
987 WREG32(VGT_GS_PER_VS, 2);
988 WREG32(VGT_GS_VERTEX_REUSE, 16);
989
990 /* more default values. 2D/3D driver should adjust as needed */
991 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
992 WREG32(VGT_STRMOUT_EN, 0);
993 WREG32(SX_MISC, 0);
994 WREG32(PA_SC_MODE_CNTL, 0);
995 WREG32(PA_SC_AA_CONFIG, 0);
996 WREG32(PA_SC_LINE_STIPPLE, 0);
997 WREG32(SPI_INPUT_Z, 0);
998 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
999 WREG32(CB_COLOR7_FRAG, 0);
1000
1001 /* Clear render buffer base addresses */
1002 WREG32(CB_COLOR0_BASE, 0);
1003 WREG32(CB_COLOR1_BASE, 0);
1004 WREG32(CB_COLOR2_BASE, 0);
1005 WREG32(CB_COLOR3_BASE, 0);
1006 WREG32(CB_COLOR4_BASE, 0);
1007 WREG32(CB_COLOR5_BASE, 0);
1008 WREG32(CB_COLOR6_BASE, 0);
1009 WREG32(CB_COLOR7_BASE, 0);
1010 WREG32(CB_COLOR7_FRAG, 0);
1011
1012 switch (rdev->family) {
1013 case CHIP_RV610:
1014 case CHIP_RS780:
1015 case CHIP_RV620:
1016 tmp = TC_L2_SIZE(8);
1017 break;
1018 case CHIP_RV630:
1019 case CHIP_RV635:
1020 tmp = TC_L2_SIZE(4);
1021 break;
1022 case CHIP_R600:
1023 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1024 break;
1025 default:
1026 tmp = TC_L2_SIZE(0);
1027 break;
1028 }
1029 WREG32(TC_CNTL, tmp);
1030
1031 tmp = RREG32(HDP_HOST_PATH_CNTL);
1032 WREG32(HDP_HOST_PATH_CNTL, tmp);
1033
1034 tmp = RREG32(ARB_POP);
1035 tmp |= ENABLE_TC128;
1036 WREG32(ARB_POP, tmp);
1037
1038 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1039 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1040 NUM_CLIP_SEQ(3)));
1041 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1042}
1043
1044
151/* 1045/*
152 * Indirect registers accessor 1046 * Indirect registers accessor
153 */ 1047 */
154uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg) 1048u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
155{ 1049{
156 uint32_t r; 1050 u32 r;
157 1051
158 WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff)); 1052 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
159 (void)RREG32(R600_PCIE_PORT_INDEX); 1053 (void)RREG32(PCIE_PORT_INDEX);
160 r = RREG32(R600_PCIE_PORT_DATA); 1054 r = RREG32(PCIE_PORT_DATA);
161 return r; 1055 return r;
162} 1056}
163 1057
164void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1058void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
165{ 1059{
166 WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff)); 1060 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
167 (void)RREG32(R600_PCIE_PORT_INDEX); 1061 (void)RREG32(PCIE_PORT_INDEX);
168 WREG32(R600_PCIE_PORT_DATA, (v)); 1062 WREG32(PCIE_PORT_DATA, (v));
169 (void)RREG32(R600_PCIE_PORT_DATA); 1063 (void)RREG32(PCIE_PORT_DATA);
1064}
1065
1066
1067/*
1068 * CP & Ring
1069 */
1070void r600_cp_stop(struct radeon_device *rdev)
1071{
1072 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1073}
1074
1075int r600_cp_init_microcode(struct radeon_device *rdev)
1076{
1077 struct platform_device *pdev;
1078 const char *chip_name;
1079 size_t pfp_req_size, me_req_size;
1080 char fw_name[30];
1081 int err;
1082
1083 DRM_DEBUG("\n");
1084
1085 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1086 err = IS_ERR(pdev);
1087 if (err) {
1088 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1089 return -EINVAL;
1090 }
1091
1092 switch (rdev->family) {
1093 case CHIP_R600: chip_name = "R600"; break;
1094 case CHIP_RV610: chip_name = "RV610"; break;
1095 case CHIP_RV630: chip_name = "RV630"; break;
1096 case CHIP_RV620: chip_name = "RV620"; break;
1097 case CHIP_RV635: chip_name = "RV635"; break;
1098 case CHIP_RV670: chip_name = "RV670"; break;
1099 case CHIP_RS780:
1100 case CHIP_RS880: chip_name = "RS780"; break;
1101 case CHIP_RV770: chip_name = "RV770"; break;
1102 case CHIP_RV730:
1103 case CHIP_RV740: chip_name = "RV730"; break;
1104 case CHIP_RV710: chip_name = "RV710"; break;
1105 default: BUG();
1106 }
1107
1108 if (rdev->family >= CHIP_RV770) {
1109 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1110 me_req_size = R700_PM4_UCODE_SIZE * 4;
1111 } else {
1112 pfp_req_size = PFP_UCODE_SIZE * 4;
1113 me_req_size = PM4_UCODE_SIZE * 12;
1114 }
1115
1116 DRM_INFO("Loading %s CP Microcode\n", chip_name);
1117
1118 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1119 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1120 if (err)
1121 goto out;
1122 if (rdev->pfp_fw->size != pfp_req_size) {
1123 printk(KERN_ERR
1124 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1125 rdev->pfp_fw->size, fw_name);
1126 err = -EINVAL;
1127 goto out;
1128 }
1129
1130 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1131 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1132 if (err)
1133 goto out;
1134 if (rdev->me_fw->size != me_req_size) {
1135 printk(KERN_ERR
1136 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1137 rdev->me_fw->size, fw_name);
1138 err = -EINVAL;
1139 }
1140out:
1141 platform_device_unregister(pdev);
1142
1143 if (err) {
1144 if (err != -EINVAL)
1145 printk(KERN_ERR
1146 "r600_cp: Failed to load firmware \"%s\"\n",
1147 fw_name);
1148 release_firmware(rdev->pfp_fw);
1149 rdev->pfp_fw = NULL;
1150 release_firmware(rdev->me_fw);
1151 rdev->me_fw = NULL;
1152 }
1153 return err;
1154}
1155
1156static int r600_cp_load_microcode(struct radeon_device *rdev)
1157{
1158 const __be32 *fw_data;
1159 int i;
1160
1161 if (!rdev->me_fw || !rdev->pfp_fw)
1162 return -EINVAL;
1163
1164 r600_cp_stop(rdev);
1165
1166 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1167
1168 /* Reset cp */
1169 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1170 RREG32(GRBM_SOFT_RESET);
1171 mdelay(15);
1172 WREG32(GRBM_SOFT_RESET, 0);
1173
1174 WREG32(CP_ME_RAM_WADDR, 0);
1175
1176 fw_data = (const __be32 *)rdev->me_fw->data;
1177 WREG32(CP_ME_RAM_WADDR, 0);
1178 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1179 WREG32(CP_ME_RAM_DATA,
1180 be32_to_cpup(fw_data++));
1181
1182 fw_data = (const __be32 *)rdev->pfp_fw->data;
1183 WREG32(CP_PFP_UCODE_ADDR, 0);
1184 for (i = 0; i < PFP_UCODE_SIZE; i++)
1185 WREG32(CP_PFP_UCODE_DATA,
1186 be32_to_cpup(fw_data++));
1187
1188 WREG32(CP_PFP_UCODE_ADDR, 0);
1189 WREG32(CP_ME_RAM_WADDR, 0);
1190 WREG32(CP_ME_RAM_RADDR, 0);
1191 return 0;
1192}
1193
1194int r600_cp_start(struct radeon_device *rdev)
1195{
1196 int r;
1197 uint32_t cp_me;
1198
1199 r = radeon_ring_lock(rdev, 7);
1200 if (r) {
1201 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1202 return r;
1203 }
1204 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1205 radeon_ring_write(rdev, 0x1);
1206 if (rdev->family < CHIP_RV770) {
1207 radeon_ring_write(rdev, 0x3);
1208 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1209 } else {
1210 radeon_ring_write(rdev, 0x0);
1211 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1212 }
1213 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1214 radeon_ring_write(rdev, 0);
1215 radeon_ring_write(rdev, 0);
1216 radeon_ring_unlock_commit(rdev);
1217
1218 cp_me = 0xff;
1219 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1220 return 0;
1221}
1222
1223int r600_cp_resume(struct radeon_device *rdev)
1224{
1225 u32 tmp;
1226 u32 rb_bufsz;
1227 int r;
1228
1229 /* Reset cp */
1230 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1231 RREG32(GRBM_SOFT_RESET);
1232 mdelay(15);
1233 WREG32(GRBM_SOFT_RESET, 0);
1234
1235 /* Set ring buffer size */
1236 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1237#ifdef __BIG_ENDIAN
1238 WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE |
1239 (drm_order(4096/8) << 8) | rb_bufsz);
1240#else
1241 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(4096/8) << 8) | rb_bufsz);
1242#endif
1243 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1244
1245 /* Set the write pointer delay */
1246 WREG32(CP_RB_WPTR_DELAY, 0);
1247
1248 /* Initialize the ring buffer's read and write pointers */
1249 tmp = RREG32(CP_RB_CNTL);
1250 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1251 WREG32(CP_RB_RPTR_WR, 0);
1252 WREG32(CP_RB_WPTR, 0);
1253 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1254 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1255 mdelay(1);
1256 WREG32(CP_RB_CNTL, tmp);
1257
1258 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1259 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1260
1261 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1262 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1263
1264 r600_cp_start(rdev);
1265 rdev->cp.ready = true;
1266 r = radeon_ring_test(rdev);
1267 if (r) {
1268 rdev->cp.ready = false;
1269 return r;
1270 }
1271 return 0;
1272}
1273
1274void r600_cp_commit(struct radeon_device *rdev)
1275{
1276 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1277 (void)RREG32(CP_RB_WPTR);
1278}
1279
1280void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1281{
1282 u32 rb_bufsz;
1283
1284 /* Align ring size */
1285 rb_bufsz = drm_order(ring_size / 8);
1286 ring_size = (1 << (rb_bufsz + 1)) * 4;
1287 rdev->cp.ring_size = ring_size;
1288 rdev->cp.align_mask = 16 - 1;
1289}
1290
1291
1292/*
1293 * GPU scratch registers helpers function.
1294 */
1295void r600_scratch_init(struct radeon_device *rdev)
1296{
1297 int i;
1298
1299 rdev->scratch.num_reg = 7;
1300 for (i = 0; i < rdev->scratch.num_reg; i++) {
1301 rdev->scratch.free[i] = true;
1302 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1303 }
1304}
1305
1306int r600_ring_test(struct radeon_device *rdev)
1307{
1308 uint32_t scratch;
1309 uint32_t tmp = 0;
1310 unsigned i;
1311 int r;
1312
1313 r = radeon_scratch_get(rdev, &scratch);
1314 if (r) {
1315 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1316 return r;
1317 }
1318 WREG32(scratch, 0xCAFEDEAD);
1319 r = radeon_ring_lock(rdev, 3);
1320 if (r) {
1321 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1322 radeon_scratch_free(rdev, scratch);
1323 return r;
1324 }
1325 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1326 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1327 radeon_ring_write(rdev, 0xDEADBEEF);
1328 radeon_ring_unlock_commit(rdev);
1329 for (i = 0; i < rdev->usec_timeout; i++) {
1330 tmp = RREG32(scratch);
1331 if (tmp == 0xDEADBEEF)
1332 break;
1333 DRM_UDELAY(1);
1334 }
1335 if (i < rdev->usec_timeout) {
1336 DRM_INFO("ring test succeeded in %d usecs\n", i);
1337 } else {
1338 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1339 scratch, tmp);
1340 r = -EINVAL;
1341 }
1342 radeon_scratch_free(rdev, scratch);
1343 return r;
1344}
1345
1346/*
1347 * Writeback
1348 */
1349int r600_wb_init(struct radeon_device *rdev)
1350{
1351 int r;
1352
1353 if (rdev->wb.wb_obj == NULL) {
1354 r = radeon_object_create(rdev, NULL, 4096,
1355 true,
1356 RADEON_GEM_DOMAIN_GTT,
1357 false, &rdev->wb.wb_obj);
1358 if (r) {
1359 DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
1360 return r;
1361 }
1362 r = radeon_object_pin(rdev->wb.wb_obj,
1363 RADEON_GEM_DOMAIN_GTT,
1364 &rdev->wb.gpu_addr);
1365 if (r) {
1366 DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
1367 return r;
1368 }
1369 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1370 if (r) {
1371 DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
1372 return r;
1373 }
1374 }
1375 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1376 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1377 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1378 WREG32(SCRATCH_UMSK, 0xff);
1379 return 0;
1380}
1381
1382void r600_wb_fini(struct radeon_device *rdev)
1383{
1384 if (rdev->wb.wb_obj) {
1385 radeon_object_kunmap(rdev->wb.wb_obj);
1386 radeon_object_unpin(rdev->wb.wb_obj);
1387 radeon_object_unref(&rdev->wb.wb_obj);
1388 rdev->wb.wb = NULL;
1389 rdev->wb.wb_obj = NULL;
1390 }
1391}
1392
1393
1394/*
1395 * CS
1396 */
1397void r600_fence_ring_emit(struct radeon_device *rdev,
1398 struct radeon_fence *fence)
1399{
1400 /* Emit fence sequence & fire IRQ */
1401 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1402 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1403 radeon_ring_write(rdev, fence->seq);
1404}
1405
1406int r600_copy_dma(struct radeon_device *rdev,
1407 uint64_t src_offset,
1408 uint64_t dst_offset,
1409 unsigned num_pages,
1410 struct radeon_fence *fence)
1411{
1412 /* FIXME: implement */
1413 return 0;
1414}
1415
1416int r600_copy_blit(struct radeon_device *rdev,
1417 uint64_t src_offset, uint64_t dst_offset,
1418 unsigned num_pages, struct radeon_fence *fence)
1419{
1420 r600_blit_prepare_copy(rdev, num_pages * 4096);
1421 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * 4096);
1422 r600_blit_done_copy(rdev, fence);
1423 return 0;
1424}
1425
1426int r600_irq_process(struct radeon_device *rdev)
1427{
1428 /* FIXME: implement */
1429 return 0;
1430}
1431
1432int r600_irq_set(struct radeon_device *rdev)
1433{
1434 /* FIXME: implement */
1435 return 0;
1436}
1437
1438int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1439 uint32_t tiling_flags, uint32_t pitch,
1440 uint32_t offset, uint32_t obj_size)
1441{
1442 /* FIXME: implement */
1443 return 0;
1444}
1445
1446void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1447{
1448 /* FIXME: implement */
1449}
1450
1451
1452bool r600_card_posted(struct radeon_device *rdev)
1453{
1454 uint32_t reg;
1455
1456 /* first check CRTCs */
1457 reg = RREG32(D1CRTC_CONTROL) |
1458 RREG32(D2CRTC_CONTROL);
1459 if (reg & CRTC_EN)
1460 return true;
1461
1462 /* then check MEM_SIZE, in case the crtcs are off */
1463 if (RREG32(CONFIG_MEMSIZE))
1464 return true;
1465
1466 return false;
1467}
1468
1469int r600_startup(struct radeon_device *rdev)
1470{
1471 int r;
1472
1473 r600_gpu_reset(rdev);
1474 r600_mc_resume(rdev);
1475 r = r600_pcie_gart_enable(rdev);
1476 if (r)
1477 return r;
1478 r600_gpu_init(rdev);
1479
1480 r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1481 &rdev->r600_blit.shader_gpu_addr);
1482 if (r) {
1483 DRM_ERROR("failed to pin blit object %d\n", r);
1484 return r;
1485 }
1486
1487 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1488 if (r)
1489 return r;
1490 r = r600_cp_load_microcode(rdev);
1491 if (r)
1492 return r;
1493 r = r600_cp_resume(rdev);
1494 if (r)
1495 return r;
1496 r = r600_wb_init(rdev);
1497 if (r)
1498 return r;
1499 return 0;
1500}
1501
1502void r600_vga_set_state(struct radeon_device *rdev, bool state)
1503{
1504 uint32_t temp;
1505
1506 temp = RREG32(CONFIG_CNTL);
1507 if (state == false) {
1508 temp &= ~(1<<0);
1509 temp |= (1<<1);
1510 } else {
1511 temp &= ~(1<<1);
1512 }
1513 WREG32(CONFIG_CNTL, temp);
1514}
1515
1516int r600_resume(struct radeon_device *rdev)
1517{
1518 int r;
1519
1520 if (radeon_gpu_reset(rdev)) {
1521 /* FIXME: what do we want to do here ? */
1522 }
1523 /* post card */
1524 if (rdev->is_atom_bios) {
1525 atom_asic_init(rdev->mode_info.atom_context);
1526 } else {
1527 radeon_combios_asic_init(rdev->ddev);
1528 }
1529 /* Initialize clocks */
1530 r = radeon_clocks_init(rdev);
1531 if (r) {
1532 return r;
1533 }
1534
1535 r = r600_startup(rdev);
1536 if (r) {
1537 DRM_ERROR("r600 startup failed on resume\n");
1538 return r;
1539 }
1540
1541 r = radeon_ib_test(rdev);
1542 if (r) {
1543 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1544 return r;
1545 }
1546 return r;
1547}
1548
1549
1550int r600_suspend(struct radeon_device *rdev)
1551{
1552 /* FIXME: we should wait for ring to be empty */
1553 r600_cp_stop(rdev);
1554 rdev->cp.ready = false;
1555
1556 r600_pcie_gart_disable(rdev);
1557 /* unpin shaders bo */
1558 radeon_object_unpin(rdev->r600_blit.shader_obj);
1559 return 0;
1560}
1561
1562/* Plan is to move initialization in that function and use
1563 * helper function so that radeon_device_init pretty much
1564 * do nothing more than calling asic specific function. This
1565 * should also allow to remove a bunch of callback function
1566 * like vram_info.
1567 */
1568int r600_init(struct radeon_device *rdev)
1569{
1570 int r;
1571
1572 rdev->new_init_path = true;
1573 r = radeon_dummy_page_init(rdev);
1574 if (r)
1575 return r;
1576 if (r600_debugfs_mc_info_init(rdev)) {
1577 DRM_ERROR("Failed to register debugfs file for mc !\n");
1578 }
1579 /* This don't do much */
1580 r = radeon_gem_init(rdev);
1581 if (r)
1582 return r;
1583 /* Read BIOS */
1584 if (!radeon_get_bios(rdev)) {
1585 if (ASIC_IS_AVIVO(rdev))
1586 return -EINVAL;
1587 }
1588 /* Must be an ATOMBIOS */
1589 if (!rdev->is_atom_bios)
1590 return -EINVAL;
1591 r = radeon_atombios_init(rdev);
1592 if (r)
1593 return r;
1594 /* Post card if necessary */
1595 if (!r600_card_posted(rdev) && rdev->bios) {
1596 DRM_INFO("GPU not posted. posting now...\n");
1597 atom_asic_init(rdev->mode_info.atom_context);
1598 }
1599 /* Initialize scratch registers */
1600 r600_scratch_init(rdev);
1601 /* Initialize surface registers */
1602 radeon_surface_init(rdev);
1603 radeon_get_clock_info(rdev->ddev);
1604 r = radeon_clocks_init(rdev);
1605 if (r)
1606 return r;
1607 /* Fence driver */
1608 r = radeon_fence_driver_init(rdev);
1609 if (r)
1610 return r;
1611 r = r600_mc_init(rdev);
1612 if (r) {
1613 if (rdev->flags & RADEON_IS_AGP) {
1614 /* Retry with disabling AGP */
1615 r600_fini(rdev);
1616 rdev->flags &= ~RADEON_IS_AGP;
1617 return r600_init(rdev);
1618 }
1619 return r;
1620 }
1621 /* Memory manager */
1622 r = radeon_object_init(rdev);
1623 if (r)
1624 return r;
1625 rdev->cp.ring_obj = NULL;
1626 r600_ring_init(rdev, 1024 * 1024);
1627
1628 if (!rdev->me_fw || !rdev->pfp_fw) {
1629 r = r600_cp_init_microcode(rdev);
1630 if (r) {
1631 DRM_ERROR("Failed to load firmware!\n");
1632 return r;
1633 }
1634 }
1635
1636 r = r600_pcie_gart_init(rdev);
1637 if (r)
1638 return r;
1639
1640 rdev->accel_working = true;
1641 r = r600_blit_init(rdev);
1642 if (r) {
1643 DRM_ERROR("radeon: failled blitter (%d).\n", r);
1644 return r;
1645 }
1646
1647 r = r600_startup(rdev);
1648 if (r) {
1649 if (rdev->flags & RADEON_IS_AGP) {
1650 /* Retry with disabling AGP */
1651 r600_fini(rdev);
1652 rdev->flags &= ~RADEON_IS_AGP;
1653 return r600_init(rdev);
1654 }
1655 rdev->accel_working = false;
1656 }
1657 if (rdev->accel_working) {
1658 r = radeon_ib_pool_init(rdev);
1659 if (r) {
1660 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
1661 rdev->accel_working = false;
1662 }
1663 r = radeon_ib_test(rdev);
1664 if (r) {
1665 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1666 rdev->accel_working = false;
1667 }
1668 }
1669 return 0;
1670}
1671
1672void r600_fini(struct radeon_device *rdev)
1673{
1674 /* Suspend operations */
1675 r600_suspend(rdev);
1676
1677 r600_blit_fini(rdev);
1678 radeon_ring_fini(rdev);
1679 r600_pcie_gart_fini(rdev);
1680 radeon_gem_fini(rdev);
1681 radeon_fence_driver_fini(rdev);
1682 radeon_clocks_fini(rdev);
1683#if __OS_HAS_AGP
1684 if (rdev->flags & RADEON_IS_AGP)
1685 radeon_agp_fini(rdev);
1686#endif
1687 radeon_object_fini(rdev);
1688 if (rdev->is_atom_bios)
1689 radeon_atombios_fini(rdev);
1690 else
1691 radeon_combios_fini(rdev);
1692 kfree(rdev->bios);
1693 rdev->bios = NULL;
1694 radeon_dummy_page_fini(rdev);
1695}
1696
1697
1698/*
1699 * CS stuff
1700 */
1701void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1702{
1703 /* FIXME: implement */
1704 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1705 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
1706 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1707 radeon_ring_write(rdev, ib->length_dw);
1708}
1709
1710int r600_ib_test(struct radeon_device *rdev)
1711{
1712 struct radeon_ib *ib;
1713 uint32_t scratch;
1714 uint32_t tmp = 0;
1715 unsigned i;
1716 int r;
1717
1718 r = radeon_scratch_get(rdev, &scratch);
1719 if (r) {
1720 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
1721 return r;
1722 }
1723 WREG32(scratch, 0xCAFEDEAD);
1724 r = radeon_ib_get(rdev, &ib);
1725 if (r) {
1726 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
1727 return r;
1728 }
1729 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1730 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1731 ib->ptr[2] = 0xDEADBEEF;
1732 ib->ptr[3] = PACKET2(0);
1733 ib->ptr[4] = PACKET2(0);
1734 ib->ptr[5] = PACKET2(0);
1735 ib->ptr[6] = PACKET2(0);
1736 ib->ptr[7] = PACKET2(0);
1737 ib->ptr[8] = PACKET2(0);
1738 ib->ptr[9] = PACKET2(0);
1739 ib->ptr[10] = PACKET2(0);
1740 ib->ptr[11] = PACKET2(0);
1741 ib->ptr[12] = PACKET2(0);
1742 ib->ptr[13] = PACKET2(0);
1743 ib->ptr[14] = PACKET2(0);
1744 ib->ptr[15] = PACKET2(0);
1745 ib->length_dw = 16;
1746 r = radeon_ib_schedule(rdev, ib);
1747 if (r) {
1748 radeon_scratch_free(rdev, scratch);
1749 radeon_ib_free(rdev, &ib);
1750 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
1751 return r;
1752 }
1753 r = radeon_fence_wait(ib->fence, false);
1754 if (r) {
1755 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
1756 return r;
1757 }
1758 for (i = 0; i < rdev->usec_timeout; i++) {
1759 tmp = RREG32(scratch);
1760 if (tmp == 0xDEADBEEF)
1761 break;
1762 DRM_UDELAY(1);
1763 }
1764 if (i < rdev->usec_timeout) {
1765 DRM_INFO("ib test succeeded in %u usecs\n", i);
1766 } else {
1767 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
1768 scratch, tmp);
1769 r = -EINVAL;
1770 }
1771 radeon_scratch_free(rdev, scratch);
1772 radeon_ib_free(rdev, &ib);
1773 return r;
1774}
1775
1776
1777
1778
1779/*
1780 * Debugfs info
1781 */
1782#if defined(CONFIG_DEBUG_FS)
1783
1784static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
1785{
1786 struct drm_info_node *node = (struct drm_info_node *) m->private;
1787 struct drm_device *dev = node->minor->dev;
1788 struct radeon_device *rdev = dev->dev_private;
1789 uint32_t rdp, wdp;
1790 unsigned count, i, j;
1791
1792 radeon_ring_free_size(rdev);
1793 rdp = RREG32(CP_RB_RPTR);
1794 wdp = RREG32(CP_RB_WPTR);
1795 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1796 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
1797 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1798 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1799 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1800 seq_printf(m, "%u dwords in ring\n", count);
1801 for (j = 0; j <= count; j++) {
1802 i = (rdp + j) & rdev->cp.ptr_mask;
1803 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1804 }
1805 return 0;
1806}
1807
1808static int r600_debugfs_mc_info(struct seq_file *m, void *data)
1809{
1810 struct drm_info_node *node = (struct drm_info_node *) m->private;
1811 struct drm_device *dev = node->minor->dev;
1812 struct radeon_device *rdev = dev->dev_private;
1813
1814 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
1815 DREG32_SYS(m, rdev, VM_L2_STATUS);
1816 return 0;
1817}
1818
1819static struct drm_info_list r600_mc_info_list[] = {
1820 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
1821 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
1822};
1823#endif
1824
1825int r600_debugfs_mc_info_init(struct radeon_device *rdev)
1826{
1827#if defined(CONFIG_DEBUG_FS)
1828 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
1829#else
1830 return 0;
1831#endif
170} 1832}
diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c
new file mode 100644
index 000000000000..dde2ccbf1d15
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_blit.c
@@ -0,0 +1,850 @@
1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Alex Deucher <alexander.deucher@amd.com>
25 */
26#include "drmP.h"
27#include "drm.h"
28#include "radeon_drm.h"
29#include "radeon_drv.h"
30
31#include "r600_blit_shaders.h"
32
33#define DI_PT_RECTLIST 0x11
34#define DI_INDEX_SIZE_16_BIT 0x0
35#define DI_SRC_SEL_AUTO_INDEX 0x2
36
37#define FMT_8 0x1
38#define FMT_5_6_5 0x8
39#define FMT_8_8_8_8 0x1a
40#define COLOR_8 0x1
41#define COLOR_5_6_5 0x8
42#define COLOR_8_8_8_8 0x1a
43
44static inline void
45set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr)
46{
47 u32 cb_color_info;
48 int pitch, slice;
49 RING_LOCALS;
50 DRM_DEBUG("\n");
51
52 h = (h + 7) & ~7;
53 if (h < 8)
54 h = 8;
55
56 cb_color_info = ((format << 2) | (1 << 27));
57 pitch = (w / 8) - 1;
58 slice = ((w * h) / 64) - 1;
59
60 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600) &&
61 ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) {
62 BEGIN_RING(21 + 2);
63 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
64 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
65 OUT_RING(gpu_addr >> 8);
66 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
67 OUT_RING(2 << 0);
68 } else {
69 BEGIN_RING(21);
70 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
71 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
72 OUT_RING(gpu_addr >> 8);
73 }
74
75 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
76 OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
77 OUT_RING((pitch << 0) | (slice << 10));
78
79 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
80 OUT_RING((R600_CB_COLOR0_VIEW - R600_SET_CONTEXT_REG_OFFSET) >> 2);
81 OUT_RING(0);
82
83 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
84 OUT_RING((R600_CB_COLOR0_INFO - R600_SET_CONTEXT_REG_OFFSET) >> 2);
85 OUT_RING(cb_color_info);
86
87 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
88 OUT_RING((R600_CB_COLOR0_TILE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
89 OUT_RING(0);
90
91 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
92 OUT_RING((R600_CB_COLOR0_FRAG - R600_SET_CONTEXT_REG_OFFSET) >> 2);
93 OUT_RING(0);
94
95 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
96 OUT_RING((R600_CB_COLOR0_MASK - R600_SET_CONTEXT_REG_OFFSET) >> 2);
97 OUT_RING(0);
98
99 ADVANCE_RING();
100}
101
102static inline void
103cp_set_surface_sync(drm_radeon_private_t *dev_priv,
104 u32 sync_type, u32 size, u64 mc_addr)
105{
106 u32 cp_coher_size;
107 RING_LOCALS;
108 DRM_DEBUG("\n");
109
110 if (size == 0xffffffff)
111 cp_coher_size = 0xffffffff;
112 else
113 cp_coher_size = ((size + 255) >> 8);
114
115 BEGIN_RING(5);
116 OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
117 OUT_RING(sync_type);
118 OUT_RING(cp_coher_size);
119 OUT_RING((mc_addr >> 8));
120 OUT_RING(10); /* poll interval */
121 ADVANCE_RING();
122}
123
124static inline void
125set_shaders(struct drm_device *dev)
126{
127 drm_radeon_private_t *dev_priv = dev->dev_private;
128 u64 gpu_addr;
129 int i;
130 u32 *vs, *ps;
131 uint32_t sq_pgm_resources;
132 RING_LOCALS;
133 DRM_DEBUG("\n");
134
135 /* load shaders */
136 vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset);
137 ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256);
138
139 for (i = 0; i < r6xx_vs_size; i++)
140 vs[i] = r6xx_vs[i];
141 for (i = 0; i < r6xx_ps_size; i++)
142 ps[i] = r6xx_ps[i];
143
144 dev_priv->blit_vb->used = 512;
145
146 gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset;
147
148 /* setup shader regs */
149 sq_pgm_resources = (1 << 0);
150
151 BEGIN_RING(9 + 12);
152 /* VS */
153 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
154 OUT_RING((R600_SQ_PGM_START_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
155 OUT_RING(gpu_addr >> 8);
156
157 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
158 OUT_RING((R600_SQ_PGM_RESOURCES_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
159 OUT_RING(sq_pgm_resources);
160
161 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
162 OUT_RING((R600_SQ_PGM_CF_OFFSET_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
163 OUT_RING(0);
164
165 /* PS */
166 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
167 OUT_RING((R600_SQ_PGM_START_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
168 OUT_RING((gpu_addr + 256) >> 8);
169
170 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
171 OUT_RING((R600_SQ_PGM_RESOURCES_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
172 OUT_RING(sq_pgm_resources | (1 << 28));
173
174 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
175 OUT_RING((R600_SQ_PGM_EXPORTS_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
176 OUT_RING(2);
177
178 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
179 OUT_RING((R600_SQ_PGM_CF_OFFSET_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
180 OUT_RING(0);
181 ADVANCE_RING();
182
183 cp_set_surface_sync(dev_priv,
184 R600_SH_ACTION_ENA, 512, gpu_addr);
185}
186
187static inline void
188set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr)
189{
190 uint32_t sq_vtx_constant_word2;
191 RING_LOCALS;
192 DRM_DEBUG("\n");
193
194 sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8));
195
196 BEGIN_RING(9);
197 OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
198 OUT_RING(0x460);
199 OUT_RING(gpu_addr & 0xffffffff);
200 OUT_RING(48 - 1);
201 OUT_RING(sq_vtx_constant_word2);
202 OUT_RING(1 << 0);
203 OUT_RING(0);
204 OUT_RING(0);
205 OUT_RING(R600_SQ_TEX_VTX_VALID_BUFFER << 30);
206 ADVANCE_RING();
207
208 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
209 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
210 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
211 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
212 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
213 cp_set_surface_sync(dev_priv,
214 R600_TC_ACTION_ENA, 48, gpu_addr);
215 else
216 cp_set_surface_sync(dev_priv,
217 R600_VC_ACTION_ENA, 48, gpu_addr);
218}
219
220static inline void
221set_tex_resource(drm_radeon_private_t *dev_priv,
222 int format, int w, int h, int pitch, u64 gpu_addr)
223{
224 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
225 RING_LOCALS;
226 DRM_DEBUG("\n");
227
228 if (h < 1)
229 h = 1;
230
231 sq_tex_resource_word0 = (1 << 0);
232 sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
233 ((w - 1) << 19));
234
235 sq_tex_resource_word1 = (format << 26);
236 sq_tex_resource_word1 |= ((h - 1) << 0);
237
238 sq_tex_resource_word4 = ((1 << 14) |
239 (0 << 16) |
240 (1 << 19) |
241 (2 << 22) |
242 (3 << 25));
243
244 BEGIN_RING(9);
245 OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
246 OUT_RING(0);
247 OUT_RING(sq_tex_resource_word0);
248 OUT_RING(sq_tex_resource_word1);
249 OUT_RING(gpu_addr >> 8);
250 OUT_RING(gpu_addr >> 8);
251 OUT_RING(sq_tex_resource_word4);
252 OUT_RING(0);
253 OUT_RING(R600_SQ_TEX_VTX_VALID_TEXTURE << 30);
254 ADVANCE_RING();
255
256}
257
258static inline void
259set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2)
260{
261 RING_LOCALS;
262 DRM_DEBUG("\n");
263
264 BEGIN_RING(12);
265 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
266 OUT_RING((R600_PA_SC_SCREEN_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
267 OUT_RING((x1 << 0) | (y1 << 16));
268 OUT_RING((x2 << 0) | (y2 << 16));
269
270 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
271 OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
272 OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
273 OUT_RING((x2 << 0) | (y2 << 16));
274
275 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
276 OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
277 OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
278 OUT_RING((x2 << 0) | (y2 << 16));
279 ADVANCE_RING();
280}
281
282static inline void
283draw_auto(drm_radeon_private_t *dev_priv)
284{
285 RING_LOCALS;
286 DRM_DEBUG("\n");
287
288 BEGIN_RING(10);
289 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
290 OUT_RING((R600_VGT_PRIMITIVE_TYPE - R600_SET_CONFIG_REG_OFFSET) >> 2);
291 OUT_RING(DI_PT_RECTLIST);
292
293 OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
294 OUT_RING(DI_INDEX_SIZE_16_BIT);
295
296 OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
297 OUT_RING(1);
298
299 OUT_RING(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
300 OUT_RING(3);
301 OUT_RING(DI_SRC_SEL_AUTO_INDEX);
302
303 ADVANCE_RING();
304 COMMIT_RING();
305}
306
307static inline void
308set_default_state(drm_radeon_private_t *dev_priv)
309{
310 int i;
311 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
312 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
313 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
314 int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
315 int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
316 RING_LOCALS;
317
318 switch ((dev_priv->flags & RADEON_FAMILY_MASK)) {
319 case CHIP_R600:
320 num_ps_gprs = 192;
321 num_vs_gprs = 56;
322 num_temp_gprs = 4;
323 num_gs_gprs = 0;
324 num_es_gprs = 0;
325 num_ps_threads = 136;
326 num_vs_threads = 48;
327 num_gs_threads = 4;
328 num_es_threads = 4;
329 num_ps_stack_entries = 128;
330 num_vs_stack_entries = 128;
331 num_gs_stack_entries = 0;
332 num_es_stack_entries = 0;
333 break;
334 case CHIP_RV630:
335 case CHIP_RV635:
336 num_ps_gprs = 84;
337 num_vs_gprs = 36;
338 num_temp_gprs = 4;
339 num_gs_gprs = 0;
340 num_es_gprs = 0;
341 num_ps_threads = 144;
342 num_vs_threads = 40;
343 num_gs_threads = 4;
344 num_es_threads = 4;
345 num_ps_stack_entries = 40;
346 num_vs_stack_entries = 40;
347 num_gs_stack_entries = 32;
348 num_es_stack_entries = 16;
349 break;
350 case CHIP_RV610:
351 case CHIP_RV620:
352 case CHIP_RS780:
353 case CHIP_RS880:
354 default:
355 num_ps_gprs = 84;
356 num_vs_gprs = 36;
357 num_temp_gprs = 4;
358 num_gs_gprs = 0;
359 num_es_gprs = 0;
360 num_ps_threads = 136;
361 num_vs_threads = 48;
362 num_gs_threads = 4;
363 num_es_threads = 4;
364 num_ps_stack_entries = 40;
365 num_vs_stack_entries = 40;
366 num_gs_stack_entries = 32;
367 num_es_stack_entries = 16;
368 break;
369 case CHIP_RV670:
370 num_ps_gprs = 144;
371 num_vs_gprs = 40;
372 num_temp_gprs = 4;
373 num_gs_gprs = 0;
374 num_es_gprs = 0;
375 num_ps_threads = 136;
376 num_vs_threads = 48;
377 num_gs_threads = 4;
378 num_es_threads = 4;
379 num_ps_stack_entries = 40;
380 num_vs_stack_entries = 40;
381 num_gs_stack_entries = 32;
382 num_es_stack_entries = 16;
383 break;
384 case CHIP_RV770:
385 num_ps_gprs = 192;
386 num_vs_gprs = 56;
387 num_temp_gprs = 4;
388 num_gs_gprs = 0;
389 num_es_gprs = 0;
390 num_ps_threads = 188;
391 num_vs_threads = 60;
392 num_gs_threads = 0;
393 num_es_threads = 0;
394 num_ps_stack_entries = 256;
395 num_vs_stack_entries = 256;
396 num_gs_stack_entries = 0;
397 num_es_stack_entries = 0;
398 break;
399 case CHIP_RV730:
400 case CHIP_RV740:
401 num_ps_gprs = 84;
402 num_vs_gprs = 36;
403 num_temp_gprs = 4;
404 num_gs_gprs = 0;
405 num_es_gprs = 0;
406 num_ps_threads = 188;
407 num_vs_threads = 60;
408 num_gs_threads = 0;
409 num_es_threads = 0;
410 num_ps_stack_entries = 128;
411 num_vs_stack_entries = 128;
412 num_gs_stack_entries = 0;
413 num_es_stack_entries = 0;
414 break;
415 case CHIP_RV710:
416 num_ps_gprs = 192;
417 num_vs_gprs = 56;
418 num_temp_gprs = 4;
419 num_gs_gprs = 0;
420 num_es_gprs = 0;
421 num_ps_threads = 144;
422 num_vs_threads = 48;
423 num_gs_threads = 0;
424 num_es_threads = 0;
425 num_ps_stack_entries = 128;
426 num_vs_stack_entries = 128;
427 num_gs_stack_entries = 0;
428 num_es_stack_entries = 0;
429 break;
430 }
431
432 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
433 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
434 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
435 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
436 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
437 sq_config = 0;
438 else
439 sq_config = R600_VC_ENABLE;
440
441 sq_config |= (R600_DX9_CONSTS |
442 R600_ALU_INST_PREFER_VECTOR |
443 R600_PS_PRIO(0) |
444 R600_VS_PRIO(1) |
445 R600_GS_PRIO(2) |
446 R600_ES_PRIO(3));
447
448 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(num_ps_gprs) |
449 R600_NUM_VS_GPRS(num_vs_gprs) |
450 R600_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
451 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(num_gs_gprs) |
452 R600_NUM_ES_GPRS(num_es_gprs));
453 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(num_ps_threads) |
454 R600_NUM_VS_THREADS(num_vs_threads) |
455 R600_NUM_GS_THREADS(num_gs_threads) |
456 R600_NUM_ES_THREADS(num_es_threads));
457 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
458 R600_NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
459 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
460 R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries));
461
462 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
463 BEGIN_RING(r7xx_default_size + 10);
464 for (i = 0; i < r7xx_default_size; i++)
465 OUT_RING(r7xx_default_state[i]);
466 } else {
467 BEGIN_RING(r6xx_default_size + 10);
468 for (i = 0; i < r6xx_default_size; i++)
469 OUT_RING(r6xx_default_state[i]);
470 }
471 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
472 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
473 /* SQ config */
474 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 6));
475 OUT_RING((R600_SQ_CONFIG - R600_SET_CONFIG_REG_OFFSET) >> 2);
476 OUT_RING(sq_config);
477 OUT_RING(sq_gpr_resource_mgmt_1);
478 OUT_RING(sq_gpr_resource_mgmt_2);
479 OUT_RING(sq_thread_resource_mgmt);
480 OUT_RING(sq_stack_resource_mgmt_1);
481 OUT_RING(sq_stack_resource_mgmt_2);
482 ADVANCE_RING();
483}
484
485static inline uint32_t i2f(uint32_t input)
486{
487 u32 result, i, exponent, fraction;
488
489 if ((input & 0x3fff) == 0)
490 result = 0; /* 0 is a special case */
491 else {
492 exponent = 140; /* exponent biased by 127; */
493 fraction = (input & 0x3fff) << 10; /* cheat and only
494 handle numbers below 2^^15 */
495 for (i = 0; i < 14; i++) {
496 if (fraction & 0x800000)
497 break;
498 else {
499 fraction = fraction << 1; /* keep
500 shifting left until top bit = 1 */
501 exponent = exponent - 1;
502 }
503 }
504 result = exponent << 23 | (fraction & 0x7fffff); /* mask
505 off top bit; assumed 1 */
506 }
507 return result;
508}
509
510
511static inline int r600_nomm_get_vb(struct drm_device *dev)
512{
513 drm_radeon_private_t *dev_priv = dev->dev_private;
514 dev_priv->blit_vb = radeon_freelist_get(dev);
515 if (!dev_priv->blit_vb) {
516 DRM_ERROR("Unable to allocate vertex buffer for blit\n");
517 return -EAGAIN;
518 }
519 return 0;
520}
521
522static inline void r600_nomm_put_vb(struct drm_device *dev)
523{
524 drm_radeon_private_t *dev_priv = dev->dev_private;
525
526 dev_priv->blit_vb->used = 0;
527 radeon_cp_discard_buffer(dev, dev_priv->blit_vb->file_priv->master, dev_priv->blit_vb);
528}
529
530static inline void *r600_nomm_get_vb_ptr(struct drm_device *dev)
531{
532 drm_radeon_private_t *dev_priv = dev->dev_private;
533 return (((char *)dev->agp_buffer_map->handle +
534 dev_priv->blit_vb->offset + dev_priv->blit_vb->used));
535}
536
537int
538r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv)
539{
540 drm_radeon_private_t *dev_priv = dev->dev_private;
541 DRM_DEBUG("\n");
542
543 r600_nomm_get_vb(dev);
544
545 dev_priv->blit_vb->file_priv = file_priv;
546
547 set_default_state(dev_priv);
548 set_shaders(dev);
549
550 return 0;
551}
552
553
554void
555r600_done_blit_copy(struct drm_device *dev)
556{
557 drm_radeon_private_t *dev_priv = dev->dev_private;
558 RING_LOCALS;
559 DRM_DEBUG("\n");
560
561 BEGIN_RING(5);
562 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
563 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
564 /* wait for 3D idle clean */
565 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
566 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
567 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
568
569 ADVANCE_RING();
570 COMMIT_RING();
571
572 r600_nomm_put_vb(dev);
573}
574
575void
576r600_blit_copy(struct drm_device *dev,
577 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
578 int size_bytes)
579{
580 drm_radeon_private_t *dev_priv = dev->dev_private;
581 int max_bytes;
582 u64 vb_addr;
583 u32 *vb;
584
585 vb = r600_nomm_get_vb_ptr(dev);
586
587 if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
588 max_bytes = 8192;
589
590 while (size_bytes) {
591 int cur_size = size_bytes;
592 int src_x = src_gpu_addr & 255;
593 int dst_x = dst_gpu_addr & 255;
594 int h = 1;
595 src_gpu_addr = src_gpu_addr & ~255;
596 dst_gpu_addr = dst_gpu_addr & ~255;
597
598 if (!src_x && !dst_x) {
599 h = (cur_size / max_bytes);
600 if (h > 8192)
601 h = 8192;
602 if (h == 0)
603 h = 1;
604 else
605 cur_size = max_bytes;
606 } else {
607 if (cur_size > max_bytes)
608 cur_size = max_bytes;
609 if (cur_size > (max_bytes - dst_x))
610 cur_size = (max_bytes - dst_x);
611 if (cur_size > (max_bytes - src_x))
612 cur_size = (max_bytes - src_x);
613 }
614
615 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
616
617 r600_nomm_put_vb(dev);
618 r600_nomm_get_vb(dev);
619 if (!dev_priv->blit_vb)
620 return;
621 set_shaders(dev);
622 vb = r600_nomm_get_vb_ptr(dev);
623 }
624
625 vb[0] = i2f(dst_x);
626 vb[1] = 0;
627 vb[2] = i2f(src_x);
628 vb[3] = 0;
629
630 vb[4] = i2f(dst_x);
631 vb[5] = i2f(h);
632 vb[6] = i2f(src_x);
633 vb[7] = i2f(h);
634
635 vb[8] = i2f(dst_x + cur_size);
636 vb[9] = i2f(h);
637 vb[10] = i2f(src_x + cur_size);
638 vb[11] = i2f(h);
639
640 /* src */
641 set_tex_resource(dev_priv, FMT_8,
642 src_x + cur_size, h, src_x + cur_size,
643 src_gpu_addr);
644
645 cp_set_surface_sync(dev_priv,
646 R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
647
648 /* dst */
649 set_render_target(dev_priv, COLOR_8,
650 dst_x + cur_size, h,
651 dst_gpu_addr);
652
653 /* scissors */
654 set_scissors(dev_priv, dst_x, 0, dst_x + cur_size, h);
655
656 /* Vertex buffer setup */
657 vb_addr = dev_priv->gart_buffers_offset +
658 dev_priv->blit_vb->offset +
659 dev_priv->blit_vb->used;
660 set_vtx_resource(dev_priv, vb_addr);
661
662 /* draw */
663 draw_auto(dev_priv);
664
665 cp_set_surface_sync(dev_priv,
666 R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
667 cur_size * h, dst_gpu_addr);
668
669 vb += 12;
670 dev_priv->blit_vb->used += 12 * 4;
671
672 src_gpu_addr += cur_size * h;
673 dst_gpu_addr += cur_size * h;
674 size_bytes -= cur_size * h;
675 }
676 } else {
677 max_bytes = 8192 * 4;
678
679 while (size_bytes) {
680 int cur_size = size_bytes;
681 int src_x = (src_gpu_addr & 255);
682 int dst_x = (dst_gpu_addr & 255);
683 int h = 1;
684 src_gpu_addr = src_gpu_addr & ~255;
685 dst_gpu_addr = dst_gpu_addr & ~255;
686
687 if (!src_x && !dst_x) {
688 h = (cur_size / max_bytes);
689 if (h > 8192)
690 h = 8192;
691 if (h == 0)
692 h = 1;
693 else
694 cur_size = max_bytes;
695 } else {
696 if (cur_size > max_bytes)
697 cur_size = max_bytes;
698 if (cur_size > (max_bytes - dst_x))
699 cur_size = (max_bytes - dst_x);
700 if (cur_size > (max_bytes - src_x))
701 cur_size = (max_bytes - src_x);
702 }
703
704 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
705 r600_nomm_put_vb(dev);
706 r600_nomm_get_vb(dev);
707 if (!dev_priv->blit_vb)
708 return;
709
710 set_shaders(dev);
711 vb = r600_nomm_get_vb_ptr(dev);
712 }
713
714 vb[0] = i2f(dst_x / 4);
715 vb[1] = 0;
716 vb[2] = i2f(src_x / 4);
717 vb[3] = 0;
718
719 vb[4] = i2f(dst_x / 4);
720 vb[5] = i2f(h);
721 vb[6] = i2f(src_x / 4);
722 vb[7] = i2f(h);
723
724 vb[8] = i2f((dst_x + cur_size) / 4);
725 vb[9] = i2f(h);
726 vb[10] = i2f((src_x + cur_size) / 4);
727 vb[11] = i2f(h);
728
729 /* src */
730 set_tex_resource(dev_priv, FMT_8_8_8_8,
731 (src_x + cur_size) / 4,
732 h, (src_x + cur_size) / 4,
733 src_gpu_addr);
734
735 cp_set_surface_sync(dev_priv,
736 R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
737
738 /* dst */
739 set_render_target(dev_priv, COLOR_8_8_8_8,
740 dst_x + cur_size, h,
741 dst_gpu_addr);
742
743 /* scissors */
744 set_scissors(dev_priv, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
745
746 /* Vertex buffer setup */
747 vb_addr = dev_priv->gart_buffers_offset +
748 dev_priv->blit_vb->offset +
749 dev_priv->blit_vb->used;
750 set_vtx_resource(dev_priv, vb_addr);
751
752 /* draw */
753 draw_auto(dev_priv);
754
755 cp_set_surface_sync(dev_priv,
756 R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
757 cur_size * h, dst_gpu_addr);
758
759 vb += 12;
760 dev_priv->blit_vb->used += 12 * 4;
761
762 src_gpu_addr += cur_size * h;
763 dst_gpu_addr += cur_size * h;
764 size_bytes -= cur_size * h;
765 }
766 }
767}
768
769void
770r600_blit_swap(struct drm_device *dev,
771 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
772 int sx, int sy, int dx, int dy,
773 int w, int h, int src_pitch, int dst_pitch, int cpp)
774{
775 drm_radeon_private_t *dev_priv = dev->dev_private;
776 int cb_format, tex_format;
777 u64 vb_addr;
778 u32 *vb;
779
780 vb = r600_nomm_get_vb_ptr(dev);
781
782 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
783
784 r600_nomm_put_vb(dev);
785 r600_nomm_get_vb(dev);
786 if (!dev_priv->blit_vb)
787 return;
788
789 set_shaders(dev);
790 vb = r600_nomm_get_vb_ptr(dev);
791 }
792
793 if (cpp == 4) {
794 cb_format = COLOR_8_8_8_8;
795 tex_format = FMT_8_8_8_8;
796 } else if (cpp == 2) {
797 cb_format = COLOR_5_6_5;
798 tex_format = FMT_5_6_5;
799 } else {
800 cb_format = COLOR_8;
801 tex_format = FMT_8;
802 }
803
804 vb[0] = i2f(dx);
805 vb[1] = i2f(dy);
806 vb[2] = i2f(sx);
807 vb[3] = i2f(sy);
808
809 vb[4] = i2f(dx);
810 vb[5] = i2f(dy + h);
811 vb[6] = i2f(sx);
812 vb[7] = i2f(sy + h);
813
814 vb[8] = i2f(dx + w);
815 vb[9] = i2f(dy + h);
816 vb[10] = i2f(sx + w);
817 vb[11] = i2f(sy + h);
818
819 /* src */
820 set_tex_resource(dev_priv, tex_format,
821 src_pitch / cpp,
822 sy + h, src_pitch / cpp,
823 src_gpu_addr);
824
825 cp_set_surface_sync(dev_priv,
826 R600_TC_ACTION_ENA, (src_pitch * (sy + h)), src_gpu_addr);
827
828 /* dst */
829 set_render_target(dev_priv, cb_format,
830 dst_pitch / cpp, dy + h,
831 dst_gpu_addr);
832
833 /* scissors */
834 set_scissors(dev_priv, dx, dy, dx + w, dy + h);
835
836 /* Vertex buffer setup */
837 vb_addr = dev_priv->gart_buffers_offset +
838 dev_priv->blit_vb->offset +
839 dev_priv->blit_vb->used;
840 set_vtx_resource(dev_priv, vb_addr);
841
842 /* draw */
843 draw_auto(dev_priv);
844
845 cp_set_surface_sync(dev_priv,
846 R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
847 dst_pitch * (dy + h), dst_gpu_addr);
848
849 dev_priv->blit_vb->used += 12 * 4;
850}
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
new file mode 100644
index 000000000000..0a6f4681f468
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -0,0 +1,805 @@
1#include "drmP.h"
2#include "drm.h"
3#include "radeon_drm.h"
4#include "radeon.h"
5
6#include "r600d.h"
7#include "r600_blit_shaders.h"
8
9#define DI_PT_RECTLIST 0x11
10#define DI_INDEX_SIZE_16_BIT 0x0
11#define DI_SRC_SEL_AUTO_INDEX 0x2
12
13#define FMT_8 0x1
14#define FMT_5_6_5 0x8
15#define FMT_8_8_8_8 0x1a
16#define COLOR_8 0x1
17#define COLOR_5_6_5 0x8
18#define COLOR_8_8_8_8 0x1a
19
20/* emits 21 on rv770+, 23 on r600 */
21static void
22set_render_target(struct radeon_device *rdev, int format,
23 int w, int h, u64 gpu_addr)
24{
25 u32 cb_color_info;
26 int pitch, slice;
27
28 h = (h + 7) & ~7;
29 if (h < 8)
30 h = 8;
31
32 cb_color_info = ((format << 2) | (1 << 27));
33 pitch = (w / 8) - 1;
34 slice = ((w * h) / 64) - 1;
35
36 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
37 radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
38 radeon_ring_write(rdev, gpu_addr >> 8);
39
40 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
41 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
42 radeon_ring_write(rdev, 2 << 0);
43 }
44
45 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
46 radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
47 radeon_ring_write(rdev, (pitch << 0) | (slice << 10));
48
49 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
50 radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
51 radeon_ring_write(rdev, 0);
52
53 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
54 radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
55 radeon_ring_write(rdev, cb_color_info);
56
57 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
58 radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
59 radeon_ring_write(rdev, 0);
60
61 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
62 radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
63 radeon_ring_write(rdev, 0);
64
65 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
66 radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
67 radeon_ring_write(rdev, 0);
68}
69
70/* emits 5dw */
71static void
72cp_set_surface_sync(struct radeon_device *rdev,
73 u32 sync_type, u32 size,
74 u64 mc_addr)
75{
76 u32 cp_coher_size;
77
78 if (size == 0xffffffff)
79 cp_coher_size = 0xffffffff;
80 else
81 cp_coher_size = ((size + 255) >> 8);
82
83 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
84 radeon_ring_write(rdev, sync_type);
85 radeon_ring_write(rdev, cp_coher_size);
86 radeon_ring_write(rdev, mc_addr >> 8);
87 radeon_ring_write(rdev, 10); /* poll interval */
88}
89
90/* emits 21dw + 1 surface sync = 26dw */
91static void
92set_shaders(struct radeon_device *rdev)
93{
94 u64 gpu_addr;
95 u32 sq_pgm_resources;
96
97 /* setup shader regs */
98 sq_pgm_resources = (1 << 0);
99
100 /* VS */
101 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
102 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
103 radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
104 radeon_ring_write(rdev, gpu_addr >> 8);
105
106 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
107 radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
108 radeon_ring_write(rdev, sq_pgm_resources);
109
110 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
111 radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
112 radeon_ring_write(rdev, 0);
113
114 /* PS */
115 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
116 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
117 radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
118 radeon_ring_write(rdev, gpu_addr >> 8);
119
120 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
121 radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
122 radeon_ring_write(rdev, sq_pgm_resources | (1 << 28));
123
124 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
125 radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
126 radeon_ring_write(rdev, 2);
127
128 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
129 radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
130 radeon_ring_write(rdev, 0);
131
132 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
133 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
134}
135
136/* emits 9 + 1 sync (5) = 14*/
137static void
138set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
139{
140 u32 sq_vtx_constant_word2;
141
142 sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
143
144 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
145 radeon_ring_write(rdev, 0x460);
146 radeon_ring_write(rdev, gpu_addr & 0xffffffff);
147 radeon_ring_write(rdev, 48 - 1);
148 radeon_ring_write(rdev, sq_vtx_constant_word2);
149 radeon_ring_write(rdev, 1 << 0);
150 radeon_ring_write(rdev, 0);
151 radeon_ring_write(rdev, 0);
152 radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
153
154 if ((rdev->family == CHIP_RV610) ||
155 (rdev->family == CHIP_RV620) ||
156 (rdev->family == CHIP_RS780) ||
157 (rdev->family == CHIP_RS880) ||
158 (rdev->family == CHIP_RV710))
159 cp_set_surface_sync(rdev,
160 PACKET3_TC_ACTION_ENA, 48, gpu_addr);
161 else
162 cp_set_surface_sync(rdev,
163 PACKET3_VC_ACTION_ENA, 48, gpu_addr);
164}
165
166/* emits 9 */
167static void
168set_tex_resource(struct radeon_device *rdev,
169 int format, int w, int h, int pitch,
170 u64 gpu_addr)
171{
172 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
173
174 if (h < 1)
175 h = 1;
176
177 sq_tex_resource_word0 = (1 << 0);
178 sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
179 ((w - 1) << 19));
180
181 sq_tex_resource_word1 = (format << 26);
182 sq_tex_resource_word1 |= ((h - 1) << 0);
183
184 sq_tex_resource_word4 = ((1 << 14) |
185 (0 << 16) |
186 (1 << 19) |
187 (2 << 22) |
188 (3 << 25));
189
190 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
191 radeon_ring_write(rdev, 0);
192 radeon_ring_write(rdev, sq_tex_resource_word0);
193 radeon_ring_write(rdev, sq_tex_resource_word1);
194 radeon_ring_write(rdev, gpu_addr >> 8);
195 radeon_ring_write(rdev, gpu_addr >> 8);
196 radeon_ring_write(rdev, sq_tex_resource_word4);
197 radeon_ring_write(rdev, 0);
198 radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);
199}
200
201/* emits 12 */
202static void
203set_scissors(struct radeon_device *rdev, int x1, int y1,
204 int x2, int y2)
205{
206 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
207 radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
208 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
209 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
210
211 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
212 radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
213 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
214 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
215
216 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
217 radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
218 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
219 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
220}
221
222/* emits 10 */
223static void
224draw_auto(struct radeon_device *rdev)
225{
226 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
227 radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
228 radeon_ring_write(rdev, DI_PT_RECTLIST);
229
230 radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
231 radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT);
232
233 radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
234 radeon_ring_write(rdev, 1);
235
236 radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
237 radeon_ring_write(rdev, 3);
238 radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
239
240}
241
242/* emits 14 */
243static void
244set_default_state(struct radeon_device *rdev)
245{
246 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
247 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
248 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
249 int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
250 int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
251 u64 gpu_addr;
252 int dwords;
253
254 switch (rdev->family) {
255 case CHIP_R600:
256 num_ps_gprs = 192;
257 num_vs_gprs = 56;
258 num_temp_gprs = 4;
259 num_gs_gprs = 0;
260 num_es_gprs = 0;
261 num_ps_threads = 136;
262 num_vs_threads = 48;
263 num_gs_threads = 4;
264 num_es_threads = 4;
265 num_ps_stack_entries = 128;
266 num_vs_stack_entries = 128;
267 num_gs_stack_entries = 0;
268 num_es_stack_entries = 0;
269 break;
270 case CHIP_RV630:
271 case CHIP_RV635:
272 num_ps_gprs = 84;
273 num_vs_gprs = 36;
274 num_temp_gprs = 4;
275 num_gs_gprs = 0;
276 num_es_gprs = 0;
277 num_ps_threads = 144;
278 num_vs_threads = 40;
279 num_gs_threads = 4;
280 num_es_threads = 4;
281 num_ps_stack_entries = 40;
282 num_vs_stack_entries = 40;
283 num_gs_stack_entries = 32;
284 num_es_stack_entries = 16;
285 break;
286 case CHIP_RV610:
287 case CHIP_RV620:
288 case CHIP_RS780:
289 case CHIP_RS880:
290 default:
291 num_ps_gprs = 84;
292 num_vs_gprs = 36;
293 num_temp_gprs = 4;
294 num_gs_gprs = 0;
295 num_es_gprs = 0;
296 num_ps_threads = 136;
297 num_vs_threads = 48;
298 num_gs_threads = 4;
299 num_es_threads = 4;
300 num_ps_stack_entries = 40;
301 num_vs_stack_entries = 40;
302 num_gs_stack_entries = 32;
303 num_es_stack_entries = 16;
304 break;
305 case CHIP_RV670:
306 num_ps_gprs = 144;
307 num_vs_gprs = 40;
308 num_temp_gprs = 4;
309 num_gs_gprs = 0;
310 num_es_gprs = 0;
311 num_ps_threads = 136;
312 num_vs_threads = 48;
313 num_gs_threads = 4;
314 num_es_threads = 4;
315 num_ps_stack_entries = 40;
316 num_vs_stack_entries = 40;
317 num_gs_stack_entries = 32;
318 num_es_stack_entries = 16;
319 break;
320 case CHIP_RV770:
321 num_ps_gprs = 192;
322 num_vs_gprs = 56;
323 num_temp_gprs = 4;
324 num_gs_gprs = 0;
325 num_es_gprs = 0;
326 num_ps_threads = 188;
327 num_vs_threads = 60;
328 num_gs_threads = 0;
329 num_es_threads = 0;
330 num_ps_stack_entries = 256;
331 num_vs_stack_entries = 256;
332 num_gs_stack_entries = 0;
333 num_es_stack_entries = 0;
334 break;
335 case CHIP_RV730:
336 case CHIP_RV740:
337 num_ps_gprs = 84;
338 num_vs_gprs = 36;
339 num_temp_gprs = 4;
340 num_gs_gprs = 0;
341 num_es_gprs = 0;
342 num_ps_threads = 188;
343 num_vs_threads = 60;
344 num_gs_threads = 0;
345 num_es_threads = 0;
346 num_ps_stack_entries = 128;
347 num_vs_stack_entries = 128;
348 num_gs_stack_entries = 0;
349 num_es_stack_entries = 0;
350 break;
351 case CHIP_RV710:
352 num_ps_gprs = 192;
353 num_vs_gprs = 56;
354 num_temp_gprs = 4;
355 num_gs_gprs = 0;
356 num_es_gprs = 0;
357 num_ps_threads = 144;
358 num_vs_threads = 48;
359 num_gs_threads = 0;
360 num_es_threads = 0;
361 num_ps_stack_entries = 128;
362 num_vs_stack_entries = 128;
363 num_gs_stack_entries = 0;
364 num_es_stack_entries = 0;
365 break;
366 }
367
368 if ((rdev->family == CHIP_RV610) ||
369 (rdev->family == CHIP_RV620) ||
370 (rdev->family == CHIP_RS780) ||
371 (rdev->family == CHIP_RS780) ||
372 (rdev->family == CHIP_RV710))
373 sq_config = 0;
374 else
375 sq_config = VC_ENABLE;
376
377 sq_config |= (DX9_CONSTS |
378 ALU_INST_PREFER_VECTOR |
379 PS_PRIO(0) |
380 VS_PRIO(1) |
381 GS_PRIO(2) |
382 ES_PRIO(3));
383
384 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
385 NUM_VS_GPRS(num_vs_gprs) |
386 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
387 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
388 NUM_ES_GPRS(num_es_gprs));
389 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
390 NUM_VS_THREADS(num_vs_threads) |
391 NUM_GS_THREADS(num_gs_threads) |
392 NUM_ES_THREADS(num_es_threads));
393 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
394 NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
395 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
396 NUM_ES_STACK_ENTRIES(num_es_stack_entries));
397
398 /* emit an IB pointing at default state */
399 dwords = (rdev->r600_blit.state_len + 0xf) & ~0xf;
400 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
401 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
402 radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
403 radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
404 radeon_ring_write(rdev, dwords);
405
406 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
407 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
408 /* SQ config */
409 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
410 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
411 radeon_ring_write(rdev, sq_config);
412 radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
413 radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
414 radeon_ring_write(rdev, sq_thread_resource_mgmt);
415 radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
416 radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
417}
418
419static inline uint32_t i2f(uint32_t input)
420{
421 u32 result, i, exponent, fraction;
422
423 if ((input & 0x3fff) == 0)
424 result = 0; /* 0 is a special case */
425 else {
426 exponent = 140; /* exponent biased by 127; */
427 fraction = (input & 0x3fff) << 10; /* cheat and only
428 handle numbers below 2^^15 */
429 for (i = 0; i < 14; i++) {
430 if (fraction & 0x800000)
431 break;
432 else {
433 fraction = fraction << 1; /* keep
434 shifting left until top bit = 1 */
435 exponent = exponent - 1;
436 }
437 }
438 result = exponent << 23 | (fraction & 0x7fffff); /* mask
439 off top bit; assumed 1 */
440 }
441 return result;
442}
443
444int r600_blit_init(struct radeon_device *rdev)
445{
446 u32 obj_size;
447 int r, dwords;
448 void *ptr;
449 u32 packet2s[16];
450 int num_packet2s = 0;
451
452 rdev->r600_blit.state_offset = 0;
453
454 if (rdev->family >= CHIP_RV770)
455 rdev->r600_blit.state_len = r7xx_default_size;
456 else
457 rdev->r600_blit.state_len = r6xx_default_size;
458
459 dwords = rdev->r600_blit.state_len;
460 while (dwords & 0xf) {
461 packet2s[num_packet2s++] = PACKET2(0);
462 dwords++;
463 }
464
465 obj_size = dwords * 4;
466 obj_size = ALIGN(obj_size, 256);
467
468 rdev->r600_blit.vs_offset = obj_size;
469 obj_size += r6xx_vs_size * 4;
470 obj_size = ALIGN(obj_size, 256);
471
472 rdev->r600_blit.ps_offset = obj_size;
473 obj_size += r6xx_ps_size * 4;
474 obj_size = ALIGN(obj_size, 256);
475
476 r = radeon_object_create(rdev, NULL, obj_size,
477 true, RADEON_GEM_DOMAIN_VRAM,
478 false, &rdev->r600_blit.shader_obj);
479 if (r) {
480 DRM_ERROR("r600 failed to allocate shader\n");
481 return r;
482 }
483
484 DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
485 obj_size,
486 rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
487
488 r = radeon_object_kmap(rdev->r600_blit.shader_obj, &ptr);
489 if (r) {
490 DRM_ERROR("failed to map blit object %d\n", r);
491 return r;
492 }
493
494 if (rdev->family >= CHIP_RV770)
495 memcpy_toio(ptr + rdev->r600_blit.state_offset,
496 r7xx_default_state, rdev->r600_blit.state_len * 4);
497 else
498 memcpy_toio(ptr + rdev->r600_blit.state_offset,
499 r6xx_default_state, rdev->r600_blit.state_len * 4);
500 if (num_packet2s)
501 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
502 packet2s, num_packet2s * 4);
503
504
505 memcpy(ptr + rdev->r600_blit.vs_offset, r6xx_vs, r6xx_vs_size * 4);
506 memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4);
507
508 radeon_object_kunmap(rdev->r600_blit.shader_obj);
509 return 0;
510}
511
512void r600_blit_fini(struct radeon_device *rdev)
513{
514 radeon_object_unpin(rdev->r600_blit.shader_obj);
515 radeon_object_unref(&rdev->r600_blit.shader_obj);
516}
517
518int r600_vb_ib_get(struct radeon_device *rdev)
519{
520 int r;
521 r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
522 if (r) {
523 DRM_ERROR("failed to get IB for vertex buffer\n");
524 return r;
525 }
526
527 rdev->r600_blit.vb_total = 64*1024;
528 rdev->r600_blit.vb_used = 0;
529 return 0;
530}
531
532void r600_vb_ib_put(struct radeon_device *rdev)
533{
534 radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
535 mutex_lock(&rdev->ib_pool.mutex);
536 list_add_tail(&rdev->r600_blit.vb_ib->list, &rdev->ib_pool.scheduled_ibs);
537 mutex_unlock(&rdev->ib_pool.mutex);
538 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
539}
540
541int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
542{
543 int r;
544 int ring_size, line_size;
545 int max_size;
546 /* loops of emits 64 + fence emit possible */
547 int dwords_per_loop = 76, num_loops;
548
549 r = r600_vb_ib_get(rdev);
550 WARN_ON(r);
551
552 /* set_render_target emits 2 extra dwords on rv6xx */
553 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
554 dwords_per_loop += 2;
555
556 /* 8 bpp vs 32 bpp for xfer unit */
557 if (size_bytes & 3)
558 line_size = 8192;
559 else
560 line_size = 8192*4;
561
562 max_size = 8192 * line_size;
563
564 /* major loops cover the max size transfer */
565 num_loops = ((size_bytes + max_size) / max_size);
566 /* minor loops cover the extra non aligned bits */
567 num_loops += ((size_bytes % line_size) ? 1 : 0);
568 /* calculate number of loops correctly */
569 ring_size = num_loops * dwords_per_loop;
570 /* set default + shaders */
571 ring_size += 40; /* shaders + def state */
572 ring_size += 3; /* fence emit for VB IB */
573 ring_size += 5; /* done copy */
574 ring_size += 3; /* fence emit for done copy */
575 r = radeon_ring_lock(rdev, ring_size);
576 WARN_ON(r);
577
578 set_default_state(rdev); /* 14 */
579 set_shaders(rdev); /* 26 */
580 return 0;
581}
582
583void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
584{
585 int r;
586
587 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
588 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
589 /* wait for 3D idle clean */
590 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
591 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
592 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
593
594 if (rdev->r600_blit.vb_ib)
595 r600_vb_ib_put(rdev);
596
597 if (fence)
598 r = radeon_fence_emit(rdev, fence);
599
600 radeon_ring_unlock_commit(rdev);
601}
602
603void r600_kms_blit_copy(struct radeon_device *rdev,
604 u64 src_gpu_addr, u64 dst_gpu_addr,
605 int size_bytes)
606{
607 int max_bytes;
608 u64 vb_gpu_addr;
609 u32 *vb;
610
611 DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
612 size_bytes, rdev->r600_blit.vb_used);
613 vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
614 if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
615 max_bytes = 8192;
616
617 while (size_bytes) {
618 int cur_size = size_bytes;
619 int src_x = src_gpu_addr & 255;
620 int dst_x = dst_gpu_addr & 255;
621 int h = 1;
622 src_gpu_addr = src_gpu_addr & ~255;
623 dst_gpu_addr = dst_gpu_addr & ~255;
624
625 if (!src_x && !dst_x) {
626 h = (cur_size / max_bytes);
627 if (h > 8192)
628 h = 8192;
629 if (h == 0)
630 h = 1;
631 else
632 cur_size = max_bytes;
633 } else {
634 if (cur_size > max_bytes)
635 cur_size = max_bytes;
636 if (cur_size > (max_bytes - dst_x))
637 cur_size = (max_bytes - dst_x);
638 if (cur_size > (max_bytes - src_x))
639 cur_size = (max_bytes - src_x);
640 }
641
642 if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
643 WARN_ON(1);
644
645#if 0
646 r600_vb_ib_put(rdev);
647
648 r600_nomm_put_vb(dev);
649 r600_nomm_get_vb(dev);
650 if (!dev_priv->blit_vb)
651 return;
652 set_shaders(dev);
653 vb = r600_nomm_get_vb_ptr(dev);
654#endif
655 }
656
657 vb[0] = i2f(dst_x);
658 vb[1] = 0;
659 vb[2] = i2f(src_x);
660 vb[3] = 0;
661
662 vb[4] = i2f(dst_x);
663 vb[5] = i2f(h);
664 vb[6] = i2f(src_x);
665 vb[7] = i2f(h);
666
667 vb[8] = i2f(dst_x + cur_size);
668 vb[9] = i2f(h);
669 vb[10] = i2f(src_x + cur_size);
670 vb[11] = i2f(h);
671
672 /* src 9 */
673 set_tex_resource(rdev, FMT_8,
674 src_x + cur_size, h, src_x + cur_size,
675 src_gpu_addr);
676
677 /* 5 */
678 cp_set_surface_sync(rdev,
679 PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
680
681 /* dst 23 */
682 set_render_target(rdev, COLOR_8,
683 dst_x + cur_size, h,
684 dst_gpu_addr);
685
686 /* scissors 12 */
687 set_scissors(rdev, dst_x, 0, dst_x + cur_size, h);
688
689 /* 14 */
690 vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
691 set_vtx_resource(rdev, vb_gpu_addr);
692
693 /* draw 10 */
694 draw_auto(rdev);
695
696 /* 5 */
697 cp_set_surface_sync(rdev,
698 PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
699 cur_size * h, dst_gpu_addr);
700
701 vb += 12;
702 rdev->r600_blit.vb_used += 12 * 4;
703
704 src_gpu_addr += cur_size * h;
705 dst_gpu_addr += cur_size * h;
706 size_bytes -= cur_size * h;
707 }
708 } else {
709 max_bytes = 8192 * 4;
710
711 while (size_bytes) {
712 int cur_size = size_bytes;
713 int src_x = (src_gpu_addr & 255);
714 int dst_x = (dst_gpu_addr & 255);
715 int h = 1;
716 src_gpu_addr = src_gpu_addr & ~255;
717 dst_gpu_addr = dst_gpu_addr & ~255;
718
719 if (!src_x && !dst_x) {
720 h = (cur_size / max_bytes);
721 if (h > 8192)
722 h = 8192;
723 if (h == 0)
724 h = 1;
725 else
726 cur_size = max_bytes;
727 } else {
728 if (cur_size > max_bytes)
729 cur_size = max_bytes;
730 if (cur_size > (max_bytes - dst_x))
731 cur_size = (max_bytes - dst_x);
732 if (cur_size > (max_bytes - src_x))
733 cur_size = (max_bytes - src_x);
734 }
735
736 if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
737 WARN_ON(1);
738 }
739#if 0
740 if ((rdev->blit_vb->used + 48) > rdev->blit_vb->total) {
741 r600_nomm_put_vb(dev);
742 r600_nomm_get_vb(dev);
743 if (!rdev->blit_vb)
744 return;
745
746 set_shaders(dev);
747 vb = r600_nomm_get_vb_ptr(dev);
748 }
749#endif
750
751 vb[0] = i2f(dst_x / 4);
752 vb[1] = 0;
753 vb[2] = i2f(src_x / 4);
754 vb[3] = 0;
755
756 vb[4] = i2f(dst_x / 4);
757 vb[5] = i2f(h);
758 vb[6] = i2f(src_x / 4);
759 vb[7] = i2f(h);
760
761 vb[8] = i2f((dst_x + cur_size) / 4);
762 vb[9] = i2f(h);
763 vb[10] = i2f((src_x + cur_size) / 4);
764 vb[11] = i2f(h);
765
766 /* src 9 */
767 set_tex_resource(rdev, FMT_8_8_8_8,
768 (src_x + cur_size) / 4,
769 h, (src_x + cur_size) / 4,
770 src_gpu_addr);
771 /* 5 */
772 cp_set_surface_sync(rdev,
773 PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
774
775 /* dst 23 */
776 set_render_target(rdev, COLOR_8_8_8_8,
777 dst_x + cur_size, h,
778 dst_gpu_addr);
779
780 /* scissors 12 */
781 set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
782
783 /* Vertex buffer setup 14 */
784 vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
785 set_vtx_resource(rdev, vb_gpu_addr);
786
787 /* draw 10 */
788 draw_auto(rdev);
789
790 /* 5 */
791 cp_set_surface_sync(rdev,
792 PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
793 cur_size * h, dst_gpu_addr);
794
795 /* 78 ring dwords per loop */
796 vb += 12;
797 rdev->r600_blit.vb_used += 12 * 4;
798
799 src_gpu_addr += cur_size * h;
800 dst_gpu_addr += cur_size * h;
801 size_bytes -= cur_size * h;
802 }
803 }
804}
805
diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c
new file mode 100644
index 000000000000..d745e815c2e8
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c
@@ -0,0 +1,1072 @@
1
2#include <linux/types.h>
3#include <linux/kernel.h>
4
5const u32 r6xx_default_state[] =
6{
7 0xc0002400,
8 0x00000000,
9 0xc0012800,
10 0x80000000,
11 0x80000000,
12 0xc0004600,
13 0x00000016,
14 0xc0016800,
15 0x00000010,
16 0x00028000,
17 0xc0016800,
18 0x00000010,
19 0x00008000,
20 0xc0016800,
21 0x00000542,
22 0x07000003,
23 0xc0016800,
24 0x000005c5,
25 0x00000000,
26 0xc0016800,
27 0x00000363,
28 0x00000000,
29 0xc0016800,
30 0x0000060c,
31 0x82000000,
32 0xc0016800,
33 0x0000060e,
34 0x01020204,
35 0xc0016f00,
36 0x00000000,
37 0x00000000,
38 0xc0016f00,
39 0x00000001,
40 0x00000000,
41 0xc0096900,
42 0x0000022a,
43 0x00000000,
44 0x00000000,
45 0x00000000,
46 0x00000000,
47 0x00000000,
48 0x00000000,
49 0x00000000,
50 0x00000000,
51 0x00000000,
52 0xc0016900,
53 0x00000004,
54 0x00000000,
55 0xc0016900,
56 0x0000000a,
57 0x00000000,
58 0xc0016900,
59 0x0000000b,
60 0x00000000,
61 0xc0016900,
62 0x0000010c,
63 0x00000000,
64 0xc0016900,
65 0x0000010d,
66 0x00000000,
67 0xc0016900,
68 0x00000200,
69 0x00000000,
70 0xc0016900,
71 0x00000343,
72 0x00000060,
73 0xc0016900,
74 0x00000344,
75 0x00000040,
76 0xc0016900,
77 0x00000351,
78 0x0000aa00,
79 0xc0016900,
80 0x00000104,
81 0x00000000,
82 0xc0016900,
83 0x0000010e,
84 0x00000000,
85 0xc0046900,
86 0x00000105,
87 0x00000000,
88 0x00000000,
89 0x00000000,
90 0x00000000,
91 0xc0036900,
92 0x00000109,
93 0x00000000,
94 0x00000000,
95 0x00000000,
96 0xc0046900,
97 0x0000030c,
98 0x01000000,
99 0x00000000,
100 0x00000000,
101 0x00000000,
102 0xc0046900,
103 0x00000048,
104 0x3f800000,
105 0x00000000,
106 0x3f800000,
107 0x3f800000,
108 0xc0016900,
109 0x0000008e,
110 0x0000000f,
111 0xc0016900,
112 0x00000080,
113 0x00000000,
114 0xc0016900,
115 0x00000083,
116 0x0000ffff,
117 0xc0016900,
118 0x00000084,
119 0x00000000,
120 0xc0016900,
121 0x00000085,
122 0x20002000,
123 0xc0016900,
124 0x00000086,
125 0x00000000,
126 0xc0016900,
127 0x00000087,
128 0x20002000,
129 0xc0016900,
130 0x00000088,
131 0x00000000,
132 0xc0016900,
133 0x00000089,
134 0x20002000,
135 0xc0016900,
136 0x0000008a,
137 0x00000000,
138 0xc0016900,
139 0x0000008b,
140 0x20002000,
141 0xc0016900,
142 0x0000008c,
143 0x00000000,
144 0xc0016900,
145 0x00000094,
146 0x80000000,
147 0xc0016900,
148 0x00000095,
149 0x20002000,
150 0xc0026900,
151 0x000000b4,
152 0x00000000,
153 0x3f800000,
154 0xc0016900,
155 0x00000096,
156 0x80000000,
157 0xc0016900,
158 0x00000097,
159 0x20002000,
160 0xc0026900,
161 0x000000b6,
162 0x00000000,
163 0x3f800000,
164 0xc0016900,
165 0x00000098,
166 0x80000000,
167 0xc0016900,
168 0x00000099,
169 0x20002000,
170 0xc0026900,
171 0x000000b8,
172 0x00000000,
173 0x3f800000,
174 0xc0016900,
175 0x0000009a,
176 0x80000000,
177 0xc0016900,
178 0x0000009b,
179 0x20002000,
180 0xc0026900,
181 0x000000ba,
182 0x00000000,
183 0x3f800000,
184 0xc0016900,
185 0x0000009c,
186 0x80000000,
187 0xc0016900,
188 0x0000009d,
189 0x20002000,
190 0xc0026900,
191 0x000000bc,
192 0x00000000,
193 0x3f800000,
194 0xc0016900,
195 0x0000009e,
196 0x80000000,
197 0xc0016900,
198 0x0000009f,
199 0x20002000,
200 0xc0026900,
201 0x000000be,
202 0x00000000,
203 0x3f800000,
204 0xc0016900,
205 0x000000a0,
206 0x80000000,
207 0xc0016900,
208 0x000000a1,
209 0x20002000,
210 0xc0026900,
211 0x000000c0,
212 0x00000000,
213 0x3f800000,
214 0xc0016900,
215 0x000000a2,
216 0x80000000,
217 0xc0016900,
218 0x000000a3,
219 0x20002000,
220 0xc0026900,
221 0x000000c2,
222 0x00000000,
223 0x3f800000,
224 0xc0016900,
225 0x000000a4,
226 0x80000000,
227 0xc0016900,
228 0x000000a5,
229 0x20002000,
230 0xc0026900,
231 0x000000c4,
232 0x00000000,
233 0x3f800000,
234 0xc0016900,
235 0x000000a6,
236 0x80000000,
237 0xc0016900,
238 0x000000a7,
239 0x20002000,
240 0xc0026900,
241 0x000000c6,
242 0x00000000,
243 0x3f800000,
244 0xc0016900,
245 0x000000a8,
246 0x80000000,
247 0xc0016900,
248 0x000000a9,
249 0x20002000,
250 0xc0026900,
251 0x000000c8,
252 0x00000000,
253 0x3f800000,
254 0xc0016900,
255 0x000000aa,
256 0x80000000,
257 0xc0016900,
258 0x000000ab,
259 0x20002000,
260 0xc0026900,
261 0x000000ca,
262 0x00000000,
263 0x3f800000,
264 0xc0016900,
265 0x000000ac,
266 0x80000000,
267 0xc0016900,
268 0x000000ad,
269 0x20002000,
270 0xc0026900,
271 0x000000cc,
272 0x00000000,
273 0x3f800000,
274 0xc0016900,
275 0x000000ae,
276 0x80000000,
277 0xc0016900,
278 0x000000af,
279 0x20002000,
280 0xc0026900,
281 0x000000ce,
282 0x00000000,
283 0x3f800000,
284 0xc0016900,
285 0x000000b0,
286 0x80000000,
287 0xc0016900,
288 0x000000b1,
289 0x20002000,
290 0xc0026900,
291 0x000000d0,
292 0x00000000,
293 0x3f800000,
294 0xc0016900,
295 0x000000b2,
296 0x80000000,
297 0xc0016900,
298 0x000000b3,
299 0x20002000,
300 0xc0026900,
301 0x000000d2,
302 0x00000000,
303 0x3f800000,
304 0xc0016900,
305 0x00000293,
306 0x00004010,
307 0xc0016900,
308 0x00000300,
309 0x00000000,
310 0xc0016900,
311 0x00000301,
312 0x00000000,
313 0xc0016900,
314 0x00000312,
315 0xffffffff,
316 0xc0016900,
317 0x00000307,
318 0x00000000,
319 0xc0016900,
320 0x00000308,
321 0x00000000,
322 0xc0016900,
323 0x00000283,
324 0x00000000,
325 0xc0016900,
326 0x00000292,
327 0x00000000,
328 0xc0066900,
329 0x0000010f,
330 0x00000000,
331 0x00000000,
332 0x00000000,
333 0x00000000,
334 0x00000000,
335 0x00000000,
336 0xc0016900,
337 0x00000206,
338 0x00000000,
339 0xc0016900,
340 0x00000207,
341 0x00000000,
342 0xc0016900,
343 0x00000208,
344 0x00000000,
345 0xc0046900,
346 0x00000303,
347 0x3f800000,
348 0x3f800000,
349 0x3f800000,
350 0x3f800000,
351 0xc0016900,
352 0x00000205,
353 0x00000004,
354 0xc0016900,
355 0x00000280,
356 0x00000000,
357 0xc0016900,
358 0x00000281,
359 0x00000000,
360 0xc0016900,
361 0x0000037e,
362 0x00000000,
363 0xc0016900,
364 0x00000382,
365 0x00000000,
366 0xc0016900,
367 0x00000380,
368 0x00000000,
369 0xc0016900,
370 0x00000383,
371 0x00000000,
372 0xc0016900,
373 0x00000381,
374 0x00000000,
375 0xc0016900,
376 0x00000282,
377 0x00000008,
378 0xc0016900,
379 0x00000302,
380 0x0000002d,
381 0xc0016900,
382 0x0000037f,
383 0x00000000,
384 0xc0016900,
385 0x000001b2,
386 0x00000000,
387 0xc0016900,
388 0x000001b6,
389 0x00000000,
390 0xc0016900,
391 0x000001b7,
392 0x00000000,
393 0xc0016900,
394 0x000001b8,
395 0x00000000,
396 0xc0016900,
397 0x000001b9,
398 0x00000000,
399 0xc0016900,
400 0x00000225,
401 0x00000000,
402 0xc0016900,
403 0x00000229,
404 0x00000000,
405 0xc0016900,
406 0x00000237,
407 0x00000000,
408 0xc0016900,
409 0x00000100,
410 0x00000800,
411 0xc0016900,
412 0x00000101,
413 0x00000000,
414 0xc0016900,
415 0x00000102,
416 0x00000000,
417 0xc0016900,
418 0x000002a8,
419 0x00000000,
420 0xc0016900,
421 0x000002a9,
422 0x00000000,
423 0xc0016900,
424 0x00000103,
425 0x00000000,
426 0xc0016900,
427 0x00000284,
428 0x00000000,
429 0xc0016900,
430 0x00000290,
431 0x00000000,
432 0xc0016900,
433 0x00000285,
434 0x00000000,
435 0xc0016900,
436 0x00000286,
437 0x00000000,
438 0xc0016900,
439 0x00000287,
440 0x00000000,
441 0xc0016900,
442 0x00000288,
443 0x00000000,
444 0xc0016900,
445 0x00000289,
446 0x00000000,
447 0xc0016900,
448 0x0000028a,
449 0x00000000,
450 0xc0016900,
451 0x0000028b,
452 0x00000000,
453 0xc0016900,
454 0x0000028c,
455 0x00000000,
456 0xc0016900,
457 0x0000028d,
458 0x00000000,
459 0xc0016900,
460 0x0000028e,
461 0x00000000,
462 0xc0016900,
463 0x0000028f,
464 0x00000000,
465 0xc0016900,
466 0x000002a1,
467 0x00000000,
468 0xc0016900,
469 0x000002a5,
470 0x00000000,
471 0xc0016900,
472 0x000002ac,
473 0x00000000,
474 0xc0016900,
475 0x000002ad,
476 0x00000000,
477 0xc0016900,
478 0x000002ae,
479 0x00000000,
480 0xc0016900,
481 0x000002c8,
482 0x00000000,
483 0xc0016900,
484 0x00000206,
485 0x00000100,
486 0xc0016900,
487 0x00000204,
488 0x00010000,
489 0xc0036e00,
490 0x00000000,
491 0x00000012,
492 0x00000000,
493 0x00000000,
494 0xc0016900,
495 0x0000008f,
496 0x0000000f,
497 0xc0016900,
498 0x000001e8,
499 0x00000001,
500 0xc0016900,
501 0x00000202,
502 0x00cc0000,
503 0xc0016900,
504 0x00000205,
505 0x00000244,
506 0xc0016900,
507 0x00000203,
508 0x00000210,
509 0xc0016900,
510 0x000001b1,
511 0x00000000,
512 0xc0016900,
513 0x00000185,
514 0x00000000,
515 0xc0016900,
516 0x000001b3,
517 0x00000001,
518 0xc0016900,
519 0x000001b4,
520 0x00000000,
521 0xc0016900,
522 0x00000191,
523 0x00000b00,
524 0xc0016900,
525 0x000001b5,
526 0x00000000,
527};
528
529const u32 r7xx_default_state[] =
530{
531 0xc0012800,
532 0x80000000,
533 0x80000000,
534 0xc0004600,
535 0x00000016,
536 0xc0016800,
537 0x00000010,
538 0x00028000,
539 0xc0016800,
540 0x00000010,
541 0x00008000,
542 0xc0016800,
543 0x00000542,
544 0x07000002,
545 0xc0016800,
546 0x000005c5,
547 0x00000000,
548 0xc0016800,
549 0x00000363,
550 0x00004000,
551 0xc0016800,
552 0x0000060c,
553 0x00000000,
554 0xc0016800,
555 0x0000060e,
556 0x00420204,
557 0xc0016f00,
558 0x00000000,
559 0x00000000,
560 0xc0016f00,
561 0x00000001,
562 0x00000000,
563 0xc0096900,
564 0x0000022a,
565 0x00000000,
566 0x00000000,
567 0x00000000,
568 0x00000000,
569 0x00000000,
570 0x00000000,
571 0x00000000,
572 0x00000000,
573 0x00000000,
574 0xc0016900,
575 0x00000004,
576 0x00000000,
577 0xc0016900,
578 0x0000000a,
579 0x00000000,
580 0xc0016900,
581 0x0000000b,
582 0x00000000,
583 0xc0016900,
584 0x0000010c,
585 0x00000000,
586 0xc0016900,
587 0x0000010d,
588 0x00000000,
589 0xc0016900,
590 0x00000200,
591 0x00000000,
592 0xc0016900,
593 0x00000343,
594 0x00000060,
595 0xc0016900,
596 0x00000344,
597 0x00000000,
598 0xc0016900,
599 0x00000351,
600 0x0000aa00,
601 0xc0016900,
602 0x00000104,
603 0x00000000,
604 0xc0016900,
605 0x0000010e,
606 0x00000000,
607 0xc0046900,
608 0x00000105,
609 0x00000000,
610 0x00000000,
611 0x00000000,
612 0x00000000,
613 0xc0046900,
614 0x0000030c,
615 0x01000000,
616 0x00000000,
617 0x00000000,
618 0x00000000,
619 0xc0016900,
620 0x0000008e,
621 0x0000000f,
622 0xc0016900,
623 0x00000080,
624 0x00000000,
625 0xc0016900,
626 0x00000083,
627 0x0000ffff,
628 0xc0016900,
629 0x00000084,
630 0x00000000,
631 0xc0016900,
632 0x00000085,
633 0x20002000,
634 0xc0016900,
635 0x00000086,
636 0x00000000,
637 0xc0016900,
638 0x00000087,
639 0x20002000,
640 0xc0016900,
641 0x00000088,
642 0x00000000,
643 0xc0016900,
644 0x00000089,
645 0x20002000,
646 0xc0016900,
647 0x0000008a,
648 0x00000000,
649 0xc0016900,
650 0x0000008b,
651 0x20002000,
652 0xc0016900,
653 0x0000008c,
654 0xaaaaaaaa,
655 0xc0016900,
656 0x00000094,
657 0x80000000,
658 0xc0016900,
659 0x00000095,
660 0x20002000,
661 0xc0026900,
662 0x000000b4,
663 0x00000000,
664 0x3f800000,
665 0xc0016900,
666 0x00000096,
667 0x80000000,
668 0xc0016900,
669 0x00000097,
670 0x20002000,
671 0xc0026900,
672 0x000000b6,
673 0x00000000,
674 0x3f800000,
675 0xc0016900,
676 0x00000098,
677 0x80000000,
678 0xc0016900,
679 0x00000099,
680 0x20002000,
681 0xc0026900,
682 0x000000b8,
683 0x00000000,
684 0x3f800000,
685 0xc0016900,
686 0x0000009a,
687 0x80000000,
688 0xc0016900,
689 0x0000009b,
690 0x20002000,
691 0xc0026900,
692 0x000000ba,
693 0x00000000,
694 0x3f800000,
695 0xc0016900,
696 0x0000009c,
697 0x80000000,
698 0xc0016900,
699 0x0000009d,
700 0x20002000,
701 0xc0026900,
702 0x000000bc,
703 0x00000000,
704 0x3f800000,
705 0xc0016900,
706 0x0000009e,
707 0x80000000,
708 0xc0016900,
709 0x0000009f,
710 0x20002000,
711 0xc0026900,
712 0x000000be,
713 0x00000000,
714 0x3f800000,
715 0xc0016900,
716 0x000000a0,
717 0x80000000,
718 0xc0016900,
719 0x000000a1,
720 0x20002000,
721 0xc0026900,
722 0x000000c0,
723 0x00000000,
724 0x3f800000,
725 0xc0016900,
726 0x000000a2,
727 0x80000000,
728 0xc0016900,
729 0x000000a3,
730 0x20002000,
731 0xc0026900,
732 0x000000c2,
733 0x00000000,
734 0x3f800000,
735 0xc0016900,
736 0x000000a4,
737 0x80000000,
738 0xc0016900,
739 0x000000a5,
740 0x20002000,
741 0xc0026900,
742 0x000000c4,
743 0x00000000,
744 0x3f800000,
745 0xc0016900,
746 0x000000a6,
747 0x80000000,
748 0xc0016900,
749 0x000000a7,
750 0x20002000,
751 0xc0026900,
752 0x000000c6,
753 0x00000000,
754 0x3f800000,
755 0xc0016900,
756 0x000000a8,
757 0x80000000,
758 0xc0016900,
759 0x000000a9,
760 0x20002000,
761 0xc0026900,
762 0x000000c8,
763 0x00000000,
764 0x3f800000,
765 0xc0016900,
766 0x000000aa,
767 0x80000000,
768 0xc0016900,
769 0x000000ab,
770 0x20002000,
771 0xc0026900,
772 0x000000ca,
773 0x00000000,
774 0x3f800000,
775 0xc0016900,
776 0x000000ac,
777 0x80000000,
778 0xc0016900,
779 0x000000ad,
780 0x20002000,
781 0xc0026900,
782 0x000000cc,
783 0x00000000,
784 0x3f800000,
785 0xc0016900,
786 0x000000ae,
787 0x80000000,
788 0xc0016900,
789 0x000000af,
790 0x20002000,
791 0xc0026900,
792 0x000000ce,
793 0x00000000,
794 0x3f800000,
795 0xc0016900,
796 0x000000b0,
797 0x80000000,
798 0xc0016900,
799 0x000000b1,
800 0x20002000,
801 0xc0026900,
802 0x000000d0,
803 0x00000000,
804 0x3f800000,
805 0xc0016900,
806 0x000000b2,
807 0x80000000,
808 0xc0016900,
809 0x000000b3,
810 0x20002000,
811 0xc0026900,
812 0x000000d2,
813 0x00000000,
814 0x3f800000,
815 0xc0016900,
816 0x00000293,
817 0x00514000,
818 0xc0016900,
819 0x00000300,
820 0x00000000,
821 0xc0016900,
822 0x00000301,
823 0x00000000,
824 0xc0016900,
825 0x00000312,
826 0xffffffff,
827 0xc0016900,
828 0x00000307,
829 0x00000000,
830 0xc0016900,
831 0x00000308,
832 0x00000000,
833 0xc0016900,
834 0x00000283,
835 0x00000000,
836 0xc0016900,
837 0x00000292,
838 0x00000000,
839 0xc0066900,
840 0x0000010f,
841 0x00000000,
842 0x00000000,
843 0x00000000,
844 0x00000000,
845 0x00000000,
846 0x00000000,
847 0xc0016900,
848 0x00000206,
849 0x00000000,
850 0xc0016900,
851 0x00000207,
852 0x00000000,
853 0xc0016900,
854 0x00000208,
855 0x00000000,
856 0xc0046900,
857 0x00000303,
858 0x3f800000,
859 0x3f800000,
860 0x3f800000,
861 0x3f800000,
862 0xc0016900,
863 0x00000205,
864 0x00000004,
865 0xc0016900,
866 0x00000280,
867 0x00000000,
868 0xc0016900,
869 0x00000281,
870 0x00000000,
871 0xc0016900,
872 0x0000037e,
873 0x00000000,
874 0xc0016900,
875 0x00000382,
876 0x00000000,
877 0xc0016900,
878 0x00000380,
879 0x00000000,
880 0xc0016900,
881 0x00000383,
882 0x00000000,
883 0xc0016900,
884 0x00000381,
885 0x00000000,
886 0xc0016900,
887 0x00000282,
888 0x00000008,
889 0xc0016900,
890 0x00000302,
891 0x0000002d,
892 0xc0016900,
893 0x0000037f,
894 0x00000000,
895 0xc0016900,
896 0x000001b2,
897 0x00000001,
898 0xc0016900,
899 0x000001b6,
900 0x00000000,
901 0xc0016900,
902 0x000001b7,
903 0x00000000,
904 0xc0016900,
905 0x000001b8,
906 0x00000000,
907 0xc0016900,
908 0x000001b9,
909 0x00000000,
910 0xc0016900,
911 0x00000225,
912 0x00000000,
913 0xc0016900,
914 0x00000229,
915 0x00000000,
916 0xc0016900,
917 0x00000237,
918 0x00000000,
919 0xc0016900,
920 0x00000100,
921 0x00000800,
922 0xc0016900,
923 0x00000101,
924 0x00000000,
925 0xc0016900,
926 0x00000102,
927 0x00000000,
928 0xc0016900,
929 0x000002a8,
930 0x00000000,
931 0xc0016900,
932 0x000002a9,
933 0x00000000,
934 0xc0016900,
935 0x00000103,
936 0x00000000,
937 0xc0016900,
938 0x00000284,
939 0x00000000,
940 0xc0016900,
941 0x00000290,
942 0x00000000,
943 0xc0016900,
944 0x00000285,
945 0x00000000,
946 0xc0016900,
947 0x00000286,
948 0x00000000,
949 0xc0016900,
950 0x00000287,
951 0x00000000,
952 0xc0016900,
953 0x00000288,
954 0x00000000,
955 0xc0016900,
956 0x00000289,
957 0x00000000,
958 0xc0016900,
959 0x0000028a,
960 0x00000000,
961 0xc0016900,
962 0x0000028b,
963 0x00000000,
964 0xc0016900,
965 0x0000028c,
966 0x00000000,
967 0xc0016900,
968 0x0000028d,
969 0x00000000,
970 0xc0016900,
971 0x0000028e,
972 0x00000000,
973 0xc0016900,
974 0x0000028f,
975 0x00000000,
976 0xc0016900,
977 0x000002a1,
978 0x00000000,
979 0xc0016900,
980 0x000002a5,
981 0x00000000,
982 0xc0016900,
983 0x000002ac,
984 0x00000000,
985 0xc0016900,
986 0x000002ad,
987 0x00000000,
988 0xc0016900,
989 0x000002ae,
990 0x00000000,
991 0xc0016900,
992 0x000002c8,
993 0x00000000,
994 0xc0016900,
995 0x00000206,
996 0x00000100,
997 0xc0016900,
998 0x00000204,
999 0x00010000,
1000 0xc0036e00,
1001 0x00000000,
1002 0x00000012,
1003 0x00000000,
1004 0x00000000,
1005 0xc0016900,
1006 0x0000008f,
1007 0x0000000f,
1008 0xc0016900,
1009 0x000001e8,
1010 0x00000001,
1011 0xc0016900,
1012 0x00000202,
1013 0x00cc0000,
1014 0xc0016900,
1015 0x00000205,
1016 0x00000244,
1017 0xc0016900,
1018 0x00000203,
1019 0x00000210,
1020 0xc0016900,
1021 0x000001b1,
1022 0x00000000,
1023 0xc0016900,
1024 0x00000185,
1025 0x00000000,
1026 0xc0016900,
1027 0x000001b3,
1028 0x00000001,
1029 0xc0016900,
1030 0x000001b4,
1031 0x00000000,
1032 0xc0016900,
1033 0x00000191,
1034 0x00000b00,
1035 0xc0016900,
1036 0x000001b5,
1037 0x00000000,
1038};
1039
1040/* same for r6xx/r7xx */
1041const u32 r6xx_vs[] =
1042{
1043 0x00000004,
1044 0x81000000,
1045 0x0000203c,
1046 0x94000b08,
1047 0x00004000,
1048 0x14200b1a,
1049 0x00000000,
1050 0x00000000,
1051 0x3c000000,
1052 0x68cd1000,
1053 0x00080000,
1054 0x00000000,
1055};
1056
1057const u32 r6xx_ps[] =
1058{
1059 0x00000002,
1060 0x80800000,
1061 0x00000000,
1062 0x94200688,
1063 0x00000010,
1064 0x000d1000,
1065 0xb0800000,
1066 0x00000000,
1067};
1068
1069const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps);
1070const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs);
1071const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state);
1072const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);
diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.h b/drivers/gpu/drm/radeon/r600_blit_shaders.h
new file mode 100644
index 000000000000..fdc3b378cbb0
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_blit_shaders.h
@@ -0,0 +1,14 @@
1
2#ifndef R600_BLIT_SHADERS_H
3#define R600_BLIT_SHADERS_H
4
5extern const u32 r6xx_ps[];
6extern const u32 r6xx_vs[];
7extern const u32 r7xx_default_state[];
8extern const u32 r6xx_default_state[];
9
10
11extern const u32 r6xx_ps_size, r6xx_vs_size;
12extern const u32 r6xx_default_size, r7xx_default_size;
13
14#endif
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index 20f17908b036..6d5a711c2e91 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -31,7 +31,38 @@
31#include "radeon_drm.h" 31#include "radeon_drm.h"
32#include "radeon_drv.h" 32#include "radeon_drv.h"
33 33
34#include "r600_microcode.h" 34#define PFP_UCODE_SIZE 576
35#define PM4_UCODE_SIZE 1792
36#define R700_PFP_UCODE_SIZE 848
37#define R700_PM4_UCODE_SIZE 1360
38
39/* Firmware Names */
40MODULE_FIRMWARE("radeon/R600_pfp.bin");
41MODULE_FIRMWARE("radeon/R600_me.bin");
42MODULE_FIRMWARE("radeon/RV610_pfp.bin");
43MODULE_FIRMWARE("radeon/RV610_me.bin");
44MODULE_FIRMWARE("radeon/RV630_pfp.bin");
45MODULE_FIRMWARE("radeon/RV630_me.bin");
46MODULE_FIRMWARE("radeon/RV620_pfp.bin");
47MODULE_FIRMWARE("radeon/RV620_me.bin");
48MODULE_FIRMWARE("radeon/RV635_pfp.bin");
49MODULE_FIRMWARE("radeon/RV635_me.bin");
50MODULE_FIRMWARE("radeon/RV670_pfp.bin");
51MODULE_FIRMWARE("radeon/RV670_me.bin");
52MODULE_FIRMWARE("radeon/RS780_pfp.bin");
53MODULE_FIRMWARE("radeon/RS780_me.bin");
54MODULE_FIRMWARE("radeon/RV770_pfp.bin");
55MODULE_FIRMWARE("radeon/RV770_me.bin");
56MODULE_FIRMWARE("radeon/RV730_pfp.bin");
57MODULE_FIRMWARE("radeon/RV730_me.bin");
58MODULE_FIRMWARE("radeon/RV710_pfp.bin");
59MODULE_FIRMWARE("radeon/RV710_me.bin");
60
61
62int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
63 unsigned family, u32 *ib, int *l);
64void r600_cs_legacy_init(void);
65
35 66
36# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ 67# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
37# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) 68# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
@@ -275,11 +306,93 @@ static void r600_vm_init(struct drm_device *dev)
275 r600_vm_flush_gart_range(dev); 306 r600_vm_flush_gart_range(dev);
276} 307}
277 308
278/* load r600 microcode */ 309static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv)
310{
311 struct platform_device *pdev;
312 const char *chip_name;
313 size_t pfp_req_size, me_req_size;
314 char fw_name[30];
315 int err;
316
317 pdev = platform_device_register_simple("r600_cp", 0, NULL, 0);
318 err = IS_ERR(pdev);
319 if (err) {
320 printk(KERN_ERR "r600_cp: Failed to register firmware\n");
321 return -EINVAL;
322 }
323
324 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
325 case CHIP_R600: chip_name = "R600"; break;
326 case CHIP_RV610: chip_name = "RV610"; break;
327 case CHIP_RV630: chip_name = "RV630"; break;
328 case CHIP_RV620: chip_name = "RV620"; break;
329 case CHIP_RV635: chip_name = "RV635"; break;
330 case CHIP_RV670: chip_name = "RV670"; break;
331 case CHIP_RS780:
332 case CHIP_RS880: chip_name = "RS780"; break;
333 case CHIP_RV770: chip_name = "RV770"; break;
334 case CHIP_RV730:
335 case CHIP_RV740: chip_name = "RV730"; break;
336 case CHIP_RV710: chip_name = "RV710"; break;
337 default: BUG();
338 }
339
340 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
341 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
342 me_req_size = R700_PM4_UCODE_SIZE * 4;
343 } else {
344 pfp_req_size = PFP_UCODE_SIZE * 4;
345 me_req_size = PM4_UCODE_SIZE * 12;
346 }
347
348 DRM_INFO("Loading %s CP Microcode\n", chip_name);
349
350 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
351 err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev);
352 if (err)
353 goto out;
354 if (dev_priv->pfp_fw->size != pfp_req_size) {
355 printk(KERN_ERR
356 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
357 dev_priv->pfp_fw->size, fw_name);
358 err = -EINVAL;
359 goto out;
360 }
361
362 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
363 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
364 if (err)
365 goto out;
366 if (dev_priv->me_fw->size != me_req_size) {
367 printk(KERN_ERR
368 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
369 dev_priv->me_fw->size, fw_name);
370 err = -EINVAL;
371 }
372out:
373 platform_device_unregister(pdev);
374
375 if (err) {
376 if (err != -EINVAL)
377 printk(KERN_ERR
378 "r600_cp: Failed to load firmware \"%s\"\n",
379 fw_name);
380 release_firmware(dev_priv->pfp_fw);
381 dev_priv->pfp_fw = NULL;
382 release_firmware(dev_priv->me_fw);
383 dev_priv->me_fw = NULL;
384 }
385 return err;
386}
387
279static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) 388static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
280{ 389{
390 const __be32 *fw_data;
281 int i; 391 int i;
282 392
393 if (!dev_priv->me_fw || !dev_priv->pfp_fw)
394 return;
395
283 r600_do_cp_stop(dev_priv); 396 r600_do_cp_stop(dev_priv);
284 397
285 RADEON_WRITE(R600_CP_RB_CNTL, 398 RADEON_WRITE(R600_CP_RB_CNTL,
@@ -292,115 +405,18 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
292 DRM_UDELAY(15000); 405 DRM_UDELAY(15000);
293 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 406 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
294 407
408 fw_data = (const __be32 *)dev_priv->me_fw->data;
295 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 409 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
410 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
411 RADEON_WRITE(R600_CP_ME_RAM_DATA,
412 be32_to_cpup(fw_data++));
296 413
297 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600)) { 414 fw_data = (const __be32 *)dev_priv->pfp_fw->data;
298 DRM_INFO("Loading R600 CP Microcode\n"); 415 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
299 for (i = 0; i < PM4_UCODE_SIZE; i++) { 416 for (i = 0; i < PFP_UCODE_SIZE; i++)
300 RADEON_WRITE(R600_CP_ME_RAM_DATA, 417 RADEON_WRITE(R600_CP_PFP_UCODE_DATA,
301 R600_cp_microcode[i][0]); 418 be32_to_cpup(fw_data++));
302 RADEON_WRITE(R600_CP_ME_RAM_DATA,
303 R600_cp_microcode[i][1]);
304 RADEON_WRITE(R600_CP_ME_RAM_DATA,
305 R600_cp_microcode[i][2]);
306 }
307
308 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
309 DRM_INFO("Loading R600 PFP Microcode\n");
310 for (i = 0; i < PFP_UCODE_SIZE; i++)
311 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, R600_pfp_microcode[i]);
312 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610)) {
313 DRM_INFO("Loading RV610 CP Microcode\n");
314 for (i = 0; i < PM4_UCODE_SIZE; i++) {
315 RADEON_WRITE(R600_CP_ME_RAM_DATA,
316 RV610_cp_microcode[i][0]);
317 RADEON_WRITE(R600_CP_ME_RAM_DATA,
318 RV610_cp_microcode[i][1]);
319 RADEON_WRITE(R600_CP_ME_RAM_DATA,
320 RV610_cp_microcode[i][2]);
321 }
322
323 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
324 DRM_INFO("Loading RV610 PFP Microcode\n");
325 for (i = 0; i < PFP_UCODE_SIZE; i++)
326 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV610_pfp_microcode[i]);
327 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
328 DRM_INFO("Loading RV630 CP Microcode\n");
329 for (i = 0; i < PM4_UCODE_SIZE; i++) {
330 RADEON_WRITE(R600_CP_ME_RAM_DATA,
331 RV630_cp_microcode[i][0]);
332 RADEON_WRITE(R600_CP_ME_RAM_DATA,
333 RV630_cp_microcode[i][1]);
334 RADEON_WRITE(R600_CP_ME_RAM_DATA,
335 RV630_cp_microcode[i][2]);
336 }
337
338 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
339 DRM_INFO("Loading RV630 PFP Microcode\n");
340 for (i = 0; i < PFP_UCODE_SIZE; i++)
341 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV630_pfp_microcode[i]);
342 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620)) {
343 DRM_INFO("Loading RV620 CP Microcode\n");
344 for (i = 0; i < PM4_UCODE_SIZE; i++) {
345 RADEON_WRITE(R600_CP_ME_RAM_DATA,
346 RV620_cp_microcode[i][0]);
347 RADEON_WRITE(R600_CP_ME_RAM_DATA,
348 RV620_cp_microcode[i][1]);
349 RADEON_WRITE(R600_CP_ME_RAM_DATA,
350 RV620_cp_microcode[i][2]);
351 }
352
353 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
354 DRM_INFO("Loading RV620 PFP Microcode\n");
355 for (i = 0; i < PFP_UCODE_SIZE; i++)
356 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV620_pfp_microcode[i]);
357 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
358 DRM_INFO("Loading RV635 CP Microcode\n");
359 for (i = 0; i < PM4_UCODE_SIZE; i++) {
360 RADEON_WRITE(R600_CP_ME_RAM_DATA,
361 RV635_cp_microcode[i][0]);
362 RADEON_WRITE(R600_CP_ME_RAM_DATA,
363 RV635_cp_microcode[i][1]);
364 RADEON_WRITE(R600_CP_ME_RAM_DATA,
365 RV635_cp_microcode[i][2]);
366 }
367
368 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
369 DRM_INFO("Loading RV635 PFP Microcode\n");
370 for (i = 0; i < PFP_UCODE_SIZE; i++)
371 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV635_pfp_microcode[i]);
372 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)) {
373 DRM_INFO("Loading RV670 CP Microcode\n");
374 for (i = 0; i < PM4_UCODE_SIZE; i++) {
375 RADEON_WRITE(R600_CP_ME_RAM_DATA,
376 RV670_cp_microcode[i][0]);
377 RADEON_WRITE(R600_CP_ME_RAM_DATA,
378 RV670_cp_microcode[i][1]);
379 RADEON_WRITE(R600_CP_ME_RAM_DATA,
380 RV670_cp_microcode[i][2]);
381 }
382
383 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
384 DRM_INFO("Loading RV670 PFP Microcode\n");
385 for (i = 0; i < PFP_UCODE_SIZE; i++)
386 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]);
387 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
388 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
389 DRM_INFO("Loading RS780/RS880 CP Microcode\n");
390 for (i = 0; i < PM4_UCODE_SIZE; i++) {
391 RADEON_WRITE(R600_CP_ME_RAM_DATA,
392 RS780_cp_microcode[i][0]);
393 RADEON_WRITE(R600_CP_ME_RAM_DATA,
394 RS780_cp_microcode[i][1]);
395 RADEON_WRITE(R600_CP_ME_RAM_DATA,
396 RS780_cp_microcode[i][2]);
397 }
398 419
399 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
400 DRM_INFO("Loading RS780/RS880 PFP Microcode\n");
401 for (i = 0; i < PFP_UCODE_SIZE; i++)
402 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RS780_pfp_microcode[i]);
403 }
404 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 420 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
405 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 421 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
406 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 422 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
@@ -459,11 +475,14 @@ static void r700_vm_init(struct drm_device *dev)
459 r600_vm_flush_gart_range(dev); 475 r600_vm_flush_gart_range(dev);
460} 476}
461 477
462/* load r600 microcode */
463static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) 478static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
464{ 479{
480 const __be32 *fw_data;
465 int i; 481 int i;
466 482
483 if (!dev_priv->me_fw || !dev_priv->pfp_fw)
484 return;
485
467 r600_do_cp_stop(dev_priv); 486 r600_do_cp_stop(dev_priv);
468 487
469 RADEON_WRITE(R600_CP_RB_CNTL, 488 RADEON_WRITE(R600_CP_RB_CNTL,
@@ -476,48 +495,18 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
476 DRM_UDELAY(15000); 495 DRM_UDELAY(15000);
477 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 496 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
478 497
498 fw_data = (const __be32 *)dev_priv->pfp_fw->data;
499 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
500 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
501 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
502 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
479 503
480 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) { 504 fw_data = (const __be32 *)dev_priv->me_fw->data;
481 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 505 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
482 DRM_INFO("Loading RV770/RV790 PFP Microcode\n"); 506 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
483 for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 507 RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
484 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]); 508 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
485 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
486
487 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
488 DRM_INFO("Loading RV770/RV790 CP Microcode\n");
489 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
490 RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]);
491 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
492
493 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730) ||
494 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)) {
495 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
496 DRM_INFO("Loading RV730/RV740 PFP Microcode\n");
497 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
498 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]);
499 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
500
501 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
502 DRM_INFO("Loading RV730/RV740 CP Microcode\n");
503 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
504 RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]);
505 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
506
507 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) {
508 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
509 DRM_INFO("Loading RV710 PFP Microcode\n");
510 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
511 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV710_pfp_microcode[i]);
512 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
513
514 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
515 DRM_INFO("Loading RV710 CP Microcode\n");
516 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
517 RADEON_WRITE(R600_CP_ME_RAM_DATA, RV710_cp_microcode[i]);
518 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
519 509
520 }
521 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 510 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
522 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 511 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
523 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 512 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
@@ -1874,6 +1863,8 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1874 1863
1875 DRM_DEBUG("\n"); 1864 DRM_DEBUG("\n");
1876 1865
1866 mutex_init(&dev_priv->cs_mutex);
1867 r600_cs_legacy_init();
1877 /* if we require new memory map but we don't have it fail */ 1868 /* if we require new memory map but we don't have it fail */
1878 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { 1869 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1879 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 1870 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
@@ -1905,7 +1896,7 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1905 /* Enable vblank on CRTC1 for older X servers 1896 /* Enable vblank on CRTC1 for older X servers
1906 */ 1897 */
1907 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; 1898 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1908 1899 dev_priv->do_boxes = 0;
1909 dev_priv->cp_mode = init->cp_mode; 1900 dev_priv->cp_mode = init->cp_mode;
1910 1901
1911 /* We don't support anything other than bus-mastering ring mode, 1902 /* We don't support anything other than bus-mastering ring mode,
@@ -1991,11 +1982,11 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1991 } else 1982 } else
1992#endif 1983#endif
1993 { 1984 {
1994 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; 1985 dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset;
1995 dev_priv->ring_rptr->handle = 1986 dev_priv->ring_rptr->handle =
1996 (void *)dev_priv->ring_rptr->offset; 1987 (void *)(unsigned long)dev_priv->ring_rptr->offset;
1997 dev->agp_buffer_map->handle = 1988 dev->agp_buffer_map->handle =
1998 (void *)dev->agp_buffer_map->offset; 1989 (void *)(unsigned long)dev->agp_buffer_map->offset;
1999 1990
2000 DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 1991 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
2001 dev_priv->cp_ring->handle); 1992 dev_priv->cp_ring->handle);
@@ -2147,6 +2138,14 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
2147 r600_vm_init(dev); 2138 r600_vm_init(dev);
2148 } 2139 }
2149 2140
2141 if (!dev_priv->me_fw || !dev_priv->pfp_fw) {
2142 int err = r600_cp_init_microcode(dev_priv);
2143 if (err) {
2144 DRM_ERROR("Failed to load firmware!\n");
2145 r600_do_cleanup_cp(dev);
2146 return err;
2147 }
2148 }
2150 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2149 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2151 r700_cp_load_microcode(dev_priv); 2150 r700_cp_load_microcode(dev_priv);
2152 else 2151 else
@@ -2291,3 +2290,239 @@ int r600_cp_dispatch_indirect(struct drm_device *dev,
2291 2290
2292 return 0; 2291 return 0;
2293} 2292}
2293
2294void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv)
2295{
2296 drm_radeon_private_t *dev_priv = dev->dev_private;
2297 struct drm_master *master = file_priv->master;
2298 struct drm_radeon_master_private *master_priv = master->driver_priv;
2299 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2300 int nbox = sarea_priv->nbox;
2301 struct drm_clip_rect *pbox = sarea_priv->boxes;
2302 int i, cpp, src_pitch, dst_pitch;
2303 uint64_t src, dst;
2304 RING_LOCALS;
2305 DRM_DEBUG("\n");
2306
2307 if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888)
2308 cpp = 4;
2309 else
2310 cpp = 2;
2311
2312 if (sarea_priv->pfCurrentPage == 0) {
2313 src_pitch = dev_priv->back_pitch;
2314 dst_pitch = dev_priv->front_pitch;
2315 src = dev_priv->back_offset + dev_priv->fb_location;
2316 dst = dev_priv->front_offset + dev_priv->fb_location;
2317 } else {
2318 src_pitch = dev_priv->front_pitch;
2319 dst_pitch = dev_priv->back_pitch;
2320 src = dev_priv->front_offset + dev_priv->fb_location;
2321 dst = dev_priv->back_offset + dev_priv->fb_location;
2322 }
2323
2324 if (r600_prepare_blit_copy(dev, file_priv)) {
2325 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2326 return;
2327 }
2328 for (i = 0; i < nbox; i++) {
2329 int x = pbox[i].x1;
2330 int y = pbox[i].y1;
2331 int w = pbox[i].x2 - x;
2332 int h = pbox[i].y2 - y;
2333
2334 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
2335
2336 r600_blit_swap(dev,
2337 src, dst,
2338 x, y, x, y, w, h,
2339 src_pitch, dst_pitch, cpp);
2340 }
2341 r600_done_blit_copy(dev);
2342
2343 /* Increment the frame counter. The client-side 3D driver must
2344 * throttle the framerate by waiting for this value before
2345 * performing the swapbuffer ioctl.
2346 */
2347 sarea_priv->last_frame++;
2348
2349 BEGIN_RING(3);
2350 R600_FRAME_AGE(sarea_priv->last_frame);
2351 ADVANCE_RING();
2352}
2353
2354int r600_cp_dispatch_texture(struct drm_device *dev,
2355 struct drm_file *file_priv,
2356 drm_radeon_texture_t *tex,
2357 drm_radeon_tex_image_t *image)
2358{
2359 drm_radeon_private_t *dev_priv = dev->dev_private;
2360 struct drm_buf *buf;
2361 u32 *buffer;
2362 const u8 __user *data;
2363 int size, pass_size;
2364 u64 src_offset, dst_offset;
2365
2366 if (!radeon_check_offset(dev_priv, tex->offset)) {
2367 DRM_ERROR("Invalid destination offset\n");
2368 return -EINVAL;
2369 }
2370
2371 /* this might fail for zero-sized uploads - are those illegal? */
2372 if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) {
2373 DRM_ERROR("Invalid final destination offset\n");
2374 return -EINVAL;
2375 }
2376
2377 size = tex->height * tex->pitch;
2378
2379 if (size == 0)
2380 return 0;
2381
2382 dst_offset = tex->offset;
2383
2384 if (r600_prepare_blit_copy(dev, file_priv)) {
2385 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2386 return -EAGAIN;
2387 }
2388 do {
2389 data = (const u8 __user *)image->data;
2390 pass_size = size;
2391
2392 buf = radeon_freelist_get(dev);
2393 if (!buf) {
2394 DRM_DEBUG("EAGAIN\n");
2395 if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
2396 return -EFAULT;
2397 return -EAGAIN;
2398 }
2399
2400 if (pass_size > buf->total)
2401 pass_size = buf->total;
2402
2403 /* Dispatch the indirect buffer.
2404 */
2405 buffer =
2406 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
2407
2408 if (DRM_COPY_FROM_USER(buffer, data, pass_size)) {
2409 DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size);
2410 return -EFAULT;
2411 }
2412
2413 buf->file_priv = file_priv;
2414 buf->used = pass_size;
2415 src_offset = dev_priv->gart_buffers_offset + buf->offset;
2416
2417 r600_blit_copy(dev, src_offset, dst_offset, pass_size);
2418
2419 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2420
2421 /* Update the input parameters for next time */
2422 image->data = (const u8 __user *)image->data + pass_size;
2423 dst_offset += pass_size;
2424 size -= pass_size;
2425 } while (size > 0);
2426 r600_done_blit_copy(dev);
2427
2428 return 0;
2429}
2430
2431/*
2432 * Legacy cs ioctl
2433 */
2434static u32 radeon_cs_id_get(struct drm_radeon_private *radeon)
2435{
2436 /* FIXME: check if wrap affect last reported wrap & sequence */
2437 radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF;
2438 if (!radeon->cs_id_scnt) {
2439 /* increment wrap counter */
2440 radeon->cs_id_wcnt += 0x01000000;
2441 /* valid sequence counter start at 1 */
2442 radeon->cs_id_scnt = 1;
2443 }
2444 return (radeon->cs_id_scnt | radeon->cs_id_wcnt);
2445}
2446
2447static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id)
2448{
2449 RING_LOCALS;
2450
2451 *id = radeon_cs_id_get(dev_priv);
2452
2453 /* SCRATCH 2 */
2454 BEGIN_RING(3);
2455 R600_CLEAR_AGE(*id);
2456 ADVANCE_RING();
2457 COMMIT_RING();
2458}
2459
2460static int r600_ib_get(struct drm_device *dev,
2461 struct drm_file *fpriv,
2462 struct drm_buf **buffer)
2463{
2464 struct drm_buf *buf;
2465
2466 *buffer = NULL;
2467 buf = radeon_freelist_get(dev);
2468 if (!buf) {
2469 return -EBUSY;
2470 }
2471 buf->file_priv = fpriv;
2472 *buffer = buf;
2473 return 0;
2474}
2475
2476static void r600_ib_free(struct drm_device *dev, struct drm_buf *buf,
2477 struct drm_file *fpriv, int l, int r)
2478{
2479 drm_radeon_private_t *dev_priv = dev->dev_private;
2480
2481 if (buf) {
2482 if (!r)
2483 r600_cp_dispatch_indirect(dev, buf, 0, l * 4);
2484 radeon_cp_discard_buffer(dev, fpriv->master, buf);
2485 COMMIT_RING();
2486 }
2487}
2488
2489int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
2490{
2491 struct drm_radeon_private *dev_priv = dev->dev_private;
2492 struct drm_radeon_cs *cs = data;
2493 struct drm_buf *buf;
2494 unsigned family;
2495 int l, r = 0;
2496 u32 *ib, cs_id = 0;
2497
2498 if (dev_priv == NULL) {
2499 DRM_ERROR("called with no initialization\n");
2500 return -EINVAL;
2501 }
2502 family = dev_priv->flags & RADEON_FAMILY_MASK;
2503 if (family < CHIP_R600) {
2504 DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n");
2505 return -EINVAL;
2506 }
2507 mutex_lock(&dev_priv->cs_mutex);
2508 /* get ib */
2509 r = r600_ib_get(dev, fpriv, &buf);
2510 if (r) {
2511 DRM_ERROR("ib_get failed\n");
2512 goto out;
2513 }
2514 ib = dev->agp_buffer_map->handle + buf->offset;
2515 /* now parse command stream */
2516 r = r600_cs_legacy(dev, data, fpriv, family, ib, &l);
2517 if (r) {
2518 goto out;
2519 }
2520
2521out:
2522 r600_ib_free(dev, buf, fpriv, l, r);
2523 /* emit cs id sequence */
2524 r600_cs_id_emit(dev_priv, &cs_id);
2525 cs->cs_id = cs_id;
2526 mutex_unlock(&dev_priv->cs_mutex);
2527 return r;
2528}
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
new file mode 100644
index 000000000000..33b89cd8743e
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -0,0 +1,657 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "radeon.h"
30#include "r600d.h"
31#include "avivod.h"
32
33static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
34 struct radeon_cs_reloc **cs_reloc);
35static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
36 struct radeon_cs_reloc **cs_reloc);
37typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
38static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
39
40/**
41 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
42 * @parser: parser structure holding parsing context.
43 * @pkt: where to store packet informations
44 *
45 * Assume that chunk_ib_index is properly set. Will return -EINVAL
46 * if packet is bigger than remaining ib size. or if packets is unknown.
47 **/
48int r600_cs_packet_parse(struct radeon_cs_parser *p,
49 struct radeon_cs_packet *pkt,
50 unsigned idx)
51{
52 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
53 uint32_t header;
54
55 if (idx >= ib_chunk->length_dw) {
56 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
57 idx, ib_chunk->length_dw);
58 return -EINVAL;
59 }
60 header = ib_chunk->kdata[idx];
61 pkt->idx = idx;
62 pkt->type = CP_PACKET_GET_TYPE(header);
63 pkt->count = CP_PACKET_GET_COUNT(header);
64 pkt->one_reg_wr = 0;
65 switch (pkt->type) {
66 case PACKET_TYPE0:
67 pkt->reg = CP_PACKET0_GET_REG(header);
68 break;
69 case PACKET_TYPE3:
70 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
71 break;
72 case PACKET_TYPE2:
73 pkt->count = -1;
74 break;
75 default:
76 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
77 return -EINVAL;
78 }
79 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
80 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
81 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
82 return -EINVAL;
83 }
84 return 0;
85}
86
87/**
88 * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
89 * @parser: parser structure holding parsing context.
90 * @data: pointer to relocation data
91 * @offset_start: starting offset
92 * @offset_mask: offset mask (to align start offset on)
93 * @reloc: reloc informations
94 *
95 * Check next packet is relocation packet3, do bo validation and compute
96 * GPU offset using the provided start.
97 **/
98static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
99 struct radeon_cs_reloc **cs_reloc)
100{
101 struct radeon_cs_chunk *ib_chunk;
102 struct radeon_cs_chunk *relocs_chunk;
103 struct radeon_cs_packet p3reloc;
104 unsigned idx;
105 int r;
106
107 if (p->chunk_relocs_idx == -1) {
108 DRM_ERROR("No relocation chunk !\n");
109 return -EINVAL;
110 }
111 *cs_reloc = NULL;
112 ib_chunk = &p->chunks[p->chunk_ib_idx];
113 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
114 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
115 if (r) {
116 return r;
117 }
118 p->idx += p3reloc.count + 2;
119 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
120 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
121 p3reloc.idx);
122 return -EINVAL;
123 }
124 idx = ib_chunk->kdata[p3reloc.idx + 1];
125 if (idx >= relocs_chunk->length_dw) {
126 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
127 idx, relocs_chunk->length_dw);
128 return -EINVAL;
129 }
130 /* FIXME: we assume reloc size is 4 dwords */
131 *cs_reloc = p->relocs_ptr[(idx / 4)];
132 return 0;
133}
134
135/**
136 * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
137 * @parser: parser structure holding parsing context.
138 * @data: pointer to relocation data
139 * @offset_start: starting offset
140 * @offset_mask: offset mask (to align start offset on)
141 * @reloc: reloc informations
142 *
143 * Check next packet is relocation packet3, do bo validation and compute
144 * GPU offset using the provided start.
145 **/
146static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
147 struct radeon_cs_reloc **cs_reloc)
148{
149 struct radeon_cs_chunk *ib_chunk;
150 struct radeon_cs_chunk *relocs_chunk;
151 struct radeon_cs_packet p3reloc;
152 unsigned idx;
153 int r;
154
155 if (p->chunk_relocs_idx == -1) {
156 DRM_ERROR("No relocation chunk !\n");
157 return -EINVAL;
158 }
159 *cs_reloc = NULL;
160 ib_chunk = &p->chunks[p->chunk_ib_idx];
161 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
162 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
163 if (r) {
164 return r;
165 }
166 p->idx += p3reloc.count + 2;
167 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
168 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
169 p3reloc.idx);
170 return -EINVAL;
171 }
172 idx = ib_chunk->kdata[p3reloc.idx + 1];
173 if (idx >= relocs_chunk->length_dw) {
174 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
175 idx, relocs_chunk->length_dw);
176 return -EINVAL;
177 }
178 *cs_reloc = &p->relocs[0];
179 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
180 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
181 return 0;
182}
183
184static int r600_packet0_check(struct radeon_cs_parser *p,
185 struct radeon_cs_packet *pkt,
186 unsigned idx, unsigned reg)
187{
188 switch (reg) {
189 case AVIVO_D1MODE_VLINE_START_END:
190 case AVIVO_D2MODE_VLINE_START_END:
191 break;
192 default:
193 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
194 reg, idx);
195 return -EINVAL;
196 }
197 return 0;
198}
199
200static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
201 struct radeon_cs_packet *pkt)
202{
203 unsigned reg, i;
204 unsigned idx;
205 int r;
206
207 idx = pkt->idx + 1;
208 reg = pkt->reg;
209 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
210 r = r600_packet0_check(p, pkt, idx, reg);
211 if (r) {
212 return r;
213 }
214 }
215 return 0;
216}
217
218static int r600_packet3_check(struct radeon_cs_parser *p,
219 struct radeon_cs_packet *pkt)
220{
221 struct radeon_cs_chunk *ib_chunk;
222 struct radeon_cs_reloc *reloc;
223 volatile u32 *ib;
224 unsigned idx;
225 unsigned i;
226 unsigned start_reg, end_reg, reg;
227 int r;
228
229 ib = p->ib->ptr;
230 ib_chunk = &p->chunks[p->chunk_ib_idx];
231 idx = pkt->idx + 1;
232 switch (pkt->opcode) {
233 case PACKET3_START_3D_CMDBUF:
234 if (p->family >= CHIP_RV770 || pkt->count) {
235 DRM_ERROR("bad START_3D\n");
236 return -EINVAL;
237 }
238 break;
239 case PACKET3_CONTEXT_CONTROL:
240 if (pkt->count != 1) {
241 DRM_ERROR("bad CONTEXT_CONTROL\n");
242 return -EINVAL;
243 }
244 break;
245 case PACKET3_INDEX_TYPE:
246 case PACKET3_NUM_INSTANCES:
247 if (pkt->count) {
248 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
249 return -EINVAL;
250 }
251 break;
252 case PACKET3_DRAW_INDEX:
253 if (pkt->count != 3) {
254 DRM_ERROR("bad DRAW_INDEX\n");
255 return -EINVAL;
256 }
257 r = r600_cs_packet_next_reloc(p, &reloc);
258 if (r) {
259 DRM_ERROR("bad DRAW_INDEX\n");
260 return -EINVAL;
261 }
262 ib[idx+0] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
263 ib[idx+1] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
264 break;
265 case PACKET3_DRAW_INDEX_AUTO:
266 if (pkt->count != 1) {
267 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
268 return -EINVAL;
269 }
270 break;
271 case PACKET3_DRAW_INDEX_IMMD_BE:
272 case PACKET3_DRAW_INDEX_IMMD:
273 if (pkt->count < 2) {
274 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
275 return -EINVAL;
276 }
277 break;
278 case PACKET3_WAIT_REG_MEM:
279 if (pkt->count != 5) {
280 DRM_ERROR("bad WAIT_REG_MEM\n");
281 return -EINVAL;
282 }
283 /* bit 4 is reg (0) or mem (1) */
284 if (ib_chunk->kdata[idx+0] & 0x10) {
285 r = r600_cs_packet_next_reloc(p, &reloc);
286 if (r) {
287 DRM_ERROR("bad WAIT_REG_MEM\n");
288 return -EINVAL;
289 }
290 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
291 ib[idx+2] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
292 }
293 break;
294 case PACKET3_SURFACE_SYNC:
295 if (pkt->count != 3) {
296 DRM_ERROR("bad SURFACE_SYNC\n");
297 return -EINVAL;
298 }
299 /* 0xffffffff/0x0 is flush all cache flag */
300 if (ib_chunk->kdata[idx+1] != 0xffffffff ||
301 ib_chunk->kdata[idx+2] != 0) {
302 r = r600_cs_packet_next_reloc(p, &reloc);
303 if (r) {
304 DRM_ERROR("bad SURFACE_SYNC\n");
305 return -EINVAL;
306 }
307 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
308 }
309 break;
310 case PACKET3_EVENT_WRITE:
311 if (pkt->count != 2 && pkt->count != 0) {
312 DRM_ERROR("bad EVENT_WRITE\n");
313 return -EINVAL;
314 }
315 if (pkt->count) {
316 r = r600_cs_packet_next_reloc(p, &reloc);
317 if (r) {
318 DRM_ERROR("bad EVENT_WRITE\n");
319 return -EINVAL;
320 }
321 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
322 ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
323 }
324 break;
325 case PACKET3_EVENT_WRITE_EOP:
326 if (pkt->count != 4) {
327 DRM_ERROR("bad EVENT_WRITE_EOP\n");
328 return -EINVAL;
329 }
330 r = r600_cs_packet_next_reloc(p, &reloc);
331 if (r) {
332 DRM_ERROR("bad EVENT_WRITE\n");
333 return -EINVAL;
334 }
335 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
336 ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
337 break;
338 case PACKET3_SET_CONFIG_REG:
339 start_reg = (ib[idx+0] << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
340 end_reg = 4 * pkt->count + start_reg - 4;
341 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
342 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
343 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
344 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
345 return -EINVAL;
346 }
347 for (i = 0; i < pkt->count; i++) {
348 reg = start_reg + (4 * i);
349 switch (reg) {
350 case CP_COHER_BASE:
351 /* use PACKET3_SURFACE_SYNC */
352 return -EINVAL;
353 default:
354 break;
355 }
356 }
357 break;
358 case PACKET3_SET_CONTEXT_REG:
359 start_reg = (ib[idx+0] << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
360 end_reg = 4 * pkt->count + start_reg - 4;
361 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
362 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
363 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
364 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
365 return -EINVAL;
366 }
367 for (i = 0; i < pkt->count; i++) {
368 reg = start_reg + (4 * i);
369 switch (reg) {
370 case DB_DEPTH_BASE:
371 case CB_COLOR0_BASE:
372 case CB_COLOR1_BASE:
373 case CB_COLOR2_BASE:
374 case CB_COLOR3_BASE:
375 case CB_COLOR4_BASE:
376 case CB_COLOR5_BASE:
377 case CB_COLOR6_BASE:
378 case CB_COLOR7_BASE:
379 case SQ_PGM_START_FS:
380 case SQ_PGM_START_ES:
381 case SQ_PGM_START_VS:
382 case SQ_PGM_START_GS:
383 case SQ_PGM_START_PS:
384 r = r600_cs_packet_next_reloc(p, &reloc);
385 if (r) {
386 DRM_ERROR("bad SET_CONTEXT_REG "
387 "0x%04X\n", reg);
388 return -EINVAL;
389 }
390 ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
391 break;
392 case VGT_DMA_BASE:
393 case VGT_DMA_BASE_HI:
394 /* These should be handled by DRAW_INDEX packet 3 */
395 case VGT_STRMOUT_BASE_OFFSET_0:
396 case VGT_STRMOUT_BASE_OFFSET_1:
397 case VGT_STRMOUT_BASE_OFFSET_2:
398 case VGT_STRMOUT_BASE_OFFSET_3:
399 case VGT_STRMOUT_BASE_OFFSET_HI_0:
400 case VGT_STRMOUT_BASE_OFFSET_HI_1:
401 case VGT_STRMOUT_BASE_OFFSET_HI_2:
402 case VGT_STRMOUT_BASE_OFFSET_HI_3:
403 case VGT_STRMOUT_BUFFER_BASE_0:
404 case VGT_STRMOUT_BUFFER_BASE_1:
405 case VGT_STRMOUT_BUFFER_BASE_2:
406 case VGT_STRMOUT_BUFFER_BASE_3:
407 case VGT_STRMOUT_BUFFER_OFFSET_0:
408 case VGT_STRMOUT_BUFFER_OFFSET_1:
409 case VGT_STRMOUT_BUFFER_OFFSET_2:
410 case VGT_STRMOUT_BUFFER_OFFSET_3:
411 /* These should be handled by STRMOUT_BUFFER packet 3 */
412 DRM_ERROR("bad context reg: 0x%08x\n", reg);
413 return -EINVAL;
414 default:
415 break;
416 }
417 }
418 break;
419 case PACKET3_SET_RESOURCE:
420 if (pkt->count % 7) {
421 DRM_ERROR("bad SET_RESOURCE\n");
422 return -EINVAL;
423 }
424 start_reg = (ib[idx+0] << 2) + PACKET3_SET_RESOURCE_OFFSET;
425 end_reg = 4 * pkt->count + start_reg - 4;
426 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
427 (start_reg >= PACKET3_SET_RESOURCE_END) ||
428 (end_reg >= PACKET3_SET_RESOURCE_END)) {
429 DRM_ERROR("bad SET_RESOURCE\n");
430 return -EINVAL;
431 }
432 for (i = 0; i < (pkt->count / 7); i++) {
433 switch (G__SQ_VTX_CONSTANT_TYPE(ib[idx+(i*7)+6+1])) {
434 case SQ_TEX_VTX_VALID_TEXTURE:
435 /* tex base */
436 r = r600_cs_packet_next_reloc(p, &reloc);
437 if (r) {
438 DRM_ERROR("bad SET_RESOURCE\n");
439 return -EINVAL;
440 }
441 ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
442 /* tex mip base */
443 r = r600_cs_packet_next_reloc(p, &reloc);
444 if (r) {
445 DRM_ERROR("bad SET_RESOURCE\n");
446 return -EINVAL;
447 }
448 ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
449 break;
450 case SQ_TEX_VTX_VALID_BUFFER:
451 /* vtx base */
452 r = r600_cs_packet_next_reloc(p, &reloc);
453 if (r) {
454 DRM_ERROR("bad SET_RESOURCE\n");
455 return -EINVAL;
456 }
457 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
458 ib[idx+1+(i*7)+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
459 break;
460 case SQ_TEX_VTX_INVALID_TEXTURE:
461 case SQ_TEX_VTX_INVALID_BUFFER:
462 default:
463 DRM_ERROR("bad SET_RESOURCE\n");
464 return -EINVAL;
465 }
466 }
467 break;
468 case PACKET3_SET_ALU_CONST:
469 start_reg = (ib[idx+0] << 2) + PACKET3_SET_ALU_CONST_OFFSET;
470 end_reg = 4 * pkt->count + start_reg - 4;
471 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
472 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
473 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
474 DRM_ERROR("bad SET_ALU_CONST\n");
475 return -EINVAL;
476 }
477 break;
478 case PACKET3_SET_BOOL_CONST:
479 start_reg = (ib[idx+0] << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
480 end_reg = 4 * pkt->count + start_reg - 4;
481 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
482 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
483 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
484 DRM_ERROR("bad SET_BOOL_CONST\n");
485 return -EINVAL;
486 }
487 break;
488 case PACKET3_SET_LOOP_CONST:
489 start_reg = (ib[idx+0] << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
490 end_reg = 4 * pkt->count + start_reg - 4;
491 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
492 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
493 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
494 DRM_ERROR("bad SET_LOOP_CONST\n");
495 return -EINVAL;
496 }
497 break;
498 case PACKET3_SET_CTL_CONST:
499 start_reg = (ib[idx+0] << 2) + PACKET3_SET_CTL_CONST_OFFSET;
500 end_reg = 4 * pkt->count + start_reg - 4;
501 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
502 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
503 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
504 DRM_ERROR("bad SET_CTL_CONST\n");
505 return -EINVAL;
506 }
507 break;
508 case PACKET3_SET_SAMPLER:
509 if (pkt->count % 3) {
510 DRM_ERROR("bad SET_SAMPLER\n");
511 return -EINVAL;
512 }
513 start_reg = (ib[idx+0] << 2) + PACKET3_SET_SAMPLER_OFFSET;
514 end_reg = 4 * pkt->count + start_reg - 4;
515 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
516 (start_reg >= PACKET3_SET_SAMPLER_END) ||
517 (end_reg >= PACKET3_SET_SAMPLER_END)) {
518 DRM_ERROR("bad SET_SAMPLER\n");
519 return -EINVAL;
520 }
521 break;
522 case PACKET3_SURFACE_BASE_UPDATE:
523 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
524 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
525 return -EINVAL;
526 }
527 if (pkt->count) {
528 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
529 return -EINVAL;
530 }
531 break;
532 case PACKET3_NOP:
533 break;
534 default:
535 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
536 return -EINVAL;
537 }
538 return 0;
539}
540
541int r600_cs_parse(struct radeon_cs_parser *p)
542{
543 struct radeon_cs_packet pkt;
544 int r;
545
546 do {
547 r = r600_cs_packet_parse(p, &pkt, p->idx);
548 if (r) {
549 return r;
550 }
551 p->idx += pkt.count + 2;
552 switch (pkt.type) {
553 case PACKET_TYPE0:
554 r = r600_cs_parse_packet0(p, &pkt);
555 break;
556 case PACKET_TYPE2:
557 break;
558 case PACKET_TYPE3:
559 r = r600_packet3_check(p, &pkt);
560 break;
561 default:
562 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
563 return -EINVAL;
564 }
565 if (r) {
566 return r;
567 }
568 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
569#if 0
570 for (r = 0; r < p->ib->length_dw; r++) {
571 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]);
572 mdelay(1);
573 }
574#endif
575 return 0;
576}
577
578static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
579{
580 if (p->chunk_relocs_idx == -1) {
581 return 0;
582 }
583 p->relocs = kcalloc(1, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
584 if (p->relocs == NULL) {
585 return -ENOMEM;
586 }
587 return 0;
588}
589
590/**
591 * cs_parser_fini() - clean parser states
592 * @parser: parser structure holding parsing context.
593 * @error: error number
594 *
595 * If error is set than unvalidate buffer, otherwise just free memory
596 * used by parsing context.
597 **/
598static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
599{
600 unsigned i;
601
602 kfree(parser->relocs);
603 for (i = 0; i < parser->nchunks; i++) {
604 kfree(parser->chunks[i].kdata);
605 }
606 kfree(parser->chunks);
607 kfree(parser->chunks_array);
608}
609
610int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
611 unsigned family, u32 *ib, int *l)
612{
613 struct radeon_cs_parser parser;
614 struct radeon_cs_chunk *ib_chunk;
615 struct radeon_ib fake_ib;
616 int r;
617
618 /* initialize parser */
619 memset(&parser, 0, sizeof(struct radeon_cs_parser));
620 parser.filp = filp;
621 parser.rdev = NULL;
622 parser.family = family;
623 parser.ib = &fake_ib;
624 fake_ib.ptr = ib;
625 r = radeon_cs_parser_init(&parser, data);
626 if (r) {
627 DRM_ERROR("Failed to initialize parser !\n");
628 r600_cs_parser_fini(&parser, r);
629 return r;
630 }
631 r = r600_cs_parser_relocs_legacy(&parser);
632 if (r) {
633 DRM_ERROR("Failed to parse relocation !\n");
634 r600_cs_parser_fini(&parser, r);
635 return r;
636 }
637 /* Copy the packet into the IB, the parser will read from the
638 * input memory (cached) and write to the IB (which can be
639 * uncached). */
640 ib_chunk = &parser.chunks[parser.chunk_ib_idx];
641 parser.ib->length_dw = ib_chunk->length_dw;
642 memcpy((void *)parser.ib->ptr, ib_chunk->kdata, ib_chunk->length_dw*4);
643 *l = parser.ib->length_dw;
644 r = r600_cs_parse(&parser);
645 if (r) {
646 DRM_ERROR("Invalid command stream !\n");
647 r600_cs_parser_fini(&parser, r);
648 return r;
649 }
650 r600_cs_parser_fini(&parser, r);
651 return r;
652}
653
654void r600_cs_legacy_init(void)
655{
656 r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
657}
diff --git a/drivers/gpu/drm/radeon/r600_microcode.h b/drivers/gpu/drm/radeon/r600_microcode.h
deleted file mode 100644
index 778c8b4b2fd9..000000000000
--- a/drivers/gpu/drm/radeon/r600_microcode.h
+++ /dev/null
@@ -1,23297 +0,0 @@
1/*
2 * Copyright 2008-2009 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
20 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26#ifndef R600_MICROCODE_H
27#define R600_MICROCODE_H
28
29static const int ME_JUMP_TABLE_START = 1764;
30static const int ME_JUMP_TABLE_END = 1792;
31
32#define PFP_UCODE_SIZE 576
33#define PM4_UCODE_SIZE 1792
34#define R700_PFP_UCODE_SIZE 848
35#define R700_PM4_UCODE_SIZE 1360
36
37static const u32 R600_cp_microcode[][3] = {
38 { 0x00000000, 0xc0200400, 0x000 },
39 { 0x00000000, 0x00a0000a, 0x000 },
40 { 0x0000ffff, 0x00284621, 0x000 },
41 { 0x00000000, 0xd9004800, 0x000 },
42 { 0x00000000, 0xc0200400, 0x000 },
43 { 0x00000000, 0x00a0000a, 0x000 },
44 { 0x00000000, 0x00e00000, 0x000 },
45 { 0x00010000, 0xc0294620, 0x000 },
46 { 0x00000000, 0xd9004800, 0x000 },
47 { 0x00000000, 0xc0200400, 0x000 },
48 { 0x00000000, 0x00a0000a, 0x000 },
49 { 0x81000000, 0x00204411, 0x000 },
50 { 0x00000001, 0x00204811, 0x000 },
51 { 0x00042004, 0x00604411, 0x614 },
52 { 0x00000000, 0x00600000, 0x5b2 },
53 { 0x00000000, 0x00600000, 0x5c5 },
54 { 0x00000000, 0xc0200800, 0x000 },
55 { 0x00000f00, 0x00281622, 0x000 },
56 { 0x00000008, 0x00211625, 0x000 },
57 { 0x00000020, 0x00203625, 0x000 },
58 { 0x8d000000, 0x00204411, 0x000 },
59 { 0x00000004, 0x002f0225, 0x000 },
60 { 0x00000000, 0x0ce00000, 0x018 },
61 { 0x00412000, 0x00404811, 0x019 },
62 { 0x00422000, 0x00204811, 0x000 },
63 { 0x8e000000, 0x00204411, 0x000 },
64 { 0x00000031, 0x00204a2d, 0x000 },
65 { 0x90000000, 0x00204411, 0x000 },
66 { 0x00000000, 0x00204805, 0x000 },
67 { 0x0000000c, 0x00211622, 0x000 },
68 { 0x00000003, 0x00281625, 0x000 },
69 { 0x00000019, 0x00211a22, 0x000 },
70 { 0x00000004, 0x00281a26, 0x000 },
71 { 0x00000000, 0x002914c5, 0x000 },
72 { 0x00000021, 0x00203625, 0x000 },
73 { 0x00000000, 0x003a1402, 0x000 },
74 { 0x00000016, 0x00211625, 0x000 },
75 { 0x00000003, 0x00281625, 0x000 },
76 { 0x0000001d, 0x00200e2d, 0x000 },
77 { 0xfffffffc, 0x00280e23, 0x000 },
78 { 0x00000000, 0x002914a3, 0x000 },
79 { 0x0000001d, 0x00203625, 0x000 },
80 { 0x00008000, 0x00280e22, 0x000 },
81 { 0x00000007, 0x00220e23, 0x000 },
82 { 0x00000000, 0x0029386e, 0x000 },
83 { 0x20000000, 0x00280e22, 0x000 },
84 { 0x00000006, 0x00210e23, 0x000 },
85 { 0x00000000, 0x0029386e, 0x000 },
86 { 0x00000000, 0x00220222, 0x000 },
87 { 0x00000000, 0x14e00000, 0x038 },
88 { 0x00000000, 0x2ee00000, 0x035 },
89 { 0x00000000, 0x2ce00000, 0x037 },
90 { 0x00000000, 0x00400e2d, 0x039 },
91 { 0x00000008, 0x00200e2d, 0x000 },
92 { 0x00000009, 0x0040122d, 0x046 },
93 { 0x00000001, 0x00400e2d, 0x039 },
94 { 0x00000000, 0xc0200c00, 0x000 },
95 { 0x003ffffc, 0x00281223, 0x000 },
96 { 0x00000002, 0x00221224, 0x000 },
97 { 0x0000001f, 0x00211e23, 0x000 },
98 { 0x00000000, 0x14e00000, 0x03e },
99 { 0x00000008, 0x00401c11, 0x041 },
100 { 0x0000000d, 0x00201e2d, 0x000 },
101 { 0x0000000f, 0x00281e27, 0x000 },
102 { 0x00000003, 0x00221e27, 0x000 },
103 { 0x7fc00000, 0x00281a23, 0x000 },
104 { 0x00000014, 0x00211a26, 0x000 },
105 { 0x00000001, 0x00331a26, 0x000 },
106 { 0x00000008, 0x00221a26, 0x000 },
107 { 0x00000000, 0x00290cc7, 0x000 },
108 { 0x00000030, 0x00203624, 0x000 },
109 { 0x00007f00, 0x00281221, 0x000 },
110 { 0x00001400, 0x002f0224, 0x000 },
111 { 0x00000000, 0x0ce00000, 0x04b },
112 { 0x00000001, 0x00290e23, 0x000 },
113 { 0x00000010, 0x00203623, 0x000 },
114 { 0x0000e000, 0x00204411, 0x000 },
115 { 0xfff80000, 0x00294a23, 0x000 },
116 { 0x00000000, 0x003a2c02, 0x000 },
117 { 0x00000002, 0x00220e2b, 0x000 },
118 { 0xfc000000, 0x00280e23, 0x000 },
119 { 0x00000011, 0x00203623, 0x000 },
120 { 0x00001fff, 0x00294a23, 0x000 },
121 { 0x00000030, 0x00204a2d, 0x000 },
122 { 0x00000000, 0x00204811, 0x000 },
123 { 0x00000032, 0x00200e2d, 0x000 },
124 { 0x060a0200, 0x00294a23, 0x000 },
125 { 0x00000000, 0x00204811, 0x000 },
126 { 0x00000000, 0x00204811, 0x000 },
127 { 0x00000001, 0x00210222, 0x000 },
128 { 0x00000000, 0x14e00000, 0x061 },
129 { 0x00000000, 0x2ee00000, 0x05f },
130 { 0x00000000, 0x2ce00000, 0x05e },
131 { 0x00000000, 0x00400e2d, 0x062 },
132 { 0x00000001, 0x00400e2d, 0x062 },
133 { 0x0000000a, 0x00200e2d, 0x000 },
134 { 0x0000000b, 0x0040122d, 0x06a },
135 { 0x00000000, 0xc0200c00, 0x000 },
136 { 0x003ffffc, 0x00281223, 0x000 },
137 { 0x00000002, 0x00221224, 0x000 },
138 { 0x7fc00000, 0x00281623, 0x000 },
139 { 0x00000014, 0x00211625, 0x000 },
140 { 0x00000001, 0x00331625, 0x000 },
141 { 0x80000000, 0x00280e23, 0x000 },
142 { 0x00000000, 0x00290ca3, 0x000 },
143 { 0x3ffffc00, 0x00290e23, 0x000 },
144 { 0x0000001f, 0x00211e23, 0x000 },
145 { 0x00000000, 0x14e00000, 0x06d },
146 { 0x00000100, 0x00401c11, 0x070 },
147 { 0x0000000d, 0x00201e2d, 0x000 },
148 { 0x000000f0, 0x00281e27, 0x000 },
149 { 0x00000004, 0x00221e27, 0x000 },
150 { 0x81000000, 0x00204411, 0x000 },
151 { 0x0000000d, 0x00204811, 0x000 },
152 { 0xfffff0ff, 0x00281a30, 0x000 },
153 { 0x0000a028, 0x00204411, 0x000 },
154 { 0x00000000, 0x002948e6, 0x000 },
155 { 0x0000a018, 0x00204411, 0x000 },
156 { 0x3fffffff, 0x00284a23, 0x000 },
157 { 0x0000a010, 0x00204411, 0x000 },
158 { 0x00000000, 0x00204804, 0x000 },
159 { 0x0000002d, 0x0020162d, 0x000 },
160 { 0x00000000, 0x002f00a3, 0x000 },
161 { 0x00000000, 0x0cc00000, 0x080 },
162 { 0x0000002e, 0x0020162d, 0x000 },
163 { 0x00000000, 0x002f00a4, 0x000 },
164 { 0x00000000, 0x0cc00000, 0x081 },
165 { 0x00000000, 0x00400000, 0x087 },
166 { 0x0000002d, 0x00203623, 0x000 },
167 { 0x0000002e, 0x00203624, 0x000 },
168 { 0x0000001d, 0x00201e2d, 0x000 },
169 { 0x00000002, 0x00210227, 0x000 },
170 { 0x00000000, 0x14e00000, 0x087 },
171 { 0x00000000, 0x00600000, 0x5ed },
172 { 0x00000000, 0x00600000, 0x5e1 },
173 { 0x00000002, 0x00210e22, 0x000 },
174 { 0x00000000, 0x14c00000, 0x08a },
175 { 0x00000018, 0xc0403620, 0x090 },
176 { 0x00000000, 0x2ee00000, 0x08e },
177 { 0x00000000, 0x2ce00000, 0x08d },
178 { 0x00000002, 0x00400e2d, 0x08f },
179 { 0x00000003, 0x00400e2d, 0x08f },
180 { 0x0000000c, 0x00200e2d, 0x000 },
181 { 0x00000018, 0x00203623, 0x000 },
182 { 0x00000003, 0x00210e22, 0x000 },
183 { 0x00000000, 0x14c00000, 0x095 },
184 { 0x0000a00c, 0x00204411, 0x000 },
185 { 0x00000000, 0xc0204800, 0x000 },
186 { 0x00000000, 0xc0404800, 0x09d },
187 { 0x0000a00c, 0x00204411, 0x000 },
188 { 0x00000000, 0x00204811, 0x000 },
189 { 0x00000000, 0x2ee00000, 0x09b },
190 { 0x00000000, 0x2ce00000, 0x09a },
191 { 0x00000002, 0x00400e2d, 0x09c },
192 { 0x00000003, 0x00400e2d, 0x09c },
193 { 0x0000000c, 0x00200e2d, 0x000 },
194 { 0x00000000, 0x00204803, 0x000 },
195 { 0x00000000, 0x003a0c02, 0x000 },
196 { 0x003f0000, 0x00280e23, 0x000 },
197 { 0x00000010, 0x00210e23, 0x000 },
198 { 0x00000013, 0x00203623, 0x000 },
199 { 0x0000001e, 0x0021022b, 0x000 },
200 { 0x00000000, 0x14c00000, 0x0a4 },
201 { 0x0000001c, 0xc0203620, 0x000 },
202 { 0x0000001f, 0x0021022b, 0x000 },
203 { 0x00000000, 0x14c00000, 0x0a7 },
204 { 0x0000001b, 0xc0203620, 0x000 },
205 { 0x00000008, 0x00210e2b, 0x000 },
206 { 0x0000007f, 0x00280e23, 0x000 },
207 { 0x00000000, 0x002f0223, 0x000 },
208 { 0x00000000, 0x0ce00000, 0x0db },
209 { 0x00000000, 0x27000000, 0x000 },
210 { 0x00000000, 0x00600000, 0x28c },
211 { 0x81000000, 0x00204411, 0x000 },
212 { 0x00000006, 0x00204811, 0x000 },
213 { 0x0000000c, 0x00221e30, 0x000 },
214 { 0x99800000, 0x00204411, 0x000 },
215 { 0x00000004, 0x0020122d, 0x000 },
216 { 0x00000008, 0x00221224, 0x000 },
217 { 0x00000010, 0x00201811, 0x000 },
218 { 0x00000000, 0x00291ce4, 0x000 },
219 { 0x00000000, 0x00604807, 0x128 },
220 { 0x9b000000, 0x00204411, 0x000 },
221 { 0x00000000, 0x00204802, 0x000 },
222 { 0x9c000000, 0x00204411, 0x000 },
223 { 0x00000000, 0x0033146f, 0x000 },
224 { 0x00000001, 0x00333e23, 0x000 },
225 { 0x00000000, 0xd9004800, 0x000 },
226 { 0x00000000, 0x00203c05, 0x000 },
227 { 0x81000000, 0x00204411, 0x000 },
228 { 0x0000000e, 0x00204811, 0x000 },
229 { 0x00000000, 0x00201010, 0x000 },
230 { 0x0000e007, 0x00204411, 0x000 },
231 { 0x0000000f, 0x0021022b, 0x000 },
232 { 0x00000000, 0x14c00000, 0x0c5 },
233 { 0x00f8ff08, 0x00204811, 0x000 },
234 { 0x98000000, 0x00404811, 0x0d6 },
235 { 0x000000f0, 0x00280e22, 0x000 },
236 { 0x000000a0, 0x002f0223, 0x000 },
237 { 0x00000000, 0x0cc00000, 0x0d4 },
238 { 0x00000013, 0x00200e2d, 0x000 },
239 { 0x00000001, 0x002f0223, 0x000 },
240 { 0x00000000, 0x0ce00000, 0x0cf },
241 { 0x00000002, 0x002f0223, 0x000 },
242 { 0x00000000, 0x0ce00000, 0x0ce },
243 { 0x00003f00, 0x00400c11, 0x0d0 },
244 { 0x00001f00, 0x00400c11, 0x0d0 },
245 { 0x00000f00, 0x00200c11, 0x000 },
246 { 0x00380009, 0x00294a23, 0x000 },
247 { 0x3f000000, 0x00280e2b, 0x000 },
248 { 0x00000002, 0x00220e23, 0x000 },
249 { 0x00000007, 0x00494a23, 0x0d6 },
250 { 0x00380f09, 0x00204811, 0x000 },
251 { 0x68000007, 0x00204811, 0x000 },
252 { 0x00000008, 0x00214a27, 0x000 },
253 { 0x00000000, 0x00204811, 0x000 },
254 { 0x060a0200, 0x00294a24, 0x000 },
255 { 0x00000000, 0x00204811, 0x000 },
256 { 0x00000000, 0x00204811, 0x000 },
257 { 0x0000a202, 0x00204411, 0x000 },
258 { 0x00ff0000, 0x00284a22, 0x000 },
259 { 0x00000030, 0x00200e2d, 0x000 },
260 { 0x0000002e, 0x0020122d, 0x000 },
261 { 0x00000000, 0x002f0083, 0x000 },
262 { 0x00000000, 0x0ce00000, 0x0e3 },
263 { 0x00000000, 0x00600000, 0x5e7 },
264 { 0x00000000, 0x00400000, 0x0e4 },
265 { 0x00000000, 0x00600000, 0x5ea },
266 { 0x00000007, 0x0020222d, 0x000 },
267 { 0x00000005, 0x00220e22, 0x000 },
268 { 0x00100000, 0x00280e23, 0x000 },
269 { 0x00000000, 0x00292068, 0x000 },
270 { 0x00000000, 0x003a0c02, 0x000 },
271 { 0x000000ef, 0x00280e23, 0x000 },
272 { 0x00000000, 0x00292068, 0x000 },
273 { 0x0000001d, 0x00200e2d, 0x000 },
274 { 0x00000003, 0x00210223, 0x000 },
275 { 0x00000000, 0x14e00000, 0x0f1 },
276 { 0x0000000b, 0x00210228, 0x000 },
277 { 0x00000000, 0x14c00000, 0x0f1 },
278 { 0x00000400, 0x00292228, 0x000 },
279 { 0x0000001a, 0x00203628, 0x000 },
280 { 0x0000001c, 0x00210e22, 0x000 },
281 { 0x00000000, 0x14c00000, 0x0f6 },
282 { 0x0000a30c, 0x00204411, 0x000 },
283 { 0x00000000, 0x00204811, 0x000 },
284 { 0x0000001e, 0x00210e22, 0x000 },
285 { 0x00000000, 0x14c00000, 0x104 },
286 { 0x0000a30f, 0x00204411, 0x000 },
287 { 0x00000013, 0x00200e2d, 0x000 },
288 { 0x00000001, 0x002f0223, 0x000 },
289 { 0x00000000, 0x0cc00000, 0x0fd },
290 { 0xffffffff, 0x00404811, 0x104 },
291 { 0x00000002, 0x002f0223, 0x000 },
292 { 0x00000000, 0x0cc00000, 0x100 },
293 { 0x0000ffff, 0x00404811, 0x104 },
294 { 0x00000004, 0x002f0223, 0x000 },
295 { 0x00000000, 0x0cc00000, 0x103 },
296 { 0x000000ff, 0x00404811, 0x104 },
297 { 0x00000001, 0x00204811, 0x000 },
298 { 0x0002c400, 0x00204411, 0x000 },
299 { 0x0000001f, 0x00210e22, 0x000 },
300 { 0x00000000, 0x14c00000, 0x10b },
301 { 0x00000010, 0x40210e20, 0x000 },
302 { 0x00000019, 0x00203623, 0x000 },
303 { 0x00000018, 0x40224a20, 0x000 },
304 { 0x00000010, 0xc0424a20, 0x10d },
305 { 0x00000000, 0x00200c11, 0x000 },
306 { 0x00000019, 0x00203623, 0x000 },
307 { 0x00000000, 0x00204811, 0x000 },
308 { 0x00000000, 0x00204811, 0x000 },
309 { 0x0000000a, 0x00201011, 0x000 },
310 { 0x00000000, 0x002f0224, 0x000 },
311 { 0x00000000, 0x0ce00000, 0x114 },
312 { 0x00000000, 0x00204811, 0x000 },
313 { 0x00000001, 0x00531224, 0x110 },
314 { 0xffbfffff, 0x00283a2e, 0x000 },
315 { 0x0000001b, 0x00210222, 0x000 },
316 { 0x00000000, 0x14c00000, 0x127 },
317 { 0x81000000, 0x00204411, 0x000 },
318 { 0x0000000d, 0x00204811, 0x000 },
319 { 0x00000018, 0x00220e30, 0x000 },
320 { 0xfc000000, 0x00280e23, 0x000 },
321 { 0x81000000, 0x00204411, 0x000 },
322 { 0x0000000e, 0x00204811, 0x000 },
323 { 0x00000000, 0x00201010, 0x000 },
324 { 0x0000e00e, 0x00204411, 0x000 },
325 { 0x07f8ff08, 0x00204811, 0x000 },
326 { 0x00000000, 0x00294a23, 0x000 },
327 { 0x00000024, 0x00201e2d, 0x000 },
328 { 0x00000008, 0x00214a27, 0x000 },
329 { 0x00000000, 0x00204811, 0x000 },
330 { 0x060a0200, 0x00294a24, 0x000 },
331 { 0x00000000, 0x00204811, 0x000 },
332 { 0x00000000, 0x00204811, 0x000 },
333 { 0x00000000, 0x00800000, 0x000 },
334 { 0x81000000, 0x00204411, 0x000 },
335 { 0x00000001, 0x00204811, 0x000 },
336 { 0x0000217c, 0x00204411, 0x000 },
337 { 0x00800000, 0x00204811, 0x000 },
338 { 0x00000000, 0x00204806, 0x000 },
339 { 0x00000008, 0x00214a27, 0x000 },
340 { 0x00000000, 0x17000000, 0x000 },
341 { 0x0004217f, 0x00604411, 0x614 },
342 { 0x0000001f, 0x00210230, 0x000 },
343 { 0x00000000, 0x14c00000, 0x613 },
344 { 0x00000004, 0x00404c11, 0x12e },
345 { 0x00000000, 0x00600000, 0x00b },
346 { 0x00000000, 0x00600411, 0x2fe },
347 { 0x00000000, 0x00200411, 0x000 },
348 { 0x00000000, 0x00600811, 0x19f },
349 { 0x00000000, 0x00600000, 0x151 },
350 { 0x0000ffff, 0x40280e20, 0x000 },
351 { 0x00000010, 0xc0211220, 0x000 },
352 { 0x0000ffff, 0x40280620, 0x000 },
353 { 0x00000010, 0xc0210a20, 0x000 },
354 { 0x00000000, 0x00341461, 0x000 },
355 { 0x00000000, 0x00741882, 0x2a4 },
356 { 0x0001a1fd, 0x00604411, 0x2c9 },
357 { 0x00003fff, 0x002f022f, 0x000 },
358 { 0x00000000, 0x0cc00000, 0x138 },
359 { 0x00000000, 0xc0400400, 0x001 },
360 { 0x00000000, 0x00600000, 0x00b },
361 { 0x00000000, 0x00600411, 0x2fe },
362 { 0x00000000, 0x00200411, 0x000 },
363 { 0x00000000, 0x00600811, 0x19f },
364 { 0x00003fff, 0x002f022f, 0x000 },
365 { 0x00000000, 0x0ce00000, 0x000 },
366 { 0x00000000, 0x00600000, 0x151 },
367 { 0x00000010, 0x40210e20, 0x000 },
368 { 0x0000ffff, 0xc0281220, 0x000 },
369 { 0x00000010, 0x40211620, 0x000 },
370 { 0x0000ffff, 0xc0681a20, 0x2a4 },
371 { 0x0001a1fd, 0x00604411, 0x2c9 },
372 { 0x00003fff, 0x002f022f, 0x000 },
373 { 0x00000000, 0x0cc00000, 0x149 },
374 { 0x00000000, 0xc0400400, 0x001 },
375 { 0x0000225c, 0x00204411, 0x000 },
376 { 0x00000001, 0x00300a2f, 0x000 },
377 { 0x00000001, 0x00210a22, 0x000 },
378 { 0x00000003, 0x00384a22, 0x000 },
379 { 0x00002256, 0x00204411, 0x000 },
380 { 0x0000001a, 0x00204811, 0x000 },
381 { 0x0000a1fc, 0x00204411, 0x000 },
382 { 0x00000001, 0x00804811, 0x000 },
383 { 0x00000000, 0x00600000, 0x00b },
384 { 0x00000000, 0x00600000, 0x17c },
385 { 0x00000000, 0x00600000, 0x18d },
386 { 0x00003fff, 0x002f022f, 0x000 },
387 { 0x00000000, 0x0ce00000, 0x000 },
388 { 0x00000000, 0x00202c08, 0x000 },
389 { 0x00000000, 0x00202411, 0x000 },
390 { 0x00000000, 0x00202811, 0x000 },
391 { 0x00002256, 0x00204411, 0x000 },
392 { 0x00000016, 0x00204811, 0x000 },
393 { 0x0000225c, 0x00204411, 0x000 },
394 { 0x00000003, 0x00204811, 0x000 },
395 { 0x93800000, 0x00204411, 0x000 },
396 { 0x00000002, 0x00221e29, 0x000 },
397 { 0x00000000, 0x007048eb, 0x189 },
398 { 0x00000000, 0x00600000, 0x2a4 },
399 { 0x00000001, 0x40330620, 0x000 },
400 { 0x00000000, 0xc0302409, 0x000 },
401 { 0x00003fff, 0x002f022f, 0x000 },
402 { 0x00000000, 0x0ce00000, 0x000 },
403 { 0x00000000, 0x00600000, 0x28c },
404 { 0x95000000, 0x00204411, 0x000 },
405 { 0x00000000, 0x002f0221, 0x000 },
406 { 0x00000000, 0x0ce00000, 0x173 },
407 { 0x00000000, 0xc0204800, 0x000 },
408 { 0x00000001, 0x00530621, 0x16f },
409 { 0x92000000, 0x00204411, 0x000 },
410 { 0x00000000, 0xc0604800, 0x184 },
411 { 0x0001a1fd, 0x00204411, 0x000 },
412 { 0x00000013, 0x0020062d, 0x000 },
413 { 0x00000000, 0x0078042a, 0x2e4 },
414 { 0x00000000, 0x00202809, 0x000 },
415 { 0x00003fff, 0x002f022f, 0x000 },
416 { 0x00000000, 0x0cc00000, 0x165 },
417 { 0x00000000, 0xc0400400, 0x001 },
418 { 0x00000210, 0x00600411, 0x2fe },
419 { 0x00003fff, 0x002f022f, 0x000 },
420 { 0x00000000, 0x0ce00000, 0x181 },
421 { 0x0000001b, 0xc0203620, 0x000 },
422 { 0x0000001c, 0xc0203620, 0x000 },
423 { 0x3f800000, 0x00200411, 0x000 },
424 { 0x46000000, 0x00600811, 0x19f },
425 { 0x00000000, 0x00800000, 0x000 },
426 { 0x0000a1fc, 0x00204411, 0x000 },
427 { 0x00003fff, 0x002f022f, 0x000 },
428 { 0x00000000, 0x0cc00000, 0x188 },
429 { 0x00000001, 0x00804811, 0x000 },
430 { 0x00000021, 0x00804811, 0x000 },
431 { 0x0000ffff, 0x40280e20, 0x000 },
432 { 0x00000010, 0xc0211220, 0x000 },
433 { 0x0000ffff, 0x40281620, 0x000 },
434 { 0x00000010, 0xc0811a20, 0x000 },
435 { 0x81000000, 0x00204411, 0x000 },
436 { 0x00000006, 0x00204811, 0x000 },
437 { 0x00000008, 0x00221e30, 0x000 },
438 { 0x00000032, 0x00201a2d, 0x000 },
439 { 0x0000e000, 0x00204411, 0x000 },
440 { 0xfffbff09, 0x00204811, 0x000 },
441 { 0x00000011, 0x0020222d, 0x000 },
442 { 0x00001fff, 0x00294a28, 0x000 },
443 { 0x00000006, 0x0020222d, 0x000 },
444 { 0x00000000, 0x002920e8, 0x000 },
445 { 0x00000000, 0x00204808, 0x000 },
446 { 0x00000000, 0x00204811, 0x000 },
447 { 0x060a0200, 0x00294a26, 0x000 },
448 { 0x00000000, 0x00204811, 0x000 },
449 { 0x00000000, 0x00204811, 0x000 },
450 { 0x00000100, 0x00201811, 0x000 },
451 { 0x00000008, 0x00621e28, 0x128 },
452 { 0x00000008, 0x00822228, 0x000 },
453 { 0x0002c000, 0x00204411, 0x000 },
454 { 0x0000001b, 0x00600e2d, 0x1aa },
455 { 0x0000001c, 0x00600e2d, 0x1aa },
456 { 0x0000c008, 0x00204411, 0x000 },
457 { 0x0000001d, 0x00200e2d, 0x000 },
458 { 0x00000000, 0x14c00000, 0x1a6 },
459 { 0x00000000, 0x00200411, 0x000 },
460 { 0x00000000, 0x00204801, 0x000 },
461 { 0x39000000, 0x00204811, 0x000 },
462 { 0x00000000, 0x00204811, 0x000 },
463 { 0x00000000, 0x00804802, 0x000 },
464 { 0x00000020, 0x00202e2d, 0x000 },
465 { 0x00000000, 0x003b0d63, 0x000 },
466 { 0x00000008, 0x00224a23, 0x000 },
467 { 0x00000010, 0x00224a23, 0x000 },
468 { 0x00000018, 0x00224a23, 0x000 },
469 { 0x00000000, 0x00804803, 0x000 },
470 { 0x00000000, 0x00600000, 0x00b },
471 { 0x00001000, 0x00600411, 0x2fe },
472 { 0x00000000, 0x00200411, 0x000 },
473 { 0x00000000, 0x00600811, 0x19f },
474 { 0x00000007, 0x0021062f, 0x000 },
475 { 0x00000019, 0x00200a2d, 0x000 },
476 { 0x00000001, 0x00202c11, 0x000 },
477 { 0x0000ffff, 0x40282220, 0x000 },
478 { 0x0000000f, 0x00262228, 0x000 },
479 { 0x00000010, 0x40212620, 0x000 },
480 { 0x0000000f, 0x00262629, 0x000 },
481 { 0x00000000, 0x00202802, 0x000 },
482 { 0x00002256, 0x00204411, 0x000 },
483 { 0x0000001b, 0x00204811, 0x000 },
484 { 0x00000000, 0x002f0221, 0x000 },
485 { 0x00000000, 0x0ce00000, 0x1cd },
486 { 0x0000225c, 0x00204411, 0x000 },
487 { 0x00000081, 0x00204811, 0x000 },
488 { 0x0000a1fc, 0x00204411, 0x000 },
489 { 0x00000001, 0x00204811, 0x000 },
490 { 0x00000080, 0x00201c11, 0x000 },
491 { 0x00000000, 0x002f0227, 0x000 },
492 { 0x00000000, 0x0ce00000, 0x1c9 },
493 { 0x00000000, 0x00600000, 0x1d6 },
494 { 0x00000001, 0x00531e27, 0x1c5 },
495 { 0x00000001, 0x00202c11, 0x000 },
496 { 0x0000001f, 0x00280a22, 0x000 },
497 { 0x0000001f, 0x00282a2a, 0x000 },
498 { 0x00000001, 0x00530621, 0x1be },
499 { 0x0000225c, 0x00204411, 0x000 },
500 { 0x00000002, 0x00304a2f, 0x000 },
501 { 0x0000a1fc, 0x00204411, 0x000 },
502 { 0x00000001, 0x00204811, 0x000 },
503 { 0x00000001, 0x00301e2f, 0x000 },
504 { 0x00000000, 0x002f0227, 0x000 },
505 { 0x00000000, 0x0ce00000, 0x000 },
506 { 0x00000000, 0x00600000, 0x1d6 },
507 { 0x00000001, 0x00531e27, 0x1d2 },
508 { 0x0000ffff, 0x40280e20, 0x000 },
509 { 0x0000000f, 0x00260e23, 0x000 },
510 { 0x00000010, 0xc0211220, 0x000 },
511 { 0x0000000f, 0x00261224, 0x000 },
512 { 0x00000000, 0x00201411, 0x000 },
513 { 0x00000000, 0x00601811, 0x2a4 },
514 { 0x0001a1fd, 0x00204411, 0x000 },
515 { 0x00000000, 0x002f022b, 0x000 },
516 { 0x00000000, 0x0ce00000, 0x1e5 },
517 { 0x00000010, 0x00221628, 0x000 },
518 { 0xffff0000, 0x00281625, 0x000 },
519 { 0x0000ffff, 0x00281a29, 0x000 },
520 { 0x00000000, 0x002948c5, 0x000 },
521 { 0x00000000, 0x0020480a, 0x000 },
522 { 0x00000000, 0x00202c11, 0x000 },
523 { 0x00000010, 0x00221623, 0x000 },
524 { 0xffff0000, 0x00281625, 0x000 },
525 { 0x0000ffff, 0x00281a24, 0x000 },
526 { 0x00000000, 0x002948c5, 0x000 },
527 { 0x00000000, 0x00731503, 0x1f2 },
528 { 0x00000000, 0x00201805, 0x000 },
529 { 0x00000000, 0x00731524, 0x1f2 },
530 { 0x00000000, 0x002d14c5, 0x000 },
531 { 0x00000000, 0x003008a2, 0x000 },
532 { 0x00000000, 0x00204802, 0x000 },
533 { 0x00000000, 0x00202802, 0x000 },
534 { 0x00000000, 0x00202003, 0x000 },
535 { 0x00000000, 0x00802404, 0x000 },
536 { 0x0000000f, 0x00210225, 0x000 },
537 { 0x00000000, 0x14c00000, 0x613 },
538 { 0x00000000, 0x002b1405, 0x000 },
539 { 0x00000001, 0x00901625, 0x000 },
540 { 0x00000000, 0x00600000, 0x00b },
541 { 0x00000000, 0x00600411, 0x2fe },
542 { 0x00000000, 0x00200411, 0x000 },
543 { 0x00000000, 0x00600811, 0x19f },
544 { 0x00002256, 0x00204411, 0x000 },
545 { 0x0000001a, 0x00294a22, 0x000 },
546 { 0x00000000, 0xc0200000, 0x000 },
547 { 0x00003fff, 0x002f022f, 0x000 },
548 { 0x00000000, 0x0ce00000, 0x000 },
549 { 0x00000000, 0xc0200400, 0x000 },
550 { 0x0000225c, 0x00204411, 0x000 },
551 { 0x00000003, 0x00384a21, 0x000 },
552 { 0x0000a1fc, 0x00204411, 0x000 },
553 { 0x00000001, 0x00204811, 0x000 },
554 { 0x0000ffff, 0x40281220, 0x000 },
555 { 0x00000010, 0xc0211a20, 0x000 },
556 { 0x0000ffff, 0x40280e20, 0x000 },
557 { 0x00000010, 0xc0211620, 0x000 },
558 { 0x00000000, 0x00741465, 0x2a4 },
559 { 0x0001a1fd, 0x00604411, 0x2c9 },
560 { 0x00000001, 0x00330621, 0x000 },
561 { 0x00000000, 0x002f0221, 0x000 },
562 { 0x00000000, 0x0cc00000, 0x206 },
563 { 0x00003fff, 0x002f022f, 0x000 },
564 { 0x00000000, 0x0cc00000, 0x1ff },
565 { 0x00000000, 0xc0400400, 0x001 },
566 { 0x00000000, 0x00600000, 0x5c5 },
567 { 0x00000000, 0x0040040f, 0x200 },
568 { 0x00000000, 0x00600000, 0x5b2 },
569 { 0x00000000, 0x00600000, 0x5c5 },
570 { 0x00000210, 0x00600411, 0x2fe },
571 { 0x00000000, 0x00600000, 0x18d },
572 { 0x00000000, 0x00600000, 0x189 },
573 { 0x00000000, 0x00600000, 0x2a4 },
574 { 0x00000000, 0x00600000, 0x28c },
575 { 0x93800000, 0x00204411, 0x000 },
576 { 0x00000000, 0x00204808, 0x000 },
577 { 0x95000000, 0x00204411, 0x000 },
578 { 0x00000000, 0x002f022f, 0x000 },
579 { 0x00000000, 0x0ce00000, 0x21f },
580 { 0x00000000, 0xc0404800, 0x21c },
581 { 0x92000000, 0x00204411, 0x000 },
582 { 0x00000000, 0xc0204800, 0x000 },
583 { 0x00002256, 0x00204411, 0x000 },
584 { 0x00000016, 0x00204811, 0x000 },
585 { 0x0000225c, 0x00204411, 0x000 },
586 { 0x00000003, 0x00204811, 0x000 },
587 { 0x0000a1fc, 0x00204411, 0x000 },
588 { 0x00000001, 0x00204811, 0x000 },
589 { 0x0001a1fd, 0x00204411, 0x000 },
590 { 0x00000000, 0x00600411, 0x2e4 },
591 { 0x00000000, 0xc0400400, 0x001 },
592 { 0x00000000, 0x00600000, 0x5b2 },
593 { 0x0000a00c, 0x00204411, 0x000 },
594 { 0x00000000, 0xc0204800, 0x000 },
595 { 0x00000000, 0xc0404800, 0x000 },
596 { 0x00000000, 0x00600000, 0x00b },
597 { 0x00000018, 0x40210a20, 0x000 },
598 { 0x00000003, 0x002f0222, 0x000 },
599 { 0x00000000, 0x0ae00000, 0x235 },
600 { 0x0000001a, 0x0020222d, 0x000 },
601 { 0x00080101, 0x00292228, 0x000 },
602 { 0x0000001a, 0x00203628, 0x000 },
603 { 0x0000a30c, 0x00204411, 0x000 },
604 { 0x00000000, 0xc0204800, 0x000 },
605 { 0x00000000, 0xc0204800, 0x000 },
606 { 0x00000000, 0xc0404800, 0x23a },
607 { 0x00000000, 0x00600000, 0x00b },
608 { 0x00000010, 0x00600411, 0x2fe },
609 { 0x3f800000, 0x00200411, 0x000 },
610 { 0x00000000, 0x00600811, 0x19f },
611 { 0x0000225c, 0x00204411, 0x000 },
612 { 0x00000003, 0x00204811, 0x000 },
613 { 0x00000000, 0x00600000, 0x265 },
614 { 0x0000001d, 0x00201e2d, 0x000 },
615 { 0x00000001, 0x00211e27, 0x000 },
616 { 0x00000000, 0x14e00000, 0x253 },
617 { 0x00000018, 0x00201e2d, 0x000 },
618 { 0x0000ffff, 0x00281e27, 0x000 },
619 { 0x00000000, 0x00341c27, 0x000 },
620 { 0x00000000, 0x12c00000, 0x248 },
621 { 0x00000000, 0x00201c11, 0x000 },
622 { 0x00000000, 0x002f00e5, 0x000 },
623 { 0x00000000, 0x08c00000, 0x24b },
624 { 0x00000000, 0x00201407, 0x000 },
625 { 0x00000018, 0x00201e2d, 0x000 },
626 { 0x00000010, 0x00211e27, 0x000 },
627 { 0x00000000, 0x00341c47, 0x000 },
628 { 0x00000000, 0x12c00000, 0x250 },
629 { 0x00000000, 0x00201c11, 0x000 },
630 { 0x00000000, 0x002f00e6, 0x000 },
631 { 0x00000000, 0x08c00000, 0x253 },
632 { 0x00000000, 0x00201807, 0x000 },
633 { 0x00000000, 0x00600000, 0x2aa },
634 { 0x00002256, 0x00204411, 0x000 },
635 { 0x00000000, 0x00342023, 0x000 },
636 { 0x00000000, 0x12c00000, 0x25b },
637 { 0x00000000, 0x00342044, 0x000 },
638 { 0x00000000, 0x12c00000, 0x25a },
639 { 0x00000016, 0x00404811, 0x25f },
640 { 0x00000018, 0x00404811, 0x25f },
641 { 0x00000000, 0x00342044, 0x000 },
642 { 0x00000000, 0x12c00000, 0x25e },
643 { 0x00000017, 0x00404811, 0x25f },
644 { 0x00000019, 0x00204811, 0x000 },
645 { 0x0000a1fc, 0x00204411, 0x000 },
646 { 0x00000001, 0x00204811, 0x000 },
647 { 0x0001a1fd, 0x00604411, 0x2d2 },
648 { 0x00003fff, 0x002f022f, 0x000 },
649 { 0x00000000, 0x0cc00000, 0x23f },
650 { 0x00000000, 0xc0400400, 0x001 },
651 { 0x00000010, 0x40210620, 0x000 },
652 { 0x0000ffff, 0xc0280a20, 0x000 },
653 { 0x00000010, 0x40210e20, 0x000 },
654 { 0x0000ffff, 0xc0281220, 0x000 },
655 { 0x00000010, 0x40211620, 0x000 },
656 { 0x0000ffff, 0xc0881a20, 0x000 },
657 { 0x81000000, 0x00204411, 0x000 },
658 { 0x00000001, 0x00204811, 0x000 },
659 { 0x00042004, 0x00604411, 0x614 },
660 { 0x00000000, 0x00600000, 0x5b2 },
661 { 0x00000000, 0xc0600000, 0x28c },
662 { 0x00000005, 0x00200a2d, 0x000 },
663 { 0x00000008, 0x00220a22, 0x000 },
664 { 0x00000034, 0x00201a2d, 0x000 },
665 { 0x00000024, 0x00201e2d, 0x000 },
666 { 0x00007000, 0x00281e27, 0x000 },
667 { 0x00000000, 0x00311ce6, 0x000 },
668 { 0x00000033, 0x00201a2d, 0x000 },
669 { 0x0000000c, 0x00221a26, 0x000 },
670 { 0x00000000, 0x002f00e6, 0x000 },
671 { 0x00000000, 0x06e00000, 0x27b },
672 { 0x00000000, 0x00201c11, 0x000 },
673 { 0x00000000, 0x00200c11, 0x000 },
674 { 0x00000034, 0x00203623, 0x000 },
675 { 0x00000010, 0x00201811, 0x000 },
676 { 0x00000000, 0x00691ce2, 0x128 },
677 { 0x93800000, 0x00204411, 0x000 },
678 { 0x00000000, 0x00204807, 0x000 },
679 { 0x95000000, 0x00204411, 0x000 },
680 { 0x00000000, 0x002f022f, 0x000 },
681 { 0x00000000, 0x0ce00000, 0x286 },
682 { 0x00000001, 0x00333e2f, 0x000 },
683 { 0x00000000, 0xd9004800, 0x000 },
684 { 0x92000000, 0x00204411, 0x000 },
685 { 0x00000000, 0xc0204800, 0x000 },
686 { 0x00000024, 0x00403627, 0x000 },
687 { 0x0000000c, 0xc0220a20, 0x000 },
688 { 0x00000032, 0x00203622, 0x000 },
689 { 0x00000031, 0xc0403620, 0x000 },
690 { 0x0000a2a4, 0x00204411, 0x000 },
691 { 0x00000009, 0x00204811, 0x000 },
692 { 0xa1000000, 0x00204411, 0x000 },
693 { 0x00000001, 0x00804811, 0x000 },
694 { 0x00000029, 0x00201e2d, 0x000 },
695 { 0x00000000, 0x002c1ce3, 0x000 },
696 { 0x00000029, 0x00203627, 0x000 },
697 { 0x0000002a, 0x00201e2d, 0x000 },
698 { 0x00000000, 0x002c1ce4, 0x000 },
699 { 0x0000002a, 0x00203627, 0x000 },
700 { 0x0000002b, 0x00201e2d, 0x000 },
701 { 0x00000000, 0x003120a3, 0x000 },
702 { 0x00000000, 0x002d1d07, 0x000 },
703 { 0x0000002b, 0x00203627, 0x000 },
704 { 0x0000002c, 0x00201e2d, 0x000 },
705 { 0x00000000, 0x003120c4, 0x000 },
706 { 0x00000000, 0x002d1d07, 0x000 },
707 { 0x0000002c, 0x00803627, 0x000 },
708 { 0x00000029, 0x00203623, 0x000 },
709 { 0x0000002a, 0x00203624, 0x000 },
710 { 0x00000000, 0x00311ca3, 0x000 },
711 { 0x0000002b, 0x00203627, 0x000 },
712 { 0x00000000, 0x00311cc4, 0x000 },
713 { 0x0000002c, 0x00803627, 0x000 },
714 { 0x00000022, 0x00203627, 0x000 },
715 { 0x00000023, 0x00203628, 0x000 },
716 { 0x0000001d, 0x00201e2d, 0x000 },
717 { 0x00000002, 0x00210227, 0x000 },
718 { 0x00000000, 0x14c00000, 0x2c5 },
719 { 0x00000000, 0x00400000, 0x2c2 },
720 { 0x00000022, 0x00203627, 0x000 },
721 { 0x00000023, 0x00203628, 0x000 },
722 { 0x0000001d, 0x00201e2d, 0x000 },
723 { 0x00000002, 0x00210227, 0x000 },
724 { 0x00000000, 0x14e00000, 0x2c2 },
725 { 0x00000003, 0x00210227, 0x000 },
726 { 0x00000000, 0x14e00000, 0x2c5 },
727 { 0x0000002b, 0x00201e2d, 0x000 },
728 { 0x00000000, 0x002e00e1, 0x000 },
729 { 0x00000000, 0x02c00000, 0x2c5 },
730 { 0x00000029, 0x00201e2d, 0x000 },
731 { 0x00000000, 0x003120a1, 0x000 },
732 { 0x00000000, 0x002e00e8, 0x000 },
733 { 0x00000000, 0x06c00000, 0x2c5 },
734 { 0x0000002c, 0x00201e2d, 0x000 },
735 { 0x00000000, 0x002e00e2, 0x000 },
736 { 0x00000000, 0x02c00000, 0x2c5 },
737 { 0x0000002a, 0x00201e2d, 0x000 },
738 { 0x00000000, 0x003120c2, 0x000 },
739 { 0x00000000, 0x002e00e8, 0x000 },
740 { 0x00000000, 0x06c00000, 0x2c5 },
741 { 0x00000000, 0x00600000, 0x5ed },
742 { 0x00000000, 0x00600000, 0x29e },
743 { 0x00000000, 0x00400000, 0x2c7 },
744 { 0x00000000, 0x00600000, 0x29e },
745 { 0x00000000, 0x00600000, 0x5e4 },
746 { 0x00000000, 0x00400000, 0x2c7 },
747 { 0x00000000, 0x00600000, 0x290 },
748 { 0x00000000, 0x00400000, 0x2c7 },
749 { 0x00000022, 0x00201e2d, 0x000 },
750 { 0x00000023, 0x0080222d, 0x000 },
751 { 0x00000010, 0x00221e23, 0x000 },
752 { 0x00000000, 0x00294887, 0x000 },
753 { 0x00000000, 0x00311ca3, 0x000 },
754 { 0x00000010, 0x00221e27, 0x000 },
755 { 0x00000000, 0x00294887, 0x000 },
756 { 0x00000010, 0x00221e23, 0x000 },
757 { 0x00000000, 0x003120c4, 0x000 },
758 { 0x0000ffff, 0x00282228, 0x000 },
759 { 0x00000000, 0x00894907, 0x000 },
760 { 0x00000010, 0x00221e23, 0x000 },
761 { 0x00000000, 0x00294887, 0x000 },
762 { 0x00000010, 0x00221e21, 0x000 },
763 { 0x00000000, 0x00294847, 0x000 },
764 { 0x00000000, 0x00311ca3, 0x000 },
765 { 0x00000010, 0x00221e27, 0x000 },
766 { 0x00000000, 0x00294887, 0x000 },
767 { 0x00000000, 0x00311ca1, 0x000 },
768 { 0x00000010, 0x00221e27, 0x000 },
769 { 0x00000000, 0x00294847, 0x000 },
770 { 0x00000010, 0x00221e23, 0x000 },
771 { 0x00000000, 0x003120c4, 0x000 },
772 { 0x0000ffff, 0x00282228, 0x000 },
773 { 0x00000000, 0x00294907, 0x000 },
774 { 0x00000010, 0x00221e21, 0x000 },
775 { 0x00000000, 0x003120c2, 0x000 },
776 { 0x0000ffff, 0x00282228, 0x000 },
777 { 0x00000000, 0x00894907, 0x000 },
778 { 0x00000010, 0x00221e23, 0x000 },
779 { 0x00000000, 0x00294887, 0x000 },
780 { 0x00000001, 0x00220a21, 0x000 },
781 { 0x00000000, 0x003308a2, 0x000 },
782 { 0x00000010, 0x00221e22, 0x000 },
783 { 0x00000010, 0x00212222, 0x000 },
784 { 0x00000000, 0x00294907, 0x000 },
785 { 0x00000000, 0x00311ca3, 0x000 },
786 { 0x00000010, 0x00221e27, 0x000 },
787 { 0x00000000, 0x00294887, 0x000 },
788 { 0x00000001, 0x00220a21, 0x000 },
789 { 0x00000000, 0x003008a2, 0x000 },
790 { 0x00000010, 0x00221e22, 0x000 },
791 { 0x00000010, 0x00212222, 0x000 },
792 { 0x00000000, 0x00294907, 0x000 },
793 { 0x00000010, 0x00221e23, 0x000 },
794 { 0x00000000, 0x003120c4, 0x000 },
795 { 0x0000ffff, 0x00282228, 0x000 },
796 { 0x00000000, 0x00294907, 0x000 },
797 { 0x00000000, 0x003808c5, 0x000 },
798 { 0x00000000, 0x00300841, 0x000 },
799 { 0x00000001, 0x00220a22, 0x000 },
800 { 0x00000000, 0x003308a2, 0x000 },
801 { 0x00000010, 0x00221e22, 0x000 },
802 { 0x00000010, 0x00212222, 0x000 },
803 { 0x00000000, 0x00894907, 0x000 },
804 { 0x0000001d, 0x0020222d, 0x000 },
805 { 0x00000000, 0x14c00000, 0x301 },
806 { 0xffffffef, 0x00280621, 0x000 },
807 { 0x0000001a, 0x0020222d, 0x000 },
808 { 0x0000f8e0, 0x00204411, 0x000 },
809 { 0x00000000, 0x00294901, 0x000 },
810 { 0x00000000, 0x00894901, 0x000 },
811 { 0x00000000, 0x00204811, 0x000 },
812 { 0x00000000, 0x00204811, 0x000 },
813 { 0x060a0200, 0x00804811, 0x000 },
814 { 0x00000000, 0xc0200000, 0x000 },
815 { 0x97000000, 0xc0204411, 0x000 },
816 { 0x00000000, 0xc0204811, 0x000 },
817 { 0x8a000000, 0x00204411, 0x000 },
818 { 0x00000000, 0x00204811, 0x000 },
819 { 0x0000225c, 0x00204411, 0x000 },
820 { 0x00000000, 0xc0204800, 0x000 },
821 { 0x0000a1fc, 0x00204411, 0x000 },
822 { 0x00000000, 0xc0204800, 0x000 },
823 { 0x00000000, 0xc0200400, 0x000 },
824 { 0x00000000, 0x00a0000a, 0x000 },
825 { 0x97000000, 0x00204411, 0x000 },
826 { 0x00000000, 0x00204811, 0x000 },
827 { 0x8a000000, 0x00204411, 0x000 },
828 { 0x00000000, 0x00204811, 0x000 },
829 { 0x0000225c, 0x00204411, 0x000 },
830 { 0x00000000, 0xc0204800, 0x000 },
831 { 0x0000a1fc, 0x00204411, 0x000 },
832 { 0x00000000, 0xc0204800, 0x000 },
833 { 0x00000000, 0xc0200400, 0x000 },
834 { 0x00000000, 0x00a0000a, 0x000 },
835 { 0x97000000, 0x00204411, 0x000 },
836 { 0x00000000, 0x00204811, 0x000 },
837 { 0x8a000000, 0x00204411, 0x000 },
838 { 0x00000000, 0x00204811, 0x000 },
839 { 0x0000225c, 0x00204411, 0x000 },
840 { 0x00000000, 0xc0204800, 0x000 },
841 { 0x0000a1fc, 0x00204411, 0x000 },
842 { 0x00000000, 0xc0204800, 0x000 },
843 { 0x0001a1fd, 0x00204411, 0x000 },
844 { 0x00000000, 0xd9004800, 0x000 },
845 { 0x00000000, 0xc0200400, 0x000 },
846 { 0x00000000, 0x00a0000a, 0x000 },
847 { 0x00002257, 0x00204411, 0x000 },
848 { 0x00000003, 0xc0484a20, 0x000 },
849 { 0x0000225d, 0x00204411, 0x000 },
850 { 0x00000000, 0xc0404800, 0x000 },
851 { 0x00000000, 0x00600000, 0x5c5 },
852 { 0x00000000, 0xc0200800, 0x000 },
853 { 0x0000225c, 0x00204411, 0x000 },
854 { 0x00000003, 0x00384a22, 0x000 },
855 { 0x0000a1fc, 0x00204411, 0x000 },
856 { 0x00000000, 0xc0204800, 0x000 },
857 { 0x0001a1fd, 0x00204411, 0x000 },
858 { 0x00000000, 0x002f0222, 0x000 },
859 { 0x00000000, 0x0ce00000, 0x000 },
860 { 0x00000000, 0x40204800, 0x000 },
861 { 0x00000001, 0x40304a20, 0x000 },
862 { 0x00000002, 0xc0304a20, 0x000 },
863 { 0x00000001, 0x00530a22, 0x334 },
864 { 0x0000003f, 0xc0280a20, 0x000 },
865 { 0x81000000, 0x00204411, 0x000 },
866 { 0x00000001, 0x00204811, 0x000 },
867 { 0x000021f8, 0x00204411, 0x000 },
868 { 0x00000017, 0x00204811, 0x000 },
869 { 0x000421f9, 0x00604411, 0x614 },
870 { 0x00000011, 0x00210230, 0x000 },
871 { 0x00000000, 0x14e00000, 0x33d },
872 { 0x00000014, 0x002f0222, 0x000 },
873 { 0x00000000, 0x0cc00000, 0x351 },
874 { 0x00002010, 0x00204411, 0x000 },
875 { 0x00008000, 0x00204811, 0x000 },
876 { 0x0001a2a4, 0x00204411, 0x000 },
877 { 0x00000000, 0x00204811, 0x000 },
878 { 0x00000016, 0x00604811, 0x35e },
879 { 0x00002100, 0x00204411, 0x000 },
880 { 0x00000000, 0xc0204800, 0x000 },
881 { 0x00000000, 0xc0204800, 0x000 },
882 { 0x00000000, 0xc0204800, 0x000 },
883 { 0x00000000, 0xc0204800, 0x000 },
884 { 0x0001a2a4, 0x00204411, 0x000 },
885 { 0x00000000, 0x00204811, 0x000 },
886 { 0x00000000, 0x00404802, 0x000 },
887 { 0x00000004, 0x002f0222, 0x000 },
888 { 0x00000000, 0x0cc00000, 0x355 },
889 { 0x00002010, 0x00204411, 0x000 },
890 { 0x00008000, 0x00404811, 0x349 },
891 { 0x00000028, 0x002f0222, 0x000 },
892 { 0x00000000, 0x0ce00000, 0x349 },
893 { 0x00002104, 0x00204411, 0x000 },
894 { 0x00000000, 0xc0204800, 0x000 },
895 { 0x00000000, 0xc0204800, 0x000 },
896 { 0x00000000, 0xc0204800, 0x000 },
897 { 0x00000000, 0xc0204800, 0x000 },
898 { 0x0000a2a4, 0x00204411, 0x000 },
899 { 0x00000000, 0x00404802, 0x000 },
900 { 0x00000035, 0x00203626, 0x000 },
901 { 0x00000049, 0x00201811, 0x000 },
902 { 0x00000000, 0x00204811, 0x000 },
903 { 0x00000001, 0x00331a26, 0x000 },
904 { 0x00000000, 0x002f0226, 0x000 },
905 { 0x00000000, 0x0cc00000, 0x360 },
906 { 0x00000035, 0x00801a2d, 0x000 },
907 { 0x0000003f, 0xc0280a20, 0x000 },
908 { 0x00000015, 0x002f0222, 0x000 },
909 { 0x00000000, 0x0ce00000, 0x376 },
910 { 0x0000001e, 0x002f0222, 0x000 },
911 { 0x00000000, 0x0ce00000, 0x380 },
912 { 0x00000020, 0x002f0222, 0x000 },
913 { 0x00000000, 0x0ce00000, 0x38c },
914 { 0x0000000f, 0x002f0222, 0x000 },
915 { 0x00000000, 0x0ce00000, 0x398 },
916 { 0x00000010, 0x002f0222, 0x000 },
917 { 0x00000000, 0x0ce00000, 0x398 },
918 { 0x00000006, 0x002f0222, 0x000 },
919 { 0x00000000, 0x0ce00000, 0x39a },
920 { 0x00000016, 0x002f0222, 0x000 },
921 { 0x00000000, 0x0ce00000, 0x39f },
922 { 0x0000a2a4, 0x00204411, 0x000 },
923 { 0x00000000, 0x00404802, 0x000 },
924 { 0x08000000, 0x00290a22, 0x000 },
925 { 0x00000003, 0x40210e20, 0x000 },
926 { 0x0000000c, 0xc0211220, 0x000 },
927 { 0x00080000, 0x00281224, 0x000 },
928 { 0x00000014, 0xc0221620, 0x000 },
929 { 0x00000000, 0x002914a4, 0x000 },
930 { 0x0000a2a4, 0x00204411, 0x000 },
931 { 0x00000000, 0x002948a2, 0x000 },
932 { 0x0000a1fe, 0x00204411, 0x000 },
933 { 0x00000000, 0x00404803, 0x000 },
934 { 0x81000000, 0x00204411, 0x000 },
935 { 0x00000001, 0x00204811, 0x000 },
936 { 0x000021f8, 0x00204411, 0x000 },
937 { 0x00000015, 0x00204811, 0x000 },
938 { 0x000421f9, 0x00604411, 0x614 },
939 { 0x00000015, 0x00210230, 0x000 },
940 { 0x00000000, 0x14e00000, 0x382 },
941 { 0x0000210e, 0x00204411, 0x000 },
942 { 0x00000000, 0xc0204800, 0x000 },
943 { 0x00000000, 0xc0204800, 0x000 },
944 { 0x0000a2a4, 0x00204411, 0x000 },
945 { 0x00000000, 0x00404802, 0x000 },
946 { 0x81000000, 0x00204411, 0x000 },
947 { 0x00000001, 0x00204811, 0x000 },
948 { 0x000021f8, 0x00204411, 0x000 },
949 { 0x00000016, 0x00204811, 0x000 },
950 { 0x000421f9, 0x00604411, 0x614 },
951 { 0x00000003, 0x00210230, 0x000 },
952 { 0x00000000, 0x14e00000, 0x38e },
953 { 0x00002108, 0x00204411, 0x000 },
954 { 0x00000000, 0xc0204800, 0x000 },
955 { 0x00000000, 0xc0204800, 0x000 },
956 { 0x0000a2a4, 0x00204411, 0x000 },
957 { 0x00000000, 0x00404802, 0x000 },
958 { 0x00002010, 0x00204411, 0x000 },
959 { 0x00008000, 0x00404811, 0x000 },
960 { 0x00002010, 0x00204411, 0x000 },
961 { 0x00008000, 0x00204811, 0x000 },
962 { 0x0001a2a4, 0x00204411, 0x000 },
963 { 0x00000000, 0x00204811, 0x000 },
964 { 0x00000006, 0x00404811, 0x000 },
965 { 0x00002010, 0x00204411, 0x000 },
966 { 0x00008000, 0x00204811, 0x000 },
967 { 0x0001a2a4, 0x00204411, 0x000 },
968 { 0x00000000, 0x00204811, 0x000 },
969 { 0x00000016, 0x00604811, 0x35e },
970 { 0x00000016, 0x00404811, 0x000 },
971 { 0x00000000, 0xc0200800, 0x000 },
972 { 0x00000000, 0xc0200c00, 0x000 },
973 { 0x0000001d, 0x00210223, 0x000 },
974 { 0x00000000, 0x14e00000, 0x3b9 },
975 { 0x81000000, 0x00204411, 0x000 },
976 { 0x00000001, 0x00204811, 0x000 },
977 { 0x000021f8, 0x00204411, 0x000 },
978 { 0x00000017, 0x00204811, 0x000 },
979 { 0x000421f9, 0x00604411, 0x614 },
980 { 0x00000011, 0x00210230, 0x000 },
981 { 0x00000000, 0x14e00000, 0x3ab },
982 { 0x00002100, 0x00204411, 0x000 },
983 { 0x00000000, 0x00204802, 0x000 },
984 { 0x00000000, 0x00204803, 0x000 },
985 { 0xbabecafe, 0x00204811, 0x000 },
986 { 0xcafebabe, 0x00204811, 0x000 },
987 { 0x00002010, 0x00204411, 0x000 },
988 { 0x00008000, 0x00204811, 0x000 },
989 { 0x0000a2a4, 0x00204411, 0x000 },
990 { 0x00000004, 0x00404811, 0x000 },
991 { 0x00002170, 0x00204411, 0x000 },
992 { 0x00000000, 0x00204802, 0x000 },
993 { 0x00000000, 0x00204803, 0x000 },
994 { 0x81000000, 0x00204411, 0x000 },
995 { 0x0000000a, 0x00204811, 0x000 },
996 { 0x00000000, 0x00200010, 0x000 },
997 { 0x00000000, 0x14c00000, 0x3be },
998 { 0x8c000000, 0x00204411, 0x000 },
999 { 0xcafebabe, 0x00404811, 0x000 },
1000 { 0x81000000, 0x00204411, 0x000 },
1001 { 0x00000001, 0x00204811, 0x000 },
1002 { 0x00003fff, 0x40280a20, 0x000 },
1003 { 0x80000000, 0x40280e20, 0x000 },
1004 { 0x40000000, 0xc0281220, 0x000 },
1005 { 0x00040000, 0x00694622, 0x614 },
1006 { 0x00000000, 0x00201410, 0x000 },
1007 { 0x00000000, 0x002f0223, 0x000 },
1008 { 0x00000000, 0x0cc00000, 0x3cc },
1009 { 0x00000000, 0xc0401800, 0x3cf },
1010 { 0x00003fff, 0xc0281a20, 0x000 },
1011 { 0x00040000, 0x00694626, 0x614 },
1012 { 0x00000000, 0x00201810, 0x000 },
1013 { 0x00000000, 0x002f0224, 0x000 },
1014 { 0x00000000, 0x0cc00000, 0x3d2 },
1015 { 0x00000000, 0xc0401c00, 0x3d5 },
1016 { 0x00003fff, 0xc0281e20, 0x000 },
1017 { 0x00040000, 0x00694627, 0x614 },
1018 { 0x00000000, 0x00201c10, 0x000 },
1019 { 0x00000000, 0x00204402, 0x000 },
1020 { 0x00000000, 0x002820c5, 0x000 },
1021 { 0x00000000, 0x004948e8, 0x000 },
1022 { 0xa5800000, 0x00200811, 0x000 },
1023 { 0x00002000, 0x00200c11, 0x000 },
1024 { 0x83000000, 0x00604411, 0x3fd },
1025 { 0x00000000, 0x00204402, 0x000 },
1026 { 0x00000000, 0xc0204800, 0x000 },
1027 { 0x00000000, 0x40204800, 0x000 },
1028 { 0x0000001f, 0xc0210220, 0x000 },
1029 { 0x00000000, 0x14c00000, 0x3e2 },
1030 { 0x00002010, 0x00204411, 0x000 },
1031 { 0x00008000, 0x00204811, 0x000 },
1032 { 0x0000ffff, 0xc0481220, 0x3ea },
1033 { 0xa7800000, 0x00200811, 0x000 },
1034 { 0x0000a000, 0x00200c11, 0x000 },
1035 { 0x83000000, 0x00604411, 0x3fd },
1036 { 0x00000000, 0x00204402, 0x000 },
1037 { 0x00000000, 0xc0204800, 0x000 },
1038 { 0x00000000, 0xc0204800, 0x000 },
1039 { 0x0000ffff, 0xc0281220, 0x000 },
1040 { 0x83000000, 0x00204411, 0x000 },
1041 { 0x00000000, 0x00304883, 0x000 },
1042 { 0x84000000, 0x00204411, 0x000 },
1043 { 0x00000000, 0xc0204800, 0x000 },
1044 { 0x00000000, 0x1d000000, 0x000 },
1045 { 0x83000000, 0x00604411, 0x3fd },
1046 { 0x00000000, 0xc0400400, 0x001 },
1047 { 0xa9800000, 0x00200811, 0x000 },
1048 { 0x0000c000, 0x00400c11, 0x3e5 },
1049 { 0xab800000, 0x00200811, 0x000 },
1050 { 0x0000f8e0, 0x00400c11, 0x3e5 },
1051 { 0xad800000, 0x00200811, 0x000 },
1052 { 0x0000f880, 0x00400c11, 0x3e5 },
1053 { 0xb3800000, 0x00200811, 0x000 },
1054 { 0x0000f3fc, 0x00400c11, 0x3e5 },
1055 { 0xaf800000, 0x00200811, 0x000 },
1056 { 0x0000e000, 0x00400c11, 0x3e5 },
1057 { 0xb1800000, 0x00200811, 0x000 },
1058 { 0x0000f000, 0x00400c11, 0x3e5 },
1059 { 0x83000000, 0x00204411, 0x000 },
1060 { 0x00002148, 0x00204811, 0x000 },
1061 { 0x84000000, 0x00204411, 0x000 },
1062 { 0x00000000, 0xc0204800, 0x000 },
1063 { 0x00000000, 0x1d000000, 0x000 },
1064 { 0x00000000, 0x00800000, 0x000 },
1065 { 0x00182000, 0xc0304620, 0x000 },
1066 { 0x00000000, 0xd9004800, 0x000 },
1067 { 0x00000000, 0xc0200400, 0x000 },
1068 { 0x00000000, 0x00a0000a, 0x000 },
1069 { 0x0018a000, 0xc0304620, 0x000 },
1070 { 0x00000000, 0xd9004800, 0x000 },
1071 { 0x00000000, 0xc0200400, 0x000 },
1072 { 0x00000000, 0x00a0000a, 0x000 },
1073 { 0x0018c000, 0xc0304620, 0x000 },
1074 { 0x00000000, 0xd9004800, 0x000 },
1075 { 0x00000000, 0xc0200400, 0x000 },
1076 { 0x00000000, 0x00a0000a, 0x000 },
1077 { 0x0018f8e0, 0xc0304620, 0x000 },
1078 { 0x00000000, 0xd9004800, 0x000 },
1079 { 0x00000000, 0xc0200400, 0x000 },
1080 { 0x00000000, 0x00a0000a, 0x000 },
1081 { 0x0018f880, 0xc0304620, 0x000 },
1082 { 0x00000000, 0xd9004800, 0x000 },
1083 { 0x00000000, 0xc0200400, 0x000 },
1084 { 0x00000000, 0x00a0000a, 0x000 },
1085 { 0x0018e000, 0xc0304620, 0x000 },
1086 { 0x00000000, 0xd9004800, 0x000 },
1087 { 0x00000000, 0xc0200400, 0x000 },
1088 { 0x00000000, 0x00a0000a, 0x000 },
1089 { 0x0018f000, 0xc0304620, 0x000 },
1090 { 0x00000000, 0xd9004800, 0x000 },
1091 { 0x00000000, 0xc0200400, 0x000 },
1092 { 0x00000000, 0x00a0000a, 0x000 },
1093 { 0x0018f3fc, 0xc0304620, 0x000 },
1094 { 0x00000000, 0xd9004800, 0x000 },
1095 { 0x00000000, 0xc0200400, 0x000 },
1096 { 0x00000000, 0x00a0000a, 0x000 },
1097 { 0x86000000, 0x00204411, 0x000 },
1098 { 0x00000000, 0x00404801, 0x000 },
1099 { 0x85000000, 0x00204411, 0x000 },
1100 { 0x00000000, 0x00404801, 0x000 },
1101 { 0x0000217c, 0x00204411, 0x000 },
1102 { 0x00000000, 0xc0204800, 0x000 },
1103 { 0x00000000, 0xc0204800, 0x000 },
1104 { 0x00000000, 0xc0204800, 0x000 },
1105 { 0x81000000, 0x00204411, 0x000 },
1106 { 0x00000001, 0x00204811, 0x000 },
1107 { 0x00000000, 0xc0200800, 0x000 },
1108 { 0x00000000, 0x17000000, 0x000 },
1109 { 0x0004217f, 0x00604411, 0x614 },
1110 { 0x0000001f, 0x00210230, 0x000 },
1111 { 0x00000000, 0x14c00000, 0x000 },
1112 { 0x00000000, 0x00404c02, 0x42e },
1113 { 0x00000000, 0xc0200c00, 0x000 },
1114 { 0x00000000, 0xc0201000, 0x000 },
1115 { 0x00000000, 0xc0201400, 0x000 },
1116 { 0x00000000, 0xc0201800, 0x000 },
1117 { 0x00000000, 0xc0201c00, 0x000 },
1118 { 0x00007f00, 0x00280a21, 0x000 },
1119 { 0x00004500, 0x002f0222, 0x000 },
1120 { 0x00000000, 0x0ce00000, 0x43c },
1121 { 0x00000000, 0xc0202000, 0x000 },
1122 { 0x00000000, 0x17000000, 0x000 },
1123 { 0x00000010, 0x00280a23, 0x000 },
1124 { 0x00000010, 0x002f0222, 0x000 },
1125 { 0x00000000, 0x0ce00000, 0x444 },
1126 { 0x81000000, 0x00204411, 0x000 },
1127 { 0x00000001, 0x00204811, 0x000 },
1128 { 0x00040000, 0x00694624, 0x614 },
1129 { 0x00000000, 0x00400000, 0x44d },
1130 { 0x81000000, 0x00204411, 0x000 },
1131 { 0x00000000, 0x00204811, 0x000 },
1132 { 0x0000216d, 0x00204411, 0x000 },
1133 { 0x00000000, 0x00204804, 0x000 },
1134 { 0x00000000, 0x00204805, 0x000 },
1135 { 0x00000000, 0x1ac00000, 0x449 },
1136 { 0x9e000000, 0x00204411, 0x000 },
1137 { 0xcafebabe, 0x00204811, 0x000 },
1138 { 0x00000000, 0x1ae00000, 0x44c },
1139 { 0x00000000, 0x002824f0, 0x000 },
1140 { 0x00000007, 0x00280a23, 0x000 },
1141 { 0x00000001, 0x002f0222, 0x000 },
1142 { 0x00000000, 0x0ae00000, 0x454 },
1143 { 0x00000000, 0x002f00c9, 0x000 },
1144 { 0x00000000, 0x04e00000, 0x46d },
1145 { 0x00000000, 0x00400000, 0x47a },
1146 { 0x00000002, 0x002f0222, 0x000 },
1147 { 0x00000000, 0x0ae00000, 0x459 },
1148 { 0x00000000, 0x002f00c9, 0x000 },
1149 { 0x00000000, 0x02e00000, 0x46d },
1150 { 0x00000000, 0x00400000, 0x47a },
1151 { 0x00000003, 0x002f0222, 0x000 },
1152 { 0x00000000, 0x0ae00000, 0x45e },
1153 { 0x00000000, 0x002f00c9, 0x000 },
1154 { 0x00000000, 0x0ce00000, 0x46d },
1155 { 0x00000000, 0x00400000, 0x47a },
1156 { 0x00000004, 0x002f0222, 0x000 },
1157 { 0x00000000, 0x0ae00000, 0x463 },
1158 { 0x00000000, 0x002f00c9, 0x000 },
1159 { 0x00000000, 0x0ae00000, 0x46d },
1160 { 0x00000000, 0x00400000, 0x47a },
1161 { 0x00000005, 0x002f0222, 0x000 },
1162 { 0x00000000, 0x0ae00000, 0x468 },
1163 { 0x00000000, 0x002f00c9, 0x000 },
1164 { 0x00000000, 0x06e00000, 0x46d },
1165 { 0x00000000, 0x00400000, 0x47a },
1166 { 0x00000006, 0x002f0222, 0x000 },
1167 { 0x00000000, 0x0ae00000, 0x46d },
1168 { 0x00000000, 0x002f00c9, 0x000 },
1169 { 0x00000000, 0x08e00000, 0x46d },
1170 { 0x00000000, 0x00400000, 0x47a },
1171 { 0x00007f00, 0x00280a21, 0x000 },
1172 { 0x00004500, 0x002f0222, 0x000 },
1173 { 0x00000000, 0x0ae00000, 0x000 },
1174 { 0x00000008, 0x00210a23, 0x000 },
1175 { 0x00000000, 0x14c00000, 0x477 },
1176 { 0x00002169, 0x00204411, 0x000 },
1177 { 0x00000000, 0xc0204800, 0x000 },
1178 { 0x00000000, 0xc0204800, 0x000 },
1179 { 0x00000000, 0xc0204800, 0x000 },
1180 { 0xcafebabe, 0x00404811, 0x000 },
1181 { 0x00000000, 0xc0204400, 0x000 },
1182 { 0x00000000, 0xc0200000, 0x000 },
1183 { 0x00000000, 0xc0404800, 0x000 },
1184 { 0x00007f00, 0x00280a21, 0x000 },
1185 { 0x00004500, 0x002f0222, 0x000 },
1186 { 0x00000000, 0x0ae00000, 0x480 },
1187 { 0x00000000, 0xc0200000, 0x000 },
1188 { 0x00000000, 0xc0200000, 0x000 },
1189 { 0x00000000, 0xc0400000, 0x000 },
1190 { 0x00000000, 0x00404c08, 0x43c },
1191 { 0x00000000, 0xc0200800, 0x000 },
1192 { 0x00000010, 0x40210e20, 0x000 },
1193 { 0x00000011, 0x40211220, 0x000 },
1194 { 0x00000012, 0x40211620, 0x000 },
1195 { 0x00002169, 0x00204411, 0x000 },
1196 { 0x00000000, 0x00204802, 0x000 },
1197 { 0x00000000, 0x00210225, 0x000 },
1198 { 0x00000000, 0x14e00000, 0x48a },
1199 { 0x00040000, 0xc0494a20, 0x48b },
1200 { 0xfffbffff, 0xc0284a20, 0x000 },
1201 { 0x00000000, 0x00210223, 0x000 },
1202 { 0x00000000, 0x14e00000, 0x497 },
1203 { 0x00000000, 0xc0204800, 0x000 },
1204 { 0x00000000, 0xc0204800, 0x000 },
1205 { 0x00000000, 0x00210224, 0x000 },
1206 { 0x00000000, 0x14c00000, 0x000 },
1207 { 0x81000000, 0x00204411, 0x000 },
1208 { 0x0000000c, 0x00204811, 0x000 },
1209 { 0x00000000, 0x00200010, 0x000 },
1210 { 0x00000000, 0x14c00000, 0x493 },
1211 { 0xa0000000, 0x00204411, 0x000 },
1212 { 0xcafebabe, 0x00404811, 0x000 },
1213 { 0x81000000, 0x00204411, 0x000 },
1214 { 0x00000004, 0x00204811, 0x000 },
1215 { 0x0000216b, 0x00204411, 0x000 },
1216 { 0x00000000, 0xc0204810, 0x000 },
1217 { 0x81000000, 0x00204411, 0x000 },
1218 { 0x00000005, 0x00204811, 0x000 },
1219 { 0x0000216c, 0x00204411, 0x000 },
1220 { 0x00000000, 0xc0204810, 0x000 },
1221 { 0x00000000, 0x002f0224, 0x000 },
1222 { 0x00000000, 0x0ce00000, 0x000 },
1223 { 0x00000000, 0x00400000, 0x491 },
1224 { 0x00000000, 0xc0210a20, 0x000 },
1225 { 0x00000000, 0x14c00000, 0x4ae },
1226 { 0x81000000, 0x00204411, 0x000 },
1227 { 0x00000000, 0x00204811, 0x000 },
1228 { 0x0000216d, 0x00204411, 0x000 },
1229 { 0x00000000, 0xc0204800, 0x000 },
1230 { 0x00000000, 0xc0204800, 0x000 },
1231 { 0x00000000, 0x1ac00000, 0x4a9 },
1232 { 0x9e000000, 0x00204411, 0x000 },
1233 { 0xcafebabe, 0x00204811, 0x000 },
1234 { 0x00000000, 0x1ae00000, 0x4ac },
1235 { 0x00000000, 0x00400000, 0x4b2 },
1236 { 0x81000000, 0x00204411, 0x000 },
1237 { 0x00000001, 0x00204811, 0x000 },
1238 { 0x00040000, 0xc0294620, 0x000 },
1239 { 0x00000000, 0xc0600000, 0x614 },
1240 { 0x00000001, 0x00210222, 0x000 },
1241 { 0x00000000, 0x14c00000, 0x4b9 },
1242 { 0x00002169, 0x00204411, 0x000 },
1243 { 0x00000000, 0xc0204800, 0x000 },
1244 { 0x00000000, 0xc0204800, 0x000 },
1245 { 0x00000000, 0x00204810, 0x000 },
1246 { 0xcafebabe, 0x00404811, 0x000 },
1247 { 0x00000000, 0xc0204400, 0x000 },
1248 { 0x00000000, 0xc0404810, 0x000 },
1249 { 0x81000000, 0x00204411, 0x000 },
1250 { 0x00000001, 0x00204811, 0x000 },
1251 { 0x000021f8, 0x00204411, 0x000 },
1252 { 0x0000000d, 0x00204811, 0x000 },
1253 { 0x000421f9, 0x00604411, 0x614 },
1254 { 0x00000000, 0x00210230, 0x000 },
1255 { 0x00000000, 0x14c00000, 0x4bb },
1256 { 0x00002180, 0x00204411, 0x000 },
1257 { 0x00000000, 0xc0204800, 0x000 },
1258 { 0x00000000, 0xc0200000, 0x000 },
1259 { 0x00000000, 0xc0204800, 0x000 },
1260 { 0x00000000, 0xc0200000, 0x000 },
1261 { 0x00000000, 0xc0404800, 0x000 },
1262 { 0x00000003, 0x00333e2f, 0x000 },
1263 { 0x00000001, 0x00210221, 0x000 },
1264 { 0x00000000, 0x14e00000, 0x4eb },
1265 { 0x00000035, 0x00200a2d, 0x000 },
1266 { 0x00040000, 0x18e00c11, 0x4da },
1267 { 0x00000001, 0x00333e2f, 0x000 },
1268 { 0x00002169, 0x00204411, 0x000 },
1269 { 0x00000000, 0x00204802, 0x000 },
1270 { 0x00000000, 0x00204803, 0x000 },
1271 { 0x00000008, 0x00300a22, 0x000 },
1272 { 0x00000000, 0xc0204800, 0x000 },
1273 { 0x00000000, 0xc0204800, 0x000 },
1274 { 0x00002169, 0x00204411, 0x000 },
1275 { 0x00000000, 0x00204802, 0x000 },
1276 { 0x00000000, 0x00204803, 0x000 },
1277 { 0x00000008, 0x00300a22, 0x000 },
1278 { 0x00000000, 0xc0204800, 0x000 },
1279 { 0x00000000, 0xd8c04800, 0x4ce },
1280 { 0x00002169, 0x00204411, 0x000 },
1281 { 0x00000000, 0x00204802, 0x000 },
1282 { 0x00000000, 0x00204803, 0x000 },
1283 { 0x00000008, 0x00300a22, 0x000 },
1284 { 0x00000000, 0xc0204800, 0x000 },
1285 { 0x00000000, 0xc0204800, 0x000 },
1286 { 0x00000036, 0x0020122d, 0x000 },
1287 { 0x00000000, 0x00290c83, 0x000 },
1288 { 0x00002169, 0x00204411, 0x000 },
1289 { 0x00000000, 0x00204802, 0x000 },
1290 { 0x00000000, 0x00204803, 0x000 },
1291 { 0x00000008, 0x00300a22, 0x000 },
1292 { 0x00000000, 0xc0204800, 0x000 },
1293 { 0x00000000, 0xc0204800, 0x000 },
1294 { 0x00000011, 0x00210224, 0x000 },
1295 { 0x00000000, 0x14c00000, 0x000 },
1296 { 0x00000000, 0x00400000, 0x491 },
1297 { 0x00000035, 0xc0203620, 0x000 },
1298 { 0x00000036, 0xc0403620, 0x000 },
1299 { 0x0000304a, 0x00204411, 0x000 },
1300 { 0xe0000000, 0xc0484a20, 0x000 },
1301 { 0x0000000f, 0x00210221, 0x000 },
1302 { 0x00000000, 0x14c00000, 0x4f2 },
1303 { 0x00000000, 0x00600000, 0x00b },
1304 { 0x00000000, 0xd9000000, 0x000 },
1305 { 0x00000000, 0xc0400400, 0x001 },
1306 { 0x81000000, 0x00204411, 0x000 },
1307 { 0x00000002, 0x00204811, 0x000 },
1308 { 0x000000ff, 0x00280e30, 0x000 },
1309 { 0x00000000, 0x002f0223, 0x000 },
1310 { 0x00000000, 0x0cc00000, 0x4f6 },
1311 { 0x00000000, 0xc0200800, 0x000 },
1312 { 0x00000000, 0x14c00000, 0x50b },
1313 { 0x00000000, 0x00200c11, 0x000 },
1314 { 0x00000024, 0x00203623, 0x000 },
1315 { 0x00000034, 0x00203623, 0x000 },
1316 { 0x00000032, 0x00203623, 0x000 },
1317 { 0x00000031, 0x00203623, 0x000 },
1318 { 0x0000001d, 0x00203623, 0x000 },
1319 { 0x0000002d, 0x00203623, 0x000 },
1320 { 0x0000002e, 0x00203623, 0x000 },
1321 { 0x0000001b, 0x00203623, 0x000 },
1322 { 0x0000001c, 0x00203623, 0x000 },
1323 { 0xffffe000, 0x00200c11, 0x000 },
1324 { 0x00000029, 0x00203623, 0x000 },
1325 { 0x0000002a, 0x00203623, 0x000 },
1326 { 0x00001fff, 0x00200c11, 0x000 },
1327 { 0x0000002b, 0x00203623, 0x000 },
1328 { 0x0000002c, 0x00203623, 0x000 },
1329 { 0xf1ffffff, 0x00283a2e, 0x000 },
1330 { 0x0000001a, 0xc0220e20, 0x000 },
1331 { 0x00000000, 0x0029386e, 0x000 },
1332 { 0x81000000, 0x00204411, 0x000 },
1333 { 0x00000006, 0x00204811, 0x000 },
1334 { 0x00000033, 0x40203620, 0x000 },
1335 { 0x87000000, 0x00204411, 0x000 },
1336 { 0x00000000, 0xc0204800, 0x000 },
1337 { 0x0000a1f4, 0x00204411, 0x000 },
1338 { 0x00000000, 0x00204810, 0x000 },
1339 { 0x9d000000, 0x00204411, 0x000 },
1340 { 0x0000001f, 0x40214a20, 0x000 },
1341 { 0x96000000, 0x00204411, 0x000 },
1342 { 0x00000000, 0xc0204800, 0x000 },
1343 { 0x00000000, 0xc0200c00, 0x000 },
1344 { 0x00000000, 0xc0201000, 0x000 },
1345 { 0x0000001f, 0x00211624, 0x000 },
1346 { 0x00000000, 0x14c00000, 0x000 },
1347 { 0x00000025, 0x00203623, 0x000 },
1348 { 0x00000003, 0x00281e23, 0x000 },
1349 { 0x00000008, 0x00222223, 0x000 },
1350 { 0xfffff000, 0x00282228, 0x000 },
1351 { 0x00000000, 0x002920e8, 0x000 },
1352 { 0x00000027, 0x00203628, 0x000 },
1353 { 0x00000018, 0x00211e23, 0x000 },
1354 { 0x00000028, 0x00203627, 0x000 },
1355 { 0x00000002, 0x00221624, 0x000 },
1356 { 0x00000000, 0x003014a8, 0x000 },
1357 { 0x00000026, 0x00203625, 0x000 },
1358 { 0x00000003, 0x00211a24, 0x000 },
1359 { 0x10000000, 0x00281a26, 0x000 },
1360 { 0xefffffff, 0x00283a2e, 0x000 },
1361 { 0x00000000, 0x004938ce, 0x602 },
1362 { 0x00000001, 0x40280a20, 0x000 },
1363 { 0x00000006, 0x40280e20, 0x000 },
1364 { 0x00000300, 0xc0281220, 0x000 },
1365 { 0x00000008, 0x00211224, 0x000 },
1366 { 0x00000000, 0xc0201620, 0x000 },
1367 { 0x00000000, 0xc0201a20, 0x000 },
1368 { 0x00000000, 0x00210222, 0x000 },
1369 { 0x00000000, 0x14c00000, 0x541 },
1370 { 0x81000000, 0x00204411, 0x000 },
1371 { 0x00000001, 0x00204811, 0x000 },
1372 { 0x00002258, 0x00300a24, 0x000 },
1373 { 0x00040000, 0x00694622, 0x614 },
1374 { 0x00002169, 0x00204411, 0x000 },
1375 { 0x00000000, 0x00204805, 0x000 },
1376 { 0x00020000, 0x00294a26, 0x000 },
1377 { 0x00000000, 0x00204810, 0x000 },
1378 { 0xcafebabe, 0x00204811, 0x000 },
1379 { 0x00000002, 0x002f0223, 0x000 },
1380 { 0x00000000, 0x0cc00000, 0x549 },
1381 { 0x00000000, 0xc0201c10, 0x000 },
1382 { 0x00000000, 0xc0400000, 0x55b },
1383 { 0x00000002, 0x002f0223, 0x000 },
1384 { 0x00000000, 0x0cc00000, 0x549 },
1385 { 0x81000000, 0x00204411, 0x000 },
1386 { 0x00000001, 0x00204811, 0x000 },
1387 { 0x00002258, 0x00300a24, 0x000 },
1388 { 0x00040000, 0x00694622, 0x614 },
1389 { 0x00000000, 0xc0201c10, 0x000 },
1390 { 0x00000000, 0xc0400000, 0x55b },
1391 { 0x00000000, 0x002f0223, 0x000 },
1392 { 0x00000000, 0x0cc00000, 0x54d },
1393 { 0x00000000, 0xc0201c00, 0x000 },
1394 { 0x00000000, 0xc0400000, 0x55b },
1395 { 0x00000004, 0x002f0223, 0x000 },
1396 { 0x00000000, 0x0cc00000, 0x559 },
1397 { 0x81000000, 0x00204411, 0x000 },
1398 { 0x00000000, 0x00204811, 0x000 },
1399 { 0x0000216d, 0x00204411, 0x000 },
1400 { 0x00000000, 0xc0204800, 0x000 },
1401 { 0x00000000, 0xc0204800, 0x000 },
1402 { 0x00000000, 0x1ac00000, 0x554 },
1403 { 0x9e000000, 0x00204411, 0x000 },
1404 { 0xcafebabe, 0x00204811, 0x000 },
1405 { 0x00000000, 0x1ae00000, 0x557 },
1406 { 0x00000000, 0x00401c10, 0x55b },
1407 { 0x00000000, 0xc0200000, 0x000 },
1408 { 0x00000000, 0xc0400000, 0x000 },
1409 { 0x00000000, 0x0ee00000, 0x55d },
1410 { 0x00000000, 0x00600000, 0x5a4 },
1411 { 0x00000000, 0x002f0224, 0x000 },
1412 { 0x00000000, 0x0cc00000, 0x56d },
1413 { 0x0000a2b7, 0x00204411, 0x000 },
1414 { 0x00000000, 0x00204807, 0x000 },
1415 { 0x81000000, 0x00204411, 0x000 },
1416 { 0x00000001, 0x00204811, 0x000 },
1417 { 0x0004a2b6, 0x00604411, 0x614 },
1418 { 0x0000001a, 0x00212230, 0x000 },
1419 { 0x00000006, 0x00222630, 0x000 },
1420 { 0x0000a2c4, 0x00204411, 0x000 },
1421 { 0x00000000, 0x003048e9, 0x000 },
1422 { 0x00000000, 0x00e00000, 0x56b },
1423 { 0x0000a2d1, 0x00204411, 0x000 },
1424 { 0x00000000, 0x00404808, 0x000 },
1425 { 0x0000a2d1, 0x00204411, 0x000 },
1426 { 0x00000001, 0x00504a28, 0x000 },
1427 { 0x00000001, 0x002f0224, 0x000 },
1428 { 0x00000000, 0x0cc00000, 0x57d },
1429 { 0x0000a2bb, 0x00204411, 0x000 },
1430 { 0x00000000, 0x00204807, 0x000 },
1431 { 0x81000000, 0x00204411, 0x000 },
1432 { 0x00000001, 0x00204811, 0x000 },
1433 { 0x0004a2ba, 0x00604411, 0x614 },
1434 { 0x0000001a, 0x00212230, 0x000 },
1435 { 0x00000006, 0x00222630, 0x000 },
1436 { 0x0000a2c5, 0x00204411, 0x000 },
1437 { 0x00000000, 0x003048e9, 0x000 },
1438 { 0x00000000, 0x00e00000, 0x57b },
1439 { 0x0000a2d2, 0x00204411, 0x000 },
1440 { 0x00000000, 0x00404808, 0x000 },
1441 { 0x0000a2d2, 0x00204411, 0x000 },
1442 { 0x00000001, 0x00504a28, 0x000 },
1443 { 0x00000002, 0x002f0224, 0x000 },
1444 { 0x00000000, 0x0cc00000, 0x58d },
1445 { 0x0000a2bf, 0x00204411, 0x000 },
1446 { 0x00000000, 0x00204807, 0x000 },
1447 { 0x81000000, 0x00204411, 0x000 },
1448 { 0x00000001, 0x00204811, 0x000 },
1449 { 0x0004a2be, 0x00604411, 0x614 },
1450 { 0x0000001a, 0x00212230, 0x000 },
1451 { 0x00000006, 0x00222630, 0x000 },
1452 { 0x0000a2c6, 0x00204411, 0x000 },
1453 { 0x00000000, 0x003048e9, 0x000 },
1454 { 0x00000000, 0x00e00000, 0x58b },
1455 { 0x0000a2d3, 0x00204411, 0x000 },
1456 { 0x00000000, 0x00404808, 0x000 },
1457 { 0x0000a2d3, 0x00204411, 0x000 },
1458 { 0x00000001, 0x00504a28, 0x000 },
1459 { 0x0000a2c3, 0x00204411, 0x000 },
1460 { 0x00000000, 0x00204807, 0x000 },
1461 { 0x81000000, 0x00204411, 0x000 },
1462 { 0x00000001, 0x00204811, 0x000 },
1463 { 0x0004a2c2, 0x00604411, 0x614 },
1464 { 0x0000001a, 0x00212230, 0x000 },
1465 { 0x00000006, 0x00222630, 0x000 },
1466 { 0x0000a2c7, 0x00204411, 0x000 },
1467 { 0x00000000, 0x003048e9, 0x000 },
1468 { 0x00000000, 0x00e00000, 0x599 },
1469 { 0x0000a2d4, 0x00204411, 0x000 },
1470 { 0x00000000, 0x00404808, 0x000 },
1471 { 0x0000a2d4, 0x00204411, 0x000 },
1472 { 0x00000001, 0x00504a28, 0x000 },
1473 { 0x85000000, 0x00204411, 0x000 },
1474 { 0x00000000, 0x00204801, 0x000 },
1475 { 0x0000304a, 0x00204411, 0x000 },
1476 { 0x01000000, 0x00204811, 0x000 },
1477 { 0x00000000, 0x00400000, 0x59f },
1478 { 0xa4000000, 0xc0204411, 0x000 },
1479 { 0x00000000, 0xc0404800, 0x000 },
1480 { 0x00000000, 0xc0600000, 0x5a4 },
1481 { 0x00000000, 0xc0400400, 0x001 },
1482 { 0x0001a2a4, 0x00204411, 0x000 },
1483 { 0x00000000, 0x00204811, 0x000 },
1484 { 0x00000000, 0x00204811, 0x000 },
1485 { 0x00000000, 0x00204811, 0x000 },
1486 { 0x00000000, 0x00204811, 0x000 },
1487 { 0x00000005, 0x00204811, 0x000 },
1488 { 0x0000a1f4, 0x00204411, 0x000 },
1489 { 0x00000000, 0x00204811, 0x000 },
1490 { 0x88000000, 0x00204411, 0x000 },
1491 { 0x00000001, 0x00204811, 0x000 },
1492 { 0xff000000, 0x00204411, 0x000 },
1493 { 0x00000000, 0x00204811, 0x000 },
1494 { 0x00000001, 0x00204811, 0x000 },
1495 { 0x00000002, 0x00804811, 0x000 },
1496 { 0x00000000, 0x0ee00000, 0x5b7 },
1497 { 0x00001000, 0x00200811, 0x000 },
1498 { 0x00000034, 0x00203622, 0x000 },
1499 { 0x00000000, 0x00600000, 0x5bb },
1500 { 0x00000000, 0x00600000, 0x5a4 },
1501 { 0x98000000, 0x00204411, 0x000 },
1502 { 0x00000000, 0x00804811, 0x000 },
1503 { 0x00000000, 0xc0600000, 0x5bb },
1504 { 0x00000000, 0xc0400400, 0x001 },
1505 { 0x0000a2a4, 0x00204411, 0x000 },
1506 { 0x00000022, 0x00204811, 0x000 },
1507 { 0x89000000, 0x00204411, 0x000 },
1508 { 0x00000001, 0x00204811, 0x000 },
1509 { 0xff000000, 0x00204411, 0x000 },
1510 { 0x00000000, 0x00204811, 0x000 },
1511 { 0x00000001, 0x00204811, 0x000 },
1512 { 0x00000002, 0x00804811, 0x000 },
1513 { 0x0000217a, 0xc0204411, 0x000 },
1514 { 0x00000000, 0x00404811, 0x000 },
1515 { 0x97000000, 0x00204411, 0x000 },
1516 { 0x00000000, 0x00204811, 0x000 },
1517 { 0x8a000000, 0x00204411, 0x000 },
1518 { 0x00000000, 0x00204811, 0x000 },
1519 { 0xff000000, 0x00204411, 0x000 },
1520 { 0x00000000, 0x00204811, 0x000 },
1521 { 0x00000001, 0x00204811, 0x000 },
1522 { 0x00000002, 0x00804811, 0x000 },
1523 { 0x00000000, 0x00600000, 0x5e1 },
1524 { 0x00002010, 0x00204411, 0x000 },
1525 { 0x00008000, 0x00204811, 0x000 },
1526 { 0x0001a2a4, 0xc0204411, 0x000 },
1527 { 0x00000000, 0x00204811, 0x000 },
1528 { 0x00000016, 0x00604811, 0x35e },
1529 { 0x00000016, 0x00204811, 0x000 },
1530 { 0x00002010, 0x00204411, 0x000 },
1531 { 0x00010000, 0x00204811, 0x000 },
1532 { 0x81000000, 0x00204411, 0x000 },
1533 { 0x00000001, 0x00204811, 0x000 },
1534 { 0x0000217c, 0x00204411, 0x000 },
1535 { 0x09800000, 0x00204811, 0x000 },
1536 { 0xffffffff, 0x00204811, 0x000 },
1537 { 0x00000000, 0x00204811, 0x000 },
1538 { 0x00000000, 0x17000000, 0x000 },
1539 { 0x0004217f, 0x00604411, 0x614 },
1540 { 0x0000001f, 0x00210230, 0x000 },
1541 { 0x00000000, 0x14c00000, 0x000 },
1542 { 0x00000004, 0x00404c11, 0x5dc },
1543 { 0x0000001d, 0x00201e2d, 0x000 },
1544 { 0x00000004, 0x00291e27, 0x000 },
1545 { 0x0000001d, 0x00803627, 0x000 },
1546 { 0x0000001d, 0x00201e2d, 0x000 },
1547 { 0xfffffffb, 0x00281e27, 0x000 },
1548 { 0x0000001d, 0x00803627, 0x000 },
1549 { 0x0000001d, 0x00201e2d, 0x000 },
1550 { 0x00000008, 0x00291e27, 0x000 },
1551 { 0x0000001d, 0x00803627, 0x000 },
1552 { 0x0000001d, 0x00201e2d, 0x000 },
1553 { 0xfffffff7, 0x00281e27, 0x000 },
1554 { 0x0000001d, 0x00803627, 0x000 },
1555 { 0x00002010, 0x00204411, 0x000 },
1556 { 0x00008000, 0x00204811, 0x000 },
1557 { 0x0001a2a4, 0x00204411, 0x000 },
1558 { 0x00000000, 0x00204811, 0x000 },
1559 { 0x00000016, 0x00604811, 0x35e },
1560 { 0x00000016, 0x00204811, 0x000 },
1561 { 0x00002010, 0x00204411, 0x000 },
1562 { 0x00010000, 0x00204811, 0x000 },
1563 { 0x0000217c, 0x00204411, 0x000 },
1564 { 0x01800000, 0x00204811, 0x000 },
1565 { 0x00ffffff, 0x00204811, 0x000 },
1566 { 0x00000000, 0x00204811, 0x000 },
1567 { 0x00000000, 0x17000000, 0x000 },
1568 { 0x81000000, 0x00204411, 0x000 },
1569 { 0x00000001, 0x00204811, 0x000 },
1570 { 0x0004217f, 0x00604411, 0x614 },
1571 { 0x00000000, 0x00200010, 0x000 },
1572 { 0x00000000, 0x14c00000, 0x613 },
1573 { 0x00000010, 0x00404c11, 0x5f9 },
1574 { 0x00000000, 0xc0200400, 0x000 },
1575 { 0x00000000, 0x38c00000, 0x000 },
1576 { 0x00000025, 0x00200a2d, 0x000 },
1577 { 0x00000026, 0x00200e2d, 0x000 },
1578 { 0x00000027, 0x0020122d, 0x000 },
1579 { 0x00000028, 0x0020162d, 0x000 },
1580 { 0x00002169, 0x00204411, 0x000 },
1581 { 0x00000000, 0x00204804, 0x000 },
1582 { 0x00000000, 0x00204805, 0x000 },
1583 { 0x00000000, 0x00204801, 0x000 },
1584 { 0xcafebabe, 0x00204811, 0x000 },
1585 { 0x00000004, 0x00301224, 0x000 },
1586 { 0x00000000, 0x002f0064, 0x000 },
1587 { 0x00000000, 0x0cc00000, 0x612 },
1588 { 0x00000003, 0x00281a22, 0x000 },
1589 { 0x00000008, 0x00221222, 0x000 },
1590 { 0xfffff000, 0x00281224, 0x000 },
1591 { 0x00000000, 0x002910c4, 0x000 },
1592 { 0x00000027, 0x00403624, 0x000 },
1593 { 0x00000000, 0x00800000, 0x000 },
1594 { 0x00000000, 0x1ac00000, 0x614 },
1595 { 0x9f000000, 0x00204411, 0x000 },
1596 { 0xcafebabe, 0x00204811, 0x000 },
1597 { 0x00000000, 0x1ae00000, 0x617 },
1598 { 0x00000000, 0x00800000, 0x000 },
1599 { 0x00000000, 0x00600000, 0x00b },
1600 { 0x00001000, 0x00600411, 0x2fe },
1601 { 0x00000000, 0x00200411, 0x000 },
1602 { 0x00000000, 0x00600811, 0x19f },
1603 { 0x0000225c, 0x00204411, 0x000 },
1604 { 0x00000003, 0x00204811, 0x000 },
1605 { 0x00002256, 0x00204411, 0x000 },
1606 { 0x0000001b, 0x00204811, 0x000 },
1607 { 0x0000a1fc, 0x00204411, 0x000 },
1608 { 0x00000001, 0x00204811, 0x000 },
1609 { 0x0001a1fd, 0xc0204411, 0x000 },
1610 { 0x00000029, 0x00201e2d, 0x000 },
1611 { 0x00000010, 0x00221e27, 0x000 },
1612 { 0x0000002c, 0x0020222d, 0x000 },
1613 { 0x0000ffff, 0x00282228, 0x000 },
1614 { 0x00000000, 0x00294907, 0x000 },
1615 { 0x00000000, 0x00204811, 0x000 },
1616 { 0x0000002a, 0x0020222d, 0x000 },
1617 { 0x0000ffff, 0x00282228, 0x000 },
1618 { 0x00000000, 0x00294907, 0x000 },
1619 { 0x00000000, 0x00204811, 0x000 },
1620 { 0x0000002b, 0x00201e2d, 0x000 },
1621 { 0x00000010, 0x00221e27, 0x000 },
1622 { 0x00000000, 0x00294907, 0x000 },
1623 { 0x00000000, 0x00404811, 0x000 },
1624 { 0x00000000, 0x00000000, 0x000 },
1625 { 0x00000000, 0x00000000, 0x000 },
1626 { 0x00000000, 0x00000000, 0x000 },
1627 { 0x00000000, 0x00000000, 0x000 },
1628 { 0x00000000, 0x00000000, 0x000 },
1629 { 0x00000000, 0x00000000, 0x000 },
1630 { 0x00000000, 0x00000000, 0x000 },
1631 { 0x00000000, 0x00000000, 0x000 },
1632 { 0x00000000, 0x00000000, 0x000 },
1633 { 0x00000000, 0x00000000, 0x000 },
1634 { 0x00000000, 0x00000000, 0x000 },
1635 { 0x00000000, 0x00000000, 0x000 },
1636 { 0x00000000, 0x00000000, 0x000 },
1637 { 0x00000000, 0x00000000, 0x000 },
1638 { 0x00000000, 0x00000000, 0x000 },
1639 { 0x00000000, 0x00000000, 0x000 },
1640 { 0x00000000, 0x00000000, 0x000 },
1641 { 0x00000000, 0x00000000, 0x000 },
1642 { 0x00000000, 0x00000000, 0x000 },
1643 { 0x00000000, 0x00000000, 0x000 },
1644 { 0x00000000, 0x00000000, 0x000 },
1645 { 0x00000000, 0x00000000, 0x000 },
1646 { 0x00000000, 0x00000000, 0x000 },
1647 { 0x00000000, 0x00000000, 0x000 },
1648 { 0x00000000, 0x00000000, 0x000 },
1649 { 0x00000000, 0x00000000, 0x000 },
1650 { 0x00000000, 0x00000000, 0x000 },
1651 { 0x00000000, 0x00000000, 0x000 },
1652 { 0x00000000, 0x00000000, 0x000 },
1653 { 0x00000000, 0x00000000, 0x000 },
1654 { 0x00000000, 0x00000000, 0x000 },
1655 { 0x00000000, 0x00000000, 0x000 },
1656 { 0x00000000, 0x00000000, 0x000 },
1657 { 0x00000000, 0x00000000, 0x000 },
1658 { 0x00000000, 0x00000000, 0x000 },
1659 { 0x00000000, 0x00000000, 0x000 },
1660 { 0x00000000, 0x00000000, 0x000 },
1661 { 0x00000000, 0x00000000, 0x000 },
1662 { 0x00000000, 0x00000000, 0x000 },
1663 { 0x00000000, 0x00000000, 0x000 },
1664 { 0x00000000, 0x00000000, 0x000 },
1665 { 0x00000000, 0x00000000, 0x000 },
1666 { 0x00000000, 0x00000000, 0x000 },
1667 { 0x00000000, 0x00000000, 0x000 },
1668 { 0x00000000, 0x00000000, 0x000 },
1669 { 0x00000000, 0x00000000, 0x000 },
1670 { 0x00000000, 0x00000000, 0x000 },
1671 { 0x00000000, 0x00000000, 0x000 },
1672 { 0x00000000, 0x00000000, 0x000 },
1673 { 0x00000000, 0x00000000, 0x000 },
1674 { 0x00000000, 0x00000000, 0x000 },
1675 { 0x00000000, 0x00000000, 0x000 },
1676 { 0x00000000, 0x00000000, 0x000 },
1677 { 0x00000000, 0x00000000, 0x000 },
1678 { 0x00000000, 0x00000000, 0x000 },
1679 { 0x00000000, 0x00000000, 0x000 },
1680 { 0x00000000, 0x00000000, 0x000 },
1681 { 0x00000000, 0x00000000, 0x000 },
1682 { 0x00000000, 0x00000000, 0x000 },
1683 { 0x00000000, 0x00000000, 0x000 },
1684 { 0x00000000, 0x00000000, 0x000 },
1685 { 0x00000000, 0x00000000, 0x000 },
1686 { 0x00000000, 0x00000000, 0x000 },
1687 { 0x00000000, 0x00000000, 0x000 },
1688 { 0x00000000, 0x00000000, 0x000 },
1689 { 0x00000000, 0x00000000, 0x000 },
1690 { 0x00000000, 0x00000000, 0x000 },
1691 { 0x00000000, 0x00000000, 0x000 },
1692 { 0x00000000, 0x00000000, 0x000 },
1693 { 0x00000000, 0x00000000, 0x000 },
1694 { 0x00000000, 0x00000000, 0x000 },
1695 { 0x00000000, 0x00000000, 0x000 },
1696 { 0x00000000, 0x00000000, 0x000 },
1697 { 0x00000000, 0x00000000, 0x000 },
1698 { 0x00000000, 0x00000000, 0x000 },
1699 { 0x00000000, 0x00000000, 0x000 },
1700 { 0x00000000, 0x00000000, 0x000 },
1701 { 0x00000000, 0x00000000, 0x000 },
1702 { 0x00000000, 0x00000000, 0x000 },
1703 { 0x00000000, 0x00000000, 0x000 },
1704 { 0x00000000, 0x00000000, 0x000 },
1705 { 0x00000000, 0x00000000, 0x000 },
1706 { 0x00000000, 0x00000000, 0x000 },
1707 { 0x00000000, 0x00000000, 0x000 },
1708 { 0x00000000, 0x00000000, 0x000 },
1709 { 0x00000000, 0x00000000, 0x000 },
1710 { 0x00000000, 0x00000000, 0x000 },
1711 { 0x00000000, 0x00000000, 0x000 },
1712 { 0x00000000, 0x00000000, 0x000 },
1713 { 0x00000000, 0x00000000, 0x000 },
1714 { 0x00000000, 0x00000000, 0x000 },
1715 { 0x00000000, 0x00000000, 0x000 },
1716 { 0x00000000, 0x00000000, 0x000 },
1717 { 0x00000000, 0x00000000, 0x000 },
1718 { 0x00000000, 0x00000000, 0x000 },
1719 { 0x00000000, 0x00000000, 0x000 },
1720 { 0x00000000, 0x00000000, 0x000 },
1721 { 0x00000000, 0x00000000, 0x000 },
1722 { 0x00000000, 0x00000000, 0x000 },
1723 { 0x00000000, 0x00000000, 0x000 },
1724 { 0x00000000, 0x00000000, 0x000 },
1725 { 0x00000000, 0x00000000, 0x000 },
1726 { 0x00000000, 0x00000000, 0x000 },
1727 { 0x00000000, 0x00000000, 0x000 },
1728 { 0x00000000, 0x00000000, 0x000 },
1729 { 0x00000000, 0x00000000, 0x000 },
1730 { 0x00000000, 0x00000000, 0x000 },
1731 { 0x00000000, 0x00000000, 0x000 },
1732 { 0x00000000, 0x00000000, 0x000 },
1733 { 0x00000000, 0x00000000, 0x000 },
1734 { 0x00000000, 0x00000000, 0x000 },
1735 { 0x00000000, 0x00000000, 0x000 },
1736 { 0x00000000, 0x00000000, 0x000 },
1737 { 0x00000000, 0x00000000, 0x000 },
1738 { 0x00000000, 0x00000000, 0x000 },
1739 { 0x00000000, 0x00000000, 0x000 },
1740 { 0x00000000, 0x00000000, 0x000 },
1741 { 0x00000000, 0x00000000, 0x000 },
1742 { 0x00000000, 0x00000000, 0x000 },
1743 { 0x00000000, 0x00000000, 0x000 },
1744 { 0x00000000, 0x00000000, 0x000 },
1745 { 0x00000000, 0x00000000, 0x000 },
1746 { 0x00000000, 0x00000000, 0x000 },
1747 { 0x00000000, 0x00000000, 0x000 },
1748 { 0x00000000, 0x00000000, 0x000 },
1749 { 0x00000000, 0x00000000, 0x000 },
1750 { 0x00000000, 0x00000000, 0x000 },
1751 { 0x00000000, 0x00000000, 0x000 },
1752 { 0x00000000, 0x00000000, 0x000 },
1753 { 0x00000000, 0x00000000, 0x000 },
1754 { 0x00000000, 0x00000000, 0x000 },
1755 { 0x00000000, 0x00000000, 0x000 },
1756 { 0x00000000, 0x00000000, 0x000 },
1757 { 0x00000000, 0x00000000, 0x000 },
1758 { 0x00000000, 0x00000000, 0x000 },
1759 { 0x00000000, 0x00000000, 0x000 },
1760 { 0x00000000, 0x00000000, 0x000 },
1761 { 0x00000000, 0x00000000, 0x000 },
1762 { 0x00000000, 0x00000000, 0x000 },
1763 { 0x00000000, 0x00000000, 0x000 },
1764 { 0x00000000, 0x00000000, 0x000 },
1765 { 0x00000000, 0x00000000, 0x000 },
1766 { 0x00000000, 0x00000000, 0x000 },
1767 { 0x00000000, 0x00000000, 0x000 },
1768 { 0x00000000, 0x00000000, 0x000 },
1769 { 0x00000000, 0x00000000, 0x000 },
1770 { 0x00000000, 0x00000000, 0x000 },
1771 { 0x00000000, 0x00000000, 0x000 },
1772 { 0x00000000, 0x00000000, 0x000 },
1773 { 0x00000000, 0x00000000, 0x000 },
1774 { 0x00000000, 0x00000000, 0x000 },
1775 { 0x00000000, 0x00000000, 0x000 },
1776 { 0x00000000, 0x00000000, 0x000 },
1777 { 0x00000000, 0x00000000, 0x000 },
1778 { 0x00000000, 0x00000000, 0x000 },
1779 { 0x00000000, 0x00000000, 0x000 },
1780 { 0x00000000, 0x00000000, 0x000 },
1781 { 0x00000000, 0x00000000, 0x000 },
1782 { 0x00000000, 0x00000000, 0x000 },
1783 { 0x00000000, 0x00000000, 0x000 },
1784 { 0x00000000, 0x00000000, 0x000 },
1785 { 0x00000000, 0x00000000, 0x000 },
1786 { 0x00000000, 0x00000000, 0x000 },
1787 { 0x00000000, 0x00000000, 0x000 },
1788 { 0x00000000, 0x00000000, 0x000 },
1789 { 0x00000000, 0x00000000, 0x000 },
1790 { 0x00000000, 0x00000000, 0x000 },
1791 { 0x00000000, 0x00000000, 0x000 },
1792 { 0x00000000, 0x00000000, 0x000 },
1793 { 0x00000000, 0x00000000, 0x000 },
1794 { 0x00000000, 0x00000000, 0x000 },
1795 { 0x00000000, 0x00000000, 0x000 },
1796 { 0x00000000, 0x00000000, 0x000 },
1797 { 0x00000000, 0x00000000, 0x000 },
1798 { 0x00000000, 0x00000000, 0x000 },
1799 { 0x00000000, 0x00000000, 0x000 },
1800 { 0x00000000, 0x00000000, 0x000 },
1801 { 0x00000000, 0x00000000, 0x000 },
1802 { 0x013304ef, 0x059b0239, 0x000 },
1803 { 0x01b00159, 0x0425059b, 0x000 },
1804 { 0x021201f6, 0x02390142, 0x000 },
1805 { 0x0210022e, 0x0289022a, 0x000 },
1806 { 0x03c2059b, 0x059b059b, 0x000 },
1807 { 0x05cd05ce, 0x0308059b, 0x000 },
1808 { 0x059b05a0, 0x03090329, 0x000 },
1809 { 0x0313026b, 0x032b031d, 0x000 },
1810 { 0x059b059b, 0x059b059b, 0x000 },
1811 { 0x059b052c, 0x059b059b, 0x000 },
1812 { 0x03a5059b, 0x04a2032d, 0x000 },
1813 { 0x04810433, 0x0423059b, 0x000 },
1814 { 0x04bb04ed, 0x042704c8, 0x000 },
1815 { 0x043304f4, 0x033a0365, 0x000 },
1816 { 0x059b059b, 0x059b059b, 0x000 },
1817 { 0x059b059b, 0x059b059b, 0x000 },
1818 { 0x059b059b, 0x05b905a2, 0x000 },
1819 { 0x059b059b, 0x0007059b, 0x000 },
1820 { 0x059b059b, 0x059b059b, 0x000 },
1821 { 0x059b059b, 0x059b059b, 0x000 },
1822 { 0x03e303d8, 0x03f303f1, 0x000 },
1823 { 0x03f903f5, 0x03f703fb, 0x000 },
1824 { 0x04070403, 0x040f040b, 0x000 },
1825 { 0x04170413, 0x041f041b, 0x000 },
1826 { 0x059b059b, 0x059b059b, 0x000 },
1827 { 0x059b059b, 0x059b059b, 0x000 },
1828 { 0x059b059b, 0x059b059b, 0x000 },
1829 { 0x00020600, 0x06190006, 0x000 },
1830};
1831
1832static const u32 R600_pfp_microcode[] = {
18330xd40071,
18340xd40072,
18350xca0400,
18360xa00000,
18370x7e828b,
18380x800003,
18390xca0400,
18400xd4401e,
18410xee001e,
18420xca0400,
18430xa00000,
18440x7e828b,
18450xc41838,
18460xca2400,
18470xca2800,
18480x9581a8,
18490xc41c3a,
18500xc3c000,
18510xca0800,
18520xca0c00,
18530x7c744b,
18540xc20005,
18550x99c000,
18560xc41c3a,
18570x7c744c,
18580xc0fff0,
18590x042c04,
18600x309002,
18610x7d2500,
18620x351402,
18630x7d350b,
18640x255403,
18650x7cd580,
18660x259c03,
18670x95c004,
18680xd5001b,
18690x7eddc1,
18700x7d9d80,
18710xd6801b,
18720xd5801b,
18730xd4401e,
18740xd5401e,
18750xd6401e,
18760xd6801e,
18770xd4801e,
18780xd4c01e,
18790x9783d4,
18800xd5c01e,
18810xca0800,
18820x80001b,
18830xca0c00,
18840xe4011e,
18850xd4001e,
18860x80000d,
18870xc41838,
18880xe4013e,
18890xd4001e,
18900x80000d,
18910xc41838,
18920xd4401e,
18930xee001e,
18940xca0400,
18950xa00000,
18960x7e828b,
18970xe4011e,
18980xd4001e,
18990xd4401e,
19000xee001e,
19010xca0400,
19020xa00000,
19030x7e828b,
19040xe4013e,
19050xd4001e,
19060xd4401e,
19070xee001e,
19080xca0400,
19090xa00000,
19100x7e828b,
19110xca1800,
19120xd4401e,
19130xd5801e,
19140x800054,
19150xd40073,
19160xd4401e,
19170xca0800,
19180xca0c00,
19190xca1000,
19200xd48019,
19210xd4c018,
19220xd50017,
19230xd4801e,
19240xd4c01e,
19250xd5001e,
19260xe2001e,
19270xca0400,
19280xa00000,
19290x7e828b,
19300xca0800,
19310xd48060,
19320xd4401e,
19330x800002,
19340xd4801e,
19350xca0800,
19360xd48061,
19370xd4401e,
19380x800002,
19390xd4801e,
19400xca0800,
19410xca0c00,
19420xd4401e,
19430xd48016,
19440xd4c016,
19450xd4801e,
19460x8001b9,
19470xd4c01e,
19480xc6083e,
19490xca0c00,
19500xca1000,
19510x948004,
19520xca1400,
19530xe420f3,
19540xd42013,
19550xd56065,
19560xd4e01c,
19570xd5201c,
19580xd5601c,
19590x800002,
19600x062001,
19610xc6083e,
19620xca0c00,
19630xca1000,
19640x9483f7,
19650xca1400,
19660xe420f3,
19670x80007a,
19680xd42013,
19690xc6083e,
19700xca0c00,
19710xca1000,
19720x9883ef,
19730xca1400,
19740xd40064,
19750x80008e,
19760x000000,
19770xc41432,
19780xc6183e,
19790xc4082f,
19800x954005,
19810xc40c30,
19820xd4401e,
19830x800002,
19840xee001e,
19850x9583f5,
19860xc41031,
19870xd44033,
19880xd52065,
19890xd4a01c,
19900xd4e01c,
19910xd5201c,
19920xd40073,
19930xe4015e,
19940xd4001e,
19950x8001b9,
19960x062001,
19970x0a2001,
19980xd60074,
19990xc40836,
20000xc61040,
20010x988007,
20020xcc3835,
20030x95010f,
20040xd4001f,
20050xd46062,
20060x800002,
20070xd42062,
20080xcc1433,
20090x8401bc,
20100xd40070,
20110xd5401e,
20120x800002,
20130xee001e,
20140xca0c00,
20150xca1000,
20160xd4c01a,
20170x8401bc,
20180xd5001a,
20190xcc0443,
20200x35101f,
20210x2c9401,
20220x7d098b,
20230x984005,
20240x7d15cb,
20250xd4001a,
20260x8001b9,
20270xd4006d,
20280x344401,
20290xcc0c44,
20300x98403a,
20310xcc2c46,
20320x958004,
20330xcc0445,
20340x8001b9,
20350xd4001a,
20360xd4c01a,
20370x282801,
20380x8400f3,
20390xcc1003,
20400x98801b,
20410x04380c,
20420x8400f3,
20430xcc1003,
20440x988017,
20450x043808,
20460x8400f3,
20470xcc1003,
20480x988013,
20490x043804,
20500x8400f3,
20510xcc1003,
20520x988014,
20530xcc1047,
20540x9a8009,
20550xcc1448,
20560x9840da,
20570xd4006d,
20580xcc1844,
20590xd5001a,
20600xd5401a,
20610x8000cc,
20620xd5801a,
20630x96c0d3,
20640xd4006d,
20650x8001b9,
20660xd4006e,
20670x9ac003,
20680xd4006d,
20690xd4006e,
20700x800002,
20710xec007f,
20720x9ac0ca,
20730xd4006d,
20740x8001b9,
20750xd4006e,
20760xcc1403,
20770xcc1803,
20780xcc1c03,
20790x7d9103,
20800x7dd583,
20810x7d190c,
20820x35cc1f,
20830x35701f,
20840x7cf0cb,
20850x7cd08b,
20860x880000,
20870x7e8e8b,
20880x95c004,
20890xd4006e,
20900x8001b9,
20910xd4001a,
20920xd4c01a,
20930xcc0803,
20940xcc0c03,
20950xcc1003,
20960xcc1403,
20970xcc1803,
20980xcc1c03,
20990xcc2403,
21000xcc2803,
21010x35c41f,
21020x36b01f,
21030x7c704b,
21040x34f01f,
21050x7c704b,
21060x35701f,
21070x7c704b,
21080x7d8881,
21090x7dccc1,
21100x7e5101,
21110x7e9541,
21120x7c9082,
21130x7cd4c2,
21140x7c848b,
21150x9ac003,
21160x7c8c8b,
21170x2c8801,
21180x98809c,
21190xd4006d,
21200x98409a,
21210xd4006e,
21220xcc0847,
21230xcc0c48,
21240xcc1044,
21250xd4801a,
21260xd4c01a,
21270x800104,
21280xd5001a,
21290xcc0832,
21300xd40032,
21310x9482d8,
21320xca0c00,
21330xd4401e,
21340x800002,
21350xd4001e,
21360xe4011e,
21370xd4001e,
21380xca0800,
21390xca0c00,
21400xca1000,
21410xd4401e,
21420xca1400,
21430xd4801e,
21440xd4c01e,
21450xd5001e,
21460xd5401e,
21470xd54034,
21480x800002,
21490xee001e,
21500x280404,
21510xe2001a,
21520xe2001a,
21530xd4401a,
21540xca3800,
21550xcc0803,
21560xcc0c03,
21570xcc0c03,
21580xcc0c03,
21590x9882bc,
21600x000000,
21610x8401bc,
21620xd7806f,
21630x800002,
21640xee001f,
21650xca0400,
21660xc2ff00,
21670xcc0834,
21680xc13fff,
21690x7c74cb,
21700x7cc90b,
21710x7d010f,
21720x9902af,
21730x7c738b,
21740x8401bc,
21750xd7806f,
21760x800002,
21770xee001f,
21780xca0800,
21790x281900,
21800x7d898b,
21810x958014,
21820x281404,
21830xca0c00,
21840xca1000,
21850xca1c00,
21860xca2400,
21870xe2001f,
21880xd4c01a,
21890xd5001a,
21900xd5401a,
21910xcc1803,
21920xcc2c03,
21930xcc2c03,
21940xcc2c03,
21950x7da58b,
21960x7d9c47,
21970x984296,
21980x000000,
21990x800164,
22000xd4c01a,
22010xd4401e,
22020xd4801e,
22030x800002,
22040xee001e,
22050xe4011e,
22060xd4001e,
22070xd4401e,
22080xee001e,
22090xca0400,
22100xa00000,
22110x7e828b,
22120xe4013e,
22130xd4001e,
22140xd4401e,
22150xee001e,
22160xca0400,
22170xa00000,
22180x7e828b,
22190xca0800,
22200x248c06,
22210x0ccc06,
22220x98c006,
22230xcc1049,
22240x990004,
22250xd40071,
22260xe4011e,
22270xd4001e,
22280xd4401e,
22290xd4801e,
22300x800002,
22310xee001e,
22320xca0800,
22330xca0c00,
22340x34d018,
22350x251001,
22360x95001f,
22370xc17fff,
22380xca1000,
22390xca1400,
22400xca1800,
22410xd4801d,
22420xd4c01d,
22430x7db18b,
22440xc14202,
22450xc2c001,
22460xd5801d,
22470x34dc0e,
22480x7d5d4c,
22490x7f734c,
22500xd7401e,
22510xd5001e,
22520xd5401e,
22530xc14200,
22540xc2c000,
22550x099c01,
22560x31dc10,
22570x7f5f4c,
22580x7f734c,
22590x7d8380,
22600xd5806f,
22610xd58066,
22620xd7401e,
22630xec005e,
22640xc82402,
22650x8001b9,
22660xd60074,
22670xd4401e,
22680xd4801e,
22690xd4c01e,
22700x800002,
22710xee001e,
22720x800002,
22730xee001f,
22740xd4001f,
22750x800002,
22760xd4001f,
22770xd4001f,
22780x880000,
22790xd4001f,
22800x000000,
22810x000000,
22820x000000,
22830x000000,
22840x000000,
22850x000000,
22860x000000,
22870x000000,
22880x000000,
22890x000000,
22900x000000,
22910x000000,
22920x000000,
22930x000000,
22940x000000,
22950x000000,
22960x000000,
22970x000000,
22980x000000,
22990x000000,
23000x000000,
23010x000000,
23020x000000,
23030x000000,
23040x000000,
23050x000000,
23060x000000,
23070x000000,
23080x000000,
23090x000000,
23100x000000,
23110x000000,
23120x000000,
23130x000000,
23140x000000,
23150x000000,
23160x000000,
23170x000000,
23180x000000,
23190x000000,
23200x000000,
23210x000000,
23220x000000,
23230x000000,
23240x000000,
23250x000000,
23260x000000,
23270x000000,
23280x000000,
23290x000000,
23300x000000,
23310x000000,
23320x000000,
23330x000000,
23340x000000,
23350x000000,
23360x000000,
23370x000000,
23380x000000,
23390x000000,
23400x000000,
23410x000000,
23420x000000,
23430x000000,
23440x000000,
23450x010174,
23460x02017b,
23470x030090,
23480x040080,
23490x050005,
23500x060040,
23510x070033,
23520x08012f,
23530x090047,
23540x0a0037,
23550x1001b7,
23560x1700a4,
23570x22013d,
23580x23014c,
23590x2000b5,
23600x240128,
23610x27004e,
23620x28006b,
23630x2a0061,
23640x2b0053,
23650x2f0066,
23660x320088,
23670x340182,
23680x3c0159,
23690x3f0073,
23700x41018f,
23710x440131,
23720x550176,
23730x56017d,
23740x60000c,
23750x610035,
23760x620039,
23770x630039,
23780x640039,
23790x650039,
23800x660039,
23810x670039,
23820x68003b,
23830x690042,
23840x6a0049,
23850x6b0049,
23860x6c0049,
23870x6d0049,
23880x6e0049,
23890x6f0049,
23900x7301b7,
23910x000007,
23920x000007,
23930x000007,
23940x000007,
23950x000007,
23960x000007,
23970x000007,
23980x000007,
23990x000007,
24000x000007,
24010x000007,
24020x000007,
24030x000007,
24040x000007,
24050x000007,
24060x000007,
24070x000007,
24080x000007,
2409};
2410
2411static const u32 RV610_cp_microcode[][3] = {
2412 { 0x00000000, 0xc0200400, 0x000 },
2413 { 0x00000000, 0x00a0000a, 0x000 },
2414 { 0x0000ffff, 0x00284621, 0x000 },
2415 { 0x00000000, 0xd9004800, 0x000 },
2416 { 0x00000000, 0xc0200400, 0x000 },
2417 { 0x00000000, 0x00a0000a, 0x000 },
2418 { 0x00000000, 0x00e00000, 0x000 },
2419 { 0x00010000, 0xc0294620, 0x000 },
2420 { 0x00000000, 0xd9004800, 0x000 },
2421 { 0x00000000, 0xc0200400, 0x000 },
2422 { 0x00000000, 0x00a0000a, 0x000 },
2423 { 0x81000000, 0x00204411, 0x000 },
2424 { 0x00000001, 0x00204811, 0x000 },
2425 { 0x00042004, 0x00604411, 0x68d },
2426 { 0x00000000, 0x00600000, 0x631 },
2427 { 0x00000000, 0x00600000, 0x645 },
2428 { 0x00000000, 0xc0200800, 0x000 },
2429 { 0x00000f00, 0x00281622, 0x000 },
2430 { 0x00000008, 0x00211625, 0x000 },
2431 { 0x00000018, 0x00203625, 0x000 },
2432 { 0x8d000000, 0x00204411, 0x000 },
2433 { 0x00000004, 0x002f0225, 0x000 },
2434 { 0x00000000, 0x0ce00000, 0x018 },
2435 { 0x00412000, 0x00404811, 0x019 },
2436 { 0x00422000, 0x00204811, 0x000 },
2437 { 0x8e000000, 0x00204411, 0x000 },
2438 { 0x00000028, 0x00204a2d, 0x000 },
2439 { 0x90000000, 0x00204411, 0x000 },
2440 { 0x00000000, 0x00204805, 0x000 },
2441 { 0x0000000c, 0x00211622, 0x000 },
2442 { 0x00000003, 0x00281625, 0x000 },
2443 { 0x00000019, 0x00211a22, 0x000 },
2444 { 0x00000004, 0x00281a26, 0x000 },
2445 { 0x00000000, 0x002914c5, 0x000 },
2446 { 0x00000019, 0x00203625, 0x000 },
2447 { 0x00000000, 0x003a1402, 0x000 },
2448 { 0x00000016, 0x00211625, 0x000 },
2449 { 0x00000003, 0x00281625, 0x000 },
2450 { 0x00000017, 0x00200e2d, 0x000 },
2451 { 0xfffffffc, 0x00280e23, 0x000 },
2452 { 0x00000000, 0x002914a3, 0x000 },
2453 { 0x00000017, 0x00203625, 0x000 },
2454 { 0x00008000, 0x00280e22, 0x000 },
2455 { 0x00000007, 0x00220e23, 0x000 },
2456 { 0x00000000, 0x0029386e, 0x000 },
2457 { 0x20000000, 0x00280e22, 0x000 },
2458 { 0x00000006, 0x00210e23, 0x000 },
2459 { 0x00000000, 0x0029386e, 0x000 },
2460 { 0x00000000, 0x00220222, 0x000 },
2461 { 0x00000000, 0x14e00000, 0x038 },
2462 { 0x00000000, 0x2ee00000, 0x035 },
2463 { 0x00000000, 0x2ce00000, 0x037 },
2464 { 0x00000000, 0x00400e2d, 0x039 },
2465 { 0x00000008, 0x00200e2d, 0x000 },
2466 { 0x00000009, 0x0040122d, 0x046 },
2467 { 0x00000001, 0x00400e2d, 0x039 },
2468 { 0x00000000, 0xc0200c00, 0x000 },
2469 { 0x003ffffc, 0x00281223, 0x000 },
2470 { 0x00000002, 0x00221224, 0x000 },
2471 { 0x0000001f, 0x00211e23, 0x000 },
2472 { 0x00000000, 0x14e00000, 0x03e },
2473 { 0x00000008, 0x00401c11, 0x041 },
2474 { 0x0000000d, 0x00201e2d, 0x000 },
2475 { 0x0000000f, 0x00281e27, 0x000 },
2476 { 0x00000003, 0x00221e27, 0x000 },
2477 { 0x7fc00000, 0x00281a23, 0x000 },
2478 { 0x00000014, 0x00211a26, 0x000 },
2479 { 0x00000001, 0x00331a26, 0x000 },
2480 { 0x00000008, 0x00221a26, 0x000 },
2481 { 0x00000000, 0x00290cc7, 0x000 },
2482 { 0x00000027, 0x00203624, 0x000 },
2483 { 0x00007f00, 0x00281221, 0x000 },
2484 { 0x00001400, 0x002f0224, 0x000 },
2485 { 0x00000000, 0x0ce00000, 0x04b },
2486 { 0x00000001, 0x00290e23, 0x000 },
2487 { 0x0000000e, 0x00203623, 0x000 },
2488 { 0x0000e000, 0x00204411, 0x000 },
2489 { 0xfff80000, 0x00294a23, 0x000 },
2490 { 0x00000000, 0x003a2c02, 0x000 },
2491 { 0x00000002, 0x00220e2b, 0x000 },
2492 { 0xfc000000, 0x00280e23, 0x000 },
2493 { 0x0000000f, 0x00203623, 0x000 },
2494 { 0x00001fff, 0x00294a23, 0x000 },
2495 { 0x00000027, 0x00204a2d, 0x000 },
2496 { 0x00000000, 0x00204811, 0x000 },
2497 { 0x00000029, 0x00200e2d, 0x000 },
2498 { 0x060a0200, 0x00294a23, 0x000 },
2499 { 0x00000000, 0x00204811, 0x000 },
2500 { 0x00000000, 0x00204811, 0x000 },
2501 { 0x00000001, 0x00210222, 0x000 },
2502 { 0x00000000, 0x14e00000, 0x061 },
2503 { 0x00000000, 0x2ee00000, 0x05f },
2504 { 0x00000000, 0x2ce00000, 0x05e },
2505 { 0x00000000, 0x00400e2d, 0x062 },
2506 { 0x00000001, 0x00400e2d, 0x062 },
2507 { 0x0000000a, 0x00200e2d, 0x000 },
2508 { 0x0000000b, 0x0040122d, 0x06a },
2509 { 0x00000000, 0xc0200c00, 0x000 },
2510 { 0x003ffffc, 0x00281223, 0x000 },
2511 { 0x00000002, 0x00221224, 0x000 },
2512 { 0x7fc00000, 0x00281623, 0x000 },
2513 { 0x00000014, 0x00211625, 0x000 },
2514 { 0x00000001, 0x00331625, 0x000 },
2515 { 0x80000000, 0x00280e23, 0x000 },
2516 { 0x00000000, 0x00290ca3, 0x000 },
2517 { 0x3ffffc00, 0x00290e23, 0x000 },
2518 { 0x0000001f, 0x00211e23, 0x000 },
2519 { 0x00000000, 0x14e00000, 0x06d },
2520 { 0x00000100, 0x00401c11, 0x070 },
2521 { 0x0000000d, 0x00201e2d, 0x000 },
2522 { 0x000000f0, 0x00281e27, 0x000 },
2523 { 0x00000004, 0x00221e27, 0x000 },
2524 { 0x81000000, 0x00204411, 0x000 },
2525 { 0x0000000d, 0x00204811, 0x000 },
2526 { 0xfffff0ff, 0x00281a30, 0x000 },
2527 { 0x0000a028, 0x00204411, 0x000 },
2528 { 0x00000000, 0x002948e6, 0x000 },
2529 { 0x0000a018, 0x00204411, 0x000 },
2530 { 0x3fffffff, 0x00284a23, 0x000 },
2531 { 0x0000a010, 0x00204411, 0x000 },
2532 { 0x00000000, 0x00204804, 0x000 },
2533 { 0x00000030, 0x0020162d, 0x000 },
2534 { 0x00000002, 0x00291625, 0x000 },
2535 { 0x00000030, 0x00203625, 0x000 },
2536 { 0x00000025, 0x0020162d, 0x000 },
2537 { 0x00000000, 0x002f00a3, 0x000 },
2538 { 0x00000000, 0x0cc00000, 0x083 },
2539 { 0x00000026, 0x0020162d, 0x000 },
2540 { 0x00000000, 0x002f00a4, 0x000 },
2541 { 0x00000000, 0x0cc00000, 0x084 },
2542 { 0x00000000, 0x00400000, 0x08a },
2543 { 0x00000025, 0x00203623, 0x000 },
2544 { 0x00000026, 0x00203624, 0x000 },
2545 { 0x00000017, 0x00201e2d, 0x000 },
2546 { 0x00000002, 0x00210227, 0x000 },
2547 { 0x00000000, 0x14e00000, 0x08a },
2548 { 0x00000000, 0x00600000, 0x668 },
2549 { 0x00000000, 0x00600000, 0x65c },
2550 { 0x00000002, 0x00210e22, 0x000 },
2551 { 0x00000000, 0x14c00000, 0x08d },
2552 { 0x00000012, 0xc0403620, 0x093 },
2553 { 0x00000000, 0x2ee00000, 0x091 },
2554 { 0x00000000, 0x2ce00000, 0x090 },
2555 { 0x00000002, 0x00400e2d, 0x092 },
2556 { 0x00000003, 0x00400e2d, 0x092 },
2557 { 0x0000000c, 0x00200e2d, 0x000 },
2558 { 0x00000012, 0x00203623, 0x000 },
2559 { 0x00000003, 0x00210e22, 0x000 },
2560 { 0x00000000, 0x14c00000, 0x098 },
2561 { 0x0000a00c, 0x00204411, 0x000 },
2562 { 0x00000000, 0xc0204800, 0x000 },
2563 { 0x00000000, 0xc0404800, 0x0a0 },
2564 { 0x0000a00c, 0x00204411, 0x000 },
2565 { 0x00000000, 0x00204811, 0x000 },
2566 { 0x00000000, 0x2ee00000, 0x09e },
2567 { 0x00000000, 0x2ce00000, 0x09d },
2568 { 0x00000002, 0x00400e2d, 0x09f },
2569 { 0x00000003, 0x00400e2d, 0x09f },
2570 { 0x0000000c, 0x00200e2d, 0x000 },
2571 { 0x00000000, 0x00204803, 0x000 },
2572 { 0x00000000, 0x003a0c02, 0x000 },
2573 { 0x003f0000, 0x00280e23, 0x000 },
2574 { 0x00000010, 0x00210e23, 0x000 },
2575 { 0x00000011, 0x00203623, 0x000 },
2576 { 0x0000001e, 0x0021022b, 0x000 },
2577 { 0x00000000, 0x14c00000, 0x0a7 },
2578 { 0x00000016, 0xc0203620, 0x000 },
2579 { 0x0000001f, 0x0021022b, 0x000 },
2580 { 0x00000000, 0x14c00000, 0x0aa },
2581 { 0x00000015, 0xc0203620, 0x000 },
2582 { 0x00000008, 0x00210e2b, 0x000 },
2583 { 0x0000007f, 0x00280e23, 0x000 },
2584 { 0x00000000, 0x002f0223, 0x000 },
2585 { 0x00000000, 0x0ce00000, 0x0e1 },
2586 { 0x00000000, 0x27000000, 0x000 },
2587 { 0x00000000, 0x00600000, 0x2a3 },
2588 { 0x00000001, 0x002f0223, 0x000 },
2589 { 0x00000000, 0x0ae00000, 0x0b3 },
2590 { 0x00000000, 0x00600000, 0x13a },
2591 { 0x81000000, 0x00204411, 0x000 },
2592 { 0x00000006, 0x00204811, 0x000 },
2593 { 0x0000000c, 0x00221e30, 0x000 },
2594 { 0x99800000, 0x00204411, 0x000 },
2595 { 0x00000004, 0x0020122d, 0x000 },
2596 { 0x00000008, 0x00221224, 0x000 },
2597 { 0x00000010, 0x00201811, 0x000 },
2598 { 0x00000000, 0x00291ce4, 0x000 },
2599 { 0x00000000, 0x00604807, 0x12f },
2600 { 0x9b000000, 0x00204411, 0x000 },
2601 { 0x00000000, 0x00204802, 0x000 },
2602 { 0x9c000000, 0x00204411, 0x000 },
2603 { 0x00000000, 0x0033146f, 0x000 },
2604 { 0x00000001, 0x00333e23, 0x000 },
2605 { 0x00000000, 0xd9004800, 0x000 },
2606 { 0x00000000, 0x00203c05, 0x000 },
2607 { 0x81000000, 0x00204411, 0x000 },
2608 { 0x0000000e, 0x00204811, 0x000 },
2609 { 0x00000000, 0x00201010, 0x000 },
2610 { 0x0000e007, 0x00204411, 0x000 },
2611 { 0x0000000f, 0x0021022b, 0x000 },
2612 { 0x00000000, 0x14c00000, 0x0cb },
2613 { 0x00f8ff08, 0x00204811, 0x000 },
2614 { 0x98000000, 0x00404811, 0x0dc },
2615 { 0x000000f0, 0x00280e22, 0x000 },
2616 { 0x000000a0, 0x002f0223, 0x000 },
2617 { 0x00000000, 0x0cc00000, 0x0da },
2618 { 0x00000011, 0x00200e2d, 0x000 },
2619 { 0x00000001, 0x002f0223, 0x000 },
2620 { 0x00000000, 0x0ce00000, 0x0d5 },
2621 { 0x00000002, 0x002f0223, 0x000 },
2622 { 0x00000000, 0x0ce00000, 0x0d4 },
2623 { 0x00003f00, 0x00400c11, 0x0d6 },
2624 { 0x00001f00, 0x00400c11, 0x0d6 },
2625 { 0x00000f00, 0x00200c11, 0x000 },
2626 { 0x00380009, 0x00294a23, 0x000 },
2627 { 0x3f000000, 0x00280e2b, 0x000 },
2628 { 0x00000002, 0x00220e23, 0x000 },
2629 { 0x00000007, 0x00494a23, 0x0dc },
2630 { 0x00380f09, 0x00204811, 0x000 },
2631 { 0x68000007, 0x00204811, 0x000 },
2632 { 0x00000008, 0x00214a27, 0x000 },
2633 { 0x00000000, 0x00204811, 0x000 },
2634 { 0x060a0200, 0x00294a24, 0x000 },
2635 { 0x00000000, 0x00204811, 0x000 },
2636 { 0x00000000, 0x00204811, 0x000 },
2637 { 0x0000a202, 0x00204411, 0x000 },
2638 { 0x00ff0000, 0x00280e22, 0x000 },
2639 { 0x00000080, 0x00294a23, 0x000 },
2640 { 0x00000027, 0x00200e2d, 0x000 },
2641 { 0x00000026, 0x0020122d, 0x000 },
2642 { 0x00000000, 0x002f0083, 0x000 },
2643 { 0x00000000, 0x0ce00000, 0x0ea },
2644 { 0x00000000, 0x00600000, 0x662 },
2645 { 0x00000000, 0x00400000, 0x0eb },
2646 { 0x00000000, 0x00600000, 0x665 },
2647 { 0x00000007, 0x0020222d, 0x000 },
2648 { 0x00000005, 0x00220e22, 0x000 },
2649 { 0x00100000, 0x00280e23, 0x000 },
2650 { 0x00000000, 0x00292068, 0x000 },
2651 { 0x00000000, 0x003a0c02, 0x000 },
2652 { 0x000000ef, 0x00280e23, 0x000 },
2653 { 0x00000000, 0x00292068, 0x000 },
2654 { 0x00000017, 0x00200e2d, 0x000 },
2655 { 0x00000003, 0x00210223, 0x000 },
2656 { 0x00000000, 0x14e00000, 0x0f8 },
2657 { 0x0000000b, 0x00210228, 0x000 },
2658 { 0x00000000, 0x14c00000, 0x0f8 },
2659 { 0x00000400, 0x00292228, 0x000 },
2660 { 0x00000014, 0x00203628, 0x000 },
2661 { 0x0000001c, 0x00210e22, 0x000 },
2662 { 0x00000000, 0x14c00000, 0x0fd },
2663 { 0x0000a30c, 0x00204411, 0x000 },
2664 { 0x00000000, 0x00204811, 0x000 },
2665 { 0x0000001e, 0x00210e22, 0x000 },
2666 { 0x00000000, 0x14c00000, 0x10b },
2667 { 0x0000a30f, 0x00204411, 0x000 },
2668 { 0x00000011, 0x00200e2d, 0x000 },
2669 { 0x00000001, 0x002f0223, 0x000 },
2670 { 0x00000000, 0x0cc00000, 0x104 },
2671 { 0xffffffff, 0x00404811, 0x10b },
2672 { 0x00000002, 0x002f0223, 0x000 },
2673 { 0x00000000, 0x0cc00000, 0x107 },
2674 { 0x0000ffff, 0x00404811, 0x10b },
2675 { 0x00000004, 0x002f0223, 0x000 },
2676 { 0x00000000, 0x0cc00000, 0x10a },
2677 { 0x000000ff, 0x00404811, 0x10b },
2678 { 0x00000001, 0x00204811, 0x000 },
2679 { 0x0002c400, 0x00204411, 0x000 },
2680 { 0x0000001f, 0x00210e22, 0x000 },
2681 { 0x00000000, 0x14c00000, 0x112 },
2682 { 0x00000010, 0x40210e20, 0x000 },
2683 { 0x00000013, 0x00203623, 0x000 },
2684 { 0x00000018, 0x40224a20, 0x000 },
2685 { 0x00000010, 0xc0424a20, 0x114 },
2686 { 0x00000000, 0x00200c11, 0x000 },
2687 { 0x00000013, 0x00203623, 0x000 },
2688 { 0x00000000, 0x00204811, 0x000 },
2689 { 0x00000000, 0x00204811, 0x000 },
2690 { 0x0000000a, 0x00201011, 0x000 },
2691 { 0x00000000, 0x002f0224, 0x000 },
2692 { 0x00000000, 0x0ce00000, 0x11b },
2693 { 0x00000000, 0x00204811, 0x000 },
2694 { 0x00000001, 0x00531224, 0x117 },
2695 { 0xffbfffff, 0x00283a2e, 0x000 },
2696 { 0x0000001b, 0x00210222, 0x000 },
2697 { 0x00000000, 0x14c00000, 0x12e },
2698 { 0x81000000, 0x00204411, 0x000 },
2699 { 0x0000000d, 0x00204811, 0x000 },
2700 { 0x00000018, 0x00220e30, 0x000 },
2701 { 0xfc000000, 0x00280e23, 0x000 },
2702 { 0x81000000, 0x00204411, 0x000 },
2703 { 0x0000000e, 0x00204811, 0x000 },
2704 { 0x00000000, 0x00201010, 0x000 },
2705 { 0x0000e00e, 0x00204411, 0x000 },
2706 { 0x07f8ff08, 0x00204811, 0x000 },
2707 { 0x00000000, 0x00294a23, 0x000 },
2708 { 0x0000001c, 0x00201e2d, 0x000 },
2709 { 0x00000008, 0x00214a27, 0x000 },
2710 { 0x00000000, 0x00204811, 0x000 },
2711 { 0x060a0200, 0x00294a24, 0x000 },
2712 { 0x00000000, 0x00204811, 0x000 },
2713 { 0x00000000, 0x00204811, 0x000 },
2714 { 0x00000000, 0x00800000, 0x000 },
2715 { 0x81000000, 0x00204411, 0x000 },
2716 { 0x00000001, 0x00204811, 0x000 },
2717 { 0x0000217c, 0x00204411, 0x000 },
2718 { 0x00800000, 0x00204811, 0x000 },
2719 { 0x00000000, 0x00204806, 0x000 },
2720 { 0x00000008, 0x00214a27, 0x000 },
2721 { 0x00000000, 0x17000000, 0x000 },
2722 { 0x0004217f, 0x00604411, 0x68d },
2723 { 0x0000001f, 0x00210230, 0x000 },
2724 { 0x00000000, 0x14c00000, 0x68c },
2725 { 0x00000004, 0x00404c11, 0x135 },
2726 { 0x81000000, 0x00204411, 0x000 },
2727 { 0x00000001, 0x00204811, 0x000 },
2728 { 0x000021f8, 0x00204411, 0x000 },
2729 { 0x0000001c, 0x00204811, 0x000 },
2730 { 0x000421f9, 0x00604411, 0x68d },
2731 { 0x00000011, 0x00210230, 0x000 },
2732 { 0x00000000, 0x14e00000, 0x13c },
2733 { 0x00000000, 0x00800000, 0x000 },
2734 { 0x00000000, 0x00600000, 0x00b },
2735 { 0x00000000, 0x00600411, 0x315 },
2736 { 0x00000000, 0x00200411, 0x000 },
2737 { 0x00000000, 0x00600811, 0x1b2 },
2738 { 0x00000000, 0x00600000, 0x160 },
2739 { 0x0000ffff, 0x40280e20, 0x000 },
2740 { 0x00000010, 0xc0211220, 0x000 },
2741 { 0x0000ffff, 0x40280620, 0x000 },
2742 { 0x00000010, 0xc0210a20, 0x000 },
2743 { 0x00000000, 0x00341461, 0x000 },
2744 { 0x00000000, 0x00741882, 0x2bb },
2745 { 0x0001a1fd, 0x00604411, 0x2e0 },
2746 { 0x00003fff, 0x002f022f, 0x000 },
2747 { 0x00000000, 0x0cc00000, 0x147 },
2748 { 0x00000000, 0xc0400400, 0x001 },
2749 { 0x00000000, 0x00600000, 0x00b },
2750 { 0x00000000, 0x00600411, 0x315 },
2751 { 0x00000000, 0x00200411, 0x000 },
2752 { 0x00000000, 0x00600811, 0x1b2 },
2753 { 0x00003fff, 0x002f022f, 0x000 },
2754 { 0x00000000, 0x0ce00000, 0x000 },
2755 { 0x00000000, 0x00600000, 0x160 },
2756 { 0x00000010, 0x40210e20, 0x000 },
2757 { 0x0000ffff, 0xc0281220, 0x000 },
2758 { 0x00000010, 0x40211620, 0x000 },
2759 { 0x0000ffff, 0xc0681a20, 0x2bb },
2760 { 0x0001a1fd, 0x00604411, 0x2e0 },
2761 { 0x00003fff, 0x002f022f, 0x000 },
2762 { 0x00000000, 0x0cc00000, 0x158 },
2763 { 0x00000000, 0xc0400400, 0x001 },
2764 { 0x0000225c, 0x00204411, 0x000 },
2765 { 0x00000001, 0x00300a2f, 0x000 },
2766 { 0x00000001, 0x00210a22, 0x000 },
2767 { 0x00000003, 0x00384a22, 0x000 },
2768 { 0x00002256, 0x00204411, 0x000 },
2769 { 0x0000001a, 0x00204811, 0x000 },
2770 { 0x0000a1fc, 0x00204411, 0x000 },
2771 { 0x00000001, 0x00804811, 0x000 },
2772 { 0x00000000, 0x00600000, 0x00b },
2773 { 0x00000000, 0x00600000, 0x18f },
2774 { 0x00000000, 0x00600000, 0x1a0 },
2775 { 0x00003fff, 0x002f022f, 0x000 },
2776 { 0x00000000, 0x0ce00000, 0x000 },
2777 { 0x00000000, 0x00202c08, 0x000 },
2778 { 0x00000000, 0x00202411, 0x000 },
2779 { 0x00000000, 0x00202811, 0x000 },
2780 { 0x00002256, 0x00204411, 0x000 },
2781 { 0x00000016, 0x00204811, 0x000 },
2782 { 0x0000225c, 0x00204411, 0x000 },
2783 { 0x00000003, 0x00204811, 0x000 },
2784 { 0x93800000, 0x00204411, 0x000 },
2785 { 0x00000002, 0x00221e29, 0x000 },
2786 { 0x00000000, 0x007048eb, 0x19c },
2787 { 0x00000000, 0x00600000, 0x2bb },
2788 { 0x00000001, 0x40330620, 0x000 },
2789 { 0x00000000, 0xc0302409, 0x000 },
2790 { 0x00003fff, 0x002f022f, 0x000 },
2791 { 0x00000000, 0x0ce00000, 0x000 },
2792 { 0x00000000, 0x00600000, 0x2a3 },
2793 { 0x00000000, 0x002f0221, 0x000 },
2794 { 0x00000000, 0x0ae00000, 0x181 },
2795 { 0x00000000, 0x00600000, 0x13a },
2796 { 0x00000000, 0x00400000, 0x186 },
2797 { 0x95000000, 0x00204411, 0x000 },
2798 { 0x00000000, 0x002f0221, 0x000 },
2799 { 0x00000000, 0x0ce00000, 0x186 },
2800 { 0x00000000, 0xc0204800, 0x000 },
2801 { 0x00000001, 0x00530621, 0x182 },
2802 { 0x92000000, 0x00204411, 0x000 },
2803 { 0x00000000, 0xc0604800, 0x197 },
2804 { 0x0001a1fd, 0x00204411, 0x000 },
2805 { 0x00000011, 0x0020062d, 0x000 },
2806 { 0x00000000, 0x0078042a, 0x2fb },
2807 { 0x00000000, 0x00202809, 0x000 },
2808 { 0x00003fff, 0x002f022f, 0x000 },
2809 { 0x00000000, 0x0cc00000, 0x174 },
2810 { 0x00000000, 0xc0400400, 0x001 },
2811 { 0x00000210, 0x00600411, 0x315 },
2812 { 0x00003fff, 0x002f022f, 0x000 },
2813 { 0x00000000, 0x0ce00000, 0x194 },
2814 { 0x00000015, 0xc0203620, 0x000 },
2815 { 0x00000016, 0xc0203620, 0x000 },
2816 { 0x3f800000, 0x00200411, 0x000 },
2817 { 0x46000000, 0x00600811, 0x1b2 },
2818 { 0x00000000, 0x00800000, 0x000 },
2819 { 0x0000a1fc, 0x00204411, 0x000 },
2820 { 0x00003fff, 0x002f022f, 0x000 },
2821 { 0x00000000, 0x0cc00000, 0x19b },
2822 { 0x00000001, 0x00804811, 0x000 },
2823 { 0x00000021, 0x00804811, 0x000 },
2824 { 0x0000ffff, 0x40280e20, 0x000 },
2825 { 0x00000010, 0xc0211220, 0x000 },
2826 { 0x0000ffff, 0x40281620, 0x000 },
2827 { 0x00000010, 0xc0811a20, 0x000 },
2828 { 0x81000000, 0x00204411, 0x000 },
2829 { 0x00000006, 0x00204811, 0x000 },
2830 { 0x00000008, 0x00221e30, 0x000 },
2831 { 0x00000029, 0x00201a2d, 0x000 },
2832 { 0x0000e000, 0x00204411, 0x000 },
2833 { 0xfffbff09, 0x00204811, 0x000 },
2834 { 0x0000000f, 0x0020222d, 0x000 },
2835 { 0x00001fff, 0x00294a28, 0x000 },
2836 { 0x00000006, 0x0020222d, 0x000 },
2837 { 0x00000000, 0x002920e8, 0x000 },
2838 { 0x00000000, 0x00204808, 0x000 },
2839 { 0x00000000, 0x00204811, 0x000 },
2840 { 0x060a0200, 0x00294a26, 0x000 },
2841 { 0x00000000, 0x00204811, 0x000 },
2842 { 0x00000000, 0x00204811, 0x000 },
2843 { 0x00000100, 0x00201811, 0x000 },
2844 { 0x00000008, 0x00621e28, 0x12f },
2845 { 0x00000008, 0x00822228, 0x000 },
2846 { 0x0002c000, 0x00204411, 0x000 },
2847 { 0x00000015, 0x00600e2d, 0x1bd },
2848 { 0x00000016, 0x00600e2d, 0x1bd },
2849 { 0x0000c008, 0x00204411, 0x000 },
2850 { 0x00000017, 0x00200e2d, 0x000 },
2851 { 0x00000000, 0x14c00000, 0x1b9 },
2852 { 0x00000000, 0x00200411, 0x000 },
2853 { 0x00000000, 0x00204801, 0x000 },
2854 { 0x39000000, 0x00204811, 0x000 },
2855 { 0x00000000, 0x00204811, 0x000 },
2856 { 0x00000000, 0x00804802, 0x000 },
2857 { 0x00000018, 0x00202e2d, 0x000 },
2858 { 0x00000000, 0x003b0d63, 0x000 },
2859 { 0x00000008, 0x00224a23, 0x000 },
2860 { 0x00000010, 0x00224a23, 0x000 },
2861 { 0x00000018, 0x00224a23, 0x000 },
2862 { 0x00000000, 0x00804803, 0x000 },
2863 { 0x00000000, 0x00600000, 0x00b },
2864 { 0x00001000, 0x00600411, 0x315 },
2865 { 0x00000000, 0x00200411, 0x000 },
2866 { 0x00000000, 0x00600811, 0x1b2 },
2867 { 0x00000007, 0x0021062f, 0x000 },
2868 { 0x00000013, 0x00200a2d, 0x000 },
2869 { 0x00000001, 0x00202c11, 0x000 },
2870 { 0x0000ffff, 0x40282220, 0x000 },
2871 { 0x0000000f, 0x00262228, 0x000 },
2872 { 0x00000010, 0x40212620, 0x000 },
2873 { 0x0000000f, 0x00262629, 0x000 },
2874 { 0x00000000, 0x00202802, 0x000 },
2875 { 0x00002256, 0x00204411, 0x000 },
2876 { 0x0000001b, 0x00204811, 0x000 },
2877 { 0x00000000, 0x002f0221, 0x000 },
2878 { 0x00000000, 0x0ce00000, 0x1e0 },
2879 { 0x0000225c, 0x00204411, 0x000 },
2880 { 0x00000081, 0x00204811, 0x000 },
2881 { 0x0000a1fc, 0x00204411, 0x000 },
2882 { 0x00000001, 0x00204811, 0x000 },
2883 { 0x00000080, 0x00201c11, 0x000 },
2884 { 0x00000000, 0x002f0227, 0x000 },
2885 { 0x00000000, 0x0ce00000, 0x1dc },
2886 { 0x00000000, 0x00600000, 0x1e9 },
2887 { 0x00000001, 0x00531e27, 0x1d8 },
2888 { 0x00000001, 0x00202c11, 0x000 },
2889 { 0x0000001f, 0x00280a22, 0x000 },
2890 { 0x0000001f, 0x00282a2a, 0x000 },
2891 { 0x00000001, 0x00530621, 0x1d1 },
2892 { 0x0000225c, 0x00204411, 0x000 },
2893 { 0x00000002, 0x00304a2f, 0x000 },
2894 { 0x0000a1fc, 0x00204411, 0x000 },
2895 { 0x00000001, 0x00204811, 0x000 },
2896 { 0x00000001, 0x00301e2f, 0x000 },
2897 { 0x00000000, 0x002f0227, 0x000 },
2898 { 0x00000000, 0x0ce00000, 0x000 },
2899 { 0x00000000, 0x00600000, 0x1e9 },
2900 { 0x00000001, 0x00531e27, 0x1e5 },
2901 { 0x0000ffff, 0x40280e20, 0x000 },
2902 { 0x0000000f, 0x00260e23, 0x000 },
2903 { 0x00000010, 0xc0211220, 0x000 },
2904 { 0x0000000f, 0x00261224, 0x000 },
2905 { 0x00000000, 0x00201411, 0x000 },
2906 { 0x00000000, 0x00601811, 0x2bb },
2907 { 0x0001a1fd, 0x00204411, 0x000 },
2908 { 0x00000000, 0x002f022b, 0x000 },
2909 { 0x00000000, 0x0ce00000, 0x1f8 },
2910 { 0x00000010, 0x00221628, 0x000 },
2911 { 0xffff0000, 0x00281625, 0x000 },
2912 { 0x0000ffff, 0x00281a29, 0x000 },
2913 { 0x00000000, 0x002948c5, 0x000 },
2914 { 0x00000000, 0x0020480a, 0x000 },
2915 { 0x00000000, 0x00202c11, 0x000 },
2916 { 0x00000010, 0x00221623, 0x000 },
2917 { 0xffff0000, 0x00281625, 0x000 },
2918 { 0x0000ffff, 0x00281a24, 0x000 },
2919 { 0x00000000, 0x002948c5, 0x000 },
2920 { 0x00000000, 0x00731503, 0x205 },
2921 { 0x00000000, 0x00201805, 0x000 },
2922 { 0x00000000, 0x00731524, 0x205 },
2923 { 0x00000000, 0x002d14c5, 0x000 },
2924 { 0x00000000, 0x003008a2, 0x000 },
2925 { 0x00000000, 0x00204802, 0x000 },
2926 { 0x00000000, 0x00202802, 0x000 },
2927 { 0x00000000, 0x00202003, 0x000 },
2928 { 0x00000000, 0x00802404, 0x000 },
2929 { 0x0000000f, 0x00210225, 0x000 },
2930 { 0x00000000, 0x14c00000, 0x68c },
2931 { 0x00000000, 0x002b1405, 0x000 },
2932 { 0x00000001, 0x00901625, 0x000 },
2933 { 0x00000000, 0x00600000, 0x00b },
2934 { 0x00000000, 0x00600411, 0x315 },
2935 { 0x00000000, 0x00200411, 0x000 },
2936 { 0x00000000, 0x00600811, 0x1b2 },
2937 { 0x00002256, 0x00204411, 0x000 },
2938 { 0x0000001a, 0x00294a22, 0x000 },
2939 { 0x00000000, 0xc0200000, 0x000 },
2940 { 0x00003fff, 0x002f022f, 0x000 },
2941 { 0x00000000, 0x0ce00000, 0x000 },
2942 { 0x00000000, 0xc0200400, 0x000 },
2943 { 0x0000225c, 0x00204411, 0x000 },
2944 { 0x00000003, 0x00384a21, 0x000 },
2945 { 0x0000a1fc, 0x00204411, 0x000 },
2946 { 0x00000001, 0x00204811, 0x000 },
2947 { 0x0000ffff, 0x40281220, 0x000 },
2948 { 0x00000010, 0xc0211a20, 0x000 },
2949 { 0x0000ffff, 0x40280e20, 0x000 },
2950 { 0x00000010, 0xc0211620, 0x000 },
2951 { 0x00000000, 0x00741465, 0x2bb },
2952 { 0x0001a1fd, 0x00604411, 0x2e0 },
2953 { 0x00000001, 0x00330621, 0x000 },
2954 { 0x00000000, 0x002f0221, 0x000 },
2955 { 0x00000000, 0x0cc00000, 0x219 },
2956 { 0x00003fff, 0x002f022f, 0x000 },
2957 { 0x00000000, 0x0cc00000, 0x212 },
2958 { 0x00000000, 0xc0400400, 0x001 },
2959 { 0x00000000, 0x00600000, 0x645 },
2960 { 0x00000000, 0x0040040f, 0x213 },
2961 { 0x00000000, 0x00600000, 0x631 },
2962 { 0x00000000, 0x00600000, 0x645 },
2963 { 0x00000210, 0x00600411, 0x315 },
2964 { 0x00000000, 0x00600000, 0x1a0 },
2965 { 0x00000000, 0x00600000, 0x19c },
2966 { 0x00000000, 0x00600000, 0x2bb },
2967 { 0x00000000, 0x00600000, 0x2a3 },
2968 { 0x93800000, 0x00204411, 0x000 },
2969 { 0x00000000, 0x00204808, 0x000 },
2970 { 0x00000000, 0x002f022f, 0x000 },
2971 { 0x00000000, 0x0ae00000, 0x232 },
2972 { 0x00000000, 0x00600000, 0x13a },
2973 { 0x00000000, 0x00400000, 0x236 },
2974 { 0x95000000, 0x00204411, 0x000 },
2975 { 0x00000000, 0x002f022f, 0x000 },
2976 { 0x00000000, 0x0ce00000, 0x236 },
2977 { 0x00000000, 0xc0404800, 0x233 },
2978 { 0x92000000, 0x00204411, 0x000 },
2979 { 0x00000000, 0xc0204800, 0x000 },
2980 { 0x00002256, 0x00204411, 0x000 },
2981 { 0x00000016, 0x00204811, 0x000 },
2982 { 0x0000225c, 0x00204411, 0x000 },
2983 { 0x00000003, 0x00204811, 0x000 },
2984 { 0x0000a1fc, 0x00204411, 0x000 },
2985 { 0x00000001, 0x00204811, 0x000 },
2986 { 0x0001a1fd, 0x00204411, 0x000 },
2987 { 0x00000000, 0x00600411, 0x2fb },
2988 { 0x00000000, 0xc0400400, 0x001 },
2989 { 0x00000000, 0x00600000, 0x631 },
2990 { 0x0000a00c, 0x00204411, 0x000 },
2991 { 0x00000000, 0xc0204800, 0x000 },
2992 { 0x00000000, 0xc0404800, 0x000 },
2993 { 0x00000000, 0x00600000, 0x00b },
2994 { 0x00000018, 0x40210a20, 0x000 },
2995 { 0x00000003, 0x002f0222, 0x000 },
2996 { 0x00000000, 0x0ae00000, 0x24c },
2997 { 0x00000014, 0x0020222d, 0x000 },
2998 { 0x00080101, 0x00292228, 0x000 },
2999 { 0x00000014, 0x00203628, 0x000 },
3000 { 0x0000a30c, 0x00204411, 0x000 },
3001 { 0x00000000, 0xc0204800, 0x000 },
3002 { 0x00000000, 0xc0204800, 0x000 },
3003 { 0x00000000, 0xc0404800, 0x251 },
3004 { 0x00000000, 0x00600000, 0x00b },
3005 { 0x00000010, 0x00600411, 0x315 },
3006 { 0x3f800000, 0x00200411, 0x000 },
3007 { 0x00000000, 0x00600811, 0x1b2 },
3008 { 0x0000225c, 0x00204411, 0x000 },
3009 { 0x00000003, 0x00204811, 0x000 },
3010 { 0x00000000, 0x00600000, 0x27c },
3011 { 0x00000017, 0x00201e2d, 0x000 },
3012 { 0x00000001, 0x00211e27, 0x000 },
3013 { 0x00000000, 0x14e00000, 0x26a },
3014 { 0x00000012, 0x00201e2d, 0x000 },
3015 { 0x0000ffff, 0x00281e27, 0x000 },
3016 { 0x00000000, 0x00341c27, 0x000 },
3017 { 0x00000000, 0x12c00000, 0x25f },
3018 { 0x00000000, 0x00201c11, 0x000 },
3019 { 0x00000000, 0x002f00e5, 0x000 },
3020 { 0x00000000, 0x08c00000, 0x262 },
3021 { 0x00000000, 0x00201407, 0x000 },
3022 { 0x00000012, 0x00201e2d, 0x000 },
3023 { 0x00000010, 0x00211e27, 0x000 },
3024 { 0x00000000, 0x00341c47, 0x000 },
3025 { 0x00000000, 0x12c00000, 0x267 },
3026 { 0x00000000, 0x00201c11, 0x000 },
3027 { 0x00000000, 0x002f00e6, 0x000 },
3028 { 0x00000000, 0x08c00000, 0x26a },
3029 { 0x00000000, 0x00201807, 0x000 },
3030 { 0x00000000, 0x00600000, 0x2c1 },
3031 { 0x00002256, 0x00204411, 0x000 },
3032 { 0x00000000, 0x00342023, 0x000 },
3033 { 0x00000000, 0x12c00000, 0x272 },
3034 { 0x00000000, 0x00342044, 0x000 },
3035 { 0x00000000, 0x12c00000, 0x271 },
3036 { 0x00000016, 0x00404811, 0x276 },
3037 { 0x00000018, 0x00404811, 0x276 },
3038 { 0x00000000, 0x00342044, 0x000 },
3039 { 0x00000000, 0x12c00000, 0x275 },
3040 { 0x00000017, 0x00404811, 0x276 },
3041 { 0x00000019, 0x00204811, 0x000 },
3042 { 0x0000a1fc, 0x00204411, 0x000 },
3043 { 0x00000001, 0x00204811, 0x000 },
3044 { 0x0001a1fd, 0x00604411, 0x2e9 },
3045 { 0x00003fff, 0x002f022f, 0x000 },
3046 { 0x00000000, 0x0cc00000, 0x256 },
3047 { 0x00000000, 0xc0400400, 0x001 },
3048 { 0x00000010, 0x40210620, 0x000 },
3049 { 0x0000ffff, 0xc0280a20, 0x000 },
3050 { 0x00000010, 0x40210e20, 0x000 },
3051 { 0x0000ffff, 0xc0281220, 0x000 },
3052 { 0x00000010, 0x40211620, 0x000 },
3053 { 0x0000ffff, 0xc0881a20, 0x000 },
3054 { 0x81000000, 0x00204411, 0x000 },
3055 { 0x00000001, 0x00204811, 0x000 },
3056 { 0x00042004, 0x00604411, 0x68d },
3057 { 0x00000000, 0x00600000, 0x631 },
3058 { 0x00000000, 0xc0600000, 0x2a3 },
3059 { 0x00000005, 0x00200a2d, 0x000 },
3060 { 0x00000008, 0x00220a22, 0x000 },
3061 { 0x0000002b, 0x00201a2d, 0x000 },
3062 { 0x0000001c, 0x00201e2d, 0x000 },
3063 { 0x00007000, 0x00281e27, 0x000 },
3064 { 0x00000000, 0x00311ce6, 0x000 },
3065 { 0x0000002a, 0x00201a2d, 0x000 },
3066 { 0x0000000c, 0x00221a26, 0x000 },
3067 { 0x00000000, 0x002f00e6, 0x000 },
3068 { 0x00000000, 0x06e00000, 0x292 },
3069 { 0x00000000, 0x00201c11, 0x000 },
3070 { 0x00000000, 0x00200c11, 0x000 },
3071 { 0x0000002b, 0x00203623, 0x000 },
3072 { 0x00000010, 0x00201811, 0x000 },
3073 { 0x00000000, 0x00691ce2, 0x12f },
3074 { 0x93800000, 0x00204411, 0x000 },
3075 { 0x00000000, 0x00204807, 0x000 },
3076 { 0x95000000, 0x00204411, 0x000 },
3077 { 0x00000000, 0x002f022f, 0x000 },
3078 { 0x00000000, 0x0ce00000, 0x29d },
3079 { 0x00000001, 0x00333e2f, 0x000 },
3080 { 0x00000000, 0xd9004800, 0x000 },
3081 { 0x92000000, 0x00204411, 0x000 },
3082 { 0x00000000, 0xc0204800, 0x000 },
3083 { 0x0000001c, 0x00403627, 0x000 },
3084 { 0x0000000c, 0xc0220a20, 0x000 },
3085 { 0x00000029, 0x00203622, 0x000 },
3086 { 0x00000028, 0xc0403620, 0x000 },
3087 { 0x0000a2a4, 0x00204411, 0x000 },
3088 { 0x00000009, 0x00204811, 0x000 },
3089 { 0xa1000000, 0x00204411, 0x000 },
3090 { 0x00000001, 0x00804811, 0x000 },
3091 { 0x00000021, 0x00201e2d, 0x000 },
3092 { 0x00000000, 0x002c1ce3, 0x000 },
3093 { 0x00000021, 0x00203627, 0x000 },
3094 { 0x00000022, 0x00201e2d, 0x000 },
3095 { 0x00000000, 0x002c1ce4, 0x000 },
3096 { 0x00000022, 0x00203627, 0x000 },
3097 { 0x00000023, 0x00201e2d, 0x000 },
3098 { 0x00000000, 0x003120a3, 0x000 },
3099 { 0x00000000, 0x002d1d07, 0x000 },
3100 { 0x00000023, 0x00203627, 0x000 },
3101 { 0x00000024, 0x00201e2d, 0x000 },
3102 { 0x00000000, 0x003120c4, 0x000 },
3103 { 0x00000000, 0x002d1d07, 0x000 },
3104 { 0x00000024, 0x00803627, 0x000 },
3105 { 0x00000021, 0x00203623, 0x000 },
3106 { 0x00000022, 0x00203624, 0x000 },
3107 { 0x00000000, 0x00311ca3, 0x000 },
3108 { 0x00000023, 0x00203627, 0x000 },
3109 { 0x00000000, 0x00311cc4, 0x000 },
3110 { 0x00000024, 0x00803627, 0x000 },
3111 { 0x0000001a, 0x00203627, 0x000 },
3112 { 0x0000001b, 0x00203628, 0x000 },
3113 { 0x00000017, 0x00201e2d, 0x000 },
3114 { 0x00000002, 0x00210227, 0x000 },
3115 { 0x00000000, 0x14c00000, 0x2dc },
3116 { 0x00000000, 0x00400000, 0x2d9 },
3117 { 0x0000001a, 0x00203627, 0x000 },
3118 { 0x0000001b, 0x00203628, 0x000 },
3119 { 0x00000017, 0x00201e2d, 0x000 },
3120 { 0x00000002, 0x00210227, 0x000 },
3121 { 0x00000000, 0x14e00000, 0x2d9 },
3122 { 0x00000003, 0x00210227, 0x000 },
3123 { 0x00000000, 0x14e00000, 0x2dc },
3124 { 0x00000023, 0x00201e2d, 0x000 },
3125 { 0x00000000, 0x002e00e1, 0x000 },
3126 { 0x00000000, 0x02c00000, 0x2dc },
3127 { 0x00000021, 0x00201e2d, 0x000 },
3128 { 0x00000000, 0x003120a1, 0x000 },
3129 { 0x00000000, 0x002e00e8, 0x000 },
3130 { 0x00000000, 0x06c00000, 0x2dc },
3131 { 0x00000024, 0x00201e2d, 0x000 },
3132 { 0x00000000, 0x002e00e2, 0x000 },
3133 { 0x00000000, 0x02c00000, 0x2dc },
3134 { 0x00000022, 0x00201e2d, 0x000 },
3135 { 0x00000000, 0x003120c2, 0x000 },
3136 { 0x00000000, 0x002e00e8, 0x000 },
3137 { 0x00000000, 0x06c00000, 0x2dc },
3138 { 0x00000000, 0x00600000, 0x668 },
3139 { 0x00000000, 0x00600000, 0x2b5 },
3140 { 0x00000000, 0x00400000, 0x2de },
3141 { 0x00000000, 0x00600000, 0x2b5 },
3142 { 0x00000000, 0x00600000, 0x65f },
3143 { 0x00000000, 0x00400000, 0x2de },
3144 { 0x00000000, 0x00600000, 0x2a7 },
3145 { 0x00000000, 0x00400000, 0x2de },
3146 { 0x0000001a, 0x00201e2d, 0x000 },
3147 { 0x0000001b, 0x0080222d, 0x000 },
3148 { 0x00000010, 0x00221e23, 0x000 },
3149 { 0x00000000, 0x00294887, 0x000 },
3150 { 0x00000000, 0x00311ca3, 0x000 },
3151 { 0x00000010, 0x00221e27, 0x000 },
3152 { 0x00000000, 0x00294887, 0x000 },
3153 { 0x00000010, 0x00221e23, 0x000 },
3154 { 0x00000000, 0x003120c4, 0x000 },
3155 { 0x0000ffff, 0x00282228, 0x000 },
3156 { 0x00000000, 0x00894907, 0x000 },
3157 { 0x00000010, 0x00221e23, 0x000 },
3158 { 0x00000000, 0x00294887, 0x000 },
3159 { 0x00000010, 0x00221e21, 0x000 },
3160 { 0x00000000, 0x00294847, 0x000 },
3161 { 0x00000000, 0x00311ca3, 0x000 },
3162 { 0x00000010, 0x00221e27, 0x000 },
3163 { 0x00000000, 0x00294887, 0x000 },
3164 { 0x00000000, 0x00311ca1, 0x000 },
3165 { 0x00000010, 0x00221e27, 0x000 },
3166 { 0x00000000, 0x00294847, 0x000 },
3167 { 0x00000010, 0x00221e23, 0x000 },
3168 { 0x00000000, 0x003120c4, 0x000 },
3169 { 0x0000ffff, 0x00282228, 0x000 },
3170 { 0x00000000, 0x00294907, 0x000 },
3171 { 0x00000010, 0x00221e21, 0x000 },
3172 { 0x00000000, 0x003120c2, 0x000 },
3173 { 0x0000ffff, 0x00282228, 0x000 },
3174 { 0x00000000, 0x00894907, 0x000 },
3175 { 0x00000010, 0x00221e23, 0x000 },
3176 { 0x00000000, 0x00294887, 0x000 },
3177 { 0x00000001, 0x00220a21, 0x000 },
3178 { 0x00000000, 0x003308a2, 0x000 },
3179 { 0x00000010, 0x00221e22, 0x000 },
3180 { 0x00000010, 0x00212222, 0x000 },
3181 { 0x00000000, 0x00294907, 0x000 },
3182 { 0x00000000, 0x00311ca3, 0x000 },
3183 { 0x00000010, 0x00221e27, 0x000 },
3184 { 0x00000000, 0x00294887, 0x000 },
3185 { 0x00000001, 0x00220a21, 0x000 },
3186 { 0x00000000, 0x003008a2, 0x000 },
3187 { 0x00000010, 0x00221e22, 0x000 },
3188 { 0x00000010, 0x00212222, 0x000 },
3189 { 0x00000000, 0x00294907, 0x000 },
3190 { 0x00000010, 0x00221e23, 0x000 },
3191 { 0x00000000, 0x003120c4, 0x000 },
3192 { 0x0000ffff, 0x00282228, 0x000 },
3193 { 0x00000000, 0x00294907, 0x000 },
3194 { 0x00000000, 0x003808c5, 0x000 },
3195 { 0x00000000, 0x00300841, 0x000 },
3196 { 0x00000001, 0x00220a22, 0x000 },
3197 { 0x00000000, 0x003308a2, 0x000 },
3198 { 0x00000010, 0x00221e22, 0x000 },
3199 { 0x00000010, 0x00212222, 0x000 },
3200 { 0x00000000, 0x00894907, 0x000 },
3201 { 0x00000017, 0x0020222d, 0x000 },
3202 { 0x00000000, 0x14c00000, 0x318 },
3203 { 0xffffffef, 0x00280621, 0x000 },
3204 { 0x00000014, 0x0020222d, 0x000 },
3205 { 0x0000f8e0, 0x00204411, 0x000 },
3206 { 0x00000000, 0x00294901, 0x000 },
3207 { 0x00000000, 0x00894901, 0x000 },
3208 { 0x00000000, 0x00204811, 0x000 },
3209 { 0x00000000, 0x00204811, 0x000 },
3210 { 0x060a0200, 0x00804811, 0x000 },
3211 { 0x00000000, 0xc0200000, 0x000 },
3212 { 0x97000000, 0xc0204411, 0x000 },
3213 { 0x00000000, 0xc0204811, 0x000 },
3214 { 0x8a000000, 0x00204411, 0x000 },
3215 { 0x00000000, 0x00204811, 0x000 },
3216 { 0x0000225c, 0x00204411, 0x000 },
3217 { 0x00000000, 0xc0204800, 0x000 },
3218 { 0x0000a1fc, 0x00204411, 0x000 },
3219 { 0x00000000, 0xc0204800, 0x000 },
3220 { 0x00000000, 0xc0200400, 0x000 },
3221 { 0x00000000, 0x00a0000a, 0x000 },
3222 { 0x97000000, 0x00204411, 0x000 },
3223 { 0x00000000, 0x00204811, 0x000 },
3224 { 0x8a000000, 0x00204411, 0x000 },
3225 { 0x00000000, 0x00204811, 0x000 },
3226 { 0x0000225c, 0x00204411, 0x000 },
3227 { 0x00000000, 0xc0204800, 0x000 },
3228 { 0x0000a1fc, 0x00204411, 0x000 },
3229 { 0x00000000, 0xc0204800, 0x000 },
3230 { 0x00000000, 0xc0200400, 0x000 },
3231 { 0x00000000, 0x00a0000a, 0x000 },
3232 { 0x97000000, 0x00204411, 0x000 },
3233 { 0x00000000, 0x00204811, 0x000 },
3234 { 0x8a000000, 0x00204411, 0x000 },
3235 { 0x00000000, 0x00204811, 0x000 },
3236 { 0x0000225c, 0x00204411, 0x000 },
3237 { 0x00000000, 0xc0204800, 0x000 },
3238 { 0x0000a1fc, 0x00204411, 0x000 },
3239 { 0x00000000, 0xc0204800, 0x000 },
3240 { 0x0001a1fd, 0x00204411, 0x000 },
3241 { 0x00000000, 0xd9004800, 0x000 },
3242 { 0x00000000, 0xc0200400, 0x000 },
3243 { 0x00000000, 0x00a0000a, 0x000 },
3244 { 0x00002257, 0x00204411, 0x000 },
3245 { 0x00000003, 0xc0484a20, 0x000 },
3246 { 0x0000225d, 0x00204411, 0x000 },
3247 { 0x00000000, 0xc0404800, 0x000 },
3248 { 0x00000000, 0x00600000, 0x645 },
3249 { 0x00000000, 0xc0200800, 0x000 },
3250 { 0x0000225c, 0x00204411, 0x000 },
3251 { 0x00000003, 0x00384a22, 0x000 },
3252 { 0x0000a1fc, 0x00204411, 0x000 },
3253 { 0x00000000, 0xc0204800, 0x000 },
3254 { 0x0001a1fd, 0x00204411, 0x000 },
3255 { 0x00000000, 0x002f0222, 0x000 },
3256 { 0x00000000, 0x0ce00000, 0x000 },
3257 { 0x00000000, 0x40204800, 0x000 },
3258 { 0x00000001, 0x40304a20, 0x000 },
3259 { 0x00000002, 0xc0304a20, 0x000 },
3260 { 0x00000001, 0x00530a22, 0x34b },
3261 { 0x0000003f, 0xc0280a20, 0x000 },
3262 { 0x81000000, 0x00204411, 0x000 },
3263 { 0x00000001, 0x00204811, 0x000 },
3264 { 0x000021f8, 0x00204411, 0x000 },
3265 { 0x00000018, 0x00204811, 0x000 },
3266 { 0x000421f9, 0x00604411, 0x68d },
3267 { 0x00000011, 0x00210230, 0x000 },
3268 { 0x00000000, 0x14e00000, 0x354 },
3269 { 0x00000014, 0x002f0222, 0x000 },
3270 { 0x00000000, 0x0cc00000, 0x364 },
3271 { 0x00002010, 0x00204411, 0x000 },
3272 { 0x00008000, 0x00204811, 0x000 },
3273 { 0x0001a2a4, 0x00204411, 0x000 },
3274 { 0x00000000, 0x00604802, 0x36e },
3275 { 0x00002100, 0x00204411, 0x000 },
3276 { 0x00000000, 0xc0204800, 0x000 },
3277 { 0x00000000, 0xc0204800, 0x000 },
3278 { 0x00000000, 0xc0204800, 0x000 },
3279 { 0x00000000, 0xc0404800, 0x000 },
3280 { 0x00000004, 0x002f0222, 0x000 },
3281 { 0x00000000, 0x0cc00000, 0x36a },
3282 { 0x00002010, 0x00204411, 0x000 },
3283 { 0x00008000, 0x00204811, 0x000 },
3284 { 0x0001a2a4, 0x00204411, 0x000 },
3285 { 0x00000000, 0x00404802, 0x35f },
3286 { 0x00000028, 0x002f0222, 0x000 },
3287 { 0x00000000, 0x0cc00000, 0x5c0 },
3288 { 0x0001a2a4, 0x00204411, 0x000 },
3289 { 0x00000000, 0x00404802, 0x35f },
3290 { 0x0000002c, 0x00203626, 0x000 },
3291 { 0x00000049, 0x00201811, 0x000 },
3292 { 0x0000003f, 0x00204811, 0x000 },
3293 { 0x00000001, 0x00331a26, 0x000 },
3294 { 0x00000000, 0x002f0226, 0x000 },
3295 { 0x00000000, 0x0cc00000, 0x370 },
3296 { 0x0000002c, 0x00801a2d, 0x000 },
3297 { 0x0000003f, 0xc0280a20, 0x000 },
3298 { 0x00000015, 0x002f0222, 0x000 },
3299 { 0x00000000, 0x0ce00000, 0x386 },
3300 { 0x00000006, 0x002f0222, 0x000 },
3301 { 0x00000000, 0x0ce00000, 0x3b1 },
3302 { 0x00000016, 0x002f0222, 0x000 },
3303 { 0x00000000, 0x0ce00000, 0x3b5 },
3304 { 0x00000020, 0x002f0222, 0x000 },
3305 { 0x00000000, 0x0ce00000, 0x39c },
3306 { 0x0000000f, 0x002f0222, 0x000 },
3307 { 0x00000000, 0x0ce00000, 0x3a8 },
3308 { 0x00000010, 0x002f0222, 0x000 },
3309 { 0x00000000, 0x0ce00000, 0x3a8 },
3310 { 0x0000001e, 0x002f0222, 0x000 },
3311 { 0x00000000, 0x0ce00000, 0x390 },
3312 { 0x0000a2a4, 0x00204411, 0x000 },
3313 { 0x00000000, 0x00404802, 0x000 },
3314 { 0x08000000, 0x00290a22, 0x000 },
3315 { 0x00000003, 0x40210e20, 0x000 },
3316 { 0x0000000c, 0xc0211220, 0x000 },
3317 { 0x00080000, 0x00281224, 0x000 },
3318 { 0x00000014, 0xc0221620, 0x000 },
3319 { 0x00000000, 0x002914a4, 0x000 },
3320 { 0x0000a2a4, 0x00204411, 0x000 },
3321 { 0x00000000, 0x002948a2, 0x000 },
3322 { 0x0000a1fe, 0x00204411, 0x000 },
3323 { 0x00000000, 0x00404803, 0x000 },
3324 { 0x81000000, 0x00204411, 0x000 },
3325 { 0x00000001, 0x00204811, 0x000 },
3326 { 0x000021f8, 0x00204411, 0x000 },
3327 { 0x00000016, 0x00204811, 0x000 },
3328 { 0x000421f9, 0x00604411, 0x68d },
3329 { 0x00000015, 0x00210230, 0x000 },
3330 { 0x00000000, 0x14e00000, 0x392 },
3331 { 0x0000210e, 0x00204411, 0x000 },
3332 { 0x00000000, 0xc0204800, 0x000 },
3333 { 0x00000000, 0xc0204800, 0x000 },
3334 { 0x0000a2a4, 0x00204411, 0x000 },
3335 { 0x00000000, 0x00404802, 0x000 },
3336 { 0x81000000, 0x00204411, 0x000 },
3337 { 0x00000001, 0x00204811, 0x000 },
3338 { 0x000021f8, 0x00204411, 0x000 },
3339 { 0x00000017, 0x00204811, 0x000 },
3340 { 0x000421f9, 0x00604411, 0x68d },
3341 { 0x00000003, 0x00210230, 0x000 },
3342 { 0x00000000, 0x14e00000, 0x39e },
3343 { 0x00002108, 0x00204411, 0x000 },
3344 { 0x00000000, 0xc0204800, 0x000 },
3345 { 0x00000000, 0xc0204800, 0x000 },
3346 { 0x0000a2a4, 0x00204411, 0x000 },
3347 { 0x00000000, 0x00404802, 0x000 },
3348 { 0x0000a2a4, 0x00204411, 0x000 },
3349 { 0x00000000, 0x00204802, 0x000 },
3350 { 0x80000000, 0x00204411, 0x000 },
3351 { 0x00000000, 0x00204811, 0x000 },
3352 { 0x81000000, 0x00204411, 0x000 },
3353 { 0x00000010, 0x00204811, 0x000 },
3354 { 0x00000000, 0x00200010, 0x000 },
3355 { 0x00000000, 0x14c00000, 0x3ae },
3356 { 0x00000000, 0x00400000, 0x000 },
3357 { 0x00002010, 0x00204411, 0x000 },
3358 { 0x00008000, 0x00204811, 0x000 },
3359 { 0x0001a2a4, 0x00204411, 0x000 },
3360 { 0x00000006, 0x00404811, 0x000 },
3361 { 0x00002010, 0x00204411, 0x000 },
3362 { 0x00008000, 0x00204811, 0x000 },
3363 { 0x0001a2a4, 0x00204411, 0x000 },
3364 { 0x00000016, 0x00604811, 0x36e },
3365 { 0x00000000, 0x00400000, 0x000 },
3366 { 0x00000000, 0xc0200800, 0x000 },
3367 { 0x00000000, 0xc0200c00, 0x000 },
3368 { 0x0000001d, 0x00210223, 0x000 },
3369 { 0x00000000, 0x14e00000, 0x3ce },
3370 { 0x81000000, 0x00204411, 0x000 },
3371 { 0x00000001, 0x00204811, 0x000 },
3372 { 0x000021f8, 0x00204411, 0x000 },
3373 { 0x00000018, 0x00204811, 0x000 },
3374 { 0x000421f9, 0x00604411, 0x68d },
3375 { 0x00000011, 0x00210230, 0x000 },
3376 { 0x00000000, 0x14e00000, 0x3c0 },
3377 { 0x00002100, 0x00204411, 0x000 },
3378 { 0x00000000, 0x00204802, 0x000 },
3379 { 0x00000000, 0x00204803, 0x000 },
3380 { 0xbabecafe, 0x00204811, 0x000 },
3381 { 0xcafebabe, 0x00204811, 0x000 },
3382 { 0x00002010, 0x00204411, 0x000 },
3383 { 0x00008000, 0x00204811, 0x000 },
3384 { 0x0000a2a4, 0x00204411, 0x000 },
3385 { 0x00000004, 0x00404811, 0x000 },
3386 { 0x00002170, 0x00204411, 0x000 },
3387 { 0x00000000, 0x00204802, 0x000 },
3388 { 0x00000000, 0x00204803, 0x000 },
3389 { 0x81000000, 0x00204411, 0x000 },
3390 { 0x0000000a, 0x00204811, 0x000 },
3391 { 0x00000000, 0x00200010, 0x000 },
3392 { 0x00000000, 0x14c00000, 0x3d3 },
3393 { 0x8c000000, 0x00204411, 0x000 },
3394 { 0xcafebabe, 0x00404811, 0x000 },
3395 { 0x81000000, 0x00204411, 0x000 },
3396 { 0x00000001, 0x00204811, 0x000 },
3397 { 0x00003fff, 0x40280a20, 0x000 },
3398 { 0x80000000, 0x40280e20, 0x000 },
3399 { 0x40000000, 0xc0281220, 0x000 },
3400 { 0x00040000, 0x00694622, 0x68d },
3401 { 0x00000000, 0x00201410, 0x000 },
3402 { 0x00000000, 0x002f0223, 0x000 },
3403 { 0x00000000, 0x0cc00000, 0x3e1 },
3404 { 0x00000000, 0xc0401800, 0x3e4 },
3405 { 0x00003fff, 0xc0281a20, 0x000 },
3406 { 0x00040000, 0x00694626, 0x68d },
3407 { 0x00000000, 0x00201810, 0x000 },
3408 { 0x00000000, 0x002f0224, 0x000 },
3409 { 0x00000000, 0x0cc00000, 0x3e7 },
3410 { 0x00000000, 0xc0401c00, 0x3ea },
3411 { 0x00003fff, 0xc0281e20, 0x000 },
3412 { 0x00040000, 0x00694627, 0x68d },
3413 { 0x00000000, 0x00201c10, 0x000 },
3414 { 0x00000000, 0x00204402, 0x000 },
3415 { 0x00000000, 0x002820c5, 0x000 },
3416 { 0x00000000, 0x004948e8, 0x000 },
3417 { 0xa5800000, 0x00200811, 0x000 },
3418 { 0x00002000, 0x00200c11, 0x000 },
3419 { 0x83000000, 0x00604411, 0x412 },
3420 { 0x00000000, 0x00204402, 0x000 },
3421 { 0x00000000, 0xc0204800, 0x000 },
3422 { 0x00000000, 0x40204800, 0x000 },
3423 { 0x0000001f, 0xc0210220, 0x000 },
3424 { 0x00000000, 0x14c00000, 0x3f7 },
3425 { 0x00002010, 0x00204411, 0x000 },
3426 { 0x00008000, 0x00204811, 0x000 },
3427 { 0x0000ffff, 0xc0481220, 0x3ff },
3428 { 0xa7800000, 0x00200811, 0x000 },
3429 { 0x0000a000, 0x00200c11, 0x000 },
3430 { 0x83000000, 0x00604411, 0x412 },
3431 { 0x00000000, 0x00204402, 0x000 },
3432 { 0x00000000, 0xc0204800, 0x000 },
3433 { 0x00000000, 0xc0204800, 0x000 },
3434 { 0x0000ffff, 0xc0281220, 0x000 },
3435 { 0x83000000, 0x00204411, 0x000 },
3436 { 0x00000000, 0x00304883, 0x000 },
3437 { 0x84000000, 0x00204411, 0x000 },
3438 { 0x00000000, 0xc0204800, 0x000 },
3439 { 0x00000000, 0x1d000000, 0x000 },
3440 { 0x83000000, 0x00604411, 0x412 },
3441 { 0x00000000, 0xc0400400, 0x001 },
3442 { 0xa9800000, 0x00200811, 0x000 },
3443 { 0x0000c000, 0x00400c11, 0x3fa },
3444 { 0xab800000, 0x00200811, 0x000 },
3445 { 0x0000f8e0, 0x00400c11, 0x3fa },
3446 { 0xad800000, 0x00200811, 0x000 },
3447 { 0x0000f880, 0x00400c11, 0x3fa },
3448 { 0xb3800000, 0x00200811, 0x000 },
3449 { 0x0000f3fc, 0x00400c11, 0x3fa },
3450 { 0xaf800000, 0x00200811, 0x000 },
3451 { 0x0000e000, 0x00400c11, 0x3fa },
3452 { 0xb1800000, 0x00200811, 0x000 },
3453 { 0x0000f000, 0x00400c11, 0x3fa },
3454 { 0x83000000, 0x00204411, 0x000 },
3455 { 0x00002148, 0x00204811, 0x000 },
3456 { 0x84000000, 0x00204411, 0x000 },
3457 { 0x00000000, 0xc0204800, 0x000 },
3458 { 0x00000000, 0x1d000000, 0x000 },
3459 { 0x00000000, 0x00800000, 0x000 },
3460 { 0x01182000, 0xc0304620, 0x000 },
3461 { 0x00000000, 0xd9004800, 0x000 },
3462 { 0x00000000, 0xc0200400, 0x000 },
3463 { 0x00000000, 0x00a0000a, 0x000 },
3464 { 0x0218a000, 0xc0304620, 0x000 },
3465 { 0x00000000, 0xd9004800, 0x000 },
3466 { 0x00000000, 0xc0200400, 0x000 },
3467 { 0x00000000, 0x00a0000a, 0x000 },
3468 { 0x0318c000, 0xc0304620, 0x000 },
3469 { 0x00000000, 0xd9004800, 0x000 },
3470 { 0x00000000, 0xc0200400, 0x000 },
3471 { 0x00000000, 0x00a0000a, 0x000 },
3472 { 0x0418f8e0, 0xc0304620, 0x000 },
3473 { 0x00000000, 0xd9004800, 0x000 },
3474 { 0x00000000, 0xc0200400, 0x000 },
3475 { 0x00000000, 0x00a0000a, 0x000 },
3476 { 0x0518f880, 0xc0304620, 0x000 },
3477 { 0x00000000, 0xd9004800, 0x000 },
3478 { 0x00000000, 0xc0200400, 0x000 },
3479 { 0x00000000, 0x00a0000a, 0x000 },
3480 { 0x0618e000, 0xc0304620, 0x000 },
3481 { 0x00000000, 0xd9004800, 0x000 },
3482 { 0x00000000, 0xc0200400, 0x000 },
3483 { 0x00000000, 0x00a0000a, 0x000 },
3484 { 0x0718f000, 0xc0304620, 0x000 },
3485 { 0x00000000, 0xd9004800, 0x000 },
3486 { 0x00000000, 0xc0200400, 0x000 },
3487 { 0x00000000, 0x00a0000a, 0x000 },
3488 { 0x0818f3fc, 0xc0304620, 0x000 },
3489 { 0x00000000, 0xd9004800, 0x000 },
3490 { 0x00000000, 0xc0200400, 0x000 },
3491 { 0x00000000, 0x00a0000a, 0x000 },
3492 { 0x00000030, 0x00200a2d, 0x000 },
3493 { 0x00000000, 0xc0290c40, 0x000 },
3494 { 0x00000030, 0x00203623, 0x000 },
3495 { 0x00000000, 0xc0200400, 0x000 },
3496 { 0x00000000, 0x00a0000a, 0x000 },
3497 { 0x86000000, 0x00204411, 0x000 },
3498 { 0x00000000, 0x00404801, 0x000 },
3499 { 0x85000000, 0xc0204411, 0x000 },
3500 { 0x00000000, 0x00404801, 0x000 },
3501 { 0x0000217c, 0x00204411, 0x000 },
3502 { 0x00000018, 0x40210220, 0x000 },
3503 { 0x00000000, 0x14c00000, 0x445 },
3504 { 0x00800000, 0xc0494a20, 0x446 },
3505 { 0x00000000, 0xc0204800, 0x000 },
3506 { 0x00000000, 0xc0204800, 0x000 },
3507 { 0x00000000, 0xc0204800, 0x000 },
3508 { 0x81000000, 0x00204411, 0x000 },
3509 { 0x00000001, 0x00204811, 0x000 },
3510 { 0x00000000, 0xc0200800, 0x000 },
3511 { 0x00000000, 0x17000000, 0x000 },
3512 { 0x0004217f, 0x00604411, 0x68d },
3513 { 0x0000001f, 0x00210230, 0x000 },
3514 { 0x00000000, 0x14c00000, 0x000 },
3515 { 0x00000000, 0x00404c02, 0x44b },
3516 { 0x00000000, 0xc0200c00, 0x000 },
3517 { 0x00000000, 0xc0201000, 0x000 },
3518 { 0x00000000, 0xc0201400, 0x000 },
3519 { 0x00000000, 0xc0201800, 0x000 },
3520 { 0x00000000, 0xc0201c00, 0x000 },
3521 { 0x00007f00, 0x00280a21, 0x000 },
3522 { 0x00004500, 0x002f0222, 0x000 },
3523 { 0x00000000, 0x0ce00000, 0x459 },
3524 { 0x00000000, 0xc0202000, 0x000 },
3525 { 0x00000000, 0x17000000, 0x000 },
3526 { 0x00000010, 0x00280a23, 0x000 },
3527 { 0x00000010, 0x002f0222, 0x000 },
3528 { 0x00000000, 0x0ce00000, 0x461 },
3529 { 0x81000000, 0x00204411, 0x000 },
3530 { 0x00000001, 0x00204811, 0x000 },
3531 { 0x00040000, 0x00694624, 0x68d },
3532 { 0x00000000, 0x00400000, 0x466 },
3533 { 0x81000000, 0x00204411, 0x000 },
3534 { 0x00000000, 0x00204811, 0x000 },
3535 { 0x0000216d, 0x00204411, 0x000 },
3536 { 0x00000000, 0x00204804, 0x000 },
3537 { 0x00000000, 0x00604805, 0x692 },
3538 { 0x00000000, 0x002824f0, 0x000 },
3539 { 0x00000007, 0x00280a23, 0x000 },
3540 { 0x00000001, 0x002f0222, 0x000 },
3541 { 0x00000000, 0x0ae00000, 0x46d },
3542 { 0x00000000, 0x002f00c9, 0x000 },
3543 { 0x00000000, 0x04e00000, 0x486 },
3544 { 0x00000000, 0x00400000, 0x493 },
3545 { 0x00000002, 0x002f0222, 0x000 },
3546 { 0x00000000, 0x0ae00000, 0x472 },
3547 { 0x00000000, 0x002f00c9, 0x000 },
3548 { 0x00000000, 0x02e00000, 0x486 },
3549 { 0x00000000, 0x00400000, 0x493 },
3550 { 0x00000003, 0x002f0222, 0x000 },
3551 { 0x00000000, 0x0ae00000, 0x477 },
3552 { 0x00000000, 0x002f00c9, 0x000 },
3553 { 0x00000000, 0x0ce00000, 0x486 },
3554 { 0x00000000, 0x00400000, 0x493 },
3555 { 0x00000004, 0x002f0222, 0x000 },
3556 { 0x00000000, 0x0ae00000, 0x47c },
3557 { 0x00000000, 0x002f00c9, 0x000 },
3558 { 0x00000000, 0x0ae00000, 0x486 },
3559 { 0x00000000, 0x00400000, 0x493 },
3560 { 0x00000005, 0x002f0222, 0x000 },
3561 { 0x00000000, 0x0ae00000, 0x481 },
3562 { 0x00000000, 0x002f00c9, 0x000 },
3563 { 0x00000000, 0x06e00000, 0x486 },
3564 { 0x00000000, 0x00400000, 0x493 },
3565 { 0x00000006, 0x002f0222, 0x000 },
3566 { 0x00000000, 0x0ae00000, 0x486 },
3567 { 0x00000000, 0x002f00c9, 0x000 },
3568 { 0x00000000, 0x08e00000, 0x486 },
3569 { 0x00000000, 0x00400000, 0x493 },
3570 { 0x00007f00, 0x00280a21, 0x000 },
3571 { 0x00004500, 0x002f0222, 0x000 },
3572 { 0x00000000, 0x0ae00000, 0x000 },
3573 { 0x00000008, 0x00210a23, 0x000 },
3574 { 0x00000000, 0x14c00000, 0x490 },
3575 { 0x00002169, 0x00204411, 0x000 },
3576 { 0x00000000, 0xc0204800, 0x000 },
3577 { 0x00000000, 0xc0204800, 0x000 },
3578 { 0x00000000, 0xc0204800, 0x000 },
3579 { 0xcafebabe, 0x00404811, 0x000 },
3580 { 0x00000000, 0xc0204400, 0x000 },
3581 { 0x00000000, 0xc0200000, 0x000 },
3582 { 0x00000000, 0xc0404800, 0x000 },
3583 { 0x00007f00, 0x00280a21, 0x000 },
3584 { 0x00004500, 0x002f0222, 0x000 },
3585 { 0x00000000, 0x0ae00000, 0x499 },
3586 { 0x00000000, 0xc0200000, 0x000 },
3587 { 0x00000000, 0xc0200000, 0x000 },
3588 { 0x00000000, 0xc0400000, 0x000 },
3589 { 0x00000000, 0x00404c08, 0x459 },
3590 { 0x00000000, 0xc0200800, 0x000 },
3591 { 0x00000010, 0x40210e20, 0x000 },
3592 { 0x00000011, 0x40211220, 0x000 },
3593 { 0x00000012, 0x40211620, 0x000 },
3594 { 0x00002169, 0x00204411, 0x000 },
3595 { 0x00000000, 0x00204802, 0x000 },
3596 { 0x00000000, 0x00210225, 0x000 },
3597 { 0x00000000, 0x14e00000, 0x4a3 },
3598 { 0x00040000, 0xc0494a20, 0x4a4 },
3599 { 0xfffbffff, 0xc0284a20, 0x000 },
3600 { 0x00000000, 0x00210223, 0x000 },
3601 { 0x00000000, 0x14e00000, 0x4b0 },
3602 { 0x00000000, 0xc0204800, 0x000 },
3603 { 0x00000000, 0xc0204800, 0x000 },
3604 { 0x00000000, 0x00210224, 0x000 },
3605 { 0x00000000, 0x14c00000, 0x000 },
3606 { 0x81000000, 0x00204411, 0x000 },
3607 { 0x0000000c, 0x00204811, 0x000 },
3608 { 0x00000000, 0x00200010, 0x000 },
3609 { 0x00000000, 0x14c00000, 0x4ac },
3610 { 0xa0000000, 0x00204411, 0x000 },
3611 { 0xcafebabe, 0x00404811, 0x000 },
3612 { 0x81000000, 0x00204411, 0x000 },
3613 { 0x00000004, 0x00204811, 0x000 },
3614 { 0x0000216b, 0x00204411, 0x000 },
3615 { 0x00000000, 0xc0204810, 0x000 },
3616 { 0x81000000, 0x00204411, 0x000 },
3617 { 0x00000005, 0x00204811, 0x000 },
3618 { 0x0000216c, 0x00204411, 0x000 },
3619 { 0x00000000, 0xc0204810, 0x000 },
3620 { 0x00000000, 0x002f0224, 0x000 },
3621 { 0x00000000, 0x0ce00000, 0x000 },
3622 { 0x00000000, 0x00400000, 0x4aa },
3623 { 0x00000000, 0xc0210a20, 0x000 },
3624 { 0x00000000, 0x14c00000, 0x4c3 },
3625 { 0x81000000, 0x00204411, 0x000 },
3626 { 0x00000000, 0x00204811, 0x000 },
3627 { 0x0000216d, 0x00204411, 0x000 },
3628 { 0x00000000, 0xc0204800, 0x000 },
3629 { 0x00000000, 0xc0604800, 0x692 },
3630 { 0x00000000, 0x00400000, 0x4c7 },
3631 { 0x81000000, 0x00204411, 0x000 },
3632 { 0x00000001, 0x00204811, 0x000 },
3633 { 0x00040000, 0xc0294620, 0x000 },
3634 { 0x00000000, 0xc0600000, 0x68d },
3635 { 0x00000001, 0x00210222, 0x000 },
3636 { 0x00000000, 0x14c00000, 0x4ce },
3637 { 0x00002169, 0x00204411, 0x000 },
3638 { 0x00000000, 0xc0204800, 0x000 },
3639 { 0x00000000, 0xc0204800, 0x000 },
3640 { 0x00000000, 0x00204810, 0x000 },
3641 { 0xcafebabe, 0x00404811, 0x000 },
3642 { 0x00000000, 0xc0204400, 0x000 },
3643 { 0x00000000, 0xc0404810, 0x000 },
3644 { 0x81000000, 0x00204411, 0x000 },
3645 { 0x00000001, 0x00204811, 0x000 },
3646 { 0x000021f8, 0x00204411, 0x000 },
3647 { 0x0000000e, 0x00204811, 0x000 },
3648 { 0x000421f9, 0x00604411, 0x68d },
3649 { 0x00000000, 0x00210230, 0x000 },
3650 { 0x00000000, 0x14c00000, 0x4d0 },
3651 { 0x00002180, 0x00204411, 0x000 },
3652 { 0x00000000, 0xc0204800, 0x000 },
3653 { 0x00000000, 0xc0200000, 0x000 },
3654 { 0x00000000, 0xc0204800, 0x000 },
3655 { 0x00000000, 0xc0200000, 0x000 },
3656 { 0x00000000, 0xc0404800, 0x000 },
3657 { 0x00000003, 0x00333e2f, 0x000 },
3658 { 0x00000001, 0x00210221, 0x000 },
3659 { 0x00000000, 0x14e00000, 0x500 },
3660 { 0x0000002c, 0x00200a2d, 0x000 },
3661 { 0x00040000, 0x18e00c11, 0x4ef },
3662 { 0x00000001, 0x00333e2f, 0x000 },
3663 { 0x00002169, 0x00204411, 0x000 },
3664 { 0x00000000, 0x00204802, 0x000 },
3665 { 0x00000000, 0x00204803, 0x000 },
3666 { 0x00000008, 0x00300a22, 0x000 },
3667 { 0x00000000, 0xc0204800, 0x000 },
3668 { 0x00000000, 0xc0204800, 0x000 },
3669 { 0x00002169, 0x00204411, 0x000 },
3670 { 0x00000000, 0x00204802, 0x000 },
3671 { 0x00000000, 0x00204803, 0x000 },
3672 { 0x00000008, 0x00300a22, 0x000 },
3673 { 0x00000000, 0xc0204800, 0x000 },
3674 { 0x00000000, 0xd8c04800, 0x4e3 },
3675 { 0x00002169, 0x00204411, 0x000 },
3676 { 0x00000000, 0x00204802, 0x000 },
3677 { 0x00000000, 0x00204803, 0x000 },
3678 { 0x00000008, 0x00300a22, 0x000 },
3679 { 0x00000000, 0xc0204800, 0x000 },
3680 { 0x00000000, 0xc0204800, 0x000 },
3681 { 0x0000002d, 0x0020122d, 0x000 },
3682 { 0x00000000, 0x00290c83, 0x000 },
3683 { 0x00002169, 0x00204411, 0x000 },
3684 { 0x00000000, 0x00204802, 0x000 },
3685 { 0x00000000, 0x00204803, 0x000 },
3686 { 0x00000008, 0x00300a22, 0x000 },
3687 { 0x00000000, 0xc0204800, 0x000 },
3688 { 0x00000000, 0xc0204800, 0x000 },
3689 { 0x00000011, 0x00210224, 0x000 },
3690 { 0x00000000, 0x14c00000, 0x000 },
3691 { 0x00000000, 0x00400000, 0x4aa },
3692 { 0x0000002c, 0xc0203620, 0x000 },
3693 { 0x0000002d, 0xc0403620, 0x000 },
3694 { 0x0000000f, 0x00210221, 0x000 },
3695 { 0x00000000, 0x14c00000, 0x505 },
3696 { 0x00000000, 0x00600000, 0x00b },
3697 { 0x00000000, 0xd9000000, 0x000 },
3698 { 0x00000000, 0xc0400400, 0x001 },
3699 { 0xb5000000, 0x00204411, 0x000 },
3700 { 0x00002000, 0x00204811, 0x000 },
3701 { 0xb6000000, 0x00204411, 0x000 },
3702 { 0x0000a000, 0x00204811, 0x000 },
3703 { 0xb7000000, 0x00204411, 0x000 },
3704 { 0x0000c000, 0x00204811, 0x000 },
3705 { 0xb8000000, 0x00204411, 0x000 },
3706 { 0x0000f8e0, 0x00204811, 0x000 },
3707 { 0xb9000000, 0x00204411, 0x000 },
3708 { 0x0000f880, 0x00204811, 0x000 },
3709 { 0xba000000, 0x00204411, 0x000 },
3710 { 0x0000e000, 0x00204811, 0x000 },
3711 { 0xbb000000, 0x00204411, 0x000 },
3712 { 0x0000f000, 0x00204811, 0x000 },
3713 { 0xbc000000, 0x00204411, 0x000 },
3714 { 0x0000f3fc, 0x00204811, 0x000 },
3715 { 0x81000000, 0x00204411, 0x000 },
3716 { 0x00000002, 0x00204811, 0x000 },
3717 { 0x000000ff, 0x00280e30, 0x000 },
3718 { 0x00000000, 0x002f0223, 0x000 },
3719 { 0x00000000, 0x0cc00000, 0x519 },
3720 { 0x00000000, 0xc0200800, 0x000 },
3721 { 0x00000000, 0x14c00000, 0x52e },
3722 { 0x00000000, 0x00200c11, 0x000 },
3723 { 0x0000001c, 0x00203623, 0x000 },
3724 { 0x0000002b, 0x00203623, 0x000 },
3725 { 0x00000029, 0x00203623, 0x000 },
3726 { 0x00000028, 0x00203623, 0x000 },
3727 { 0x00000017, 0x00203623, 0x000 },
3728 { 0x00000025, 0x00203623, 0x000 },
3729 { 0x00000026, 0x00203623, 0x000 },
3730 { 0x00000015, 0x00203623, 0x000 },
3731 { 0x00000016, 0x00203623, 0x000 },
3732 { 0xffffe000, 0x00200c11, 0x000 },
3733 { 0x00000021, 0x00203623, 0x000 },
3734 { 0x00000022, 0x00203623, 0x000 },
3735 { 0x00001fff, 0x00200c11, 0x000 },
3736 { 0x00000023, 0x00203623, 0x000 },
3737 { 0x00000024, 0x00203623, 0x000 },
3738 { 0xf1ffffff, 0x00283a2e, 0x000 },
3739 { 0x0000001a, 0xc0220e20, 0x000 },
3740 { 0x00000000, 0x0029386e, 0x000 },
3741 { 0x81000000, 0x00204411, 0x000 },
3742 { 0x00000006, 0x00204811, 0x000 },
3743 { 0x0000002a, 0x40203620, 0x000 },
3744 { 0x87000000, 0x00204411, 0x000 },
3745 { 0x00000000, 0xc0204800, 0x000 },
3746 { 0x0000a1f4, 0x00204411, 0x000 },
3747 { 0x00000000, 0x00204810, 0x000 },
3748 { 0x00000000, 0x00200c11, 0x000 },
3749 { 0x00000030, 0x00203623, 0x000 },
3750 { 0x9d000000, 0x00204411, 0x000 },
3751 { 0x0000001f, 0x40214a20, 0x000 },
3752 { 0x96000000, 0x00204411, 0x000 },
3753 { 0x00000000, 0xc0204800, 0x000 },
3754 { 0x00000000, 0xc0200c00, 0x000 },
3755 { 0x00000000, 0xc0201000, 0x000 },
3756 { 0x0000001f, 0x00211624, 0x000 },
3757 { 0x00000000, 0x14c00000, 0x000 },
3758 { 0x0000001d, 0x00203623, 0x000 },
3759 { 0x00000003, 0x00281e23, 0x000 },
3760 { 0x00000008, 0x00222223, 0x000 },
3761 { 0xfffff000, 0x00282228, 0x000 },
3762 { 0x00000000, 0x002920e8, 0x000 },
3763 { 0x0000001f, 0x00203628, 0x000 },
3764 { 0x00000018, 0x00211e23, 0x000 },
3765 { 0x00000020, 0x00203627, 0x000 },
3766 { 0x00000002, 0x00221624, 0x000 },
3767 { 0x00000000, 0x003014a8, 0x000 },
3768 { 0x0000001e, 0x00203625, 0x000 },
3769 { 0x00000003, 0x00211a24, 0x000 },
3770 { 0x10000000, 0x00281a26, 0x000 },
3771 { 0xefffffff, 0x00283a2e, 0x000 },
3772 { 0x00000000, 0x004938ce, 0x67b },
3773 { 0x00000001, 0x40280a20, 0x000 },
3774 { 0x00000006, 0x40280e20, 0x000 },
3775 { 0x00000300, 0xc0281220, 0x000 },
3776 { 0x00000008, 0x00211224, 0x000 },
3777 { 0x00000000, 0xc0201620, 0x000 },
3778 { 0x00000000, 0xc0201a20, 0x000 },
3779 { 0x00000000, 0x00210222, 0x000 },
3780 { 0x00000000, 0x14c00000, 0x566 },
3781 { 0x81000000, 0x00204411, 0x000 },
3782 { 0x00000001, 0x00204811, 0x000 },
3783 { 0x00002258, 0x00300a24, 0x000 },
3784 { 0x00040000, 0x00694622, 0x68d },
3785 { 0x00002169, 0x00204411, 0x000 },
3786 { 0x00000000, 0x00204805, 0x000 },
3787 { 0x00020000, 0x00294a26, 0x000 },
3788 { 0x00000000, 0x00204810, 0x000 },
3789 { 0xcafebabe, 0x00204811, 0x000 },
3790 { 0x00000002, 0x002f0223, 0x000 },
3791 { 0x00000000, 0x0cc00000, 0x56e },
3792 { 0x00000000, 0xc0201c10, 0x000 },
3793 { 0x00000000, 0xc0400000, 0x57c },
3794 { 0x00000002, 0x002f0223, 0x000 },
3795 { 0x00000000, 0x0cc00000, 0x56e },
3796 { 0x81000000, 0x00204411, 0x000 },
3797 { 0x00000001, 0x00204811, 0x000 },
3798 { 0x00002258, 0x00300a24, 0x000 },
3799 { 0x00040000, 0x00694622, 0x68d },
3800 { 0x00000000, 0xc0201c10, 0x000 },
3801 { 0x00000000, 0xc0400000, 0x57c },
3802 { 0x00000000, 0x002f0223, 0x000 },
3803 { 0x00000000, 0x0cc00000, 0x572 },
3804 { 0x00000000, 0xc0201c00, 0x000 },
3805 { 0x00000000, 0xc0400000, 0x57c },
3806 { 0x00000004, 0x002f0223, 0x000 },
3807 { 0x00000000, 0x0cc00000, 0x57a },
3808 { 0x81000000, 0x00204411, 0x000 },
3809 { 0x00000000, 0x00204811, 0x000 },
3810 { 0x0000216d, 0x00204411, 0x000 },
3811 { 0x00000000, 0xc0204800, 0x000 },
3812 { 0x00000000, 0xc0604800, 0x692 },
3813 { 0x00000000, 0x00401c10, 0x57c },
3814 { 0x00000000, 0xc0200000, 0x000 },
3815 { 0x00000000, 0xc0400000, 0x000 },
3816 { 0x00000000, 0x0ee00000, 0x57e },
3817 { 0x00000000, 0x00600000, 0x5c9 },
3818 { 0x00000000, 0x002f0224, 0x000 },
3819 { 0x00000000, 0x0cc00000, 0x58f },
3820 { 0x0000a2b7, 0x00204411, 0x000 },
3821 { 0x00000000, 0x00204807, 0x000 },
3822 { 0x81000000, 0x00204411, 0x000 },
3823 { 0x00000001, 0x00204811, 0x000 },
3824 { 0x0004a2b6, 0x00604411, 0x68d },
3825 { 0x0000001a, 0x00212230, 0x000 },
3826 { 0x00000006, 0x00222630, 0x000 },
3827 { 0x00042004, 0x00604411, 0x68d },
3828 { 0x0000a2c4, 0x00204411, 0x000 },
3829 { 0x00000000, 0x003048e9, 0x000 },
3830 { 0x00000000, 0x00e00000, 0x58d },
3831 { 0x0000a2d1, 0x00204411, 0x000 },
3832 { 0x00000000, 0x00404808, 0x000 },
3833 { 0x0000a2d1, 0x00204411, 0x000 },
3834 { 0x00000001, 0x00504a28, 0x000 },
3835 { 0x00000001, 0x002f0224, 0x000 },
3836 { 0x00000000, 0x0cc00000, 0x5a0 },
3837 { 0x0000a2bb, 0x00204411, 0x000 },
3838 { 0x00000000, 0x00204807, 0x000 },
3839 { 0x81000000, 0x00204411, 0x000 },
3840 { 0x00000001, 0x00204811, 0x000 },
3841 { 0x0004a2ba, 0x00604411, 0x68d },
3842 { 0x0000001a, 0x00212230, 0x000 },
3843 { 0x00000006, 0x00222630, 0x000 },
3844 { 0x00042004, 0x00604411, 0x68d },
3845 { 0x0000a2c5, 0x00204411, 0x000 },
3846 { 0x00000000, 0x003048e9, 0x000 },
3847 { 0x00000000, 0x00e00000, 0x59e },
3848 { 0x0000a2d2, 0x00204411, 0x000 },
3849 { 0x00000000, 0x00404808, 0x000 },
3850 { 0x0000a2d2, 0x00204411, 0x000 },
3851 { 0x00000001, 0x00504a28, 0x000 },
3852 { 0x00000002, 0x002f0224, 0x000 },
3853 { 0x00000000, 0x0cc00000, 0x5b1 },
3854 { 0x0000a2bf, 0x00204411, 0x000 },
3855 { 0x00000000, 0x00204807, 0x000 },
3856 { 0x81000000, 0x00204411, 0x000 },
3857 { 0x00000001, 0x00204811, 0x000 },
3858 { 0x0004a2be, 0x00604411, 0x68d },
3859 { 0x0000001a, 0x00212230, 0x000 },
3860 { 0x00000006, 0x00222630, 0x000 },
3861 { 0x00042004, 0x00604411, 0x68d },
3862 { 0x0000a2c6, 0x00204411, 0x000 },
3863 { 0x00000000, 0x003048e9, 0x000 },
3864 { 0x00000000, 0x00e00000, 0x5af },
3865 { 0x0000a2d3, 0x00204411, 0x000 },
3866 { 0x00000000, 0x00404808, 0x000 },
3867 { 0x0000a2d3, 0x00204411, 0x000 },
3868 { 0x00000001, 0x00504a28, 0x000 },
3869 { 0x0000a2c3, 0x00204411, 0x000 },
3870 { 0x00000000, 0x00204807, 0x000 },
3871 { 0x81000000, 0x00204411, 0x000 },
3872 { 0x00000001, 0x00204811, 0x000 },
3873 { 0x0004a2c2, 0x00604411, 0x68d },
3874 { 0x0000001a, 0x00212230, 0x000 },
3875 { 0x00000006, 0x00222630, 0x000 },
3876 { 0x00042004, 0x00604411, 0x68d },
3877 { 0x0000a2c7, 0x00204411, 0x000 },
3878 { 0x00000000, 0x003048e9, 0x000 },
3879 { 0x00000000, 0x00e00000, 0x5be },
3880 { 0x0000a2d4, 0x00204411, 0x000 },
3881 { 0x00000000, 0x00404808, 0x000 },
3882 { 0x0000a2d4, 0x00204411, 0x000 },
3883 { 0x00000001, 0x00504a28, 0x000 },
3884 { 0x85000000, 0x00204411, 0x000 },
3885 { 0x00000000, 0x00204801, 0x000 },
3886 { 0x0000304a, 0x00204411, 0x000 },
3887 { 0x01000000, 0x00204811, 0x000 },
3888 { 0x00000000, 0x00400000, 0x5c4 },
3889 { 0xa4000000, 0xc0204411, 0x000 },
3890 { 0x00000000, 0xc0404800, 0x000 },
3891 { 0x00000000, 0xc0600000, 0x5c9 },
3892 { 0x00000000, 0xc0400400, 0x001 },
3893 { 0x0000002c, 0x00203621, 0x000 },
3894 { 0x81000000, 0x00204411, 0x000 },
3895 { 0x00000006, 0x00204811, 0x000 },
3896 { 0x00000000, 0x002f0230, 0x000 },
3897 { 0x00000000, 0x0cc00000, 0x5d0 },
3898 { 0x00000000, 0x00200411, 0x000 },
3899 { 0x00000030, 0x00403621, 0x5e3 },
3900 { 0x00000030, 0x0020062d, 0x000 },
3901 { 0x00007e00, 0x00280621, 0x000 },
3902 { 0x00000000, 0x002f0221, 0x000 },
3903 { 0x00000000, 0x0ce00000, 0x5e3 },
3904 { 0x81000000, 0x00204411, 0x000 },
3905 { 0x00000001, 0x00204811, 0x000 },
3906 { 0x0004a092, 0x00604411, 0x68d },
3907 { 0x00000031, 0x00203630, 0x000 },
3908 { 0x0004a093, 0x00604411, 0x68d },
3909 { 0x00000032, 0x00203630, 0x000 },
3910 { 0x0004a2b6, 0x00604411, 0x68d },
3911 { 0x00000033, 0x00203630, 0x000 },
3912 { 0x0004a2ba, 0x00604411, 0x68d },
3913 { 0x00000034, 0x00203630, 0x000 },
3914 { 0x0004a2be, 0x00604411, 0x68d },
3915 { 0x00000035, 0x00203630, 0x000 },
3916 { 0x0004a2c2, 0x00604411, 0x68d },
3917 { 0x00000036, 0x00203630, 0x000 },
3918 { 0x00042004, 0x00604411, 0x68d },
3919 { 0x0001a2a4, 0x00204411, 0x000 },
3920 { 0x0000003f, 0x00204811, 0x000 },
3921 { 0x0000003f, 0x00204811, 0x000 },
3922 { 0x0000003f, 0x00204811, 0x000 },
3923 { 0x0000003f, 0x00204811, 0x000 },
3924 { 0x00000005, 0x00204811, 0x000 },
3925 { 0x0000a1f4, 0x00204411, 0x000 },
3926 { 0x00000000, 0x00204811, 0x000 },
3927 { 0x88000000, 0x00204411, 0x000 },
3928 { 0x00000001, 0x00204811, 0x000 },
3929 { 0x81000000, 0x00204411, 0x000 },
3930 { 0x00000006, 0x00204811, 0x000 },
3931 { 0x00000001, 0x002f0230, 0x000 },
3932 { 0x00000000, 0x0ce00000, 0x62c },
3933 { 0x00000030, 0x0020062d, 0x000 },
3934 { 0x00000000, 0x002f0221, 0x000 },
3935 { 0x00000000, 0x0ce00000, 0x62c },
3936 { 0x81000000, 0x00204411, 0x000 },
3937 { 0x00000001, 0x00204811, 0x000 },
3938 { 0x00007e00, 0x00280621, 0x000 },
3939 { 0x00000000, 0x002f0221, 0x000 },
3940 { 0x00000000, 0x0ce00000, 0x605 },
3941 { 0x0000a092, 0x00204411, 0x000 },
3942 { 0x00000031, 0x00204a2d, 0x000 },
3943 { 0x0000a093, 0x00204411, 0x000 },
3944 { 0x00000032, 0x00204a2d, 0x000 },
3945 { 0x0000a2b6, 0x00204411, 0x000 },
3946 { 0x00000033, 0x00204a2d, 0x000 },
3947 { 0x0000a2ba, 0x00204411, 0x000 },
3948 { 0x00000034, 0x00204a2d, 0x000 },
3949 { 0x0000a2be, 0x00204411, 0x000 },
3950 { 0x00000035, 0x00204a2d, 0x000 },
3951 { 0x0000a2c2, 0x00204411, 0x000 },
3952 { 0x00000036, 0x00204a2d, 0x000 },
3953 { 0x00000030, 0x0020062d, 0x000 },
3954 { 0x000001ff, 0x00280621, 0x000 },
3955 { 0x00000000, 0x002f0221, 0x000 },
3956 { 0x00000000, 0x0ce00000, 0x62b },
3957 { 0x00000000, 0x00210221, 0x000 },
3958 { 0x00000000, 0x14c00000, 0x60e },
3959 { 0x0004a003, 0x00604411, 0x68d },
3960 { 0x0000a003, 0x00204411, 0x000 },
3961 { 0x00000000, 0x00204810, 0x000 },
3962 { 0x00000001, 0x00210621, 0x000 },
3963 { 0x00000000, 0x14c00000, 0x613 },
3964 { 0x0004a010, 0x00604411, 0x68d },
3965 { 0x0000a010, 0x00204411, 0x000 },
3966 { 0x00000000, 0x00204810, 0x000 },
3967 { 0x00000001, 0x00210621, 0x000 },
3968 { 0x00000000, 0x002f0221, 0x000 },
3969 { 0x00000000, 0x0ce00000, 0x62b },
3970 { 0x0004a011, 0x00604411, 0x68d },
3971 { 0x0000a011, 0x00204411, 0x000 },
3972 { 0x00000000, 0x00204810, 0x000 },
3973 { 0x0004a012, 0x00604411, 0x68d },
3974 { 0x0000a012, 0x00204411, 0x000 },
3975 { 0x00000000, 0x00204810, 0x000 },
3976 { 0x0004a013, 0x00604411, 0x68d },
3977 { 0x0000a013, 0x00204411, 0x000 },
3978 { 0x00000000, 0x00204810, 0x000 },
3979 { 0x0004a014, 0x00604411, 0x68d },
3980 { 0x0000a014, 0x00204411, 0x000 },
3981 { 0x00000000, 0x00204810, 0x000 },
3982 { 0x0004a015, 0x00604411, 0x68d },
3983 { 0x0000a015, 0x00204411, 0x000 },
3984 { 0x00000000, 0x00204810, 0x000 },
3985 { 0x0004a016, 0x00604411, 0x68d },
3986 { 0x0000a016, 0x00204411, 0x000 },
3987 { 0x00000000, 0x00204810, 0x000 },
3988 { 0x0004a017, 0x00604411, 0x68d },
3989 { 0x0000a017, 0x00204411, 0x000 },
3990 { 0x00000000, 0x00204810, 0x000 },
3991 { 0x00042004, 0x00604411, 0x68d },
3992 { 0x0000002c, 0x0080062d, 0x000 },
3993 { 0xff000000, 0x00204411, 0x000 },
3994 { 0x00000000, 0x00204811, 0x000 },
3995 { 0x00000001, 0x00204811, 0x000 },
3996 { 0x00000002, 0x00804811, 0x000 },
3997 { 0x00000000, 0x0ee00000, 0x63d },
3998 { 0x00000030, 0x0020062d, 0x000 },
3999 { 0x00000002, 0x00280621, 0x000 },
4000 { 0x00000000, 0x002f0221, 0x000 },
4001 { 0x00000000, 0x0ce00000, 0x63b },
4002 { 0x81000000, 0x00204411, 0x000 },
4003 { 0x00000001, 0x00204811, 0x000 },
4004 { 0x00042004, 0x00604411, 0x68d },
4005 { 0x00001000, 0x00200811, 0x000 },
4006 { 0x0000002b, 0x00203622, 0x000 },
4007 { 0x00000000, 0x00600000, 0x641 },
4008 { 0x00000000, 0x00600000, 0x5c9 },
4009 { 0x98000000, 0x00204411, 0x000 },
4010 { 0x00000000, 0x00804811, 0x000 },
4011 { 0x00000000, 0xc0600000, 0x641 },
4012 { 0x00000000, 0xc0400400, 0x001 },
4013 { 0x0000a2a4, 0x00204411, 0x000 },
4014 { 0x00000022, 0x00204811, 0x000 },
4015 { 0x89000000, 0x00204411, 0x000 },
4016 { 0x00000001, 0x00404811, 0x62d },
4017 { 0x97000000, 0x00204411, 0x000 },
4018 { 0x00000000, 0x00204811, 0x000 },
4019 { 0x8a000000, 0x00204411, 0x000 },
4020 { 0x00000000, 0x00404811, 0x62d },
4021 { 0x00000000, 0x00600000, 0x65c },
4022 { 0x00002010, 0x00204411, 0x000 },
4023 { 0x00008000, 0x00204811, 0x000 },
4024 { 0x0001a2a4, 0xc0204411, 0x000 },
4025 { 0x00000016, 0x00604811, 0x36e },
4026 { 0x00002010, 0x00204411, 0x000 },
4027 { 0x00010000, 0x00204811, 0x000 },
4028 { 0x81000000, 0x00204411, 0x000 },
4029 { 0x00000001, 0x00204811, 0x000 },
4030 { 0x0000217c, 0x00204411, 0x000 },
4031 { 0x09800000, 0x00204811, 0x000 },
4032 { 0xffffffff, 0x00204811, 0x000 },
4033 { 0x00000000, 0x00204811, 0x000 },
4034 { 0x00000000, 0x17000000, 0x000 },
4035 { 0x0004217f, 0x00604411, 0x68d },
4036 { 0x0000001f, 0x00210230, 0x000 },
4037 { 0x00000000, 0x14c00000, 0x000 },
4038 { 0x00000004, 0x00404c11, 0x656 },
4039 { 0x00000000, 0x00400000, 0x000 },
4040 { 0x00000017, 0x00201e2d, 0x000 },
4041 { 0x00000004, 0x00291e27, 0x000 },
4042 { 0x00000017, 0x00803627, 0x000 },
4043 { 0x00000017, 0x00201e2d, 0x000 },
4044 { 0xfffffffb, 0x00281e27, 0x000 },
4045 { 0x00000017, 0x00803627, 0x000 },
4046 { 0x00000017, 0x00201e2d, 0x000 },
4047 { 0x00000008, 0x00291e27, 0x000 },
4048 { 0x00000017, 0x00803627, 0x000 },
4049 { 0x00000017, 0x00201e2d, 0x000 },
4050 { 0xfffffff7, 0x00281e27, 0x000 },
4051 { 0x00000017, 0x00803627, 0x000 },
4052 { 0x00002010, 0x00204411, 0x000 },
4053 { 0x00008000, 0x00204811, 0x000 },
4054 { 0x0001a2a4, 0x00204411, 0x000 },
4055 { 0x00000016, 0x00604811, 0x36e },
4056 { 0x00002010, 0x00204411, 0x000 },
4057 { 0x00010000, 0x00204811, 0x000 },
4058 { 0x0000217c, 0x00204411, 0x000 },
4059 { 0x01800000, 0x00204811, 0x000 },
4060 { 0xffffffff, 0x00204811, 0x000 },
4061 { 0x00000000, 0x00204811, 0x000 },
4062 { 0x00000000, 0x17000000, 0x000 },
4063 { 0x81000000, 0x00204411, 0x000 },
4064 { 0x00000001, 0x00204811, 0x000 },
4065 { 0x0004217f, 0x00604411, 0x68d },
4066 { 0x0000001f, 0x00210230, 0x000 },
4067 { 0x00000000, 0x14c00000, 0x68c },
4068 { 0x00000010, 0x00404c11, 0x672 },
4069 { 0x00000000, 0xc0200400, 0x000 },
4070 { 0x00000000, 0x38c00000, 0x000 },
4071 { 0x0000001d, 0x00200a2d, 0x000 },
4072 { 0x0000001e, 0x00200e2d, 0x000 },
4073 { 0x0000001f, 0x0020122d, 0x000 },
4074 { 0x00000020, 0x0020162d, 0x000 },
4075 { 0x00002169, 0x00204411, 0x000 },
4076 { 0x00000000, 0x00204804, 0x000 },
4077 { 0x00000000, 0x00204805, 0x000 },
4078 { 0x00000000, 0x00204801, 0x000 },
4079 { 0xcafebabe, 0x00204811, 0x000 },
4080 { 0x00000004, 0x00301224, 0x000 },
4081 { 0x00000000, 0x002f0064, 0x000 },
4082 { 0x00000000, 0x0cc00000, 0x68b },
4083 { 0x00000003, 0x00281a22, 0x000 },
4084 { 0x00000008, 0x00221222, 0x000 },
4085 { 0xfffff000, 0x00281224, 0x000 },
4086 { 0x00000000, 0x002910c4, 0x000 },
4087 { 0x0000001f, 0x00403624, 0x000 },
4088 { 0x00000000, 0x00800000, 0x000 },
4089 { 0x00000000, 0x1ac00000, 0x68d },
4090 { 0x9f000000, 0x00204411, 0x000 },
4091 { 0xcafebabe, 0x00204811, 0x000 },
4092 { 0x00000000, 0x1ae00000, 0x690 },
4093 { 0x00000000, 0x00800000, 0x000 },
4094 { 0x00000000, 0x1ac00000, 0x692 },
4095 { 0x9e000000, 0x00204411, 0x000 },
4096 { 0xcafebabe, 0x00204811, 0x000 },
4097 { 0x00000000, 0x1ae00000, 0x695 },
4098 { 0x00000000, 0x00800000, 0x000 },
4099 { 0x00000000, 0x00600000, 0x00b },
4100 { 0x00001000, 0x00600411, 0x315 },
4101 { 0x00000000, 0x00200411, 0x000 },
4102 { 0x00000000, 0x00600811, 0x1b2 },
4103 { 0x0000225c, 0x00204411, 0x000 },
4104 { 0x00000003, 0x00204811, 0x000 },
4105 { 0x00002256, 0x00204411, 0x000 },
4106 { 0x0000001b, 0x00204811, 0x000 },
4107 { 0x0000a1fc, 0x00204411, 0x000 },
4108 { 0x00000001, 0x00204811, 0x000 },
4109 { 0x0001a1fd, 0xc0204411, 0x000 },
4110 { 0x00000021, 0x00201e2d, 0x000 },
4111 { 0x00000010, 0x00221e27, 0x000 },
4112 { 0x00000024, 0x0020222d, 0x000 },
4113 { 0x0000ffff, 0x00282228, 0x000 },
4114 { 0x00000000, 0x00294907, 0x000 },
4115 { 0x00000000, 0x00204811, 0x000 },
4116 { 0x00000022, 0x0020222d, 0x000 },
4117 { 0x0000ffff, 0x00282228, 0x000 },
4118 { 0x00000000, 0x00294907, 0x000 },
4119 { 0x00000000, 0x00204811, 0x000 },
4120 { 0x00000023, 0x00201e2d, 0x000 },
4121 { 0x00000010, 0x00221e27, 0x000 },
4122 { 0x00000000, 0x00294907, 0x000 },
4123 { 0x00000000, 0x00404811, 0x000 },
4124 { 0x00000000, 0x00000000, 0x000 },
4125 { 0x00000000, 0x00000000, 0x000 },
4126 { 0x00000000, 0x00000000, 0x000 },
4127 { 0x00000000, 0x00000000, 0x000 },
4128 { 0x00000000, 0x00000000, 0x000 },
4129 { 0x00000000, 0x00000000, 0x000 },
4130 { 0x00000000, 0x00000000, 0x000 },
4131 { 0x00000000, 0x00000000, 0x000 },
4132 { 0x00000000, 0x00000000, 0x000 },
4133 { 0x00000000, 0x00000000, 0x000 },
4134 { 0x00000000, 0x00000000, 0x000 },
4135 { 0x00000000, 0x00000000, 0x000 },
4136 { 0x00000000, 0x00000000, 0x000 },
4137 { 0x00000000, 0x00000000, 0x000 },
4138 { 0x00000000, 0x00000000, 0x000 },
4139 { 0x00000000, 0x00000000, 0x000 },
4140 { 0x00000000, 0x00000000, 0x000 },
4141 { 0x00000000, 0x00000000, 0x000 },
4142 { 0x00000000, 0x00000000, 0x000 },
4143 { 0x00000000, 0x00000000, 0x000 },
4144 { 0x00000000, 0x00000000, 0x000 },
4145 { 0x00000000, 0x00000000, 0x000 },
4146 { 0x00000000, 0x00000000, 0x000 },
4147 { 0x00000000, 0x00000000, 0x000 },
4148 { 0x00000000, 0x00000000, 0x000 },
4149 { 0x00000000, 0x00000000, 0x000 },
4150 { 0x00000000, 0x00000000, 0x000 },
4151 { 0x00000000, 0x00000000, 0x000 },
4152 { 0x00000000, 0x00000000, 0x000 },
4153 { 0x00000000, 0x00000000, 0x000 },
4154 { 0x00000000, 0x00000000, 0x000 },
4155 { 0x00000000, 0x00000000, 0x000 },
4156 { 0x00000000, 0x00000000, 0x000 },
4157 { 0x00000000, 0x00000000, 0x000 },
4158 { 0x00000000, 0x00000000, 0x000 },
4159 { 0x00000000, 0x00000000, 0x000 },
4160 { 0x00000000, 0x00000000, 0x000 },
4161 { 0x00000000, 0x00000000, 0x000 },
4162 { 0x00000000, 0x00000000, 0x000 },
4163 { 0x00000000, 0x00000000, 0x000 },
4164 { 0x00000000, 0x00000000, 0x000 },
4165 { 0x00000000, 0x00000000, 0x000 },
4166 { 0x00000000, 0x00000000, 0x000 },
4167 { 0x00000000, 0x00000000, 0x000 },
4168 { 0x00000000, 0x00000000, 0x000 },
4169 { 0x00000000, 0x00000000, 0x000 },
4170 { 0x00000000, 0x00000000, 0x000 },
4171 { 0x00000000, 0x00000000, 0x000 },
4172 { 0x00000000, 0x00000000, 0x000 },
4173 { 0x00000000, 0x00000000, 0x000 },
4174 { 0x00000000, 0x00000000, 0x000 },
4175 { 0x00000000, 0x00000000, 0x000 },
4176 { 0x01420502, 0x05c00250, 0x000 },
4177 { 0x01c30168, 0x043f05c0, 0x000 },
4178 { 0x02250209, 0x02500151, 0x000 },
4179 { 0x02230245, 0x02a00241, 0x000 },
4180 { 0x03d705c0, 0x05c005c0, 0x000 },
4181 { 0x0649064a, 0x031f05c0, 0x000 },
4182 { 0x05c005c5, 0x03200340, 0x000 },
4183 { 0x032a0282, 0x03420334, 0x000 },
4184 { 0x05c005c0, 0x05c005c0, 0x000 },
4185 { 0x05c00551, 0x05c005c0, 0x000 },
4186 { 0x03ba05c0, 0x04bb0344, 0x000 },
4187 { 0x049a0450, 0x043d05c0, 0x000 },
4188 { 0x04d005c0, 0x044104dd, 0x000 },
4189 { 0x04500507, 0x03510375, 0x000 },
4190 { 0x05c005c0, 0x05c005c0, 0x000 },
4191 { 0x05c005c0, 0x05c005c0, 0x000 },
4192 { 0x05c005c0, 0x063f05c7, 0x000 },
4193 { 0x05c005c0, 0x000705c0, 0x000 },
4194 { 0x05c005c0, 0x05c005c0, 0x000 },
4195 { 0x05c005c0, 0x05c005c0, 0x000 },
4196 { 0x03f803ed, 0x04080406, 0x000 },
4197 { 0x040e040a, 0x040c0410, 0x000 },
4198 { 0x041c0418, 0x04240420, 0x000 },
4199 { 0x042c0428, 0x04340430, 0x000 },
4200 { 0x05c005c0, 0x043805c0, 0x000 },
4201 { 0x05c005c0, 0x05c005c0, 0x000 },
4202 { 0x05c005c0, 0x05c005c0, 0x000 },
4203 { 0x00020679, 0x06970006, 0x000 },
4204};
4205
4206static const u32 RV610_pfp_microcode[] = {
42070xca0400,
42080xa00000,
42090x7e828b,
42100x7c038b,
42110x8001b8,
42120x7c038b,
42130xd4401e,
42140xee001e,
42150xca0400,
42160xa00000,
42170x7e828b,
42180xc41838,
42190xca2400,
42200xca2800,
42210x9581a8,
42220xc41c3a,
42230xc3c000,
42240xca0800,
42250xca0c00,
42260x7c744b,
42270xc20005,
42280x99c000,
42290xc41c3a,
42300x7c744c,
42310xc0fff0,
42320x042c04,
42330x309002,
42340x7d2500,
42350x351402,
42360x7d350b,
42370x255403,
42380x7cd580,
42390x259c03,
42400x95c004,
42410xd5001b,
42420x7eddc1,
42430x7d9d80,
42440xd6801b,
42450xd5801b,
42460xd4401e,
42470xd5401e,
42480xd6401e,
42490xd6801e,
42500xd4801e,
42510xd4c01e,
42520x9783d3,
42530xd5c01e,
42540xca0800,
42550x80001a,
42560xca0c00,
42570xe4011e,
42580xd4001e,
42590x80000c,
42600xc41838,
42610xe4013e,
42620xd4001e,
42630x80000c,
42640xc41838,
42650xd4401e,
42660xee001e,
42670xca0400,
42680xa00000,
42690x7e828b,
42700xe4011e,
42710xd4001e,
42720xd4401e,
42730xee001e,
42740xca0400,
42750xa00000,
42760x7e828b,
42770xe4013e,
42780xd4001e,
42790xd4401e,
42800xee001e,
42810xca0400,
42820xa00000,
42830x7e828b,
42840xca1800,
42850xd4401e,
42860xd5801e,
42870x800053,
42880xd40075,
42890xd4401e,
42900xca0800,
42910xca0c00,
42920xca1000,
42930xd48019,
42940xd4c018,
42950xd50017,
42960xd4801e,
42970xd4c01e,
42980xd5001e,
42990xe2001e,
43000xca0400,
43010xa00000,
43020x7e828b,
43030xca0800,
43040xd48060,
43050xd4401e,
43060x800000,
43070xd4801e,
43080xca0800,
43090xd48061,
43100xd4401e,
43110x800000,
43120xd4801e,
43130xca0800,
43140xca0c00,
43150xd4401e,
43160xd48016,
43170xd4c016,
43180xd4801e,
43190x8001b8,
43200xd4c01e,
43210xc60843,
43220xca0c00,
43230xca1000,
43240x948004,
43250xca1400,
43260xe420f3,
43270xd42013,
43280xd56065,
43290xd4e01c,
43300xd5201c,
43310xd5601c,
43320x800000,
43330x062001,
43340xc60843,
43350xca0c00,
43360xca1000,
43370x9483f7,
43380xca1400,
43390xe420f3,
43400x800079,
43410xd42013,
43420xc60843,
43430xca0c00,
43440xca1000,
43450x9883ef,
43460xca1400,
43470xd40064,
43480x80008d,
43490x000000,
43500xc41432,
43510xc61843,
43520xc4082f,
43530x954005,
43540xc40c30,
43550xd4401e,
43560x800000,
43570xee001e,
43580x9583f5,
43590xc41031,
43600xd44033,
43610xd52065,
43620xd4a01c,
43630xd4e01c,
43640xd5201c,
43650xe4015e,
43660xd4001e,
43670x800000,
43680x062001,
43690xca1800,
43700x0a2001,
43710xd60076,
43720xc40836,
43730x988007,
43740xc61045,
43750x950110,
43760xd4001f,
43770xd46062,
43780x800000,
43790xd42062,
43800xcc3835,
43810xcc1433,
43820x8401bb,
43830xd40072,
43840xd5401e,
43850x800000,
43860xee001e,
43870xe2001a,
43880x8401bb,
43890xe2001a,
43900xcc104b,
43910xcc0447,
43920x2c9401,
43930x7d098b,
43940x984005,
43950x7d15cb,
43960xd4001a,
43970x8001b8,
43980xd4006d,
43990x344401,
44000xcc0c48,
44010x98403a,
44020xcc2c4a,
44030x958004,
44040xcc0449,
44050x8001b8,
44060xd4001a,
44070xd4c01a,
44080x282801,
44090x8400f0,
44100xcc1003,
44110x98801b,
44120x04380c,
44130x8400f0,
44140xcc1003,
44150x988017,
44160x043808,
44170x8400f0,
44180xcc1003,
44190x988013,
44200x043804,
44210x8400f0,
44220xcc1003,
44230x988014,
44240xcc104c,
44250x9a8009,
44260xcc144d,
44270x9840dc,
44280xd4006d,
44290xcc1848,
44300xd5001a,
44310xd5401a,
44320x8000c9,
44330xd5801a,
44340x96c0d5,
44350xd4006d,
44360x8001b8,
44370xd4006e,
44380x9ac003,
44390xd4006d,
44400xd4006e,
44410x800000,
44420xec007f,
44430x9ac0cc,
44440xd4006d,
44450x8001b8,
44460xd4006e,
44470xcc1403,
44480xcc1803,
44490xcc1c03,
44500x7d9103,
44510x7dd583,
44520x7d190c,
44530x35cc1f,
44540x35701f,
44550x7cf0cb,
44560x7cd08b,
44570x880000,
44580x7e8e8b,
44590x95c004,
44600xd4006e,
44610x8001b8,
44620xd4001a,
44630xd4c01a,
44640xcc0803,
44650xcc0c03,
44660xcc1003,
44670xcc1403,
44680xcc1803,
44690xcc1c03,
44700xcc2403,
44710xcc2803,
44720x35c41f,
44730x36b01f,
44740x7c704b,
44750x34f01f,
44760x7c704b,
44770x35701f,
44780x7c704b,
44790x7d8881,
44800x7dccc1,
44810x7e5101,
44820x7e9541,
44830x7c9082,
44840x7cd4c2,
44850x7c848b,
44860x9ac003,
44870x7c8c8b,
44880x2c8801,
44890x98809e,
44900xd4006d,
44910x98409c,
44920xd4006e,
44930xcc084c,
44940xcc0c4d,
44950xcc1048,
44960xd4801a,
44970xd4c01a,
44980x800101,
44990xd5001a,
45000xcc0832,
45010xd40032,
45020x9482d9,
45030xca0c00,
45040xd4401e,
45050x800000,
45060xd4001e,
45070xe4011e,
45080xd4001e,
45090xca0800,
45100xca0c00,
45110xca1000,
45120xd4401e,
45130xca1400,
45140xd4801e,
45150xd4c01e,
45160xd5001e,
45170xd5401e,
45180xd54034,
45190x800000,
45200xee001e,
45210x280404,
45220xe2001a,
45230xe2001a,
45240xd4401a,
45250xca3800,
45260xcc0803,
45270xcc0c03,
45280xcc0c03,
45290xcc0c03,
45300x9882bd,
45310x000000,
45320x8401bb,
45330xd7a06f,
45340x800000,
45350xee001f,
45360xca0400,
45370xc2ff00,
45380xcc0834,
45390xc13fff,
45400x7c74cb,
45410x7cc90b,
45420x7d010f,
45430x9902b0,
45440x7c738b,
45450x8401bb,
45460xd7a06f,
45470x800000,
45480xee001f,
45490xca0800,
45500x281900,
45510x7d898b,
45520x958014,
45530x281404,
45540xca0c00,
45550xca1000,
45560xca1c00,
45570xca2400,
45580xe2001f,
45590xd4c01a,
45600xd5001a,
45610xd5401a,
45620xcc1803,
45630xcc2c03,
45640xcc2c03,
45650xcc2c03,
45660x7da58b,
45670x7d9c47,
45680x984297,
45690x000000,
45700x800161,
45710xd4c01a,
45720xd4401e,
45730xd4801e,
45740x800000,
45750xee001e,
45760xe4011e,
45770xd4001e,
45780xd4401e,
45790xee001e,
45800xca0400,
45810xa00000,
45820x7e828b,
45830xe4013e,
45840xd4001e,
45850xd4401e,
45860xee001e,
45870xca0400,
45880xa00000,
45890x7e828b,
45900xca0800,
45910x248c06,
45920x0ccc06,
45930x98c006,
45940xcc104e,
45950x990004,
45960xd40073,
45970xe4011e,
45980xd4001e,
45990xd4401e,
46000xd4801e,
46010x800000,
46020xee001e,
46030xca0800,
46040xca0c00,
46050x34d018,
46060x251001,
46070x950021,
46080xc17fff,
46090xca1000,
46100xca1400,
46110xca1800,
46120xd4801d,
46130xd4c01d,
46140x7db18b,
46150xc14202,
46160xc2c001,
46170xd5801d,
46180x34dc0e,
46190x7d5d4c,
46200x7f734c,
46210xd7401e,
46220xd5001e,
46230xd5401e,
46240xc14200,
46250xc2c000,
46260x099c01,
46270x31dc10,
46280x7f5f4c,
46290x7f734c,
46300x042802,
46310x7d8380,
46320xd5a86f,
46330xd58066,
46340xd7401e,
46350xec005e,
46360xc82402,
46370xc82402,
46380x8001b8,
46390xd60076,
46400xd4401e,
46410xd4801e,
46420xd4c01e,
46430x800000,
46440xee001e,
46450x800000,
46460xee001f,
46470xd4001f,
46480x800000,
46490xd4001f,
46500xd4001f,
46510x880000,
46520xd4001f,
46530x000000,
46540x000000,
46550x000000,
46560x000000,
46570x000000,
46580x000000,
46590x000000,
46600x000000,
46610x000000,
46620x000000,
46630x000000,
46640x000000,
46650x000000,
46660x000000,
46670x000000,
46680x000000,
46690x000000,
46700x000000,
46710x000000,
46720x000000,
46730x000000,
46740x000000,
46750x000000,
46760x000000,
46770x000000,
46780x000000,
46790x000000,
46800x000000,
46810x000000,
46820x000000,
46830x000000,
46840x000000,
46850x000000,
46860x000000,
46870x000000,
46880x000000,
46890x000000,
46900x000000,
46910x000000,
46920x000000,
46930x000000,
46940x000000,
46950x000000,
46960x000000,
46970x000000,
46980x000000,
46990x000000,
47000x000000,
47010x000000,
47020x000000,
47030x000000,
47040x000000,
47050x000000,
47060x000000,
47070x000000,
47080x000000,
47090x000000,
47100x000000,
47110x000000,
47120x000000,
47130x000000,
47140x000000,
47150x000000,
47160x000000,
47170x000000,
47180x000000,
47190x010171,
47200x020178,
47210x03008f,
47220x04007f,
47230x050003,
47240x06003f,
47250x070032,
47260x08012c,
47270x090046,
47280x0a0036,
47290x1001b6,
47300x1700a2,
47310x22013a,
47320x230149,
47330x2000b4,
47340x240125,
47350x27004d,
47360x28006a,
47370x2a0060,
47380x2b0052,
47390x2f0065,
47400x320087,
47410x34017f,
47420x3c0156,
47430x3f0072,
47440x41018c,
47450x44012e,
47460x550173,
47470x56017a,
47480x60000b,
47490x610034,
47500x620038,
47510x630038,
47520x640038,
47530x650038,
47540x660038,
47550x670038,
47560x68003a,
47570x690041,
47580x6a0048,
47590x6b0048,
47600x6c0048,
47610x6d0048,
47620x6e0048,
47630x6f0048,
47640x000006,
47650x000006,
47660x000006,
47670x000006,
47680x000006,
47690x000006,
47700x000006,
47710x000006,
47720x000006,
47730x000006,
47740x000006,
47750x000006,
47760x000006,
47770x000006,
47780x000006,
47790x000006,
47800x000006,
47810x000006,
47820x000006,
4783};
4784
4785static const u32 RV620_cp_microcode[][3] = {
4786 { 0x00000000, 0xc0200400, 0x000 },
4787 { 0x00000000, 0x00a0000a, 0x000 },
4788 { 0x0000ffff, 0x00284621, 0x000 },
4789 { 0x00000000, 0xd9004800, 0x000 },
4790 { 0x00000000, 0xc0200400, 0x000 },
4791 { 0x00000000, 0x00a0000a, 0x000 },
4792 { 0x00000000, 0x00e00000, 0x000 },
4793 { 0x00010000, 0xc0294620, 0x000 },
4794 { 0x00000000, 0xd9004800, 0x000 },
4795 { 0x00000000, 0xc0200400, 0x000 },
4796 { 0x00000000, 0x00a0000a, 0x000 },
4797 { 0x81000000, 0x00204411, 0x000 },
4798 { 0x00000001, 0x00204811, 0x000 },
4799 { 0x00042004, 0x00604411, 0x68d },
4800 { 0x00000000, 0x00600000, 0x631 },
4801 { 0x00000000, 0x00600000, 0x645 },
4802 { 0x00000000, 0xc0200800, 0x000 },
4803 { 0x00000f00, 0x00281622, 0x000 },
4804 { 0x00000008, 0x00211625, 0x000 },
4805 { 0x00000018, 0x00203625, 0x000 },
4806 { 0x8d000000, 0x00204411, 0x000 },
4807 { 0x00000004, 0x002f0225, 0x000 },
4808 { 0x00000000, 0x0ce00000, 0x018 },
4809 { 0x00412000, 0x00404811, 0x019 },
4810 { 0x00422000, 0x00204811, 0x000 },
4811 { 0x8e000000, 0x00204411, 0x000 },
4812 { 0x00000028, 0x00204a2d, 0x000 },
4813 { 0x90000000, 0x00204411, 0x000 },
4814 { 0x00000000, 0x00204805, 0x000 },
4815 { 0x0000000c, 0x00211622, 0x000 },
4816 { 0x00000003, 0x00281625, 0x000 },
4817 { 0x00000019, 0x00211a22, 0x000 },
4818 { 0x00000004, 0x00281a26, 0x000 },
4819 { 0x00000000, 0x002914c5, 0x000 },
4820 { 0x00000019, 0x00203625, 0x000 },
4821 { 0x00000000, 0x003a1402, 0x000 },
4822 { 0x00000016, 0x00211625, 0x000 },
4823 { 0x00000003, 0x00281625, 0x000 },
4824 { 0x00000017, 0x00200e2d, 0x000 },
4825 { 0xfffffffc, 0x00280e23, 0x000 },
4826 { 0x00000000, 0x002914a3, 0x000 },
4827 { 0x00000017, 0x00203625, 0x000 },
4828 { 0x00008000, 0x00280e22, 0x000 },
4829 { 0x00000007, 0x00220e23, 0x000 },
4830 { 0x00000000, 0x0029386e, 0x000 },
4831 { 0x20000000, 0x00280e22, 0x000 },
4832 { 0x00000006, 0x00210e23, 0x000 },
4833 { 0x00000000, 0x0029386e, 0x000 },
4834 { 0x00000000, 0x00220222, 0x000 },
4835 { 0x00000000, 0x14e00000, 0x038 },
4836 { 0x00000000, 0x2ee00000, 0x035 },
4837 { 0x00000000, 0x2ce00000, 0x037 },
4838 { 0x00000000, 0x00400e2d, 0x039 },
4839 { 0x00000008, 0x00200e2d, 0x000 },
4840 { 0x00000009, 0x0040122d, 0x046 },
4841 { 0x00000001, 0x00400e2d, 0x039 },
4842 { 0x00000000, 0xc0200c00, 0x000 },
4843 { 0x003ffffc, 0x00281223, 0x000 },
4844 { 0x00000002, 0x00221224, 0x000 },
4845 { 0x0000001f, 0x00211e23, 0x000 },
4846 { 0x00000000, 0x14e00000, 0x03e },
4847 { 0x00000008, 0x00401c11, 0x041 },
4848 { 0x0000000d, 0x00201e2d, 0x000 },
4849 { 0x0000000f, 0x00281e27, 0x000 },
4850 { 0x00000003, 0x00221e27, 0x000 },
4851 { 0x7fc00000, 0x00281a23, 0x000 },
4852 { 0x00000014, 0x00211a26, 0x000 },
4853 { 0x00000001, 0x00331a26, 0x000 },
4854 { 0x00000008, 0x00221a26, 0x000 },
4855 { 0x00000000, 0x00290cc7, 0x000 },
4856 { 0x00000027, 0x00203624, 0x000 },
4857 { 0x00007f00, 0x00281221, 0x000 },
4858 { 0x00001400, 0x002f0224, 0x000 },
4859 { 0x00000000, 0x0ce00000, 0x04b },
4860 { 0x00000001, 0x00290e23, 0x000 },
4861 { 0x0000000e, 0x00203623, 0x000 },
4862 { 0x0000e000, 0x00204411, 0x000 },
4863 { 0xfff80000, 0x00294a23, 0x000 },
4864 { 0x00000000, 0x003a2c02, 0x000 },
4865 { 0x00000002, 0x00220e2b, 0x000 },
4866 { 0xfc000000, 0x00280e23, 0x000 },
4867 { 0x0000000f, 0x00203623, 0x000 },
4868 { 0x00001fff, 0x00294a23, 0x000 },
4869 { 0x00000027, 0x00204a2d, 0x000 },
4870 { 0x00000000, 0x00204811, 0x000 },
4871 { 0x00000029, 0x00200e2d, 0x000 },
4872 { 0x060a0200, 0x00294a23, 0x000 },
4873 { 0x00000000, 0x00204811, 0x000 },
4874 { 0x00000000, 0x00204811, 0x000 },
4875 { 0x00000001, 0x00210222, 0x000 },
4876 { 0x00000000, 0x14e00000, 0x061 },
4877 { 0x00000000, 0x2ee00000, 0x05f },
4878 { 0x00000000, 0x2ce00000, 0x05e },
4879 { 0x00000000, 0x00400e2d, 0x062 },
4880 { 0x00000001, 0x00400e2d, 0x062 },
4881 { 0x0000000a, 0x00200e2d, 0x000 },
4882 { 0x0000000b, 0x0040122d, 0x06a },
4883 { 0x00000000, 0xc0200c00, 0x000 },
4884 { 0x003ffffc, 0x00281223, 0x000 },
4885 { 0x00000002, 0x00221224, 0x000 },
4886 { 0x7fc00000, 0x00281623, 0x000 },
4887 { 0x00000014, 0x00211625, 0x000 },
4888 { 0x00000001, 0x00331625, 0x000 },
4889 { 0x80000000, 0x00280e23, 0x000 },
4890 { 0x00000000, 0x00290ca3, 0x000 },
4891 { 0x3ffffc00, 0x00290e23, 0x000 },
4892 { 0x0000001f, 0x00211e23, 0x000 },
4893 { 0x00000000, 0x14e00000, 0x06d },
4894 { 0x00000100, 0x00401c11, 0x070 },
4895 { 0x0000000d, 0x00201e2d, 0x000 },
4896 { 0x000000f0, 0x00281e27, 0x000 },
4897 { 0x00000004, 0x00221e27, 0x000 },
4898 { 0x81000000, 0x00204411, 0x000 },
4899 { 0x0000000d, 0x00204811, 0x000 },
4900 { 0xfffff0ff, 0x00281a30, 0x000 },
4901 { 0x0000a028, 0x00204411, 0x000 },
4902 { 0x00000000, 0x002948e6, 0x000 },
4903 { 0x0000a018, 0x00204411, 0x000 },
4904 { 0x3fffffff, 0x00284a23, 0x000 },
4905 { 0x0000a010, 0x00204411, 0x000 },
4906 { 0x00000000, 0x00204804, 0x000 },
4907 { 0x00000030, 0x0020162d, 0x000 },
4908 { 0x00000002, 0x00291625, 0x000 },
4909 { 0x00000030, 0x00203625, 0x000 },
4910 { 0x00000025, 0x0020162d, 0x000 },
4911 { 0x00000000, 0x002f00a3, 0x000 },
4912 { 0x00000000, 0x0cc00000, 0x083 },
4913 { 0x00000026, 0x0020162d, 0x000 },
4914 { 0x00000000, 0x002f00a4, 0x000 },
4915 { 0x00000000, 0x0cc00000, 0x084 },
4916 { 0x00000000, 0x00400000, 0x08a },
4917 { 0x00000025, 0x00203623, 0x000 },
4918 { 0x00000026, 0x00203624, 0x000 },
4919 { 0x00000017, 0x00201e2d, 0x000 },
4920 { 0x00000002, 0x00210227, 0x000 },
4921 { 0x00000000, 0x14e00000, 0x08a },
4922 { 0x00000000, 0x00600000, 0x668 },
4923 { 0x00000000, 0x00600000, 0x65c },
4924 { 0x00000002, 0x00210e22, 0x000 },
4925 { 0x00000000, 0x14c00000, 0x08d },
4926 { 0x00000012, 0xc0403620, 0x093 },
4927 { 0x00000000, 0x2ee00000, 0x091 },
4928 { 0x00000000, 0x2ce00000, 0x090 },
4929 { 0x00000002, 0x00400e2d, 0x092 },
4930 { 0x00000003, 0x00400e2d, 0x092 },
4931 { 0x0000000c, 0x00200e2d, 0x000 },
4932 { 0x00000012, 0x00203623, 0x000 },
4933 { 0x00000003, 0x00210e22, 0x000 },
4934 { 0x00000000, 0x14c00000, 0x098 },
4935 { 0x0000a00c, 0x00204411, 0x000 },
4936 { 0x00000000, 0xc0204800, 0x000 },
4937 { 0x00000000, 0xc0404800, 0x0a0 },
4938 { 0x0000a00c, 0x00204411, 0x000 },
4939 { 0x00000000, 0x00204811, 0x000 },
4940 { 0x00000000, 0x2ee00000, 0x09e },
4941 { 0x00000000, 0x2ce00000, 0x09d },
4942 { 0x00000002, 0x00400e2d, 0x09f },
4943 { 0x00000003, 0x00400e2d, 0x09f },
4944 { 0x0000000c, 0x00200e2d, 0x000 },
4945 { 0x00000000, 0x00204803, 0x000 },
4946 { 0x00000000, 0x003a0c02, 0x000 },
4947 { 0x003f0000, 0x00280e23, 0x000 },
4948 { 0x00000010, 0x00210e23, 0x000 },
4949 { 0x00000011, 0x00203623, 0x000 },
4950 { 0x0000001e, 0x0021022b, 0x000 },
4951 { 0x00000000, 0x14c00000, 0x0a7 },
4952 { 0x00000016, 0xc0203620, 0x000 },
4953 { 0x0000001f, 0x0021022b, 0x000 },
4954 { 0x00000000, 0x14c00000, 0x0aa },
4955 { 0x00000015, 0xc0203620, 0x000 },
4956 { 0x00000008, 0x00210e2b, 0x000 },
4957 { 0x0000007f, 0x00280e23, 0x000 },
4958 { 0x00000000, 0x002f0223, 0x000 },
4959 { 0x00000000, 0x0ce00000, 0x0e1 },
4960 { 0x00000000, 0x27000000, 0x000 },
4961 { 0x00000000, 0x00600000, 0x2a3 },
4962 { 0x00000001, 0x002f0223, 0x000 },
4963 { 0x00000000, 0x0ae00000, 0x0b3 },
4964 { 0x00000000, 0x00600000, 0x13a },
4965 { 0x81000000, 0x00204411, 0x000 },
4966 { 0x00000006, 0x00204811, 0x000 },
4967 { 0x0000000c, 0x00221e30, 0x000 },
4968 { 0x99800000, 0x00204411, 0x000 },
4969 { 0x00000004, 0x0020122d, 0x000 },
4970 { 0x00000008, 0x00221224, 0x000 },
4971 { 0x00000010, 0x00201811, 0x000 },
4972 { 0x00000000, 0x00291ce4, 0x000 },
4973 { 0x00000000, 0x00604807, 0x12f },
4974 { 0x9b000000, 0x00204411, 0x000 },
4975 { 0x00000000, 0x00204802, 0x000 },
4976 { 0x9c000000, 0x00204411, 0x000 },
4977 { 0x00000000, 0x0033146f, 0x000 },
4978 { 0x00000001, 0x00333e23, 0x000 },
4979 { 0x00000000, 0xd9004800, 0x000 },
4980 { 0x00000000, 0x00203c05, 0x000 },
4981 { 0x81000000, 0x00204411, 0x000 },
4982 { 0x0000000e, 0x00204811, 0x000 },
4983 { 0x00000000, 0x00201010, 0x000 },
4984 { 0x0000e007, 0x00204411, 0x000 },
4985 { 0x0000000f, 0x0021022b, 0x000 },
4986 { 0x00000000, 0x14c00000, 0x0cb },
4987 { 0x00f8ff08, 0x00204811, 0x000 },
4988 { 0x98000000, 0x00404811, 0x0dc },
4989 { 0x000000f0, 0x00280e22, 0x000 },
4990 { 0x000000a0, 0x002f0223, 0x000 },
4991 { 0x00000000, 0x0cc00000, 0x0da },
4992 { 0x00000011, 0x00200e2d, 0x000 },
4993 { 0x00000001, 0x002f0223, 0x000 },
4994 { 0x00000000, 0x0ce00000, 0x0d5 },
4995 { 0x00000002, 0x002f0223, 0x000 },
4996 { 0x00000000, 0x0ce00000, 0x0d4 },
4997 { 0x00003f00, 0x00400c11, 0x0d6 },
4998 { 0x00001f00, 0x00400c11, 0x0d6 },
4999 { 0x00000f00, 0x00200c11, 0x000 },
5000 { 0x00380009, 0x00294a23, 0x000 },
5001 { 0x3f000000, 0x00280e2b, 0x000 },
5002 { 0x00000002, 0x00220e23, 0x000 },
5003 { 0x00000007, 0x00494a23, 0x0dc },
5004 { 0x00380f09, 0x00204811, 0x000 },
5005 { 0x68000007, 0x00204811, 0x000 },
5006 { 0x00000008, 0x00214a27, 0x000 },
5007 { 0x00000000, 0x00204811, 0x000 },
5008 { 0x060a0200, 0x00294a24, 0x000 },
5009 { 0x00000000, 0x00204811, 0x000 },
5010 { 0x00000000, 0x00204811, 0x000 },
5011 { 0x0000a202, 0x00204411, 0x000 },
5012 { 0x00ff0000, 0x00280e22, 0x000 },
5013 { 0x00000080, 0x00294a23, 0x000 },
5014 { 0x00000027, 0x00200e2d, 0x000 },
5015 { 0x00000026, 0x0020122d, 0x000 },
5016 { 0x00000000, 0x002f0083, 0x000 },
5017 { 0x00000000, 0x0ce00000, 0x0ea },
5018 { 0x00000000, 0x00600000, 0x662 },
5019 { 0x00000000, 0x00400000, 0x0eb },
5020 { 0x00000000, 0x00600000, 0x665 },
5021 { 0x00000007, 0x0020222d, 0x000 },
5022 { 0x00000005, 0x00220e22, 0x000 },
5023 { 0x00100000, 0x00280e23, 0x000 },
5024 { 0x00000000, 0x00292068, 0x000 },
5025 { 0x00000000, 0x003a0c02, 0x000 },
5026 { 0x000000ef, 0x00280e23, 0x000 },
5027 { 0x00000000, 0x00292068, 0x000 },
5028 { 0x00000017, 0x00200e2d, 0x000 },
5029 { 0x00000003, 0x00210223, 0x000 },
5030 { 0x00000000, 0x14e00000, 0x0f8 },
5031 { 0x0000000b, 0x00210228, 0x000 },
5032 { 0x00000000, 0x14c00000, 0x0f8 },
5033 { 0x00000400, 0x00292228, 0x000 },
5034 { 0x00000014, 0x00203628, 0x000 },
5035 { 0x0000001c, 0x00210e22, 0x000 },
5036 { 0x00000000, 0x14c00000, 0x0fd },
5037 { 0x0000a30c, 0x00204411, 0x000 },
5038 { 0x00000000, 0x00204811, 0x000 },
5039 { 0x0000001e, 0x00210e22, 0x000 },
5040 { 0x00000000, 0x14c00000, 0x10b },
5041 { 0x0000a30f, 0x00204411, 0x000 },
5042 { 0x00000011, 0x00200e2d, 0x000 },
5043 { 0x00000001, 0x002f0223, 0x000 },
5044 { 0x00000000, 0x0cc00000, 0x104 },
5045 { 0xffffffff, 0x00404811, 0x10b },
5046 { 0x00000002, 0x002f0223, 0x000 },
5047 { 0x00000000, 0x0cc00000, 0x107 },
5048 { 0x0000ffff, 0x00404811, 0x10b },
5049 { 0x00000004, 0x002f0223, 0x000 },
5050 { 0x00000000, 0x0cc00000, 0x10a },
5051 { 0x000000ff, 0x00404811, 0x10b },
5052 { 0x00000001, 0x00204811, 0x000 },
5053 { 0x0002c400, 0x00204411, 0x000 },
5054 { 0x0000001f, 0x00210e22, 0x000 },
5055 { 0x00000000, 0x14c00000, 0x112 },
5056 { 0x00000010, 0x40210e20, 0x000 },
5057 { 0x00000013, 0x00203623, 0x000 },
5058 { 0x00000018, 0x40224a20, 0x000 },
5059 { 0x00000010, 0xc0424a20, 0x114 },
5060 { 0x00000000, 0x00200c11, 0x000 },
5061 { 0x00000013, 0x00203623, 0x000 },
5062 { 0x00000000, 0x00204811, 0x000 },
5063 { 0x00000000, 0x00204811, 0x000 },
5064 { 0x0000000a, 0x00201011, 0x000 },
5065 { 0x00000000, 0x002f0224, 0x000 },
5066 { 0x00000000, 0x0ce00000, 0x11b },
5067 { 0x00000000, 0x00204811, 0x000 },
5068 { 0x00000001, 0x00531224, 0x117 },
5069 { 0xffbfffff, 0x00283a2e, 0x000 },
5070 { 0x0000001b, 0x00210222, 0x000 },
5071 { 0x00000000, 0x14c00000, 0x12e },
5072 { 0x81000000, 0x00204411, 0x000 },
5073 { 0x0000000d, 0x00204811, 0x000 },
5074 { 0x00000018, 0x00220e30, 0x000 },
5075 { 0xfc000000, 0x00280e23, 0x000 },
5076 { 0x81000000, 0x00204411, 0x000 },
5077 { 0x0000000e, 0x00204811, 0x000 },
5078 { 0x00000000, 0x00201010, 0x000 },
5079 { 0x0000e00e, 0x00204411, 0x000 },
5080 { 0x07f8ff08, 0x00204811, 0x000 },
5081 { 0x00000000, 0x00294a23, 0x000 },
5082 { 0x0000001c, 0x00201e2d, 0x000 },
5083 { 0x00000008, 0x00214a27, 0x000 },
5084 { 0x00000000, 0x00204811, 0x000 },
5085 { 0x060a0200, 0x00294a24, 0x000 },
5086 { 0x00000000, 0x00204811, 0x000 },
5087 { 0x00000000, 0x00204811, 0x000 },
5088 { 0x00000000, 0x00800000, 0x000 },
5089 { 0x81000000, 0x00204411, 0x000 },
5090 { 0x00000001, 0x00204811, 0x000 },
5091 { 0x0000217c, 0x00204411, 0x000 },
5092 { 0x00800000, 0x00204811, 0x000 },
5093 { 0x00000000, 0x00204806, 0x000 },
5094 { 0x00000008, 0x00214a27, 0x000 },
5095 { 0x00000000, 0x17000000, 0x000 },
5096 { 0x0004217f, 0x00604411, 0x68d },
5097 { 0x0000001f, 0x00210230, 0x000 },
5098 { 0x00000000, 0x14c00000, 0x68c },
5099 { 0x00000004, 0x00404c11, 0x135 },
5100 { 0x81000000, 0x00204411, 0x000 },
5101 { 0x00000001, 0x00204811, 0x000 },
5102 { 0x000021f8, 0x00204411, 0x000 },
5103 { 0x0000001c, 0x00204811, 0x000 },
5104 { 0x000421f9, 0x00604411, 0x68d },
5105 { 0x00000011, 0x00210230, 0x000 },
5106 { 0x00000000, 0x14e00000, 0x13c },
5107 { 0x00000000, 0x00800000, 0x000 },
5108 { 0x00000000, 0x00600000, 0x00b },
5109 { 0x00000000, 0x00600411, 0x315 },
5110 { 0x00000000, 0x00200411, 0x000 },
5111 { 0x00000000, 0x00600811, 0x1b2 },
5112 { 0x00000000, 0x00600000, 0x160 },
5113 { 0x0000ffff, 0x40280e20, 0x000 },
5114 { 0x00000010, 0xc0211220, 0x000 },
5115 { 0x0000ffff, 0x40280620, 0x000 },
5116 { 0x00000010, 0xc0210a20, 0x000 },
5117 { 0x00000000, 0x00341461, 0x000 },
5118 { 0x00000000, 0x00741882, 0x2bb },
5119 { 0x0001a1fd, 0x00604411, 0x2e0 },
5120 { 0x00003fff, 0x002f022f, 0x000 },
5121 { 0x00000000, 0x0cc00000, 0x147 },
5122 { 0x00000000, 0xc0400400, 0x001 },
5123 { 0x00000000, 0x00600000, 0x00b },
5124 { 0x00000000, 0x00600411, 0x315 },
5125 { 0x00000000, 0x00200411, 0x000 },
5126 { 0x00000000, 0x00600811, 0x1b2 },
5127 { 0x00003fff, 0x002f022f, 0x000 },
5128 { 0x00000000, 0x0ce00000, 0x000 },
5129 { 0x00000000, 0x00600000, 0x160 },
5130 { 0x00000010, 0x40210e20, 0x000 },
5131 { 0x0000ffff, 0xc0281220, 0x000 },
5132 { 0x00000010, 0x40211620, 0x000 },
5133 { 0x0000ffff, 0xc0681a20, 0x2bb },
5134 { 0x0001a1fd, 0x00604411, 0x2e0 },
5135 { 0x00003fff, 0x002f022f, 0x000 },
5136 { 0x00000000, 0x0cc00000, 0x158 },
5137 { 0x00000000, 0xc0400400, 0x001 },
5138 { 0x0000225c, 0x00204411, 0x000 },
5139 { 0x00000001, 0x00300a2f, 0x000 },
5140 { 0x00000001, 0x00210a22, 0x000 },
5141 { 0x00000003, 0x00384a22, 0x000 },
5142 { 0x00002256, 0x00204411, 0x000 },
5143 { 0x0000001a, 0x00204811, 0x000 },
5144 { 0x0000a1fc, 0x00204411, 0x000 },
5145 { 0x00000001, 0x00804811, 0x000 },
5146 { 0x00000000, 0x00600000, 0x00b },
5147 { 0x00000000, 0x00600000, 0x18f },
5148 { 0x00000000, 0x00600000, 0x1a0 },
5149 { 0x00003fff, 0x002f022f, 0x000 },
5150 { 0x00000000, 0x0ce00000, 0x000 },
5151 { 0x00000000, 0x00202c08, 0x000 },
5152 { 0x00000000, 0x00202411, 0x000 },
5153 { 0x00000000, 0x00202811, 0x000 },
5154 { 0x00002256, 0x00204411, 0x000 },
5155 { 0x00000016, 0x00204811, 0x000 },
5156 { 0x0000225c, 0x00204411, 0x000 },
5157 { 0x00000003, 0x00204811, 0x000 },
5158 { 0x93800000, 0x00204411, 0x000 },
5159 { 0x00000002, 0x00221e29, 0x000 },
5160 { 0x00000000, 0x007048eb, 0x19c },
5161 { 0x00000000, 0x00600000, 0x2bb },
5162 { 0x00000001, 0x40330620, 0x000 },
5163 { 0x00000000, 0xc0302409, 0x000 },
5164 { 0x00003fff, 0x002f022f, 0x000 },
5165 { 0x00000000, 0x0ce00000, 0x000 },
5166 { 0x00000000, 0x00600000, 0x2a3 },
5167 { 0x00000000, 0x002f0221, 0x000 },
5168 { 0x00000000, 0x0ae00000, 0x181 },
5169 { 0x00000000, 0x00600000, 0x13a },
5170 { 0x00000000, 0x00400000, 0x186 },
5171 { 0x95000000, 0x00204411, 0x000 },
5172 { 0x00000000, 0x002f0221, 0x000 },
5173 { 0x00000000, 0x0ce00000, 0x186 },
5174 { 0x00000000, 0xc0204800, 0x000 },
5175 { 0x00000001, 0x00530621, 0x182 },
5176 { 0x92000000, 0x00204411, 0x000 },
5177 { 0x00000000, 0xc0604800, 0x197 },
5178 { 0x0001a1fd, 0x00204411, 0x000 },
5179 { 0x00000011, 0x0020062d, 0x000 },
5180 { 0x00000000, 0x0078042a, 0x2fb },
5181 { 0x00000000, 0x00202809, 0x000 },
5182 { 0x00003fff, 0x002f022f, 0x000 },
5183 { 0x00000000, 0x0cc00000, 0x174 },
5184 { 0x00000000, 0xc0400400, 0x001 },
5185 { 0x00000210, 0x00600411, 0x315 },
5186 { 0x00003fff, 0x002f022f, 0x000 },
5187 { 0x00000000, 0x0ce00000, 0x194 },
5188 { 0x00000015, 0xc0203620, 0x000 },
5189 { 0x00000016, 0xc0203620, 0x000 },
5190 { 0x3f800000, 0x00200411, 0x000 },
5191 { 0x46000000, 0x00600811, 0x1b2 },
5192 { 0x00000000, 0x00800000, 0x000 },
5193 { 0x0000a1fc, 0x00204411, 0x000 },
5194 { 0x00003fff, 0x002f022f, 0x000 },
5195 { 0x00000000, 0x0cc00000, 0x19b },
5196 { 0x00000001, 0x00804811, 0x000 },
5197 { 0x00000021, 0x00804811, 0x000 },
5198 { 0x0000ffff, 0x40280e20, 0x000 },
5199 { 0x00000010, 0xc0211220, 0x000 },
5200 { 0x0000ffff, 0x40281620, 0x000 },
5201 { 0x00000010, 0xc0811a20, 0x000 },
5202 { 0x81000000, 0x00204411, 0x000 },
5203 { 0x00000006, 0x00204811, 0x000 },
5204 { 0x00000008, 0x00221e30, 0x000 },
5205 { 0x00000029, 0x00201a2d, 0x000 },
5206 { 0x0000e000, 0x00204411, 0x000 },
5207 { 0xfffbff09, 0x00204811, 0x000 },
5208 { 0x0000000f, 0x0020222d, 0x000 },
5209 { 0x00001fff, 0x00294a28, 0x000 },
5210 { 0x00000006, 0x0020222d, 0x000 },
5211 { 0x00000000, 0x002920e8, 0x000 },
5212 { 0x00000000, 0x00204808, 0x000 },
5213 { 0x00000000, 0x00204811, 0x000 },
5214 { 0x060a0200, 0x00294a26, 0x000 },
5215 { 0x00000000, 0x00204811, 0x000 },
5216 { 0x00000000, 0x00204811, 0x000 },
5217 { 0x00000100, 0x00201811, 0x000 },
5218 { 0x00000008, 0x00621e28, 0x12f },
5219 { 0x00000008, 0x00822228, 0x000 },
5220 { 0x0002c000, 0x00204411, 0x000 },
5221 { 0x00000015, 0x00600e2d, 0x1bd },
5222 { 0x00000016, 0x00600e2d, 0x1bd },
5223 { 0x0000c008, 0x00204411, 0x000 },
5224 { 0x00000017, 0x00200e2d, 0x000 },
5225 { 0x00000000, 0x14c00000, 0x1b9 },
5226 { 0x00000000, 0x00200411, 0x000 },
5227 { 0x00000000, 0x00204801, 0x000 },
5228 { 0x39000000, 0x00204811, 0x000 },
5229 { 0x00000000, 0x00204811, 0x000 },
5230 { 0x00000000, 0x00804802, 0x000 },
5231 { 0x00000018, 0x00202e2d, 0x000 },
5232 { 0x00000000, 0x003b0d63, 0x000 },
5233 { 0x00000008, 0x00224a23, 0x000 },
5234 { 0x00000010, 0x00224a23, 0x000 },
5235 { 0x00000018, 0x00224a23, 0x000 },
5236 { 0x00000000, 0x00804803, 0x000 },
5237 { 0x00000000, 0x00600000, 0x00b },
5238 { 0x00001000, 0x00600411, 0x315 },
5239 { 0x00000000, 0x00200411, 0x000 },
5240 { 0x00000000, 0x00600811, 0x1b2 },
5241 { 0x00000007, 0x0021062f, 0x000 },
5242 { 0x00000013, 0x00200a2d, 0x000 },
5243 { 0x00000001, 0x00202c11, 0x000 },
5244 { 0x0000ffff, 0x40282220, 0x000 },
5245 { 0x0000000f, 0x00262228, 0x000 },
5246 { 0x00000010, 0x40212620, 0x000 },
5247 { 0x0000000f, 0x00262629, 0x000 },
5248 { 0x00000000, 0x00202802, 0x000 },
5249 { 0x00002256, 0x00204411, 0x000 },
5250 { 0x0000001b, 0x00204811, 0x000 },
5251 { 0x00000000, 0x002f0221, 0x000 },
5252 { 0x00000000, 0x0ce00000, 0x1e0 },
5253 { 0x0000225c, 0x00204411, 0x000 },
5254 { 0x00000081, 0x00204811, 0x000 },
5255 { 0x0000a1fc, 0x00204411, 0x000 },
5256 { 0x00000001, 0x00204811, 0x000 },
5257 { 0x00000080, 0x00201c11, 0x000 },
5258 { 0x00000000, 0x002f0227, 0x000 },
5259 { 0x00000000, 0x0ce00000, 0x1dc },
5260 { 0x00000000, 0x00600000, 0x1e9 },
5261 { 0x00000001, 0x00531e27, 0x1d8 },
5262 { 0x00000001, 0x00202c11, 0x000 },
5263 { 0x0000001f, 0x00280a22, 0x000 },
5264 { 0x0000001f, 0x00282a2a, 0x000 },
5265 { 0x00000001, 0x00530621, 0x1d1 },
5266 { 0x0000225c, 0x00204411, 0x000 },
5267 { 0x00000002, 0x00304a2f, 0x000 },
5268 { 0x0000a1fc, 0x00204411, 0x000 },
5269 { 0x00000001, 0x00204811, 0x000 },
5270 { 0x00000001, 0x00301e2f, 0x000 },
5271 { 0x00000000, 0x002f0227, 0x000 },
5272 { 0x00000000, 0x0ce00000, 0x000 },
5273 { 0x00000000, 0x00600000, 0x1e9 },
5274 { 0x00000001, 0x00531e27, 0x1e5 },
5275 { 0x0000ffff, 0x40280e20, 0x000 },
5276 { 0x0000000f, 0x00260e23, 0x000 },
5277 { 0x00000010, 0xc0211220, 0x000 },
5278 { 0x0000000f, 0x00261224, 0x000 },
5279 { 0x00000000, 0x00201411, 0x000 },
5280 { 0x00000000, 0x00601811, 0x2bb },
5281 { 0x0001a1fd, 0x00204411, 0x000 },
5282 { 0x00000000, 0x002f022b, 0x000 },
5283 { 0x00000000, 0x0ce00000, 0x1f8 },
5284 { 0x00000010, 0x00221628, 0x000 },
5285 { 0xffff0000, 0x00281625, 0x000 },
5286 { 0x0000ffff, 0x00281a29, 0x000 },
5287 { 0x00000000, 0x002948c5, 0x000 },
5288 { 0x00000000, 0x0020480a, 0x000 },
5289 { 0x00000000, 0x00202c11, 0x000 },
5290 { 0x00000010, 0x00221623, 0x000 },
5291 { 0xffff0000, 0x00281625, 0x000 },
5292 { 0x0000ffff, 0x00281a24, 0x000 },
5293 { 0x00000000, 0x002948c5, 0x000 },
5294 { 0x00000000, 0x00731503, 0x205 },
5295 { 0x00000000, 0x00201805, 0x000 },
5296 { 0x00000000, 0x00731524, 0x205 },
5297 { 0x00000000, 0x002d14c5, 0x000 },
5298 { 0x00000000, 0x003008a2, 0x000 },
5299 { 0x00000000, 0x00204802, 0x000 },
5300 { 0x00000000, 0x00202802, 0x000 },
5301 { 0x00000000, 0x00202003, 0x000 },
5302 { 0x00000000, 0x00802404, 0x000 },
5303 { 0x0000000f, 0x00210225, 0x000 },
5304 { 0x00000000, 0x14c00000, 0x68c },
5305 { 0x00000000, 0x002b1405, 0x000 },
5306 { 0x00000001, 0x00901625, 0x000 },
5307 { 0x00000000, 0x00600000, 0x00b },
5308 { 0x00000000, 0x00600411, 0x315 },
5309 { 0x00000000, 0x00200411, 0x000 },
5310 { 0x00000000, 0x00600811, 0x1b2 },
5311 { 0x00002256, 0x00204411, 0x000 },
5312 { 0x0000001a, 0x00294a22, 0x000 },
5313 { 0x00000000, 0xc0200000, 0x000 },
5314 { 0x00003fff, 0x002f022f, 0x000 },
5315 { 0x00000000, 0x0ce00000, 0x000 },
5316 { 0x00000000, 0xc0200400, 0x000 },
5317 { 0x0000225c, 0x00204411, 0x000 },
5318 { 0x00000003, 0x00384a21, 0x000 },
5319 { 0x0000a1fc, 0x00204411, 0x000 },
5320 { 0x00000001, 0x00204811, 0x000 },
5321 { 0x0000ffff, 0x40281220, 0x000 },
5322 { 0x00000010, 0xc0211a20, 0x000 },
5323 { 0x0000ffff, 0x40280e20, 0x000 },
5324 { 0x00000010, 0xc0211620, 0x000 },
5325 { 0x00000000, 0x00741465, 0x2bb },
5326 { 0x0001a1fd, 0x00604411, 0x2e0 },
5327 { 0x00000001, 0x00330621, 0x000 },
5328 { 0x00000000, 0x002f0221, 0x000 },
5329 { 0x00000000, 0x0cc00000, 0x219 },
5330 { 0x00003fff, 0x002f022f, 0x000 },
5331 { 0x00000000, 0x0cc00000, 0x212 },
5332 { 0x00000000, 0xc0400400, 0x001 },
5333 { 0x00000000, 0x00600000, 0x645 },
5334 { 0x00000000, 0x0040040f, 0x213 },
5335 { 0x00000000, 0x00600000, 0x631 },
5336 { 0x00000000, 0x00600000, 0x645 },
5337 { 0x00000210, 0x00600411, 0x315 },
5338 { 0x00000000, 0x00600000, 0x1a0 },
5339 { 0x00000000, 0x00600000, 0x19c },
5340 { 0x00000000, 0x00600000, 0x2bb },
5341 { 0x00000000, 0x00600000, 0x2a3 },
5342 { 0x93800000, 0x00204411, 0x000 },
5343 { 0x00000000, 0x00204808, 0x000 },
5344 { 0x00000000, 0x002f022f, 0x000 },
5345 { 0x00000000, 0x0ae00000, 0x232 },
5346 { 0x00000000, 0x00600000, 0x13a },
5347 { 0x00000000, 0x00400000, 0x236 },
5348 { 0x95000000, 0x00204411, 0x000 },
5349 { 0x00000000, 0x002f022f, 0x000 },
5350 { 0x00000000, 0x0ce00000, 0x236 },
5351 { 0x00000000, 0xc0404800, 0x233 },
5352 { 0x92000000, 0x00204411, 0x000 },
5353 { 0x00000000, 0xc0204800, 0x000 },
5354 { 0x00002256, 0x00204411, 0x000 },
5355 { 0x00000016, 0x00204811, 0x000 },
5356 { 0x0000225c, 0x00204411, 0x000 },
5357 { 0x00000003, 0x00204811, 0x000 },
5358 { 0x0000a1fc, 0x00204411, 0x000 },
5359 { 0x00000001, 0x00204811, 0x000 },
5360 { 0x0001a1fd, 0x00204411, 0x000 },
5361 { 0x00000000, 0x00600411, 0x2fb },
5362 { 0x00000000, 0xc0400400, 0x001 },
5363 { 0x00000000, 0x00600000, 0x631 },
5364 { 0x0000a00c, 0x00204411, 0x000 },
5365 { 0x00000000, 0xc0204800, 0x000 },
5366 { 0x00000000, 0xc0404800, 0x000 },
5367 { 0x00000000, 0x00600000, 0x00b },
5368 { 0x00000018, 0x40210a20, 0x000 },
5369 { 0x00000003, 0x002f0222, 0x000 },
5370 { 0x00000000, 0x0ae00000, 0x24c },
5371 { 0x00000014, 0x0020222d, 0x000 },
5372 { 0x00080101, 0x00292228, 0x000 },
5373 { 0x00000014, 0x00203628, 0x000 },
5374 { 0x0000a30c, 0x00204411, 0x000 },
5375 { 0x00000000, 0xc0204800, 0x000 },
5376 { 0x00000000, 0xc0204800, 0x000 },
5377 { 0x00000000, 0xc0404800, 0x251 },
5378 { 0x00000000, 0x00600000, 0x00b },
5379 { 0x00000010, 0x00600411, 0x315 },
5380 { 0x3f800000, 0x00200411, 0x000 },
5381 { 0x00000000, 0x00600811, 0x1b2 },
5382 { 0x0000225c, 0x00204411, 0x000 },
5383 { 0x00000003, 0x00204811, 0x000 },
5384 { 0x00000000, 0x00600000, 0x27c },
5385 { 0x00000017, 0x00201e2d, 0x000 },
5386 { 0x00000001, 0x00211e27, 0x000 },
5387 { 0x00000000, 0x14e00000, 0x26a },
5388 { 0x00000012, 0x00201e2d, 0x000 },
5389 { 0x0000ffff, 0x00281e27, 0x000 },
5390 { 0x00000000, 0x00341c27, 0x000 },
5391 { 0x00000000, 0x12c00000, 0x25f },
5392 { 0x00000000, 0x00201c11, 0x000 },
5393 { 0x00000000, 0x002f00e5, 0x000 },
5394 { 0x00000000, 0x08c00000, 0x262 },
5395 { 0x00000000, 0x00201407, 0x000 },
5396 { 0x00000012, 0x00201e2d, 0x000 },
5397 { 0x00000010, 0x00211e27, 0x000 },
5398 { 0x00000000, 0x00341c47, 0x000 },
5399 { 0x00000000, 0x12c00000, 0x267 },
5400 { 0x00000000, 0x00201c11, 0x000 },
5401 { 0x00000000, 0x002f00e6, 0x000 },
5402 { 0x00000000, 0x08c00000, 0x26a },
5403 { 0x00000000, 0x00201807, 0x000 },
5404 { 0x00000000, 0x00600000, 0x2c1 },
5405 { 0x00002256, 0x00204411, 0x000 },
5406 { 0x00000000, 0x00342023, 0x000 },
5407 { 0x00000000, 0x12c00000, 0x272 },
5408 { 0x00000000, 0x00342044, 0x000 },
5409 { 0x00000000, 0x12c00000, 0x271 },
5410 { 0x00000016, 0x00404811, 0x276 },
5411 { 0x00000018, 0x00404811, 0x276 },
5412 { 0x00000000, 0x00342044, 0x000 },
5413 { 0x00000000, 0x12c00000, 0x275 },
5414 { 0x00000017, 0x00404811, 0x276 },
5415 { 0x00000019, 0x00204811, 0x000 },
5416 { 0x0000a1fc, 0x00204411, 0x000 },
5417 { 0x00000001, 0x00204811, 0x000 },
5418 { 0x0001a1fd, 0x00604411, 0x2e9 },
5419 { 0x00003fff, 0x002f022f, 0x000 },
5420 { 0x00000000, 0x0cc00000, 0x256 },
5421 { 0x00000000, 0xc0400400, 0x001 },
5422 { 0x00000010, 0x40210620, 0x000 },
5423 { 0x0000ffff, 0xc0280a20, 0x000 },
5424 { 0x00000010, 0x40210e20, 0x000 },
5425 { 0x0000ffff, 0xc0281220, 0x000 },
5426 { 0x00000010, 0x40211620, 0x000 },
5427 { 0x0000ffff, 0xc0881a20, 0x000 },
5428 { 0x81000000, 0x00204411, 0x000 },
5429 { 0x00000001, 0x00204811, 0x000 },
5430 { 0x00042004, 0x00604411, 0x68d },
5431 { 0x00000000, 0x00600000, 0x631 },
5432 { 0x00000000, 0xc0600000, 0x2a3 },
5433 { 0x00000005, 0x00200a2d, 0x000 },
5434 { 0x00000008, 0x00220a22, 0x000 },
5435 { 0x0000002b, 0x00201a2d, 0x000 },
5436 { 0x0000001c, 0x00201e2d, 0x000 },
5437 { 0x00007000, 0x00281e27, 0x000 },
5438 { 0x00000000, 0x00311ce6, 0x000 },
5439 { 0x0000002a, 0x00201a2d, 0x000 },
5440 { 0x0000000c, 0x00221a26, 0x000 },
5441 { 0x00000000, 0x002f00e6, 0x000 },
5442 { 0x00000000, 0x06e00000, 0x292 },
5443 { 0x00000000, 0x00201c11, 0x000 },
5444 { 0x00000000, 0x00200c11, 0x000 },
5445 { 0x0000002b, 0x00203623, 0x000 },
5446 { 0x00000010, 0x00201811, 0x000 },
5447 { 0x00000000, 0x00691ce2, 0x12f },
5448 { 0x93800000, 0x00204411, 0x000 },
5449 { 0x00000000, 0x00204807, 0x000 },
5450 { 0x95000000, 0x00204411, 0x000 },
5451 { 0x00000000, 0x002f022f, 0x000 },
5452 { 0x00000000, 0x0ce00000, 0x29d },
5453 { 0x00000001, 0x00333e2f, 0x000 },
5454 { 0x00000000, 0xd9004800, 0x000 },
5455 { 0x92000000, 0x00204411, 0x000 },
5456 { 0x00000000, 0xc0204800, 0x000 },
5457 { 0x0000001c, 0x00403627, 0x000 },
5458 { 0x0000000c, 0xc0220a20, 0x000 },
5459 { 0x00000029, 0x00203622, 0x000 },
5460 { 0x00000028, 0xc0403620, 0x000 },
5461 { 0x0000a2a4, 0x00204411, 0x000 },
5462 { 0x00000009, 0x00204811, 0x000 },
5463 { 0xa1000000, 0x00204411, 0x000 },
5464 { 0x00000001, 0x00804811, 0x000 },
5465 { 0x00000021, 0x00201e2d, 0x000 },
5466 { 0x00000000, 0x002c1ce3, 0x000 },
5467 { 0x00000021, 0x00203627, 0x000 },
5468 { 0x00000022, 0x00201e2d, 0x000 },
5469 { 0x00000000, 0x002c1ce4, 0x000 },
5470 { 0x00000022, 0x00203627, 0x000 },
5471 { 0x00000023, 0x00201e2d, 0x000 },
5472 { 0x00000000, 0x003120a3, 0x000 },
5473 { 0x00000000, 0x002d1d07, 0x000 },
5474 { 0x00000023, 0x00203627, 0x000 },
5475 { 0x00000024, 0x00201e2d, 0x000 },
5476 { 0x00000000, 0x003120c4, 0x000 },
5477 { 0x00000000, 0x002d1d07, 0x000 },
5478 { 0x00000024, 0x00803627, 0x000 },
5479 { 0x00000021, 0x00203623, 0x000 },
5480 { 0x00000022, 0x00203624, 0x000 },
5481 { 0x00000000, 0x00311ca3, 0x000 },
5482 { 0x00000023, 0x00203627, 0x000 },
5483 { 0x00000000, 0x00311cc4, 0x000 },
5484 { 0x00000024, 0x00803627, 0x000 },
5485 { 0x0000001a, 0x00203627, 0x000 },
5486 { 0x0000001b, 0x00203628, 0x000 },
5487 { 0x00000017, 0x00201e2d, 0x000 },
5488 { 0x00000002, 0x00210227, 0x000 },
5489 { 0x00000000, 0x14c00000, 0x2dc },
5490 { 0x00000000, 0x00400000, 0x2d9 },
5491 { 0x0000001a, 0x00203627, 0x000 },
5492 { 0x0000001b, 0x00203628, 0x000 },
5493 { 0x00000017, 0x00201e2d, 0x000 },
5494 { 0x00000002, 0x00210227, 0x000 },
5495 { 0x00000000, 0x14e00000, 0x2d9 },
5496 { 0x00000003, 0x00210227, 0x000 },
5497 { 0x00000000, 0x14e00000, 0x2dc },
5498 { 0x00000023, 0x00201e2d, 0x000 },
5499 { 0x00000000, 0x002e00e1, 0x000 },
5500 { 0x00000000, 0x02c00000, 0x2dc },
5501 { 0x00000021, 0x00201e2d, 0x000 },
5502 { 0x00000000, 0x003120a1, 0x000 },
5503 { 0x00000000, 0x002e00e8, 0x000 },
5504 { 0x00000000, 0x06c00000, 0x2dc },
5505 { 0x00000024, 0x00201e2d, 0x000 },
5506 { 0x00000000, 0x002e00e2, 0x000 },
5507 { 0x00000000, 0x02c00000, 0x2dc },
5508 { 0x00000022, 0x00201e2d, 0x000 },
5509 { 0x00000000, 0x003120c2, 0x000 },
5510 { 0x00000000, 0x002e00e8, 0x000 },
5511 { 0x00000000, 0x06c00000, 0x2dc },
5512 { 0x00000000, 0x00600000, 0x668 },
5513 { 0x00000000, 0x00600000, 0x2b5 },
5514 { 0x00000000, 0x00400000, 0x2de },
5515 { 0x00000000, 0x00600000, 0x2b5 },
5516 { 0x00000000, 0x00600000, 0x65f },
5517 { 0x00000000, 0x00400000, 0x2de },
5518 { 0x00000000, 0x00600000, 0x2a7 },
5519 { 0x00000000, 0x00400000, 0x2de },
5520 { 0x0000001a, 0x00201e2d, 0x000 },
5521 { 0x0000001b, 0x0080222d, 0x000 },
5522 { 0x00000010, 0x00221e23, 0x000 },
5523 { 0x00000000, 0x00294887, 0x000 },
5524 { 0x00000000, 0x00311ca3, 0x000 },
5525 { 0x00000010, 0x00221e27, 0x000 },
5526 { 0x00000000, 0x00294887, 0x000 },
5527 { 0x00000010, 0x00221e23, 0x000 },
5528 { 0x00000000, 0x003120c4, 0x000 },
5529 { 0x0000ffff, 0x00282228, 0x000 },
5530 { 0x00000000, 0x00894907, 0x000 },
5531 { 0x00000010, 0x00221e23, 0x000 },
5532 { 0x00000000, 0x00294887, 0x000 },
5533 { 0x00000010, 0x00221e21, 0x000 },
5534 { 0x00000000, 0x00294847, 0x000 },
5535 { 0x00000000, 0x00311ca3, 0x000 },
5536 { 0x00000010, 0x00221e27, 0x000 },
5537 { 0x00000000, 0x00294887, 0x000 },
5538 { 0x00000000, 0x00311ca1, 0x000 },
5539 { 0x00000010, 0x00221e27, 0x000 },
5540 { 0x00000000, 0x00294847, 0x000 },
5541 { 0x00000010, 0x00221e23, 0x000 },
5542 { 0x00000000, 0x003120c4, 0x000 },
5543 { 0x0000ffff, 0x00282228, 0x000 },
5544 { 0x00000000, 0x00294907, 0x000 },
5545 { 0x00000010, 0x00221e21, 0x000 },
5546 { 0x00000000, 0x003120c2, 0x000 },
5547 { 0x0000ffff, 0x00282228, 0x000 },
5548 { 0x00000000, 0x00894907, 0x000 },
5549 { 0x00000010, 0x00221e23, 0x000 },
5550 { 0x00000000, 0x00294887, 0x000 },
5551 { 0x00000001, 0x00220a21, 0x000 },
5552 { 0x00000000, 0x003308a2, 0x000 },
5553 { 0x00000010, 0x00221e22, 0x000 },
5554 { 0x00000010, 0x00212222, 0x000 },
5555 { 0x00000000, 0x00294907, 0x000 },
5556 { 0x00000000, 0x00311ca3, 0x000 },
5557 { 0x00000010, 0x00221e27, 0x000 },
5558 { 0x00000000, 0x00294887, 0x000 },
5559 { 0x00000001, 0x00220a21, 0x000 },
5560 { 0x00000000, 0x003008a2, 0x000 },
5561 { 0x00000010, 0x00221e22, 0x000 },
5562 { 0x00000010, 0x00212222, 0x000 },
5563 { 0x00000000, 0x00294907, 0x000 },
5564 { 0x00000010, 0x00221e23, 0x000 },
5565 { 0x00000000, 0x003120c4, 0x000 },
5566 { 0x0000ffff, 0x00282228, 0x000 },
5567 { 0x00000000, 0x00294907, 0x000 },
5568 { 0x00000000, 0x003808c5, 0x000 },
5569 { 0x00000000, 0x00300841, 0x000 },
5570 { 0x00000001, 0x00220a22, 0x000 },
5571 { 0x00000000, 0x003308a2, 0x000 },
5572 { 0x00000010, 0x00221e22, 0x000 },
5573 { 0x00000010, 0x00212222, 0x000 },
5574 { 0x00000000, 0x00894907, 0x000 },
5575 { 0x00000017, 0x0020222d, 0x000 },
5576 { 0x00000000, 0x14c00000, 0x318 },
5577 { 0xffffffef, 0x00280621, 0x000 },
5578 { 0x00000014, 0x0020222d, 0x000 },
5579 { 0x0000f8e0, 0x00204411, 0x000 },
5580 { 0x00000000, 0x00294901, 0x000 },
5581 { 0x00000000, 0x00894901, 0x000 },
5582 { 0x00000000, 0x00204811, 0x000 },
5583 { 0x00000000, 0x00204811, 0x000 },
5584 { 0x060a0200, 0x00804811, 0x000 },
5585 { 0x00000000, 0xc0200000, 0x000 },
5586 { 0x97000000, 0xc0204411, 0x000 },
5587 { 0x00000000, 0xc0204811, 0x000 },
5588 { 0x8a000000, 0x00204411, 0x000 },
5589 { 0x00000000, 0x00204811, 0x000 },
5590 { 0x0000225c, 0x00204411, 0x000 },
5591 { 0x00000000, 0xc0204800, 0x000 },
5592 { 0x0000a1fc, 0x00204411, 0x000 },
5593 { 0x00000000, 0xc0204800, 0x000 },
5594 { 0x00000000, 0xc0200400, 0x000 },
5595 { 0x00000000, 0x00a0000a, 0x000 },
5596 { 0x97000000, 0x00204411, 0x000 },
5597 { 0x00000000, 0x00204811, 0x000 },
5598 { 0x8a000000, 0x00204411, 0x000 },
5599 { 0x00000000, 0x00204811, 0x000 },
5600 { 0x0000225c, 0x00204411, 0x000 },
5601 { 0x00000000, 0xc0204800, 0x000 },
5602 { 0x0000a1fc, 0x00204411, 0x000 },
5603 { 0x00000000, 0xc0204800, 0x000 },
5604 { 0x00000000, 0xc0200400, 0x000 },
5605 { 0x00000000, 0x00a0000a, 0x000 },
5606 { 0x97000000, 0x00204411, 0x000 },
5607 { 0x00000000, 0x00204811, 0x000 },
5608 { 0x8a000000, 0x00204411, 0x000 },
5609 { 0x00000000, 0x00204811, 0x000 },
5610 { 0x0000225c, 0x00204411, 0x000 },
5611 { 0x00000000, 0xc0204800, 0x000 },
5612 { 0x0000a1fc, 0x00204411, 0x000 },
5613 { 0x00000000, 0xc0204800, 0x000 },
5614 { 0x0001a1fd, 0x00204411, 0x000 },
5615 { 0x00000000, 0xd9004800, 0x000 },
5616 { 0x00000000, 0xc0200400, 0x000 },
5617 { 0x00000000, 0x00a0000a, 0x000 },
5618 { 0x00002257, 0x00204411, 0x000 },
5619 { 0x00000003, 0xc0484a20, 0x000 },
5620 { 0x0000225d, 0x00204411, 0x000 },
5621 { 0x00000000, 0xc0404800, 0x000 },
5622 { 0x00000000, 0x00600000, 0x645 },
5623 { 0x00000000, 0xc0200800, 0x000 },
5624 { 0x0000225c, 0x00204411, 0x000 },
5625 { 0x00000003, 0x00384a22, 0x000 },
5626 { 0x0000a1fc, 0x00204411, 0x000 },
5627 { 0x00000000, 0xc0204800, 0x000 },
5628 { 0x0001a1fd, 0x00204411, 0x000 },
5629 { 0x00000000, 0x002f0222, 0x000 },
5630 { 0x00000000, 0x0ce00000, 0x000 },
5631 { 0x00000000, 0x40204800, 0x000 },
5632 { 0x00000001, 0x40304a20, 0x000 },
5633 { 0x00000002, 0xc0304a20, 0x000 },
5634 { 0x00000001, 0x00530a22, 0x34b },
5635 { 0x0000003f, 0xc0280a20, 0x000 },
5636 { 0x81000000, 0x00204411, 0x000 },
5637 { 0x00000001, 0x00204811, 0x000 },
5638 { 0x000021f8, 0x00204411, 0x000 },
5639 { 0x00000018, 0x00204811, 0x000 },
5640 { 0x000421f9, 0x00604411, 0x68d },
5641 { 0x00000011, 0x00210230, 0x000 },
5642 { 0x00000000, 0x14e00000, 0x354 },
5643 { 0x00000014, 0x002f0222, 0x000 },
5644 { 0x00000000, 0x0cc00000, 0x364 },
5645 { 0x00002010, 0x00204411, 0x000 },
5646 { 0x00008000, 0x00204811, 0x000 },
5647 { 0x0001a2a4, 0x00204411, 0x000 },
5648 { 0x00000000, 0x00604802, 0x36e },
5649 { 0x00002100, 0x00204411, 0x000 },
5650 { 0x00000000, 0xc0204800, 0x000 },
5651 { 0x00000000, 0xc0204800, 0x000 },
5652 { 0x00000000, 0xc0204800, 0x000 },
5653 { 0x00000000, 0xc0404800, 0x000 },
5654 { 0x00000004, 0x002f0222, 0x000 },
5655 { 0x00000000, 0x0cc00000, 0x36a },
5656 { 0x00002010, 0x00204411, 0x000 },
5657 { 0x00008000, 0x00204811, 0x000 },
5658 { 0x0001a2a4, 0x00204411, 0x000 },
5659 { 0x00000000, 0x00404802, 0x35f },
5660 { 0x00000028, 0x002f0222, 0x000 },
5661 { 0x00000000, 0x0cc00000, 0x5c0 },
5662 { 0x0001a2a4, 0x00204411, 0x000 },
5663 { 0x00000000, 0x00404802, 0x35f },
5664 { 0x0000002c, 0x00203626, 0x000 },
5665 { 0x00000049, 0x00201811, 0x000 },
5666 { 0x0000003f, 0x00204811, 0x000 },
5667 { 0x00000001, 0x00331a26, 0x000 },
5668 { 0x00000000, 0x002f0226, 0x000 },
5669 { 0x00000000, 0x0cc00000, 0x370 },
5670 { 0x0000002c, 0x00801a2d, 0x000 },
5671 { 0x0000003f, 0xc0280a20, 0x000 },
5672 { 0x00000015, 0x002f0222, 0x000 },
5673 { 0x00000000, 0x0ce00000, 0x386 },
5674 { 0x00000006, 0x002f0222, 0x000 },
5675 { 0x00000000, 0x0ce00000, 0x3b1 },
5676 { 0x00000016, 0x002f0222, 0x000 },
5677 { 0x00000000, 0x0ce00000, 0x3b5 },
5678 { 0x00000020, 0x002f0222, 0x000 },
5679 { 0x00000000, 0x0ce00000, 0x39c },
5680 { 0x0000000f, 0x002f0222, 0x000 },
5681 { 0x00000000, 0x0ce00000, 0x3a8 },
5682 { 0x00000010, 0x002f0222, 0x000 },
5683 { 0x00000000, 0x0ce00000, 0x3a8 },
5684 { 0x0000001e, 0x002f0222, 0x000 },
5685 { 0x00000000, 0x0ce00000, 0x390 },
5686 { 0x0000a2a4, 0x00204411, 0x000 },
5687 { 0x00000000, 0x00404802, 0x000 },
5688 { 0x08000000, 0x00290a22, 0x000 },
5689 { 0x00000003, 0x40210e20, 0x000 },
5690 { 0x0000000c, 0xc0211220, 0x000 },
5691 { 0x00080000, 0x00281224, 0x000 },
5692 { 0x00000014, 0xc0221620, 0x000 },
5693 { 0x00000000, 0x002914a4, 0x000 },
5694 { 0x0000a2a4, 0x00204411, 0x000 },
5695 { 0x00000000, 0x002948a2, 0x000 },
5696 { 0x0000a1fe, 0x00204411, 0x000 },
5697 { 0x00000000, 0x00404803, 0x000 },
5698 { 0x81000000, 0x00204411, 0x000 },
5699 { 0x00000001, 0x00204811, 0x000 },
5700 { 0x000021f8, 0x00204411, 0x000 },
5701 { 0x00000016, 0x00204811, 0x000 },
5702 { 0x000421f9, 0x00604411, 0x68d },
5703 { 0x00000015, 0x00210230, 0x000 },
5704 { 0x00000000, 0x14e00000, 0x392 },
5705 { 0x0000210e, 0x00204411, 0x000 },
5706 { 0x00000000, 0xc0204800, 0x000 },
5707 { 0x00000000, 0xc0204800, 0x000 },
5708 { 0x0000a2a4, 0x00204411, 0x000 },
5709 { 0x00000000, 0x00404802, 0x000 },
5710 { 0x81000000, 0x00204411, 0x000 },
5711 { 0x00000001, 0x00204811, 0x000 },
5712 { 0x000021f8, 0x00204411, 0x000 },
5713 { 0x00000017, 0x00204811, 0x000 },
5714 { 0x000421f9, 0x00604411, 0x68d },
5715 { 0x00000003, 0x00210230, 0x000 },
5716 { 0x00000000, 0x14e00000, 0x39e },
5717 { 0x00002108, 0x00204411, 0x000 },
5718 { 0x00000000, 0xc0204800, 0x000 },
5719 { 0x00000000, 0xc0204800, 0x000 },
5720 { 0x0000a2a4, 0x00204411, 0x000 },
5721 { 0x00000000, 0x00404802, 0x000 },
5722 { 0x0000a2a4, 0x00204411, 0x000 },
5723 { 0x00000000, 0x00204802, 0x000 },
5724 { 0x80000000, 0x00204411, 0x000 },
5725 { 0x00000000, 0x00204811, 0x000 },
5726 { 0x81000000, 0x00204411, 0x000 },
5727 { 0x00000010, 0x00204811, 0x000 },
5728 { 0x00000000, 0x00200010, 0x000 },
5729 { 0x00000000, 0x14c00000, 0x3ae },
5730 { 0x00000000, 0x00400000, 0x000 },
5731 { 0x00002010, 0x00204411, 0x000 },
5732 { 0x00008000, 0x00204811, 0x000 },
5733 { 0x0001a2a4, 0x00204411, 0x000 },
5734 { 0x00000006, 0x00404811, 0x000 },
5735 { 0x00002010, 0x00204411, 0x000 },
5736 { 0x00008000, 0x00204811, 0x000 },
5737 { 0x0001a2a4, 0x00204411, 0x000 },
5738 { 0x00000016, 0x00604811, 0x36e },
5739 { 0x00000000, 0x00400000, 0x000 },
5740 { 0x00000000, 0xc0200800, 0x000 },
5741 { 0x00000000, 0xc0200c00, 0x000 },
5742 { 0x0000001d, 0x00210223, 0x000 },
5743 { 0x00000000, 0x14e00000, 0x3ce },
5744 { 0x81000000, 0x00204411, 0x000 },
5745 { 0x00000001, 0x00204811, 0x000 },
5746 { 0x000021f8, 0x00204411, 0x000 },
5747 { 0x00000018, 0x00204811, 0x000 },
5748 { 0x000421f9, 0x00604411, 0x68d },
5749 { 0x00000011, 0x00210230, 0x000 },
5750 { 0x00000000, 0x14e00000, 0x3c0 },
5751 { 0x00002100, 0x00204411, 0x000 },
5752 { 0x00000000, 0x00204802, 0x000 },
5753 { 0x00000000, 0x00204803, 0x000 },
5754 { 0xbabecafe, 0x00204811, 0x000 },
5755 { 0xcafebabe, 0x00204811, 0x000 },
5756 { 0x00002010, 0x00204411, 0x000 },
5757 { 0x00008000, 0x00204811, 0x000 },
5758 { 0x0000a2a4, 0x00204411, 0x000 },
5759 { 0x00000004, 0x00404811, 0x000 },
5760 { 0x00002170, 0x00204411, 0x000 },
5761 { 0x00000000, 0x00204802, 0x000 },
5762 { 0x00000000, 0x00204803, 0x000 },
5763 { 0x81000000, 0x00204411, 0x000 },
5764 { 0x0000000a, 0x00204811, 0x000 },
5765 { 0x00000000, 0x00200010, 0x000 },
5766 { 0x00000000, 0x14c00000, 0x3d3 },
5767 { 0x8c000000, 0x00204411, 0x000 },
5768 { 0xcafebabe, 0x00404811, 0x000 },
5769 { 0x81000000, 0x00204411, 0x000 },
5770 { 0x00000001, 0x00204811, 0x000 },
5771 { 0x00003fff, 0x40280a20, 0x000 },
5772 { 0x80000000, 0x40280e20, 0x000 },
5773 { 0x40000000, 0xc0281220, 0x000 },
5774 { 0x00040000, 0x00694622, 0x68d },
5775 { 0x00000000, 0x00201410, 0x000 },
5776 { 0x00000000, 0x002f0223, 0x000 },
5777 { 0x00000000, 0x0cc00000, 0x3e1 },
5778 { 0x00000000, 0xc0401800, 0x3e4 },
5779 { 0x00003fff, 0xc0281a20, 0x000 },
5780 { 0x00040000, 0x00694626, 0x68d },
5781 { 0x00000000, 0x00201810, 0x000 },
5782 { 0x00000000, 0x002f0224, 0x000 },
5783 { 0x00000000, 0x0cc00000, 0x3e7 },
5784 { 0x00000000, 0xc0401c00, 0x3ea },
5785 { 0x00003fff, 0xc0281e20, 0x000 },
5786 { 0x00040000, 0x00694627, 0x68d },
5787 { 0x00000000, 0x00201c10, 0x000 },
5788 { 0x00000000, 0x00204402, 0x000 },
5789 { 0x00000000, 0x002820c5, 0x000 },
5790 { 0x00000000, 0x004948e8, 0x000 },
5791 { 0xa5800000, 0x00200811, 0x000 },
5792 { 0x00002000, 0x00200c11, 0x000 },
5793 { 0x83000000, 0x00604411, 0x412 },
5794 { 0x00000000, 0x00204402, 0x000 },
5795 { 0x00000000, 0xc0204800, 0x000 },
5796 { 0x00000000, 0x40204800, 0x000 },
5797 { 0x0000001f, 0xc0210220, 0x000 },
5798 { 0x00000000, 0x14c00000, 0x3f7 },
5799 { 0x00002010, 0x00204411, 0x000 },
5800 { 0x00008000, 0x00204811, 0x000 },
5801 { 0x0000ffff, 0xc0481220, 0x3ff },
5802 { 0xa7800000, 0x00200811, 0x000 },
5803 { 0x0000a000, 0x00200c11, 0x000 },
5804 { 0x83000000, 0x00604411, 0x412 },
5805 { 0x00000000, 0x00204402, 0x000 },
5806 { 0x00000000, 0xc0204800, 0x000 },
5807 { 0x00000000, 0xc0204800, 0x000 },
5808 { 0x0000ffff, 0xc0281220, 0x000 },
5809 { 0x83000000, 0x00204411, 0x000 },
5810 { 0x00000000, 0x00304883, 0x000 },
5811 { 0x84000000, 0x00204411, 0x000 },
5812 { 0x00000000, 0xc0204800, 0x000 },
5813 { 0x00000000, 0x1d000000, 0x000 },
5814 { 0x83000000, 0x00604411, 0x412 },
5815 { 0x00000000, 0xc0400400, 0x001 },
5816 { 0xa9800000, 0x00200811, 0x000 },
5817 { 0x0000c000, 0x00400c11, 0x3fa },
5818 { 0xab800000, 0x00200811, 0x000 },
5819 { 0x0000f8e0, 0x00400c11, 0x3fa },
5820 { 0xad800000, 0x00200811, 0x000 },
5821 { 0x0000f880, 0x00400c11, 0x3fa },
5822 { 0xb3800000, 0x00200811, 0x000 },
5823 { 0x0000f3fc, 0x00400c11, 0x3fa },
5824 { 0xaf800000, 0x00200811, 0x000 },
5825 { 0x0000e000, 0x00400c11, 0x3fa },
5826 { 0xb1800000, 0x00200811, 0x000 },
5827 { 0x0000f000, 0x00400c11, 0x3fa },
5828 { 0x83000000, 0x00204411, 0x000 },
5829 { 0x00002148, 0x00204811, 0x000 },
5830 { 0x84000000, 0x00204411, 0x000 },
5831 { 0x00000000, 0xc0204800, 0x000 },
5832 { 0x00000000, 0x1d000000, 0x000 },
5833 { 0x00000000, 0x00800000, 0x000 },
5834 { 0x01182000, 0xc0304620, 0x000 },
5835 { 0x00000000, 0xd9004800, 0x000 },
5836 { 0x00000000, 0xc0200400, 0x000 },
5837 { 0x00000000, 0x00a0000a, 0x000 },
5838 { 0x0218a000, 0xc0304620, 0x000 },
5839 { 0x00000000, 0xd9004800, 0x000 },
5840 { 0x00000000, 0xc0200400, 0x000 },
5841 { 0x00000000, 0x00a0000a, 0x000 },
5842 { 0x0318c000, 0xc0304620, 0x000 },
5843 { 0x00000000, 0xd9004800, 0x000 },
5844 { 0x00000000, 0xc0200400, 0x000 },
5845 { 0x00000000, 0x00a0000a, 0x000 },
5846 { 0x0418f8e0, 0xc0304620, 0x000 },
5847 { 0x00000000, 0xd9004800, 0x000 },
5848 { 0x00000000, 0xc0200400, 0x000 },
5849 { 0x00000000, 0x00a0000a, 0x000 },
5850 { 0x0518f880, 0xc0304620, 0x000 },
5851 { 0x00000000, 0xd9004800, 0x000 },
5852 { 0x00000000, 0xc0200400, 0x000 },
5853 { 0x00000000, 0x00a0000a, 0x000 },
5854 { 0x0618e000, 0xc0304620, 0x000 },
5855 { 0x00000000, 0xd9004800, 0x000 },
5856 { 0x00000000, 0xc0200400, 0x000 },
5857 { 0x00000000, 0x00a0000a, 0x000 },
5858 { 0x0718f000, 0xc0304620, 0x000 },
5859 { 0x00000000, 0xd9004800, 0x000 },
5860 { 0x00000000, 0xc0200400, 0x000 },
5861 { 0x00000000, 0x00a0000a, 0x000 },
5862 { 0x0818f3fc, 0xc0304620, 0x000 },
5863 { 0x00000000, 0xd9004800, 0x000 },
5864 { 0x00000000, 0xc0200400, 0x000 },
5865 { 0x00000000, 0x00a0000a, 0x000 },
5866 { 0x00000030, 0x00200a2d, 0x000 },
5867 { 0x00000000, 0xc0290c40, 0x000 },
5868 { 0x00000030, 0x00203623, 0x000 },
5869 { 0x00000000, 0xc0200400, 0x000 },
5870 { 0x00000000, 0x00a0000a, 0x000 },
5871 { 0x86000000, 0x00204411, 0x000 },
5872 { 0x00000000, 0x00404801, 0x000 },
5873 { 0x85000000, 0xc0204411, 0x000 },
5874 { 0x00000000, 0x00404801, 0x000 },
5875 { 0x0000217c, 0x00204411, 0x000 },
5876 { 0x00000018, 0x40210220, 0x000 },
5877 { 0x00000000, 0x14c00000, 0x445 },
5878 { 0x00800000, 0xc0494a20, 0x446 },
5879 { 0x00000000, 0xc0204800, 0x000 },
5880 { 0x00000000, 0xc0204800, 0x000 },
5881 { 0x00000000, 0xc0204800, 0x000 },
5882 { 0x81000000, 0x00204411, 0x000 },
5883 { 0x00000001, 0x00204811, 0x000 },
5884 { 0x00000000, 0xc0200800, 0x000 },
5885 { 0x00000000, 0x17000000, 0x000 },
5886 { 0x0004217f, 0x00604411, 0x68d },
5887 { 0x0000001f, 0x00210230, 0x000 },
5888 { 0x00000000, 0x14c00000, 0x000 },
5889 { 0x00000000, 0x00404c02, 0x44b },
5890 { 0x00000000, 0xc0200c00, 0x000 },
5891 { 0x00000000, 0xc0201000, 0x000 },
5892 { 0x00000000, 0xc0201400, 0x000 },
5893 { 0x00000000, 0xc0201800, 0x000 },
5894 { 0x00000000, 0xc0201c00, 0x000 },
5895 { 0x00007f00, 0x00280a21, 0x000 },
5896 { 0x00004500, 0x002f0222, 0x000 },
5897 { 0x00000000, 0x0ce00000, 0x459 },
5898 { 0x00000000, 0xc0202000, 0x000 },
5899 { 0x00000000, 0x17000000, 0x000 },
5900 { 0x00000010, 0x00280a23, 0x000 },
5901 { 0x00000010, 0x002f0222, 0x000 },
5902 { 0x00000000, 0x0ce00000, 0x461 },
5903 { 0x81000000, 0x00204411, 0x000 },
5904 { 0x00000001, 0x00204811, 0x000 },
5905 { 0x00040000, 0x00694624, 0x68d },
5906 { 0x00000000, 0x00400000, 0x466 },
5907 { 0x81000000, 0x00204411, 0x000 },
5908 { 0x00000000, 0x00204811, 0x000 },
5909 { 0x0000216d, 0x00204411, 0x000 },
5910 { 0x00000000, 0x00204804, 0x000 },
5911 { 0x00000000, 0x00604805, 0x692 },
5912 { 0x00000000, 0x002824f0, 0x000 },
5913 { 0x00000007, 0x00280a23, 0x000 },
5914 { 0x00000001, 0x002f0222, 0x000 },
5915 { 0x00000000, 0x0ae00000, 0x46d },
5916 { 0x00000000, 0x002f00c9, 0x000 },
5917 { 0x00000000, 0x04e00000, 0x486 },
5918 { 0x00000000, 0x00400000, 0x493 },
5919 { 0x00000002, 0x002f0222, 0x000 },
5920 { 0x00000000, 0x0ae00000, 0x472 },
5921 { 0x00000000, 0x002f00c9, 0x000 },
5922 { 0x00000000, 0x02e00000, 0x486 },
5923 { 0x00000000, 0x00400000, 0x493 },
5924 { 0x00000003, 0x002f0222, 0x000 },
5925 { 0x00000000, 0x0ae00000, 0x477 },
5926 { 0x00000000, 0x002f00c9, 0x000 },
5927 { 0x00000000, 0x0ce00000, 0x486 },
5928 { 0x00000000, 0x00400000, 0x493 },
5929 { 0x00000004, 0x002f0222, 0x000 },
5930 { 0x00000000, 0x0ae00000, 0x47c },
5931 { 0x00000000, 0x002f00c9, 0x000 },
5932 { 0x00000000, 0x0ae00000, 0x486 },
5933 { 0x00000000, 0x00400000, 0x493 },
5934 { 0x00000005, 0x002f0222, 0x000 },
5935 { 0x00000000, 0x0ae00000, 0x481 },
5936 { 0x00000000, 0x002f00c9, 0x000 },
5937 { 0x00000000, 0x06e00000, 0x486 },
5938 { 0x00000000, 0x00400000, 0x493 },
5939 { 0x00000006, 0x002f0222, 0x000 },
5940 { 0x00000000, 0x0ae00000, 0x486 },
5941 { 0x00000000, 0x002f00c9, 0x000 },
5942 { 0x00000000, 0x08e00000, 0x486 },
5943 { 0x00000000, 0x00400000, 0x493 },
5944 { 0x00007f00, 0x00280a21, 0x000 },
5945 { 0x00004500, 0x002f0222, 0x000 },
5946 { 0x00000000, 0x0ae00000, 0x000 },
5947 { 0x00000008, 0x00210a23, 0x000 },
5948 { 0x00000000, 0x14c00000, 0x490 },
5949 { 0x00002169, 0x00204411, 0x000 },
5950 { 0x00000000, 0xc0204800, 0x000 },
5951 { 0x00000000, 0xc0204800, 0x000 },
5952 { 0x00000000, 0xc0204800, 0x000 },
5953 { 0xcafebabe, 0x00404811, 0x000 },
5954 { 0x00000000, 0xc0204400, 0x000 },
5955 { 0x00000000, 0xc0200000, 0x000 },
5956 { 0x00000000, 0xc0404800, 0x000 },
5957 { 0x00007f00, 0x00280a21, 0x000 },
5958 { 0x00004500, 0x002f0222, 0x000 },
5959 { 0x00000000, 0x0ae00000, 0x499 },
5960 { 0x00000000, 0xc0200000, 0x000 },
5961 { 0x00000000, 0xc0200000, 0x000 },
5962 { 0x00000000, 0xc0400000, 0x000 },
5963 { 0x00000000, 0x00404c08, 0x459 },
5964 { 0x00000000, 0xc0200800, 0x000 },
5965 { 0x00000010, 0x40210e20, 0x000 },
5966 { 0x00000011, 0x40211220, 0x000 },
5967 { 0x00000012, 0x40211620, 0x000 },
5968 { 0x00002169, 0x00204411, 0x000 },
5969 { 0x00000000, 0x00204802, 0x000 },
5970 { 0x00000000, 0x00210225, 0x000 },
5971 { 0x00000000, 0x14e00000, 0x4a3 },
5972 { 0x00040000, 0xc0494a20, 0x4a4 },
5973 { 0xfffbffff, 0xc0284a20, 0x000 },
5974 { 0x00000000, 0x00210223, 0x000 },
5975 { 0x00000000, 0x14e00000, 0x4b0 },
5976 { 0x00000000, 0xc0204800, 0x000 },
5977 { 0x00000000, 0xc0204800, 0x000 },
5978 { 0x00000000, 0x00210224, 0x000 },
5979 { 0x00000000, 0x14c00000, 0x000 },
5980 { 0x81000000, 0x00204411, 0x000 },
5981 { 0x0000000c, 0x00204811, 0x000 },
5982 { 0x00000000, 0x00200010, 0x000 },
5983 { 0x00000000, 0x14c00000, 0x4ac },
5984 { 0xa0000000, 0x00204411, 0x000 },
5985 { 0xcafebabe, 0x00404811, 0x000 },
5986 { 0x81000000, 0x00204411, 0x000 },
5987 { 0x00000004, 0x00204811, 0x000 },
5988 { 0x0000216b, 0x00204411, 0x000 },
5989 { 0x00000000, 0xc0204810, 0x000 },
5990 { 0x81000000, 0x00204411, 0x000 },
5991 { 0x00000005, 0x00204811, 0x000 },
5992 { 0x0000216c, 0x00204411, 0x000 },
5993 { 0x00000000, 0xc0204810, 0x000 },
5994 { 0x00000000, 0x002f0224, 0x000 },
5995 { 0x00000000, 0x0ce00000, 0x000 },
5996 { 0x00000000, 0x00400000, 0x4aa },
5997 { 0x00000000, 0xc0210a20, 0x000 },
5998 { 0x00000000, 0x14c00000, 0x4c3 },
5999 { 0x81000000, 0x00204411, 0x000 },
6000 { 0x00000000, 0x00204811, 0x000 },
6001 { 0x0000216d, 0x00204411, 0x000 },
6002 { 0x00000000, 0xc0204800, 0x000 },
6003 { 0x00000000, 0xc0604800, 0x692 },
6004 { 0x00000000, 0x00400000, 0x4c7 },
6005 { 0x81000000, 0x00204411, 0x000 },
6006 { 0x00000001, 0x00204811, 0x000 },
6007 { 0x00040000, 0xc0294620, 0x000 },
6008 { 0x00000000, 0xc0600000, 0x68d },
6009 { 0x00000001, 0x00210222, 0x000 },
6010 { 0x00000000, 0x14c00000, 0x4ce },
6011 { 0x00002169, 0x00204411, 0x000 },
6012 { 0x00000000, 0xc0204800, 0x000 },
6013 { 0x00000000, 0xc0204800, 0x000 },
6014 { 0x00000000, 0x00204810, 0x000 },
6015 { 0xcafebabe, 0x00404811, 0x000 },
6016 { 0x00000000, 0xc0204400, 0x000 },
6017 { 0x00000000, 0xc0404810, 0x000 },
6018 { 0x81000000, 0x00204411, 0x000 },
6019 { 0x00000001, 0x00204811, 0x000 },
6020 { 0x000021f8, 0x00204411, 0x000 },
6021 { 0x0000000e, 0x00204811, 0x000 },
6022 { 0x000421f9, 0x00604411, 0x68d },
6023 { 0x00000000, 0x00210230, 0x000 },
6024 { 0x00000000, 0x14c00000, 0x4d0 },
6025 { 0x00002180, 0x00204411, 0x000 },
6026 { 0x00000000, 0xc0204800, 0x000 },
6027 { 0x00000000, 0xc0200000, 0x000 },
6028 { 0x00000000, 0xc0204800, 0x000 },
6029 { 0x00000000, 0xc0200000, 0x000 },
6030 { 0x00000000, 0xc0404800, 0x000 },
6031 { 0x00000003, 0x00333e2f, 0x000 },
6032 { 0x00000001, 0x00210221, 0x000 },
6033 { 0x00000000, 0x14e00000, 0x500 },
6034 { 0x0000002c, 0x00200a2d, 0x000 },
6035 { 0x00040000, 0x18e00c11, 0x4ef },
6036 { 0x00000001, 0x00333e2f, 0x000 },
6037 { 0x00002169, 0x00204411, 0x000 },
6038 { 0x00000000, 0x00204802, 0x000 },
6039 { 0x00000000, 0x00204803, 0x000 },
6040 { 0x00000008, 0x00300a22, 0x000 },
6041 { 0x00000000, 0xc0204800, 0x000 },
6042 { 0x00000000, 0xc0204800, 0x000 },
6043 { 0x00002169, 0x00204411, 0x000 },
6044 { 0x00000000, 0x00204802, 0x000 },
6045 { 0x00000000, 0x00204803, 0x000 },
6046 { 0x00000008, 0x00300a22, 0x000 },
6047 { 0x00000000, 0xc0204800, 0x000 },
6048 { 0x00000000, 0xd8c04800, 0x4e3 },
6049 { 0x00002169, 0x00204411, 0x000 },
6050 { 0x00000000, 0x00204802, 0x000 },
6051 { 0x00000000, 0x00204803, 0x000 },
6052 { 0x00000008, 0x00300a22, 0x000 },
6053 { 0x00000000, 0xc0204800, 0x000 },
6054 { 0x00000000, 0xc0204800, 0x000 },
6055 { 0x0000002d, 0x0020122d, 0x000 },
6056 { 0x00000000, 0x00290c83, 0x000 },
6057 { 0x00002169, 0x00204411, 0x000 },
6058 { 0x00000000, 0x00204802, 0x000 },
6059 { 0x00000000, 0x00204803, 0x000 },
6060 { 0x00000008, 0x00300a22, 0x000 },
6061 { 0x00000000, 0xc0204800, 0x000 },
6062 { 0x00000000, 0xc0204800, 0x000 },
6063 { 0x00000011, 0x00210224, 0x000 },
6064 { 0x00000000, 0x14c00000, 0x000 },
6065 { 0x00000000, 0x00400000, 0x4aa },
6066 { 0x0000002c, 0xc0203620, 0x000 },
6067 { 0x0000002d, 0xc0403620, 0x000 },
6068 { 0x0000000f, 0x00210221, 0x000 },
6069 { 0x00000000, 0x14c00000, 0x505 },
6070 { 0x00000000, 0x00600000, 0x00b },
6071 { 0x00000000, 0xd9000000, 0x000 },
6072 { 0x00000000, 0xc0400400, 0x001 },
6073 { 0xb5000000, 0x00204411, 0x000 },
6074 { 0x00002000, 0x00204811, 0x000 },
6075 { 0xb6000000, 0x00204411, 0x000 },
6076 { 0x0000a000, 0x00204811, 0x000 },
6077 { 0xb7000000, 0x00204411, 0x000 },
6078 { 0x0000c000, 0x00204811, 0x000 },
6079 { 0xb8000000, 0x00204411, 0x000 },
6080 { 0x0000f8e0, 0x00204811, 0x000 },
6081 { 0xb9000000, 0x00204411, 0x000 },
6082 { 0x0000f880, 0x00204811, 0x000 },
6083 { 0xba000000, 0x00204411, 0x000 },
6084 { 0x0000e000, 0x00204811, 0x000 },
6085 { 0xbb000000, 0x00204411, 0x000 },
6086 { 0x0000f000, 0x00204811, 0x000 },
6087 { 0xbc000000, 0x00204411, 0x000 },
6088 { 0x0000f3fc, 0x00204811, 0x000 },
6089 { 0x81000000, 0x00204411, 0x000 },
6090 { 0x00000002, 0x00204811, 0x000 },
6091 { 0x000000ff, 0x00280e30, 0x000 },
6092 { 0x00000000, 0x002f0223, 0x000 },
6093 { 0x00000000, 0x0cc00000, 0x519 },
6094 { 0x00000000, 0xc0200800, 0x000 },
6095 { 0x00000000, 0x14c00000, 0x52e },
6096 { 0x00000000, 0x00200c11, 0x000 },
6097 { 0x0000001c, 0x00203623, 0x000 },
6098 { 0x0000002b, 0x00203623, 0x000 },
6099 { 0x00000029, 0x00203623, 0x000 },
6100 { 0x00000028, 0x00203623, 0x000 },
6101 { 0x00000017, 0x00203623, 0x000 },
6102 { 0x00000025, 0x00203623, 0x000 },
6103 { 0x00000026, 0x00203623, 0x000 },
6104 { 0x00000015, 0x00203623, 0x000 },
6105 { 0x00000016, 0x00203623, 0x000 },
6106 { 0xffffe000, 0x00200c11, 0x000 },
6107 { 0x00000021, 0x00203623, 0x000 },
6108 { 0x00000022, 0x00203623, 0x000 },
6109 { 0x00001fff, 0x00200c11, 0x000 },
6110 { 0x00000023, 0x00203623, 0x000 },
6111 { 0x00000024, 0x00203623, 0x000 },
6112 { 0xf1ffffff, 0x00283a2e, 0x000 },
6113 { 0x0000001a, 0xc0220e20, 0x000 },
6114 { 0x00000000, 0x0029386e, 0x000 },
6115 { 0x81000000, 0x00204411, 0x000 },
6116 { 0x00000006, 0x00204811, 0x000 },
6117 { 0x0000002a, 0x40203620, 0x000 },
6118 { 0x87000000, 0x00204411, 0x000 },
6119 { 0x00000000, 0xc0204800, 0x000 },
6120 { 0x0000a1f4, 0x00204411, 0x000 },
6121 { 0x00000000, 0x00204810, 0x000 },
6122 { 0x00000000, 0x00200c11, 0x000 },
6123 { 0x00000030, 0x00203623, 0x000 },
6124 { 0x9d000000, 0x00204411, 0x000 },
6125 { 0x0000001f, 0x40214a20, 0x000 },
6126 { 0x96000000, 0x00204411, 0x000 },
6127 { 0x00000000, 0xc0204800, 0x000 },
6128 { 0x00000000, 0xc0200c00, 0x000 },
6129 { 0x00000000, 0xc0201000, 0x000 },
6130 { 0x0000001f, 0x00211624, 0x000 },
6131 { 0x00000000, 0x14c00000, 0x000 },
6132 { 0x0000001d, 0x00203623, 0x000 },
6133 { 0x00000003, 0x00281e23, 0x000 },
6134 { 0x00000008, 0x00222223, 0x000 },
6135 { 0xfffff000, 0x00282228, 0x000 },
6136 { 0x00000000, 0x002920e8, 0x000 },
6137 { 0x0000001f, 0x00203628, 0x000 },
6138 { 0x00000018, 0x00211e23, 0x000 },
6139 { 0x00000020, 0x00203627, 0x000 },
6140 { 0x00000002, 0x00221624, 0x000 },
6141 { 0x00000000, 0x003014a8, 0x000 },
6142 { 0x0000001e, 0x00203625, 0x000 },
6143 { 0x00000003, 0x00211a24, 0x000 },
6144 { 0x10000000, 0x00281a26, 0x000 },
6145 { 0xefffffff, 0x00283a2e, 0x000 },
6146 { 0x00000000, 0x004938ce, 0x67b },
6147 { 0x00000001, 0x40280a20, 0x000 },
6148 { 0x00000006, 0x40280e20, 0x000 },
6149 { 0x00000300, 0xc0281220, 0x000 },
6150 { 0x00000008, 0x00211224, 0x000 },
6151 { 0x00000000, 0xc0201620, 0x000 },
6152 { 0x00000000, 0xc0201a20, 0x000 },
6153 { 0x00000000, 0x00210222, 0x000 },
6154 { 0x00000000, 0x14c00000, 0x566 },
6155 { 0x81000000, 0x00204411, 0x000 },
6156 { 0x00000001, 0x00204811, 0x000 },
6157 { 0x00002258, 0x00300a24, 0x000 },
6158 { 0x00040000, 0x00694622, 0x68d },
6159 { 0x00002169, 0x00204411, 0x000 },
6160 { 0x00000000, 0x00204805, 0x000 },
6161 { 0x00020000, 0x00294a26, 0x000 },
6162 { 0x00000000, 0x00204810, 0x000 },
6163 { 0xcafebabe, 0x00204811, 0x000 },
6164 { 0x00000002, 0x002f0223, 0x000 },
6165 { 0x00000000, 0x0cc00000, 0x56e },
6166 { 0x00000000, 0xc0201c10, 0x000 },
6167 { 0x00000000, 0xc0400000, 0x57c },
6168 { 0x00000002, 0x002f0223, 0x000 },
6169 { 0x00000000, 0x0cc00000, 0x56e },
6170 { 0x81000000, 0x00204411, 0x000 },
6171 { 0x00000001, 0x00204811, 0x000 },
6172 { 0x00002258, 0x00300a24, 0x000 },
6173 { 0x00040000, 0x00694622, 0x68d },
6174 { 0x00000000, 0xc0201c10, 0x000 },
6175 { 0x00000000, 0xc0400000, 0x57c },
6176 { 0x00000000, 0x002f0223, 0x000 },
6177 { 0x00000000, 0x0cc00000, 0x572 },
6178 { 0x00000000, 0xc0201c00, 0x000 },
6179 { 0x00000000, 0xc0400000, 0x57c },
6180 { 0x00000004, 0x002f0223, 0x000 },
6181 { 0x00000000, 0x0cc00000, 0x57a },
6182 { 0x81000000, 0x00204411, 0x000 },
6183 { 0x00000000, 0x00204811, 0x000 },
6184 { 0x0000216d, 0x00204411, 0x000 },
6185 { 0x00000000, 0xc0204800, 0x000 },
6186 { 0x00000000, 0xc0604800, 0x692 },
6187 { 0x00000000, 0x00401c10, 0x57c },
6188 { 0x00000000, 0xc0200000, 0x000 },
6189 { 0x00000000, 0xc0400000, 0x000 },
6190 { 0x00000000, 0x0ee00000, 0x57e },
6191 { 0x00000000, 0x00600000, 0x5c9 },
6192 { 0x00000000, 0x002f0224, 0x000 },
6193 { 0x00000000, 0x0cc00000, 0x58f },
6194 { 0x0000a2b7, 0x00204411, 0x000 },
6195 { 0x00000000, 0x00204807, 0x000 },
6196 { 0x81000000, 0x00204411, 0x000 },
6197 { 0x00000001, 0x00204811, 0x000 },
6198 { 0x0004a2b6, 0x00604411, 0x68d },
6199 { 0x0000001a, 0x00212230, 0x000 },
6200 { 0x00000006, 0x00222630, 0x000 },
6201 { 0x00042004, 0x00604411, 0x68d },
6202 { 0x0000a2c4, 0x00204411, 0x000 },
6203 { 0x00000000, 0x003048e9, 0x000 },
6204 { 0x00000000, 0x00e00000, 0x58d },
6205 { 0x0000a2d1, 0x00204411, 0x000 },
6206 { 0x00000000, 0x00404808, 0x000 },
6207 { 0x0000a2d1, 0x00204411, 0x000 },
6208 { 0x00000001, 0x00504a28, 0x000 },
6209 { 0x00000001, 0x002f0224, 0x000 },
6210 { 0x00000000, 0x0cc00000, 0x5a0 },
6211 { 0x0000a2bb, 0x00204411, 0x000 },
6212 { 0x00000000, 0x00204807, 0x000 },
6213 { 0x81000000, 0x00204411, 0x000 },
6214 { 0x00000001, 0x00204811, 0x000 },
6215 { 0x0004a2ba, 0x00604411, 0x68d },
6216 { 0x0000001a, 0x00212230, 0x000 },
6217 { 0x00000006, 0x00222630, 0x000 },
6218 { 0x00042004, 0x00604411, 0x68d },
6219 { 0x0000a2c5, 0x00204411, 0x000 },
6220 { 0x00000000, 0x003048e9, 0x000 },
6221 { 0x00000000, 0x00e00000, 0x59e },
6222 { 0x0000a2d2, 0x00204411, 0x000 },
6223 { 0x00000000, 0x00404808, 0x000 },
6224 { 0x0000a2d2, 0x00204411, 0x000 },
6225 { 0x00000001, 0x00504a28, 0x000 },
6226 { 0x00000002, 0x002f0224, 0x000 },
6227 { 0x00000000, 0x0cc00000, 0x5b1 },
6228 { 0x0000a2bf, 0x00204411, 0x000 },
6229 { 0x00000000, 0x00204807, 0x000 },
6230 { 0x81000000, 0x00204411, 0x000 },
6231 { 0x00000001, 0x00204811, 0x000 },
6232 { 0x0004a2be, 0x00604411, 0x68d },
6233 { 0x0000001a, 0x00212230, 0x000 },
6234 { 0x00000006, 0x00222630, 0x000 },
6235 { 0x00042004, 0x00604411, 0x68d },
6236 { 0x0000a2c6, 0x00204411, 0x000 },
6237 { 0x00000000, 0x003048e9, 0x000 },
6238 { 0x00000000, 0x00e00000, 0x5af },
6239 { 0x0000a2d3, 0x00204411, 0x000 },
6240 { 0x00000000, 0x00404808, 0x000 },
6241 { 0x0000a2d3, 0x00204411, 0x000 },
6242 { 0x00000001, 0x00504a28, 0x000 },
6243 { 0x0000a2c3, 0x00204411, 0x000 },
6244 { 0x00000000, 0x00204807, 0x000 },
6245 { 0x81000000, 0x00204411, 0x000 },
6246 { 0x00000001, 0x00204811, 0x000 },
6247 { 0x0004a2c2, 0x00604411, 0x68d },
6248 { 0x0000001a, 0x00212230, 0x000 },
6249 { 0x00000006, 0x00222630, 0x000 },
6250 { 0x00042004, 0x00604411, 0x68d },
6251 { 0x0000a2c7, 0x00204411, 0x000 },
6252 { 0x00000000, 0x003048e9, 0x000 },
6253 { 0x00000000, 0x00e00000, 0x5be },
6254 { 0x0000a2d4, 0x00204411, 0x000 },
6255 { 0x00000000, 0x00404808, 0x000 },
6256 { 0x0000a2d4, 0x00204411, 0x000 },
6257 { 0x00000001, 0x00504a28, 0x000 },
6258 { 0x85000000, 0x00204411, 0x000 },
6259 { 0x00000000, 0x00204801, 0x000 },
6260 { 0x0000304a, 0x00204411, 0x000 },
6261 { 0x01000000, 0x00204811, 0x000 },
6262 { 0x00000000, 0x00400000, 0x5c4 },
6263 { 0xa4000000, 0xc0204411, 0x000 },
6264 { 0x00000000, 0xc0404800, 0x000 },
6265 { 0x00000000, 0xc0600000, 0x5c9 },
6266 { 0x00000000, 0xc0400400, 0x001 },
6267 { 0x0000002c, 0x00203621, 0x000 },
6268 { 0x81000000, 0x00204411, 0x000 },
6269 { 0x00000006, 0x00204811, 0x000 },
6270 { 0x00000000, 0x002f0230, 0x000 },
6271 { 0x00000000, 0x0cc00000, 0x5d0 },
6272 { 0x00000000, 0x00200411, 0x000 },
6273 { 0x00000030, 0x00403621, 0x5e3 },
6274 { 0x00000030, 0x0020062d, 0x000 },
6275 { 0x00007e00, 0x00280621, 0x000 },
6276 { 0x00000000, 0x002f0221, 0x000 },
6277 { 0x00000000, 0x0ce00000, 0x5e3 },
6278 { 0x81000000, 0x00204411, 0x000 },
6279 { 0x00000001, 0x00204811, 0x000 },
6280 { 0x0004a092, 0x00604411, 0x68d },
6281 { 0x00000031, 0x00203630, 0x000 },
6282 { 0x0004a093, 0x00604411, 0x68d },
6283 { 0x00000032, 0x00203630, 0x000 },
6284 { 0x0004a2b6, 0x00604411, 0x68d },
6285 { 0x00000033, 0x00203630, 0x000 },
6286 { 0x0004a2ba, 0x00604411, 0x68d },
6287 { 0x00000034, 0x00203630, 0x000 },
6288 { 0x0004a2be, 0x00604411, 0x68d },
6289 { 0x00000035, 0x00203630, 0x000 },
6290 { 0x0004a2c2, 0x00604411, 0x68d },
6291 { 0x00000036, 0x00203630, 0x000 },
6292 { 0x00042004, 0x00604411, 0x68d },
6293 { 0x0001a2a4, 0x00204411, 0x000 },
6294 { 0x0000003f, 0x00204811, 0x000 },
6295 { 0x0000003f, 0x00204811, 0x000 },
6296 { 0x0000003f, 0x00204811, 0x000 },
6297 { 0x0000003f, 0x00204811, 0x000 },
6298 { 0x00000005, 0x00204811, 0x000 },
6299 { 0x0000a1f4, 0x00204411, 0x000 },
6300 { 0x00000000, 0x00204811, 0x000 },
6301 { 0x88000000, 0x00204411, 0x000 },
6302 { 0x00000001, 0x00204811, 0x000 },
6303 { 0x81000000, 0x00204411, 0x000 },
6304 { 0x00000006, 0x00204811, 0x000 },
6305 { 0x00000001, 0x002f0230, 0x000 },
6306 { 0x00000000, 0x0ce00000, 0x62c },
6307 { 0x00000030, 0x0020062d, 0x000 },
6308 { 0x00000000, 0x002f0221, 0x000 },
6309 { 0x00000000, 0x0ce00000, 0x62c },
6310 { 0x81000000, 0x00204411, 0x000 },
6311 { 0x00000001, 0x00204811, 0x000 },
6312 { 0x00007e00, 0x00280621, 0x000 },
6313 { 0x00000000, 0x002f0221, 0x000 },
6314 { 0x00000000, 0x0ce00000, 0x605 },
6315 { 0x0000a092, 0x00204411, 0x000 },
6316 { 0x00000031, 0x00204a2d, 0x000 },
6317 { 0x0000a093, 0x00204411, 0x000 },
6318 { 0x00000032, 0x00204a2d, 0x000 },
6319 { 0x0000a2b6, 0x00204411, 0x000 },
6320 { 0x00000033, 0x00204a2d, 0x000 },
6321 { 0x0000a2ba, 0x00204411, 0x000 },
6322 { 0x00000034, 0x00204a2d, 0x000 },
6323 { 0x0000a2be, 0x00204411, 0x000 },
6324 { 0x00000035, 0x00204a2d, 0x000 },
6325 { 0x0000a2c2, 0x00204411, 0x000 },
6326 { 0x00000036, 0x00204a2d, 0x000 },
6327 { 0x00000030, 0x0020062d, 0x000 },
6328 { 0x000001ff, 0x00280621, 0x000 },
6329 { 0x00000000, 0x002f0221, 0x000 },
6330 { 0x00000000, 0x0ce00000, 0x62b },
6331 { 0x00000000, 0x00210221, 0x000 },
6332 { 0x00000000, 0x14c00000, 0x60e },
6333 { 0x0004a003, 0x00604411, 0x68d },
6334 { 0x0000a003, 0x00204411, 0x000 },
6335 { 0x00000000, 0x00204810, 0x000 },
6336 { 0x00000001, 0x00210621, 0x000 },
6337 { 0x00000000, 0x14c00000, 0x613 },
6338 { 0x0004a010, 0x00604411, 0x68d },
6339 { 0x0000a010, 0x00204411, 0x000 },
6340 { 0x00000000, 0x00204810, 0x000 },
6341 { 0x00000001, 0x00210621, 0x000 },
6342 { 0x00000000, 0x002f0221, 0x000 },
6343 { 0x00000000, 0x0ce00000, 0x62b },
6344 { 0x0004a011, 0x00604411, 0x68d },
6345 { 0x0000a011, 0x00204411, 0x000 },
6346 { 0x00000000, 0x00204810, 0x000 },
6347 { 0x0004a012, 0x00604411, 0x68d },
6348 { 0x0000a012, 0x00204411, 0x000 },
6349 { 0x00000000, 0x00204810, 0x000 },
6350 { 0x0004a013, 0x00604411, 0x68d },
6351 { 0x0000a013, 0x00204411, 0x000 },
6352 { 0x00000000, 0x00204810, 0x000 },
6353 { 0x0004a014, 0x00604411, 0x68d },
6354 { 0x0000a014, 0x00204411, 0x000 },
6355 { 0x00000000, 0x00204810, 0x000 },
6356 { 0x0004a015, 0x00604411, 0x68d },
6357 { 0x0000a015, 0x00204411, 0x000 },
6358 { 0x00000000, 0x00204810, 0x000 },
6359 { 0x0004a016, 0x00604411, 0x68d },
6360 { 0x0000a016, 0x00204411, 0x000 },
6361 { 0x00000000, 0x00204810, 0x000 },
6362 { 0x0004a017, 0x00604411, 0x68d },
6363 { 0x0000a017, 0x00204411, 0x000 },
6364 { 0x00000000, 0x00204810, 0x000 },
6365 { 0x00042004, 0x00604411, 0x68d },
6366 { 0x0000002c, 0x0080062d, 0x000 },
6367 { 0xff000000, 0x00204411, 0x000 },
6368 { 0x00000000, 0x00204811, 0x000 },
6369 { 0x00000001, 0x00204811, 0x000 },
6370 { 0x00000002, 0x00804811, 0x000 },
6371 { 0x00000000, 0x0ee00000, 0x63d },
6372 { 0x00000030, 0x0020062d, 0x000 },
6373 { 0x00000002, 0x00280621, 0x000 },
6374 { 0x00000000, 0x002f0221, 0x000 },
6375 { 0x00000000, 0x0ce00000, 0x63b },
6376 { 0x81000000, 0x00204411, 0x000 },
6377 { 0x00000001, 0x00204811, 0x000 },
6378 { 0x00042004, 0x00604411, 0x68d },
6379 { 0x00001000, 0x00200811, 0x000 },
6380 { 0x0000002b, 0x00203622, 0x000 },
6381 { 0x00000000, 0x00600000, 0x641 },
6382 { 0x00000000, 0x00600000, 0x5c9 },
6383 { 0x98000000, 0x00204411, 0x000 },
6384 { 0x00000000, 0x00804811, 0x000 },
6385 { 0x00000000, 0xc0600000, 0x641 },
6386 { 0x00000000, 0xc0400400, 0x001 },
6387 { 0x0000a2a4, 0x00204411, 0x000 },
6388 { 0x00000022, 0x00204811, 0x000 },
6389 { 0x89000000, 0x00204411, 0x000 },
6390 { 0x00000001, 0x00404811, 0x62d },
6391 { 0x97000000, 0x00204411, 0x000 },
6392 { 0x00000000, 0x00204811, 0x000 },
6393 { 0x8a000000, 0x00204411, 0x000 },
6394 { 0x00000000, 0x00404811, 0x62d },
6395 { 0x00000000, 0x00600000, 0x65c },
6396 { 0x00002010, 0x00204411, 0x000 },
6397 { 0x00008000, 0x00204811, 0x000 },
6398 { 0x0001a2a4, 0xc0204411, 0x000 },
6399 { 0x00000016, 0x00604811, 0x36e },
6400 { 0x00002010, 0x00204411, 0x000 },
6401 { 0x00010000, 0x00204811, 0x000 },
6402 { 0x81000000, 0x00204411, 0x000 },
6403 { 0x00000001, 0x00204811, 0x000 },
6404 { 0x0000217c, 0x00204411, 0x000 },
6405 { 0x09800000, 0x00204811, 0x000 },
6406 { 0xffffffff, 0x00204811, 0x000 },
6407 { 0x00000000, 0x00204811, 0x000 },
6408 { 0x00000000, 0x17000000, 0x000 },
6409 { 0x0004217f, 0x00604411, 0x68d },
6410 { 0x0000001f, 0x00210230, 0x000 },
6411 { 0x00000000, 0x14c00000, 0x000 },
6412 { 0x00000004, 0x00404c11, 0x656 },
6413 { 0x00000000, 0x00400000, 0x000 },
6414 { 0x00000017, 0x00201e2d, 0x000 },
6415 { 0x00000004, 0x00291e27, 0x000 },
6416 { 0x00000017, 0x00803627, 0x000 },
6417 { 0x00000017, 0x00201e2d, 0x000 },
6418 { 0xfffffffb, 0x00281e27, 0x000 },
6419 { 0x00000017, 0x00803627, 0x000 },
6420 { 0x00000017, 0x00201e2d, 0x000 },
6421 { 0x00000008, 0x00291e27, 0x000 },
6422 { 0x00000017, 0x00803627, 0x000 },
6423 { 0x00000017, 0x00201e2d, 0x000 },
6424 { 0xfffffff7, 0x00281e27, 0x000 },
6425 { 0x00000017, 0x00803627, 0x000 },
6426 { 0x00002010, 0x00204411, 0x000 },
6427 { 0x00008000, 0x00204811, 0x000 },
6428 { 0x0001a2a4, 0x00204411, 0x000 },
6429 { 0x00000016, 0x00604811, 0x36e },
6430 { 0x00002010, 0x00204411, 0x000 },
6431 { 0x00010000, 0x00204811, 0x000 },
6432 { 0x0000217c, 0x00204411, 0x000 },
6433 { 0x01800000, 0x00204811, 0x000 },
6434 { 0xffffffff, 0x00204811, 0x000 },
6435 { 0x00000000, 0x00204811, 0x000 },
6436 { 0x00000000, 0x17000000, 0x000 },
6437 { 0x81000000, 0x00204411, 0x000 },
6438 { 0x00000001, 0x00204811, 0x000 },
6439 { 0x0004217f, 0x00604411, 0x68d },
6440 { 0x0000001f, 0x00210230, 0x000 },
6441 { 0x00000000, 0x14c00000, 0x68c },
6442 { 0x00000010, 0x00404c11, 0x672 },
6443 { 0x00000000, 0xc0200400, 0x000 },
6444 { 0x00000000, 0x38c00000, 0x000 },
6445 { 0x0000001d, 0x00200a2d, 0x000 },
6446 { 0x0000001e, 0x00200e2d, 0x000 },
6447 { 0x0000001f, 0x0020122d, 0x000 },
6448 { 0x00000020, 0x0020162d, 0x000 },
6449 { 0x00002169, 0x00204411, 0x000 },
6450 { 0x00000000, 0x00204804, 0x000 },
6451 { 0x00000000, 0x00204805, 0x000 },
6452 { 0x00000000, 0x00204801, 0x000 },
6453 { 0xcafebabe, 0x00204811, 0x000 },
6454 { 0x00000004, 0x00301224, 0x000 },
6455 { 0x00000000, 0x002f0064, 0x000 },
6456 { 0x00000000, 0x0cc00000, 0x68b },
6457 { 0x00000003, 0x00281a22, 0x000 },
6458 { 0x00000008, 0x00221222, 0x000 },
6459 { 0xfffff000, 0x00281224, 0x000 },
6460 { 0x00000000, 0x002910c4, 0x000 },
6461 { 0x0000001f, 0x00403624, 0x000 },
6462 { 0x00000000, 0x00800000, 0x000 },
6463 { 0x00000000, 0x1ac00000, 0x68d },
6464 { 0x9f000000, 0x00204411, 0x000 },
6465 { 0xcafebabe, 0x00204811, 0x000 },
6466 { 0x00000000, 0x1ae00000, 0x690 },
6467 { 0x00000000, 0x00800000, 0x000 },
6468 { 0x00000000, 0x1ac00000, 0x692 },
6469 { 0x9e000000, 0x00204411, 0x000 },
6470 { 0xcafebabe, 0x00204811, 0x000 },
6471 { 0x00000000, 0x1ae00000, 0x695 },
6472 { 0x00000000, 0x00800000, 0x000 },
6473 { 0x00000000, 0x00600000, 0x00b },
6474 { 0x00001000, 0x00600411, 0x315 },
6475 { 0x00000000, 0x00200411, 0x000 },
6476 { 0x00000000, 0x00600811, 0x1b2 },
6477 { 0x0000225c, 0x00204411, 0x000 },
6478 { 0x00000003, 0x00204811, 0x000 },
6479 { 0x00002256, 0x00204411, 0x000 },
6480 { 0x0000001b, 0x00204811, 0x000 },
6481 { 0x0000a1fc, 0x00204411, 0x000 },
6482 { 0x00000001, 0x00204811, 0x000 },
6483 { 0x0001a1fd, 0xc0204411, 0x000 },
6484 { 0x00000021, 0x00201e2d, 0x000 },
6485 { 0x00000010, 0x00221e27, 0x000 },
6486 { 0x00000024, 0x0020222d, 0x000 },
6487 { 0x0000ffff, 0x00282228, 0x000 },
6488 { 0x00000000, 0x00294907, 0x000 },
6489 { 0x00000000, 0x00204811, 0x000 },
6490 { 0x00000022, 0x0020222d, 0x000 },
6491 { 0x0000ffff, 0x00282228, 0x000 },
6492 { 0x00000000, 0x00294907, 0x000 },
6493 { 0x00000000, 0x00204811, 0x000 },
6494 { 0x00000023, 0x00201e2d, 0x000 },
6495 { 0x00000010, 0x00221e27, 0x000 },
6496 { 0x00000000, 0x00294907, 0x000 },
6497 { 0x00000000, 0x00404811, 0x000 },
6498 { 0x00000000, 0x00000000, 0x000 },
6499 { 0x00000000, 0x00000000, 0x000 },
6500 { 0x00000000, 0x00000000, 0x000 },
6501 { 0x00000000, 0x00000000, 0x000 },
6502 { 0x00000000, 0x00000000, 0x000 },
6503 { 0x00000000, 0x00000000, 0x000 },
6504 { 0x00000000, 0x00000000, 0x000 },
6505 { 0x00000000, 0x00000000, 0x000 },
6506 { 0x00000000, 0x00000000, 0x000 },
6507 { 0x00000000, 0x00000000, 0x000 },
6508 { 0x00000000, 0x00000000, 0x000 },
6509 { 0x00000000, 0x00000000, 0x000 },
6510 { 0x00000000, 0x00000000, 0x000 },
6511 { 0x00000000, 0x00000000, 0x000 },
6512 { 0x00000000, 0x00000000, 0x000 },
6513 { 0x00000000, 0x00000000, 0x000 },
6514 { 0x00000000, 0x00000000, 0x000 },
6515 { 0x00000000, 0x00000000, 0x000 },
6516 { 0x00000000, 0x00000000, 0x000 },
6517 { 0x00000000, 0x00000000, 0x000 },
6518 { 0x00000000, 0x00000000, 0x000 },
6519 { 0x00000000, 0x00000000, 0x000 },
6520 { 0x00000000, 0x00000000, 0x000 },
6521 { 0x00000000, 0x00000000, 0x000 },
6522 { 0x00000000, 0x00000000, 0x000 },
6523 { 0x00000000, 0x00000000, 0x000 },
6524 { 0x00000000, 0x00000000, 0x000 },
6525 { 0x00000000, 0x00000000, 0x000 },
6526 { 0x00000000, 0x00000000, 0x000 },
6527 { 0x00000000, 0x00000000, 0x000 },
6528 { 0x00000000, 0x00000000, 0x000 },
6529 { 0x00000000, 0x00000000, 0x000 },
6530 { 0x00000000, 0x00000000, 0x000 },
6531 { 0x00000000, 0x00000000, 0x000 },
6532 { 0x00000000, 0x00000000, 0x000 },
6533 { 0x00000000, 0x00000000, 0x000 },
6534 { 0x00000000, 0x00000000, 0x000 },
6535 { 0x00000000, 0x00000000, 0x000 },
6536 { 0x00000000, 0x00000000, 0x000 },
6537 { 0x00000000, 0x00000000, 0x000 },
6538 { 0x00000000, 0x00000000, 0x000 },
6539 { 0x00000000, 0x00000000, 0x000 },
6540 { 0x00000000, 0x00000000, 0x000 },
6541 { 0x00000000, 0x00000000, 0x000 },
6542 { 0x00000000, 0x00000000, 0x000 },
6543 { 0x00000000, 0x00000000, 0x000 },
6544 { 0x00000000, 0x00000000, 0x000 },
6545 { 0x00000000, 0x00000000, 0x000 },
6546 { 0x00000000, 0x00000000, 0x000 },
6547 { 0x00000000, 0x00000000, 0x000 },
6548 { 0x00000000, 0x00000000, 0x000 },
6549 { 0x00000000, 0x00000000, 0x000 },
6550 { 0x01420502, 0x05c00250, 0x000 },
6551 { 0x01c30168, 0x043f05c0, 0x000 },
6552 { 0x02250209, 0x02500151, 0x000 },
6553 { 0x02230245, 0x02a00241, 0x000 },
6554 { 0x03d705c0, 0x05c005c0, 0x000 },
6555 { 0x0649064a, 0x031f05c0, 0x000 },
6556 { 0x05c005c5, 0x03200340, 0x000 },
6557 { 0x032a0282, 0x03420334, 0x000 },
6558 { 0x05c005c0, 0x05c005c0, 0x000 },
6559 { 0x05c00551, 0x05c005c0, 0x000 },
6560 { 0x03ba05c0, 0x04bb0344, 0x000 },
6561 { 0x049a0450, 0x043d05c0, 0x000 },
6562 { 0x04d005c0, 0x044104dd, 0x000 },
6563 { 0x04500507, 0x03510375, 0x000 },
6564 { 0x05c005c0, 0x05c005c0, 0x000 },
6565 { 0x05c005c0, 0x05c005c0, 0x000 },
6566 { 0x05c005c0, 0x063f05c7, 0x000 },
6567 { 0x05c005c0, 0x000705c0, 0x000 },
6568 { 0x05c005c0, 0x05c005c0, 0x000 },
6569 { 0x05c005c0, 0x05c005c0, 0x000 },
6570 { 0x03f803ed, 0x04080406, 0x000 },
6571 { 0x040e040a, 0x040c0410, 0x000 },
6572 { 0x041c0418, 0x04240420, 0x000 },
6573 { 0x042c0428, 0x04340430, 0x000 },
6574 { 0x05c005c0, 0x043805c0, 0x000 },
6575 { 0x05c005c0, 0x05c005c0, 0x000 },
6576 { 0x05c005c0, 0x05c005c0, 0x000 },
6577 { 0x00020679, 0x06970006, 0x000 },
6578};
6579
6580static const u32 RV620_pfp_microcode[] = {
65810xca0400,
65820xa00000,
65830x7e828b,
65840x7c038b,
65850x8001b8,
65860x7c038b,
65870xd4401e,
65880xee001e,
65890xca0400,
65900xa00000,
65910x7e828b,
65920xc41838,
65930xca2400,
65940xca2800,
65950x9581a8,
65960xc41c3a,
65970xc3c000,
65980xca0800,
65990xca0c00,
66000x7c744b,
66010xc20005,
66020x99c000,
66030xc41c3a,
66040x7c744c,
66050xc0fff0,
66060x042c04,
66070x309002,
66080x7d2500,
66090x351402,
66100x7d350b,
66110x255403,
66120x7cd580,
66130x259c03,
66140x95c004,
66150xd5001b,
66160x7eddc1,
66170x7d9d80,
66180xd6801b,
66190xd5801b,
66200xd4401e,
66210xd5401e,
66220xd6401e,
66230xd6801e,
66240xd4801e,
66250xd4c01e,
66260x9783d3,
66270xd5c01e,
66280xca0800,
66290x80001a,
66300xca0c00,
66310xe4011e,
66320xd4001e,
66330x80000c,
66340xc41838,
66350xe4013e,
66360xd4001e,
66370x80000c,
66380xc41838,
66390xd4401e,
66400xee001e,
66410xca0400,
66420xa00000,
66430x7e828b,
66440xe4011e,
66450xd4001e,
66460xd4401e,
66470xee001e,
66480xca0400,
66490xa00000,
66500x7e828b,
66510xe4013e,
66520xd4001e,
66530xd4401e,
66540xee001e,
66550xca0400,
66560xa00000,
66570x7e828b,
66580xca1800,
66590xd4401e,
66600xd5801e,
66610x800053,
66620xd40075,
66630xd4401e,
66640xca0800,
66650xca0c00,
66660xca1000,
66670xd48019,
66680xd4c018,
66690xd50017,
66700xd4801e,
66710xd4c01e,
66720xd5001e,
66730xe2001e,
66740xca0400,
66750xa00000,
66760x7e828b,
66770xca0800,
66780xd48060,
66790xd4401e,
66800x800000,
66810xd4801e,
66820xca0800,
66830xd48061,
66840xd4401e,
66850x800000,
66860xd4801e,
66870xca0800,
66880xca0c00,
66890xd4401e,
66900xd48016,
66910xd4c016,
66920xd4801e,
66930x8001b8,
66940xd4c01e,
66950xc60843,
66960xca0c00,
66970xca1000,
66980x948004,
66990xca1400,
67000xe420f3,
67010xd42013,
67020xd56065,
67030xd4e01c,
67040xd5201c,
67050xd5601c,
67060x800000,
67070x062001,
67080xc60843,
67090xca0c00,
67100xca1000,
67110x9483f7,
67120xca1400,
67130xe420f3,
67140x800079,
67150xd42013,
67160xc60843,
67170xca0c00,
67180xca1000,
67190x9883ef,
67200xca1400,
67210xd40064,
67220x80008d,
67230x000000,
67240xc41432,
67250xc61843,
67260xc4082f,
67270x954005,
67280xc40c30,
67290xd4401e,
67300x800000,
67310xee001e,
67320x9583f5,
67330xc41031,
67340xd44033,
67350xd52065,
67360xd4a01c,
67370xd4e01c,
67380xd5201c,
67390xe4015e,
67400xd4001e,
67410x800000,
67420x062001,
67430xca1800,
67440x0a2001,
67450xd60076,
67460xc40836,
67470x988007,
67480xc61045,
67490x950110,
67500xd4001f,
67510xd46062,
67520x800000,
67530xd42062,
67540xcc3835,
67550xcc1433,
67560x8401bb,
67570xd40072,
67580xd5401e,
67590x800000,
67600xee001e,
67610xe2001a,
67620x8401bb,
67630xe2001a,
67640xcc104b,
67650xcc0447,
67660x2c9401,
67670x7d098b,
67680x984005,
67690x7d15cb,
67700xd4001a,
67710x8001b8,
67720xd4006d,
67730x344401,
67740xcc0c48,
67750x98403a,
67760xcc2c4a,
67770x958004,
67780xcc0449,
67790x8001b8,
67800xd4001a,
67810xd4c01a,
67820x282801,
67830x8400f0,
67840xcc1003,
67850x98801b,
67860x04380c,
67870x8400f0,
67880xcc1003,
67890x988017,
67900x043808,
67910x8400f0,
67920xcc1003,
67930x988013,
67940x043804,
67950x8400f0,
67960xcc1003,
67970x988014,
67980xcc104c,
67990x9a8009,
68000xcc144d,
68010x9840dc,
68020xd4006d,
68030xcc1848,
68040xd5001a,
68050xd5401a,
68060x8000c9,
68070xd5801a,
68080x96c0d5,
68090xd4006d,
68100x8001b8,
68110xd4006e,
68120x9ac003,
68130xd4006d,
68140xd4006e,
68150x800000,
68160xec007f,
68170x9ac0cc,
68180xd4006d,
68190x8001b8,
68200xd4006e,
68210xcc1403,
68220xcc1803,
68230xcc1c03,
68240x7d9103,
68250x7dd583,
68260x7d190c,
68270x35cc1f,
68280x35701f,
68290x7cf0cb,
68300x7cd08b,
68310x880000,
68320x7e8e8b,
68330x95c004,
68340xd4006e,
68350x8001b8,
68360xd4001a,
68370xd4c01a,
68380xcc0803,
68390xcc0c03,
68400xcc1003,
68410xcc1403,
68420xcc1803,
68430xcc1c03,
68440xcc2403,
68450xcc2803,
68460x35c41f,
68470x36b01f,
68480x7c704b,
68490x34f01f,
68500x7c704b,
68510x35701f,
68520x7c704b,
68530x7d8881,
68540x7dccc1,
68550x7e5101,
68560x7e9541,
68570x7c9082,
68580x7cd4c2,
68590x7c848b,
68600x9ac003,
68610x7c8c8b,
68620x2c8801,
68630x98809e,
68640xd4006d,
68650x98409c,
68660xd4006e,
68670xcc084c,
68680xcc0c4d,
68690xcc1048,
68700xd4801a,
68710xd4c01a,
68720x800101,
68730xd5001a,
68740xcc0832,
68750xd40032,
68760x9482d9,
68770xca0c00,
68780xd4401e,
68790x800000,
68800xd4001e,
68810xe4011e,
68820xd4001e,
68830xca0800,
68840xca0c00,
68850xca1000,
68860xd4401e,
68870xca1400,
68880xd4801e,
68890xd4c01e,
68900xd5001e,
68910xd5401e,
68920xd54034,
68930x800000,
68940xee001e,
68950x280404,
68960xe2001a,
68970xe2001a,
68980xd4401a,
68990xca3800,
69000xcc0803,
69010xcc0c03,
69020xcc0c03,
69030xcc0c03,
69040x9882bd,
69050x000000,
69060x8401bb,
69070xd7a06f,
69080x800000,
69090xee001f,
69100xca0400,
69110xc2ff00,
69120xcc0834,
69130xc13fff,
69140x7c74cb,
69150x7cc90b,
69160x7d010f,
69170x9902b0,
69180x7c738b,
69190x8401bb,
69200xd7a06f,
69210x800000,
69220xee001f,
69230xca0800,
69240x281900,
69250x7d898b,
69260x958014,
69270x281404,
69280xca0c00,
69290xca1000,
69300xca1c00,
69310xca2400,
69320xe2001f,
69330xd4c01a,
69340xd5001a,
69350xd5401a,
69360xcc1803,
69370xcc2c03,
69380xcc2c03,
69390xcc2c03,
69400x7da58b,
69410x7d9c47,
69420x984297,
69430x000000,
69440x800161,
69450xd4c01a,
69460xd4401e,
69470xd4801e,
69480x800000,
69490xee001e,
69500xe4011e,
69510xd4001e,
69520xd4401e,
69530xee001e,
69540xca0400,
69550xa00000,
69560x7e828b,
69570xe4013e,
69580xd4001e,
69590xd4401e,
69600xee001e,
69610xca0400,
69620xa00000,
69630x7e828b,
69640xca0800,
69650x248c06,
69660x0ccc06,
69670x98c006,
69680xcc104e,
69690x990004,
69700xd40073,
69710xe4011e,
69720xd4001e,
69730xd4401e,
69740xd4801e,
69750x800000,
69760xee001e,
69770xca0800,
69780xca0c00,
69790x34d018,
69800x251001,
69810x950021,
69820xc17fff,
69830xca1000,
69840xca1400,
69850xca1800,
69860xd4801d,
69870xd4c01d,
69880x7db18b,
69890xc14202,
69900xc2c001,
69910xd5801d,
69920x34dc0e,
69930x7d5d4c,
69940x7f734c,
69950xd7401e,
69960xd5001e,
69970xd5401e,
69980xc14200,
69990xc2c000,
70000x099c01,
70010x31dc10,
70020x7f5f4c,
70030x7f734c,
70040x042802,
70050x7d8380,
70060xd5a86f,
70070xd58066,
70080xd7401e,
70090xec005e,
70100xc82402,
70110xc82402,
70120x8001b8,
70130xd60076,
70140xd4401e,
70150xd4801e,
70160xd4c01e,
70170x800000,
70180xee001e,
70190x800000,
70200xee001f,
70210xd4001f,
70220x800000,
70230xd4001f,
70240xd4001f,
70250x880000,
70260xd4001f,
70270x000000,
70280x000000,
70290x000000,
70300x000000,
70310x000000,
70320x000000,
70330x000000,
70340x000000,
70350x000000,
70360x000000,
70370x000000,
70380x000000,
70390x000000,
70400x000000,
70410x000000,
70420x000000,
70430x000000,
70440x000000,
70450x000000,
70460x000000,
70470x000000,
70480x000000,
70490x000000,
70500x000000,
70510x000000,
70520x000000,
70530x000000,
70540x000000,
70550x000000,
70560x000000,
70570x000000,
70580x000000,
70590x000000,
70600x000000,
70610x000000,
70620x000000,
70630x000000,
70640x000000,
70650x000000,
70660x000000,
70670x000000,
70680x000000,
70690x000000,
70700x000000,
70710x000000,
70720x000000,
70730x000000,
70740x000000,
70750x000000,
70760x000000,
70770x000000,
70780x000000,
70790x000000,
70800x000000,
70810x000000,
70820x000000,
70830x000000,
70840x000000,
70850x000000,
70860x000000,
70870x000000,
70880x000000,
70890x000000,
70900x000000,
70910x000000,
70920x000000,
70930x010171,
70940x020178,
70950x03008f,
70960x04007f,
70970x050003,
70980x06003f,
70990x070032,
71000x08012c,
71010x090046,
71020x0a0036,
71030x1001b6,
71040x1700a2,
71050x22013a,
71060x230149,
71070x2000b4,
71080x240125,
71090x27004d,
71100x28006a,
71110x2a0060,
71120x2b0052,
71130x2f0065,
71140x320087,
71150x34017f,
71160x3c0156,
71170x3f0072,
71180x41018c,
71190x44012e,
71200x550173,
71210x56017a,
71220x60000b,
71230x610034,
71240x620038,
71250x630038,
71260x640038,
71270x650038,
71280x660038,
71290x670038,
71300x68003a,
71310x690041,
71320x6a0048,
71330x6b0048,
71340x6c0048,
71350x6d0048,
71360x6e0048,
71370x6f0048,
71380x000006,
71390x000006,
71400x000006,
71410x000006,
71420x000006,
71430x000006,
71440x000006,
71450x000006,
71460x000006,
71470x000006,
71480x000006,
71490x000006,
71500x000006,
71510x000006,
71520x000006,
71530x000006,
71540x000006,
71550x000006,
71560x000006,
7157};
7158
7159static const u32 RV630_cp_microcode[][3] = {
7160 { 0x00000000, 0xc0200400, 0x000 },
7161 { 0x00000000, 0x00a0000a, 0x000 },
7162 { 0x0000ffff, 0x00284621, 0x000 },
7163 { 0x00000000, 0xd9004800, 0x000 },
7164 { 0x00000000, 0xc0200400, 0x000 },
7165 { 0x00000000, 0x00a0000a, 0x000 },
7166 { 0x00000000, 0x00e00000, 0x000 },
7167 { 0x00010000, 0xc0294620, 0x000 },
7168 { 0x00000000, 0xd9004800, 0x000 },
7169 { 0x00000000, 0xc0200400, 0x000 },
7170 { 0x00000000, 0x00a0000a, 0x000 },
7171 { 0x81000000, 0x00204411, 0x000 },
7172 { 0x00000001, 0x00204811, 0x000 },
7173 { 0x00042004, 0x00604411, 0x68a },
7174 { 0x00000000, 0x00600000, 0x62e },
7175 { 0x00000000, 0x00600000, 0x642 },
7176 { 0x00000000, 0xc0200800, 0x000 },
7177 { 0x00000f00, 0x00281622, 0x000 },
7178 { 0x00000008, 0x00211625, 0x000 },
7179 { 0x00000018, 0x00203625, 0x000 },
7180 { 0x8d000000, 0x00204411, 0x000 },
7181 { 0x00000004, 0x002f0225, 0x000 },
7182 { 0x00000000, 0x0ce00000, 0x018 },
7183 { 0x00412000, 0x00404811, 0x019 },
7184 { 0x00422000, 0x00204811, 0x000 },
7185 { 0x8e000000, 0x00204411, 0x000 },
7186 { 0x00000028, 0x00204a2d, 0x000 },
7187 { 0x90000000, 0x00204411, 0x000 },
7188 { 0x00000000, 0x00204805, 0x000 },
7189 { 0x0000000c, 0x00211622, 0x000 },
7190 { 0x00000003, 0x00281625, 0x000 },
7191 { 0x00000019, 0x00211a22, 0x000 },
7192 { 0x00000004, 0x00281a26, 0x000 },
7193 { 0x00000000, 0x002914c5, 0x000 },
7194 { 0x00000019, 0x00203625, 0x000 },
7195 { 0x00000000, 0x003a1402, 0x000 },
7196 { 0x00000016, 0x00211625, 0x000 },
7197 { 0x00000003, 0x00281625, 0x000 },
7198 { 0x00000017, 0x00200e2d, 0x000 },
7199 { 0xfffffffc, 0x00280e23, 0x000 },
7200 { 0x00000000, 0x002914a3, 0x000 },
7201 { 0x00000017, 0x00203625, 0x000 },
7202 { 0x00008000, 0x00280e22, 0x000 },
7203 { 0x00000007, 0x00220e23, 0x000 },
7204 { 0x00000000, 0x0029386e, 0x000 },
7205 { 0x20000000, 0x00280e22, 0x000 },
7206 { 0x00000006, 0x00210e23, 0x000 },
7207 { 0x00000000, 0x0029386e, 0x000 },
7208 { 0x00000000, 0x00220222, 0x000 },
7209 { 0x00000000, 0x14e00000, 0x038 },
7210 { 0x00000000, 0x2ee00000, 0x035 },
7211 { 0x00000000, 0x2ce00000, 0x037 },
7212 { 0x00000000, 0x00400e2d, 0x039 },
7213 { 0x00000008, 0x00200e2d, 0x000 },
7214 { 0x00000009, 0x0040122d, 0x046 },
7215 { 0x00000001, 0x00400e2d, 0x039 },
7216 { 0x00000000, 0xc0200c00, 0x000 },
7217 { 0x003ffffc, 0x00281223, 0x000 },
7218 { 0x00000002, 0x00221224, 0x000 },
7219 { 0x0000001f, 0x00211e23, 0x000 },
7220 { 0x00000000, 0x14e00000, 0x03e },
7221 { 0x00000008, 0x00401c11, 0x041 },
7222 { 0x0000000d, 0x00201e2d, 0x000 },
7223 { 0x0000000f, 0x00281e27, 0x000 },
7224 { 0x00000003, 0x00221e27, 0x000 },
7225 { 0x7fc00000, 0x00281a23, 0x000 },
7226 { 0x00000014, 0x00211a26, 0x000 },
7227 { 0x00000001, 0x00331a26, 0x000 },
7228 { 0x00000008, 0x00221a26, 0x000 },
7229 { 0x00000000, 0x00290cc7, 0x000 },
7230 { 0x00000027, 0x00203624, 0x000 },
7231 { 0x00007f00, 0x00281221, 0x000 },
7232 { 0x00001400, 0x002f0224, 0x000 },
7233 { 0x00000000, 0x0ce00000, 0x04b },
7234 { 0x00000001, 0x00290e23, 0x000 },
7235 { 0x0000000e, 0x00203623, 0x000 },
7236 { 0x0000e000, 0x00204411, 0x000 },
7237 { 0xfff80000, 0x00294a23, 0x000 },
7238 { 0x00000000, 0x003a2c02, 0x000 },
7239 { 0x00000002, 0x00220e2b, 0x000 },
7240 { 0xfc000000, 0x00280e23, 0x000 },
7241 { 0x0000000f, 0x00203623, 0x000 },
7242 { 0x00001fff, 0x00294a23, 0x000 },
7243 { 0x00000027, 0x00204a2d, 0x000 },
7244 { 0x00000000, 0x00204811, 0x000 },
7245 { 0x00000029, 0x00200e2d, 0x000 },
7246 { 0x060a0200, 0x00294a23, 0x000 },
7247 { 0x00000000, 0x00204811, 0x000 },
7248 { 0x00000000, 0x00204811, 0x000 },
7249 { 0x00000001, 0x00210222, 0x000 },
7250 { 0x00000000, 0x14e00000, 0x061 },
7251 { 0x00000000, 0x2ee00000, 0x05f },
7252 { 0x00000000, 0x2ce00000, 0x05e },
7253 { 0x00000000, 0x00400e2d, 0x062 },
7254 { 0x00000001, 0x00400e2d, 0x062 },
7255 { 0x0000000a, 0x00200e2d, 0x000 },
7256 { 0x0000000b, 0x0040122d, 0x06a },
7257 { 0x00000000, 0xc0200c00, 0x000 },
7258 { 0x003ffffc, 0x00281223, 0x000 },
7259 { 0x00000002, 0x00221224, 0x000 },
7260 { 0x7fc00000, 0x00281623, 0x000 },
7261 { 0x00000014, 0x00211625, 0x000 },
7262 { 0x00000001, 0x00331625, 0x000 },
7263 { 0x80000000, 0x00280e23, 0x000 },
7264 { 0x00000000, 0x00290ca3, 0x000 },
7265 { 0x3ffffc00, 0x00290e23, 0x000 },
7266 { 0x0000001f, 0x00211e23, 0x000 },
7267 { 0x00000000, 0x14e00000, 0x06d },
7268 { 0x00000100, 0x00401c11, 0x070 },
7269 { 0x0000000d, 0x00201e2d, 0x000 },
7270 { 0x000000f0, 0x00281e27, 0x000 },
7271 { 0x00000004, 0x00221e27, 0x000 },
7272 { 0x81000000, 0x00204411, 0x000 },
7273 { 0x0000000d, 0x00204811, 0x000 },
7274 { 0xfffff0ff, 0x00281a30, 0x000 },
7275 { 0x0000a028, 0x00204411, 0x000 },
7276 { 0x00000000, 0x002948e6, 0x000 },
7277 { 0x0000a018, 0x00204411, 0x000 },
7278 { 0x3fffffff, 0x00284a23, 0x000 },
7279 { 0x0000a010, 0x00204411, 0x000 },
7280 { 0x00000000, 0x00204804, 0x000 },
7281 { 0x00000030, 0x0020162d, 0x000 },
7282 { 0x00000002, 0x00291625, 0x000 },
7283 { 0x00000030, 0x00203625, 0x000 },
7284 { 0x00000025, 0x0020162d, 0x000 },
7285 { 0x00000000, 0x002f00a3, 0x000 },
7286 { 0x00000000, 0x0cc00000, 0x083 },
7287 { 0x00000026, 0x0020162d, 0x000 },
7288 { 0x00000000, 0x002f00a4, 0x000 },
7289 { 0x00000000, 0x0cc00000, 0x084 },
7290 { 0x00000000, 0x00400000, 0x08a },
7291 { 0x00000025, 0x00203623, 0x000 },
7292 { 0x00000026, 0x00203624, 0x000 },
7293 { 0x00000017, 0x00201e2d, 0x000 },
7294 { 0x00000002, 0x00210227, 0x000 },
7295 { 0x00000000, 0x14e00000, 0x08a },
7296 { 0x00000000, 0x00600000, 0x665 },
7297 { 0x00000000, 0x00600000, 0x659 },
7298 { 0x00000002, 0x00210e22, 0x000 },
7299 { 0x00000000, 0x14c00000, 0x08d },
7300 { 0x00000012, 0xc0403620, 0x093 },
7301 { 0x00000000, 0x2ee00000, 0x091 },
7302 { 0x00000000, 0x2ce00000, 0x090 },
7303 { 0x00000002, 0x00400e2d, 0x092 },
7304 { 0x00000003, 0x00400e2d, 0x092 },
7305 { 0x0000000c, 0x00200e2d, 0x000 },
7306 { 0x00000012, 0x00203623, 0x000 },
7307 { 0x00000003, 0x00210e22, 0x000 },
7308 { 0x00000000, 0x14c00000, 0x098 },
7309 { 0x0000a00c, 0x00204411, 0x000 },
7310 { 0x00000000, 0xc0204800, 0x000 },
7311 { 0x00000000, 0xc0404800, 0x0a0 },
7312 { 0x0000a00c, 0x00204411, 0x000 },
7313 { 0x00000000, 0x00204811, 0x000 },
7314 { 0x00000000, 0x2ee00000, 0x09e },
7315 { 0x00000000, 0x2ce00000, 0x09d },
7316 { 0x00000002, 0x00400e2d, 0x09f },
7317 { 0x00000003, 0x00400e2d, 0x09f },
7318 { 0x0000000c, 0x00200e2d, 0x000 },
7319 { 0x00000000, 0x00204803, 0x000 },
7320 { 0x00000000, 0x003a0c02, 0x000 },
7321 { 0x003f0000, 0x00280e23, 0x000 },
7322 { 0x00000010, 0x00210e23, 0x000 },
7323 { 0x00000011, 0x00203623, 0x000 },
7324 { 0x0000001e, 0x0021022b, 0x000 },
7325 { 0x00000000, 0x14c00000, 0x0a7 },
7326 { 0x00000016, 0xc0203620, 0x000 },
7327 { 0x0000001f, 0x0021022b, 0x000 },
7328 { 0x00000000, 0x14c00000, 0x0aa },
7329 { 0x00000015, 0xc0203620, 0x000 },
7330 { 0x00000008, 0x00210e2b, 0x000 },
7331 { 0x0000007f, 0x00280e23, 0x000 },
7332 { 0x00000000, 0x002f0223, 0x000 },
7333 { 0x00000000, 0x0ce00000, 0x0e1 },
7334 { 0x00000000, 0x27000000, 0x000 },
7335 { 0x00000000, 0x00600000, 0x2a3 },
7336 { 0x00000001, 0x002f0223, 0x000 },
7337 { 0x00000000, 0x0ae00000, 0x0b3 },
7338 { 0x00000000, 0x00600000, 0x13a },
7339 { 0x81000000, 0x00204411, 0x000 },
7340 { 0x00000006, 0x00204811, 0x000 },
7341 { 0x0000000c, 0x00221e30, 0x000 },
7342 { 0x99800000, 0x00204411, 0x000 },
7343 { 0x00000004, 0x0020122d, 0x000 },
7344 { 0x00000008, 0x00221224, 0x000 },
7345 { 0x00000010, 0x00201811, 0x000 },
7346 { 0x00000000, 0x00291ce4, 0x000 },
7347 { 0x00000000, 0x00604807, 0x12f },
7348 { 0x9b000000, 0x00204411, 0x000 },
7349 { 0x00000000, 0x00204802, 0x000 },
7350 { 0x9c000000, 0x00204411, 0x000 },
7351 { 0x00000000, 0x0033146f, 0x000 },
7352 { 0x00000001, 0x00333e23, 0x000 },
7353 { 0x00000000, 0xd9004800, 0x000 },
7354 { 0x00000000, 0x00203c05, 0x000 },
7355 { 0x81000000, 0x00204411, 0x000 },
7356 { 0x0000000e, 0x00204811, 0x000 },
7357 { 0x00000000, 0x00201010, 0x000 },
7358 { 0x0000e007, 0x00204411, 0x000 },
7359 { 0x0000000f, 0x0021022b, 0x000 },
7360 { 0x00000000, 0x14c00000, 0x0cb },
7361 { 0x00f8ff08, 0x00204811, 0x000 },
7362 { 0x98000000, 0x00404811, 0x0dc },
7363 { 0x000000f0, 0x00280e22, 0x000 },
7364 { 0x000000a0, 0x002f0223, 0x000 },
7365 { 0x00000000, 0x0cc00000, 0x0da },
7366 { 0x00000011, 0x00200e2d, 0x000 },
7367 { 0x00000001, 0x002f0223, 0x000 },
7368 { 0x00000000, 0x0ce00000, 0x0d5 },
7369 { 0x00000002, 0x002f0223, 0x000 },
7370 { 0x00000000, 0x0ce00000, 0x0d4 },
7371 { 0x00003f00, 0x00400c11, 0x0d6 },
7372 { 0x00001f00, 0x00400c11, 0x0d6 },
7373 { 0x00000f00, 0x00200c11, 0x000 },
7374 { 0x00380009, 0x00294a23, 0x000 },
7375 { 0x3f000000, 0x00280e2b, 0x000 },
7376 { 0x00000002, 0x00220e23, 0x000 },
7377 { 0x00000007, 0x00494a23, 0x0dc },
7378 { 0x00380f09, 0x00204811, 0x000 },
7379 { 0x68000007, 0x00204811, 0x000 },
7380 { 0x00000008, 0x00214a27, 0x000 },
7381 { 0x00000000, 0x00204811, 0x000 },
7382 { 0x060a0200, 0x00294a24, 0x000 },
7383 { 0x00000000, 0x00204811, 0x000 },
7384 { 0x00000000, 0x00204811, 0x000 },
7385 { 0x0000a202, 0x00204411, 0x000 },
7386 { 0x00ff0000, 0x00280e22, 0x000 },
7387 { 0x00000080, 0x00294a23, 0x000 },
7388 { 0x00000027, 0x00200e2d, 0x000 },
7389 { 0x00000026, 0x0020122d, 0x000 },
7390 { 0x00000000, 0x002f0083, 0x000 },
7391 { 0x00000000, 0x0ce00000, 0x0ea },
7392 { 0x00000000, 0x00600000, 0x65f },
7393 { 0x00000000, 0x00400000, 0x0eb },
7394 { 0x00000000, 0x00600000, 0x662 },
7395 { 0x00000007, 0x0020222d, 0x000 },
7396 { 0x00000005, 0x00220e22, 0x000 },
7397 { 0x00100000, 0x00280e23, 0x000 },
7398 { 0x00000000, 0x00292068, 0x000 },
7399 { 0x00000000, 0x003a0c02, 0x000 },
7400 { 0x000000ef, 0x00280e23, 0x000 },
7401 { 0x00000000, 0x00292068, 0x000 },
7402 { 0x00000017, 0x00200e2d, 0x000 },
7403 { 0x00000003, 0x00210223, 0x000 },
7404 { 0x00000000, 0x14e00000, 0x0f8 },
7405 { 0x0000000b, 0x00210228, 0x000 },
7406 { 0x00000000, 0x14c00000, 0x0f8 },
7407 { 0x00000400, 0x00292228, 0x000 },
7408 { 0x00000014, 0x00203628, 0x000 },
7409 { 0x0000001c, 0x00210e22, 0x000 },
7410 { 0x00000000, 0x14c00000, 0x0fd },
7411 { 0x0000a30c, 0x00204411, 0x000 },
7412 { 0x00000000, 0x00204811, 0x000 },
7413 { 0x0000001e, 0x00210e22, 0x000 },
7414 { 0x00000000, 0x14c00000, 0x10b },
7415 { 0x0000a30f, 0x00204411, 0x000 },
7416 { 0x00000011, 0x00200e2d, 0x000 },
7417 { 0x00000001, 0x002f0223, 0x000 },
7418 { 0x00000000, 0x0cc00000, 0x104 },
7419 { 0xffffffff, 0x00404811, 0x10b },
7420 { 0x00000002, 0x002f0223, 0x000 },
7421 { 0x00000000, 0x0cc00000, 0x107 },
7422 { 0x0000ffff, 0x00404811, 0x10b },
7423 { 0x00000004, 0x002f0223, 0x000 },
7424 { 0x00000000, 0x0cc00000, 0x10a },
7425 { 0x000000ff, 0x00404811, 0x10b },
7426 { 0x00000001, 0x00204811, 0x000 },
7427 { 0x0002c400, 0x00204411, 0x000 },
7428 { 0x0000001f, 0x00210e22, 0x000 },
7429 { 0x00000000, 0x14c00000, 0x112 },
7430 { 0x00000010, 0x40210e20, 0x000 },
7431 { 0x00000013, 0x00203623, 0x000 },
7432 { 0x00000018, 0x40224a20, 0x000 },
7433 { 0x00000010, 0xc0424a20, 0x114 },
7434 { 0x00000000, 0x00200c11, 0x000 },
7435 { 0x00000013, 0x00203623, 0x000 },
7436 { 0x00000000, 0x00204811, 0x000 },
7437 { 0x00000000, 0x00204811, 0x000 },
7438 { 0x0000000a, 0x00201011, 0x000 },
7439 { 0x00000000, 0x002f0224, 0x000 },
7440 { 0x00000000, 0x0ce00000, 0x11b },
7441 { 0x00000000, 0x00204811, 0x000 },
7442 { 0x00000001, 0x00531224, 0x117 },
7443 { 0xffbfffff, 0x00283a2e, 0x000 },
7444 { 0x0000001b, 0x00210222, 0x000 },
7445 { 0x00000000, 0x14c00000, 0x12e },
7446 { 0x81000000, 0x00204411, 0x000 },
7447 { 0x0000000d, 0x00204811, 0x000 },
7448 { 0x00000018, 0x00220e30, 0x000 },
7449 { 0xfc000000, 0x00280e23, 0x000 },
7450 { 0x81000000, 0x00204411, 0x000 },
7451 { 0x0000000e, 0x00204811, 0x000 },
7452 { 0x00000000, 0x00201010, 0x000 },
7453 { 0x0000e00e, 0x00204411, 0x000 },
7454 { 0x07f8ff08, 0x00204811, 0x000 },
7455 { 0x00000000, 0x00294a23, 0x000 },
7456 { 0x0000001c, 0x00201e2d, 0x000 },
7457 { 0x00000008, 0x00214a27, 0x000 },
7458 { 0x00000000, 0x00204811, 0x000 },
7459 { 0x060a0200, 0x00294a24, 0x000 },
7460 { 0x00000000, 0x00204811, 0x000 },
7461 { 0x00000000, 0x00204811, 0x000 },
7462 { 0x00000000, 0x00800000, 0x000 },
7463 { 0x81000000, 0x00204411, 0x000 },
7464 { 0x00000001, 0x00204811, 0x000 },
7465 { 0x0000217c, 0x00204411, 0x000 },
7466 { 0x00800000, 0x00204811, 0x000 },
7467 { 0x00000000, 0x00204806, 0x000 },
7468 { 0x00000008, 0x00214a27, 0x000 },
7469 { 0x00000000, 0x17000000, 0x000 },
7470 { 0x0004217f, 0x00604411, 0x68a },
7471 { 0x0000001f, 0x00210230, 0x000 },
7472 { 0x00000000, 0x14c00000, 0x689 },
7473 { 0x00000004, 0x00404c11, 0x135 },
7474 { 0x81000000, 0x00204411, 0x000 },
7475 { 0x00000001, 0x00204811, 0x000 },
7476 { 0x000021f8, 0x00204411, 0x000 },
7477 { 0x0000001c, 0x00204811, 0x000 },
7478 { 0x000421f9, 0x00604411, 0x68a },
7479 { 0x00000011, 0x00210230, 0x000 },
7480 { 0x00000000, 0x14e00000, 0x13c },
7481 { 0x00000000, 0x00800000, 0x000 },
7482 { 0x00000000, 0x00600000, 0x00b },
7483 { 0x00000000, 0x00600411, 0x315 },
7484 { 0x00000000, 0x00200411, 0x000 },
7485 { 0x00000000, 0x00600811, 0x1b2 },
7486 { 0x00000000, 0x00600000, 0x160 },
7487 { 0x0000ffff, 0x40280e20, 0x000 },
7488 { 0x00000010, 0xc0211220, 0x000 },
7489 { 0x0000ffff, 0x40280620, 0x000 },
7490 { 0x00000010, 0xc0210a20, 0x000 },
7491 { 0x00000000, 0x00341461, 0x000 },
7492 { 0x00000000, 0x00741882, 0x2bb },
7493 { 0x0001a1fd, 0x00604411, 0x2e0 },
7494 { 0x00003fff, 0x002f022f, 0x000 },
7495 { 0x00000000, 0x0cc00000, 0x147 },
7496 { 0x00000000, 0xc0400400, 0x001 },
7497 { 0x00000000, 0x00600000, 0x00b },
7498 { 0x00000000, 0x00600411, 0x315 },
7499 { 0x00000000, 0x00200411, 0x000 },
7500 { 0x00000000, 0x00600811, 0x1b2 },
7501 { 0x00003fff, 0x002f022f, 0x000 },
7502 { 0x00000000, 0x0ce00000, 0x000 },
7503 { 0x00000000, 0x00600000, 0x160 },
7504 { 0x00000010, 0x40210e20, 0x000 },
7505 { 0x0000ffff, 0xc0281220, 0x000 },
7506 { 0x00000010, 0x40211620, 0x000 },
7507 { 0x0000ffff, 0xc0681a20, 0x2bb },
7508 { 0x0001a1fd, 0x00604411, 0x2e0 },
7509 { 0x00003fff, 0x002f022f, 0x000 },
7510 { 0x00000000, 0x0cc00000, 0x158 },
7511 { 0x00000000, 0xc0400400, 0x001 },
7512 { 0x0000225c, 0x00204411, 0x000 },
7513 { 0x00000001, 0x00300a2f, 0x000 },
7514 { 0x00000001, 0x00210a22, 0x000 },
7515 { 0x00000003, 0x00384a22, 0x000 },
7516 { 0x00002256, 0x00204411, 0x000 },
7517 { 0x0000001a, 0x00204811, 0x000 },
7518 { 0x0000a1fc, 0x00204411, 0x000 },
7519 { 0x00000001, 0x00804811, 0x000 },
7520 { 0x00000000, 0x00600000, 0x00b },
7521 { 0x00000000, 0x00600000, 0x18f },
7522 { 0x00000000, 0x00600000, 0x1a0 },
7523 { 0x00003fff, 0x002f022f, 0x000 },
7524 { 0x00000000, 0x0ce00000, 0x000 },
7525 { 0x00000000, 0x00202c08, 0x000 },
7526 { 0x00000000, 0x00202411, 0x000 },
7527 { 0x00000000, 0x00202811, 0x000 },
7528 { 0x00002256, 0x00204411, 0x000 },
7529 { 0x00000016, 0x00204811, 0x000 },
7530 { 0x0000225c, 0x00204411, 0x000 },
7531 { 0x00000003, 0x00204811, 0x000 },
7532 { 0x93800000, 0x00204411, 0x000 },
7533 { 0x00000002, 0x00221e29, 0x000 },
7534 { 0x00000000, 0x007048eb, 0x19c },
7535 { 0x00000000, 0x00600000, 0x2bb },
7536 { 0x00000001, 0x40330620, 0x000 },
7537 { 0x00000000, 0xc0302409, 0x000 },
7538 { 0x00003fff, 0x002f022f, 0x000 },
7539 { 0x00000000, 0x0ce00000, 0x000 },
7540 { 0x00000000, 0x00600000, 0x2a3 },
7541 { 0x00000000, 0x002f0221, 0x000 },
7542 { 0x00000000, 0x0ae00000, 0x181 },
7543 { 0x00000000, 0x00600000, 0x13a },
7544 { 0x00000000, 0x00400000, 0x186 },
7545 { 0x95000000, 0x00204411, 0x000 },
7546 { 0x00000000, 0x002f0221, 0x000 },
7547 { 0x00000000, 0x0ce00000, 0x186 },
7548 { 0x00000000, 0xc0204800, 0x000 },
7549 { 0x00000001, 0x00530621, 0x182 },
7550 { 0x92000000, 0x00204411, 0x000 },
7551 { 0x00000000, 0xc0604800, 0x197 },
7552 { 0x0001a1fd, 0x00204411, 0x000 },
7553 { 0x00000011, 0x0020062d, 0x000 },
7554 { 0x00000000, 0x0078042a, 0x2fb },
7555 { 0x00000000, 0x00202809, 0x000 },
7556 { 0x00003fff, 0x002f022f, 0x000 },
7557 { 0x00000000, 0x0cc00000, 0x174 },
7558 { 0x00000000, 0xc0400400, 0x001 },
7559 { 0x00000210, 0x00600411, 0x315 },
7560 { 0x00003fff, 0x002f022f, 0x000 },
7561 { 0x00000000, 0x0ce00000, 0x194 },
7562 { 0x00000015, 0xc0203620, 0x000 },
7563 { 0x00000016, 0xc0203620, 0x000 },
7564 { 0x3f800000, 0x00200411, 0x000 },
7565 { 0x46000000, 0x00600811, 0x1b2 },
7566 { 0x00000000, 0x00800000, 0x000 },
7567 { 0x0000a1fc, 0x00204411, 0x000 },
7568 { 0x00003fff, 0x002f022f, 0x000 },
7569 { 0x00000000, 0x0cc00000, 0x19b },
7570 { 0x00000001, 0x00804811, 0x000 },
7571 { 0x00000021, 0x00804811, 0x000 },
7572 { 0x0000ffff, 0x40280e20, 0x000 },
7573 { 0x00000010, 0xc0211220, 0x000 },
7574 { 0x0000ffff, 0x40281620, 0x000 },
7575 { 0x00000010, 0xc0811a20, 0x000 },
7576 { 0x81000000, 0x00204411, 0x000 },
7577 { 0x00000006, 0x00204811, 0x000 },
7578 { 0x00000008, 0x00221e30, 0x000 },
7579 { 0x00000029, 0x00201a2d, 0x000 },
7580 { 0x0000e000, 0x00204411, 0x000 },
7581 { 0xfffbff09, 0x00204811, 0x000 },
7582 { 0x0000000f, 0x0020222d, 0x000 },
7583 { 0x00001fff, 0x00294a28, 0x000 },
7584 { 0x00000006, 0x0020222d, 0x000 },
7585 { 0x00000000, 0x002920e8, 0x000 },
7586 { 0x00000000, 0x00204808, 0x000 },
7587 { 0x00000000, 0x00204811, 0x000 },
7588 { 0x060a0200, 0x00294a26, 0x000 },
7589 { 0x00000000, 0x00204811, 0x000 },
7590 { 0x00000000, 0x00204811, 0x000 },
7591 { 0x00000100, 0x00201811, 0x000 },
7592 { 0x00000008, 0x00621e28, 0x12f },
7593 { 0x00000008, 0x00822228, 0x000 },
7594 { 0x0002c000, 0x00204411, 0x000 },
7595 { 0x00000015, 0x00600e2d, 0x1bd },
7596 { 0x00000016, 0x00600e2d, 0x1bd },
7597 { 0x0000c008, 0x00204411, 0x000 },
7598 { 0x00000017, 0x00200e2d, 0x000 },
7599 { 0x00000000, 0x14c00000, 0x1b9 },
7600 { 0x00000000, 0x00200411, 0x000 },
7601 { 0x00000000, 0x00204801, 0x000 },
7602 { 0x39000000, 0x00204811, 0x000 },
7603 { 0x00000000, 0x00204811, 0x000 },
7604 { 0x00000000, 0x00804802, 0x000 },
7605 { 0x00000018, 0x00202e2d, 0x000 },
7606 { 0x00000000, 0x003b0d63, 0x000 },
7607 { 0x00000008, 0x00224a23, 0x000 },
7608 { 0x00000010, 0x00224a23, 0x000 },
7609 { 0x00000018, 0x00224a23, 0x000 },
7610 { 0x00000000, 0x00804803, 0x000 },
7611 { 0x00000000, 0x00600000, 0x00b },
7612 { 0x00001000, 0x00600411, 0x315 },
7613 { 0x00000000, 0x00200411, 0x000 },
7614 { 0x00000000, 0x00600811, 0x1b2 },
7615 { 0x00000007, 0x0021062f, 0x000 },
7616 { 0x00000013, 0x00200a2d, 0x000 },
7617 { 0x00000001, 0x00202c11, 0x000 },
7618 { 0x0000ffff, 0x40282220, 0x000 },
7619 { 0x0000000f, 0x00262228, 0x000 },
7620 { 0x00000010, 0x40212620, 0x000 },
7621 { 0x0000000f, 0x00262629, 0x000 },
7622 { 0x00000000, 0x00202802, 0x000 },
7623 { 0x00002256, 0x00204411, 0x000 },
7624 { 0x0000001b, 0x00204811, 0x000 },
7625 { 0x00000000, 0x002f0221, 0x000 },
7626 { 0x00000000, 0x0ce00000, 0x1e0 },
7627 { 0x0000225c, 0x00204411, 0x000 },
7628 { 0x00000081, 0x00204811, 0x000 },
7629 { 0x0000a1fc, 0x00204411, 0x000 },
7630 { 0x00000001, 0x00204811, 0x000 },
7631 { 0x00000080, 0x00201c11, 0x000 },
7632 { 0x00000000, 0x002f0227, 0x000 },
7633 { 0x00000000, 0x0ce00000, 0x1dc },
7634 { 0x00000000, 0x00600000, 0x1e9 },
7635 { 0x00000001, 0x00531e27, 0x1d8 },
7636 { 0x00000001, 0x00202c11, 0x000 },
7637 { 0x0000001f, 0x00280a22, 0x000 },
7638 { 0x0000001f, 0x00282a2a, 0x000 },
7639 { 0x00000001, 0x00530621, 0x1d1 },
7640 { 0x0000225c, 0x00204411, 0x000 },
7641 { 0x00000002, 0x00304a2f, 0x000 },
7642 { 0x0000a1fc, 0x00204411, 0x000 },
7643 { 0x00000001, 0x00204811, 0x000 },
7644 { 0x00000001, 0x00301e2f, 0x000 },
7645 { 0x00000000, 0x002f0227, 0x000 },
7646 { 0x00000000, 0x0ce00000, 0x000 },
7647 { 0x00000000, 0x00600000, 0x1e9 },
7648 { 0x00000001, 0x00531e27, 0x1e5 },
7649 { 0x0000ffff, 0x40280e20, 0x000 },
7650 { 0x0000000f, 0x00260e23, 0x000 },
7651 { 0x00000010, 0xc0211220, 0x000 },
7652 { 0x0000000f, 0x00261224, 0x000 },
7653 { 0x00000000, 0x00201411, 0x000 },
7654 { 0x00000000, 0x00601811, 0x2bb },
7655 { 0x0001a1fd, 0x00204411, 0x000 },
7656 { 0x00000000, 0x002f022b, 0x000 },
7657 { 0x00000000, 0x0ce00000, 0x1f8 },
7658 { 0x00000010, 0x00221628, 0x000 },
7659 { 0xffff0000, 0x00281625, 0x000 },
7660 { 0x0000ffff, 0x00281a29, 0x000 },
7661 { 0x00000000, 0x002948c5, 0x000 },
7662 { 0x00000000, 0x0020480a, 0x000 },
7663 { 0x00000000, 0x00202c11, 0x000 },
7664 { 0x00000010, 0x00221623, 0x000 },
7665 { 0xffff0000, 0x00281625, 0x000 },
7666 { 0x0000ffff, 0x00281a24, 0x000 },
7667 { 0x00000000, 0x002948c5, 0x000 },
7668 { 0x00000000, 0x00731503, 0x205 },
7669 { 0x00000000, 0x00201805, 0x000 },
7670 { 0x00000000, 0x00731524, 0x205 },
7671 { 0x00000000, 0x002d14c5, 0x000 },
7672 { 0x00000000, 0x003008a2, 0x000 },
7673 { 0x00000000, 0x00204802, 0x000 },
7674 { 0x00000000, 0x00202802, 0x000 },
7675 { 0x00000000, 0x00202003, 0x000 },
7676 { 0x00000000, 0x00802404, 0x000 },
7677 { 0x0000000f, 0x00210225, 0x000 },
7678 { 0x00000000, 0x14c00000, 0x689 },
7679 { 0x00000000, 0x002b1405, 0x000 },
7680 { 0x00000001, 0x00901625, 0x000 },
7681 { 0x00000000, 0x00600000, 0x00b },
7682 { 0x00000000, 0x00600411, 0x315 },
7683 { 0x00000000, 0x00200411, 0x000 },
7684 { 0x00000000, 0x00600811, 0x1b2 },
7685 { 0x00002256, 0x00204411, 0x000 },
7686 { 0x0000001a, 0x00294a22, 0x000 },
7687 { 0x00000000, 0xc0200000, 0x000 },
7688 { 0x00003fff, 0x002f022f, 0x000 },
7689 { 0x00000000, 0x0ce00000, 0x000 },
7690 { 0x00000000, 0xc0200400, 0x000 },
7691 { 0x0000225c, 0x00204411, 0x000 },
7692 { 0x00000003, 0x00384a21, 0x000 },
7693 { 0x0000a1fc, 0x00204411, 0x000 },
7694 { 0x00000001, 0x00204811, 0x000 },
7695 { 0x0000ffff, 0x40281220, 0x000 },
7696 { 0x00000010, 0xc0211a20, 0x000 },
7697 { 0x0000ffff, 0x40280e20, 0x000 },
7698 { 0x00000010, 0xc0211620, 0x000 },
7699 { 0x00000000, 0x00741465, 0x2bb },
7700 { 0x0001a1fd, 0x00604411, 0x2e0 },
7701 { 0x00000001, 0x00330621, 0x000 },
7702 { 0x00000000, 0x002f0221, 0x000 },
7703 { 0x00000000, 0x0cc00000, 0x219 },
7704 { 0x00003fff, 0x002f022f, 0x000 },
7705 { 0x00000000, 0x0cc00000, 0x212 },
7706 { 0x00000000, 0xc0400400, 0x001 },
7707 { 0x00000000, 0x00600000, 0x642 },
7708 { 0x00000000, 0x0040040f, 0x213 },
7709 { 0x00000000, 0x00600000, 0x62e },
7710 { 0x00000000, 0x00600000, 0x642 },
7711 { 0x00000210, 0x00600411, 0x315 },
7712 { 0x00000000, 0x00600000, 0x1a0 },
7713 { 0x00000000, 0x00600000, 0x19c },
7714 { 0x00000000, 0x00600000, 0x2bb },
7715 { 0x00000000, 0x00600000, 0x2a3 },
7716 { 0x93800000, 0x00204411, 0x000 },
7717 { 0x00000000, 0x00204808, 0x000 },
7718 { 0x00000000, 0x002f022f, 0x000 },
7719 { 0x00000000, 0x0ae00000, 0x232 },
7720 { 0x00000000, 0x00600000, 0x13a },
7721 { 0x00000000, 0x00400000, 0x236 },
7722 { 0x95000000, 0x00204411, 0x000 },
7723 { 0x00000000, 0x002f022f, 0x000 },
7724 { 0x00000000, 0x0ce00000, 0x236 },
7725 { 0x00000000, 0xc0404800, 0x233 },
7726 { 0x92000000, 0x00204411, 0x000 },
7727 { 0x00000000, 0xc0204800, 0x000 },
7728 { 0x00002256, 0x00204411, 0x000 },
7729 { 0x00000016, 0x00204811, 0x000 },
7730 { 0x0000225c, 0x00204411, 0x000 },
7731 { 0x00000003, 0x00204811, 0x000 },
7732 { 0x0000a1fc, 0x00204411, 0x000 },
7733 { 0x00000001, 0x00204811, 0x000 },
7734 { 0x0001a1fd, 0x00204411, 0x000 },
7735 { 0x00000000, 0x00600411, 0x2fb },
7736 { 0x00000000, 0xc0400400, 0x001 },
7737 { 0x00000000, 0x00600000, 0x62e },
7738 { 0x0000a00c, 0x00204411, 0x000 },
7739 { 0x00000000, 0xc0204800, 0x000 },
7740 { 0x00000000, 0xc0404800, 0x000 },
7741 { 0x00000000, 0x00600000, 0x00b },
7742 { 0x00000018, 0x40210a20, 0x000 },
7743 { 0x00000003, 0x002f0222, 0x000 },
7744 { 0x00000000, 0x0ae00000, 0x24c },
7745 { 0x00000014, 0x0020222d, 0x000 },
7746 { 0x00080101, 0x00292228, 0x000 },
7747 { 0x00000014, 0x00203628, 0x000 },
7748 { 0x0000a30c, 0x00204411, 0x000 },
7749 { 0x00000000, 0xc0204800, 0x000 },
7750 { 0x00000000, 0xc0204800, 0x000 },
7751 { 0x00000000, 0xc0404800, 0x251 },
7752 { 0x00000000, 0x00600000, 0x00b },
7753 { 0x00000010, 0x00600411, 0x315 },
7754 { 0x3f800000, 0x00200411, 0x000 },
7755 { 0x00000000, 0x00600811, 0x1b2 },
7756 { 0x0000225c, 0x00204411, 0x000 },
7757 { 0x00000003, 0x00204811, 0x000 },
7758 { 0x00000000, 0x00600000, 0x27c },
7759 { 0x00000017, 0x00201e2d, 0x000 },
7760 { 0x00000001, 0x00211e27, 0x000 },
7761 { 0x00000000, 0x14e00000, 0x26a },
7762 { 0x00000012, 0x00201e2d, 0x000 },
7763 { 0x0000ffff, 0x00281e27, 0x000 },
7764 { 0x00000000, 0x00341c27, 0x000 },
7765 { 0x00000000, 0x12c00000, 0x25f },
7766 { 0x00000000, 0x00201c11, 0x000 },
7767 { 0x00000000, 0x002f00e5, 0x000 },
7768 { 0x00000000, 0x08c00000, 0x262 },
7769 { 0x00000000, 0x00201407, 0x000 },
7770 { 0x00000012, 0x00201e2d, 0x000 },
7771 { 0x00000010, 0x00211e27, 0x000 },
7772 { 0x00000000, 0x00341c47, 0x000 },
7773 { 0x00000000, 0x12c00000, 0x267 },
7774 { 0x00000000, 0x00201c11, 0x000 },
7775 { 0x00000000, 0x002f00e6, 0x000 },
7776 { 0x00000000, 0x08c00000, 0x26a },
7777 { 0x00000000, 0x00201807, 0x000 },
7778 { 0x00000000, 0x00600000, 0x2c1 },
7779 { 0x00002256, 0x00204411, 0x000 },
7780 { 0x00000000, 0x00342023, 0x000 },
7781 { 0x00000000, 0x12c00000, 0x272 },
7782 { 0x00000000, 0x00342044, 0x000 },
7783 { 0x00000000, 0x12c00000, 0x271 },
7784 { 0x00000016, 0x00404811, 0x276 },
7785 { 0x00000018, 0x00404811, 0x276 },
7786 { 0x00000000, 0x00342044, 0x000 },
7787 { 0x00000000, 0x12c00000, 0x275 },
7788 { 0x00000017, 0x00404811, 0x276 },
7789 { 0x00000019, 0x00204811, 0x000 },
7790 { 0x0000a1fc, 0x00204411, 0x000 },
7791 { 0x00000001, 0x00204811, 0x000 },
7792 { 0x0001a1fd, 0x00604411, 0x2e9 },
7793 { 0x00003fff, 0x002f022f, 0x000 },
7794 { 0x00000000, 0x0cc00000, 0x256 },
7795 { 0x00000000, 0xc0400400, 0x001 },
7796 { 0x00000010, 0x40210620, 0x000 },
7797 { 0x0000ffff, 0xc0280a20, 0x000 },
7798 { 0x00000010, 0x40210e20, 0x000 },
7799 { 0x0000ffff, 0xc0281220, 0x000 },
7800 { 0x00000010, 0x40211620, 0x000 },
7801 { 0x0000ffff, 0xc0881a20, 0x000 },
7802 { 0x81000000, 0x00204411, 0x000 },
7803 { 0x00000001, 0x00204811, 0x000 },
7804 { 0x00042004, 0x00604411, 0x68a },
7805 { 0x00000000, 0x00600000, 0x62e },
7806 { 0x00000000, 0xc0600000, 0x2a3 },
7807 { 0x00000005, 0x00200a2d, 0x000 },
7808 { 0x00000008, 0x00220a22, 0x000 },
7809 { 0x0000002b, 0x00201a2d, 0x000 },
7810 { 0x0000001c, 0x00201e2d, 0x000 },
7811 { 0x00007000, 0x00281e27, 0x000 },
7812 { 0x00000000, 0x00311ce6, 0x000 },
7813 { 0x0000002a, 0x00201a2d, 0x000 },
7814 { 0x0000000c, 0x00221a26, 0x000 },
7815 { 0x00000000, 0x002f00e6, 0x000 },
7816 { 0x00000000, 0x06e00000, 0x292 },
7817 { 0x00000000, 0x00201c11, 0x000 },
7818 { 0x00000000, 0x00200c11, 0x000 },
7819 { 0x0000002b, 0x00203623, 0x000 },
7820 { 0x00000010, 0x00201811, 0x000 },
7821 { 0x00000000, 0x00691ce2, 0x12f },
7822 { 0x93800000, 0x00204411, 0x000 },
7823 { 0x00000000, 0x00204807, 0x000 },
7824 { 0x95000000, 0x00204411, 0x000 },
7825 { 0x00000000, 0x002f022f, 0x000 },
7826 { 0x00000000, 0x0ce00000, 0x29d },
7827 { 0x00000001, 0x00333e2f, 0x000 },
7828 { 0x00000000, 0xd9004800, 0x000 },
7829 { 0x92000000, 0x00204411, 0x000 },
7830 { 0x00000000, 0xc0204800, 0x000 },
7831 { 0x0000001c, 0x00403627, 0x000 },
7832 { 0x0000000c, 0xc0220a20, 0x000 },
7833 { 0x00000029, 0x00203622, 0x000 },
7834 { 0x00000028, 0xc0403620, 0x000 },
7835 { 0x0000a2a4, 0x00204411, 0x000 },
7836 { 0x00000009, 0x00204811, 0x000 },
7837 { 0xa1000000, 0x00204411, 0x000 },
7838 { 0x00000001, 0x00804811, 0x000 },
7839 { 0x00000021, 0x00201e2d, 0x000 },
7840 { 0x00000000, 0x002c1ce3, 0x000 },
7841 { 0x00000021, 0x00203627, 0x000 },
7842 { 0x00000022, 0x00201e2d, 0x000 },
7843 { 0x00000000, 0x002c1ce4, 0x000 },
7844 { 0x00000022, 0x00203627, 0x000 },
7845 { 0x00000023, 0x00201e2d, 0x000 },
7846 { 0x00000000, 0x003120a3, 0x000 },
7847 { 0x00000000, 0x002d1d07, 0x000 },
7848 { 0x00000023, 0x00203627, 0x000 },
7849 { 0x00000024, 0x00201e2d, 0x000 },
7850 { 0x00000000, 0x003120c4, 0x000 },
7851 { 0x00000000, 0x002d1d07, 0x000 },
7852 { 0x00000024, 0x00803627, 0x000 },
7853 { 0x00000021, 0x00203623, 0x000 },
7854 { 0x00000022, 0x00203624, 0x000 },
7855 { 0x00000000, 0x00311ca3, 0x000 },
7856 { 0x00000023, 0x00203627, 0x000 },
7857 { 0x00000000, 0x00311cc4, 0x000 },
7858 { 0x00000024, 0x00803627, 0x000 },
7859 { 0x0000001a, 0x00203627, 0x000 },
7860 { 0x0000001b, 0x00203628, 0x000 },
7861 { 0x00000017, 0x00201e2d, 0x000 },
7862 { 0x00000002, 0x00210227, 0x000 },
7863 { 0x00000000, 0x14c00000, 0x2dc },
7864 { 0x00000000, 0x00400000, 0x2d9 },
7865 { 0x0000001a, 0x00203627, 0x000 },
7866 { 0x0000001b, 0x00203628, 0x000 },
7867 { 0x00000017, 0x00201e2d, 0x000 },
7868 { 0x00000002, 0x00210227, 0x000 },
7869 { 0x00000000, 0x14e00000, 0x2d9 },
7870 { 0x00000003, 0x00210227, 0x000 },
7871 { 0x00000000, 0x14e00000, 0x2dc },
7872 { 0x00000023, 0x00201e2d, 0x000 },
7873 { 0x00000000, 0x002e00e1, 0x000 },
7874 { 0x00000000, 0x02c00000, 0x2dc },
7875 { 0x00000021, 0x00201e2d, 0x000 },
7876 { 0x00000000, 0x003120a1, 0x000 },
7877 { 0x00000000, 0x002e00e8, 0x000 },
7878 { 0x00000000, 0x06c00000, 0x2dc },
7879 { 0x00000024, 0x00201e2d, 0x000 },
7880 { 0x00000000, 0x002e00e2, 0x000 },
7881 { 0x00000000, 0x02c00000, 0x2dc },
7882 { 0x00000022, 0x00201e2d, 0x000 },
7883 { 0x00000000, 0x003120c2, 0x000 },
7884 { 0x00000000, 0x002e00e8, 0x000 },
7885 { 0x00000000, 0x06c00000, 0x2dc },
7886 { 0x00000000, 0x00600000, 0x665 },
7887 { 0x00000000, 0x00600000, 0x2b5 },
7888 { 0x00000000, 0x00400000, 0x2de },
7889 { 0x00000000, 0x00600000, 0x2b5 },
7890 { 0x00000000, 0x00600000, 0x65c },
7891 { 0x00000000, 0x00400000, 0x2de },
7892 { 0x00000000, 0x00600000, 0x2a7 },
7893 { 0x00000000, 0x00400000, 0x2de },
7894 { 0x0000001a, 0x00201e2d, 0x000 },
7895 { 0x0000001b, 0x0080222d, 0x000 },
7896 { 0x00000010, 0x00221e23, 0x000 },
7897 { 0x00000000, 0x00294887, 0x000 },
7898 { 0x00000000, 0x00311ca3, 0x000 },
7899 { 0x00000010, 0x00221e27, 0x000 },
7900 { 0x00000000, 0x00294887, 0x000 },
7901 { 0x00000010, 0x00221e23, 0x000 },
7902 { 0x00000000, 0x003120c4, 0x000 },
7903 { 0x0000ffff, 0x00282228, 0x000 },
7904 { 0x00000000, 0x00894907, 0x000 },
7905 { 0x00000010, 0x00221e23, 0x000 },
7906 { 0x00000000, 0x00294887, 0x000 },
7907 { 0x00000010, 0x00221e21, 0x000 },
7908 { 0x00000000, 0x00294847, 0x000 },
7909 { 0x00000000, 0x00311ca3, 0x000 },
7910 { 0x00000010, 0x00221e27, 0x000 },
7911 { 0x00000000, 0x00294887, 0x000 },
7912 { 0x00000000, 0x00311ca1, 0x000 },
7913 { 0x00000010, 0x00221e27, 0x000 },
7914 { 0x00000000, 0x00294847, 0x000 },
7915 { 0x00000010, 0x00221e23, 0x000 },
7916 { 0x00000000, 0x003120c4, 0x000 },
7917 { 0x0000ffff, 0x00282228, 0x000 },
7918 { 0x00000000, 0x00294907, 0x000 },
7919 { 0x00000010, 0x00221e21, 0x000 },
7920 { 0x00000000, 0x003120c2, 0x000 },
7921 { 0x0000ffff, 0x00282228, 0x000 },
7922 { 0x00000000, 0x00894907, 0x000 },
7923 { 0x00000010, 0x00221e23, 0x000 },
7924 { 0x00000000, 0x00294887, 0x000 },
7925 { 0x00000001, 0x00220a21, 0x000 },
7926 { 0x00000000, 0x003308a2, 0x000 },
7927 { 0x00000010, 0x00221e22, 0x000 },
7928 { 0x00000010, 0x00212222, 0x000 },
7929 { 0x00000000, 0x00294907, 0x000 },
7930 { 0x00000000, 0x00311ca3, 0x000 },
7931 { 0x00000010, 0x00221e27, 0x000 },
7932 { 0x00000000, 0x00294887, 0x000 },
7933 { 0x00000001, 0x00220a21, 0x000 },
7934 { 0x00000000, 0x003008a2, 0x000 },
7935 { 0x00000010, 0x00221e22, 0x000 },
7936 { 0x00000010, 0x00212222, 0x000 },
7937 { 0x00000000, 0x00294907, 0x000 },
7938 { 0x00000010, 0x00221e23, 0x000 },
7939 { 0x00000000, 0x003120c4, 0x000 },
7940 { 0x0000ffff, 0x00282228, 0x000 },
7941 { 0x00000000, 0x00294907, 0x000 },
7942 { 0x00000000, 0x003808c5, 0x000 },
7943 { 0x00000000, 0x00300841, 0x000 },
7944 { 0x00000001, 0x00220a22, 0x000 },
7945 { 0x00000000, 0x003308a2, 0x000 },
7946 { 0x00000010, 0x00221e22, 0x000 },
7947 { 0x00000010, 0x00212222, 0x000 },
7948 { 0x00000000, 0x00894907, 0x000 },
7949 { 0x00000017, 0x0020222d, 0x000 },
7950 { 0x00000000, 0x14c00000, 0x318 },
7951 { 0xffffffef, 0x00280621, 0x000 },
7952 { 0x00000014, 0x0020222d, 0x000 },
7953 { 0x0000f8e0, 0x00204411, 0x000 },
7954 { 0x00000000, 0x00294901, 0x000 },
7955 { 0x00000000, 0x00894901, 0x000 },
7956 { 0x00000000, 0x00204811, 0x000 },
7957 { 0x00000000, 0x00204811, 0x000 },
7958 { 0x060a0200, 0x00804811, 0x000 },
7959 { 0x00000000, 0xc0200000, 0x000 },
7960 { 0x97000000, 0xc0204411, 0x000 },
7961 { 0x00000000, 0xc0204811, 0x000 },
7962 { 0x8a000000, 0x00204411, 0x000 },
7963 { 0x00000000, 0x00204811, 0x000 },
7964 { 0x0000225c, 0x00204411, 0x000 },
7965 { 0x00000000, 0xc0204800, 0x000 },
7966 { 0x0000a1fc, 0x00204411, 0x000 },
7967 { 0x00000000, 0xc0204800, 0x000 },
7968 { 0x00000000, 0xc0200400, 0x000 },
7969 { 0x00000000, 0x00a0000a, 0x000 },
7970 { 0x97000000, 0x00204411, 0x000 },
7971 { 0x00000000, 0x00204811, 0x000 },
7972 { 0x8a000000, 0x00204411, 0x000 },
7973 { 0x00000000, 0x00204811, 0x000 },
7974 { 0x0000225c, 0x00204411, 0x000 },
7975 { 0x00000000, 0xc0204800, 0x000 },
7976 { 0x0000a1fc, 0x00204411, 0x000 },
7977 { 0x00000000, 0xc0204800, 0x000 },
7978 { 0x00000000, 0xc0200400, 0x000 },
7979 { 0x00000000, 0x00a0000a, 0x000 },
7980 { 0x97000000, 0x00204411, 0x000 },
7981 { 0x00000000, 0x00204811, 0x000 },
7982 { 0x8a000000, 0x00204411, 0x000 },
7983 { 0x00000000, 0x00204811, 0x000 },
7984 { 0x0000225c, 0x00204411, 0x000 },
7985 { 0x00000000, 0xc0204800, 0x000 },
7986 { 0x0000a1fc, 0x00204411, 0x000 },
7987 { 0x00000000, 0xc0204800, 0x000 },
7988 { 0x0001a1fd, 0x00204411, 0x000 },
7989 { 0x00000000, 0xd9004800, 0x000 },
7990 { 0x00000000, 0xc0200400, 0x000 },
7991 { 0x00000000, 0x00a0000a, 0x000 },
7992 { 0x00002257, 0x00204411, 0x000 },
7993 { 0x00000003, 0xc0484a20, 0x000 },
7994 { 0x0000225d, 0x00204411, 0x000 },
7995 { 0x00000000, 0xc0404800, 0x000 },
7996 { 0x00000000, 0x00600000, 0x642 },
7997 { 0x00000000, 0xc0200800, 0x000 },
7998 { 0x0000225c, 0x00204411, 0x000 },
7999 { 0x00000003, 0x00384a22, 0x000 },
8000 { 0x0000a1fc, 0x00204411, 0x000 },
8001 { 0x00000000, 0xc0204800, 0x000 },
8002 { 0x0001a1fd, 0x00204411, 0x000 },
8003 { 0x00000000, 0x002f0222, 0x000 },
8004 { 0x00000000, 0x0ce00000, 0x000 },
8005 { 0x00000000, 0x40204800, 0x000 },
8006 { 0x00000001, 0x40304a20, 0x000 },
8007 { 0x00000002, 0xc0304a20, 0x000 },
8008 { 0x00000001, 0x00530a22, 0x34b },
8009 { 0x0000003f, 0xc0280a20, 0x000 },
8010 { 0x81000000, 0x00204411, 0x000 },
8011 { 0x00000001, 0x00204811, 0x000 },
8012 { 0x000021f8, 0x00204411, 0x000 },
8013 { 0x00000018, 0x00204811, 0x000 },
8014 { 0x000421f9, 0x00604411, 0x68a },
8015 { 0x00000011, 0x00210230, 0x000 },
8016 { 0x00000000, 0x14e00000, 0x354 },
8017 { 0x00000014, 0x002f0222, 0x000 },
8018 { 0x00000000, 0x0cc00000, 0x364 },
8019 { 0x00002010, 0x00204411, 0x000 },
8020 { 0x00008000, 0x00204811, 0x000 },
8021 { 0x0001a2a4, 0x00204411, 0x000 },
8022 { 0x00000000, 0x00604802, 0x36e },
8023 { 0x00002100, 0x00204411, 0x000 },
8024 { 0x00000000, 0xc0204800, 0x000 },
8025 { 0x00000000, 0xc0204800, 0x000 },
8026 { 0x00000000, 0xc0204800, 0x000 },
8027 { 0x00000000, 0xc0404800, 0x000 },
8028 { 0x00000004, 0x002f0222, 0x000 },
8029 { 0x00000000, 0x0cc00000, 0x36a },
8030 { 0x00002010, 0x00204411, 0x000 },
8031 { 0x00008000, 0x00204811, 0x000 },
8032 { 0x0001a2a4, 0x00204411, 0x000 },
8033 { 0x00000000, 0x00404802, 0x35f },
8034 { 0x00000028, 0x002f0222, 0x000 },
8035 { 0x00000000, 0x0cc00000, 0x5bd },
8036 { 0x0001a2a4, 0x00204411, 0x000 },
8037 { 0x00000000, 0x00404802, 0x35f },
8038 { 0x0000002c, 0x00203626, 0x000 },
8039 { 0x00000049, 0x00201811, 0x000 },
8040 { 0x0000003f, 0x00204811, 0x000 },
8041 { 0x00000001, 0x00331a26, 0x000 },
8042 { 0x00000000, 0x002f0226, 0x000 },
8043 { 0x00000000, 0x0cc00000, 0x370 },
8044 { 0x0000002c, 0x00801a2d, 0x000 },
8045 { 0x0000003f, 0xc0280a20, 0x000 },
8046 { 0x00000015, 0x002f0222, 0x000 },
8047 { 0x00000000, 0x0ce00000, 0x386 },
8048 { 0x00000006, 0x002f0222, 0x000 },
8049 { 0x00000000, 0x0ce00000, 0x3b1 },
8050 { 0x00000016, 0x002f0222, 0x000 },
8051 { 0x00000000, 0x0ce00000, 0x3b5 },
8052 { 0x00000020, 0x002f0222, 0x000 },
8053 { 0x00000000, 0x0ce00000, 0x39c },
8054 { 0x0000000f, 0x002f0222, 0x000 },
8055 { 0x00000000, 0x0ce00000, 0x3a8 },
8056 { 0x00000010, 0x002f0222, 0x000 },
8057 { 0x00000000, 0x0ce00000, 0x3a8 },
8058 { 0x0000001e, 0x002f0222, 0x000 },
8059 { 0x00000000, 0x0ce00000, 0x390 },
8060 { 0x0000a2a4, 0x00204411, 0x000 },
8061 { 0x00000000, 0x00404802, 0x000 },
8062 { 0x08000000, 0x00290a22, 0x000 },
8063 { 0x00000003, 0x40210e20, 0x000 },
8064 { 0x0000000c, 0xc0211220, 0x000 },
8065 { 0x00080000, 0x00281224, 0x000 },
8066 { 0x00000014, 0xc0221620, 0x000 },
8067 { 0x00000000, 0x002914a4, 0x000 },
8068 { 0x0000a2a4, 0x00204411, 0x000 },
8069 { 0x00000000, 0x002948a2, 0x000 },
8070 { 0x0000a1fe, 0x00204411, 0x000 },
8071 { 0x00000000, 0x00404803, 0x000 },
8072 { 0x81000000, 0x00204411, 0x000 },
8073 { 0x00000001, 0x00204811, 0x000 },
8074 { 0x000021f8, 0x00204411, 0x000 },
8075 { 0x00000016, 0x00204811, 0x000 },
8076 { 0x000421f9, 0x00604411, 0x68a },
8077 { 0x00000015, 0x00210230, 0x000 },
8078 { 0x00000000, 0x14e00000, 0x392 },
8079 { 0x0000210e, 0x00204411, 0x000 },
8080 { 0x00000000, 0xc0204800, 0x000 },
8081 { 0x00000000, 0xc0204800, 0x000 },
8082 { 0x0000a2a4, 0x00204411, 0x000 },
8083 { 0x00000000, 0x00404802, 0x000 },
8084 { 0x81000000, 0x00204411, 0x000 },
8085 { 0x00000001, 0x00204811, 0x000 },
8086 { 0x000021f8, 0x00204411, 0x000 },
8087 { 0x00000017, 0x00204811, 0x000 },
8088 { 0x000421f9, 0x00604411, 0x68a },
8089 { 0x00000003, 0x00210230, 0x000 },
8090 { 0x00000000, 0x14e00000, 0x39e },
8091 { 0x00002108, 0x00204411, 0x000 },
8092 { 0x00000000, 0xc0204800, 0x000 },
8093 { 0x00000000, 0xc0204800, 0x000 },
8094 { 0x0000a2a4, 0x00204411, 0x000 },
8095 { 0x00000000, 0x00404802, 0x000 },
8096 { 0x0000a2a4, 0x00204411, 0x000 },
8097 { 0x00000000, 0x00204802, 0x000 },
8098 { 0x80000000, 0x00204411, 0x000 },
8099 { 0x00000000, 0x00204811, 0x000 },
8100 { 0x81000000, 0x00204411, 0x000 },
8101 { 0x00000010, 0x00204811, 0x000 },
8102 { 0x00000000, 0x00200010, 0x000 },
8103 { 0x00000000, 0x14c00000, 0x3ae },
8104 { 0x00000000, 0x00400000, 0x000 },
8105 { 0x00002010, 0x00204411, 0x000 },
8106 { 0x00008000, 0x00204811, 0x000 },
8107 { 0x0001a2a4, 0x00204411, 0x000 },
8108 { 0x00000006, 0x00404811, 0x000 },
8109 { 0x00002010, 0x00204411, 0x000 },
8110 { 0x00008000, 0x00204811, 0x000 },
8111 { 0x0001a2a4, 0x00204411, 0x000 },
8112 { 0x00000016, 0x00604811, 0x36e },
8113 { 0x00000000, 0x00400000, 0x000 },
8114 { 0x00000000, 0xc0200800, 0x000 },
8115 { 0x00000000, 0xc0200c00, 0x000 },
8116 { 0x0000001d, 0x00210223, 0x000 },
8117 { 0x00000000, 0x14e00000, 0x3ce },
8118 { 0x81000000, 0x00204411, 0x000 },
8119 { 0x00000001, 0x00204811, 0x000 },
8120 { 0x000021f8, 0x00204411, 0x000 },
8121 { 0x00000018, 0x00204811, 0x000 },
8122 { 0x000421f9, 0x00604411, 0x68a },
8123 { 0x00000011, 0x00210230, 0x000 },
8124 { 0x00000000, 0x14e00000, 0x3c0 },
8125 { 0x00002100, 0x00204411, 0x000 },
8126 { 0x00000000, 0x00204802, 0x000 },
8127 { 0x00000000, 0x00204803, 0x000 },
8128 { 0xbabecafe, 0x00204811, 0x000 },
8129 { 0xcafebabe, 0x00204811, 0x000 },
8130 { 0x00002010, 0x00204411, 0x000 },
8131 { 0x00008000, 0x00204811, 0x000 },
8132 { 0x0000a2a4, 0x00204411, 0x000 },
8133 { 0x00000004, 0x00404811, 0x000 },
8134 { 0x00002170, 0x00204411, 0x000 },
8135 { 0x00000000, 0x00204802, 0x000 },
8136 { 0x00000000, 0x00204803, 0x000 },
8137 { 0x81000000, 0x00204411, 0x000 },
8138 { 0x0000000a, 0x00204811, 0x000 },
8139 { 0x00000000, 0x00200010, 0x000 },
8140 { 0x00000000, 0x14c00000, 0x3d3 },
8141 { 0x8c000000, 0x00204411, 0x000 },
8142 { 0xcafebabe, 0x00404811, 0x000 },
8143 { 0x81000000, 0x00204411, 0x000 },
8144 { 0x00000001, 0x00204811, 0x000 },
8145 { 0x00003fff, 0x40280a20, 0x000 },
8146 { 0x80000000, 0x40280e20, 0x000 },
8147 { 0x40000000, 0xc0281220, 0x000 },
8148 { 0x00040000, 0x00694622, 0x68a },
8149 { 0x00000000, 0x00201410, 0x000 },
8150 { 0x00000000, 0x002f0223, 0x000 },
8151 { 0x00000000, 0x0cc00000, 0x3e1 },
8152 { 0x00000000, 0xc0401800, 0x3e4 },
8153 { 0x00003fff, 0xc0281a20, 0x000 },
8154 { 0x00040000, 0x00694626, 0x68a },
8155 { 0x00000000, 0x00201810, 0x000 },
8156 { 0x00000000, 0x002f0224, 0x000 },
8157 { 0x00000000, 0x0cc00000, 0x3e7 },
8158 { 0x00000000, 0xc0401c00, 0x3ea },
8159 { 0x00003fff, 0xc0281e20, 0x000 },
8160 { 0x00040000, 0x00694627, 0x68a },
8161 { 0x00000000, 0x00201c10, 0x000 },
8162 { 0x00000000, 0x00204402, 0x000 },
8163 { 0x00000000, 0x002820c5, 0x000 },
8164 { 0x00000000, 0x004948e8, 0x000 },
8165 { 0xa5800000, 0x00200811, 0x000 },
8166 { 0x00002000, 0x00200c11, 0x000 },
8167 { 0x83000000, 0x00604411, 0x412 },
8168 { 0x00000000, 0x00204402, 0x000 },
8169 { 0x00000000, 0xc0204800, 0x000 },
8170 { 0x00000000, 0x40204800, 0x000 },
8171 { 0x0000001f, 0xc0210220, 0x000 },
8172 { 0x00000000, 0x14c00000, 0x3f7 },
8173 { 0x00002010, 0x00204411, 0x000 },
8174 { 0x00008000, 0x00204811, 0x000 },
8175 { 0x0000ffff, 0xc0481220, 0x3ff },
8176 { 0xa7800000, 0x00200811, 0x000 },
8177 { 0x0000a000, 0x00200c11, 0x000 },
8178 { 0x83000000, 0x00604411, 0x412 },
8179 { 0x00000000, 0x00204402, 0x000 },
8180 { 0x00000000, 0xc0204800, 0x000 },
8181 { 0x00000000, 0xc0204800, 0x000 },
8182 { 0x0000ffff, 0xc0281220, 0x000 },
8183 { 0x83000000, 0x00204411, 0x000 },
8184 { 0x00000000, 0x00304883, 0x000 },
8185 { 0x84000000, 0x00204411, 0x000 },
8186 { 0x00000000, 0xc0204800, 0x000 },
8187 { 0x00000000, 0x1d000000, 0x000 },
8188 { 0x83000000, 0x00604411, 0x412 },
8189 { 0x00000000, 0xc0400400, 0x001 },
8190 { 0xa9800000, 0x00200811, 0x000 },
8191 { 0x0000c000, 0x00400c11, 0x3fa },
8192 { 0xab800000, 0x00200811, 0x000 },
8193 { 0x0000f8e0, 0x00400c11, 0x3fa },
8194 { 0xad800000, 0x00200811, 0x000 },
8195 { 0x0000f880, 0x00400c11, 0x3fa },
8196 { 0xb3800000, 0x00200811, 0x000 },
8197 { 0x0000f3fc, 0x00400c11, 0x3fa },
8198 { 0xaf800000, 0x00200811, 0x000 },
8199 { 0x0000e000, 0x00400c11, 0x3fa },
8200 { 0xb1800000, 0x00200811, 0x000 },
8201 { 0x0000f000, 0x00400c11, 0x3fa },
8202 { 0x83000000, 0x00204411, 0x000 },
8203 { 0x00002148, 0x00204811, 0x000 },
8204 { 0x84000000, 0x00204411, 0x000 },
8205 { 0x00000000, 0xc0204800, 0x000 },
8206 { 0x00000000, 0x1d000000, 0x000 },
8207 { 0x00000000, 0x00800000, 0x000 },
8208 { 0x01182000, 0xc0304620, 0x000 },
8209 { 0x00000000, 0xd9004800, 0x000 },
8210 { 0x00000000, 0xc0200400, 0x000 },
8211 { 0x00000000, 0x00a0000a, 0x000 },
8212 { 0x0218a000, 0xc0304620, 0x000 },
8213 { 0x00000000, 0xd9004800, 0x000 },
8214 { 0x00000000, 0xc0200400, 0x000 },
8215 { 0x00000000, 0x00a0000a, 0x000 },
8216 { 0x0318c000, 0xc0304620, 0x000 },
8217 { 0x00000000, 0xd9004800, 0x000 },
8218 { 0x00000000, 0xc0200400, 0x000 },
8219 { 0x00000000, 0x00a0000a, 0x000 },
8220 { 0x0418f8e0, 0xc0304620, 0x000 },
8221 { 0x00000000, 0xd9004800, 0x000 },
8222 { 0x00000000, 0xc0200400, 0x000 },
8223 { 0x00000000, 0x00a0000a, 0x000 },
8224 { 0x0518f880, 0xc0304620, 0x000 },
8225 { 0x00000000, 0xd9004800, 0x000 },
8226 { 0x00000000, 0xc0200400, 0x000 },
8227 { 0x00000000, 0x00a0000a, 0x000 },
8228 { 0x0618e000, 0xc0304620, 0x000 },
8229 { 0x00000000, 0xd9004800, 0x000 },
8230 { 0x00000000, 0xc0200400, 0x000 },
8231 { 0x00000000, 0x00a0000a, 0x000 },
8232 { 0x0718f000, 0xc0304620, 0x000 },
8233 { 0x00000000, 0xd9004800, 0x000 },
8234 { 0x00000000, 0xc0200400, 0x000 },
8235 { 0x00000000, 0x00a0000a, 0x000 },
8236 { 0x0818f3fc, 0xc0304620, 0x000 },
8237 { 0x00000000, 0xd9004800, 0x000 },
8238 { 0x00000000, 0xc0200400, 0x000 },
8239 { 0x00000000, 0x00a0000a, 0x000 },
8240 { 0x00000030, 0x00200a2d, 0x000 },
8241 { 0x00000000, 0xc0290c40, 0x000 },
8242 { 0x00000030, 0x00203623, 0x000 },
8243 { 0x00000000, 0xc0200400, 0x000 },
8244 { 0x00000000, 0x00a0000a, 0x000 },
8245 { 0x86000000, 0x00204411, 0x000 },
8246 { 0x00000000, 0x00404801, 0x000 },
8247 { 0x85000000, 0xc0204411, 0x000 },
8248 { 0x00000000, 0x00404801, 0x000 },
8249 { 0x0000217c, 0x00204411, 0x000 },
8250 { 0x00000000, 0xc0204800, 0x000 },
8251 { 0x00000000, 0xc0204800, 0x000 },
8252 { 0x00000000, 0xc0204800, 0x000 },
8253 { 0x81000000, 0x00204411, 0x000 },
8254 { 0x00000001, 0x00204811, 0x000 },
8255 { 0x00000000, 0xc0200800, 0x000 },
8256 { 0x00000000, 0x17000000, 0x000 },
8257 { 0x0004217f, 0x00604411, 0x68a },
8258 { 0x0000001f, 0x00210230, 0x000 },
8259 { 0x00000000, 0x14c00000, 0x000 },
8260 { 0x00000000, 0x00404c02, 0x448 },
8261 { 0x00000000, 0xc0200c00, 0x000 },
8262 { 0x00000000, 0xc0201000, 0x000 },
8263 { 0x00000000, 0xc0201400, 0x000 },
8264 { 0x00000000, 0xc0201800, 0x000 },
8265 { 0x00000000, 0xc0201c00, 0x000 },
8266 { 0x00007f00, 0x00280a21, 0x000 },
8267 { 0x00004500, 0x002f0222, 0x000 },
8268 { 0x00000000, 0x0ce00000, 0x456 },
8269 { 0x00000000, 0xc0202000, 0x000 },
8270 { 0x00000000, 0x17000000, 0x000 },
8271 { 0x00000010, 0x00280a23, 0x000 },
8272 { 0x00000010, 0x002f0222, 0x000 },
8273 { 0x00000000, 0x0ce00000, 0x45e },
8274 { 0x81000000, 0x00204411, 0x000 },
8275 { 0x00000001, 0x00204811, 0x000 },
8276 { 0x00040000, 0x00694624, 0x68a },
8277 { 0x00000000, 0x00400000, 0x463 },
8278 { 0x81000000, 0x00204411, 0x000 },
8279 { 0x00000000, 0x00204811, 0x000 },
8280 { 0x0000216d, 0x00204411, 0x000 },
8281 { 0x00000000, 0x00204804, 0x000 },
8282 { 0x00000000, 0x00604805, 0x68f },
8283 { 0x00000000, 0x002824f0, 0x000 },
8284 { 0x00000007, 0x00280a23, 0x000 },
8285 { 0x00000001, 0x002f0222, 0x000 },
8286 { 0x00000000, 0x0ae00000, 0x46a },
8287 { 0x00000000, 0x002f00c9, 0x000 },
8288 { 0x00000000, 0x04e00000, 0x483 },
8289 { 0x00000000, 0x00400000, 0x490 },
8290 { 0x00000002, 0x002f0222, 0x000 },
8291 { 0x00000000, 0x0ae00000, 0x46f },
8292 { 0x00000000, 0x002f00c9, 0x000 },
8293 { 0x00000000, 0x02e00000, 0x483 },
8294 { 0x00000000, 0x00400000, 0x490 },
8295 { 0x00000003, 0x002f0222, 0x000 },
8296 { 0x00000000, 0x0ae00000, 0x474 },
8297 { 0x00000000, 0x002f00c9, 0x000 },
8298 { 0x00000000, 0x0ce00000, 0x483 },
8299 { 0x00000000, 0x00400000, 0x490 },
8300 { 0x00000004, 0x002f0222, 0x000 },
8301 { 0x00000000, 0x0ae00000, 0x479 },
8302 { 0x00000000, 0x002f00c9, 0x000 },
8303 { 0x00000000, 0x0ae00000, 0x483 },
8304 { 0x00000000, 0x00400000, 0x490 },
8305 { 0x00000005, 0x002f0222, 0x000 },
8306 { 0x00000000, 0x0ae00000, 0x47e },
8307 { 0x00000000, 0x002f00c9, 0x000 },
8308 { 0x00000000, 0x06e00000, 0x483 },
8309 { 0x00000000, 0x00400000, 0x490 },
8310 { 0x00000006, 0x002f0222, 0x000 },
8311 { 0x00000000, 0x0ae00000, 0x483 },
8312 { 0x00000000, 0x002f00c9, 0x000 },
8313 { 0x00000000, 0x08e00000, 0x483 },
8314 { 0x00000000, 0x00400000, 0x490 },
8315 { 0x00007f00, 0x00280a21, 0x000 },
8316 { 0x00004500, 0x002f0222, 0x000 },
8317 { 0x00000000, 0x0ae00000, 0x000 },
8318 { 0x00000008, 0x00210a23, 0x000 },
8319 { 0x00000000, 0x14c00000, 0x48d },
8320 { 0x00002169, 0x00204411, 0x000 },
8321 { 0x00000000, 0xc0204800, 0x000 },
8322 { 0x00000000, 0xc0204800, 0x000 },
8323 { 0x00000000, 0xc0204800, 0x000 },
8324 { 0xcafebabe, 0x00404811, 0x000 },
8325 { 0x00000000, 0xc0204400, 0x000 },
8326 { 0x00000000, 0xc0200000, 0x000 },
8327 { 0x00000000, 0xc0404800, 0x000 },
8328 { 0x00007f00, 0x00280a21, 0x000 },
8329 { 0x00004500, 0x002f0222, 0x000 },
8330 { 0x00000000, 0x0ae00000, 0x496 },
8331 { 0x00000000, 0xc0200000, 0x000 },
8332 { 0x00000000, 0xc0200000, 0x000 },
8333 { 0x00000000, 0xc0400000, 0x000 },
8334 { 0x00000000, 0x00404c08, 0x456 },
8335 { 0x00000000, 0xc0200800, 0x000 },
8336 { 0x00000010, 0x40210e20, 0x000 },
8337 { 0x00000011, 0x40211220, 0x000 },
8338 { 0x00000012, 0x40211620, 0x000 },
8339 { 0x00002169, 0x00204411, 0x000 },
8340 { 0x00000000, 0x00204802, 0x000 },
8341 { 0x00000000, 0x00210225, 0x000 },
8342 { 0x00000000, 0x14e00000, 0x4a0 },
8343 { 0x00040000, 0xc0494a20, 0x4a1 },
8344 { 0xfffbffff, 0xc0284a20, 0x000 },
8345 { 0x00000000, 0x00210223, 0x000 },
8346 { 0x00000000, 0x14e00000, 0x4ad },
8347 { 0x00000000, 0xc0204800, 0x000 },
8348 { 0x00000000, 0xc0204800, 0x000 },
8349 { 0x00000000, 0x00210224, 0x000 },
8350 { 0x00000000, 0x14c00000, 0x000 },
8351 { 0x81000000, 0x00204411, 0x000 },
8352 { 0x0000000c, 0x00204811, 0x000 },
8353 { 0x00000000, 0x00200010, 0x000 },
8354 { 0x00000000, 0x14c00000, 0x4a9 },
8355 { 0xa0000000, 0x00204411, 0x000 },
8356 { 0xcafebabe, 0x00404811, 0x000 },
8357 { 0x81000000, 0x00204411, 0x000 },
8358 { 0x00000004, 0x00204811, 0x000 },
8359 { 0x0000216b, 0x00204411, 0x000 },
8360 { 0x00000000, 0xc0204810, 0x000 },
8361 { 0x81000000, 0x00204411, 0x000 },
8362 { 0x00000005, 0x00204811, 0x000 },
8363 { 0x0000216c, 0x00204411, 0x000 },
8364 { 0x00000000, 0xc0204810, 0x000 },
8365 { 0x00000000, 0x002f0224, 0x000 },
8366 { 0x00000000, 0x0ce00000, 0x000 },
8367 { 0x00000000, 0x00400000, 0x4a7 },
8368 { 0x00000000, 0xc0210a20, 0x000 },
8369 { 0x00000000, 0x14c00000, 0x4c0 },
8370 { 0x81000000, 0x00204411, 0x000 },
8371 { 0x00000000, 0x00204811, 0x000 },
8372 { 0x0000216d, 0x00204411, 0x000 },
8373 { 0x00000000, 0xc0204800, 0x000 },
8374 { 0x00000000, 0xc0604800, 0x68f },
8375 { 0x00000000, 0x00400000, 0x4c4 },
8376 { 0x81000000, 0x00204411, 0x000 },
8377 { 0x00000001, 0x00204811, 0x000 },
8378 { 0x00040000, 0xc0294620, 0x000 },
8379 { 0x00000000, 0xc0600000, 0x68a },
8380 { 0x00000001, 0x00210222, 0x000 },
8381 { 0x00000000, 0x14c00000, 0x4cb },
8382 { 0x00002169, 0x00204411, 0x000 },
8383 { 0x00000000, 0xc0204800, 0x000 },
8384 { 0x00000000, 0xc0204800, 0x000 },
8385 { 0x00000000, 0x00204810, 0x000 },
8386 { 0xcafebabe, 0x00404811, 0x000 },
8387 { 0x00000000, 0xc0204400, 0x000 },
8388 { 0x00000000, 0xc0404810, 0x000 },
8389 { 0x81000000, 0x00204411, 0x000 },
8390 { 0x00000001, 0x00204811, 0x000 },
8391 { 0x000021f8, 0x00204411, 0x000 },
8392 { 0x0000000e, 0x00204811, 0x000 },
8393 { 0x000421f9, 0x00604411, 0x68a },
8394 { 0x00000000, 0x00210230, 0x000 },
8395 { 0x00000000, 0x14c00000, 0x4cd },
8396 { 0x00002180, 0x00204411, 0x000 },
8397 { 0x00000000, 0xc0204800, 0x000 },
8398 { 0x00000000, 0xc0200000, 0x000 },
8399 { 0x00000000, 0xc0204800, 0x000 },
8400 { 0x00000000, 0xc0200000, 0x000 },
8401 { 0x00000000, 0xc0404800, 0x000 },
8402 { 0x00000003, 0x00333e2f, 0x000 },
8403 { 0x00000001, 0x00210221, 0x000 },
8404 { 0x00000000, 0x14e00000, 0x4fd },
8405 { 0x0000002c, 0x00200a2d, 0x000 },
8406 { 0x00040000, 0x18e00c11, 0x4ec },
8407 { 0x00000001, 0x00333e2f, 0x000 },
8408 { 0x00002169, 0x00204411, 0x000 },
8409 { 0x00000000, 0x00204802, 0x000 },
8410 { 0x00000000, 0x00204803, 0x000 },
8411 { 0x00000008, 0x00300a22, 0x000 },
8412 { 0x00000000, 0xc0204800, 0x000 },
8413 { 0x00000000, 0xc0204800, 0x000 },
8414 { 0x00002169, 0x00204411, 0x000 },
8415 { 0x00000000, 0x00204802, 0x000 },
8416 { 0x00000000, 0x00204803, 0x000 },
8417 { 0x00000008, 0x00300a22, 0x000 },
8418 { 0x00000000, 0xc0204800, 0x000 },
8419 { 0x00000000, 0xd8c04800, 0x4e0 },
8420 { 0x00002169, 0x00204411, 0x000 },
8421 { 0x00000000, 0x00204802, 0x000 },
8422 { 0x00000000, 0x00204803, 0x000 },
8423 { 0x00000008, 0x00300a22, 0x000 },
8424 { 0x00000000, 0xc0204800, 0x000 },
8425 { 0x00000000, 0xc0204800, 0x000 },
8426 { 0x0000002d, 0x0020122d, 0x000 },
8427 { 0x00000000, 0x00290c83, 0x000 },
8428 { 0x00002169, 0x00204411, 0x000 },
8429 { 0x00000000, 0x00204802, 0x000 },
8430 { 0x00000000, 0x00204803, 0x000 },
8431 { 0x00000008, 0x00300a22, 0x000 },
8432 { 0x00000000, 0xc0204800, 0x000 },
8433 { 0x00000000, 0xc0204800, 0x000 },
8434 { 0x00000011, 0x00210224, 0x000 },
8435 { 0x00000000, 0x14c00000, 0x000 },
8436 { 0x00000000, 0x00400000, 0x4a7 },
8437 { 0x0000002c, 0xc0203620, 0x000 },
8438 { 0x0000002d, 0xc0403620, 0x000 },
8439 { 0x0000000f, 0x00210221, 0x000 },
8440 { 0x00000000, 0x14c00000, 0x502 },
8441 { 0x00000000, 0x00600000, 0x00b },
8442 { 0x00000000, 0xd9000000, 0x000 },
8443 { 0x00000000, 0xc0400400, 0x001 },
8444 { 0xb5000000, 0x00204411, 0x000 },
8445 { 0x00002000, 0x00204811, 0x000 },
8446 { 0xb6000000, 0x00204411, 0x000 },
8447 { 0x0000a000, 0x00204811, 0x000 },
8448 { 0xb7000000, 0x00204411, 0x000 },
8449 { 0x0000c000, 0x00204811, 0x000 },
8450 { 0xb8000000, 0x00204411, 0x000 },
8451 { 0x0000f8e0, 0x00204811, 0x000 },
8452 { 0xb9000000, 0x00204411, 0x000 },
8453 { 0x0000f880, 0x00204811, 0x000 },
8454 { 0xba000000, 0x00204411, 0x000 },
8455 { 0x0000e000, 0x00204811, 0x000 },
8456 { 0xbb000000, 0x00204411, 0x000 },
8457 { 0x0000f000, 0x00204811, 0x000 },
8458 { 0xbc000000, 0x00204411, 0x000 },
8459 { 0x0000f3fc, 0x00204811, 0x000 },
8460 { 0x81000000, 0x00204411, 0x000 },
8461 { 0x00000002, 0x00204811, 0x000 },
8462 { 0x000000ff, 0x00280e30, 0x000 },
8463 { 0x00000000, 0x002f0223, 0x000 },
8464 { 0x00000000, 0x0cc00000, 0x516 },
8465 { 0x00000000, 0xc0200800, 0x000 },
8466 { 0x00000000, 0x14c00000, 0x52b },
8467 { 0x00000000, 0x00200c11, 0x000 },
8468 { 0x0000001c, 0x00203623, 0x000 },
8469 { 0x0000002b, 0x00203623, 0x000 },
8470 { 0x00000029, 0x00203623, 0x000 },
8471 { 0x00000028, 0x00203623, 0x000 },
8472 { 0x00000017, 0x00203623, 0x000 },
8473 { 0x00000025, 0x00203623, 0x000 },
8474 { 0x00000026, 0x00203623, 0x000 },
8475 { 0x00000015, 0x00203623, 0x000 },
8476 { 0x00000016, 0x00203623, 0x000 },
8477 { 0xffffe000, 0x00200c11, 0x000 },
8478 { 0x00000021, 0x00203623, 0x000 },
8479 { 0x00000022, 0x00203623, 0x000 },
8480 { 0x00001fff, 0x00200c11, 0x000 },
8481 { 0x00000023, 0x00203623, 0x000 },
8482 { 0x00000024, 0x00203623, 0x000 },
8483 { 0xf1ffffff, 0x00283a2e, 0x000 },
8484 { 0x0000001a, 0xc0220e20, 0x000 },
8485 { 0x00000000, 0x0029386e, 0x000 },
8486 { 0x81000000, 0x00204411, 0x000 },
8487 { 0x00000006, 0x00204811, 0x000 },
8488 { 0x0000002a, 0x40203620, 0x000 },
8489 { 0x87000000, 0x00204411, 0x000 },
8490 { 0x00000000, 0xc0204800, 0x000 },
8491 { 0x0000a1f4, 0x00204411, 0x000 },
8492 { 0x00000000, 0x00204810, 0x000 },
8493 { 0x00000000, 0x00200c11, 0x000 },
8494 { 0x00000030, 0x00203623, 0x000 },
8495 { 0x9d000000, 0x00204411, 0x000 },
8496 { 0x0000001f, 0x40214a20, 0x000 },
8497 { 0x96000000, 0x00204411, 0x000 },
8498 { 0x00000000, 0xc0204800, 0x000 },
8499 { 0x00000000, 0xc0200c00, 0x000 },
8500 { 0x00000000, 0xc0201000, 0x000 },
8501 { 0x0000001f, 0x00211624, 0x000 },
8502 { 0x00000000, 0x14c00000, 0x000 },
8503 { 0x0000001d, 0x00203623, 0x000 },
8504 { 0x00000003, 0x00281e23, 0x000 },
8505 { 0x00000008, 0x00222223, 0x000 },
8506 { 0xfffff000, 0x00282228, 0x000 },
8507 { 0x00000000, 0x002920e8, 0x000 },
8508 { 0x0000001f, 0x00203628, 0x000 },
8509 { 0x00000018, 0x00211e23, 0x000 },
8510 { 0x00000020, 0x00203627, 0x000 },
8511 { 0x00000002, 0x00221624, 0x000 },
8512 { 0x00000000, 0x003014a8, 0x000 },
8513 { 0x0000001e, 0x00203625, 0x000 },
8514 { 0x00000003, 0x00211a24, 0x000 },
8515 { 0x10000000, 0x00281a26, 0x000 },
8516 { 0xefffffff, 0x00283a2e, 0x000 },
8517 { 0x00000000, 0x004938ce, 0x678 },
8518 { 0x00000001, 0x40280a20, 0x000 },
8519 { 0x00000006, 0x40280e20, 0x000 },
8520 { 0x00000300, 0xc0281220, 0x000 },
8521 { 0x00000008, 0x00211224, 0x000 },
8522 { 0x00000000, 0xc0201620, 0x000 },
8523 { 0x00000000, 0xc0201a20, 0x000 },
8524 { 0x00000000, 0x00210222, 0x000 },
8525 { 0x00000000, 0x14c00000, 0x563 },
8526 { 0x81000000, 0x00204411, 0x000 },
8527 { 0x00000001, 0x00204811, 0x000 },
8528 { 0x00002258, 0x00300a24, 0x000 },
8529 { 0x00040000, 0x00694622, 0x68a },
8530 { 0x00002169, 0x00204411, 0x000 },
8531 { 0x00000000, 0x00204805, 0x000 },
8532 { 0x00020000, 0x00294a26, 0x000 },
8533 { 0x00000000, 0x00204810, 0x000 },
8534 { 0xcafebabe, 0x00204811, 0x000 },
8535 { 0x00000002, 0x002f0223, 0x000 },
8536 { 0x00000000, 0x0cc00000, 0x56b },
8537 { 0x00000000, 0xc0201c10, 0x000 },
8538 { 0x00000000, 0xc0400000, 0x579 },
8539 { 0x00000002, 0x002f0223, 0x000 },
8540 { 0x00000000, 0x0cc00000, 0x56b },
8541 { 0x81000000, 0x00204411, 0x000 },
8542 { 0x00000001, 0x00204811, 0x000 },
8543 { 0x00002258, 0x00300a24, 0x000 },
8544 { 0x00040000, 0x00694622, 0x68a },
8545 { 0x00000000, 0xc0201c10, 0x000 },
8546 { 0x00000000, 0xc0400000, 0x579 },
8547 { 0x00000000, 0x002f0223, 0x000 },
8548 { 0x00000000, 0x0cc00000, 0x56f },
8549 { 0x00000000, 0xc0201c00, 0x000 },
8550 { 0x00000000, 0xc0400000, 0x579 },
8551 { 0x00000004, 0x002f0223, 0x000 },
8552 { 0x00000000, 0x0cc00000, 0x577 },
8553 { 0x81000000, 0x00204411, 0x000 },
8554 { 0x00000000, 0x00204811, 0x000 },
8555 { 0x0000216d, 0x00204411, 0x000 },
8556 { 0x00000000, 0xc0204800, 0x000 },
8557 { 0x00000000, 0xc0604800, 0x68f },
8558 { 0x00000000, 0x00401c10, 0x579 },
8559 { 0x00000000, 0xc0200000, 0x000 },
8560 { 0x00000000, 0xc0400000, 0x000 },
8561 { 0x00000000, 0x0ee00000, 0x57b },
8562 { 0x00000000, 0x00600000, 0x5c6 },
8563 { 0x00000000, 0x002f0224, 0x000 },
8564 { 0x00000000, 0x0cc00000, 0x58c },
8565 { 0x0000a2b7, 0x00204411, 0x000 },
8566 { 0x00000000, 0x00204807, 0x000 },
8567 { 0x81000000, 0x00204411, 0x000 },
8568 { 0x00000001, 0x00204811, 0x000 },
8569 { 0x0004a2b6, 0x00604411, 0x68a },
8570 { 0x0000001a, 0x00212230, 0x000 },
8571 { 0x00000006, 0x00222630, 0x000 },
8572 { 0x00042004, 0x00604411, 0x68a },
8573 { 0x0000a2c4, 0x00204411, 0x000 },
8574 { 0x00000000, 0x003048e9, 0x000 },
8575 { 0x00000000, 0x00e00000, 0x58a },
8576 { 0x0000a2d1, 0x00204411, 0x000 },
8577 { 0x00000000, 0x00404808, 0x000 },
8578 { 0x0000a2d1, 0x00204411, 0x000 },
8579 { 0x00000001, 0x00504a28, 0x000 },
8580 { 0x00000001, 0x002f0224, 0x000 },
8581 { 0x00000000, 0x0cc00000, 0x59d },
8582 { 0x0000a2bb, 0x00204411, 0x000 },
8583 { 0x00000000, 0x00204807, 0x000 },
8584 { 0x81000000, 0x00204411, 0x000 },
8585 { 0x00000001, 0x00204811, 0x000 },
8586 { 0x0004a2ba, 0x00604411, 0x68a },
8587 { 0x0000001a, 0x00212230, 0x000 },
8588 { 0x00000006, 0x00222630, 0x000 },
8589 { 0x00042004, 0x00604411, 0x68a },
8590 { 0x0000a2c5, 0x00204411, 0x000 },
8591 { 0x00000000, 0x003048e9, 0x000 },
8592 { 0x00000000, 0x00e00000, 0x59b },
8593 { 0x0000a2d2, 0x00204411, 0x000 },
8594 { 0x00000000, 0x00404808, 0x000 },
8595 { 0x0000a2d2, 0x00204411, 0x000 },
8596 { 0x00000001, 0x00504a28, 0x000 },
8597 { 0x00000002, 0x002f0224, 0x000 },
8598 { 0x00000000, 0x0cc00000, 0x5ae },
8599 { 0x0000a2bf, 0x00204411, 0x000 },
8600 { 0x00000000, 0x00204807, 0x000 },
8601 { 0x81000000, 0x00204411, 0x000 },
8602 { 0x00000001, 0x00204811, 0x000 },
8603 { 0x0004a2be, 0x00604411, 0x68a },
8604 { 0x0000001a, 0x00212230, 0x000 },
8605 { 0x00000006, 0x00222630, 0x000 },
8606 { 0x00042004, 0x00604411, 0x68a },
8607 { 0x0000a2c6, 0x00204411, 0x000 },
8608 { 0x00000000, 0x003048e9, 0x000 },
8609 { 0x00000000, 0x00e00000, 0x5ac },
8610 { 0x0000a2d3, 0x00204411, 0x000 },
8611 { 0x00000000, 0x00404808, 0x000 },
8612 { 0x0000a2d3, 0x00204411, 0x000 },
8613 { 0x00000001, 0x00504a28, 0x000 },
8614 { 0x0000a2c3, 0x00204411, 0x000 },
8615 { 0x00000000, 0x00204807, 0x000 },
8616 { 0x81000000, 0x00204411, 0x000 },
8617 { 0x00000001, 0x00204811, 0x000 },
8618 { 0x0004a2c2, 0x00604411, 0x68a },
8619 { 0x0000001a, 0x00212230, 0x000 },
8620 { 0x00000006, 0x00222630, 0x000 },
8621 { 0x00042004, 0x00604411, 0x68a },
8622 { 0x0000a2c7, 0x00204411, 0x000 },
8623 { 0x00000000, 0x003048e9, 0x000 },
8624 { 0x00000000, 0x00e00000, 0x5bb },
8625 { 0x0000a2d4, 0x00204411, 0x000 },
8626 { 0x00000000, 0x00404808, 0x000 },
8627 { 0x0000a2d4, 0x00204411, 0x000 },
8628 { 0x00000001, 0x00504a28, 0x000 },
8629 { 0x85000000, 0x00204411, 0x000 },
8630 { 0x00000000, 0x00204801, 0x000 },
8631 { 0x0000304a, 0x00204411, 0x000 },
8632 { 0x01000000, 0x00204811, 0x000 },
8633 { 0x00000000, 0x00400000, 0x5c1 },
8634 { 0xa4000000, 0xc0204411, 0x000 },
8635 { 0x00000000, 0xc0404800, 0x000 },
8636 { 0x00000000, 0xc0600000, 0x5c6 },
8637 { 0x00000000, 0xc0400400, 0x001 },
8638 { 0x0000002c, 0x00203621, 0x000 },
8639 { 0x81000000, 0x00204411, 0x000 },
8640 { 0x00000006, 0x00204811, 0x000 },
8641 { 0x00000000, 0x002f0230, 0x000 },
8642 { 0x00000000, 0x0cc00000, 0x5cd },
8643 { 0x00000000, 0x00200411, 0x000 },
8644 { 0x00000030, 0x00403621, 0x5e0 },
8645 { 0x00000030, 0x0020062d, 0x000 },
8646 { 0x00007e00, 0x00280621, 0x000 },
8647 { 0x00000000, 0x002f0221, 0x000 },
8648 { 0x00000000, 0x0ce00000, 0x5e0 },
8649 { 0x81000000, 0x00204411, 0x000 },
8650 { 0x00000001, 0x00204811, 0x000 },
8651 { 0x0004a092, 0x00604411, 0x68a },
8652 { 0x00000031, 0x00203630, 0x000 },
8653 { 0x0004a093, 0x00604411, 0x68a },
8654 { 0x00000032, 0x00203630, 0x000 },
8655 { 0x0004a2b6, 0x00604411, 0x68a },
8656 { 0x00000033, 0x00203630, 0x000 },
8657 { 0x0004a2ba, 0x00604411, 0x68a },
8658 { 0x00000034, 0x00203630, 0x000 },
8659 { 0x0004a2be, 0x00604411, 0x68a },
8660 { 0x00000035, 0x00203630, 0x000 },
8661 { 0x0004a2c2, 0x00604411, 0x68a },
8662 { 0x00000036, 0x00203630, 0x000 },
8663 { 0x00042004, 0x00604411, 0x68a },
8664 { 0x0001a2a4, 0x00204411, 0x000 },
8665 { 0x0000003f, 0x00204811, 0x000 },
8666 { 0x0000003f, 0x00204811, 0x000 },
8667 { 0x0000003f, 0x00204811, 0x000 },
8668 { 0x0000003f, 0x00204811, 0x000 },
8669 { 0x00000005, 0x00204811, 0x000 },
8670 { 0x0000a1f4, 0x00204411, 0x000 },
8671 { 0x00000000, 0x00204811, 0x000 },
8672 { 0x88000000, 0x00204411, 0x000 },
8673 { 0x00000001, 0x00204811, 0x000 },
8674 { 0x81000000, 0x00204411, 0x000 },
8675 { 0x00000006, 0x00204811, 0x000 },
8676 { 0x00000001, 0x002f0230, 0x000 },
8677 { 0x00000000, 0x0ce00000, 0x629 },
8678 { 0x00000030, 0x0020062d, 0x000 },
8679 { 0x00000000, 0x002f0221, 0x000 },
8680 { 0x00000000, 0x0ce00000, 0x629 },
8681 { 0x81000000, 0x00204411, 0x000 },
8682 { 0x00000001, 0x00204811, 0x000 },
8683 { 0x00007e00, 0x00280621, 0x000 },
8684 { 0x00000000, 0x002f0221, 0x000 },
8685 { 0x00000000, 0x0ce00000, 0x602 },
8686 { 0x0000a092, 0x00204411, 0x000 },
8687 { 0x00000031, 0x00204a2d, 0x000 },
8688 { 0x0000a093, 0x00204411, 0x000 },
8689 { 0x00000032, 0x00204a2d, 0x000 },
8690 { 0x0000a2b6, 0x00204411, 0x000 },
8691 { 0x00000033, 0x00204a2d, 0x000 },
8692 { 0x0000a2ba, 0x00204411, 0x000 },
8693 { 0x00000034, 0x00204a2d, 0x000 },
8694 { 0x0000a2be, 0x00204411, 0x000 },
8695 { 0x00000035, 0x00204a2d, 0x000 },
8696 { 0x0000a2c2, 0x00204411, 0x000 },
8697 { 0x00000036, 0x00204a2d, 0x000 },
8698 { 0x00000030, 0x0020062d, 0x000 },
8699 { 0x000001ff, 0x00280621, 0x000 },
8700 { 0x00000000, 0x002f0221, 0x000 },
8701 { 0x00000000, 0x0ce00000, 0x628 },
8702 { 0x00000000, 0x00210221, 0x000 },
8703 { 0x00000000, 0x14c00000, 0x60b },
8704 { 0x0004a003, 0x00604411, 0x68a },
8705 { 0x0000a003, 0x00204411, 0x000 },
8706 { 0x00000000, 0x00204810, 0x000 },
8707 { 0x00000001, 0x00210621, 0x000 },
8708 { 0x00000000, 0x14c00000, 0x610 },
8709 { 0x0004a010, 0x00604411, 0x68a },
8710 { 0x0000a010, 0x00204411, 0x000 },
8711 { 0x00000000, 0x00204810, 0x000 },
8712 { 0x00000001, 0x00210621, 0x000 },
8713 { 0x00000000, 0x002f0221, 0x000 },
8714 { 0x00000000, 0x0ce00000, 0x628 },
8715 { 0x0004a011, 0x00604411, 0x68a },
8716 { 0x0000a011, 0x00204411, 0x000 },
8717 { 0x00000000, 0x00204810, 0x000 },
8718 { 0x0004a012, 0x00604411, 0x68a },
8719 { 0x0000a012, 0x00204411, 0x000 },
8720 { 0x00000000, 0x00204810, 0x000 },
8721 { 0x0004a013, 0x00604411, 0x68a },
8722 { 0x0000a013, 0x00204411, 0x000 },
8723 { 0x00000000, 0x00204810, 0x000 },
8724 { 0x0004a014, 0x00604411, 0x68a },
8725 { 0x0000a014, 0x00204411, 0x000 },
8726 { 0x00000000, 0x00204810, 0x000 },
8727 { 0x0004a015, 0x00604411, 0x68a },
8728 { 0x0000a015, 0x00204411, 0x000 },
8729 { 0x00000000, 0x00204810, 0x000 },
8730 { 0x0004a016, 0x00604411, 0x68a },
8731 { 0x0000a016, 0x00204411, 0x000 },
8732 { 0x00000000, 0x00204810, 0x000 },
8733 { 0x0004a017, 0x00604411, 0x68a },
8734 { 0x0000a017, 0x00204411, 0x000 },
8735 { 0x00000000, 0x00204810, 0x000 },
8736 { 0x00042004, 0x00604411, 0x68a },
8737 { 0x0000002c, 0x0080062d, 0x000 },
8738 { 0xff000000, 0x00204411, 0x000 },
8739 { 0x00000000, 0x00204811, 0x000 },
8740 { 0x00000001, 0x00204811, 0x000 },
8741 { 0x00000002, 0x00804811, 0x000 },
8742 { 0x00000000, 0x0ee00000, 0x63a },
8743 { 0x00000030, 0x0020062d, 0x000 },
8744 { 0x00000002, 0x00280621, 0x000 },
8745 { 0x00000000, 0x002f0221, 0x000 },
8746 { 0x00000000, 0x0ce00000, 0x638 },
8747 { 0x81000000, 0x00204411, 0x000 },
8748 { 0x00000001, 0x00204811, 0x000 },
8749 { 0x00042004, 0x00604411, 0x68a },
8750 { 0x00001000, 0x00200811, 0x000 },
8751 { 0x0000002b, 0x00203622, 0x000 },
8752 { 0x00000000, 0x00600000, 0x63e },
8753 { 0x00000000, 0x00600000, 0x5c6 },
8754 { 0x98000000, 0x00204411, 0x000 },
8755 { 0x00000000, 0x00804811, 0x000 },
8756 { 0x00000000, 0xc0600000, 0x63e },
8757 { 0x00000000, 0xc0400400, 0x001 },
8758 { 0x0000a2a4, 0x00204411, 0x000 },
8759 { 0x00000022, 0x00204811, 0x000 },
8760 { 0x89000000, 0x00204411, 0x000 },
8761 { 0x00000001, 0x00404811, 0x62a },
8762 { 0x97000000, 0x00204411, 0x000 },
8763 { 0x00000000, 0x00204811, 0x000 },
8764 { 0x8a000000, 0x00204411, 0x000 },
8765 { 0x00000000, 0x00404811, 0x62a },
8766 { 0x00000000, 0x00600000, 0x659 },
8767 { 0x00002010, 0x00204411, 0x000 },
8768 { 0x00008000, 0x00204811, 0x000 },
8769 { 0x0001a2a4, 0xc0204411, 0x000 },
8770 { 0x00000016, 0x00604811, 0x36e },
8771 { 0x00002010, 0x00204411, 0x000 },
8772 { 0x00010000, 0x00204811, 0x000 },
8773 { 0x81000000, 0x00204411, 0x000 },
8774 { 0x00000001, 0x00204811, 0x000 },
8775 { 0x0000217c, 0x00204411, 0x000 },
8776 { 0x09800000, 0x00204811, 0x000 },
8777 { 0xffffffff, 0x00204811, 0x000 },
8778 { 0x00000000, 0x00204811, 0x000 },
8779 { 0x00000000, 0x17000000, 0x000 },
8780 { 0x0004217f, 0x00604411, 0x68a },
8781 { 0x0000001f, 0x00210230, 0x000 },
8782 { 0x00000000, 0x14c00000, 0x000 },
8783 { 0x00000004, 0x00404c11, 0x653 },
8784 { 0x00000000, 0x00400000, 0x000 },
8785 { 0x00000017, 0x00201e2d, 0x000 },
8786 { 0x00000004, 0x00291e27, 0x000 },
8787 { 0x00000017, 0x00803627, 0x000 },
8788 { 0x00000017, 0x00201e2d, 0x000 },
8789 { 0xfffffffb, 0x00281e27, 0x000 },
8790 { 0x00000017, 0x00803627, 0x000 },
8791 { 0x00000017, 0x00201e2d, 0x000 },
8792 { 0x00000008, 0x00291e27, 0x000 },
8793 { 0x00000017, 0x00803627, 0x000 },
8794 { 0x00000017, 0x00201e2d, 0x000 },
8795 { 0xfffffff7, 0x00281e27, 0x000 },
8796 { 0x00000017, 0x00803627, 0x000 },
8797 { 0x00002010, 0x00204411, 0x000 },
8798 { 0x00008000, 0x00204811, 0x000 },
8799 { 0x0001a2a4, 0x00204411, 0x000 },
8800 { 0x00000016, 0x00604811, 0x36e },
8801 { 0x00002010, 0x00204411, 0x000 },
8802 { 0x00010000, 0x00204811, 0x000 },
8803 { 0x0000217c, 0x00204411, 0x000 },
8804 { 0x01800000, 0x00204811, 0x000 },
8805 { 0xffffffff, 0x00204811, 0x000 },
8806 { 0x00000000, 0x00204811, 0x000 },
8807 { 0x00000000, 0x17000000, 0x000 },
8808 { 0x81000000, 0x00204411, 0x000 },
8809 { 0x00000001, 0x00204811, 0x000 },
8810 { 0x0004217f, 0x00604411, 0x68a },
8811 { 0x0000001f, 0x00210230, 0x000 },
8812 { 0x00000000, 0x14c00000, 0x689 },
8813 { 0x00000010, 0x00404c11, 0x66f },
8814 { 0x00000000, 0xc0200400, 0x000 },
8815 { 0x00000000, 0x38c00000, 0x000 },
8816 { 0x0000001d, 0x00200a2d, 0x000 },
8817 { 0x0000001e, 0x00200e2d, 0x000 },
8818 { 0x0000001f, 0x0020122d, 0x000 },
8819 { 0x00000020, 0x0020162d, 0x000 },
8820 { 0x00002169, 0x00204411, 0x000 },
8821 { 0x00000000, 0x00204804, 0x000 },
8822 { 0x00000000, 0x00204805, 0x000 },
8823 { 0x00000000, 0x00204801, 0x000 },
8824 { 0xcafebabe, 0x00204811, 0x000 },
8825 { 0x00000004, 0x00301224, 0x000 },
8826 { 0x00000000, 0x002f0064, 0x000 },
8827 { 0x00000000, 0x0cc00000, 0x688 },
8828 { 0x00000003, 0x00281a22, 0x000 },
8829 { 0x00000008, 0x00221222, 0x000 },
8830 { 0xfffff000, 0x00281224, 0x000 },
8831 { 0x00000000, 0x002910c4, 0x000 },
8832 { 0x0000001f, 0x00403624, 0x000 },
8833 { 0x00000000, 0x00800000, 0x000 },
8834 { 0x00000000, 0x1ac00000, 0x68a },
8835 { 0x9f000000, 0x00204411, 0x000 },
8836 { 0xcafebabe, 0x00204811, 0x000 },
8837 { 0x00000000, 0x1ae00000, 0x68d },
8838 { 0x00000000, 0x00800000, 0x000 },
8839 { 0x00000000, 0x1ac00000, 0x68f },
8840 { 0x9e000000, 0x00204411, 0x000 },
8841 { 0xcafebabe, 0x00204811, 0x000 },
8842 { 0x00000000, 0x1ae00000, 0x692 },
8843 { 0x00000000, 0x00800000, 0x000 },
8844 { 0x00000000, 0x00600000, 0x00b },
8845 { 0x00001000, 0x00600411, 0x315 },
8846 { 0x00000000, 0x00200411, 0x000 },
8847 { 0x00000000, 0x00600811, 0x1b2 },
8848 { 0x0000225c, 0x00204411, 0x000 },
8849 { 0x00000003, 0x00204811, 0x000 },
8850 { 0x00002256, 0x00204411, 0x000 },
8851 { 0x0000001b, 0x00204811, 0x000 },
8852 { 0x0000a1fc, 0x00204411, 0x000 },
8853 { 0x00000001, 0x00204811, 0x000 },
8854 { 0x0001a1fd, 0xc0204411, 0x000 },
8855 { 0x00000021, 0x00201e2d, 0x000 },
8856 { 0x00000010, 0x00221e27, 0x000 },
8857 { 0x00000024, 0x0020222d, 0x000 },
8858 { 0x0000ffff, 0x00282228, 0x000 },
8859 { 0x00000000, 0x00294907, 0x000 },
8860 { 0x00000000, 0x00204811, 0x000 },
8861 { 0x00000022, 0x0020222d, 0x000 },
8862 { 0x0000ffff, 0x00282228, 0x000 },
8863 { 0x00000000, 0x00294907, 0x000 },
8864 { 0x00000000, 0x00204811, 0x000 },
8865 { 0x00000023, 0x00201e2d, 0x000 },
8866 { 0x00000010, 0x00221e27, 0x000 },
8867 { 0x00000000, 0x00294907, 0x000 },
8868 { 0x00000000, 0x00404811, 0x000 },
8869 { 0x00000000, 0x00000000, 0x000 },
8870 { 0x00000000, 0x00000000, 0x000 },
8871 { 0x00000000, 0x00000000, 0x000 },
8872 { 0x00000000, 0x00000000, 0x000 },
8873 { 0x00000000, 0x00000000, 0x000 },
8874 { 0x00000000, 0x00000000, 0x000 },
8875 { 0x00000000, 0x00000000, 0x000 },
8876 { 0x00000000, 0x00000000, 0x000 },
8877 { 0x00000000, 0x00000000, 0x000 },
8878 { 0x00000000, 0x00000000, 0x000 },
8879 { 0x00000000, 0x00000000, 0x000 },
8880 { 0x00000000, 0x00000000, 0x000 },
8881 { 0x00000000, 0x00000000, 0x000 },
8882 { 0x00000000, 0x00000000, 0x000 },
8883 { 0x00000000, 0x00000000, 0x000 },
8884 { 0x00000000, 0x00000000, 0x000 },
8885 { 0x00000000, 0x00000000, 0x000 },
8886 { 0x00000000, 0x00000000, 0x000 },
8887 { 0x00000000, 0x00000000, 0x000 },
8888 { 0x00000000, 0x00000000, 0x000 },
8889 { 0x00000000, 0x00000000, 0x000 },
8890 { 0x00000000, 0x00000000, 0x000 },
8891 { 0x00000000, 0x00000000, 0x000 },
8892 { 0x00000000, 0x00000000, 0x000 },
8893 { 0x00000000, 0x00000000, 0x000 },
8894 { 0x00000000, 0x00000000, 0x000 },
8895 { 0x00000000, 0x00000000, 0x000 },
8896 { 0x00000000, 0x00000000, 0x000 },
8897 { 0x00000000, 0x00000000, 0x000 },
8898 { 0x00000000, 0x00000000, 0x000 },
8899 { 0x00000000, 0x00000000, 0x000 },
8900 { 0x00000000, 0x00000000, 0x000 },
8901 { 0x00000000, 0x00000000, 0x000 },
8902 { 0x00000000, 0x00000000, 0x000 },
8903 { 0x00000000, 0x00000000, 0x000 },
8904 { 0x00000000, 0x00000000, 0x000 },
8905 { 0x00000000, 0x00000000, 0x000 },
8906 { 0x00000000, 0x00000000, 0x000 },
8907 { 0x00000000, 0x00000000, 0x000 },
8908 { 0x00000000, 0x00000000, 0x000 },
8909 { 0x00000000, 0x00000000, 0x000 },
8910 { 0x00000000, 0x00000000, 0x000 },
8911 { 0x00000000, 0x00000000, 0x000 },
8912 { 0x00000000, 0x00000000, 0x000 },
8913 { 0x00000000, 0x00000000, 0x000 },
8914 { 0x00000000, 0x00000000, 0x000 },
8915 { 0x00000000, 0x00000000, 0x000 },
8916 { 0x00000000, 0x00000000, 0x000 },
8917 { 0x00000000, 0x00000000, 0x000 },
8918 { 0x00000000, 0x00000000, 0x000 },
8919 { 0x00000000, 0x00000000, 0x000 },
8920 { 0x00000000, 0x00000000, 0x000 },
8921 { 0x00000000, 0x00000000, 0x000 },
8922 { 0x00000000, 0x00000000, 0x000 },
8923 { 0x00000000, 0x00000000, 0x000 },
8924 { 0x014204ff, 0x05bd0250, 0x000 },
8925 { 0x01c30168, 0x043f05bd, 0x000 },
8926 { 0x02250209, 0x02500151, 0x000 },
8927 { 0x02230245, 0x02a00241, 0x000 },
8928 { 0x03d705bd, 0x05bd05bd, 0x000 },
8929 { 0x06460647, 0x031f05bd, 0x000 },
8930 { 0x05bd05c2, 0x03200340, 0x000 },
8931 { 0x032a0282, 0x03420334, 0x000 },
8932 { 0x05bd05bd, 0x05bd05bd, 0x000 },
8933 { 0x05bd054e, 0x05bd05bd, 0x000 },
8934 { 0x03ba05bd, 0x04b80344, 0x000 },
8935 { 0x0497044d, 0x043d05bd, 0x000 },
8936 { 0x04cd05bd, 0x044104da, 0x000 },
8937 { 0x044d0504, 0x03510375, 0x000 },
8938 { 0x05bd05bd, 0x05bd05bd, 0x000 },
8939 { 0x05bd05bd, 0x05bd05bd, 0x000 },
8940 { 0x05bd05bd, 0x063c05c4, 0x000 },
8941 { 0x05bd05bd, 0x000705bd, 0x000 },
8942 { 0x05bd05bd, 0x05bd05bd, 0x000 },
8943 { 0x05bd05bd, 0x05bd05bd, 0x000 },
8944 { 0x03f803ed, 0x04080406, 0x000 },
8945 { 0x040e040a, 0x040c0410, 0x000 },
8946 { 0x041c0418, 0x04240420, 0x000 },
8947 { 0x042c0428, 0x04340430, 0x000 },
8948 { 0x05bd05bd, 0x043805bd, 0x000 },
8949 { 0x05bd05bd, 0x05bd05bd, 0x000 },
8950 { 0x05bd05bd, 0x05bd05bd, 0x000 },
8951 { 0x00020676, 0x06940006, 0x000 },
8952};
8953
8954static const u32 RV630_pfp_microcode[] = {
89550xca0400,
89560xa00000,
89570x7e828b,
89580x7c038b,
89590x8001b8,
89600x7c038b,
89610xd4401e,
89620xee001e,
89630xca0400,
89640xa00000,
89650x7e828b,
89660xc41838,
89670xca2400,
89680xca2800,
89690x9581a8,
89700xc41c3a,
89710xc3c000,
89720xca0800,
89730xca0c00,
89740x7c744b,
89750xc20005,
89760x99c000,
89770xc41c3a,
89780x7c744c,
89790xc0fff0,
89800x042c04,
89810x309002,
89820x7d2500,
89830x351402,
89840x7d350b,
89850x255403,
89860x7cd580,
89870x259c03,
89880x95c004,
89890xd5001b,
89900x7eddc1,
89910x7d9d80,
89920xd6801b,
89930xd5801b,
89940xd4401e,
89950xd5401e,
89960xd6401e,
89970xd6801e,
89980xd4801e,
89990xd4c01e,
90000x9783d3,
90010xd5c01e,
90020xca0800,
90030x80001a,
90040xca0c00,
90050xe4011e,
90060xd4001e,
90070x80000c,
90080xc41838,
90090xe4013e,
90100xd4001e,
90110x80000c,
90120xc41838,
90130xd4401e,
90140xee001e,
90150xca0400,
90160xa00000,
90170x7e828b,
90180xe4011e,
90190xd4001e,
90200xd4401e,
90210xee001e,
90220xca0400,
90230xa00000,
90240x7e828b,
90250xe4013e,
90260xd4001e,
90270xd4401e,
90280xee001e,
90290xca0400,
90300xa00000,
90310x7e828b,
90320xca1800,
90330xd4401e,
90340xd5801e,
90350x800053,
90360xd40075,
90370xd4401e,
90380xca0800,
90390xca0c00,
90400xca1000,
90410xd48019,
90420xd4c018,
90430xd50017,
90440xd4801e,
90450xd4c01e,
90460xd5001e,
90470xe2001e,
90480xca0400,
90490xa00000,
90500x7e828b,
90510xca0800,
90520xd48060,
90530xd4401e,
90540x800000,
90550xd4801e,
90560xca0800,
90570xd48061,
90580xd4401e,
90590x800000,
90600xd4801e,
90610xca0800,
90620xca0c00,
90630xd4401e,
90640xd48016,
90650xd4c016,
90660xd4801e,
90670x8001b8,
90680xd4c01e,
90690xc60843,
90700xca0c00,
90710xca1000,
90720x948004,
90730xca1400,
90740xe420f3,
90750xd42013,
90760xd56065,
90770xd4e01c,
90780xd5201c,
90790xd5601c,
90800x800000,
90810x062001,
90820xc60843,
90830xca0c00,
90840xca1000,
90850x9483f7,
90860xca1400,
90870xe420f3,
90880x800079,
90890xd42013,
90900xc60843,
90910xca0c00,
90920xca1000,
90930x9883ef,
90940xca1400,
90950xd40064,
90960x80008d,
90970x000000,
90980xc41432,
90990xc61843,
91000xc4082f,
91010x954005,
91020xc40c30,
91030xd4401e,
91040x800000,
91050xee001e,
91060x9583f5,
91070xc41031,
91080xd44033,
91090xd52065,
91100xd4a01c,
91110xd4e01c,
91120xd5201c,
91130xe4015e,
91140xd4001e,
91150x800000,
91160x062001,
91170xca1800,
91180x0a2001,
91190xd60076,
91200xc40836,
91210x988007,
91220xc61045,
91230x950110,
91240xd4001f,
91250xd46062,
91260x800000,
91270xd42062,
91280xcc3835,
91290xcc1433,
91300x8401bb,
91310xd40072,
91320xd5401e,
91330x800000,
91340xee001e,
91350xe2001a,
91360x8401bb,
91370xe2001a,
91380xcc104b,
91390xcc0447,
91400x2c9401,
91410x7d098b,
91420x984005,
91430x7d15cb,
91440xd4001a,
91450x8001b8,
91460xd4006d,
91470x344401,
91480xcc0c48,
91490x98403a,
91500xcc2c4a,
91510x958004,
91520xcc0449,
91530x8001b8,
91540xd4001a,
91550xd4c01a,
91560x282801,
91570x8400f0,
91580xcc1003,
91590x98801b,
91600x04380c,
91610x8400f0,
91620xcc1003,
91630x988017,
91640x043808,
91650x8400f0,
91660xcc1003,
91670x988013,
91680x043804,
91690x8400f0,
91700xcc1003,
91710x988014,
91720xcc104c,
91730x9a8009,
91740xcc144d,
91750x9840dc,
91760xd4006d,
91770xcc1848,
91780xd5001a,
91790xd5401a,
91800x8000c9,
91810xd5801a,
91820x96c0d5,
91830xd4006d,
91840x8001b8,
91850xd4006e,
91860x9ac003,
91870xd4006d,
91880xd4006e,
91890x800000,
91900xec007f,
91910x9ac0cc,
91920xd4006d,
91930x8001b8,
91940xd4006e,
91950xcc1403,
91960xcc1803,
91970xcc1c03,
91980x7d9103,
91990x7dd583,
92000x7d190c,
92010x35cc1f,
92020x35701f,
92030x7cf0cb,
92040x7cd08b,
92050x880000,
92060x7e8e8b,
92070x95c004,
92080xd4006e,
92090x8001b8,
92100xd4001a,
92110xd4c01a,
92120xcc0803,
92130xcc0c03,
92140xcc1003,
92150xcc1403,
92160xcc1803,
92170xcc1c03,
92180xcc2403,
92190xcc2803,
92200x35c41f,
92210x36b01f,
92220x7c704b,
92230x34f01f,
92240x7c704b,
92250x35701f,
92260x7c704b,
92270x7d8881,
92280x7dccc1,
92290x7e5101,
92300x7e9541,
92310x7c9082,
92320x7cd4c2,
92330x7c848b,
92340x9ac003,
92350x7c8c8b,
92360x2c8801,
92370x98809e,
92380xd4006d,
92390x98409c,
92400xd4006e,
92410xcc084c,
92420xcc0c4d,
92430xcc1048,
92440xd4801a,
92450xd4c01a,
92460x800101,
92470xd5001a,
92480xcc0832,
92490xd40032,
92500x9482d9,
92510xca0c00,
92520xd4401e,
92530x800000,
92540xd4001e,
92550xe4011e,
92560xd4001e,
92570xca0800,
92580xca0c00,
92590xca1000,
92600xd4401e,
92610xca1400,
92620xd4801e,
92630xd4c01e,
92640xd5001e,
92650xd5401e,
92660xd54034,
92670x800000,
92680xee001e,
92690x280404,
92700xe2001a,
92710xe2001a,
92720xd4401a,
92730xca3800,
92740xcc0803,
92750xcc0c03,
92760xcc0c03,
92770xcc0c03,
92780x9882bd,
92790x000000,
92800x8401bb,
92810xd7a06f,
92820x800000,
92830xee001f,
92840xca0400,
92850xc2ff00,
92860xcc0834,
92870xc13fff,
92880x7c74cb,
92890x7cc90b,
92900x7d010f,
92910x9902b0,
92920x7c738b,
92930x8401bb,
92940xd7a06f,
92950x800000,
92960xee001f,
92970xca0800,
92980x281900,
92990x7d898b,
93000x958014,
93010x281404,
93020xca0c00,
93030xca1000,
93040xca1c00,
93050xca2400,
93060xe2001f,
93070xd4c01a,
93080xd5001a,
93090xd5401a,
93100xcc1803,
93110xcc2c03,
93120xcc2c03,
93130xcc2c03,
93140x7da58b,
93150x7d9c47,
93160x984297,
93170x000000,
93180x800161,
93190xd4c01a,
93200xd4401e,
93210xd4801e,
93220x800000,
93230xee001e,
93240xe4011e,
93250xd4001e,
93260xd4401e,
93270xee001e,
93280xca0400,
93290xa00000,
93300x7e828b,
93310xe4013e,
93320xd4001e,
93330xd4401e,
93340xee001e,
93350xca0400,
93360xa00000,
93370x7e828b,
93380xca0800,
93390x248c06,
93400x0ccc06,
93410x98c006,
93420xcc104e,
93430x990004,
93440xd40073,
93450xe4011e,
93460xd4001e,
93470xd4401e,
93480xd4801e,
93490x800000,
93500xee001e,
93510xca0800,
93520xca0c00,
93530x34d018,
93540x251001,
93550x950021,
93560xc17fff,
93570xca1000,
93580xca1400,
93590xca1800,
93600xd4801d,
93610xd4c01d,
93620x7db18b,
93630xc14202,
93640xc2c001,
93650xd5801d,
93660x34dc0e,
93670x7d5d4c,
93680x7f734c,
93690xd7401e,
93700xd5001e,
93710xd5401e,
93720xc14200,
93730xc2c000,
93740x099c01,
93750x31dc10,
93760x7f5f4c,
93770x7f734c,
93780x042802,
93790x7d8380,
93800xd5a86f,
93810xd58066,
93820xd7401e,
93830xec005e,
93840xc82402,
93850xc82402,
93860x8001b8,
93870xd60076,
93880xd4401e,
93890xd4801e,
93900xd4c01e,
93910x800000,
93920xee001e,
93930x800000,
93940xee001f,
93950xd4001f,
93960x800000,
93970xd4001f,
93980xd4001f,
93990x880000,
94000xd4001f,
94010x000000,
94020x000000,
94030x000000,
94040x000000,
94050x000000,
94060x000000,
94070x000000,
94080x000000,
94090x000000,
94100x000000,
94110x000000,
94120x000000,
94130x000000,
94140x000000,
94150x000000,
94160x000000,
94170x000000,
94180x000000,
94190x000000,
94200x000000,
94210x000000,
94220x000000,
94230x000000,
94240x000000,
94250x000000,
94260x000000,
94270x000000,
94280x000000,
94290x000000,
94300x000000,
94310x000000,
94320x000000,
94330x000000,
94340x000000,
94350x000000,
94360x000000,
94370x000000,
94380x000000,
94390x000000,
94400x000000,
94410x000000,
94420x000000,
94430x000000,
94440x000000,
94450x000000,
94460x000000,
94470x000000,
94480x000000,
94490x000000,
94500x000000,
94510x000000,
94520x000000,
94530x000000,
94540x000000,
94550x000000,
94560x000000,
94570x000000,
94580x000000,
94590x000000,
94600x000000,
94610x000000,
94620x000000,
94630x000000,
94640x000000,
94650x000000,
94660x000000,
94670x010171,
94680x020178,
94690x03008f,
94700x04007f,
94710x050003,
94720x06003f,
94730x070032,
94740x08012c,
94750x090046,
94760x0a0036,
94770x1001b6,
94780x1700a2,
94790x22013a,
94800x230149,
94810x2000b4,
94820x240125,
94830x27004d,
94840x28006a,
94850x2a0060,
94860x2b0052,
94870x2f0065,
94880x320087,
94890x34017f,
94900x3c0156,
94910x3f0072,
94920x41018c,
94930x44012e,
94940x550173,
94950x56017a,
94960x60000b,
94970x610034,
94980x620038,
94990x630038,
95000x640038,
95010x650038,
95020x660038,
95030x670038,
95040x68003a,
95050x690041,
95060x6a0048,
95070x6b0048,
95080x6c0048,
95090x6d0048,
95100x6e0048,
95110x6f0048,
95120x000006,
95130x000006,
95140x000006,
95150x000006,
95160x000006,
95170x000006,
95180x000006,
95190x000006,
95200x000006,
95210x000006,
95220x000006,
95230x000006,
95240x000006,
95250x000006,
95260x000006,
95270x000006,
95280x000006,
95290x000006,
95300x000006,
9531};
9532
9533static const u32 RV635_cp_microcode[][3] = {
9534 { 0x00000000, 0xc0200400, 0x000 },
9535 { 0x00000000, 0x00a0000a, 0x000 },
9536 { 0x0000ffff, 0x00284621, 0x000 },
9537 { 0x00000000, 0xd9004800, 0x000 },
9538 { 0x00000000, 0xc0200400, 0x000 },
9539 { 0x00000000, 0x00a0000a, 0x000 },
9540 { 0x00000000, 0x00e00000, 0x000 },
9541 { 0x00010000, 0xc0294620, 0x000 },
9542 { 0x00000000, 0xd9004800, 0x000 },
9543 { 0x00000000, 0xc0200400, 0x000 },
9544 { 0x00000000, 0x00a0000a, 0x000 },
9545 { 0x81000000, 0x00204411, 0x000 },
9546 { 0x00000001, 0x00204811, 0x000 },
9547 { 0x00042004, 0x00604411, 0x68a },
9548 { 0x00000000, 0x00600000, 0x62e },
9549 { 0x00000000, 0x00600000, 0x642 },
9550 { 0x00000000, 0xc0200800, 0x000 },
9551 { 0x00000f00, 0x00281622, 0x000 },
9552 { 0x00000008, 0x00211625, 0x000 },
9553 { 0x00000018, 0x00203625, 0x000 },
9554 { 0x8d000000, 0x00204411, 0x000 },
9555 { 0x00000004, 0x002f0225, 0x000 },
9556 { 0x00000000, 0x0ce00000, 0x018 },
9557 { 0x00412000, 0x00404811, 0x019 },
9558 { 0x00422000, 0x00204811, 0x000 },
9559 { 0x8e000000, 0x00204411, 0x000 },
9560 { 0x00000028, 0x00204a2d, 0x000 },
9561 { 0x90000000, 0x00204411, 0x000 },
9562 { 0x00000000, 0x00204805, 0x000 },
9563 { 0x0000000c, 0x00211622, 0x000 },
9564 { 0x00000003, 0x00281625, 0x000 },
9565 { 0x00000019, 0x00211a22, 0x000 },
9566 { 0x00000004, 0x00281a26, 0x000 },
9567 { 0x00000000, 0x002914c5, 0x000 },
9568 { 0x00000019, 0x00203625, 0x000 },
9569 { 0x00000000, 0x003a1402, 0x000 },
9570 { 0x00000016, 0x00211625, 0x000 },
9571 { 0x00000003, 0x00281625, 0x000 },
9572 { 0x00000017, 0x00200e2d, 0x000 },
9573 { 0xfffffffc, 0x00280e23, 0x000 },
9574 { 0x00000000, 0x002914a3, 0x000 },
9575 { 0x00000017, 0x00203625, 0x000 },
9576 { 0x00008000, 0x00280e22, 0x000 },
9577 { 0x00000007, 0x00220e23, 0x000 },
9578 { 0x00000000, 0x0029386e, 0x000 },
9579 { 0x20000000, 0x00280e22, 0x000 },
9580 { 0x00000006, 0x00210e23, 0x000 },
9581 { 0x00000000, 0x0029386e, 0x000 },
9582 { 0x00000000, 0x00220222, 0x000 },
9583 { 0x00000000, 0x14e00000, 0x038 },
9584 { 0x00000000, 0x2ee00000, 0x035 },
9585 { 0x00000000, 0x2ce00000, 0x037 },
9586 { 0x00000000, 0x00400e2d, 0x039 },
9587 { 0x00000008, 0x00200e2d, 0x000 },
9588 { 0x00000009, 0x0040122d, 0x046 },
9589 { 0x00000001, 0x00400e2d, 0x039 },
9590 { 0x00000000, 0xc0200c00, 0x000 },
9591 { 0x003ffffc, 0x00281223, 0x000 },
9592 { 0x00000002, 0x00221224, 0x000 },
9593 { 0x0000001f, 0x00211e23, 0x000 },
9594 { 0x00000000, 0x14e00000, 0x03e },
9595 { 0x00000008, 0x00401c11, 0x041 },
9596 { 0x0000000d, 0x00201e2d, 0x000 },
9597 { 0x0000000f, 0x00281e27, 0x000 },
9598 { 0x00000003, 0x00221e27, 0x000 },
9599 { 0x7fc00000, 0x00281a23, 0x000 },
9600 { 0x00000014, 0x00211a26, 0x000 },
9601 { 0x00000001, 0x00331a26, 0x000 },
9602 { 0x00000008, 0x00221a26, 0x000 },
9603 { 0x00000000, 0x00290cc7, 0x000 },
9604 { 0x00000027, 0x00203624, 0x000 },
9605 { 0x00007f00, 0x00281221, 0x000 },
9606 { 0x00001400, 0x002f0224, 0x000 },
9607 { 0x00000000, 0x0ce00000, 0x04b },
9608 { 0x00000001, 0x00290e23, 0x000 },
9609 { 0x0000000e, 0x00203623, 0x000 },
9610 { 0x0000e000, 0x00204411, 0x000 },
9611 { 0xfff80000, 0x00294a23, 0x000 },
9612 { 0x00000000, 0x003a2c02, 0x000 },
9613 { 0x00000002, 0x00220e2b, 0x000 },
9614 { 0xfc000000, 0x00280e23, 0x000 },
9615 { 0x0000000f, 0x00203623, 0x000 },
9616 { 0x00001fff, 0x00294a23, 0x000 },
9617 { 0x00000027, 0x00204a2d, 0x000 },
9618 { 0x00000000, 0x00204811, 0x000 },
9619 { 0x00000029, 0x00200e2d, 0x000 },
9620 { 0x060a0200, 0x00294a23, 0x000 },
9621 { 0x00000000, 0x00204811, 0x000 },
9622 { 0x00000000, 0x00204811, 0x000 },
9623 { 0x00000001, 0x00210222, 0x000 },
9624 { 0x00000000, 0x14e00000, 0x061 },
9625 { 0x00000000, 0x2ee00000, 0x05f },
9626 { 0x00000000, 0x2ce00000, 0x05e },
9627 { 0x00000000, 0x00400e2d, 0x062 },
9628 { 0x00000001, 0x00400e2d, 0x062 },
9629 { 0x0000000a, 0x00200e2d, 0x000 },
9630 { 0x0000000b, 0x0040122d, 0x06a },
9631 { 0x00000000, 0xc0200c00, 0x000 },
9632 { 0x003ffffc, 0x00281223, 0x000 },
9633 { 0x00000002, 0x00221224, 0x000 },
9634 { 0x7fc00000, 0x00281623, 0x000 },
9635 { 0x00000014, 0x00211625, 0x000 },
9636 { 0x00000001, 0x00331625, 0x000 },
9637 { 0x80000000, 0x00280e23, 0x000 },
9638 { 0x00000000, 0x00290ca3, 0x000 },
9639 { 0x3ffffc00, 0x00290e23, 0x000 },
9640 { 0x0000001f, 0x00211e23, 0x000 },
9641 { 0x00000000, 0x14e00000, 0x06d },
9642 { 0x00000100, 0x00401c11, 0x070 },
9643 { 0x0000000d, 0x00201e2d, 0x000 },
9644 { 0x000000f0, 0x00281e27, 0x000 },
9645 { 0x00000004, 0x00221e27, 0x000 },
9646 { 0x81000000, 0x00204411, 0x000 },
9647 { 0x0000000d, 0x00204811, 0x000 },
9648 { 0xfffff0ff, 0x00281a30, 0x000 },
9649 { 0x0000a028, 0x00204411, 0x000 },
9650 { 0x00000000, 0x002948e6, 0x000 },
9651 { 0x0000a018, 0x00204411, 0x000 },
9652 { 0x3fffffff, 0x00284a23, 0x000 },
9653 { 0x0000a010, 0x00204411, 0x000 },
9654 { 0x00000000, 0x00204804, 0x000 },
9655 { 0x00000030, 0x0020162d, 0x000 },
9656 { 0x00000002, 0x00291625, 0x000 },
9657 { 0x00000030, 0x00203625, 0x000 },
9658 { 0x00000025, 0x0020162d, 0x000 },
9659 { 0x00000000, 0x002f00a3, 0x000 },
9660 { 0x00000000, 0x0cc00000, 0x083 },
9661 { 0x00000026, 0x0020162d, 0x000 },
9662 { 0x00000000, 0x002f00a4, 0x000 },
9663 { 0x00000000, 0x0cc00000, 0x084 },
9664 { 0x00000000, 0x00400000, 0x08a },
9665 { 0x00000025, 0x00203623, 0x000 },
9666 { 0x00000026, 0x00203624, 0x000 },
9667 { 0x00000017, 0x00201e2d, 0x000 },
9668 { 0x00000002, 0x00210227, 0x000 },
9669 { 0x00000000, 0x14e00000, 0x08a },
9670 { 0x00000000, 0x00600000, 0x665 },
9671 { 0x00000000, 0x00600000, 0x659 },
9672 { 0x00000002, 0x00210e22, 0x000 },
9673 { 0x00000000, 0x14c00000, 0x08d },
9674 { 0x00000012, 0xc0403620, 0x093 },
9675 { 0x00000000, 0x2ee00000, 0x091 },
9676 { 0x00000000, 0x2ce00000, 0x090 },
9677 { 0x00000002, 0x00400e2d, 0x092 },
9678 { 0x00000003, 0x00400e2d, 0x092 },
9679 { 0x0000000c, 0x00200e2d, 0x000 },
9680 { 0x00000012, 0x00203623, 0x000 },
9681 { 0x00000003, 0x00210e22, 0x000 },
9682 { 0x00000000, 0x14c00000, 0x098 },
9683 { 0x0000a00c, 0x00204411, 0x000 },
9684 { 0x00000000, 0xc0204800, 0x000 },
9685 { 0x00000000, 0xc0404800, 0x0a0 },
9686 { 0x0000a00c, 0x00204411, 0x000 },
9687 { 0x00000000, 0x00204811, 0x000 },
9688 { 0x00000000, 0x2ee00000, 0x09e },
9689 { 0x00000000, 0x2ce00000, 0x09d },
9690 { 0x00000002, 0x00400e2d, 0x09f },
9691 { 0x00000003, 0x00400e2d, 0x09f },
9692 { 0x0000000c, 0x00200e2d, 0x000 },
9693 { 0x00000000, 0x00204803, 0x000 },
9694 { 0x00000000, 0x003a0c02, 0x000 },
9695 { 0x003f0000, 0x00280e23, 0x000 },
9696 { 0x00000010, 0x00210e23, 0x000 },
9697 { 0x00000011, 0x00203623, 0x000 },
9698 { 0x0000001e, 0x0021022b, 0x000 },
9699 { 0x00000000, 0x14c00000, 0x0a7 },
9700 { 0x00000016, 0xc0203620, 0x000 },
9701 { 0x0000001f, 0x0021022b, 0x000 },
9702 { 0x00000000, 0x14c00000, 0x0aa },
9703 { 0x00000015, 0xc0203620, 0x000 },
9704 { 0x00000008, 0x00210e2b, 0x000 },
9705 { 0x0000007f, 0x00280e23, 0x000 },
9706 { 0x00000000, 0x002f0223, 0x000 },
9707 { 0x00000000, 0x0ce00000, 0x0e1 },
9708 { 0x00000000, 0x27000000, 0x000 },
9709 { 0x00000000, 0x00600000, 0x2a3 },
9710 { 0x00000001, 0x002f0223, 0x000 },
9711 { 0x00000000, 0x0ae00000, 0x0b3 },
9712 { 0x00000000, 0x00600000, 0x13a },
9713 { 0x81000000, 0x00204411, 0x000 },
9714 { 0x00000006, 0x00204811, 0x000 },
9715 { 0x0000000c, 0x00221e30, 0x000 },
9716 { 0x99800000, 0x00204411, 0x000 },
9717 { 0x00000004, 0x0020122d, 0x000 },
9718 { 0x00000008, 0x00221224, 0x000 },
9719 { 0x00000010, 0x00201811, 0x000 },
9720 { 0x00000000, 0x00291ce4, 0x000 },
9721 { 0x00000000, 0x00604807, 0x12f },
9722 { 0x9b000000, 0x00204411, 0x000 },
9723 { 0x00000000, 0x00204802, 0x000 },
9724 { 0x9c000000, 0x00204411, 0x000 },
9725 { 0x00000000, 0x0033146f, 0x000 },
9726 { 0x00000001, 0x00333e23, 0x000 },
9727 { 0x00000000, 0xd9004800, 0x000 },
9728 { 0x00000000, 0x00203c05, 0x000 },
9729 { 0x81000000, 0x00204411, 0x000 },
9730 { 0x0000000e, 0x00204811, 0x000 },
9731 { 0x00000000, 0x00201010, 0x000 },
9732 { 0x0000e007, 0x00204411, 0x000 },
9733 { 0x0000000f, 0x0021022b, 0x000 },
9734 { 0x00000000, 0x14c00000, 0x0cb },
9735 { 0x00f8ff08, 0x00204811, 0x000 },
9736 { 0x98000000, 0x00404811, 0x0dc },
9737 { 0x000000f0, 0x00280e22, 0x000 },
9738 { 0x000000a0, 0x002f0223, 0x000 },
9739 { 0x00000000, 0x0cc00000, 0x0da },
9740 { 0x00000011, 0x00200e2d, 0x000 },
9741 { 0x00000001, 0x002f0223, 0x000 },
9742 { 0x00000000, 0x0ce00000, 0x0d5 },
9743 { 0x00000002, 0x002f0223, 0x000 },
9744 { 0x00000000, 0x0ce00000, 0x0d4 },
9745 { 0x00003f00, 0x00400c11, 0x0d6 },
9746 { 0x00001f00, 0x00400c11, 0x0d6 },
9747 { 0x00000f00, 0x00200c11, 0x000 },
9748 { 0x00380009, 0x00294a23, 0x000 },
9749 { 0x3f000000, 0x00280e2b, 0x000 },
9750 { 0x00000002, 0x00220e23, 0x000 },
9751 { 0x00000007, 0x00494a23, 0x0dc },
9752 { 0x00380f09, 0x00204811, 0x000 },
9753 { 0x68000007, 0x00204811, 0x000 },
9754 { 0x00000008, 0x00214a27, 0x000 },
9755 { 0x00000000, 0x00204811, 0x000 },
9756 { 0x060a0200, 0x00294a24, 0x000 },
9757 { 0x00000000, 0x00204811, 0x000 },
9758 { 0x00000000, 0x00204811, 0x000 },
9759 { 0x0000a202, 0x00204411, 0x000 },
9760 { 0x00ff0000, 0x00280e22, 0x000 },
9761 { 0x00000080, 0x00294a23, 0x000 },
9762 { 0x00000027, 0x00200e2d, 0x000 },
9763 { 0x00000026, 0x0020122d, 0x000 },
9764 { 0x00000000, 0x002f0083, 0x000 },
9765 { 0x00000000, 0x0ce00000, 0x0ea },
9766 { 0x00000000, 0x00600000, 0x65f },
9767 { 0x00000000, 0x00400000, 0x0eb },
9768 { 0x00000000, 0x00600000, 0x662 },
9769 { 0x00000007, 0x0020222d, 0x000 },
9770 { 0x00000005, 0x00220e22, 0x000 },
9771 { 0x00100000, 0x00280e23, 0x000 },
9772 { 0x00000000, 0x00292068, 0x000 },
9773 { 0x00000000, 0x003a0c02, 0x000 },
9774 { 0x000000ef, 0x00280e23, 0x000 },
9775 { 0x00000000, 0x00292068, 0x000 },
9776 { 0x00000017, 0x00200e2d, 0x000 },
9777 { 0x00000003, 0x00210223, 0x000 },
9778 { 0x00000000, 0x14e00000, 0x0f8 },
9779 { 0x0000000b, 0x00210228, 0x000 },
9780 { 0x00000000, 0x14c00000, 0x0f8 },
9781 { 0x00000400, 0x00292228, 0x000 },
9782 { 0x00000014, 0x00203628, 0x000 },
9783 { 0x0000001c, 0x00210e22, 0x000 },
9784 { 0x00000000, 0x14c00000, 0x0fd },
9785 { 0x0000a30c, 0x00204411, 0x000 },
9786 { 0x00000000, 0x00204811, 0x000 },
9787 { 0x0000001e, 0x00210e22, 0x000 },
9788 { 0x00000000, 0x14c00000, 0x10b },
9789 { 0x0000a30f, 0x00204411, 0x000 },
9790 { 0x00000011, 0x00200e2d, 0x000 },
9791 { 0x00000001, 0x002f0223, 0x000 },
9792 { 0x00000000, 0x0cc00000, 0x104 },
9793 { 0xffffffff, 0x00404811, 0x10b },
9794 { 0x00000002, 0x002f0223, 0x000 },
9795 { 0x00000000, 0x0cc00000, 0x107 },
9796 { 0x0000ffff, 0x00404811, 0x10b },
9797 { 0x00000004, 0x002f0223, 0x000 },
9798 { 0x00000000, 0x0cc00000, 0x10a },
9799 { 0x000000ff, 0x00404811, 0x10b },
9800 { 0x00000001, 0x00204811, 0x000 },
9801 { 0x0002c400, 0x00204411, 0x000 },
9802 { 0x0000001f, 0x00210e22, 0x000 },
9803 { 0x00000000, 0x14c00000, 0x112 },
9804 { 0x00000010, 0x40210e20, 0x000 },
9805 { 0x00000013, 0x00203623, 0x000 },
9806 { 0x00000018, 0x40224a20, 0x000 },
9807 { 0x00000010, 0xc0424a20, 0x114 },
9808 { 0x00000000, 0x00200c11, 0x000 },
9809 { 0x00000013, 0x00203623, 0x000 },
9810 { 0x00000000, 0x00204811, 0x000 },
9811 { 0x00000000, 0x00204811, 0x000 },
9812 { 0x0000000a, 0x00201011, 0x000 },
9813 { 0x00000000, 0x002f0224, 0x000 },
9814 { 0x00000000, 0x0ce00000, 0x11b },
9815 { 0x00000000, 0x00204811, 0x000 },
9816 { 0x00000001, 0x00531224, 0x117 },
9817 { 0xffbfffff, 0x00283a2e, 0x000 },
9818 { 0x0000001b, 0x00210222, 0x000 },
9819 { 0x00000000, 0x14c00000, 0x12e },
9820 { 0x81000000, 0x00204411, 0x000 },
9821 { 0x0000000d, 0x00204811, 0x000 },
9822 { 0x00000018, 0x00220e30, 0x000 },
9823 { 0xfc000000, 0x00280e23, 0x000 },
9824 { 0x81000000, 0x00204411, 0x000 },
9825 { 0x0000000e, 0x00204811, 0x000 },
9826 { 0x00000000, 0x00201010, 0x000 },
9827 { 0x0000e00e, 0x00204411, 0x000 },
9828 { 0x07f8ff08, 0x00204811, 0x000 },
9829 { 0x00000000, 0x00294a23, 0x000 },
9830 { 0x0000001c, 0x00201e2d, 0x000 },
9831 { 0x00000008, 0x00214a27, 0x000 },
9832 { 0x00000000, 0x00204811, 0x000 },
9833 { 0x060a0200, 0x00294a24, 0x000 },
9834 { 0x00000000, 0x00204811, 0x000 },
9835 { 0x00000000, 0x00204811, 0x000 },
9836 { 0x00000000, 0x00800000, 0x000 },
9837 { 0x81000000, 0x00204411, 0x000 },
9838 { 0x00000001, 0x00204811, 0x000 },
9839 { 0x0000217c, 0x00204411, 0x000 },
9840 { 0x00800000, 0x00204811, 0x000 },
9841 { 0x00000000, 0x00204806, 0x000 },
9842 { 0x00000008, 0x00214a27, 0x000 },
9843 { 0x00000000, 0x17000000, 0x000 },
9844 { 0x0004217f, 0x00604411, 0x68a },
9845 { 0x0000001f, 0x00210230, 0x000 },
9846 { 0x00000000, 0x14c00000, 0x689 },
9847 { 0x00000004, 0x00404c11, 0x135 },
9848 { 0x81000000, 0x00204411, 0x000 },
9849 { 0x00000001, 0x00204811, 0x000 },
9850 { 0x000021f8, 0x00204411, 0x000 },
9851 { 0x0000001c, 0x00204811, 0x000 },
9852 { 0x000421f9, 0x00604411, 0x68a },
9853 { 0x00000011, 0x00210230, 0x000 },
9854 { 0x00000000, 0x14e00000, 0x13c },
9855 { 0x00000000, 0x00800000, 0x000 },
9856 { 0x00000000, 0x00600000, 0x00b },
9857 { 0x00000000, 0x00600411, 0x315 },
9858 { 0x00000000, 0x00200411, 0x000 },
9859 { 0x00000000, 0x00600811, 0x1b2 },
9860 { 0x00000000, 0x00600000, 0x160 },
9861 { 0x0000ffff, 0x40280e20, 0x000 },
9862 { 0x00000010, 0xc0211220, 0x000 },
9863 { 0x0000ffff, 0x40280620, 0x000 },
9864 { 0x00000010, 0xc0210a20, 0x000 },
9865 { 0x00000000, 0x00341461, 0x000 },
9866 { 0x00000000, 0x00741882, 0x2bb },
9867 { 0x0001a1fd, 0x00604411, 0x2e0 },
9868 { 0x00003fff, 0x002f022f, 0x000 },
9869 { 0x00000000, 0x0cc00000, 0x147 },
9870 { 0x00000000, 0xc0400400, 0x001 },
9871 { 0x00000000, 0x00600000, 0x00b },
9872 { 0x00000000, 0x00600411, 0x315 },
9873 { 0x00000000, 0x00200411, 0x000 },
9874 { 0x00000000, 0x00600811, 0x1b2 },
9875 { 0x00003fff, 0x002f022f, 0x000 },
9876 { 0x00000000, 0x0ce00000, 0x000 },
9877 { 0x00000000, 0x00600000, 0x160 },
9878 { 0x00000010, 0x40210e20, 0x000 },
9879 { 0x0000ffff, 0xc0281220, 0x000 },
9880 { 0x00000010, 0x40211620, 0x000 },
9881 { 0x0000ffff, 0xc0681a20, 0x2bb },
9882 { 0x0001a1fd, 0x00604411, 0x2e0 },
9883 { 0x00003fff, 0x002f022f, 0x000 },
9884 { 0x00000000, 0x0cc00000, 0x158 },
9885 { 0x00000000, 0xc0400400, 0x001 },
9886 { 0x0000225c, 0x00204411, 0x000 },
9887 { 0x00000001, 0x00300a2f, 0x000 },
9888 { 0x00000001, 0x00210a22, 0x000 },
9889 { 0x00000003, 0x00384a22, 0x000 },
9890 { 0x00002256, 0x00204411, 0x000 },
9891 { 0x0000001a, 0x00204811, 0x000 },
9892 { 0x0000a1fc, 0x00204411, 0x000 },
9893 { 0x00000001, 0x00804811, 0x000 },
9894 { 0x00000000, 0x00600000, 0x00b },
9895 { 0x00000000, 0x00600000, 0x18f },
9896 { 0x00000000, 0x00600000, 0x1a0 },
9897 { 0x00003fff, 0x002f022f, 0x000 },
9898 { 0x00000000, 0x0ce00000, 0x000 },
9899 { 0x00000000, 0x00202c08, 0x000 },
9900 { 0x00000000, 0x00202411, 0x000 },
9901 { 0x00000000, 0x00202811, 0x000 },
9902 { 0x00002256, 0x00204411, 0x000 },
9903 { 0x00000016, 0x00204811, 0x000 },
9904 { 0x0000225c, 0x00204411, 0x000 },
9905 { 0x00000003, 0x00204811, 0x000 },
9906 { 0x93800000, 0x00204411, 0x000 },
9907 { 0x00000002, 0x00221e29, 0x000 },
9908 { 0x00000000, 0x007048eb, 0x19c },
9909 { 0x00000000, 0x00600000, 0x2bb },
9910 { 0x00000001, 0x40330620, 0x000 },
9911 { 0x00000000, 0xc0302409, 0x000 },
9912 { 0x00003fff, 0x002f022f, 0x000 },
9913 { 0x00000000, 0x0ce00000, 0x000 },
9914 { 0x00000000, 0x00600000, 0x2a3 },
9915 { 0x00000000, 0x002f0221, 0x000 },
9916 { 0x00000000, 0x0ae00000, 0x181 },
9917 { 0x00000000, 0x00600000, 0x13a },
9918 { 0x00000000, 0x00400000, 0x186 },
9919 { 0x95000000, 0x00204411, 0x000 },
9920 { 0x00000000, 0x002f0221, 0x000 },
9921 { 0x00000000, 0x0ce00000, 0x186 },
9922 { 0x00000000, 0xc0204800, 0x000 },
9923 { 0x00000001, 0x00530621, 0x182 },
9924 { 0x92000000, 0x00204411, 0x000 },
9925 { 0x00000000, 0xc0604800, 0x197 },
9926 { 0x0001a1fd, 0x00204411, 0x000 },
9927 { 0x00000011, 0x0020062d, 0x000 },
9928 { 0x00000000, 0x0078042a, 0x2fb },
9929 { 0x00000000, 0x00202809, 0x000 },
9930 { 0x00003fff, 0x002f022f, 0x000 },
9931 { 0x00000000, 0x0cc00000, 0x174 },
9932 { 0x00000000, 0xc0400400, 0x001 },
9933 { 0x00000210, 0x00600411, 0x315 },
9934 { 0x00003fff, 0x002f022f, 0x000 },
9935 { 0x00000000, 0x0ce00000, 0x194 },
9936 { 0x00000015, 0xc0203620, 0x000 },
9937 { 0x00000016, 0xc0203620, 0x000 },
9938 { 0x3f800000, 0x00200411, 0x000 },
9939 { 0x46000000, 0x00600811, 0x1b2 },
9940 { 0x00000000, 0x00800000, 0x000 },
9941 { 0x0000a1fc, 0x00204411, 0x000 },
9942 { 0x00003fff, 0x002f022f, 0x000 },
9943 { 0x00000000, 0x0cc00000, 0x19b },
9944 { 0x00000001, 0x00804811, 0x000 },
9945 { 0x00000021, 0x00804811, 0x000 },
9946 { 0x0000ffff, 0x40280e20, 0x000 },
9947 { 0x00000010, 0xc0211220, 0x000 },
9948 { 0x0000ffff, 0x40281620, 0x000 },
9949 { 0x00000010, 0xc0811a20, 0x000 },
9950 { 0x81000000, 0x00204411, 0x000 },
9951 { 0x00000006, 0x00204811, 0x000 },
9952 { 0x00000008, 0x00221e30, 0x000 },
9953 { 0x00000029, 0x00201a2d, 0x000 },
9954 { 0x0000e000, 0x00204411, 0x000 },
9955 { 0xfffbff09, 0x00204811, 0x000 },
9956 { 0x0000000f, 0x0020222d, 0x000 },
9957 { 0x00001fff, 0x00294a28, 0x000 },
9958 { 0x00000006, 0x0020222d, 0x000 },
9959 { 0x00000000, 0x002920e8, 0x000 },
9960 { 0x00000000, 0x00204808, 0x000 },
9961 { 0x00000000, 0x00204811, 0x000 },
9962 { 0x060a0200, 0x00294a26, 0x000 },
9963 { 0x00000000, 0x00204811, 0x000 },
9964 { 0x00000000, 0x00204811, 0x000 },
9965 { 0x00000100, 0x00201811, 0x000 },
9966 { 0x00000008, 0x00621e28, 0x12f },
9967 { 0x00000008, 0x00822228, 0x000 },
9968 { 0x0002c000, 0x00204411, 0x000 },
9969 { 0x00000015, 0x00600e2d, 0x1bd },
9970 { 0x00000016, 0x00600e2d, 0x1bd },
9971 { 0x0000c008, 0x00204411, 0x000 },
9972 { 0x00000017, 0x00200e2d, 0x000 },
9973 { 0x00000000, 0x14c00000, 0x1b9 },
9974 { 0x00000000, 0x00200411, 0x000 },
9975 { 0x00000000, 0x00204801, 0x000 },
9976 { 0x39000000, 0x00204811, 0x000 },
9977 { 0x00000000, 0x00204811, 0x000 },
9978 { 0x00000000, 0x00804802, 0x000 },
9979 { 0x00000018, 0x00202e2d, 0x000 },
9980 { 0x00000000, 0x003b0d63, 0x000 },
9981 { 0x00000008, 0x00224a23, 0x000 },
9982 { 0x00000010, 0x00224a23, 0x000 },
9983 { 0x00000018, 0x00224a23, 0x000 },
9984 { 0x00000000, 0x00804803, 0x000 },
9985 { 0x00000000, 0x00600000, 0x00b },
9986 { 0x00001000, 0x00600411, 0x315 },
9987 { 0x00000000, 0x00200411, 0x000 },
9988 { 0x00000000, 0x00600811, 0x1b2 },
9989 { 0x00000007, 0x0021062f, 0x000 },
9990 { 0x00000013, 0x00200a2d, 0x000 },
9991 { 0x00000001, 0x00202c11, 0x000 },
9992 { 0x0000ffff, 0x40282220, 0x000 },
9993 { 0x0000000f, 0x00262228, 0x000 },
9994 { 0x00000010, 0x40212620, 0x000 },
9995 { 0x0000000f, 0x00262629, 0x000 },
9996 { 0x00000000, 0x00202802, 0x000 },
9997 { 0x00002256, 0x00204411, 0x000 },
9998 { 0x0000001b, 0x00204811, 0x000 },
9999 { 0x00000000, 0x002f0221, 0x000 },
10000 { 0x00000000, 0x0ce00000, 0x1e0 },
10001 { 0x0000225c, 0x00204411, 0x000 },
10002 { 0x00000081, 0x00204811, 0x000 },
10003 { 0x0000a1fc, 0x00204411, 0x000 },
10004 { 0x00000001, 0x00204811, 0x000 },
10005 { 0x00000080, 0x00201c11, 0x000 },
10006 { 0x00000000, 0x002f0227, 0x000 },
10007 { 0x00000000, 0x0ce00000, 0x1dc },
10008 { 0x00000000, 0x00600000, 0x1e9 },
10009 { 0x00000001, 0x00531e27, 0x1d8 },
10010 { 0x00000001, 0x00202c11, 0x000 },
10011 { 0x0000001f, 0x00280a22, 0x000 },
10012 { 0x0000001f, 0x00282a2a, 0x000 },
10013 { 0x00000001, 0x00530621, 0x1d1 },
10014 { 0x0000225c, 0x00204411, 0x000 },
10015 { 0x00000002, 0x00304a2f, 0x000 },
10016 { 0x0000a1fc, 0x00204411, 0x000 },
10017 { 0x00000001, 0x00204811, 0x000 },
10018 { 0x00000001, 0x00301e2f, 0x000 },
10019 { 0x00000000, 0x002f0227, 0x000 },
10020 { 0x00000000, 0x0ce00000, 0x000 },
10021 { 0x00000000, 0x00600000, 0x1e9 },
10022 { 0x00000001, 0x00531e27, 0x1e5 },
10023 { 0x0000ffff, 0x40280e20, 0x000 },
10024 { 0x0000000f, 0x00260e23, 0x000 },
10025 { 0x00000010, 0xc0211220, 0x000 },
10026 { 0x0000000f, 0x00261224, 0x000 },
10027 { 0x00000000, 0x00201411, 0x000 },
10028 { 0x00000000, 0x00601811, 0x2bb },
10029 { 0x0001a1fd, 0x00204411, 0x000 },
10030 { 0x00000000, 0x002f022b, 0x000 },
10031 { 0x00000000, 0x0ce00000, 0x1f8 },
10032 { 0x00000010, 0x00221628, 0x000 },
10033 { 0xffff0000, 0x00281625, 0x000 },
10034 { 0x0000ffff, 0x00281a29, 0x000 },
10035 { 0x00000000, 0x002948c5, 0x000 },
10036 { 0x00000000, 0x0020480a, 0x000 },
10037 { 0x00000000, 0x00202c11, 0x000 },
10038 { 0x00000010, 0x00221623, 0x000 },
10039 { 0xffff0000, 0x00281625, 0x000 },
10040 { 0x0000ffff, 0x00281a24, 0x000 },
10041 { 0x00000000, 0x002948c5, 0x000 },
10042 { 0x00000000, 0x00731503, 0x205 },
10043 { 0x00000000, 0x00201805, 0x000 },
10044 { 0x00000000, 0x00731524, 0x205 },
10045 { 0x00000000, 0x002d14c5, 0x000 },
10046 { 0x00000000, 0x003008a2, 0x000 },
10047 { 0x00000000, 0x00204802, 0x000 },
10048 { 0x00000000, 0x00202802, 0x000 },
10049 { 0x00000000, 0x00202003, 0x000 },
10050 { 0x00000000, 0x00802404, 0x000 },
10051 { 0x0000000f, 0x00210225, 0x000 },
10052 { 0x00000000, 0x14c00000, 0x689 },
10053 { 0x00000000, 0x002b1405, 0x000 },
10054 { 0x00000001, 0x00901625, 0x000 },
10055 { 0x00000000, 0x00600000, 0x00b },
10056 { 0x00000000, 0x00600411, 0x315 },
10057 { 0x00000000, 0x00200411, 0x000 },
10058 { 0x00000000, 0x00600811, 0x1b2 },
10059 { 0x00002256, 0x00204411, 0x000 },
10060 { 0x0000001a, 0x00294a22, 0x000 },
10061 { 0x00000000, 0xc0200000, 0x000 },
10062 { 0x00003fff, 0x002f022f, 0x000 },
10063 { 0x00000000, 0x0ce00000, 0x000 },
10064 { 0x00000000, 0xc0200400, 0x000 },
10065 { 0x0000225c, 0x00204411, 0x000 },
10066 { 0x00000003, 0x00384a21, 0x000 },
10067 { 0x0000a1fc, 0x00204411, 0x000 },
10068 { 0x00000001, 0x00204811, 0x000 },
10069 { 0x0000ffff, 0x40281220, 0x000 },
10070 { 0x00000010, 0xc0211a20, 0x000 },
10071 { 0x0000ffff, 0x40280e20, 0x000 },
10072 { 0x00000010, 0xc0211620, 0x000 },
10073 { 0x00000000, 0x00741465, 0x2bb },
10074 { 0x0001a1fd, 0x00604411, 0x2e0 },
10075 { 0x00000001, 0x00330621, 0x000 },
10076 { 0x00000000, 0x002f0221, 0x000 },
10077 { 0x00000000, 0x0cc00000, 0x219 },
10078 { 0x00003fff, 0x002f022f, 0x000 },
10079 { 0x00000000, 0x0cc00000, 0x212 },
10080 { 0x00000000, 0xc0400400, 0x001 },
10081 { 0x00000000, 0x00600000, 0x642 },
10082 { 0x00000000, 0x0040040f, 0x213 },
10083 { 0x00000000, 0x00600000, 0x62e },
10084 { 0x00000000, 0x00600000, 0x642 },
10085 { 0x00000210, 0x00600411, 0x315 },
10086 { 0x00000000, 0x00600000, 0x1a0 },
10087 { 0x00000000, 0x00600000, 0x19c },
10088 { 0x00000000, 0x00600000, 0x2bb },
10089 { 0x00000000, 0x00600000, 0x2a3 },
10090 { 0x93800000, 0x00204411, 0x000 },
10091 { 0x00000000, 0x00204808, 0x000 },
10092 { 0x00000000, 0x002f022f, 0x000 },
10093 { 0x00000000, 0x0ae00000, 0x232 },
10094 { 0x00000000, 0x00600000, 0x13a },
10095 { 0x00000000, 0x00400000, 0x236 },
10096 { 0x95000000, 0x00204411, 0x000 },
10097 { 0x00000000, 0x002f022f, 0x000 },
10098 { 0x00000000, 0x0ce00000, 0x236 },
10099 { 0x00000000, 0xc0404800, 0x233 },
10100 { 0x92000000, 0x00204411, 0x000 },
10101 { 0x00000000, 0xc0204800, 0x000 },
10102 { 0x00002256, 0x00204411, 0x000 },
10103 { 0x00000016, 0x00204811, 0x000 },
10104 { 0x0000225c, 0x00204411, 0x000 },
10105 { 0x00000003, 0x00204811, 0x000 },
10106 { 0x0000a1fc, 0x00204411, 0x000 },
10107 { 0x00000001, 0x00204811, 0x000 },
10108 { 0x0001a1fd, 0x00204411, 0x000 },
10109 { 0x00000000, 0x00600411, 0x2fb },
10110 { 0x00000000, 0xc0400400, 0x001 },
10111 { 0x00000000, 0x00600000, 0x62e },
10112 { 0x0000a00c, 0x00204411, 0x000 },
10113 { 0x00000000, 0xc0204800, 0x000 },
10114 { 0x00000000, 0xc0404800, 0x000 },
10115 { 0x00000000, 0x00600000, 0x00b },
10116 { 0x00000018, 0x40210a20, 0x000 },
10117 { 0x00000003, 0x002f0222, 0x000 },
10118 { 0x00000000, 0x0ae00000, 0x24c },
10119 { 0x00000014, 0x0020222d, 0x000 },
10120 { 0x00080101, 0x00292228, 0x000 },
10121 { 0x00000014, 0x00203628, 0x000 },
10122 { 0x0000a30c, 0x00204411, 0x000 },
10123 { 0x00000000, 0xc0204800, 0x000 },
10124 { 0x00000000, 0xc0204800, 0x000 },
10125 { 0x00000000, 0xc0404800, 0x251 },
10126 { 0x00000000, 0x00600000, 0x00b },
10127 { 0x00000010, 0x00600411, 0x315 },
10128 { 0x3f800000, 0x00200411, 0x000 },
10129 { 0x00000000, 0x00600811, 0x1b2 },
10130 { 0x0000225c, 0x00204411, 0x000 },
10131 { 0x00000003, 0x00204811, 0x000 },
10132 { 0x00000000, 0x00600000, 0x27c },
10133 { 0x00000017, 0x00201e2d, 0x000 },
10134 { 0x00000001, 0x00211e27, 0x000 },
10135 { 0x00000000, 0x14e00000, 0x26a },
10136 { 0x00000012, 0x00201e2d, 0x000 },
10137 { 0x0000ffff, 0x00281e27, 0x000 },
10138 { 0x00000000, 0x00341c27, 0x000 },
10139 { 0x00000000, 0x12c00000, 0x25f },
10140 { 0x00000000, 0x00201c11, 0x000 },
10141 { 0x00000000, 0x002f00e5, 0x000 },
10142 { 0x00000000, 0x08c00000, 0x262 },
10143 { 0x00000000, 0x00201407, 0x000 },
10144 { 0x00000012, 0x00201e2d, 0x000 },
10145 { 0x00000010, 0x00211e27, 0x000 },
10146 { 0x00000000, 0x00341c47, 0x000 },
10147 { 0x00000000, 0x12c00000, 0x267 },
10148 { 0x00000000, 0x00201c11, 0x000 },
10149 { 0x00000000, 0x002f00e6, 0x000 },
10150 { 0x00000000, 0x08c00000, 0x26a },
10151 { 0x00000000, 0x00201807, 0x000 },
10152 { 0x00000000, 0x00600000, 0x2c1 },
10153 { 0x00002256, 0x00204411, 0x000 },
10154 { 0x00000000, 0x00342023, 0x000 },
10155 { 0x00000000, 0x12c00000, 0x272 },
10156 { 0x00000000, 0x00342044, 0x000 },
10157 { 0x00000000, 0x12c00000, 0x271 },
10158 { 0x00000016, 0x00404811, 0x276 },
10159 { 0x00000018, 0x00404811, 0x276 },
10160 { 0x00000000, 0x00342044, 0x000 },
10161 { 0x00000000, 0x12c00000, 0x275 },
10162 { 0x00000017, 0x00404811, 0x276 },
10163 { 0x00000019, 0x00204811, 0x000 },
10164 { 0x0000a1fc, 0x00204411, 0x000 },
10165 { 0x00000001, 0x00204811, 0x000 },
10166 { 0x0001a1fd, 0x00604411, 0x2e9 },
10167 { 0x00003fff, 0x002f022f, 0x000 },
10168 { 0x00000000, 0x0cc00000, 0x256 },
10169 { 0x00000000, 0xc0400400, 0x001 },
10170 { 0x00000010, 0x40210620, 0x000 },
10171 { 0x0000ffff, 0xc0280a20, 0x000 },
10172 { 0x00000010, 0x40210e20, 0x000 },
10173 { 0x0000ffff, 0xc0281220, 0x000 },
10174 { 0x00000010, 0x40211620, 0x000 },
10175 { 0x0000ffff, 0xc0881a20, 0x000 },
10176 { 0x81000000, 0x00204411, 0x000 },
10177 { 0x00000001, 0x00204811, 0x000 },
10178 { 0x00042004, 0x00604411, 0x68a },
10179 { 0x00000000, 0x00600000, 0x62e },
10180 { 0x00000000, 0xc0600000, 0x2a3 },
10181 { 0x00000005, 0x00200a2d, 0x000 },
10182 { 0x00000008, 0x00220a22, 0x000 },
10183 { 0x0000002b, 0x00201a2d, 0x000 },
10184 { 0x0000001c, 0x00201e2d, 0x000 },
10185 { 0x00007000, 0x00281e27, 0x000 },
10186 { 0x00000000, 0x00311ce6, 0x000 },
10187 { 0x0000002a, 0x00201a2d, 0x000 },
10188 { 0x0000000c, 0x00221a26, 0x000 },
10189 { 0x00000000, 0x002f00e6, 0x000 },
10190 { 0x00000000, 0x06e00000, 0x292 },
10191 { 0x00000000, 0x00201c11, 0x000 },
10192 { 0x00000000, 0x00200c11, 0x000 },
10193 { 0x0000002b, 0x00203623, 0x000 },
10194 { 0x00000010, 0x00201811, 0x000 },
10195 { 0x00000000, 0x00691ce2, 0x12f },
10196 { 0x93800000, 0x00204411, 0x000 },
10197 { 0x00000000, 0x00204807, 0x000 },
10198 { 0x95000000, 0x00204411, 0x000 },
10199 { 0x00000000, 0x002f022f, 0x000 },
10200 { 0x00000000, 0x0ce00000, 0x29d },
10201 { 0x00000001, 0x00333e2f, 0x000 },
10202 { 0x00000000, 0xd9004800, 0x000 },
10203 { 0x92000000, 0x00204411, 0x000 },
10204 { 0x00000000, 0xc0204800, 0x000 },
10205 { 0x0000001c, 0x00403627, 0x000 },
10206 { 0x0000000c, 0xc0220a20, 0x000 },
10207 { 0x00000029, 0x00203622, 0x000 },
10208 { 0x00000028, 0xc0403620, 0x000 },
10209 { 0x0000a2a4, 0x00204411, 0x000 },
10210 { 0x00000009, 0x00204811, 0x000 },
10211 { 0xa1000000, 0x00204411, 0x000 },
10212 { 0x00000001, 0x00804811, 0x000 },
10213 { 0x00000021, 0x00201e2d, 0x000 },
10214 { 0x00000000, 0x002c1ce3, 0x000 },
10215 { 0x00000021, 0x00203627, 0x000 },
10216 { 0x00000022, 0x00201e2d, 0x000 },
10217 { 0x00000000, 0x002c1ce4, 0x000 },
10218 { 0x00000022, 0x00203627, 0x000 },
10219 { 0x00000023, 0x00201e2d, 0x000 },
10220 { 0x00000000, 0x003120a3, 0x000 },
10221 { 0x00000000, 0x002d1d07, 0x000 },
10222 { 0x00000023, 0x00203627, 0x000 },
10223 { 0x00000024, 0x00201e2d, 0x000 },
10224 { 0x00000000, 0x003120c4, 0x000 },
10225 { 0x00000000, 0x002d1d07, 0x000 },
10226 { 0x00000024, 0x00803627, 0x000 },
10227 { 0x00000021, 0x00203623, 0x000 },
10228 { 0x00000022, 0x00203624, 0x000 },
10229 { 0x00000000, 0x00311ca3, 0x000 },
10230 { 0x00000023, 0x00203627, 0x000 },
10231 { 0x00000000, 0x00311cc4, 0x000 },
10232 { 0x00000024, 0x00803627, 0x000 },
10233 { 0x0000001a, 0x00203627, 0x000 },
10234 { 0x0000001b, 0x00203628, 0x000 },
10235 { 0x00000017, 0x00201e2d, 0x000 },
10236 { 0x00000002, 0x00210227, 0x000 },
10237 { 0x00000000, 0x14c00000, 0x2dc },
10238 { 0x00000000, 0x00400000, 0x2d9 },
10239 { 0x0000001a, 0x00203627, 0x000 },
10240 { 0x0000001b, 0x00203628, 0x000 },
10241 { 0x00000017, 0x00201e2d, 0x000 },
10242 { 0x00000002, 0x00210227, 0x000 },
10243 { 0x00000000, 0x14e00000, 0x2d9 },
10244 { 0x00000003, 0x00210227, 0x000 },
10245 { 0x00000000, 0x14e00000, 0x2dc },
10246 { 0x00000023, 0x00201e2d, 0x000 },
10247 { 0x00000000, 0x002e00e1, 0x000 },
10248 { 0x00000000, 0x02c00000, 0x2dc },
10249 { 0x00000021, 0x00201e2d, 0x000 },
10250 { 0x00000000, 0x003120a1, 0x000 },
10251 { 0x00000000, 0x002e00e8, 0x000 },
10252 { 0x00000000, 0x06c00000, 0x2dc },
10253 { 0x00000024, 0x00201e2d, 0x000 },
10254 { 0x00000000, 0x002e00e2, 0x000 },
10255 { 0x00000000, 0x02c00000, 0x2dc },
10256 { 0x00000022, 0x00201e2d, 0x000 },
10257 { 0x00000000, 0x003120c2, 0x000 },
10258 { 0x00000000, 0x002e00e8, 0x000 },
10259 { 0x00000000, 0x06c00000, 0x2dc },
10260 { 0x00000000, 0x00600000, 0x665 },
10261 { 0x00000000, 0x00600000, 0x2b5 },
10262 { 0x00000000, 0x00400000, 0x2de },
10263 { 0x00000000, 0x00600000, 0x2b5 },
10264 { 0x00000000, 0x00600000, 0x65c },
10265 { 0x00000000, 0x00400000, 0x2de },
10266 { 0x00000000, 0x00600000, 0x2a7 },
10267 { 0x00000000, 0x00400000, 0x2de },
10268 { 0x0000001a, 0x00201e2d, 0x000 },
10269 { 0x0000001b, 0x0080222d, 0x000 },
10270 { 0x00000010, 0x00221e23, 0x000 },
10271 { 0x00000000, 0x00294887, 0x000 },
10272 { 0x00000000, 0x00311ca3, 0x000 },
10273 { 0x00000010, 0x00221e27, 0x000 },
10274 { 0x00000000, 0x00294887, 0x000 },
10275 { 0x00000010, 0x00221e23, 0x000 },
10276 { 0x00000000, 0x003120c4, 0x000 },
10277 { 0x0000ffff, 0x00282228, 0x000 },
10278 { 0x00000000, 0x00894907, 0x000 },
10279 { 0x00000010, 0x00221e23, 0x000 },
10280 { 0x00000000, 0x00294887, 0x000 },
10281 { 0x00000010, 0x00221e21, 0x000 },
10282 { 0x00000000, 0x00294847, 0x000 },
10283 { 0x00000000, 0x00311ca3, 0x000 },
10284 { 0x00000010, 0x00221e27, 0x000 },
10285 { 0x00000000, 0x00294887, 0x000 },
10286 { 0x00000000, 0x00311ca1, 0x000 },
10287 { 0x00000010, 0x00221e27, 0x000 },
10288 { 0x00000000, 0x00294847, 0x000 },
10289 { 0x00000010, 0x00221e23, 0x000 },
10290 { 0x00000000, 0x003120c4, 0x000 },
10291 { 0x0000ffff, 0x00282228, 0x000 },
10292 { 0x00000000, 0x00294907, 0x000 },
10293 { 0x00000010, 0x00221e21, 0x000 },
10294 { 0x00000000, 0x003120c2, 0x000 },
10295 { 0x0000ffff, 0x00282228, 0x000 },
10296 { 0x00000000, 0x00894907, 0x000 },
10297 { 0x00000010, 0x00221e23, 0x000 },
10298 { 0x00000000, 0x00294887, 0x000 },
10299 { 0x00000001, 0x00220a21, 0x000 },
10300 { 0x00000000, 0x003308a2, 0x000 },
10301 { 0x00000010, 0x00221e22, 0x000 },
10302 { 0x00000010, 0x00212222, 0x000 },
10303 { 0x00000000, 0x00294907, 0x000 },
10304 { 0x00000000, 0x00311ca3, 0x000 },
10305 { 0x00000010, 0x00221e27, 0x000 },
10306 { 0x00000000, 0x00294887, 0x000 },
10307 { 0x00000001, 0x00220a21, 0x000 },
10308 { 0x00000000, 0x003008a2, 0x000 },
10309 { 0x00000010, 0x00221e22, 0x000 },
10310 { 0x00000010, 0x00212222, 0x000 },
10311 { 0x00000000, 0x00294907, 0x000 },
10312 { 0x00000010, 0x00221e23, 0x000 },
10313 { 0x00000000, 0x003120c4, 0x000 },
10314 { 0x0000ffff, 0x00282228, 0x000 },
10315 { 0x00000000, 0x00294907, 0x000 },
10316 { 0x00000000, 0x003808c5, 0x000 },
10317 { 0x00000000, 0x00300841, 0x000 },
10318 { 0x00000001, 0x00220a22, 0x000 },
10319 { 0x00000000, 0x003308a2, 0x000 },
10320 { 0x00000010, 0x00221e22, 0x000 },
10321 { 0x00000010, 0x00212222, 0x000 },
10322 { 0x00000000, 0x00894907, 0x000 },
10323 { 0x00000017, 0x0020222d, 0x000 },
10324 { 0x00000000, 0x14c00000, 0x318 },
10325 { 0xffffffef, 0x00280621, 0x000 },
10326 { 0x00000014, 0x0020222d, 0x000 },
10327 { 0x0000f8e0, 0x00204411, 0x000 },
10328 { 0x00000000, 0x00294901, 0x000 },
10329 { 0x00000000, 0x00894901, 0x000 },
10330 { 0x00000000, 0x00204811, 0x000 },
10331 { 0x00000000, 0x00204811, 0x000 },
10332 { 0x060a0200, 0x00804811, 0x000 },
10333 { 0x00000000, 0xc0200000, 0x000 },
10334 { 0x97000000, 0xc0204411, 0x000 },
10335 { 0x00000000, 0xc0204811, 0x000 },
10336 { 0x8a000000, 0x00204411, 0x000 },
10337 { 0x00000000, 0x00204811, 0x000 },
10338 { 0x0000225c, 0x00204411, 0x000 },
10339 { 0x00000000, 0xc0204800, 0x000 },
10340 { 0x0000a1fc, 0x00204411, 0x000 },
10341 { 0x00000000, 0xc0204800, 0x000 },
10342 { 0x00000000, 0xc0200400, 0x000 },
10343 { 0x00000000, 0x00a0000a, 0x000 },
10344 { 0x97000000, 0x00204411, 0x000 },
10345 { 0x00000000, 0x00204811, 0x000 },
10346 { 0x8a000000, 0x00204411, 0x000 },
10347 { 0x00000000, 0x00204811, 0x000 },
10348 { 0x0000225c, 0x00204411, 0x000 },
10349 { 0x00000000, 0xc0204800, 0x000 },
10350 { 0x0000a1fc, 0x00204411, 0x000 },
10351 { 0x00000000, 0xc0204800, 0x000 },
10352 { 0x00000000, 0xc0200400, 0x000 },
10353 { 0x00000000, 0x00a0000a, 0x000 },
10354 { 0x97000000, 0x00204411, 0x000 },
10355 { 0x00000000, 0x00204811, 0x000 },
10356 { 0x8a000000, 0x00204411, 0x000 },
10357 { 0x00000000, 0x00204811, 0x000 },
10358 { 0x0000225c, 0x00204411, 0x000 },
10359 { 0x00000000, 0xc0204800, 0x000 },
10360 { 0x0000a1fc, 0x00204411, 0x000 },
10361 { 0x00000000, 0xc0204800, 0x000 },
10362 { 0x0001a1fd, 0x00204411, 0x000 },
10363 { 0x00000000, 0xd9004800, 0x000 },
10364 { 0x00000000, 0xc0200400, 0x000 },
10365 { 0x00000000, 0x00a0000a, 0x000 },
10366 { 0x00002257, 0x00204411, 0x000 },
10367 { 0x00000003, 0xc0484a20, 0x000 },
10368 { 0x0000225d, 0x00204411, 0x000 },
10369 { 0x00000000, 0xc0404800, 0x000 },
10370 { 0x00000000, 0x00600000, 0x642 },
10371 { 0x00000000, 0xc0200800, 0x000 },
10372 { 0x0000225c, 0x00204411, 0x000 },
10373 { 0x00000003, 0x00384a22, 0x000 },
10374 { 0x0000a1fc, 0x00204411, 0x000 },
10375 { 0x00000000, 0xc0204800, 0x000 },
10376 { 0x0001a1fd, 0x00204411, 0x000 },
10377 { 0x00000000, 0x002f0222, 0x000 },
10378 { 0x00000000, 0x0ce00000, 0x000 },
10379 { 0x00000000, 0x40204800, 0x000 },
10380 { 0x00000001, 0x40304a20, 0x000 },
10381 { 0x00000002, 0xc0304a20, 0x000 },
10382 { 0x00000001, 0x00530a22, 0x34b },
10383 { 0x0000003f, 0xc0280a20, 0x000 },
10384 { 0x81000000, 0x00204411, 0x000 },
10385 { 0x00000001, 0x00204811, 0x000 },
10386 { 0x000021f8, 0x00204411, 0x000 },
10387 { 0x00000018, 0x00204811, 0x000 },
10388 { 0x000421f9, 0x00604411, 0x68a },
10389 { 0x00000011, 0x00210230, 0x000 },
10390 { 0x00000000, 0x14e00000, 0x354 },
10391 { 0x00000014, 0x002f0222, 0x000 },
10392 { 0x00000000, 0x0cc00000, 0x364 },
10393 { 0x00002010, 0x00204411, 0x000 },
10394 { 0x00008000, 0x00204811, 0x000 },
10395 { 0x0001a2a4, 0x00204411, 0x000 },
10396 { 0x00000000, 0x00604802, 0x36e },
10397 { 0x00002100, 0x00204411, 0x000 },
10398 { 0x00000000, 0xc0204800, 0x000 },
10399 { 0x00000000, 0xc0204800, 0x000 },
10400 { 0x00000000, 0xc0204800, 0x000 },
10401 { 0x00000000, 0xc0404800, 0x000 },
10402 { 0x00000004, 0x002f0222, 0x000 },
10403 { 0x00000000, 0x0cc00000, 0x36a },
10404 { 0x00002010, 0x00204411, 0x000 },
10405 { 0x00008000, 0x00204811, 0x000 },
10406 { 0x0001a2a4, 0x00204411, 0x000 },
10407 { 0x00000000, 0x00404802, 0x35f },
10408 { 0x00000028, 0x002f0222, 0x000 },
10409 { 0x00000000, 0x0cc00000, 0x5bd },
10410 { 0x0001a2a4, 0x00204411, 0x000 },
10411 { 0x00000000, 0x00404802, 0x35f },
10412 { 0x0000002c, 0x00203626, 0x000 },
10413 { 0x00000049, 0x00201811, 0x000 },
10414 { 0x0000003f, 0x00204811, 0x000 },
10415 { 0x00000001, 0x00331a26, 0x000 },
10416 { 0x00000000, 0x002f0226, 0x000 },
10417 { 0x00000000, 0x0cc00000, 0x370 },
10418 { 0x0000002c, 0x00801a2d, 0x000 },
10419 { 0x0000003f, 0xc0280a20, 0x000 },
10420 { 0x00000015, 0x002f0222, 0x000 },
10421 { 0x00000000, 0x0ce00000, 0x386 },
10422 { 0x00000006, 0x002f0222, 0x000 },
10423 { 0x00000000, 0x0ce00000, 0x3b1 },
10424 { 0x00000016, 0x002f0222, 0x000 },
10425 { 0x00000000, 0x0ce00000, 0x3b5 },
10426 { 0x00000020, 0x002f0222, 0x000 },
10427 { 0x00000000, 0x0ce00000, 0x39c },
10428 { 0x0000000f, 0x002f0222, 0x000 },
10429 { 0x00000000, 0x0ce00000, 0x3a8 },
10430 { 0x00000010, 0x002f0222, 0x000 },
10431 { 0x00000000, 0x0ce00000, 0x3a8 },
10432 { 0x0000001e, 0x002f0222, 0x000 },
10433 { 0x00000000, 0x0ce00000, 0x390 },
10434 { 0x0000a2a4, 0x00204411, 0x000 },
10435 { 0x00000000, 0x00404802, 0x000 },
10436 { 0x08000000, 0x00290a22, 0x000 },
10437 { 0x00000003, 0x40210e20, 0x000 },
10438 { 0x0000000c, 0xc0211220, 0x000 },
10439 { 0x00080000, 0x00281224, 0x000 },
10440 { 0x00000014, 0xc0221620, 0x000 },
10441 { 0x00000000, 0x002914a4, 0x000 },
10442 { 0x0000a2a4, 0x00204411, 0x000 },
10443 { 0x00000000, 0x002948a2, 0x000 },
10444 { 0x0000a1fe, 0x00204411, 0x000 },
10445 { 0x00000000, 0x00404803, 0x000 },
10446 { 0x81000000, 0x00204411, 0x000 },
10447 { 0x00000001, 0x00204811, 0x000 },
10448 { 0x000021f8, 0x00204411, 0x000 },
10449 { 0x00000016, 0x00204811, 0x000 },
10450 { 0x000421f9, 0x00604411, 0x68a },
10451 { 0x00000015, 0x00210230, 0x000 },
10452 { 0x00000000, 0x14e00000, 0x392 },
10453 { 0x0000210e, 0x00204411, 0x000 },
10454 { 0x00000000, 0xc0204800, 0x000 },
10455 { 0x00000000, 0xc0204800, 0x000 },
10456 { 0x0000a2a4, 0x00204411, 0x000 },
10457 { 0x00000000, 0x00404802, 0x000 },
10458 { 0x81000000, 0x00204411, 0x000 },
10459 { 0x00000001, 0x00204811, 0x000 },
10460 { 0x000021f8, 0x00204411, 0x000 },
10461 { 0x00000017, 0x00204811, 0x000 },
10462 { 0x000421f9, 0x00604411, 0x68a },
10463 { 0x00000003, 0x00210230, 0x000 },
10464 { 0x00000000, 0x14e00000, 0x39e },
10465 { 0x00002108, 0x00204411, 0x000 },
10466 { 0x00000000, 0xc0204800, 0x000 },
10467 { 0x00000000, 0xc0204800, 0x000 },
10468 { 0x0000a2a4, 0x00204411, 0x000 },
10469 { 0x00000000, 0x00404802, 0x000 },
10470 { 0x0000a2a4, 0x00204411, 0x000 },
10471 { 0x00000000, 0x00204802, 0x000 },
10472 { 0x80000000, 0x00204411, 0x000 },
10473 { 0x00000000, 0x00204811, 0x000 },
10474 { 0x81000000, 0x00204411, 0x000 },
10475 { 0x00000010, 0x00204811, 0x000 },
10476 { 0x00000000, 0x00200010, 0x000 },
10477 { 0x00000000, 0x14c00000, 0x3ae },
10478 { 0x00000000, 0x00400000, 0x000 },
10479 { 0x00002010, 0x00204411, 0x000 },
10480 { 0x00008000, 0x00204811, 0x000 },
10481 { 0x0001a2a4, 0x00204411, 0x000 },
10482 { 0x00000006, 0x00404811, 0x000 },
10483 { 0x00002010, 0x00204411, 0x000 },
10484 { 0x00008000, 0x00204811, 0x000 },
10485 { 0x0001a2a4, 0x00204411, 0x000 },
10486 { 0x00000016, 0x00604811, 0x36e },
10487 { 0x00000000, 0x00400000, 0x000 },
10488 { 0x00000000, 0xc0200800, 0x000 },
10489 { 0x00000000, 0xc0200c00, 0x000 },
10490 { 0x0000001d, 0x00210223, 0x000 },
10491 { 0x00000000, 0x14e00000, 0x3ce },
10492 { 0x81000000, 0x00204411, 0x000 },
10493 { 0x00000001, 0x00204811, 0x000 },
10494 { 0x000021f8, 0x00204411, 0x000 },
10495 { 0x00000018, 0x00204811, 0x000 },
10496 { 0x000421f9, 0x00604411, 0x68a },
10497 { 0x00000011, 0x00210230, 0x000 },
10498 { 0x00000000, 0x14e00000, 0x3c0 },
10499 { 0x00002100, 0x00204411, 0x000 },
10500 { 0x00000000, 0x00204802, 0x000 },
10501 { 0x00000000, 0x00204803, 0x000 },
10502 { 0xbabecafe, 0x00204811, 0x000 },
10503 { 0xcafebabe, 0x00204811, 0x000 },
10504 { 0x00002010, 0x00204411, 0x000 },
10505 { 0x00008000, 0x00204811, 0x000 },
10506 { 0x0000a2a4, 0x00204411, 0x000 },
10507 { 0x00000004, 0x00404811, 0x000 },
10508 { 0x00002170, 0x00204411, 0x000 },
10509 { 0x00000000, 0x00204802, 0x000 },
10510 { 0x00000000, 0x00204803, 0x000 },
10511 { 0x81000000, 0x00204411, 0x000 },
10512 { 0x0000000a, 0x00204811, 0x000 },
10513 { 0x00000000, 0x00200010, 0x000 },
10514 { 0x00000000, 0x14c00000, 0x3d3 },
10515 { 0x8c000000, 0x00204411, 0x000 },
10516 { 0xcafebabe, 0x00404811, 0x000 },
10517 { 0x81000000, 0x00204411, 0x000 },
10518 { 0x00000001, 0x00204811, 0x000 },
10519 { 0x00003fff, 0x40280a20, 0x000 },
10520 { 0x80000000, 0x40280e20, 0x000 },
10521 { 0x40000000, 0xc0281220, 0x000 },
10522 { 0x00040000, 0x00694622, 0x68a },
10523 { 0x00000000, 0x00201410, 0x000 },
10524 { 0x00000000, 0x002f0223, 0x000 },
10525 { 0x00000000, 0x0cc00000, 0x3e1 },
10526 { 0x00000000, 0xc0401800, 0x3e4 },
10527 { 0x00003fff, 0xc0281a20, 0x000 },
10528 { 0x00040000, 0x00694626, 0x68a },
10529 { 0x00000000, 0x00201810, 0x000 },
10530 { 0x00000000, 0x002f0224, 0x000 },
10531 { 0x00000000, 0x0cc00000, 0x3e7 },
10532 { 0x00000000, 0xc0401c00, 0x3ea },
10533 { 0x00003fff, 0xc0281e20, 0x000 },
10534 { 0x00040000, 0x00694627, 0x68a },
10535 { 0x00000000, 0x00201c10, 0x000 },
10536 { 0x00000000, 0x00204402, 0x000 },
10537 { 0x00000000, 0x002820c5, 0x000 },
10538 { 0x00000000, 0x004948e8, 0x000 },
10539 { 0xa5800000, 0x00200811, 0x000 },
10540 { 0x00002000, 0x00200c11, 0x000 },
10541 { 0x83000000, 0x00604411, 0x412 },
10542 { 0x00000000, 0x00204402, 0x000 },
10543 { 0x00000000, 0xc0204800, 0x000 },
10544 { 0x00000000, 0x40204800, 0x000 },
10545 { 0x0000001f, 0xc0210220, 0x000 },
10546 { 0x00000000, 0x14c00000, 0x3f7 },
10547 { 0x00002010, 0x00204411, 0x000 },
10548 { 0x00008000, 0x00204811, 0x000 },
10549 { 0x0000ffff, 0xc0481220, 0x3ff },
10550 { 0xa7800000, 0x00200811, 0x000 },
10551 { 0x0000a000, 0x00200c11, 0x000 },
10552 { 0x83000000, 0x00604411, 0x412 },
10553 { 0x00000000, 0x00204402, 0x000 },
10554 { 0x00000000, 0xc0204800, 0x000 },
10555 { 0x00000000, 0xc0204800, 0x000 },
10556 { 0x0000ffff, 0xc0281220, 0x000 },
10557 { 0x83000000, 0x00204411, 0x000 },
10558 { 0x00000000, 0x00304883, 0x000 },
10559 { 0x84000000, 0x00204411, 0x000 },
10560 { 0x00000000, 0xc0204800, 0x000 },
10561 { 0x00000000, 0x1d000000, 0x000 },
10562 { 0x83000000, 0x00604411, 0x412 },
10563 { 0x00000000, 0xc0400400, 0x001 },
10564 { 0xa9800000, 0x00200811, 0x000 },
10565 { 0x0000c000, 0x00400c11, 0x3fa },
10566 { 0xab800000, 0x00200811, 0x000 },
10567 { 0x0000f8e0, 0x00400c11, 0x3fa },
10568 { 0xad800000, 0x00200811, 0x000 },
10569 { 0x0000f880, 0x00400c11, 0x3fa },
10570 { 0xb3800000, 0x00200811, 0x000 },
10571 { 0x0000f3fc, 0x00400c11, 0x3fa },
10572 { 0xaf800000, 0x00200811, 0x000 },
10573 { 0x0000e000, 0x00400c11, 0x3fa },
10574 { 0xb1800000, 0x00200811, 0x000 },
10575 { 0x0000f000, 0x00400c11, 0x3fa },
10576 { 0x83000000, 0x00204411, 0x000 },
10577 { 0x00002148, 0x00204811, 0x000 },
10578 { 0x84000000, 0x00204411, 0x000 },
10579 { 0x00000000, 0xc0204800, 0x000 },
10580 { 0x00000000, 0x1d000000, 0x000 },
10581 { 0x00000000, 0x00800000, 0x000 },
10582 { 0x01182000, 0xc0304620, 0x000 },
10583 { 0x00000000, 0xd9004800, 0x000 },
10584 { 0x00000000, 0xc0200400, 0x000 },
10585 { 0x00000000, 0x00a0000a, 0x000 },
10586 { 0x0218a000, 0xc0304620, 0x000 },
10587 { 0x00000000, 0xd9004800, 0x000 },
10588 { 0x00000000, 0xc0200400, 0x000 },
10589 { 0x00000000, 0x00a0000a, 0x000 },
10590 { 0x0318c000, 0xc0304620, 0x000 },
10591 { 0x00000000, 0xd9004800, 0x000 },
10592 { 0x00000000, 0xc0200400, 0x000 },
10593 { 0x00000000, 0x00a0000a, 0x000 },
10594 { 0x0418f8e0, 0xc0304620, 0x000 },
10595 { 0x00000000, 0xd9004800, 0x000 },
10596 { 0x00000000, 0xc0200400, 0x000 },
10597 { 0x00000000, 0x00a0000a, 0x000 },
10598 { 0x0518f880, 0xc0304620, 0x000 },
10599 { 0x00000000, 0xd9004800, 0x000 },
10600 { 0x00000000, 0xc0200400, 0x000 },
10601 { 0x00000000, 0x00a0000a, 0x000 },
10602 { 0x0618e000, 0xc0304620, 0x000 },
10603 { 0x00000000, 0xd9004800, 0x000 },
10604 { 0x00000000, 0xc0200400, 0x000 },
10605 { 0x00000000, 0x00a0000a, 0x000 },
10606 { 0x0718f000, 0xc0304620, 0x000 },
10607 { 0x00000000, 0xd9004800, 0x000 },
10608 { 0x00000000, 0xc0200400, 0x000 },
10609 { 0x00000000, 0x00a0000a, 0x000 },
10610 { 0x0818f3fc, 0xc0304620, 0x000 },
10611 { 0x00000000, 0xd9004800, 0x000 },
10612 { 0x00000000, 0xc0200400, 0x000 },
10613 { 0x00000000, 0x00a0000a, 0x000 },
10614 { 0x00000030, 0x00200a2d, 0x000 },
10615 { 0x00000000, 0xc0290c40, 0x000 },
10616 { 0x00000030, 0x00203623, 0x000 },
10617 { 0x00000000, 0xc0200400, 0x000 },
10618 { 0x00000000, 0x00a0000a, 0x000 },
10619 { 0x86000000, 0x00204411, 0x000 },
10620 { 0x00000000, 0x00404801, 0x000 },
10621 { 0x85000000, 0xc0204411, 0x000 },
10622 { 0x00000000, 0x00404801, 0x000 },
10623 { 0x0000217c, 0x00204411, 0x000 },
10624 { 0x00000000, 0xc0204800, 0x000 },
10625 { 0x00000000, 0xc0204800, 0x000 },
10626 { 0x00000000, 0xc0204800, 0x000 },
10627 { 0x81000000, 0x00204411, 0x000 },
10628 { 0x00000001, 0x00204811, 0x000 },
10629 { 0x00000000, 0xc0200800, 0x000 },
10630 { 0x00000000, 0x17000000, 0x000 },
10631 { 0x0004217f, 0x00604411, 0x68a },
10632 { 0x0000001f, 0x00210230, 0x000 },
10633 { 0x00000000, 0x14c00000, 0x000 },
10634 { 0x00000000, 0x00404c02, 0x448 },
10635 { 0x00000000, 0xc0200c00, 0x000 },
10636 { 0x00000000, 0xc0201000, 0x000 },
10637 { 0x00000000, 0xc0201400, 0x000 },
10638 { 0x00000000, 0xc0201800, 0x000 },
10639 { 0x00000000, 0xc0201c00, 0x000 },
10640 { 0x00007f00, 0x00280a21, 0x000 },
10641 { 0x00004500, 0x002f0222, 0x000 },
10642 { 0x00000000, 0x0ce00000, 0x456 },
10643 { 0x00000000, 0xc0202000, 0x000 },
10644 { 0x00000000, 0x17000000, 0x000 },
10645 { 0x00000010, 0x00280a23, 0x000 },
10646 { 0x00000010, 0x002f0222, 0x000 },
10647 { 0x00000000, 0x0ce00000, 0x45e },
10648 { 0x81000000, 0x00204411, 0x000 },
10649 { 0x00000001, 0x00204811, 0x000 },
10650 { 0x00040000, 0x00694624, 0x68a },
10651 { 0x00000000, 0x00400000, 0x463 },
10652 { 0x81000000, 0x00204411, 0x000 },
10653 { 0x00000000, 0x00204811, 0x000 },
10654 { 0x0000216d, 0x00204411, 0x000 },
10655 { 0x00000000, 0x00204804, 0x000 },
10656 { 0x00000000, 0x00604805, 0x68f },
10657 { 0x00000000, 0x002824f0, 0x000 },
10658 { 0x00000007, 0x00280a23, 0x000 },
10659 { 0x00000001, 0x002f0222, 0x000 },
10660 { 0x00000000, 0x0ae00000, 0x46a },
10661 { 0x00000000, 0x002f00c9, 0x000 },
10662 { 0x00000000, 0x04e00000, 0x483 },
10663 { 0x00000000, 0x00400000, 0x490 },
10664 { 0x00000002, 0x002f0222, 0x000 },
10665 { 0x00000000, 0x0ae00000, 0x46f },
10666 { 0x00000000, 0x002f00c9, 0x000 },
10667 { 0x00000000, 0x02e00000, 0x483 },
10668 { 0x00000000, 0x00400000, 0x490 },
10669 { 0x00000003, 0x002f0222, 0x000 },
10670 { 0x00000000, 0x0ae00000, 0x474 },
10671 { 0x00000000, 0x002f00c9, 0x000 },
10672 { 0x00000000, 0x0ce00000, 0x483 },
10673 { 0x00000000, 0x00400000, 0x490 },
10674 { 0x00000004, 0x002f0222, 0x000 },
10675 { 0x00000000, 0x0ae00000, 0x479 },
10676 { 0x00000000, 0x002f00c9, 0x000 },
10677 { 0x00000000, 0x0ae00000, 0x483 },
10678 { 0x00000000, 0x00400000, 0x490 },
10679 { 0x00000005, 0x002f0222, 0x000 },
10680 { 0x00000000, 0x0ae00000, 0x47e },
10681 { 0x00000000, 0x002f00c9, 0x000 },
10682 { 0x00000000, 0x06e00000, 0x483 },
10683 { 0x00000000, 0x00400000, 0x490 },
10684 { 0x00000006, 0x002f0222, 0x000 },
10685 { 0x00000000, 0x0ae00000, 0x483 },
10686 { 0x00000000, 0x002f00c9, 0x000 },
10687 { 0x00000000, 0x08e00000, 0x483 },
10688 { 0x00000000, 0x00400000, 0x490 },
10689 { 0x00007f00, 0x00280a21, 0x000 },
10690 { 0x00004500, 0x002f0222, 0x000 },
10691 { 0x00000000, 0x0ae00000, 0x000 },
10692 { 0x00000008, 0x00210a23, 0x000 },
10693 { 0x00000000, 0x14c00000, 0x48d },
10694 { 0x00002169, 0x00204411, 0x000 },
10695 { 0x00000000, 0xc0204800, 0x000 },
10696 { 0x00000000, 0xc0204800, 0x000 },
10697 { 0x00000000, 0xc0204800, 0x000 },
10698 { 0xcafebabe, 0x00404811, 0x000 },
10699 { 0x00000000, 0xc0204400, 0x000 },
10700 { 0x00000000, 0xc0200000, 0x000 },
10701 { 0x00000000, 0xc0404800, 0x000 },
10702 { 0x00007f00, 0x00280a21, 0x000 },
10703 { 0x00004500, 0x002f0222, 0x000 },
10704 { 0x00000000, 0x0ae00000, 0x496 },
10705 { 0x00000000, 0xc0200000, 0x000 },
10706 { 0x00000000, 0xc0200000, 0x000 },
10707 { 0x00000000, 0xc0400000, 0x000 },
10708 { 0x00000000, 0x00404c08, 0x456 },
10709 { 0x00000000, 0xc0200800, 0x000 },
10710 { 0x00000010, 0x40210e20, 0x000 },
10711 { 0x00000011, 0x40211220, 0x000 },
10712 { 0x00000012, 0x40211620, 0x000 },
10713 { 0x00002169, 0x00204411, 0x000 },
10714 { 0x00000000, 0x00204802, 0x000 },
10715 { 0x00000000, 0x00210225, 0x000 },
10716 { 0x00000000, 0x14e00000, 0x4a0 },
10717 { 0x00040000, 0xc0494a20, 0x4a1 },
10718 { 0xfffbffff, 0xc0284a20, 0x000 },
10719 { 0x00000000, 0x00210223, 0x000 },
10720 { 0x00000000, 0x14e00000, 0x4ad },
10721 { 0x00000000, 0xc0204800, 0x000 },
10722 { 0x00000000, 0xc0204800, 0x000 },
10723 { 0x00000000, 0x00210224, 0x000 },
10724 { 0x00000000, 0x14c00000, 0x000 },
10725 { 0x81000000, 0x00204411, 0x000 },
10726 { 0x0000000c, 0x00204811, 0x000 },
10727 { 0x00000000, 0x00200010, 0x000 },
10728 { 0x00000000, 0x14c00000, 0x4a9 },
10729 { 0xa0000000, 0x00204411, 0x000 },
10730 { 0xcafebabe, 0x00404811, 0x000 },
10731 { 0x81000000, 0x00204411, 0x000 },
10732 { 0x00000004, 0x00204811, 0x000 },
10733 { 0x0000216b, 0x00204411, 0x000 },
10734 { 0x00000000, 0xc0204810, 0x000 },
10735 { 0x81000000, 0x00204411, 0x000 },
10736 { 0x00000005, 0x00204811, 0x000 },
10737 { 0x0000216c, 0x00204411, 0x000 },
10738 { 0x00000000, 0xc0204810, 0x000 },
10739 { 0x00000000, 0x002f0224, 0x000 },
10740 { 0x00000000, 0x0ce00000, 0x000 },
10741 { 0x00000000, 0x00400000, 0x4a7 },
10742 { 0x00000000, 0xc0210a20, 0x000 },
10743 { 0x00000000, 0x14c00000, 0x4c0 },
10744 { 0x81000000, 0x00204411, 0x000 },
10745 { 0x00000000, 0x00204811, 0x000 },
10746 { 0x0000216d, 0x00204411, 0x000 },
10747 { 0x00000000, 0xc0204800, 0x000 },
10748 { 0x00000000, 0xc0604800, 0x68f },
10749 { 0x00000000, 0x00400000, 0x4c4 },
10750 { 0x81000000, 0x00204411, 0x000 },
10751 { 0x00000001, 0x00204811, 0x000 },
10752 { 0x00040000, 0xc0294620, 0x000 },
10753 { 0x00000000, 0xc0600000, 0x68a },
10754 { 0x00000001, 0x00210222, 0x000 },
10755 { 0x00000000, 0x14c00000, 0x4cb },
10756 { 0x00002169, 0x00204411, 0x000 },
10757 { 0x00000000, 0xc0204800, 0x000 },
10758 { 0x00000000, 0xc0204800, 0x000 },
10759 { 0x00000000, 0x00204810, 0x000 },
10760 { 0xcafebabe, 0x00404811, 0x000 },
10761 { 0x00000000, 0xc0204400, 0x000 },
10762 { 0x00000000, 0xc0404810, 0x000 },
10763 { 0x81000000, 0x00204411, 0x000 },
10764 { 0x00000001, 0x00204811, 0x000 },
10765 { 0x000021f8, 0x00204411, 0x000 },
10766 { 0x0000000e, 0x00204811, 0x000 },
10767 { 0x000421f9, 0x00604411, 0x68a },
10768 { 0x00000000, 0x00210230, 0x000 },
10769 { 0x00000000, 0x14c00000, 0x4cd },
10770 { 0x00002180, 0x00204411, 0x000 },
10771 { 0x00000000, 0xc0204800, 0x000 },
10772 { 0x00000000, 0xc0200000, 0x000 },
10773 { 0x00000000, 0xc0204800, 0x000 },
10774 { 0x00000000, 0xc0200000, 0x000 },
10775 { 0x00000000, 0xc0404800, 0x000 },
10776 { 0x00000003, 0x00333e2f, 0x000 },
10777 { 0x00000001, 0x00210221, 0x000 },
10778 { 0x00000000, 0x14e00000, 0x4fd },
10779 { 0x0000002c, 0x00200a2d, 0x000 },
10780 { 0x00040000, 0x18e00c11, 0x4ec },
10781 { 0x00000001, 0x00333e2f, 0x000 },
10782 { 0x00002169, 0x00204411, 0x000 },
10783 { 0x00000000, 0x00204802, 0x000 },
10784 { 0x00000000, 0x00204803, 0x000 },
10785 { 0x00000008, 0x00300a22, 0x000 },
10786 { 0x00000000, 0xc0204800, 0x000 },
10787 { 0x00000000, 0xc0204800, 0x000 },
10788 { 0x00002169, 0x00204411, 0x000 },
10789 { 0x00000000, 0x00204802, 0x000 },
10790 { 0x00000000, 0x00204803, 0x000 },
10791 { 0x00000008, 0x00300a22, 0x000 },
10792 { 0x00000000, 0xc0204800, 0x000 },
10793 { 0x00000000, 0xd8c04800, 0x4e0 },
10794 { 0x00002169, 0x00204411, 0x000 },
10795 { 0x00000000, 0x00204802, 0x000 },
10796 { 0x00000000, 0x00204803, 0x000 },
10797 { 0x00000008, 0x00300a22, 0x000 },
10798 { 0x00000000, 0xc0204800, 0x000 },
10799 { 0x00000000, 0xc0204800, 0x000 },
10800 { 0x0000002d, 0x0020122d, 0x000 },
10801 { 0x00000000, 0x00290c83, 0x000 },
10802 { 0x00002169, 0x00204411, 0x000 },
10803 { 0x00000000, 0x00204802, 0x000 },
10804 { 0x00000000, 0x00204803, 0x000 },
10805 { 0x00000008, 0x00300a22, 0x000 },
10806 { 0x00000000, 0xc0204800, 0x000 },
10807 { 0x00000000, 0xc0204800, 0x000 },
10808 { 0x00000011, 0x00210224, 0x000 },
10809 { 0x00000000, 0x14c00000, 0x000 },
10810 { 0x00000000, 0x00400000, 0x4a7 },
10811 { 0x0000002c, 0xc0203620, 0x000 },
10812 { 0x0000002d, 0xc0403620, 0x000 },
10813 { 0x0000000f, 0x00210221, 0x000 },
10814 { 0x00000000, 0x14c00000, 0x502 },
10815 { 0x00000000, 0x00600000, 0x00b },
10816 { 0x00000000, 0xd9000000, 0x000 },
10817 { 0x00000000, 0xc0400400, 0x001 },
10818 { 0xb5000000, 0x00204411, 0x000 },
10819 { 0x00002000, 0x00204811, 0x000 },
10820 { 0xb6000000, 0x00204411, 0x000 },
10821 { 0x0000a000, 0x00204811, 0x000 },
10822 { 0xb7000000, 0x00204411, 0x000 },
10823 { 0x0000c000, 0x00204811, 0x000 },
10824 { 0xb8000000, 0x00204411, 0x000 },
10825 { 0x0000f8e0, 0x00204811, 0x000 },
10826 { 0xb9000000, 0x00204411, 0x000 },
10827 { 0x0000f880, 0x00204811, 0x000 },
10828 { 0xba000000, 0x00204411, 0x000 },
10829 { 0x0000e000, 0x00204811, 0x000 },
10830 { 0xbb000000, 0x00204411, 0x000 },
10831 { 0x0000f000, 0x00204811, 0x000 },
10832 { 0xbc000000, 0x00204411, 0x000 },
10833 { 0x0000f3fc, 0x00204811, 0x000 },
10834 { 0x81000000, 0x00204411, 0x000 },
10835 { 0x00000002, 0x00204811, 0x000 },
10836 { 0x000000ff, 0x00280e30, 0x000 },
10837 { 0x00000000, 0x002f0223, 0x000 },
10838 { 0x00000000, 0x0cc00000, 0x516 },
10839 { 0x00000000, 0xc0200800, 0x000 },
10840 { 0x00000000, 0x14c00000, 0x52b },
10841 { 0x00000000, 0x00200c11, 0x000 },
10842 { 0x0000001c, 0x00203623, 0x000 },
10843 { 0x0000002b, 0x00203623, 0x000 },
10844 { 0x00000029, 0x00203623, 0x000 },
10845 { 0x00000028, 0x00203623, 0x000 },
10846 { 0x00000017, 0x00203623, 0x000 },
10847 { 0x00000025, 0x00203623, 0x000 },
10848 { 0x00000026, 0x00203623, 0x000 },
10849 { 0x00000015, 0x00203623, 0x000 },
10850 { 0x00000016, 0x00203623, 0x000 },
10851 { 0xffffe000, 0x00200c11, 0x000 },
10852 { 0x00000021, 0x00203623, 0x000 },
10853 { 0x00000022, 0x00203623, 0x000 },
10854 { 0x00001fff, 0x00200c11, 0x000 },
10855 { 0x00000023, 0x00203623, 0x000 },
10856 { 0x00000024, 0x00203623, 0x000 },
10857 { 0xf1ffffff, 0x00283a2e, 0x000 },
10858 { 0x0000001a, 0xc0220e20, 0x000 },
10859 { 0x00000000, 0x0029386e, 0x000 },
10860 { 0x81000000, 0x00204411, 0x000 },
10861 { 0x00000006, 0x00204811, 0x000 },
10862 { 0x0000002a, 0x40203620, 0x000 },
10863 { 0x87000000, 0x00204411, 0x000 },
10864 { 0x00000000, 0xc0204800, 0x000 },
10865 { 0x0000a1f4, 0x00204411, 0x000 },
10866 { 0x00000000, 0x00204810, 0x000 },
10867 { 0x00000000, 0x00200c11, 0x000 },
10868 { 0x00000030, 0x00203623, 0x000 },
10869 { 0x9d000000, 0x00204411, 0x000 },
10870 { 0x0000001f, 0x40214a20, 0x000 },
10871 { 0x96000000, 0x00204411, 0x000 },
10872 { 0x00000000, 0xc0204800, 0x000 },
10873 { 0x00000000, 0xc0200c00, 0x000 },
10874 { 0x00000000, 0xc0201000, 0x000 },
10875 { 0x0000001f, 0x00211624, 0x000 },
10876 { 0x00000000, 0x14c00000, 0x000 },
10877 { 0x0000001d, 0x00203623, 0x000 },
10878 { 0x00000003, 0x00281e23, 0x000 },
10879 { 0x00000008, 0x00222223, 0x000 },
10880 { 0xfffff000, 0x00282228, 0x000 },
10881 { 0x00000000, 0x002920e8, 0x000 },
10882 { 0x0000001f, 0x00203628, 0x000 },
10883 { 0x00000018, 0x00211e23, 0x000 },
10884 { 0x00000020, 0x00203627, 0x000 },
10885 { 0x00000002, 0x00221624, 0x000 },
10886 { 0x00000000, 0x003014a8, 0x000 },
10887 { 0x0000001e, 0x00203625, 0x000 },
10888 { 0x00000003, 0x00211a24, 0x000 },
10889 { 0x10000000, 0x00281a26, 0x000 },
10890 { 0xefffffff, 0x00283a2e, 0x000 },
10891 { 0x00000000, 0x004938ce, 0x678 },
10892 { 0x00000001, 0x40280a20, 0x000 },
10893 { 0x00000006, 0x40280e20, 0x000 },
10894 { 0x00000300, 0xc0281220, 0x000 },
10895 { 0x00000008, 0x00211224, 0x000 },
10896 { 0x00000000, 0xc0201620, 0x000 },
10897 { 0x00000000, 0xc0201a20, 0x000 },
10898 { 0x00000000, 0x00210222, 0x000 },
10899 { 0x00000000, 0x14c00000, 0x563 },
10900 { 0x81000000, 0x00204411, 0x000 },
10901 { 0x00000001, 0x00204811, 0x000 },
10902 { 0x00002258, 0x00300a24, 0x000 },
10903 { 0x00040000, 0x00694622, 0x68a },
10904 { 0x00002169, 0x00204411, 0x000 },
10905 { 0x00000000, 0x00204805, 0x000 },
10906 { 0x00020000, 0x00294a26, 0x000 },
10907 { 0x00000000, 0x00204810, 0x000 },
10908 { 0xcafebabe, 0x00204811, 0x000 },
10909 { 0x00000002, 0x002f0223, 0x000 },
10910 { 0x00000000, 0x0cc00000, 0x56b },
10911 { 0x00000000, 0xc0201c10, 0x000 },
10912 { 0x00000000, 0xc0400000, 0x579 },
10913 { 0x00000002, 0x002f0223, 0x000 },
10914 { 0x00000000, 0x0cc00000, 0x56b },
10915 { 0x81000000, 0x00204411, 0x000 },
10916 { 0x00000001, 0x00204811, 0x000 },
10917 { 0x00002258, 0x00300a24, 0x000 },
10918 { 0x00040000, 0x00694622, 0x68a },
10919 { 0x00000000, 0xc0201c10, 0x000 },
10920 { 0x00000000, 0xc0400000, 0x579 },
10921 { 0x00000000, 0x002f0223, 0x000 },
10922 { 0x00000000, 0x0cc00000, 0x56f },
10923 { 0x00000000, 0xc0201c00, 0x000 },
10924 { 0x00000000, 0xc0400000, 0x579 },
10925 { 0x00000004, 0x002f0223, 0x000 },
10926 { 0x00000000, 0x0cc00000, 0x577 },
10927 { 0x81000000, 0x00204411, 0x000 },
10928 { 0x00000000, 0x00204811, 0x000 },
10929 { 0x0000216d, 0x00204411, 0x000 },
10930 { 0x00000000, 0xc0204800, 0x000 },
10931 { 0x00000000, 0xc0604800, 0x68f },
10932 { 0x00000000, 0x00401c10, 0x579 },
10933 { 0x00000000, 0xc0200000, 0x000 },
10934 { 0x00000000, 0xc0400000, 0x000 },
10935 { 0x00000000, 0x0ee00000, 0x57b },
10936 { 0x00000000, 0x00600000, 0x5c6 },
10937 { 0x00000000, 0x002f0224, 0x000 },
10938 { 0x00000000, 0x0cc00000, 0x58c },
10939 { 0x0000a2b7, 0x00204411, 0x000 },
10940 { 0x00000000, 0x00204807, 0x000 },
10941 { 0x81000000, 0x00204411, 0x000 },
10942 { 0x00000001, 0x00204811, 0x000 },
10943 { 0x0004a2b6, 0x00604411, 0x68a },
10944 { 0x0000001a, 0x00212230, 0x000 },
10945 { 0x00000006, 0x00222630, 0x000 },
10946 { 0x00042004, 0x00604411, 0x68a },
10947 { 0x0000a2c4, 0x00204411, 0x000 },
10948 { 0x00000000, 0x003048e9, 0x000 },
10949 { 0x00000000, 0x00e00000, 0x58a },
10950 { 0x0000a2d1, 0x00204411, 0x000 },
10951 { 0x00000000, 0x00404808, 0x000 },
10952 { 0x0000a2d1, 0x00204411, 0x000 },
10953 { 0x00000001, 0x00504a28, 0x000 },
10954 { 0x00000001, 0x002f0224, 0x000 },
10955 { 0x00000000, 0x0cc00000, 0x59d },
10956 { 0x0000a2bb, 0x00204411, 0x000 },
10957 { 0x00000000, 0x00204807, 0x000 },
10958 { 0x81000000, 0x00204411, 0x000 },
10959 { 0x00000001, 0x00204811, 0x000 },
10960 { 0x0004a2ba, 0x00604411, 0x68a },
10961 { 0x0000001a, 0x00212230, 0x000 },
10962 { 0x00000006, 0x00222630, 0x000 },
10963 { 0x00042004, 0x00604411, 0x68a },
10964 { 0x0000a2c5, 0x00204411, 0x000 },
10965 { 0x00000000, 0x003048e9, 0x000 },
10966 { 0x00000000, 0x00e00000, 0x59b },
10967 { 0x0000a2d2, 0x00204411, 0x000 },
10968 { 0x00000000, 0x00404808, 0x000 },
10969 { 0x0000a2d2, 0x00204411, 0x000 },
10970 { 0x00000001, 0x00504a28, 0x000 },
10971 { 0x00000002, 0x002f0224, 0x000 },
10972 { 0x00000000, 0x0cc00000, 0x5ae },
10973 { 0x0000a2bf, 0x00204411, 0x000 },
10974 { 0x00000000, 0x00204807, 0x000 },
10975 { 0x81000000, 0x00204411, 0x000 },
10976 { 0x00000001, 0x00204811, 0x000 },
10977 { 0x0004a2be, 0x00604411, 0x68a },
10978 { 0x0000001a, 0x00212230, 0x000 },
10979 { 0x00000006, 0x00222630, 0x000 },
10980 { 0x00042004, 0x00604411, 0x68a },
10981 { 0x0000a2c6, 0x00204411, 0x000 },
10982 { 0x00000000, 0x003048e9, 0x000 },
10983 { 0x00000000, 0x00e00000, 0x5ac },
10984 { 0x0000a2d3, 0x00204411, 0x000 },
10985 { 0x00000000, 0x00404808, 0x000 },
10986 { 0x0000a2d3, 0x00204411, 0x000 },
10987 { 0x00000001, 0x00504a28, 0x000 },
10988 { 0x0000a2c3, 0x00204411, 0x000 },
10989 { 0x00000000, 0x00204807, 0x000 },
10990 { 0x81000000, 0x00204411, 0x000 },
10991 { 0x00000001, 0x00204811, 0x000 },
10992 { 0x0004a2c2, 0x00604411, 0x68a },
10993 { 0x0000001a, 0x00212230, 0x000 },
10994 { 0x00000006, 0x00222630, 0x000 },
10995 { 0x00042004, 0x00604411, 0x68a },
10996 { 0x0000a2c7, 0x00204411, 0x000 },
10997 { 0x00000000, 0x003048e9, 0x000 },
10998 { 0x00000000, 0x00e00000, 0x5bb },
10999 { 0x0000a2d4, 0x00204411, 0x000 },
11000 { 0x00000000, 0x00404808, 0x000 },
11001 { 0x0000a2d4, 0x00204411, 0x000 },
11002 { 0x00000001, 0x00504a28, 0x000 },
11003 { 0x85000000, 0x00204411, 0x000 },
11004 { 0x00000000, 0x00204801, 0x000 },
11005 { 0x0000304a, 0x00204411, 0x000 },
11006 { 0x01000000, 0x00204811, 0x000 },
11007 { 0x00000000, 0x00400000, 0x5c1 },
11008 { 0xa4000000, 0xc0204411, 0x000 },
11009 { 0x00000000, 0xc0404800, 0x000 },
11010 { 0x00000000, 0xc0600000, 0x5c6 },
11011 { 0x00000000, 0xc0400400, 0x001 },
11012 { 0x0000002c, 0x00203621, 0x000 },
11013 { 0x81000000, 0x00204411, 0x000 },
11014 { 0x00000006, 0x00204811, 0x000 },
11015 { 0x00000000, 0x002f0230, 0x000 },
11016 { 0x00000000, 0x0cc00000, 0x5cd },
11017 { 0x00000000, 0x00200411, 0x000 },
11018 { 0x00000030, 0x00403621, 0x5e0 },
11019 { 0x00000030, 0x0020062d, 0x000 },
11020 { 0x00007e00, 0x00280621, 0x000 },
11021 { 0x00000000, 0x002f0221, 0x000 },
11022 { 0x00000000, 0x0ce00000, 0x5e0 },
11023 { 0x81000000, 0x00204411, 0x000 },
11024 { 0x00000001, 0x00204811, 0x000 },
11025 { 0x0004a092, 0x00604411, 0x68a },
11026 { 0x00000031, 0x00203630, 0x000 },
11027 { 0x0004a093, 0x00604411, 0x68a },
11028 { 0x00000032, 0x00203630, 0x000 },
11029 { 0x0004a2b6, 0x00604411, 0x68a },
11030 { 0x00000033, 0x00203630, 0x000 },
11031 { 0x0004a2ba, 0x00604411, 0x68a },
11032 { 0x00000034, 0x00203630, 0x000 },
11033 { 0x0004a2be, 0x00604411, 0x68a },
11034 { 0x00000035, 0x00203630, 0x000 },
11035 { 0x0004a2c2, 0x00604411, 0x68a },
11036 { 0x00000036, 0x00203630, 0x000 },
11037 { 0x00042004, 0x00604411, 0x68a },
11038 { 0x0001a2a4, 0x00204411, 0x000 },
11039 { 0x0000003f, 0x00204811, 0x000 },
11040 { 0x0000003f, 0x00204811, 0x000 },
11041 { 0x0000003f, 0x00204811, 0x000 },
11042 { 0x0000003f, 0x00204811, 0x000 },
11043 { 0x00000005, 0x00204811, 0x000 },
11044 { 0x0000a1f4, 0x00204411, 0x000 },
11045 { 0x00000000, 0x00204811, 0x000 },
11046 { 0x88000000, 0x00204411, 0x000 },
11047 { 0x00000001, 0x00204811, 0x000 },
11048 { 0x81000000, 0x00204411, 0x000 },
11049 { 0x00000006, 0x00204811, 0x000 },
11050 { 0x00000001, 0x002f0230, 0x000 },
11051 { 0x00000000, 0x0ce00000, 0x629 },
11052 { 0x00000030, 0x0020062d, 0x000 },
11053 { 0x00000000, 0x002f0221, 0x000 },
11054 { 0x00000000, 0x0ce00000, 0x629 },
11055 { 0x81000000, 0x00204411, 0x000 },
11056 { 0x00000001, 0x00204811, 0x000 },
11057 { 0x00007e00, 0x00280621, 0x000 },
11058 { 0x00000000, 0x002f0221, 0x000 },
11059 { 0x00000000, 0x0ce00000, 0x602 },
11060 { 0x0000a092, 0x00204411, 0x000 },
11061 { 0x00000031, 0x00204a2d, 0x000 },
11062 { 0x0000a093, 0x00204411, 0x000 },
11063 { 0x00000032, 0x00204a2d, 0x000 },
11064 { 0x0000a2b6, 0x00204411, 0x000 },
11065 { 0x00000033, 0x00204a2d, 0x000 },
11066 { 0x0000a2ba, 0x00204411, 0x000 },
11067 { 0x00000034, 0x00204a2d, 0x000 },
11068 { 0x0000a2be, 0x00204411, 0x000 },
11069 { 0x00000035, 0x00204a2d, 0x000 },
11070 { 0x0000a2c2, 0x00204411, 0x000 },
11071 { 0x00000036, 0x00204a2d, 0x000 },
11072 { 0x00000030, 0x0020062d, 0x000 },
11073 { 0x000001ff, 0x00280621, 0x000 },
11074 { 0x00000000, 0x002f0221, 0x000 },
11075 { 0x00000000, 0x0ce00000, 0x628 },
11076 { 0x00000000, 0x00210221, 0x000 },
11077 { 0x00000000, 0x14c00000, 0x60b },
11078 { 0x0004a003, 0x00604411, 0x68a },
11079 { 0x0000a003, 0x00204411, 0x000 },
11080 { 0x00000000, 0x00204810, 0x000 },
11081 { 0x00000001, 0x00210621, 0x000 },
11082 { 0x00000000, 0x14c00000, 0x610 },
11083 { 0x0004a010, 0x00604411, 0x68a },
11084 { 0x0000a010, 0x00204411, 0x000 },
11085 { 0x00000000, 0x00204810, 0x000 },
11086 { 0x00000001, 0x00210621, 0x000 },
11087 { 0x00000000, 0x002f0221, 0x000 },
11088 { 0x00000000, 0x0ce00000, 0x628 },
11089 { 0x0004a011, 0x00604411, 0x68a },
11090 { 0x0000a011, 0x00204411, 0x000 },
11091 { 0x00000000, 0x00204810, 0x000 },
11092 { 0x0004a012, 0x00604411, 0x68a },
11093 { 0x0000a012, 0x00204411, 0x000 },
11094 { 0x00000000, 0x00204810, 0x000 },
11095 { 0x0004a013, 0x00604411, 0x68a },
11096 { 0x0000a013, 0x00204411, 0x000 },
11097 { 0x00000000, 0x00204810, 0x000 },
11098 { 0x0004a014, 0x00604411, 0x68a },
11099 { 0x0000a014, 0x00204411, 0x000 },
11100 { 0x00000000, 0x00204810, 0x000 },
11101 { 0x0004a015, 0x00604411, 0x68a },
11102 { 0x0000a015, 0x00204411, 0x000 },
11103 { 0x00000000, 0x00204810, 0x000 },
11104 { 0x0004a016, 0x00604411, 0x68a },
11105 { 0x0000a016, 0x00204411, 0x000 },
11106 { 0x00000000, 0x00204810, 0x000 },
11107 { 0x0004a017, 0x00604411, 0x68a },
11108 { 0x0000a017, 0x00204411, 0x000 },
11109 { 0x00000000, 0x00204810, 0x000 },
11110 { 0x00042004, 0x00604411, 0x68a },
11111 { 0x0000002c, 0x0080062d, 0x000 },
11112 { 0xff000000, 0x00204411, 0x000 },
11113 { 0x00000000, 0x00204811, 0x000 },
11114 { 0x00000001, 0x00204811, 0x000 },
11115 { 0x00000002, 0x00804811, 0x000 },
11116 { 0x00000000, 0x0ee00000, 0x63a },
11117 { 0x00000030, 0x0020062d, 0x000 },
11118 { 0x00000002, 0x00280621, 0x000 },
11119 { 0x00000000, 0x002f0221, 0x000 },
11120 { 0x00000000, 0x0ce00000, 0x638 },
11121 { 0x81000000, 0x00204411, 0x000 },
11122 { 0x00000001, 0x00204811, 0x000 },
11123 { 0x00042004, 0x00604411, 0x68a },
11124 { 0x00001000, 0x00200811, 0x000 },
11125 { 0x0000002b, 0x00203622, 0x000 },
11126 { 0x00000000, 0x00600000, 0x63e },
11127 { 0x00000000, 0x00600000, 0x5c6 },
11128 { 0x98000000, 0x00204411, 0x000 },
11129 { 0x00000000, 0x00804811, 0x000 },
11130 { 0x00000000, 0xc0600000, 0x63e },
11131 { 0x00000000, 0xc0400400, 0x001 },
11132 { 0x0000a2a4, 0x00204411, 0x000 },
11133 { 0x00000022, 0x00204811, 0x000 },
11134 { 0x89000000, 0x00204411, 0x000 },
11135 { 0x00000001, 0x00404811, 0x62a },
11136 { 0x97000000, 0x00204411, 0x000 },
11137 { 0x00000000, 0x00204811, 0x000 },
11138 { 0x8a000000, 0x00204411, 0x000 },
11139 { 0x00000000, 0x00404811, 0x62a },
11140 { 0x00000000, 0x00600000, 0x659 },
11141 { 0x00002010, 0x00204411, 0x000 },
11142 { 0x00008000, 0x00204811, 0x000 },
11143 { 0x0001a2a4, 0xc0204411, 0x000 },
11144 { 0x00000016, 0x00604811, 0x36e },
11145 { 0x00002010, 0x00204411, 0x000 },
11146 { 0x00010000, 0x00204811, 0x000 },
11147 { 0x81000000, 0x00204411, 0x000 },
11148 { 0x00000001, 0x00204811, 0x000 },
11149 { 0x0000217c, 0x00204411, 0x000 },
11150 { 0x09800000, 0x00204811, 0x000 },
11151 { 0xffffffff, 0x00204811, 0x000 },
11152 { 0x00000000, 0x00204811, 0x000 },
11153 { 0x00000000, 0x17000000, 0x000 },
11154 { 0x0004217f, 0x00604411, 0x68a },
11155 { 0x0000001f, 0x00210230, 0x000 },
11156 { 0x00000000, 0x14c00000, 0x000 },
11157 { 0x00000004, 0x00404c11, 0x653 },
11158 { 0x00000000, 0x00400000, 0x000 },
11159 { 0x00000017, 0x00201e2d, 0x000 },
11160 { 0x00000004, 0x00291e27, 0x000 },
11161 { 0x00000017, 0x00803627, 0x000 },
11162 { 0x00000017, 0x00201e2d, 0x000 },
11163 { 0xfffffffb, 0x00281e27, 0x000 },
11164 { 0x00000017, 0x00803627, 0x000 },
11165 { 0x00000017, 0x00201e2d, 0x000 },
11166 { 0x00000008, 0x00291e27, 0x000 },
11167 { 0x00000017, 0x00803627, 0x000 },
11168 { 0x00000017, 0x00201e2d, 0x000 },
11169 { 0xfffffff7, 0x00281e27, 0x000 },
11170 { 0x00000017, 0x00803627, 0x000 },
11171 { 0x00002010, 0x00204411, 0x000 },
11172 { 0x00008000, 0x00204811, 0x000 },
11173 { 0x0001a2a4, 0x00204411, 0x000 },
11174 { 0x00000016, 0x00604811, 0x36e },
11175 { 0x00002010, 0x00204411, 0x000 },
11176 { 0x00010000, 0x00204811, 0x000 },
11177 { 0x0000217c, 0x00204411, 0x000 },
11178 { 0x01800000, 0x00204811, 0x000 },
11179 { 0xffffffff, 0x00204811, 0x000 },
11180 { 0x00000000, 0x00204811, 0x000 },
11181 { 0x00000000, 0x17000000, 0x000 },
11182 { 0x81000000, 0x00204411, 0x000 },
11183 { 0x00000001, 0x00204811, 0x000 },
11184 { 0x0004217f, 0x00604411, 0x68a },
11185 { 0x0000001f, 0x00210230, 0x000 },
11186 { 0x00000000, 0x14c00000, 0x689 },
11187 { 0x00000010, 0x00404c11, 0x66f },
11188 { 0x00000000, 0xc0200400, 0x000 },
11189 { 0x00000000, 0x38c00000, 0x000 },
11190 { 0x0000001d, 0x00200a2d, 0x000 },
11191 { 0x0000001e, 0x00200e2d, 0x000 },
11192 { 0x0000001f, 0x0020122d, 0x000 },
11193 { 0x00000020, 0x0020162d, 0x000 },
11194 { 0x00002169, 0x00204411, 0x000 },
11195 { 0x00000000, 0x00204804, 0x000 },
11196 { 0x00000000, 0x00204805, 0x000 },
11197 { 0x00000000, 0x00204801, 0x000 },
11198 { 0xcafebabe, 0x00204811, 0x000 },
11199 { 0x00000004, 0x00301224, 0x000 },
11200 { 0x00000000, 0x002f0064, 0x000 },
11201 { 0x00000000, 0x0cc00000, 0x688 },
11202 { 0x00000003, 0x00281a22, 0x000 },
11203 { 0x00000008, 0x00221222, 0x000 },
11204 { 0xfffff000, 0x00281224, 0x000 },
11205 { 0x00000000, 0x002910c4, 0x000 },
11206 { 0x0000001f, 0x00403624, 0x000 },
11207 { 0x00000000, 0x00800000, 0x000 },
11208 { 0x00000000, 0x1ac00000, 0x68a },
11209 { 0x9f000000, 0x00204411, 0x000 },
11210 { 0xcafebabe, 0x00204811, 0x000 },
11211 { 0x00000000, 0x1ae00000, 0x68d },
11212 { 0x00000000, 0x00800000, 0x000 },
11213 { 0x00000000, 0x1ac00000, 0x68f },
11214 { 0x9e000000, 0x00204411, 0x000 },
11215 { 0xcafebabe, 0x00204811, 0x000 },
11216 { 0x00000000, 0x1ae00000, 0x692 },
11217 { 0x00000000, 0x00800000, 0x000 },
11218 { 0x00000000, 0x00600000, 0x00b },
11219 { 0x00001000, 0x00600411, 0x315 },
11220 { 0x00000000, 0x00200411, 0x000 },
11221 { 0x00000000, 0x00600811, 0x1b2 },
11222 { 0x0000225c, 0x00204411, 0x000 },
11223 { 0x00000003, 0x00204811, 0x000 },
11224 { 0x00002256, 0x00204411, 0x000 },
11225 { 0x0000001b, 0x00204811, 0x000 },
11226 { 0x0000a1fc, 0x00204411, 0x000 },
11227 { 0x00000001, 0x00204811, 0x000 },
11228 { 0x0001a1fd, 0xc0204411, 0x000 },
11229 { 0x00000021, 0x00201e2d, 0x000 },
11230 { 0x00000010, 0x00221e27, 0x000 },
11231 { 0x00000024, 0x0020222d, 0x000 },
11232 { 0x0000ffff, 0x00282228, 0x000 },
11233 { 0x00000000, 0x00294907, 0x000 },
11234 { 0x00000000, 0x00204811, 0x000 },
11235 { 0x00000022, 0x0020222d, 0x000 },
11236 { 0x0000ffff, 0x00282228, 0x000 },
11237 { 0x00000000, 0x00294907, 0x000 },
11238 { 0x00000000, 0x00204811, 0x000 },
11239 { 0x00000023, 0x00201e2d, 0x000 },
11240 { 0x00000010, 0x00221e27, 0x000 },
11241 { 0x00000000, 0x00294907, 0x000 },
11242 { 0x00000000, 0x00404811, 0x000 },
11243 { 0x00000000, 0x00000000, 0x000 },
11244 { 0x00000000, 0x00000000, 0x000 },
11245 { 0x00000000, 0x00000000, 0x000 },
11246 { 0x00000000, 0x00000000, 0x000 },
11247 { 0x00000000, 0x00000000, 0x000 },
11248 { 0x00000000, 0x00000000, 0x000 },
11249 { 0x00000000, 0x00000000, 0x000 },
11250 { 0x00000000, 0x00000000, 0x000 },
11251 { 0x00000000, 0x00000000, 0x000 },
11252 { 0x00000000, 0x00000000, 0x000 },
11253 { 0x00000000, 0x00000000, 0x000 },
11254 { 0x00000000, 0x00000000, 0x000 },
11255 { 0x00000000, 0x00000000, 0x000 },
11256 { 0x00000000, 0x00000000, 0x000 },
11257 { 0x00000000, 0x00000000, 0x000 },
11258 { 0x00000000, 0x00000000, 0x000 },
11259 { 0x00000000, 0x00000000, 0x000 },
11260 { 0x00000000, 0x00000000, 0x000 },
11261 { 0x00000000, 0x00000000, 0x000 },
11262 { 0x00000000, 0x00000000, 0x000 },
11263 { 0x00000000, 0x00000000, 0x000 },
11264 { 0x00000000, 0x00000000, 0x000 },
11265 { 0x00000000, 0x00000000, 0x000 },
11266 { 0x00000000, 0x00000000, 0x000 },
11267 { 0x00000000, 0x00000000, 0x000 },
11268 { 0x00000000, 0x00000000, 0x000 },
11269 { 0x00000000, 0x00000000, 0x000 },
11270 { 0x00000000, 0x00000000, 0x000 },
11271 { 0x00000000, 0x00000000, 0x000 },
11272 { 0x00000000, 0x00000000, 0x000 },
11273 { 0x00000000, 0x00000000, 0x000 },
11274 { 0x00000000, 0x00000000, 0x000 },
11275 { 0x00000000, 0x00000000, 0x000 },
11276 { 0x00000000, 0x00000000, 0x000 },
11277 { 0x00000000, 0x00000000, 0x000 },
11278 { 0x00000000, 0x00000000, 0x000 },
11279 { 0x00000000, 0x00000000, 0x000 },
11280 { 0x00000000, 0x00000000, 0x000 },
11281 { 0x00000000, 0x00000000, 0x000 },
11282 { 0x00000000, 0x00000000, 0x000 },
11283 { 0x00000000, 0x00000000, 0x000 },
11284 { 0x00000000, 0x00000000, 0x000 },
11285 { 0x00000000, 0x00000000, 0x000 },
11286 { 0x00000000, 0x00000000, 0x000 },
11287 { 0x00000000, 0x00000000, 0x000 },
11288 { 0x00000000, 0x00000000, 0x000 },
11289 { 0x00000000, 0x00000000, 0x000 },
11290 { 0x00000000, 0x00000000, 0x000 },
11291 { 0x00000000, 0x00000000, 0x000 },
11292 { 0x00000000, 0x00000000, 0x000 },
11293 { 0x00000000, 0x00000000, 0x000 },
11294 { 0x00000000, 0x00000000, 0x000 },
11295 { 0x00000000, 0x00000000, 0x000 },
11296 { 0x00000000, 0x00000000, 0x000 },
11297 { 0x00000000, 0x00000000, 0x000 },
11298 { 0x014204ff, 0x05bd0250, 0x000 },
11299 { 0x01c30168, 0x043f05bd, 0x000 },
11300 { 0x02250209, 0x02500151, 0x000 },
11301 { 0x02230245, 0x02a00241, 0x000 },
11302 { 0x03d705bd, 0x05bd05bd, 0x000 },
11303 { 0x06460647, 0x031f05bd, 0x000 },
11304 { 0x05bd05c2, 0x03200340, 0x000 },
11305 { 0x032a0282, 0x03420334, 0x000 },
11306 { 0x05bd05bd, 0x05bd05bd, 0x000 },
11307 { 0x05bd054e, 0x05bd05bd, 0x000 },
11308 { 0x03ba05bd, 0x04b80344, 0x000 },
11309 { 0x0497044d, 0x043d05bd, 0x000 },
11310 { 0x04cd05bd, 0x044104da, 0x000 },
11311 { 0x044d0504, 0x03510375, 0x000 },
11312 { 0x05bd05bd, 0x05bd05bd, 0x000 },
11313 { 0x05bd05bd, 0x05bd05bd, 0x000 },
11314 { 0x05bd05bd, 0x063c05c4, 0x000 },
11315 { 0x05bd05bd, 0x000705bd, 0x000 },
11316 { 0x05bd05bd, 0x05bd05bd, 0x000 },
11317 { 0x05bd05bd, 0x05bd05bd, 0x000 },
11318 { 0x03f803ed, 0x04080406, 0x000 },
11319 { 0x040e040a, 0x040c0410, 0x000 },
11320 { 0x041c0418, 0x04240420, 0x000 },
11321 { 0x042c0428, 0x04340430, 0x000 },
11322 { 0x05bd05bd, 0x043805bd, 0x000 },
11323 { 0x05bd05bd, 0x05bd05bd, 0x000 },
11324 { 0x05bd05bd, 0x05bd05bd, 0x000 },
11325 { 0x00020676, 0x06940006, 0x000 },
11326};
11327
11328static const u32 RV635_pfp_microcode[] = {
113290xca0400,
113300xa00000,
113310x7e828b,
113320x7c038b,
113330x8001b8,
113340x7c038b,
113350xd4401e,
113360xee001e,
113370xca0400,
113380xa00000,
113390x7e828b,
113400xc41838,
113410xca2400,
113420xca2800,
113430x9581a8,
113440xc41c3a,
113450xc3c000,
113460xca0800,
113470xca0c00,
113480x7c744b,
113490xc20005,
113500x99c000,
113510xc41c3a,
113520x7c744c,
113530xc0fff0,
113540x042c04,
113550x309002,
113560x7d2500,
113570x351402,
113580x7d350b,
113590x255403,
113600x7cd580,
113610x259c03,
113620x95c004,
113630xd5001b,
113640x7eddc1,
113650x7d9d80,
113660xd6801b,
113670xd5801b,
113680xd4401e,
113690xd5401e,
113700xd6401e,
113710xd6801e,
113720xd4801e,
113730xd4c01e,
113740x9783d3,
113750xd5c01e,
113760xca0800,
113770x80001a,
113780xca0c00,
113790xe4011e,
113800xd4001e,
113810x80000c,
113820xc41838,
113830xe4013e,
113840xd4001e,
113850x80000c,
113860xc41838,
113870xd4401e,
113880xee001e,
113890xca0400,
113900xa00000,
113910x7e828b,
113920xe4011e,
113930xd4001e,
113940xd4401e,
113950xee001e,
113960xca0400,
113970xa00000,
113980x7e828b,
113990xe4013e,
114000xd4001e,
114010xd4401e,
114020xee001e,
114030xca0400,
114040xa00000,
114050x7e828b,
114060xca1800,
114070xd4401e,
114080xd5801e,
114090x800053,
114100xd40075,
114110xd4401e,
114120xca0800,
114130xca0c00,
114140xca1000,
114150xd48019,
114160xd4c018,
114170xd50017,
114180xd4801e,
114190xd4c01e,
114200xd5001e,
114210xe2001e,
114220xca0400,
114230xa00000,
114240x7e828b,
114250xca0800,
114260xd48060,
114270xd4401e,
114280x800000,
114290xd4801e,
114300xca0800,
114310xd48061,
114320xd4401e,
114330x800000,
114340xd4801e,
114350xca0800,
114360xca0c00,
114370xd4401e,
114380xd48016,
114390xd4c016,
114400xd4801e,
114410x8001b8,
114420xd4c01e,
114430xc60843,
114440xca0c00,
114450xca1000,
114460x948004,
114470xca1400,
114480xe420f3,
114490xd42013,
114500xd56065,
114510xd4e01c,
114520xd5201c,
114530xd5601c,
114540x800000,
114550x062001,
114560xc60843,
114570xca0c00,
114580xca1000,
114590x9483f7,
114600xca1400,
114610xe420f3,
114620x800079,
114630xd42013,
114640xc60843,
114650xca0c00,
114660xca1000,
114670x9883ef,
114680xca1400,
114690xd40064,
114700x80008d,
114710x000000,
114720xc41432,
114730xc61843,
114740xc4082f,
114750x954005,
114760xc40c30,
114770xd4401e,
114780x800000,
114790xee001e,
114800x9583f5,
114810xc41031,
114820xd44033,
114830xd52065,
114840xd4a01c,
114850xd4e01c,
114860xd5201c,
114870xe4015e,
114880xd4001e,
114890x800000,
114900x062001,
114910xca1800,
114920x0a2001,
114930xd60076,
114940xc40836,
114950x988007,
114960xc61045,
114970x950110,
114980xd4001f,
114990xd46062,
115000x800000,
115010xd42062,
115020xcc3835,
115030xcc1433,
115040x8401bb,
115050xd40072,
115060xd5401e,
115070x800000,
115080xee001e,
115090xe2001a,
115100x8401bb,
115110xe2001a,
115120xcc104b,
115130xcc0447,
115140x2c9401,
115150x7d098b,
115160x984005,
115170x7d15cb,
115180xd4001a,
115190x8001b8,
115200xd4006d,
115210x344401,
115220xcc0c48,
115230x98403a,
115240xcc2c4a,
115250x958004,
115260xcc0449,
115270x8001b8,
115280xd4001a,
115290xd4c01a,
115300x282801,
115310x8400f0,
115320xcc1003,
115330x98801b,
115340x04380c,
115350x8400f0,
115360xcc1003,
115370x988017,
115380x043808,
115390x8400f0,
115400xcc1003,
115410x988013,
115420x043804,
115430x8400f0,
115440xcc1003,
115450x988014,
115460xcc104c,
115470x9a8009,
115480xcc144d,
115490x9840dc,
115500xd4006d,
115510xcc1848,
115520xd5001a,
115530xd5401a,
115540x8000c9,
115550xd5801a,
115560x96c0d5,
115570xd4006d,
115580x8001b8,
115590xd4006e,
115600x9ac003,
115610xd4006d,
115620xd4006e,
115630x800000,
115640xec007f,
115650x9ac0cc,
115660xd4006d,
115670x8001b8,
115680xd4006e,
115690xcc1403,
115700xcc1803,
115710xcc1c03,
115720x7d9103,
115730x7dd583,
115740x7d190c,
115750x35cc1f,
115760x35701f,
115770x7cf0cb,
115780x7cd08b,
115790x880000,
115800x7e8e8b,
115810x95c004,
115820xd4006e,
115830x8001b8,
115840xd4001a,
115850xd4c01a,
115860xcc0803,
115870xcc0c03,
115880xcc1003,
115890xcc1403,
115900xcc1803,
115910xcc1c03,
115920xcc2403,
115930xcc2803,
115940x35c41f,
115950x36b01f,
115960x7c704b,
115970x34f01f,
115980x7c704b,
115990x35701f,
116000x7c704b,
116010x7d8881,
116020x7dccc1,
116030x7e5101,
116040x7e9541,
116050x7c9082,
116060x7cd4c2,
116070x7c848b,
116080x9ac003,
116090x7c8c8b,
116100x2c8801,
116110x98809e,
116120xd4006d,
116130x98409c,
116140xd4006e,
116150xcc084c,
116160xcc0c4d,
116170xcc1048,
116180xd4801a,
116190xd4c01a,
116200x800101,
116210xd5001a,
116220xcc0832,
116230xd40032,
116240x9482d9,
116250xca0c00,
116260xd4401e,
116270x800000,
116280xd4001e,
116290xe4011e,
116300xd4001e,
116310xca0800,
116320xca0c00,
116330xca1000,
116340xd4401e,
116350xca1400,
116360xd4801e,
116370xd4c01e,
116380xd5001e,
116390xd5401e,
116400xd54034,
116410x800000,
116420xee001e,
116430x280404,
116440xe2001a,
116450xe2001a,
116460xd4401a,
116470xca3800,
116480xcc0803,
116490xcc0c03,
116500xcc0c03,
116510xcc0c03,
116520x9882bd,
116530x000000,
116540x8401bb,
116550xd7a06f,
116560x800000,
116570xee001f,
116580xca0400,
116590xc2ff00,
116600xcc0834,
116610xc13fff,
116620x7c74cb,
116630x7cc90b,
116640x7d010f,
116650x9902b0,
116660x7c738b,
116670x8401bb,
116680xd7a06f,
116690x800000,
116700xee001f,
116710xca0800,
116720x281900,
116730x7d898b,
116740x958014,
116750x281404,
116760xca0c00,
116770xca1000,
116780xca1c00,
116790xca2400,
116800xe2001f,
116810xd4c01a,
116820xd5001a,
116830xd5401a,
116840xcc1803,
116850xcc2c03,
116860xcc2c03,
116870xcc2c03,
116880x7da58b,
116890x7d9c47,
116900x984297,
116910x000000,
116920x800161,
116930xd4c01a,
116940xd4401e,
116950xd4801e,
116960x800000,
116970xee001e,
116980xe4011e,
116990xd4001e,
117000xd4401e,
117010xee001e,
117020xca0400,
117030xa00000,
117040x7e828b,
117050xe4013e,
117060xd4001e,
117070xd4401e,
117080xee001e,
117090xca0400,
117100xa00000,
117110x7e828b,
117120xca0800,
117130x248c06,
117140x0ccc06,
117150x98c006,
117160xcc104e,
117170x990004,
117180xd40073,
117190xe4011e,
117200xd4001e,
117210xd4401e,
117220xd4801e,
117230x800000,
117240xee001e,
117250xca0800,
117260xca0c00,
117270x34d018,
117280x251001,
117290x950021,
117300xc17fff,
117310xca1000,
117320xca1400,
117330xca1800,
117340xd4801d,
117350xd4c01d,
117360x7db18b,
117370xc14202,
117380xc2c001,
117390xd5801d,
117400x34dc0e,
117410x7d5d4c,
117420x7f734c,
117430xd7401e,
117440xd5001e,
117450xd5401e,
117460xc14200,
117470xc2c000,
117480x099c01,
117490x31dc10,
117500x7f5f4c,
117510x7f734c,
117520x042802,
117530x7d8380,
117540xd5a86f,
117550xd58066,
117560xd7401e,
117570xec005e,
117580xc82402,
117590xc82402,
117600x8001b8,
117610xd60076,
117620xd4401e,
117630xd4801e,
117640xd4c01e,
117650x800000,
117660xee001e,
117670x800000,
117680xee001f,
117690xd4001f,
117700x800000,
117710xd4001f,
117720xd4001f,
117730x880000,
117740xd4001f,
117750x000000,
117760x000000,
117770x000000,
117780x000000,
117790x000000,
117800x000000,
117810x000000,
117820x000000,
117830x000000,
117840x000000,
117850x000000,
117860x000000,
117870x000000,
117880x000000,
117890x000000,
117900x000000,
117910x000000,
117920x000000,
117930x000000,
117940x000000,
117950x000000,
117960x000000,
117970x000000,
117980x000000,
117990x000000,
118000x000000,
118010x000000,
118020x000000,
118030x000000,
118040x000000,
118050x000000,
118060x000000,
118070x000000,
118080x000000,
118090x000000,
118100x000000,
118110x000000,
118120x000000,
118130x000000,
118140x000000,
118150x000000,
118160x000000,
118170x000000,
118180x000000,
118190x000000,
118200x000000,
118210x000000,
118220x000000,
118230x000000,
118240x000000,
118250x000000,
118260x000000,
118270x000000,
118280x000000,
118290x000000,
118300x000000,
118310x000000,
118320x000000,
118330x000000,
118340x000000,
118350x000000,
118360x000000,
118370x000000,
118380x000000,
118390x000000,
118400x000000,
118410x010171,
118420x020178,
118430x03008f,
118440x04007f,
118450x050003,
118460x06003f,
118470x070032,
118480x08012c,
118490x090046,
118500x0a0036,
118510x1001b6,
118520x1700a2,
118530x22013a,
118540x230149,
118550x2000b4,
118560x240125,
118570x27004d,
118580x28006a,
118590x2a0060,
118600x2b0052,
118610x2f0065,
118620x320087,
118630x34017f,
118640x3c0156,
118650x3f0072,
118660x41018c,
118670x44012e,
118680x550173,
118690x56017a,
118700x60000b,
118710x610034,
118720x620038,
118730x630038,
118740x640038,
118750x650038,
118760x660038,
118770x670038,
118780x68003a,
118790x690041,
118800x6a0048,
118810x6b0048,
118820x6c0048,
118830x6d0048,
118840x6e0048,
118850x6f0048,
118860x000006,
118870x000006,
118880x000006,
118890x000006,
118900x000006,
118910x000006,
118920x000006,
118930x000006,
118940x000006,
118950x000006,
118960x000006,
118970x000006,
118980x000006,
118990x000006,
119000x000006,
119010x000006,
119020x000006,
119030x000006,
119040x000006,
11905};
11906
11907static const u32 RV670_cp_microcode[][3] = {
11908 { 0x00000000, 0xc0200400, 0x000 },
11909 { 0x00000000, 0x00a0000a, 0x000 },
11910 { 0x0000ffff, 0x00284621, 0x000 },
11911 { 0x00000000, 0xd9004800, 0x000 },
11912 { 0x00000000, 0xc0200400, 0x000 },
11913 { 0x00000000, 0x00a0000a, 0x000 },
11914 { 0x00000000, 0x00e00000, 0x000 },
11915 { 0x00010000, 0xc0294620, 0x000 },
11916 { 0x00000000, 0xd9004800, 0x000 },
11917 { 0x00000000, 0xc0200400, 0x000 },
11918 { 0x00000000, 0x00a0000a, 0x000 },
11919 { 0x81000000, 0x00204411, 0x000 },
11920 { 0x00000001, 0x00204811, 0x000 },
11921 { 0x00042004, 0x00604411, 0x67c },
11922 { 0x00000000, 0x00600000, 0x624 },
11923 { 0x00000000, 0x00600000, 0x638 },
11924 { 0x00000000, 0xc0200800, 0x000 },
11925 { 0x00000f00, 0x00281622, 0x000 },
11926 { 0x00000008, 0x00211625, 0x000 },
11927 { 0x00000018, 0x00203625, 0x000 },
11928 { 0x8d000000, 0x00204411, 0x000 },
11929 { 0x00000004, 0x002f0225, 0x000 },
11930 { 0x00000000, 0x0ce00000, 0x018 },
11931 { 0x00412000, 0x00404811, 0x019 },
11932 { 0x00422000, 0x00204811, 0x000 },
11933 { 0x8e000000, 0x00204411, 0x000 },
11934 { 0x00000028, 0x00204a2d, 0x000 },
11935 { 0x90000000, 0x00204411, 0x000 },
11936 { 0x00000000, 0x00204805, 0x000 },
11937 { 0x0000000c, 0x00211622, 0x000 },
11938 { 0x00000003, 0x00281625, 0x000 },
11939 { 0x00000019, 0x00211a22, 0x000 },
11940 { 0x00000004, 0x00281a26, 0x000 },
11941 { 0x00000000, 0x002914c5, 0x000 },
11942 { 0x00000019, 0x00203625, 0x000 },
11943 { 0x00000000, 0x003a1402, 0x000 },
11944 { 0x00000016, 0x00211625, 0x000 },
11945 { 0x00000003, 0x00281625, 0x000 },
11946 { 0x00000017, 0x00200e2d, 0x000 },
11947 { 0xfffffffc, 0x00280e23, 0x000 },
11948 { 0x00000000, 0x002914a3, 0x000 },
11949 { 0x00000017, 0x00203625, 0x000 },
11950 { 0x00008000, 0x00280e22, 0x000 },
11951 { 0x00000007, 0x00220e23, 0x000 },
11952 { 0x00000000, 0x0029386e, 0x000 },
11953 { 0x20000000, 0x00280e22, 0x000 },
11954 { 0x00000006, 0x00210e23, 0x000 },
11955 { 0x00000000, 0x0029386e, 0x000 },
11956 { 0x00000000, 0x00220222, 0x000 },
11957 { 0x00000000, 0x14e00000, 0x038 },
11958 { 0x00000000, 0x2ee00000, 0x035 },
11959 { 0x00000000, 0x2ce00000, 0x037 },
11960 { 0x00000000, 0x00400e2d, 0x039 },
11961 { 0x00000008, 0x00200e2d, 0x000 },
11962 { 0x00000009, 0x0040122d, 0x046 },
11963 { 0x00000001, 0x00400e2d, 0x039 },
11964 { 0x00000000, 0xc0200c00, 0x000 },
11965 { 0x003ffffc, 0x00281223, 0x000 },
11966 { 0x00000002, 0x00221224, 0x000 },
11967 { 0x0000001f, 0x00211e23, 0x000 },
11968 { 0x00000000, 0x14e00000, 0x03e },
11969 { 0x00000008, 0x00401c11, 0x041 },
11970 { 0x0000000d, 0x00201e2d, 0x000 },
11971 { 0x0000000f, 0x00281e27, 0x000 },
11972 { 0x00000003, 0x00221e27, 0x000 },
11973 { 0x7fc00000, 0x00281a23, 0x000 },
11974 { 0x00000014, 0x00211a26, 0x000 },
11975 { 0x00000001, 0x00331a26, 0x000 },
11976 { 0x00000008, 0x00221a26, 0x000 },
11977 { 0x00000000, 0x00290cc7, 0x000 },
11978 { 0x00000027, 0x00203624, 0x000 },
11979 { 0x00007f00, 0x00281221, 0x000 },
11980 { 0x00001400, 0x002f0224, 0x000 },
11981 { 0x00000000, 0x0ce00000, 0x04b },
11982 { 0x00000001, 0x00290e23, 0x000 },
11983 { 0x0000000e, 0x00203623, 0x000 },
11984 { 0x0000e000, 0x00204411, 0x000 },
11985 { 0xfff80000, 0x00294a23, 0x000 },
11986 { 0x00000000, 0x003a2c02, 0x000 },
11987 { 0x00000002, 0x00220e2b, 0x000 },
11988 { 0xfc000000, 0x00280e23, 0x000 },
11989 { 0x0000000f, 0x00203623, 0x000 },
11990 { 0x00001fff, 0x00294a23, 0x000 },
11991 { 0x00000027, 0x00204a2d, 0x000 },
11992 { 0x00000000, 0x00204811, 0x000 },
11993 { 0x00000029, 0x00200e2d, 0x000 },
11994 { 0x060a0200, 0x00294a23, 0x000 },
11995 { 0x00000000, 0x00204811, 0x000 },
11996 { 0x00000000, 0x00204811, 0x000 },
11997 { 0x00000001, 0x00210222, 0x000 },
11998 { 0x00000000, 0x14e00000, 0x061 },
11999 { 0x00000000, 0x2ee00000, 0x05f },
12000 { 0x00000000, 0x2ce00000, 0x05e },
12001 { 0x00000000, 0x00400e2d, 0x062 },
12002 { 0x00000001, 0x00400e2d, 0x062 },
12003 { 0x0000000a, 0x00200e2d, 0x000 },
12004 { 0x0000000b, 0x0040122d, 0x06a },
12005 { 0x00000000, 0xc0200c00, 0x000 },
12006 { 0x003ffffc, 0x00281223, 0x000 },
12007 { 0x00000002, 0x00221224, 0x000 },
12008 { 0x7fc00000, 0x00281623, 0x000 },
12009 { 0x00000014, 0x00211625, 0x000 },
12010 { 0x00000001, 0x00331625, 0x000 },
12011 { 0x80000000, 0x00280e23, 0x000 },
12012 { 0x00000000, 0x00290ca3, 0x000 },
12013 { 0x3ffffc00, 0x00290e23, 0x000 },
12014 { 0x0000001f, 0x00211e23, 0x000 },
12015 { 0x00000000, 0x14e00000, 0x06d },
12016 { 0x00000100, 0x00401c11, 0x070 },
12017 { 0x0000000d, 0x00201e2d, 0x000 },
12018 { 0x000000f0, 0x00281e27, 0x000 },
12019 { 0x00000004, 0x00221e27, 0x000 },
12020 { 0x81000000, 0x00204411, 0x000 },
12021 { 0x0000000d, 0x00204811, 0x000 },
12022 { 0xfffff0ff, 0x00281a30, 0x000 },
12023 { 0x0000a028, 0x00204411, 0x000 },
12024 { 0x00000000, 0x002948e6, 0x000 },
12025 { 0x0000a018, 0x00204411, 0x000 },
12026 { 0x3fffffff, 0x00284a23, 0x000 },
12027 { 0x0000a010, 0x00204411, 0x000 },
12028 { 0x00000000, 0x00204804, 0x000 },
12029 { 0x00000030, 0x0020162d, 0x000 },
12030 { 0x00000002, 0x00291625, 0x000 },
12031 { 0x00000030, 0x00203625, 0x000 },
12032 { 0x00000025, 0x0020162d, 0x000 },
12033 { 0x00000000, 0x002f00a3, 0x000 },
12034 { 0x00000000, 0x0cc00000, 0x083 },
12035 { 0x00000026, 0x0020162d, 0x000 },
12036 { 0x00000000, 0x002f00a4, 0x000 },
12037 { 0x00000000, 0x0cc00000, 0x084 },
12038 { 0x00000000, 0x00400000, 0x08a },
12039 { 0x00000025, 0x00203623, 0x000 },
12040 { 0x00000026, 0x00203624, 0x000 },
12041 { 0x00000017, 0x00201e2d, 0x000 },
12042 { 0x00000002, 0x00210227, 0x000 },
12043 { 0x00000000, 0x14e00000, 0x08a },
12044 { 0x00000000, 0x00600000, 0x659 },
12045 { 0x00000000, 0x00600000, 0x64d },
12046 { 0x00000002, 0x00210e22, 0x000 },
12047 { 0x00000000, 0x14c00000, 0x08d },
12048 { 0x00000012, 0xc0403620, 0x093 },
12049 { 0x00000000, 0x2ee00000, 0x091 },
12050 { 0x00000000, 0x2ce00000, 0x090 },
12051 { 0x00000002, 0x00400e2d, 0x092 },
12052 { 0x00000003, 0x00400e2d, 0x092 },
12053 { 0x0000000c, 0x00200e2d, 0x000 },
12054 { 0x00000012, 0x00203623, 0x000 },
12055 { 0x00000003, 0x00210e22, 0x000 },
12056 { 0x00000000, 0x14c00000, 0x098 },
12057 { 0x0000a00c, 0x00204411, 0x000 },
12058 { 0x00000000, 0xc0204800, 0x000 },
12059 { 0x00000000, 0xc0404800, 0x0a0 },
12060 { 0x0000a00c, 0x00204411, 0x000 },
12061 { 0x00000000, 0x00204811, 0x000 },
12062 { 0x00000000, 0x2ee00000, 0x09e },
12063 { 0x00000000, 0x2ce00000, 0x09d },
12064 { 0x00000002, 0x00400e2d, 0x09f },
12065 { 0x00000003, 0x00400e2d, 0x09f },
12066 { 0x0000000c, 0x00200e2d, 0x000 },
12067 { 0x00000000, 0x00204803, 0x000 },
12068 { 0x00000000, 0x003a0c02, 0x000 },
12069 { 0x003f0000, 0x00280e23, 0x000 },
12070 { 0x00000010, 0x00210e23, 0x000 },
12071 { 0x00000011, 0x00203623, 0x000 },
12072 { 0x0000001e, 0x0021022b, 0x000 },
12073 { 0x00000000, 0x14c00000, 0x0a7 },
12074 { 0x00000016, 0xc0203620, 0x000 },
12075 { 0x0000001f, 0x0021022b, 0x000 },
12076 { 0x00000000, 0x14c00000, 0x0aa },
12077 { 0x00000015, 0xc0203620, 0x000 },
12078 { 0x00000008, 0x00210e2b, 0x000 },
12079 { 0x0000007f, 0x00280e23, 0x000 },
12080 { 0x00000000, 0x002f0223, 0x000 },
12081 { 0x00000000, 0x0ce00000, 0x0e1 },
12082 { 0x00000000, 0x27000000, 0x000 },
12083 { 0x00000000, 0x00600000, 0x2a3 },
12084 { 0x00000001, 0x002f0223, 0x000 },
12085 { 0x00000000, 0x0ae00000, 0x0b3 },
12086 { 0x00000000, 0x00600000, 0x13a },
12087 { 0x81000000, 0x00204411, 0x000 },
12088 { 0x00000006, 0x00204811, 0x000 },
12089 { 0x0000000c, 0x00221e30, 0x000 },
12090 { 0x99800000, 0x00204411, 0x000 },
12091 { 0x00000004, 0x0020122d, 0x000 },
12092 { 0x00000008, 0x00221224, 0x000 },
12093 { 0x00000010, 0x00201811, 0x000 },
12094 { 0x00000000, 0x00291ce4, 0x000 },
12095 { 0x00000000, 0x00604807, 0x12f },
12096 { 0x9b000000, 0x00204411, 0x000 },
12097 { 0x00000000, 0x00204802, 0x000 },
12098 { 0x9c000000, 0x00204411, 0x000 },
12099 { 0x00000000, 0x0033146f, 0x000 },
12100 { 0x00000001, 0x00333e23, 0x000 },
12101 { 0x00000000, 0xd9004800, 0x000 },
12102 { 0x00000000, 0x00203c05, 0x000 },
12103 { 0x81000000, 0x00204411, 0x000 },
12104 { 0x0000000e, 0x00204811, 0x000 },
12105 { 0x00000000, 0x00201010, 0x000 },
12106 { 0x0000e007, 0x00204411, 0x000 },
12107 { 0x0000000f, 0x0021022b, 0x000 },
12108 { 0x00000000, 0x14c00000, 0x0cb },
12109 { 0x00f8ff08, 0x00204811, 0x000 },
12110 { 0x98000000, 0x00404811, 0x0dc },
12111 { 0x000000f0, 0x00280e22, 0x000 },
12112 { 0x000000a0, 0x002f0223, 0x000 },
12113 { 0x00000000, 0x0cc00000, 0x0da },
12114 { 0x00000011, 0x00200e2d, 0x000 },
12115 { 0x00000001, 0x002f0223, 0x000 },
12116 { 0x00000000, 0x0ce00000, 0x0d5 },
12117 { 0x00000002, 0x002f0223, 0x000 },
12118 { 0x00000000, 0x0ce00000, 0x0d4 },
12119 { 0x00003f00, 0x00400c11, 0x0d6 },
12120 { 0x00001f00, 0x00400c11, 0x0d6 },
12121 { 0x00000f00, 0x00200c11, 0x000 },
12122 { 0x00380009, 0x00294a23, 0x000 },
12123 { 0x3f000000, 0x00280e2b, 0x000 },
12124 { 0x00000002, 0x00220e23, 0x000 },
12125 { 0x00000007, 0x00494a23, 0x0dc },
12126 { 0x00380f09, 0x00204811, 0x000 },
12127 { 0x68000007, 0x00204811, 0x000 },
12128 { 0x00000008, 0x00214a27, 0x000 },
12129 { 0x00000000, 0x00204811, 0x000 },
12130 { 0x060a0200, 0x00294a24, 0x000 },
12131 { 0x00000000, 0x00204811, 0x000 },
12132 { 0x00000000, 0x00204811, 0x000 },
12133 { 0x0000a202, 0x00204411, 0x000 },
12134 { 0x00ff0000, 0x00280e22, 0x000 },
12135 { 0x00000080, 0x00294a23, 0x000 },
12136 { 0x00000027, 0x00200e2d, 0x000 },
12137 { 0x00000026, 0x0020122d, 0x000 },
12138 { 0x00000000, 0x002f0083, 0x000 },
12139 { 0x00000000, 0x0ce00000, 0x0ea },
12140 { 0x00000000, 0x00600000, 0x653 },
12141 { 0x00000000, 0x00400000, 0x0eb },
12142 { 0x00000000, 0x00600000, 0x656 },
12143 { 0x00000007, 0x0020222d, 0x000 },
12144 { 0x00000005, 0x00220e22, 0x000 },
12145 { 0x00100000, 0x00280e23, 0x000 },
12146 { 0x00000000, 0x00292068, 0x000 },
12147 { 0x00000000, 0x003a0c02, 0x000 },
12148 { 0x000000ef, 0x00280e23, 0x000 },
12149 { 0x00000000, 0x00292068, 0x000 },
12150 { 0x00000017, 0x00200e2d, 0x000 },
12151 { 0x00000003, 0x00210223, 0x000 },
12152 { 0x00000000, 0x14e00000, 0x0f8 },
12153 { 0x0000000b, 0x00210228, 0x000 },
12154 { 0x00000000, 0x14c00000, 0x0f8 },
12155 { 0x00000400, 0x00292228, 0x000 },
12156 { 0x00000014, 0x00203628, 0x000 },
12157 { 0x0000001c, 0x00210e22, 0x000 },
12158 { 0x00000000, 0x14c00000, 0x0fd },
12159 { 0x0000a30c, 0x00204411, 0x000 },
12160 { 0x00000000, 0x00204811, 0x000 },
12161 { 0x0000001e, 0x00210e22, 0x000 },
12162 { 0x00000000, 0x14c00000, 0x10b },
12163 { 0x0000a30f, 0x00204411, 0x000 },
12164 { 0x00000011, 0x00200e2d, 0x000 },
12165 { 0x00000001, 0x002f0223, 0x000 },
12166 { 0x00000000, 0x0cc00000, 0x104 },
12167 { 0xffffffff, 0x00404811, 0x10b },
12168 { 0x00000002, 0x002f0223, 0x000 },
12169 { 0x00000000, 0x0cc00000, 0x107 },
12170 { 0x0000ffff, 0x00404811, 0x10b },
12171 { 0x00000004, 0x002f0223, 0x000 },
12172 { 0x00000000, 0x0cc00000, 0x10a },
12173 { 0x000000ff, 0x00404811, 0x10b },
12174 { 0x00000001, 0x00204811, 0x000 },
12175 { 0x0002c400, 0x00204411, 0x000 },
12176 { 0x0000001f, 0x00210e22, 0x000 },
12177 { 0x00000000, 0x14c00000, 0x112 },
12178 { 0x00000010, 0x40210e20, 0x000 },
12179 { 0x00000013, 0x00203623, 0x000 },
12180 { 0x00000018, 0x40224a20, 0x000 },
12181 { 0x00000010, 0xc0424a20, 0x114 },
12182 { 0x00000000, 0x00200c11, 0x000 },
12183 { 0x00000013, 0x00203623, 0x000 },
12184 { 0x00000000, 0x00204811, 0x000 },
12185 { 0x00000000, 0x00204811, 0x000 },
12186 { 0x0000000a, 0x00201011, 0x000 },
12187 { 0x00000000, 0x002f0224, 0x000 },
12188 { 0x00000000, 0x0ce00000, 0x11b },
12189 { 0x00000000, 0x00204811, 0x000 },
12190 { 0x00000001, 0x00531224, 0x117 },
12191 { 0xffbfffff, 0x00283a2e, 0x000 },
12192 { 0x0000001b, 0x00210222, 0x000 },
12193 { 0x00000000, 0x14c00000, 0x12e },
12194 { 0x81000000, 0x00204411, 0x000 },
12195 { 0x0000000d, 0x00204811, 0x000 },
12196 { 0x00000018, 0x00220e30, 0x000 },
12197 { 0xfc000000, 0x00280e23, 0x000 },
12198 { 0x81000000, 0x00204411, 0x000 },
12199 { 0x0000000e, 0x00204811, 0x000 },
12200 { 0x00000000, 0x00201010, 0x000 },
12201 { 0x0000e00e, 0x00204411, 0x000 },
12202 { 0x07f8ff08, 0x00204811, 0x000 },
12203 { 0x00000000, 0x00294a23, 0x000 },
12204 { 0x0000001c, 0x00201e2d, 0x000 },
12205 { 0x00000008, 0x00214a27, 0x000 },
12206 { 0x00000000, 0x00204811, 0x000 },
12207 { 0x060a0200, 0x00294a24, 0x000 },
12208 { 0x00000000, 0x00204811, 0x000 },
12209 { 0x00000000, 0x00204811, 0x000 },
12210 { 0x00000000, 0x00800000, 0x000 },
12211 { 0x81000000, 0x00204411, 0x000 },
12212 { 0x00000001, 0x00204811, 0x000 },
12213 { 0x0000217c, 0x00204411, 0x000 },
12214 { 0x00800000, 0x00204811, 0x000 },
12215 { 0x00000000, 0x00204806, 0x000 },
12216 { 0x00000008, 0x00214a27, 0x000 },
12217 { 0x00000000, 0x17000000, 0x000 },
12218 { 0x0004217f, 0x00604411, 0x67c },
12219 { 0x0000001f, 0x00210230, 0x000 },
12220 { 0x00000000, 0x14c00000, 0x67b },
12221 { 0x00000004, 0x00404c11, 0x135 },
12222 { 0x81000000, 0x00204411, 0x000 },
12223 { 0x00000001, 0x00204811, 0x000 },
12224 { 0x000021f8, 0x00204411, 0x000 },
12225 { 0x0000001c, 0x00204811, 0x000 },
12226 { 0x000421f9, 0x00604411, 0x67c },
12227 { 0x00000011, 0x00210230, 0x000 },
12228 { 0x00000000, 0x14e00000, 0x13c },
12229 { 0x00000000, 0x00800000, 0x000 },
12230 { 0x00000000, 0x00600000, 0x00b },
12231 { 0x00000000, 0x00600411, 0x315 },
12232 { 0x00000000, 0x00200411, 0x000 },
12233 { 0x00000000, 0x00600811, 0x1b2 },
12234 { 0x00000000, 0x00600000, 0x160 },
12235 { 0x0000ffff, 0x40280e20, 0x000 },
12236 { 0x00000010, 0xc0211220, 0x000 },
12237 { 0x0000ffff, 0x40280620, 0x000 },
12238 { 0x00000010, 0xc0210a20, 0x000 },
12239 { 0x00000000, 0x00341461, 0x000 },
12240 { 0x00000000, 0x00741882, 0x2bb },
12241 { 0x0001a1fd, 0x00604411, 0x2e0 },
12242 { 0x00003fff, 0x002f022f, 0x000 },
12243 { 0x00000000, 0x0cc00000, 0x147 },
12244 { 0x00000000, 0xc0400400, 0x001 },
12245 { 0x00000000, 0x00600000, 0x00b },
12246 { 0x00000000, 0x00600411, 0x315 },
12247 { 0x00000000, 0x00200411, 0x000 },
12248 { 0x00000000, 0x00600811, 0x1b2 },
12249 { 0x00003fff, 0x002f022f, 0x000 },
12250 { 0x00000000, 0x0ce00000, 0x000 },
12251 { 0x00000000, 0x00600000, 0x160 },
12252 { 0x00000010, 0x40210e20, 0x000 },
12253 { 0x0000ffff, 0xc0281220, 0x000 },
12254 { 0x00000010, 0x40211620, 0x000 },
12255 { 0x0000ffff, 0xc0681a20, 0x2bb },
12256 { 0x0001a1fd, 0x00604411, 0x2e0 },
12257 { 0x00003fff, 0x002f022f, 0x000 },
12258 { 0x00000000, 0x0cc00000, 0x158 },
12259 { 0x00000000, 0xc0400400, 0x001 },
12260 { 0x0000225c, 0x00204411, 0x000 },
12261 { 0x00000001, 0x00300a2f, 0x000 },
12262 { 0x00000001, 0x00210a22, 0x000 },
12263 { 0x00000003, 0x00384a22, 0x000 },
12264 { 0x00002256, 0x00204411, 0x000 },
12265 { 0x0000001a, 0x00204811, 0x000 },
12266 { 0x0000a1fc, 0x00204411, 0x000 },
12267 { 0x00000001, 0x00804811, 0x000 },
12268 { 0x00000000, 0x00600000, 0x00b },
12269 { 0x00000000, 0x00600000, 0x18f },
12270 { 0x00000000, 0x00600000, 0x1a0 },
12271 { 0x00003fff, 0x002f022f, 0x000 },
12272 { 0x00000000, 0x0ce00000, 0x000 },
12273 { 0x00000000, 0x00202c08, 0x000 },
12274 { 0x00000000, 0x00202411, 0x000 },
12275 { 0x00000000, 0x00202811, 0x000 },
12276 { 0x00002256, 0x00204411, 0x000 },
12277 { 0x00000016, 0x00204811, 0x000 },
12278 { 0x0000225c, 0x00204411, 0x000 },
12279 { 0x00000003, 0x00204811, 0x000 },
12280 { 0x93800000, 0x00204411, 0x000 },
12281 { 0x00000002, 0x00221e29, 0x000 },
12282 { 0x00000000, 0x007048eb, 0x19c },
12283 { 0x00000000, 0x00600000, 0x2bb },
12284 { 0x00000001, 0x40330620, 0x000 },
12285 { 0x00000000, 0xc0302409, 0x000 },
12286 { 0x00003fff, 0x002f022f, 0x000 },
12287 { 0x00000000, 0x0ce00000, 0x000 },
12288 { 0x00000000, 0x00600000, 0x2a3 },
12289 { 0x00000000, 0x002f0221, 0x000 },
12290 { 0x00000000, 0x0ae00000, 0x181 },
12291 { 0x00000000, 0x00600000, 0x13a },
12292 { 0x00000000, 0x00400000, 0x186 },
12293 { 0x95000000, 0x00204411, 0x000 },
12294 { 0x00000000, 0x002f0221, 0x000 },
12295 { 0x00000000, 0x0ce00000, 0x186 },
12296 { 0x00000000, 0xc0204800, 0x000 },
12297 { 0x00000001, 0x00530621, 0x182 },
12298 { 0x92000000, 0x00204411, 0x000 },
12299 { 0x00000000, 0xc0604800, 0x197 },
12300 { 0x0001a1fd, 0x00204411, 0x000 },
12301 { 0x00000011, 0x0020062d, 0x000 },
12302 { 0x00000000, 0x0078042a, 0x2fb },
12303 { 0x00000000, 0x00202809, 0x000 },
12304 { 0x00003fff, 0x002f022f, 0x000 },
12305 { 0x00000000, 0x0cc00000, 0x174 },
12306 { 0x00000000, 0xc0400400, 0x001 },
12307 { 0x00000210, 0x00600411, 0x315 },
12308 { 0x00003fff, 0x002f022f, 0x000 },
12309 { 0x00000000, 0x0ce00000, 0x194 },
12310 { 0x00000015, 0xc0203620, 0x000 },
12311 { 0x00000016, 0xc0203620, 0x000 },
12312 { 0x3f800000, 0x00200411, 0x000 },
12313 { 0x46000000, 0x00600811, 0x1b2 },
12314 { 0x00000000, 0x00800000, 0x000 },
12315 { 0x0000a1fc, 0x00204411, 0x000 },
12316 { 0x00003fff, 0x002f022f, 0x000 },
12317 { 0x00000000, 0x0cc00000, 0x19b },
12318 { 0x00000001, 0x00804811, 0x000 },
12319 { 0x00000021, 0x00804811, 0x000 },
12320 { 0x0000ffff, 0x40280e20, 0x000 },
12321 { 0x00000010, 0xc0211220, 0x000 },
12322 { 0x0000ffff, 0x40281620, 0x000 },
12323 { 0x00000010, 0xc0811a20, 0x000 },
12324 { 0x81000000, 0x00204411, 0x000 },
12325 { 0x00000006, 0x00204811, 0x000 },
12326 { 0x00000008, 0x00221e30, 0x000 },
12327 { 0x00000029, 0x00201a2d, 0x000 },
12328 { 0x0000e000, 0x00204411, 0x000 },
12329 { 0xfffbff09, 0x00204811, 0x000 },
12330 { 0x0000000f, 0x0020222d, 0x000 },
12331 { 0x00001fff, 0x00294a28, 0x000 },
12332 { 0x00000006, 0x0020222d, 0x000 },
12333 { 0x00000000, 0x002920e8, 0x000 },
12334 { 0x00000000, 0x00204808, 0x000 },
12335 { 0x00000000, 0x00204811, 0x000 },
12336 { 0x060a0200, 0x00294a26, 0x000 },
12337 { 0x00000000, 0x00204811, 0x000 },
12338 { 0x00000000, 0x00204811, 0x000 },
12339 { 0x00000100, 0x00201811, 0x000 },
12340 { 0x00000008, 0x00621e28, 0x12f },
12341 { 0x00000008, 0x00822228, 0x000 },
12342 { 0x0002c000, 0x00204411, 0x000 },
12343 { 0x00000015, 0x00600e2d, 0x1bd },
12344 { 0x00000016, 0x00600e2d, 0x1bd },
12345 { 0x0000c008, 0x00204411, 0x000 },
12346 { 0x00000017, 0x00200e2d, 0x000 },
12347 { 0x00000000, 0x14c00000, 0x1b9 },
12348 { 0x00000000, 0x00200411, 0x000 },
12349 { 0x00000000, 0x00204801, 0x000 },
12350 { 0x39000000, 0x00204811, 0x000 },
12351 { 0x00000000, 0x00204811, 0x000 },
12352 { 0x00000000, 0x00804802, 0x000 },
12353 { 0x00000018, 0x00202e2d, 0x000 },
12354 { 0x00000000, 0x003b0d63, 0x000 },
12355 { 0x00000008, 0x00224a23, 0x000 },
12356 { 0x00000010, 0x00224a23, 0x000 },
12357 { 0x00000018, 0x00224a23, 0x000 },
12358 { 0x00000000, 0x00804803, 0x000 },
12359 { 0x00000000, 0x00600000, 0x00b },
12360 { 0x00001000, 0x00600411, 0x315 },
12361 { 0x00000000, 0x00200411, 0x000 },
12362 { 0x00000000, 0x00600811, 0x1b2 },
12363 { 0x00000007, 0x0021062f, 0x000 },
12364 { 0x00000013, 0x00200a2d, 0x000 },
12365 { 0x00000001, 0x00202c11, 0x000 },
12366 { 0x0000ffff, 0x40282220, 0x000 },
12367 { 0x0000000f, 0x00262228, 0x000 },
12368 { 0x00000010, 0x40212620, 0x000 },
12369 { 0x0000000f, 0x00262629, 0x000 },
12370 { 0x00000000, 0x00202802, 0x000 },
12371 { 0x00002256, 0x00204411, 0x000 },
12372 { 0x0000001b, 0x00204811, 0x000 },
12373 { 0x00000000, 0x002f0221, 0x000 },
12374 { 0x00000000, 0x0ce00000, 0x1e0 },
12375 { 0x0000225c, 0x00204411, 0x000 },
12376 { 0x00000081, 0x00204811, 0x000 },
12377 { 0x0000a1fc, 0x00204411, 0x000 },
12378 { 0x00000001, 0x00204811, 0x000 },
12379 { 0x00000080, 0x00201c11, 0x000 },
12380 { 0x00000000, 0x002f0227, 0x000 },
12381 { 0x00000000, 0x0ce00000, 0x1dc },
12382 { 0x00000000, 0x00600000, 0x1e9 },
12383 { 0x00000001, 0x00531e27, 0x1d8 },
12384 { 0x00000001, 0x00202c11, 0x000 },
12385 { 0x0000001f, 0x00280a22, 0x000 },
12386 { 0x0000001f, 0x00282a2a, 0x000 },
12387 { 0x00000001, 0x00530621, 0x1d1 },
12388 { 0x0000225c, 0x00204411, 0x000 },
12389 { 0x00000002, 0x00304a2f, 0x000 },
12390 { 0x0000a1fc, 0x00204411, 0x000 },
12391 { 0x00000001, 0x00204811, 0x000 },
12392 { 0x00000001, 0x00301e2f, 0x000 },
12393 { 0x00000000, 0x002f0227, 0x000 },
12394 { 0x00000000, 0x0ce00000, 0x000 },
12395 { 0x00000000, 0x00600000, 0x1e9 },
12396 { 0x00000001, 0x00531e27, 0x1e5 },
12397 { 0x0000ffff, 0x40280e20, 0x000 },
12398 { 0x0000000f, 0x00260e23, 0x000 },
12399 { 0x00000010, 0xc0211220, 0x000 },
12400 { 0x0000000f, 0x00261224, 0x000 },
12401 { 0x00000000, 0x00201411, 0x000 },
12402 { 0x00000000, 0x00601811, 0x2bb },
12403 { 0x0001a1fd, 0x00204411, 0x000 },
12404 { 0x00000000, 0x002f022b, 0x000 },
12405 { 0x00000000, 0x0ce00000, 0x1f8 },
12406 { 0x00000010, 0x00221628, 0x000 },
12407 { 0xffff0000, 0x00281625, 0x000 },
12408 { 0x0000ffff, 0x00281a29, 0x000 },
12409 { 0x00000000, 0x002948c5, 0x000 },
12410 { 0x00000000, 0x0020480a, 0x000 },
12411 { 0x00000000, 0x00202c11, 0x000 },
12412 { 0x00000010, 0x00221623, 0x000 },
12413 { 0xffff0000, 0x00281625, 0x000 },
12414 { 0x0000ffff, 0x00281a24, 0x000 },
12415 { 0x00000000, 0x002948c5, 0x000 },
12416 { 0x00000000, 0x00731503, 0x205 },
12417 { 0x00000000, 0x00201805, 0x000 },
12418 { 0x00000000, 0x00731524, 0x205 },
12419 { 0x00000000, 0x002d14c5, 0x000 },
12420 { 0x00000000, 0x003008a2, 0x000 },
12421 { 0x00000000, 0x00204802, 0x000 },
12422 { 0x00000000, 0x00202802, 0x000 },
12423 { 0x00000000, 0x00202003, 0x000 },
12424 { 0x00000000, 0x00802404, 0x000 },
12425 { 0x0000000f, 0x00210225, 0x000 },
12426 { 0x00000000, 0x14c00000, 0x67b },
12427 { 0x00000000, 0x002b1405, 0x000 },
12428 { 0x00000001, 0x00901625, 0x000 },
12429 { 0x00000000, 0x00600000, 0x00b },
12430 { 0x00000000, 0x00600411, 0x315 },
12431 { 0x00000000, 0x00200411, 0x000 },
12432 { 0x00000000, 0x00600811, 0x1b2 },
12433 { 0x00002256, 0x00204411, 0x000 },
12434 { 0x0000001a, 0x00294a22, 0x000 },
12435 { 0x00000000, 0xc0200000, 0x000 },
12436 { 0x00003fff, 0x002f022f, 0x000 },
12437 { 0x00000000, 0x0ce00000, 0x000 },
12438 { 0x00000000, 0xc0200400, 0x000 },
12439 { 0x0000225c, 0x00204411, 0x000 },
12440 { 0x00000003, 0x00384a21, 0x000 },
12441 { 0x0000a1fc, 0x00204411, 0x000 },
12442 { 0x00000001, 0x00204811, 0x000 },
12443 { 0x0000ffff, 0x40281220, 0x000 },
12444 { 0x00000010, 0xc0211a20, 0x000 },
12445 { 0x0000ffff, 0x40280e20, 0x000 },
12446 { 0x00000010, 0xc0211620, 0x000 },
12447 { 0x00000000, 0x00741465, 0x2bb },
12448 { 0x0001a1fd, 0x00604411, 0x2e0 },
12449 { 0x00000001, 0x00330621, 0x000 },
12450 { 0x00000000, 0x002f0221, 0x000 },
12451 { 0x00000000, 0x0cc00000, 0x219 },
12452 { 0x00003fff, 0x002f022f, 0x000 },
12453 { 0x00000000, 0x0cc00000, 0x212 },
12454 { 0x00000000, 0xc0400400, 0x001 },
12455 { 0x00000000, 0x00600000, 0x638 },
12456 { 0x00000000, 0x0040040f, 0x213 },
12457 { 0x00000000, 0x00600000, 0x624 },
12458 { 0x00000000, 0x00600000, 0x638 },
12459 { 0x00000210, 0x00600411, 0x315 },
12460 { 0x00000000, 0x00600000, 0x1a0 },
12461 { 0x00000000, 0x00600000, 0x19c },
12462 { 0x00000000, 0x00600000, 0x2bb },
12463 { 0x00000000, 0x00600000, 0x2a3 },
12464 { 0x93800000, 0x00204411, 0x000 },
12465 { 0x00000000, 0x00204808, 0x000 },
12466 { 0x00000000, 0x002f022f, 0x000 },
12467 { 0x00000000, 0x0ae00000, 0x232 },
12468 { 0x00000000, 0x00600000, 0x13a },
12469 { 0x00000000, 0x00400000, 0x236 },
12470 { 0x95000000, 0x00204411, 0x000 },
12471 { 0x00000000, 0x002f022f, 0x000 },
12472 { 0x00000000, 0x0ce00000, 0x236 },
12473 { 0x00000000, 0xc0404800, 0x233 },
12474 { 0x92000000, 0x00204411, 0x000 },
12475 { 0x00000000, 0xc0204800, 0x000 },
12476 { 0x00002256, 0x00204411, 0x000 },
12477 { 0x00000016, 0x00204811, 0x000 },
12478 { 0x0000225c, 0x00204411, 0x000 },
12479 { 0x00000003, 0x00204811, 0x000 },
12480 { 0x0000a1fc, 0x00204411, 0x000 },
12481 { 0x00000001, 0x00204811, 0x000 },
12482 { 0x0001a1fd, 0x00204411, 0x000 },
12483 { 0x00000000, 0x00600411, 0x2fb },
12484 { 0x00000000, 0xc0400400, 0x001 },
12485 { 0x00000000, 0x00600000, 0x624 },
12486 { 0x0000a00c, 0x00204411, 0x000 },
12487 { 0x00000000, 0xc0204800, 0x000 },
12488 { 0x00000000, 0xc0404800, 0x000 },
12489 { 0x00000000, 0x00600000, 0x00b },
12490 { 0x00000018, 0x40210a20, 0x000 },
12491 { 0x00000003, 0x002f0222, 0x000 },
12492 { 0x00000000, 0x0ae00000, 0x24c },
12493 { 0x00000014, 0x0020222d, 0x000 },
12494 { 0x00080101, 0x00292228, 0x000 },
12495 { 0x00000014, 0x00203628, 0x000 },
12496 { 0x0000a30c, 0x00204411, 0x000 },
12497 { 0x00000000, 0xc0204800, 0x000 },
12498 { 0x00000000, 0xc0204800, 0x000 },
12499 { 0x00000000, 0xc0404800, 0x251 },
12500 { 0x00000000, 0x00600000, 0x00b },
12501 { 0x00000010, 0x00600411, 0x315 },
12502 { 0x3f800000, 0x00200411, 0x000 },
12503 { 0x00000000, 0x00600811, 0x1b2 },
12504 { 0x0000225c, 0x00204411, 0x000 },
12505 { 0x00000003, 0x00204811, 0x000 },
12506 { 0x00000000, 0x00600000, 0x27c },
12507 { 0x00000017, 0x00201e2d, 0x000 },
12508 { 0x00000001, 0x00211e27, 0x000 },
12509 { 0x00000000, 0x14e00000, 0x26a },
12510 { 0x00000012, 0x00201e2d, 0x000 },
12511 { 0x0000ffff, 0x00281e27, 0x000 },
12512 { 0x00000000, 0x00341c27, 0x000 },
12513 { 0x00000000, 0x12c00000, 0x25f },
12514 { 0x00000000, 0x00201c11, 0x000 },
12515 { 0x00000000, 0x002f00e5, 0x000 },
12516 { 0x00000000, 0x08c00000, 0x262 },
12517 { 0x00000000, 0x00201407, 0x000 },
12518 { 0x00000012, 0x00201e2d, 0x000 },
12519 { 0x00000010, 0x00211e27, 0x000 },
12520 { 0x00000000, 0x00341c47, 0x000 },
12521 { 0x00000000, 0x12c00000, 0x267 },
12522 { 0x00000000, 0x00201c11, 0x000 },
12523 { 0x00000000, 0x002f00e6, 0x000 },
12524 { 0x00000000, 0x08c00000, 0x26a },
12525 { 0x00000000, 0x00201807, 0x000 },
12526 { 0x00000000, 0x00600000, 0x2c1 },
12527 { 0x00002256, 0x00204411, 0x000 },
12528 { 0x00000000, 0x00342023, 0x000 },
12529 { 0x00000000, 0x12c00000, 0x272 },
12530 { 0x00000000, 0x00342044, 0x000 },
12531 { 0x00000000, 0x12c00000, 0x271 },
12532 { 0x00000016, 0x00404811, 0x276 },
12533 { 0x00000018, 0x00404811, 0x276 },
12534 { 0x00000000, 0x00342044, 0x000 },
12535 { 0x00000000, 0x12c00000, 0x275 },
12536 { 0x00000017, 0x00404811, 0x276 },
12537 { 0x00000019, 0x00204811, 0x000 },
12538 { 0x0000a1fc, 0x00204411, 0x000 },
12539 { 0x00000001, 0x00204811, 0x000 },
12540 { 0x0001a1fd, 0x00604411, 0x2e9 },
12541 { 0x00003fff, 0x002f022f, 0x000 },
12542 { 0x00000000, 0x0cc00000, 0x256 },
12543 { 0x00000000, 0xc0400400, 0x001 },
12544 { 0x00000010, 0x40210620, 0x000 },
12545 { 0x0000ffff, 0xc0280a20, 0x000 },
12546 { 0x00000010, 0x40210e20, 0x000 },
12547 { 0x0000ffff, 0xc0281220, 0x000 },
12548 { 0x00000010, 0x40211620, 0x000 },
12549 { 0x0000ffff, 0xc0881a20, 0x000 },
12550 { 0x81000000, 0x00204411, 0x000 },
12551 { 0x00000001, 0x00204811, 0x000 },
12552 { 0x00042004, 0x00604411, 0x67c },
12553 { 0x00000000, 0x00600000, 0x624 },
12554 { 0x00000000, 0xc0600000, 0x2a3 },
12555 { 0x00000005, 0x00200a2d, 0x000 },
12556 { 0x00000008, 0x00220a22, 0x000 },
12557 { 0x0000002b, 0x00201a2d, 0x000 },
12558 { 0x0000001c, 0x00201e2d, 0x000 },
12559 { 0x00007000, 0x00281e27, 0x000 },
12560 { 0x00000000, 0x00311ce6, 0x000 },
12561 { 0x0000002a, 0x00201a2d, 0x000 },
12562 { 0x0000000c, 0x00221a26, 0x000 },
12563 { 0x00000000, 0x002f00e6, 0x000 },
12564 { 0x00000000, 0x06e00000, 0x292 },
12565 { 0x00000000, 0x00201c11, 0x000 },
12566 { 0x00000000, 0x00200c11, 0x000 },
12567 { 0x0000002b, 0x00203623, 0x000 },
12568 { 0x00000010, 0x00201811, 0x000 },
12569 { 0x00000000, 0x00691ce2, 0x12f },
12570 { 0x93800000, 0x00204411, 0x000 },
12571 { 0x00000000, 0x00204807, 0x000 },
12572 { 0x95000000, 0x00204411, 0x000 },
12573 { 0x00000000, 0x002f022f, 0x000 },
12574 { 0x00000000, 0x0ce00000, 0x29d },
12575 { 0x00000001, 0x00333e2f, 0x000 },
12576 { 0x00000000, 0xd9004800, 0x000 },
12577 { 0x92000000, 0x00204411, 0x000 },
12578 { 0x00000000, 0xc0204800, 0x000 },
12579 { 0x0000001c, 0x00403627, 0x000 },
12580 { 0x0000000c, 0xc0220a20, 0x000 },
12581 { 0x00000029, 0x00203622, 0x000 },
12582 { 0x00000028, 0xc0403620, 0x000 },
12583 { 0x0000a2a4, 0x00204411, 0x000 },
12584 { 0x00000009, 0x00204811, 0x000 },
12585 { 0xa1000000, 0x00204411, 0x000 },
12586 { 0x00000001, 0x00804811, 0x000 },
12587 { 0x00000021, 0x00201e2d, 0x000 },
12588 { 0x00000000, 0x002c1ce3, 0x000 },
12589 { 0x00000021, 0x00203627, 0x000 },
12590 { 0x00000022, 0x00201e2d, 0x000 },
12591 { 0x00000000, 0x002c1ce4, 0x000 },
12592 { 0x00000022, 0x00203627, 0x000 },
12593 { 0x00000023, 0x00201e2d, 0x000 },
12594 { 0x00000000, 0x003120a3, 0x000 },
12595 { 0x00000000, 0x002d1d07, 0x000 },
12596 { 0x00000023, 0x00203627, 0x000 },
12597 { 0x00000024, 0x00201e2d, 0x000 },
12598 { 0x00000000, 0x003120c4, 0x000 },
12599 { 0x00000000, 0x002d1d07, 0x000 },
12600 { 0x00000024, 0x00803627, 0x000 },
12601 { 0x00000021, 0x00203623, 0x000 },
12602 { 0x00000022, 0x00203624, 0x000 },
12603 { 0x00000000, 0x00311ca3, 0x000 },
12604 { 0x00000023, 0x00203627, 0x000 },
12605 { 0x00000000, 0x00311cc4, 0x000 },
12606 { 0x00000024, 0x00803627, 0x000 },
12607 { 0x0000001a, 0x00203627, 0x000 },
12608 { 0x0000001b, 0x00203628, 0x000 },
12609 { 0x00000017, 0x00201e2d, 0x000 },
12610 { 0x00000002, 0x00210227, 0x000 },
12611 { 0x00000000, 0x14c00000, 0x2dc },
12612 { 0x00000000, 0x00400000, 0x2d9 },
12613 { 0x0000001a, 0x00203627, 0x000 },
12614 { 0x0000001b, 0x00203628, 0x000 },
12615 { 0x00000017, 0x00201e2d, 0x000 },
12616 { 0x00000002, 0x00210227, 0x000 },
12617 { 0x00000000, 0x14e00000, 0x2d9 },
12618 { 0x00000003, 0x00210227, 0x000 },
12619 { 0x00000000, 0x14e00000, 0x2dc },
12620 { 0x00000023, 0x00201e2d, 0x000 },
12621 { 0x00000000, 0x002e00e1, 0x000 },
12622 { 0x00000000, 0x02c00000, 0x2dc },
12623 { 0x00000021, 0x00201e2d, 0x000 },
12624 { 0x00000000, 0x003120a1, 0x000 },
12625 { 0x00000000, 0x002e00e8, 0x000 },
12626 { 0x00000000, 0x06c00000, 0x2dc },
12627 { 0x00000024, 0x00201e2d, 0x000 },
12628 { 0x00000000, 0x002e00e2, 0x000 },
12629 { 0x00000000, 0x02c00000, 0x2dc },
12630 { 0x00000022, 0x00201e2d, 0x000 },
12631 { 0x00000000, 0x003120c2, 0x000 },
12632 { 0x00000000, 0x002e00e8, 0x000 },
12633 { 0x00000000, 0x06c00000, 0x2dc },
12634 { 0x00000000, 0x00600000, 0x659 },
12635 { 0x00000000, 0x00600000, 0x2b5 },
12636 { 0x00000000, 0x00400000, 0x2de },
12637 { 0x00000000, 0x00600000, 0x2b5 },
12638 { 0x00000000, 0x00600000, 0x650 },
12639 { 0x00000000, 0x00400000, 0x2de },
12640 { 0x00000000, 0x00600000, 0x2a7 },
12641 { 0x00000000, 0x00400000, 0x2de },
12642 { 0x0000001a, 0x00201e2d, 0x000 },
12643 { 0x0000001b, 0x0080222d, 0x000 },
12644 { 0x00000010, 0x00221e23, 0x000 },
12645 { 0x00000000, 0x00294887, 0x000 },
12646 { 0x00000000, 0x00311ca3, 0x000 },
12647 { 0x00000010, 0x00221e27, 0x000 },
12648 { 0x00000000, 0x00294887, 0x000 },
12649 { 0x00000010, 0x00221e23, 0x000 },
12650 { 0x00000000, 0x003120c4, 0x000 },
12651 { 0x0000ffff, 0x00282228, 0x000 },
12652 { 0x00000000, 0x00894907, 0x000 },
12653 { 0x00000010, 0x00221e23, 0x000 },
12654 { 0x00000000, 0x00294887, 0x000 },
12655 { 0x00000010, 0x00221e21, 0x000 },
12656 { 0x00000000, 0x00294847, 0x000 },
12657 { 0x00000000, 0x00311ca3, 0x000 },
12658 { 0x00000010, 0x00221e27, 0x000 },
12659 { 0x00000000, 0x00294887, 0x000 },
12660 { 0x00000000, 0x00311ca1, 0x000 },
12661 { 0x00000010, 0x00221e27, 0x000 },
12662 { 0x00000000, 0x00294847, 0x000 },
12663 { 0x00000010, 0x00221e23, 0x000 },
12664 { 0x00000000, 0x003120c4, 0x000 },
12665 { 0x0000ffff, 0x00282228, 0x000 },
12666 { 0x00000000, 0x00294907, 0x000 },
12667 { 0x00000010, 0x00221e21, 0x000 },
12668 { 0x00000000, 0x003120c2, 0x000 },
12669 { 0x0000ffff, 0x00282228, 0x000 },
12670 { 0x00000000, 0x00894907, 0x000 },
12671 { 0x00000010, 0x00221e23, 0x000 },
12672 { 0x00000000, 0x00294887, 0x000 },
12673 { 0x00000001, 0x00220a21, 0x000 },
12674 { 0x00000000, 0x003308a2, 0x000 },
12675 { 0x00000010, 0x00221e22, 0x000 },
12676 { 0x00000010, 0x00212222, 0x000 },
12677 { 0x00000000, 0x00294907, 0x000 },
12678 { 0x00000000, 0x00311ca3, 0x000 },
12679 { 0x00000010, 0x00221e27, 0x000 },
12680 { 0x00000000, 0x00294887, 0x000 },
12681 { 0x00000001, 0x00220a21, 0x000 },
12682 { 0x00000000, 0x003008a2, 0x000 },
12683 { 0x00000010, 0x00221e22, 0x000 },
12684 { 0x00000010, 0x00212222, 0x000 },
12685 { 0x00000000, 0x00294907, 0x000 },
12686 { 0x00000010, 0x00221e23, 0x000 },
12687 { 0x00000000, 0x003120c4, 0x000 },
12688 { 0x0000ffff, 0x00282228, 0x000 },
12689 { 0x00000000, 0x00294907, 0x000 },
12690 { 0x00000000, 0x003808c5, 0x000 },
12691 { 0x00000000, 0x00300841, 0x000 },
12692 { 0x00000001, 0x00220a22, 0x000 },
12693 { 0x00000000, 0x003308a2, 0x000 },
12694 { 0x00000010, 0x00221e22, 0x000 },
12695 { 0x00000010, 0x00212222, 0x000 },
12696 { 0x00000000, 0x00894907, 0x000 },
12697 { 0x00000017, 0x0020222d, 0x000 },
12698 { 0x00000000, 0x14c00000, 0x318 },
12699 { 0xffffffef, 0x00280621, 0x000 },
12700 { 0x00000014, 0x0020222d, 0x000 },
12701 { 0x0000f8e0, 0x00204411, 0x000 },
12702 { 0x00000000, 0x00294901, 0x000 },
12703 { 0x00000000, 0x00894901, 0x000 },
12704 { 0x00000000, 0x00204811, 0x000 },
12705 { 0x00000000, 0x00204811, 0x000 },
12706 { 0x060a0200, 0x00804811, 0x000 },
12707 { 0x00000000, 0xc0200000, 0x000 },
12708 { 0x97000000, 0xc0204411, 0x000 },
12709 { 0x00000000, 0xc0204811, 0x000 },
12710 { 0x8a000000, 0x00204411, 0x000 },
12711 { 0x00000000, 0x00204811, 0x000 },
12712 { 0x0000225c, 0x00204411, 0x000 },
12713 { 0x00000000, 0xc0204800, 0x000 },
12714 { 0x0000a1fc, 0x00204411, 0x000 },
12715 { 0x00000000, 0xc0204800, 0x000 },
12716 { 0x00000000, 0xc0200400, 0x000 },
12717 { 0x00000000, 0x00a0000a, 0x000 },
12718 { 0x97000000, 0x00204411, 0x000 },
12719 { 0x00000000, 0x00204811, 0x000 },
12720 { 0x8a000000, 0x00204411, 0x000 },
12721 { 0x00000000, 0x00204811, 0x000 },
12722 { 0x0000225c, 0x00204411, 0x000 },
12723 { 0x00000000, 0xc0204800, 0x000 },
12724 { 0x0000a1fc, 0x00204411, 0x000 },
12725 { 0x00000000, 0xc0204800, 0x000 },
12726 { 0x00000000, 0xc0200400, 0x000 },
12727 { 0x00000000, 0x00a0000a, 0x000 },
12728 { 0x97000000, 0x00204411, 0x000 },
12729 { 0x00000000, 0x00204811, 0x000 },
12730 { 0x8a000000, 0x00204411, 0x000 },
12731 { 0x00000000, 0x00204811, 0x000 },
12732 { 0x0000225c, 0x00204411, 0x000 },
12733 { 0x00000000, 0xc0204800, 0x000 },
12734 { 0x0000a1fc, 0x00204411, 0x000 },
12735 { 0x00000000, 0xc0204800, 0x000 },
12736 { 0x0001a1fd, 0x00204411, 0x000 },
12737 { 0x00000000, 0xd9004800, 0x000 },
12738 { 0x00000000, 0xc0200400, 0x000 },
12739 { 0x00000000, 0x00a0000a, 0x000 },
12740 { 0x00002257, 0x00204411, 0x000 },
12741 { 0x00000003, 0xc0484a20, 0x000 },
12742 { 0x0000225d, 0x00204411, 0x000 },
12743 { 0x00000000, 0xc0404800, 0x000 },
12744 { 0x00000000, 0x00600000, 0x638 },
12745 { 0x00000000, 0xc0200800, 0x000 },
12746 { 0x0000225c, 0x00204411, 0x000 },
12747 { 0x00000003, 0x00384a22, 0x000 },
12748 { 0x0000a1fc, 0x00204411, 0x000 },
12749 { 0x00000000, 0xc0204800, 0x000 },
12750 { 0x0001a1fd, 0x00204411, 0x000 },
12751 { 0x00000000, 0x002f0222, 0x000 },
12752 { 0x00000000, 0x0ce00000, 0x000 },
12753 { 0x00000000, 0x40204800, 0x000 },
12754 { 0x00000001, 0x40304a20, 0x000 },
12755 { 0x00000002, 0xc0304a20, 0x000 },
12756 { 0x00000001, 0x00530a22, 0x34b },
12757 { 0x0000003f, 0xc0280a20, 0x000 },
12758 { 0x81000000, 0x00204411, 0x000 },
12759 { 0x00000001, 0x00204811, 0x000 },
12760 { 0x000021f8, 0x00204411, 0x000 },
12761 { 0x00000018, 0x00204811, 0x000 },
12762 { 0x000421f9, 0x00604411, 0x67c },
12763 { 0x00000011, 0x00210230, 0x000 },
12764 { 0x00000000, 0x14e00000, 0x354 },
12765 { 0x00000014, 0x002f0222, 0x000 },
12766 { 0x00000000, 0x0cc00000, 0x362 },
12767 { 0x0001a2a4, 0x00204411, 0x000 },
12768 { 0x00000000, 0x00604802, 0x36a },
12769 { 0x00002100, 0x00204411, 0x000 },
12770 { 0x00000000, 0xc0204800, 0x000 },
12771 { 0x00000000, 0xc0204800, 0x000 },
12772 { 0x00000000, 0xc0204800, 0x000 },
12773 { 0x00000000, 0xc0404800, 0x000 },
12774 { 0x00000004, 0x002f0222, 0x000 },
12775 { 0x00000000, 0x0cc00000, 0x366 },
12776 { 0x0001a2a4, 0x00204411, 0x000 },
12777 { 0x00000000, 0x00404802, 0x35d },
12778 { 0x00000028, 0x002f0222, 0x000 },
12779 { 0x00000000, 0x0cc00000, 0x5b3 },
12780 { 0x0001a2a4, 0x00204411, 0x000 },
12781 { 0x00000000, 0x00404802, 0x35d },
12782 { 0x0000002c, 0x00203626, 0x000 },
12783 { 0x00000049, 0x00201811, 0x000 },
12784 { 0x0000003f, 0x00204811, 0x000 },
12785 { 0x00000001, 0x00331a26, 0x000 },
12786 { 0x00000000, 0x002f0226, 0x000 },
12787 { 0x00000000, 0x0cc00000, 0x36c },
12788 { 0x0000002c, 0x00801a2d, 0x000 },
12789 { 0x0000003f, 0xc0280a20, 0x000 },
12790 { 0x00000015, 0x002f0222, 0x000 },
12791 { 0x00000000, 0x0ce00000, 0x382 },
12792 { 0x00000006, 0x002f0222, 0x000 },
12793 { 0x00000000, 0x0ce00000, 0x3ad },
12794 { 0x00000016, 0x002f0222, 0x000 },
12795 { 0x00000000, 0x0ce00000, 0x3af },
12796 { 0x00000020, 0x002f0222, 0x000 },
12797 { 0x00000000, 0x0ce00000, 0x398 },
12798 { 0x0000000f, 0x002f0222, 0x000 },
12799 { 0x00000000, 0x0ce00000, 0x3a4 },
12800 { 0x00000010, 0x002f0222, 0x000 },
12801 { 0x00000000, 0x0ce00000, 0x3a4 },
12802 { 0x0000001e, 0x002f0222, 0x000 },
12803 { 0x00000000, 0x0ce00000, 0x38c },
12804 { 0x0000a2a4, 0x00204411, 0x000 },
12805 { 0x00000000, 0x00404802, 0x000 },
12806 { 0x08000000, 0x00290a22, 0x000 },
12807 { 0x00000003, 0x40210e20, 0x000 },
12808 { 0x0000000c, 0xc0211220, 0x000 },
12809 { 0x00080000, 0x00281224, 0x000 },
12810 { 0x00000014, 0xc0221620, 0x000 },
12811 { 0x00000000, 0x002914a4, 0x000 },
12812 { 0x0000a2a4, 0x00204411, 0x000 },
12813 { 0x00000000, 0x002948a2, 0x000 },
12814 { 0x0000a1fe, 0x00204411, 0x000 },
12815 { 0x00000000, 0x00404803, 0x000 },
12816 { 0x81000000, 0x00204411, 0x000 },
12817 { 0x00000001, 0x00204811, 0x000 },
12818 { 0x000021f8, 0x00204411, 0x000 },
12819 { 0x00000016, 0x00204811, 0x000 },
12820 { 0x000421f9, 0x00604411, 0x67c },
12821 { 0x00000015, 0x00210230, 0x000 },
12822 { 0x00000000, 0x14e00000, 0x38e },
12823 { 0x0000210e, 0x00204411, 0x000 },
12824 { 0x00000000, 0xc0204800, 0x000 },
12825 { 0x00000000, 0xc0204800, 0x000 },
12826 { 0x0000a2a4, 0x00204411, 0x000 },
12827 { 0x00000000, 0x00404802, 0x000 },
12828 { 0x81000000, 0x00204411, 0x000 },
12829 { 0x00000001, 0x00204811, 0x000 },
12830 { 0x000021f8, 0x00204411, 0x000 },
12831 { 0x00000017, 0x00204811, 0x000 },
12832 { 0x000421f9, 0x00604411, 0x67c },
12833 { 0x00000003, 0x00210230, 0x000 },
12834 { 0x00000000, 0x14e00000, 0x39a },
12835 { 0x00002108, 0x00204411, 0x000 },
12836 { 0x00000000, 0xc0204800, 0x000 },
12837 { 0x00000000, 0xc0204800, 0x000 },
12838 { 0x0000a2a4, 0x00204411, 0x000 },
12839 { 0x00000000, 0x00404802, 0x000 },
12840 { 0x0000a2a4, 0x00204411, 0x000 },
12841 { 0x00000000, 0x00204802, 0x000 },
12842 { 0x80000000, 0x00204411, 0x000 },
12843 { 0x00000000, 0x00204811, 0x000 },
12844 { 0x81000000, 0x00204411, 0x000 },
12845 { 0x00000010, 0x00204811, 0x000 },
12846 { 0x00000000, 0x00200010, 0x000 },
12847 { 0x00000000, 0x14c00000, 0x3aa },
12848 { 0x00000000, 0x00400000, 0x000 },
12849 { 0x0001a2a4, 0x00204411, 0x000 },
12850 { 0x00000006, 0x00404811, 0x000 },
12851 { 0x0001a2a4, 0x00204411, 0x000 },
12852 { 0x00000016, 0x00604811, 0x36a },
12853 { 0x00000000, 0x00400000, 0x000 },
12854 { 0x00000000, 0xc0200800, 0x000 },
12855 { 0x00000000, 0xc0200c00, 0x000 },
12856 { 0x0000001d, 0x00210223, 0x000 },
12857 { 0x00000000, 0x14e00000, 0x3c4 },
12858 { 0x81000000, 0x00204411, 0x000 },
12859 { 0x00000001, 0x00204811, 0x000 },
12860 { 0x000021f8, 0x00204411, 0x000 },
12861 { 0x00000018, 0x00204811, 0x000 },
12862 { 0x000421f9, 0x00604411, 0x67c },
12863 { 0x00000011, 0x00210230, 0x000 },
12864 { 0x00000000, 0x14e00000, 0x3b8 },
12865 { 0x00002100, 0x00204411, 0x000 },
12866 { 0x00000000, 0x00204802, 0x000 },
12867 { 0x00000000, 0x00204803, 0x000 },
12868 { 0xbabecafe, 0x00204811, 0x000 },
12869 { 0xcafebabe, 0x00204811, 0x000 },
12870 { 0x0000a2a4, 0x00204411, 0x000 },
12871 { 0x00000004, 0x00404811, 0x000 },
12872 { 0x00002170, 0x00204411, 0x000 },
12873 { 0x00000000, 0x00204802, 0x000 },
12874 { 0x00000000, 0x00204803, 0x000 },
12875 { 0x81000000, 0x00204411, 0x000 },
12876 { 0x0000000a, 0x00204811, 0x000 },
12877 { 0x00000000, 0x00200010, 0x000 },
12878 { 0x00000000, 0x14c00000, 0x3c9 },
12879 { 0x8c000000, 0x00204411, 0x000 },
12880 { 0xcafebabe, 0x00404811, 0x000 },
12881 { 0x81000000, 0x00204411, 0x000 },
12882 { 0x00000001, 0x00204811, 0x000 },
12883 { 0x00003fff, 0x40280a20, 0x000 },
12884 { 0x80000000, 0x40280e20, 0x000 },
12885 { 0x40000000, 0xc0281220, 0x000 },
12886 { 0x00040000, 0x00694622, 0x67c },
12887 { 0x00000000, 0x00201410, 0x000 },
12888 { 0x00000000, 0x002f0223, 0x000 },
12889 { 0x00000000, 0x0cc00000, 0x3d7 },
12890 { 0x00000000, 0xc0401800, 0x3da },
12891 { 0x00003fff, 0xc0281a20, 0x000 },
12892 { 0x00040000, 0x00694626, 0x67c },
12893 { 0x00000000, 0x00201810, 0x000 },
12894 { 0x00000000, 0x002f0224, 0x000 },
12895 { 0x00000000, 0x0cc00000, 0x3dd },
12896 { 0x00000000, 0xc0401c00, 0x3e0 },
12897 { 0x00003fff, 0xc0281e20, 0x000 },
12898 { 0x00040000, 0x00694627, 0x67c },
12899 { 0x00000000, 0x00201c10, 0x000 },
12900 { 0x00000000, 0x00204402, 0x000 },
12901 { 0x00000000, 0x002820c5, 0x000 },
12902 { 0x00000000, 0x004948e8, 0x000 },
12903 { 0xa5800000, 0x00200811, 0x000 },
12904 { 0x00002000, 0x00200c11, 0x000 },
12905 { 0x83000000, 0x00604411, 0x408 },
12906 { 0x00000000, 0x00204402, 0x000 },
12907 { 0x00000000, 0xc0204800, 0x000 },
12908 { 0x00000000, 0x40204800, 0x000 },
12909 { 0x0000001f, 0xc0210220, 0x000 },
12910 { 0x00000000, 0x14c00000, 0x3ed },
12911 { 0x00002010, 0x00204411, 0x000 },
12912 { 0x00008000, 0x00204811, 0x000 },
12913 { 0x0000ffff, 0xc0481220, 0x3f5 },
12914 { 0xa7800000, 0x00200811, 0x000 },
12915 { 0x0000a000, 0x00200c11, 0x000 },
12916 { 0x83000000, 0x00604411, 0x408 },
12917 { 0x00000000, 0x00204402, 0x000 },
12918 { 0x00000000, 0xc0204800, 0x000 },
12919 { 0x00000000, 0xc0204800, 0x000 },
12920 { 0x0000ffff, 0xc0281220, 0x000 },
12921 { 0x83000000, 0x00204411, 0x000 },
12922 { 0x00000000, 0x00304883, 0x000 },
12923 { 0x84000000, 0x00204411, 0x000 },
12924 { 0x00000000, 0xc0204800, 0x000 },
12925 { 0x00000000, 0x1d000000, 0x000 },
12926 { 0x83000000, 0x00604411, 0x408 },
12927 { 0x00000000, 0xc0400400, 0x001 },
12928 { 0xa9800000, 0x00200811, 0x000 },
12929 { 0x0000c000, 0x00400c11, 0x3f0 },
12930 { 0xab800000, 0x00200811, 0x000 },
12931 { 0x0000f8e0, 0x00400c11, 0x3f0 },
12932 { 0xad800000, 0x00200811, 0x000 },
12933 { 0x0000f880, 0x00400c11, 0x3f0 },
12934 { 0xb3800000, 0x00200811, 0x000 },
12935 { 0x0000f3fc, 0x00400c11, 0x3f0 },
12936 { 0xaf800000, 0x00200811, 0x000 },
12937 { 0x0000e000, 0x00400c11, 0x3f0 },
12938 { 0xb1800000, 0x00200811, 0x000 },
12939 { 0x0000f000, 0x00400c11, 0x3f0 },
12940 { 0x83000000, 0x00204411, 0x000 },
12941 { 0x00002148, 0x00204811, 0x000 },
12942 { 0x84000000, 0x00204411, 0x000 },
12943 { 0x00000000, 0xc0204800, 0x000 },
12944 { 0x00000000, 0x1d000000, 0x000 },
12945 { 0x00000000, 0x00800000, 0x000 },
12946 { 0x01182000, 0xc0304620, 0x000 },
12947 { 0x00000000, 0xd9004800, 0x000 },
12948 { 0x00000000, 0xc0200400, 0x000 },
12949 { 0x00000000, 0x00a0000a, 0x000 },
12950 { 0x0218a000, 0xc0304620, 0x000 },
12951 { 0x00000000, 0xd9004800, 0x000 },
12952 { 0x00000000, 0xc0200400, 0x000 },
12953 { 0x00000000, 0x00a0000a, 0x000 },
12954 { 0x0318c000, 0xc0304620, 0x000 },
12955 { 0x00000000, 0xd9004800, 0x000 },
12956 { 0x00000000, 0xc0200400, 0x000 },
12957 { 0x00000000, 0x00a0000a, 0x000 },
12958 { 0x0418f8e0, 0xc0304620, 0x000 },
12959 { 0x00000000, 0xd9004800, 0x000 },
12960 { 0x00000000, 0xc0200400, 0x000 },
12961 { 0x00000000, 0x00a0000a, 0x000 },
12962 { 0x0518f880, 0xc0304620, 0x000 },
12963 { 0x00000000, 0xd9004800, 0x000 },
12964 { 0x00000000, 0xc0200400, 0x000 },
12965 { 0x00000000, 0x00a0000a, 0x000 },
12966 { 0x0618e000, 0xc0304620, 0x000 },
12967 { 0x00000000, 0xd9004800, 0x000 },
12968 { 0x00000000, 0xc0200400, 0x000 },
12969 { 0x00000000, 0x00a0000a, 0x000 },
12970 { 0x0718f000, 0xc0304620, 0x000 },
12971 { 0x00000000, 0xd9004800, 0x000 },
12972 { 0x00000000, 0xc0200400, 0x000 },
12973 { 0x00000000, 0x00a0000a, 0x000 },
12974 { 0x0818f3fc, 0xc0304620, 0x000 },
12975 { 0x00000000, 0xd9004800, 0x000 },
12976 { 0x00000000, 0xc0200400, 0x000 },
12977 { 0x00000000, 0x00a0000a, 0x000 },
12978 { 0x00000030, 0x00200a2d, 0x000 },
12979 { 0x00000000, 0xc0290c40, 0x000 },
12980 { 0x00000030, 0x00203623, 0x000 },
12981 { 0x00000000, 0xc0200400, 0x000 },
12982 { 0x00000000, 0x00a0000a, 0x000 },
12983 { 0x86000000, 0x00204411, 0x000 },
12984 { 0x00000000, 0x00404801, 0x000 },
12985 { 0x85000000, 0xc0204411, 0x000 },
12986 { 0x00000000, 0x00404801, 0x000 },
12987 { 0x0000217c, 0x00204411, 0x000 },
12988 { 0x00000000, 0xc0204800, 0x000 },
12989 { 0x00000000, 0xc0204800, 0x000 },
12990 { 0x00000000, 0xc0204800, 0x000 },
12991 { 0x81000000, 0x00204411, 0x000 },
12992 { 0x00000001, 0x00204811, 0x000 },
12993 { 0x00000000, 0xc0200800, 0x000 },
12994 { 0x00000000, 0x17000000, 0x000 },
12995 { 0x0004217f, 0x00604411, 0x67c },
12996 { 0x0000001f, 0x00210230, 0x000 },
12997 { 0x00000000, 0x14c00000, 0x000 },
12998 { 0x00000000, 0x00404c02, 0x43e },
12999 { 0x00000000, 0xc0200c00, 0x000 },
13000 { 0x00000000, 0xc0201000, 0x000 },
13001 { 0x00000000, 0xc0201400, 0x000 },
13002 { 0x00000000, 0xc0201800, 0x000 },
13003 { 0x00000000, 0xc0201c00, 0x000 },
13004 { 0x00007f00, 0x00280a21, 0x000 },
13005 { 0x00004500, 0x002f0222, 0x000 },
13006 { 0x00000000, 0x0ce00000, 0x44c },
13007 { 0x00000000, 0xc0202000, 0x000 },
13008 { 0x00000000, 0x17000000, 0x000 },
13009 { 0x00000010, 0x00280a23, 0x000 },
13010 { 0x00000010, 0x002f0222, 0x000 },
13011 { 0x00000000, 0x0ce00000, 0x454 },
13012 { 0x81000000, 0x00204411, 0x000 },
13013 { 0x00000001, 0x00204811, 0x000 },
13014 { 0x00040000, 0x00694624, 0x67c },
13015 { 0x00000000, 0x00400000, 0x459 },
13016 { 0x81000000, 0x00204411, 0x000 },
13017 { 0x00000000, 0x00204811, 0x000 },
13018 { 0x0000216d, 0x00204411, 0x000 },
13019 { 0x00000000, 0x00204804, 0x000 },
13020 { 0x00000000, 0x00604805, 0x681 },
13021 { 0x00000000, 0x002824f0, 0x000 },
13022 { 0x00000007, 0x00280a23, 0x000 },
13023 { 0x00000001, 0x002f0222, 0x000 },
13024 { 0x00000000, 0x0ae00000, 0x460 },
13025 { 0x00000000, 0x002f00c9, 0x000 },
13026 { 0x00000000, 0x04e00000, 0x479 },
13027 { 0x00000000, 0x00400000, 0x486 },
13028 { 0x00000002, 0x002f0222, 0x000 },
13029 { 0x00000000, 0x0ae00000, 0x465 },
13030 { 0x00000000, 0x002f00c9, 0x000 },
13031 { 0x00000000, 0x02e00000, 0x479 },
13032 { 0x00000000, 0x00400000, 0x486 },
13033 { 0x00000003, 0x002f0222, 0x000 },
13034 { 0x00000000, 0x0ae00000, 0x46a },
13035 { 0x00000000, 0x002f00c9, 0x000 },
13036 { 0x00000000, 0x0ce00000, 0x479 },
13037 { 0x00000000, 0x00400000, 0x486 },
13038 { 0x00000004, 0x002f0222, 0x000 },
13039 { 0x00000000, 0x0ae00000, 0x46f },
13040 { 0x00000000, 0x002f00c9, 0x000 },
13041 { 0x00000000, 0x0ae00000, 0x479 },
13042 { 0x00000000, 0x00400000, 0x486 },
13043 { 0x00000005, 0x002f0222, 0x000 },
13044 { 0x00000000, 0x0ae00000, 0x474 },
13045 { 0x00000000, 0x002f00c9, 0x000 },
13046 { 0x00000000, 0x06e00000, 0x479 },
13047 { 0x00000000, 0x00400000, 0x486 },
13048 { 0x00000006, 0x002f0222, 0x000 },
13049 { 0x00000000, 0x0ae00000, 0x479 },
13050 { 0x00000000, 0x002f00c9, 0x000 },
13051 { 0x00000000, 0x08e00000, 0x479 },
13052 { 0x00000000, 0x00400000, 0x486 },
13053 { 0x00007f00, 0x00280a21, 0x000 },
13054 { 0x00004500, 0x002f0222, 0x000 },
13055 { 0x00000000, 0x0ae00000, 0x000 },
13056 { 0x00000008, 0x00210a23, 0x000 },
13057 { 0x00000000, 0x14c00000, 0x483 },
13058 { 0x00002169, 0x00204411, 0x000 },
13059 { 0x00000000, 0xc0204800, 0x000 },
13060 { 0x00000000, 0xc0204800, 0x000 },
13061 { 0x00000000, 0xc0204800, 0x000 },
13062 { 0xcafebabe, 0x00404811, 0x000 },
13063 { 0x00000000, 0xc0204400, 0x000 },
13064 { 0x00000000, 0xc0200000, 0x000 },
13065 { 0x00000000, 0xc0404800, 0x000 },
13066 { 0x00007f00, 0x00280a21, 0x000 },
13067 { 0x00004500, 0x002f0222, 0x000 },
13068 { 0x00000000, 0x0ae00000, 0x48c },
13069 { 0x00000000, 0xc0200000, 0x000 },
13070 { 0x00000000, 0xc0200000, 0x000 },
13071 { 0x00000000, 0xc0400000, 0x000 },
13072 { 0x00000000, 0x00404c08, 0x44c },
13073 { 0x00000000, 0xc0200800, 0x000 },
13074 { 0x00000010, 0x40210e20, 0x000 },
13075 { 0x00000011, 0x40211220, 0x000 },
13076 { 0x00000012, 0x40211620, 0x000 },
13077 { 0x00002169, 0x00204411, 0x000 },
13078 { 0x00000000, 0x00204802, 0x000 },
13079 { 0x00000000, 0x00210225, 0x000 },
13080 { 0x00000000, 0x14e00000, 0x496 },
13081 { 0x00040000, 0xc0494a20, 0x497 },
13082 { 0xfffbffff, 0xc0284a20, 0x000 },
13083 { 0x00000000, 0x00210223, 0x000 },
13084 { 0x00000000, 0x14e00000, 0x4a3 },
13085 { 0x00000000, 0xc0204800, 0x000 },
13086 { 0x00000000, 0xc0204800, 0x000 },
13087 { 0x00000000, 0x00210224, 0x000 },
13088 { 0x00000000, 0x14c00000, 0x000 },
13089 { 0x81000000, 0x00204411, 0x000 },
13090 { 0x0000000c, 0x00204811, 0x000 },
13091 { 0x00000000, 0x00200010, 0x000 },
13092 { 0x00000000, 0x14c00000, 0x49f },
13093 { 0xa0000000, 0x00204411, 0x000 },
13094 { 0xcafebabe, 0x00404811, 0x000 },
13095 { 0x81000000, 0x00204411, 0x000 },
13096 { 0x00000004, 0x00204811, 0x000 },
13097 { 0x0000216b, 0x00204411, 0x000 },
13098 { 0x00000000, 0xc0204810, 0x000 },
13099 { 0x81000000, 0x00204411, 0x000 },
13100 { 0x00000005, 0x00204811, 0x000 },
13101 { 0x0000216c, 0x00204411, 0x000 },
13102 { 0x00000000, 0xc0204810, 0x000 },
13103 { 0x00000000, 0x002f0224, 0x000 },
13104 { 0x00000000, 0x0ce00000, 0x000 },
13105 { 0x00000000, 0x00400000, 0x49d },
13106 { 0x00000000, 0xc0210a20, 0x000 },
13107 { 0x00000000, 0x14c00000, 0x4b6 },
13108 { 0x81000000, 0x00204411, 0x000 },
13109 { 0x00000000, 0x00204811, 0x000 },
13110 { 0x0000216d, 0x00204411, 0x000 },
13111 { 0x00000000, 0xc0204800, 0x000 },
13112 { 0x00000000, 0xc0604800, 0x681 },
13113 { 0x00000000, 0x00400000, 0x4ba },
13114 { 0x81000000, 0x00204411, 0x000 },
13115 { 0x00000001, 0x00204811, 0x000 },
13116 { 0x00040000, 0xc0294620, 0x000 },
13117 { 0x00000000, 0xc0600000, 0x67c },
13118 { 0x00000001, 0x00210222, 0x000 },
13119 { 0x00000000, 0x14c00000, 0x4c1 },
13120 { 0x00002169, 0x00204411, 0x000 },
13121 { 0x00000000, 0xc0204800, 0x000 },
13122 { 0x00000000, 0xc0204800, 0x000 },
13123 { 0x00000000, 0x00204810, 0x000 },
13124 { 0xcafebabe, 0x00404811, 0x000 },
13125 { 0x00000000, 0xc0204400, 0x000 },
13126 { 0x00000000, 0xc0404810, 0x000 },
13127 { 0x81000000, 0x00204411, 0x000 },
13128 { 0x00000001, 0x00204811, 0x000 },
13129 { 0x000021f8, 0x00204411, 0x000 },
13130 { 0x0000000e, 0x00204811, 0x000 },
13131 { 0x000421f9, 0x00604411, 0x67c },
13132 { 0x00000000, 0x00210230, 0x000 },
13133 { 0x00000000, 0x14c00000, 0x4c3 },
13134 { 0x00002180, 0x00204411, 0x000 },
13135 { 0x00000000, 0xc0204800, 0x000 },
13136 { 0x00000000, 0xc0200000, 0x000 },
13137 { 0x00000000, 0xc0204800, 0x000 },
13138 { 0x00000000, 0xc0200000, 0x000 },
13139 { 0x00000000, 0xc0404800, 0x000 },
13140 { 0x00000003, 0x00333e2f, 0x000 },
13141 { 0x00000001, 0x00210221, 0x000 },
13142 { 0x00000000, 0x14e00000, 0x4f3 },
13143 { 0x0000002c, 0x00200a2d, 0x000 },
13144 { 0x00040000, 0x18e00c11, 0x4e2 },
13145 { 0x00000001, 0x00333e2f, 0x000 },
13146 { 0x00002169, 0x00204411, 0x000 },
13147 { 0x00000000, 0x00204802, 0x000 },
13148 { 0x00000000, 0x00204803, 0x000 },
13149 { 0x00000008, 0x00300a22, 0x000 },
13150 { 0x00000000, 0xc0204800, 0x000 },
13151 { 0x00000000, 0xc0204800, 0x000 },
13152 { 0x00002169, 0x00204411, 0x000 },
13153 { 0x00000000, 0x00204802, 0x000 },
13154 { 0x00000000, 0x00204803, 0x000 },
13155 { 0x00000008, 0x00300a22, 0x000 },
13156 { 0x00000000, 0xc0204800, 0x000 },
13157 { 0x00000000, 0xd8c04800, 0x4d6 },
13158 { 0x00002169, 0x00204411, 0x000 },
13159 { 0x00000000, 0x00204802, 0x000 },
13160 { 0x00000000, 0x00204803, 0x000 },
13161 { 0x00000008, 0x00300a22, 0x000 },
13162 { 0x00000000, 0xc0204800, 0x000 },
13163 { 0x00000000, 0xc0204800, 0x000 },
13164 { 0x0000002d, 0x0020122d, 0x000 },
13165 { 0x00000000, 0x00290c83, 0x000 },
13166 { 0x00002169, 0x00204411, 0x000 },
13167 { 0x00000000, 0x00204802, 0x000 },
13168 { 0x00000000, 0x00204803, 0x000 },
13169 { 0x00000008, 0x00300a22, 0x000 },
13170 { 0x00000000, 0xc0204800, 0x000 },
13171 { 0x00000000, 0xc0204800, 0x000 },
13172 { 0x00000011, 0x00210224, 0x000 },
13173 { 0x00000000, 0x14c00000, 0x000 },
13174 { 0x00000000, 0x00400000, 0x49d },
13175 { 0x0000002c, 0xc0203620, 0x000 },
13176 { 0x0000002d, 0xc0403620, 0x000 },
13177 { 0x0000000f, 0x00210221, 0x000 },
13178 { 0x00000000, 0x14c00000, 0x4f8 },
13179 { 0x00000000, 0x00600000, 0x00b },
13180 { 0x00000000, 0xd9000000, 0x000 },
13181 { 0x00000000, 0xc0400400, 0x001 },
13182 { 0xb5000000, 0x00204411, 0x000 },
13183 { 0x00002000, 0x00204811, 0x000 },
13184 { 0xb6000000, 0x00204411, 0x000 },
13185 { 0x0000a000, 0x00204811, 0x000 },
13186 { 0xb7000000, 0x00204411, 0x000 },
13187 { 0x0000c000, 0x00204811, 0x000 },
13188 { 0xb8000000, 0x00204411, 0x000 },
13189 { 0x0000f8e0, 0x00204811, 0x000 },
13190 { 0xb9000000, 0x00204411, 0x000 },
13191 { 0x0000f880, 0x00204811, 0x000 },
13192 { 0xba000000, 0x00204411, 0x000 },
13193 { 0x0000e000, 0x00204811, 0x000 },
13194 { 0xbb000000, 0x00204411, 0x000 },
13195 { 0x0000f000, 0x00204811, 0x000 },
13196 { 0xbc000000, 0x00204411, 0x000 },
13197 { 0x0000f3fc, 0x00204811, 0x000 },
13198 { 0x81000000, 0x00204411, 0x000 },
13199 { 0x00000002, 0x00204811, 0x000 },
13200 { 0x000000ff, 0x00280e30, 0x000 },
13201 { 0x00000000, 0x002f0223, 0x000 },
13202 { 0x00000000, 0x0cc00000, 0x50c },
13203 { 0x00000000, 0xc0200800, 0x000 },
13204 { 0x00000000, 0x14c00000, 0x521 },
13205 { 0x00000000, 0x00200c11, 0x000 },
13206 { 0x0000001c, 0x00203623, 0x000 },
13207 { 0x0000002b, 0x00203623, 0x000 },
13208 { 0x00000029, 0x00203623, 0x000 },
13209 { 0x00000028, 0x00203623, 0x000 },
13210 { 0x00000017, 0x00203623, 0x000 },
13211 { 0x00000025, 0x00203623, 0x000 },
13212 { 0x00000026, 0x00203623, 0x000 },
13213 { 0x00000015, 0x00203623, 0x000 },
13214 { 0x00000016, 0x00203623, 0x000 },
13215 { 0xffffe000, 0x00200c11, 0x000 },
13216 { 0x00000021, 0x00203623, 0x000 },
13217 { 0x00000022, 0x00203623, 0x000 },
13218 { 0x00001fff, 0x00200c11, 0x000 },
13219 { 0x00000023, 0x00203623, 0x000 },
13220 { 0x00000024, 0x00203623, 0x000 },
13221 { 0xf1ffffff, 0x00283a2e, 0x000 },
13222 { 0x0000001a, 0xc0220e20, 0x000 },
13223 { 0x00000000, 0x0029386e, 0x000 },
13224 { 0x81000000, 0x00204411, 0x000 },
13225 { 0x00000006, 0x00204811, 0x000 },
13226 { 0x0000002a, 0x40203620, 0x000 },
13227 { 0x87000000, 0x00204411, 0x000 },
13228 { 0x00000000, 0xc0204800, 0x000 },
13229 { 0x0000a1f4, 0x00204411, 0x000 },
13230 { 0x00000000, 0x00204810, 0x000 },
13231 { 0x00000000, 0x00200c11, 0x000 },
13232 { 0x00000030, 0x00203623, 0x000 },
13233 { 0x9d000000, 0x00204411, 0x000 },
13234 { 0x0000001f, 0x40214a20, 0x000 },
13235 { 0x96000000, 0x00204411, 0x000 },
13236 { 0x00000000, 0xc0204800, 0x000 },
13237 { 0x00000000, 0xc0200c00, 0x000 },
13238 { 0x00000000, 0xc0201000, 0x000 },
13239 { 0x0000001f, 0x00211624, 0x000 },
13240 { 0x00000000, 0x14c00000, 0x000 },
13241 { 0x0000001d, 0x00203623, 0x000 },
13242 { 0x00000003, 0x00281e23, 0x000 },
13243 { 0x00000008, 0x00222223, 0x000 },
13244 { 0xfffff000, 0x00282228, 0x000 },
13245 { 0x00000000, 0x002920e8, 0x000 },
13246 { 0x0000001f, 0x00203628, 0x000 },
13247 { 0x00000018, 0x00211e23, 0x000 },
13248 { 0x00000020, 0x00203627, 0x000 },
13249 { 0x00000002, 0x00221624, 0x000 },
13250 { 0x00000000, 0x003014a8, 0x000 },
13251 { 0x0000001e, 0x00203625, 0x000 },
13252 { 0x00000003, 0x00211a24, 0x000 },
13253 { 0x10000000, 0x00281a26, 0x000 },
13254 { 0xefffffff, 0x00283a2e, 0x000 },
13255 { 0x00000000, 0x004938ce, 0x66a },
13256 { 0x00000001, 0x40280a20, 0x000 },
13257 { 0x00000006, 0x40280e20, 0x000 },
13258 { 0x00000300, 0xc0281220, 0x000 },
13259 { 0x00000008, 0x00211224, 0x000 },
13260 { 0x00000000, 0xc0201620, 0x000 },
13261 { 0x00000000, 0xc0201a20, 0x000 },
13262 { 0x00000000, 0x00210222, 0x000 },
13263 { 0x00000000, 0x14c00000, 0x559 },
13264 { 0x81000000, 0x00204411, 0x000 },
13265 { 0x00000001, 0x00204811, 0x000 },
13266 { 0x00002258, 0x00300a24, 0x000 },
13267 { 0x00040000, 0x00694622, 0x67c },
13268 { 0x00002169, 0x00204411, 0x000 },
13269 { 0x00000000, 0x00204805, 0x000 },
13270 { 0x00020000, 0x00294a26, 0x000 },
13271 { 0x00000000, 0x00204810, 0x000 },
13272 { 0xcafebabe, 0x00204811, 0x000 },
13273 { 0x00000002, 0x002f0223, 0x000 },
13274 { 0x00000000, 0x0cc00000, 0x561 },
13275 { 0x00000000, 0xc0201c10, 0x000 },
13276 { 0x00000000, 0xc0400000, 0x56f },
13277 { 0x00000002, 0x002f0223, 0x000 },
13278 { 0x00000000, 0x0cc00000, 0x561 },
13279 { 0x81000000, 0x00204411, 0x000 },
13280 { 0x00000001, 0x00204811, 0x000 },
13281 { 0x00002258, 0x00300a24, 0x000 },
13282 { 0x00040000, 0x00694622, 0x67c },
13283 { 0x00000000, 0xc0201c10, 0x000 },
13284 { 0x00000000, 0xc0400000, 0x56f },
13285 { 0x00000000, 0x002f0223, 0x000 },
13286 { 0x00000000, 0x0cc00000, 0x565 },
13287 { 0x00000000, 0xc0201c00, 0x000 },
13288 { 0x00000000, 0xc0400000, 0x56f },
13289 { 0x00000004, 0x002f0223, 0x000 },
13290 { 0x00000000, 0x0cc00000, 0x56d },
13291 { 0x81000000, 0x00204411, 0x000 },
13292 { 0x00000000, 0x00204811, 0x000 },
13293 { 0x0000216d, 0x00204411, 0x000 },
13294 { 0x00000000, 0xc0204800, 0x000 },
13295 { 0x00000000, 0xc0604800, 0x681 },
13296 { 0x00000000, 0x00401c10, 0x56f },
13297 { 0x00000000, 0xc0200000, 0x000 },
13298 { 0x00000000, 0xc0400000, 0x000 },
13299 { 0x00000000, 0x0ee00000, 0x571 },
13300 { 0x00000000, 0x00600000, 0x5bc },
13301 { 0x00000000, 0x002f0224, 0x000 },
13302 { 0x00000000, 0x0cc00000, 0x582 },
13303 { 0x0000a2b7, 0x00204411, 0x000 },
13304 { 0x00000000, 0x00204807, 0x000 },
13305 { 0x81000000, 0x00204411, 0x000 },
13306 { 0x00000001, 0x00204811, 0x000 },
13307 { 0x0004a2b6, 0x00604411, 0x67c },
13308 { 0x0000001a, 0x00212230, 0x000 },
13309 { 0x00000006, 0x00222630, 0x000 },
13310 { 0x00042004, 0x00604411, 0x67c },
13311 { 0x0000a2c4, 0x00204411, 0x000 },
13312 { 0x00000000, 0x003048e9, 0x000 },
13313 { 0x00000000, 0x00e00000, 0x580 },
13314 { 0x0000a2d1, 0x00204411, 0x000 },
13315 { 0x00000000, 0x00404808, 0x000 },
13316 { 0x0000a2d1, 0x00204411, 0x000 },
13317 { 0x00000001, 0x00504a28, 0x000 },
13318 { 0x00000001, 0x002f0224, 0x000 },
13319 { 0x00000000, 0x0cc00000, 0x593 },
13320 { 0x0000a2bb, 0x00204411, 0x000 },
13321 { 0x00000000, 0x00204807, 0x000 },
13322 { 0x81000000, 0x00204411, 0x000 },
13323 { 0x00000001, 0x00204811, 0x000 },
13324 { 0x0004a2ba, 0x00604411, 0x67c },
13325 { 0x0000001a, 0x00212230, 0x000 },
13326 { 0x00000006, 0x00222630, 0x000 },
13327 { 0x00042004, 0x00604411, 0x67c },
13328 { 0x0000a2c5, 0x00204411, 0x000 },
13329 { 0x00000000, 0x003048e9, 0x000 },
13330 { 0x00000000, 0x00e00000, 0x591 },
13331 { 0x0000a2d2, 0x00204411, 0x000 },
13332 { 0x00000000, 0x00404808, 0x000 },
13333 { 0x0000a2d2, 0x00204411, 0x000 },
13334 { 0x00000001, 0x00504a28, 0x000 },
13335 { 0x00000002, 0x002f0224, 0x000 },
13336 { 0x00000000, 0x0cc00000, 0x5a4 },
13337 { 0x0000a2bf, 0x00204411, 0x000 },
13338 { 0x00000000, 0x00204807, 0x000 },
13339 { 0x81000000, 0x00204411, 0x000 },
13340 { 0x00000001, 0x00204811, 0x000 },
13341 { 0x0004a2be, 0x00604411, 0x67c },
13342 { 0x0000001a, 0x00212230, 0x000 },
13343 { 0x00000006, 0x00222630, 0x000 },
13344 { 0x00042004, 0x00604411, 0x67c },
13345 { 0x0000a2c6, 0x00204411, 0x000 },
13346 { 0x00000000, 0x003048e9, 0x000 },
13347 { 0x00000000, 0x00e00000, 0x5a2 },
13348 { 0x0000a2d3, 0x00204411, 0x000 },
13349 { 0x00000000, 0x00404808, 0x000 },
13350 { 0x0000a2d3, 0x00204411, 0x000 },
13351 { 0x00000001, 0x00504a28, 0x000 },
13352 { 0x0000a2c3, 0x00204411, 0x000 },
13353 { 0x00000000, 0x00204807, 0x000 },
13354 { 0x81000000, 0x00204411, 0x000 },
13355 { 0x00000001, 0x00204811, 0x000 },
13356 { 0x0004a2c2, 0x00604411, 0x67c },
13357 { 0x0000001a, 0x00212230, 0x000 },
13358 { 0x00000006, 0x00222630, 0x000 },
13359 { 0x00042004, 0x00604411, 0x67c },
13360 { 0x0000a2c7, 0x00204411, 0x000 },
13361 { 0x00000000, 0x003048e9, 0x000 },
13362 { 0x00000000, 0x00e00000, 0x5b1 },
13363 { 0x0000a2d4, 0x00204411, 0x000 },
13364 { 0x00000000, 0x00404808, 0x000 },
13365 { 0x0000a2d4, 0x00204411, 0x000 },
13366 { 0x00000001, 0x00504a28, 0x000 },
13367 { 0x85000000, 0x00204411, 0x000 },
13368 { 0x00000000, 0x00204801, 0x000 },
13369 { 0x0000304a, 0x00204411, 0x000 },
13370 { 0x01000000, 0x00204811, 0x000 },
13371 { 0x00000000, 0x00400000, 0x5b7 },
13372 { 0xa4000000, 0xc0204411, 0x000 },
13373 { 0x00000000, 0xc0404800, 0x000 },
13374 { 0x00000000, 0xc0600000, 0x5bc },
13375 { 0x00000000, 0xc0400400, 0x001 },
13376 { 0x0000002c, 0x00203621, 0x000 },
13377 { 0x81000000, 0x00204411, 0x000 },
13378 { 0x00000006, 0x00204811, 0x000 },
13379 { 0x00000000, 0x002f0230, 0x000 },
13380 { 0x00000000, 0x0cc00000, 0x5c3 },
13381 { 0x00000000, 0x00200411, 0x000 },
13382 { 0x00000030, 0x00403621, 0x5d6 },
13383 { 0x00000030, 0x0020062d, 0x000 },
13384 { 0x00007e00, 0x00280621, 0x000 },
13385 { 0x00000000, 0x002f0221, 0x000 },
13386 { 0x00000000, 0x0ce00000, 0x5d6 },
13387 { 0x81000000, 0x00204411, 0x000 },
13388 { 0x00000001, 0x00204811, 0x000 },
13389 { 0x0004a092, 0x00604411, 0x67c },
13390 { 0x00000031, 0x00203630, 0x000 },
13391 { 0x0004a093, 0x00604411, 0x67c },
13392 { 0x00000032, 0x00203630, 0x000 },
13393 { 0x0004a2b6, 0x00604411, 0x67c },
13394 { 0x00000033, 0x00203630, 0x000 },
13395 { 0x0004a2ba, 0x00604411, 0x67c },
13396 { 0x00000034, 0x00203630, 0x000 },
13397 { 0x0004a2be, 0x00604411, 0x67c },
13398 { 0x00000035, 0x00203630, 0x000 },
13399 { 0x0004a2c2, 0x00604411, 0x67c },
13400 { 0x00000036, 0x00203630, 0x000 },
13401 { 0x00042004, 0x00604411, 0x67c },
13402 { 0x0001a2a4, 0x00204411, 0x000 },
13403 { 0x0000003f, 0x00204811, 0x000 },
13404 { 0x0000003f, 0x00204811, 0x000 },
13405 { 0x0000003f, 0x00204811, 0x000 },
13406 { 0x0000003f, 0x00204811, 0x000 },
13407 { 0x00000005, 0x00204811, 0x000 },
13408 { 0x0000a1f4, 0x00204411, 0x000 },
13409 { 0x00000000, 0x00204811, 0x000 },
13410 { 0x88000000, 0x00204411, 0x000 },
13411 { 0x00000001, 0x00204811, 0x000 },
13412 { 0x81000000, 0x00204411, 0x000 },
13413 { 0x00000006, 0x00204811, 0x000 },
13414 { 0x00000001, 0x002f0230, 0x000 },
13415 { 0x00000000, 0x0ce00000, 0x61f },
13416 { 0x00000030, 0x0020062d, 0x000 },
13417 { 0x00000000, 0x002f0221, 0x000 },
13418 { 0x00000000, 0x0ce00000, 0x61f },
13419 { 0x81000000, 0x00204411, 0x000 },
13420 { 0x00000001, 0x00204811, 0x000 },
13421 { 0x00007e00, 0x00280621, 0x000 },
13422 { 0x00000000, 0x002f0221, 0x000 },
13423 { 0x00000000, 0x0ce00000, 0x5f8 },
13424 { 0x0000a092, 0x00204411, 0x000 },
13425 { 0x00000031, 0x00204a2d, 0x000 },
13426 { 0x0000a093, 0x00204411, 0x000 },
13427 { 0x00000032, 0x00204a2d, 0x000 },
13428 { 0x0000a2b6, 0x00204411, 0x000 },
13429 { 0x00000033, 0x00204a2d, 0x000 },
13430 { 0x0000a2ba, 0x00204411, 0x000 },
13431 { 0x00000034, 0x00204a2d, 0x000 },
13432 { 0x0000a2be, 0x00204411, 0x000 },
13433 { 0x00000035, 0x00204a2d, 0x000 },
13434 { 0x0000a2c2, 0x00204411, 0x000 },
13435 { 0x00000036, 0x00204a2d, 0x000 },
13436 { 0x00000030, 0x0020062d, 0x000 },
13437 { 0x000001ff, 0x00280621, 0x000 },
13438 { 0x00000000, 0x002f0221, 0x000 },
13439 { 0x00000000, 0x0ce00000, 0x61e },
13440 { 0x00000000, 0x00210221, 0x000 },
13441 { 0x00000000, 0x14c00000, 0x601 },
13442 { 0x0004a003, 0x00604411, 0x67c },
13443 { 0x0000a003, 0x00204411, 0x000 },
13444 { 0x00000000, 0x00204810, 0x000 },
13445 { 0x00000001, 0x00210621, 0x000 },
13446 { 0x00000000, 0x14c00000, 0x606 },
13447 { 0x0004a010, 0x00604411, 0x67c },
13448 { 0x0000a010, 0x00204411, 0x000 },
13449 { 0x00000000, 0x00204810, 0x000 },
13450 { 0x00000001, 0x00210621, 0x000 },
13451 { 0x00000000, 0x002f0221, 0x000 },
13452 { 0x00000000, 0x0ce00000, 0x61e },
13453 { 0x0004a011, 0x00604411, 0x67c },
13454 { 0x0000a011, 0x00204411, 0x000 },
13455 { 0x00000000, 0x00204810, 0x000 },
13456 { 0x0004a012, 0x00604411, 0x67c },
13457 { 0x0000a012, 0x00204411, 0x000 },
13458 { 0x00000000, 0x00204810, 0x000 },
13459 { 0x0004a013, 0x00604411, 0x67c },
13460 { 0x0000a013, 0x00204411, 0x000 },
13461 { 0x00000000, 0x00204810, 0x000 },
13462 { 0x0004a014, 0x00604411, 0x67c },
13463 { 0x0000a014, 0x00204411, 0x000 },
13464 { 0x00000000, 0x00204810, 0x000 },
13465 { 0x0004a015, 0x00604411, 0x67c },
13466 { 0x0000a015, 0x00204411, 0x000 },
13467 { 0x00000000, 0x00204810, 0x000 },
13468 { 0x0004a016, 0x00604411, 0x67c },
13469 { 0x0000a016, 0x00204411, 0x000 },
13470 { 0x00000000, 0x00204810, 0x000 },
13471 { 0x0004a017, 0x00604411, 0x67c },
13472 { 0x0000a017, 0x00204411, 0x000 },
13473 { 0x00000000, 0x00204810, 0x000 },
13474 { 0x00042004, 0x00604411, 0x67c },
13475 { 0x0000002c, 0x0080062d, 0x000 },
13476 { 0xff000000, 0x00204411, 0x000 },
13477 { 0x00000000, 0x00204811, 0x000 },
13478 { 0x00000001, 0x00204811, 0x000 },
13479 { 0x00000002, 0x00804811, 0x000 },
13480 { 0x00000000, 0x0ee00000, 0x630 },
13481 { 0x00000030, 0x0020062d, 0x000 },
13482 { 0x00000002, 0x00280621, 0x000 },
13483 { 0x00000000, 0x002f0221, 0x000 },
13484 { 0x00000000, 0x0ce00000, 0x62e },
13485 { 0x81000000, 0x00204411, 0x000 },
13486 { 0x00000001, 0x00204811, 0x000 },
13487 { 0x00042004, 0x00604411, 0x67c },
13488 { 0x00001000, 0x00200811, 0x000 },
13489 { 0x0000002b, 0x00203622, 0x000 },
13490 { 0x00000000, 0x00600000, 0x634 },
13491 { 0x00000000, 0x00600000, 0x5bc },
13492 { 0x98000000, 0x00204411, 0x000 },
13493 { 0x00000000, 0x00804811, 0x000 },
13494 { 0x00000000, 0xc0600000, 0x634 },
13495 { 0x00000000, 0xc0400400, 0x001 },
13496 { 0x0000a2a4, 0x00204411, 0x000 },
13497 { 0x00000022, 0x00204811, 0x000 },
13498 { 0x89000000, 0x00204411, 0x000 },
13499 { 0x00000001, 0x00404811, 0x620 },
13500 { 0x97000000, 0x00204411, 0x000 },
13501 { 0x00000000, 0x00204811, 0x000 },
13502 { 0x8a000000, 0x00204411, 0x000 },
13503 { 0x00000000, 0x00404811, 0x620 },
13504 { 0x00000000, 0x00600000, 0x64d },
13505 { 0x0001a2a4, 0xc0204411, 0x000 },
13506 { 0x00000016, 0x00604811, 0x36a },
13507 { 0x00002010, 0x00204411, 0x000 },
13508 { 0x00010000, 0x00204811, 0x000 },
13509 { 0x81000000, 0x00204411, 0x000 },
13510 { 0x00000001, 0x00204811, 0x000 },
13511 { 0x0000217c, 0x00204411, 0x000 },
13512 { 0x09800000, 0x00204811, 0x000 },
13513 { 0xffffffff, 0x00204811, 0x000 },
13514 { 0x00000000, 0x00204811, 0x000 },
13515 { 0x00000000, 0x17000000, 0x000 },
13516 { 0x0004217f, 0x00604411, 0x67c },
13517 { 0x0000001f, 0x00210230, 0x000 },
13518 { 0x00000000, 0x14c00000, 0x000 },
13519 { 0x00000004, 0x00404c11, 0x647 },
13520 { 0x00000000, 0x00400000, 0x000 },
13521 { 0x00000017, 0x00201e2d, 0x000 },
13522 { 0x00000004, 0x00291e27, 0x000 },
13523 { 0x00000017, 0x00803627, 0x000 },
13524 { 0x00000017, 0x00201e2d, 0x000 },
13525 { 0xfffffffb, 0x00281e27, 0x000 },
13526 { 0x00000017, 0x00803627, 0x000 },
13527 { 0x00000017, 0x00201e2d, 0x000 },
13528 { 0x00000008, 0x00291e27, 0x000 },
13529 { 0x00000017, 0x00803627, 0x000 },
13530 { 0x00000017, 0x00201e2d, 0x000 },
13531 { 0xfffffff7, 0x00281e27, 0x000 },
13532 { 0x00000017, 0x00803627, 0x000 },
13533 { 0x0001a2a4, 0x00204411, 0x000 },
13534 { 0x00000016, 0x00604811, 0x36a },
13535 { 0x00002010, 0x00204411, 0x000 },
13536 { 0x00010000, 0x00204811, 0x000 },
13537 { 0x0000217c, 0x00204411, 0x000 },
13538 { 0x01800000, 0x00204811, 0x000 },
13539 { 0xffffffff, 0x00204811, 0x000 },
13540 { 0x00000000, 0x00204811, 0x000 },
13541 { 0x00000000, 0x17000000, 0x000 },
13542 { 0x81000000, 0x00204411, 0x000 },
13543 { 0x00000001, 0x00204811, 0x000 },
13544 { 0x0004217f, 0x00604411, 0x67c },
13545 { 0x0000001f, 0x00210230, 0x000 },
13546 { 0x00000000, 0x14c00000, 0x67b },
13547 { 0x00000010, 0x00404c11, 0x661 },
13548 { 0x00000000, 0xc0200400, 0x000 },
13549 { 0x00000000, 0x38c00000, 0x000 },
13550 { 0x0000001d, 0x00200a2d, 0x000 },
13551 { 0x0000001e, 0x00200e2d, 0x000 },
13552 { 0x0000001f, 0x0020122d, 0x000 },
13553 { 0x00000020, 0x0020162d, 0x000 },
13554 { 0x00002169, 0x00204411, 0x000 },
13555 { 0x00000000, 0x00204804, 0x000 },
13556 { 0x00000000, 0x00204805, 0x000 },
13557 { 0x00000000, 0x00204801, 0x000 },
13558 { 0xcafebabe, 0x00204811, 0x000 },
13559 { 0x00000004, 0x00301224, 0x000 },
13560 { 0x00000000, 0x002f0064, 0x000 },
13561 { 0x00000000, 0x0cc00000, 0x67a },
13562 { 0x00000003, 0x00281a22, 0x000 },
13563 { 0x00000008, 0x00221222, 0x000 },
13564 { 0xfffff000, 0x00281224, 0x000 },
13565 { 0x00000000, 0x002910c4, 0x000 },
13566 { 0x0000001f, 0x00403624, 0x000 },
13567 { 0x00000000, 0x00800000, 0x000 },
13568 { 0x00000000, 0x1ac00000, 0x67c },
13569 { 0x9f000000, 0x00204411, 0x000 },
13570 { 0xcafebabe, 0x00204811, 0x000 },
13571 { 0x00000000, 0x1ae00000, 0x67f },
13572 { 0x00000000, 0x00800000, 0x000 },
13573 { 0x00000000, 0x1ac00000, 0x681 },
13574 { 0x9e000000, 0x00204411, 0x000 },
13575 { 0xcafebabe, 0x00204811, 0x000 },
13576 { 0x00000000, 0x1ae00000, 0x684 },
13577 { 0x00000000, 0x00800000, 0x000 },
13578 { 0x00000000, 0x00600000, 0x00b },
13579 { 0x00001000, 0x00600411, 0x315 },
13580 { 0x00000000, 0x00200411, 0x000 },
13581 { 0x00000000, 0x00600811, 0x1b2 },
13582 { 0x0000225c, 0x00204411, 0x000 },
13583 { 0x00000003, 0x00204811, 0x000 },
13584 { 0x00002256, 0x00204411, 0x000 },
13585 { 0x0000001b, 0x00204811, 0x000 },
13586 { 0x0000a1fc, 0x00204411, 0x000 },
13587 { 0x00000001, 0x00204811, 0x000 },
13588 { 0x0001a1fd, 0xc0204411, 0x000 },
13589 { 0x00000021, 0x00201e2d, 0x000 },
13590 { 0x00000010, 0x00221e27, 0x000 },
13591 { 0x00000024, 0x0020222d, 0x000 },
13592 { 0x0000ffff, 0x00282228, 0x000 },
13593 { 0x00000000, 0x00294907, 0x000 },
13594 { 0x00000000, 0x00204811, 0x000 },
13595 { 0x00000022, 0x0020222d, 0x000 },
13596 { 0x0000ffff, 0x00282228, 0x000 },
13597 { 0x00000000, 0x00294907, 0x000 },
13598 { 0x00000000, 0x00204811, 0x000 },
13599 { 0x00000023, 0x00201e2d, 0x000 },
13600 { 0x00000010, 0x00221e27, 0x000 },
13601 { 0x00000000, 0x00294907, 0x000 },
13602 { 0x00000000, 0x00404811, 0x000 },
13603 { 0x00000000, 0x00000000, 0x000 },
13604 { 0x00000000, 0x00000000, 0x000 },
13605 { 0x00000000, 0x00000000, 0x000 },
13606 { 0x00000000, 0x00000000, 0x000 },
13607 { 0x00000000, 0x00000000, 0x000 },
13608 { 0x00000000, 0x00000000, 0x000 },
13609 { 0x00000000, 0x00000000, 0x000 },
13610 { 0x00000000, 0x00000000, 0x000 },
13611 { 0x00000000, 0x00000000, 0x000 },
13612 { 0x00000000, 0x00000000, 0x000 },
13613 { 0x00000000, 0x00000000, 0x000 },
13614 { 0x00000000, 0x00000000, 0x000 },
13615 { 0x00000000, 0x00000000, 0x000 },
13616 { 0x00000000, 0x00000000, 0x000 },
13617 { 0x00000000, 0x00000000, 0x000 },
13618 { 0x00000000, 0x00000000, 0x000 },
13619 { 0x00000000, 0x00000000, 0x000 },
13620 { 0x00000000, 0x00000000, 0x000 },
13621 { 0x00000000, 0x00000000, 0x000 },
13622 { 0x00000000, 0x00000000, 0x000 },
13623 { 0x00000000, 0x00000000, 0x000 },
13624 { 0x00000000, 0x00000000, 0x000 },
13625 { 0x00000000, 0x00000000, 0x000 },
13626 { 0x00000000, 0x00000000, 0x000 },
13627 { 0x00000000, 0x00000000, 0x000 },
13628 { 0x00000000, 0x00000000, 0x000 },
13629 { 0x00000000, 0x00000000, 0x000 },
13630 { 0x00000000, 0x00000000, 0x000 },
13631 { 0x00000000, 0x00000000, 0x000 },
13632 { 0x00000000, 0x00000000, 0x000 },
13633 { 0x00000000, 0x00000000, 0x000 },
13634 { 0x00000000, 0x00000000, 0x000 },
13635 { 0x00000000, 0x00000000, 0x000 },
13636 { 0x00000000, 0x00000000, 0x000 },
13637 { 0x00000000, 0x00000000, 0x000 },
13638 { 0x00000000, 0x00000000, 0x000 },
13639 { 0x00000000, 0x00000000, 0x000 },
13640 { 0x00000000, 0x00000000, 0x000 },
13641 { 0x00000000, 0x00000000, 0x000 },
13642 { 0x00000000, 0x00000000, 0x000 },
13643 { 0x00000000, 0x00000000, 0x000 },
13644 { 0x00000000, 0x00000000, 0x000 },
13645 { 0x00000000, 0x00000000, 0x000 },
13646 { 0x00000000, 0x00000000, 0x000 },
13647 { 0x00000000, 0x00000000, 0x000 },
13648 { 0x00000000, 0x00000000, 0x000 },
13649 { 0x00000000, 0x00000000, 0x000 },
13650 { 0x00000000, 0x00000000, 0x000 },
13651 { 0x00000000, 0x00000000, 0x000 },
13652 { 0x00000000, 0x00000000, 0x000 },
13653 { 0x00000000, 0x00000000, 0x000 },
13654 { 0x00000000, 0x00000000, 0x000 },
13655 { 0x00000000, 0x00000000, 0x000 },
13656 { 0x00000000, 0x00000000, 0x000 },
13657 { 0x00000000, 0x00000000, 0x000 },
13658 { 0x00000000, 0x00000000, 0x000 },
13659 { 0x00000000, 0x00000000, 0x000 },
13660 { 0x00000000, 0x00000000, 0x000 },
13661 { 0x00000000, 0x00000000, 0x000 },
13662 { 0x00000000, 0x00000000, 0x000 },
13663 { 0x00000000, 0x00000000, 0x000 },
13664 { 0x00000000, 0x00000000, 0x000 },
13665 { 0x00000000, 0x00000000, 0x000 },
13666 { 0x00000000, 0x00000000, 0x000 },
13667 { 0x00000000, 0x00000000, 0x000 },
13668 { 0x00000000, 0x00000000, 0x000 },
13669 { 0x00000000, 0x00000000, 0x000 },
13670 { 0x00000000, 0x00000000, 0x000 },
13671 { 0x00000000, 0x00000000, 0x000 },
13672 { 0x014204f5, 0x05b30250, 0x000 },
13673 { 0x01c30168, 0x043505b3, 0x000 },
13674 { 0x02250209, 0x02500151, 0x000 },
13675 { 0x02230245, 0x02a00241, 0x000 },
13676 { 0x03cd05b3, 0x05b305b3, 0x000 },
13677 { 0x063c063d, 0x031f05b3, 0x000 },
13678 { 0x05b305b8, 0x03200340, 0x000 },
13679 { 0x032a0282, 0x03420334, 0x000 },
13680 { 0x05b305b3, 0x05b305b3, 0x000 },
13681 { 0x05b30544, 0x05b305b3, 0x000 },
13682 { 0x03b205b3, 0x04ae0344, 0x000 },
13683 { 0x048d0443, 0x043305b3, 0x000 },
13684 { 0x04c305b3, 0x043704d0, 0x000 },
13685 { 0x044304fa, 0x03510371, 0x000 },
13686 { 0x05b305b3, 0x05b305b3, 0x000 },
13687 { 0x05b305b3, 0x05b305b3, 0x000 },
13688 { 0x05b305b3, 0x063205ba, 0x000 },
13689 { 0x05b305b3, 0x000705b3, 0x000 },
13690 { 0x05b305b3, 0x05b305b3, 0x000 },
13691 { 0x05b305b3, 0x05b305b3, 0x000 },
13692 { 0x03ee03e3, 0x03fe03fc, 0x000 },
13693 { 0x04040400, 0x04020406, 0x000 },
13694 { 0x0412040e, 0x041a0416, 0x000 },
13695 { 0x0422041e, 0x042a0426, 0x000 },
13696 { 0x05b305b3, 0x042e05b3, 0x000 },
13697 { 0x05b305b3, 0x05b305b3, 0x000 },
13698 { 0x05b305b3, 0x05b305b3, 0x000 },
13699 { 0x00020668, 0x06860006, 0x000 },
13700};
13701
13702static const u32 RV670_pfp_microcode[] = {
137030xca0400,
137040xa00000,
137050x7e828b,
137060x7c038b,
137070x8001b8,
137080x7c038b,
137090xd4401e,
137100xee001e,
137110xca0400,
137120xa00000,
137130x7e828b,
137140xc41838,
137150xca2400,
137160xca2800,
137170x9581a8,
137180xc41c3a,
137190xc3c000,
137200xca0800,
137210xca0c00,
137220x7c744b,
137230xc20005,
137240x99c000,
137250xc41c3a,
137260x7c744c,
137270xc0fff0,
137280x042c04,
137290x309002,
137300x7d2500,
137310x351402,
137320x7d350b,
137330x255403,
137340x7cd580,
137350x259c03,
137360x95c004,
137370xd5001b,
137380x7eddc1,
137390x7d9d80,
137400xd6801b,
137410xd5801b,
137420xd4401e,
137430xd5401e,
137440xd6401e,
137450xd6801e,
137460xd4801e,
137470xd4c01e,
137480x9783d3,
137490xd5c01e,
137500xca0800,
137510x80001a,
137520xca0c00,
137530xe4011e,
137540xd4001e,
137550x80000c,
137560xc41838,
137570xe4013e,
137580xd4001e,
137590x80000c,
137600xc41838,
137610xd4401e,
137620xee001e,
137630xca0400,
137640xa00000,
137650x7e828b,
137660xe4011e,
137670xd4001e,
137680xd4401e,
137690xee001e,
137700xca0400,
137710xa00000,
137720x7e828b,
137730xe4013e,
137740xd4001e,
137750xd4401e,
137760xee001e,
137770xca0400,
137780xa00000,
137790x7e828b,
137800xca1800,
137810xd4401e,
137820xd5801e,
137830x800053,
137840xd40075,
137850xd4401e,
137860xca0800,
137870xca0c00,
137880xca1000,
137890xd48019,
137900xd4c018,
137910xd50017,
137920xd4801e,
137930xd4c01e,
137940xd5001e,
137950xe2001e,
137960xca0400,
137970xa00000,
137980x7e828b,
137990xca0800,
138000xd48060,
138010xd4401e,
138020x800000,
138030xd4801e,
138040xca0800,
138050xd48061,
138060xd4401e,
138070x800000,
138080xd4801e,
138090xca0800,
138100xca0c00,
138110xd4401e,
138120xd48016,
138130xd4c016,
138140xd4801e,
138150x8001b8,
138160xd4c01e,
138170xc60843,
138180xca0c00,
138190xca1000,
138200x948004,
138210xca1400,
138220xe420f3,
138230xd42013,
138240xd56065,
138250xd4e01c,
138260xd5201c,
138270xd5601c,
138280x800000,
138290x062001,
138300xc60843,
138310xca0c00,
138320xca1000,
138330x9483f7,
138340xca1400,
138350xe420f3,
138360x800079,
138370xd42013,
138380xc60843,
138390xca0c00,
138400xca1000,
138410x9883ef,
138420xca1400,
138430xd40064,
138440x80008d,
138450x000000,
138460xc41432,
138470xc61843,
138480xc4082f,
138490x954005,
138500xc40c30,
138510xd4401e,
138520x800000,
138530xee001e,
138540x9583f5,
138550xc41031,
138560xd44033,
138570xd52065,
138580xd4a01c,
138590xd4e01c,
138600xd5201c,
138610xe4015e,
138620xd4001e,
138630x800000,
138640x062001,
138650xca1800,
138660x0a2001,
138670xd60076,
138680xc40836,
138690x988007,
138700xc61045,
138710x950110,
138720xd4001f,
138730xd46062,
138740x800000,
138750xd42062,
138760xcc3835,
138770xcc1433,
138780x8401bb,
138790xd40072,
138800xd5401e,
138810x800000,
138820xee001e,
138830xe2001a,
138840x8401bb,
138850xe2001a,
138860xcc104b,
138870xcc0447,
138880x2c9401,
138890x7d098b,
138900x984005,
138910x7d15cb,
138920xd4001a,
138930x8001b8,
138940xd4006d,
138950x344401,
138960xcc0c48,
138970x98403a,
138980xcc2c4a,
138990x958004,
139000xcc0449,
139010x8001b8,
139020xd4001a,
139030xd4c01a,
139040x282801,
139050x8400f0,
139060xcc1003,
139070x98801b,
139080x04380c,
139090x8400f0,
139100xcc1003,
139110x988017,
139120x043808,
139130x8400f0,
139140xcc1003,
139150x988013,
139160x043804,
139170x8400f0,
139180xcc1003,
139190x988014,
139200xcc104c,
139210x9a8009,
139220xcc144d,
139230x9840dc,
139240xd4006d,
139250xcc1848,
139260xd5001a,
139270xd5401a,
139280x8000c9,
139290xd5801a,
139300x96c0d5,
139310xd4006d,
139320x8001b8,
139330xd4006e,
139340x9ac003,
139350xd4006d,
139360xd4006e,
139370x800000,
139380xec007f,
139390x9ac0cc,
139400xd4006d,
139410x8001b8,
139420xd4006e,
139430xcc1403,
139440xcc1803,
139450xcc1c03,
139460x7d9103,
139470x7dd583,
139480x7d190c,
139490x35cc1f,
139500x35701f,
139510x7cf0cb,
139520x7cd08b,
139530x880000,
139540x7e8e8b,
139550x95c004,
139560xd4006e,
139570x8001b8,
139580xd4001a,
139590xd4c01a,
139600xcc0803,
139610xcc0c03,
139620xcc1003,
139630xcc1403,
139640xcc1803,
139650xcc1c03,
139660xcc2403,
139670xcc2803,
139680x35c41f,
139690x36b01f,
139700x7c704b,
139710x34f01f,
139720x7c704b,
139730x35701f,
139740x7c704b,
139750x7d8881,
139760x7dccc1,
139770x7e5101,
139780x7e9541,
139790x7c9082,
139800x7cd4c2,
139810x7c848b,
139820x9ac003,
139830x7c8c8b,
139840x2c8801,
139850x98809e,
139860xd4006d,
139870x98409c,
139880xd4006e,
139890xcc084c,
139900xcc0c4d,
139910xcc1048,
139920xd4801a,
139930xd4c01a,
139940x800101,
139950xd5001a,
139960xcc0832,
139970xd40032,
139980x9482d9,
139990xca0c00,
140000xd4401e,
140010x800000,
140020xd4001e,
140030xe4011e,
140040xd4001e,
140050xca0800,
140060xca0c00,
140070xca1000,
140080xd4401e,
140090xca1400,
140100xd4801e,
140110xd4c01e,
140120xd5001e,
140130xd5401e,
140140xd54034,
140150x800000,
140160xee001e,
140170x280404,
140180xe2001a,
140190xe2001a,
140200xd4401a,
140210xca3800,
140220xcc0803,
140230xcc0c03,
140240xcc0c03,
140250xcc0c03,
140260x9882bd,
140270x000000,
140280x8401bb,
140290xd7a06f,
140300x800000,
140310xee001f,
140320xca0400,
140330xc2ff00,
140340xcc0834,
140350xc13fff,
140360x7c74cb,
140370x7cc90b,
140380x7d010f,
140390x9902b0,
140400x7c738b,
140410x8401bb,
140420xd7a06f,
140430x800000,
140440xee001f,
140450xca0800,
140460x281900,
140470x7d898b,
140480x958014,
140490x281404,
140500xca0c00,
140510xca1000,
140520xca1c00,
140530xca2400,
140540xe2001f,
140550xd4c01a,
140560xd5001a,
140570xd5401a,
140580xcc1803,
140590xcc2c03,
140600xcc2c03,
140610xcc2c03,
140620x7da58b,
140630x7d9c47,
140640x984297,
140650x000000,
140660x800161,
140670xd4c01a,
140680xd4401e,
140690xd4801e,
140700x800000,
140710xee001e,
140720xe4011e,
140730xd4001e,
140740xd4401e,
140750xee001e,
140760xca0400,
140770xa00000,
140780x7e828b,
140790xe4013e,
140800xd4001e,
140810xd4401e,
140820xee001e,
140830xca0400,
140840xa00000,
140850x7e828b,
140860xca0800,
140870x248c06,
140880x0ccc06,
140890x98c006,
140900xcc104e,
140910x990004,
140920xd40073,
140930xe4011e,
140940xd4001e,
140950xd4401e,
140960xd4801e,
140970x800000,
140980xee001e,
140990xca0800,
141000xca0c00,
141010x34d018,
141020x251001,
141030x950021,
141040xc17fff,
141050xca1000,
141060xca1400,
141070xca1800,
141080xd4801d,
141090xd4c01d,
141100x7db18b,
141110xc14202,
141120xc2c001,
141130xd5801d,
141140x34dc0e,
141150x7d5d4c,
141160x7f734c,
141170xd7401e,
141180xd5001e,
141190xd5401e,
141200xc14200,
141210xc2c000,
141220x099c01,
141230x31dc10,
141240x7f5f4c,
141250x7f734c,
141260x042802,
141270x7d8380,
141280xd5a86f,
141290xd58066,
141300xd7401e,
141310xec005e,
141320xc82402,
141330xc82402,
141340x8001b8,
141350xd60076,
141360xd4401e,
141370xd4801e,
141380xd4c01e,
141390x800000,
141400xee001e,
141410x800000,
141420xee001f,
141430xd4001f,
141440x800000,
141450xd4001f,
141460xd4001f,
141470x880000,
141480xd4001f,
141490x000000,
141500x000000,
141510x000000,
141520x000000,
141530x000000,
141540x000000,
141550x000000,
141560x000000,
141570x000000,
141580x000000,
141590x000000,
141600x000000,
141610x000000,
141620x000000,
141630x000000,
141640x000000,
141650x000000,
141660x000000,
141670x000000,
141680x000000,
141690x000000,
141700x000000,
141710x000000,
141720x000000,
141730x000000,
141740x000000,
141750x000000,
141760x000000,
141770x000000,
141780x000000,
141790x000000,
141800x000000,
141810x000000,
141820x000000,
141830x000000,
141840x000000,
141850x000000,
141860x000000,
141870x000000,
141880x000000,
141890x000000,
141900x000000,
141910x000000,
141920x000000,
141930x000000,
141940x000000,
141950x000000,
141960x000000,
141970x000000,
141980x000000,
141990x000000,
142000x000000,
142010x000000,
142020x000000,
142030x000000,
142040x000000,
142050x000000,
142060x000000,
142070x000000,
142080x000000,
142090x000000,
142100x000000,
142110x000000,
142120x000000,
142130x000000,
142140x000000,
142150x010171,
142160x020178,
142170x03008f,
142180x04007f,
142190x050003,
142200x06003f,
142210x070032,
142220x08012c,
142230x090046,
142240x0a0036,
142250x1001b6,
142260x1700a2,
142270x22013a,
142280x230149,
142290x2000b4,
142300x240125,
142310x27004d,
142320x28006a,
142330x2a0060,
142340x2b0052,
142350x2f0065,
142360x320087,
142370x34017f,
142380x3c0156,
142390x3f0072,
142400x41018c,
142410x44012e,
142420x550173,
142430x56017a,
142440x60000b,
142450x610034,
142460x620038,
142470x630038,
142480x640038,
142490x650038,
142500x660038,
142510x670038,
142520x68003a,
142530x690041,
142540x6a0048,
142550x6b0048,
142560x6c0048,
142570x6d0048,
142580x6e0048,
142590x6f0048,
142600x000006,
142610x000006,
142620x000006,
142630x000006,
142640x000006,
142650x000006,
142660x000006,
142670x000006,
142680x000006,
142690x000006,
142700x000006,
142710x000006,
142720x000006,
142730x000006,
142740x000006,
142750x000006,
142760x000006,
142770x000006,
142780x000006,
14279};
14280
14281static const u32 RS780_cp_microcode[][3] = {
14282 { 0x00000000, 0xc0200400, 0x000 },
14283 { 0x00000000, 0x00a0000a, 0x000 },
14284 { 0x0000ffff, 0x00284621, 0x000 },
14285 { 0x00000000, 0xd9004800, 0x000 },
14286 { 0x00000000, 0xc0200400, 0x000 },
14287 { 0x00000000, 0x00a0000a, 0x000 },
14288 { 0x00000000, 0x00e00000, 0x000 },
14289 { 0x00010000, 0xc0294620, 0x000 },
14290 { 0x00000000, 0xd9004800, 0x000 },
14291 { 0x00000000, 0xc0200400, 0x000 },
14292 { 0x00000000, 0x00a0000a, 0x000 },
14293 { 0x81000000, 0x00204411, 0x000 },
14294 { 0x00000001, 0x00204811, 0x000 },
14295 { 0x00042004, 0x00604411, 0x622 },
14296 { 0x00000000, 0x00600000, 0x5d1 },
14297 { 0x00000000, 0x00600000, 0x5de },
14298 { 0x00000000, 0xc0200800, 0x000 },
14299 { 0x00000f00, 0x00281622, 0x000 },
14300 { 0x00000008, 0x00211625, 0x000 },
14301 { 0x00000018, 0x00203625, 0x000 },
14302 { 0x8d000000, 0x00204411, 0x000 },
14303 { 0x00000004, 0x002f0225, 0x000 },
14304 { 0x00000000, 0x0ce00000, 0x018 },
14305 { 0x00412000, 0x00404811, 0x019 },
14306 { 0x00422000, 0x00204811, 0x000 },
14307 { 0x8e000000, 0x00204411, 0x000 },
14308 { 0x00000028, 0x00204a2d, 0x000 },
14309 { 0x90000000, 0x00204411, 0x000 },
14310 { 0x00000000, 0x00204805, 0x000 },
14311 { 0x0000000c, 0x00211622, 0x000 },
14312 { 0x00000003, 0x00281625, 0x000 },
14313 { 0x00000019, 0x00211a22, 0x000 },
14314 { 0x00000004, 0x00281a26, 0x000 },
14315 { 0x00000000, 0x002914c5, 0x000 },
14316 { 0x00000019, 0x00203625, 0x000 },
14317 { 0x00000000, 0x003a1402, 0x000 },
14318 { 0x00000016, 0x00211625, 0x000 },
14319 { 0x00000003, 0x00281625, 0x000 },
14320 { 0x00000017, 0x00200e2d, 0x000 },
14321 { 0xfffffffc, 0x00280e23, 0x000 },
14322 { 0x00000000, 0x002914a3, 0x000 },
14323 { 0x00000017, 0x00203625, 0x000 },
14324 { 0x00008000, 0x00280e22, 0x000 },
14325 { 0x00000007, 0x00220e23, 0x000 },
14326 { 0x00000000, 0x0029386e, 0x000 },
14327 { 0x20000000, 0x00280e22, 0x000 },
14328 { 0x00000006, 0x00210e23, 0x000 },
14329 { 0x00000000, 0x0029386e, 0x000 },
14330 { 0x00000000, 0x00220222, 0x000 },
14331 { 0x00000000, 0x14e00000, 0x038 },
14332 { 0x00000000, 0x2ee00000, 0x035 },
14333 { 0x00000000, 0x2ce00000, 0x037 },
14334 { 0x00000000, 0x00400e2d, 0x039 },
14335 { 0x00000008, 0x00200e2d, 0x000 },
14336 { 0x00000009, 0x0040122d, 0x046 },
14337 { 0x00000001, 0x00400e2d, 0x039 },
14338 { 0x00000000, 0xc0200c00, 0x000 },
14339 { 0x003ffffc, 0x00281223, 0x000 },
14340 { 0x00000002, 0x00221224, 0x000 },
14341 { 0x0000001f, 0x00211e23, 0x000 },
14342 { 0x00000000, 0x14e00000, 0x03e },
14343 { 0x00000008, 0x00401c11, 0x041 },
14344 { 0x0000000d, 0x00201e2d, 0x000 },
14345 { 0x0000000f, 0x00281e27, 0x000 },
14346 { 0x00000003, 0x00221e27, 0x000 },
14347 { 0x7fc00000, 0x00281a23, 0x000 },
14348 { 0x00000014, 0x00211a26, 0x000 },
14349 { 0x00000001, 0x00331a26, 0x000 },
14350 { 0x00000008, 0x00221a26, 0x000 },
14351 { 0x00000000, 0x00290cc7, 0x000 },
14352 { 0x00000027, 0x00203624, 0x000 },
14353 { 0x00007f00, 0x00281221, 0x000 },
14354 { 0x00001400, 0x002f0224, 0x000 },
14355 { 0x00000000, 0x0ce00000, 0x04b },
14356 { 0x00000001, 0x00290e23, 0x000 },
14357 { 0x0000000e, 0x00203623, 0x000 },
14358 { 0x0000e000, 0x00204411, 0x000 },
14359 { 0xfff80000, 0x00294a23, 0x000 },
14360 { 0x00000000, 0x003a2c02, 0x000 },
14361 { 0x00000002, 0x00220e2b, 0x000 },
14362 { 0xfc000000, 0x00280e23, 0x000 },
14363 { 0x0000000f, 0x00203623, 0x000 },
14364 { 0x00001fff, 0x00294a23, 0x000 },
14365 { 0x00000027, 0x00204a2d, 0x000 },
14366 { 0x00000000, 0x00204811, 0x000 },
14367 { 0x00000029, 0x00200e2d, 0x000 },
14368 { 0x060a0200, 0x00294a23, 0x000 },
14369 { 0x00000000, 0x00204811, 0x000 },
14370 { 0x00000000, 0x00204811, 0x000 },
14371 { 0x00000001, 0x00210222, 0x000 },
14372 { 0x00000000, 0x14e00000, 0x061 },
14373 { 0x00000000, 0x2ee00000, 0x05f },
14374 { 0x00000000, 0x2ce00000, 0x05e },
14375 { 0x00000000, 0x00400e2d, 0x062 },
14376 { 0x00000001, 0x00400e2d, 0x062 },
14377 { 0x0000000a, 0x00200e2d, 0x000 },
14378 { 0x0000000b, 0x0040122d, 0x06a },
14379 { 0x00000000, 0xc0200c00, 0x000 },
14380 { 0x003ffffc, 0x00281223, 0x000 },
14381 { 0x00000002, 0x00221224, 0x000 },
14382 { 0x7fc00000, 0x00281623, 0x000 },
14383 { 0x00000014, 0x00211625, 0x000 },
14384 { 0x00000001, 0x00331625, 0x000 },
14385 { 0x80000000, 0x00280e23, 0x000 },
14386 { 0x00000000, 0x00290ca3, 0x000 },
14387 { 0x3ffffc00, 0x00290e23, 0x000 },
14388 { 0x0000001f, 0x00211e23, 0x000 },
14389 { 0x00000000, 0x14e00000, 0x06d },
14390 { 0x00000100, 0x00401c11, 0x070 },
14391 { 0x0000000d, 0x00201e2d, 0x000 },
14392 { 0x000000f0, 0x00281e27, 0x000 },
14393 { 0x00000004, 0x00221e27, 0x000 },
14394 { 0x81000000, 0x00204411, 0x000 },
14395 { 0x0000000d, 0x00204811, 0x000 },
14396 { 0xfffff0ff, 0x00281a30, 0x000 },
14397 { 0x0000a028, 0x00204411, 0x000 },
14398 { 0x00000000, 0x002948e6, 0x000 },
14399 { 0x0000a018, 0x00204411, 0x000 },
14400 { 0x3fffffff, 0x00284a23, 0x000 },
14401 { 0x0000a010, 0x00204411, 0x000 },
14402 { 0x00000000, 0x00204804, 0x000 },
14403 { 0x00000030, 0x0020162d, 0x000 },
14404 { 0x00000002, 0x00291625, 0x000 },
14405 { 0x00000030, 0x00203625, 0x000 },
14406 { 0x00000025, 0x0020162d, 0x000 },
14407 { 0x00000000, 0x002f00a3, 0x000 },
14408 { 0x00000000, 0x0cc00000, 0x083 },
14409 { 0x00000026, 0x0020162d, 0x000 },
14410 { 0x00000000, 0x002f00a4, 0x000 },
14411 { 0x00000000, 0x0cc00000, 0x084 },
14412 { 0x00000000, 0x00400000, 0x08a },
14413 { 0x00000025, 0x00203623, 0x000 },
14414 { 0x00000026, 0x00203624, 0x000 },
14415 { 0x00000017, 0x00201e2d, 0x000 },
14416 { 0x00000002, 0x00210227, 0x000 },
14417 { 0x00000000, 0x14e00000, 0x08a },
14418 { 0x00000000, 0x00600000, 0x5ff },
14419 { 0x00000000, 0x00600000, 0x5f3 },
14420 { 0x00000002, 0x00210e22, 0x000 },
14421 { 0x00000000, 0x14c00000, 0x08d },
14422 { 0x00000012, 0xc0403620, 0x093 },
14423 { 0x00000000, 0x2ee00000, 0x091 },
14424 { 0x00000000, 0x2ce00000, 0x090 },
14425 { 0x00000002, 0x00400e2d, 0x092 },
14426 { 0x00000003, 0x00400e2d, 0x092 },
14427 { 0x0000000c, 0x00200e2d, 0x000 },
14428 { 0x00000012, 0x00203623, 0x000 },
14429 { 0x00000003, 0x00210e22, 0x000 },
14430 { 0x00000000, 0x14c00000, 0x098 },
14431 { 0x0000a00c, 0x00204411, 0x000 },
14432 { 0x00000000, 0xc0204800, 0x000 },
14433 { 0x00000000, 0xc0404800, 0x0a0 },
14434 { 0x0000a00c, 0x00204411, 0x000 },
14435 { 0x00000000, 0x00204811, 0x000 },
14436 { 0x00000000, 0x2ee00000, 0x09e },
14437 { 0x00000000, 0x2ce00000, 0x09d },
14438 { 0x00000002, 0x00400e2d, 0x09f },
14439 { 0x00000003, 0x00400e2d, 0x09f },
14440 { 0x0000000c, 0x00200e2d, 0x000 },
14441 { 0x00000000, 0x00204803, 0x000 },
14442 { 0x00000000, 0x003a0c02, 0x000 },
14443 { 0x003f0000, 0x00280e23, 0x000 },
14444 { 0x00000010, 0x00210e23, 0x000 },
14445 { 0x00000011, 0x00203623, 0x000 },
14446 { 0x0000001e, 0x0021022b, 0x000 },
14447 { 0x00000000, 0x14c00000, 0x0a7 },
14448 { 0x00000016, 0xc0203620, 0x000 },
14449 { 0x0000001f, 0x0021022b, 0x000 },
14450 { 0x00000000, 0x14c00000, 0x0aa },
14451 { 0x00000015, 0xc0203620, 0x000 },
14452 { 0x00000008, 0x00210e2b, 0x000 },
14453 { 0x0000007f, 0x00280e23, 0x000 },
14454 { 0x00000000, 0x002f0223, 0x000 },
14455 { 0x00000000, 0x0ce00000, 0x0e1 },
14456 { 0x00000000, 0x27000000, 0x000 },
14457 { 0x00000000, 0x00600000, 0x2a3 },
14458 { 0x00000001, 0x002f0223, 0x000 },
14459 { 0x00000000, 0x0ae00000, 0x0b3 },
14460 { 0x00000000, 0x00600000, 0x13a },
14461 { 0x81000000, 0x00204411, 0x000 },
14462 { 0x00000006, 0x00204811, 0x000 },
14463 { 0x0000000c, 0x00221e30, 0x000 },
14464 { 0x99800000, 0x00204411, 0x000 },
14465 { 0x00000004, 0x0020122d, 0x000 },
14466 { 0x00000008, 0x00221224, 0x000 },
14467 { 0x00000010, 0x00201811, 0x000 },
14468 { 0x00000000, 0x00291ce4, 0x000 },
14469 { 0x00000000, 0x00604807, 0x12f },
14470 { 0x9b000000, 0x00204411, 0x000 },
14471 { 0x00000000, 0x00204802, 0x000 },
14472 { 0x9c000000, 0x00204411, 0x000 },
14473 { 0x00000000, 0x0033146f, 0x000 },
14474 { 0x00000001, 0x00333e23, 0x000 },
14475 { 0x00000000, 0xd9004800, 0x000 },
14476 { 0x00000000, 0x00203c05, 0x000 },
14477 { 0x81000000, 0x00204411, 0x000 },
14478 { 0x0000000e, 0x00204811, 0x000 },
14479 { 0x00000000, 0x00201010, 0x000 },
14480 { 0x0000e007, 0x00204411, 0x000 },
14481 { 0x0000000f, 0x0021022b, 0x000 },
14482 { 0x00000000, 0x14c00000, 0x0cb },
14483 { 0x00f8ff08, 0x00204811, 0x000 },
14484 { 0x98000000, 0x00404811, 0x0dc },
14485 { 0x000000f0, 0x00280e22, 0x000 },
14486 { 0x000000a0, 0x002f0223, 0x000 },
14487 { 0x00000000, 0x0cc00000, 0x0da },
14488 { 0x00000011, 0x00200e2d, 0x000 },
14489 { 0x00000001, 0x002f0223, 0x000 },
14490 { 0x00000000, 0x0ce00000, 0x0d5 },
14491 { 0x00000002, 0x002f0223, 0x000 },
14492 { 0x00000000, 0x0ce00000, 0x0d4 },
14493 { 0x00003f00, 0x00400c11, 0x0d6 },
14494 { 0x00001f00, 0x00400c11, 0x0d6 },
14495 { 0x00000f00, 0x00200c11, 0x000 },
14496 { 0x00380009, 0x00294a23, 0x000 },
14497 { 0x3f000000, 0x00280e2b, 0x000 },
14498 { 0x00000002, 0x00220e23, 0x000 },
14499 { 0x00000007, 0x00494a23, 0x0dc },
14500 { 0x00380f09, 0x00204811, 0x000 },
14501 { 0x68000007, 0x00204811, 0x000 },
14502 { 0x00000008, 0x00214a27, 0x000 },
14503 { 0x00000000, 0x00204811, 0x000 },
14504 { 0x060a0200, 0x00294a24, 0x000 },
14505 { 0x00000000, 0x00204811, 0x000 },
14506 { 0x00000000, 0x00204811, 0x000 },
14507 { 0x0000a202, 0x00204411, 0x000 },
14508 { 0x00ff0000, 0x00280e22, 0x000 },
14509 { 0x00000080, 0x00294a23, 0x000 },
14510 { 0x00000027, 0x00200e2d, 0x000 },
14511 { 0x00000026, 0x0020122d, 0x000 },
14512 { 0x00000000, 0x002f0083, 0x000 },
14513 { 0x00000000, 0x0ce00000, 0x0ea },
14514 { 0x00000000, 0x00600000, 0x5f9 },
14515 { 0x00000000, 0x00400000, 0x0eb },
14516 { 0x00000000, 0x00600000, 0x5fc },
14517 { 0x00000007, 0x0020222d, 0x000 },
14518 { 0x00000005, 0x00220e22, 0x000 },
14519 { 0x00100000, 0x00280e23, 0x000 },
14520 { 0x00000000, 0x00292068, 0x000 },
14521 { 0x00000000, 0x003a0c02, 0x000 },
14522 { 0x000000ef, 0x00280e23, 0x000 },
14523 { 0x00000000, 0x00292068, 0x000 },
14524 { 0x00000017, 0x00200e2d, 0x000 },
14525 { 0x00000003, 0x00210223, 0x000 },
14526 { 0x00000000, 0x14e00000, 0x0f8 },
14527 { 0x0000000b, 0x00210228, 0x000 },
14528 { 0x00000000, 0x14c00000, 0x0f8 },
14529 { 0x00000400, 0x00292228, 0x000 },
14530 { 0x00000014, 0x00203628, 0x000 },
14531 { 0x0000001c, 0x00210e22, 0x000 },
14532 { 0x00000000, 0x14c00000, 0x0fd },
14533 { 0x0000a30c, 0x00204411, 0x000 },
14534 { 0x00000000, 0x00204811, 0x000 },
14535 { 0x0000001e, 0x00210e22, 0x000 },
14536 { 0x00000000, 0x14c00000, 0x10b },
14537 { 0x0000a30f, 0x00204411, 0x000 },
14538 { 0x00000011, 0x00200e2d, 0x000 },
14539 { 0x00000001, 0x002f0223, 0x000 },
14540 { 0x00000000, 0x0cc00000, 0x104 },
14541 { 0xffffffff, 0x00404811, 0x10b },
14542 { 0x00000002, 0x002f0223, 0x000 },
14543 { 0x00000000, 0x0cc00000, 0x107 },
14544 { 0x0000ffff, 0x00404811, 0x10b },
14545 { 0x00000004, 0x002f0223, 0x000 },
14546 { 0x00000000, 0x0cc00000, 0x10a },
14547 { 0x000000ff, 0x00404811, 0x10b },
14548 { 0x00000001, 0x00204811, 0x000 },
14549 { 0x0002c400, 0x00204411, 0x000 },
14550 { 0x0000001f, 0x00210e22, 0x000 },
14551 { 0x00000000, 0x14c00000, 0x112 },
14552 { 0x00000010, 0x40210e20, 0x000 },
14553 { 0x00000013, 0x00203623, 0x000 },
14554 { 0x00000018, 0x40224a20, 0x000 },
14555 { 0x00000010, 0xc0424a20, 0x114 },
14556 { 0x00000000, 0x00200c11, 0x000 },
14557 { 0x00000013, 0x00203623, 0x000 },
14558 { 0x00000000, 0x00204811, 0x000 },
14559 { 0x00000000, 0x00204811, 0x000 },
14560 { 0x0000000a, 0x00201011, 0x000 },
14561 { 0x00000000, 0x002f0224, 0x000 },
14562 { 0x00000000, 0x0ce00000, 0x11b },
14563 { 0x00000000, 0x00204811, 0x000 },
14564 { 0x00000001, 0x00531224, 0x117 },
14565 { 0xffbfffff, 0x00283a2e, 0x000 },
14566 { 0x0000001b, 0x00210222, 0x000 },
14567 { 0x00000000, 0x14c00000, 0x12e },
14568 { 0x81000000, 0x00204411, 0x000 },
14569 { 0x0000000d, 0x00204811, 0x000 },
14570 { 0x00000018, 0x00220e30, 0x000 },
14571 { 0xfc000000, 0x00280e23, 0x000 },
14572 { 0x81000000, 0x00204411, 0x000 },
14573 { 0x0000000e, 0x00204811, 0x000 },
14574 { 0x00000000, 0x00201010, 0x000 },
14575 { 0x0000e00e, 0x00204411, 0x000 },
14576 { 0x07f8ff08, 0x00204811, 0x000 },
14577 { 0x00000000, 0x00294a23, 0x000 },
14578 { 0x0000001c, 0x00201e2d, 0x000 },
14579 { 0x00000008, 0x00214a27, 0x000 },
14580 { 0x00000000, 0x00204811, 0x000 },
14581 { 0x060a0200, 0x00294a24, 0x000 },
14582 { 0x00000000, 0x00204811, 0x000 },
14583 { 0x00000000, 0x00204811, 0x000 },
14584 { 0x00000000, 0x00800000, 0x000 },
14585 { 0x81000000, 0x00204411, 0x000 },
14586 { 0x00000001, 0x00204811, 0x000 },
14587 { 0x0000217c, 0x00204411, 0x000 },
14588 { 0x00800000, 0x00204811, 0x000 },
14589 { 0x00000000, 0x00204806, 0x000 },
14590 { 0x00000008, 0x00214a27, 0x000 },
14591 { 0x00000000, 0x17000000, 0x000 },
14592 { 0x0004217f, 0x00604411, 0x622 },
14593 { 0x0000001f, 0x00210230, 0x000 },
14594 { 0x00000000, 0x14c00000, 0x621 },
14595 { 0x00000004, 0x00404c11, 0x135 },
14596 { 0x81000000, 0x00204411, 0x000 },
14597 { 0x00000001, 0x00204811, 0x000 },
14598 { 0x000021f8, 0x00204411, 0x000 },
14599 { 0x0000001c, 0x00204811, 0x000 },
14600 { 0x000421f9, 0x00604411, 0x622 },
14601 { 0x00000011, 0x00210230, 0x000 },
14602 { 0x00000000, 0x14e00000, 0x13c },
14603 { 0x00000000, 0x00800000, 0x000 },
14604 { 0x00000000, 0x00600000, 0x00b },
14605 { 0x00000000, 0x00600411, 0x315 },
14606 { 0x00000000, 0x00200411, 0x000 },
14607 { 0x00000000, 0x00600811, 0x1b2 },
14608 { 0x00000000, 0x00600000, 0x160 },
14609 { 0x0000ffff, 0x40280e20, 0x000 },
14610 { 0x00000010, 0xc0211220, 0x000 },
14611 { 0x0000ffff, 0x40280620, 0x000 },
14612 { 0x00000010, 0xc0210a20, 0x000 },
14613 { 0x00000000, 0x00341461, 0x000 },
14614 { 0x00000000, 0x00741882, 0x2bb },
14615 { 0x0001a1fd, 0x00604411, 0x2e0 },
14616 { 0x00003fff, 0x002f022f, 0x000 },
14617 { 0x00000000, 0x0cc00000, 0x147 },
14618 { 0x00000000, 0xc0400400, 0x001 },
14619 { 0x00000000, 0x00600000, 0x00b },
14620 { 0x00000000, 0x00600411, 0x315 },
14621 { 0x00000000, 0x00200411, 0x000 },
14622 { 0x00000000, 0x00600811, 0x1b2 },
14623 { 0x00003fff, 0x002f022f, 0x000 },
14624 { 0x00000000, 0x0ce00000, 0x000 },
14625 { 0x00000000, 0x00600000, 0x160 },
14626 { 0x00000010, 0x40210e20, 0x000 },
14627 { 0x0000ffff, 0xc0281220, 0x000 },
14628 { 0x00000010, 0x40211620, 0x000 },
14629 { 0x0000ffff, 0xc0681a20, 0x2bb },
14630 { 0x0001a1fd, 0x00604411, 0x2e0 },
14631 { 0x00003fff, 0x002f022f, 0x000 },
14632 { 0x00000000, 0x0cc00000, 0x158 },
14633 { 0x00000000, 0xc0400400, 0x001 },
14634 { 0x0000225c, 0x00204411, 0x000 },
14635 { 0x00000001, 0x00300a2f, 0x000 },
14636 { 0x00000001, 0x00210a22, 0x000 },
14637 { 0x00000003, 0x00384a22, 0x000 },
14638 { 0x00002256, 0x00204411, 0x000 },
14639 { 0x0000001a, 0x00204811, 0x000 },
14640 { 0x0000a1fc, 0x00204411, 0x000 },
14641 { 0x00000001, 0x00804811, 0x000 },
14642 { 0x00000000, 0x00600000, 0x00b },
14643 { 0x00000000, 0x00600000, 0x18f },
14644 { 0x00000000, 0x00600000, 0x1a0 },
14645 { 0x00003fff, 0x002f022f, 0x000 },
14646 { 0x00000000, 0x0ce00000, 0x000 },
14647 { 0x00000000, 0x00202c08, 0x000 },
14648 { 0x00000000, 0x00202411, 0x000 },
14649 { 0x00000000, 0x00202811, 0x000 },
14650 { 0x00002256, 0x00204411, 0x000 },
14651 { 0x00000016, 0x00204811, 0x000 },
14652 { 0x0000225c, 0x00204411, 0x000 },
14653 { 0x00000003, 0x00204811, 0x000 },
14654 { 0x93800000, 0x00204411, 0x000 },
14655 { 0x00000002, 0x00221e29, 0x000 },
14656 { 0x00000000, 0x007048eb, 0x19c },
14657 { 0x00000000, 0x00600000, 0x2bb },
14658 { 0x00000001, 0x40330620, 0x000 },
14659 { 0x00000000, 0xc0302409, 0x000 },
14660 { 0x00003fff, 0x002f022f, 0x000 },
14661 { 0x00000000, 0x0ce00000, 0x000 },
14662 { 0x00000000, 0x00600000, 0x2a3 },
14663 { 0x00000000, 0x002f0221, 0x000 },
14664 { 0x00000000, 0x0ae00000, 0x181 },
14665 { 0x00000000, 0x00600000, 0x13a },
14666 { 0x00000000, 0x00400000, 0x186 },
14667 { 0x95000000, 0x00204411, 0x000 },
14668 { 0x00000000, 0x002f0221, 0x000 },
14669 { 0x00000000, 0x0ce00000, 0x186 },
14670 { 0x00000000, 0xc0204800, 0x000 },
14671 { 0x00000001, 0x00530621, 0x182 },
14672 { 0x92000000, 0x00204411, 0x000 },
14673 { 0x00000000, 0xc0604800, 0x197 },
14674 { 0x0001a1fd, 0x00204411, 0x000 },
14675 { 0x00000011, 0x0020062d, 0x000 },
14676 { 0x00000000, 0x0078042a, 0x2fb },
14677 { 0x00000000, 0x00202809, 0x000 },
14678 { 0x00003fff, 0x002f022f, 0x000 },
14679 { 0x00000000, 0x0cc00000, 0x174 },
14680 { 0x00000000, 0xc0400400, 0x001 },
14681 { 0x00000210, 0x00600411, 0x315 },
14682 { 0x00003fff, 0x002f022f, 0x000 },
14683 { 0x00000000, 0x0ce00000, 0x194 },
14684 { 0x00000015, 0xc0203620, 0x000 },
14685 { 0x00000016, 0xc0203620, 0x000 },
14686 { 0x3f800000, 0x00200411, 0x000 },
14687 { 0x46000000, 0x00600811, 0x1b2 },
14688 { 0x00000000, 0x00800000, 0x000 },
14689 { 0x0000a1fc, 0x00204411, 0x000 },
14690 { 0x00003fff, 0x002f022f, 0x000 },
14691 { 0x00000000, 0x0cc00000, 0x19b },
14692 { 0x00000001, 0x00804811, 0x000 },
14693 { 0x00000021, 0x00804811, 0x000 },
14694 { 0x0000ffff, 0x40280e20, 0x000 },
14695 { 0x00000010, 0xc0211220, 0x000 },
14696 { 0x0000ffff, 0x40281620, 0x000 },
14697 { 0x00000010, 0xc0811a20, 0x000 },
14698 { 0x81000000, 0x00204411, 0x000 },
14699 { 0x00000006, 0x00204811, 0x000 },
14700 { 0x00000008, 0x00221e30, 0x000 },
14701 { 0x00000029, 0x00201a2d, 0x000 },
14702 { 0x0000e000, 0x00204411, 0x000 },
14703 { 0xfffbff09, 0x00204811, 0x000 },
14704 { 0x0000000f, 0x0020222d, 0x000 },
14705 { 0x00001fff, 0x00294a28, 0x000 },
14706 { 0x00000006, 0x0020222d, 0x000 },
14707 { 0x00000000, 0x002920e8, 0x000 },
14708 { 0x00000000, 0x00204808, 0x000 },
14709 { 0x00000000, 0x00204811, 0x000 },
14710 { 0x060a0200, 0x00294a26, 0x000 },
14711 { 0x00000000, 0x00204811, 0x000 },
14712 { 0x00000000, 0x00204811, 0x000 },
14713 { 0x00000100, 0x00201811, 0x000 },
14714 { 0x00000008, 0x00621e28, 0x12f },
14715 { 0x00000008, 0x00822228, 0x000 },
14716 { 0x0002c000, 0x00204411, 0x000 },
14717 { 0x00000015, 0x00600e2d, 0x1bd },
14718 { 0x00000016, 0x00600e2d, 0x1bd },
14719 { 0x0000c008, 0x00204411, 0x000 },
14720 { 0x00000017, 0x00200e2d, 0x000 },
14721 { 0x00000000, 0x14c00000, 0x1b9 },
14722 { 0x00000000, 0x00200411, 0x000 },
14723 { 0x00000000, 0x00204801, 0x000 },
14724 { 0x39000000, 0x00204811, 0x000 },
14725 { 0x00000000, 0x00204811, 0x000 },
14726 { 0x00000000, 0x00804802, 0x000 },
14727 { 0x00000018, 0x00202e2d, 0x000 },
14728 { 0x00000000, 0x003b0d63, 0x000 },
14729 { 0x00000008, 0x00224a23, 0x000 },
14730 { 0x00000010, 0x00224a23, 0x000 },
14731 { 0x00000018, 0x00224a23, 0x000 },
14732 { 0x00000000, 0x00804803, 0x000 },
14733 { 0x00000000, 0x00600000, 0x00b },
14734 { 0x00001000, 0x00600411, 0x315 },
14735 { 0x00000000, 0x00200411, 0x000 },
14736 { 0x00000000, 0x00600811, 0x1b2 },
14737 { 0x00000007, 0x0021062f, 0x000 },
14738 { 0x00000013, 0x00200a2d, 0x000 },
14739 { 0x00000001, 0x00202c11, 0x000 },
14740 { 0x0000ffff, 0x40282220, 0x000 },
14741 { 0x0000000f, 0x00262228, 0x000 },
14742 { 0x00000010, 0x40212620, 0x000 },
14743 { 0x0000000f, 0x00262629, 0x000 },
14744 { 0x00000000, 0x00202802, 0x000 },
14745 { 0x00002256, 0x00204411, 0x000 },
14746 { 0x0000001b, 0x00204811, 0x000 },
14747 { 0x00000000, 0x002f0221, 0x000 },
14748 { 0x00000000, 0x0ce00000, 0x1e0 },
14749 { 0x0000225c, 0x00204411, 0x000 },
14750 { 0x00000081, 0x00204811, 0x000 },
14751 { 0x0000a1fc, 0x00204411, 0x000 },
14752 { 0x00000001, 0x00204811, 0x000 },
14753 { 0x00000080, 0x00201c11, 0x000 },
14754 { 0x00000000, 0x002f0227, 0x000 },
14755 { 0x00000000, 0x0ce00000, 0x1dc },
14756 { 0x00000000, 0x00600000, 0x1e9 },
14757 { 0x00000001, 0x00531e27, 0x1d8 },
14758 { 0x00000001, 0x00202c11, 0x000 },
14759 { 0x0000001f, 0x00280a22, 0x000 },
14760 { 0x0000001f, 0x00282a2a, 0x000 },
14761 { 0x00000001, 0x00530621, 0x1d1 },
14762 { 0x0000225c, 0x00204411, 0x000 },
14763 { 0x00000002, 0x00304a2f, 0x000 },
14764 { 0x0000a1fc, 0x00204411, 0x000 },
14765 { 0x00000001, 0x00204811, 0x000 },
14766 { 0x00000001, 0x00301e2f, 0x000 },
14767 { 0x00000000, 0x002f0227, 0x000 },
14768 { 0x00000000, 0x0ce00000, 0x000 },
14769 { 0x00000000, 0x00600000, 0x1e9 },
14770 { 0x00000001, 0x00531e27, 0x1e5 },
14771 { 0x0000ffff, 0x40280e20, 0x000 },
14772 { 0x0000000f, 0x00260e23, 0x000 },
14773 { 0x00000010, 0xc0211220, 0x000 },
14774 { 0x0000000f, 0x00261224, 0x000 },
14775 { 0x00000000, 0x00201411, 0x000 },
14776 { 0x00000000, 0x00601811, 0x2bb },
14777 { 0x0001a1fd, 0x00204411, 0x000 },
14778 { 0x00000000, 0x002f022b, 0x000 },
14779 { 0x00000000, 0x0ce00000, 0x1f8 },
14780 { 0x00000010, 0x00221628, 0x000 },
14781 { 0xffff0000, 0x00281625, 0x000 },
14782 { 0x0000ffff, 0x00281a29, 0x000 },
14783 { 0x00000000, 0x002948c5, 0x000 },
14784 { 0x00000000, 0x0020480a, 0x000 },
14785 { 0x00000000, 0x00202c11, 0x000 },
14786 { 0x00000010, 0x00221623, 0x000 },
14787 { 0xffff0000, 0x00281625, 0x000 },
14788 { 0x0000ffff, 0x00281a24, 0x000 },
14789 { 0x00000000, 0x002948c5, 0x000 },
14790 { 0x00000000, 0x00731503, 0x205 },
14791 { 0x00000000, 0x00201805, 0x000 },
14792 { 0x00000000, 0x00731524, 0x205 },
14793 { 0x00000000, 0x002d14c5, 0x000 },
14794 { 0x00000000, 0x003008a2, 0x000 },
14795 { 0x00000000, 0x00204802, 0x000 },
14796 { 0x00000000, 0x00202802, 0x000 },
14797 { 0x00000000, 0x00202003, 0x000 },
14798 { 0x00000000, 0x00802404, 0x000 },
14799 { 0x0000000f, 0x00210225, 0x000 },
14800 { 0x00000000, 0x14c00000, 0x621 },
14801 { 0x00000000, 0x002b1405, 0x000 },
14802 { 0x00000001, 0x00901625, 0x000 },
14803 { 0x00000000, 0x00600000, 0x00b },
14804 { 0x00000000, 0x00600411, 0x315 },
14805 { 0x00000000, 0x00200411, 0x000 },
14806 { 0x00000000, 0x00600811, 0x1b2 },
14807 { 0x00002256, 0x00204411, 0x000 },
14808 { 0x0000001a, 0x00294a22, 0x000 },
14809 { 0x00000000, 0xc0200000, 0x000 },
14810 { 0x00003fff, 0x002f022f, 0x000 },
14811 { 0x00000000, 0x0ce00000, 0x000 },
14812 { 0x00000000, 0xc0200400, 0x000 },
14813 { 0x0000225c, 0x00204411, 0x000 },
14814 { 0x00000003, 0x00384a21, 0x000 },
14815 { 0x0000a1fc, 0x00204411, 0x000 },
14816 { 0x00000001, 0x00204811, 0x000 },
14817 { 0x0000ffff, 0x40281220, 0x000 },
14818 { 0x00000010, 0xc0211a20, 0x000 },
14819 { 0x0000ffff, 0x40280e20, 0x000 },
14820 { 0x00000010, 0xc0211620, 0x000 },
14821 { 0x00000000, 0x00741465, 0x2bb },
14822 { 0x0001a1fd, 0x00604411, 0x2e0 },
14823 { 0x00000001, 0x00330621, 0x000 },
14824 { 0x00000000, 0x002f0221, 0x000 },
14825 { 0x00000000, 0x0cc00000, 0x219 },
14826 { 0x00003fff, 0x002f022f, 0x000 },
14827 { 0x00000000, 0x0cc00000, 0x212 },
14828 { 0x00000000, 0xc0400400, 0x001 },
14829 { 0x00000000, 0x00600000, 0x5de },
14830 { 0x00000000, 0x0040040f, 0x213 },
14831 { 0x00000000, 0x00600000, 0x5d1 },
14832 { 0x00000000, 0x00600000, 0x5de },
14833 { 0x00000210, 0x00600411, 0x315 },
14834 { 0x00000000, 0x00600000, 0x1a0 },
14835 { 0x00000000, 0x00600000, 0x19c },
14836 { 0x00000000, 0x00600000, 0x2bb },
14837 { 0x00000000, 0x00600000, 0x2a3 },
14838 { 0x93800000, 0x00204411, 0x000 },
14839 { 0x00000000, 0x00204808, 0x000 },
14840 { 0x00000000, 0x002f022f, 0x000 },
14841 { 0x00000000, 0x0ae00000, 0x232 },
14842 { 0x00000000, 0x00600000, 0x13a },
14843 { 0x00000000, 0x00400000, 0x236 },
14844 { 0x95000000, 0x00204411, 0x000 },
14845 { 0x00000000, 0x002f022f, 0x000 },
14846 { 0x00000000, 0x0ce00000, 0x236 },
14847 { 0x00000000, 0xc0404800, 0x233 },
14848 { 0x92000000, 0x00204411, 0x000 },
14849 { 0x00000000, 0xc0204800, 0x000 },
14850 { 0x00002256, 0x00204411, 0x000 },
14851 { 0x00000016, 0x00204811, 0x000 },
14852 { 0x0000225c, 0x00204411, 0x000 },
14853 { 0x00000003, 0x00204811, 0x000 },
14854 { 0x0000a1fc, 0x00204411, 0x000 },
14855 { 0x00000001, 0x00204811, 0x000 },
14856 { 0x0001a1fd, 0x00204411, 0x000 },
14857 { 0x00000000, 0x00600411, 0x2fb },
14858 { 0x00000000, 0xc0400400, 0x001 },
14859 { 0x00000000, 0x00600000, 0x5d1 },
14860 { 0x0000a00c, 0x00204411, 0x000 },
14861 { 0x00000000, 0xc0204800, 0x000 },
14862 { 0x00000000, 0xc0404800, 0x000 },
14863 { 0x00000000, 0x00600000, 0x00b },
14864 { 0x00000018, 0x40210a20, 0x000 },
14865 { 0x00000003, 0x002f0222, 0x000 },
14866 { 0x00000000, 0x0ae00000, 0x24c },
14867 { 0x00000014, 0x0020222d, 0x000 },
14868 { 0x00080101, 0x00292228, 0x000 },
14869 { 0x00000014, 0x00203628, 0x000 },
14870 { 0x0000a30c, 0x00204411, 0x000 },
14871 { 0x00000000, 0xc0204800, 0x000 },
14872 { 0x00000000, 0xc0204800, 0x000 },
14873 { 0x00000000, 0xc0404800, 0x251 },
14874 { 0x00000000, 0x00600000, 0x00b },
14875 { 0x00000010, 0x00600411, 0x315 },
14876 { 0x3f800000, 0x00200411, 0x000 },
14877 { 0x00000000, 0x00600811, 0x1b2 },
14878 { 0x0000225c, 0x00204411, 0x000 },
14879 { 0x00000003, 0x00204811, 0x000 },
14880 { 0x00000000, 0x00600000, 0x27c },
14881 { 0x00000017, 0x00201e2d, 0x000 },
14882 { 0x00000001, 0x00211e27, 0x000 },
14883 { 0x00000000, 0x14e00000, 0x26a },
14884 { 0x00000012, 0x00201e2d, 0x000 },
14885 { 0x0000ffff, 0x00281e27, 0x000 },
14886 { 0x00000000, 0x00341c27, 0x000 },
14887 { 0x00000000, 0x12c00000, 0x25f },
14888 { 0x00000000, 0x00201c11, 0x000 },
14889 { 0x00000000, 0x002f00e5, 0x000 },
14890 { 0x00000000, 0x08c00000, 0x262 },
14891 { 0x00000000, 0x00201407, 0x000 },
14892 { 0x00000012, 0x00201e2d, 0x000 },
14893 { 0x00000010, 0x00211e27, 0x000 },
14894 { 0x00000000, 0x00341c47, 0x000 },
14895 { 0x00000000, 0x12c00000, 0x267 },
14896 { 0x00000000, 0x00201c11, 0x000 },
14897 { 0x00000000, 0x002f00e6, 0x000 },
14898 { 0x00000000, 0x08c00000, 0x26a },
14899 { 0x00000000, 0x00201807, 0x000 },
14900 { 0x00000000, 0x00600000, 0x2c1 },
14901 { 0x00002256, 0x00204411, 0x000 },
14902 { 0x00000000, 0x00342023, 0x000 },
14903 { 0x00000000, 0x12c00000, 0x272 },
14904 { 0x00000000, 0x00342044, 0x000 },
14905 { 0x00000000, 0x12c00000, 0x271 },
14906 { 0x00000016, 0x00404811, 0x276 },
14907 { 0x00000018, 0x00404811, 0x276 },
14908 { 0x00000000, 0x00342044, 0x000 },
14909 { 0x00000000, 0x12c00000, 0x275 },
14910 { 0x00000017, 0x00404811, 0x276 },
14911 { 0x00000019, 0x00204811, 0x000 },
14912 { 0x0000a1fc, 0x00204411, 0x000 },
14913 { 0x00000001, 0x00204811, 0x000 },
14914 { 0x0001a1fd, 0x00604411, 0x2e9 },
14915 { 0x00003fff, 0x002f022f, 0x000 },
14916 { 0x00000000, 0x0cc00000, 0x256 },
14917 { 0x00000000, 0xc0400400, 0x001 },
14918 { 0x00000010, 0x40210620, 0x000 },
14919 { 0x0000ffff, 0xc0280a20, 0x000 },
14920 { 0x00000010, 0x40210e20, 0x000 },
14921 { 0x0000ffff, 0xc0281220, 0x000 },
14922 { 0x00000010, 0x40211620, 0x000 },
14923 { 0x0000ffff, 0xc0881a20, 0x000 },
14924 { 0x81000000, 0x00204411, 0x000 },
14925 { 0x00000001, 0x00204811, 0x000 },
14926 { 0x00042004, 0x00604411, 0x622 },
14927 { 0x00000000, 0x00600000, 0x5d1 },
14928 { 0x00000000, 0xc0600000, 0x2a3 },
14929 { 0x00000005, 0x00200a2d, 0x000 },
14930 { 0x00000008, 0x00220a22, 0x000 },
14931 { 0x0000002b, 0x00201a2d, 0x000 },
14932 { 0x0000001c, 0x00201e2d, 0x000 },
14933 { 0x00007000, 0x00281e27, 0x000 },
14934 { 0x00000000, 0x00311ce6, 0x000 },
14935 { 0x0000002a, 0x00201a2d, 0x000 },
14936 { 0x0000000c, 0x00221a26, 0x000 },
14937 { 0x00000000, 0x002f00e6, 0x000 },
14938 { 0x00000000, 0x06e00000, 0x292 },
14939 { 0x00000000, 0x00201c11, 0x000 },
14940 { 0x00000000, 0x00200c11, 0x000 },
14941 { 0x0000002b, 0x00203623, 0x000 },
14942 { 0x00000010, 0x00201811, 0x000 },
14943 { 0x00000000, 0x00691ce2, 0x12f },
14944 { 0x93800000, 0x00204411, 0x000 },
14945 { 0x00000000, 0x00204807, 0x000 },
14946 { 0x95000000, 0x00204411, 0x000 },
14947 { 0x00000000, 0x002f022f, 0x000 },
14948 { 0x00000000, 0x0ce00000, 0x29d },
14949 { 0x00000001, 0x00333e2f, 0x000 },
14950 { 0x00000000, 0xd9004800, 0x000 },
14951 { 0x92000000, 0x00204411, 0x000 },
14952 { 0x00000000, 0xc0204800, 0x000 },
14953 { 0x0000001c, 0x00403627, 0x000 },
14954 { 0x0000000c, 0xc0220a20, 0x000 },
14955 { 0x00000029, 0x00203622, 0x000 },
14956 { 0x00000028, 0xc0403620, 0x000 },
14957 { 0x0000a2a4, 0x00204411, 0x000 },
14958 { 0x00000009, 0x00204811, 0x000 },
14959 { 0xa1000000, 0x00204411, 0x000 },
14960 { 0x00000001, 0x00804811, 0x000 },
14961 { 0x00000021, 0x00201e2d, 0x000 },
14962 { 0x00000000, 0x002c1ce3, 0x000 },
14963 { 0x00000021, 0x00203627, 0x000 },
14964 { 0x00000022, 0x00201e2d, 0x000 },
14965 { 0x00000000, 0x002c1ce4, 0x000 },
14966 { 0x00000022, 0x00203627, 0x000 },
14967 { 0x00000023, 0x00201e2d, 0x000 },
14968 { 0x00000000, 0x003120a3, 0x000 },
14969 { 0x00000000, 0x002d1d07, 0x000 },
14970 { 0x00000023, 0x00203627, 0x000 },
14971 { 0x00000024, 0x00201e2d, 0x000 },
14972 { 0x00000000, 0x003120c4, 0x000 },
14973 { 0x00000000, 0x002d1d07, 0x000 },
14974 { 0x00000024, 0x00803627, 0x000 },
14975 { 0x00000021, 0x00203623, 0x000 },
14976 { 0x00000022, 0x00203624, 0x000 },
14977 { 0x00000000, 0x00311ca3, 0x000 },
14978 { 0x00000023, 0x00203627, 0x000 },
14979 { 0x00000000, 0x00311cc4, 0x000 },
14980 { 0x00000024, 0x00803627, 0x000 },
14981 { 0x0000001a, 0x00203627, 0x000 },
14982 { 0x0000001b, 0x00203628, 0x000 },
14983 { 0x00000017, 0x00201e2d, 0x000 },
14984 { 0x00000002, 0x00210227, 0x000 },
14985 { 0x00000000, 0x14c00000, 0x2dc },
14986 { 0x00000000, 0x00400000, 0x2d9 },
14987 { 0x0000001a, 0x00203627, 0x000 },
14988 { 0x0000001b, 0x00203628, 0x000 },
14989 { 0x00000017, 0x00201e2d, 0x000 },
14990 { 0x00000002, 0x00210227, 0x000 },
14991 { 0x00000000, 0x14e00000, 0x2d9 },
14992 { 0x00000003, 0x00210227, 0x000 },
14993 { 0x00000000, 0x14e00000, 0x2dc },
14994 { 0x00000023, 0x00201e2d, 0x000 },
14995 { 0x00000000, 0x002e00e1, 0x000 },
14996 { 0x00000000, 0x02c00000, 0x2dc },
14997 { 0x00000021, 0x00201e2d, 0x000 },
14998 { 0x00000000, 0x003120a1, 0x000 },
14999 { 0x00000000, 0x002e00e8, 0x000 },
15000 { 0x00000000, 0x06c00000, 0x2dc },
15001 { 0x00000024, 0x00201e2d, 0x000 },
15002 { 0x00000000, 0x002e00e2, 0x000 },
15003 { 0x00000000, 0x02c00000, 0x2dc },
15004 { 0x00000022, 0x00201e2d, 0x000 },
15005 { 0x00000000, 0x003120c2, 0x000 },
15006 { 0x00000000, 0x002e00e8, 0x000 },
15007 { 0x00000000, 0x06c00000, 0x2dc },
15008 { 0x00000000, 0x00600000, 0x5ff },
15009 { 0x00000000, 0x00600000, 0x2b5 },
15010 { 0x00000000, 0x00400000, 0x2de },
15011 { 0x00000000, 0x00600000, 0x2b5 },
15012 { 0x00000000, 0x00600000, 0x5f6 },
15013 { 0x00000000, 0x00400000, 0x2de },
15014 { 0x00000000, 0x00600000, 0x2a7 },
15015 { 0x00000000, 0x00400000, 0x2de },
15016 { 0x0000001a, 0x00201e2d, 0x000 },
15017 { 0x0000001b, 0x0080222d, 0x000 },
15018 { 0x00000010, 0x00221e23, 0x000 },
15019 { 0x00000000, 0x00294887, 0x000 },
15020 { 0x00000000, 0x00311ca3, 0x000 },
15021 { 0x00000010, 0x00221e27, 0x000 },
15022 { 0x00000000, 0x00294887, 0x000 },
15023 { 0x00000010, 0x00221e23, 0x000 },
15024 { 0x00000000, 0x003120c4, 0x000 },
15025 { 0x0000ffff, 0x00282228, 0x000 },
15026 { 0x00000000, 0x00894907, 0x000 },
15027 { 0x00000010, 0x00221e23, 0x000 },
15028 { 0x00000000, 0x00294887, 0x000 },
15029 { 0x00000010, 0x00221e21, 0x000 },
15030 { 0x00000000, 0x00294847, 0x000 },
15031 { 0x00000000, 0x00311ca3, 0x000 },
15032 { 0x00000010, 0x00221e27, 0x000 },
15033 { 0x00000000, 0x00294887, 0x000 },
15034 { 0x00000000, 0x00311ca1, 0x000 },
15035 { 0x00000010, 0x00221e27, 0x000 },
15036 { 0x00000000, 0x00294847, 0x000 },
15037 { 0x00000010, 0x00221e23, 0x000 },
15038 { 0x00000000, 0x003120c4, 0x000 },
15039 { 0x0000ffff, 0x00282228, 0x000 },
15040 { 0x00000000, 0x00294907, 0x000 },
15041 { 0x00000010, 0x00221e21, 0x000 },
15042 { 0x00000000, 0x003120c2, 0x000 },
15043 { 0x0000ffff, 0x00282228, 0x000 },
15044 { 0x00000000, 0x00894907, 0x000 },
15045 { 0x00000010, 0x00221e23, 0x000 },
15046 { 0x00000000, 0x00294887, 0x000 },
15047 { 0x00000001, 0x00220a21, 0x000 },
15048 { 0x00000000, 0x003308a2, 0x000 },
15049 { 0x00000010, 0x00221e22, 0x000 },
15050 { 0x00000010, 0x00212222, 0x000 },
15051 { 0x00000000, 0x00294907, 0x000 },
15052 { 0x00000000, 0x00311ca3, 0x000 },
15053 { 0x00000010, 0x00221e27, 0x000 },
15054 { 0x00000000, 0x00294887, 0x000 },
15055 { 0x00000001, 0x00220a21, 0x000 },
15056 { 0x00000000, 0x003008a2, 0x000 },
15057 { 0x00000010, 0x00221e22, 0x000 },
15058 { 0x00000010, 0x00212222, 0x000 },
15059 { 0x00000000, 0x00294907, 0x000 },
15060 { 0x00000010, 0x00221e23, 0x000 },
15061 { 0x00000000, 0x003120c4, 0x000 },
15062 { 0x0000ffff, 0x00282228, 0x000 },
15063 { 0x00000000, 0x00294907, 0x000 },
15064 { 0x00000000, 0x003808c5, 0x000 },
15065 { 0x00000000, 0x00300841, 0x000 },
15066 { 0x00000001, 0x00220a22, 0x000 },
15067 { 0x00000000, 0x003308a2, 0x000 },
15068 { 0x00000010, 0x00221e22, 0x000 },
15069 { 0x00000010, 0x00212222, 0x000 },
15070 { 0x00000000, 0x00894907, 0x000 },
15071 { 0x00000017, 0x0020222d, 0x000 },
15072 { 0x00000000, 0x14c00000, 0x318 },
15073 { 0xffffffef, 0x00280621, 0x000 },
15074 { 0x00000014, 0x0020222d, 0x000 },
15075 { 0x0000f8e0, 0x00204411, 0x000 },
15076 { 0x00000000, 0x00294901, 0x000 },
15077 { 0x00000000, 0x00894901, 0x000 },
15078 { 0x00000000, 0x00204811, 0x000 },
15079 { 0x00000000, 0x00204811, 0x000 },
15080 { 0x060a0200, 0x00804811, 0x000 },
15081 { 0x00000000, 0xc0200000, 0x000 },
15082 { 0x97000000, 0xc0204411, 0x000 },
15083 { 0x00000000, 0xc0204811, 0x000 },
15084 { 0x8a000000, 0x00204411, 0x000 },
15085 { 0x00000000, 0x00204811, 0x000 },
15086 { 0x0000225c, 0x00204411, 0x000 },
15087 { 0x00000000, 0xc0204800, 0x000 },
15088 { 0x0000a1fc, 0x00204411, 0x000 },
15089 { 0x00000000, 0xc0204800, 0x000 },
15090 { 0x00000000, 0xc0200400, 0x000 },
15091 { 0x00000000, 0x00a0000a, 0x000 },
15092 { 0x97000000, 0xc0204411, 0x000 },
15093 { 0x00000000, 0xc0204811, 0x000 },
15094 { 0x8a000000, 0xc0204411, 0x000 },
15095 { 0x00000000, 0x00204811, 0x000 },
15096 { 0x0000225c, 0x00204411, 0x000 },
15097 { 0x00000000, 0xc0204800, 0x000 },
15098 { 0x0000a1fc, 0x00204411, 0x000 },
15099 { 0x00000000, 0xc0204800, 0x000 },
15100 { 0x00000000, 0xc0200400, 0x000 },
15101 { 0x00000000, 0x00a0000a, 0x000 },
15102 { 0x97000000, 0x00204411, 0x000 },
15103 { 0x00000000, 0x00204811, 0x000 },
15104 { 0x8a000000, 0x00204411, 0x000 },
15105 { 0x00000000, 0x00204811, 0x000 },
15106 { 0x0000225c, 0x00204411, 0x000 },
15107 { 0x00000000, 0xc0204800, 0x000 },
15108 { 0x0000a1fc, 0x00204411, 0x000 },
15109 { 0x00000000, 0xc0204800, 0x000 },
15110 { 0x00000000, 0xc0200400, 0x000 },
15111 { 0x00000000, 0x00a0000a, 0x000 },
15112 { 0x97000000, 0x00204411, 0x000 },
15113 { 0x00000000, 0x00204811, 0x000 },
15114 { 0x8a000000, 0x00204411, 0x000 },
15115 { 0x00000000, 0x00204811, 0x000 },
15116 { 0x0000225c, 0x00204411, 0x000 },
15117 { 0x00000000, 0xc0204800, 0x000 },
15118 { 0x0000a1fc, 0x00204411, 0x000 },
15119 { 0x00000000, 0xc0204800, 0x000 },
15120 { 0x0001a1fd, 0x00204411, 0x000 },
15121 { 0x00000000, 0xd9004800, 0x000 },
15122 { 0x00000000, 0xc0200400, 0x000 },
15123 { 0x00000000, 0x00a0000a, 0x000 },
15124 { 0x00002257, 0x00204411, 0x000 },
15125 { 0x00000003, 0xc0484a20, 0x000 },
15126 { 0x0000225d, 0x00204411, 0x000 },
15127 { 0x00000000, 0xc0404800, 0x000 },
15128 { 0x00000000, 0x00600000, 0x5de },
15129 { 0x00000000, 0xc0200800, 0x000 },
15130 { 0x0000225c, 0x00204411, 0x000 },
15131 { 0x00000003, 0x00384a22, 0x000 },
15132 { 0x0000a1fc, 0x00204411, 0x000 },
15133 { 0x00000000, 0xc0204800, 0x000 },
15134 { 0x0001a1fd, 0x00204411, 0x000 },
15135 { 0x00000000, 0x002f0222, 0x000 },
15136 { 0x00000000, 0x0ce00000, 0x000 },
15137 { 0x00000000, 0x40204800, 0x000 },
15138 { 0x00000001, 0x40304a20, 0x000 },
15139 { 0x00000002, 0xc0304a20, 0x000 },
15140 { 0x00000001, 0x00530a22, 0x355 },
15141 { 0x0000003f, 0xc0280a20, 0x000 },
15142 { 0x81000000, 0x00204411, 0x000 },
15143 { 0x00000001, 0x00204811, 0x000 },
15144 { 0x000021f8, 0x00204411, 0x000 },
15145 { 0x00000018, 0x00204811, 0x000 },
15146 { 0x000421f9, 0x00604411, 0x622 },
15147 { 0x00000011, 0x00210230, 0x000 },
15148 { 0x00000000, 0x14e00000, 0x35e },
15149 { 0x00000014, 0x002f0222, 0x000 },
15150 { 0x00000000, 0x0cc00000, 0x36c },
15151 { 0x0001a2a4, 0x00204411, 0x000 },
15152 { 0x00000000, 0x00604802, 0x374 },
15153 { 0x00002100, 0x00204411, 0x000 },
15154 { 0x00000000, 0xc0204800, 0x000 },
15155 { 0x00000000, 0xc0204800, 0x000 },
15156 { 0x00000000, 0xc0204800, 0x000 },
15157 { 0x00000000, 0xc0404800, 0x000 },
15158 { 0x00000004, 0x002f0222, 0x000 },
15159 { 0x00000000, 0x0cc00000, 0x370 },
15160 { 0x0001a2a4, 0x00204411, 0x000 },
15161 { 0x00000000, 0x00404802, 0x367 },
15162 { 0x00000028, 0x002f0222, 0x000 },
15163 { 0x00000000, 0x0cc00000, 0x5ba },
15164 { 0x0001a2a4, 0x00204411, 0x000 },
15165 { 0x00000000, 0x00404802, 0x367 },
15166 { 0x0000002c, 0x00203626, 0x000 },
15167 { 0x00000049, 0x00201811, 0x000 },
15168 { 0x0000003f, 0x00204811, 0x000 },
15169 { 0x00000001, 0x00331a26, 0x000 },
15170 { 0x00000000, 0x002f0226, 0x000 },
15171 { 0x00000000, 0x0cc00000, 0x376 },
15172 { 0x0000002c, 0x00801a2d, 0x000 },
15173 { 0x0000003f, 0xc0280a20, 0x000 },
15174 { 0x00000015, 0x002f0222, 0x000 },
15175 { 0x00000000, 0x0ce00000, 0x38c },
15176 { 0x00000006, 0x002f0222, 0x000 },
15177 { 0x00000000, 0x0ce00000, 0x3b7 },
15178 { 0x00000016, 0x002f0222, 0x000 },
15179 { 0x00000000, 0x0ce00000, 0x3b9 },
15180 { 0x00000020, 0x002f0222, 0x000 },
15181 { 0x00000000, 0x0ce00000, 0x3a2 },
15182 { 0x0000000f, 0x002f0222, 0x000 },
15183 { 0x00000000, 0x0ce00000, 0x3ae },
15184 { 0x00000010, 0x002f0222, 0x000 },
15185 { 0x00000000, 0x0ce00000, 0x3ae },
15186 { 0x0000001e, 0x002f0222, 0x000 },
15187 { 0x00000000, 0x0ce00000, 0x396 },
15188 { 0x0000a2a4, 0x00204411, 0x000 },
15189 { 0x00000000, 0x00404802, 0x000 },
15190 { 0x08000000, 0x00290a22, 0x000 },
15191 { 0x00000003, 0x40210e20, 0x000 },
15192 { 0x0000000c, 0xc0211220, 0x000 },
15193 { 0x00080000, 0x00281224, 0x000 },
15194 { 0x00000014, 0xc0221620, 0x000 },
15195 { 0x00000000, 0x002914a4, 0x000 },
15196 { 0x0000a2a4, 0x00204411, 0x000 },
15197 { 0x00000000, 0x002948a2, 0x000 },
15198 { 0x0000a1fe, 0x00204411, 0x000 },
15199 { 0x00000000, 0x00404803, 0x000 },
15200 { 0x81000000, 0x00204411, 0x000 },
15201 { 0x00000001, 0x00204811, 0x000 },
15202 { 0x000021f8, 0x00204411, 0x000 },
15203 { 0x00000016, 0x00204811, 0x000 },
15204 { 0x000421f9, 0x00604411, 0x622 },
15205 { 0x00000015, 0x00210230, 0x000 },
15206 { 0x00000000, 0x14e00000, 0x398 },
15207 { 0x0000210e, 0x00204411, 0x000 },
15208 { 0x00000000, 0xc0204800, 0x000 },
15209 { 0x00000000, 0xc0204800, 0x000 },
15210 { 0x0000a2a4, 0x00204411, 0x000 },
15211 { 0x00000000, 0x00404802, 0x000 },
15212 { 0x81000000, 0x00204411, 0x000 },
15213 { 0x00000001, 0x00204811, 0x000 },
15214 { 0x000021f8, 0x00204411, 0x000 },
15215 { 0x00000017, 0x00204811, 0x000 },
15216 { 0x000421f9, 0x00604411, 0x622 },
15217 { 0x00000003, 0x00210230, 0x000 },
15218 { 0x00000000, 0x14e00000, 0x3a4 },
15219 { 0x00002108, 0x00204411, 0x000 },
15220 { 0x00000000, 0xc0204800, 0x000 },
15221 { 0x00000000, 0xc0204800, 0x000 },
15222 { 0x0000a2a4, 0x00204411, 0x000 },
15223 { 0x00000000, 0x00404802, 0x000 },
15224 { 0x0000a2a4, 0x00204411, 0x000 },
15225 { 0x00000000, 0x00204802, 0x000 },
15226 { 0x80000000, 0x00204411, 0x000 },
15227 { 0x00000000, 0x00204811, 0x000 },
15228 { 0x81000000, 0x00204411, 0x000 },
15229 { 0x00000010, 0x00204811, 0x000 },
15230 { 0x00000000, 0x00200010, 0x000 },
15231 { 0x00000000, 0x14c00000, 0x3b4 },
15232 { 0x00000000, 0x00400000, 0x000 },
15233 { 0x0001a2a4, 0x00204411, 0x000 },
15234 { 0x00000006, 0x00404811, 0x000 },
15235 { 0x0001a2a4, 0x00204411, 0x000 },
15236 { 0x00000016, 0x00604811, 0x374 },
15237 { 0x00000000, 0x00400000, 0x000 },
15238 { 0x00000000, 0xc0200800, 0x000 },
15239 { 0x00000000, 0xc0200c00, 0x000 },
15240 { 0x0000001d, 0x00210223, 0x000 },
15241 { 0x00000000, 0x14e00000, 0x3ce },
15242 { 0x81000000, 0x00204411, 0x000 },
15243 { 0x00000001, 0x00204811, 0x000 },
15244 { 0x000021f8, 0x00204411, 0x000 },
15245 { 0x00000018, 0x00204811, 0x000 },
15246 { 0x000421f9, 0x00604411, 0x622 },
15247 { 0x00000011, 0x00210230, 0x000 },
15248 { 0x00000000, 0x14e00000, 0x3c2 },
15249 { 0x00002100, 0x00204411, 0x000 },
15250 { 0x00000000, 0x00204802, 0x000 },
15251 { 0x00000000, 0x00204803, 0x000 },
15252 { 0xbabecafe, 0x00204811, 0x000 },
15253 { 0xcafebabe, 0x00204811, 0x000 },
15254 { 0x0000a2a4, 0x00204411, 0x000 },
15255 { 0x00000004, 0x00404811, 0x000 },
15256 { 0x00002170, 0x00204411, 0x000 },
15257 { 0x00000000, 0x00204802, 0x000 },
15258 { 0x00000000, 0x00204803, 0x000 },
15259 { 0x81000000, 0x00204411, 0x000 },
15260 { 0x0000000a, 0x00204811, 0x000 },
15261 { 0x00000000, 0x00200010, 0x000 },
15262 { 0x00000000, 0x14c00000, 0x3d3 },
15263 { 0x8c000000, 0x00204411, 0x000 },
15264 { 0xcafebabe, 0x00404811, 0x000 },
15265 { 0x81000000, 0x00204411, 0x000 },
15266 { 0x00000001, 0x00204811, 0x000 },
15267 { 0x00003fff, 0x40280a20, 0x000 },
15268 { 0x80000000, 0x40280e20, 0x000 },
15269 { 0x40000000, 0xc0281220, 0x000 },
15270 { 0x00040000, 0x00694622, 0x622 },
15271 { 0x00000000, 0x00201410, 0x000 },
15272 { 0x00000000, 0x002f0223, 0x000 },
15273 { 0x00000000, 0x0cc00000, 0x3e1 },
15274 { 0x00000000, 0xc0401800, 0x3e4 },
15275 { 0x00003fff, 0xc0281a20, 0x000 },
15276 { 0x00040000, 0x00694626, 0x622 },
15277 { 0x00000000, 0x00201810, 0x000 },
15278 { 0x00000000, 0x002f0224, 0x000 },
15279 { 0x00000000, 0x0cc00000, 0x3e7 },
15280 { 0x00000000, 0xc0401c00, 0x3ea },
15281 { 0x00003fff, 0xc0281e20, 0x000 },
15282 { 0x00040000, 0x00694627, 0x622 },
15283 { 0x00000000, 0x00201c10, 0x000 },
15284 { 0x00000000, 0x00204402, 0x000 },
15285 { 0x00000000, 0x002820c5, 0x000 },
15286 { 0x00000000, 0x004948e8, 0x000 },
15287 { 0xa5800000, 0x00200811, 0x000 },
15288 { 0x00002000, 0x00200c11, 0x000 },
15289 { 0x83000000, 0x00604411, 0x412 },
15290 { 0x00000000, 0x00204402, 0x000 },
15291 { 0x00000000, 0xc0204800, 0x000 },
15292 { 0x00000000, 0x40204800, 0x000 },
15293 { 0x0000001f, 0xc0210220, 0x000 },
15294 { 0x00000000, 0x14c00000, 0x3f7 },
15295 { 0x00002010, 0x00204411, 0x000 },
15296 { 0x00008000, 0x00204811, 0x000 },
15297 { 0x0000ffff, 0xc0481220, 0x3ff },
15298 { 0xa7800000, 0x00200811, 0x000 },
15299 { 0x0000a000, 0x00200c11, 0x000 },
15300 { 0x83000000, 0x00604411, 0x412 },
15301 { 0x00000000, 0x00204402, 0x000 },
15302 { 0x00000000, 0xc0204800, 0x000 },
15303 { 0x00000000, 0xc0204800, 0x000 },
15304 { 0x0000ffff, 0xc0281220, 0x000 },
15305 { 0x83000000, 0x00204411, 0x000 },
15306 { 0x00000000, 0x00304883, 0x000 },
15307 { 0x84000000, 0x00204411, 0x000 },
15308 { 0x00000000, 0xc0204800, 0x000 },
15309 { 0x00000000, 0x1d000000, 0x000 },
15310 { 0x83000000, 0x00604411, 0x412 },
15311 { 0x00000000, 0xc0400400, 0x001 },
15312 { 0xa9800000, 0x00200811, 0x000 },
15313 { 0x0000c000, 0x00400c11, 0x3fa },
15314 { 0xab800000, 0x00200811, 0x000 },
15315 { 0x0000f8e0, 0x00400c11, 0x3fa },
15316 { 0xad800000, 0x00200811, 0x000 },
15317 { 0x0000f880, 0x00400c11, 0x3fa },
15318 { 0xb3800000, 0x00200811, 0x000 },
15319 { 0x0000f3fc, 0x00400c11, 0x3fa },
15320 { 0xaf800000, 0x00200811, 0x000 },
15321 { 0x0000e000, 0x00400c11, 0x3fa },
15322 { 0xb1800000, 0x00200811, 0x000 },
15323 { 0x0000f000, 0x00400c11, 0x3fa },
15324 { 0x83000000, 0x00204411, 0x000 },
15325 { 0x00002148, 0x00204811, 0x000 },
15326 { 0x84000000, 0x00204411, 0x000 },
15327 { 0x00000000, 0xc0204800, 0x000 },
15328 { 0x00000000, 0x1d000000, 0x000 },
15329 { 0x00000000, 0x00800000, 0x000 },
15330 { 0x01182000, 0xc0304620, 0x000 },
15331 { 0x00000000, 0xd9004800, 0x000 },
15332 { 0x00000000, 0xc0200400, 0x000 },
15333 { 0x00000000, 0x00a0000a, 0x000 },
15334 { 0x0218a000, 0xc0304620, 0x000 },
15335 { 0x00000000, 0xd9004800, 0x000 },
15336 { 0x00000000, 0xc0200400, 0x000 },
15337 { 0x00000000, 0x00a0000a, 0x000 },
15338 { 0x0318c000, 0xc0304620, 0x000 },
15339 { 0x00000000, 0xd9004800, 0x000 },
15340 { 0x00000000, 0xc0200400, 0x000 },
15341 { 0x00000000, 0x00a0000a, 0x000 },
15342 { 0x0418f8e0, 0xc0304620, 0x000 },
15343 { 0x00000000, 0xd9004800, 0x000 },
15344 { 0x00000000, 0xc0200400, 0x000 },
15345 { 0x00000000, 0x00a0000a, 0x000 },
15346 { 0x0518f880, 0xc0304620, 0x000 },
15347 { 0x00000000, 0xd9004800, 0x000 },
15348 { 0x00000000, 0xc0200400, 0x000 },
15349 { 0x00000000, 0x00a0000a, 0x000 },
15350 { 0x0618e000, 0xc0304620, 0x000 },
15351 { 0x00000000, 0xd9004800, 0x000 },
15352 { 0x00000000, 0xc0200400, 0x000 },
15353 { 0x00000000, 0x00a0000a, 0x000 },
15354 { 0x0718f000, 0xc0304620, 0x000 },
15355 { 0x00000000, 0xd9004800, 0x000 },
15356 { 0x00000000, 0xc0200400, 0x000 },
15357 { 0x00000000, 0x00a0000a, 0x000 },
15358 { 0x0818f3fc, 0xc0304620, 0x000 },
15359 { 0x00000000, 0xd9004800, 0x000 },
15360 { 0x00000000, 0xc0200400, 0x000 },
15361 { 0x00000000, 0x00a0000a, 0x000 },
15362 { 0x00000033, 0xc0300a20, 0x000 },
15363 { 0x00000000, 0xc0403440, 0x000 },
15364 { 0x00000030, 0x00200a2d, 0x000 },
15365 { 0x00000000, 0xc0290c40, 0x000 },
15366 { 0x00000030, 0x00203623, 0x000 },
15367 { 0x00000000, 0xc0200400, 0x000 },
15368 { 0x00000000, 0x00a0000a, 0x000 },
15369 { 0x86000000, 0x00204411, 0x000 },
15370 { 0x00000000, 0x00404801, 0x000 },
15371 { 0x85000000, 0xc0204411, 0x000 },
15372 { 0x00000000, 0x00404801, 0x000 },
15373 { 0x0000217c, 0x00204411, 0x000 },
15374 { 0x00000018, 0x40210220, 0x000 },
15375 { 0x00000000, 0x14c00000, 0x447 },
15376 { 0x00800000, 0xc0494a20, 0x448 },
15377 { 0x00000000, 0xc0204800, 0x000 },
15378 { 0x00000000, 0xc0204800, 0x000 },
15379 { 0x00000000, 0xc0204800, 0x000 },
15380 { 0x81000000, 0x00204411, 0x000 },
15381 { 0x00000001, 0x00204811, 0x000 },
15382 { 0x00000000, 0xc0200800, 0x000 },
15383 { 0x00000004, 0x002f0222, 0x000 },
15384 { 0x00000000, 0x06e00000, 0x450 },
15385 { 0x00000004, 0x00200811, 0x000 },
15386 { 0x00000000, 0x17000000, 0x000 },
15387 { 0x0004217f, 0x00604411, 0x622 },
15388 { 0x0000001f, 0x00210230, 0x000 },
15389 { 0x00000000, 0x14c00000, 0x000 },
15390 { 0x00000000, 0x00404c02, 0x450 },
15391 { 0x00000000, 0xc0200c00, 0x000 },
15392 { 0x00000000, 0xc0201000, 0x000 },
15393 { 0x00000000, 0xc0201400, 0x000 },
15394 { 0x00000000, 0xc0201800, 0x000 },
15395 { 0x00000000, 0xc0201c00, 0x000 },
15396 { 0x00007f00, 0x00280a21, 0x000 },
15397 { 0x00004500, 0x002f0222, 0x000 },
15398 { 0x00000000, 0x0ce00000, 0x461 },
15399 { 0x00000000, 0xc0202000, 0x000 },
15400 { 0x00000004, 0x002f0228, 0x000 },
15401 { 0x00000000, 0x06e00000, 0x461 },
15402 { 0x00000004, 0x00202011, 0x000 },
15403 { 0x00000000, 0x17000000, 0x000 },
15404 { 0x00000010, 0x00280a23, 0x000 },
15405 { 0x00000010, 0x002f0222, 0x000 },
15406 { 0x00000000, 0x0ce00000, 0x469 },
15407 { 0x81000000, 0x00204411, 0x000 },
15408 { 0x00000001, 0x00204811, 0x000 },
15409 { 0x00040000, 0x00694624, 0x622 },
15410 { 0x00000000, 0x00400000, 0x46e },
15411 { 0x81000000, 0x00204411, 0x000 },
15412 { 0x00000000, 0x00204811, 0x000 },
15413 { 0x0000216d, 0x00204411, 0x000 },
15414 { 0x00000000, 0x00204804, 0x000 },
15415 { 0x00000000, 0x00604805, 0x627 },
15416 { 0x00000000, 0x002824f0, 0x000 },
15417 { 0x00000007, 0x00280a23, 0x000 },
15418 { 0x00000001, 0x002f0222, 0x000 },
15419 { 0x00000000, 0x0ae00000, 0x475 },
15420 { 0x00000000, 0x002f00c9, 0x000 },
15421 { 0x00000000, 0x04e00000, 0x48e },
15422 { 0x00000000, 0x00400000, 0x49b },
15423 { 0x00000002, 0x002f0222, 0x000 },
15424 { 0x00000000, 0x0ae00000, 0x47a },
15425 { 0x00000000, 0x002f00c9, 0x000 },
15426 { 0x00000000, 0x02e00000, 0x48e },
15427 { 0x00000000, 0x00400000, 0x49b },
15428 { 0x00000003, 0x002f0222, 0x000 },
15429 { 0x00000000, 0x0ae00000, 0x47f },
15430 { 0x00000000, 0x002f00c9, 0x000 },
15431 { 0x00000000, 0x0ce00000, 0x48e },
15432 { 0x00000000, 0x00400000, 0x49b },
15433 { 0x00000004, 0x002f0222, 0x000 },
15434 { 0x00000000, 0x0ae00000, 0x484 },
15435 { 0x00000000, 0x002f00c9, 0x000 },
15436 { 0x00000000, 0x0ae00000, 0x48e },
15437 { 0x00000000, 0x00400000, 0x49b },
15438 { 0x00000005, 0x002f0222, 0x000 },
15439 { 0x00000000, 0x0ae00000, 0x489 },
15440 { 0x00000000, 0x002f00c9, 0x000 },
15441 { 0x00000000, 0x06e00000, 0x48e },
15442 { 0x00000000, 0x00400000, 0x49b },
15443 { 0x00000006, 0x002f0222, 0x000 },
15444 { 0x00000000, 0x0ae00000, 0x48e },
15445 { 0x00000000, 0x002f00c9, 0x000 },
15446 { 0x00000000, 0x08e00000, 0x48e },
15447 { 0x00000000, 0x00400000, 0x49b },
15448 { 0x00007f00, 0x00280a21, 0x000 },
15449 { 0x00004500, 0x002f0222, 0x000 },
15450 { 0x00000000, 0x0ae00000, 0x000 },
15451 { 0x00000008, 0x00210a23, 0x000 },
15452 { 0x00000000, 0x14c00000, 0x498 },
15453 { 0x00002169, 0x00204411, 0x000 },
15454 { 0x00000000, 0xc0204800, 0x000 },
15455 { 0x00000000, 0xc0204800, 0x000 },
15456 { 0x00000000, 0xc0204800, 0x000 },
15457 { 0xcafebabe, 0x00404811, 0x000 },
15458 { 0x00000000, 0xc0204400, 0x000 },
15459 { 0x00000000, 0xc0200000, 0x000 },
15460 { 0x00000000, 0xc0404800, 0x000 },
15461 { 0x00007f00, 0x00280a21, 0x000 },
15462 { 0x00004500, 0x002f0222, 0x000 },
15463 { 0x00000000, 0x0ae00000, 0x4a1 },
15464 { 0x00000000, 0xc0200000, 0x000 },
15465 { 0x00000000, 0xc0200000, 0x000 },
15466 { 0x00000000, 0xc0400000, 0x000 },
15467 { 0x00000000, 0x00404c08, 0x461 },
15468 { 0x00000000, 0xc0200800, 0x000 },
15469 { 0x00000010, 0x40210e20, 0x000 },
15470 { 0x00000011, 0x40211220, 0x000 },
15471 { 0x00000012, 0x40211620, 0x000 },
15472 { 0x00002169, 0x00204411, 0x000 },
15473 { 0x00000000, 0x00204802, 0x000 },
15474 { 0x00000000, 0x00210225, 0x000 },
15475 { 0x00000000, 0x14e00000, 0x4ab },
15476 { 0x00040000, 0xc0494a20, 0x4ac },
15477 { 0xfffbffff, 0xc0284a20, 0x000 },
15478 { 0x00000000, 0x00210223, 0x000 },
15479 { 0x00000000, 0x14e00000, 0x4b8 },
15480 { 0x00000000, 0xc0204800, 0x000 },
15481 { 0x00000000, 0xc0204800, 0x000 },
15482 { 0x00000000, 0x00210224, 0x000 },
15483 { 0x00000000, 0x14c00000, 0x000 },
15484 { 0x81000000, 0x00204411, 0x000 },
15485 { 0x0000000c, 0x00204811, 0x000 },
15486 { 0x00000000, 0x00200010, 0x000 },
15487 { 0x00000000, 0x14c00000, 0x4b4 },
15488 { 0xa0000000, 0x00204411, 0x000 },
15489 { 0xcafebabe, 0x00404811, 0x000 },
15490 { 0x81000000, 0x00204411, 0x000 },
15491 { 0x00000004, 0x00204811, 0x000 },
15492 { 0x0000216b, 0x00204411, 0x000 },
15493 { 0x00000000, 0xc0204810, 0x000 },
15494 { 0x81000000, 0x00204411, 0x000 },
15495 { 0x00000005, 0x00204811, 0x000 },
15496 { 0x0000216c, 0x00204411, 0x000 },
15497 { 0x00000000, 0xc0204810, 0x000 },
15498 { 0x00000000, 0x002f0224, 0x000 },
15499 { 0x00000000, 0x0ce00000, 0x000 },
15500 { 0x00000000, 0x00400000, 0x4b2 },
15501 { 0x00000000, 0xc0210a20, 0x000 },
15502 { 0x00000000, 0x14c00000, 0x4cb },
15503 { 0x81000000, 0x00204411, 0x000 },
15504 { 0x00000000, 0x00204811, 0x000 },
15505 { 0x0000216d, 0x00204411, 0x000 },
15506 { 0x00000000, 0xc0204800, 0x000 },
15507 { 0x00000000, 0xc0604800, 0x627 },
15508 { 0x00000000, 0x00400000, 0x4cf },
15509 { 0x81000000, 0x00204411, 0x000 },
15510 { 0x00000001, 0x00204811, 0x000 },
15511 { 0x00040000, 0xc0294620, 0x000 },
15512 { 0x00000000, 0xc0600000, 0x622 },
15513 { 0x00000001, 0x00210222, 0x000 },
15514 { 0x00000000, 0x14c00000, 0x4d6 },
15515 { 0x00002169, 0x00204411, 0x000 },
15516 { 0x00000000, 0xc0204800, 0x000 },
15517 { 0x00000000, 0xc0204800, 0x000 },
15518 { 0x00000000, 0x00204810, 0x000 },
15519 { 0xcafebabe, 0x00404811, 0x000 },
15520 { 0x00000000, 0xc0204400, 0x000 },
15521 { 0x00000000, 0xc0404810, 0x000 },
15522 { 0x81000000, 0x00204411, 0x000 },
15523 { 0x00000001, 0x00204811, 0x000 },
15524 { 0x000021f8, 0x00204411, 0x000 },
15525 { 0x0000000e, 0x00204811, 0x000 },
15526 { 0x000421f9, 0x00604411, 0x622 },
15527 { 0x00000000, 0x00210230, 0x000 },
15528 { 0x00000000, 0x14c00000, 0x4d8 },
15529 { 0x00002180, 0x00204411, 0x000 },
15530 { 0x00000000, 0xc0204800, 0x000 },
15531 { 0x00000000, 0xc0200000, 0x000 },
15532 { 0x00000000, 0xc0204800, 0x000 },
15533 { 0x00000000, 0xc0200000, 0x000 },
15534 { 0x00000000, 0xc0404800, 0x000 },
15535 { 0x00000003, 0x00333e2f, 0x000 },
15536 { 0x00000001, 0x00210221, 0x000 },
15537 { 0x00000000, 0x14e00000, 0x508 },
15538 { 0x0000002c, 0x00200a2d, 0x000 },
15539 { 0x00040000, 0x18e00c11, 0x4f7 },
15540 { 0x00000001, 0x00333e2f, 0x000 },
15541 { 0x00002169, 0x00204411, 0x000 },
15542 { 0x00000000, 0x00204802, 0x000 },
15543 { 0x00000000, 0x00204803, 0x000 },
15544 { 0x00000008, 0x00300a22, 0x000 },
15545 { 0x00000000, 0xc0204800, 0x000 },
15546 { 0x00000000, 0xc0204800, 0x000 },
15547 { 0x00002169, 0x00204411, 0x000 },
15548 { 0x00000000, 0x00204802, 0x000 },
15549 { 0x00000000, 0x00204803, 0x000 },
15550 { 0x00000008, 0x00300a22, 0x000 },
15551 { 0x00000000, 0xc0204800, 0x000 },
15552 { 0x00000000, 0xd8c04800, 0x4eb },
15553 { 0x00002169, 0x00204411, 0x000 },
15554 { 0x00000000, 0x00204802, 0x000 },
15555 { 0x00000000, 0x00204803, 0x000 },
15556 { 0x00000008, 0x00300a22, 0x000 },
15557 { 0x00000000, 0xc0204800, 0x000 },
15558 { 0x00000000, 0xc0204800, 0x000 },
15559 { 0x0000002d, 0x0020122d, 0x000 },
15560 { 0x00000000, 0x00290c83, 0x000 },
15561 { 0x00002169, 0x00204411, 0x000 },
15562 { 0x00000000, 0x00204802, 0x000 },
15563 { 0x00000000, 0x00204803, 0x000 },
15564 { 0x00000008, 0x00300a22, 0x000 },
15565 { 0x00000000, 0xc0204800, 0x000 },
15566 { 0x00000000, 0xc0204800, 0x000 },
15567 { 0x00000011, 0x00210224, 0x000 },
15568 { 0x00000000, 0x14c00000, 0x000 },
15569 { 0x00000000, 0x00400000, 0x4b2 },
15570 { 0x0000002c, 0xc0203620, 0x000 },
15571 { 0x0000002d, 0xc0403620, 0x000 },
15572 { 0x0000000f, 0x00210221, 0x000 },
15573 { 0x00000000, 0x14c00000, 0x50d },
15574 { 0x00000000, 0x00600000, 0x00b },
15575 { 0x00000000, 0xd9000000, 0x000 },
15576 { 0x00000000, 0xc0400400, 0x001 },
15577 { 0xb5000000, 0x00204411, 0x000 },
15578 { 0x00002000, 0x00204811, 0x000 },
15579 { 0xb6000000, 0x00204411, 0x000 },
15580 { 0x0000a000, 0x00204811, 0x000 },
15581 { 0xb7000000, 0x00204411, 0x000 },
15582 { 0x0000c000, 0x00204811, 0x000 },
15583 { 0xb8000000, 0x00204411, 0x000 },
15584 { 0x0000f8e0, 0x00204811, 0x000 },
15585 { 0xb9000000, 0x00204411, 0x000 },
15586 { 0x0000f880, 0x00204811, 0x000 },
15587 { 0xba000000, 0x00204411, 0x000 },
15588 { 0x0000e000, 0x00204811, 0x000 },
15589 { 0xbb000000, 0x00204411, 0x000 },
15590 { 0x0000f000, 0x00204811, 0x000 },
15591 { 0xbc000000, 0x00204411, 0x000 },
15592 { 0x0000f3fc, 0x00204811, 0x000 },
15593 { 0x81000000, 0x00204411, 0x000 },
15594 { 0x00000002, 0x00204811, 0x000 },
15595 { 0x000000ff, 0x00280e30, 0x000 },
15596 { 0x00000000, 0x002f0223, 0x000 },
15597 { 0x00000000, 0x0cc00000, 0x521 },
15598 { 0x00000000, 0xc0200800, 0x000 },
15599 { 0x00000000, 0x14c00000, 0x536 },
15600 { 0x00000000, 0x00200c11, 0x000 },
15601 { 0x0000001c, 0x00203623, 0x000 },
15602 { 0x0000002b, 0x00203623, 0x000 },
15603 { 0x00000029, 0x00203623, 0x000 },
15604 { 0x00000028, 0x00203623, 0x000 },
15605 { 0x00000017, 0x00203623, 0x000 },
15606 { 0x00000025, 0x00203623, 0x000 },
15607 { 0x00000026, 0x00203623, 0x000 },
15608 { 0x00000015, 0x00203623, 0x000 },
15609 { 0x00000016, 0x00203623, 0x000 },
15610 { 0xffffe000, 0x00200c11, 0x000 },
15611 { 0x00000021, 0x00203623, 0x000 },
15612 { 0x00000022, 0x00203623, 0x000 },
15613 { 0x00001fff, 0x00200c11, 0x000 },
15614 { 0x00000023, 0x00203623, 0x000 },
15615 { 0x00000024, 0x00203623, 0x000 },
15616 { 0xf1ffffff, 0x00283a2e, 0x000 },
15617 { 0x0000001a, 0xc0220e20, 0x000 },
15618 { 0x00000000, 0x0029386e, 0x000 },
15619 { 0x81000000, 0x00204411, 0x000 },
15620 { 0x00000006, 0x00204811, 0x000 },
15621 { 0x0000002a, 0x40203620, 0x000 },
15622 { 0x87000000, 0x00204411, 0x000 },
15623 { 0x00000000, 0xc0204800, 0x000 },
15624 { 0x0000a1f4, 0x00204411, 0x000 },
15625 { 0x00000000, 0x00204810, 0x000 },
15626 { 0x9d000000, 0x00204411, 0x000 },
15627 { 0x0000001f, 0x40214a20, 0x000 },
15628 { 0x96000000, 0x00204411, 0x000 },
15629 { 0x00000000, 0xc0204800, 0x000 },
15630 { 0x00000000, 0xc0200c00, 0x000 },
15631 { 0x00000000, 0xc0201000, 0x000 },
15632 { 0x0000001f, 0x00211624, 0x000 },
15633 { 0x00000000, 0x14c00000, 0x000 },
15634 { 0x0000001d, 0x00203623, 0x000 },
15635 { 0x00000003, 0x00281e23, 0x000 },
15636 { 0x00000008, 0x00222223, 0x000 },
15637 { 0xfffff000, 0x00282228, 0x000 },
15638 { 0x00000000, 0x002920e8, 0x000 },
15639 { 0x0000001f, 0x00203628, 0x000 },
15640 { 0x00000018, 0x00211e23, 0x000 },
15641 { 0x00000020, 0x00203627, 0x000 },
15642 { 0x00000002, 0x00221624, 0x000 },
15643 { 0x00000000, 0x003014a8, 0x000 },
15644 { 0x0000001e, 0x00203625, 0x000 },
15645 { 0x00000003, 0x00211a24, 0x000 },
15646 { 0x10000000, 0x00281a26, 0x000 },
15647 { 0xefffffff, 0x00283a2e, 0x000 },
15648 { 0x00000000, 0x004938ce, 0x610 },
15649 { 0x00000001, 0x40280a20, 0x000 },
15650 { 0x00000006, 0x40280e20, 0x000 },
15651 { 0x00000300, 0xc0281220, 0x000 },
15652 { 0x00000008, 0x00211224, 0x000 },
15653 { 0x00000000, 0xc0201620, 0x000 },
15654 { 0x00000000, 0xc0201a20, 0x000 },
15655 { 0x00000000, 0x00210222, 0x000 },
15656 { 0x00000000, 0x14c00000, 0x56c },
15657 { 0x81000000, 0x00204411, 0x000 },
15658 { 0x00000001, 0x00204811, 0x000 },
15659 { 0x00002258, 0x00300a24, 0x000 },
15660 { 0x00040000, 0x00694622, 0x622 },
15661 { 0x00002169, 0x00204411, 0x000 },
15662 { 0x00000000, 0x00204805, 0x000 },
15663 { 0x00020000, 0x00294a26, 0x000 },
15664 { 0x00000000, 0x00204810, 0x000 },
15665 { 0xcafebabe, 0x00204811, 0x000 },
15666 { 0x00000002, 0x002f0223, 0x000 },
15667 { 0x00000000, 0x0cc00000, 0x574 },
15668 { 0x00000000, 0xc0201c10, 0x000 },
15669 { 0x00000000, 0xc0400000, 0x582 },
15670 { 0x00000002, 0x002f0223, 0x000 },
15671 { 0x00000000, 0x0cc00000, 0x574 },
15672 { 0x81000000, 0x00204411, 0x000 },
15673 { 0x00000001, 0x00204811, 0x000 },
15674 { 0x00002258, 0x00300a24, 0x000 },
15675 { 0x00040000, 0x00694622, 0x622 },
15676 { 0x00000000, 0xc0201c10, 0x000 },
15677 { 0x00000000, 0xc0400000, 0x582 },
15678 { 0x00000000, 0x002f0223, 0x000 },
15679 { 0x00000000, 0x0cc00000, 0x578 },
15680 { 0x00000000, 0xc0201c00, 0x000 },
15681 { 0x00000000, 0xc0400000, 0x582 },
15682 { 0x00000004, 0x002f0223, 0x000 },
15683 { 0x00000000, 0x0cc00000, 0x580 },
15684 { 0x81000000, 0x00204411, 0x000 },
15685 { 0x00000000, 0x00204811, 0x000 },
15686 { 0x0000216d, 0x00204411, 0x000 },
15687 { 0x00000000, 0xc0204800, 0x000 },
15688 { 0x00000000, 0xc0604800, 0x627 },
15689 { 0x00000000, 0x00401c10, 0x582 },
15690 { 0x00000000, 0xc0200000, 0x000 },
15691 { 0x00000000, 0xc0400000, 0x000 },
15692 { 0x00000000, 0x0ee00000, 0x584 },
15693 { 0x00000000, 0x00600000, 0x5c3 },
15694 { 0x00000000, 0x002f0224, 0x000 },
15695 { 0x00000000, 0x0cc00000, 0x592 },
15696 { 0x0000a2b7, 0x00204411, 0x000 },
15697 { 0x00000000, 0x00204807, 0x000 },
15698 { 0x00000033, 0x0020262d, 0x000 },
15699 { 0x0000001a, 0x00212229, 0x000 },
15700 { 0x00000006, 0x00222629, 0x000 },
15701 { 0x0000a2c4, 0x00204411, 0x000 },
15702 { 0x00000000, 0x003048e9, 0x000 },
15703 { 0x00000000, 0x00e00000, 0x590 },
15704 { 0x0000a2d1, 0x00204411, 0x000 },
15705 { 0x00000000, 0x00404808, 0x000 },
15706 { 0x0000a2d1, 0x00204411, 0x000 },
15707 { 0x00000001, 0x00504a28, 0x000 },
15708 { 0x00000001, 0x002f0224, 0x000 },
15709 { 0x00000000, 0x0cc00000, 0x5a0 },
15710 { 0x0000a2bb, 0x00204411, 0x000 },
15711 { 0x00000000, 0x00204807, 0x000 },
15712 { 0x00000034, 0x0020262d, 0x000 },
15713 { 0x0000001a, 0x00212229, 0x000 },
15714 { 0x00000006, 0x00222629, 0x000 },
15715 { 0x0000a2c5, 0x00204411, 0x000 },
15716 { 0x00000000, 0x003048e9, 0x000 },
15717 { 0x00000000, 0x00e00000, 0x59e },
15718 { 0x0000a2d2, 0x00204411, 0x000 },
15719 { 0x00000000, 0x00404808, 0x000 },
15720 { 0x0000a2d2, 0x00204411, 0x000 },
15721 { 0x00000001, 0x00504a28, 0x000 },
15722 { 0x00000002, 0x002f0224, 0x000 },
15723 { 0x00000000, 0x0cc00000, 0x5ae },
15724 { 0x0000a2bf, 0x00204411, 0x000 },
15725 { 0x00000000, 0x00204807, 0x000 },
15726 { 0x00000035, 0x0020262d, 0x000 },
15727 { 0x0000001a, 0x00212229, 0x000 },
15728 { 0x00000006, 0x00222629, 0x000 },
15729 { 0x0000a2c6, 0x00204411, 0x000 },
15730 { 0x00000000, 0x003048e9, 0x000 },
15731 { 0x00000000, 0x00e00000, 0x5ac },
15732 { 0x0000a2d3, 0x00204411, 0x000 },
15733 { 0x00000000, 0x00404808, 0x000 },
15734 { 0x0000a2d3, 0x00204411, 0x000 },
15735 { 0x00000001, 0x00504a28, 0x000 },
15736 { 0x0000a2c3, 0x00204411, 0x000 },
15737 { 0x00000000, 0x00204807, 0x000 },
15738 { 0x00000036, 0x0020262d, 0x000 },
15739 { 0x0000001a, 0x00212229, 0x000 },
15740 { 0x00000006, 0x00222629, 0x000 },
15741 { 0x0000a2c7, 0x00204411, 0x000 },
15742 { 0x00000000, 0x003048e9, 0x000 },
15743 { 0x00000000, 0x00e00000, 0x5b8 },
15744 { 0x0000a2d4, 0x00204411, 0x000 },
15745 { 0x00000000, 0x00404808, 0x000 },
15746 { 0x0000a2d4, 0x00204411, 0x000 },
15747 { 0x00000001, 0x00504a28, 0x000 },
15748 { 0x85000000, 0x00204411, 0x000 },
15749 { 0x00000000, 0x00204801, 0x000 },
15750 { 0x0000304a, 0x00204411, 0x000 },
15751 { 0x01000000, 0x00204811, 0x000 },
15752 { 0x00000000, 0x00400000, 0x5be },
15753 { 0xa4000000, 0xc0204411, 0x000 },
15754 { 0x00000000, 0xc0404800, 0x000 },
15755 { 0x00000000, 0xc0600000, 0x5c3 },
15756 { 0x00000000, 0xc0400400, 0x001 },
15757 { 0x0001a2a4, 0x00204411, 0x000 },
15758 { 0x0000003f, 0x00204811, 0x000 },
15759 { 0x0000003f, 0x00204811, 0x000 },
15760 { 0x0000003f, 0x00204811, 0x000 },
15761 { 0x0000003f, 0x00204811, 0x000 },
15762 { 0x00000005, 0x00204811, 0x000 },
15763 { 0x0000a1f4, 0x00204411, 0x000 },
15764 { 0x00000000, 0x00204811, 0x000 },
15765 { 0x88000000, 0x00204411, 0x000 },
15766 { 0x00000001, 0x00204811, 0x000 },
15767 { 0xff000000, 0x00204411, 0x000 },
15768 { 0x00000000, 0x00204811, 0x000 },
15769 { 0x00000001, 0x00204811, 0x000 },
15770 { 0x00000002, 0x00804811, 0x000 },
15771 { 0x00000000, 0x0ee00000, 0x5d6 },
15772 { 0x00001000, 0x00200811, 0x000 },
15773 { 0x0000002b, 0x00203622, 0x000 },
15774 { 0x00000000, 0x00600000, 0x5da },
15775 { 0x00000000, 0x00600000, 0x5c3 },
15776 { 0x98000000, 0x00204411, 0x000 },
15777 { 0x00000000, 0x00804811, 0x000 },
15778 { 0x00000000, 0xc0600000, 0x5da },
15779 { 0x00000000, 0xc0400400, 0x001 },
15780 { 0x0000a2a4, 0x00204411, 0x000 },
15781 { 0x00000022, 0x00204811, 0x000 },
15782 { 0x89000000, 0x00204411, 0x000 },
15783 { 0x00000001, 0x00404811, 0x5cd },
15784 { 0x97000000, 0x00204411, 0x000 },
15785 { 0x00000000, 0x00204811, 0x000 },
15786 { 0x8a000000, 0x00204411, 0x000 },
15787 { 0x00000000, 0x00404811, 0x5cd },
15788 { 0x00000000, 0x00600000, 0x5f3 },
15789 { 0x0001a2a4, 0xc0204411, 0x000 },
15790 { 0x00000016, 0x00604811, 0x374 },
15791 { 0x00002010, 0x00204411, 0x000 },
15792 { 0x00010000, 0x00204811, 0x000 },
15793 { 0x81000000, 0x00204411, 0x000 },
15794 { 0x00000001, 0x00204811, 0x000 },
15795 { 0x0000217c, 0x00204411, 0x000 },
15796 { 0x09800000, 0x00204811, 0x000 },
15797 { 0xffffffff, 0x00204811, 0x000 },
15798 { 0x00000000, 0x00204811, 0x000 },
15799 { 0x00000000, 0x17000000, 0x000 },
15800 { 0x0004217f, 0x00604411, 0x622 },
15801 { 0x0000001f, 0x00210230, 0x000 },
15802 { 0x00000000, 0x14c00000, 0x000 },
15803 { 0x00000004, 0x00404c11, 0x5ed },
15804 { 0x00000000, 0x00400000, 0x000 },
15805 { 0x00000017, 0x00201e2d, 0x000 },
15806 { 0x00000004, 0x00291e27, 0x000 },
15807 { 0x00000017, 0x00803627, 0x000 },
15808 { 0x00000017, 0x00201e2d, 0x000 },
15809 { 0xfffffffb, 0x00281e27, 0x000 },
15810 { 0x00000017, 0x00803627, 0x000 },
15811 { 0x00000017, 0x00201e2d, 0x000 },
15812 { 0x00000008, 0x00291e27, 0x000 },
15813 { 0x00000017, 0x00803627, 0x000 },
15814 { 0x00000017, 0x00201e2d, 0x000 },
15815 { 0xfffffff7, 0x00281e27, 0x000 },
15816 { 0x00000017, 0x00803627, 0x000 },
15817 { 0x0001a2a4, 0x00204411, 0x000 },
15818 { 0x00000016, 0x00604811, 0x374 },
15819 { 0x00002010, 0x00204411, 0x000 },
15820 { 0x00010000, 0x00204811, 0x000 },
15821 { 0x0000217c, 0x00204411, 0x000 },
15822 { 0x01800000, 0x00204811, 0x000 },
15823 { 0xffffffff, 0x00204811, 0x000 },
15824 { 0x00000000, 0x00204811, 0x000 },
15825 { 0x00000000, 0x17000000, 0x000 },
15826 { 0x81000000, 0x00204411, 0x000 },
15827 { 0x00000001, 0x00204811, 0x000 },
15828 { 0x0004217f, 0x00604411, 0x622 },
15829 { 0x0000001f, 0x00210230, 0x000 },
15830 { 0x00000000, 0x14c00000, 0x621 },
15831 { 0x00000010, 0x00404c11, 0x607 },
15832 { 0x00000000, 0xc0200400, 0x000 },
15833 { 0x00000000, 0x38c00000, 0x000 },
15834 { 0x0000001d, 0x00200a2d, 0x000 },
15835 { 0x0000001e, 0x00200e2d, 0x000 },
15836 { 0x0000001f, 0x0020122d, 0x000 },
15837 { 0x00000020, 0x0020162d, 0x000 },
15838 { 0x00002169, 0x00204411, 0x000 },
15839 { 0x00000000, 0x00204804, 0x000 },
15840 { 0x00000000, 0x00204805, 0x000 },
15841 { 0x00000000, 0x00204801, 0x000 },
15842 { 0xcafebabe, 0x00204811, 0x000 },
15843 { 0x00000004, 0x00301224, 0x000 },
15844 { 0x00000000, 0x002f0064, 0x000 },
15845 { 0x00000000, 0x0cc00000, 0x620 },
15846 { 0x00000003, 0x00281a22, 0x000 },
15847 { 0x00000008, 0x00221222, 0x000 },
15848 { 0xfffff000, 0x00281224, 0x000 },
15849 { 0x00000000, 0x002910c4, 0x000 },
15850 { 0x0000001f, 0x00403624, 0x000 },
15851 { 0x00000000, 0x00800000, 0x000 },
15852 { 0x00000000, 0x1ac00000, 0x622 },
15853 { 0x9f000000, 0x00204411, 0x000 },
15854 { 0xcafebabe, 0x00204811, 0x000 },
15855 { 0x00000000, 0x1ae00000, 0x625 },
15856 { 0x00000000, 0x00800000, 0x000 },
15857 { 0x00000000, 0x1ac00000, 0x627 },
15858 { 0x9e000000, 0x00204411, 0x000 },
15859 { 0xcafebabe, 0x00204811, 0x000 },
15860 { 0x00000000, 0x1ae00000, 0x62a },
15861 { 0x00000000, 0x00800000, 0x000 },
15862 { 0x00000000, 0x00600000, 0x00b },
15863 { 0x00001000, 0x00600411, 0x315 },
15864 { 0x00000000, 0x00200411, 0x000 },
15865 { 0x00000000, 0x00600811, 0x1b2 },
15866 { 0x0000225c, 0x00204411, 0x000 },
15867 { 0x00000003, 0x00204811, 0x000 },
15868 { 0x00002256, 0x00204411, 0x000 },
15869 { 0x0000001b, 0x00204811, 0x000 },
15870 { 0x0000a1fc, 0x00204411, 0x000 },
15871 { 0x00000001, 0x00204811, 0x000 },
15872 { 0x0001a1fd, 0xc0204411, 0x000 },
15873 { 0x00000021, 0x00201e2d, 0x000 },
15874 { 0x00000010, 0x00221e27, 0x000 },
15875 { 0x00000024, 0x0020222d, 0x000 },
15876 { 0x0000ffff, 0x00282228, 0x000 },
15877 { 0x00000000, 0x00294907, 0x000 },
15878 { 0x00000000, 0x00204811, 0x000 },
15879 { 0x00000022, 0x0020222d, 0x000 },
15880 { 0x0000ffff, 0x00282228, 0x000 },
15881 { 0x00000000, 0x00294907, 0x000 },
15882 { 0x00000000, 0x00204811, 0x000 },
15883 { 0x00000023, 0x00201e2d, 0x000 },
15884 { 0x00000010, 0x00221e27, 0x000 },
15885 { 0x00000000, 0x00294907, 0x000 },
15886 { 0x00000000, 0x00404811, 0x000 },
15887 { 0x00000000, 0x00000000, 0x000 },
15888 { 0x00000000, 0x00000000, 0x000 },
15889 { 0x00000000, 0x00000000, 0x000 },
15890 { 0x00000000, 0x00000000, 0x000 },
15891 { 0x00000000, 0x00000000, 0x000 },
15892 { 0x00000000, 0x00000000, 0x000 },
15893 { 0x00000000, 0x00000000, 0x000 },
15894 { 0x00000000, 0x00000000, 0x000 },
15895 { 0x00000000, 0x00000000, 0x000 },
15896 { 0x00000000, 0x00000000, 0x000 },
15897 { 0x00000000, 0x00000000, 0x000 },
15898 { 0x00000000, 0x00000000, 0x000 },
15899 { 0x00000000, 0x00000000, 0x000 },
15900 { 0x00000000, 0x00000000, 0x000 },
15901 { 0x00000000, 0x00000000, 0x000 },
15902 { 0x00000000, 0x00000000, 0x000 },
15903 { 0x00000000, 0x00000000, 0x000 },
15904 { 0x00000000, 0x00000000, 0x000 },
15905 { 0x00000000, 0x00000000, 0x000 },
15906 { 0x00000000, 0x00000000, 0x000 },
15907 { 0x00000000, 0x00000000, 0x000 },
15908 { 0x00000000, 0x00000000, 0x000 },
15909 { 0x00000000, 0x00000000, 0x000 },
15910 { 0x00000000, 0x00000000, 0x000 },
15911 { 0x00000000, 0x00000000, 0x000 },
15912 { 0x00000000, 0x00000000, 0x000 },
15913 { 0x00000000, 0x00000000, 0x000 },
15914 { 0x00000000, 0x00000000, 0x000 },
15915 { 0x00000000, 0x00000000, 0x000 },
15916 { 0x00000000, 0x00000000, 0x000 },
15917 { 0x00000000, 0x00000000, 0x000 },
15918 { 0x00000000, 0x00000000, 0x000 },
15919 { 0x00000000, 0x00000000, 0x000 },
15920 { 0x00000000, 0x00000000, 0x000 },
15921 { 0x00000000, 0x00000000, 0x000 },
15922 { 0x00000000, 0x00000000, 0x000 },
15923 { 0x00000000, 0x00000000, 0x000 },
15924 { 0x00000000, 0x00000000, 0x000 },
15925 { 0x00000000, 0x00000000, 0x000 },
15926 { 0x00000000, 0x00000000, 0x000 },
15927 { 0x00000000, 0x00000000, 0x000 },
15928 { 0x00000000, 0x00000000, 0x000 },
15929 { 0x00000000, 0x00000000, 0x000 },
15930 { 0x00000000, 0x00000000, 0x000 },
15931 { 0x00000000, 0x00000000, 0x000 },
15932 { 0x00000000, 0x00000000, 0x000 },
15933 { 0x00000000, 0x00000000, 0x000 },
15934 { 0x00000000, 0x00000000, 0x000 },
15935 { 0x00000000, 0x00000000, 0x000 },
15936 { 0x00000000, 0x00000000, 0x000 },
15937 { 0x00000000, 0x00000000, 0x000 },
15938 { 0x00000000, 0x00000000, 0x000 },
15939 { 0x00000000, 0x00000000, 0x000 },
15940 { 0x00000000, 0x00000000, 0x000 },
15941 { 0x00000000, 0x00000000, 0x000 },
15942 { 0x00000000, 0x00000000, 0x000 },
15943 { 0x00000000, 0x00000000, 0x000 },
15944 { 0x00000000, 0x00000000, 0x000 },
15945 { 0x00000000, 0x00000000, 0x000 },
15946 { 0x00000000, 0x00000000, 0x000 },
15947 { 0x00000000, 0x00000000, 0x000 },
15948 { 0x00000000, 0x00000000, 0x000 },
15949 { 0x00000000, 0x00000000, 0x000 },
15950 { 0x00000000, 0x00000000, 0x000 },
15951 { 0x00000000, 0x00000000, 0x000 },
15952 { 0x00000000, 0x00000000, 0x000 },
15953 { 0x00000000, 0x00000000, 0x000 },
15954 { 0x00000000, 0x00000000, 0x000 },
15955 { 0x00000000, 0x00000000, 0x000 },
15956 { 0x00000000, 0x00000000, 0x000 },
15957 { 0x00000000, 0x00000000, 0x000 },
15958 { 0x00000000, 0x00000000, 0x000 },
15959 { 0x00000000, 0x00000000, 0x000 },
15960 { 0x00000000, 0x00000000, 0x000 },
15961 { 0x00000000, 0x00000000, 0x000 },
15962 { 0x00000000, 0x00000000, 0x000 },
15963 { 0x00000000, 0x00000000, 0x000 },
15964 { 0x00000000, 0x00000000, 0x000 },
15965 { 0x00000000, 0x00000000, 0x000 },
15966 { 0x00000000, 0x00000000, 0x000 },
15967 { 0x00000000, 0x00000000, 0x000 },
15968 { 0x00000000, 0x00000000, 0x000 },
15969 { 0x00000000, 0x00000000, 0x000 },
15970 { 0x00000000, 0x00000000, 0x000 },
15971 { 0x00000000, 0x00000000, 0x000 },
15972 { 0x00000000, 0x00000000, 0x000 },
15973 { 0x00000000, 0x00000000, 0x000 },
15974 { 0x00000000, 0x00000000, 0x000 },
15975 { 0x00000000, 0x00000000, 0x000 },
15976 { 0x00000000, 0x00000000, 0x000 },
15977 { 0x00000000, 0x00000000, 0x000 },
15978 { 0x00000000, 0x00000000, 0x000 },
15979 { 0x00000000, 0x00000000, 0x000 },
15980 { 0x00000000, 0x00000000, 0x000 },
15981 { 0x00000000, 0x00000000, 0x000 },
15982 { 0x00000000, 0x00000000, 0x000 },
15983 { 0x00000000, 0x00000000, 0x000 },
15984 { 0x00000000, 0x00000000, 0x000 },
15985 { 0x00000000, 0x00000000, 0x000 },
15986 { 0x00000000, 0x00000000, 0x000 },
15987 { 0x00000000, 0x00000000, 0x000 },
15988 { 0x00000000, 0x00000000, 0x000 },
15989 { 0x00000000, 0x00000000, 0x000 },
15990 { 0x00000000, 0x00000000, 0x000 },
15991 { 0x00000000, 0x00000000, 0x000 },
15992 { 0x00000000, 0x00000000, 0x000 },
15993 { 0x00000000, 0x00000000, 0x000 },
15994 { 0x00000000, 0x00000000, 0x000 },
15995 { 0x00000000, 0x00000000, 0x000 },
15996 { 0x00000000, 0x00000000, 0x000 },
15997 { 0x00000000, 0x00000000, 0x000 },
15998 { 0x00000000, 0x00000000, 0x000 },
15999 { 0x00000000, 0x00000000, 0x000 },
16000 { 0x00000000, 0x00000000, 0x000 },
16001 { 0x00000000, 0x00000000, 0x000 },
16002 { 0x00000000, 0x00000000, 0x000 },
16003 { 0x00000000, 0x00000000, 0x000 },
16004 { 0x00000000, 0x00000000, 0x000 },
16005 { 0x00000000, 0x00000000, 0x000 },
16006 { 0x00000000, 0x00000000, 0x000 },
16007 { 0x00000000, 0x00000000, 0x000 },
16008 { 0x00000000, 0x00000000, 0x000 },
16009 { 0x00000000, 0x00000000, 0x000 },
16010 { 0x00000000, 0x00000000, 0x000 },
16011 { 0x00000000, 0x00000000, 0x000 },
16012 { 0x00000000, 0x00000000, 0x000 },
16013 { 0x00000000, 0x00000000, 0x000 },
16014 { 0x00000000, 0x00000000, 0x000 },
16015 { 0x00000000, 0x00000000, 0x000 },
16016 { 0x00000000, 0x00000000, 0x000 },
16017 { 0x00000000, 0x00000000, 0x000 },
16018 { 0x00000000, 0x00000000, 0x000 },
16019 { 0x00000000, 0x00000000, 0x000 },
16020 { 0x00000000, 0x00000000, 0x000 },
16021 { 0x00000000, 0x00000000, 0x000 },
16022 { 0x00000000, 0x00000000, 0x000 },
16023 { 0x00000000, 0x00000000, 0x000 },
16024 { 0x00000000, 0x00000000, 0x000 },
16025 { 0x00000000, 0x00000000, 0x000 },
16026 { 0x00000000, 0x00000000, 0x000 },
16027 { 0x00000000, 0x00000000, 0x000 },
16028 { 0x00000000, 0x00000000, 0x000 },
16029 { 0x00000000, 0x00000000, 0x000 },
16030 { 0x00000000, 0x00000000, 0x000 },
16031 { 0x00000000, 0x00000000, 0x000 },
16032 { 0x00000000, 0x00000000, 0x000 },
16033 { 0x00000000, 0x00000000, 0x000 },
16034 { 0x00000000, 0x00000000, 0x000 },
16035 { 0x00000000, 0x00000000, 0x000 },
16036 { 0x00000000, 0x00000000, 0x000 },
16037 { 0x00000000, 0x00000000, 0x000 },
16038 { 0x00000000, 0x00000000, 0x000 },
16039 { 0x00000000, 0x00000000, 0x000 },
16040 { 0x00000000, 0x00000000, 0x000 },
16041 { 0x00000000, 0x00000000, 0x000 },
16042 { 0x00000000, 0x00000000, 0x000 },
16043 { 0x00000000, 0x00000000, 0x000 },
16044 { 0x00000000, 0x00000000, 0x000 },
16045 { 0x00000000, 0x00000000, 0x000 },
16046 { 0x0142050a, 0x05ba0250, 0x000 },
16047 { 0x01c30168, 0x044105ba, 0x000 },
16048 { 0x02250209, 0x02500151, 0x000 },
16049 { 0x02230245, 0x02a00241, 0x000 },
16050 { 0x03d705ba, 0x05ba05ba, 0x000 },
16051 { 0x05e205e3, 0x031f05ba, 0x000 },
16052 { 0x032005bf, 0x0320034a, 0x000 },
16053 { 0x03340282, 0x034c033e, 0x000 },
16054 { 0x05ba05ba, 0x05ba05ba, 0x000 },
16055 { 0x05ba0557, 0x05ba032a, 0x000 },
16056 { 0x03bc05ba, 0x04c3034e, 0x000 },
16057 { 0x04a20455, 0x043f05ba, 0x000 },
16058 { 0x04d805ba, 0x044304e5, 0x000 },
16059 { 0x0455050f, 0x035b037b, 0x000 },
16060 { 0x05ba05ba, 0x05ba05ba, 0x000 },
16061 { 0x05ba05ba, 0x05ba05ba, 0x000 },
16062 { 0x05ba05ba, 0x05d805c1, 0x000 },
16063 { 0x05ba05ba, 0x000705ba, 0x000 },
16064 { 0x05ba05ba, 0x05ba05ba, 0x000 },
16065 { 0x05ba05ba, 0x05ba05ba, 0x000 },
16066 { 0x03f803ed, 0x04080406, 0x000 },
16067 { 0x040e040a, 0x040c0410, 0x000 },
16068 { 0x041c0418, 0x04240420, 0x000 },
16069 { 0x042c0428, 0x04340430, 0x000 },
16070 { 0x05ba05ba, 0x043a0438, 0x000 },
16071 { 0x05ba05ba, 0x05ba05ba, 0x000 },
16072 { 0x05ba05ba, 0x05ba05ba, 0x000 },
16073 { 0x0002060e, 0x062c0006, 0x000 },
16074};
16075
16076static const u32 RS780_pfp_microcode[] = {
160770xca0400,
160780xa00000,
160790x7e828b,
160800x7c038b,
160810x8001db,
160820x7c038b,
160830xd4401e,
160840xee001e,
160850xca0400,
160860xa00000,
160870x7e828b,
160880xc41838,
160890xca2400,
160900xca2800,
160910x9581cb,
160920xc41c3a,
160930xc3c000,
160940xca0800,
160950xca0c00,
160960x7c744b,
160970xc20005,
160980x99c000,
160990xc41c3a,
161000x7c744c,
161010xc0ffe0,
161020x042c08,
161030x309002,
161040x7d2500,
161050x351402,
161060x7d350b,
161070x255407,
161080x7cd580,
161090x259c07,
161100x95c004,
161110xd5001b,
161120x7eddc1,
161130x7d9d80,
161140xd6801b,
161150xd5801b,
161160xd4401e,
161170xd5401e,
161180xd6401e,
161190xd6801e,
161200xd4801e,
161210xd4c01e,
161220x9783d3,
161230xd5c01e,
161240xca0800,
161250x80001a,
161260xca0c00,
161270xe4011e,
161280xd4001e,
161290x80000c,
161300xc41838,
161310xe4013e,
161320xd4001e,
161330x80000c,
161340xc41838,
161350xd4401e,
161360xee001e,
161370xca0400,
161380xa00000,
161390x7e828b,
161400xe4011e,
161410xd4001e,
161420xd4401e,
161430xee001e,
161440xca0400,
161450xa00000,
161460x7e828b,
161470xe4013e,
161480xd4001e,
161490xd4401e,
161500xee001e,
161510xca0400,
161520xa00000,
161530x7e828b,
161540xca0800,
161550xca0c00,
161560x8001db,
161570xd48024,
161580xca0800,
161590x7c00c0,
161600xc81425,
161610xc81824,
161620x7c9488,
161630x7c9880,
161640xc20003,
161650xd40075,
161660x7c744c,
161670x800064,
161680xd4401e,
161690xca1800,
161700xd4401e,
161710xd5801e,
161720x800062,
161730xd40075,
161740xd4401e,
161750xca0800,
161760xca0c00,
161770xca1000,
161780xd48019,
161790xd4c018,
161800xd50017,
161810xd4801e,
161820xd4c01e,
161830xd5001e,
161840xe2001e,
161850xca0400,
161860xa00000,
161870x7e828b,
161880xd40075,
161890xd4401e,
161900xca0800,
161910xca0c00,
161920xca1000,
161930xd48019,
161940xd4c018,
161950xd50017,
161960xd4801e,
161970xd4c01e,
161980xd5001e,
161990xee001e,
162000xca0400,
162010xa00000,
162020x7e828b,
162030xca0800,
162040x248c01,
162050xd48060,
162060x94c003,
162070x041001,
162080x041002,
162090xd50025,
162100xd4401e,
162110x800000,
162120xd4801e,
162130xca0800,
162140xd48061,
162150xd4401e,
162160x800000,
162170xd4801e,
162180xca0800,
162190xca0c00,
162200xd4401e,
162210xd48016,
162220xd4c016,
162230xd4801e,
162240x8001db,
162250xd4c01e,
162260xc60843,
162270xca0c00,
162280xca1000,
162290x948004,
162300xca1400,
162310xe420f3,
162320xd42013,
162330xd56065,
162340xd4e01c,
162350xd5201c,
162360xd5601c,
162370x800000,
162380x062001,
162390xc60843,
162400xca0c00,
162410xca1000,
162420x9483f7,
162430xca1400,
162440xe420f3,
162450x80009c,
162460xd42013,
162470xc60843,
162480xca0c00,
162490xca1000,
162500x9883ef,
162510xca1400,
162520xd40064,
162530x8000b0,
162540x000000,
162550xc41432,
162560xc61843,
162570xc4082f,
162580x954005,
162590xc40c30,
162600xd4401e,
162610x800000,
162620xee001e,
162630x9583f5,
162640xc41031,
162650xd44033,
162660xd52065,
162670xd4a01c,
162680xd4e01c,
162690xd5201c,
162700xe4015e,
162710xd4001e,
162720x800000,
162730x062001,
162740xca1800,
162750x0a2001,
162760xd60076,
162770xc40836,
162780x988007,
162790xc61045,
162800x950110,
162810xd4001f,
162820xd46062,
162830x800000,
162840xd42062,
162850xcc3835,
162860xcc1433,
162870x8401de,
162880xd40072,
162890xd5401e,
162900x800000,
162910xee001e,
162920xe2001a,
162930x8401de,
162940xe2001a,
162950xcc104b,
162960xcc0447,
162970x2c9401,
162980x7d098b,
162990x984005,
163000x7d15cb,
163010xd4001a,
163020x8001db,
163030xd4006d,
163040x344401,
163050xcc0c48,
163060x98403a,
163070xcc2c4a,
163080x958004,
163090xcc0449,
163100x8001db,
163110xd4001a,
163120xd4c01a,
163130x282801,
163140x840113,
163150xcc1003,
163160x98801b,
163170x04380c,
163180x840113,
163190xcc1003,
163200x988017,
163210x043808,
163220x840113,
163230xcc1003,
163240x988013,
163250x043804,
163260x840113,
163270xcc1003,
163280x988014,
163290xcc104c,
163300x9a8009,
163310xcc144d,
163320x9840dc,
163330xd4006d,
163340xcc1848,
163350xd5001a,
163360xd5401a,
163370x8000ec,
163380xd5801a,
163390x96c0d5,
163400xd4006d,
163410x8001db,
163420xd4006e,
163430x9ac003,
163440xd4006d,
163450xd4006e,
163460x800000,
163470xec007f,
163480x9ac0cc,
163490xd4006d,
163500x8001db,
163510xd4006e,
163520xcc1403,
163530xcc1803,
163540xcc1c03,
163550x7d9103,
163560x7dd583,
163570x7d190c,
163580x35cc1f,
163590x35701f,
163600x7cf0cb,
163610x7cd08b,
163620x880000,
163630x7e8e8b,
163640x95c004,
163650xd4006e,
163660x8001db,
163670xd4001a,
163680xd4c01a,
163690xcc0803,
163700xcc0c03,
163710xcc1003,
163720xcc1403,
163730xcc1803,
163740xcc1c03,
163750xcc2403,
163760xcc2803,
163770x35c41f,
163780x36b01f,
163790x7c704b,
163800x34f01f,
163810x7c704b,
163820x35701f,
163830x7c704b,
163840x7d8881,
163850x7dccc1,
163860x7e5101,
163870x7e9541,
163880x7c9082,
163890x7cd4c2,
163900x7c848b,
163910x9ac003,
163920x7c8c8b,
163930x2c8801,
163940x98809e,
163950xd4006d,
163960x98409c,
163970xd4006e,
163980xcc084c,
163990xcc0c4d,
164000xcc1048,
164010xd4801a,
164020xd4c01a,
164030x800124,
164040xd5001a,
164050xcc0832,
164060xd40032,
164070x9482b6,
164080xca0c00,
164090xd4401e,
164100x800000,
164110xd4001e,
164120xe4011e,
164130xd4001e,
164140xca0800,
164150xca0c00,
164160xca1000,
164170xd4401e,
164180xca1400,
164190xd4801e,
164200xd4c01e,
164210xd5001e,
164220xd5401e,
164230xd54034,
164240x800000,
164250xee001e,
164260x280404,
164270xe2001a,
164280xe2001a,
164290xd4401a,
164300xca3800,
164310xcc0803,
164320xcc0c03,
164330xcc0c03,
164340xcc0c03,
164350x98829a,
164360x000000,
164370x8401de,
164380xd7a06f,
164390x800000,
164400xee001f,
164410xca0400,
164420xc2ff00,
164430xcc0834,
164440xc13fff,
164450x7c74cb,
164460x7cc90b,
164470x7d010f,
164480x99028d,
164490x7c738b,
164500x8401de,
164510xd7a06f,
164520x800000,
164530xee001f,
164540xca0800,
164550x281900,
164560x7d898b,
164570x958014,
164580x281404,
164590xca0c00,
164600xca1000,
164610xca1c00,
164620xca2400,
164630xe2001f,
164640xd4c01a,
164650xd5001a,
164660xd5401a,
164670xcc1803,
164680xcc2c03,
164690xcc2c03,
164700xcc2c03,
164710x7da58b,
164720x7d9c47,
164730x984274,
164740x000000,
164750x800184,
164760xd4c01a,
164770xd4401e,
164780xd4801e,
164790x800000,
164800xee001e,
164810xe4011e,
164820xd4001e,
164830xd4401e,
164840xee001e,
164850xca0400,
164860xa00000,
164870x7e828b,
164880xe4013e,
164890xd4001e,
164900xd4401e,
164910xee001e,
164920xca0400,
164930xa00000,
164940x7e828b,
164950xca0800,
164960x248c06,
164970x0ccc06,
164980x98c006,
164990xcc104e,
165000x990004,
165010xd40073,
165020xe4011e,
165030xd4001e,
165040xd4401e,
165050xd4801e,
165060x800000,
165070xee001e,
165080xca0800,
165090xca0c00,
165100x34d018,
165110x251001,
165120x950021,
165130xc17fff,
165140xca1000,
165150xca1400,
165160xca1800,
165170xd4801d,
165180xd4c01d,
165190x7db18b,
165200xc14202,
165210xc2c001,
165220xd5801d,
165230x34dc0e,
165240x7d5d4c,
165250x7f734c,
165260xd7401e,
165270xd5001e,
165280xd5401e,
165290xc14200,
165300xc2c000,
165310x099c01,
165320x31dc10,
165330x7f5f4c,
165340x7f734c,
165350x042802,
165360x7d8380,
165370xd5a86f,
165380xd58066,
165390xd7401e,
165400xec005e,
165410xc82402,
165420xc82402,
165430x8001db,
165440xd60076,
165450xd4401e,
165460xd4801e,
165470xd4c01e,
165480x800000,
165490xee001e,
165500x800000,
165510xee001f,
165520xd4001f,
165530x800000,
165540xd4001f,
165550xd4001f,
165560x880000,
165570xd4001f,
165580x000000,
165590x000000,
165600x000000,
165610x000000,
165620x000000,
165630x000000,
165640x000000,
165650x000000,
165660x000000,
165670x000000,
165680x000000,
165690x000000,
165700x000000,
165710x000000,
165720x000000,
165730x000000,
165740x000000,
165750x000000,
165760x000000,
165770x000000,
165780x000000,
165790x000000,
165800x000000,
165810x000000,
165820x000000,
165830x000000,
165840x000000,
165850x000000,
165860x000000,
165870x000000,
165880x000000,
165890x010194,
165900x02019b,
165910x0300b2,
165920x0400a2,
165930x050003,
165940x06003f,
165950x070032,
165960x08014f,
165970x090046,
165980x0a0036,
165990x1001d9,
166000x1700c5,
166010x22015d,
166020x23016c,
166030x2000d7,
166040x240148,
166050x26004d,
166060x27005c,
166070x28008d,
166080x290051,
166090x2a007e,
166100x2b0061,
166110x2f0088,
166120x3200aa,
166130x3401a2,
166140x36006f,
166150x3c0179,
166160x3f0095,
166170x4101af,
166180x440151,
166190x550196,
166200x56019d,
166210x60000b,
166220x610034,
166230x620038,
166240x630038,
166250x640038,
166260x650038,
166270x660038,
166280x670038,
166290x68003a,
166300x690041,
166310x6a0048,
166320x6b0048,
166330x6c0048,
166340x6d0048,
166350x6e0048,
166360x6f0048,
166370x7301d9,
166380x000006,
166390x000006,
166400x000006,
166410x000006,
166420x000006,
166430x000006,
166440x000006,
166450x000006,
166460x000006,
166470x000006,
166480x000006,
166490x000006,
166500x000006,
166510x000006,
166520x000006,
16653};
16654
16655static const u32 RV770_cp_microcode[] = {
166560xcc0003ea,
166570x7c408000,
166580xa0000000,
166590xcc800062,
166600x80000001,
166610xd040007f,
166620x80000001,
166630xcc400041,
166640x7c40c000,
166650xc0160004,
166660x30d03fff,
166670x7d15000c,
166680xcc110000,
166690x28d8001e,
166700x31980001,
166710x28dc001f,
166720xc8200004,
166730x95c00006,
166740x7c424000,
166750xcc000062,
166760x7e56800c,
166770xcc290000,
166780xc8240004,
166790x7e26000b,
166800x95800006,
166810x7c42c000,
166820xcc000062,
166830x7ed7000c,
166840xcc310000,
166850xc82c0004,
166860x7e2e000c,
166870xcc000062,
166880x31103fff,
166890x80000001,
166900xce110000,
166910x7c40c000,
166920x80000001,
166930xcc400040,
166940x80000001,
166950xcc412257,
166960x7c418000,
166970xcc400045,
166980xcc400048,
166990xcc41225c,
167000xcc41a1fc,
167010x7c408000,
167020xa0000000,
167030xcc800062,
167040xcc400045,
167050xcc400048,
167060x7c40c000,
167070xcc41225c,
167080xcc41a1fc,
167090x7c408000,
167100xa0000000,
167110xcc800062,
167120xcc000045,
167130xcc000048,
167140xcc41225c,
167150xcc41a1fc,
167160x7c408000,
167170xa0000000,
167180xcc800062,
167190x040ca1fd,
167200xc0120001,
167210xcc000045,
167220xcc000048,
167230x7cd0c00c,
167240xcc41225c,
167250xcc41a1fc,
167260xd04d0000,
167270x7c408000,
167280xa0000000,
167290xcc800062,
167300x80000001,
167310xcc41225d,
167320x7c408000,
167330x7c40c000,
167340xc02a0002,
167350x7c410000,
167360x7d29000c,
167370x30940001,
167380x30980006,
167390x309c0300,
167400x29dc0008,
167410x7c420000,
167420x7c424000,
167430x9540000f,
167440xc02e0004,
167450x05f02258,
167460x7f2f000c,
167470xcc310000,
167480xc8280004,
167490xccc12169,
167500xcd01216a,
167510xce81216b,
167520x0db40002,
167530xcc01216c,
167540x9740000e,
167550x0db40000,
167560x8000007b,
167570xc834000a,
167580x0db40002,
167590x97400009,
167600x0db40000,
167610xc02e0004,
167620x05f02258,
167630x7f2f000c,
167640xcc310000,
167650xc8280004,
167660x8000007b,
167670xc834000a,
167680x97400004,
167690x7e028000,
167700x8000007b,
167710xc834000a,
167720x0db40004,
167730x9740ff8c,
167740x00000000,
167750xce01216d,
167760xce41216e,
167770xc8280003,
167780xc834000a,
167790x9b400004,
167800x043c0005,
167810x8400026d,
167820xcc000062,
167830x0df40000,
167840x9740000b,
167850xc82c03e6,
167860xce81a2b7,
167870xc0300006,
167880x7ef34028,
167890xc0300020,
167900x7f6b8020,
167910x7fb3c029,
167920xcf81a2c4,
167930x80000001,
167940xcfc1a2d1,
167950x0df40001,
167960x9740000b,
167970xc82c03e7,
167980xce81a2bb,
167990xc0300006,
168000x7ef34028,
168010xc0300020,
168020x7f6b8020,
168030x7fb3c029,
168040xcf81a2c5,
168050x80000001,
168060xcfc1a2d2,
168070x0df40002,
168080x9740000b,
168090xc82c03e8,
168100xce81a2bf,
168110xc0300006,
168120x7ef34028,
168130xc0300020,
168140x7f6b8020,
168150x7fb3c029,
168160xcf81a2c6,
168170x80000001,
168180xcfc1a2d3,
168190xc82c03e9,
168200xce81a2c3,
168210xc0300006,
168220x7ef34028,
168230xc0300020,
168240x7f6b8020,
168250x7fb3c029,
168260xcf81a2c7,
168270x80000001,
168280xcfc1a2d4,
168290x80000001,
168300xcc400042,
168310x7c40c000,
168320x7c410000,
168330x2914001d,
168340x31540001,
168350x9940000d,
168360x31181000,
168370xc81c0011,
168380x09dc0001,
168390x95c0ffff,
168400xc81c0011,
168410xccc12100,
168420xcd012101,
168430xccc12102,
168440xcd012103,
168450x04180004,
168460x8000039f,
168470xcd81a2a4,
168480xc02a0004,
168490x95800008,
168500x36a821a3,
168510xcc290000,
168520xc8280004,
168530xc81c0011,
168540x0de40040,
168550x9640ffff,
168560xc81c0011,
168570xccc12170,
168580xcd012171,
168590xc8200012,
168600x96000000,
168610xc8200012,
168620x8000039f,
168630xcc000064,
168640x7c40c000,
168650x7c410000,
168660xcc000045,
168670xcc000048,
168680x40d40003,
168690xcd41225c,
168700xcd01a1fc,
168710xc01a0001,
168720x041ca1fd,
168730x7dd9c00c,
168740x7c420000,
168750x08cc0001,
168760x06240001,
168770x06280002,
168780xce1d0000,
168790xce5d0000,
168800x98c0fffa,
168810xce9d0000,
168820x7c408000,
168830xa0000000,
168840xcc800062,
168850x7c40c000,
168860x30d00001,
168870x28cc0001,
168880x7c414000,
168890x95000006,
168900x7c418000,
168910xcd41216d,
168920xcd81216e,
168930x800000f3,
168940xc81c0003,
168950xc0220004,
168960x7e16000c,
168970xcc210000,
168980xc81c0004,
168990x7c424000,
169000x98c00004,
169010x7c428000,
169020x80000001,
169030xcde50000,
169040xce412169,
169050xce81216a,
169060xcdc1216b,
169070x80000001,
169080xcc01216c,
169090x7c40c000,
169100x7c410000,
169110x7c414000,
169120x7c418000,
169130x7c41c000,
169140x28a40008,
169150x326400ff,
169160x0e68003c,
169170x9680000a,
169180x7c020000,
169190x7c420000,
169200x1e300003,
169210xcc00006a,
169220x9b000003,
169230x42200005,
169240x04200040,
169250x80000110,
169260x7c024000,
169270x7e024000,
169280x9a400000,
169290x0a640001,
169300x30ec0010,
169310x9ac0000a,
169320xcc000062,
169330xc02a0004,
169340xc82c0021,
169350x7e92800c,
169360xcc000041,
169370xcc290000,
169380xcec00021,
169390x80000120,
169400xc8300004,
169410xcd01216d,
169420xcd41216e,
169430xc8300003,
169440x7f1f000b,
169450x30f40007,
169460x27780001,
169470x9740002a,
169480x07b80125,
169490x9f800000,
169500x00000000,
169510x80000135,
169520x7f1b8004,
169530x80000139,
169540x7f1b8005,
169550x8000013d,
169560x7f1b8002,
169570x80000141,
169580x7f1b8003,
169590x80000145,
169600x7f1b8007,
169610x80000149,
169620x7f1b8006,
169630x8000014e,
169640x28a40008,
169650x9b800019,
169660x28a40008,
169670x8000015e,
169680x326400ff,
169690x9b800015,
169700x28a40008,
169710x8000015e,
169720x326400ff,
169730x9b800011,
169740x28a40008,
169750x8000015e,
169760x326400ff,
169770x9b80000d,
169780x28a40008,
169790x8000015e,
169800x326400ff,
169810x9b800009,
169820x28a40008,
169830x8000015e,
169840x326400ff,
169850x9b800005,
169860x28a40008,
169870x8000015e,
169880x326400ff,
169890x28a40008,
169900x326400ff,
169910x0e68003c,
169920x9a80feb1,
169930x28ec0008,
169940x7c434000,
169950x7c438000,
169960x7c43c000,
169970x96c00007,
169980xcc000062,
169990xcf412169,
170000xcf81216a,
170010xcfc1216b,
170020x80000001,
170030xcc01216c,
170040x80000001,
170050xcff50000,
170060xcc00006b,
170070x840003a2,
170080x0e68003c,
170090x9a800004,
170100xc8280015,
170110x80000001,
170120xd040007f,
170130x9680ffab,
170140x7e024000,
170150x8400023b,
170160xc00e0002,
170170xcc000041,
170180x80000239,
170190xccc1304a,
170200x7c40c000,
170210x7c410000,
170220xc01e0001,
170230x29240012,
170240xc0220002,
170250x96400005,
170260xc0260004,
170270xc027fffb,
170280x7d25000b,
170290xc0260000,
170300x7dd2800b,
170310x7e12c00b,
170320x7d25000c,
170330x7c414000,
170340x7c418000,
170350xccc12169,
170360x9a80000a,
170370xcd01216a,
170380xcd41216b,
170390x96c0fe82,
170400xcd81216c,
170410xc8300018,
170420x97000000,
170430xc8300018,
170440x80000001,
170450xcc000018,
170460x840003a2,
170470xcc00007f,
170480xc8140013,
170490xc8180014,
170500xcd41216b,
170510x96c0fe76,
170520xcd81216c,
170530x80000182,
170540xc8300018,
170550xc80c0008,
170560x98c00000,
170570xc80c0008,
170580x7c410000,
170590x95000002,
170600x00000000,
170610x7c414000,
170620xc8200009,
170630xcc400043,
170640xce01a1f4,
170650xcc400044,
170660xc00e8000,
170670x7c424000,
170680x7c428000,
170690x2aac001f,
170700x96c0fe63,
170710xc035f000,
170720xce4003e2,
170730x32780003,
170740x267c0008,
170750x7ff7c00b,
170760x7ffbc00c,
170770x2a780018,
170780xcfc003e3,
170790xcf8003e4,
170800x26b00002,
170810x7f3f0000,
170820xcf0003e5,
170830x8000031f,
170840x7c80c000,
170850x7c40c000,
170860x28d00008,
170870x3110000f,
170880x9500000f,
170890x25280001,
170900x06a801b3,
170910x9e800000,
170920x00000000,
170930x800001d4,
170940xc0120800,
170950x800001e2,
170960xc814000f,
170970x800001e9,
170980xc8140010,
170990x800001f0,
171000xccc1a2a4,
171010x800001f9,
171020xc8140011,
171030x30d0003f,
171040x0d280015,
171050x9a800012,
171060x0d28001e,
171070x9a80001e,
171080x0d280020,
171090x9a800023,
171100x0d24000f,
171110x0d280010,
171120x7e6a800c,
171130x9a800026,
171140x0d200004,
171150x0d240014,
171160x0d280028,
171170x7e62400c,
171180x7ea6800c,
171190x9a80002a,
171200xc8140011,
171210x80000001,
171220xccc1a2a4,
171230xc0120800,
171240x7c414000,
171250x7d0cc00c,
171260xc0120008,
171270x29580003,
171280x295c000c,
171290x7c420000,
171300x7dd1c00b,
171310x26200014,
171320x7e1e400c,
171330x7e4e800c,
171340xce81a2a4,
171350x80000001,
171360xcd81a1fe,
171370xc814000f,
171380x0410210e,
171390x95400000,
171400xc814000f,
171410xd0510000,
171420x80000001,
171430xccc1a2a4,
171440xc8140010,
171450x04102108,
171460x95400000,
171470xc8140010,
171480xd0510000,
171490x80000001,
171500xccc1a2a4,
171510xccc1a2a4,
171520x04100001,
171530xcd000019,
171540x840003a2,
171550xcc00007f,
171560xc8100019,
171570x99000000,
171580xc8100019,
171590x80000002,
171600x7c408000,
171610x04102100,
171620x09540001,
171630x9540ffff,
171640xc8140011,
171650xd0510000,
171660x8000039f,
171670xccc1a2a4,
171680x7c40c000,
171690xcc40000d,
171700x94c0fdff,
171710xcc40000e,
171720x7c410000,
171730x95000005,
171740x08cc0001,
171750xc8140005,
171760x99400014,
171770x00000000,
171780x98c0fffb,
171790x7c410000,
171800x80000002,
171810x7d008000,
171820xc8140005,
171830x7c40c000,
171840x9940000c,
171850xc818000c,
171860x7c410000,
171870x9580fdee,
171880xc820000e,
171890xc81c000d,
171900x66200020,
171910x7e1e002c,
171920x25240002,
171930x7e624020,
171940x80000001,
171950xcce60000,
171960x7c410000,
171970xcc00006c,
171980xcc00006d,
171990xc818001f,
172000xc81c001e,
172010x65980020,
172020x7dd9c02c,
172030x7cd4c00c,
172040xccde0000,
172050x45dc0004,
172060xc8280017,
172070x9680000f,
172080xc00e0001,
172090x28680008,
172100x2aac0016,
172110x32a800ff,
172120x0eb00049,
172130x7f2f000b,
172140x97000006,
172150x00000000,
172160xc8140005,
172170x7c40c000,
172180x80000223,
172190x7c410000,
172200x80000226,
172210xd040007f,
172220x8400023b,
172230xcc000041,
172240xccc1304a,
172250x94000000,
172260xc83c001a,
172270x043c0005,
172280xcfc1a2a4,
172290xc0361f90,
172300xc0387fff,
172310x7c03c010,
172320x7f7b400c,
172330xcf41217c,
172340xcfc1217d,
172350xcc01217e,
172360xc03a0004,
172370x0434217f,
172380x7f7b400c,
172390xcc350000,
172400xc83c0004,
172410x2bfc001f,
172420x04380020,
172430x97c00005,
172440xcc000062,
172450x9b800000,
172460x0bb80001,
172470x80000247,
172480xcc000071,
172490xcc01a1f4,
172500x04380016,
172510xc0360002,
172520xcf81a2a4,
172530x88000000,
172540xcf412010,
172550x7c40c000,
172560x28d0001c,
172570x95000005,
172580x04d40001,
172590xcd400065,
172600x80000001,
172610xcd400068,
172620x09540002,
172630x80000001,
172640xcd400066,
172650x8400026c,
172660xc81803ea,
172670x7c40c000,
172680x9980fd9d,
172690xc8140016,
172700x08d00001,
172710x9940002b,
172720xcd000068,
172730x7c408000,
172740xa0000000,
172750xcc800062,
172760x043c0005,
172770xcfc1a2a4,
172780xcc01a1f4,
172790x840003a2,
172800xcc000046,
172810x88000000,
172820xcc00007f,
172830x8400027e,
172840xc81803ea,
172850x7c40c000,
172860x9980fd8b,
172870xc8140016,
172880x08d00001,
172890x99400019,
172900xcd000068,
172910x7c408000,
172920xa0000000,
172930xcc800062,
172940x043c0022,
172950xcfc1a2a4,
172960x840003a2,
172970xcc000047,
172980x88000000,
172990xcc00007f,
173000xc8100016,
173010x9900000d,
173020xcc400067,
173030x80000002,
173040x7c408000,
173050xc81803ea,
173060x9980fd77,
173070x7c40c000,
173080x94c00003,
173090xc8100016,
173100x99000004,
173110xccc00068,
173120x80000002,
173130x7c408000,
173140x8400023b,
173150xc0148000,
173160xcc000041,
173170xcd41304a,
173180xc0148000,
173190x99000000,
173200xc8100016,
173210x80000002,
173220x7c408000,
173230xc0120001,
173240x7c51400c,
173250x80000001,
173260xd0550000,
173270x7c40c000,
173280x7c410000,
173290x7c414000,
173300x7c418000,
173310x291c001f,
173320xccc0004a,
173330xcd00004b,
173340x95c00003,
173350xc01c8000,
173360xcdc12010,
173370xdd830000,
173380x055c2000,
173390xcc000062,
173400x80000001,
173410xd81f4100,
173420x7c40c000,
173430x7c410000,
173440x7c414000,
173450x7c418000,
173460xccc0004c,
173470xcd00004d,
173480xdd830000,
173490x055ca000,
173500x80000001,
173510xd81f4100,
173520x7c40c000,
173530x7c410000,
173540x7c414000,
173550x7c418000,
173560xccc0004e,
173570xcd00004f,
173580xdd830000,
173590x055cc000,
173600x80000001,
173610xd81f4100,
173620x7c40c000,
173630x7c410000,
173640x7c414000,
173650x7c418000,
173660xccc00050,
173670xcd000051,
173680xdd830000,
173690x055cf8e0,
173700x80000001,
173710xd81f4100,
173720x7c40c000,
173730x7c410000,
173740x7c414000,
173750x7c418000,
173760xccc00052,
173770xcd000053,
173780xdd830000,
173790x055cf880,
173800x80000001,
173810xd81f4100,
173820x7c40c000,
173830x7c410000,
173840x7c414000,
173850x7c418000,
173860xccc00054,
173870xcd000055,
173880xdd830000,
173890x055ce000,
173900x80000001,
173910xd81f4100,
173920x7c40c000,
173930x7c410000,
173940x7c414000,
173950x7c418000,
173960xccc00056,
173970xcd000057,
173980xdd830000,
173990x055cf000,
174000x80000001,
174010xd81f4100,
174020x7c40c000,
174030x7c410000,
174040x7c414000,
174050x7c418000,
174060xccc00058,
174070xcd000059,
174080xdd830000,
174090x055cf3fc,
174100x80000001,
174110xd81f4100,
174120xd0432000,
174130x7c408000,
174140xa0000000,
174150xcc800062,
174160xd043a000,
174170x7c408000,
174180xa0000000,
174190xcc800062,
174200xd043c000,
174210x7c408000,
174220xa0000000,
174230xcc800062,
174240xd043f8e0,
174250x7c408000,
174260xa0000000,
174270xcc800062,
174280xd043f880,
174290x7c408000,
174300xa0000000,
174310xcc800062,
174320xd043e000,
174330x7c408000,
174340xa0000000,
174350xcc800062,
174360xd043f000,
174370x7c408000,
174380xa0000000,
174390xcc800062,
174400xd043f3fc,
174410x7c408000,
174420xa0000000,
174430xcc800062,
174440xc81403e0,
174450xcc430000,
174460xcc430000,
174470xcc430000,
174480x7d45c000,
174490xcdc30000,
174500xd0430000,
174510x7c408000,
174520xa0000000,
174530xcc800062,
174540x7c40c000,
174550xc81003e2,
174560xc81403e5,
174570xc81803e3,
174580xc81c03e4,
174590xcd812169,
174600xcdc1216a,
174610xccc1216b,
174620xcc01216c,
174630x04200004,
174640x7da18000,
174650x7d964002,
174660x9640fcd7,
174670xcd8003e3,
174680x31280003,
174690xc02df000,
174700x25180008,
174710x7dad800b,
174720x7da9800c,
174730x80000001,
174740xcd8003e3,
174750x308cffff,
174760xd04d0000,
174770x7c408000,
174780xa0000000,
174790xcc800062,
174800x7c40c000,
174810x7c410000,
174820x29240018,
174830x32640001,
174840x9a400013,
174850xc8140020,
174860x15580002,
174870x9580ffff,
174880xc8140020,
174890xcc00006e,
174900xccc12180,
174910xcd01218d,
174920xcc412181,
174930x2914001f,
174940x34588000,
174950xcd81218c,
174960x9540fcb9,
174970xcc412182,
174980xc8140020,
174990x9940ffff,
175000xc8140020,
175010x80000002,
175020x7c408000,
175030x7c414000,
175040x7c418000,
175050x7c41c000,
175060x65b40020,
175070x7f57402c,
175080xd4378100,
175090x47740004,
175100xd4378100,
175110x47740004,
175120xd4378100,
175130x47740004,
175140x09dc0004,
175150xd4378100,
175160x99c0fff8,
175170x47740004,
175180x2924001f,
175190xc0380019,
175200x9640fca1,
175210xc03e0004,
175220xcf8121f8,
175230x37e021f9,
175240xcc210000,
175250xc8200004,
175260x2a200018,
175270x32200001,
175280x9a00fffb,
175290xcf8121f8,
175300x80000002,
175310x7c408000,
175320x7c40c000,
175330x28d00018,
175340x31100001,
175350xc0160080,
175360x95000003,
175370xc02a0004,
175380x7cd4c00c,
175390xccc1217c,
175400xcc41217d,
175410xcc41217e,
175420x7c418000,
175430x1db00003,
175440x36a0217f,
175450x9b000003,
175460x419c0005,
175470x041c0040,
175480x99c00000,
175490x09dc0001,
175500xcc210000,
175510xc8240004,
175520x2a6c001f,
175530x419c0005,
175540x9ac0fffa,
175550xcc800062,
175560x80000002,
175570x7c408000,
175580x7c40c000,
175590x04d403e6,
175600x80000001,
175610xcc540000,
175620x8000039f,
175630xcc4003ea,
175640xc01c8000,
175650x044ca000,
175660xcdc12010,
175670x7c410000,
175680xc8140009,
175690x04180000,
175700x041c0008,
175710xcd800071,
175720x09dc0001,
175730x05980001,
175740xcd0d0000,
175750x99c0fffc,
175760xcc800062,
175770x8000039f,
175780xcd400071,
175790xc00e0100,
175800xcc000041,
175810xccc1304a,
175820xc83c007f,
175830xcc00007f,
175840x80000001,
175850xcc00007f,
175860xcc00007f,
175870x88000000,
175880xcc00007f,
175890x00000000,
175900x00000000,
175910x00000000,
175920x00000000,
175930x00000000,
175940x00000000,
175950x00000000,
175960x00000000,
175970x00000000,
175980x00000000,
175990x00000000,
176000x00000000,
176010x00000000,
176020x00000000,
176030x00000000,
176040x00000000,
176050x00000000,
176060x00000000,
176070x00000000,
176080x00000000,
176090x00000000,
176100x00000000,
176110x00000000,
176120x00000000,
176130x00000000,
176140x00000000,
176150x00000000,
176160x00000000,
176170x00000000,
176180x00000000,
176190x00000000,
176200x00000000,
176210x00000000,
176220x00000000,
176230x00000000,
176240x00000000,
176250x00000000,
176260x00000000,
176270x00000000,
176280x00000000,
176290x00000000,
176300x00000000,
176310x00000000,
176320x00000000,
176330x00000000,
176340x00000000,
176350x00000000,
176360x00000000,
176370x00000000,
176380x00000000,
176390x00000000,
176400x00000000,
176410x00000000,
176420x00000000,
176430x00000000,
176440x00000000,
176450x00000000,
176460x00000000,
176470x00000000,
176480x00000000,
176490x00000000,
176500x00000000,
176510x00000000,
176520x00000000,
176530x00000000,
176540x00000000,
176550x00000000,
176560x00000000,
176570x00000000,
176580x00000000,
176590x00000000,
176600x00000000,
176610x00000000,
176620x00000000,
176630x00000000,
176640x00000000,
176650x00000000,
176660x00000000,
176670x00000000,
176680x00000000,
176690x00000000,
176700x00000000,
176710x00000000,
176720x00000000,
176730x00000000,
176740x00000000,
176750x00000000,
176760x00000000,
176770x00000000,
176780x00000000,
176790x00000000,
176800x00000000,
176810x00000000,
176820x00000000,
176830x00000000,
176840x00000000,
176850x00000000,
176860x00000000,
176870x00000000,
176880x00000000,
176890x00000000,
176900x00000000,
176910x00000000,
176920x00000000,
176930x00000000,
176940x00000000,
176950x00000000,
176960x00000000,
176970x00000000,
176980x00000000,
176990x00000000,
177000x00000000,
177010x00000000,
177020x00000000,
177030x00000000,
177040x00000000,
177050x00000000,
177060x00000000,
177070x00000000,
177080x00000000,
177090x00000000,
177100x00000000,
177110x00000000,
177120x00000000,
177130x00000000,
177140x00000000,
177150x00000000,
177160x00000000,
177170x00000000,
177180x00000000,
177190x00000000,
177200x00000000,
177210x00000000,
177220x00000000,
177230x00000000,
177240x00000000,
177250x00000000,
177260x00000000,
177270x00000000,
177280x00000000,
177290x00000000,
177300x00000000,
177310x00000000,
177320x00000000,
177330x00000000,
177340x00000000,
177350x00000000,
177360x00000000,
177370x00000000,
177380x00000000,
177390x00000000,
177400x00000000,
177410x00000000,
177420x00000000,
177430x00000000,
177440x00000000,
177450x00000000,
177460x00000000,
177470x00000000,
177480x00000000,
177490x00000000,
177500x00000000,
177510x00000000,
177520x00000000,
177530x00000000,
177540x00000000,
177550x00000000,
177560x00000000,
177570x00000000,
177580x00000000,
177590x00000000,
177600x00000000,
177610x00000000,
177620x00000000,
177630x00000000,
177640x00000000,
177650x00000000,
177660x00000000,
177670x00000000,
177680x00000000,
177690x00000000,
177700x00000000,
177710x00000000,
177720x00000000,
177730x00000000,
177740x00000000,
177750x00000000,
177760x00000000,
177770x00000000,
177780x00000000,
177790x00000000,
177800x00000000,
177810x00000000,
177820x00000000,
177830x00000000,
177840x00000000,
177850x00000000,
177860x00000000,
177870x00000000,
177880x00000000,
177890x00000000,
177900x00000000,
177910x00000000,
177920x00000000,
177930x00000000,
177940x00000000,
177950x00000000,
177960x00000000,
177970x00000000,
177980x00000000,
177990x00000000,
178000x00000000,
178010x00000000,
178020x00000000,
178030x00000000,
178040x00000000,
178050x00000000,
178060x00000000,
178070x00000000,
178080x00000000,
178090x00000000,
178100x00000000,
178110x00000000,
178120x00000000,
178130x00000000,
178140x00000000,
178150x00000000,
178160x00000000,
178170x00000000,
178180x00000000,
178190x00000000,
178200x00000000,
178210x00000000,
178220x00000000,
178230x00000000,
178240x00000000,
178250x00000000,
178260x00000000,
178270x00000000,
178280x00000000,
178290x00000000,
178300x00000000,
178310x00000000,
178320x00000000,
178330x00000000,
178340x00000000,
178350x00000000,
178360x00000000,
178370x00000000,
178380x00000000,
178390x00000000,
178400x00000000,
178410x00000000,
178420x00000000,
178430x00000000,
178440x00000000,
178450x00000000,
178460x00000000,
178470x00000000,
178480x00000000,
178490x00000000,
178500x00000000,
178510x00000000,
178520x00000000,
178530x00000000,
178540x00000000,
178550x00000000,
178560x00000000,
178570x00000000,
178580x00000000,
178590x00000000,
178600x00000000,
178610x00000000,
178620x00000000,
178630x00000000,
178640x00000000,
178650x00000000,
178660x00000000,
178670x00000000,
178680x00000000,
178690x00000000,
178700x00000000,
178710x00000000,
178720x00000000,
178730x00000000,
178740x00000000,
178750x00000000,
178760x00000000,
178770x00000000,
178780x00000000,
178790x00000000,
178800x00000000,
178810x00000000,
178820x00000000,
178830x00000000,
178840x00000000,
178850x00000000,
178860x00000000,
178870x00000000,
178880x00000000,
178890x00000000,
178900x00000000,
178910x00000000,
178920x00000000,
178930x00000000,
178940x00000000,
178950x00000000,
178960x00000000,
178970x00000000,
178980x00000000,
178990x00000000,
179000x00000000,
179010x00000000,
179020x00000000,
179030x00000000,
179040x00000000,
179050x00000000,
179060x00000000,
179070x00000000,
179080x00000000,
179090x00000000,
179100x00000000,
179110x00000000,
179120x00000000,
179130x00000000,
179140x00000000,
179150x00000000,
179160x00000000,
179170x00000000,
179180x00000000,
179190x00000000,
179200x00000000,
179210x00000000,
179220x00000000,
179230x00000000,
179240x00000000,
179250x00000000,
179260x00000000,
179270x00000000,
179280x00000000,
179290x00000000,
179300x00000000,
179310x00000000,
179320x00000000,
179330x00000000,
179340x00000000,
179350x00000000,
179360x00010333,
179370x00100004,
179380x00170006,
179390x00210008,
179400x00270028,
179410x00280023,
179420x00290029,
179430x002a0026,
179440x002b0029,
179450x002d0038,
179460x002e003f,
179470x002f004a,
179480x0034004c,
179490x00360030,
179500x003900af,
179510x003a00d0,
179520x003b00e5,
179530x003c00fd,
179540x003d016c,
179550x003f00ad,
179560x00410338,
179570x0043036c,
179580x0044018f,
179590x004500fd,
179600x004601ad,
179610x004701ad,
179620x00480200,
179630x0049020e,
179640x004a0257,
179650x004b0284,
179660x00520261,
179670x00530273,
179680x00540289,
179690x0057029b,
179700x0060029f,
179710x006102ae,
179720x006202b8,
179730x006302c2,
179740x006402cc,
179750x006502d6,
179760x006602e0,
179770x006702ea,
179780x006802f4,
179790x006902f8,
179800x006a02fc,
179810x006b0300,
179820x006c0304,
179830x006d0308,
179840x006e030c,
179850x006f0310,
179860x00700314,
179870x00720386,
179880x0074038c,
179890x0079038a,
179900x007c031e,
179910x000f039b,
179920x000f039b,
179930x000f039b,
179940x000f039b,
179950x000f039b,
179960x000f039b,
179970x000f039b,
179980x000f039b,
179990x000f039b,
180000x000f039b,
180010x000f039b,
180020x000f039b,
180030x000f039b,
180040x000f039b,
180050x000f039b,
180060x000f039b,
180070x000f039b,
180080x000f039b,
180090x000f039b,
180100x000f039b,
180110x000f039b,
180120x000f039b,
180130x000f039b,
180140x000f039b,
180150x000f039b,
18016};
18017
18018static const u32 RV770_pfp_microcode[] = {
180190x7c408000,
180200xa0000000,
180210x7e82800b,
180220x80000000,
180230xdc030000,
180240xcc800040,
180250xd0400040,
180260x7c408000,
180270xa0000000,
180280x7e82800b,
180290xc818000e,
180300x31980001,
180310x7c424000,
180320x95800252,
180330x7c428000,
180340xc81c001c,
180350xc037c000,
180360x7c40c000,
180370x7c410000,
180380x7cb4800b,
180390xc0360003,
180400x99c00000,
180410xc81c001c,
180420x7cb4800c,
180430x24d40002,
180440x7d654000,
180450xcd400043,
180460xce800043,
180470xcd000043,
180480xcc800040,
180490xce400040,
180500xce800040,
180510xccc00040,
180520xdc3a0000,
180530x9780ffde,
180540xcd000040,
180550x7c40c000,
180560x80000018,
180570x7c410000,
180580xd4000340,
180590xd4000fc0,
180600xd4000fa2,
180610xc818000e,
180620x8000000c,
180630x31980002,
180640xd40003c0,
180650xd4000fc0,
180660xd4000fa2,
180670xc818000e,
180680x288c0008,
180690x30cc000f,
180700x34100001,
180710x7d0d0008,
180720x8000000c,
180730x7d91800b,
180740xcc800040,
180750xd0400040,
180760x7c408000,
180770xa0000000,
180780x7e82800b,
180790xd4000340,
180800xd4000fc0,
180810xd4000fa2,
180820xcc800040,
180830xd0400040,
180840x7c408000,
180850xa0000000,
180860x7e82800b,
180870xd40003c0,
180880xd4000fc0,
180890xd4000fa2,
180900xcc800040,
180910xd0400040,
180920x7c408000,
180930xa0000000,
180940x7e82800b,
180950xcc4003f9,
180960x80000261,
180970xcc4003f8,
180980xc82003f8,
180990xc81c03f9,
181000xc81803fb,
181010xc037ffff,
181020x7c414000,
181030xcf41a29e,
181040x66200020,
181050x7de1c02c,
181060x7d58c008,
181070x7cdcc020,
181080x68d00020,
181090xc0360003,
181100xcc000054,
181110x7cb4800c,
181120x8000006a,
181130xcc800040,
181140x7c418000,
181150xcd81a29e,
181160xcc800040,
181170xcd800040,
181180x80000068,
181190xcc000054,
181200xc019ffff,
181210xcc800040,
181220xcd81a29e,
181230x7c40c000,
181240x7c410000,
181250x7c414000,
181260xccc1a1fa,
181270xcd01a1f9,
181280xcd41a29d,
181290xccc00040,
181300xcd000040,
181310xcd400040,
181320xcc400040,
181330x7c408000,
181340xa0000000,
181350x7e82800b,
181360xcc000054,
181370xcc800040,
181380x7c40c000,
181390x7c410000,
181400x7c414000,
181410xccc1a1fa,
181420xcd01a1f9,
181430xcd41a29d,
181440xccc00040,
181450xcd000040,
181460xcd400040,
181470xd0400040,
181480x7c408000,
181490xa0000000,
181500x7e82800b,
181510x7c40c000,
181520x30d00001,
181530xccc1a29f,
181540x95000003,
181550x04140001,
181560x04140002,
181570xcd4003fb,
181580xcc800040,
181590x80000000,
181600xccc00040,
181610x7c40c000,
181620xcc800040,
181630xccc1a2a2,
181640x80000000,
181650xccc00040,
181660x7c40c000,
181670x28d4001f,
181680xcc800040,
181690x95400003,
181700x7c410000,
181710xccc00057,
181720x2918001f,
181730xccc00040,
181740x95800003,
181750xcd000040,
181760xcd000058,
181770x80000261,
181780xcc00007f,
181790xc8200017,
181800xc8300022,
181810x9a000006,
181820x0e280001,
181830xc824001e,
181840x0a640001,
181850xd4001240,
181860xce400040,
181870xc036c000,
181880x96800007,
181890x37747900,
181900x041c0001,
181910xcf400040,
181920xcdc00040,
181930xcf0003fa,
181940x7c030000,
181950xca0c0010,
181960x7c410000,
181970x94c00004,
181980x7c414000,
181990xd42002c4,
182000xcde00044,
182010x9b00000b,
182020x7c418000,
182030xcc00004b,
182040xcda00049,
182050xcd200041,
182060xcd600041,
182070xcda00041,
182080x06200001,
182090xce000056,
182100x80000261,
182110xcc00007f,
182120xc8280020,
182130xc82c0021,
182140xcc000063,
182150x7eea4001,
182160x65740020,
182170x7f53402c,
182180x269c0002,
182190x7df5c020,
182200x69f80020,
182210xce80004b,
182220xce600049,
182230xcde00041,
182240xcfa00041,
182250xce600041,
182260x271c0002,
182270x7df5c020,
182280x69f80020,
182290x7db24001,
182300xcf00004b,
182310xce600049,
182320xcde00041,
182330xcfa00041,
182340x800000bd,
182350xce600041,
182360xc8200017,
182370xc8300022,
182380x9a000006,
182390x0e280001,
182400xc824001e,
182410x0a640001,
182420xd4001240,
182430xce400040,
182440xca0c0010,
182450x7c410000,
182460x94c0000b,
182470xc036c000,
182480x96800007,
182490x37747900,
182500x041c0001,
182510xcf400040,
182520xcdc00040,
182530xcf0003fa,
182540x7c030000,
182550x800000b6,
182560x7c414000,
182570xcc000048,
182580x800000ef,
182590x00000000,
182600xc8200017,
182610xc81c0023,
182620x0e240002,
182630x99c00015,
182640x7c418000,
182650x0a200001,
182660xce000056,
182670xd4000440,
182680xcc000040,
182690xc036c000,
182700xca140013,
182710x96400007,
182720x37747900,
182730xcf400040,
182740xcc000040,
182750xc83003fa,
182760x80000104,
182770xcf000022,
182780xcc000022,
182790x9540015d,
182800xcc00007f,
182810xcca00046,
182820x80000000,
182830xcc200046,
182840x80000261,
182850xcc000064,
182860xc8200017,
182870xc810001f,
182880x96000005,
182890x09100001,
182900xd4000440,
182910xcd000040,
182920xcd000022,
182930xcc800040,
182940xd0400040,
182950xc80c0025,
182960x94c0feeb,
182970xc8100008,
182980xcd000040,
182990xd4000fc0,
183000x80000000,
183010xd4000fa2,
183020x7c40c000,
183030x7c410000,
183040xccc003fd,
183050xcd0003fc,
183060xccc00042,
183070xcd000042,
183080x2914001f,
183090x29180010,
183100x31980007,
183110x3b5c0001,
183120x7d76000b,
183130x99800005,
183140x7d5e400b,
183150xcc000042,
183160x80000261,
183170xcc00004d,
183180x29980001,
183190x292c0008,
183200x9980003d,
183210x32ec0001,
183220x96000004,
183230x2930000c,
183240x80000261,
183250xcc000042,
183260x04140010,
183270xcd400042,
183280x33300001,
183290x34280001,
183300x8400015e,
183310xc8140003,
183320x9b40001b,
183330x0438000c,
183340x8400015e,
183350xc8140003,
183360x9b400017,
183370x04380008,
183380x8400015e,
183390xc8140003,
183400x9b400013,
183410x04380004,
183420x8400015e,
183430xc8140003,
183440x9b400015,
183450xc80c03fd,
183460x9a800009,
183470xc81003fc,
183480x9b000118,
183490xcc00004d,
183500x04140010,
183510xccc00042,
183520xcd000042,
183530x80000136,
183540xcd400042,
183550x96c00111,
183560xcc00004d,
183570x80000261,
183580xcc00004e,
183590x9ac00003,
183600xcc00004d,
183610xcc00004e,
183620xdf830000,
183630x80000000,
183640xd80301ff,
183650x9ac00107,
183660xcc00004d,
183670x80000261,
183680xcc00004e,
183690xc8180003,
183700xc81c0003,
183710xc8200003,
183720x7d5d4003,
183730x7da1c003,
183740x7d5d400c,
183750x2a10001f,
183760x299c001f,
183770x7d1d000b,
183780x7d17400b,
183790x88000000,
183800x7e92800b,
183810x96400004,
183820xcc00004e,
183830x80000261,
183840xcc000042,
183850x04380008,
183860xcf800042,
183870xc8080003,
183880xc80c0003,
183890xc8100003,
183900xc8140003,
183910xc8180003,
183920xc81c0003,
183930xc8240003,
183940xc8280003,
183950x29fc001f,
183960x2ab0001f,
183970x7ff3c00b,
183980x28f0001f,
183990x7ff3c00b,
184000x2970001f,
184010x7ff3c00b,
184020x7d888001,
184030x7dccc001,
184040x7e510001,
184050x7e954001,
184060x7c908002,
184070x7cd4c002,
184080x7cbc800b,
184090x9ac00003,
184100x7c8f400b,
184110x38b40001,
184120x9b4000d8,
184130xcc00004d,
184140x9bc000d6,
184150xcc00004e,
184160xc80c03fd,
184170xc81003fc,
184180xccc00042,
184190x8000016f,
184200xcd000042,
184210xd4000340,
184220xd4000fc0,
184230xd4000fa2,
184240xcc800040,
184250xcc400040,
184260xcc400040,
184270xcc400040,
184280x7c40c000,
184290xccc00040,
184300xccc0000d,
184310x80000000,
184320xd0400040,
184330x7c40c000,
184340x7c410000,
184350x65140020,
184360x7d4d402c,
184370x24580002,
184380x7d598020,
184390x7c41c000,
184400xcd800042,
184410x69980020,
184420xcd800042,
184430xcdc00042,
184440xc023c000,
184450x05e40002,
184460x7ca0800b,
184470x26640010,
184480x7ca4800c,
184490xcc800040,
184500xcdc00040,
184510xccc00040,
184520x95c0000e,
184530xcd000040,
184540x09dc0001,
184550xc8280003,
184560x96800008,
184570xce800040,
184580xc834001d,
184590x97400000,
184600xc834001d,
184610x26a80008,
184620x84000264,
184630xcc2b0000,
184640x99c0fff7,
184650x09dc0001,
184660xdc3a0000,
184670x97800004,
184680x7c418000,
184690x800001a3,
184700x25980002,
184710xa0000000,
184720x7d808000,
184730xc818001d,
184740x7c40c000,
184750x64d00008,
184760x95800000,
184770xc818001d,
184780xcc130000,
184790xcc800040,
184800xccc00040,
184810x80000000,
184820xcc400040,
184830xc810001f,
184840x7c40c000,
184850xcc800040,
184860x7cd1400c,
184870xcd400040,
184880x05180001,
184890x80000000,
184900xcd800022,
184910x7c40c000,
184920x64500020,
184930x84000264,
184940xcc000061,
184950x7cd0c02c,
184960xc8200017,
184970xc8d60000,
184980x99400008,
184990x7c438000,
185000xdf830000,
185010xcfa0004f,
185020x84000264,
185030xcc000062,
185040x80000000,
185050xd040007f,
185060x80000261,
185070xcc000062,
185080x84000264,
185090xcc000061,
185100xc8200017,
185110x7c40c000,
185120xc036ff00,
185130xc810000d,
185140xc0303fff,
185150x7cf5400b,
185160x7d51800b,
185170x7d81800f,
185180x99800008,
185190x7cf3800b,
185200xdf830000,
185210xcfa0004f,
185220x84000264,
185230xcc000062,
185240x80000000,
185250xd040007f,
185260x80000261,
185270xcc000062,
185280x84000264,
185290x7c40c000,
185300x28dc0008,
185310x95c00019,
185320x30dc0010,
185330x7c410000,
185340x99c00004,
185350x64540020,
185360x80000209,
185370xc91d0000,
185380x7d15002c,
185390xc91e0000,
185400x7c420000,
185410x7c424000,
185420x7c418000,
185430x7de5c00b,
185440x7de28007,
185450x9a80000e,
185460x41ac0005,
185470x9ac00000,
185480x0aec0001,
185490x30dc0010,
185500x99c00004,
185510x00000000,
185520x8000020c,
185530xc91d0000,
185540x8000020c,
185550xc91e0000,
185560xcc800040,
185570xccc00040,
185580xd0400040,
185590xc80c0025,
185600x94c0fde3,
185610xc8100008,
185620xcd000040,
185630xd4000fc0,
185640x80000000,
185650xd4000fa2,
185660xd4000340,
185670xd4000fc0,
185680xd4000fa2,
185690xcc800040,
185700xd0400040,
185710x7c408000,
185720xa0000000,
185730x7e82800b,
185740xd40003c0,
185750xd4000fc0,
185760xd4000fa2,
185770xcc800040,
185780xd0400040,
185790x7c408000,
185800xa0000000,
185810x7e82800b,
185820x7c40c000,
185830x30d00006,
185840x0d100006,
185850x99000007,
185860xc8140015,
185870x99400005,
185880xcc000052,
185890xd4000340,
185900xd4000fc0,
185910xd4000fa2,
185920xcc800040,
185930xccc00040,
185940x80000000,
185950xd0400040,
185960x7c40c000,
185970xcc4d0000,
185980xdc3a0000,
185990x9780fdbc,
186000x04cc0001,
186010x80000243,
186020xcc4d0000,
186030x7c40c000,
186040x7c410000,
186050x29240018,
186060x32640001,
186070x9640000f,
186080xcc800040,
186090x7c414000,
186100x7c418000,
186110x7c41c000,
186120xccc00043,
186130xcd000043,
186140x31dc7fff,
186150xcdc00043,
186160xccc00040,
186170xcd000040,
186180xcd400040,
186190xcd800040,
186200x80000000,
186210xcdc00040,
186220xccc00040,
186230xcd000040,
186240x80000000,
186250xd0400040,
186260x80000000,
186270xd040007f,
186280xcc00007f,
186290x80000000,
186300xcc00007f,
186310xcc00007f,
186320x88000000,
186330xcc00007f,
186340x00000000,
186350x00000000,
186360x00000000,
186370x00000000,
186380x00000000,
186390x00000000,
186400x00000000,
186410x00000000,
186420x00000000,
186430x00000000,
186440x00000000,
186450x00000000,
186460x00000000,
186470x00000000,
186480x00000000,
186490x00000000,
186500x00000000,
186510x00000000,
186520x00000000,
186530x00000000,
186540x00000000,
186550x00000000,
186560x00000000,
186570x00000000,
186580x00000000,
186590x00000000,
186600x00000000,
186610x00000000,
186620x00000000,
186630x00000000,
186640x00000000,
186650x00000000,
186660x00000000,
186670x00000000,
186680x00000000,
186690x00000000,
186700x00000000,
186710x00000000,
186720x00000000,
186730x00000000,
186740x00000000,
186750x00000000,
186760x00000000,
186770x00000000,
186780x00000000,
186790x00000000,
186800x00000000,
186810x00000000,
186820x00000000,
186830x00000000,
186840x00000000,
186850x00000000,
186860x00000000,
186870x00000000,
186880x00000000,
186890x00000000,
186900x00000000,
186910x00000000,
186920x00000000,
186930x00000000,
186940x00000000,
186950x00000000,
186960x00000000,
186970x00000000,
186980x00000000,
186990x00000000,
187000x00000000,
187010x00000000,
187020x00000000,
187030x00000000,
187040x00000000,
187050x00000000,
187060x00000000,
187070x00000000,
187080x00000000,
187090x00000000,
187100x00000000,
187110x00000000,
187120x00000000,
187130x00000000,
187140x00000000,
187150x00000000,
187160x00000000,
187170x00000000,
187180x00000000,
187190x00000000,
187200x00000000,
187210x00000000,
187220x00000000,
187230x00000000,
187240x00000000,
187250x00000000,
187260x00000000,
187270x00000000,
187280x00000000,
187290x00000000,
187300x00000000,
187310x00000000,
187320x00000000,
187330x00000000,
187340x00000000,
187350x00000000,
187360x00000000,
187370x00000000,
187380x00000000,
187390x00000000,
187400x00000000,
187410x00000000,
187420x00000000,
187430x00000000,
187440x00000000,
187450x00000000,
187460x00000000,
187470x00000000,
187480x00000000,
187490x00000000,
187500x00000000,
187510x00000000,
187520x00000000,
187530x00000000,
187540x00000000,
187550x00000000,
187560x00000000,
187570x00000000,
187580x00000000,
187590x00000000,
187600x00000000,
187610x00000000,
187620x00000000,
187630x00000000,
187640x00000000,
187650x00000000,
187660x00000000,
187670x00000000,
187680x00000000,
187690x00000000,
187700x00000000,
187710x00000000,
187720x00000000,
187730x00000000,
187740x00000000,
187750x00000000,
187760x00000000,
187770x00000000,
187780x00000000,
187790x00000000,
187800x00000000,
187810x00000000,
187820x00000000,
187830x00000000,
187840x00000000,
187850x00000000,
187860x00000000,
187870x00030223,
187880x0004022b,
187890x000500a0,
187900x00020003,
187910x0006003c,
187920x00070027,
187930x00080192,
187940x00090044,
187950x000a002d,
187960x0010025f,
187970x001700f1,
187980x002201d8,
187990x002301e9,
188000x0026004c,
188010x0027005f,
188020x0020011b,
188030x00280093,
188040x0029004f,
188050x002a0084,
188060x002b0065,
188070x002f008e,
188080x003200d9,
188090x00340233,
188100x00360075,
188110x0039010b,
188120x003c01fd,
188130x003f00a0,
188140x00410248,
188150x00440195,
188160x0048019e,
188170x004901c6,
188180x004a01d0,
188190x00550226,
188200x0056022e,
188210x0060000a,
188220x0061002a,
188230x00620030,
188240x00630030,
188250x00640030,
188260x00650030,
188270x00660030,
188280x00670030,
188290x00680037,
188300x0069003f,
188310x006a0047,
188320x006b0047,
188330x006c0047,
188340x006d0047,
188350x006e0047,
188360x006f0047,
188370x00700047,
188380x0073025f,
188390x007b0241,
188400x00000005,
188410x00000005,
188420x00000005,
188430x00000005,
188440x00000005,
188450x00000005,
188460x00000005,
188470x00000005,
188480x00000005,
188490x00000005,
188500x00000005,
188510x00000005,
188520x00000005,
188530x00000005,
188540x00000005,
188550x00000005,
188560x00000005,
188570x00000005,
188580x00000005,
188590x00000005,
188600x00000005,
188610x00000005,
188620x00000005,
188630x00000005,
188640x00000005,
188650x00000005,
188660x00000005,
18867};
18868
18869static const u32 RV730_pfp_microcode[] = {
188700x7c408000,
188710xa0000000,
188720x7e82800b,
188730x80000000,
188740xdc030000,
188750xcc800040,
188760xd0400040,
188770x7c408000,
188780xa0000000,
188790x7e82800b,
188800xc818000e,
188810x31980001,
188820x7c424000,
188830x9580023a,
188840x7c428000,
188850xc81c001c,
188860xc037c000,
188870x7c40c000,
188880x7c410000,
188890x7cb4800b,
188900xc0360003,
188910x99c00000,
188920xc81c001c,
188930x7cb4800c,
188940x24d40002,
188950x7d654000,
188960xcd400043,
188970xce800043,
188980xcd000043,
188990xcc800040,
189000xce400040,
189010xce800040,
189020xccc00040,
189030xdc3a0000,
189040x9780ffde,
189050xcd000040,
189060x7c40c000,
189070x80000018,
189080x7c410000,
189090xd4000340,
189100xd4000fc0,
189110xd4000fa2,
189120xc818000e,
189130x8000000c,
189140x31980002,
189150xd40003c0,
189160xd4000fc0,
189170xd4000fa2,
189180xc818000e,
189190x288c0008,
189200x30cc000f,
189210x34100001,
189220x7d0d0008,
189230x8000000c,
189240x7d91800b,
189250xcc800040,
189260xd0400040,
189270x7c408000,
189280xa0000000,
189290x7e82800b,
189300xd4000340,
189310xd4000fc0,
189320xd4000fa2,
189330xcc800040,
189340xd0400040,
189350x7c408000,
189360xa0000000,
189370x7e82800b,
189380xd40003c0,
189390xd4000fc0,
189400xd4000fa2,
189410xcc800040,
189420xd0400040,
189430x7c408000,
189440xa0000000,
189450x7e82800b,
189460xcc4003f9,
189470x80000249,
189480xcc4003f8,
189490xc037ffff,
189500x7c414000,
189510xcf41a29e,
189520xc82003f8,
189530xc81c03f9,
189540x66200020,
189550xc81803fb,
189560x7de1c02c,
189570x7d58c008,
189580x7cdcc020,
189590x69100020,
189600xc0360003,
189610xcc000054,
189620x7cb4800c,
189630x80000069,
189640xcc800040,
189650x7c418000,
189660xcd81a29e,
189670xcc800040,
189680x80000067,
189690xcd800040,
189700xc019ffff,
189710xcc800040,
189720xcd81a29e,
189730x7c40c000,
189740x7c410000,
189750x7c414000,
189760xccc1a1fa,
189770xcd01a1f9,
189780xcd41a29d,
189790xccc00040,
189800xcd000040,
189810xcd400040,
189820xcc400040,
189830x7c408000,
189840xa0000000,
189850x7e82800b,
189860xcc000054,
189870xcc800040,
189880x7c40c000,
189890x7c410000,
189900x7c414000,
189910xccc1a1fa,
189920xcd01a1f9,
189930xcd41a29d,
189940xccc00040,
189950xcd000040,
189960xcd400040,
189970xd0400040,
189980x7c408000,
189990xa0000000,
190000x7e82800b,
190010x7c40c000,
190020x30d00001,
190030xccc1a29f,
190040x95000003,
190050x04140001,
190060x04140002,
190070xcd4003fb,
190080xcc800040,
190090x80000000,
190100xccc00040,
190110x7c40c000,
190120xcc800040,
190130xccc1a2a2,
190140x80000000,
190150xccc00040,
190160x7c40c000,
190170x28d4001f,
190180xcc800040,
190190x95400003,
190200x7c410000,
190210xccc00057,
190220x2918001f,
190230xccc00040,
190240x95800003,
190250xcd000040,
190260xcd000058,
190270x80000249,
190280xcc00007f,
190290xc8200017,
190300xc8300022,
190310x9a000006,
190320x0e280001,
190330xc824001e,
190340x0a640001,
190350xd4001240,
190360xce400040,
190370xc036c000,
190380x96800007,
190390x37747900,
190400x041c0001,
190410xcf400040,
190420xcdc00040,
190430xcf0003fa,
190440x7c030000,
190450xca0c0010,
190460x7c410000,
190470x94c00004,
190480x7c414000,
190490xd42002c4,
190500xcde00044,
190510x9b00000b,
190520x7c418000,
190530xcc00004b,
190540xcda00049,
190550xcd200041,
190560xcd600041,
190570xcda00041,
190580x06200001,
190590xce000056,
190600x80000249,
190610xcc00007f,
190620xc8280020,
190630xc82c0021,
190640xcc000063,
190650x7eea4001,
190660x65740020,
190670x7f53402c,
190680x269c0002,
190690x7df5c020,
190700x69f80020,
190710xce80004b,
190720xce600049,
190730xcde00041,
190740xcfa00041,
190750xce600041,
190760x271c0002,
190770x7df5c020,
190780x69f80020,
190790x7db24001,
190800xcf00004b,
190810xce600049,
190820xcde00041,
190830xcfa00041,
190840x800000bc,
190850xce600041,
190860xc8200017,
190870xc8300022,
190880x9a000006,
190890x0e280001,
190900xc824001e,
190910x0a640001,
190920xd4001240,
190930xce400040,
190940xca0c0010,
190950x7c410000,
190960x94c0000b,
190970xc036c000,
190980x96800007,
190990x37747900,
191000x041c0001,
191010xcf400040,
191020xcdc00040,
191030xcf0003fa,
191040x7c030000,
191050x800000b5,
191060x7c414000,
191070xcc000048,
191080x800000ee,
191090x00000000,
191100xc8200017,
191110xc81c0023,
191120x0e240002,
191130x99c00015,
191140x7c418000,
191150x0a200001,
191160xce000056,
191170xd4000440,
191180xcc000040,
191190xc036c000,
191200xca140013,
191210x96400007,
191220x37747900,
191230xcf400040,
191240xcc000040,
191250xc83003fa,
191260x80000103,
191270xcf000022,
191280xcc000022,
191290x95400146,
191300xcc00007f,
191310xcca00046,
191320x80000000,
191330xcc200046,
191340x80000249,
191350xcc000064,
191360xc8200017,
191370xc810001f,
191380x96000005,
191390x09100001,
191400xd4000440,
191410xcd000040,
191420xcd000022,
191430xcc800040,
191440xd0400040,
191450xc80c0025,
191460x94c0feec,
191470xc8100008,
191480xcd000040,
191490xd4000fc0,
191500x80000000,
191510xd4000fa2,
191520x7c40c000,
191530x7c410000,
191540xccc003fd,
191550xcd0003fc,
191560xccc00042,
191570xcd000042,
191580x2914001f,
191590x29180010,
191600x31980007,
191610x3b5c0001,
191620x7d76000b,
191630x99800005,
191640x7d5e400b,
191650xcc000042,
191660x80000249,
191670xcc00004d,
191680x29980001,
191690x292c0008,
191700x9980003d,
191710x32ec0001,
191720x96000004,
191730x2930000c,
191740x80000249,
191750xcc000042,
191760x04140010,
191770xcd400042,
191780x33300001,
191790x34280001,
191800x8400015d,
191810xc8140003,
191820x9b40001b,
191830x0438000c,
191840x8400015d,
191850xc8140003,
191860x9b400017,
191870x04380008,
191880x8400015d,
191890xc8140003,
191900x9b400013,
191910x04380004,
191920x8400015d,
191930xc8140003,
191940x9b400015,
191950xc80c03fd,
191960x9a800009,
191970xc81003fc,
191980x9b000101,
191990xcc00004d,
192000x04140010,
192010xccc00042,
192020xcd000042,
192030x80000135,
192040xcd400042,
192050x96c000fa,
192060xcc00004d,
192070x80000249,
192080xcc00004e,
192090x9ac00003,
192100xcc00004d,
192110xcc00004e,
192120xdf830000,
192130x80000000,
192140xd80301ff,
192150x9ac000f0,
192160xcc00004d,
192170x80000249,
192180xcc00004e,
192190xc8180003,
192200xc81c0003,
192210xc8200003,
192220x7d5d4003,
192230x7da1c003,
192240x7d5d400c,
192250x2a10001f,
192260x299c001f,
192270x7d1d000b,
192280x7d17400b,
192290x88000000,
192300x7e92800b,
192310x96400004,
192320xcc00004e,
192330x80000249,
192340xcc000042,
192350x04380008,
192360xcf800042,
192370xc8080003,
192380xc80c0003,
192390xc8100003,
192400xc8140003,
192410xc8180003,
192420xc81c0003,
192430xc8240003,
192440xc8280003,
192450x29fc001f,
192460x2ab0001f,
192470x7ff3c00b,
192480x28f0001f,
192490x7ff3c00b,
192500x2970001f,
192510x7ff3c00b,
192520x7d888001,
192530x7dccc001,
192540x7e510001,
192550x7e954001,
192560x7c908002,
192570x7cd4c002,
192580x7cbc800b,
192590x9ac00003,
192600x7c8f400b,
192610x38b40001,
192620x9b4000c1,
192630xcc00004d,
192640x9bc000bf,
192650xcc00004e,
192660xc80c03fd,
192670xc81003fc,
192680xccc00042,
192690x8000016e,
192700xcd000042,
192710xd4000340,
192720xd4000fc0,
192730xd4000fa2,
192740xcc800040,
192750xcc400040,
192760xcc400040,
192770xcc400040,
192780x7c40c000,
192790xccc00040,
192800xccc0000d,
192810x80000000,
192820xd0400040,
192830x7c40c000,
192840x7c410000,
192850x65140020,
192860x7d4d402c,
192870x24580002,
192880x7d598020,
192890x7c41c000,
192900xcd800042,
192910x69980020,
192920xcd800042,
192930xcdc00042,
192940xc023c000,
192950x05e40002,
192960x7ca0800b,
192970x26640010,
192980x7ca4800c,
192990xcc800040,
193000xcdc00040,
193010xccc00040,
193020x95c0000e,
193030xcd000040,
193040x09dc0001,
193050xc8280003,
193060x96800008,
193070xce800040,
193080xc834001d,
193090x97400000,
193100xc834001d,
193110x26a80008,
193120x8400024c,
193130xcc2b0000,
193140x99c0fff7,
193150x09dc0001,
193160xdc3a0000,
193170x97800004,
193180x7c418000,
193190x800001a2,
193200x25980002,
193210xa0000000,
193220x7d808000,
193230xc818001d,
193240x7c40c000,
193250x64d00008,
193260x95800000,
193270xc818001d,
193280xcc130000,
193290xcc800040,
193300xccc00040,
193310x80000000,
193320xcc400040,
193330xc810001f,
193340x7c40c000,
193350xcc800040,
193360x7cd1400c,
193370xcd400040,
193380x05180001,
193390x80000000,
193400xcd800022,
193410x7c40c000,
193420x64500020,
193430x8400024c,
193440xcc000061,
193450x7cd0c02c,
193460xc8200017,
193470xc8d60000,
193480x99400008,
193490x7c438000,
193500xdf830000,
193510xcfa0004f,
193520x8400024c,
193530xcc000062,
193540x80000000,
193550xd040007f,
193560x80000249,
193570xcc000062,
193580x8400024c,
193590xcc000061,
193600xc8200017,
193610x7c40c000,
193620xc036ff00,
193630xc810000d,
193640xc0303fff,
193650x7cf5400b,
193660x7d51800b,
193670x7d81800f,
193680x99800008,
193690x7cf3800b,
193700xdf830000,
193710xcfa0004f,
193720x8400024c,
193730xcc000062,
193740x80000000,
193750xd040007f,
193760x80000249,
193770xcc000062,
193780x8400024c,
193790x7c40c000,
193800x28dc0008,
193810x95c00019,
193820x30dc0010,
193830x7c410000,
193840x99c00004,
193850x64540020,
193860x80000208,
193870xc91d0000,
193880x7d15002c,
193890xc91e0000,
193900x7c420000,
193910x7c424000,
193920x7c418000,
193930x7de5c00b,
193940x7de28007,
193950x9a80000e,
193960x41ac0005,
193970x9ac00000,
193980x0aec0001,
193990x30dc0010,
194000x99c00004,
194010x00000000,
194020x8000020b,
194030xc91d0000,
194040x8000020b,
194050xc91e0000,
194060xcc800040,
194070xccc00040,
194080xd0400040,
194090xc80c0025,
194100x94c0fde4,
194110xc8100008,
194120xcd000040,
194130xd4000fc0,
194140x80000000,
194150xd4000fa2,
194160xd4000340,
194170xd4000fc0,
194180xd4000fa2,
194190xcc800040,
194200xd0400040,
194210x7c408000,
194220xa0000000,
194230x7e82800b,
194240xd40003c0,
194250xd4000fc0,
194260xd4000fa2,
194270xcc800040,
194280xd0400040,
194290x7c408000,
194300xa0000000,
194310x7e82800b,
194320x7c40c000,
194330x30d00006,
194340x0d100006,
194350x99000007,
194360xc8140015,
194370x99400005,
194380xcc000052,
194390xd4000340,
194400xd4000fc0,
194410xd4000fa2,
194420xcc800040,
194430xccc00040,
194440x80000000,
194450xd0400040,
194460x7c40c000,
194470xcc4d0000,
194480xdc3a0000,
194490x9780fdbd,
194500x04cc0001,
194510x80000242,
194520xcc4d0000,
194530x80000000,
194540xd040007f,
194550xcc00007f,
194560x80000000,
194570xcc00007f,
194580xcc00007f,
194590x88000000,
194600xcc00007f,
194610x00000000,
194620x00000000,
194630x00000000,
194640x00000000,
194650x00000000,
194660x00000000,
194670x00000000,
194680x00000000,
194690x00000000,
194700x00000000,
194710x00000000,
194720x00000000,
194730x00000000,
194740x00000000,
194750x00000000,
194760x00000000,
194770x00000000,
194780x00000000,
194790x00000000,
194800x00000000,
194810x00000000,
194820x00000000,
194830x00000000,
194840x00000000,
194850x00000000,
194860x00000000,
194870x00000000,
194880x00000000,
194890x00000000,
194900x00000000,
194910x00000000,
194920x00000000,
194930x00000000,
194940x00000000,
194950x00000000,
194960x00000000,
194970x00000000,
194980x00000000,
194990x00000000,
195000x00000000,
195010x00000000,
195020x00000000,
195030x00000000,
195040x00000000,
195050x00000000,
195060x00000000,
195070x00000000,
195080x00000000,
195090x00000000,
195100x00000000,
195110x00000000,
195120x00000000,
195130x00000000,
195140x00000000,
195150x00000000,
195160x00000000,
195170x00000000,
195180x00000000,
195190x00000000,
195200x00000000,
195210x00000000,
195220x00000000,
195230x00000000,
195240x00000000,
195250x00000000,
195260x00000000,
195270x00000000,
195280x00000000,
195290x00000000,
195300x00000000,
195310x00000000,
195320x00000000,
195330x00000000,
195340x00000000,
195350x00000000,
195360x00000000,
195370x00000000,
195380x00000000,
195390x00000000,
195400x00000000,
195410x00000000,
195420x00000000,
195430x00000000,
195440x00000000,
195450x00000000,
195460x00000000,
195470x00000000,
195480x00000000,
195490x00000000,
195500x00000000,
195510x00000000,
195520x00000000,
195530x00000000,
195540x00000000,
195550x00000000,
195560x00000000,
195570x00000000,
195580x00000000,
195590x00000000,
195600x00000000,
195610x00000000,
195620x00000000,
195630x00000000,
195640x00000000,
195650x00000000,
195660x00000000,
195670x00000000,
195680x00000000,
195690x00000000,
195700x00000000,
195710x00000000,
195720x00000000,
195730x00000000,
195740x00000000,
195750x00000000,
195760x00000000,
195770x00000000,
195780x00000000,
195790x00000000,
195800x00000000,
195810x00000000,
195820x00000000,
195830x00000000,
195840x00000000,
195850x00000000,
195860x00000000,
195870x00000000,
195880x00000000,
195890x00000000,
195900x00000000,
195910x00000000,
195920x00000000,
195930x00000000,
195940x00000000,
195950x00000000,
195960x00000000,
195970x00000000,
195980x00000000,
195990x00000000,
196000x00000000,
196010x00000000,
196020x00000000,
196030x00000000,
196040x00000000,
196050x00000000,
196060x00000000,
196070x00000000,
196080x00000000,
196090x00000000,
196100x00000000,
196110x00000000,
196120x00000000,
196130x00000000,
196140x00000000,
196150x00000000,
196160x00000000,
196170x00000000,
196180x00000000,
196190x00000000,
196200x00000000,
196210x00000000,
196220x00000000,
196230x00000000,
196240x00000000,
196250x00000000,
196260x00000000,
196270x00000000,
196280x00000000,
196290x00000000,
196300x00000000,
196310x00000000,
196320x00000000,
196330x00000000,
196340x00000000,
196350x00000000,
196360x00000000,
196370x00000000,
196380x00030222,
196390x0004022a,
196400x0005009f,
196410x00020003,
196420x0006003c,
196430x00070027,
196440x00080191,
196450x00090044,
196460x000a002d,
196470x00100247,
196480x001700f0,
196490x002201d7,
196500x002301e8,
196510x0026004c,
196520x0027005f,
196530x0020011a,
196540x00280092,
196550x0029004f,
196560x002a0083,
196570x002b0064,
196580x002f008d,
196590x003200d8,
196600x00340232,
196610x00360074,
196620x0039010a,
196630x003c01fc,
196640x003f009f,
196650x00410005,
196660x00440194,
196670x0048019d,
196680x004901c5,
196690x004a01cf,
196700x00550225,
196710x0056022d,
196720x0060000a,
196730x0061002a,
196740x00620030,
196750x00630030,
196760x00640030,
196770x00650030,
196780x00660030,
196790x00670030,
196800x00680037,
196810x0069003f,
196820x006a0047,
196830x006b0047,
196840x006c0047,
196850x006d0047,
196860x006e0047,
196870x006f0047,
196880x00700047,
196890x00730247,
196900x007b0240,
196910x00000005,
196920x00000005,
196930x00000005,
196940x00000005,
196950x00000005,
196960x00000005,
196970x00000005,
196980x00000005,
196990x00000005,
197000x00000005,
197010x00000005,
197020x00000005,
197030x00000005,
197040x00000005,
197050x00000005,
197060x00000005,
197070x00000005,
197080x00000005,
197090x00000005,
197100x00000005,
197110x00000005,
197120x00000005,
197130x00000005,
197140x00000005,
197150x00000005,
197160x00000005,
197170x00000005,
19718};
19719
19720static const u32 RV730_cp_microcode[] = {
197210xcc0003ea,
197220x7c408000,
197230xa0000000,
197240xcc800062,
197250x80000001,
197260xd040007f,
197270x80000001,
197280xcc400041,
197290x7c40c000,
197300xc0160004,
197310x30d03fff,
197320x7d15000c,
197330xcc110000,
197340x28d8001e,
197350x31980001,
197360x28dc001f,
197370xc8200004,
197380x95c00006,
197390x7c424000,
197400xcc000062,
197410x7e56800c,
197420xcc290000,
197430xc8240004,
197440x7e26000b,
197450x95800006,
197460x7c42c000,
197470xcc000062,
197480x7ed7000c,
197490xcc310000,
197500xc82c0004,
197510x7e2e000c,
197520xcc000062,
197530x31103fff,
197540x80000001,
197550xce110000,
197560x7c40c000,
197570x80000001,
197580xcc400040,
197590x80000001,
197600xcc412257,
197610x7c418000,
197620xcc400045,
197630xcc400048,
197640xcc41225c,
197650xcc41a1fc,
197660x7c408000,
197670xa0000000,
197680xcc800062,
197690xcc400045,
197700xcc400048,
197710x7c40c000,
197720xcc41225c,
197730xcc41a1fc,
197740x7c408000,
197750xa0000000,
197760xcc800062,
197770xcc000045,
197780xcc000048,
197790xcc41225c,
197800xcc41a1fc,
197810x7c408000,
197820xa0000000,
197830xcc800062,
197840x040ca1fd,
197850xc0120001,
197860xcc000045,
197870xcc000048,
197880x7cd0c00c,
197890xcc41225c,
197900xcc41a1fc,
197910xd04d0000,
197920x7c408000,
197930xa0000000,
197940xcc800062,
197950x80000001,
197960xcc41225d,
197970x7c408000,
197980x7c40c000,
197990xc02a0002,
198000x7c410000,
198010x7d29000c,
198020x30940001,
198030x30980006,
198040x309c0300,
198050x29dc0008,
198060x7c420000,
198070x7c424000,
198080x9540000f,
198090xc02e0004,
198100x05f02258,
198110x7f2f000c,
198120xcc310000,
198130xc8280004,
198140xccc12169,
198150xcd01216a,
198160xce81216b,
198170x0db40002,
198180xcc01216c,
198190x9740000e,
198200x0db40000,
198210x8000007b,
198220xc834000a,
198230x0db40002,
198240x97400009,
198250x0db40000,
198260xc02e0004,
198270x05f02258,
198280x7f2f000c,
198290xcc310000,
198300xc8280004,
198310x8000007b,
198320xc834000a,
198330x97400004,
198340x7e028000,
198350x8000007b,
198360xc834000a,
198370x0db40004,
198380x9740ff8c,
198390x00000000,
198400xce01216d,
198410xce41216e,
198420xc8280003,
198430xc834000a,
198440x9b400004,
198450x043c0005,
198460x8400026b,
198470xcc000062,
198480x0df40000,
198490x9740000b,
198500xc82c03e6,
198510xce81a2b7,
198520xc0300006,
198530x7ef34028,
198540xc0300020,
198550x7f6b8020,
198560x7fb3c029,
198570xcf81a2c4,
198580x80000001,
198590xcfc1a2d1,
198600x0df40001,
198610x9740000b,
198620xc82c03e7,
198630xce81a2bb,
198640xc0300006,
198650x7ef34028,
198660xc0300020,
198670x7f6b8020,
198680x7fb3c029,
198690xcf81a2c5,
198700x80000001,
198710xcfc1a2d2,
198720x0df40002,
198730x9740000b,
198740xc82c03e8,
198750xce81a2bf,
198760xc0300006,
198770x7ef34028,
198780xc0300020,
198790x7f6b8020,
198800x7fb3c029,
198810xcf81a2c6,
198820x80000001,
198830xcfc1a2d3,
198840xc82c03e9,
198850xce81a2c3,
198860xc0300006,
198870x7ef34028,
198880xc0300020,
198890x7f6b8020,
198900x7fb3c029,
198910xcf81a2c7,
198920x80000001,
198930xcfc1a2d4,
198940x80000001,
198950xcc400042,
198960x7c40c000,
198970x7c410000,
198980x2914001d,
198990x31540001,
199000x9940000c,
199010x31181000,
199020xc81c0011,
199030x95c00000,
199040xc81c0011,
199050xccc12100,
199060xcd012101,
199070xccc12102,
199080xcd012103,
199090x04180004,
199100x8000037c,
199110xcd81a2a4,
199120xc02a0004,
199130x95800008,
199140x36a821a3,
199150xcc290000,
199160xc8280004,
199170xc81c0011,
199180x0de40040,
199190x9640ffff,
199200xc81c0011,
199210xccc12170,
199220xcd012171,
199230xc8200012,
199240x96000000,
199250xc8200012,
199260x8000037c,
199270xcc000064,
199280x7c40c000,
199290x7c410000,
199300xcc000045,
199310xcc000048,
199320x40d40003,
199330xcd41225c,
199340xcd01a1fc,
199350xc01a0001,
199360x041ca1fd,
199370x7dd9c00c,
199380x7c420000,
199390x08cc0001,
199400x06240001,
199410x06280002,
199420xce1d0000,
199430xce5d0000,
199440x98c0fffa,
199450xce9d0000,
199460x7c408000,
199470xa0000000,
199480xcc800062,
199490x7c40c000,
199500x30d00001,
199510x28cc0001,
199520x7c414000,
199530x95000006,
199540x7c418000,
199550xcd41216d,
199560xcd81216e,
199570x800000f2,
199580xc81c0003,
199590xc0220004,
199600x7e16000c,
199610xcc210000,
199620xc81c0004,
199630x7c424000,
199640x98c00004,
199650x7c428000,
199660x80000001,
199670xcde50000,
199680xce412169,
199690xce81216a,
199700xcdc1216b,
199710x80000001,
199720xcc01216c,
199730x7c40c000,
199740x7c410000,
199750x7c414000,
199760x7c418000,
199770x7c41c000,
199780x28a40008,
199790x326400ff,
199800x0e68003c,
199810x9680000a,
199820x7c020000,
199830x7c420000,
199840x1e300003,
199850xcc00006a,
199860x9b000003,
199870x42200005,
199880x04200040,
199890x8000010f,
199900x7c024000,
199910x7e024000,
199920x9a400000,
199930x0a640001,
199940x30ec0010,
199950x9ac0000a,
199960xcc000062,
199970xc02a0004,
199980xc82c0021,
199990x7e92800c,
200000xcc000041,
200010xcc290000,
200020xcec00021,
200030x8000011f,
200040xc8300004,
200050xcd01216d,
200060xcd41216e,
200070xc8300003,
200080x7f1f000b,
200090x30f40007,
200100x27780001,
200110x9740002a,
200120x07b80124,
200130x9f800000,
200140x00000000,
200150x80000134,
200160x7f1b8004,
200170x80000138,
200180x7f1b8005,
200190x8000013c,
200200x7f1b8002,
200210x80000140,
200220x7f1b8003,
200230x80000144,
200240x7f1b8007,
200250x80000148,
200260x7f1b8006,
200270x8000014d,
200280x28a40008,
200290x9b800019,
200300x28a40008,
200310x8000015d,
200320x326400ff,
200330x9b800015,
200340x28a40008,
200350x8000015d,
200360x326400ff,
200370x9b800011,
200380x28a40008,
200390x8000015d,
200400x326400ff,
200410x9b80000d,
200420x28a40008,
200430x8000015d,
200440x326400ff,
200450x9b800009,
200460x28a40008,
200470x8000015d,
200480x326400ff,
200490x9b800005,
200500x28a40008,
200510x8000015d,
200520x326400ff,
200530x28a40008,
200540x326400ff,
200550x0e68003c,
200560x9a80feb2,
200570x28ec0008,
200580x7c434000,
200590x7c438000,
200600x7c43c000,
200610x96c00007,
200620xcc000062,
200630xcf412169,
200640xcf81216a,
200650xcfc1216b,
200660x80000001,
200670xcc01216c,
200680x80000001,
200690xcff50000,
200700xcc00006b,
200710x8400037f,
200720x0e68003c,
200730x9a800004,
200740xc8280015,
200750x80000001,
200760xd040007f,
200770x9680ffab,
200780x7e024000,
200790x84000239,
200800xc00e0002,
200810xcc000041,
200820x80000237,
200830xccc1304a,
200840x7c40c000,
200850x7c410000,
200860xc01e0001,
200870x29240012,
200880xc0220002,
200890x96400005,
200900xc0260004,
200910xc027fffb,
200920x7d25000b,
200930xc0260000,
200940x7dd2800b,
200950x7e12c00b,
200960x7d25000c,
200970x7c414000,
200980x7c418000,
200990xccc12169,
201000x9a80000a,
201010xcd01216a,
201020xcd41216b,
201030x96c0fe83,
201040xcd81216c,
201050xc8300018,
201060x97000000,
201070xc8300018,
201080x80000001,
201090xcc000018,
201100x8400037f,
201110xcc00007f,
201120xc8140013,
201130xc8180014,
201140xcd41216b,
201150x96c0fe77,
201160xcd81216c,
201170x80000181,
201180xc8300018,
201190xc80c0008,
201200x98c00000,
201210xc80c0008,
201220x7c410000,
201230x95000002,
201240x00000000,
201250x7c414000,
201260xc8200009,
201270xcc400043,
201280xce01a1f4,
201290xcc400044,
201300xc00e8000,
201310x7c424000,
201320x7c428000,
201330x2aac001f,
201340x96c0fe64,
201350xc035f000,
201360xce4003e2,
201370x32780003,
201380x267c0008,
201390x7ff7c00b,
201400x7ffbc00c,
201410x2a780018,
201420xcfc003e3,
201430xcf8003e4,
201440x26b00002,
201450x7f3f0000,
201460xcf0003e5,
201470x8000031d,
201480x7c80c000,
201490x7c40c000,
201500x28d00008,
201510x3110000f,
201520x9500000f,
201530x25280001,
201540x06a801b2,
201550x9e800000,
201560x00000000,
201570x800001d3,
201580xc0120800,
201590x800001e1,
201600xc814000f,
201610x800001e8,
201620xc8140010,
201630x800001ef,
201640xccc1a2a4,
201650x800001f8,
201660xc8140011,
201670x30d0003f,
201680x0d280015,
201690x9a800012,
201700x0d28001e,
201710x9a80001e,
201720x0d280020,
201730x9a800023,
201740x0d24000f,
201750x0d280010,
201760x7e6a800c,
201770x9a800026,
201780x0d200004,
201790x0d240014,
201800x0d280028,
201810x7e62400c,
201820x7ea6800c,
201830x9a80002a,
201840xc8140011,
201850x80000001,
201860xccc1a2a4,
201870xc0120800,
201880x7c414000,
201890x7d0cc00c,
201900xc0120008,
201910x29580003,
201920x295c000c,
201930x7c420000,
201940x7dd1c00b,
201950x26200014,
201960x7e1e400c,
201970x7e4e800c,
201980xce81a2a4,
201990x80000001,
202000xcd81a1fe,
202010xc814000f,
202020x0410210e,
202030x95400000,
202040xc814000f,
202050xd0510000,
202060x80000001,
202070xccc1a2a4,
202080xc8140010,
202090x04102108,
202100x95400000,
202110xc8140010,
202120xd0510000,
202130x80000001,
202140xccc1a2a4,
202150xccc1a2a4,
202160x04100001,
202170xcd000019,
202180x8400037f,
202190xcc00007f,
202200xc8100019,
202210x99000000,
202220xc8100019,
202230x80000002,
202240x7c408000,
202250x04102100,
202260x95400000,
202270xc8140011,
202280xd0510000,
202290x8000037c,
202300xccc1a2a4,
202310x7c40c000,
202320xcc40000d,
202330x94c0fe01,
202340xcc40000e,
202350x7c410000,
202360x95000005,
202370x08cc0001,
202380xc8140005,
202390x99400014,
202400x00000000,
202410x98c0fffb,
202420x7c410000,
202430x80000002,
202440x7d008000,
202450xc8140005,
202460x7c40c000,
202470x9940000c,
202480xc818000c,
202490x7c410000,
202500x9580fdf0,
202510xc820000e,
202520xc81c000d,
202530x66200020,
202540x7e1e002c,
202550x25240002,
202560x7e624020,
202570x80000001,
202580xcce60000,
202590x7c410000,
202600xcc00006c,
202610xcc00006d,
202620xc818001f,
202630xc81c001e,
202640x65980020,
202650x7dd9c02c,
202660x7cd4c00c,
202670xccde0000,
202680x45dc0004,
202690xc8280017,
202700x9680000f,
202710xc00e0001,
202720x28680008,
202730x2aac0016,
202740x32a800ff,
202750x0eb00049,
202760x7f2f000b,
202770x97000006,
202780x00000000,
202790xc8140005,
202800x7c40c000,
202810x80000221,
202820x7c410000,
202830x80000224,
202840xd040007f,
202850x84000239,
202860xcc000041,
202870xccc1304a,
202880x94000000,
202890xc83c001a,
202900x043c0005,
202910xcfc1a2a4,
202920xc0361f90,
202930xc0387fff,
202940x7c03c010,
202950x7f7b400c,
202960xcf41217c,
202970xcfc1217d,
202980xcc01217e,
202990xc03a0004,
203000x0434217f,
203010x7f7b400c,
203020xcc350000,
203030xc83c0004,
203040x2bfc001f,
203050x04380020,
203060x97c00005,
203070xcc000062,
203080x9b800000,
203090x0bb80001,
203100x80000245,
203110xcc000071,
203120xcc01a1f4,
203130x04380016,
203140xc0360002,
203150xcf81a2a4,
203160x88000000,
203170xcf412010,
203180x7c40c000,
203190x28d0001c,
203200x95000005,
203210x04d40001,
203220xcd400065,
203230x80000001,
203240xcd400068,
203250x09540002,
203260x80000001,
203270xcd400066,
203280x8400026a,
203290xc81803ea,
203300x7c40c000,
203310x9980fd9f,
203320xc8140016,
203330x08d00001,
203340x9940002b,
203350xcd000068,
203360x7c408000,
203370xa0000000,
203380xcc800062,
203390x043c0005,
203400xcfc1a2a4,
203410xcc01a1f4,
203420x8400037f,
203430xcc000046,
203440x88000000,
203450xcc00007f,
203460x8400027c,
203470xc81803ea,
203480x7c40c000,
203490x9980fd8d,
203500xc8140016,
203510x08d00001,
203520x99400019,
203530xcd000068,
203540x7c408000,
203550xa0000000,
203560xcc800062,
203570x043c0022,
203580xcfc1a2a4,
203590x8400037f,
203600xcc000047,
203610x88000000,
203620xcc00007f,
203630xc8100016,
203640x9900000d,
203650xcc400067,
203660x80000002,
203670x7c408000,
203680xc81803ea,
203690x9980fd79,
203700x7c40c000,
203710x94c00003,
203720xc8100016,
203730x99000004,
203740xccc00068,
203750x80000002,
203760x7c408000,
203770x84000239,
203780xc0148000,
203790xcc000041,
203800xcd41304a,
203810xc0148000,
203820x99000000,
203830xc8100016,
203840x80000002,
203850x7c408000,
203860xc0120001,
203870x7c51400c,
203880x80000001,
203890xd0550000,
203900x7c40c000,
203910x7c410000,
203920x7c414000,
203930x7c418000,
203940x291c001f,
203950xccc0004a,
203960xcd00004b,
203970x95c00003,
203980xc01c8000,
203990xcdc12010,
204000xdd830000,
204010x055c2000,
204020xcc000062,
204030x80000001,
204040xd81f4100,
204050x7c40c000,
204060x7c410000,
204070x7c414000,
204080x7c418000,
204090xccc0004c,
204100xcd00004d,
204110xdd830000,
204120x055ca000,
204130x80000001,
204140xd81f4100,
204150x7c40c000,
204160x7c410000,
204170x7c414000,
204180x7c418000,
204190xccc0004e,
204200xcd00004f,
204210xdd830000,
204220x055cc000,
204230x80000001,
204240xd81f4100,
204250x7c40c000,
204260x7c410000,
204270x7c414000,
204280x7c418000,
204290xccc00050,
204300xcd000051,
204310xdd830000,
204320x055cf8e0,
204330x80000001,
204340xd81f4100,
204350x7c40c000,
204360x7c410000,
204370x7c414000,
204380x7c418000,
204390xccc00052,
204400xcd000053,
204410xdd830000,
204420x055cf880,
204430x80000001,
204440xd81f4100,
204450x7c40c000,
204460x7c410000,
204470x7c414000,
204480x7c418000,
204490xccc00054,
204500xcd000055,
204510xdd830000,
204520x055ce000,
204530x80000001,
204540xd81f4100,
204550x7c40c000,
204560x7c410000,
204570x7c414000,
204580x7c418000,
204590xccc00056,
204600xcd000057,
204610xdd830000,
204620x055cf000,
204630x80000001,
204640xd81f4100,
204650x7c40c000,
204660x7c410000,
204670x7c414000,
204680x7c418000,
204690xccc00058,
204700xcd000059,
204710xdd830000,
204720x055cf3fc,
204730x80000001,
204740xd81f4100,
204750xd0432000,
204760x7c408000,
204770xa0000000,
204780xcc800062,
204790xd043a000,
204800x7c408000,
204810xa0000000,
204820xcc800062,
204830xd043c000,
204840x7c408000,
204850xa0000000,
204860xcc800062,
204870xd043f8e0,
204880x7c408000,
204890xa0000000,
204900xcc800062,
204910xd043f880,
204920x7c408000,
204930xa0000000,
204940xcc800062,
204950xd043e000,
204960x7c408000,
204970xa0000000,
204980xcc800062,
204990xd043f000,
205000x7c408000,
205010xa0000000,
205020xcc800062,
205030xd043f3fc,
205040x7c408000,
205050xa0000000,
205060xcc800062,
205070xc81403e0,
205080xcc430000,
205090xcc430000,
205100xcc430000,
205110x7d45c000,
205120xcdc30000,
205130xd0430000,
205140x7c408000,
205150xa0000000,
205160xcc800062,
205170x7c40c000,
205180xc81003e2,
205190xc81403e5,
205200xc81803e3,
205210xc81c03e4,
205220xcd812169,
205230xcdc1216a,
205240xccc1216b,
205250xcc01216c,
205260x04200004,
205270x7da18000,
205280x7d964002,
205290x9640fcd9,
205300xcd8003e3,
205310x31280003,
205320xc02df000,
205330x25180008,
205340x7dad800b,
205350x7da9800c,
205360x80000001,
205370xcd8003e3,
205380x308cffff,
205390xd04d0000,
205400x7c408000,
205410xa0000000,
205420xcc800062,
205430xc8140020,
205440x15580002,
205450x9580ffff,
205460xc8140020,
205470xcc00006e,
205480xcc412180,
205490x7c40c000,
205500xccc1218d,
205510xcc412181,
205520x28d0001f,
205530x34588000,
205540xcd81218c,
205550x9500fcbf,
205560xcc412182,
205570xc8140020,
205580x9940ffff,
205590xc8140020,
205600x80000002,
205610x7c408000,
205620x7c40c000,
205630x28d00018,
205640x31100001,
205650xc0160080,
205660x95000003,
205670xc02a0004,
205680x7cd4c00c,
205690xccc1217c,
205700xcc41217d,
205710xcc41217e,
205720x7c418000,
205730x1db00003,
205740x36a0217f,
205750x9b000003,
205760x419c0005,
205770x041c0040,
205780x99c00000,
205790x09dc0001,
205800xcc210000,
205810xc8240004,
205820x2a6c001f,
205830x419c0005,
205840x9ac0fffa,
205850xcc800062,
205860x80000002,
205870x7c408000,
205880x7c40c000,
205890x04d403e6,
205900x80000001,
205910xcc540000,
205920x8000037c,
205930xcc4003ea,
205940xc01c8000,
205950x044ca000,
205960xcdc12010,
205970x7c410000,
205980xc8140009,
205990x04180000,
206000x041c0008,
206010xcd800071,
206020x09dc0001,
206030x05980001,
206040xcd0d0000,
206050x99c0fffc,
206060xcc800062,
206070x8000037c,
206080xcd400071,
206090xc00e0100,
206100xcc000041,
206110xccc1304a,
206120xc83c007f,
206130xcc00007f,
206140x80000001,
206150xcc00007f,
206160xcc00007f,
206170x88000000,
206180xcc00007f,
206190x00000000,
206200x00000000,
206210x00000000,
206220x00000000,
206230x00000000,
206240x00000000,
206250x00000000,
206260x00000000,
206270x00000000,
206280x00000000,
206290x00000000,
206300x00000000,
206310x00000000,
206320x00000000,
206330x00000000,
206340x00000000,
206350x00000000,
206360x00000000,
206370x00000000,
206380x00000000,
206390x00000000,
206400x00000000,
206410x00000000,
206420x00000000,
206430x00000000,
206440x00000000,
206450x00000000,
206460x00000000,
206470x00000000,
206480x00000000,
206490x00000000,
206500x00000000,
206510x00000000,
206520x00000000,
206530x00000000,
206540x00000000,
206550x00000000,
206560x00000000,
206570x00000000,
206580x00000000,
206590x00000000,
206600x00000000,
206610x00000000,
206620x00000000,
206630x00000000,
206640x00000000,
206650x00000000,
206660x00000000,
206670x00000000,
206680x00000000,
206690x00000000,
206700x00000000,
206710x00000000,
206720x00000000,
206730x00000000,
206740x00000000,
206750x00000000,
206760x00000000,
206770x00000000,
206780x00000000,
206790x00000000,
206800x00000000,
206810x00000000,
206820x00000000,
206830x00000000,
206840x00000000,
206850x00000000,
206860x00000000,
206870x00000000,
206880x00000000,
206890x00000000,
206900x00000000,
206910x00000000,
206920x00000000,
206930x00000000,
206940x00000000,
206950x00000000,
206960x00000000,
206970x00000000,
206980x00000000,
206990x00000000,
207000x00000000,
207010x00000000,
207020x00000000,
207030x00000000,
207040x00000000,
207050x00000000,
207060x00000000,
207070x00000000,
207080x00000000,
207090x00000000,
207100x00000000,
207110x00000000,
207120x00000000,
207130x00000000,
207140x00000000,
207150x00000000,
207160x00000000,
207170x00000000,
207180x00000000,
207190x00000000,
207200x00000000,
207210x00000000,
207220x00000000,
207230x00000000,
207240x00000000,
207250x00000000,
207260x00000000,
207270x00000000,
207280x00000000,
207290x00000000,
207300x00000000,
207310x00000000,
207320x00000000,
207330x00000000,
207340x00000000,
207350x00000000,
207360x00000000,
207370x00000000,
207380x00000000,
207390x00000000,
207400x00000000,
207410x00000000,
207420x00000000,
207430x00000000,
207440x00000000,
207450x00000000,
207460x00000000,
207470x00000000,
207480x00000000,
207490x00000000,
207500x00000000,
207510x00000000,
207520x00000000,
207530x00000000,
207540x00000000,
207550x00000000,
207560x00000000,
207570x00000000,
207580x00000000,
207590x00000000,
207600x00000000,
207610x00000000,
207620x00000000,
207630x00000000,
207640x00000000,
207650x00000000,
207660x00000000,
207670x00000000,
207680x00000000,
207690x00000000,
207700x00000000,
207710x00000000,
207720x00000000,
207730x00000000,
207740x00000000,
207750x00000000,
207760x00000000,
207770x00000000,
207780x00000000,
207790x00000000,
207800x00000000,
207810x00000000,
207820x00000000,
207830x00000000,
207840x00000000,
207850x00000000,
207860x00000000,
207870x00000000,
207880x00000000,
207890x00000000,
207900x00000000,
207910x00000000,
207920x00000000,
207930x00000000,
207940x00000000,
207950x00000000,
207960x00000000,
207970x00000000,
207980x00000000,
207990x00000000,
208000x00000000,
208010x00000000,
208020x00000000,
208030x00000000,
208040x00000000,
208050x00000000,
208060x00000000,
208070x00000000,
208080x00000000,
208090x00000000,
208100x00000000,
208110x00000000,
208120x00000000,
208130x00000000,
208140x00000000,
208150x00000000,
208160x00000000,
208170x00000000,
208180x00000000,
208190x00000000,
208200x00000000,
208210x00000000,
208220x00000000,
208230x00000000,
208240x00000000,
208250x00000000,
208260x00000000,
208270x00000000,
208280x00000000,
208290x00000000,
208300x00000000,
208310x00000000,
208320x00000000,
208330x00000000,
208340x00000000,
208350x00000000,
208360x00000000,
208370x00000000,
208380x00000000,
208390x00000000,
208400x00000000,
208410x00000000,
208420x00000000,
208430x00000000,
208440x00000000,
208450x00000000,
208460x00000000,
208470x00000000,
208480x00000000,
208490x00000000,
208500x00000000,
208510x00000000,
208520x00000000,
208530x00000000,
208540x00000000,
208550x00000000,
208560x00000000,
208570x00000000,
208580x00000000,
208590x00000000,
208600x00000000,
208610x00000000,
208620x00000000,
208630x00000000,
208640x00000000,
208650x00000000,
208660x00000000,
208670x00000000,
208680x00000000,
208690x00000000,
208700x00000000,
208710x00000000,
208720x00000000,
208730x00000000,
208740x00000000,
208750x00000000,
208760x00000000,
208770x00000000,
208780x00000000,
208790x00000000,
208800x00000000,
208810x00000000,
208820x00000000,
208830x00000000,
208840x00000000,
208850x00000000,
208860x00000000,
208870x00000000,
208880x00000000,
208890x00000000,
208900x00000000,
208910x00000000,
208920x00000000,
208930x00000000,
208940x00000000,
208950x00000000,
208960x00000000,
208970x00000000,
208980x00000000,
208990x00000000,
209000x00000000,
209010x00000000,
209020x00000000,
209030x00000000,
209040x00000000,
209050x00000000,
209060x00000000,
209070x00000000,
209080x00000000,
209090x00000000,
209100x00000000,
209110x00000000,
209120x00000000,
209130x00000000,
209140x00000000,
209150x00000000,
209160x00000000,
209170x00000000,
209180x00000000,
209190x00000000,
209200x00000000,
209210x00000000,
209220x00000000,
209230x00000000,
209240x00000000,
209250x00000000,
209260x00000000,
209270x00000000,
209280x00000000,
209290x00000000,
209300x00000000,
209310x00000000,
209320x00000000,
209330x00000000,
209340x00000000,
209350x00000000,
209360x00000000,
209370x00000000,
209380x00000000,
209390x00000000,
209400x00000000,
209410x00000000,
209420x00000000,
209430x00000000,
209440x00000000,
209450x00000000,
209460x00000000,
209470x00000000,
209480x00000000,
209490x00000000,
209500x00000000,
209510x00000000,
209520x00000000,
209530x00000000,
209540x00000000,
209550x00000000,
209560x00000000,
209570x00000000,
209580x00000000,
209590x00000000,
209600x00000000,
209610x00000000,
209620x00000000,
209630x00000000,
209640x00000000,
209650x00000000,
209660x00000000,
209670x00000000,
209680x00000000,
209690x00000000,
209700x00000000,
209710x00000000,
209720x00000000,
209730x00000000,
209740x00000000,
209750x00000000,
209760x00000000,
209770x00000000,
209780x00000000,
209790x00000000,
209800x00000000,
209810x00000000,
209820x00000000,
209830x00000000,
209840x00000000,
209850x00000000,
209860x00000000,
209870x00000000,
209880x00000000,
209890x00000000,
209900x00000000,
209910x00000000,
209920x00000000,
209930x00000000,
209940x00000000,
209950x00000000,
209960x00000000,
209970x00000000,
209980x00000000,
209990x00000000,
210000x00000000,
210010x00010331,
210020x00100004,
210030x00170006,
210040x00210008,
210050x00270028,
210060x00280023,
210070x00290029,
210080x002a0026,
210090x002b0029,
210100x002d0038,
210110x002e003f,
210120x002f004a,
210130x0034004c,
210140x00360030,
210150x003900af,
210160x003a00cf,
210170x003b00e4,
210180x003c00fc,
210190x003d016b,
210200x003f00ad,
210210x00410336,
210220x00430349,
210230x0044018e,
210240x004500fc,
210250x004601ac,
210260x004701ac,
210270x004801fe,
210280x0049020c,
210290x004a0255,
210300x004b0282,
210310x0052025f,
210320x00530271,
210330x00540287,
210340x00570299,
210350x0060029d,
210360x006102ac,
210370x006202b6,
210380x006302c0,
210390x006402ca,
210400x006502d4,
210410x006602de,
210420x006702e8,
210430x006802f2,
210440x006902f6,
210450x006a02fa,
210460x006b02fe,
210470x006c0302,
210480x006d0306,
210490x006e030a,
210500x006f030e,
210510x00700312,
210520x00720363,
210530x00740369,
210540x00790367,
210550x007c031c,
210560x000f0378,
210570x000f0378,
210580x000f0378,
210590x000f0378,
210600x000f0378,
210610x000f0378,
210620x000f0378,
210630x000f0378,
210640x000f0378,
210650x000f0378,
210660x000f0378,
210670x000f0378,
210680x000f0378,
210690x000f0378,
210700x000f0378,
210710x000f0378,
210720x000f0378,
210730x000f0378,
210740x000f0378,
210750x000f0378,
210760x000f0378,
210770x000f0378,
210780x000f0378,
210790x000f0378,
210800x000f0378,
21081};
21082
21083static const u32 RV710_pfp_microcode[] = {
210840x7c408000,
210850xa0000000,
210860x7e82800b,
210870x80000000,
210880xdc030000,
210890xcc800040,
210900xd0400040,
210910x7c408000,
210920xa0000000,
210930x7e82800b,
210940xc818000e,
210950x31980001,
210960x7c424000,
210970x9580023a,
210980x7c428000,
210990xc81c001c,
211000xc037c000,
211010x7c40c000,
211020x7c410000,
211030x7cb4800b,
211040xc0360003,
211050x99c00000,
211060xc81c001c,
211070x7cb4800c,
211080x24d40002,
211090x7d654000,
211100xcd400043,
211110xce800043,
211120xcd000043,
211130xcc800040,
211140xce400040,
211150xce800040,
211160xccc00040,
211170xdc3a0000,
211180x9780ffde,
211190xcd000040,
211200x7c40c000,
211210x80000018,
211220x7c410000,
211230xd4000340,
211240xd4000fc0,
211250xd4000fa2,
211260xc818000e,
211270x8000000c,
211280x31980002,
211290xd40003c0,
211300xd4000fc0,
211310xd4000fa2,
211320xc818000e,
211330x288c0008,
211340x30cc000f,
211350x34100001,
211360x7d0d0008,
211370x8000000c,
211380x7d91800b,
211390xcc800040,
211400xd0400040,
211410x7c408000,
211420xa0000000,
211430x7e82800b,
211440xd4000340,
211450xd4000fc0,
211460xd4000fa2,
211470xcc800040,
211480xd0400040,
211490x7c408000,
211500xa0000000,
211510x7e82800b,
211520xd40003c0,
211530xd4000fc0,
211540xd4000fa2,
211550xcc800040,
211560xd0400040,
211570x7c408000,
211580xa0000000,
211590x7e82800b,
211600xcc4003f9,
211610x80000249,
211620xcc4003f8,
211630xc037ffff,
211640x7c414000,
211650xcf41a29e,
211660xc82003f8,
211670xc81c03f9,
211680x66200020,
211690xc81803fb,
211700x7de1c02c,
211710x7d58c008,
211720x7cdcc020,
211730x69100020,
211740xc0360003,
211750xcc000054,
211760x7cb4800c,
211770x80000069,
211780xcc800040,
211790x7c418000,
211800xcd81a29e,
211810xcc800040,
211820x80000067,
211830xcd800040,
211840xc019ffff,
211850xcc800040,
211860xcd81a29e,
211870x7c40c000,
211880x7c410000,
211890x7c414000,
211900xccc1a1fa,
211910xcd01a1f9,
211920xcd41a29d,
211930xccc00040,
211940xcd000040,
211950xcd400040,
211960xcc400040,
211970x7c408000,
211980xa0000000,
211990x7e82800b,
212000xcc000054,
212010xcc800040,
212020x7c40c000,
212030x7c410000,
212040x7c414000,
212050xccc1a1fa,
212060xcd01a1f9,
212070xcd41a29d,
212080xccc00040,
212090xcd000040,
212100xcd400040,
212110xd0400040,
212120x7c408000,
212130xa0000000,
212140x7e82800b,
212150x7c40c000,
212160x30d00001,
212170xccc1a29f,
212180x95000003,
212190x04140001,
212200x04140002,
212210xcd4003fb,
212220xcc800040,
212230x80000000,
212240xccc00040,
212250x7c40c000,
212260xcc800040,
212270xccc1a2a2,
212280x80000000,
212290xccc00040,
212300x7c40c000,
212310x28d4001f,
212320xcc800040,
212330x95400003,
212340x7c410000,
212350xccc00057,
212360x2918001f,
212370xccc00040,
212380x95800003,
212390xcd000040,
212400xcd000058,
212410x80000249,
212420xcc00007f,
212430xc8200017,
212440xc8300022,
212450x9a000006,
212460x0e280001,
212470xc824001e,
212480x0a640001,
212490xd4001240,
212500xce400040,
212510xc036c000,
212520x96800007,
212530x37747900,
212540x041c0001,
212550xcf400040,
212560xcdc00040,
212570xcf0003fa,
212580x7c030000,
212590xca0c0010,
212600x7c410000,
212610x94c00004,
212620x7c414000,
212630xd42002c4,
212640xcde00044,
212650x9b00000b,
212660x7c418000,
212670xcc00004b,
212680xcda00049,
212690xcd200041,
212700xcd600041,
212710xcda00041,
212720x06200001,
212730xce000056,
212740x80000249,
212750xcc00007f,
212760xc8280020,
212770xc82c0021,
212780xcc000063,
212790x7eea4001,
212800x65740020,
212810x7f53402c,
212820x269c0002,
212830x7df5c020,
212840x69f80020,
212850xce80004b,
212860xce600049,
212870xcde00041,
212880xcfa00041,
212890xce600041,
212900x271c0002,
212910x7df5c020,
212920x69f80020,
212930x7db24001,
212940xcf00004b,
212950xce600049,
212960xcde00041,
212970xcfa00041,
212980x800000bc,
212990xce600041,
213000xc8200017,
213010xc8300022,
213020x9a000006,
213030x0e280001,
213040xc824001e,
213050x0a640001,
213060xd4001240,
213070xce400040,
213080xca0c0010,
213090x7c410000,
213100x94c0000b,
213110xc036c000,
213120x96800007,
213130x37747900,
213140x041c0001,
213150xcf400040,
213160xcdc00040,
213170xcf0003fa,
213180x7c030000,
213190x800000b5,
213200x7c414000,
213210xcc000048,
213220x800000ee,
213230x00000000,
213240xc8200017,
213250xc81c0023,
213260x0e240002,
213270x99c00015,
213280x7c418000,
213290x0a200001,
213300xce000056,
213310xd4000440,
213320xcc000040,
213330xc036c000,
213340xca140013,
213350x96400007,
213360x37747900,
213370xcf400040,
213380xcc000040,
213390xc83003fa,
213400x80000103,
213410xcf000022,
213420xcc000022,
213430x95400146,
213440xcc00007f,
213450xcca00046,
213460x80000000,
213470xcc200046,
213480x80000249,
213490xcc000064,
213500xc8200017,
213510xc810001f,
213520x96000005,
213530x09100001,
213540xd4000440,
213550xcd000040,
213560xcd000022,
213570xcc800040,
213580xd0400040,
213590xc80c0025,
213600x94c0feec,
213610xc8100008,
213620xcd000040,
213630xd4000fc0,
213640x80000000,
213650xd4000fa2,
213660x7c40c000,
213670x7c410000,
213680xccc003fd,
213690xcd0003fc,
213700xccc00042,
213710xcd000042,
213720x2914001f,
213730x29180010,
213740x31980007,
213750x3b5c0001,
213760x7d76000b,
213770x99800005,
213780x7d5e400b,
213790xcc000042,
213800x80000249,
213810xcc00004d,
213820x29980001,
213830x292c0008,
213840x9980003d,
213850x32ec0001,
213860x96000004,
213870x2930000c,
213880x80000249,
213890xcc000042,
213900x04140010,
213910xcd400042,
213920x33300001,
213930x34280001,
213940x8400015d,
213950xc8140003,
213960x9b40001b,
213970x0438000c,
213980x8400015d,
213990xc8140003,
214000x9b400017,
214010x04380008,
214020x8400015d,
214030xc8140003,
214040x9b400013,
214050x04380004,
214060x8400015d,
214070xc8140003,
214080x9b400015,
214090xc80c03fd,
214100x9a800009,
214110xc81003fc,
214120x9b000101,
214130xcc00004d,
214140x04140010,
214150xccc00042,
214160xcd000042,
214170x80000135,
214180xcd400042,
214190x96c000fa,
214200xcc00004d,
214210x80000249,
214220xcc00004e,
214230x9ac00003,
214240xcc00004d,
214250xcc00004e,
214260xdf830000,
214270x80000000,
214280xd80301ff,
214290x9ac000f0,
214300xcc00004d,
214310x80000249,
214320xcc00004e,
214330xc8180003,
214340xc81c0003,
214350xc8200003,
214360x7d5d4003,
214370x7da1c003,
214380x7d5d400c,
214390x2a10001f,
214400x299c001f,
214410x7d1d000b,
214420x7d17400b,
214430x88000000,
214440x7e92800b,
214450x96400004,
214460xcc00004e,
214470x80000249,
214480xcc000042,
214490x04380008,
214500xcf800042,
214510xc8080003,
214520xc80c0003,
214530xc8100003,
214540xc8140003,
214550xc8180003,
214560xc81c0003,
214570xc8240003,
214580xc8280003,
214590x29fc001f,
214600x2ab0001f,
214610x7ff3c00b,
214620x28f0001f,
214630x7ff3c00b,
214640x2970001f,
214650x7ff3c00b,
214660x7d888001,
214670x7dccc001,
214680x7e510001,
214690x7e954001,
214700x7c908002,
214710x7cd4c002,
214720x7cbc800b,
214730x9ac00003,
214740x7c8f400b,
214750x38b40001,
214760x9b4000c1,
214770xcc00004d,
214780x9bc000bf,
214790xcc00004e,
214800xc80c03fd,
214810xc81003fc,
214820xccc00042,
214830x8000016e,
214840xcd000042,
214850xd4000340,
214860xd4000fc0,
214870xd4000fa2,
214880xcc800040,
214890xcc400040,
214900xcc400040,
214910xcc400040,
214920x7c40c000,
214930xccc00040,
214940xccc0000d,
214950x80000000,
214960xd0400040,
214970x7c40c000,
214980x7c410000,
214990x65140020,
215000x7d4d402c,
215010x24580002,
215020x7d598020,
215030x7c41c000,
215040xcd800042,
215050x69980020,
215060xcd800042,
215070xcdc00042,
215080xc023c000,
215090x05e40002,
215100x7ca0800b,
215110x26640010,
215120x7ca4800c,
215130xcc800040,
215140xcdc00040,
215150xccc00040,
215160x95c0000e,
215170xcd000040,
215180x09dc0001,
215190xc8280003,
215200x96800008,
215210xce800040,
215220xc834001d,
215230x97400000,
215240xc834001d,
215250x26a80008,
215260x8400024c,
215270xcc2b0000,
215280x99c0fff7,
215290x09dc0001,
215300xdc3a0000,
215310x97800004,
215320x7c418000,
215330x800001a2,
215340x25980002,
215350xa0000000,
215360x7d808000,
215370xc818001d,
215380x7c40c000,
215390x64d00008,
215400x95800000,
215410xc818001d,
215420xcc130000,
215430xcc800040,
215440xccc00040,
215450x80000000,
215460xcc400040,
215470xc810001f,
215480x7c40c000,
215490xcc800040,
215500x7cd1400c,
215510xcd400040,
215520x05180001,
215530x80000000,
215540xcd800022,
215550x7c40c000,
215560x64500020,
215570x8400024c,
215580xcc000061,
215590x7cd0c02c,
215600xc8200017,
215610xc8d60000,
215620x99400008,
215630x7c438000,
215640xdf830000,
215650xcfa0004f,
215660x8400024c,
215670xcc000062,
215680x80000000,
215690xd040007f,
215700x80000249,
215710xcc000062,
215720x8400024c,
215730xcc000061,
215740xc8200017,
215750x7c40c000,
215760xc036ff00,
215770xc810000d,
215780xc0303fff,
215790x7cf5400b,
215800x7d51800b,
215810x7d81800f,
215820x99800008,
215830x7cf3800b,
215840xdf830000,
215850xcfa0004f,
215860x8400024c,
215870xcc000062,
215880x80000000,
215890xd040007f,
215900x80000249,
215910xcc000062,
215920x8400024c,
215930x7c40c000,
215940x28dc0008,
215950x95c00019,
215960x30dc0010,
215970x7c410000,
215980x99c00004,
215990x64540020,
216000x80000208,
216010xc91d0000,
216020x7d15002c,
216030xc91e0000,
216040x7c420000,
216050x7c424000,
216060x7c418000,
216070x7de5c00b,
216080x7de28007,
216090x9a80000e,
216100x41ac0005,
216110x9ac00000,
216120x0aec0001,
216130x30dc0010,
216140x99c00004,
216150x00000000,
216160x8000020b,
216170xc91d0000,
216180x8000020b,
216190xc91e0000,
216200xcc800040,
216210xccc00040,
216220xd0400040,
216230xc80c0025,
216240x94c0fde4,
216250xc8100008,
216260xcd000040,
216270xd4000fc0,
216280x80000000,
216290xd4000fa2,
216300xd4000340,
216310xd4000fc0,
216320xd4000fa2,
216330xcc800040,
216340xd0400040,
216350x7c408000,
216360xa0000000,
216370x7e82800b,
216380xd40003c0,
216390xd4000fc0,
216400xd4000fa2,
216410xcc800040,
216420xd0400040,
216430x7c408000,
216440xa0000000,
216450x7e82800b,
216460x7c40c000,
216470x30d00006,
216480x0d100006,
216490x99000007,
216500xc8140015,
216510x99400005,
216520xcc000052,
216530xd4000340,
216540xd4000fc0,
216550xd4000fa2,
216560xcc800040,
216570xccc00040,
216580x80000000,
216590xd0400040,
216600x7c40c000,
216610xcc4d0000,
216620xdc3a0000,
216630x9780fdbd,
216640x04cc0001,
216650x80000242,
216660xcc4d0000,
216670x80000000,
216680xd040007f,
216690xcc00007f,
216700x80000000,
216710xcc00007f,
216720xcc00007f,
216730x88000000,
216740xcc00007f,
216750x00000000,
216760x00000000,
216770x00000000,
216780x00000000,
216790x00000000,
216800x00000000,
216810x00000000,
216820x00000000,
216830x00000000,
216840x00000000,
216850x00000000,
216860x00000000,
216870x00000000,
216880x00000000,
216890x00000000,
216900x00000000,
216910x00000000,
216920x00000000,
216930x00000000,
216940x00000000,
216950x00000000,
216960x00000000,
216970x00000000,
216980x00000000,
216990x00000000,
217000x00000000,
217010x00000000,
217020x00000000,
217030x00000000,
217040x00000000,
217050x00000000,
217060x00000000,
217070x00000000,
217080x00000000,
217090x00000000,
217100x00000000,
217110x00000000,
217120x00000000,
217130x00000000,
217140x00000000,
217150x00000000,
217160x00000000,
217170x00000000,
217180x00000000,
217190x00000000,
217200x00000000,
217210x00000000,
217220x00000000,
217230x00000000,
217240x00000000,
217250x00000000,
217260x00000000,
217270x00000000,
217280x00000000,
217290x00000000,
217300x00000000,
217310x00000000,
217320x00000000,
217330x00000000,
217340x00000000,
217350x00000000,
217360x00000000,
217370x00000000,
217380x00000000,
217390x00000000,
217400x00000000,
217410x00000000,
217420x00000000,
217430x00000000,
217440x00000000,
217450x00000000,
217460x00000000,
217470x00000000,
217480x00000000,
217490x00000000,
217500x00000000,
217510x00000000,
217520x00000000,
217530x00000000,
217540x00000000,
217550x00000000,
217560x00000000,
217570x00000000,
217580x00000000,
217590x00000000,
217600x00000000,
217610x00000000,
217620x00000000,
217630x00000000,
217640x00000000,
217650x00000000,
217660x00000000,
217670x00000000,
217680x00000000,
217690x00000000,
217700x00000000,
217710x00000000,
217720x00000000,
217730x00000000,
217740x00000000,
217750x00000000,
217760x00000000,
217770x00000000,
217780x00000000,
217790x00000000,
217800x00000000,
217810x00000000,
217820x00000000,
217830x00000000,
217840x00000000,
217850x00000000,
217860x00000000,
217870x00000000,
217880x00000000,
217890x00000000,
217900x00000000,
217910x00000000,
217920x00000000,
217930x00000000,
217940x00000000,
217950x00000000,
217960x00000000,
217970x00000000,
217980x00000000,
217990x00000000,
218000x00000000,
218010x00000000,
218020x00000000,
218030x00000000,
218040x00000000,
218050x00000000,
218060x00000000,
218070x00000000,
218080x00000000,
218090x00000000,
218100x00000000,
218110x00000000,
218120x00000000,
218130x00000000,
218140x00000000,
218150x00000000,
218160x00000000,
218170x00000000,
218180x00000000,
218190x00000000,
218200x00000000,
218210x00000000,
218220x00000000,
218230x00000000,
218240x00000000,
218250x00000000,
218260x00000000,
218270x00000000,
218280x00000000,
218290x00000000,
218300x00000000,
218310x00000000,
218320x00000000,
218330x00000000,
218340x00000000,
218350x00000000,
218360x00000000,
218370x00000000,
218380x00000000,
218390x00000000,
218400x00000000,
218410x00000000,
218420x00000000,
218430x00000000,
218440x00000000,
218450x00000000,
218460x00000000,
218470x00000000,
218480x00000000,
218490x00000000,
218500x00000000,
218510x00000000,
218520x00030222,
218530x0004022a,
218540x0005009f,
218550x00020003,
218560x0006003c,
218570x00070027,
218580x00080191,
218590x00090044,
218600x000a002d,
218610x00100247,
218620x001700f0,
218630x002201d7,
218640x002301e8,
218650x0026004c,
218660x0027005f,
218670x0020011a,
218680x00280092,
218690x0029004f,
218700x002a0083,
218710x002b0064,
218720x002f008d,
218730x003200d8,
218740x00340232,
218750x00360074,
218760x0039010a,
218770x003c01fc,
218780x003f009f,
218790x00410005,
218800x00440194,
218810x0048019d,
218820x004901c5,
218830x004a01cf,
218840x00550225,
218850x0056022d,
218860x0060000a,
218870x0061002a,
218880x00620030,
218890x00630030,
218900x00640030,
218910x00650030,
218920x00660030,
218930x00670030,
218940x00680037,
218950x0069003f,
218960x006a0047,
218970x006b0047,
218980x006c0047,
218990x006d0047,
219000x006e0047,
219010x006f0047,
219020x00700047,
219030x00730247,
219040x007b0240,
219050x00000005,
219060x00000005,
219070x00000005,
219080x00000005,
219090x00000005,
219100x00000005,
219110x00000005,
219120x00000005,
219130x00000005,
219140x00000005,
219150x00000005,
219160x00000005,
219170x00000005,
219180x00000005,
219190x00000005,
219200x00000005,
219210x00000005,
219220x00000005,
219230x00000005,
219240x00000005,
219250x00000005,
219260x00000005,
219270x00000005,
219280x00000005,
219290x00000005,
219300x00000005,
219310x00000005,
21932};
21933
21934static const u32 RV710_cp_microcode[] = {
219350xcc0003ea,
219360x04080003,
219370xcc800043,
219380x7c408000,
219390xa0000000,
219400xcc800062,
219410x80000003,
219420xd040007f,
219430x80000003,
219440xcc400041,
219450x7c40c000,
219460xc0160004,
219470x30d03fff,
219480x7d15000c,
219490xcc110000,
219500x28d8001e,
219510x31980001,
219520x28dc001f,
219530xc8200004,
219540x95c00006,
219550x7c424000,
219560xcc000062,
219570x7e56800c,
219580xcc290000,
219590xc8240004,
219600x7e26000b,
219610x95800006,
219620x7c42c000,
219630xcc000062,
219640x7ed7000c,
219650xcc310000,
219660xc82c0004,
219670x7e2e000c,
219680xcc000062,
219690x31103fff,
219700x80000003,
219710xce110000,
219720x7c40c000,
219730x80000003,
219740xcc400040,
219750x80000003,
219760xcc412257,
219770x7c418000,
219780xcc400045,
219790xcc400048,
219800xcc41225c,
219810xcc41a1fc,
219820x7c408000,
219830xa0000000,
219840xcc800062,
219850xcc400045,
219860xcc400048,
219870x7c40c000,
219880xcc41225c,
219890xcc41a1fc,
219900x7c408000,
219910xa0000000,
219920xcc800062,
219930xcc000045,
219940xcc000048,
219950xcc41225c,
219960xcc41a1fc,
219970x7c408000,
219980xa0000000,
219990xcc800062,
220000x040ca1fd,
220010xc0120001,
220020xcc000045,
220030xcc000048,
220040x7cd0c00c,
220050xcc41225c,
220060xcc41a1fc,
220070xd04d0000,
220080x7c408000,
220090xa0000000,
220100xcc800062,
220110x80000003,
220120xcc41225d,
220130x7c408000,
220140x7c40c000,
220150xc02a0002,
220160x7c410000,
220170x7d29000c,
220180x30940001,
220190x30980006,
220200x309c0300,
220210x29dc0008,
220220x7c420000,
220230x7c424000,
220240x9540000f,
220250xc02e0004,
220260x05f02258,
220270x7f2f000c,
220280xcc310000,
220290xc8280004,
220300xccc12169,
220310xcd01216a,
220320xce81216b,
220330x0db40002,
220340xcc01216c,
220350x9740000e,
220360x0db40000,
220370x8000007d,
220380xc834000a,
220390x0db40002,
220400x97400009,
220410x0db40000,
220420xc02e0004,
220430x05f02258,
220440x7f2f000c,
220450xcc310000,
220460xc8280004,
220470x8000007d,
220480xc834000a,
220490x97400004,
220500x7e028000,
220510x8000007d,
220520xc834000a,
220530x0db40004,
220540x9740ff8c,
220550x00000000,
220560xce01216d,
220570xce41216e,
220580xc8280003,
220590xc834000a,
220600x9b400004,
220610x043c0005,
220620x8400026d,
220630xcc000062,
220640x0df40000,
220650x9740000b,
220660xc82c03e6,
220670xce81a2b7,
220680xc0300006,
220690x7ef34028,
220700xc0300020,
220710x7f6b8020,
220720x7fb3c029,
220730xcf81a2c4,
220740x80000003,
220750xcfc1a2d1,
220760x0df40001,
220770x9740000b,
220780xc82c03e7,
220790xce81a2bb,
220800xc0300006,
220810x7ef34028,
220820xc0300020,
220830x7f6b8020,
220840x7fb3c029,
220850xcf81a2c5,
220860x80000003,
220870xcfc1a2d2,
220880x0df40002,
220890x9740000b,
220900xc82c03e8,
220910xce81a2bf,
220920xc0300006,
220930x7ef34028,
220940xc0300020,
220950x7f6b8020,
220960x7fb3c029,
220970xcf81a2c6,
220980x80000003,
220990xcfc1a2d3,
221000xc82c03e9,
221010xce81a2c3,
221020xc0300006,
221030x7ef34028,
221040xc0300020,
221050x7f6b8020,
221060x7fb3c029,
221070xcf81a2c7,
221080x80000003,
221090xcfc1a2d4,
221100x80000003,
221110xcc400042,
221120x7c40c000,
221130x7c410000,
221140x2914001d,
221150x31540001,
221160x9940000c,
221170x31181000,
221180xc81c0011,
221190x95c00000,
221200xc81c0011,
221210xccc12100,
221220xcd012101,
221230xccc12102,
221240xcd012103,
221250x04180004,
221260x8000037e,
221270xcd81a2a4,
221280xc02a0004,
221290x95800008,
221300x36a821a3,
221310xcc290000,
221320xc8280004,
221330xc81c0011,
221340x0de40040,
221350x9640ffff,
221360xc81c0011,
221370xccc12170,
221380xcd012171,
221390xc8200012,
221400x96000000,
221410xc8200012,
221420x8000037e,
221430xcc000064,
221440x7c40c000,
221450x7c410000,
221460xcc000045,
221470xcc000048,
221480x40d40003,
221490xcd41225c,
221500xcd01a1fc,
221510xc01a0001,
221520x041ca1fd,
221530x7dd9c00c,
221540x7c420000,
221550x08cc0001,
221560x06240001,
221570x06280002,
221580xce1d0000,
221590xce5d0000,
221600x98c0fffa,
221610xce9d0000,
221620x7c408000,
221630xa0000000,
221640xcc800062,
221650x7c40c000,
221660x30d00001,
221670x28cc0001,
221680x7c414000,
221690x95000006,
221700x7c418000,
221710xcd41216d,
221720xcd81216e,
221730x800000f4,
221740xc81c0003,
221750xc0220004,
221760x7e16000c,
221770xcc210000,
221780xc81c0004,
221790x7c424000,
221800x98c00004,
221810x7c428000,
221820x80000003,
221830xcde50000,
221840xce412169,
221850xce81216a,
221860xcdc1216b,
221870x80000003,
221880xcc01216c,
221890x7c40c000,
221900x7c410000,
221910x7c414000,
221920x7c418000,
221930x7c41c000,
221940x28a40008,
221950x326400ff,
221960x0e68003c,
221970x9680000a,
221980x7c020000,
221990x7c420000,
222000x1e300003,
222010xcc00006a,
222020x9b000003,
222030x42200005,
222040x04200040,
222050x80000111,
222060x7c024000,
222070x7e024000,
222080x9a400000,
222090x0a640001,
222100x30ec0010,
222110x9ac0000a,
222120xcc000062,
222130xc02a0004,
222140xc82c0021,
222150x7e92800c,
222160xcc000041,
222170xcc290000,
222180xcec00021,
222190x80000121,
222200xc8300004,
222210xcd01216d,
222220xcd41216e,
222230xc8300003,
222240x7f1f000b,
222250x30f40007,
222260x27780001,
222270x9740002a,
222280x07b80126,
222290x9f800000,
222300x00000000,
222310x80000136,
222320x7f1b8004,
222330x8000013a,
222340x7f1b8005,
222350x8000013e,
222360x7f1b8002,
222370x80000142,
222380x7f1b8003,
222390x80000146,
222400x7f1b8007,
222410x8000014a,
222420x7f1b8006,
222430x8000014f,
222440x28a40008,
222450x9b800019,
222460x28a40008,
222470x8000015f,
222480x326400ff,
222490x9b800015,
222500x28a40008,
222510x8000015f,
222520x326400ff,
222530x9b800011,
222540x28a40008,
222550x8000015f,
222560x326400ff,
222570x9b80000d,
222580x28a40008,
222590x8000015f,
222600x326400ff,
222610x9b800009,
222620x28a40008,
222630x8000015f,
222640x326400ff,
222650x9b800005,
222660x28a40008,
222670x8000015f,
222680x326400ff,
222690x28a40008,
222700x326400ff,
222710x0e68003c,
222720x9a80feb2,
222730x28ec0008,
222740x7c434000,
222750x7c438000,
222760x7c43c000,
222770x96c00007,
222780xcc000062,
222790xcf412169,
222800xcf81216a,
222810xcfc1216b,
222820x80000003,
222830xcc01216c,
222840x80000003,
222850xcff50000,
222860xcc00006b,
222870x84000381,
222880x0e68003c,
222890x9a800004,
222900xc8280015,
222910x80000003,
222920xd040007f,
222930x9680ffab,
222940x7e024000,
222950x8400023b,
222960xc00e0002,
222970xcc000041,
222980x80000239,
222990xccc1304a,
223000x7c40c000,
223010x7c410000,
223020xc01e0001,
223030x29240012,
223040xc0220002,
223050x96400005,
223060xc0260004,
223070xc027fffb,
223080x7d25000b,
223090xc0260000,
223100x7dd2800b,
223110x7e12c00b,
223120x7d25000c,
223130x7c414000,
223140x7c418000,
223150xccc12169,
223160x9a80000a,
223170xcd01216a,
223180xcd41216b,
223190x96c0fe83,
223200xcd81216c,
223210xc8300018,
223220x97000000,
223230xc8300018,
223240x80000003,
223250xcc000018,
223260x84000381,
223270xcc00007f,
223280xc8140013,
223290xc8180014,
223300xcd41216b,
223310x96c0fe77,
223320xcd81216c,
223330x80000183,
223340xc8300018,
223350xc80c0008,
223360x98c00000,
223370xc80c0008,
223380x7c410000,
223390x95000002,
223400x00000000,
223410x7c414000,
223420xc8200009,
223430xcc400043,
223440xce01a1f4,
223450xcc400044,
223460xc00e8000,
223470x7c424000,
223480x7c428000,
223490x2aac001f,
223500x96c0fe64,
223510xc035f000,
223520xce4003e2,
223530x32780003,
223540x267c0008,
223550x7ff7c00b,
223560x7ffbc00c,
223570x2a780018,
223580xcfc003e3,
223590xcf8003e4,
223600x26b00002,
223610x7f3f0000,
223620xcf0003e5,
223630x8000031f,
223640x7c80c000,
223650x7c40c000,
223660x28d00008,
223670x3110000f,
223680x9500000f,
223690x25280001,
223700x06a801b4,
223710x9e800000,
223720x00000000,
223730x800001d5,
223740xc0120800,
223750x800001e3,
223760xc814000f,
223770x800001ea,
223780xc8140010,
223790x800001f1,
223800xccc1a2a4,
223810x800001fa,
223820xc8140011,
223830x30d0003f,
223840x0d280015,
223850x9a800012,
223860x0d28001e,
223870x9a80001e,
223880x0d280020,
223890x9a800023,
223900x0d24000f,
223910x0d280010,
223920x7e6a800c,
223930x9a800026,
223940x0d200004,
223950x0d240014,
223960x0d280028,
223970x7e62400c,
223980x7ea6800c,
223990x9a80002a,
224000xc8140011,
224010x80000003,
224020xccc1a2a4,
224030xc0120800,
224040x7c414000,
224050x7d0cc00c,
224060xc0120008,
224070x29580003,
224080x295c000c,
224090x7c420000,
224100x7dd1c00b,
224110x26200014,
224120x7e1e400c,
224130x7e4e800c,
224140xce81a2a4,
224150x80000003,
224160xcd81a1fe,
224170xc814000f,
224180x0410210e,
224190x95400000,
224200xc814000f,
224210xd0510000,
224220x80000003,
224230xccc1a2a4,
224240xc8140010,
224250x04102108,
224260x95400000,
224270xc8140010,
224280xd0510000,
224290x80000003,
224300xccc1a2a4,
224310xccc1a2a4,
224320x04100001,
224330xcd000019,
224340x84000381,
224350xcc00007f,
224360xc8100019,
224370x99000000,
224380xc8100019,
224390x80000004,
224400x7c408000,
224410x04102100,
224420x95400000,
224430xc8140011,
224440xd0510000,
224450x8000037e,
224460xccc1a2a4,
224470x7c40c000,
224480xcc40000d,
224490x94c0fe01,
224500xcc40000e,
224510x7c410000,
224520x95000005,
224530x08cc0001,
224540xc8140005,
224550x99400014,
224560x00000000,
224570x98c0fffb,
224580x7c410000,
224590x80000004,
224600x7d008000,
224610xc8140005,
224620x7c40c000,
224630x9940000c,
224640xc818000c,
224650x7c410000,
224660x9580fdf0,
224670xc820000e,
224680xc81c000d,
224690x66200020,
224700x7e1e002c,
224710x25240002,
224720x7e624020,
224730x80000003,
224740xcce60000,
224750x7c410000,
224760xcc00006c,
224770xcc00006d,
224780xc818001f,
224790xc81c001e,
224800x65980020,
224810x7dd9c02c,
224820x7cd4c00c,
224830xccde0000,
224840x45dc0004,
224850xc8280017,
224860x9680000f,
224870xc00e0001,
224880x28680008,
224890x2aac0016,
224900x32a800ff,
224910x0eb00049,
224920x7f2f000b,
224930x97000006,
224940x00000000,
224950xc8140005,
224960x7c40c000,
224970x80000223,
224980x7c410000,
224990x80000226,
225000xd040007f,
225010x8400023b,
225020xcc000041,
225030xccc1304a,
225040x94000000,
225050xc83c001a,
225060x043c0005,
225070xcfc1a2a4,
225080xc0361f90,
225090xc0387fff,
225100x7c03c010,
225110x7f7b400c,
225120xcf41217c,
225130xcfc1217d,
225140xcc01217e,
225150xc03a0004,
225160x0434217f,
225170x7f7b400c,
225180xcc350000,
225190xc83c0004,
225200x2bfc001f,
225210x04380020,
225220x97c00005,
225230xcc000062,
225240x9b800000,
225250x0bb80001,
225260x80000247,
225270xcc000071,
225280xcc01a1f4,
225290x04380016,
225300xc0360002,
225310xcf81a2a4,
225320x88000000,
225330xcf412010,
225340x7c40c000,
225350x28d0001c,
225360x95000005,
225370x04d40001,
225380xcd400065,
225390x80000003,
225400xcd400068,
225410x09540002,
225420x80000003,
225430xcd400066,
225440x8400026c,
225450xc81803ea,
225460x7c40c000,
225470x9980fd9f,
225480xc8140016,
225490x08d00001,
225500x9940002b,
225510xcd000068,
225520x7c408000,
225530xa0000000,
225540xcc800062,
225550x043c0005,
225560xcfc1a2a4,
225570xcc01a1f4,
225580x84000381,
225590xcc000046,
225600x88000000,
225610xcc00007f,
225620x8400027e,
225630xc81803ea,
225640x7c40c000,
225650x9980fd8d,
225660xc8140016,
225670x08d00001,
225680x99400019,
225690xcd000068,
225700x7c408000,
225710xa0000000,
225720xcc800062,
225730x043c0022,
225740xcfc1a2a4,
225750x84000381,
225760xcc000047,
225770x88000000,
225780xcc00007f,
225790xc8100016,
225800x9900000d,
225810xcc400067,
225820x80000004,
225830x7c408000,
225840xc81803ea,
225850x9980fd79,
225860x7c40c000,
225870x94c00003,
225880xc8100016,
225890x99000004,
225900xccc00068,
225910x80000004,
225920x7c408000,
225930x8400023b,
225940xc0148000,
225950xcc000041,
225960xcd41304a,
225970xc0148000,
225980x99000000,
225990xc8100016,
226000x80000004,
226010x7c408000,
226020xc0120001,
226030x7c51400c,
226040x80000003,
226050xd0550000,
226060x7c40c000,
226070x7c410000,
226080x7c414000,
226090x7c418000,
226100x291c001f,
226110xccc0004a,
226120xcd00004b,
226130x95c00003,
226140xc01c8000,
226150xcdc12010,
226160xdd830000,
226170x055c2000,
226180xcc000062,
226190x80000003,
226200xd81f4100,
226210x7c40c000,
226220x7c410000,
226230x7c414000,
226240x7c418000,
226250xccc0004c,
226260xcd00004d,
226270xdd830000,
226280x055ca000,
226290x80000003,
226300xd81f4100,
226310x7c40c000,
226320x7c410000,
226330x7c414000,
226340x7c418000,
226350xccc0004e,
226360xcd00004f,
226370xdd830000,
226380x055cc000,
226390x80000003,
226400xd81f4100,
226410x7c40c000,
226420x7c410000,
226430x7c414000,
226440x7c418000,
226450xccc00050,
226460xcd000051,
226470xdd830000,
226480x055cf8e0,
226490x80000003,
226500xd81f4100,
226510x7c40c000,
226520x7c410000,
226530x7c414000,
226540x7c418000,
226550xccc00052,
226560xcd000053,
226570xdd830000,
226580x055cf880,
226590x80000003,
226600xd81f4100,
226610x7c40c000,
226620x7c410000,
226630x7c414000,
226640x7c418000,
226650xccc00054,
226660xcd000055,
226670xdd830000,
226680x055ce000,
226690x80000003,
226700xd81f4100,
226710x7c40c000,
226720x7c410000,
226730x7c414000,
226740x7c418000,
226750xccc00056,
226760xcd000057,
226770xdd830000,
226780x055cf000,
226790x80000003,
226800xd81f4100,
226810x7c40c000,
226820x7c410000,
226830x7c414000,
226840x7c418000,
226850xccc00058,
226860xcd000059,
226870xdd830000,
226880x055cf3fc,
226890x80000003,
226900xd81f4100,
226910xd0432000,
226920x7c408000,
226930xa0000000,
226940xcc800062,
226950xd043a000,
226960x7c408000,
226970xa0000000,
226980xcc800062,
226990xd043c000,
227000x7c408000,
227010xa0000000,
227020xcc800062,
227030xd043f8e0,
227040x7c408000,
227050xa0000000,
227060xcc800062,
227070xd043f880,
227080x7c408000,
227090xa0000000,
227100xcc800062,
227110xd043e000,
227120x7c408000,
227130xa0000000,
227140xcc800062,
227150xd043f000,
227160x7c408000,
227170xa0000000,
227180xcc800062,
227190xd043f3fc,
227200x7c408000,
227210xa0000000,
227220xcc800062,
227230xc81403e0,
227240xcc430000,
227250xcc430000,
227260xcc430000,
227270x7d45c000,
227280xcdc30000,
227290xd0430000,
227300x7c408000,
227310xa0000000,
227320xcc800062,
227330x7c40c000,
227340xc81003e2,
227350xc81403e5,
227360xc81803e3,
227370xc81c03e4,
227380xcd812169,
227390xcdc1216a,
227400xccc1216b,
227410xcc01216c,
227420x04200004,
227430x7da18000,
227440x7d964002,
227450x9640fcd9,
227460xcd8003e3,
227470x31280003,
227480xc02df000,
227490x25180008,
227500x7dad800b,
227510x7da9800c,
227520x80000003,
227530xcd8003e3,
227540x308cffff,
227550xd04d0000,
227560x7c408000,
227570xa0000000,
227580xcc800062,
227590xc8140020,
227600x15580002,
227610x9580ffff,
227620xc8140020,
227630xcc00006e,
227640xcc412180,
227650x7c40c000,
227660xccc1218d,
227670xcc412181,
227680x28d0001f,
227690x34588000,
227700xcd81218c,
227710x9500fcbf,
227720xcc412182,
227730xc8140020,
227740x9940ffff,
227750xc8140020,
227760x80000004,
227770x7c408000,
227780x7c40c000,
227790x28d00018,
227800x31100001,
227810xc0160080,
227820x95000003,
227830xc02a0004,
227840x7cd4c00c,
227850xccc1217c,
227860xcc41217d,
227870xcc41217e,
227880x7c418000,
227890x1db00003,
227900x36a0217f,
227910x9b000003,
227920x419c0005,
227930x041c0040,
227940x99c00000,
227950x09dc0001,
227960xcc210000,
227970xc8240004,
227980x2a6c001f,
227990x419c0005,
228000x9ac0fffa,
228010xcc800062,
228020x80000004,
228030x7c408000,
228040x7c40c000,
228050x04d403e6,
228060x80000003,
228070xcc540000,
228080x8000037e,
228090xcc4003ea,
228100xc01c8000,
228110x044ca000,
228120xcdc12010,
228130x7c410000,
228140xc8140009,
228150x04180000,
228160x041c0008,
228170xcd800071,
228180x09dc0001,
228190x05980001,
228200xcd0d0000,
228210x99c0fffc,
228220xcc800062,
228230x8000037e,
228240xcd400071,
228250xc00e0100,
228260xcc000041,
228270xccc1304a,
228280xc83c007f,
228290xcc00007f,
228300x80000003,
228310xcc00007f,
228320xcc00007f,
228330x88000000,
228340xcc00007f,
228350x00000000,
228360x00000000,
228370x00000000,
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228390x00000000,
228400x00000000,
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228690x00000000,
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228990x00000000,
229000x00000000,
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229100x00000000,
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232150x00010333,
232160x00100006,
232170x00170008,
232180x0021000a,
232190x0027002a,
232200x00280025,
232210x0029002b,
232220x002a0028,
232230x002b002b,
232240x002d003a,
232250x002e0041,
232260x002f004c,
232270x0034004e,
232280x00360032,
232290x003900b1,
232300x003a00d1,
232310x003b00e6,
232320x003c00fe,
232330x003d016d,
232340x003f00af,
232350x00410338,
232360x0043034b,
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232390x004601ae,
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232410x00480200,
232420x0049020e,
232430x004a0257,
232440x004b0284,
232450x00520261,
232460x00530273,
232470x00540289,
232480x0057029b,
232490x0060029f,
232500x006102ae,
232510x006202b8,
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232550x006602e0,
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232570x006802f4,
232580x006902f8,
232590x006a02fc,
232600x006b0300,
232610x006c0304,
232620x006d0308,
232630x006e030c,
232640x006f0310,
232650x00700314,
232660x00720365,
232670x0074036b,
232680x00790369,
232690x007c031e,
232700x000f037a,
232710x000f037a,
232720x000f037a,
232730x000f037a,
232740x000f037a,
232750x000f037a,
232760x000f037a,
232770x000f037a,
232780x000f037a,
232790x000f037a,
232800x000f037a,
232810x000f037a,
232820x000f037a,
232830x000f037a,
232840x000f037a,
232850x000f037a,
232860x000f037a,
232870x000f037a,
232880x000f037a,
232890x000f037a,
232900x000f037a,
232910x000f037a,
232920x000f037a,
232930x000f037a,
232940x000f037a,
23295};
23296
23297#endif
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
new file mode 100644
index 000000000000..4a9028a85c9b
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -0,0 +1,662 @@
1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 * Jerome Glisse
26 */
27#ifndef R600D_H
28#define R600D_H
29
30#define CP_PACKET2 0x80000000
31#define PACKET2_PAD_SHIFT 0
32#define PACKET2_PAD_MASK (0x3fffffff << 0)
33
34#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
35
36#define R6XX_MAX_SH_GPRS 256
37#define R6XX_MAX_TEMP_GPRS 16
38#define R6XX_MAX_SH_THREADS 256
39#define R6XX_MAX_SH_STACK_ENTRIES 4096
40#define R6XX_MAX_BACKENDS 8
41#define R6XX_MAX_BACKENDS_MASK 0xff
42#define R6XX_MAX_SIMDS 8
43#define R6XX_MAX_SIMDS_MASK 0xff
44#define R6XX_MAX_PIPES 8
45#define R6XX_MAX_PIPES_MASK 0xff
46
47/* PTE flags */
48#define PTE_VALID (1 << 0)
49#define PTE_SYSTEM (1 << 1)
50#define PTE_SNOOPED (1 << 2)
51#define PTE_READABLE (1 << 5)
52#define PTE_WRITEABLE (1 << 6)
53
54/* Registers */
55#define ARB_POP 0x2418
56#define ENABLE_TC128 (1 << 30)
57#define ARB_GDEC_RD_CNTL 0x246C
58
59#define CC_GC_SHADER_PIPE_CONFIG 0x8950
60#define CC_RB_BACKEND_DISABLE 0x98F4
61#define BACKEND_DISABLE(x) ((x) << 16)
62
63#define CB_COLOR0_BASE 0x28040
64#define CB_COLOR1_BASE 0x28044
65#define CB_COLOR2_BASE 0x28048
66#define CB_COLOR3_BASE 0x2804C
67#define CB_COLOR4_BASE 0x28050
68#define CB_COLOR5_BASE 0x28054
69#define CB_COLOR6_BASE 0x28058
70#define CB_COLOR7_BASE 0x2805C
71#define CB_COLOR7_FRAG 0x280FC
72
73#define CB_COLOR0_SIZE 0x28060
74#define CB_COLOR0_VIEW 0x28080
75#define CB_COLOR0_INFO 0x280a0
76#define CB_COLOR0_TILE 0x280c0
77#define CB_COLOR0_FRAG 0x280e0
78#define CB_COLOR0_MASK 0x28100
79
80#define CONFIG_MEMSIZE 0x5428
81#define CONFIG_CNTL 0x5424
82#define CP_STAT 0x8680
83#define CP_COHER_BASE 0x85F8
84#define CP_DEBUG 0xC1FC
85#define R_0086D8_CP_ME_CNTL 0x86D8
86#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28)
87#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF)
88#define CP_ME_RAM_DATA 0xC160
89#define CP_ME_RAM_RADDR 0xC158
90#define CP_ME_RAM_WADDR 0xC15C
91#define CP_MEQ_THRESHOLDS 0x8764
92#define MEQ_END(x) ((x) << 16)
93#define ROQ_END(x) ((x) << 24)
94#define CP_PERFMON_CNTL 0x87FC
95#define CP_PFP_UCODE_ADDR 0xC150
96#define CP_PFP_UCODE_DATA 0xC154
97#define CP_QUEUE_THRESHOLDS 0x8760
98#define ROQ_IB1_START(x) ((x) << 0)
99#define ROQ_IB2_START(x) ((x) << 8)
100#define CP_RB_BASE 0xC100
101#define CP_RB_CNTL 0xC104
102#define RB_BUFSZ(x) ((x)<<0)
103#define RB_BLKSZ(x) ((x)<<8)
104#define RB_NO_UPDATE (1<<27)
105#define RB_RPTR_WR_ENA (1<<31)
106#define BUF_SWAP_32BIT (2 << 16)
107#define CP_RB_RPTR 0x8700
108#define CP_RB_RPTR_ADDR 0xC10C
109#define CP_RB_RPTR_ADDR_HI 0xC110
110#define CP_RB_RPTR_WR 0xC108
111#define CP_RB_WPTR 0xC114
112#define CP_RB_WPTR_ADDR 0xC118
113#define CP_RB_WPTR_ADDR_HI 0xC11C
114#define CP_RB_WPTR_DELAY 0x8704
115#define CP_ROQ_IB1_STAT 0x8784
116#define CP_ROQ_IB2_STAT 0x8788
117#define CP_SEM_WAIT_TIMER 0x85BC
118
119#define DB_DEBUG 0x9830
120#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
121#define DB_DEPTH_BASE 0x2800C
122#define DB_WATERMARKS 0x9838
123#define DEPTH_FREE(x) ((x) << 0)
124#define DEPTH_FLUSH(x) ((x) << 5)
125#define DEPTH_PENDING_FREE(x) ((x) << 15)
126#define DEPTH_CACHELINE_FREE(x) ((x) << 20)
127
128#define DCP_TILING_CONFIG 0x6CA0
129#define PIPE_TILING(x) ((x) << 1)
130#define BANK_TILING(x) ((x) << 4)
131#define GROUP_SIZE(x) ((x) << 6)
132#define ROW_TILING(x) ((x) << 8)
133#define BANK_SWAPS(x) ((x) << 11)
134#define SAMPLE_SPLIT(x) ((x) << 14)
135#define BACKEND_MAP(x) ((x) << 16)
136
137#define GB_TILING_CONFIG 0x98F0
138
139#define GC_USER_SHADER_PIPE_CONFIG 0x8954
140#define INACTIVE_QD_PIPES(x) ((x) << 8)
141#define INACTIVE_QD_PIPES_MASK 0x0000FF00
142#define INACTIVE_SIMDS(x) ((x) << 16)
143#define INACTIVE_SIMDS_MASK 0x00FF0000
144
145#define SQ_CONFIG 0x8c00
146# define VC_ENABLE (1 << 0)
147# define EXPORT_SRC_C (1 << 1)
148# define DX9_CONSTS (1 << 2)
149# define ALU_INST_PREFER_VECTOR (1 << 3)
150# define DX10_CLAMP (1 << 4)
151# define CLAUSE_SEQ_PRIO(x) ((x) << 8)
152# define PS_PRIO(x) ((x) << 24)
153# define VS_PRIO(x) ((x) << 26)
154# define GS_PRIO(x) ((x) << 28)
155# define ES_PRIO(x) ((x) << 30)
156#define SQ_GPR_RESOURCE_MGMT_1 0x8c04
157# define NUM_PS_GPRS(x) ((x) << 0)
158# define NUM_VS_GPRS(x) ((x) << 16)
159# define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
160#define SQ_GPR_RESOURCE_MGMT_2 0x8c08
161# define NUM_GS_GPRS(x) ((x) << 0)
162# define NUM_ES_GPRS(x) ((x) << 16)
163#define SQ_THREAD_RESOURCE_MGMT 0x8c0c
164# define NUM_PS_THREADS(x) ((x) << 0)
165# define NUM_VS_THREADS(x) ((x) << 8)
166# define NUM_GS_THREADS(x) ((x) << 16)
167# define NUM_ES_THREADS(x) ((x) << 24)
168#define SQ_STACK_RESOURCE_MGMT_1 0x8c10
169# define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
170# define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
171#define SQ_STACK_RESOURCE_MGMT_2 0x8c14
172# define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
173# define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
174
175#define GRBM_CNTL 0x8000
176# define GRBM_READ_TIMEOUT(x) ((x) << 0)
177#define GRBM_STATUS 0x8010
178#define CMDFIFO_AVAIL_MASK 0x0000001F
179#define GUI_ACTIVE (1<<31)
180#define GRBM_STATUS2 0x8014
181#define GRBM_SOFT_RESET 0x8020
182#define SOFT_RESET_CP (1<<0)
183
184#define HDP_HOST_PATH_CNTL 0x2C00
185#define HDP_NONSURFACE_BASE 0x2C04
186#define HDP_NONSURFACE_INFO 0x2C08
187#define HDP_NONSURFACE_SIZE 0x2C0C
188#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
189#define HDP_TILING_CONFIG 0x2F3C
190
191#define MC_VM_AGP_TOP 0x2184
192#define MC_VM_AGP_BOT 0x2188
193#define MC_VM_AGP_BASE 0x218C
194#define MC_VM_FB_LOCATION 0x2180
195#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C
196#define ENABLE_L1_TLB (1 << 0)
197#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
198#define ENABLE_L1_STRICT_ORDERING (1 << 2)
199#define SYSTEM_ACCESS_MODE_MASK 0x000000C0
200#define SYSTEM_ACCESS_MODE_SHIFT 6
201#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
202#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
203#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
204#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
205#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
206#define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
207#define ENABLE_SEMAPHORE_MODE (1 << 10)
208#define ENABLE_WAIT_L2_QUERY (1 << 11)
209#define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12)
210#define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000
211#define EFFECTIVE_L1_TLB_SIZE_SHIFT 12
212#define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15)
213#define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000
214#define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15
215#define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0
216#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC
217#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204
218#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208
219#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C
220#define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200
221#define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4
222#define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8
223#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210
224#define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218
225#define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C
226#define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220
227#define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214
228#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
229#define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
230#define LOGICAL_PAGE_NUMBER_SHIFT 0
231#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
232#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
233
234#define PA_CL_ENHANCE 0x8A14
235#define CLIP_VTX_REORDER_ENA (1 << 0)
236#define NUM_CLIP_SEQ(x) ((x) << 1)
237#define PA_SC_AA_CONFIG 0x28C04
238#define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40
239#define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44
240#define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48
241#define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C
242#define S0_X(x) ((x) << 0)
243#define S0_Y(x) ((x) << 4)
244#define S1_X(x) ((x) << 8)
245#define S1_Y(x) ((x) << 12)
246#define S2_X(x) ((x) << 16)
247#define S2_Y(x) ((x) << 20)
248#define S3_X(x) ((x) << 24)
249#define S3_Y(x) ((x) << 28)
250#define S4_X(x) ((x) << 0)
251#define S4_Y(x) ((x) << 4)
252#define S5_X(x) ((x) << 8)
253#define S5_Y(x) ((x) << 12)
254#define S6_X(x) ((x) << 16)
255#define S6_Y(x) ((x) << 20)
256#define S7_X(x) ((x) << 24)
257#define S7_Y(x) ((x) << 28)
258#define PA_SC_CLIPRECT_RULE 0x2820c
259#define PA_SC_ENHANCE 0x8BF0
260#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
261#define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
262#define PA_SC_LINE_STIPPLE 0x28A0C
263#define PA_SC_LINE_STIPPLE_STATE 0x8B10
264#define PA_SC_MODE_CNTL 0x28A4C
265#define PA_SC_MULTI_CHIP_CNTL 0x8B20
266
267#define PA_SC_SCREEN_SCISSOR_TL 0x28030
268#define PA_SC_GENERIC_SCISSOR_TL 0x28240
269#define PA_SC_WINDOW_SCISSOR_TL 0x28204
270
271#define PCIE_PORT_INDEX 0x0038
272#define PCIE_PORT_DATA 0x003C
273
274#define RAMCFG 0x2408
275#define NOOFBANK_SHIFT 0
276#define NOOFBANK_MASK 0x00000001
277#define NOOFRANK_SHIFT 1
278#define NOOFRANK_MASK 0x00000002
279#define NOOFROWS_SHIFT 2
280#define NOOFROWS_MASK 0x0000001C
281#define NOOFCOLS_SHIFT 5
282#define NOOFCOLS_MASK 0x00000060
283#define CHANSIZE_SHIFT 7
284#define CHANSIZE_MASK 0x00000080
285#define BURSTLENGTH_SHIFT 8
286#define BURSTLENGTH_MASK 0x00000100
287#define CHANSIZE_OVERRIDE (1 << 10)
288
289#define SCRATCH_REG0 0x8500
290#define SCRATCH_REG1 0x8504
291#define SCRATCH_REG2 0x8508
292#define SCRATCH_REG3 0x850C
293#define SCRATCH_REG4 0x8510
294#define SCRATCH_REG5 0x8514
295#define SCRATCH_REG6 0x8518
296#define SCRATCH_REG7 0x851C
297#define SCRATCH_UMSK 0x8540
298#define SCRATCH_ADDR 0x8544
299
300#define SPI_CONFIG_CNTL 0x9100
301#define GPR_WRITE_PRIORITY(x) ((x) << 0)
302#define DISABLE_INTERP_1 (1 << 5)
303#define SPI_CONFIG_CNTL_1 0x913C
304#define VTX_DONE_DELAY(x) ((x) << 0)
305#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
306#define SPI_INPUT_Z 0x286D8
307#define SPI_PS_IN_CONTROL_0 0x286CC
308#define NUM_INTERP(x) ((x)<<0)
309#define POSITION_ENA (1<<8)
310#define POSITION_CENTROID (1<<9)
311#define POSITION_ADDR(x) ((x)<<10)
312#define PARAM_GEN(x) ((x)<<15)
313#define PARAM_GEN_ADDR(x) ((x)<<19)
314#define BARYC_SAMPLE_CNTL(x) ((x)<<26)
315#define PERSP_GRADIENT_ENA (1<<28)
316#define LINEAR_GRADIENT_ENA (1<<29)
317#define POSITION_SAMPLE (1<<30)
318#define BARYC_AT_SAMPLE_ENA (1<<31)
319#define SPI_PS_IN_CONTROL_1 0x286D0
320#define GEN_INDEX_PIX (1<<0)
321#define GEN_INDEX_PIX_ADDR(x) ((x)<<1)
322#define FRONT_FACE_ENA (1<<8)
323#define FRONT_FACE_CHAN(x) ((x)<<9)
324#define FRONT_FACE_ALL_BITS (1<<11)
325#define FRONT_FACE_ADDR(x) ((x)<<12)
326#define FOG_ADDR(x) ((x)<<17)
327#define FIXED_PT_POSITION_ENA (1<<24)
328#define FIXED_PT_POSITION_ADDR(x) ((x)<<25)
329
330#define SQ_MS_FIFO_SIZES 0x8CF0
331#define CACHE_FIFO_SIZE(x) ((x) << 0)
332#define FETCH_FIFO_HIWATER(x) ((x) << 8)
333#define DONE_FIFO_HIWATER(x) ((x) << 16)
334#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
335#define SQ_PGM_START_ES 0x28880
336#define SQ_PGM_START_FS 0x28894
337#define SQ_PGM_START_GS 0x2886C
338#define SQ_PGM_START_PS 0x28840
339#define SQ_PGM_RESOURCES_PS 0x28850
340#define SQ_PGM_EXPORTS_PS 0x28854
341#define SQ_PGM_CF_OFFSET_PS 0x288cc
342#define SQ_PGM_START_VS 0x28858
343#define SQ_PGM_RESOURCES_VS 0x28868
344#define SQ_PGM_CF_OFFSET_VS 0x288d0
345#define SQ_VTX_CONSTANT_WORD6_0 0x38018
346#define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30)
347#define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3)
348#define SQ_TEX_VTX_INVALID_TEXTURE 0x0
349#define SQ_TEX_VTX_INVALID_BUFFER 0x1
350#define SQ_TEX_VTX_VALID_TEXTURE 0x2
351#define SQ_TEX_VTX_VALID_BUFFER 0x3
352
353
354#define SX_MISC 0x28350
355#define SX_DEBUG_1 0x9054
356#define SMX_EVENT_RELEASE (1 << 0)
357#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
358
359#define TA_CNTL_AUX 0x9508
360#define DISABLE_CUBE_WRAP (1 << 0)
361#define DISABLE_CUBE_ANISO (1 << 1)
362#define SYNC_GRADIENT (1 << 24)
363#define SYNC_WALKER (1 << 25)
364#define SYNC_ALIGNER (1 << 26)
365#define BILINEAR_PRECISION_6_BIT (0 << 31)
366#define BILINEAR_PRECISION_8_BIT (1 << 31)
367
368#define TC_CNTL 0x9608
369#define TC_L2_SIZE(x) ((x)<<5)
370#define L2_DISABLE_LATE_HIT (1<<9)
371
372
373#define VGT_CACHE_INVALIDATION 0x88C4
374#define CACHE_INVALIDATION(x) ((x)<<0)
375#define VC_ONLY 0
376#define TC_ONLY 1
377#define VC_AND_TC 2
378#define VGT_DMA_BASE 0x287E8
379#define VGT_DMA_BASE_HI 0x287E4
380#define VGT_ES_PER_GS 0x88CC
381#define VGT_GS_PER_ES 0x88C8
382#define VGT_GS_PER_VS 0x88E8
383#define VGT_GS_VERTEX_REUSE 0x88D4
384#define VGT_PRIMITIVE_TYPE 0x8958
385#define VGT_NUM_INSTANCES 0x8974
386#define VGT_OUT_DEALLOC_CNTL 0x28C5C
387#define DEALLOC_DIST_MASK 0x0000007F
388#define VGT_STRMOUT_BASE_OFFSET_0 0x28B10
389#define VGT_STRMOUT_BASE_OFFSET_1 0x28B14
390#define VGT_STRMOUT_BASE_OFFSET_2 0x28B18
391#define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c
392#define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44
393#define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48
394#define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c
395#define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50
396#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8
397#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8
398#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8
399#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08
400#define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC
401#define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC
402#define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC
403#define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C
404#define VGT_STRMOUT_EN 0x28AB0
405#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
406#define VTX_REUSE_DEPTH_MASK 0x000000FF
407#define VGT_EVENT_INITIATOR 0x28a90
408# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
409
410#define VM_CONTEXT0_CNTL 0x1410
411#define ENABLE_CONTEXT (1 << 0)
412#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
413#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
414#define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
415#define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0
416#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
417#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
418#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4
419#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554
420#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
421#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
422#define RESPONSE_TYPE_MASK 0x000000F0
423#define RESPONSE_TYPE_SHIFT 4
424#define VM_L2_CNTL 0x1400
425#define ENABLE_L2_CACHE (1 << 0)
426#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
427#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
428#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13)
429#define VM_L2_CNTL2 0x1404
430#define INVALIDATE_ALL_L1_TLBS (1 << 0)
431#define INVALIDATE_L2_CACHE (1 << 1)
432#define VM_L2_CNTL3 0x1408
433#define BANK_SELECT_0(x) (((x) & 0x1f) << 0)
434#define BANK_SELECT_1(x) (((x) & 0x1f) << 5)
435#define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10)
436#define VM_L2_STATUS 0x140C
437#define L2_BUSY (1 << 0)
438
439#define WAIT_UNTIL 0x8040
440#define WAIT_2D_IDLE_bit (1 << 14)
441#define WAIT_3D_IDLE_bit (1 << 15)
442#define WAIT_2D_IDLECLEAN_bit (1 << 16)
443#define WAIT_3D_IDLECLEAN_bit (1 << 17)
444
445
446
447/*
448 * PM4
449 */
450#define PACKET_TYPE0 0
451#define PACKET_TYPE1 1
452#define PACKET_TYPE2 2
453#define PACKET_TYPE3 3
454
455#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
456#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
457#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
458#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
459#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
460 (((reg) >> 2) & 0xFFFF) | \
461 ((n) & 0x3FFF) << 16)
462#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
463 (((op) & 0xFF) << 8) | \
464 ((n) & 0x3FFF) << 16)
465
466/* Packet 3 types */
467#define PACKET3_NOP 0x10
468#define PACKET3_INDIRECT_BUFFER_END 0x17
469#define PACKET3_SET_PREDICATION 0x20
470#define PACKET3_REG_RMW 0x21
471#define PACKET3_COND_EXEC 0x22
472#define PACKET3_PRED_EXEC 0x23
473#define PACKET3_START_3D_CMDBUF 0x24
474#define PACKET3_DRAW_INDEX_2 0x27
475#define PACKET3_CONTEXT_CONTROL 0x28
476#define PACKET3_DRAW_INDEX_IMMD_BE 0x29
477#define PACKET3_INDEX_TYPE 0x2A
478#define PACKET3_DRAW_INDEX 0x2B
479#define PACKET3_DRAW_INDEX_AUTO 0x2D
480#define PACKET3_DRAW_INDEX_IMMD 0x2E
481#define PACKET3_NUM_INSTANCES 0x2F
482#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
483#define PACKET3_INDIRECT_BUFFER_MP 0x38
484#define PACKET3_MEM_SEMAPHORE 0x39
485#define PACKET3_MPEG_INDEX 0x3A
486#define PACKET3_WAIT_REG_MEM 0x3C
487#define PACKET3_MEM_WRITE 0x3D
488#define PACKET3_INDIRECT_BUFFER 0x32
489#define PACKET3_CP_INTERRUPT 0x40
490#define PACKET3_SURFACE_SYNC 0x43
491# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
492# define PACKET3_TC_ACTION_ENA (1 << 23)
493# define PACKET3_VC_ACTION_ENA (1 << 24)
494# define PACKET3_CB_ACTION_ENA (1 << 25)
495# define PACKET3_DB_ACTION_ENA (1 << 26)
496# define PACKET3_SH_ACTION_ENA (1 << 27)
497# define PACKET3_SMX_ACTION_ENA (1 << 28)
498#define PACKET3_ME_INITIALIZE 0x44
499#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
500#define PACKET3_COND_WRITE 0x45
501#define PACKET3_EVENT_WRITE 0x46
502#define PACKET3_EVENT_WRITE_EOP 0x47
503#define PACKET3_ONE_REG_WRITE 0x57
504#define PACKET3_SET_CONFIG_REG 0x68
505#define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000
506#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
507#define PACKET3_SET_CONTEXT_REG 0x69
508#define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000
509#define PACKET3_SET_CONTEXT_REG_END 0x00029000
510#define PACKET3_SET_ALU_CONST 0x6A
511#define PACKET3_SET_ALU_CONST_OFFSET 0x00030000
512#define PACKET3_SET_ALU_CONST_END 0x00032000
513#define PACKET3_SET_BOOL_CONST 0x6B
514#define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380
515#define PACKET3_SET_BOOL_CONST_END 0x00040000
516#define PACKET3_SET_LOOP_CONST 0x6C
517#define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200
518#define PACKET3_SET_LOOP_CONST_END 0x0003e380
519#define PACKET3_SET_RESOURCE 0x6D
520#define PACKET3_SET_RESOURCE_OFFSET 0x00038000
521#define PACKET3_SET_RESOURCE_END 0x0003c000
522#define PACKET3_SET_SAMPLER 0x6E
523#define PACKET3_SET_SAMPLER_OFFSET 0x0003c000
524#define PACKET3_SET_SAMPLER_END 0x0003cff0
525#define PACKET3_SET_CTL_CONST 0x6F
526#define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0
527#define PACKET3_SET_CTL_CONST_END 0x0003e200
528#define PACKET3_SURFACE_BASE_UPDATE 0x73
529
530
531#define R_008020_GRBM_SOFT_RESET 0x8020
532#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0)
533#define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1)
534#define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2)
535#define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3)
536#define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5)
537#define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6)
538#define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7)
539#define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8)
540#define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9)
541#define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10)
542#define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11)
543#define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12)
544#define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13)
545#define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14)
546#define R_008010_GRBM_STATUS 0x8010
547#define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0)
548#define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6)
549#define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7)
550#define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8)
551#define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10)
552#define S_008010_VC_BUSY(x) (((x) & 1) << 11)
553#define S_008010_DB03_CLEAN(x) (((x) & 1) << 12)
554#define S_008010_CB03_CLEAN(x) (((x) & 1) << 13)
555#define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16)
556#define S_008010_VGT_BUSY(x) (((x) & 1) << 17)
557#define S_008010_TA03_BUSY(x) (((x) & 1) << 18)
558#define S_008010_TC_BUSY(x) (((x) & 1) << 19)
559#define S_008010_SX_BUSY(x) (((x) & 1) << 20)
560#define S_008010_SH_BUSY(x) (((x) & 1) << 21)
561#define S_008010_SPI03_BUSY(x) (((x) & 1) << 22)
562#define S_008010_SMX_BUSY(x) (((x) & 1) << 23)
563#define S_008010_SC_BUSY(x) (((x) & 1) << 24)
564#define S_008010_PA_BUSY(x) (((x) & 1) << 25)
565#define S_008010_DB03_BUSY(x) (((x) & 1) << 26)
566#define S_008010_CR_BUSY(x) (((x) & 1) << 27)
567#define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28)
568#define S_008010_CP_BUSY(x) (((x) & 1) << 29)
569#define S_008010_CB03_BUSY(x) (((x) & 1) << 30)
570#define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31)
571#define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F)
572#define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1)
573#define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1)
574#define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1)
575#define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1)
576#define G_008010_VC_BUSY(x) (((x) >> 11) & 1)
577#define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1)
578#define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1)
579#define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1)
580#define G_008010_VGT_BUSY(x) (((x) >> 17) & 1)
581#define G_008010_TA03_BUSY(x) (((x) >> 18) & 1)
582#define G_008010_TC_BUSY(x) (((x) >> 19) & 1)
583#define G_008010_SX_BUSY(x) (((x) >> 20) & 1)
584#define G_008010_SH_BUSY(x) (((x) >> 21) & 1)
585#define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1)
586#define G_008010_SMX_BUSY(x) (((x) >> 23) & 1)
587#define G_008010_SC_BUSY(x) (((x) >> 24) & 1)
588#define G_008010_PA_BUSY(x) (((x) >> 25) & 1)
589#define G_008010_DB03_BUSY(x) (((x) >> 26) & 1)
590#define G_008010_CR_BUSY(x) (((x) >> 27) & 1)
591#define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1)
592#define G_008010_CP_BUSY(x) (((x) >> 29) & 1)
593#define G_008010_CB03_BUSY(x) (((x) >> 30) & 1)
594#define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1)
595#define R_008014_GRBM_STATUS2 0x8014
596#define S_008014_CR_CLEAN(x) (((x) & 1) << 0)
597#define S_008014_SMX_CLEAN(x) (((x) & 1) << 1)
598#define S_008014_SPI0_BUSY(x) (((x) & 1) << 8)
599#define S_008014_SPI1_BUSY(x) (((x) & 1) << 9)
600#define S_008014_SPI2_BUSY(x) (((x) & 1) << 10)
601#define S_008014_SPI3_BUSY(x) (((x) & 1) << 11)
602#define S_008014_TA0_BUSY(x) (((x) & 1) << 12)
603#define S_008014_TA1_BUSY(x) (((x) & 1) << 13)
604#define S_008014_TA2_BUSY(x) (((x) & 1) << 14)
605#define S_008014_TA3_BUSY(x) (((x) & 1) << 15)
606#define S_008014_DB0_BUSY(x) (((x) & 1) << 16)
607#define S_008014_DB1_BUSY(x) (((x) & 1) << 17)
608#define S_008014_DB2_BUSY(x) (((x) & 1) << 18)
609#define S_008014_DB3_BUSY(x) (((x) & 1) << 19)
610#define S_008014_CB0_BUSY(x) (((x) & 1) << 20)
611#define S_008014_CB1_BUSY(x) (((x) & 1) << 21)
612#define S_008014_CB2_BUSY(x) (((x) & 1) << 22)
613#define S_008014_CB3_BUSY(x) (((x) & 1) << 23)
614#define G_008014_CR_CLEAN(x) (((x) >> 0) & 1)
615#define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1)
616#define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1)
617#define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1)
618#define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1)
619#define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1)
620#define G_008014_TA0_BUSY(x) (((x) >> 12) & 1)
621#define G_008014_TA1_BUSY(x) (((x) >> 13) & 1)
622#define G_008014_TA2_BUSY(x) (((x) >> 14) & 1)
623#define G_008014_TA3_BUSY(x) (((x) >> 15) & 1)
624#define G_008014_DB0_BUSY(x) (((x) >> 16) & 1)
625#define G_008014_DB1_BUSY(x) (((x) >> 17) & 1)
626#define G_008014_DB2_BUSY(x) (((x) >> 18) & 1)
627#define G_008014_DB3_BUSY(x) (((x) >> 19) & 1)
628#define G_008014_CB0_BUSY(x) (((x) >> 20) & 1)
629#define G_008014_CB1_BUSY(x) (((x) >> 21) & 1)
630#define G_008014_CB2_BUSY(x) (((x) >> 22) & 1)
631#define G_008014_CB3_BUSY(x) (((x) >> 23) & 1)
632#define R_000E50_SRBM_STATUS 0x0E50
633#define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1)
634#define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1)
635#define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1)
636#define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1)
637#define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1)
638#define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1)
639#define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1)
640#define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1)
641#define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1)
642#define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1)
643#define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1)
644#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1)
645#define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1)
646#define R_000E60_SRBM_SOFT_RESET 0x0E60
647#define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1)
648#define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2)
649#define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3)
650#define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4)
651#define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5)
652#define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8)
653#define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9)
654#define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10)
655#define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11)
656#define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13)
657#define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14)
658#define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15)
659#define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16)
660#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17)
661
662#endif
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index b519fb2fecbb..c839b608970f 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -51,7 +51,6 @@
51 51
52#include "radeon_mode.h" 52#include "radeon_mode.h"
53#include "radeon_reg.h" 53#include "radeon_reg.h"
54#include "r300.h"
55 54
56/* 55/*
57 * Modules parameters. 56 * Modules parameters.
@@ -66,6 +65,7 @@ extern int radeon_gart_size;
66extern int radeon_benchmarking; 65extern int radeon_benchmarking;
67extern int radeon_testing; 66extern int radeon_testing;
68extern int radeon_connector_table; 67extern int radeon_connector_table;
68extern int radeon_tv;
69 69
70/* 70/*
71 * Copy from radeon_drv.h so we don't have to include both and have conflicting 71 * Copy from radeon_drv.h so we don't have to include both and have conflicting
@@ -75,6 +75,7 @@ extern int radeon_connector_table;
75#define RADEON_IB_POOL_SIZE 16 75#define RADEON_IB_POOL_SIZE 16
76#define RADEON_DEBUGFS_MAX_NUM_FILES 32 76#define RADEON_DEBUGFS_MAX_NUM_FILES 32
77#define RADEONFB_CONN_LIMIT 4 77#define RADEONFB_CONN_LIMIT 4
78#define RADEON_BIOS_NUM_SCRATCH 8
78 79
79enum radeon_family { 80enum radeon_family {
80 CHIP_R100, 81 CHIP_R100,
@@ -107,14 +108,15 @@ enum radeon_family {
107 CHIP_R600, 108 CHIP_R600,
108 CHIP_RV610, 109 CHIP_RV610,
109 CHIP_RV630, 110 CHIP_RV630,
111 CHIP_RV670,
110 CHIP_RV620, 112 CHIP_RV620,
111 CHIP_RV635, 113 CHIP_RV635,
112 CHIP_RV670,
113 CHIP_RS780, 114 CHIP_RS780,
115 CHIP_RS880,
114 CHIP_RV770, 116 CHIP_RV770,
115 CHIP_RV730, 117 CHIP_RV730,
116 CHIP_RV710, 118 CHIP_RV710,
117 CHIP_RS880, 119 CHIP_RV740,
118 CHIP_LAST, 120 CHIP_LAST,
119}; 121};
120 122
@@ -151,10 +153,21 @@ struct radeon_device;
151 */ 153 */
152bool radeon_get_bios(struct radeon_device *rdev); 154bool radeon_get_bios(struct radeon_device *rdev);
153 155
156
154/* 157/*
155 * Clocks 158 * Dummy page
156 */ 159 */
160struct radeon_dummy_page {
161 struct page *page;
162 dma_addr_t addr;
163};
164int radeon_dummy_page_init(struct radeon_device *rdev);
165void radeon_dummy_page_fini(struct radeon_device *rdev);
166
157 167
168/*
169 * Clocks
170 */
158struct radeon_clock { 171struct radeon_clock {
159 struct radeon_pll p1pll; 172 struct radeon_pll p1pll;
160 struct radeon_pll p2pll; 173 struct radeon_pll p2pll;
@@ -165,6 +178,7 @@ struct radeon_clock {
165 uint32_t default_sclk; 178 uint32_t default_sclk;
166}; 179};
167 180
181
168/* 182/*
169 * Fences. 183 * Fences.
170 */ 184 */
@@ -331,14 +345,18 @@ struct radeon_mc {
331 resource_size_t aper_size; 345 resource_size_t aper_size;
332 resource_size_t aper_base; 346 resource_size_t aper_base;
333 resource_size_t agp_base; 347 resource_size_t agp_base;
334 unsigned gtt_location;
335 unsigned gtt_size;
336 unsigned vram_location;
337 /* for some chips with <= 32MB we need to lie 348 /* for some chips with <= 32MB we need to lie
338 * about vram size near mc fb location */ 349 * about vram size near mc fb location */
339 unsigned mc_vram_size; 350 u64 mc_vram_size;
351 u64 gtt_location;
352 u64 gtt_size;
353 u64 gtt_start;
354 u64 gtt_end;
355 u64 vram_location;
356 u64 vram_start;
357 u64 vram_end;
340 unsigned vram_width; 358 unsigned vram_width;
341 unsigned real_vram_size; 359 u64 real_vram_size;
342 int vram_mtrr; 360 int vram_mtrr;
343 bool vram_is_ddr; 361 bool vram_is_ddr;
344}; 362};
@@ -385,6 +403,10 @@ struct radeon_ib {
385 uint32_t length_dw; 403 uint32_t length_dw;
386}; 404};
387 405
406/*
407 * locking -
408 * mutex protects scheduled_ibs, ready, alloc_bm
409 */
388struct radeon_ib_pool { 410struct radeon_ib_pool {
389 struct mutex mutex; 411 struct mutex mutex;
390 struct radeon_object *robj; 412 struct radeon_object *robj;
@@ -410,6 +432,16 @@ struct radeon_cp {
410 bool ready; 432 bool ready;
411}; 433};
412 434
435struct r600_blit {
436 struct radeon_object *shader_obj;
437 u64 shader_gpu_addr;
438 u32 vs_offset, ps_offset;
439 u32 state_offset;
440 u32 state_len;
441 u32 vb_used, vb_total;
442 struct radeon_ib *vb_ib;
443};
444
413int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); 445int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
414void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); 446void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
415int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); 447int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
@@ -462,6 +494,7 @@ struct radeon_cs_parser {
462 int chunk_relocs_idx; 494 int chunk_relocs_idx;
463 struct radeon_ib *ib; 495 struct radeon_ib *ib;
464 void *track; 496 void *track;
497 unsigned family;
465}; 498};
466 499
467struct radeon_cs_packet { 500struct radeon_cs_packet {
@@ -558,13 +591,19 @@ int r100_debugfs_cp_init(struct radeon_device *rdev);
558 */ 591 */
559struct radeon_asic { 592struct radeon_asic {
560 int (*init)(struct radeon_device *rdev); 593 int (*init)(struct radeon_device *rdev);
594 void (*fini)(struct radeon_device *rdev);
595 int (*resume)(struct radeon_device *rdev);
596 int (*suspend)(struct radeon_device *rdev);
561 void (*errata)(struct radeon_device *rdev); 597 void (*errata)(struct radeon_device *rdev);
562 void (*vram_info)(struct radeon_device *rdev); 598 void (*vram_info)(struct radeon_device *rdev);
599 void (*vga_set_state)(struct radeon_device *rdev, bool state);
563 int (*gpu_reset)(struct radeon_device *rdev); 600 int (*gpu_reset)(struct radeon_device *rdev);
564 int (*mc_init)(struct radeon_device *rdev); 601 int (*mc_init)(struct radeon_device *rdev);
565 void (*mc_fini)(struct radeon_device *rdev); 602 void (*mc_fini)(struct radeon_device *rdev);
566 int (*wb_init)(struct radeon_device *rdev); 603 int (*wb_init)(struct radeon_device *rdev);
567 void (*wb_fini)(struct radeon_device *rdev); 604 void (*wb_fini)(struct radeon_device *rdev);
605 int (*gart_init)(struct radeon_device *rdev);
606 void (*gart_fini)(struct radeon_device *rdev);
568 int (*gart_enable)(struct radeon_device *rdev); 607 int (*gart_enable)(struct radeon_device *rdev);
569 void (*gart_disable)(struct radeon_device *rdev); 608 void (*gart_disable)(struct radeon_device *rdev);
570 void (*gart_tlb_flush)(struct radeon_device *rdev); 609 void (*gart_tlb_flush)(struct radeon_device *rdev);
@@ -572,7 +611,11 @@ struct radeon_asic {
572 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); 611 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
573 void (*cp_fini)(struct radeon_device *rdev); 612 void (*cp_fini)(struct radeon_device *rdev);
574 void (*cp_disable)(struct radeon_device *rdev); 613 void (*cp_disable)(struct radeon_device *rdev);
614 void (*cp_commit)(struct radeon_device *rdev);
575 void (*ring_start)(struct radeon_device *rdev); 615 void (*ring_start)(struct radeon_device *rdev);
616 int (*ring_test)(struct radeon_device *rdev);
617 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
618 int (*ib_test)(struct radeon_device *rdev);
576 int (*irq_set)(struct radeon_device *rdev); 619 int (*irq_set)(struct radeon_device *rdev);
577 int (*irq_process)(struct radeon_device *rdev); 620 int (*irq_process)(struct radeon_device *rdev);
578 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 621 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
@@ -604,8 +647,60 @@ struct radeon_asic {
604 void (*bandwidth_update)(struct radeon_device *rdev); 647 void (*bandwidth_update)(struct radeon_device *rdev);
605}; 648};
606 649
650/*
651 * Asic structures
652 */
653struct r100_asic {
654 const unsigned *reg_safe_bm;
655 unsigned reg_safe_bm_size;
656};
657
658struct r300_asic {
659 const unsigned *reg_safe_bm;
660 unsigned reg_safe_bm_size;
661};
662
663struct r600_asic {
664 unsigned max_pipes;
665 unsigned max_tile_pipes;
666 unsigned max_simds;
667 unsigned max_backends;
668 unsigned max_gprs;
669 unsigned max_threads;
670 unsigned max_stack_entries;
671 unsigned max_hw_contexts;
672 unsigned max_gs_threads;
673 unsigned sx_max_export_size;
674 unsigned sx_max_export_pos_size;
675 unsigned sx_max_export_smx_size;
676 unsigned sq_num_cf_insts;
677};
678
679struct rv770_asic {
680 unsigned max_pipes;
681 unsigned max_tile_pipes;
682 unsigned max_simds;
683 unsigned max_backends;
684 unsigned max_gprs;
685 unsigned max_threads;
686 unsigned max_stack_entries;
687 unsigned max_hw_contexts;
688 unsigned max_gs_threads;
689 unsigned sx_max_export_size;
690 unsigned sx_max_export_pos_size;
691 unsigned sx_max_export_smx_size;
692 unsigned sq_num_cf_insts;
693 unsigned sx_num_of_sets;
694 unsigned sc_prim_fifo_size;
695 unsigned sc_hiz_tile_fifo_size;
696 unsigned sc_earlyz_tile_fifo_fize;
697};
698
607union radeon_asic_config { 699union radeon_asic_config {
608 struct r300_asic r300; 700 struct r300_asic r300;
701 struct r100_asic r100;
702 struct r600_asic r600;
703 struct rv770_asic rv770;
609}; 704};
610 705
611 706
@@ -646,6 +741,7 @@ typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
646typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 741typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
647 742
648struct radeon_device { 743struct radeon_device {
744 struct device *dev;
649 struct drm_device *ddev; 745 struct drm_device *ddev;
650 struct pci_dev *pdev; 746 struct pci_dev *pdev;
651 /* ASIC */ 747 /* ASIC */
@@ -689,13 +785,20 @@ struct radeon_device {
689 struct radeon_asic *asic; 785 struct radeon_asic *asic;
690 struct radeon_gem gem; 786 struct radeon_gem gem;
691 struct radeon_pm pm; 787 struct radeon_pm pm;
788 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
692 struct mutex cs_mutex; 789 struct mutex cs_mutex;
693 struct radeon_wb wb; 790 struct radeon_wb wb;
791 struct radeon_dummy_page dummy_page;
694 bool gpu_lockup; 792 bool gpu_lockup;
695 bool shutdown; 793 bool shutdown;
696 bool suspend; 794 bool suspend;
697 bool need_dma32; 795 bool need_dma32;
796 bool new_init_path;
797 bool accel_working;
698 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 798 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
799 const struct firmware *me_fw; /* all family ME firmware */
800 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
801 struct r600_blit r600_blit;
699}; 802};
700 803
701int radeon_device_init(struct radeon_device *rdev, 804int radeon_device_init(struct radeon_device *rdev,
@@ -705,6 +808,13 @@ int radeon_device_init(struct radeon_device *rdev,
705void radeon_device_fini(struct radeon_device *rdev); 808void radeon_device_fini(struct radeon_device *rdev);
706int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 809int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
707 810
811/* r600 blit */
812int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
813void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
814void r600_kms_blit_copy(struct radeon_device *rdev,
815 u64 src_gpu_addr, u64 dst_gpu_addr,
816 int size_bytes);
817
708static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 818static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
709{ 819{
710 if (reg < 0x10000) 820 if (reg < 0x10000)
@@ -732,6 +842,7 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
732#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) 842#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
733#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) 843#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
734#define RREG32(reg) r100_mm_rreg(rdev, (reg)) 844#define RREG32(reg) r100_mm_rreg(rdev, (reg))
845#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
735#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) 846#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
736#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 847#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
737#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 848#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
@@ -755,6 +866,7 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
755 tmp_ |= ((val) & ~(mask)); \ 866 tmp_ |= ((val) & ~(mask)); \
756 WREG32_PLL(reg, tmp_); \ 867 WREG32_PLL(reg, tmp_); \
757 } while (0) 868 } while (0)
869#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
758 870
759/* 871/*
760 * Indirect registers accessor 872 * Indirect registers accessor
@@ -819,51 +931,6 @@ void radeon_atombios_fini(struct radeon_device *rdev);
819/* 931/*
820 * RING helpers. 932 * RING helpers.
821 */ 933 */
822#define CP_PACKET0 0x00000000
823#define PACKET0_BASE_INDEX_SHIFT 0
824#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
825#define PACKET0_COUNT_SHIFT 16
826#define PACKET0_COUNT_MASK (0x3fff << 16)
827#define CP_PACKET1 0x40000000
828#define CP_PACKET2 0x80000000
829#define PACKET2_PAD_SHIFT 0
830#define PACKET2_PAD_MASK (0x3fffffff << 0)
831#define CP_PACKET3 0xC0000000
832#define PACKET3_IT_OPCODE_SHIFT 8
833#define PACKET3_IT_OPCODE_MASK (0xff << 8)
834#define PACKET3_COUNT_SHIFT 16
835#define PACKET3_COUNT_MASK (0x3fff << 16)
836/* PACKET3 op code */
837#define PACKET3_NOP 0x10
838#define PACKET3_3D_DRAW_VBUF 0x28
839#define PACKET3_3D_DRAW_IMMD 0x29
840#define PACKET3_3D_DRAW_INDX 0x2A
841#define PACKET3_3D_LOAD_VBPNTR 0x2F
842#define PACKET3_INDX_BUFFER 0x33
843#define PACKET3_3D_DRAW_VBUF_2 0x34
844#define PACKET3_3D_DRAW_IMMD_2 0x35
845#define PACKET3_3D_DRAW_INDX_2 0x36
846#define PACKET3_BITBLT_MULTI 0x9B
847
848#define PACKET0(reg, n) (CP_PACKET0 | \
849 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
850 REG_SET(PACKET0_COUNT, (n)))
851#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
852#define PACKET3(op, n) (CP_PACKET3 | \
853 REG_SET(PACKET3_IT_OPCODE, (op)) | \
854 REG_SET(PACKET3_COUNT, (n)))
855
856#define PACKET_TYPE0 0
857#define PACKET_TYPE1 1
858#define PACKET_TYPE2 2
859#define PACKET_TYPE3 3
860
861#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
862#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
863#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
864#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
865#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
866
867static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) 934static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
868{ 935{
869#if DRM_DEBUG_CODE 936#if DRM_DEBUG_CODE
@@ -882,14 +949,20 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
882 * ASICs macro. 949 * ASICs macro.
883 */ 950 */
884#define radeon_init(rdev) (rdev)->asic->init((rdev)) 951#define radeon_init(rdev) (rdev)->asic->init((rdev))
952#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
953#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
954#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
885#define radeon_cs_parse(p) rdev->asic->cs_parse((p)) 955#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
886#define radeon_errata(rdev) (rdev)->asic->errata((rdev)) 956#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
887#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev)) 957#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
958#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
888#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) 959#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
889#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev)) 960#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
890#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev)) 961#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
891#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev)) 962#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
892#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev)) 963#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
964#define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev))
965#define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev))
893#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev)) 966#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
894#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev)) 967#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
895#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) 968#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
@@ -897,7 +970,11 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
897#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize)) 970#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
898#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev)) 971#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
899#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev)) 972#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
973#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
900#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) 974#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
975#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
976#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
977#define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev))
901#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) 978#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
902#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) 979#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
903#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) 980#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
@@ -913,4 +990,88 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
913#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) 990#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
914#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) 991#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
915 992
993/* Common functions */
994extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
995extern int radeon_modeset_init(struct radeon_device *rdev);
996extern void radeon_modeset_fini(struct radeon_device *rdev);
997extern bool radeon_card_posted(struct radeon_device *rdev);
998extern int radeon_clocks_init(struct radeon_device *rdev);
999extern void radeon_clocks_fini(struct radeon_device *rdev);
1000extern void radeon_scratch_init(struct radeon_device *rdev);
1001extern void radeon_surface_init(struct radeon_device *rdev);
1002extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1003
1004/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1005struct r100_mc_save {
1006 u32 GENMO_WT;
1007 u32 CRTC_EXT_CNTL;
1008 u32 CRTC_GEN_CNTL;
1009 u32 CRTC2_GEN_CNTL;
1010 u32 CUR_OFFSET;
1011 u32 CUR2_OFFSET;
1012};
1013extern void r100_cp_disable(struct radeon_device *rdev);
1014extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1015extern void r100_cp_fini(struct radeon_device *rdev);
1016extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
1017extern int r100_pci_gart_init(struct radeon_device *rdev);
1018extern void r100_pci_gart_fini(struct radeon_device *rdev);
1019extern int r100_pci_gart_enable(struct radeon_device *rdev);
1020extern void r100_pci_gart_disable(struct radeon_device *rdev);
1021extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
1022extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1023extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1024extern void r100_ib_fini(struct radeon_device *rdev);
1025extern int r100_ib_init(struct radeon_device *rdev);
1026extern void r100_irq_disable(struct radeon_device *rdev);
1027extern int r100_irq_set(struct radeon_device *rdev);
1028extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1029extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
1030extern void r100_vram_init_sizes(struct radeon_device *rdev);
1031extern void r100_wb_disable(struct radeon_device *rdev);
1032extern void r100_wb_fini(struct radeon_device *rdev);
1033extern int r100_wb_init(struct radeon_device *rdev);
1034
1035/* r300,r350,rv350,rv370,rv380 */
1036extern void r300_set_reg_safe(struct radeon_device *rdev);
1037extern void r300_mc_program(struct radeon_device *rdev);
1038extern void r300_vram_info(struct radeon_device *rdev);
1039extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1040extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1041extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1042extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1043
1044/* r420,r423,rv410 */
1045extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1046extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1047extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1048
1049/* rv515 */
1050extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1051
1052/* rs690, rs740 */
1053extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1054 struct drm_display_mode *mode1,
1055 struct drm_display_mode *mode2);
1056
1057/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1058extern bool r600_card_posted(struct radeon_device *rdev);
1059extern void r600_cp_stop(struct radeon_device *rdev);
1060extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1061extern int r600_cp_resume(struct radeon_device *rdev);
1062extern int r600_count_pipe_bits(uint32_t val);
1063extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1064extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1065extern int r600_pcie_gart_init(struct radeon_device *rdev);
1066extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1067extern int r600_ib_test(struct radeon_device *rdev);
1068extern int r600_ring_test(struct radeon_device *rdev);
1069extern int r600_wb_init(struct radeon_device *rdev);
1070extern void r600_wb_fini(struct radeon_device *rdev);
1071extern void r600_scratch_init(struct radeon_device *rdev);
1072extern int r600_blit_init(struct radeon_device *rdev);
1073extern void r600_blit_fini(struct radeon_device *rdev);
1074extern int r600_cp_init_microcode(struct radeon_device *rdev);
1075extern int r600_gpu_reset(struct radeon_device *rdev);
1076
916#endif 1077#endif
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 93d8f8889302..8968f78fa1e3 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -42,23 +42,28 @@ void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
42 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 42 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
43 */ 43 */
44int r100_init(struct radeon_device *rdev); 44int r100_init(struct radeon_device *rdev);
45int r200_init(struct radeon_device *rdev);
45uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); 46uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
46void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 47void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
47void r100_errata(struct radeon_device *rdev); 48void r100_errata(struct radeon_device *rdev);
48void r100_vram_info(struct radeon_device *rdev); 49void r100_vram_info(struct radeon_device *rdev);
50void r100_vga_set_state(struct radeon_device *rdev, bool state);
49int r100_gpu_reset(struct radeon_device *rdev); 51int r100_gpu_reset(struct radeon_device *rdev);
50int r100_mc_init(struct radeon_device *rdev); 52int r100_mc_init(struct radeon_device *rdev);
51void r100_mc_fini(struct radeon_device *rdev); 53void r100_mc_fini(struct radeon_device *rdev);
52u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 54u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
53int r100_wb_init(struct radeon_device *rdev); 55int r100_wb_init(struct radeon_device *rdev);
54void r100_wb_fini(struct radeon_device *rdev); 56void r100_wb_fini(struct radeon_device *rdev);
55int r100_gart_enable(struct radeon_device *rdev); 57int r100_pci_gart_init(struct radeon_device *rdev);
58void r100_pci_gart_fini(struct radeon_device *rdev);
59int r100_pci_gart_enable(struct radeon_device *rdev);
56void r100_pci_gart_disable(struct radeon_device *rdev); 60void r100_pci_gart_disable(struct radeon_device *rdev);
57void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 61void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
58int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 62int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
59int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 63int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
60void r100_cp_fini(struct radeon_device *rdev); 64void r100_cp_fini(struct radeon_device *rdev);
61void r100_cp_disable(struct radeon_device *rdev); 65void r100_cp_disable(struct radeon_device *rdev);
66void r100_cp_commit(struct radeon_device *rdev);
62void r100_ring_start(struct radeon_device *rdev); 67void r100_ring_start(struct radeon_device *rdev);
63int r100_irq_set(struct radeon_device *rdev); 68int r100_irq_set(struct radeon_device *rdev);
64int r100_irq_process(struct radeon_device *rdev); 69int r100_irq_process(struct radeon_device *rdev);
@@ -77,24 +82,34 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
77 uint32_t offset, uint32_t obj_size); 82 uint32_t offset, uint32_t obj_size);
78int r100_clear_surface_reg(struct radeon_device *rdev, int reg); 83int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
79void r100_bandwidth_update(struct radeon_device *rdev); 84void r100_bandwidth_update(struct radeon_device *rdev);
85void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
86int r100_ib_test(struct radeon_device *rdev);
87int r100_ring_test(struct radeon_device *rdev);
80 88
81static struct radeon_asic r100_asic = { 89static struct radeon_asic r100_asic = {
82 .init = &r100_init, 90 .init = &r100_init,
83 .errata = &r100_errata, 91 .errata = &r100_errata,
84 .vram_info = &r100_vram_info, 92 .vram_info = &r100_vram_info,
93 .vga_set_state = &r100_vga_set_state,
85 .gpu_reset = &r100_gpu_reset, 94 .gpu_reset = &r100_gpu_reset,
86 .mc_init = &r100_mc_init, 95 .mc_init = &r100_mc_init,
87 .mc_fini = &r100_mc_fini, 96 .mc_fini = &r100_mc_fini,
88 .wb_init = &r100_wb_init, 97 .wb_init = &r100_wb_init,
89 .wb_fini = &r100_wb_fini, 98 .wb_fini = &r100_wb_fini,
90 .gart_enable = &r100_gart_enable, 99 .gart_init = &r100_pci_gart_init,
100 .gart_fini = &r100_pci_gart_fini,
101 .gart_enable = &r100_pci_gart_enable,
91 .gart_disable = &r100_pci_gart_disable, 102 .gart_disable = &r100_pci_gart_disable,
92 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 103 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
93 .gart_set_page = &r100_pci_gart_set_page, 104 .gart_set_page = &r100_pci_gart_set_page,
94 .cp_init = &r100_cp_init, 105 .cp_init = &r100_cp_init,
95 .cp_fini = &r100_cp_fini, 106 .cp_fini = &r100_cp_fini,
96 .cp_disable = &r100_cp_disable, 107 .cp_disable = &r100_cp_disable,
108 .cp_commit = &r100_cp_commit,
97 .ring_start = &r100_ring_start, 109 .ring_start = &r100_ring_start,
110 .ring_test = &r100_ring_test,
111 .ring_ib_execute = &r100_ring_ib_execute,
112 .ib_test = &r100_ib_test,
98 .irq_set = &r100_irq_set, 113 .irq_set = &r100_irq_set,
99 .irq_process = &r100_irq_process, 114 .irq_process = &r100_irq_process,
100 .get_vblank_counter = &r100_get_vblank_counter, 115 .get_vblank_counter = &r100_get_vblank_counter,
@@ -126,7 +141,9 @@ void r300_ring_start(struct radeon_device *rdev);
126void r300_fence_ring_emit(struct radeon_device *rdev, 141void r300_fence_ring_emit(struct radeon_device *rdev,
127 struct radeon_fence *fence); 142 struct radeon_fence *fence);
128int r300_cs_parse(struct radeon_cs_parser *p); 143int r300_cs_parse(struct radeon_cs_parser *p);
129int r300_gart_enable(struct radeon_device *rdev); 144int rv370_pcie_gart_init(struct radeon_device *rdev);
145void rv370_pcie_gart_fini(struct radeon_device *rdev);
146int rv370_pcie_gart_enable(struct radeon_device *rdev);
130void rv370_pcie_gart_disable(struct radeon_device *rdev); 147void rv370_pcie_gart_disable(struct radeon_device *rdev);
131void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 148void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
132int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 149int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
@@ -143,19 +160,26 @@ static struct radeon_asic r300_asic = {
143 .init = &r300_init, 160 .init = &r300_init,
144 .errata = &r300_errata, 161 .errata = &r300_errata,
145 .vram_info = &r300_vram_info, 162 .vram_info = &r300_vram_info,
163 .vga_set_state = &r100_vga_set_state,
146 .gpu_reset = &r300_gpu_reset, 164 .gpu_reset = &r300_gpu_reset,
147 .mc_init = &r300_mc_init, 165 .mc_init = &r300_mc_init,
148 .mc_fini = &r300_mc_fini, 166 .mc_fini = &r300_mc_fini,
149 .wb_init = &r100_wb_init, 167 .wb_init = &r100_wb_init,
150 .wb_fini = &r100_wb_fini, 168 .wb_fini = &r100_wb_fini,
151 .gart_enable = &r300_gart_enable, 169 .gart_init = &r100_pci_gart_init,
170 .gart_fini = &r100_pci_gart_fini,
171 .gart_enable = &r100_pci_gart_enable,
152 .gart_disable = &r100_pci_gart_disable, 172 .gart_disable = &r100_pci_gart_disable,
153 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 173 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
154 .gart_set_page = &r100_pci_gart_set_page, 174 .gart_set_page = &r100_pci_gart_set_page,
155 .cp_init = &r100_cp_init, 175 .cp_init = &r100_cp_init,
156 .cp_fini = &r100_cp_fini, 176 .cp_fini = &r100_cp_fini,
157 .cp_disable = &r100_cp_disable, 177 .cp_disable = &r100_cp_disable,
178 .cp_commit = &r100_cp_commit,
158 .ring_start = &r300_ring_start, 179 .ring_start = &r300_ring_start,
180 .ring_test = &r100_ring_test,
181 .ring_ib_execute = &r100_ring_ib_execute,
182 .ib_test = &r100_ib_test,
159 .irq_set = &r100_irq_set, 183 .irq_set = &r100_irq_set,
160 .irq_process = &r100_irq_process, 184 .irq_process = &r100_irq_process,
161 .get_vblank_counter = &r100_get_vblank_counter, 185 .get_vblank_counter = &r100_get_vblank_counter,
@@ -176,27 +200,35 @@ static struct radeon_asic r300_asic = {
176/* 200/*
177 * r420,r423,rv410 201 * r420,r423,rv410
178 */ 202 */
179void r420_errata(struct radeon_device *rdev); 203extern int r420_init(struct radeon_device *rdev);
180void r420_vram_info(struct radeon_device *rdev); 204extern void r420_fini(struct radeon_device *rdev);
181int r420_mc_init(struct radeon_device *rdev); 205extern int r420_suspend(struct radeon_device *rdev);
182void r420_mc_fini(struct radeon_device *rdev); 206extern int r420_resume(struct radeon_device *rdev);
183static struct radeon_asic r420_asic = { 207static struct radeon_asic r420_asic = {
184 .init = &r300_init, 208 .init = &r420_init,
185 .errata = &r420_errata, 209 .fini = &r420_fini,
186 .vram_info = &r420_vram_info, 210 .suspend = &r420_suspend,
211 .resume = &r420_resume,
212 .errata = NULL,
213 .vram_info = NULL,
214 .vga_set_state = &r100_vga_set_state,
187 .gpu_reset = &r300_gpu_reset, 215 .gpu_reset = &r300_gpu_reset,
188 .mc_init = &r420_mc_init, 216 .mc_init = NULL,
189 .mc_fini = &r420_mc_fini, 217 .mc_fini = NULL,
190 .wb_init = &r100_wb_init, 218 .wb_init = NULL,
191 .wb_fini = &r100_wb_fini, 219 .wb_fini = NULL,
192 .gart_enable = &r300_gart_enable, 220 .gart_enable = NULL,
193 .gart_disable = &rv370_pcie_gart_disable, 221 .gart_disable = NULL,
194 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 222 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
195 .gart_set_page = &rv370_pcie_gart_set_page, 223 .gart_set_page = &rv370_pcie_gart_set_page,
196 .cp_init = &r100_cp_init, 224 .cp_init = NULL,
197 .cp_fini = &r100_cp_fini, 225 .cp_fini = NULL,
198 .cp_disable = &r100_cp_disable, 226 .cp_disable = NULL,
227 .cp_commit = &r100_cp_commit,
199 .ring_start = &r300_ring_start, 228 .ring_start = &r300_ring_start,
229 .ring_test = &r100_ring_test,
230 .ring_ib_execute = &r100_ring_ib_execute,
231 .ib_test = NULL,
200 .irq_set = &r100_irq_set, 232 .irq_set = &r100_irq_set,
201 .irq_process = &r100_irq_process, 233 .irq_process = &r100_irq_process,
202 .get_vblank_counter = &r100_get_vblank_counter, 234 .get_vblank_counter = &r100_get_vblank_counter,
@@ -222,6 +254,8 @@ void rs400_errata(struct radeon_device *rdev);
222void rs400_vram_info(struct radeon_device *rdev); 254void rs400_vram_info(struct radeon_device *rdev);
223int rs400_mc_init(struct radeon_device *rdev); 255int rs400_mc_init(struct radeon_device *rdev);
224void rs400_mc_fini(struct radeon_device *rdev); 256void rs400_mc_fini(struct radeon_device *rdev);
257int rs400_gart_init(struct radeon_device *rdev);
258void rs400_gart_fini(struct radeon_device *rdev);
225int rs400_gart_enable(struct radeon_device *rdev); 259int rs400_gart_enable(struct radeon_device *rdev);
226void rs400_gart_disable(struct radeon_device *rdev); 260void rs400_gart_disable(struct radeon_device *rdev);
227void rs400_gart_tlb_flush(struct radeon_device *rdev); 261void rs400_gart_tlb_flush(struct radeon_device *rdev);
@@ -232,11 +266,14 @@ static struct radeon_asic rs400_asic = {
232 .init = &r300_init, 266 .init = &r300_init,
233 .errata = &rs400_errata, 267 .errata = &rs400_errata,
234 .vram_info = &rs400_vram_info, 268 .vram_info = &rs400_vram_info,
269 .vga_set_state = &r100_vga_set_state,
235 .gpu_reset = &r300_gpu_reset, 270 .gpu_reset = &r300_gpu_reset,
236 .mc_init = &rs400_mc_init, 271 .mc_init = &rs400_mc_init,
237 .mc_fini = &rs400_mc_fini, 272 .mc_fini = &rs400_mc_fini,
238 .wb_init = &r100_wb_init, 273 .wb_init = &r100_wb_init,
239 .wb_fini = &r100_wb_fini, 274 .wb_fini = &r100_wb_fini,
275 .gart_init = &rs400_gart_init,
276 .gart_fini = &rs400_gart_fini,
240 .gart_enable = &rs400_gart_enable, 277 .gart_enable = &rs400_gart_enable,
241 .gart_disable = &rs400_gart_disable, 278 .gart_disable = &rs400_gart_disable,
242 .gart_tlb_flush = &rs400_gart_tlb_flush, 279 .gart_tlb_flush = &rs400_gart_tlb_flush,
@@ -244,7 +281,11 @@ static struct radeon_asic rs400_asic = {
244 .cp_init = &r100_cp_init, 281 .cp_init = &r100_cp_init,
245 .cp_fini = &r100_cp_fini, 282 .cp_fini = &r100_cp_fini,
246 .cp_disable = &r100_cp_disable, 283 .cp_disable = &r100_cp_disable,
284 .cp_commit = &r100_cp_commit,
247 .ring_start = &r300_ring_start, 285 .ring_start = &r300_ring_start,
286 .ring_test = &r100_ring_test,
287 .ring_ib_execute = &r100_ring_ib_execute,
288 .ib_test = &r100_ib_test,
248 .irq_set = &r100_irq_set, 289 .irq_set = &r100_irq_set,
249 .irq_process = &r100_irq_process, 290 .irq_process = &r100_irq_process,
250 .get_vblank_counter = &r100_get_vblank_counter, 291 .get_vblank_counter = &r100_get_vblank_counter,
@@ -266,7 +307,7 @@ static struct radeon_asic rs400_asic = {
266/* 307/*
267 * rs600. 308 * rs600.
268 */ 309 */
269int rs600_init(struct radeon_device *dev); 310int rs600_init(struct radeon_device *rdev);
270void rs600_errata(struct radeon_device *rdev); 311void rs600_errata(struct radeon_device *rdev);
271void rs600_vram_info(struct radeon_device *rdev); 312void rs600_vram_info(struct radeon_device *rdev);
272int rs600_mc_init(struct radeon_device *rdev); 313int rs600_mc_init(struct radeon_device *rdev);
@@ -274,6 +315,8 @@ void rs600_mc_fini(struct radeon_device *rdev);
274int rs600_irq_set(struct radeon_device *rdev); 315int rs600_irq_set(struct radeon_device *rdev);
275int rs600_irq_process(struct radeon_device *rdev); 316int rs600_irq_process(struct radeon_device *rdev);
276u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 317u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
318int rs600_gart_init(struct radeon_device *rdev);
319void rs600_gart_fini(struct radeon_device *rdev);
277int rs600_gart_enable(struct radeon_device *rdev); 320int rs600_gart_enable(struct radeon_device *rdev);
278void rs600_gart_disable(struct radeon_device *rdev); 321void rs600_gart_disable(struct radeon_device *rdev);
279void rs600_gart_tlb_flush(struct radeon_device *rdev); 322void rs600_gart_tlb_flush(struct radeon_device *rdev);
@@ -285,11 +328,14 @@ static struct radeon_asic rs600_asic = {
285 .init = &rs600_init, 328 .init = &rs600_init,
286 .errata = &rs600_errata, 329 .errata = &rs600_errata,
287 .vram_info = &rs600_vram_info, 330 .vram_info = &rs600_vram_info,
331 .vga_set_state = &r100_vga_set_state,
288 .gpu_reset = &r300_gpu_reset, 332 .gpu_reset = &r300_gpu_reset,
289 .mc_init = &rs600_mc_init, 333 .mc_init = &rs600_mc_init,
290 .mc_fini = &rs600_mc_fini, 334 .mc_fini = &rs600_mc_fini,
291 .wb_init = &r100_wb_init, 335 .wb_init = &r100_wb_init,
292 .wb_fini = &r100_wb_fini, 336 .wb_fini = &r100_wb_fini,
337 .gart_init = &rs600_gart_init,
338 .gart_fini = &rs600_gart_fini,
293 .gart_enable = &rs600_gart_enable, 339 .gart_enable = &rs600_gart_enable,
294 .gart_disable = &rs600_gart_disable, 340 .gart_disable = &rs600_gart_disable,
295 .gart_tlb_flush = &rs600_gart_tlb_flush, 341 .gart_tlb_flush = &rs600_gart_tlb_flush,
@@ -297,7 +343,11 @@ static struct radeon_asic rs600_asic = {
297 .cp_init = &r100_cp_init, 343 .cp_init = &r100_cp_init,
298 .cp_fini = &r100_cp_fini, 344 .cp_fini = &r100_cp_fini,
299 .cp_disable = &r100_cp_disable, 345 .cp_disable = &r100_cp_disable,
346 .cp_commit = &r100_cp_commit,
300 .ring_start = &r300_ring_start, 347 .ring_start = &r300_ring_start,
348 .ring_test = &r100_ring_test,
349 .ring_ib_execute = &r100_ring_ib_execute,
350 .ib_test = &r100_ib_test,
301 .irq_set = &rs600_irq_set, 351 .irq_set = &rs600_irq_set,
302 .irq_process = &rs600_irq_process, 352 .irq_process = &rs600_irq_process,
303 .get_vblank_counter = &rs600_get_vblank_counter, 353 .get_vblank_counter = &rs600_get_vblank_counter,
@@ -328,11 +378,14 @@ static struct radeon_asic rs690_asic = {
328 .init = &rs600_init, 378 .init = &rs600_init,
329 .errata = &rs690_errata, 379 .errata = &rs690_errata,
330 .vram_info = &rs690_vram_info, 380 .vram_info = &rs690_vram_info,
381 .vga_set_state = &r100_vga_set_state,
331 .gpu_reset = &r300_gpu_reset, 382 .gpu_reset = &r300_gpu_reset,
332 .mc_init = &rs690_mc_init, 383 .mc_init = &rs690_mc_init,
333 .mc_fini = &rs690_mc_fini, 384 .mc_fini = &rs690_mc_fini,
334 .wb_init = &r100_wb_init, 385 .wb_init = &r100_wb_init,
335 .wb_fini = &r100_wb_fini, 386 .wb_fini = &r100_wb_fini,
387 .gart_init = &rs400_gart_init,
388 .gart_fini = &rs400_gart_fini,
336 .gart_enable = &rs400_gart_enable, 389 .gart_enable = &rs400_gart_enable,
337 .gart_disable = &rs400_gart_disable, 390 .gart_disable = &rs400_gart_disable,
338 .gart_tlb_flush = &rs400_gart_tlb_flush, 391 .gart_tlb_flush = &rs400_gart_tlb_flush,
@@ -340,7 +393,11 @@ static struct radeon_asic rs690_asic = {
340 .cp_init = &r100_cp_init, 393 .cp_init = &r100_cp_init,
341 .cp_fini = &r100_cp_fini, 394 .cp_fini = &r100_cp_fini,
342 .cp_disable = &r100_cp_disable, 395 .cp_disable = &r100_cp_disable,
396 .cp_commit = &r100_cp_commit,
343 .ring_start = &r300_ring_start, 397 .ring_start = &r300_ring_start,
398 .ring_test = &r100_ring_test,
399 .ring_ib_execute = &r100_ring_ib_execute,
400 .ib_test = &r100_ib_test,
344 .irq_set = &rs600_irq_set, 401 .irq_set = &rs600_irq_set,
345 .irq_process = &rs600_irq_process, 402 .irq_process = &rs600_irq_process,
346 .get_vblank_counter = &rs600_get_vblank_counter, 403 .get_vblank_counter = &rs600_get_vblank_counter,
@@ -378,19 +435,26 @@ static struct radeon_asic rv515_asic = {
378 .init = &rv515_init, 435 .init = &rv515_init,
379 .errata = &rv515_errata, 436 .errata = &rv515_errata,
380 .vram_info = &rv515_vram_info, 437 .vram_info = &rv515_vram_info,
438 .vga_set_state = &r100_vga_set_state,
381 .gpu_reset = &rv515_gpu_reset, 439 .gpu_reset = &rv515_gpu_reset,
382 .mc_init = &rv515_mc_init, 440 .mc_init = &rv515_mc_init,
383 .mc_fini = &rv515_mc_fini, 441 .mc_fini = &rv515_mc_fini,
384 .wb_init = &r100_wb_init, 442 .wb_init = &r100_wb_init,
385 .wb_fini = &r100_wb_fini, 443 .wb_fini = &r100_wb_fini,
386 .gart_enable = &r300_gart_enable, 444 .gart_init = &rv370_pcie_gart_init,
445 .gart_fini = &rv370_pcie_gart_fini,
446 .gart_enable = &rv370_pcie_gart_enable,
387 .gart_disable = &rv370_pcie_gart_disable, 447 .gart_disable = &rv370_pcie_gart_disable,
388 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 448 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
389 .gart_set_page = &rv370_pcie_gart_set_page, 449 .gart_set_page = &rv370_pcie_gart_set_page,
390 .cp_init = &r100_cp_init, 450 .cp_init = &r100_cp_init,
391 .cp_fini = &r100_cp_fini, 451 .cp_fini = &r100_cp_fini,
392 .cp_disable = &r100_cp_disable, 452 .cp_disable = &r100_cp_disable,
453 .cp_commit = &r100_cp_commit,
393 .ring_start = &rv515_ring_start, 454 .ring_start = &rv515_ring_start,
455 .ring_test = &r100_ring_test,
456 .ring_ib_execute = &r100_ring_ib_execute,
457 .ib_test = &r100_ib_test,
394 .irq_set = &rs600_irq_set, 458 .irq_set = &rs600_irq_set,
395 .irq_process = &rs600_irq_process, 459 .irq_process = &rs600_irq_process,
396 .get_vblank_counter = &rs600_get_vblank_counter, 460 .get_vblank_counter = &rs600_get_vblank_counter,
@@ -421,19 +485,26 @@ static struct radeon_asic r520_asic = {
421 .init = &rv515_init, 485 .init = &rv515_init,
422 .errata = &r520_errata, 486 .errata = &r520_errata,
423 .vram_info = &r520_vram_info, 487 .vram_info = &r520_vram_info,
488 .vga_set_state = &r100_vga_set_state,
424 .gpu_reset = &rv515_gpu_reset, 489 .gpu_reset = &rv515_gpu_reset,
425 .mc_init = &r520_mc_init, 490 .mc_init = &r520_mc_init,
426 .mc_fini = &r520_mc_fini, 491 .mc_fini = &r520_mc_fini,
427 .wb_init = &r100_wb_init, 492 .wb_init = &r100_wb_init,
428 .wb_fini = &r100_wb_fini, 493 .wb_fini = &r100_wb_fini,
429 .gart_enable = &r300_gart_enable, 494 .gart_init = &rv370_pcie_gart_init,
495 .gart_fini = &rv370_pcie_gart_fini,
496 .gart_enable = &rv370_pcie_gart_enable,
430 .gart_disable = &rv370_pcie_gart_disable, 497 .gart_disable = &rv370_pcie_gart_disable,
431 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 498 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
432 .gart_set_page = &rv370_pcie_gart_set_page, 499 .gart_set_page = &rv370_pcie_gart_set_page,
433 .cp_init = &r100_cp_init, 500 .cp_init = &r100_cp_init,
434 .cp_fini = &r100_cp_fini, 501 .cp_fini = &r100_cp_fini,
435 .cp_disable = &r100_cp_disable, 502 .cp_disable = &r100_cp_disable,
503 .cp_commit = &r100_cp_commit,
436 .ring_start = &rv515_ring_start, 504 .ring_start = &rv515_ring_start,
505 .ring_test = &r100_ring_test,
506 .ring_ib_execute = &r100_ring_ib_execute,
507 .ib_test = &r100_ib_test,
437 .irq_set = &rs600_irq_set, 508 .irq_set = &rs600_irq_set,
438 .irq_process = &rs600_irq_process, 509 .irq_process = &rs600_irq_process,
439 .get_vblank_counter = &rs600_get_vblank_counter, 510 .get_vblank_counter = &rs600_get_vblank_counter,
@@ -452,9 +523,130 @@ static struct radeon_asic r520_asic = {
452}; 523};
453 524
454/* 525/*
455 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rv770,rv730,rv710 526 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
456 */ 527 */
528int r600_init(struct radeon_device *rdev);
529void r600_fini(struct radeon_device *rdev);
530int r600_suspend(struct radeon_device *rdev);
531int r600_resume(struct radeon_device *rdev);
532void r600_vga_set_state(struct radeon_device *rdev, bool state);
533int r600_wb_init(struct radeon_device *rdev);
534void r600_wb_fini(struct radeon_device *rdev);
535void r600_cp_commit(struct radeon_device *rdev);
536void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
457uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 537uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
458void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 538void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
539int r600_cs_parse(struct radeon_cs_parser *p);
540void r600_fence_ring_emit(struct radeon_device *rdev,
541 struct radeon_fence *fence);
542int r600_copy_dma(struct radeon_device *rdev,
543 uint64_t src_offset,
544 uint64_t dst_offset,
545 unsigned num_pages,
546 struct radeon_fence *fence);
547int r600_irq_process(struct radeon_device *rdev);
548int r600_irq_set(struct radeon_device *rdev);
549int r600_gpu_reset(struct radeon_device *rdev);
550int r600_set_surface_reg(struct radeon_device *rdev, int reg,
551 uint32_t tiling_flags, uint32_t pitch,
552 uint32_t offset, uint32_t obj_size);
553int r600_clear_surface_reg(struct radeon_device *rdev, int reg);
554void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
555int r600_ib_test(struct radeon_device *rdev);
556int r600_ring_test(struct radeon_device *rdev);
557int r600_copy_blit(struct radeon_device *rdev,
558 uint64_t src_offset, uint64_t dst_offset,
559 unsigned num_pages, struct radeon_fence *fence);
560
561static struct radeon_asic r600_asic = {
562 .errata = NULL,
563 .init = &r600_init,
564 .fini = &r600_fini,
565 .suspend = &r600_suspend,
566 .resume = &r600_resume,
567 .cp_commit = &r600_cp_commit,
568 .vram_info = NULL,
569 .vga_set_state = &r600_vga_set_state,
570 .gpu_reset = &r600_gpu_reset,
571 .mc_init = NULL,
572 .mc_fini = NULL,
573 .wb_init = &r600_wb_init,
574 .wb_fini = &r600_wb_fini,
575 .gart_enable = NULL,
576 .gart_disable = NULL,
577 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
578 .gart_set_page = &rs600_gart_set_page,
579 .cp_init = NULL,
580 .cp_fini = NULL,
581 .cp_disable = NULL,
582 .ring_start = NULL,
583 .ring_test = &r600_ring_test,
584 .ring_ib_execute = &r600_ring_ib_execute,
585 .ib_test = &r600_ib_test,
586 .irq_set = &r600_irq_set,
587 .irq_process = &r600_irq_process,
588 .fence_ring_emit = &r600_fence_ring_emit,
589 .cs_parse = &r600_cs_parse,
590 .copy_blit = &r600_copy_blit,
591 .copy_dma = &r600_copy_blit,
592 .copy = &r600_copy_blit,
593 .set_engine_clock = &radeon_atom_set_engine_clock,
594 .set_memory_clock = &radeon_atom_set_memory_clock,
595 .set_pcie_lanes = NULL,
596 .set_clock_gating = &radeon_atom_set_clock_gating,
597 .set_surface_reg = r600_set_surface_reg,
598 .clear_surface_reg = r600_clear_surface_reg,
599 .bandwidth_update = &r520_bandwidth_update,
600};
601
602/*
603 * rv770,rv730,rv710,rv740
604 */
605int rv770_init(struct radeon_device *rdev);
606void rv770_fini(struct radeon_device *rdev);
607int rv770_suspend(struct radeon_device *rdev);
608int rv770_resume(struct radeon_device *rdev);
609int rv770_gpu_reset(struct radeon_device *rdev);
610
611static struct radeon_asic rv770_asic = {
612 .errata = NULL,
613 .init = &rv770_init,
614 .fini = &rv770_fini,
615 .suspend = &rv770_suspend,
616 .resume = &rv770_resume,
617 .cp_commit = &r600_cp_commit,
618 .vram_info = NULL,
619 .gpu_reset = &rv770_gpu_reset,
620 .vga_set_state = &r600_vga_set_state,
621 .mc_init = NULL,
622 .mc_fini = NULL,
623 .wb_init = &r600_wb_init,
624 .wb_fini = &r600_wb_fini,
625 .gart_enable = NULL,
626 .gart_disable = NULL,
627 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
628 .gart_set_page = &rs600_gart_set_page,
629 .cp_init = NULL,
630 .cp_fini = NULL,
631 .cp_disable = NULL,
632 .ring_start = NULL,
633 .ring_test = &r600_ring_test,
634 .ring_ib_execute = &r600_ring_ib_execute,
635 .ib_test = &r600_ib_test,
636 .irq_set = &r600_irq_set,
637 .irq_process = &r600_irq_process,
638 .fence_ring_emit = &r600_fence_ring_emit,
639 .cs_parse = &r600_cs_parse,
640 .copy_blit = &r600_copy_blit,
641 .copy_dma = &r600_copy_blit,
642 .copy = &r600_copy_blit,
643 .set_engine_clock = &radeon_atom_set_engine_clock,
644 .set_memory_clock = &radeon_atom_set_memory_clock,
645 .set_pcie_lanes = NULL,
646 .set_clock_gating = &radeon_atom_set_clock_gating,
647 .set_surface_reg = r600_set_surface_reg,
648 .clear_surface_reg = r600_clear_surface_reg,
649 .bandwidth_update = &r520_bandwidth_update,
650};
459 651
460#endif 652#endif
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index fcfe5c02d744..743742128307 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -104,7 +104,7 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
104 uint32_t supported_device, 104 uint32_t supported_device,
105 int *connector_type, 105 int *connector_type,
106 struct radeon_i2c_bus_rec *i2c_bus, 106 struct radeon_i2c_bus_rec *i2c_bus,
107 uint8_t *line_mux) 107 uint16_t *line_mux)
108{ 108{
109 109
110 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ 110 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
@@ -143,20 +143,31 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
143 return false; 143 return false;
144 } 144 }
145 145
146 /* some BIOSes seem to report DAC on HDMI - they hurt me with their lies */
147 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) ||
148 (*connector_type == DRM_MODE_CONNECTOR_HDMIB)) {
149 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
150 return false;
151 }
152 }
153
154 /* ASUS HD 3600 XT board lists the DVI port as HDMI */ 146 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
155 if ((dev->pdev->device == 0x9598) && 147 if ((dev->pdev->device == 0x9598) &&
156 (dev->pdev->subsystem_vendor == 0x1043) && 148 (dev->pdev->subsystem_vendor == 0x1043) &&
157 (dev->pdev->subsystem_device == 0x01da)) { 149 (dev->pdev->subsystem_device == 0x01da)) {
158 if (*connector_type == DRM_MODE_CONNECTOR_HDMIB) { 150 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
159 *connector_type = DRM_MODE_CONNECTOR_DVID; 151 *connector_type = DRM_MODE_CONNECTOR_DVII;
152 }
153 }
154
155 /* ASUS HD 3450 board lists the DVI port as HDMI */
156 if ((dev->pdev->device == 0x95C5) &&
157 (dev->pdev->subsystem_vendor == 0x1043) &&
158 (dev->pdev->subsystem_device == 0x01e2)) {
159 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
160 *connector_type = DRM_MODE_CONNECTOR_DVII;
161 }
162 }
163
164 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
165 * HDMI + VGA reporting as HDMI
166 */
167 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
168 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
169 *connector_type = DRM_MODE_CONNECTOR_VGA;
170 *line_mux = 0;
160 } 171 }
161 } 172 }
162 173
@@ -192,11 +203,11 @@ const int object_connector_convert[] = {
192 DRM_MODE_CONNECTOR_Composite, 203 DRM_MODE_CONNECTOR_Composite,
193 DRM_MODE_CONNECTOR_SVIDEO, 204 DRM_MODE_CONNECTOR_SVIDEO,
194 DRM_MODE_CONNECTOR_Unknown, 205 DRM_MODE_CONNECTOR_Unknown,
206 DRM_MODE_CONNECTOR_Unknown,
195 DRM_MODE_CONNECTOR_9PinDIN, 207 DRM_MODE_CONNECTOR_9PinDIN,
196 DRM_MODE_CONNECTOR_Unknown, 208 DRM_MODE_CONNECTOR_Unknown,
197 DRM_MODE_CONNECTOR_HDMIA, 209 DRM_MODE_CONNECTOR_HDMIA,
198 DRM_MODE_CONNECTOR_HDMIB, 210 DRM_MODE_CONNECTOR_HDMIB,
199 DRM_MODE_CONNECTOR_HDMIB,
200 DRM_MODE_CONNECTOR_LVDS, 211 DRM_MODE_CONNECTOR_LVDS,
201 DRM_MODE_CONNECTOR_9PinDIN, 212 DRM_MODE_CONNECTOR_9PinDIN,
202 DRM_MODE_CONNECTOR_Unknown, 213 DRM_MODE_CONNECTOR_Unknown,
@@ -218,7 +229,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
218 ATOM_OBJECT_HEADER *obj_header; 229 ATOM_OBJECT_HEADER *obj_header;
219 int i, j, path_size, device_support; 230 int i, j, path_size, device_support;
220 int connector_type; 231 int connector_type;
221 uint16_t igp_lane_info; 232 uint16_t igp_lane_info, conn_id;
222 bool linkb; 233 bool linkb;
223 struct radeon_i2c_bus_rec ddc_bus; 234 struct radeon_i2c_bus_rec ddc_bus;
224 235
@@ -370,10 +381,6 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
370 && record-> 381 && record->
371 ucRecordType <= 382 ucRecordType <=
372 ATOM_MAX_OBJECT_RECORD_NUMBER) { 383 ATOM_MAX_OBJECT_RECORD_NUMBER) {
373 DRM_ERROR
374 ("record type %d\n",
375 record->
376 ucRecordType);
377 switch (record-> 384 switch (record->
378 ucRecordType) { 385 ucRecordType) {
379 case ATOM_I2C_RECORD_TYPE: 386 case ATOM_I2C_RECORD_TYPE:
@@ -409,9 +416,15 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
409 else 416 else
410 ddc_bus = radeon_lookup_gpio(dev, line_mux); 417 ddc_bus = radeon_lookup_gpio(dev, line_mux);
411 418
419 conn_id = le16_to_cpu(path->usConnObjectId);
420
421 if (!radeon_atom_apply_quirks
422 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
423 &ddc_bus, &conn_id))
424 continue;
425
412 radeon_add_atom_connector(dev, 426 radeon_add_atom_connector(dev,
413 le16_to_cpu(path-> 427 conn_id,
414 usConnObjectId),
415 le16_to_cpu(path-> 428 le16_to_cpu(path->
416 usDeviceTag), 429 usDeviceTag),
417 connector_type, &ddc_bus, 430 connector_type, &ddc_bus,
@@ -427,7 +440,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
427 440
428struct bios_connector { 441struct bios_connector {
429 bool valid; 442 bool valid;
430 uint8_t line_mux; 443 uint16_t line_mux;
431 uint16_t devices; 444 uint16_t devices;
432 int connector_type; 445 int connector_type;
433 struct radeon_i2c_bus_rec ddc_bus; 446 struct radeon_i2c_bus_rec ddc_bus;
@@ -471,11 +484,6 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
471 continue; 484 continue;
472 } 485 }
473 486
474 if (i == ATOM_DEVICE_TV1_INDEX) {
475 DRM_DEBUG("Skipping TV Out\n");
476 continue;
477 }
478
479 bios_connectors[i].connector_type = 487 bios_connectors[i].connector_type =
480 supported_devices_connector_convert[ci.sucConnectorInfo. 488 supported_devices_connector_convert[ci.sucConnectorInfo.
481 sbfAccess. 489 sbfAccess.
@@ -711,9 +719,8 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
711 return false; 719 return false;
712} 720}
713 721
714struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct 722bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
715 radeon_encoder 723 struct radeon_encoder_int_tmds *tmds)
716 *encoder)
717{ 724{
718 struct drm_device *dev = encoder->base.dev; 725 struct drm_device *dev = encoder->base.dev;
719 struct radeon_device *rdev = dev->dev_private; 726 struct radeon_device *rdev = dev->dev_private;
@@ -724,7 +731,6 @@ struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
724 uint8_t frev, crev; 731 uint8_t frev, crev;
725 uint16_t maxfreq; 732 uint16_t maxfreq;
726 int i; 733 int i;
727 struct radeon_encoder_int_tmds *tmds = NULL;
728 734
729 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, 735 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
730 &crev, &data_offset); 736 &crev, &data_offset);
@@ -734,12 +740,6 @@ struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
734 data_offset); 740 data_offset);
735 741
736 if (tmds_info) { 742 if (tmds_info) {
737 tmds =
738 kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
739
740 if (!tmds)
741 return NULL;
742
743 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); 743 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
744 for (i = 0; i < 4; i++) { 744 for (i = 0; i < 4; i++) {
745 tmds->tmds_pll[i].freq = 745 tmds->tmds_pll[i].freq =
@@ -765,8 +765,9 @@ struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
765 break; 765 break;
766 } 766 }
767 } 767 }
768 return true;
768 } 769 }
769 return tmds; 770 return false;
770} 771}
771 772
772union lvds_info { 773union lvds_info {
@@ -858,6 +859,72 @@ radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
858 return p_dac; 859 return p_dac;
859} 860}
860 861
862bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
863 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
864 int32_t *pixel_clock)
865{
866 struct radeon_mode_info *mode_info = &rdev->mode_info;
867 ATOM_ANALOG_TV_INFO *tv_info;
868 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
869 ATOM_DTD_FORMAT *dtd_timings;
870 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
871 u8 frev, crev;
872 uint16_t data_offset;
873
874 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
875
876 switch (crev) {
877 case 1:
878 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
879 if (index > MAX_SUPPORTED_TV_TIMING)
880 return false;
881
882 crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
883 crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
884 crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
885 crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
886
887 crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
888 crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
889 crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
890 crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
891
892 crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo;
893
894 crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight);
895 crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft);
896 crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom);
897 crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop);
898 *pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
899
900 if (index == 1) {
901 /* PAL timings appear to have wrong values for totals */
902 crtc_timing->usH_Total -= 1;
903 crtc_timing->usV_Total -= 1;
904 }
905 break;
906 case 2:
907 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
908 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
909 return false;
910
911 dtd_timings = &tv_info_v1_2->aModeTimings[index];
912 crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time);
913 crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive);
914 crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset);
915 crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth);
916 crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time);
917 crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive);
918 crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset);
919 crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth);
920
921 crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
922 *pixel_clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
923 break;
924 }
925 return true;
926}
927
861struct radeon_encoder_tv_dac * 928struct radeon_encoder_tv_dac *
862radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 929radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
863{ 930{
@@ -948,10 +1015,10 @@ void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
948 uint32_t bios_2_scratch, bios_6_scratch; 1015 uint32_t bios_2_scratch, bios_6_scratch;
949 1016
950 if (rdev->family >= CHIP_R600) { 1017 if (rdev->family >= CHIP_R600) {
951 bios_2_scratch = RREG32(R600_BIOS_0_SCRATCH); 1018 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
952 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 1019 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
953 } else { 1020 } else {
954 bios_2_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 1021 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
955 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 1022 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
956 } 1023 }
957 1024
@@ -971,6 +1038,34 @@ void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
971 1038
972} 1039}
973 1040
1041void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1042{
1043 uint32_t scratch_reg;
1044 int i;
1045
1046 if (rdev->family >= CHIP_R600)
1047 scratch_reg = R600_BIOS_0_SCRATCH;
1048 else
1049 scratch_reg = RADEON_BIOS_0_SCRATCH;
1050
1051 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1052 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1053}
1054
1055void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1056{
1057 uint32_t scratch_reg;
1058 int i;
1059
1060 if (rdev->family >= CHIP_R600)
1061 scratch_reg = R600_BIOS_0_SCRATCH;
1062 else
1063 scratch_reg = RADEON_BIOS_0_SCRATCH;
1064
1065 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1066 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1067}
1068
974void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) 1069void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
975{ 1070{
976 struct drm_device *dev = encoder->dev; 1071 struct drm_device *dev = encoder->dev;
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index a37cbce53181..152eef13197a 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -102,10 +102,12 @@ void radeon_get_clock_info(struct drm_device *dev)
102 p1pll->reference_div = 12; 102 p1pll->reference_div = 12;
103 if (p2pll->reference_div < 2) 103 if (p2pll->reference_div < 2)
104 p2pll->reference_div = 12; 104 p2pll->reference_div = 12;
105 if (spll->reference_div < 2) 105 if (rdev->family < CHIP_RS600) {
106 spll->reference_div = 106 if (spll->reference_div < 2)
107 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & 107 spll->reference_div =
108 RADEON_M_SPLL_REF_DIV_MASK; 108 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
109 RADEON_M_SPLL_REF_DIV_MASK;
110 }
109 if (mpll->reference_div < 2) 111 if (mpll->reference_div < 2)
110 mpll->reference_div = spll->reference_div; 112 mpll->reference_div = spll->reference_div;
111 } else { 113 } else {
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 2a027e00762a..748265a105b3 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -863,8 +863,10 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
863 int tmp, i; 863 int tmp, i;
864 struct radeon_encoder_lvds *lvds = NULL; 864 struct radeon_encoder_lvds *lvds = NULL;
865 865
866 if (rdev->bios == NULL) 866 if (rdev->bios == NULL) {
867 return radeon_legacy_get_lvds_info_from_regs(rdev); 867 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
868 goto out;
869 }
868 870
869 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 871 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
870 872
@@ -965,11 +967,13 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
965 lvds->native_mode.flags = 0; 967 lvds->native_mode.flags = 0;
966 } 968 }
967 } 969 }
968 encoder->native_mode = lvds->native_mode;
969 } else { 970 } else {
970 DRM_INFO("No panel info found in BIOS\n"); 971 DRM_INFO("No panel info found in BIOS\n");
971 return radeon_legacy_get_lvds_info_from_regs(rdev); 972 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
972 } 973 }
974out:
975 if (lvds)
976 encoder->native_mode = lvds->native_mode;
973 return lvds; 977 return lvds;
974} 978}
975 979
@@ -994,48 +998,37 @@ static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
994 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RS480 */ 998 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RS480 */
995}; 999};
996 1000
997static struct radeon_encoder_int_tmds 1001bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
998 *radeon_legacy_get_tmds_info_from_table(struct radeon_device *rdev) 1002 struct radeon_encoder_int_tmds *tmds)
999{ 1003{
1004 struct drm_device *dev = encoder->base.dev;
1005 struct radeon_device *rdev = dev->dev_private;
1000 int i; 1006 int i;
1001 struct radeon_encoder_int_tmds *tmds = NULL;
1002
1003 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1004
1005 if (!tmds)
1006 return NULL;
1007 1007
1008 for (i = 0; i < 4; i++) { 1008 for (i = 0; i < 4; i++) {
1009 tmds->tmds_pll[i].value = 1009 tmds->tmds_pll[i].value =
1010 default_tmds_pll[rdev->family][i].value; 1010 default_tmds_pll[rdev->family][i].value;
1011 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; 1011 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1012 } 1012 }
1013 1013
1014 return tmds; 1014 return true;
1015} 1015}
1016 1016
1017struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct 1017bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1018 radeon_encoder 1018 struct radeon_encoder_int_tmds *tmds)
1019 *encoder)
1020{ 1019{
1021 struct drm_device *dev = encoder->base.dev; 1020 struct drm_device *dev = encoder->base.dev;
1022 struct radeon_device *rdev = dev->dev_private; 1021 struct radeon_device *rdev = dev->dev_private;
1023 uint16_t tmds_info; 1022 uint16_t tmds_info;
1024 int i, n; 1023 int i, n;
1025 uint8_t ver; 1024 uint8_t ver;
1026 struct radeon_encoder_int_tmds *tmds = NULL;
1027 1025
1028 if (rdev->bios == NULL) 1026 if (rdev->bios == NULL)
1029 return radeon_legacy_get_tmds_info_from_table(rdev); 1027 return false;
1030 1028
1031 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1029 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1032 1030
1033 if (tmds_info) { 1031 if (tmds_info) {
1034 tmds =
1035 kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1036
1037 if (!tmds)
1038 return NULL;
1039 1032
1040 ver = RBIOS8(tmds_info); 1033 ver = RBIOS8(tmds_info);
1041 DRM_INFO("DFP table revision: %d\n", ver); 1034 DRM_INFO("DFP table revision: %d\n", ver);
@@ -1073,6 +1066,23 @@ struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct
1073 } 1066 }
1074 } else 1067 } else
1075 DRM_INFO("No TMDS info found in BIOS\n"); 1068 DRM_INFO("No TMDS info found in BIOS\n");
1069 return true;
1070}
1071
1072struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct radeon_encoder *encoder)
1073{
1074 struct radeon_encoder_int_tmds *tmds = NULL;
1075 bool ret;
1076
1077 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1078
1079 if (!tmds)
1080 return NULL;
1081
1082 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1083 if (ret == false)
1084 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1085
1076 return tmds; 1086 return tmds;
1077} 1087}
1078 1088
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 70ede6a52d4e..af1d551f1a8f 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -28,6 +28,7 @@
28#include "drm_crtc_helper.h" 28#include "drm_crtc_helper.h"
29#include "radeon_drm.h" 29#include "radeon_drm.h"
30#include "radeon.h" 30#include "radeon.h"
31#include "atom.h"
31 32
32extern void 33extern void
33radeon_combios_connected_scratch_regs(struct drm_connector *connector, 34radeon_combios_connected_scratch_regs(struct drm_connector *connector,
@@ -38,6 +39,15 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
38 struct drm_encoder *encoder, 39 struct drm_encoder *encoder,
39 bool connected); 40 bool connected);
40 41
42static void radeon_property_change_mode(struct drm_encoder *encoder)
43{
44 struct drm_crtc *crtc = encoder->crtc;
45
46 if (crtc && crtc->enabled) {
47 drm_crtc_helper_set_mode(crtc, &crtc->mode,
48 crtc->x, crtc->y, crtc->fb);
49 }
50}
41static void 51static void
42radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_connector_status status) 52radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_connector_status status)
43{ 53{
@@ -77,6 +87,27 @@ radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_c
77 } 87 }
78} 88}
79 89
90struct drm_encoder *radeon_find_encoder(struct drm_connector *connector, int encoder_type)
91{
92 struct drm_mode_object *obj;
93 struct drm_encoder *encoder;
94 int i;
95
96 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
97 if (connector->encoder_ids[i] == 0)
98 break;
99
100 obj = drm_mode_object_find(connector->dev, connector->encoder_ids[i], DRM_MODE_OBJECT_ENCODER);
101 if (!obj)
102 continue;
103
104 encoder = obj_to_encoder(obj);
105 if (encoder->encoder_type == encoder_type)
106 return encoder;
107 }
108 return NULL;
109}
110
80struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector) 111struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector)
81{ 112{
82 int enc_id = connector->encoder_ids[0]; 113 int enc_id = connector->encoder_ids[0];
@@ -94,6 +125,53 @@ struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector)
94 return NULL; 125 return NULL;
95} 126}
96 127
128/*
129 * radeon_connector_analog_encoder_conflict_solve
130 * - search for other connectors sharing this encoder
131 * if priority is true, then set them disconnected if this is connected
132 * if priority is false, set us disconnected if they are connected
133 */
134static enum drm_connector_status
135radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector,
136 struct drm_encoder *encoder,
137 enum drm_connector_status current_status,
138 bool priority)
139{
140 struct drm_device *dev = connector->dev;
141 struct drm_connector *conflict;
142 int i;
143
144 list_for_each_entry(conflict, &dev->mode_config.connector_list, head) {
145 if (conflict == connector)
146 continue;
147
148 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
149 if (conflict->encoder_ids[i] == 0)
150 break;
151
152 /* if the IDs match */
153 if (conflict->encoder_ids[i] == encoder->base.id) {
154 if (conflict->status != connector_status_connected)
155 continue;
156
157 if (priority == true) {
158 DRM_INFO("1: conflicting encoders switching off %s\n", drm_get_connector_name(conflict));
159 DRM_INFO("in favor of %s\n", drm_get_connector_name(connector));
160 conflict->status = connector_status_disconnected;
161 radeon_connector_update_scratch_regs(conflict, connector_status_disconnected);
162 } else {
163 DRM_INFO("2: conflicting encoders switching off %s\n", drm_get_connector_name(connector));
164 DRM_INFO("in favor of %s\n", drm_get_connector_name(conflict));
165 current_status = connector_status_disconnected;
166 }
167 break;
168 }
169 }
170 }
171 return current_status;
172
173}
174
97static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encoder) 175static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encoder)
98{ 176{
99 struct drm_device *dev = encoder->dev; 177 struct drm_device *dev = encoder->dev;
@@ -126,12 +204,171 @@ static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encode
126 return mode; 204 return mode;
127} 205}
128 206
207static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_connector *connector)
208{
209 struct drm_device *dev = encoder->dev;
210 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
211 struct drm_display_mode *mode = NULL;
212 struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
213 int i;
214 struct mode_size {
215 int w;
216 int h;
217 } common_modes[17] = {
218 { 640, 480},
219 { 720, 480},
220 { 800, 600},
221 { 848, 480},
222 {1024, 768},
223 {1152, 768},
224 {1280, 720},
225 {1280, 800},
226 {1280, 854},
227 {1280, 960},
228 {1280, 1024},
229 {1440, 900},
230 {1400, 1050},
231 {1680, 1050},
232 {1600, 1200},
233 {1920, 1080},
234 {1920, 1200}
235 };
236
237 for (i = 0; i < 17; i++) {
238 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
239 if (common_modes[i].w > native_mode->panel_xres ||
240 common_modes[i].h > native_mode->panel_yres ||
241 (common_modes[i].w == native_mode->panel_xres &&
242 common_modes[i].h == native_mode->panel_yres))
243 continue;
244 }
245 if (common_modes[i].w < 320 || common_modes[i].h < 200)
246 continue;
247
248 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false);
249 drm_mode_probed_add(connector, mode);
250 }
251}
252
129int radeon_connector_set_property(struct drm_connector *connector, struct drm_property *property, 253int radeon_connector_set_property(struct drm_connector *connector, struct drm_property *property,
130 uint64_t val) 254 uint64_t val)
131{ 255{
256 struct drm_device *dev = connector->dev;
257 struct radeon_device *rdev = dev->dev_private;
258 struct drm_encoder *encoder;
259 struct radeon_encoder *radeon_encoder;
260
261 if (property == rdev->mode_info.coherent_mode_property) {
262 struct radeon_encoder_atom_dig *dig;
263
264 /* need to find digital encoder on connector */
265 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
266 if (!encoder)
267 return 0;
268
269 radeon_encoder = to_radeon_encoder(encoder);
270
271 if (!radeon_encoder->enc_priv)
272 return 0;
273
274 dig = radeon_encoder->enc_priv;
275 dig->coherent_mode = val ? true : false;
276 radeon_property_change_mode(&radeon_encoder->base);
277 }
278
279 if (property == rdev->mode_info.tv_std_property) {
280 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TVDAC);
281 if (!encoder) {
282 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_DAC);
283 }
284
285 if (!encoder)
286 return 0;
287
288 radeon_encoder = to_radeon_encoder(encoder);
289 if (!radeon_encoder->enc_priv)
290 return 0;
291 if (rdev->is_atom_bios) {
292 struct radeon_encoder_atom_dac *dac_int;
293 dac_int = radeon_encoder->enc_priv;
294 dac_int->tv_std = val;
295 } else {
296 struct radeon_encoder_tv_dac *dac_int;
297 dac_int = radeon_encoder->enc_priv;
298 dac_int->tv_std = val;
299 }
300 radeon_property_change_mode(&radeon_encoder->base);
301 }
302
303 if (property == rdev->mode_info.load_detect_property) {
304 struct radeon_connector *radeon_connector =
305 to_radeon_connector(connector);
306
307 if (val == 0)
308 radeon_connector->dac_load_detect = false;
309 else
310 radeon_connector->dac_load_detect = true;
311 }
312
313 if (property == rdev->mode_info.tmds_pll_property) {
314 struct radeon_encoder_int_tmds *tmds = NULL;
315 bool ret = false;
316 /* need to find digital encoder on connector */
317 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
318 if (!encoder)
319 return 0;
320
321 radeon_encoder = to_radeon_encoder(encoder);
322
323 tmds = radeon_encoder->enc_priv;
324 if (!tmds)
325 return 0;
326
327 if (val == 0) {
328 if (rdev->is_atom_bios)
329 ret = radeon_atombios_get_tmds_info(radeon_encoder, tmds);
330 else
331 ret = radeon_legacy_get_tmds_info_from_combios(radeon_encoder, tmds);
332 }
333 if (val == 1 || ret == false) {
334 radeon_legacy_get_tmds_info_from_table(radeon_encoder, tmds);
335 }
336 radeon_property_change_mode(&radeon_encoder->base);
337 }
338
132 return 0; 339 return 0;
133} 340}
134 341
342static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder,
343 struct drm_connector *connector)
344{
345 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
346 struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
347
348 /* Try to get native mode details from EDID if necessary */
349 if (!native_mode->dotclock) {
350 struct drm_display_mode *t, *mode;
351
352 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
353 if (mode->hdisplay == native_mode->panel_xres &&
354 mode->vdisplay == native_mode->panel_yres) {
355 native_mode->hblank = mode->htotal - mode->hdisplay;
356 native_mode->hoverplus = mode->hsync_start - mode->hdisplay;
357 native_mode->hsync_width = mode->hsync_end - mode->hsync_start;
358 native_mode->vblank = mode->vtotal - mode->vdisplay;
359 native_mode->voverplus = mode->vsync_start - mode->vdisplay;
360 native_mode->vsync_width = mode->vsync_end - mode->vsync_start;
361 native_mode->dotclock = mode->clock;
362 DRM_INFO("Determined LVDS native mode details from EDID\n");
363 break;
364 }
365 }
366 }
367 if (!native_mode->dotclock) {
368 DRM_INFO("No LVDS native mode details, disabling RMX\n");
369 radeon_encoder->rmx_type = RMX_OFF;
370 }
371}
135 372
136static int radeon_lvds_get_modes(struct drm_connector *connector) 373static int radeon_lvds_get_modes(struct drm_connector *connector)
137{ 374{
@@ -143,6 +380,12 @@ static int radeon_lvds_get_modes(struct drm_connector *connector)
143 if (radeon_connector->ddc_bus) { 380 if (radeon_connector->ddc_bus) {
144 ret = radeon_ddc_get_modes(radeon_connector); 381 ret = radeon_ddc_get_modes(radeon_connector);
145 if (ret > 0) { 382 if (ret > 0) {
383 encoder = radeon_best_single_encoder(connector);
384 if (encoder) {
385 radeon_fixup_lvds_native_mode(encoder, connector);
386 /* add scaled modes */
387 radeon_add_common_modes(encoder, connector);
388 }
146 return ret; 389 return ret;
147 } 390 }
148 } 391 }
@@ -156,7 +399,10 @@ static int radeon_lvds_get_modes(struct drm_connector *connector)
156 if (mode) { 399 if (mode) {
157 ret = 1; 400 ret = 1;
158 drm_mode_probed_add(connector, mode); 401 drm_mode_probed_add(connector, mode);
402 /* add scaled modes */
403 radeon_add_common_modes(encoder, connector);
159 } 404 }
405
160 return ret; 406 return ret;
161} 407}
162 408
@@ -186,6 +432,42 @@ static void radeon_connector_destroy(struct drm_connector *connector)
186 kfree(connector); 432 kfree(connector);
187} 433}
188 434
435static int radeon_lvds_set_property(struct drm_connector *connector,
436 struct drm_property *property,
437 uint64_t value)
438{
439 struct drm_device *dev = connector->dev;
440 struct radeon_encoder *radeon_encoder;
441 enum radeon_rmx_type rmx_type;
442
443 DRM_DEBUG("\n");
444 if (property != dev->mode_config.scaling_mode_property)
445 return 0;
446
447 if (connector->encoder)
448 radeon_encoder = to_radeon_encoder(connector->encoder);
449 else {
450 struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
451 radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector));
452 }
453
454 switch (value) {
455 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
456 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
457 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
458 default:
459 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
460 }
461 if (radeon_encoder->rmx_type == rmx_type)
462 return 0;
463
464 radeon_encoder->rmx_type = rmx_type;
465
466 radeon_property_change_mode(&radeon_encoder->base);
467 return 0;
468}
469
470
189struct drm_connector_helper_funcs radeon_lvds_connector_helper_funcs = { 471struct drm_connector_helper_funcs radeon_lvds_connector_helper_funcs = {
190 .get_modes = radeon_lvds_get_modes, 472 .get_modes = radeon_lvds_get_modes,
191 .mode_valid = radeon_lvds_mode_valid, 473 .mode_valid = radeon_lvds_mode_valid,
@@ -197,7 +479,7 @@ struct drm_connector_funcs radeon_lvds_connector_funcs = {
197 .detect = radeon_lvds_detect, 479 .detect = radeon_lvds_detect,
198 .fill_modes = drm_helper_probe_single_connector_modes, 480 .fill_modes = drm_helper_probe_single_connector_modes,
199 .destroy = radeon_connector_destroy, 481 .destroy = radeon_connector_destroy,
200 .set_property = radeon_connector_set_property, 482 .set_property = radeon_lvds_set_property,
201}; 483};
202 484
203static int radeon_vga_get_modes(struct drm_connector *connector) 485static int radeon_vga_get_modes(struct drm_connector *connector)
@@ -213,7 +495,6 @@ static int radeon_vga_get_modes(struct drm_connector *connector)
213static int radeon_vga_mode_valid(struct drm_connector *connector, 495static int radeon_vga_mode_valid(struct drm_connector *connector,
214 struct drm_display_mode *mode) 496 struct drm_display_mode *mode)
215{ 497{
216
217 return MODE_OK; 498 return MODE_OK;
218} 499}
219 500
@@ -225,22 +506,24 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect
225 bool dret; 506 bool dret;
226 enum drm_connector_status ret = connector_status_disconnected; 507 enum drm_connector_status ret = connector_status_disconnected;
227 508
509 encoder = radeon_best_single_encoder(connector);
510 if (!encoder)
511 ret = connector_status_disconnected;
512
228 radeon_i2c_do_lock(radeon_connector, 1); 513 radeon_i2c_do_lock(radeon_connector, 1);
229 dret = radeon_ddc_probe(radeon_connector); 514 dret = radeon_ddc_probe(radeon_connector);
230 radeon_i2c_do_lock(radeon_connector, 0); 515 radeon_i2c_do_lock(radeon_connector, 0);
231 if (dret) 516 if (dret)
232 ret = connector_status_connected; 517 ret = connector_status_connected;
233 else { 518 else {
234 /* if EDID fails to a load detect */ 519 if (radeon_connector->dac_load_detect) {
235 encoder = radeon_best_single_encoder(connector);
236 if (!encoder)
237 ret = connector_status_disconnected;
238 else {
239 encoder_funcs = encoder->helper_private; 520 encoder_funcs = encoder->helper_private;
240 ret = encoder_funcs->detect(encoder, connector); 521 ret = encoder_funcs->detect(encoder, connector);
241 } 522 }
242 } 523 }
243 524
525 if (ret == connector_status_connected)
526 ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true);
244 radeon_connector_update_scratch_regs(connector, ret); 527 radeon_connector_update_scratch_regs(connector, ret);
245 return ret; 528 return ret;
246} 529}
@@ -259,21 +542,97 @@ struct drm_connector_funcs radeon_vga_connector_funcs = {
259 .set_property = radeon_connector_set_property, 542 .set_property = radeon_connector_set_property,
260}; 543};
261 544
545static int radeon_tv_get_modes(struct drm_connector *connector)
546{
547 struct drm_device *dev = connector->dev;
548 struct radeon_device *rdev = dev->dev_private;
549 struct drm_display_mode *tv_mode;
550 struct drm_encoder *encoder;
551
552 encoder = radeon_best_single_encoder(connector);
553 if (!encoder)
554 return 0;
555
556 /* avivo chips can scale any mode */
557 if (rdev->family >= CHIP_RS600)
558 /* add scaled modes */
559 radeon_add_common_modes(encoder, connector);
560 else {
561 /* only 800x600 is supported right now on pre-avivo chips */
562 tv_mode = drm_cvt_mode(dev, 800, 600, 60, false, false);
563 tv_mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
564 drm_mode_probed_add(connector, tv_mode);
565 }
566 return 1;
567}
568
569static int radeon_tv_mode_valid(struct drm_connector *connector,
570 struct drm_display_mode *mode)
571{
572 return MODE_OK;
573}
574
575static enum drm_connector_status radeon_tv_detect(struct drm_connector *connector)
576{
577 struct drm_encoder *encoder;
578 struct drm_encoder_helper_funcs *encoder_funcs;
579 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
580 enum drm_connector_status ret = connector_status_disconnected;
581
582 if (!radeon_connector->dac_load_detect)
583 return ret;
584
585 encoder = radeon_best_single_encoder(connector);
586 if (!encoder)
587 ret = connector_status_disconnected;
588 else {
589 encoder_funcs = encoder->helper_private;
590 ret = encoder_funcs->detect(encoder, connector);
591 }
592 if (ret == connector_status_connected)
593 ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, false);
594 radeon_connector_update_scratch_regs(connector, ret);
595 return ret;
596}
597
598struct drm_connector_helper_funcs radeon_tv_connector_helper_funcs = {
599 .get_modes = radeon_tv_get_modes,
600 .mode_valid = radeon_tv_mode_valid,
601 .best_encoder = radeon_best_single_encoder,
602};
603
604struct drm_connector_funcs radeon_tv_connector_funcs = {
605 .dpms = drm_helper_connector_dpms,
606 .detect = radeon_tv_detect,
607 .fill_modes = drm_helper_probe_single_connector_modes,
608 .destroy = radeon_connector_destroy,
609 .set_property = radeon_connector_set_property,
610};
611
262static int radeon_dvi_get_modes(struct drm_connector *connector) 612static int radeon_dvi_get_modes(struct drm_connector *connector)
263{ 613{
264 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 614 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
265 int ret; 615 int ret;
266 616
267 ret = radeon_ddc_get_modes(radeon_connector); 617 ret = radeon_ddc_get_modes(radeon_connector);
268 /* reset scratch regs here since radeon_dvi_detect doesn't check digital bit */
269 radeon_connector_update_scratch_regs(connector, connector_status_connected);
270 return ret; 618 return ret;
271} 619}
272 620
621/*
622 * DVI is complicated
623 * Do a DDC probe, if DDC probe passes, get the full EDID so
624 * we can do analog/digital monitor detection at this point.
625 * If the monitor is an analog monitor or we got no DDC,
626 * we need to find the DAC encoder object for this connector.
627 * If we got no DDC, we do load detection on the DAC encoder object.
628 * If we got analog DDC or load detection passes on the DAC encoder
629 * we have to check if this analog encoder is shared with anyone else (TV)
630 * if its shared we have to set the other connector to disconnected.
631 */
273static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connector) 632static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connector)
274{ 633{
275 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 634 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
276 struct drm_encoder *encoder; 635 struct drm_encoder *encoder = NULL;
277 struct drm_encoder_helper_funcs *encoder_funcs; 636 struct drm_encoder_helper_funcs *encoder_funcs;
278 struct drm_mode_object *obj; 637 struct drm_mode_object *obj;
279 int i; 638 int i;
@@ -283,9 +642,29 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
283 radeon_i2c_do_lock(radeon_connector, 1); 642 radeon_i2c_do_lock(radeon_connector, 1);
284 dret = radeon_ddc_probe(radeon_connector); 643 dret = radeon_ddc_probe(radeon_connector);
285 radeon_i2c_do_lock(radeon_connector, 0); 644 radeon_i2c_do_lock(radeon_connector, 0);
286 if (dret) 645 if (dret) {
287 ret = connector_status_connected; 646 radeon_i2c_do_lock(radeon_connector, 1);
288 else { 647 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
648 radeon_i2c_do_lock(radeon_connector, 0);
649
650 if (!radeon_connector->edid) {
651 DRM_ERROR("DDC responded but not EDID found for %s\n",
652 drm_get_connector_name(connector));
653 } else {
654 radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
655
656 /* if this isn't a digital monitor
657 then we need to make sure we don't have any
658 TV conflicts */
659 ret = connector_status_connected;
660 }
661 }
662
663 if ((ret == connector_status_connected) && (radeon_connector->use_digital == true))
664 goto out;
665
666 /* find analog encoder */
667 if (radeon_connector->dac_load_detect) {
289 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 668 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
290 if (connector->encoder_ids[i] == 0) 669 if (connector->encoder_ids[i] == 0)
291 break; 670 break;
@@ -300,15 +679,23 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
300 679
301 encoder_funcs = encoder->helper_private; 680 encoder_funcs = encoder->helper_private;
302 if (encoder_funcs->detect) { 681 if (encoder_funcs->detect) {
303 ret = encoder_funcs->detect(encoder, connector); 682 if (ret != connector_status_connected) {
304 if (ret == connector_status_connected) { 683 ret = encoder_funcs->detect(encoder, connector);
305 radeon_connector->use_digital = 0; 684 if (ret == connector_status_connected) {
306 break; 685 radeon_connector->use_digital = false;
686 }
307 } 687 }
688 break;
308 } 689 }
309 } 690 }
310 } 691 }
311 692
693 if ((ret == connector_status_connected) && (radeon_connector->use_digital == false) &&
694 encoder) {
695 ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true);
696 }
697
698out:
312 /* updated in get modes as well since we need to know if it's analog or digital */ 699 /* updated in get modes as well since we need to know if it's analog or digital */
313 radeon_connector_update_scratch_regs(connector, ret); 700 radeon_connector_update_scratch_regs(connector, ret);
314 return ret; 701 return ret;
@@ -332,7 +719,7 @@ struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector)
332 719
333 encoder = obj_to_encoder(obj); 720 encoder = obj_to_encoder(obj);
334 721
335 if (radeon_connector->use_digital) { 722 if (radeon_connector->use_digital == true) {
336 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 723 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
337 return encoder; 724 return encoder;
338 } else { 725 } else {
@@ -379,16 +766,14 @@ radeon_add_atom_connector(struct drm_device *dev,
379 bool linkb, 766 bool linkb,
380 uint32_t igp_lane_info) 767 uint32_t igp_lane_info)
381{ 768{
769 struct radeon_device *rdev = dev->dev_private;
382 struct drm_connector *connector; 770 struct drm_connector *connector;
383 struct radeon_connector *radeon_connector; 771 struct radeon_connector *radeon_connector;
384 struct radeon_connector_atom_dig *radeon_dig_connector; 772 struct radeon_connector_atom_dig *radeon_dig_connector;
385 uint32_t subpixel_order = SubPixelNone; 773 uint32_t subpixel_order = SubPixelNone;
386 774
387 /* fixme - tv/cv/din */ 775 /* fixme - tv/cv/din */
388 if ((connector_type == DRM_MODE_CONNECTOR_Unknown) || 776 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
389 (connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
390 (connector_type == DRM_MODE_CONNECTOR_Composite) ||
391 (connector_type == DRM_MODE_CONNECTOR_9PinDIN))
392 return; 777 return;
393 778
394 /* see if we already added it */ 779 /* see if we already added it */
@@ -417,6 +802,9 @@ radeon_add_atom_connector(struct drm_device *dev,
417 if (!radeon_connector->ddc_bus) 802 if (!radeon_connector->ddc_bus)
418 goto failed; 803 goto failed;
419 } 804 }
805 drm_connector_attach_property(&radeon_connector->base,
806 rdev->mode_info.load_detect_property,
807 1);
420 break; 808 break;
421 case DRM_MODE_CONNECTOR_DVIA: 809 case DRM_MODE_CONNECTOR_DVIA:
422 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); 810 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
@@ -426,6 +814,9 @@ radeon_add_atom_connector(struct drm_device *dev,
426 if (!radeon_connector->ddc_bus) 814 if (!radeon_connector->ddc_bus)
427 goto failed; 815 goto failed;
428 } 816 }
817 drm_connector_attach_property(&radeon_connector->base,
818 rdev->mode_info.load_detect_property,
819 1);
429 break; 820 break;
430 case DRM_MODE_CONNECTOR_DVII: 821 case DRM_MODE_CONNECTOR_DVII:
431 case DRM_MODE_CONNECTOR_DVID: 822 case DRM_MODE_CONNECTOR_DVID:
@@ -443,6 +834,12 @@ radeon_add_atom_connector(struct drm_device *dev,
443 goto failed; 834 goto failed;
444 } 835 }
445 subpixel_order = SubPixelHorizontalRGB; 836 subpixel_order = SubPixelHorizontalRGB;
837 drm_connector_attach_property(&radeon_connector->base,
838 rdev->mode_info.coherent_mode_property,
839 1);
840 drm_connector_attach_property(&radeon_connector->base,
841 rdev->mode_info.load_detect_property,
842 1);
446 break; 843 break;
447 case DRM_MODE_CONNECTOR_HDMIA: 844 case DRM_MODE_CONNECTOR_HDMIA:
448 case DRM_MODE_CONNECTOR_HDMIB: 845 case DRM_MODE_CONNECTOR_HDMIB:
@@ -459,6 +856,9 @@ radeon_add_atom_connector(struct drm_device *dev,
459 if (!radeon_connector->ddc_bus) 856 if (!radeon_connector->ddc_bus)
460 goto failed; 857 goto failed;
461 } 858 }
859 drm_connector_attach_property(&radeon_connector->base,
860 rdev->mode_info.coherent_mode_property,
861 1);
462 subpixel_order = SubPixelHorizontalRGB; 862 subpixel_order = SubPixelHorizontalRGB;
463 break; 863 break;
464 case DRM_MODE_CONNECTOR_DisplayPort: 864 case DRM_MODE_CONNECTOR_DisplayPort:
@@ -480,6 +880,13 @@ radeon_add_atom_connector(struct drm_device *dev,
480 case DRM_MODE_CONNECTOR_SVIDEO: 880 case DRM_MODE_CONNECTOR_SVIDEO:
481 case DRM_MODE_CONNECTOR_Composite: 881 case DRM_MODE_CONNECTOR_Composite:
482 case DRM_MODE_CONNECTOR_9PinDIN: 882 case DRM_MODE_CONNECTOR_9PinDIN:
883 if (radeon_tv == 1) {
884 drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
885 drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
886 }
887 drm_connector_attach_property(&radeon_connector->base,
888 rdev->mode_info.load_detect_property,
889 1);
483 break; 890 break;
484 case DRM_MODE_CONNECTOR_LVDS: 891 case DRM_MODE_CONNECTOR_LVDS:
485 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); 892 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
@@ -495,6 +902,10 @@ radeon_add_atom_connector(struct drm_device *dev,
495 if (!radeon_connector->ddc_bus) 902 if (!radeon_connector->ddc_bus)
496 goto failed; 903 goto failed;
497 } 904 }
905 drm_mode_create_scaling_mode_property(dev);
906 drm_connector_attach_property(&radeon_connector->base,
907 dev->mode_config.scaling_mode_property,
908 DRM_MODE_SCALE_FULLSCREEN);
498 subpixel_order = SubPixelHorizontalRGB; 909 subpixel_order = SubPixelHorizontalRGB;
499 break; 910 break;
500 } 911 }
@@ -517,15 +928,13 @@ radeon_add_legacy_connector(struct drm_device *dev,
517 int connector_type, 928 int connector_type,
518 struct radeon_i2c_bus_rec *i2c_bus) 929 struct radeon_i2c_bus_rec *i2c_bus)
519{ 930{
931 struct radeon_device *rdev = dev->dev_private;
520 struct drm_connector *connector; 932 struct drm_connector *connector;
521 struct radeon_connector *radeon_connector; 933 struct radeon_connector *radeon_connector;
522 uint32_t subpixel_order = SubPixelNone; 934 uint32_t subpixel_order = SubPixelNone;
523 935
524 /* fixme - tv/cv/din */ 936 /* fixme - tv/cv/din */
525 if ((connector_type == DRM_MODE_CONNECTOR_Unknown) || 937 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
526 (connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
527 (connector_type == DRM_MODE_CONNECTOR_Composite) ||
528 (connector_type == DRM_MODE_CONNECTOR_9PinDIN))
529 return; 938 return;
530 939
531 /* see if we already added it */ 940 /* see if we already added it */
@@ -554,6 +963,9 @@ radeon_add_legacy_connector(struct drm_device *dev,
554 if (!radeon_connector->ddc_bus) 963 if (!radeon_connector->ddc_bus)
555 goto failed; 964 goto failed;
556 } 965 }
966 drm_connector_attach_property(&radeon_connector->base,
967 rdev->mode_info.load_detect_property,
968 1);
557 break; 969 break;
558 case DRM_MODE_CONNECTOR_DVIA: 970 case DRM_MODE_CONNECTOR_DVIA:
559 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); 971 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
@@ -563,6 +975,9 @@ radeon_add_legacy_connector(struct drm_device *dev,
563 if (!radeon_connector->ddc_bus) 975 if (!radeon_connector->ddc_bus)
564 goto failed; 976 goto failed;
565 } 977 }
978 drm_connector_attach_property(&radeon_connector->base,
979 rdev->mode_info.load_detect_property,
980 1);
566 break; 981 break;
567 case DRM_MODE_CONNECTOR_DVII: 982 case DRM_MODE_CONNECTOR_DVII:
568 case DRM_MODE_CONNECTOR_DVID: 983 case DRM_MODE_CONNECTOR_DVID:
@@ -572,12 +987,22 @@ radeon_add_legacy_connector(struct drm_device *dev,
572 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); 987 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI");
573 if (!radeon_connector->ddc_bus) 988 if (!radeon_connector->ddc_bus)
574 goto failed; 989 goto failed;
990 drm_connector_attach_property(&radeon_connector->base,
991 rdev->mode_info.load_detect_property,
992 1);
575 } 993 }
576 subpixel_order = SubPixelHorizontalRGB; 994 subpixel_order = SubPixelHorizontalRGB;
577 break; 995 break;
578 case DRM_MODE_CONNECTOR_SVIDEO: 996 case DRM_MODE_CONNECTOR_SVIDEO:
579 case DRM_MODE_CONNECTOR_Composite: 997 case DRM_MODE_CONNECTOR_Composite:
580 case DRM_MODE_CONNECTOR_9PinDIN: 998 case DRM_MODE_CONNECTOR_9PinDIN:
999 if (radeon_tv == 1) {
1000 drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
1001 drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
1002 drm_connector_attach_property(&radeon_connector->base,
1003 rdev->mode_info.load_detect_property,
1004 1);
1005 }
581 break; 1006 break;
582 case DRM_MODE_CONNECTOR_LVDS: 1007 case DRM_MODE_CONNECTOR_LVDS:
583 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); 1008 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
@@ -587,6 +1012,9 @@ radeon_add_legacy_connector(struct drm_device *dev,
587 if (!radeon_connector->ddc_bus) 1012 if (!radeon_connector->ddc_bus)
588 goto failed; 1013 goto failed;
589 } 1014 }
1015 drm_connector_attach_property(&radeon_connector->base,
1016 dev->mode_config.scaling_mode_property,
1017 DRM_MODE_SCALE_FULLSCREEN);
590 subpixel_order = SubPixelHorizontalRGB; 1018 subpixel_order = SubPixelHorizontalRGB;
591 break; 1019 break;
592 } 1020 }
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 7a52c461145c..4f7afc79dd82 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -36,10 +36,25 @@
36#include "radeon_drv.h" 36#include "radeon_drv.h"
37#include "r300_reg.h" 37#include "r300_reg.h"
38 38
39#include "radeon_microcode.h"
40
41#define RADEON_FIFO_DEBUG 0 39#define RADEON_FIFO_DEBUG 0
42 40
41/* Firmware Names */
42#define FIRMWARE_R100 "radeon/R100_cp.bin"
43#define FIRMWARE_R200 "radeon/R200_cp.bin"
44#define FIRMWARE_R300 "radeon/R300_cp.bin"
45#define FIRMWARE_R420 "radeon/R420_cp.bin"
46#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
47#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
48#define FIRMWARE_R520 "radeon/R520_cp.bin"
49
50MODULE_FIRMWARE(FIRMWARE_R100);
51MODULE_FIRMWARE(FIRMWARE_R200);
52MODULE_FIRMWARE(FIRMWARE_R300);
53MODULE_FIRMWARE(FIRMWARE_R420);
54MODULE_FIRMWARE(FIRMWARE_RS690);
55MODULE_FIRMWARE(FIRMWARE_RS600);
56MODULE_FIRMWARE(FIRMWARE_R520);
57
43static int radeon_do_cleanup_cp(struct drm_device * dev); 58static int radeon_do_cleanup_cp(struct drm_device * dev);
44static void radeon_do_cp_start(drm_radeon_private_t * dev_priv); 59static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
45 60
@@ -460,37 +475,34 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
460 */ 475 */
461 476
462/* Load the microcode for the CP */ 477/* Load the microcode for the CP */
463static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) 478static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
464{ 479{
465 int i; 480 struct platform_device *pdev;
481 const char *fw_name = NULL;
482 int err;
483
466 DRM_DEBUG("\n"); 484 DRM_DEBUG("\n");
467 485
468 radeon_do_wait_for_idle(dev_priv); 486 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
487 err = IS_ERR(pdev);
488 if (err) {
489 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
490 return -EINVAL;
491 }
469 492
470 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
471 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) || 493 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
472 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) || 494 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
473 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) || 495 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
474 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) || 496 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
475 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) { 497 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
476 DRM_INFO("Loading R100 Microcode\n"); 498 DRM_INFO("Loading R100 Microcode\n");
477 for (i = 0; i < 256; i++) { 499 fw_name = FIRMWARE_R100;
478 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
479 R100_cp_microcode[i][1]);
480 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
481 R100_cp_microcode[i][0]);
482 }
483 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) || 500 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
484 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) || 501 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
485 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) || 502 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
486 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) { 503 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
487 DRM_INFO("Loading R200 Microcode\n"); 504 DRM_INFO("Loading R200 Microcode\n");
488 for (i = 0; i < 256; i++) { 505 fw_name = FIRMWARE_R200;
489 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
490 R200_cp_microcode[i][1]);
491 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
492 R200_cp_microcode[i][0]);
493 }
494 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || 506 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
495 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || 507 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
496 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || 508 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
@@ -498,39 +510,19 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
498 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || 510 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
499 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { 511 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
500 DRM_INFO("Loading R300 Microcode\n"); 512 DRM_INFO("Loading R300 Microcode\n");
501 for (i = 0; i < 256; i++) { 513 fw_name = FIRMWARE_R300;
502 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
503 R300_cp_microcode[i][1]);
504 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
505 R300_cp_microcode[i][0]);
506 }
507 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || 514 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
508 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) || 515 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
509 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { 516 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
510 DRM_INFO("Loading R400 Microcode\n"); 517 DRM_INFO("Loading R400 Microcode\n");
511 for (i = 0; i < 256; i++) { 518 fw_name = FIRMWARE_R420;
512 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
513 R420_cp_microcode[i][1]);
514 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
515 R420_cp_microcode[i][0]);
516 }
517 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 519 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
518 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { 520 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
519 DRM_INFO("Loading RS690/RS740 Microcode\n"); 521 DRM_INFO("Loading RS690/RS740 Microcode\n");
520 for (i = 0; i < 256; i++) { 522 fw_name = FIRMWARE_RS690;
521 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
522 RS690_cp_microcode[i][1]);
523 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
524 RS690_cp_microcode[i][0]);
525 }
526 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { 523 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
527 DRM_INFO("Loading RS600 Microcode\n"); 524 DRM_INFO("Loading RS600 Microcode\n");
528 for (i = 0; i < 256; i++) { 525 fw_name = FIRMWARE_RS600;
529 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
530 RS600_cp_microcode[i][1]);
531 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
532 RS600_cp_microcode[i][0]);
533 }
534 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || 526 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
535 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || 527 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
536 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || 528 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
@@ -538,11 +530,41 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
538 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) || 530 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
539 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) { 531 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
540 DRM_INFO("Loading R500 Microcode\n"); 532 DRM_INFO("Loading R500 Microcode\n");
541 for (i = 0; i < 256; i++) { 533 fw_name = FIRMWARE_R520;
534 }
535
536 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
537 platform_device_unregister(pdev);
538 if (err) {
539 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
540 fw_name);
541 } else if (dev_priv->me_fw->size % 8) {
542 printk(KERN_ERR
543 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
544 dev_priv->me_fw->size, fw_name);
545 err = -EINVAL;
546 release_firmware(dev_priv->me_fw);
547 dev_priv->me_fw = NULL;
548 }
549 return err;
550}
551
552static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
553{
554 const __be32 *fw_data;
555 int i, size;
556
557 radeon_do_wait_for_idle(dev_priv);
558
559 if (dev_priv->me_fw) {
560 size = dev_priv->me_fw->size / 4;
561 fw_data = (const __be32 *)&dev_priv->me_fw->data[0];
562 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
563 for (i = 0; i < size; i += 2) {
542 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 564 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
543 R520_cp_microcode[i][1]); 565 be32_to_cpup(&fw_data[i]));
544 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 566 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
545 R520_cp_microcode[i][0]); 567 be32_to_cpup(&fw_data[i + 1]));
546 } 568 }
547 } 569 }
548} 570}
@@ -594,6 +616,18 @@ static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
594 616
595 dev_priv->cp_running = 1; 617 dev_priv->cp_running = 1;
596 618
619 /* on r420, any DMA from CP to system memory while 2D is active
620 * can cause a hang. workaround is to queue a CP RESYNC token
621 */
622 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
623 BEGIN_RING(3);
624 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
625 OUT_RING(5); /* scratch reg 5 */
626 OUT_RING(0xdeadbeef);
627 ADVANCE_RING();
628 COMMIT_RING();
629 }
630
597 BEGIN_RING(8); 631 BEGIN_RING(8);
598 /* isync can only be written through cp on r5xx write it here */ 632 /* isync can only be written through cp on r5xx write it here */
599 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); 633 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
@@ -631,8 +665,19 @@ static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
631 */ 665 */
632static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) 666static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
633{ 667{
668 RING_LOCALS;
634 DRM_DEBUG("\n"); 669 DRM_DEBUG("\n");
635 670
671 /* finish the pending CP_RESYNC token */
672 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
673 BEGIN_RING(2);
674 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
675 OUT_RING(R300_RB3D_DC_FINISH);
676 ADVANCE_RING();
677 COMMIT_RING();
678 radeon_do_wait_for_idle(dev_priv);
679 }
680
636 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); 681 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
637 682
638 dev_priv->cp_running = 0; 683 dev_priv->cp_running = 0;
@@ -1495,6 +1540,14 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1495 radeon_set_pcigart(dev_priv, 1); 1540 radeon_set_pcigart(dev_priv, 1);
1496 } 1541 }
1497 1542
1543 if (!dev_priv->me_fw) {
1544 int err = radeon_cp_init_microcode(dev_priv);
1545 if (err) {
1546 DRM_ERROR("Failed to load firmware!\n");
1547 radeon_do_cleanup_cp(dev);
1548 return err;
1549 }
1550 }
1498 radeon_cp_load_microcode(dev_priv); 1551 radeon_cp_load_microcode(dev_priv);
1499 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); 1552 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1500 1553
@@ -1764,6 +1817,14 @@ void radeon_do_release(struct drm_device * dev)
1764 r600_do_cleanup_cp(dev); 1817 r600_do_cleanup_cp(dev);
1765 else 1818 else
1766 radeon_do_cleanup_cp(dev); 1819 radeon_do_cleanup_cp(dev);
1820 if (dev_priv->me_fw) {
1821 release_firmware(dev_priv->me_fw);
1822 dev_priv->me_fw = NULL;
1823 }
1824 if (dev_priv->pfp_fw) {
1825 release_firmware(dev_priv->pfp_fw);
1826 dev_priv->pfp_fw = NULL;
1827 }
1767 } 1828 }
1768} 1829}
1769 1830
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index a169067efc4e..12f5990c2d2a 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -145,7 +145,7 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
145 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; 145 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
146 146
147 size = p->chunks[i].length_dw * sizeof(uint32_t); 147 size = p->chunks[i].length_dw * sizeof(uint32_t);
148 p->chunks[i].kdata = kzalloc(size, GFP_KERNEL); 148 p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
149 if (p->chunks[i].kdata == NULL) { 149 if (p->chunks[i].kdata == NULL) {
150 return -ENOMEM; 150 return -ENOMEM;
151 } 151 }
@@ -185,6 +185,7 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
185 mutex_unlock(&parser->rdev->ddev->struct_mutex); 185 mutex_unlock(&parser->rdev->ddev->struct_mutex);
186 } 186 }
187 } 187 }
188 kfree(parser->track);
188 kfree(parser->relocs); 189 kfree(parser->relocs);
189 kfree(parser->relocs_ptr); 190 kfree(parser->relocs_ptr);
190 for (i = 0; i < parser->nchunks; i++) { 191 for (i = 0; i < parser->nchunks; i++) {
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 7693f7c67bd3..daf5db780956 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -29,6 +29,7 @@
29#include <drm/drmP.h> 29#include <drm/drmP.h>
30#include <drm/drm_crtc_helper.h> 30#include <drm/drm_crtc_helper.h>
31#include <drm/radeon_drm.h> 31#include <drm/radeon_drm.h>
32#include <linux/vgaarb.h>
32#include "radeon_reg.h" 33#include "radeon_reg.h"
33#include "radeon.h" 34#include "radeon.h"
34#include "radeon_asic.h" 35#include "radeon_asic.h"
@@ -37,7 +38,7 @@
37/* 38/*
38 * Clear GPU surface registers. 39 * Clear GPU surface registers.
39 */ 40 */
40static void radeon_surface_init(struct radeon_device *rdev) 41void radeon_surface_init(struct radeon_device *rdev)
41{ 42{
42 /* FIXME: check this out */ 43 /* FIXME: check this out */
43 if (rdev->family < CHIP_R600) { 44 if (rdev->family < CHIP_R600) {
@@ -56,7 +57,7 @@ static void radeon_surface_init(struct radeon_device *rdev)
56/* 57/*
57 * GPU scratch registers helpers function. 58 * GPU scratch registers helpers function.
58 */ 59 */
59static void radeon_scratch_init(struct radeon_device *rdev) 60void radeon_scratch_init(struct radeon_device *rdev)
60{ 61{
61 int i; 62 int i;
62 63
@@ -156,16 +157,18 @@ int radeon_mc_setup(struct radeon_device *rdev)
156 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); 157 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
157 rdev->mc.gtt_location = tmp; 158 rdev->mc.gtt_location = tmp;
158 } 159 }
159 DRM_INFO("radeon: VRAM %uM\n", rdev->mc.real_vram_size >> 20); 160 rdev->mc.vram_start = rdev->mc.vram_location;
161 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
162 rdev->mc.gtt_start = rdev->mc.gtt_location;
163 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
164 DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
160 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", 165 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
161 rdev->mc.vram_location, 166 (unsigned)rdev->mc.vram_location,
162 rdev->mc.vram_location + rdev->mc.mc_vram_size - 1); 167 (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
163 if (rdev->mc.real_vram_size != rdev->mc.mc_vram_size) 168 DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
164 DRM_INFO("radeon: VRAM less than aperture workaround enabled\n");
165 DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);
166 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", 169 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
167 rdev->mc.gtt_location, 170 (unsigned)rdev->mc.gtt_location,
168 rdev->mc.gtt_location + rdev->mc.gtt_size - 1); 171 (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
169 return 0; 172 return 0;
170} 173}
171 174
@@ -173,7 +176,7 @@ int radeon_mc_setup(struct radeon_device *rdev)
173/* 176/*
174 * GPU helpers function. 177 * GPU helpers function.
175 */ 178 */
176static bool radeon_card_posted(struct radeon_device *rdev) 179bool radeon_card_posted(struct radeon_device *rdev)
177{ 180{
178 uint32_t reg; 181 uint32_t reg;
179 182
@@ -205,6 +208,31 @@ static bool radeon_card_posted(struct radeon_device *rdev)
205 208
206} 209}
207 210
211int radeon_dummy_page_init(struct radeon_device *rdev)
212{
213 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
214 if (rdev->dummy_page.page == NULL)
215 return -ENOMEM;
216 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
217 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
218 if (!rdev->dummy_page.addr) {
219 __free_page(rdev->dummy_page.page);
220 rdev->dummy_page.page = NULL;
221 return -ENOMEM;
222 }
223 return 0;
224}
225
226void radeon_dummy_page_fini(struct radeon_device *rdev)
227{
228 if (rdev->dummy_page.page == NULL)
229 return;
230 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
231 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
232 __free_page(rdev->dummy_page.page);
233 rdev->dummy_page.page = NULL;
234}
235
208 236
209/* 237/*
210 * Registers accessors functions. 238 * Registers accessors functions.
@@ -243,6 +271,10 @@ void radeon_register_accessor_init(struct radeon_device *rdev)
243 rdev->pll_rreg = &r100_pll_rreg; 271 rdev->pll_rreg = &r100_pll_rreg;
244 rdev->pll_wreg = &r100_pll_wreg; 272 rdev->pll_wreg = &r100_pll_wreg;
245 } 273 }
274 if (rdev->family >= CHIP_R420) {
275 rdev->mc_rreg = &r420_mc_rreg;
276 rdev->mc_wreg = &r420_mc_wreg;
277 }
246 if (rdev->family >= CHIP_RV515) { 278 if (rdev->family >= CHIP_RV515) {
247 rdev->mc_rreg = &rv515_mc_rreg; 279 rdev->mc_rreg = &rv515_mc_rreg;
248 rdev->mc_wreg = &rv515_mc_wreg; 280 rdev->mc_wreg = &rv515_mc_wreg;
@@ -289,6 +321,14 @@ int radeon_asic_init(struct radeon_device *rdev)
289 case CHIP_RV350: 321 case CHIP_RV350:
290 case CHIP_RV380: 322 case CHIP_RV380:
291 rdev->asic = &r300_asic; 323 rdev->asic = &r300_asic;
324 if (rdev->flags & RADEON_IS_PCIE) {
325 rdev->asic->gart_init = &rv370_pcie_gart_init;
326 rdev->asic->gart_fini = &rv370_pcie_gart_fini;
327 rdev->asic->gart_enable = &rv370_pcie_gart_enable;
328 rdev->asic->gart_disable = &rv370_pcie_gart_disable;
329 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
330 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
331 }
292 break; 332 break;
293 case CHIP_R420: 333 case CHIP_R420:
294 case CHIP_R423: 334 case CHIP_R423:
@@ -323,9 +363,15 @@ int radeon_asic_init(struct radeon_device *rdev)
323 case CHIP_RV635: 363 case CHIP_RV635:
324 case CHIP_RV670: 364 case CHIP_RV670:
325 case CHIP_RS780: 365 case CHIP_RS780:
366 case CHIP_RS880:
367 rdev->asic = &r600_asic;
368 break;
326 case CHIP_RV770: 369 case CHIP_RV770:
327 case CHIP_RV730: 370 case CHIP_RV730:
328 case CHIP_RV710: 371 case CHIP_RV710:
372 case CHIP_RV740:
373 rdev->asic = &rv770_asic;
374 break;
329 default: 375 default:
330 /* FIXME: not supported yet */ 376 /* FIXME: not supported yet */
331 return -EINVAL; 377 return -EINVAL;
@@ -341,7 +387,6 @@ int radeon_clocks_init(struct radeon_device *rdev)
341{ 387{
342 int r; 388 int r;
343 389
344 radeon_get_clock_info(rdev->ddev);
345 r = radeon_static_clocks_init(rdev->ddev); 390 r = radeon_static_clocks_init(rdev->ddev);
346 if (r) { 391 if (r) {
347 return r; 392 return r;
@@ -436,10 +481,18 @@ void radeon_combios_fini(struct radeon_device *rdev)
436{ 481{
437} 482}
438 483
439int radeon_modeset_init(struct radeon_device *rdev); 484/* if we get transitioned to only one device, tak VGA back */
440void radeon_modeset_fini(struct radeon_device *rdev); 485static unsigned int radeon_vga_set_decode(void *cookie, bool state)
441 486{
487 struct radeon_device *rdev = cookie;
442 488
489 radeon_vga_set_state(rdev, state);
490 if (state)
491 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
492 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
493 else
494 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
495}
443/* 496/*
444 * Radeon device. 497 * Radeon device.
445 */ 498 */
@@ -448,11 +501,12 @@ int radeon_device_init(struct radeon_device *rdev,
448 struct pci_dev *pdev, 501 struct pci_dev *pdev,
449 uint32_t flags) 502 uint32_t flags)
450{ 503{
451 int r, ret; 504 int r;
452 int dma_bits; 505 int dma_bits;
453 506
454 DRM_INFO("radeon: Initializing kernel modesetting.\n"); 507 DRM_INFO("radeon: Initializing kernel modesetting.\n");
455 rdev->shutdown = false; 508 rdev->shutdown = false;
509 rdev->dev = &pdev->dev;
456 rdev->ddev = ddev; 510 rdev->ddev = ddev;
457 rdev->pdev = pdev; 511 rdev->pdev = pdev;
458 rdev->flags = flags; 512 rdev->flags = flags;
@@ -461,37 +515,47 @@ int radeon_device_init(struct radeon_device *rdev,
461 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 515 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
462 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 516 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
463 rdev->gpu_lockup = false; 517 rdev->gpu_lockup = false;
518 rdev->accel_working = false;
464 /* mutex initialization are all done here so we 519 /* mutex initialization are all done here so we
465 * can recall function without having locking issues */ 520 * can recall function without having locking issues */
466 mutex_init(&rdev->cs_mutex); 521 mutex_init(&rdev->cs_mutex);
467 mutex_init(&rdev->ib_pool.mutex); 522 mutex_init(&rdev->ib_pool.mutex);
468 mutex_init(&rdev->cp.mutex); 523 mutex_init(&rdev->cp.mutex);
469 rwlock_init(&rdev->fence_drv.lock); 524 rwlock_init(&rdev->fence_drv.lock);
525 INIT_LIST_HEAD(&rdev->gem.objects);
526
527 /* Set asic functions */
528 r = radeon_asic_init(rdev);
529 if (r) {
530 return r;
531 }
470 532
471 if (radeon_agpmode == -1) { 533 if (radeon_agpmode == -1) {
472 rdev->flags &= ~RADEON_IS_AGP; 534 rdev->flags &= ~RADEON_IS_AGP;
473 if (rdev->family > CHIP_RV515 || 535 if (rdev->family >= CHIP_RV515 ||
474 rdev->family == CHIP_RV380 || 536 rdev->family == CHIP_RV380 ||
475 rdev->family == CHIP_RV410 || 537 rdev->family == CHIP_RV410 ||
476 rdev->family == CHIP_R423) { 538 rdev->family == CHIP_R423) {
477 DRM_INFO("Forcing AGP to PCIE mode\n"); 539 DRM_INFO("Forcing AGP to PCIE mode\n");
478 rdev->flags |= RADEON_IS_PCIE; 540 rdev->flags |= RADEON_IS_PCIE;
541 rdev->asic->gart_init = &rv370_pcie_gart_init;
542 rdev->asic->gart_fini = &rv370_pcie_gart_fini;
543 rdev->asic->gart_enable = &rv370_pcie_gart_enable;
544 rdev->asic->gart_disable = &rv370_pcie_gart_disable;
545 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
546 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
479 } else { 547 } else {
480 DRM_INFO("Forcing AGP to PCI mode\n"); 548 DRM_INFO("Forcing AGP to PCI mode\n");
481 rdev->flags |= RADEON_IS_PCI; 549 rdev->flags |= RADEON_IS_PCI;
550 rdev->asic->gart_init = &r100_pci_gart_init;
551 rdev->asic->gart_fini = &r100_pci_gart_fini;
552 rdev->asic->gart_enable = &r100_pci_gart_enable;
553 rdev->asic->gart_disable = &r100_pci_gart_disable;
554 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
555 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
482 } 556 }
483 } 557 }
484 558
485 /* Set asic functions */
486 r = radeon_asic_init(rdev);
487 if (r) {
488 return r;
489 }
490 r = radeon_init(rdev);
491 if (r) {
492 return r;
493 }
494
495 /* set DMA mask + need_dma32 flags. 559 /* set DMA mask + need_dma32 flags.
496 * PCIE - can handle 40-bits. 560 * PCIE - can handle 40-bits.
497 * IGP - can handle 40-bits (in theory) 561 * IGP - can handle 40-bits (in theory)
@@ -521,156 +585,150 @@ int radeon_device_init(struct radeon_device *rdev,
521 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 585 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
522 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 586 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
523 587
524 /* Setup errata flags */ 588 rdev->new_init_path = false;
525 radeon_errata(rdev); 589 r = radeon_init(rdev);
526 /* Initialize scratch registers */
527 radeon_scratch_init(rdev);
528 /* Initialize surface registers */
529 radeon_surface_init(rdev);
530
531 /* TODO: disable VGA need to use VGA request */
532 /* BIOS*/
533 if (!radeon_get_bios(rdev)) {
534 if (ASIC_IS_AVIVO(rdev))
535 return -EINVAL;
536 }
537 if (rdev->is_atom_bios) {
538 r = radeon_atombios_init(rdev);
539 if (r) {
540 return r;
541 }
542 } else {
543 r = radeon_combios_init(rdev);
544 if (r) {
545 return r;
546 }
547 }
548 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
549 if (radeon_gpu_reset(rdev)) {
550 /* FIXME: what do we want to do here ? */
551 }
552 /* check if cards are posted or not */
553 if (!radeon_card_posted(rdev) && rdev->bios) {
554 DRM_INFO("GPU not posted. posting now...\n");
555 if (rdev->is_atom_bios) {
556 atom_asic_init(rdev->mode_info.atom_context);
557 } else {
558 radeon_combios_asic_init(rdev->ddev);
559 }
560 }
561 /* Initialize clocks */
562 r = radeon_clocks_init(rdev);
563 if (r) {
564 return r;
565 }
566 /* Get vram informations */
567 radeon_vram_info(rdev);
568
569 /* Add an MTRR for the VRAM */
570 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
571 MTRR_TYPE_WRCOMB, 1);
572 DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
573 rdev->mc.real_vram_size >> 20,
574 (unsigned)rdev->mc.aper_size >> 20);
575 DRM_INFO("RAM width %dbits %cDR\n",
576 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
577 /* Initialize memory controller (also test AGP) */
578 r = radeon_mc_init(rdev);
579 if (r) {
580 return r;
581 }
582 /* Fence driver */
583 r = radeon_fence_driver_init(rdev);
584 if (r) {
585 return r;
586 }
587 r = radeon_irq_kms_init(rdev);
588 if (r) { 590 if (r) {
589 return r; 591 return r;
590 } 592 }
591 /* Memory manager */ 593
592 r = radeon_object_init(rdev); 594 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
595 r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
593 if (r) { 596 if (r) {
594 return r; 597 return -EINVAL;
595 }
596 /* Initialize GART (initialize after TTM so we can allocate
597 * memory through TTM but finalize after TTM) */
598 r = radeon_gart_enable(rdev);
599 if (!r) {
600 r = radeon_gem_init(rdev);
601 } 598 }
602 599
603 /* 1M ring buffer */ 600 if (!rdev->new_init_path) {
604 if (!r) { 601 /* Setup errata flags */
605 r = radeon_cp_init(rdev, 1024 * 1024); 602 radeon_errata(rdev);
606 } 603 /* Initialize scratch registers */
607 if (!r) { 604 radeon_scratch_init(rdev);
608 r = radeon_wb_init(rdev); 605 /* Initialize surface registers */
606 radeon_surface_init(rdev);
607
608 /* BIOS*/
609 if (!radeon_get_bios(rdev)) {
610 if (ASIC_IS_AVIVO(rdev))
611 return -EINVAL;
612 }
613 if (rdev->is_atom_bios) {
614 r = radeon_atombios_init(rdev);
615 if (r) {
616 return r;
617 }
618 } else {
619 r = radeon_combios_init(rdev);
620 if (r) {
621 return r;
622 }
623 }
624 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
625 if (radeon_gpu_reset(rdev)) {
626 /* FIXME: what do we want to do here ? */
627 }
628 /* check if cards are posted or not */
629 if (!radeon_card_posted(rdev) && rdev->bios) {
630 DRM_INFO("GPU not posted. posting now...\n");
631 if (rdev->is_atom_bios) {
632 atom_asic_init(rdev->mode_info.atom_context);
633 } else {
634 radeon_combios_asic_init(rdev->ddev);
635 }
636 }
637 /* Get clock & vram information */
638 radeon_get_clock_info(rdev->ddev);
639 radeon_vram_info(rdev);
640 /* Initialize clocks */
641 r = radeon_clocks_init(rdev);
609 if (r) { 642 if (r) {
610 DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
611 return r; 643 return r;
612 } 644 }
613 } 645
614 if (!r) { 646 /* Initialize memory controller (also test AGP) */
615 r = radeon_ib_pool_init(rdev); 647 r = radeon_mc_init(rdev);
616 if (r) { 648 if (r) {
617 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
618 return r; 649 return r;
619 } 650 }
620 } 651 /* Fence driver */
621 if (!r) { 652 r = radeon_fence_driver_init(rdev);
622 r = radeon_ib_test(rdev);
623 if (r) { 653 if (r) {
624 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
625 return r; 654 return r;
626 } 655 }
656 r = radeon_irq_kms_init(rdev);
657 if (r) {
658 return r;
659 }
660 /* Memory manager */
661 r = radeon_object_init(rdev);
662 if (r) {
663 return r;
664 }
665 r = radeon_gpu_gart_init(rdev);
666 if (r)
667 return r;
668 /* Initialize GART (initialize after TTM so we can allocate
669 * memory through TTM but finalize after TTM) */
670 r = radeon_gart_enable(rdev);
671 if (r)
672 return 0;
673 r = radeon_gem_init(rdev);
674 if (r)
675 return 0;
676
677 /* 1M ring buffer */
678 r = radeon_cp_init(rdev, 1024 * 1024);
679 if (r)
680 return 0;
681 r = radeon_wb_init(rdev);
682 if (r)
683 DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
684 r = radeon_ib_pool_init(rdev);
685 if (r)
686 return 0;
687 r = radeon_ib_test(rdev);
688 if (r)
689 return 0;
690 rdev->accel_working = true;
627 } 691 }
628 ret = r; 692 DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
629 r = radeon_modeset_init(rdev);
630 if (r) {
631 return r;
632 }
633 if (!ret) {
634 DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
635 }
636 if (radeon_testing) { 693 if (radeon_testing) {
637 radeon_test_moves(rdev); 694 radeon_test_moves(rdev);
638 } 695 }
639 if (radeon_benchmarking) { 696 if (radeon_benchmarking) {
640 radeon_benchmark(rdev); 697 radeon_benchmark(rdev);
641 } 698 }
642 return ret; 699 return 0;
643} 700}
644 701
645void radeon_device_fini(struct radeon_device *rdev) 702void radeon_device_fini(struct radeon_device *rdev)
646{ 703{
647 if (rdev == NULL || rdev->rmmio == NULL) {
648 return;
649 }
650 DRM_INFO("radeon: finishing device.\n"); 704 DRM_INFO("radeon: finishing device.\n");
651 rdev->shutdown = true; 705 rdev->shutdown = true;
652 /* Order matter so becarefull if you rearrange anythings */ 706 /* Order matter so becarefull if you rearrange anythings */
653 radeon_modeset_fini(rdev); 707 if (!rdev->new_init_path) {
654 radeon_ib_pool_fini(rdev); 708 radeon_ib_pool_fini(rdev);
655 radeon_cp_fini(rdev); 709 radeon_cp_fini(rdev);
656 radeon_wb_fini(rdev); 710 radeon_wb_fini(rdev);
657 radeon_gem_fini(rdev); 711 radeon_gpu_gart_fini(rdev);
658 radeon_object_fini(rdev); 712 radeon_gem_fini(rdev);
659 /* mc_fini must be after object_fini */ 713 radeon_mc_fini(rdev);
660 radeon_mc_fini(rdev);
661#if __OS_HAS_AGP 714#if __OS_HAS_AGP
662 radeon_agp_fini(rdev); 715 radeon_agp_fini(rdev);
663#endif 716#endif
664 radeon_irq_kms_fini(rdev); 717 radeon_irq_kms_fini(rdev);
665 radeon_fence_driver_fini(rdev); 718 vga_client_register(rdev->pdev, NULL, NULL, NULL);
666 radeon_clocks_fini(rdev); 719 radeon_fence_driver_fini(rdev);
667 if (rdev->is_atom_bios) { 720 radeon_clocks_fini(rdev);
668 radeon_atombios_fini(rdev); 721 radeon_object_fini(rdev);
722 if (rdev->is_atom_bios) {
723 radeon_atombios_fini(rdev);
724 } else {
725 radeon_combios_fini(rdev);
726 }
727 kfree(rdev->bios);
728 rdev->bios = NULL;
669 } else { 729 } else {
670 radeon_combios_fini(rdev); 730 radeon_fini(rdev);
671 } 731 }
672 kfree(rdev->bios);
673 rdev->bios = NULL;
674 iounmap(rdev->rmmio); 732 iounmap(rdev->rmmio);
675 rdev->rmmio = NULL; 733 rdev->rmmio = NULL;
676} 734}
@@ -708,15 +766,19 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
708 /* wait for gpu to finish processing current batch */ 766 /* wait for gpu to finish processing current batch */
709 radeon_fence_wait_last(rdev); 767 radeon_fence_wait_last(rdev);
710 768
711 radeon_cp_disable(rdev); 769 radeon_save_bios_scratch_regs(rdev);
712 radeon_gart_disable(rdev);
713 770
771 if (!rdev->new_init_path) {
772 radeon_cp_disable(rdev);
773 radeon_gart_disable(rdev);
774 rdev->irq.sw_int = false;
775 radeon_irq_set(rdev);
776 } else {
777 radeon_suspend(rdev);
778 }
714 /* evict remaining vram memory */ 779 /* evict remaining vram memory */
715 radeon_object_evict_vram(rdev); 780 radeon_object_evict_vram(rdev);
716 781
717 rdev->irq.sw_int = false;
718 radeon_irq_set(rdev);
719
720 pci_save_state(dev->pdev); 782 pci_save_state(dev->pdev);
721 if (state.event == PM_EVENT_SUSPEND) { 783 if (state.event == PM_EVENT_SUSPEND) {
722 /* Shut down the device */ 784 /* Shut down the device */
@@ -743,38 +805,43 @@ int radeon_resume_kms(struct drm_device *dev)
743 } 805 }
744 pci_set_master(dev->pdev); 806 pci_set_master(dev->pdev);
745 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 807 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
746 if (radeon_gpu_reset(rdev)) { 808 if (!rdev->new_init_path) {
747 /* FIXME: what do we want to do here ? */ 809 if (radeon_gpu_reset(rdev)) {
748 } 810 /* FIXME: what do we want to do here ? */
749 /* post card */ 811 }
750 if (rdev->is_atom_bios) { 812 /* post card */
751 atom_asic_init(rdev->mode_info.atom_context); 813 if (rdev->is_atom_bios) {
814 atom_asic_init(rdev->mode_info.atom_context);
815 } else {
816 radeon_combios_asic_init(rdev->ddev);
817 }
818 /* Initialize clocks */
819 r = radeon_clocks_init(rdev);
820 if (r) {
821 release_console_sem();
822 return r;
823 }
824 /* Enable IRQ */
825 rdev->irq.sw_int = true;
826 radeon_irq_set(rdev);
827 /* Initialize GPU Memory Controller */
828 r = radeon_mc_init(rdev);
829 if (r) {
830 goto out;
831 }
832 r = radeon_gart_enable(rdev);
833 if (r) {
834 goto out;
835 }
836 r = radeon_cp_init(rdev, rdev->cp.ring_size);
837 if (r) {
838 goto out;
839 }
752 } else { 840 } else {
753 radeon_combios_asic_init(rdev->ddev); 841 radeon_resume(rdev);
754 }
755 /* Initialize clocks */
756 r = radeon_clocks_init(rdev);
757 if (r) {
758 release_console_sem();
759 return r;
760 }
761 /* Enable IRQ */
762 rdev->irq.sw_int = true;
763 radeon_irq_set(rdev);
764 /* Initialize GPU Memory Controller */
765 r = radeon_mc_init(rdev);
766 if (r) {
767 goto out;
768 }
769 r = radeon_gart_enable(rdev);
770 if (r) {
771 goto out;
772 }
773 r = radeon_cp_init(rdev, rdev->cp.ring_size);
774 if (r) {
775 goto out;
776 } 842 }
777out: 843out:
844 radeon_restore_bios_scratch_regs(rdev);
778 fb_set_suspend(rdev->fbdev_info, 0); 845 fb_set_suspend(rdev->fbdev_info, 0);
779 release_console_sem(); 846 release_console_sem();
780 847
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index a8fa1bb84cf7..5d8141b13765 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -158,9 +158,6 @@ static void radeon_crtc_destroy(struct drm_crtc *crtc)
158{ 158{
159 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 159 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
160 160
161 if (radeon_crtc->mode_set.mode) {
162 drm_mode_destroy(crtc->dev, radeon_crtc->mode_set.mode);
163 }
164 drm_crtc_cleanup(crtc); 161 drm_crtc_cleanup(crtc);
165 kfree(radeon_crtc); 162 kfree(radeon_crtc);
166} 163}
@@ -189,9 +186,11 @@ static void radeon_crtc_init(struct drm_device *dev, int index)
189 radeon_crtc->crtc_id = index; 186 radeon_crtc->crtc_id = index;
190 rdev->mode_info.crtcs[index] = radeon_crtc; 187 rdev->mode_info.crtcs[index] = radeon_crtc;
191 188
189#if 0
192 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 190 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
193 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 191 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
194 radeon_crtc->mode_set.num_connectors = 0; 192 radeon_crtc->mode_set.num_connectors = 0;
193#endif
195 194
196 for (i = 0; i < 256; i++) { 195 for (i = 0; i < 256; i++) {
197 radeon_crtc->lut_r[i] = i << 2; 196 radeon_crtc->lut_r[i] = i << 2;
@@ -313,7 +312,7 @@ static void radeon_print_display_setup(struct drm_device *dev)
313 } 312 }
314} 313}
315 314
316bool radeon_setup_enc_conn(struct drm_device *dev) 315static bool radeon_setup_enc_conn(struct drm_device *dev)
317{ 316{
318 struct radeon_device *rdev = dev->dev_private; 317 struct radeon_device *rdev = dev->dev_private;
319 struct drm_connector *drm_connector; 318 struct drm_connector *drm_connector;
@@ -347,9 +346,13 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
347 346
348 if (!radeon_connector->ddc_bus) 347 if (!radeon_connector->ddc_bus)
349 return -1; 348 return -1;
350 radeon_i2c_do_lock(radeon_connector, 1); 349 if (!radeon_connector->edid) {
351 edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); 350 radeon_i2c_do_lock(radeon_connector, 1);
352 radeon_i2c_do_lock(radeon_connector, 0); 351 edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
352 radeon_i2c_do_lock(radeon_connector, 0);
353 } else
354 edid = radeon_connector->edid;
355
353 if (edid) { 356 if (edid) {
354 /* update digital bits here */ 357 /* update digital bits here */
355 if (edid->input & DRM_EDID_INPUT_DIGITAL) 358 if (edid->input & DRM_EDID_INPUT_DIGITAL)
@@ -362,7 +365,7 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
362 return ret; 365 return ret;
363 } 366 }
364 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); 367 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
365 return -1; 368 return 0;
366} 369}
367 370
368static int radeon_ddc_dump(struct drm_connector *connector) 371static int radeon_ddc_dump(struct drm_connector *connector)
@@ -620,6 +623,83 @@ static const struct drm_mode_config_funcs radeon_mode_funcs = {
620 .fb_changed = radeonfb_probe, 623 .fb_changed = radeonfb_probe,
621}; 624};
622 625
626struct drm_prop_enum_list {
627 int type;
628 char *name;
629};
630
631static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
632{ { 0, "driver" },
633 { 1, "bios" },
634};
635
636static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
637{ { TV_STD_NTSC, "ntsc" },
638 { TV_STD_PAL, "pal" },
639 { TV_STD_PAL_M, "pal-m" },
640 { TV_STD_PAL_60, "pal-60" },
641 { TV_STD_NTSC_J, "ntsc-j" },
642 { TV_STD_SCART_PAL, "scart-pal" },
643 { TV_STD_PAL_CN, "pal-cn" },
644 { TV_STD_SECAM, "secam" },
645};
646
647int radeon_modeset_create_props(struct radeon_device *rdev)
648{
649 int i, sz;
650
651 if (rdev->is_atom_bios) {
652 rdev->mode_info.coherent_mode_property =
653 drm_property_create(rdev->ddev,
654 DRM_MODE_PROP_RANGE,
655 "coherent", 2);
656 if (!rdev->mode_info.coherent_mode_property)
657 return -ENOMEM;
658
659 rdev->mode_info.coherent_mode_property->values[0] = 0;
660 rdev->mode_info.coherent_mode_property->values[0] = 1;
661 }
662
663 if (!ASIC_IS_AVIVO(rdev)) {
664 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
665 rdev->mode_info.tmds_pll_property =
666 drm_property_create(rdev->ddev,
667 DRM_MODE_PROP_ENUM,
668 "tmds_pll", sz);
669 for (i = 0; i < sz; i++) {
670 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
671 i,
672 radeon_tmds_pll_enum_list[i].type,
673 radeon_tmds_pll_enum_list[i].name);
674 }
675 }
676
677 rdev->mode_info.load_detect_property =
678 drm_property_create(rdev->ddev,
679 DRM_MODE_PROP_RANGE,
680 "load detection", 2);
681 if (!rdev->mode_info.load_detect_property)
682 return -ENOMEM;
683 rdev->mode_info.load_detect_property->values[0] = 0;
684 rdev->mode_info.load_detect_property->values[0] = 1;
685
686 drm_mode_create_scaling_mode_property(rdev->ddev);
687
688 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
689 rdev->mode_info.tv_std_property =
690 drm_property_create(rdev->ddev,
691 DRM_MODE_PROP_ENUM,
692 "tv standard", sz);
693 for (i = 0; i < sz; i++) {
694 drm_property_add_enum(rdev->mode_info.tv_std_property,
695 i,
696 radeon_tv_std_enum_list[i].type,
697 radeon_tv_std_enum_list[i].name);
698 }
699
700 return 0;
701}
702
623int radeon_modeset_init(struct radeon_device *rdev) 703int radeon_modeset_init(struct radeon_device *rdev)
624{ 704{
625 int num_crtc = 2, i; 705 int num_crtc = 2, i;
@@ -640,6 +720,10 @@ int radeon_modeset_init(struct radeon_device *rdev)
640 720
641 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 721 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
642 722
723 ret = radeon_modeset_create_props(rdev);
724 if (ret) {
725 return ret;
726 }
643 /* allocate crtcs - TODO single crtc */ 727 /* allocate crtcs - TODO single crtc */
644 for (i = 0; i < num_crtc; i++) { 728 for (i = 0; i < num_crtc; i++) {
645 radeon_crtc_init(rdev->ddev, i); 729 radeon_crtc_init(rdev->ddev, i);
@@ -678,7 +762,6 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
678 continue; 762 continue;
679 if (first) { 763 if (first) {
680 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 764 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
681 radeon_crtc->devices = radeon_encoder->devices;
682 memcpy(&radeon_crtc->native_mode, 765 memcpy(&radeon_crtc->native_mode,
683 &radeon_encoder->native_mode, 766 &radeon_encoder->native_mode,
684 sizeof(struct radeon_native_mode)); 767 sizeof(struct radeon_native_mode));
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 0bd5879a4957..50fce498910c 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -38,7 +38,6 @@
38#include <linux/console.h> 38#include <linux/console.h>
39 39
40 40
41#if defined(CONFIG_DRM_RADEON_KMS)
42/* 41/*
43 * KMS wrapper. 42 * KMS wrapper.
44 */ 43 */
@@ -77,11 +76,9 @@ int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
77int radeon_debugfs_init(struct drm_minor *minor); 76int radeon_debugfs_init(struct drm_minor *minor);
78void radeon_debugfs_cleanup(struct drm_minor *minor); 77void radeon_debugfs_cleanup(struct drm_minor *minor);
79#endif 78#endif
80#endif
81 79
82 80
83int radeon_no_wb; 81int radeon_no_wb;
84#if defined(CONFIG_DRM_RADEON_KMS)
85int radeon_modeset = -1; 82int radeon_modeset = -1;
86int radeon_dynclks = -1; 83int radeon_dynclks = -1;
87int radeon_r4xx_atom = 0; 84int radeon_r4xx_atom = 0;
@@ -91,12 +88,11 @@ int radeon_gart_size = 512; /* default gart size */
91int radeon_benchmarking = 0; 88int radeon_benchmarking = 0;
92int radeon_testing = 0; 89int radeon_testing = 0;
93int radeon_connector_table = 0; 90int radeon_connector_table = 0;
94#endif 91int radeon_tv = 1;
95 92
96MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 93MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
97module_param_named(no_wb, radeon_no_wb, int, 0444); 94module_param_named(no_wb, radeon_no_wb, int, 0444);
98 95
99#if defined(CONFIG_DRM_RADEON_KMS)
100MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 96MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
101module_param_named(modeset, radeon_modeset, int, 0400); 97module_param_named(modeset, radeon_modeset, int, 0400);
102 98
@@ -123,7 +119,9 @@ module_param_named(test, radeon_testing, int, 0444);
123 119
124MODULE_PARM_DESC(connector_table, "Force connector table"); 120MODULE_PARM_DESC(connector_table, "Force connector table");
125module_param_named(connector_table, radeon_connector_table, int, 0444); 121module_param_named(connector_table, radeon_connector_table, int, 0444);
126#endif 122
123MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
124module_param_named(tv, radeon_tv, int, 0444);
127 125
128static int radeon_suspend(struct drm_device *dev, pm_message_t state) 126static int radeon_suspend(struct drm_device *dev, pm_message_t state)
129{ 127{
@@ -215,7 +213,6 @@ static struct drm_driver driver_old = {
215 .patchlevel = DRIVER_PATCHLEVEL, 213 .patchlevel = DRIVER_PATCHLEVEL,
216}; 214};
217 215
218#if defined(CONFIG_DRM_RADEON_KMS)
219static struct drm_driver kms_driver; 216static struct drm_driver kms_driver;
220 217
221static int __devinit 218static int __devinit
@@ -289,7 +286,7 @@ static struct drm_driver kms_driver = {
289 .poll = drm_poll, 286 .poll = drm_poll,
290 .fasync = drm_fasync, 287 .fasync = drm_fasync,
291#ifdef CONFIG_COMPAT 288#ifdef CONFIG_COMPAT
292 .compat_ioctl = NULL, 289 .compat_ioctl = radeon_kms_compat_ioctl,
293#endif 290#endif
294 }, 291 },
295 292
@@ -309,7 +306,6 @@ static struct drm_driver kms_driver = {
309 .minor = KMS_DRIVER_MINOR, 306 .minor = KMS_DRIVER_MINOR,
310 .patchlevel = KMS_DRIVER_PATCHLEVEL, 307 .patchlevel = KMS_DRIVER_PATCHLEVEL,
311}; 308};
312#endif
313 309
314static struct drm_driver *driver; 310static struct drm_driver *driver;
315 311
@@ -317,7 +313,6 @@ static int __init radeon_init(void)
317{ 313{
318 driver = &driver_old; 314 driver = &driver_old;
319 driver->num_ioctls = radeon_max_ioctl; 315 driver->num_ioctls = radeon_max_ioctl;
320#if defined(CONFIG_DRM_RADEON_KMS)
321#ifdef CONFIG_VGA_CONSOLE 316#ifdef CONFIG_VGA_CONSOLE
322 if (vgacon_text_force() && radeon_modeset == -1) { 317 if (vgacon_text_force() && radeon_modeset == -1) {
323 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 318 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
@@ -328,8 +323,13 @@ static int __init radeon_init(void)
328#endif 323#endif
329 /* if enabled by default */ 324 /* if enabled by default */
330 if (radeon_modeset == -1) { 325 if (radeon_modeset == -1) {
331 DRM_INFO("radeon default to kernel modesetting.\n"); 326#ifdef CONFIG_DRM_RADEON_KMS
327 DRM_INFO("radeon defaulting to kernel modesetting.\n");
332 radeon_modeset = 1; 328 radeon_modeset = 1;
329#else
330 DRM_INFO("radeon defaulting to userspace modesetting.\n");
331 radeon_modeset = 0;
332#endif
333 } 333 }
334 if (radeon_modeset == 1) { 334 if (radeon_modeset == 1) {
335 DRM_INFO("radeon kernel modesetting enabled.\n"); 335 DRM_INFO("radeon kernel modesetting enabled.\n");
@@ -339,7 +339,6 @@ static int __init radeon_init(void)
339 } 339 }
340 /* if the vga console setting is enabled still 340 /* if the vga console setting is enabled still
341 * let modprobe override it */ 341 * let modprobe override it */
342#endif
343 return drm_init(driver); 342 return drm_init(driver);
344} 343}
345 344
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 6fa32dac4e97..cb0cfe4b3082 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -31,6 +31,9 @@
31#ifndef __RADEON_DRV_H__ 31#ifndef __RADEON_DRV_H__
32#define __RADEON_DRV_H__ 32#define __RADEON_DRV_H__
33 33
34#include <linux/firmware.h>
35#include <linux/platform_device.h>
36
34/* General customization: 37/* General customization:
35 */ 38 */
36 39
@@ -353,6 +356,14 @@ typedef struct drm_radeon_private {
353 int r700_sc_hiz_tile_fifo_size; 356 int r700_sc_hiz_tile_fifo_size;
354 int r700_sc_earlyz_tile_fifo_fize; 357 int r700_sc_earlyz_tile_fifo_fize;
355 358
359 struct mutex cs_mutex;
360 u32 cs_id_scnt;
361 u32 cs_id_wcnt;
362 /* r6xx/r7xx drm blit vertex buffer */
363 struct drm_buf *blit_vb;
364
365 /* firmware */
366 const struct firmware *me_fw, *pfp_fw;
356} drm_radeon_private_t; 367} drm_radeon_private_t;
357 368
358typedef struct drm_radeon_buf_priv { 369typedef struct drm_radeon_buf_priv {
@@ -391,6 +402,9 @@ static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
391 (off >= gart_start && off <= gart_end)); 402 (off >= gart_start && off <= gart_end));
392} 403}
393 404
405/* radeon_state.c */
406extern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf);
407
394 /* radeon_cp.c */ 408 /* radeon_cp.c */
395extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 409extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
396extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 410extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
@@ -457,6 +471,8 @@ extern int radeon_driver_open(struct drm_device *dev,
457 struct drm_file *file_priv); 471 struct drm_file *file_priv);
458extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 472extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
459 unsigned long arg); 473 unsigned long arg);
474extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
475 unsigned long arg);
460 476
461extern int radeon_master_create(struct drm_device *dev, struct drm_master *master); 477extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
462extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master); 478extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
@@ -482,6 +498,22 @@ extern int r600_cp_dispatch_indirect(struct drm_device *dev,
482 struct drm_buf *buf, int start, int end); 498 struct drm_buf *buf, int start, int end);
483extern int r600_page_table_init(struct drm_device *dev); 499extern int r600_page_table_init(struct drm_device *dev);
484extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info); 500extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info);
501extern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
502extern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv);
503extern int r600_cp_dispatch_texture(struct drm_device *dev,
504 struct drm_file *file_priv,
505 drm_radeon_texture_t *tex,
506 drm_radeon_tex_image_t *image);
507/* r600_blit.c */
508extern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv);
509extern void r600_done_blit_copy(struct drm_device *dev);
510extern void r600_blit_copy(struct drm_device *dev,
511 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
512 int size_bytes);
513extern void r600_blit_swap(struct drm_device *dev,
514 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
515 int sx, int sy, int dx, int dy,
516 int w, int h, int src_pitch, int dst_pitch, int cpp);
485 517
486/* Flags for stats.boxes 518/* Flags for stats.boxes
487 */ 519 */
@@ -1067,6 +1099,9 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
1067# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 1099# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
1068# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 1100# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
1069 1101
1102#define R300_CP_RESYNC_ADDR 0x0778
1103#define R300_CP_RESYNC_DATA 0x077c
1104
1070#define RADEON_AIC_CNTL 0x01d0 1105#define RADEON_AIC_CNTL 0x01d0
1071# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 1106# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
1072# define RS400_MSI_REARM (1 << 3) 1107# define RS400_MSI_REARM (1 << 3)
@@ -1109,13 +1144,71 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
1109# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 1144# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
1110# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 1145# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
1111 1146
1112# define R600_IT_INDIRECT_BUFFER 0x00003200 1147# define R600_IT_INDIRECT_BUFFER_END 0x00001700
1113# define R600_IT_ME_INITIALIZE 0x00004400 1148# define R600_IT_SET_PREDICATION 0x00002000
1149# define R600_IT_REG_RMW 0x00002100
1150# define R600_IT_COND_EXEC 0x00002200
1151# define R600_IT_PRED_EXEC 0x00002300
1152# define R600_IT_START_3D_CMDBUF 0x00002400
1153# define R600_IT_DRAW_INDEX_2 0x00002700
1154# define R600_IT_CONTEXT_CONTROL 0x00002800
1155# define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900
1156# define R600_IT_INDEX_TYPE 0x00002A00
1157# define R600_IT_DRAW_INDEX 0x00002B00
1158# define R600_IT_DRAW_INDEX_AUTO 0x00002D00
1159# define R600_IT_DRAW_INDEX_IMMD 0x00002E00
1160# define R600_IT_NUM_INSTANCES 0x00002F00
1161# define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400
1162# define R600_IT_INDIRECT_BUFFER_MP 0x00003800
1163# define R600_IT_MEM_SEMAPHORE 0x00003900
1164# define R600_IT_MPEG_INDEX 0x00003A00
1165# define R600_IT_WAIT_REG_MEM 0x00003C00
1166# define R600_IT_MEM_WRITE 0x00003D00
1167# define R600_IT_INDIRECT_BUFFER 0x00003200
1168# define R600_IT_CP_INTERRUPT 0x00004000
1169# define R600_IT_SURFACE_SYNC 0x00004300
1170# define R600_CB0_DEST_BASE_ENA (1 << 6)
1171# define R600_TC_ACTION_ENA (1 << 23)
1172# define R600_VC_ACTION_ENA (1 << 24)
1173# define R600_CB_ACTION_ENA (1 << 25)
1174# define R600_DB_ACTION_ENA (1 << 26)
1175# define R600_SH_ACTION_ENA (1 << 27)
1176# define R600_SMX_ACTION_ENA (1 << 28)
1177# define R600_IT_ME_INITIALIZE 0x00004400
1114# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1178# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1115# define R600_IT_EVENT_WRITE 0x00004600 1179# define R600_IT_COND_WRITE 0x00004500
1116# define R600_IT_SET_CONFIG_REG 0x00006800 1180# define R600_IT_EVENT_WRITE 0x00004600
1117# define R600_SET_CONFIG_REG_OFFSET 0x00008000 1181# define R600_IT_EVENT_WRITE_EOP 0x00004700
1118# define R600_SET_CONFIG_REG_END 0x0000ac00 1182# define R600_IT_ONE_REG_WRITE 0x00005700
1183# define R600_IT_SET_CONFIG_REG 0x00006800
1184# define R600_SET_CONFIG_REG_OFFSET 0x00008000
1185# define R600_SET_CONFIG_REG_END 0x0000ac00
1186# define R600_IT_SET_CONTEXT_REG 0x00006900
1187# define R600_SET_CONTEXT_REG_OFFSET 0x00028000
1188# define R600_SET_CONTEXT_REG_END 0x00029000
1189# define R600_IT_SET_ALU_CONST 0x00006A00
1190# define R600_SET_ALU_CONST_OFFSET 0x00030000
1191# define R600_SET_ALU_CONST_END 0x00032000
1192# define R600_IT_SET_BOOL_CONST 0x00006B00
1193# define R600_SET_BOOL_CONST_OFFSET 0x0003e380
1194# define R600_SET_BOOL_CONST_END 0x00040000
1195# define R600_IT_SET_LOOP_CONST 0x00006C00
1196# define R600_SET_LOOP_CONST_OFFSET 0x0003e200
1197# define R600_SET_LOOP_CONST_END 0x0003e380
1198# define R600_IT_SET_RESOURCE 0x00006D00
1199# define R600_SET_RESOURCE_OFFSET 0x00038000
1200# define R600_SET_RESOURCE_END 0x0003c000
1201# define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0
1202# define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1
1203# define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2
1204# define R600_SQ_TEX_VTX_VALID_BUFFER 0x3
1205# define R600_IT_SET_SAMPLER 0x00006E00
1206# define R600_SET_SAMPLER_OFFSET 0x0003c000
1207# define R600_SET_SAMPLER_END 0x0003cff0
1208# define R600_IT_SET_CTL_CONST 0x00006F00
1209# define R600_SET_CTL_CONST_OFFSET 0x0003cff0
1210# define R600_SET_CTL_CONST_END 0x0003e200
1211# define R600_IT_SURFACE_BASE_UPDATE 0x00007300
1119 1212
1120#define RADEON_CP_PACKET_MASK 0xC0000000 1213#define RADEON_CP_PACKET_MASK 0xC0000000
1121#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 1214#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
@@ -1593,6 +1686,52 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
1593#define R600_CB_COLOR7_BASE 0x2805c 1686#define R600_CB_COLOR7_BASE 0x2805c
1594#define R600_CB_COLOR7_FRAG 0x280fc 1687#define R600_CB_COLOR7_FRAG 0x280fc
1595 1688
1689#define R600_CB_COLOR0_SIZE 0x28060
1690#define R600_CB_COLOR0_VIEW 0x28080
1691#define R600_CB_COLOR0_INFO 0x280a0
1692#define R600_CB_COLOR0_TILE 0x280c0
1693#define R600_CB_COLOR0_FRAG 0x280e0
1694#define R600_CB_COLOR0_MASK 0x28100
1695
1696#define AVIVO_D1MODE_VLINE_START_END 0x6538
1697#define AVIVO_D2MODE_VLINE_START_END 0x6d38
1698#define R600_CP_COHER_BASE 0x85f8
1699#define R600_DB_DEPTH_BASE 0x2800c
1700#define R600_SQ_PGM_START_FS 0x28894
1701#define R600_SQ_PGM_START_ES 0x28880
1702#define R600_SQ_PGM_START_VS 0x28858
1703#define R600_SQ_PGM_RESOURCES_VS 0x28868
1704#define R600_SQ_PGM_CF_OFFSET_VS 0x288d0
1705#define R600_SQ_PGM_START_GS 0x2886c
1706#define R600_SQ_PGM_START_PS 0x28840
1707#define R600_SQ_PGM_RESOURCES_PS 0x28850
1708#define R600_SQ_PGM_EXPORTS_PS 0x28854
1709#define R600_SQ_PGM_CF_OFFSET_PS 0x288cc
1710#define R600_VGT_DMA_BASE 0x287e8
1711#define R600_VGT_DMA_BASE_HI 0x287e4
1712#define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10
1713#define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14
1714#define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18
1715#define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c
1716#define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44
1717#define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48
1718#define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c
1719#define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50
1720#define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8
1721#define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8
1722#define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8
1723#define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08
1724#define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc
1725#define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec
1726#define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc
1727#define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c
1728
1729#define R600_VGT_PRIMITIVE_TYPE 0x8958
1730
1731#define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030
1732#define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240
1733#define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204
1734
1596#define R600_TC_CNTL 0x9608 1735#define R600_TC_CNTL 0x9608
1597# define R600_TC_L2_SIZE(x) ((x) << 5) 1736# define R600_TC_L2_SIZE(x) ((x) << 5)
1598# define R600_L2_DISABLE_LATE_HIT (1 << 9) 1737# define R600_L2_DISABLE_LATE_HIT (1 << 9)
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 0a92706eac19..621646752cd2 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -126,6 +126,23 @@ radeon_link_encoder_connector(struct drm_device *dev)
126 } 126 }
127} 127}
128 128
129void radeon_encoder_set_active_device(struct drm_encoder *encoder)
130{
131 struct drm_device *dev = encoder->dev;
132 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
133 struct drm_connector *connector;
134
135 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
136 if (connector->encoder == encoder) {
137 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
138 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
139 DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
140 radeon_encoder->active_device, radeon_encoder->devices,
141 radeon_connector->devices, encoder->encoder_type);
142 }
143 }
144}
145
129static struct drm_connector * 146static struct drm_connector *
130radeon_get_connector_for_encoder(struct drm_encoder *encoder) 147radeon_get_connector_for_encoder(struct drm_encoder *encoder)
131{ 148{
@@ -224,9 +241,12 @@ atombios_dac_setup(struct drm_encoder *encoder, int action)
224 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 241 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
225 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 242 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
226 int index = 0, num = 0; 243 int index = 0, num = 0;
227 /* fixme - fill in enc_priv for atom dac */ 244 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
228 enum radeon_tv_std tv_std = TV_STD_NTSC; 245 enum radeon_tv_std tv_std = TV_STD_NTSC;
229 246
247 if (dac_info->tv_std)
248 tv_std = dac_info->tv_std;
249
230 memset(&args, 0, sizeof(args)); 250 memset(&args, 0, sizeof(args));
231 251
232 switch (radeon_encoder->encoder_id) { 252 switch (radeon_encoder->encoder_id) {
@@ -244,9 +264,9 @@ atombios_dac_setup(struct drm_encoder *encoder, int action)
244 264
245 args.ucAction = action; 265 args.ucAction = action;
246 266
247 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 267 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
248 args.ucDacStandard = ATOM_DAC1_PS2; 268 args.ucDacStandard = ATOM_DAC1_PS2;
249 else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) 269 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
250 args.ucDacStandard = ATOM_DAC1_CV; 270 args.ucDacStandard = ATOM_DAC1_CV;
251 else { 271 else {
252 switch (tv_std) { 272 switch (tv_std) {
@@ -279,16 +299,19 @@ atombios_tv_setup(struct drm_encoder *encoder, int action)
279 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 299 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
280 TV_ENCODER_CONTROL_PS_ALLOCATION args; 300 TV_ENCODER_CONTROL_PS_ALLOCATION args;
281 int index = 0; 301 int index = 0;
282 /* fixme - fill in enc_priv for atom dac */ 302 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
283 enum radeon_tv_std tv_std = TV_STD_NTSC; 303 enum radeon_tv_std tv_std = TV_STD_NTSC;
284 304
305 if (dac_info->tv_std)
306 tv_std = dac_info->tv_std;
307
285 memset(&args, 0, sizeof(args)); 308 memset(&args, 0, sizeof(args));
286 309
287 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 310 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
288 311
289 args.sTVEncoder.ucAction = action; 312 args.sTVEncoder.ucAction = action;
290 313
291 if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) 314 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
292 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 315 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
293 else { 316 else {
294 switch (tv_std) { 317 switch (tv_std) {
@@ -520,6 +543,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
520 543
521 switch (connector->connector_type) { 544 switch (connector->connector_type) {
522 case DRM_MODE_CONNECTOR_DVII: 545 case DRM_MODE_CONNECTOR_DVII:
546 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
523 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) 547 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
524 return ATOM_ENCODER_MODE_HDMI; 548 return ATOM_ENCODER_MODE_HDMI;
525 else if (radeon_connector->use_digital) 549 else if (radeon_connector->use_digital)
@@ -529,7 +553,6 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
529 break; 553 break;
530 case DRM_MODE_CONNECTOR_DVID: 554 case DRM_MODE_CONNECTOR_DVID:
531 case DRM_MODE_CONNECTOR_HDMIA: 555 case DRM_MODE_CONNECTOR_HDMIA:
532 case DRM_MODE_CONNECTOR_HDMIB:
533 default: 556 default:
534 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) 557 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
535 return ATOM_ENCODER_MODE_HDMI; 558 return ATOM_ENCODER_MODE_HDMI;
@@ -825,10 +848,10 @@ atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
825 848
826 /* XXX: fix up scratch reg handling */ 849 /* XXX: fix up scratch reg handling */
827 temp = RREG32(reg); 850 temp = RREG32(reg);
828 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) 851 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
829 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 852 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
830 (radeon_crtc->crtc_id << 18))); 853 (radeon_crtc->crtc_id << 18)));
831 else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) 854 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
832 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 855 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
833 else 856 else
834 WREG32(reg, 0); 857 WREG32(reg, 0);
@@ -851,9 +874,19 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
851 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 874 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
852 int index = 0; 875 int index = 0;
853 bool is_dig = false; 876 bool is_dig = false;
877 int devices;
854 878
855 memset(&args, 0, sizeof(args)); 879 memset(&args, 0, sizeof(args));
856 880
881 /* on DPMS off we have no idea if active device is meaningful */
882 if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device)
883 devices = radeon_encoder->devices;
884 else
885 devices = radeon_encoder->active_device;
886
887 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
888 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
889 radeon_encoder->active_device);
857 switch (radeon_encoder->encoder_id) { 890 switch (radeon_encoder->encoder_id) {
858 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 891 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
859 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 892 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
@@ -881,18 +914,18 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
881 break; 914 break;
882 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 915 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
883 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 916 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
884 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) 917 if (devices & (ATOM_DEVICE_TV_SUPPORT))
885 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 918 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
886 else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) 919 else if (devices & (ATOM_DEVICE_CV_SUPPORT))
887 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 920 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
888 else 921 else
889 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 922 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
890 break; 923 break;
891 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 924 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
892 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 925 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
893 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) 926 if (devices & (ATOM_DEVICE_TV_SUPPORT))
894 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 927 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
895 else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) 928 else if (devices & (ATOM_DEVICE_CV_SUPPORT))
896 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 929 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
897 else 930 else
898 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 931 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
@@ -979,18 +1012,18 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
979 break; 1012 break;
980 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1013 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
981 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1014 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
982 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) 1015 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
983 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1016 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
984 else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) 1017 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
985 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1018 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
986 else 1019 else
987 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1020 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
988 break; 1021 break;
989 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1022 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
990 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1023 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
991 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) 1024 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
992 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1025 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
993 else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) 1026 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
994 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1027 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
995 else 1028 else
996 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1029 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
@@ -1019,17 +1052,17 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1019 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1052 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1020 break; 1053 break;
1021 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1054 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1022 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) 1055 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1023 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1056 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1024 else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) 1057 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1025 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1058 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1026 else 1059 else
1027 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1060 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1028 break; 1061 break;
1029 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1062 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1030 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) 1063 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1031 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1064 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1032 else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) 1065 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1033 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1066 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1034 else 1067 else
1035 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1068 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
@@ -1097,7 +1130,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1097 atombios_set_encoder_crtc_source(encoder); 1130 atombios_set_encoder_crtc_source(encoder);
1098 1131
1099 if (ASIC_IS_AVIVO(rdev)) { 1132 if (ASIC_IS_AVIVO(rdev)) {
1100 if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 1133 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1101 atombios_yuv_setup(encoder, true); 1134 atombios_yuv_setup(encoder, true);
1102 else 1135 else
1103 atombios_yuv_setup(encoder, false); 1136 atombios_yuv_setup(encoder, false);
@@ -1135,7 +1168,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1135 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1168 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1136 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1169 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1137 atombios_dac_setup(encoder, ATOM_ENABLE); 1170 atombios_dac_setup(encoder, ATOM_ENABLE);
1138 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1171 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1139 atombios_tv_setup(encoder, ATOM_ENABLE); 1172 atombios_tv_setup(encoder, ATOM_ENABLE);
1140 break; 1173 break;
1141 } 1174 }
@@ -1143,11 +1176,12 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1143} 1176}
1144 1177
1145static bool 1178static bool
1146atombios_dac_load_detect(struct drm_encoder *encoder) 1179atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1147{ 1180{
1148 struct drm_device *dev = encoder->dev; 1181 struct drm_device *dev = encoder->dev;
1149 struct radeon_device *rdev = dev->dev_private; 1182 struct radeon_device *rdev = dev->dev_private;
1150 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1183 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1184 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1151 1185
1152 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 1186 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1153 ATOM_DEVICE_CV_SUPPORT | 1187 ATOM_DEVICE_CV_SUPPORT |
@@ -1168,15 +1202,15 @@ atombios_dac_load_detect(struct drm_encoder *encoder)
1168 else 1202 else
1169 args.sDacload.ucDacType = ATOM_DAC_B; 1203 args.sDacload.ucDacType = ATOM_DAC_B;
1170 1204
1171 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) 1205 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1172 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 1206 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1173 else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) 1207 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1174 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 1208 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1175 else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 1209 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1176 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 1210 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1177 if (crev >= 3) 1211 if (crev >= 3)
1178 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1212 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1179 } else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 1213 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1180 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 1214 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1181 if (crev >= 3) 1215 if (crev >= 3)
1182 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1216 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
@@ -1195,9 +1229,10 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec
1195 struct drm_device *dev = encoder->dev; 1229 struct drm_device *dev = encoder->dev;
1196 struct radeon_device *rdev = dev->dev_private; 1230 struct radeon_device *rdev = dev->dev_private;
1197 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1231 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1232 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1198 uint32_t bios_0_scratch; 1233 uint32_t bios_0_scratch;
1199 1234
1200 if (!atombios_dac_load_detect(encoder)) { 1235 if (!atombios_dac_load_detect(encoder, connector)) {
1201 DRM_DEBUG("detect returned false \n"); 1236 DRM_DEBUG("detect returned false \n");
1202 return connector_status_unknown; 1237 return connector_status_unknown;
1203 } 1238 }
@@ -1207,17 +1242,20 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec
1207 else 1242 else
1208 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 1243 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1209 1244
1210 DRM_DEBUG("Bios 0 scratch %x\n", bios_0_scratch); 1245 DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1211 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 1246 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1212 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 1247 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1213 return connector_status_connected; 1248 return connector_status_connected;
1214 } else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 1249 }
1250 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1215 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 1251 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1216 return connector_status_connected; 1252 return connector_status_connected;
1217 } else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 1253 }
1254 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1218 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 1255 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1219 return connector_status_connected; 1256 return connector_status_connected;
1220 } else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 1257 }
1258 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1221 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 1259 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1222 return connector_status_connected; /* CTV */ 1260 return connector_status_connected; /* CTV */
1223 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 1261 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
@@ -1230,6 +1268,8 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1230{ 1268{
1231 radeon_atom_output_lock(encoder, true); 1269 radeon_atom_output_lock(encoder, true);
1232 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 1270 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1271
1272 radeon_encoder_set_active_device(encoder);
1233} 1273}
1234 1274
1235static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 1275static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
@@ -1238,12 +1278,20 @@ static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1238 radeon_atom_output_lock(encoder, false); 1278 radeon_atom_output_lock(encoder, false);
1239} 1279}
1240 1280
1281static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1282{
1283 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1284 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1285 radeon_encoder->active_device = 0;
1286}
1287
1241static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 1288static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1242 .dpms = radeon_atom_encoder_dpms, 1289 .dpms = radeon_atom_encoder_dpms,
1243 .mode_fixup = radeon_atom_mode_fixup, 1290 .mode_fixup = radeon_atom_mode_fixup,
1244 .prepare = radeon_atom_encoder_prepare, 1291 .prepare = radeon_atom_encoder_prepare,
1245 .mode_set = radeon_atom_encoder_mode_set, 1292 .mode_set = radeon_atom_encoder_mode_set,
1246 .commit = radeon_atom_encoder_commit, 1293 .commit = radeon_atom_encoder_commit,
1294 .disable = radeon_atom_encoder_disable,
1247 /* no detect for TMDS/LVDS yet */ 1295 /* no detect for TMDS/LVDS yet */
1248}; 1296};
1249 1297
@@ -1268,6 +1316,18 @@ static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1268 .destroy = radeon_enc_destroy, 1316 .destroy = radeon_enc_destroy,
1269}; 1317};
1270 1318
1319struct radeon_encoder_atom_dac *
1320radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1321{
1322 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1323
1324 if (!dac)
1325 return NULL;
1326
1327 dac->tv_std = TV_STD_NTSC;
1328 return dac;
1329}
1330
1271struct radeon_encoder_atom_dig * 1331struct radeon_encoder_atom_dig *
1272radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 1332radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1273{ 1333{
@@ -1336,6 +1396,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
1336 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1396 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1337 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1397 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1338 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); 1398 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1399 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1339 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 1400 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1340 break; 1401 break;
1341 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1402 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
@@ -1345,8 +1406,14 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
1345 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1406 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1346 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1407 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1347 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1408 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1348 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 1409 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1349 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 1410 radeon_encoder->rmx_type = RMX_FULL;
1411 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1412 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1413 } else {
1414 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1415 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1416 }
1350 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 1417 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1351 break; 1418 break;
1352 } 1419 }
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index ec383edf5f38..944e4fa78db5 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -28,15 +28,7 @@
28 */ 28 */
29 29
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/errno.h>
33#include <linux/string.h>
34#include <linux/mm.h>
35#include <linux/tty.h>
36#include <linux/slab.h>
37#include <linux/delay.h>
38#include <linux/fb.h> 31#include <linux/fb.h>
39#include <linux/init.h>
40 32
41#include "drmP.h" 33#include "drmP.h"
42#include "drm.h" 34#include "drm.h"
@@ -45,375 +37,24 @@
45#include "radeon_drm.h" 37#include "radeon_drm.h"
46#include "radeon.h" 38#include "radeon.h"
47 39
40#include "drm_fb_helper.h"
41
48struct radeon_fb_device { 42struct radeon_fb_device {
49 struct radeon_device *rdev; 43 struct drm_fb_helper helper;
50 struct drm_display_mode *mode;
51 struct radeon_framebuffer *rfb; 44 struct radeon_framebuffer *rfb;
52 int crtc_count; 45 struct radeon_device *rdev;
53 /* crtc currently bound to this */
54 uint32_t crtc_ids[2];
55}; 46};
56 47
57static int radeonfb_setcolreg(unsigned regno,
58 unsigned red,
59 unsigned green,
60 unsigned blue,
61 unsigned transp,
62 struct fb_info *info)
63{
64 struct radeon_fb_device *rfbdev = info->par;
65 struct drm_device *dev = rfbdev->rdev->ddev;
66 struct drm_crtc *crtc;
67 int i;
68
69 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
70 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
71 struct drm_mode_set *modeset = &radeon_crtc->mode_set;
72 struct drm_framebuffer *fb = modeset->fb;
73
74 for (i = 0; i < rfbdev->crtc_count; i++) {
75 if (crtc->base.id == rfbdev->crtc_ids[i]) {
76 break;
77 }
78 }
79 if (i == rfbdev->crtc_count) {
80 continue;
81 }
82 if (regno > 255) {
83 return 1;
84 }
85 if (fb->depth == 8) {
86 radeon_crtc_fb_gamma_set(crtc, red, green, blue, regno);
87 return 0;
88 }
89
90 if (regno < 16) {
91 switch (fb->depth) {
92 case 15:
93 fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) |
94 ((green & 0xf800) >> 6) |
95 ((blue & 0xf800) >> 11);
96 break;
97 case 16:
98 fb->pseudo_palette[regno] = (red & 0xf800) |
99 ((green & 0xfc00) >> 5) |
100 ((blue & 0xf800) >> 11);
101 break;
102 case 24:
103 case 32:
104 fb->pseudo_palette[regno] =
105 (((red >> 8) & 0xff) << info->var.red.offset) |
106 (((green >> 8) & 0xff) << info->var.green.offset) |
107 (((blue >> 8) & 0xff) << info->var.blue.offset);
108 break;
109 }
110 }
111 }
112 return 0;
113}
114
115static int radeonfb_check_var(struct fb_var_screeninfo *var,
116 struct fb_info *info)
117{
118 struct radeon_fb_device *rfbdev = info->par;
119 struct radeon_framebuffer *rfb = rfbdev->rfb;
120 struct drm_framebuffer *fb = &rfb->base;
121 int depth;
122
123 if (var->pixclock == -1 || !var->pixclock) {
124 return -EINVAL;
125 }
126 /* Need to resize the fb object !!! */
127 if (var->xres > fb->width || var->yres > fb->height) {
128 DRM_ERROR("Requested width/height is greater than current fb "
129 "object %dx%d > %dx%d\n", var->xres, var->yres,
130 fb->width, fb->height);
131 DRM_ERROR("Need resizing code.\n");
132 return -EINVAL;
133 }
134
135 switch (var->bits_per_pixel) {
136 case 16:
137 depth = (var->green.length == 6) ? 16 : 15;
138 break;
139 case 32:
140 depth = (var->transp.length > 0) ? 32 : 24;
141 break;
142 default:
143 depth = var->bits_per_pixel;
144 break;
145 }
146
147 switch (depth) {
148 case 8:
149 var->red.offset = 0;
150 var->green.offset = 0;
151 var->blue.offset = 0;
152 var->red.length = 8;
153 var->green.length = 8;
154 var->blue.length = 8;
155 var->transp.length = 0;
156 var->transp.offset = 0;
157 break;
158#ifdef __LITTLE_ENDIAN
159 case 15:
160 var->red.offset = 10;
161 var->green.offset = 5;
162 var->blue.offset = 0;
163 var->red.length = 5;
164 var->green.length = 5;
165 var->blue.length = 5;
166 var->transp.length = 1;
167 var->transp.offset = 15;
168 break;
169 case 16:
170 var->red.offset = 11;
171 var->green.offset = 5;
172 var->blue.offset = 0;
173 var->red.length = 5;
174 var->green.length = 6;
175 var->blue.length = 5;
176 var->transp.length = 0;
177 var->transp.offset = 0;
178 break;
179 case 24:
180 var->red.offset = 16;
181 var->green.offset = 8;
182 var->blue.offset = 0;
183 var->red.length = 8;
184 var->green.length = 8;
185 var->blue.length = 8;
186 var->transp.length = 0;
187 var->transp.offset = 0;
188 break;
189 case 32:
190 var->red.offset = 16;
191 var->green.offset = 8;
192 var->blue.offset = 0;
193 var->red.length = 8;
194 var->green.length = 8;
195 var->blue.length = 8;
196 var->transp.length = 8;
197 var->transp.offset = 24;
198 break;
199#else
200 case 24:
201 var->red.offset = 8;
202 var->green.offset = 16;
203 var->blue.offset = 24;
204 var->red.length = 8;
205 var->green.length = 8;
206 var->blue.length = 8;
207 var->transp.length = 0;
208 var->transp.offset = 0;
209 break;
210 case 32:
211 var->red.offset = 8;
212 var->green.offset = 16;
213 var->blue.offset = 24;
214 var->red.length = 8;
215 var->green.length = 8;
216 var->blue.length = 8;
217 var->transp.length = 8;
218 var->transp.offset = 0;
219 break;
220#endif
221 default:
222 return -EINVAL;
223 }
224 return 0;
225}
226
227/* this will let fbcon do the mode init */
228static int radeonfb_set_par(struct fb_info *info)
229{
230 struct radeon_fb_device *rfbdev = info->par;
231 struct drm_device *dev = rfbdev->rdev->ddev;
232 struct fb_var_screeninfo *var = &info->var;
233 struct drm_crtc *crtc;
234 int ret;
235 int i;
236
237 if (var->pixclock != -1) {
238 DRM_ERROR("PIXEL CLCOK SET\n");
239 return -EINVAL;
240 }
241
242 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
243 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
244
245 for (i = 0; i < rfbdev->crtc_count; i++) {
246 if (crtc->base.id == rfbdev->crtc_ids[i]) {
247 break;
248 }
249 }
250 if (i == rfbdev->crtc_count) {
251 continue;
252 }
253 if (crtc->fb == radeon_crtc->mode_set.fb) {
254 mutex_lock(&dev->mode_config.mutex);
255 ret = crtc->funcs->set_config(&radeon_crtc->mode_set);
256 mutex_unlock(&dev->mode_config.mutex);
257 if (ret) {
258 return ret;
259 }
260 }
261 }
262 return 0;
263}
264
265static int radeonfb_pan_display(struct fb_var_screeninfo *var,
266 struct fb_info *info)
267{
268 struct radeon_fb_device *rfbdev = info->par;
269 struct drm_device *dev = rfbdev->rdev->ddev;
270 struct drm_mode_set *modeset;
271 struct drm_crtc *crtc;
272 struct radeon_crtc *radeon_crtc;
273 int ret = 0;
274 int i;
275
276 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
277 for (i = 0; i < rfbdev->crtc_count; i++) {
278 if (crtc->base.id == rfbdev->crtc_ids[i]) {
279 break;
280 }
281 }
282
283 if (i == rfbdev->crtc_count) {
284 continue;
285 }
286
287 radeon_crtc = to_radeon_crtc(crtc);
288 modeset = &radeon_crtc->mode_set;
289
290 modeset->x = var->xoffset;
291 modeset->y = var->yoffset;
292
293 if (modeset->num_connectors) {
294 mutex_lock(&dev->mode_config.mutex);
295 ret = crtc->funcs->set_config(modeset);
296 mutex_unlock(&dev->mode_config.mutex);
297 if (!ret) {
298 info->var.xoffset = var->xoffset;
299 info->var.yoffset = var->yoffset;
300 }
301 }
302 }
303 return ret;
304}
305
306static void radeonfb_on(struct fb_info *info)
307{
308 struct radeon_fb_device *rfbdev = info->par;
309 struct drm_device *dev = rfbdev->rdev->ddev;
310 struct drm_crtc *crtc;
311 struct drm_encoder *encoder;
312 int i;
313
314 /*
315 * For each CRTC in this fb, find all associated encoders
316 * and turn them off, then turn off the CRTC.
317 */
318 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
319 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
320
321 for (i = 0; i < rfbdev->crtc_count; i++) {
322 if (crtc->base.id == rfbdev->crtc_ids[i]) {
323 break;
324 }
325 }
326
327 mutex_lock(&dev->mode_config.mutex);
328 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
329 mutex_unlock(&dev->mode_config.mutex);
330
331 /* Found a CRTC on this fb, now find encoders */
332 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
333 if (encoder->crtc == crtc) {
334 struct drm_encoder_helper_funcs *encoder_funcs;
335
336 encoder_funcs = encoder->helper_private;
337 mutex_lock(&dev->mode_config.mutex);
338 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
339 mutex_unlock(&dev->mode_config.mutex);
340 }
341 }
342 }
343}
344
345static void radeonfb_off(struct fb_info *info, int dpms_mode)
346{
347 struct radeon_fb_device *rfbdev = info->par;
348 struct drm_device *dev = rfbdev->rdev->ddev;
349 struct drm_crtc *crtc;
350 struct drm_encoder *encoder;
351 int i;
352
353 /*
354 * For each CRTC in this fb, find all associated encoders
355 * and turn them off, then turn off the CRTC.
356 */
357 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
358 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
359
360 for (i = 0; i < rfbdev->crtc_count; i++) {
361 if (crtc->base.id == rfbdev->crtc_ids[i]) {
362 break;
363 }
364 }
365
366 /* Found a CRTC on this fb, now find encoders */
367 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
368 if (encoder->crtc == crtc) {
369 struct drm_encoder_helper_funcs *encoder_funcs;
370
371 encoder_funcs = encoder->helper_private;
372 mutex_lock(&dev->mode_config.mutex);
373 encoder_funcs->dpms(encoder, dpms_mode);
374 mutex_unlock(&dev->mode_config.mutex);
375 }
376 }
377 if (dpms_mode == DRM_MODE_DPMS_OFF) {
378 mutex_lock(&dev->mode_config.mutex);
379 crtc_funcs->dpms(crtc, dpms_mode);
380 mutex_unlock(&dev->mode_config.mutex);
381 }
382 }
383}
384
385int radeonfb_blank(int blank, struct fb_info *info)
386{
387 switch (blank) {
388 case FB_BLANK_UNBLANK:
389 radeonfb_on(info);
390 break;
391 case FB_BLANK_NORMAL:
392 radeonfb_off(info, DRM_MODE_DPMS_STANDBY);
393 break;
394 case FB_BLANK_HSYNC_SUSPEND:
395 radeonfb_off(info, DRM_MODE_DPMS_STANDBY);
396 break;
397 case FB_BLANK_VSYNC_SUSPEND:
398 radeonfb_off(info, DRM_MODE_DPMS_SUSPEND);
399 break;
400 case FB_BLANK_POWERDOWN:
401 radeonfb_off(info, DRM_MODE_DPMS_OFF);
402 break;
403 }
404 return 0;
405}
406
407static struct fb_ops radeonfb_ops = { 48static struct fb_ops radeonfb_ops = {
408 .owner = THIS_MODULE, 49 .owner = THIS_MODULE,
409 .fb_check_var = radeonfb_check_var, 50 .fb_check_var = drm_fb_helper_check_var,
410 .fb_set_par = radeonfb_set_par, 51 .fb_set_par = drm_fb_helper_set_par,
411 .fb_setcolreg = radeonfb_setcolreg, 52 .fb_setcolreg = drm_fb_helper_setcolreg,
412 .fb_fillrect = cfb_fillrect, 53 .fb_fillrect = cfb_fillrect,
413 .fb_copyarea = cfb_copyarea, 54 .fb_copyarea = cfb_copyarea,
414 .fb_imageblit = cfb_imageblit, 55 .fb_imageblit = cfb_imageblit,
415 .fb_pan_display = radeonfb_pan_display, 56 .fb_pan_display = drm_fb_helper_pan_display,
416 .fb_blank = radeonfb_blank, 57 .fb_blank = drm_fb_helper_blank,
417}; 58};
418 59
419/** 60/**
@@ -456,21 +97,6 @@ int radeonfb_resize(struct drm_device *dev, struct drm_crtc *crtc)
456} 97}
457EXPORT_SYMBOL(radeonfb_resize); 98EXPORT_SYMBOL(radeonfb_resize);
458 99
459static struct drm_mode_set panic_mode;
460
461int radeonfb_panic(struct notifier_block *n, unsigned long ununsed,
462 void *panic_str)
463{
464 DRM_ERROR("panic occurred, switching back to text console\n");
465 drm_crtc_helper_set_config(&panic_mode);
466 return 0;
467}
468EXPORT_SYMBOL(radeonfb_panic);
469
470static struct notifier_block paniced = {
471 .notifier_call = radeonfb_panic,
472};
473
474static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled) 100static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
475{ 101{
476 int aligned = width; 102 int aligned = width;
@@ -495,11 +121,16 @@ static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bo
495 return aligned; 121 return aligned;
496} 122}
497 123
498int radeonfb_create(struct radeon_device *rdev, 124static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
125 .gamma_set = radeon_crtc_fb_gamma_set,
126};
127
128int radeonfb_create(struct drm_device *dev,
499 uint32_t fb_width, uint32_t fb_height, 129 uint32_t fb_width, uint32_t fb_height,
500 uint32_t surface_width, uint32_t surface_height, 130 uint32_t surface_width, uint32_t surface_height,
501 struct radeon_framebuffer **rfb_p) 131 struct drm_framebuffer **fb_p)
502{ 132{
133 struct radeon_device *rdev = dev->dev_private;
503 struct fb_info *info; 134 struct fb_info *info;
504 struct radeon_fb_device *rfbdev; 135 struct radeon_fb_device *rfbdev;
505 struct drm_framebuffer *fb = NULL; 136 struct drm_framebuffer *fb = NULL;
@@ -513,6 +144,7 @@ int radeonfb_create(struct radeon_device *rdev,
513 void *fbptr = NULL; 144 void *fbptr = NULL;
514 unsigned long tmp; 145 unsigned long tmp;
515 bool fb_tiled = false; /* useful for testing */ 146 bool fb_tiled = false; /* useful for testing */
147 u32 tiling_flags = 0;
516 148
517 mode_cmd.width = surface_width; 149 mode_cmd.width = surface_width;
518 mode_cmd.height = surface_height; 150 mode_cmd.height = surface_height;
@@ -537,7 +169,22 @@ int radeonfb_create(struct radeon_device *rdev,
537 robj = gobj->driver_private; 169 robj = gobj->driver_private;
538 170
539 if (fb_tiled) 171 if (fb_tiled)
540 radeon_object_set_tiling_flags(robj, RADEON_TILING_MACRO|RADEON_TILING_SURFACE, mode_cmd.pitch); 172 tiling_flags = RADEON_TILING_MACRO;
173
174#ifdef __BIG_ENDIAN
175 switch (mode_cmd.bpp) {
176 case 32:
177 tiling_flags |= RADEON_TILING_SWAP_32BIT;
178 break;
179 case 16:
180 tiling_flags |= RADEON_TILING_SWAP_16BIT;
181 default:
182 break;
183 }
184#endif
185
186 if (tiling_flags)
187 radeon_object_set_tiling_flags(robj, tiling_flags | RADEON_TILING_SURFACE, mode_cmd.pitch);
541 mutex_lock(&rdev->ddev->struct_mutex); 188 mutex_lock(&rdev->ddev->struct_mutex);
542 fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj); 189 fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj);
543 if (fb == NULL) { 190 if (fb == NULL) {
@@ -554,8 +201,8 @@ int radeonfb_create(struct radeon_device *rdev,
554 201
555 list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list); 202 list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list);
556 203
204 *fb_p = fb;
557 rfb = to_radeon_framebuffer(fb); 205 rfb = to_radeon_framebuffer(fb);
558 *rfb_p = rfb;
559 rdev->fbdev_rfb = rfb; 206 rdev->fbdev_rfb = rfb;
560 rdev->fbdev_robj = robj; 207 rdev->fbdev_robj = robj;
561 208
@@ -564,7 +211,15 @@ int radeonfb_create(struct radeon_device *rdev,
564 ret = -ENOMEM; 211 ret = -ENOMEM;
565 goto out_unref; 212 goto out_unref;
566 } 213 }
214
215 rdev->fbdev_info = info;
567 rfbdev = info->par; 216 rfbdev = info->par;
217 rfbdev->helper.funcs = &radeon_fb_helper_funcs;
218 rfbdev->helper.dev = dev;
219 ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, 2,
220 RADEONFB_CONN_LIMIT);
221 if (ret)
222 goto out_unref;
568 223
569 if (fb_tiled) 224 if (fb_tiled)
570 radeon_object_check_tiling(robj, 0, 0); 225 radeon_object_check_tiling(robj, 0, 0);
@@ -577,33 +232,19 @@ int radeonfb_create(struct radeon_device *rdev,
577 memset_io(fbptr, 0, aligned_size); 232 memset_io(fbptr, 0, aligned_size);
578 233
579 strcpy(info->fix.id, "radeondrmfb"); 234 strcpy(info->fix.id, "radeondrmfb");
580 info->fix.type = FB_TYPE_PACKED_PIXELS; 235
581 info->fix.visual = FB_VISUAL_TRUECOLOR; 236 drm_fb_helper_fill_fix(info, fb->pitch);
582 info->fix.type_aux = 0; 237
583 info->fix.xpanstep = 1; /* doing it in hw */
584 info->fix.ypanstep = 1; /* doing it in hw */
585 info->fix.ywrapstep = 0;
586 info->fix.accel = FB_ACCEL_NONE;
587 info->fix.type_aux = 0;
588 info->flags = FBINFO_DEFAULT; 238 info->flags = FBINFO_DEFAULT;
589 info->fbops = &radeonfb_ops; 239 info->fbops = &radeonfb_ops;
590 info->fix.line_length = fb->pitch; 240
591 tmp = fb_gpuaddr - rdev->mc.vram_location; 241 tmp = fb_gpuaddr - rdev->mc.vram_location;
592 info->fix.smem_start = rdev->mc.aper_base + tmp; 242 info->fix.smem_start = rdev->mc.aper_base + tmp;
593 info->fix.smem_len = size; 243 info->fix.smem_len = size;
594 info->screen_base = fbptr; 244 info->screen_base = fbptr;
595 info->screen_size = size; 245 info->screen_size = size;
596 info->pseudo_palette = fb->pseudo_palette; 246
597 info->var.xres_virtual = fb->width; 247 drm_fb_helper_fill_var(info, fb, fb_width, fb_height);
598 info->var.yres_virtual = fb->height;
599 info->var.bits_per_pixel = fb->bits_per_pixel;
600 info->var.xoffset = 0;
601 info->var.yoffset = 0;
602 info->var.activate = FB_ACTIVATE_NOW;
603 info->var.height = -1;
604 info->var.width = -1;
605 info->var.xres = fb_width;
606 info->var.yres = fb_height;
607 248
608 /* setup aperture base/size for vesafb takeover */ 249 /* setup aperture base/size for vesafb takeover */
609 info->aperture_base = rdev->ddev->mode_config.fb_base; 250 info->aperture_base = rdev->ddev->mode_config.fb_base;
@@ -626,83 +267,6 @@ int radeonfb_create(struct radeon_device *rdev,
626 DRM_INFO("fb depth is %d\n", fb->depth); 267 DRM_INFO("fb depth is %d\n", fb->depth);
627 DRM_INFO(" pitch is %d\n", fb->pitch); 268 DRM_INFO(" pitch is %d\n", fb->pitch);
628 269
629 switch (fb->depth) {
630 case 8:
631 info->var.red.offset = 0;
632 info->var.green.offset = 0;
633 info->var.blue.offset = 0;
634 info->var.red.length = 8; /* 8bit DAC */
635 info->var.green.length = 8;
636 info->var.blue.length = 8;
637 info->var.transp.offset = 0;
638 info->var.transp.length = 0;
639 break;
640#ifdef __LITTLE_ENDIAN
641 case 15:
642 info->var.red.offset = 10;
643 info->var.green.offset = 5;
644 info->var.blue.offset = 0;
645 info->var.red.length = 5;
646 info->var.green.length = 5;
647 info->var.blue.length = 5;
648 info->var.transp.offset = 15;
649 info->var.transp.length = 1;
650 break;
651 case 16:
652 info->var.red.offset = 11;
653 info->var.green.offset = 5;
654 info->var.blue.offset = 0;
655 info->var.red.length = 5;
656 info->var.green.length = 6;
657 info->var.blue.length = 5;
658 info->var.transp.offset = 0;
659 break;
660 case 24:
661 info->var.red.offset = 16;
662 info->var.green.offset = 8;
663 info->var.blue.offset = 0;
664 info->var.red.length = 8;
665 info->var.green.length = 8;
666 info->var.blue.length = 8;
667 info->var.transp.offset = 0;
668 info->var.transp.length = 0;
669 break;
670 case 32:
671 info->var.red.offset = 16;
672 info->var.green.offset = 8;
673 info->var.blue.offset = 0;
674 info->var.red.length = 8;
675 info->var.green.length = 8;
676 info->var.blue.length = 8;
677 info->var.transp.offset = 24;
678 info->var.transp.length = 8;
679 break;
680#else
681 case 24:
682 info->var.red.offset = 8;
683 info->var.green.offset = 16;
684 info->var.blue.offset = 24;
685 info->var.red.length = 8;
686 info->var.green.length = 8;
687 info->var.blue.length = 8;
688 info->var.transp.offset = 0;
689 info->var.transp.length = 0;
690 break;
691 case 32:
692 info->var.red.offset = 8;
693 info->var.green.offset = 16;
694 info->var.blue.offset = 24;
695 info->var.red.length = 8;
696 info->var.green.length = 8;
697 info->var.blue.length = 8;
698 info->var.transp.offset = 0;
699 info->var.transp.length = 8;
700 break;
701 default:
702#endif
703 break;
704 }
705
706 fb->fbdev = info; 270 fb->fbdev = info;
707 rfbdev->rfb = rfb; 271 rfbdev->rfb = rfb;
708 rfbdev->rdev = rdev; 272 rfbdev->rdev = rdev;
@@ -726,145 +290,10 @@ out:
726 return ret; 290 return ret;
727} 291}
728 292
729static int radeonfb_single_fb_probe(struct radeon_device *rdev)
730{
731 struct drm_crtc *crtc;
732 struct drm_connector *connector;
733 unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1;
734 unsigned int surface_width = 0, surface_height = 0;
735 int new_fb = 0;
736 int crtc_count = 0;
737 int ret, i, conn_count = 0;
738 struct radeon_framebuffer *rfb;
739 struct fb_info *info;
740 struct radeon_fb_device *rfbdev;
741 struct drm_mode_set *modeset = NULL;
742
743 /* first up get a count of crtcs now in use and new min/maxes width/heights */
744 list_for_each_entry(crtc, &rdev->ddev->mode_config.crtc_list, head) {
745 if (drm_helper_crtc_in_use(crtc)) {
746 if (crtc->desired_mode) {
747 if (crtc->desired_mode->hdisplay < fb_width)
748 fb_width = crtc->desired_mode->hdisplay;
749
750 if (crtc->desired_mode->vdisplay < fb_height)
751 fb_height = crtc->desired_mode->vdisplay;
752
753 if (crtc->desired_mode->hdisplay > surface_width)
754 surface_width = crtc->desired_mode->hdisplay;
755
756 if (crtc->desired_mode->vdisplay > surface_height)
757 surface_height = crtc->desired_mode->vdisplay;
758 }
759 crtc_count++;
760 }
761 }
762
763 if (crtc_count == 0 || fb_width == -1 || fb_height == -1) {
764 /* hmm everyone went away - assume VGA cable just fell out
765 and will come back later. */
766 return 0;
767 }
768
769 /* do we have an fb already? */
770 if (list_empty(&rdev->ddev->mode_config.fb_kernel_list)) {
771 /* create an fb if we don't have one */
772 ret = radeonfb_create(rdev, fb_width, fb_height, surface_width, surface_height, &rfb);
773 if (ret) {
774 return -EINVAL;
775 }
776 new_fb = 1;
777 } else {
778 struct drm_framebuffer *fb;
779 fb = list_first_entry(&rdev->ddev->mode_config.fb_kernel_list, struct drm_framebuffer, filp_head);
780 rfb = to_radeon_framebuffer(fb);
781
782 /* if someone hotplugs something bigger than we have already allocated, we are pwned.
783 As really we can't resize an fbdev that is in the wild currently due to fbdev
784 not really being designed for the lower layers moving stuff around under it.
785 - so in the grand style of things - punt. */
786 if ((fb->width < surface_width) || (fb->height < surface_height)) {
787 DRM_ERROR("Framebuffer not large enough to scale console onto.\n");
788 return -EINVAL;
789 }
790 }
791
792 info = rfb->base.fbdev;
793 rdev->fbdev_info = info;
794 rfbdev = info->par;
795
796 crtc_count = 0;
797 /* okay we need to setup new connector sets in the crtcs */
798 list_for_each_entry(crtc, &rdev->ddev->mode_config.crtc_list, head) {
799 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
800 modeset = &radeon_crtc->mode_set;
801 modeset->fb = &rfb->base;
802 conn_count = 0;
803 list_for_each_entry(connector, &rdev->ddev->mode_config.connector_list, head) {
804 if (connector->encoder)
805 if (connector->encoder->crtc == modeset->crtc) {
806 modeset->connectors[conn_count] = connector;
807 conn_count++;
808 if (conn_count > RADEONFB_CONN_LIMIT)
809 BUG();
810 }
811 }
812
813 for (i = conn_count; i < RADEONFB_CONN_LIMIT; i++)
814 modeset->connectors[i] = NULL;
815
816
817 rfbdev->crtc_ids[crtc_count++] = crtc->base.id;
818
819 modeset->num_connectors = conn_count;
820 if (modeset->crtc->desired_mode) {
821 if (modeset->mode) {
822 drm_mode_destroy(rdev->ddev, modeset->mode);
823 }
824 modeset->mode = drm_mode_duplicate(rdev->ddev,
825 modeset->crtc->desired_mode);
826 }
827 }
828 rfbdev->crtc_count = crtc_count;
829
830 if (new_fb) {
831 info->var.pixclock = -1;
832 if (register_framebuffer(info) < 0)
833 return -EINVAL;
834 } else {
835 radeonfb_set_par(info);
836 }
837 printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
838 info->fix.id);
839
840 /* Switch back to kernel console on panic */
841 panic_mode = *modeset;
842 atomic_notifier_chain_register(&panic_notifier_list, &paniced);
843 printk(KERN_INFO "registered panic notifier\n");
844
845 return 0;
846}
847
848int radeonfb_probe(struct drm_device *dev) 293int radeonfb_probe(struct drm_device *dev)
849{ 294{
850 int ret; 295 int ret;
851 296 ret = drm_fb_helper_single_fb_probe(dev, &radeonfb_create);
852 /* something has changed in the lower levels of hell - deal with it
853 here */
854
855 /* two modes : a) 1 fb to rule all crtcs.
856 b) one fb per crtc.
857 two actions 1) new connected device
858 2) device removed.
859 case a/1 : if the fb surface isn't big enough - resize the surface fb.
860 if the fb size isn't big enough - resize fb into surface.
861 if everything big enough configure the new crtc/etc.
862 case a/2 : undo the configuration
863 possibly resize down the fb to fit the new configuration.
864 case b/1 : see if it is on a new crtc - setup a new fb and add it.
865 case b/2 : teardown the new fb.
866 */
867 ret = radeonfb_single_fb_probe(dev->dev_private);
868 return ret; 297 return ret;
869} 298}
870EXPORT_SYMBOL(radeonfb_probe); 299EXPORT_SYMBOL(radeonfb_probe);
@@ -880,16 +309,17 @@ int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb)
880 } 309 }
881 info = fb->fbdev; 310 info = fb->fbdev;
882 if (info) { 311 if (info) {
312 struct radeon_fb_device *rfbdev = info->par;
883 robj = rfb->obj->driver_private; 313 robj = rfb->obj->driver_private;
884 unregister_framebuffer(info); 314 unregister_framebuffer(info);
885 radeon_object_kunmap(robj); 315 radeon_object_kunmap(robj);
886 radeon_object_unpin(robj); 316 radeon_object_unpin(robj);
317 drm_fb_helper_free(&rfbdev->helper);
887 framebuffer_release(info); 318 framebuffer_release(info);
888 } 319 }
889 320
890 printk(KERN_INFO "unregistered panic notifier\n"); 321 printk(KERN_INFO "unregistered panic notifier\n");
891 atomic_notifier_chain_unregister(&panic_notifier_list, &paniced); 322
892 memset(&panic_mode, 0, sizeof(struct drm_mode_set));
893 return 0; 323 return 0;
894} 324}
895EXPORT_SYMBOL(radeonfb_remove); 325EXPORT_SYMBOL(radeonfb_remove);
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index b4e48dd2e859..3beb26d74719 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -53,9 +53,9 @@ int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
53 * away 53 * away
54 */ 54 */
55 WREG32(rdev->fence_drv.scratch_reg, fence->seq); 55 WREG32(rdev->fence_drv.scratch_reg, fence->seq);
56 } else { 56 } else
57 radeon_fence_ring_emit(rdev, fence); 57 radeon_fence_ring_emit(rdev, fence);
58 } 58
59 fence->emited = true; 59 fence->emited = true;
60 fence->timeout = jiffies + ((2000 * HZ) / 1000); 60 fence->timeout = jiffies + ((2000 * HZ) / 1000);
61 list_del(&fence->list); 61 list_del(&fence->list);
@@ -168,7 +168,38 @@ bool radeon_fence_signaled(struct radeon_fence *fence)
168 return signaled; 168 return signaled;
169} 169}
170 170
171int radeon_fence_wait(struct radeon_fence *fence, bool interruptible) 171int r600_fence_wait(struct radeon_fence *fence, bool intr, bool lazy)
172{
173 struct radeon_device *rdev;
174 int ret = 0;
175
176 rdev = fence->rdev;
177
178 __set_current_state(intr ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
179
180 while (1) {
181 if (radeon_fence_signaled(fence))
182 break;
183
184 if (time_after_eq(jiffies, fence->timeout)) {
185 ret = -EBUSY;
186 break;
187 }
188
189 if (lazy)
190 schedule_timeout(1);
191
192 if (intr && signal_pending(current)) {
193 ret = -ERESTARTSYS;
194 break;
195 }
196 }
197 __set_current_state(TASK_RUNNING);
198 return ret;
199}
200
201
202int radeon_fence_wait(struct radeon_fence *fence, bool intr)
172{ 203{
173 struct radeon_device *rdev; 204 struct radeon_device *rdev;
174 unsigned long cur_jiffies; 205 unsigned long cur_jiffies;
@@ -176,7 +207,6 @@ int radeon_fence_wait(struct radeon_fence *fence, bool interruptible)
176 bool expired = false; 207 bool expired = false;
177 int r; 208 int r;
178 209
179
180 if (fence == NULL) { 210 if (fence == NULL) {
181 WARN(1, "Querying an invalid fence : %p !\n", fence); 211 WARN(1, "Querying an invalid fence : %p !\n", fence);
182 return 0; 212 return 0;
@@ -185,13 +215,22 @@ int radeon_fence_wait(struct radeon_fence *fence, bool interruptible)
185 if (radeon_fence_signaled(fence)) { 215 if (radeon_fence_signaled(fence)) {
186 return 0; 216 return 0;
187 } 217 }
218
219 if (rdev->family >= CHIP_R600) {
220 r = r600_fence_wait(fence, intr, 0);
221 if (r == -ERESTARTSYS)
222 return -EBUSY;
223 return r;
224 }
225
188retry: 226retry:
189 cur_jiffies = jiffies; 227 cur_jiffies = jiffies;
190 timeout = HZ / 100; 228 timeout = HZ / 100;
191 if (time_after(fence->timeout, cur_jiffies)) { 229 if (time_after(fence->timeout, cur_jiffies)) {
192 timeout = fence->timeout - cur_jiffies; 230 timeout = fence->timeout - cur_jiffies;
193 } 231 }
194 if (interruptible) { 232
233 if (intr) {
195 r = wait_event_interruptible_timeout(rdev->fence_drv.queue, 234 r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
196 radeon_fence_signaled(fence), timeout); 235 radeon_fence_signaled(fence), timeout);
197 if (unlikely(r == -ERESTARTSYS)) { 236 if (unlikely(r == -ERESTARTSYS)) {
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index 2977539880fb..a931af065dd4 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -75,7 +75,6 @@ void radeon_gart_table_ram_free(struct radeon_device *rdev)
75 75
76int radeon_gart_table_vram_alloc(struct radeon_device *rdev) 76int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
77{ 77{
78 uint64_t gpu_addr;
79 int r; 78 int r;
80 79
81 if (rdev->gart.table.vram.robj == NULL) { 80 if (rdev->gart.table.vram.robj == NULL) {
@@ -88,6 +87,14 @@ int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
88 return r; 87 return r;
89 } 88 }
90 } 89 }
90 return 0;
91}
92
93int radeon_gart_table_vram_pin(struct radeon_device *rdev)
94{
95 uint64_t gpu_addr;
96 int r;
97
91 r = radeon_object_pin(rdev->gart.table.vram.robj, 98 r = radeon_object_pin(rdev->gart.table.vram.robj,
92 RADEON_GEM_DOMAIN_VRAM, &gpu_addr); 99 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
93 if (r) { 100 if (r) {
diff --git a/drivers/gpu/drm/radeon/radeon_ioc32.c b/drivers/gpu/drm/radeon/radeon_ioc32.c
index 56decda2a71f..a1bf11de308a 100644
--- a/drivers/gpu/drm/radeon/radeon_ioc32.c
+++ b/drivers/gpu/drm/radeon/radeon_ioc32.c
@@ -422,3 +422,18 @@ long radeon_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
422 422
423 return ret; 423 return ret;
424} 424}
425
426long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
427{
428 unsigned int nr = DRM_IOCTL_NR(cmd);
429 int ret;
430
431 if (nr < DRM_COMMAND_BASE)
432 return drm_compat_ioctl(filp, cmd, arg);
433
434 lock_kernel(); /* XXX for now */
435 ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg);
436 unlock_kernel();
437
438 return ret;
439}
diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c
index 9836c705a952..b79ecc4a7cc4 100644
--- a/drivers/gpu/drm/radeon/radeon_irq.c
+++ b/drivers/gpu/drm/radeon/radeon_irq.c
@@ -188,6 +188,9 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
188 u32 stat; 188 u32 stat;
189 u32 r500_disp_int; 189 u32 r500_disp_int;
190 190
191 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
192 return IRQ_NONE;
193
191 /* Only consider the bits we're interested in - others could be used 194 /* Only consider the bits we're interested in - others could be used
192 * outside the DRM 195 * outside the DRM
193 */ 196 */
@@ -286,6 +289,9 @@ int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_pr
286 drm_radeon_irq_emit_t *emit = data; 289 drm_radeon_irq_emit_t *emit = data;
287 int result; 290 int result;
288 291
292 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
293 return -EINVAL;
294
289 LOCK_TEST_WITH_RETURN(dev, file_priv); 295 LOCK_TEST_WITH_RETURN(dev, file_priv);
290 296
291 if (!dev_priv) { 297 if (!dev_priv) {
@@ -315,6 +321,9 @@ int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_pr
315 return -EINVAL; 321 return -EINVAL;
316 } 322 }
317 323
324 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
325 return -EINVAL;
326
318 return radeon_wait_irq(dev, irqwait->irq_seq); 327 return radeon_wait_irq(dev, irqwait->irq_seq);
319} 328}
320 329
@@ -326,6 +335,9 @@ void radeon_driver_irq_preinstall(struct drm_device * dev)
326 (drm_radeon_private_t *) dev->dev_private; 335 (drm_radeon_private_t *) dev->dev_private;
327 u32 dummy; 336 u32 dummy;
328 337
338 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
339 return;
340
329 /* Disable *all* interrupts */ 341 /* Disable *all* interrupts */
330 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 342 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
331 RADEON_WRITE(R500_DxMODE_INT_MASK, 0); 343 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
@@ -345,6 +357,9 @@ int radeon_driver_irq_postinstall(struct drm_device *dev)
345 357
346 dev->max_vblank_count = 0x001fffff; 358 dev->max_vblank_count = 0x001fffff;
347 359
360 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
361 return 0;
362
348 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); 363 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
349 364
350 return 0; 365 return 0;
@@ -357,6 +372,9 @@ void radeon_driver_irq_uninstall(struct drm_device * dev)
357 if (!dev_priv) 372 if (!dev_priv)
358 return; 373 return;
359 374
375 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
376 return;
377
360 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 378 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
361 RADEON_WRITE(R500_DxMODE_INT_MASK, 0); 379 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
362 /* Disable *all* interrupts */ 380 /* Disable *all* interrupts */
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 9805e4b6ca1b..1841145a7c4f 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -28,7 +28,6 @@
28#include "drmP.h" 28#include "drmP.h"
29#include "radeon_drm.h" 29#include "radeon_drm.h"
30#include "radeon_reg.h" 30#include "radeon_reg.h"
31#include "radeon_microcode.h"
32#include "radeon.h" 31#include "radeon.h"
33#include "atom.h" 32#include "atom.h"
34 33
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index dce09ada32bc..709bd892b3a9 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -54,12 +54,23 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
54 flags |= RADEON_IS_PCI; 54 flags |= RADEON_IS_PCI;
55 } 55 }
56 56
57 /* radeon_device_init should report only fatal error
58 * like memory allocation failure or iomapping failure,
59 * or memory manager initialization failure, it must
60 * properly initialize the GPU MC controller and permit
61 * VRAM allocation
62 */
57 r = radeon_device_init(rdev, dev, dev->pdev, flags); 63 r = radeon_device_init(rdev, dev, dev->pdev, flags);
58 if (r) { 64 if (r) {
59 DRM_ERROR("Failed to initialize radeon, disabling IOCTL\n"); 65 DRM_ERROR("Fatal error while trying to initialize radeon.\n");
60 radeon_device_fini(rdev); 66 return r;
61 kfree(rdev); 67 }
62 dev->dev_private = NULL; 68 /* Again modeset_init should fail only on fatal error
69 * otherwise it should provide enough functionalities
70 * for shadowfb to run
71 */
72 r = radeon_modeset_init(rdev);
73 if (r) {
63 return r; 74 return r;
64 } 75 }
65 return 0; 76 return 0;
@@ -69,6 +80,9 @@ int radeon_driver_unload_kms(struct drm_device *dev)
69{ 80{
70 struct radeon_device *rdev = dev->dev_private; 81 struct radeon_device *rdev = dev->dev_private;
71 82
83 if (rdev == NULL)
84 return 0;
85 radeon_modeset_fini(rdev);
72 radeon_device_fini(rdev); 86 radeon_device_fini(rdev);
73 kfree(rdev); 87 kfree(rdev);
74 dev->dev_private = NULL; 88 dev->dev_private = NULL;
@@ -98,6 +112,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
98 case RADEON_INFO_NUM_Z_PIPES: 112 case RADEON_INFO_NUM_Z_PIPES:
99 value = rdev->num_z_pipes; 113 value = rdev->num_z_pipes;
100 break; 114 break;
115 case RADEON_INFO_ACCEL_WORKING:
116 value = rdev->accel_working;
117 break;
101 default: 118 default:
102 DRM_DEBUG("Invalid request %d\n", info->request); 119 DRM_DEBUG("Invalid request %d\n", info->request);
103 return -EINVAL; 120 return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 0da72f18fd3a..2b997a15fb1f 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -28,6 +28,7 @@
28#include <drm/radeon_drm.h> 28#include <drm/radeon_drm.h>
29#include "radeon_fixed.h" 29#include "radeon_fixed.h"
30#include "radeon.h" 30#include "radeon.h"
31#include "atom.h"
31 32
32static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, 33static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
33 struct drm_display_mode *mode, 34 struct drm_display_mode *mode,
@@ -340,6 +341,9 @@ void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
340 uint32_t crtc_pitch; 341 uint32_t crtc_pitch;
341 342
342 switch (crtc->fb->bits_per_pixel) { 343 switch (crtc->fb->bits_per_pixel) {
344 case 8:
345 format = 2;
346 break;
343 case 15: /* 555 */ 347 case 15: /* 555 */
344 format = 3; 348 format = 3;
345 break; 349 break;
@@ -400,11 +404,33 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
400 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; 404 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
401 uint32_t crtc_pitch, pitch_pixels; 405 uint32_t crtc_pitch, pitch_pixels;
402 uint32_t tiling_flags; 406 uint32_t tiling_flags;
407 int format;
408 uint32_t gen_cntl_reg, gen_cntl_val;
403 409
404 DRM_DEBUG("\n"); 410 DRM_DEBUG("\n");
405 411
406 radeon_fb = to_radeon_framebuffer(crtc->fb); 412 radeon_fb = to_radeon_framebuffer(crtc->fb);
407 413
414 switch (crtc->fb->bits_per_pixel) {
415 case 8:
416 format = 2;
417 break;
418 case 15: /* 555 */
419 format = 3;
420 break;
421 case 16: /* 565 */
422 format = 4;
423 break;
424 case 24: /* RGB */
425 format = 5;
426 break;
427 case 32: /* xRGB */
428 format = 6;
429 break;
430 default:
431 return false;
432 }
433
408 obj = radeon_fb->obj; 434 obj = radeon_fb->obj;
409 if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) { 435 if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
410 return -EINVAL; 436 return -EINVAL;
@@ -457,6 +483,9 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
457 } else { 483 } else {
458 int offset = y * pitch_pixels + x; 484 int offset = y * pitch_pixels + x;
459 switch (crtc->fb->bits_per_pixel) { 485 switch (crtc->fb->bits_per_pixel) {
486 case 8:
487 offset *= 1;
488 break;
460 case 15: 489 case 15:
461 case 16: 490 case 16:
462 offset *= 2; 491 offset *= 2;
@@ -475,6 +504,16 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
475 504
476 base &= ~7; 505 base &= ~7;
477 506
507 if (radeon_crtc->crtc_id == 1)
508 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
509 else
510 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
511
512 gen_cntl_val = RREG32(gen_cntl_reg);
513 gen_cntl_val &= ~(0xf << 8);
514 gen_cntl_val |= (format << 8);
515 WREG32(gen_cntl_reg, gen_cntl_val);
516
478 crtc_offset = (u32)base; 517 crtc_offset = (u32)base;
479 518
480 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); 519 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
@@ -501,6 +540,7 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
501 struct drm_device *dev = crtc->dev; 540 struct drm_device *dev = crtc->dev;
502 struct radeon_device *rdev = dev->dev_private; 541 struct radeon_device *rdev = dev->dev_private;
503 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 542 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
543 struct drm_encoder *encoder;
504 int format; 544 int format;
505 int hsync_start; 545 int hsync_start;
506 int hsync_wid; 546 int hsync_wid;
@@ -509,10 +549,24 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
509 uint32_t crtc_h_sync_strt_wid; 549 uint32_t crtc_h_sync_strt_wid;
510 uint32_t crtc_v_total_disp; 550 uint32_t crtc_v_total_disp;
511 uint32_t crtc_v_sync_strt_wid; 551 uint32_t crtc_v_sync_strt_wid;
552 bool is_tv = false;
512 553
513 DRM_DEBUG("\n"); 554 DRM_DEBUG("\n");
555 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
556 if (encoder->crtc == crtc) {
557 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
558 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
559 is_tv = true;
560 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
561 break;
562 }
563 }
564 }
514 565
515 switch (crtc->fb->bits_per_pixel) { 566 switch (crtc->fb->bits_per_pixel) {
567 case 8:
568 format = 2;
569 break;
516 case 15: /* 555 */ 570 case 15: /* 555 */
517 format = 3; 571 format = 3;
518 break; 572 break;
@@ -642,6 +696,11 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
642 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 696 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
643 } 697 }
644 698
699 if (is_tv)
700 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
701 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
702 &crtc_v_sync_strt_wid);
703
645 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); 704 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
646 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); 705 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
647 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); 706 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
@@ -668,7 +727,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
668 uint32_t pll_ref_div = 0; 727 uint32_t pll_ref_div = 0;
669 uint32_t pll_fb_post_div = 0; 728 uint32_t pll_fb_post_div = 0;
670 uint32_t htotal_cntl = 0; 729 uint32_t htotal_cntl = 0;
671 730 bool is_tv = false;
672 struct radeon_pll *pll; 731 struct radeon_pll *pll;
673 732
674 struct { 733 struct {
@@ -703,6 +762,13 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
703 762
704 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 763 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
705 if (encoder->crtc == crtc) { 764 if (encoder->crtc == crtc) {
765 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
766
767 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
768 is_tv = true;
769 break;
770 }
771
706 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 772 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
707 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 773 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
708 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { 774 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
@@ -766,6 +832,12 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
766 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | 832 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
767 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); 833 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
768 834
835 if (is_tv) {
836 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
837 &pll_ref_div, &pll_fb_post_div,
838 &pixclks_cntl);
839 }
840
769 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 841 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
770 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 842 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
771 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 843 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
@@ -820,6 +892,15 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
820 892
821 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 893 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
822 } else { 894 } else {
895 uint32_t pixclks_cntl;
896
897
898 if (is_tv) {
899 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
900 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
901 &pll_fb_post_div, &pixclks_cntl);
902 }
903
823 if (rdev->flags & RADEON_IS_MOBILITY) { 904 if (rdev->flags & RADEON_IS_MOBILITY) {
824 /* A temporal workaround for the occational blanking on certain laptop panels. 905 /* A temporal workaround for the occational blanking on certain laptop panels.
825 This appears to related to the PLL divider registers (fail to lock?). 906 This appears to related to the PLL divider registers (fail to lock?).
@@ -914,6 +995,8 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
914 RADEON_VCLK_SRC_SEL_PPLLCLK, 995 RADEON_VCLK_SRC_SEL_PPLLCLK,
915 ~(RADEON_VCLK_SRC_SEL_MASK)); 996 ~(RADEON_VCLK_SRC_SEL_MASK));
916 997
998 if (is_tv)
999 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
917 } 1000 }
918} 1001}
919 1002
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 9322675ef6d0..b1547f700d73 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -29,6 +29,15 @@
29#include "radeon.h" 29#include "radeon.h"
30#include "atom.h" 30#include "atom.h"
31 31
32static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
33{
34 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
35 struct drm_encoder_helper_funcs *encoder_funcs;
36
37 encoder_funcs = encoder->helper_private;
38 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
39 radeon_encoder->active_device = 0;
40}
32 41
33static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) 42static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
34{ 43{
@@ -98,6 +107,8 @@ static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
98 else 107 else
99 radeon_combios_output_lock(encoder, true); 108 radeon_combios_output_lock(encoder, true);
100 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF); 109 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
110
111 radeon_encoder_set_active_device(encoder);
101} 112}
102 113
103static void radeon_legacy_lvds_commit(struct drm_encoder *encoder) 114static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
@@ -195,6 +206,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
195 .prepare = radeon_legacy_lvds_prepare, 206 .prepare = radeon_legacy_lvds_prepare,
196 .mode_set = radeon_legacy_lvds_mode_set, 207 .mode_set = radeon_legacy_lvds_mode_set,
197 .commit = radeon_legacy_lvds_commit, 208 .commit = radeon_legacy_lvds_commit,
209 .disable = radeon_legacy_encoder_disable,
198}; 210};
199 211
200 212
@@ -260,6 +272,7 @@ static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
260 else 272 else
261 radeon_combios_output_lock(encoder, true); 273 radeon_combios_output_lock(encoder, true);
262 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF); 274 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
275 radeon_encoder_set_active_device(encoder);
263} 276}
264 277
265static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder) 278static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
@@ -402,6 +415,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_fu
402 .mode_set = radeon_legacy_primary_dac_mode_set, 415 .mode_set = radeon_legacy_primary_dac_mode_set,
403 .commit = radeon_legacy_primary_dac_commit, 416 .commit = radeon_legacy_primary_dac_commit,
404 .detect = radeon_legacy_primary_dac_detect, 417 .detect = radeon_legacy_primary_dac_detect,
418 .disable = radeon_legacy_encoder_disable,
405}; 419};
406 420
407 421
@@ -454,6 +468,7 @@ static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
454 else 468 else
455 radeon_combios_output_lock(encoder, true); 469 radeon_combios_output_lock(encoder, true);
456 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF); 470 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
471 radeon_encoder_set_active_device(encoder);
457} 472}
458 473
459static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder) 474static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
@@ -566,6 +581,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs
566 .prepare = radeon_legacy_tmds_int_prepare, 581 .prepare = radeon_legacy_tmds_int_prepare,
567 .mode_set = radeon_legacy_tmds_int_mode_set, 582 .mode_set = radeon_legacy_tmds_int_mode_set,
568 .commit = radeon_legacy_tmds_int_commit, 583 .commit = radeon_legacy_tmds_int_commit,
584 .disable = radeon_legacy_encoder_disable,
569}; 585};
570 586
571 587
@@ -620,6 +636,7 @@ static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
620 else 636 else
621 radeon_combios_output_lock(encoder, true); 637 radeon_combios_output_lock(encoder, true);
622 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF); 638 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
639 radeon_encoder_set_active_device(encoder);
623} 640}
624 641
625static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder) 642static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
@@ -706,6 +723,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs
706 .prepare = radeon_legacy_tmds_ext_prepare, 723 .prepare = radeon_legacy_tmds_ext_prepare,
707 .mode_set = radeon_legacy_tmds_ext_mode_set, 724 .mode_set = radeon_legacy_tmds_ext_mode_set,
708 .commit = radeon_legacy_tmds_ext_commit, 725 .commit = radeon_legacy_tmds_ext_commit,
726 .disable = radeon_legacy_encoder_disable,
709}; 727};
710 728
711 729
@@ -727,17 +745,21 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
727{ 745{
728 struct drm_device *dev = encoder->dev; 746 struct drm_device *dev = encoder->dev;
729 struct radeon_device *rdev = dev->dev_private; 747 struct radeon_device *rdev = dev->dev_private;
748 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
730 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; 749 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
731 /* uint32_t tv_master_cntl = 0; */ 750 uint32_t tv_master_cntl = 0;
732 751 bool is_tv;
733 DRM_DEBUG("\n"); 752 DRM_DEBUG("\n");
734 753
754 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
755
735 if (rdev->family == CHIP_R200) 756 if (rdev->family == CHIP_R200)
736 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 757 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
737 else { 758 else {
738 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 759 if (is_tv)
739 /* FIXME TV */ 760 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
740 /* tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); */ 761 else
762 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
741 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 763 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
742 } 764 }
743 765
@@ -746,20 +768,23 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
746 if (rdev->family == CHIP_R200) { 768 if (rdev->family == CHIP_R200) {
747 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); 769 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
748 } else { 770 } else {
749 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; 771 if (is_tv)
750 /* tv_master_cntl |= RADEON_TV_ON; */ 772 tv_master_cntl |= RADEON_TV_ON;
773 else
774 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
775
751 if (rdev->family == CHIP_R420 || 776 if (rdev->family == CHIP_R420 ||
752 rdev->family == CHIP_R423 || 777 rdev->family == CHIP_R423 ||
753 rdev->family == CHIP_RV410) 778 rdev->family == CHIP_RV410)
754 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD | 779 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
755 R420_TV_DAC_GDACPD | 780 R420_TV_DAC_GDACPD |
756 R420_TV_DAC_BDACPD | 781 R420_TV_DAC_BDACPD |
757 RADEON_TV_DAC_BGSLEEP); 782 RADEON_TV_DAC_BGSLEEP);
758 else 783 else
759 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | 784 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
760 RADEON_TV_DAC_GDACPD | 785 RADEON_TV_DAC_GDACPD |
761 RADEON_TV_DAC_BDACPD | 786 RADEON_TV_DAC_BDACPD |
762 RADEON_TV_DAC_BGSLEEP); 787 RADEON_TV_DAC_BGSLEEP);
763 } 788 }
764 break; 789 break;
765 case DRM_MODE_DPMS_STANDBY: 790 case DRM_MODE_DPMS_STANDBY:
@@ -768,8 +793,11 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
768 if (rdev->family == CHIP_R200) 793 if (rdev->family == CHIP_R200)
769 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); 794 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
770 else { 795 else {
771 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; 796 if (is_tv)
772 /* tv_master_cntl &= ~RADEON_TV_ON; */ 797 tv_master_cntl &= ~RADEON_TV_ON;
798 else
799 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
800
773 if (rdev->family == CHIP_R420 || 801 if (rdev->family == CHIP_R420 ||
774 rdev->family == CHIP_R423 || 802 rdev->family == CHIP_R423 ||
775 rdev->family == CHIP_RV410) 803 rdev->family == CHIP_RV410)
@@ -789,8 +817,10 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
789 if (rdev->family == CHIP_R200) { 817 if (rdev->family == CHIP_R200) {
790 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 818 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
791 } else { 819 } else {
792 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 820 if (is_tv)
793 /* WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); */ 821 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
822 else
823 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
794 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 824 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
795 } 825 }
796 826
@@ -809,6 +839,7 @@ static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
809 else 839 else
810 radeon_combios_output_lock(encoder, true); 840 radeon_combios_output_lock(encoder, true);
811 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF); 841 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
842 radeon_encoder_set_active_device(encoder);
812} 843}
813 844
814static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder) 845static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
@@ -831,11 +862,15 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
831 struct radeon_device *rdev = dev->dev_private; 862 struct radeon_device *rdev = dev->dev_private;
832 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 863 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
833 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 864 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
865 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
834 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0; 866 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
835 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0; 867 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
868 bool is_tv = false;
836 869
837 DRM_DEBUG("\n"); 870 DRM_DEBUG("\n");
838 871
872 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
873
839 if (rdev->family != CHIP_R200) { 874 if (rdev->family != CHIP_R200) {
840 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 875 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
841 if (rdev->family == CHIP_R420 || 876 if (rdev->family == CHIP_R420 ||
@@ -858,7 +893,7 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
858 } 893 }
859 894
860 /* FIXME TV */ 895 /* FIXME TV */
861 if (radeon_encoder->enc_priv) { 896 if (tv_dac) {
862 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 897 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
863 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 898 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
864 RADEON_TV_DAC_NHOLD | 899 RADEON_TV_DAC_NHOLD |
@@ -875,44 +910,93 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
875 if (ASIC_IS_R300(rdev)) { 910 if (ASIC_IS_R300(rdev)) {
876 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1; 911 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
877 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 912 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
878 } else if (rdev->family == CHIP_R200) 913 }
879 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 914
915 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev))
916 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
880 else 917 else
881 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 918 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
882 919
883 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; 920 if (rdev->family == CHIP_R200)
921 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
884 922
885 if (radeon_crtc->crtc_id == 0) { 923 if (is_tv) {
886 if (ASIC_IS_R300(rdev)) { 924 uint32_t dac_cntl;
887 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 925
888 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; 926 dac_cntl = RREG32(RADEON_DAC_CNTL);
889 } else if (rdev->family == CHIP_R200) { 927 dac_cntl &= ~RADEON_DAC_TVO_EN;
890 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | 928 WREG32(RADEON_DAC_CNTL, dac_cntl);
891 RADEON_FP2_DVO_RATE_SEL_SDR); 929
892 } else 930 if (ASIC_IS_R300(rdev))
893 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 931 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
932
933 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
934 if (radeon_crtc->crtc_id == 0) {
935 if (ASIC_IS_R300(rdev)) {
936 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
937 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
938 RADEON_DISP_TV_SOURCE_CRTC);
939 }
940 if (rdev->family >= CHIP_R200) {
941 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
942 } else {
943 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
944 }
945 } else {
946 if (ASIC_IS_R300(rdev)) {
947 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
948 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
949 }
950 if (rdev->family >= CHIP_R200) {
951 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
952 } else {
953 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
954 }
955 }
956 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
894 } else { 957 } else {
895 if (ASIC_IS_R300(rdev)) {
896 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
897 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
898 } else if (rdev->family == CHIP_R200) {
899 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
900 RADEON_FP2_DVO_RATE_SEL_SDR);
901 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
902 } else
903 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
904 }
905 958
906 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 959 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
960
961 if (radeon_crtc->crtc_id == 0) {
962 if (ASIC_IS_R300(rdev)) {
963 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
964 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
965 } else if (rdev->family == CHIP_R200) {
966 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
967 RADEON_FP2_DVO_RATE_SEL_SDR);
968 } else
969 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
970 } else {
971 if (ASIC_IS_R300(rdev)) {
972 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
973 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
974 } else if (rdev->family == CHIP_R200) {
975 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
976 RADEON_FP2_DVO_RATE_SEL_SDR);
977 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
978 } else
979 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
980 }
981 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
982 }
907 983
908 if (ASIC_IS_R300(rdev)) { 984 if (ASIC_IS_R300(rdev)) {
909 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 985 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
910 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_output_cntl); 986 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
911 } else if (rdev->family == CHIP_R200) 987 }
912 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 988
989 if (rdev->family >= CHIP_R200)
990 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
913 else 991 else
914 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 992 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
915 993
994 if (rdev->family == CHIP_R200)
995 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
996
997 if (is_tv)
998 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
999
916 if (rdev->is_atom_bios) 1000 if (rdev->is_atom_bios)
917 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1001 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
918 else 1002 else
@@ -920,6 +1004,141 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
920 1004
921} 1005}
922 1006
1007static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1008 struct drm_connector *connector)
1009{
1010 struct drm_device *dev = encoder->dev;
1011 struct radeon_device *rdev = dev->dev_private;
1012 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1013 uint32_t disp_output_cntl, gpiopad_a, tmp;
1014 bool found = false;
1015
1016 /* save regs needed */
1017 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1018 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1019 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1020 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1021 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1022 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1023
1024 WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1025
1026 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1027
1028 WREG32(RADEON_CRTC2_GEN_CNTL,
1029 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1030
1031 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1032 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1033 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1034
1035 WREG32(RADEON_DAC_EXT_CNTL,
1036 RADEON_DAC2_FORCE_BLANK_OFF_EN |
1037 RADEON_DAC2_FORCE_DATA_EN |
1038 RADEON_DAC_FORCE_DATA_SEL_RGB |
1039 (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1040
1041 WREG32(RADEON_TV_DAC_CNTL,
1042 RADEON_TV_DAC_STD_NTSC |
1043 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1044 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1045
1046 RREG32(RADEON_TV_DAC_CNTL);
1047 mdelay(4);
1048
1049 WREG32(RADEON_TV_DAC_CNTL,
1050 RADEON_TV_DAC_NBLANK |
1051 RADEON_TV_DAC_NHOLD |
1052 RADEON_TV_MONITOR_DETECT_EN |
1053 RADEON_TV_DAC_STD_NTSC |
1054 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1055 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1056
1057 RREG32(RADEON_TV_DAC_CNTL);
1058 mdelay(6);
1059
1060 tmp = RREG32(RADEON_TV_DAC_CNTL);
1061 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1062 found = true;
1063 DRM_DEBUG("S-video TV connection detected\n");
1064 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1065 found = true;
1066 DRM_DEBUG("Composite TV connection detected\n");
1067 }
1068
1069 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1070 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1071 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1072 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1073 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1074 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1075 return found;
1076}
1077
1078static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1079 struct drm_connector *connector)
1080{
1081 struct drm_device *dev = encoder->dev;
1082 struct radeon_device *rdev = dev->dev_private;
1083 uint32_t tv_dac_cntl, dac_cntl2;
1084 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1085 bool found = false;
1086
1087 if (ASIC_IS_R300(rdev))
1088 return r300_legacy_tv_detect(encoder, connector);
1089
1090 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1091 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1092 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1093 config_cntl = RREG32(RADEON_CONFIG_CNTL);
1094 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1095
1096 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1097 WREG32(RADEON_DAC_CNTL2, tmp);
1098
1099 tmp = tv_master_cntl | RADEON_TV_ON;
1100 tmp &= ~(RADEON_TV_ASYNC_RST |
1101 RADEON_RESTART_PHASE_FIX |
1102 RADEON_CRT_FIFO_CE_EN |
1103 RADEON_TV_FIFO_CE_EN |
1104 RADEON_RE_SYNC_NOW_SEL_MASK);
1105 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1106 WREG32(RADEON_TV_MASTER_CNTL, tmp);
1107
1108 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1109 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1110 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1111
1112 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1113 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1114 else
1115 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1116 WREG32(RADEON_TV_DAC_CNTL, tmp);
1117
1118 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1119 RADEON_RED_MX_FORCE_DAC_DATA |
1120 RADEON_GRN_MX_FORCE_DAC_DATA |
1121 RADEON_BLU_MX_FORCE_DAC_DATA |
1122 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1123 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1124
1125 mdelay(3);
1126 tmp = RREG32(RADEON_TV_DAC_CNTL);
1127 if (tmp & RADEON_TV_DAC_GDACDET) {
1128 found = true;
1129 DRM_DEBUG("S-video TV connection detected\n");
1130 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1131 found = true;
1132 DRM_DEBUG("Composite TV connection detected\n");
1133 }
1134
1135 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1136 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1137 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1138 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1139 return found;
1140}
1141
923static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, 1142static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
924 struct drm_connector *connector) 1143 struct drm_connector *connector)
925{ 1144{
@@ -928,9 +1147,29 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder
928 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; 1147 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
929 uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; 1148 uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
930 enum drm_connector_status found = connector_status_disconnected; 1149 enum drm_connector_status found = connector_status_disconnected;
1150 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1151 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
931 bool color = true; 1152 bool color = true;
932 1153
933 /* FIXME tv */ 1154 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1155 connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1156 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1157 bool tv_detect;
1158
1159 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1160 return connector_status_disconnected;
1161
1162 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1163 if (tv_detect && tv_dac)
1164 found = connector_status_connected;
1165 return found;
1166 }
1167
1168 /* don't probe if the encoder is being used for something else not CRT related */
1169 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1170 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1171 return connector_status_disconnected;
1172 }
934 1173
935 /* save the regs we need */ 1174 /* save the regs we need */
936 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 1175 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
@@ -1013,8 +1252,7 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder
1013 } 1252 }
1014 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 1253 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1015 1254
1016 /* return found; */ 1255 return found;
1017 return connector_status_disconnected;
1018 1256
1019} 1257}
1020 1258
@@ -1025,6 +1263,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs =
1025 .mode_set = radeon_legacy_tv_dac_mode_set, 1263 .mode_set = radeon_legacy_tv_dac_mode_set,
1026 .commit = radeon_legacy_tv_dac_commit, 1264 .commit = radeon_legacy_tv_dac_commit,
1027 .detect = radeon_legacy_tv_dac_detect, 1265 .detect = radeon_legacy_tv_dac_detect,
1266 .disable = radeon_legacy_encoder_disable,
1028}; 1267};
1029 1268
1030 1269
@@ -1032,6 +1271,30 @@ static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1032 .destroy = radeon_enc_destroy, 1271 .destroy = radeon_enc_destroy,
1033}; 1272};
1034 1273
1274
1275static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1276{
1277 struct drm_device *dev = encoder->base.dev;
1278 struct radeon_device *rdev = dev->dev_private;
1279 struct radeon_encoder_int_tmds *tmds = NULL;
1280 bool ret;
1281
1282 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1283
1284 if (!tmds)
1285 return NULL;
1286
1287 if (rdev->is_atom_bios)
1288 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1289 else
1290 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1291
1292 if (ret == false)
1293 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1294
1295 return tmds;
1296}
1297
1035void 1298void
1036radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) 1299radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1037{ 1300{
@@ -1078,10 +1341,7 @@ radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t
1078 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1341 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1079 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS); 1342 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1080 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs); 1343 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1081 if (rdev->is_atom_bios) 1344 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1082 radeon_encoder->enc_priv = radeon_atombios_get_tmds_info(radeon_encoder);
1083 else
1084 radeon_encoder->enc_priv = radeon_combios_get_tmds_info(radeon_encoder);
1085 break; 1345 break;
1086 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1346 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1087 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC); 1347 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
new file mode 100644
index 000000000000..3a12bb0c0563
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
@@ -0,0 +1,904 @@
1#include "drmP.h"
2#include "drm_crtc_helper.h"
3#include "radeon.h"
4
5/*
6 * Integrated TV out support based on the GATOS code by
7 * Federico Ulivi <fulivi@lycos.com>
8 */
9
10
11/*
12 * Limits of h/v positions (hPos & vPos)
13 */
14#define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */
15#define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */
16
17/*
18 * Unit for hPos (in TV clock periods)
19 */
20#define H_POS_UNIT 10
21
22/*
23 * Indexes in h. code timing table for horizontal line position adjustment
24 */
25#define H_TABLE_POS1 6
26#define H_TABLE_POS2 8
27
28/*
29 * Limits of hor. size (hSize)
30 */
31#define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */
32
33/* tv standard constants */
34#define NTSC_TV_CLOCK_T 233
35#define NTSC_TV_VFTOTAL 1
36#define NTSC_TV_LINES_PER_FRAME 525
37#define NTSC_TV_ZERO_H_SIZE 479166
38#define NTSC_TV_H_SIZE_UNIT 9478
39
40#define PAL_TV_CLOCK_T 188
41#define PAL_TV_VFTOTAL 3
42#define PAL_TV_LINES_PER_FRAME 625
43#define PAL_TV_ZERO_H_SIZE 473200
44#define PAL_TV_H_SIZE_UNIT 9360
45
46/* tv pll setting for 27 mhz ref clk */
47#define NTSC_TV_PLL_M_27 22
48#define NTSC_TV_PLL_N_27 175
49#define NTSC_TV_PLL_P_27 5
50
51#define PAL_TV_PLL_M_27 113
52#define PAL_TV_PLL_N_27 668
53#define PAL_TV_PLL_P_27 3
54
55/* tv pll setting for 14 mhz ref clk */
56#define NTSC_TV_PLL_M_14 33
57#define NTSC_TV_PLL_N_14 693
58#define NTSC_TV_PLL_P_14 7
59
60#define VERT_LEAD_IN_LINES 2
61#define FRAC_BITS 0xe
62#define FRAC_MASK 0x3fff
63
64struct radeon_tv_mode_constants {
65 uint16_t hor_resolution;
66 uint16_t ver_resolution;
67 enum radeon_tv_std standard;
68 uint16_t hor_total;
69 uint16_t ver_total;
70 uint16_t hor_start;
71 uint16_t hor_syncstart;
72 uint16_t ver_syncstart;
73 unsigned def_restart;
74 uint16_t crtcPLL_N;
75 uint8_t crtcPLL_M;
76 uint8_t crtcPLL_post_div;
77 unsigned pix_to_tv;
78};
79
80static const uint16_t hor_timing_NTSC[] = {
81 0x0007,
82 0x003f,
83 0x0263,
84 0x0a24,
85 0x2a6b,
86 0x0a36,
87 0x126d, /* H_TABLE_POS1 */
88 0x1bfe,
89 0x1a8f, /* H_TABLE_POS2 */
90 0x1ec7,
91 0x3863,
92 0x1bfe,
93 0x1bfe,
94 0x1a2a,
95 0x1e95,
96 0x0e31,
97 0x201b,
98 0
99};
100
101static const uint16_t vert_timing_NTSC[] = {
102 0x2001,
103 0x200d,
104 0x1006,
105 0x0c06,
106 0x1006,
107 0x1818,
108 0x21e3,
109 0x1006,
110 0x0c06,
111 0x1006,
112 0x1817,
113 0x21d4,
114 0x0002,
115 0
116};
117
118static const uint16_t hor_timing_PAL[] = {
119 0x0007,
120 0x0058,
121 0x027c,
122 0x0a31,
123 0x2a77,
124 0x0a95,
125 0x124f, /* H_TABLE_POS1 */
126 0x1bfe,
127 0x1b22, /* H_TABLE_POS2 */
128 0x1ef9,
129 0x387c,
130 0x1bfe,
131 0x1bfe,
132 0x1b31,
133 0x1eb5,
134 0x0e43,
135 0x201b,
136 0
137};
138
139static const uint16_t vert_timing_PAL[] = {
140 0x2001,
141 0x200c,
142 0x1005,
143 0x0c05,
144 0x1005,
145 0x1401,
146 0x1821,
147 0x2240,
148 0x1005,
149 0x0c05,
150 0x1005,
151 0x1401,
152 0x1822,
153 0x2230,
154 0x0002,
155 0
156};
157
158/**********************************************************************
159 *
160 * availableModes
161 *
162 * Table of all allowed modes for tv output
163 *
164 **********************************************************************/
165static const struct radeon_tv_mode_constants available_tv_modes[] = {
166 { /* NTSC timing for 27 Mhz ref clk */
167 800, /* horResolution */
168 600, /* verResolution */
169 TV_STD_NTSC, /* standard */
170 990, /* horTotal */
171 740, /* verTotal */
172 813, /* horStart */
173 824, /* horSyncStart */
174 632, /* verSyncStart */
175 625592, /* defRestart */
176 592, /* crtcPLL_N */
177 91, /* crtcPLL_M */
178 4, /* crtcPLL_postDiv */
179 1022, /* pixToTV */
180 },
181 { /* PAL timing for 27 Mhz ref clk */
182 800, /* horResolution */
183 600, /* verResolution */
184 TV_STD_PAL, /* standard */
185 1144, /* horTotal */
186 706, /* verTotal */
187 812, /* horStart */
188 824, /* horSyncStart */
189 669, /* verSyncStart */
190 696700, /* defRestart */
191 1382, /* crtcPLL_N */
192 231, /* crtcPLL_M */
193 4, /* crtcPLL_postDiv */
194 759, /* pixToTV */
195 },
196 { /* NTSC timing for 14 Mhz ref clk */
197 800, /* horResolution */
198 600, /* verResolution */
199 TV_STD_NTSC, /* standard */
200 1018, /* horTotal */
201 727, /* verTotal */
202 813, /* horStart */
203 840, /* horSyncStart */
204 633, /* verSyncStart */
205 630627, /* defRestart */
206 347, /* crtcPLL_N */
207 14, /* crtcPLL_M */
208 8, /* crtcPLL_postDiv */
209 1022, /* pixToTV */
210 },
211};
212
213#define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes)
214
215static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder,
216 uint16_t *pll_ref_freq)
217{
218 struct drm_device *dev = radeon_encoder->base.dev;
219 struct radeon_device *rdev = dev->dev_private;
220 struct radeon_crtc *radeon_crtc;
221 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
222 const struct radeon_tv_mode_constants *const_ptr;
223 struct radeon_pll *pll;
224
225 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);
226 if (radeon_crtc->crtc_id == 1)
227 pll = &rdev->clock.p2pll;
228 else
229 pll = &rdev->clock.p1pll;
230
231 if (pll_ref_freq)
232 *pll_ref_freq = pll->reference_freq;
233
234 if (tv_dac->tv_std == TV_STD_NTSC ||
235 tv_dac->tv_std == TV_STD_NTSC_J ||
236 tv_dac->tv_std == TV_STD_PAL_M) {
237 if (pll->reference_freq == 2700)
238 const_ptr = &available_tv_modes[0];
239 else
240 const_ptr = &available_tv_modes[2];
241 } else {
242 if (pll->reference_freq == 2700)
243 const_ptr = &available_tv_modes[1];
244 else
245 const_ptr = &available_tv_modes[1]; /* FIX ME */
246 }
247 return const_ptr;
248}
249
250static long YCOEF_value[5] = { 2, 2, 0, 4, 0 };
251static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 };
252static long SLOPE_value[5] = { 1, 2, 2, 4, 8 };
253static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 };
254
255static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests,
256 unsigned n_wait_loops, unsigned cnt_threshold)
257{
258 struct drm_device *dev = encoder->dev;
259 struct radeon_device *rdev = dev->dev_private;
260 uint32_t save_pll_test;
261 unsigned int i, j;
262
263 WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100);
264 save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL);
265 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B);
266
267 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL);
268 for (i = 0; i < n_tests; i++) {
269 WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0);
270 for (j = 0; j < n_wait_loops; j++)
271 if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold)
272 break;
273 }
274 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test);
275 WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff);
276}
277
278
279static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder,
280 uint16_t addr, uint32_t value)
281{
282 struct drm_device *dev = radeon_encoder->base.dev;
283 struct radeon_device *rdev = dev->dev_private;
284 uint32_t tmp;
285 int i = 0;
286
287 WREG32(RADEON_TV_HOST_WRITE_DATA, value);
288
289 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);
290 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT);
291
292 do {
293 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
294 if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0)
295 break;
296 i++;
297 } while (i < 10000);
298 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
299}
300
301#if 0 /* included for completeness */
302static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr)
303{
304 struct drm_device *dev = radeon_encoder->base.dev;
305 struct radeon_device *rdev = dev->dev_private;
306 uint32_t tmp;
307 int i = 0;
308
309 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);
310 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD);
311
312 do {
313 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
314 if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0)
315 break;
316 i++;
317 } while (i < 10000);
318 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
319 return RREG32(RADEON_TV_HOST_READ_DATA);
320}
321#endif
322
323static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr)
324{
325 uint16_t h_table;
326
327 switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) {
328 case 0:
329 h_table = RADEON_TV_MAX_FIFO_ADDR_INTERNAL;
330 break;
331 case 1:
332 h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2;
333 break;
334 case 2:
335 h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2;
336 break;
337 default:
338 h_table = 0;
339 break;
340 }
341 return h_table;
342}
343
344static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr)
345{
346 uint16_t v_table;
347
348 switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) {
349 case 0:
350 v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1;
351 break;
352 case 1:
353 v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1;
354 break;
355 case 2:
356 v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1;
357 break;
358 default:
359 v_table = 0;
360 break;
361 }
362 return v_table;
363}
364
365static void radeon_restore_tv_timing_tables(struct radeon_encoder *radeon_encoder)
366{
367 struct drm_device *dev = radeon_encoder->base.dev;
368 struct radeon_device *rdev = dev->dev_private;
369 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
370 uint16_t h_table, v_table;
371 uint32_t tmp;
372 int i;
373
374 WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr);
375 h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr);
376 v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr);
377
378 for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, h_table--) {
379 tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]);
380 radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp);
381 if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0)
382 break;
383 }
384 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) {
385 tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]);
386 radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp);
387 if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0)
388 break;
389 }
390}
391
392static void radeon_legacy_write_tv_restarts(struct radeon_encoder *radeon_encoder)
393{
394 struct drm_device *dev = radeon_encoder->base.dev;
395 struct radeon_device *rdev = dev->dev_private;
396 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
397 WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart);
398 WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart);
399 WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart);
400}
401
402static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder)
403{
404 struct drm_device *dev = encoder->dev;
405 struct radeon_device *rdev = dev->dev_private;
406 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
407 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
408 struct radeon_crtc *radeon_crtc;
409 int restart;
410 unsigned int h_total, v_total, f_total;
411 int v_offset, h_offset;
412 u16 p1, p2, h_inc;
413 bool h_changed;
414 const struct radeon_tv_mode_constants *const_ptr;
415 struct radeon_pll *pll;
416
417 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);
418 if (radeon_crtc->crtc_id == 1)
419 pll = &rdev->clock.p2pll;
420 else
421 pll = &rdev->clock.p1pll;
422
423 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
424 if (!const_ptr)
425 return false;
426
427 h_total = const_ptr->hor_total;
428 v_total = const_ptr->ver_total;
429
430 if (tv_dac->tv_std == TV_STD_NTSC ||
431 tv_dac->tv_std == TV_STD_NTSC_J ||
432 tv_dac->tv_std == TV_STD_PAL_M ||
433 tv_dac->tv_std == TV_STD_PAL_60)
434 f_total = NTSC_TV_VFTOTAL + 1;
435 else
436 f_total = PAL_TV_VFTOTAL + 1;
437
438 /* adjust positions 1&2 in hor. cod timing table */
439 h_offset = tv_dac->h_pos * H_POS_UNIT;
440
441 if (tv_dac->tv_std == TV_STD_NTSC ||
442 tv_dac->tv_std == TV_STD_NTSC_J ||
443 tv_dac->tv_std == TV_STD_PAL_M) {
444 h_offset -= 50;
445 p1 = hor_timing_NTSC[H_TABLE_POS1];
446 p2 = hor_timing_NTSC[H_TABLE_POS2];
447 } else {
448 p1 = hor_timing_PAL[H_TABLE_POS1];
449 p2 = hor_timing_PAL[H_TABLE_POS2];
450 }
451
452 p1 = (u16)((int)p1 + h_offset);
453 p2 = (u16)((int)p2 - h_offset);
454
455 h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] ||
456 p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]);
457
458 tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1;
459 tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2;
460
461 /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */
462 h_offset = (h_offset * (int)(const_ptr->pix_to_tv)) / 1000;
463
464 /* adjust restart */
465 restart = const_ptr->def_restart;
466
467 /*
468 * convert v_pos TV lines to n. of CRTC pixels
469 */
470 if (tv_dac->tv_std == TV_STD_NTSC ||
471 tv_dac->tv_std == TV_STD_NTSC_J ||
472 tv_dac->tv_std == TV_STD_PAL_M ||
473 tv_dac->tv_std == TV_STD_PAL_60)
474 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME);
475 else
476 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME);
477
478 restart -= v_offset + h_offset;
479
480 DRM_DEBUG("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n",
481 const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart);
482
483 tv_dac->tv.hrestart = restart % h_total;
484 restart /= h_total;
485 tv_dac->tv.vrestart = restart % v_total;
486 restart /= v_total;
487 tv_dac->tv.frestart = restart % f_total;
488
489 DRM_DEBUG("compute_restart: F/H/V=%u,%u,%u\n",
490 (unsigned)tv_dac->tv.frestart,
491 (unsigned)tv_dac->tv.vrestart,
492 (unsigned)tv_dac->tv.hrestart);
493
494 /* compute h_inc from hsize */
495 if (tv_dac->tv_std == TV_STD_NTSC ||
496 tv_dac->tv_std == TV_STD_NTSC_J ||
497 tv_dac->tv_std == TV_STD_PAL_M)
498 h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * NTSC_TV_CLOCK_T) /
499 (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE)));
500 else
501 h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * PAL_TV_CLOCK_T) /
502 (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE)));
503
504 tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) |
505 ((u32)h_inc << RADEON_H_INC_SHIFT);
506
507 DRM_DEBUG("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc);
508
509 return h_changed;
510}
511
512void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
513 struct drm_display_mode *mode,
514 struct drm_display_mode *adjusted_mode)
515{
516 struct drm_device *dev = encoder->dev;
517 struct radeon_device *rdev = dev->dev_private;
518 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
519 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
520 const struct radeon_tv_mode_constants *const_ptr;
521 struct radeon_crtc *radeon_crtc;
522 int i;
523 uint16_t pll_ref_freq;
524 uint32_t vert_space, flicker_removal, tmp;
525 uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl;
526 uint32_t tv_modulator_cntl1, tv_modulator_cntl2;
527 uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2;
528 uint32_t tv_pll_cntl, tv_pll_cntl1, tv_ftotal;
529 uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl;
530 uint32_t m, n, p;
531 const uint16_t *hor_timing;
532 const uint16_t *vert_timing;
533
534 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq);
535 if (!const_ptr)
536 return;
537
538 radeon_crtc = to_radeon_crtc(encoder->crtc);
539
540 tv_master_cntl = (RADEON_VIN_ASYNC_RST |
541 RADEON_CRT_FIFO_CE_EN |
542 RADEON_TV_FIFO_CE_EN |
543 RADEON_TV_ON);
544
545 if (!ASIC_IS_R300(rdev))
546 tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb;
547
548 if (tv_dac->tv_std == TV_STD_NTSC ||
549 tv_dac->tv_std == TV_STD_NTSC_J)
550 tv_master_cntl |= RADEON_RESTART_PHASE_FIX;
551
552 tv_modulator_cntl1 = (RADEON_SLEW_RATE_LIMIT |
553 RADEON_SYNC_TIP_LEVEL |
554 RADEON_YFLT_EN |
555 RADEON_UVFLT_EN |
556 (6 << RADEON_CY_FILT_BLEND_SHIFT));
557
558 if (tv_dac->tv_std == TV_STD_NTSC ||
559 tv_dac->tv_std == TV_STD_NTSC_J) {
560 tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) |
561 (0x3b << RADEON_BLANK_LEVEL_SHIFT);
562 tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) |
563 ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
564 } else if (tv_dac->tv_std == TV_STD_SCART_PAL) {
565 tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN;
566 tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) |
567 ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
568 } else {
569 tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN |
570 (0x3b << RADEON_SET_UP_LEVEL_SHIFT) |
571 (0x3b << RADEON_BLANK_LEVEL_SHIFT);
572 tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) |
573 ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
574 }
575
576
577 tv_rgb_cntl = (RADEON_RGB_DITHER_EN
578 | RADEON_TVOUT_SCALE_EN
579 | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT)
580 | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT)
581 | RADEON_RGB_ATTEN_SEL(0x3)
582 | RADEON_RGB_ATTEN_VAL(0xc));
583
584 if (radeon_crtc->crtc_id == 1)
585 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2;
586 else {
587 if (radeon_crtc->rmx_type != RMX_OFF)
588 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX;
589 else
590 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1;
591 }
592
593 if (tv_dac->tv_std == TV_STD_NTSC ||
594 tv_dac->tv_std == TV_STD_NTSC_J ||
595 tv_dac->tv_std == TV_STD_PAL_M ||
596 tv_dac->tv_std == TV_STD_PAL_60)
597 vert_space = const_ptr->ver_total * 2 * 10000 / NTSC_TV_LINES_PER_FRAME;
598 else
599 vert_space = const_ptr->ver_total * 2 * 10000 / PAL_TV_LINES_PER_FRAME;
600
601 tmp = RREG32(RADEON_TV_VSCALER_CNTL1);
602 tmp &= 0xe3ff0000;
603 tmp |= (vert_space * (1 << FRAC_BITS) / 10000);
604 tv_vscaler_cntl1 = tmp;
605
606 if (pll_ref_freq == 2700)
607 tv_vscaler_cntl1 |= RADEON_RESTART_FIELD;
608
609 if (const_ptr->hor_resolution == 1024)
610 tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT);
611 else
612 tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT);
613
614 /* scale up for int divide */
615 tmp = const_ptr->ver_total * 2 * 1000;
616 if (tv_dac->tv_std == TV_STD_NTSC ||
617 tv_dac->tv_std == TV_STD_NTSC_J ||
618 tv_dac->tv_std == TV_STD_PAL_M ||
619 tv_dac->tv_std == TV_STD_PAL_60) {
620 tmp /= NTSC_TV_LINES_PER_FRAME;
621 } else {
622 tmp /= PAL_TV_LINES_PER_FRAME;
623 }
624 flicker_removal = (tmp + 500) / 1000;
625
626 if (flicker_removal < 3)
627 flicker_removal = 3;
628 for (i = 0; i < 6; ++i) {
629 if (flicker_removal == SLOPE_limit[i])
630 break;
631 }
632
633 tv_y_saw_tooth_cntl = (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) +
634 5001) / 10000 / 8 | ((SLOPE_value[i] *
635 (1 << (FRAC_BITS - 1)) / 8) << 16);
636 tv_y_fall_cntl =
637 (YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) |
638 RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) /
639 1024;
640 tv_y_rise_cntl = RADEON_Y_RISE_PING_PONG|
641 (flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024;
642
643 tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0;
644 tv_vscaler_cntl2 |= (0x10 << 24) |
645 RADEON_DITHER_MODE |
646 RADEON_Y_OUTPUT_DITHER_EN |
647 RADEON_UV_OUTPUT_DITHER_EN |
648 RADEON_UV_TO_BUF_DITHER_EN;
649
650 tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK;
651 tmp = ((16384 * 256 * 10) / tmp + 5) / 10;
652 tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000;
653 tv_dac->tv.timing_cntl = tmp;
654
655 if (tv_dac->tv_std == TV_STD_NTSC ||
656 tv_dac->tv_std == TV_STD_NTSC_J ||
657 tv_dac->tv_std == TV_STD_PAL_M ||
658 tv_dac->tv_std == TV_STD_PAL_60)
659 tv_dac_cntl = tv_dac->ntsc_tvdac_adj;
660 else
661 tv_dac_cntl = tv_dac->pal_tvdac_adj;
662
663 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
664
665 if (tv_dac->tv_std == TV_STD_NTSC ||
666 tv_dac->tv_std == TV_STD_NTSC_J)
667 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
668 else
669 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
670
671 if (tv_dac->tv_std == TV_STD_NTSC ||
672 tv_dac->tv_std == TV_STD_NTSC_J) {
673 if (pll_ref_freq == 2700) {
674 m = NTSC_TV_PLL_M_27;
675 n = NTSC_TV_PLL_N_27;
676 p = NTSC_TV_PLL_P_27;
677 } else {
678 m = NTSC_TV_PLL_M_14;
679 n = NTSC_TV_PLL_N_14;
680 p = NTSC_TV_PLL_P_14;
681 }
682 } else {
683 if (pll_ref_freq == 2700) {
684 m = PAL_TV_PLL_M_27;
685 n = PAL_TV_PLL_N_27;
686 p = PAL_TV_PLL_P_27;
687 } else {
688 m = PAL_TV_PLL_M_27;
689 n = PAL_TV_PLL_N_27;
690 p = PAL_TV_PLL_P_27;
691 }
692 }
693
694 tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) |
695 (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) |
696 ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
697 (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
698 ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
699
700 tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK) << RADEON_TVPCP_SHIFT) |
701 ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) |
702 ((1 & RADEON_TVPDC_MASK) << RADEON_TVPDC_SHIFT) |
703 RADEON_TVCLK_SRC_SEL_TVPLL |
704 RADEON_TVPLL_TEST_DIS);
705
706 tv_dac->tv.tv_uv_adr = 0xc8;
707
708 if (tv_dac->tv_std == TV_STD_NTSC ||
709 tv_dac->tv_std == TV_STD_NTSC_J ||
710 tv_dac->tv_std == TV_STD_PAL_M ||
711 tv_dac->tv_std == TV_STD_PAL_60) {
712 tv_ftotal = NTSC_TV_VFTOTAL;
713 hor_timing = hor_timing_NTSC;
714 vert_timing = vert_timing_NTSC;
715 } else {
716 hor_timing = hor_timing_PAL;
717 vert_timing = vert_timing_PAL;
718 tv_ftotal = PAL_TV_VFTOTAL;
719 }
720
721 for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) {
722 if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0)
723 break;
724 }
725
726 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) {
727 if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0)
728 break;
729 }
730
731 radeon_legacy_tv_init_restarts(encoder);
732
733 /* play with DAC_CNTL */
734 /* play with GPIOPAD_A */
735 /* DISP_OUTPUT_CNTL */
736 /* use reference freq */
737
738 /* program the TV registers */
739 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |
740 RADEON_CRT_ASYNC_RST | RADEON_TV_FIFO_ASYNC_RST));
741
742 tmp = RREG32(RADEON_TV_DAC_CNTL);
743 tmp &= ~RADEON_TV_DAC_NBLANK;
744 tmp |= RADEON_TV_DAC_BGSLEEP |
745 RADEON_TV_DAC_RDACPD |
746 RADEON_TV_DAC_GDACPD |
747 RADEON_TV_DAC_BDACPD;
748 WREG32(RADEON_TV_DAC_CNTL, tmp);
749
750 /* TV PLL */
751 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL);
752 WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl);
753 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET);
754
755 radeon_wait_pll_lock(encoder, 200, 800, 135);
756
757 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET);
758
759 radeon_wait_pll_lock(encoder, 300, 160, 27);
760 radeon_wait_pll_lock(encoder, 200, 800, 135);
761
762 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf);
763 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL);
764
765 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK);
766 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP);
767
768 /* TV HV */
769 WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl);
770 WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1);
771 WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1);
772 WREG32(RADEON_TV_HSTART, const_ptr->hor_start);
773
774 WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1);
775 WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1);
776 WREG32(RADEON_TV_FTOTAL, tv_ftotal);
777 WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1);
778 WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2);
779
780 WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl);
781 WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl);
782 WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl);
783
784 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |
785 RADEON_CRT_ASYNC_RST));
786
787 /* TV restarts */
788 radeon_legacy_write_tv_restarts(radeon_encoder);
789
790 /* tv timings */
791 radeon_restore_tv_timing_tables(radeon_encoder);
792
793 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST));
794
795 /* tv std */
796 WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE));
797 WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl);
798 WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1);
799 WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2);
800 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN |
801 RADEON_C_GRN_EN |
802 RADEON_CMP_BLU_EN |
803 RADEON_DAC_DITHER_EN));
804
805 WREG32(RADEON_TV_CRC_CNTL, 0);
806
807 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
808
809 WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) |
810 (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT)));
811 WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) |
812 (0x100 << RADEON_Y_GAIN_SHIFT)));
813
814 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
815
816}
817
818void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
819 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
820 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid)
821{
822 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
823 const struct radeon_tv_mode_constants *const_ptr;
824 uint32_t tmp;
825
826 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
827 if (!const_ptr)
828 return;
829
830 *h_total_disp = (((const_ptr->hor_resolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
831 (((const_ptr->hor_total / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT);
832
833 tmp = *h_sync_strt_wid;
834 tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR);
835 tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) |
836 (const_ptr->hor_syncstart & 7);
837 *h_sync_strt_wid = tmp;
838
839 *v_total_disp = ((const_ptr->ver_resolution - 1) << RADEON_CRTC_V_DISP_SHIFT) |
840 ((const_ptr->ver_total - 1) << RADEON_CRTC_V_TOTAL_SHIFT);
841
842 tmp = *v_sync_strt_wid;
843 tmp &= ~RADEON_CRTC_V_SYNC_STRT;
844 tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT);
845 *v_sync_strt_wid = tmp;
846}
847
848static inline int get_post_div(int value)
849{
850 int post_div;
851 switch (value) {
852 case 1: post_div = 0; break;
853 case 2: post_div = 1; break;
854 case 3: post_div = 4; break;
855 case 4: post_div = 2; break;
856 case 6: post_div = 6; break;
857 case 8: post_div = 3; break;
858 case 12: post_div = 7; break;
859 case 16:
860 default: post_div = 5; break;
861 }
862 return post_div;
863}
864
865void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
866 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
867 uint32_t *ppll_div_3, uint32_t *pixclks_cntl)
868{
869 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
870 const struct radeon_tv_mode_constants *const_ptr;
871
872 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
873 if (!const_ptr)
874 return;
875
876 *htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN;
877
878 *ppll_ref_div = const_ptr->crtcPLL_M;
879
880 *ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16);
881 *pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL);
882 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK;
883}
884
885void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
886 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
887 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl)
888{
889 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
890 const struct radeon_tv_mode_constants *const_ptr;
891
892 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
893 if (!const_ptr)
894 return;
895
896 *htotal2_cntl = (const_ptr->hor_total & 0x7);
897
898 *p2pll_ref_div = const_ptr->crtcPLL_M;
899
900 *p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16);
901 *pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK;
902 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK | RADEON_PIXCLK_TV_SRC_SEL;
903}
904
diff --git a/drivers/gpu/drm/radeon/radeon_microcode.h b/drivers/gpu/drm/radeon/radeon_microcode.h
deleted file mode 100644
index a348c9e7db1c..000000000000
--- a/drivers/gpu/drm/radeon/radeon_microcode.h
+++ /dev/null
@@ -1,1844 +0,0 @@
1/*
2 * Copyright 2007 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
20 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26#ifndef RADEON_MICROCODE_H
27#define RADEON_MICROCODE_H
28
29/* production radeon ucode r1xx-r6xx */
30static const u32 R100_cp_microcode[][2] = {
31 { 0x21007000, 0000000000 },
32 { 0x20007000, 0000000000 },
33 { 0x000000b4, 0x00000004 },
34 { 0x000000b8, 0x00000004 },
35 { 0x6f5b4d4c, 0000000000 },
36 { 0x4c4c427f, 0000000000 },
37 { 0x5b568a92, 0000000000 },
38 { 0x4ca09c6d, 0000000000 },
39 { 0xad4c4c4c, 0000000000 },
40 { 0x4ce1af3d, 0000000000 },
41 { 0xd8afafaf, 0000000000 },
42 { 0xd64c4cdc, 0000000000 },
43 { 0x4cd10d10, 0000000000 },
44 { 0x000f0000, 0x00000016 },
45 { 0x362f242d, 0000000000 },
46 { 0x00000012, 0x00000004 },
47 { 0x000f0000, 0x00000016 },
48 { 0x362f282d, 0000000000 },
49 { 0x000380e7, 0x00000002 },
50 { 0x04002c97, 0x00000002 },
51 { 0x000f0001, 0x00000016 },
52 { 0x333a3730, 0000000000 },
53 { 0x000077ef, 0x00000002 },
54 { 0x00061000, 0x00000002 },
55 { 0x00000021, 0x0000001a },
56 { 0x00004000, 0x0000001e },
57 { 0x00061000, 0x00000002 },
58 { 0x00000021, 0x0000001a },
59 { 0x00004000, 0x0000001e },
60 { 0x00061000, 0x00000002 },
61 { 0x00000021, 0x0000001a },
62 { 0x00004000, 0x0000001e },
63 { 0x00000017, 0x00000004 },
64 { 0x0003802b, 0x00000002 },
65 { 0x040067e0, 0x00000002 },
66 { 0x00000017, 0x00000004 },
67 { 0x000077e0, 0x00000002 },
68 { 0x00065000, 0x00000002 },
69 { 0x000037e1, 0x00000002 },
70 { 0x040067e1, 0x00000006 },
71 { 0x000077e0, 0x00000002 },
72 { 0x000077e1, 0x00000002 },
73 { 0x000077e1, 0x00000006 },
74 { 0xffffffff, 0000000000 },
75 { 0x10000000, 0000000000 },
76 { 0x0003802b, 0x00000002 },
77 { 0x040067e0, 0x00000006 },
78 { 0x00007675, 0x00000002 },
79 { 0x00007676, 0x00000002 },
80 { 0x00007677, 0x00000002 },
81 { 0x00007678, 0x00000006 },
82 { 0x0003802c, 0x00000002 },
83 { 0x04002676, 0x00000002 },
84 { 0x00007677, 0x00000002 },
85 { 0x00007678, 0x00000006 },
86 { 0x0000002f, 0x00000018 },
87 { 0x0000002f, 0x00000018 },
88 { 0000000000, 0x00000006 },
89 { 0x00000030, 0x00000018 },
90 { 0x00000030, 0x00000018 },
91 { 0000000000, 0x00000006 },
92 { 0x01605000, 0x00000002 },
93 { 0x00065000, 0x00000002 },
94 { 0x00098000, 0x00000002 },
95 { 0x00061000, 0x00000002 },
96 { 0x64c0603e, 0x00000004 },
97 { 0x000380e6, 0x00000002 },
98 { 0x040025c5, 0x00000002 },
99 { 0x00080000, 0x00000016 },
100 { 0000000000, 0000000000 },
101 { 0x0400251d, 0x00000002 },
102 { 0x00007580, 0x00000002 },
103 { 0x00067581, 0x00000002 },
104 { 0x04002580, 0x00000002 },
105 { 0x00067581, 0x00000002 },
106 { 0x00000049, 0x00000004 },
107 { 0x00005000, 0000000000 },
108 { 0x000380e6, 0x00000002 },
109 { 0x040025c5, 0x00000002 },
110 { 0x00061000, 0x00000002 },
111 { 0x0000750e, 0x00000002 },
112 { 0x00019000, 0x00000002 },
113 { 0x00011055, 0x00000014 },
114 { 0x00000055, 0x00000012 },
115 { 0x0400250f, 0x00000002 },
116 { 0x0000504f, 0x00000004 },
117 { 0x000380e6, 0x00000002 },
118 { 0x040025c5, 0x00000002 },
119 { 0x00007565, 0x00000002 },
120 { 0x00007566, 0x00000002 },
121 { 0x00000058, 0x00000004 },
122 { 0x000380e6, 0x00000002 },
123 { 0x040025c5, 0x00000002 },
124 { 0x01e655b4, 0x00000002 },
125 { 0x4401b0e4, 0x00000002 },
126 { 0x01c110e4, 0x00000002 },
127 { 0x26667066, 0x00000018 },
128 { 0x040c2565, 0x00000002 },
129 { 0x00000066, 0x00000018 },
130 { 0x04002564, 0x00000002 },
131 { 0x00007566, 0x00000002 },
132 { 0x0000005d, 0x00000004 },
133 { 0x00401069, 0x00000008 },
134 { 0x00101000, 0x00000002 },
135 { 0x000d80ff, 0x00000002 },
136 { 0x0080006c, 0x00000008 },
137 { 0x000f9000, 0x00000002 },
138 { 0x000e00ff, 0x00000002 },
139 { 0000000000, 0x00000006 },
140 { 0x0000008f, 0x00000018 },
141 { 0x0000005b, 0x00000004 },
142 { 0x000380e6, 0x00000002 },
143 { 0x040025c5, 0x00000002 },
144 { 0x00007576, 0x00000002 },
145 { 0x00065000, 0x00000002 },
146 { 0x00009000, 0x00000002 },
147 { 0x00041000, 0x00000002 },
148 { 0x0c00350e, 0x00000002 },
149 { 0x00049000, 0x00000002 },
150 { 0x00051000, 0x00000002 },
151 { 0x01e785f8, 0x00000002 },
152 { 0x00200000, 0x00000002 },
153 { 0x0060007e, 0x0000000c },
154 { 0x00007563, 0x00000002 },
155 { 0x006075f0, 0x00000021 },
156 { 0x20007073, 0x00000004 },
157 { 0x00005073, 0x00000004 },
158 { 0x000380e6, 0x00000002 },
159 { 0x040025c5, 0x00000002 },
160 { 0x00007576, 0x00000002 },
161 { 0x00007577, 0x00000002 },
162 { 0x0000750e, 0x00000002 },
163 { 0x0000750f, 0x00000002 },
164 { 0x00a05000, 0x00000002 },
165 { 0x00600083, 0x0000000c },
166 { 0x006075f0, 0x00000021 },
167 { 0x000075f8, 0x00000002 },
168 { 0x00000083, 0x00000004 },
169 { 0x000a750e, 0x00000002 },
170 { 0x000380e6, 0x00000002 },
171 { 0x040025c5, 0x00000002 },
172 { 0x0020750f, 0x00000002 },
173 { 0x00600086, 0x00000004 },
174 { 0x00007570, 0x00000002 },
175 { 0x00007571, 0x00000002 },
176 { 0x00007572, 0x00000006 },
177 { 0x000380e6, 0x00000002 },
178 { 0x040025c5, 0x00000002 },
179 { 0x00005000, 0x00000002 },
180 { 0x00a05000, 0x00000002 },
181 { 0x00007568, 0x00000002 },
182 { 0x00061000, 0x00000002 },
183 { 0x00000095, 0x0000000c },
184 { 0x00058000, 0x00000002 },
185 { 0x0c607562, 0x00000002 },
186 { 0x00000097, 0x00000004 },
187 { 0x000380e6, 0x00000002 },
188 { 0x040025c5, 0x00000002 },
189 { 0x00600096, 0x00000004 },
190 { 0x400070e5, 0000000000 },
191 { 0x000380e6, 0x00000002 },
192 { 0x040025c5, 0x00000002 },
193 { 0x000380e5, 0x00000002 },
194 { 0x000000a8, 0x0000001c },
195 { 0x000650aa, 0x00000018 },
196 { 0x040025bb, 0x00000002 },
197 { 0x000610ab, 0x00000018 },
198 { 0x040075bc, 0000000000 },
199 { 0x000075bb, 0x00000002 },
200 { 0x000075bc, 0000000000 },
201 { 0x00090000, 0x00000006 },
202 { 0x00090000, 0x00000002 },
203 { 0x000d8002, 0x00000006 },
204 { 0x00007832, 0x00000002 },
205 { 0x00005000, 0x00000002 },
206 { 0x000380e7, 0x00000002 },
207 { 0x04002c97, 0x00000002 },
208 { 0x00007820, 0x00000002 },
209 { 0x00007821, 0x00000002 },
210 { 0x00007800, 0000000000 },
211 { 0x01200000, 0x00000002 },
212 { 0x20077000, 0x00000002 },
213 { 0x01200000, 0x00000002 },
214 { 0x20007000, 0x00000002 },
215 { 0x00061000, 0x00000002 },
216 { 0x0120751b, 0x00000002 },
217 { 0x8040750a, 0x00000002 },
218 { 0x8040750b, 0x00000002 },
219 { 0x00110000, 0x00000002 },
220 { 0x000380e5, 0x00000002 },
221 { 0x000000c6, 0x0000001c },
222 { 0x000610ab, 0x00000018 },
223 { 0x844075bd, 0x00000002 },
224 { 0x000610aa, 0x00000018 },
225 { 0x840075bb, 0x00000002 },
226 { 0x000610ab, 0x00000018 },
227 { 0x844075bc, 0x00000002 },
228 { 0x000000c9, 0x00000004 },
229 { 0x804075bd, 0x00000002 },
230 { 0x800075bb, 0x00000002 },
231 { 0x804075bc, 0x00000002 },
232 { 0x00108000, 0x00000002 },
233 { 0x01400000, 0x00000002 },
234 { 0x006000cd, 0x0000000c },
235 { 0x20c07000, 0x00000020 },
236 { 0x000000cf, 0x00000012 },
237 { 0x00800000, 0x00000006 },
238 { 0x0080751d, 0x00000006 },
239 { 0000000000, 0000000000 },
240 { 0x0000775c, 0x00000002 },
241 { 0x00a05000, 0x00000002 },
242 { 0x00661000, 0x00000002 },
243 { 0x0460275d, 0x00000020 },
244 { 0x00004000, 0000000000 },
245 { 0x01e00830, 0x00000002 },
246 { 0x21007000, 0000000000 },
247 { 0x6464614d, 0000000000 },
248 { 0x69687420, 0000000000 },
249 { 0x00000073, 0000000000 },
250 { 0000000000, 0000000000 },
251 { 0x00005000, 0x00000002 },
252 { 0x000380d0, 0x00000002 },
253 { 0x040025e0, 0x00000002 },
254 { 0x000075e1, 0000000000 },
255 { 0x00000001, 0000000000 },
256 { 0x000380e0, 0x00000002 },
257 { 0x04002394, 0x00000002 },
258 { 0x00005000, 0000000000 },
259 { 0000000000, 0000000000 },
260 { 0000000000, 0000000000 },
261 { 0x00000008, 0000000000 },
262 { 0x00000004, 0000000000 },
263 { 0000000000, 0000000000 },
264 { 0000000000, 0000000000 },
265 { 0000000000, 0000000000 },
266 { 0000000000, 0000000000 },
267 { 0000000000, 0000000000 },
268 { 0000000000, 0000000000 },
269 { 0000000000, 0000000000 },
270 { 0000000000, 0000000000 },
271 { 0000000000, 0000000000 },
272 { 0000000000, 0000000000 },
273 { 0000000000, 0000000000 },
274 { 0000000000, 0000000000 },
275 { 0000000000, 0000000000 },
276 { 0000000000, 0000000000 },
277 { 0000000000, 0000000000 },
278 { 0000000000, 0000000000 },
279 { 0000000000, 0000000000 },
280 { 0000000000, 0000000000 },
281 { 0000000000, 0000000000 },
282 { 0000000000, 0000000000 },
283 { 0000000000, 0000000000 },
284 { 0000000000, 0000000000 },
285 { 0000000000, 0000000000 },
286 { 0000000000, 0000000000 },
287};
288
289static const u32 R200_cp_microcode[][2] = {
290 { 0x21007000, 0000000000 },
291 { 0x20007000, 0000000000 },
292 { 0x000000bf, 0x00000004 },
293 { 0x000000c3, 0x00000004 },
294 { 0x7a685e5d, 0000000000 },
295 { 0x5d5d5588, 0000000000 },
296 { 0x68659197, 0000000000 },
297 { 0x5da19f78, 0000000000 },
298 { 0x5d5d5d5d, 0000000000 },
299 { 0x5dee5d50, 0000000000 },
300 { 0xf2acacac, 0000000000 },
301 { 0xe75df9e9, 0000000000 },
302 { 0xb1dd0e11, 0000000000 },
303 { 0xe2afafaf, 0000000000 },
304 { 0x000f0000, 0x00000016 },
305 { 0x452f232d, 0000000000 },
306 { 0x00000013, 0x00000004 },
307 { 0x000f0000, 0x00000016 },
308 { 0x452f272d, 0000000000 },
309 { 0x000f0001, 0x00000016 },
310 { 0x3e4d4a37, 0000000000 },
311 { 0x000077ef, 0x00000002 },
312 { 0x00061000, 0x00000002 },
313 { 0x00000020, 0x0000001a },
314 { 0x00004000, 0x0000001e },
315 { 0x00061000, 0x00000002 },
316 { 0x00000020, 0x0000001a },
317 { 0x00004000, 0x0000001e },
318 { 0x00061000, 0x00000002 },
319 { 0x00000020, 0x0000001a },
320 { 0x00004000, 0x0000001e },
321 { 0x00000016, 0x00000004 },
322 { 0x0003802a, 0x00000002 },
323 { 0x040067e0, 0x00000002 },
324 { 0x00000016, 0x00000004 },
325 { 0x000077e0, 0x00000002 },
326 { 0x00065000, 0x00000002 },
327 { 0x000037e1, 0x00000002 },
328 { 0x040067e1, 0x00000006 },
329 { 0x000077e0, 0x00000002 },
330 { 0x000077e1, 0x00000002 },
331 { 0x000077e1, 0x00000006 },
332 { 0xffffffff, 0000000000 },
333 { 0x10000000, 0000000000 },
334 { 0x07f007f0, 0000000000 },
335 { 0x0003802a, 0x00000002 },
336 { 0x040067e0, 0x00000006 },
337 { 0x0003802c, 0x00000002 },
338 { 0x04002741, 0x00000002 },
339 { 0x04002741, 0x00000002 },
340 { 0x04002743, 0x00000002 },
341 { 0x00007675, 0x00000002 },
342 { 0x00007676, 0x00000002 },
343 { 0x00007677, 0x00000002 },
344 { 0x00007678, 0x00000006 },
345 { 0x0003802c, 0x00000002 },
346 { 0x04002741, 0x00000002 },
347 { 0x04002741, 0x00000002 },
348 { 0x04002743, 0x00000002 },
349 { 0x00007676, 0x00000002 },
350 { 0x00007677, 0x00000002 },
351 { 0x00007678, 0x00000006 },
352 { 0x0003802b, 0x00000002 },
353 { 0x04002676, 0x00000002 },
354 { 0x00007677, 0x00000002 },
355 { 0x0003802c, 0x00000002 },
356 { 0x04002741, 0x00000002 },
357 { 0x04002743, 0x00000002 },
358 { 0x00007678, 0x00000006 },
359 { 0x0003802c, 0x00000002 },
360 { 0x04002741, 0x00000002 },
361 { 0x04002741, 0x00000002 },
362 { 0x04002743, 0x00000002 },
363 { 0x00007678, 0x00000006 },
364 { 0x0000002f, 0x00000018 },
365 { 0x0000002f, 0x00000018 },
366 { 0000000000, 0x00000006 },
367 { 0x00000037, 0x00000018 },
368 { 0x00000037, 0x00000018 },
369 { 0000000000, 0x00000006 },
370 { 0x01605000, 0x00000002 },
371 { 0x00065000, 0x00000002 },
372 { 0x00098000, 0x00000002 },
373 { 0x00061000, 0x00000002 },
374 { 0x64c06051, 0x00000004 },
375 { 0x00080000, 0x00000016 },
376 { 0000000000, 0000000000 },
377 { 0x0400251d, 0x00000002 },
378 { 0x00007580, 0x00000002 },
379 { 0x00067581, 0x00000002 },
380 { 0x04002580, 0x00000002 },
381 { 0x00067581, 0x00000002 },
382 { 0x0000005a, 0x00000004 },
383 { 0x00005000, 0000000000 },
384 { 0x00061000, 0x00000002 },
385 { 0x0000750e, 0x00000002 },
386 { 0x00019000, 0x00000002 },
387 { 0x00011064, 0x00000014 },
388 { 0x00000064, 0x00000012 },
389 { 0x0400250f, 0x00000002 },
390 { 0x0000505e, 0x00000004 },
391 { 0x00007565, 0x00000002 },
392 { 0x00007566, 0x00000002 },
393 { 0x00000065, 0x00000004 },
394 { 0x01e655b4, 0x00000002 },
395 { 0x4401b0f0, 0x00000002 },
396 { 0x01c110f0, 0x00000002 },
397 { 0x26667071, 0x00000018 },
398 { 0x040c2565, 0x00000002 },
399 { 0x00000071, 0x00000018 },
400 { 0x04002564, 0x00000002 },
401 { 0x00007566, 0x00000002 },
402 { 0x00000068, 0x00000004 },
403 { 0x00401074, 0x00000008 },
404 { 0x00101000, 0x00000002 },
405 { 0x000d80ff, 0x00000002 },
406 { 0x00800077, 0x00000008 },
407 { 0x000f9000, 0x00000002 },
408 { 0x000e00ff, 0x00000002 },
409 { 0000000000, 0x00000006 },
410 { 0x00000094, 0x00000018 },
411 { 0x00000068, 0x00000004 },
412 { 0x00007576, 0x00000002 },
413 { 0x00065000, 0x00000002 },
414 { 0x00009000, 0x00000002 },
415 { 0x00041000, 0x00000002 },
416 { 0x0c00350e, 0x00000002 },
417 { 0x00049000, 0x00000002 },
418 { 0x00051000, 0x00000002 },
419 { 0x01e785f8, 0x00000002 },
420 { 0x00200000, 0x00000002 },
421 { 0x00600087, 0x0000000c },
422 { 0x00007563, 0x00000002 },
423 { 0x006075f0, 0x00000021 },
424 { 0x2000707c, 0x00000004 },
425 { 0x0000507c, 0x00000004 },
426 { 0x00007576, 0x00000002 },
427 { 0x00007577, 0x00000002 },
428 { 0x0000750e, 0x00000002 },
429 { 0x0000750f, 0x00000002 },
430 { 0x00a05000, 0x00000002 },
431 { 0x0060008a, 0x0000000c },
432 { 0x006075f0, 0x00000021 },
433 { 0x000075f8, 0x00000002 },
434 { 0x0000008a, 0x00000004 },
435 { 0x000a750e, 0x00000002 },
436 { 0x0020750f, 0x00000002 },
437 { 0x0060008d, 0x00000004 },
438 { 0x00007570, 0x00000002 },
439 { 0x00007571, 0x00000002 },
440 { 0x00007572, 0x00000006 },
441 { 0x00005000, 0x00000002 },
442 { 0x00a05000, 0x00000002 },
443 { 0x00007568, 0x00000002 },
444 { 0x00061000, 0x00000002 },
445 { 0x00000098, 0x0000000c },
446 { 0x00058000, 0x00000002 },
447 { 0x0c607562, 0x00000002 },
448 { 0x0000009a, 0x00000004 },
449 { 0x00600099, 0x00000004 },
450 { 0x400070f1, 0000000000 },
451 { 0x000380f1, 0x00000002 },
452 { 0x000000a7, 0x0000001c },
453 { 0x000650a9, 0x00000018 },
454 { 0x040025bb, 0x00000002 },
455 { 0x000610aa, 0x00000018 },
456 { 0x040075bc, 0000000000 },
457 { 0x000075bb, 0x00000002 },
458 { 0x000075bc, 0000000000 },
459 { 0x00090000, 0x00000006 },
460 { 0x00090000, 0x00000002 },
461 { 0x000d8002, 0x00000006 },
462 { 0x00005000, 0x00000002 },
463 { 0x00007821, 0x00000002 },
464 { 0x00007800, 0000000000 },
465 { 0x00007821, 0x00000002 },
466 { 0x00007800, 0000000000 },
467 { 0x01665000, 0x00000002 },
468 { 0x000a0000, 0x00000002 },
469 { 0x000671cc, 0x00000002 },
470 { 0x0286f1cd, 0x00000002 },
471 { 0x000000b7, 0x00000010 },
472 { 0x21007000, 0000000000 },
473 { 0x000000be, 0x0000001c },
474 { 0x00065000, 0x00000002 },
475 { 0x000a0000, 0x00000002 },
476 { 0x00061000, 0x00000002 },
477 { 0x000b0000, 0x00000002 },
478 { 0x38067000, 0x00000002 },
479 { 0x000a00ba, 0x00000004 },
480 { 0x20007000, 0000000000 },
481 { 0x01200000, 0x00000002 },
482 { 0x20077000, 0x00000002 },
483 { 0x01200000, 0x00000002 },
484 { 0x20007000, 0000000000 },
485 { 0x00061000, 0x00000002 },
486 { 0x0120751b, 0x00000002 },
487 { 0x8040750a, 0x00000002 },
488 { 0x8040750b, 0x00000002 },
489 { 0x00110000, 0x00000002 },
490 { 0x000380f1, 0x00000002 },
491 { 0x000000d1, 0x0000001c },
492 { 0x000610aa, 0x00000018 },
493 { 0x844075bd, 0x00000002 },
494 { 0x000610a9, 0x00000018 },
495 { 0x840075bb, 0x00000002 },
496 { 0x000610aa, 0x00000018 },
497 { 0x844075bc, 0x00000002 },
498 { 0x000000d4, 0x00000004 },
499 { 0x804075bd, 0x00000002 },
500 { 0x800075bb, 0x00000002 },
501 { 0x804075bc, 0x00000002 },
502 { 0x00108000, 0x00000002 },
503 { 0x01400000, 0x00000002 },
504 { 0x006000d8, 0x0000000c },
505 { 0x20c07000, 0x00000020 },
506 { 0x000000da, 0x00000012 },
507 { 0x00800000, 0x00000006 },
508 { 0x0080751d, 0x00000006 },
509 { 0x000025bb, 0x00000002 },
510 { 0x000040d4, 0x00000004 },
511 { 0x0000775c, 0x00000002 },
512 { 0x00a05000, 0x00000002 },
513 { 0x00661000, 0x00000002 },
514 { 0x0460275d, 0x00000020 },
515 { 0x00004000, 0000000000 },
516 { 0x00007999, 0x00000002 },
517 { 0x00a05000, 0x00000002 },
518 { 0x00661000, 0x00000002 },
519 { 0x0460299b, 0x00000020 },
520 { 0x00004000, 0000000000 },
521 { 0x01e00830, 0x00000002 },
522 { 0x21007000, 0000000000 },
523 { 0x00005000, 0x00000002 },
524 { 0x00038056, 0x00000002 },
525 { 0x040025e0, 0x00000002 },
526 { 0x000075e1, 0000000000 },
527 { 0x00000001, 0000000000 },
528 { 0x000380ed, 0x00000002 },
529 { 0x04007394, 0000000000 },
530 { 0000000000, 0000000000 },
531 { 0000000000, 0000000000 },
532 { 0x000078c4, 0x00000002 },
533 { 0x000078c5, 0x00000002 },
534 { 0x000078c6, 0x00000002 },
535 { 0x00007924, 0x00000002 },
536 { 0x00007925, 0x00000002 },
537 { 0x00007926, 0x00000002 },
538 { 0x000000f2, 0x00000004 },
539 { 0x00007924, 0x00000002 },
540 { 0x00007925, 0x00000002 },
541 { 0x00007926, 0x00000002 },
542 { 0x000000f9, 0x00000004 },
543 { 0000000000, 0000000000 },
544 { 0000000000, 0000000000 },
545 { 0000000000, 0000000000 },
546};
547
548static const u32 R300_cp_microcode[][2] = {
549 { 0x4200e000, 0000000000 },
550 { 0x4000e000, 0000000000 },
551 { 0x000000ae, 0x00000008 },
552 { 0x000000b2, 0x00000008 },
553 { 0x67554b4a, 0000000000 },
554 { 0x4a4a4475, 0000000000 },
555 { 0x55527d83, 0000000000 },
556 { 0x4a8c8b65, 0000000000 },
557 { 0x4aef4af6, 0000000000 },
558 { 0x4ae14a4a, 0000000000 },
559 { 0xe4979797, 0000000000 },
560 { 0xdb4aebdd, 0000000000 },
561 { 0x9ccc4a4a, 0000000000 },
562 { 0xd1989898, 0000000000 },
563 { 0x4a0f9ad6, 0000000000 },
564 { 0x000ca000, 0x00000004 },
565 { 0x000d0012, 0x00000038 },
566 { 0x0000e8b4, 0x00000004 },
567 { 0x000d0014, 0x00000038 },
568 { 0x0000e8b6, 0x00000004 },
569 { 0x000d0016, 0x00000038 },
570 { 0x0000e854, 0x00000004 },
571 { 0x000d0018, 0x00000038 },
572 { 0x0000e855, 0x00000004 },
573 { 0x000d001a, 0x00000038 },
574 { 0x0000e856, 0x00000004 },
575 { 0x000d001c, 0x00000038 },
576 { 0x0000e857, 0x00000004 },
577 { 0x000d001e, 0x00000038 },
578 { 0x0000e824, 0x00000004 },
579 { 0x000d0020, 0x00000038 },
580 { 0x0000e825, 0x00000004 },
581 { 0x000d0022, 0x00000038 },
582 { 0x0000e830, 0x00000004 },
583 { 0x000d0024, 0x00000038 },
584 { 0x0000f0c0, 0x00000004 },
585 { 0x000d0026, 0x00000038 },
586 { 0x0000f0c1, 0x00000004 },
587 { 0x000d0028, 0x00000038 },
588 { 0x0000f041, 0x00000004 },
589 { 0x000d002a, 0x00000038 },
590 { 0x0000f184, 0x00000004 },
591 { 0x000d002c, 0x00000038 },
592 { 0x0000f185, 0x00000004 },
593 { 0x000d002e, 0x00000038 },
594 { 0x0000f186, 0x00000004 },
595 { 0x000d0030, 0x00000038 },
596 { 0x0000f187, 0x00000004 },
597 { 0x000d0032, 0x00000038 },
598 { 0x0000f180, 0x00000004 },
599 { 0x000d0034, 0x00000038 },
600 { 0x0000f393, 0x00000004 },
601 { 0x000d0036, 0x00000038 },
602 { 0x0000f38a, 0x00000004 },
603 { 0x000d0038, 0x00000038 },
604 { 0x0000f38e, 0x00000004 },
605 { 0x0000e821, 0x00000004 },
606 { 0x0140a000, 0x00000004 },
607 { 0x00000043, 0x00000018 },
608 { 0x00cce800, 0x00000004 },
609 { 0x001b0001, 0x00000004 },
610 { 0x08004800, 0x00000004 },
611 { 0x001b0001, 0x00000004 },
612 { 0x08004800, 0x00000004 },
613 { 0x001b0001, 0x00000004 },
614 { 0x08004800, 0x00000004 },
615 { 0x0000003a, 0x00000008 },
616 { 0x0000a000, 0000000000 },
617 { 0x2000451d, 0x00000004 },
618 { 0x0000e580, 0x00000004 },
619 { 0x000ce581, 0x00000004 },
620 { 0x08004580, 0x00000004 },
621 { 0x000ce581, 0x00000004 },
622 { 0x00000047, 0x00000008 },
623 { 0x0000a000, 0000000000 },
624 { 0x000c2000, 0x00000004 },
625 { 0x0000e50e, 0x00000004 },
626 { 0x00032000, 0x00000004 },
627 { 0x00022051, 0x00000028 },
628 { 0x00000051, 0x00000024 },
629 { 0x0800450f, 0x00000004 },
630 { 0x0000a04b, 0x00000008 },
631 { 0x0000e565, 0x00000004 },
632 { 0x0000e566, 0x00000004 },
633 { 0x00000052, 0x00000008 },
634 { 0x03cca5b4, 0x00000004 },
635 { 0x05432000, 0x00000004 },
636 { 0x00022000, 0x00000004 },
637 { 0x4ccce05e, 0x00000030 },
638 { 0x08274565, 0x00000004 },
639 { 0x0000005e, 0x00000030 },
640 { 0x08004564, 0x00000004 },
641 { 0x0000e566, 0x00000004 },
642 { 0x00000055, 0x00000008 },
643 { 0x00802061, 0x00000010 },
644 { 0x00202000, 0x00000004 },
645 { 0x001b00ff, 0x00000004 },
646 { 0x01000064, 0x00000010 },
647 { 0x001f2000, 0x00000004 },
648 { 0x001c00ff, 0x00000004 },
649 { 0000000000, 0x0000000c },
650 { 0x00000080, 0x00000030 },
651 { 0x00000055, 0x00000008 },
652 { 0x0000e576, 0x00000004 },
653 { 0x000ca000, 0x00000004 },
654 { 0x00012000, 0x00000004 },
655 { 0x00082000, 0x00000004 },
656 { 0x1800650e, 0x00000004 },
657 { 0x00092000, 0x00000004 },
658 { 0x000a2000, 0x00000004 },
659 { 0x000f0000, 0x00000004 },
660 { 0x00400000, 0x00000004 },
661 { 0x00000074, 0x00000018 },
662 { 0x0000e563, 0x00000004 },
663 { 0x00c0e5f9, 0x000000c2 },
664 { 0x00000069, 0x00000008 },
665 { 0x0000a069, 0x00000008 },
666 { 0x0000e576, 0x00000004 },
667 { 0x0000e577, 0x00000004 },
668 { 0x0000e50e, 0x00000004 },
669 { 0x0000e50f, 0x00000004 },
670 { 0x0140a000, 0x00000004 },
671 { 0x00000077, 0x00000018 },
672 { 0x00c0e5f9, 0x000000c2 },
673 { 0x00000077, 0x00000008 },
674 { 0x0014e50e, 0x00000004 },
675 { 0x0040e50f, 0x00000004 },
676 { 0x00c0007a, 0x00000008 },
677 { 0x0000e570, 0x00000004 },
678 { 0x0000e571, 0x00000004 },
679 { 0x0000e572, 0x0000000c },
680 { 0x0000a000, 0x00000004 },
681 { 0x0140a000, 0x00000004 },
682 { 0x0000e568, 0x00000004 },
683 { 0x000c2000, 0x00000004 },
684 { 0x00000084, 0x00000018 },
685 { 0x000b0000, 0x00000004 },
686 { 0x18c0e562, 0x00000004 },
687 { 0x00000086, 0x00000008 },
688 { 0x00c00085, 0x00000008 },
689 { 0x000700e3, 0x00000004 },
690 { 0x00000092, 0x00000038 },
691 { 0x000ca094, 0x00000030 },
692 { 0x080045bb, 0x00000004 },
693 { 0x000c2095, 0x00000030 },
694 { 0x0800e5bc, 0000000000 },
695 { 0x0000e5bb, 0x00000004 },
696 { 0x0000e5bc, 0000000000 },
697 { 0x00120000, 0x0000000c },
698 { 0x00120000, 0x00000004 },
699 { 0x001b0002, 0x0000000c },
700 { 0x0000a000, 0x00000004 },
701 { 0x0000e821, 0x00000004 },
702 { 0x0000e800, 0000000000 },
703 { 0x0000e821, 0x00000004 },
704 { 0x0000e82e, 0000000000 },
705 { 0x02cca000, 0x00000004 },
706 { 0x00140000, 0x00000004 },
707 { 0x000ce1cc, 0x00000004 },
708 { 0x050de1cd, 0x00000004 },
709 { 0x00400000, 0x00000004 },
710 { 0x000000a4, 0x00000018 },
711 { 0x00c0a000, 0x00000004 },
712 { 0x000000a1, 0x00000008 },
713 { 0x000000a6, 0x00000020 },
714 { 0x4200e000, 0000000000 },
715 { 0x000000ad, 0x00000038 },
716 { 0x000ca000, 0x00000004 },
717 { 0x00140000, 0x00000004 },
718 { 0x000c2000, 0x00000004 },
719 { 0x00160000, 0x00000004 },
720 { 0x700ce000, 0x00000004 },
721 { 0x001400a9, 0x00000008 },
722 { 0x4000e000, 0000000000 },
723 { 0x02400000, 0x00000004 },
724 { 0x400ee000, 0x00000004 },
725 { 0x02400000, 0x00000004 },
726 { 0x4000e000, 0000000000 },
727 { 0x000c2000, 0x00000004 },
728 { 0x0240e51b, 0x00000004 },
729 { 0x0080e50a, 0x00000005 },
730 { 0x0080e50b, 0x00000005 },
731 { 0x00220000, 0x00000004 },
732 { 0x000700e3, 0x00000004 },
733 { 0x000000c0, 0x00000038 },
734 { 0x000c2095, 0x00000030 },
735 { 0x0880e5bd, 0x00000005 },
736 { 0x000c2094, 0x00000030 },
737 { 0x0800e5bb, 0x00000005 },
738 { 0x000c2095, 0x00000030 },
739 { 0x0880e5bc, 0x00000005 },
740 { 0x000000c3, 0x00000008 },
741 { 0x0080e5bd, 0x00000005 },
742 { 0x0000e5bb, 0x00000005 },
743 { 0x0080e5bc, 0x00000005 },
744 { 0x00210000, 0x00000004 },
745 { 0x02800000, 0x00000004 },
746 { 0x00c000c7, 0x00000018 },
747 { 0x4180e000, 0x00000040 },
748 { 0x000000c9, 0x00000024 },
749 { 0x01000000, 0x0000000c },
750 { 0x0100e51d, 0x0000000c },
751 { 0x000045bb, 0x00000004 },
752 { 0x000080c3, 0x00000008 },
753 { 0x0000f3ce, 0x00000004 },
754 { 0x0140a000, 0x00000004 },
755 { 0x00cc2000, 0x00000004 },
756 { 0x08c053cf, 0x00000040 },
757 { 0x00008000, 0000000000 },
758 { 0x0000f3d2, 0x00000004 },
759 { 0x0140a000, 0x00000004 },
760 { 0x00cc2000, 0x00000004 },
761 { 0x08c053d3, 0x00000040 },
762 { 0x00008000, 0000000000 },
763 { 0x0000f39d, 0x00000004 },
764 { 0x0140a000, 0x00000004 },
765 { 0x00cc2000, 0x00000004 },
766 { 0x08c0539e, 0x00000040 },
767 { 0x00008000, 0000000000 },
768 { 0x03c00830, 0x00000004 },
769 { 0x4200e000, 0000000000 },
770 { 0x0000a000, 0x00000004 },
771 { 0x200045e0, 0x00000004 },
772 { 0x0000e5e1, 0000000000 },
773 { 0x00000001, 0000000000 },
774 { 0x000700e0, 0x00000004 },
775 { 0x0800e394, 0000000000 },
776 { 0000000000, 0000000000 },
777 { 0x0000e8c4, 0x00000004 },
778 { 0x0000e8c5, 0x00000004 },
779 { 0x0000e8c6, 0x00000004 },
780 { 0x0000e928, 0x00000004 },
781 { 0x0000e929, 0x00000004 },
782 { 0x0000e92a, 0x00000004 },
783 { 0x000000e4, 0x00000008 },
784 { 0x0000e928, 0x00000004 },
785 { 0x0000e929, 0x00000004 },
786 { 0x0000e92a, 0x00000004 },
787 { 0x000000eb, 0x00000008 },
788 { 0x02c02000, 0x00000004 },
789 { 0x00060000, 0x00000004 },
790 { 0x000000f3, 0x00000034 },
791 { 0x000000f0, 0x00000008 },
792 { 0x00008000, 0x00000004 },
793 { 0xc000e000, 0000000000 },
794 { 0000000000, 0000000000 },
795 { 0x000c2000, 0x00000004 },
796 { 0x001d0018, 0x00000004 },
797 { 0x001a0001, 0x00000004 },
798 { 0x000000fb, 0x00000034 },
799 { 0x0000004a, 0x00000008 },
800 { 0x0500a04a, 0x00000008 },
801 { 0000000000, 0000000000 },
802 { 0000000000, 0000000000 },
803 { 0000000000, 0000000000 },
804 { 0000000000, 0000000000 },
805};
806
807static const u32 R420_cp_microcode[][2] = {
808 { 0x4200e000, 0000000000 },
809 { 0x4000e000, 0000000000 },
810 { 0x00000099, 0x00000008 },
811 { 0x0000009d, 0x00000008 },
812 { 0x4a554b4a, 0000000000 },
813 { 0x4a4a4467, 0000000000 },
814 { 0x55526f75, 0000000000 },
815 { 0x4a7e7d65, 0000000000 },
816 { 0xd9d3dff6, 0000000000 },
817 { 0x4ac54a4a, 0000000000 },
818 { 0xc8828282, 0000000000 },
819 { 0xbf4acfc1, 0000000000 },
820 { 0x87b04a4a, 0000000000 },
821 { 0xb5838383, 0000000000 },
822 { 0x4a0f85ba, 0000000000 },
823 { 0x000ca000, 0x00000004 },
824 { 0x000d0012, 0x00000038 },
825 { 0x0000e8b4, 0x00000004 },
826 { 0x000d0014, 0x00000038 },
827 { 0x0000e8b6, 0x00000004 },
828 { 0x000d0016, 0x00000038 },
829 { 0x0000e854, 0x00000004 },
830 { 0x000d0018, 0x00000038 },
831 { 0x0000e855, 0x00000004 },
832 { 0x000d001a, 0x00000038 },
833 { 0x0000e856, 0x00000004 },
834 { 0x000d001c, 0x00000038 },
835 { 0x0000e857, 0x00000004 },
836 { 0x000d001e, 0x00000038 },
837 { 0x0000e824, 0x00000004 },
838 { 0x000d0020, 0x00000038 },
839 { 0x0000e825, 0x00000004 },
840 { 0x000d0022, 0x00000038 },
841 { 0x0000e830, 0x00000004 },
842 { 0x000d0024, 0x00000038 },
843 { 0x0000f0c0, 0x00000004 },
844 { 0x000d0026, 0x00000038 },
845 { 0x0000f0c1, 0x00000004 },
846 { 0x000d0028, 0x00000038 },
847 { 0x0000f041, 0x00000004 },
848 { 0x000d002a, 0x00000038 },
849 { 0x0000f184, 0x00000004 },
850 { 0x000d002c, 0x00000038 },
851 { 0x0000f185, 0x00000004 },
852 { 0x000d002e, 0x00000038 },
853 { 0x0000f186, 0x00000004 },
854 { 0x000d0030, 0x00000038 },
855 { 0x0000f187, 0x00000004 },
856 { 0x000d0032, 0x00000038 },
857 { 0x0000f180, 0x00000004 },
858 { 0x000d0034, 0x00000038 },
859 { 0x0000f393, 0x00000004 },
860 { 0x000d0036, 0x00000038 },
861 { 0x0000f38a, 0x00000004 },
862 { 0x000d0038, 0x00000038 },
863 { 0x0000f38e, 0x00000004 },
864 { 0x0000e821, 0x00000004 },
865 { 0x0140a000, 0x00000004 },
866 { 0x00000043, 0x00000018 },
867 { 0x00cce800, 0x00000004 },
868 { 0x001b0001, 0x00000004 },
869 { 0x08004800, 0x00000004 },
870 { 0x001b0001, 0x00000004 },
871 { 0x08004800, 0x00000004 },
872 { 0x001b0001, 0x00000004 },
873 { 0x08004800, 0x00000004 },
874 { 0x0000003a, 0x00000008 },
875 { 0x0000a000, 0000000000 },
876 { 0x2000451d, 0x00000004 },
877 { 0x0000e580, 0x00000004 },
878 { 0x000ce581, 0x00000004 },
879 { 0x08004580, 0x00000004 },
880 { 0x000ce581, 0x00000004 },
881 { 0x00000047, 0x00000008 },
882 { 0x0000a000, 0000000000 },
883 { 0x000c2000, 0x00000004 },
884 { 0x0000e50e, 0x00000004 },
885 { 0x00032000, 0x00000004 },
886 { 0x00022051, 0x00000028 },
887 { 0x00000051, 0x00000024 },
888 { 0x0800450f, 0x00000004 },
889 { 0x0000a04b, 0x00000008 },
890 { 0x0000e565, 0x00000004 },
891 { 0x0000e566, 0x00000004 },
892 { 0x00000052, 0x00000008 },
893 { 0x03cca5b4, 0x00000004 },
894 { 0x05432000, 0x00000004 },
895 { 0x00022000, 0x00000004 },
896 { 0x4ccce05e, 0x00000030 },
897 { 0x08274565, 0x00000004 },
898 { 0x0000005e, 0x00000030 },
899 { 0x08004564, 0x00000004 },
900 { 0x0000e566, 0x00000004 },
901 { 0x00000055, 0x00000008 },
902 { 0x00802061, 0x00000010 },
903 { 0x00202000, 0x00000004 },
904 { 0x001b00ff, 0x00000004 },
905 { 0x01000064, 0x00000010 },
906 { 0x001f2000, 0x00000004 },
907 { 0x001c00ff, 0x00000004 },
908 { 0000000000, 0x0000000c },
909 { 0x00000072, 0x00000030 },
910 { 0x00000055, 0x00000008 },
911 { 0x0000e576, 0x00000004 },
912 { 0x0000e577, 0x00000004 },
913 { 0x0000e50e, 0x00000004 },
914 { 0x0000e50f, 0x00000004 },
915 { 0x0140a000, 0x00000004 },
916 { 0x00000069, 0x00000018 },
917 { 0x00c0e5f9, 0x000000c2 },
918 { 0x00000069, 0x00000008 },
919 { 0x0014e50e, 0x00000004 },
920 { 0x0040e50f, 0x00000004 },
921 { 0x00c0006c, 0x00000008 },
922 { 0x0000e570, 0x00000004 },
923 { 0x0000e571, 0x00000004 },
924 { 0x0000e572, 0x0000000c },
925 { 0x0000a000, 0x00000004 },
926 { 0x0140a000, 0x00000004 },
927 { 0x0000e568, 0x00000004 },
928 { 0x000c2000, 0x00000004 },
929 { 0x00000076, 0x00000018 },
930 { 0x000b0000, 0x00000004 },
931 { 0x18c0e562, 0x00000004 },
932 { 0x00000078, 0x00000008 },
933 { 0x00c00077, 0x00000008 },
934 { 0x000700c7, 0x00000004 },
935 { 0x00000080, 0x00000038 },
936 { 0x0000e5bb, 0x00000004 },
937 { 0x0000e5bc, 0000000000 },
938 { 0x0000a000, 0x00000004 },
939 { 0x0000e821, 0x00000004 },
940 { 0x0000e800, 0000000000 },
941 { 0x0000e821, 0x00000004 },
942 { 0x0000e82e, 0000000000 },
943 { 0x02cca000, 0x00000004 },
944 { 0x00140000, 0x00000004 },
945 { 0x000ce1cc, 0x00000004 },
946 { 0x050de1cd, 0x00000004 },
947 { 0x00400000, 0x00000004 },
948 { 0x0000008f, 0x00000018 },
949 { 0x00c0a000, 0x00000004 },
950 { 0x0000008c, 0x00000008 },
951 { 0x00000091, 0x00000020 },
952 { 0x4200e000, 0000000000 },
953 { 0x00000098, 0x00000038 },
954 { 0x000ca000, 0x00000004 },
955 { 0x00140000, 0x00000004 },
956 { 0x000c2000, 0x00000004 },
957 { 0x00160000, 0x00000004 },
958 { 0x700ce000, 0x00000004 },
959 { 0x00140094, 0x00000008 },
960 { 0x4000e000, 0000000000 },
961 { 0x02400000, 0x00000004 },
962 { 0x400ee000, 0x00000004 },
963 { 0x02400000, 0x00000004 },
964 { 0x4000e000, 0000000000 },
965 { 0x000c2000, 0x00000004 },
966 { 0x0240e51b, 0x00000004 },
967 { 0x0080e50a, 0x00000005 },
968 { 0x0080e50b, 0x00000005 },
969 { 0x00220000, 0x00000004 },
970 { 0x000700c7, 0x00000004 },
971 { 0x000000a4, 0x00000038 },
972 { 0x0080e5bd, 0x00000005 },
973 { 0x0000e5bb, 0x00000005 },
974 { 0x0080e5bc, 0x00000005 },
975 { 0x00210000, 0x00000004 },
976 { 0x02800000, 0x00000004 },
977 { 0x00c000ab, 0x00000018 },
978 { 0x4180e000, 0x00000040 },
979 { 0x000000ad, 0x00000024 },
980 { 0x01000000, 0x0000000c },
981 { 0x0100e51d, 0x0000000c },
982 { 0x000045bb, 0x00000004 },
983 { 0x000080a7, 0x00000008 },
984 { 0x0000f3ce, 0x00000004 },
985 { 0x0140a000, 0x00000004 },
986 { 0x00cc2000, 0x00000004 },
987 { 0x08c053cf, 0x00000040 },
988 { 0x00008000, 0000000000 },
989 { 0x0000f3d2, 0x00000004 },
990 { 0x0140a000, 0x00000004 },
991 { 0x00cc2000, 0x00000004 },
992 { 0x08c053d3, 0x00000040 },
993 { 0x00008000, 0000000000 },
994 { 0x0000f39d, 0x00000004 },
995 { 0x0140a000, 0x00000004 },
996 { 0x00cc2000, 0x00000004 },
997 { 0x08c0539e, 0x00000040 },
998 { 0x00008000, 0000000000 },
999 { 0x03c00830, 0x00000004 },
1000 { 0x4200e000, 0000000000 },
1001 { 0x0000a000, 0x00000004 },
1002 { 0x200045e0, 0x00000004 },
1003 { 0x0000e5e1, 0000000000 },
1004 { 0x00000001, 0000000000 },
1005 { 0x000700c4, 0x00000004 },
1006 { 0x0800e394, 0000000000 },
1007 { 0000000000, 0000000000 },
1008 { 0x0000e8c4, 0x00000004 },
1009 { 0x0000e8c5, 0x00000004 },
1010 { 0x0000e8c6, 0x00000004 },
1011 { 0x0000e928, 0x00000004 },
1012 { 0x0000e929, 0x00000004 },
1013 { 0x0000e92a, 0x00000004 },
1014 { 0x000000c8, 0x00000008 },
1015 { 0x0000e928, 0x00000004 },
1016 { 0x0000e929, 0x00000004 },
1017 { 0x0000e92a, 0x00000004 },
1018 { 0x000000cf, 0x00000008 },
1019 { 0x02c02000, 0x00000004 },
1020 { 0x00060000, 0x00000004 },
1021 { 0x000000d7, 0x00000034 },
1022 { 0x000000d4, 0x00000008 },
1023 { 0x00008000, 0x00000004 },
1024 { 0xc000e000, 0000000000 },
1025 { 0x0000e1cc, 0x00000004 },
1026 { 0x0500e1cd, 0x00000004 },
1027 { 0x000ca000, 0x00000004 },
1028 { 0x000000de, 0x00000034 },
1029 { 0x000000da, 0x00000008 },
1030 { 0x0000a000, 0000000000 },
1031 { 0x0019e1cc, 0x00000004 },
1032 { 0x001b0001, 0x00000004 },
1033 { 0x0500a000, 0x00000004 },
1034 { 0x080041cd, 0x00000004 },
1035 { 0x000ca000, 0x00000004 },
1036 { 0x000000fb, 0x00000034 },
1037 { 0x0000004a, 0x00000008 },
1038 { 0000000000, 0000000000 },
1039 { 0000000000, 0000000000 },
1040 { 0000000000, 0000000000 },
1041 { 0000000000, 0000000000 },
1042 { 0000000000, 0000000000 },
1043 { 0000000000, 0000000000 },
1044 { 0000000000, 0000000000 },
1045 { 0000000000, 0000000000 },
1046 { 0000000000, 0000000000 },
1047 { 0000000000, 0000000000 },
1048 { 0000000000, 0000000000 },
1049 { 0000000000, 0000000000 },
1050 { 0000000000, 0000000000 },
1051 { 0000000000, 0000000000 },
1052 { 0000000000, 0000000000 },
1053 { 0000000000, 0000000000 },
1054 { 0x000c2000, 0x00000004 },
1055 { 0x001d0018, 0x00000004 },
1056 { 0x001a0001, 0x00000004 },
1057 { 0x000000fb, 0x00000034 },
1058 { 0x0000004a, 0x00000008 },
1059 { 0x0500a04a, 0x00000008 },
1060 { 0000000000, 0000000000 },
1061 { 0000000000, 0000000000 },
1062 { 0000000000, 0000000000 },
1063 { 0000000000, 0000000000 },
1064};
1065
1066static const u32 RS600_cp_microcode[][2] = {
1067 { 0x4200e000, 0000000000 },
1068 { 0x4000e000, 0000000000 },
1069 { 0x000000a0, 0x00000008 },
1070 { 0x000000a4, 0x00000008 },
1071 { 0x4a554b4a, 0000000000 },
1072 { 0x4a4a4467, 0000000000 },
1073 { 0x55526f75, 0000000000 },
1074 { 0x4a7e7d65, 0000000000 },
1075 { 0x4ae74af6, 0000000000 },
1076 { 0x4ad34a4a, 0000000000 },
1077 { 0xd6898989, 0000000000 },
1078 { 0xcd4addcf, 0000000000 },
1079 { 0x8ebe4ae2, 0000000000 },
1080 { 0xc38a8a8a, 0000000000 },
1081 { 0x4a0f8cc8, 0000000000 },
1082 { 0x000ca000, 0x00000004 },
1083 { 0x000d0012, 0x00000038 },
1084 { 0x0000e8b4, 0x00000004 },
1085 { 0x000d0014, 0x00000038 },
1086 { 0x0000e8b6, 0x00000004 },
1087 { 0x000d0016, 0x00000038 },
1088 { 0x0000e854, 0x00000004 },
1089 { 0x000d0018, 0x00000038 },
1090 { 0x0000e855, 0x00000004 },
1091 { 0x000d001a, 0x00000038 },
1092 { 0x0000e856, 0x00000004 },
1093 { 0x000d001c, 0x00000038 },
1094 { 0x0000e857, 0x00000004 },
1095 { 0x000d001e, 0x00000038 },
1096 { 0x0000e824, 0x00000004 },
1097 { 0x000d0020, 0x00000038 },
1098 { 0x0000e825, 0x00000004 },
1099 { 0x000d0022, 0x00000038 },
1100 { 0x0000e830, 0x00000004 },
1101 { 0x000d0024, 0x00000038 },
1102 { 0x0000f0c0, 0x00000004 },
1103 { 0x000d0026, 0x00000038 },
1104 { 0x0000f0c1, 0x00000004 },
1105 { 0x000d0028, 0x00000038 },
1106 { 0x0000f041, 0x00000004 },
1107 { 0x000d002a, 0x00000038 },
1108 { 0x0000f184, 0x00000004 },
1109 { 0x000d002c, 0x00000038 },
1110 { 0x0000f185, 0x00000004 },
1111 { 0x000d002e, 0x00000038 },
1112 { 0x0000f186, 0x00000004 },
1113 { 0x000d0030, 0x00000038 },
1114 { 0x0000f187, 0x00000004 },
1115 { 0x000d0032, 0x00000038 },
1116 { 0x0000f180, 0x00000004 },
1117 { 0x000d0034, 0x00000038 },
1118 { 0x0000f393, 0x00000004 },
1119 { 0x000d0036, 0x00000038 },
1120 { 0x0000f38a, 0x00000004 },
1121 { 0x000d0038, 0x00000038 },
1122 { 0x0000f38e, 0x00000004 },
1123 { 0x0000e821, 0x00000004 },
1124 { 0x0140a000, 0x00000004 },
1125 { 0x00000043, 0x00000018 },
1126 { 0x00cce800, 0x00000004 },
1127 { 0x001b0001, 0x00000004 },
1128 { 0x08004800, 0x00000004 },
1129 { 0x001b0001, 0x00000004 },
1130 { 0x08004800, 0x00000004 },
1131 { 0x001b0001, 0x00000004 },
1132 { 0x08004800, 0x00000004 },
1133 { 0x0000003a, 0x00000008 },
1134 { 0x0000a000, 0000000000 },
1135 { 0x2000451d, 0x00000004 },
1136 { 0x0000e580, 0x00000004 },
1137 { 0x000ce581, 0x00000004 },
1138 { 0x08004580, 0x00000004 },
1139 { 0x000ce581, 0x00000004 },
1140 { 0x00000047, 0x00000008 },
1141 { 0x0000a000, 0000000000 },
1142 { 0x000c2000, 0x00000004 },
1143 { 0x0000e50e, 0x00000004 },
1144 { 0x00032000, 0x00000004 },
1145 { 0x00022051, 0x00000028 },
1146 { 0x00000051, 0x00000024 },
1147 { 0x0800450f, 0x00000004 },
1148 { 0x0000a04b, 0x00000008 },
1149 { 0x0000e565, 0x00000004 },
1150 { 0x0000e566, 0x00000004 },
1151 { 0x00000052, 0x00000008 },
1152 { 0x03cca5b4, 0x00000004 },
1153 { 0x05432000, 0x00000004 },
1154 { 0x00022000, 0x00000004 },
1155 { 0x4ccce05e, 0x00000030 },
1156 { 0x08274565, 0x00000004 },
1157 { 0x0000005e, 0x00000030 },
1158 { 0x08004564, 0x00000004 },
1159 { 0x0000e566, 0x00000004 },
1160 { 0x00000055, 0x00000008 },
1161 { 0x00802061, 0x00000010 },
1162 { 0x00202000, 0x00000004 },
1163 { 0x001b00ff, 0x00000004 },
1164 { 0x01000064, 0x00000010 },
1165 { 0x001f2000, 0x00000004 },
1166 { 0x001c00ff, 0x00000004 },
1167 { 0000000000, 0x0000000c },
1168 { 0x00000072, 0x00000030 },
1169 { 0x00000055, 0x00000008 },
1170 { 0x0000e576, 0x00000004 },
1171 { 0x0000e577, 0x00000004 },
1172 { 0x0000e50e, 0x00000004 },
1173 { 0x0000e50f, 0x00000004 },
1174 { 0x0140a000, 0x00000004 },
1175 { 0x00000069, 0x00000018 },
1176 { 0x00c0e5f9, 0x000000c2 },
1177 { 0x00000069, 0x00000008 },
1178 { 0x0014e50e, 0x00000004 },
1179 { 0x0040e50f, 0x00000004 },
1180 { 0x00c0006c, 0x00000008 },
1181 { 0x0000e570, 0x00000004 },
1182 { 0x0000e571, 0x00000004 },
1183 { 0x0000e572, 0x0000000c },
1184 { 0x0000a000, 0x00000004 },
1185 { 0x0140a000, 0x00000004 },
1186 { 0x0000e568, 0x00000004 },
1187 { 0x000c2000, 0x00000004 },
1188 { 0x00000076, 0x00000018 },
1189 { 0x000b0000, 0x00000004 },
1190 { 0x18c0e562, 0x00000004 },
1191 { 0x00000078, 0x00000008 },
1192 { 0x00c00077, 0x00000008 },
1193 { 0x000700d5, 0x00000004 },
1194 { 0x00000084, 0x00000038 },
1195 { 0x000ca086, 0x00000030 },
1196 { 0x080045bb, 0x00000004 },
1197 { 0x000c2087, 0x00000030 },
1198 { 0x0800e5bc, 0000000000 },
1199 { 0x0000e5bb, 0x00000004 },
1200 { 0x0000e5bc, 0000000000 },
1201 { 0x00120000, 0x0000000c },
1202 { 0x00120000, 0x00000004 },
1203 { 0x001b0002, 0x0000000c },
1204 { 0x0000a000, 0x00000004 },
1205 { 0x0000e821, 0x00000004 },
1206 { 0x0000e800, 0000000000 },
1207 { 0x0000e821, 0x00000004 },
1208 { 0x0000e82e, 0000000000 },
1209 { 0x02cca000, 0x00000004 },
1210 { 0x00140000, 0x00000004 },
1211 { 0x000ce1cc, 0x00000004 },
1212 { 0x050de1cd, 0x00000004 },
1213 { 0x00400000, 0x00000004 },
1214 { 0x00000096, 0x00000018 },
1215 { 0x00c0a000, 0x00000004 },
1216 { 0x00000093, 0x00000008 },
1217 { 0x00000098, 0x00000020 },
1218 { 0x4200e000, 0000000000 },
1219 { 0x0000009f, 0x00000038 },
1220 { 0x000ca000, 0x00000004 },
1221 { 0x00140000, 0x00000004 },
1222 { 0x000c2000, 0x00000004 },
1223 { 0x00160000, 0x00000004 },
1224 { 0x700ce000, 0x00000004 },
1225 { 0x0014009b, 0x00000008 },
1226 { 0x4000e000, 0000000000 },
1227 { 0x02400000, 0x00000004 },
1228 { 0x400ee000, 0x00000004 },
1229 { 0x02400000, 0x00000004 },
1230 { 0x4000e000, 0000000000 },
1231 { 0x000c2000, 0x00000004 },
1232 { 0x0240e51b, 0x00000004 },
1233 { 0x0080e50a, 0x00000005 },
1234 { 0x0080e50b, 0x00000005 },
1235 { 0x00220000, 0x00000004 },
1236 { 0x000700d5, 0x00000004 },
1237 { 0x000000b2, 0x00000038 },
1238 { 0x000c2087, 0x00000030 },
1239 { 0x0880e5bd, 0x00000005 },
1240 { 0x000c2086, 0x00000030 },
1241 { 0x0800e5bb, 0x00000005 },
1242 { 0x000c2087, 0x00000030 },
1243 { 0x0880e5bc, 0x00000005 },
1244 { 0x000000b5, 0x00000008 },
1245 { 0x0080e5bd, 0x00000005 },
1246 { 0x0000e5bb, 0x00000005 },
1247 { 0x0080e5bc, 0x00000005 },
1248 { 0x00210000, 0x00000004 },
1249 { 0x02800000, 0x00000004 },
1250 { 0x00c000b9, 0x00000018 },
1251 { 0x4180e000, 0x00000040 },
1252 { 0x000000bb, 0x00000024 },
1253 { 0x01000000, 0x0000000c },
1254 { 0x0100e51d, 0x0000000c },
1255 { 0x000045bb, 0x00000004 },
1256 { 0x000080b5, 0x00000008 },
1257 { 0x0000f3ce, 0x00000004 },
1258 { 0x0140a000, 0x00000004 },
1259 { 0x00cc2000, 0x00000004 },
1260 { 0x08c053cf, 0x00000040 },
1261 { 0x00008000, 0000000000 },
1262 { 0x0000f3d2, 0x00000004 },
1263 { 0x0140a000, 0x00000004 },
1264 { 0x00cc2000, 0x00000004 },
1265 { 0x08c053d3, 0x00000040 },
1266 { 0x00008000, 0000000000 },
1267 { 0x0000f39d, 0x00000004 },
1268 { 0x0140a000, 0x00000004 },
1269 { 0x00cc2000, 0x00000004 },
1270 { 0x08c0539e, 0x00000040 },
1271 { 0x00008000, 0000000000 },
1272 { 0x03c00830, 0x00000004 },
1273 { 0x4200e000, 0000000000 },
1274 { 0x0000a000, 0x00000004 },
1275 { 0x200045e0, 0x00000004 },
1276 { 0x0000e5e1, 0000000000 },
1277 { 0x00000001, 0000000000 },
1278 { 0x000700d2, 0x00000004 },
1279 { 0x0800e394, 0000000000 },
1280 { 0000000000, 0000000000 },
1281 { 0x0000e8c4, 0x00000004 },
1282 { 0x0000e8c5, 0x00000004 },
1283 { 0x0000e8c6, 0x00000004 },
1284 { 0x0000e928, 0x00000004 },
1285 { 0x0000e929, 0x00000004 },
1286 { 0x0000e92a, 0x00000004 },
1287 { 0x000000d6, 0x00000008 },
1288 { 0x0000e928, 0x00000004 },
1289 { 0x0000e929, 0x00000004 },
1290 { 0x0000e92a, 0x00000004 },
1291 { 0x000000dd, 0x00000008 },
1292 { 0x00e00116, 0000000000 },
1293 { 0x000700e1, 0x00000004 },
1294 { 0x0800401c, 0x00000004 },
1295 { 0x200050e7, 0x00000004 },
1296 { 0x0000e01d, 0x00000004 },
1297 { 0x000000e4, 0x00000008 },
1298 { 0x02c02000, 0x00000004 },
1299 { 0x00060000, 0x00000004 },
1300 { 0x000000eb, 0x00000034 },
1301 { 0x000000e8, 0x00000008 },
1302 { 0x00008000, 0x00000004 },
1303 { 0xc000e000, 0000000000 },
1304 { 0000000000, 0000000000 },
1305 { 0000000000, 0000000000 },
1306 { 0000000000, 0000000000 },
1307 { 0000000000, 0000000000 },
1308 { 0000000000, 0000000000 },
1309 { 0000000000, 0000000000 },
1310 { 0000000000, 0000000000 },
1311 { 0000000000, 0000000000 },
1312 { 0000000000, 0000000000 },
1313 { 0x000c2000, 0x00000004 },
1314 { 0x001d0018, 0x00000004 },
1315 { 0x001a0001, 0x00000004 },
1316 { 0x000000fb, 0x00000034 },
1317 { 0x0000004a, 0x00000008 },
1318 { 0x0500a04a, 0x00000008 },
1319 { 0000000000, 0000000000 },
1320 { 0000000000, 0000000000 },
1321 { 0000000000, 0000000000 },
1322 { 0000000000, 0000000000 },
1323};
1324
1325static const u32 RS690_cp_microcode[][2] = {
1326 { 0x000000dd, 0x00000008 },
1327 { 0x000000df, 0x00000008 },
1328 { 0x000000a0, 0x00000008 },
1329 { 0x000000a4, 0x00000008 },
1330 { 0x4a554b4a, 0000000000 },
1331 { 0x4a4a4467, 0000000000 },
1332 { 0x55526f75, 0000000000 },
1333 { 0x4a7e7d65, 0000000000 },
1334 { 0x4ad74af6, 0000000000 },
1335 { 0x4ac94a4a, 0000000000 },
1336 { 0xcc898989, 0000000000 },
1337 { 0xc34ad3c5, 0000000000 },
1338 { 0x8e4a4a4a, 0000000000 },
1339 { 0x4a8a8a8a, 0000000000 },
1340 { 0x4a0f8c4a, 0000000000 },
1341 { 0x000ca000, 0x00000004 },
1342 { 0x000d0012, 0x00000038 },
1343 { 0x0000e8b4, 0x00000004 },
1344 { 0x000d0014, 0x00000038 },
1345 { 0x0000e8b6, 0x00000004 },
1346 { 0x000d0016, 0x00000038 },
1347 { 0x0000e854, 0x00000004 },
1348 { 0x000d0018, 0x00000038 },
1349 { 0x0000e855, 0x00000004 },
1350 { 0x000d001a, 0x00000038 },
1351 { 0x0000e856, 0x00000004 },
1352 { 0x000d001c, 0x00000038 },
1353 { 0x0000e857, 0x00000004 },
1354 { 0x000d001e, 0x00000038 },
1355 { 0x0000e824, 0x00000004 },
1356 { 0x000d0020, 0x00000038 },
1357 { 0x0000e825, 0x00000004 },
1358 { 0x000d0022, 0x00000038 },
1359 { 0x0000e830, 0x00000004 },
1360 { 0x000d0024, 0x00000038 },
1361 { 0x0000f0c0, 0x00000004 },
1362 { 0x000d0026, 0x00000038 },
1363 { 0x0000f0c1, 0x00000004 },
1364 { 0x000d0028, 0x00000038 },
1365 { 0x0000f041, 0x00000004 },
1366 { 0x000d002a, 0x00000038 },
1367 { 0x0000f184, 0x00000004 },
1368 { 0x000d002c, 0x00000038 },
1369 { 0x0000f185, 0x00000004 },
1370 { 0x000d002e, 0x00000038 },
1371 { 0x0000f186, 0x00000004 },
1372 { 0x000d0030, 0x00000038 },
1373 { 0x0000f187, 0x00000004 },
1374 { 0x000d0032, 0x00000038 },
1375 { 0x0000f180, 0x00000004 },
1376 { 0x000d0034, 0x00000038 },
1377 { 0x0000f393, 0x00000004 },
1378 { 0x000d0036, 0x00000038 },
1379 { 0x0000f38a, 0x00000004 },
1380 { 0x000d0038, 0x00000038 },
1381 { 0x0000f38e, 0x00000004 },
1382 { 0x0000e821, 0x00000004 },
1383 { 0x0140a000, 0x00000004 },
1384 { 0x00000043, 0x00000018 },
1385 { 0x00cce800, 0x00000004 },
1386 { 0x001b0001, 0x00000004 },
1387 { 0x08004800, 0x00000004 },
1388 { 0x001b0001, 0x00000004 },
1389 { 0x08004800, 0x00000004 },
1390 { 0x001b0001, 0x00000004 },
1391 { 0x08004800, 0x00000004 },
1392 { 0x0000003a, 0x00000008 },
1393 { 0x0000a000, 0000000000 },
1394 { 0x2000451d, 0x00000004 },
1395 { 0x0000e580, 0x00000004 },
1396 { 0x000ce581, 0x00000004 },
1397 { 0x08004580, 0x00000004 },
1398 { 0x000ce581, 0x00000004 },
1399 { 0x00000047, 0x00000008 },
1400 { 0x0000a000, 0000000000 },
1401 { 0x000c2000, 0x00000004 },
1402 { 0x0000e50e, 0x00000004 },
1403 { 0x00032000, 0x00000004 },
1404 { 0x00022051, 0x00000028 },
1405 { 0x00000051, 0x00000024 },
1406 { 0x0800450f, 0x00000004 },
1407 { 0x0000a04b, 0x00000008 },
1408 { 0x0000e565, 0x00000004 },
1409 { 0x0000e566, 0x00000004 },
1410 { 0x00000052, 0x00000008 },
1411 { 0x03cca5b4, 0x00000004 },
1412 { 0x05432000, 0x00000004 },
1413 { 0x00022000, 0x00000004 },
1414 { 0x4ccce05e, 0x00000030 },
1415 { 0x08274565, 0x00000004 },
1416 { 0x0000005e, 0x00000030 },
1417 { 0x08004564, 0x00000004 },
1418 { 0x0000e566, 0x00000004 },
1419 { 0x00000055, 0x00000008 },
1420 { 0x00802061, 0x00000010 },
1421 { 0x00202000, 0x00000004 },
1422 { 0x001b00ff, 0x00000004 },
1423 { 0x01000064, 0x00000010 },
1424 { 0x001f2000, 0x00000004 },
1425 { 0x001c00ff, 0x00000004 },
1426 { 0000000000, 0x0000000c },
1427 { 0x00000072, 0x00000030 },
1428 { 0x00000055, 0x00000008 },
1429 { 0x0000e576, 0x00000004 },
1430 { 0x0000e577, 0x00000004 },
1431 { 0x0000e50e, 0x00000004 },
1432 { 0x0000e50f, 0x00000004 },
1433 { 0x0140a000, 0x00000004 },
1434 { 0x00000069, 0x00000018 },
1435 { 0x00c0e5f9, 0x000000c2 },
1436 { 0x00000069, 0x00000008 },
1437 { 0x0014e50e, 0x00000004 },
1438 { 0x0040e50f, 0x00000004 },
1439 { 0x00c0006c, 0x00000008 },
1440 { 0x0000e570, 0x00000004 },
1441 { 0x0000e571, 0x00000004 },
1442 { 0x0000e572, 0x0000000c },
1443 { 0x0000a000, 0x00000004 },
1444 { 0x0140a000, 0x00000004 },
1445 { 0x0000e568, 0x00000004 },
1446 { 0x000c2000, 0x00000004 },
1447 { 0x00000076, 0x00000018 },
1448 { 0x000b0000, 0x00000004 },
1449 { 0x18c0e562, 0x00000004 },
1450 { 0x00000078, 0x00000008 },
1451 { 0x00c00077, 0x00000008 },
1452 { 0x000700cb, 0x00000004 },
1453 { 0x00000084, 0x00000038 },
1454 { 0x000ca086, 0x00000030 },
1455 { 0x080045bb, 0x00000004 },
1456 { 0x000c2087, 0x00000030 },
1457 { 0x0800e5bc, 0000000000 },
1458 { 0x0000e5bb, 0x00000004 },
1459 { 0x0000e5bc, 0000000000 },
1460 { 0x00120000, 0x0000000c },
1461 { 0x00120000, 0x00000004 },
1462 { 0x001b0002, 0x0000000c },
1463 { 0x0000a000, 0x00000004 },
1464 { 0x0000e821, 0x00000004 },
1465 { 0x0000e800, 0000000000 },
1466 { 0x0000e821, 0x00000004 },
1467 { 0x0000e82e, 0000000000 },
1468 { 0x02cca000, 0x00000004 },
1469 { 0x00140000, 0x00000004 },
1470 { 0x000ce1cc, 0x00000004 },
1471 { 0x050de1cd, 0x00000004 },
1472 { 0x00400000, 0x00000004 },
1473 { 0x00000096, 0x00000018 },
1474 { 0x00c0a000, 0x00000004 },
1475 { 0x00000093, 0x00000008 },
1476 { 0x00000098, 0x00000020 },
1477 { 0x4200e000, 0000000000 },
1478 { 0x0000009f, 0x00000038 },
1479 { 0x000ca000, 0x00000004 },
1480 { 0x00140000, 0x00000004 },
1481 { 0x000c2000, 0x00000004 },
1482 { 0x00160000, 0x00000004 },
1483 { 0x700ce000, 0x00000004 },
1484 { 0x0014009b, 0x00000008 },
1485 { 0x4000e000, 0000000000 },
1486 { 0x02400000, 0x00000004 },
1487 { 0x400ee000, 0x00000004 },
1488 { 0x02400000, 0x00000004 },
1489 { 0x4000e000, 0000000000 },
1490 { 0x00100000, 0x0000002c },
1491 { 0x00004000, 0000000000 },
1492 { 0x080045c8, 0x00000004 },
1493 { 0x00240005, 0x00000004 },
1494 { 0x08004d0b, 0x00000004 },
1495 { 0x000c2000, 0x00000004 },
1496 { 0x0240e51b, 0x00000004 },
1497 { 0x0080e50a, 0x00000005 },
1498 { 0x0080e50b, 0x00000005 },
1499 { 0x00220000, 0x00000004 },
1500 { 0x000700cb, 0x00000004 },
1501 { 0x000000b7, 0x00000038 },
1502 { 0x000c2087, 0x00000030 },
1503 { 0x0880e5bd, 0x00000005 },
1504 { 0x000c2086, 0x00000030 },
1505 { 0x0800e5bb, 0x00000005 },
1506 { 0x000c2087, 0x00000030 },
1507 { 0x0880e5bc, 0x00000005 },
1508 { 0x000000ba, 0x00000008 },
1509 { 0x0080e5bd, 0x00000005 },
1510 { 0x0000e5bb, 0x00000005 },
1511 { 0x0080e5bc, 0x00000005 },
1512 { 0x00210000, 0x00000004 },
1513 { 0x02800000, 0x00000004 },
1514 { 0x00c000be, 0x00000018 },
1515 { 0x4180e000, 0x00000040 },
1516 { 0x000000c0, 0x00000024 },
1517 { 0x01000000, 0x0000000c },
1518 { 0x0100e51d, 0x0000000c },
1519 { 0x000045bb, 0x00000004 },
1520 { 0x000080ba, 0x00000008 },
1521 { 0x03c00830, 0x00000004 },
1522 { 0x4200e000, 0000000000 },
1523 { 0x0000a000, 0x00000004 },
1524 { 0x200045e0, 0x00000004 },
1525 { 0x0000e5e1, 0000000000 },
1526 { 0x00000001, 0000000000 },
1527 { 0x000700c8, 0x00000004 },
1528 { 0x0800e394, 0000000000 },
1529 { 0000000000, 0000000000 },
1530 { 0x0000e8c4, 0x00000004 },
1531 { 0x0000e8c5, 0x00000004 },
1532 { 0x0000e8c6, 0x00000004 },
1533 { 0x0000e928, 0x00000004 },
1534 { 0x0000e929, 0x00000004 },
1535 { 0x0000e92a, 0x00000004 },
1536 { 0x000000cc, 0x00000008 },
1537 { 0x0000e928, 0x00000004 },
1538 { 0x0000e929, 0x00000004 },
1539 { 0x0000e92a, 0x00000004 },
1540 { 0x000000d3, 0x00000008 },
1541 { 0x02c02000, 0x00000004 },
1542 { 0x00060000, 0x00000004 },
1543 { 0x000000db, 0x00000034 },
1544 { 0x000000d8, 0x00000008 },
1545 { 0x00008000, 0x00000004 },
1546 { 0xc000e000, 0000000000 },
1547 { 0x000000e1, 0x00000030 },
1548 { 0x4200e000, 0000000000 },
1549 { 0x000000e1, 0x00000030 },
1550 { 0x4000e000, 0000000000 },
1551 { 0x0025001b, 0x00000004 },
1552 { 0x00230000, 0x00000004 },
1553 { 0x00250005, 0x00000004 },
1554 { 0x000000e6, 0x00000034 },
1555 { 0000000000, 0x0000000c },
1556 { 0x00244000, 0x00000004 },
1557 { 0x080045c8, 0x00000004 },
1558 { 0x00240005, 0x00000004 },
1559 { 0x08004d0b, 0x0000000c },
1560 { 0000000000, 0000000000 },
1561 { 0000000000, 0000000000 },
1562 { 0000000000, 0000000000 },
1563 { 0000000000, 0000000000 },
1564 { 0000000000, 0000000000 },
1565 { 0000000000, 0000000000 },
1566 { 0000000000, 0000000000 },
1567 { 0000000000, 0000000000 },
1568 { 0000000000, 0000000000 },
1569 { 0000000000, 0000000000 },
1570 { 0000000000, 0000000000 },
1571 { 0000000000, 0000000000 },
1572 { 0x000c2000, 0x00000004 },
1573 { 0x001d0018, 0x00000004 },
1574 { 0x001a0001, 0x00000004 },
1575 { 0x000000fb, 0x00000034 },
1576 { 0x0000004a, 0x00000008 },
1577 { 0x0500a04a, 0x00000008 },
1578 { 0000000000, 0000000000 },
1579 { 0000000000, 0000000000 },
1580 { 0000000000, 0000000000 },
1581 { 0000000000, 0000000000 },
1582};
1583
1584static const u32 R520_cp_microcode[][2] = {
1585 { 0x4200e000, 0000000000 },
1586 { 0x4000e000, 0000000000 },
1587 { 0x00000099, 0x00000008 },
1588 { 0x0000009d, 0x00000008 },
1589 { 0x4a554b4a, 0000000000 },
1590 { 0x4a4a4467, 0000000000 },
1591 { 0x55526f75, 0000000000 },
1592 { 0x4a7e7d65, 0000000000 },
1593 { 0xe0dae6f6, 0000000000 },
1594 { 0x4ac54a4a, 0000000000 },
1595 { 0xc8828282, 0000000000 },
1596 { 0xbf4acfc1, 0000000000 },
1597 { 0x87b04ad5, 0000000000 },
1598 { 0xb5838383, 0000000000 },
1599 { 0x4a0f85ba, 0000000000 },
1600 { 0x000ca000, 0x00000004 },
1601 { 0x000d0012, 0x00000038 },
1602 { 0x0000e8b4, 0x00000004 },
1603 { 0x000d0014, 0x00000038 },
1604 { 0x0000e8b6, 0x00000004 },
1605 { 0x000d0016, 0x00000038 },
1606 { 0x0000e854, 0x00000004 },
1607 { 0x000d0018, 0x00000038 },
1608 { 0x0000e855, 0x00000004 },
1609 { 0x000d001a, 0x00000038 },
1610 { 0x0000e856, 0x00000004 },
1611 { 0x000d001c, 0x00000038 },
1612 { 0x0000e857, 0x00000004 },
1613 { 0x000d001e, 0x00000038 },
1614 { 0x0000e824, 0x00000004 },
1615 { 0x000d0020, 0x00000038 },
1616 { 0x0000e825, 0x00000004 },
1617 { 0x000d0022, 0x00000038 },
1618 { 0x0000e830, 0x00000004 },
1619 { 0x000d0024, 0x00000038 },
1620 { 0x0000f0c0, 0x00000004 },
1621 { 0x000d0026, 0x00000038 },
1622 { 0x0000f0c1, 0x00000004 },
1623 { 0x000d0028, 0x00000038 },
1624 { 0x0000e000, 0x00000004 },
1625 { 0x000d002a, 0x00000038 },
1626 { 0x0000e000, 0x00000004 },
1627 { 0x000d002c, 0x00000038 },
1628 { 0x0000e000, 0x00000004 },
1629 { 0x000d002e, 0x00000038 },
1630 { 0x0000e000, 0x00000004 },
1631 { 0x000d0030, 0x00000038 },
1632 { 0x0000e000, 0x00000004 },
1633 { 0x000d0032, 0x00000038 },
1634 { 0x0000f180, 0x00000004 },
1635 { 0x000d0034, 0x00000038 },
1636 { 0x0000f393, 0x00000004 },
1637 { 0x000d0036, 0x00000038 },
1638 { 0x0000f38a, 0x00000004 },
1639 { 0x000d0038, 0x00000038 },
1640 { 0x0000f38e, 0x00000004 },
1641 { 0x0000e821, 0x00000004 },
1642 { 0x0140a000, 0x00000004 },
1643 { 0x00000043, 0x00000018 },
1644 { 0x00cce800, 0x00000004 },
1645 { 0x001b0001, 0x00000004 },
1646 { 0x08004800, 0x00000004 },
1647 { 0x001b0001, 0x00000004 },
1648 { 0x08004800, 0x00000004 },
1649 { 0x001b0001, 0x00000004 },
1650 { 0x08004800, 0x00000004 },
1651 { 0x0000003a, 0x00000008 },
1652 { 0x0000a000, 0000000000 },
1653 { 0x2000451d, 0x00000004 },
1654 { 0x0000e580, 0x00000004 },
1655 { 0x000ce581, 0x00000004 },
1656 { 0x08004580, 0x00000004 },
1657 { 0x000ce581, 0x00000004 },
1658 { 0x00000047, 0x00000008 },
1659 { 0x0000a000, 0000000000 },
1660 { 0x000c2000, 0x00000004 },
1661 { 0x0000e50e, 0x00000004 },
1662 { 0x00032000, 0x00000004 },
1663 { 0x00022051, 0x00000028 },
1664 { 0x00000051, 0x00000024 },
1665 { 0x0800450f, 0x00000004 },
1666 { 0x0000a04b, 0x00000008 },
1667 { 0x0000e565, 0x00000004 },
1668 { 0x0000e566, 0x00000004 },
1669 { 0x00000052, 0x00000008 },
1670 { 0x03cca5b4, 0x00000004 },
1671 { 0x05432000, 0x00000004 },
1672 { 0x00022000, 0x00000004 },
1673 { 0x4ccce05e, 0x00000030 },
1674 { 0x08274565, 0x00000004 },
1675 { 0x0000005e, 0x00000030 },
1676 { 0x08004564, 0x00000004 },
1677 { 0x0000e566, 0x00000004 },
1678 { 0x00000055, 0x00000008 },
1679 { 0x00802061, 0x00000010 },
1680 { 0x00202000, 0x00000004 },
1681 { 0x001b00ff, 0x00000004 },
1682 { 0x01000064, 0x00000010 },
1683 { 0x001f2000, 0x00000004 },
1684 { 0x001c00ff, 0x00000004 },
1685 { 0000000000, 0x0000000c },
1686 { 0x00000072, 0x00000030 },
1687 { 0x00000055, 0x00000008 },
1688 { 0x0000e576, 0x00000004 },
1689 { 0x0000e577, 0x00000004 },
1690 { 0x0000e50e, 0x00000004 },
1691 { 0x0000e50f, 0x00000004 },
1692 { 0x0140a000, 0x00000004 },
1693 { 0x00000069, 0x00000018 },
1694 { 0x00c0e5f9, 0x000000c2 },
1695 { 0x00000069, 0x00000008 },
1696 { 0x0014e50e, 0x00000004 },
1697 { 0x0040e50f, 0x00000004 },
1698 { 0x00c0006c, 0x00000008 },
1699 { 0x0000e570, 0x00000004 },
1700 { 0x0000e571, 0x00000004 },
1701 { 0x0000e572, 0x0000000c },
1702 { 0x0000a000, 0x00000004 },
1703 { 0x0140a000, 0x00000004 },
1704 { 0x0000e568, 0x00000004 },
1705 { 0x000c2000, 0x00000004 },
1706 { 0x00000076, 0x00000018 },
1707 { 0x000b0000, 0x00000004 },
1708 { 0x18c0e562, 0x00000004 },
1709 { 0x00000078, 0x00000008 },
1710 { 0x00c00077, 0x00000008 },
1711 { 0x000700c7, 0x00000004 },
1712 { 0x00000080, 0x00000038 },
1713 { 0x0000e5bb, 0x00000004 },
1714 { 0x0000e5bc, 0000000000 },
1715 { 0x0000a000, 0x00000004 },
1716 { 0x0000e821, 0x00000004 },
1717 { 0x0000e800, 0000000000 },
1718 { 0x0000e821, 0x00000004 },
1719 { 0x0000e82e, 0000000000 },
1720 { 0x02cca000, 0x00000004 },
1721 { 0x00140000, 0x00000004 },
1722 { 0x000ce1cc, 0x00000004 },
1723 { 0x050de1cd, 0x00000004 },
1724 { 0x00400000, 0x00000004 },
1725 { 0x0000008f, 0x00000018 },
1726 { 0x00c0a000, 0x00000004 },
1727 { 0x0000008c, 0x00000008 },
1728 { 0x00000091, 0x00000020 },
1729 { 0x4200e000, 0000000000 },
1730 { 0x00000098, 0x00000038 },
1731 { 0x000ca000, 0x00000004 },
1732 { 0x00140000, 0x00000004 },
1733 { 0x000c2000, 0x00000004 },
1734 { 0x00160000, 0x00000004 },
1735 { 0x700ce000, 0x00000004 },
1736 { 0x00140094, 0x00000008 },
1737 { 0x4000e000, 0000000000 },
1738 { 0x02400000, 0x00000004 },
1739 { 0x400ee000, 0x00000004 },
1740 { 0x02400000, 0x00000004 },
1741 { 0x4000e000, 0000000000 },
1742 { 0x000c2000, 0x00000004 },
1743 { 0x0240e51b, 0x00000004 },
1744 { 0x0080e50a, 0x00000005 },
1745 { 0x0080e50b, 0x00000005 },
1746 { 0x00220000, 0x00000004 },
1747 { 0x000700c7, 0x00000004 },
1748 { 0x000000a4, 0x00000038 },
1749 { 0x0080e5bd, 0x00000005 },
1750 { 0x0000e5bb, 0x00000005 },
1751 { 0x0080e5bc, 0x00000005 },
1752 { 0x00210000, 0x00000004 },
1753 { 0x02800000, 0x00000004 },
1754 { 0x00c000ab, 0x00000018 },
1755 { 0x4180e000, 0x00000040 },
1756 { 0x000000ad, 0x00000024 },
1757 { 0x01000000, 0x0000000c },
1758 { 0x0100e51d, 0x0000000c },
1759 { 0x000045bb, 0x00000004 },
1760 { 0x000080a7, 0x00000008 },
1761 { 0x0000f3ce, 0x00000004 },
1762 { 0x0140a000, 0x00000004 },
1763 { 0x00cc2000, 0x00000004 },
1764 { 0x08c053cf, 0x00000040 },
1765 { 0x00008000, 0000000000 },
1766 { 0x0000f3d2, 0x00000004 },
1767 { 0x0140a000, 0x00000004 },
1768 { 0x00cc2000, 0x00000004 },
1769 { 0x08c053d3, 0x00000040 },
1770 { 0x00008000, 0000000000 },
1771 { 0x0000f39d, 0x00000004 },
1772 { 0x0140a000, 0x00000004 },
1773 { 0x00cc2000, 0x00000004 },
1774 { 0x08c0539e, 0x00000040 },
1775 { 0x00008000, 0000000000 },
1776 { 0x03c00830, 0x00000004 },
1777 { 0x4200e000, 0000000000 },
1778 { 0x0000a000, 0x00000004 },
1779 { 0x200045e0, 0x00000004 },
1780 { 0x0000e5e1, 0000000000 },
1781 { 0x00000001, 0000000000 },
1782 { 0x000700c4, 0x00000004 },
1783 { 0x0800e394, 0000000000 },
1784 { 0000000000, 0000000000 },
1785 { 0x0000e8c4, 0x00000004 },
1786 { 0x0000e8c5, 0x00000004 },
1787 { 0x0000e8c6, 0x00000004 },
1788 { 0x0000e928, 0x00000004 },
1789 { 0x0000e929, 0x00000004 },
1790 { 0x0000e92a, 0x00000004 },
1791 { 0x000000c8, 0x00000008 },
1792 { 0x0000e928, 0x00000004 },
1793 { 0x0000e929, 0x00000004 },
1794 { 0x0000e92a, 0x00000004 },
1795 { 0x000000cf, 0x00000008 },
1796 { 0xdeadbeef, 0000000000 },
1797 { 0x00000116, 0000000000 },
1798 { 0x000700d3, 0x00000004 },
1799 { 0x080050e7, 0x00000004 },
1800 { 0x000700d4, 0x00000004 },
1801 { 0x0800401c, 0x00000004 },
1802 { 0x0000e01d, 0000000000 },
1803 { 0x02c02000, 0x00000004 },
1804 { 0x00060000, 0x00000004 },
1805 { 0x000000de, 0x00000034 },
1806 { 0x000000db, 0x00000008 },
1807 { 0x00008000, 0x00000004 },
1808 { 0xc000e000, 0000000000 },
1809 { 0x0000e1cc, 0x00000004 },
1810 { 0x0500e1cd, 0x00000004 },
1811 { 0x000ca000, 0x00000004 },
1812 { 0x000000e5, 0x00000034 },
1813 { 0x000000e1, 0x00000008 },
1814 { 0x0000a000, 0000000000 },
1815 { 0x0019e1cc, 0x00000004 },
1816 { 0x001b0001, 0x00000004 },
1817 { 0x0500a000, 0x00000004 },
1818 { 0x080041cd, 0x00000004 },
1819 { 0x000ca000, 0x00000004 },
1820 { 0x000000fb, 0x00000034 },
1821 { 0x0000004a, 0x00000008 },
1822 { 0000000000, 0000000000 },
1823 { 0000000000, 0000000000 },
1824 { 0000000000, 0000000000 },
1825 { 0000000000, 0000000000 },
1826 { 0000000000, 0000000000 },
1827 { 0000000000, 0000000000 },
1828 { 0000000000, 0000000000 },
1829 { 0000000000, 0000000000 },
1830 { 0000000000, 0000000000 },
1831 { 0x000c2000, 0x00000004 },
1832 { 0x001d0018, 0x00000004 },
1833 { 0x001a0001, 0x00000004 },
1834 { 0x000000fb, 0x00000034 },
1835 { 0x0000004a, 0x00000008 },
1836 { 0x0500a04a, 0x00000008 },
1837 { 0000000000, 0000000000 },
1838 { 0000000000, 0000000000 },
1839 { 0000000000, 0000000000 },
1840 { 0000000000, 0000000000 },
1841};
1842
1843
1844#endif
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 3b09a1f2d8f9..570a58729daf 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -175,6 +175,15 @@ struct radeon_mode_info {
175 enum radeon_connector_table connector_table; 175 enum radeon_connector_table connector_table;
176 bool mode_config_initialized; 176 bool mode_config_initialized;
177 struct radeon_crtc *crtcs[2]; 177 struct radeon_crtc *crtcs[2];
178 /* DVI-I properties */
179 struct drm_property *coherent_mode_property;
180 /* DAC enable load detect */
181 struct drm_property *load_detect_property;
182 /* TV standard load detect */
183 struct drm_property *tv_std_property;
184 /* legacy TMDS PLL detect */
185 struct drm_property *tmds_pll_property;
186
178}; 187};
179 188
180struct radeon_native_mode { 189struct radeon_native_mode {
@@ -188,6 +197,21 @@ struct radeon_native_mode {
188 uint32_t flags; 197 uint32_t flags;
189}; 198};
190 199
200#define MAX_H_CODE_TIMING_LEN 32
201#define MAX_V_CODE_TIMING_LEN 32
202
203/* need to store these as reading
204 back code tables is excessive */
205struct radeon_tv_regs {
206 uint32_t tv_uv_adr;
207 uint32_t timing_cntl;
208 uint32_t hrestart;
209 uint32_t vrestart;
210 uint32_t frestart;
211 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
212 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
213};
214
191struct radeon_crtc { 215struct radeon_crtc {
192 struct drm_crtc base; 216 struct drm_crtc base;
193 int crtc_id; 217 int crtc_id;
@@ -195,8 +219,6 @@ struct radeon_crtc {
195 bool enabled; 219 bool enabled;
196 bool can_tile; 220 bool can_tile;
197 uint32_t crtc_offset; 221 uint32_t crtc_offset;
198 struct radeon_framebuffer *fbdev_fb;
199 struct drm_mode_set mode_set;
200 struct drm_gem_object *cursor_bo; 222 struct drm_gem_object *cursor_bo;
201 uint64_t cursor_addr; 223 uint64_t cursor_addr;
202 int cursor_width; 224 int cursor_width;
@@ -204,7 +226,6 @@ struct radeon_crtc {
204 uint32_t legacy_display_base_addr; 226 uint32_t legacy_display_base_addr;
205 uint32_t legacy_cursor_offset; 227 uint32_t legacy_cursor_offset;
206 enum radeon_rmx_type rmx_type; 228 enum radeon_rmx_type rmx_type;
207 uint32_t devices;
208 fixed20_12 vsc; 229 fixed20_12 vsc;
209 fixed20_12 hsc; 230 fixed20_12 hsc;
210 struct radeon_native_mode native_mode; 231 struct radeon_native_mode native_mode;
@@ -236,7 +257,13 @@ struct radeon_encoder_tv_dac {
236 uint32_t ntsc_tvdac_adj; 257 uint32_t ntsc_tvdac_adj;
237 uint32_t pal_tvdac_adj; 258 uint32_t pal_tvdac_adj;
238 259
260 int h_pos;
261 int v_pos;
262 int h_size;
263 int supported_tv_stds;
264 bool tv_on;
239 enum radeon_tv_std tv_std; 265 enum radeon_tv_std tv_std;
266 struct radeon_tv_regs tv;
240}; 267};
241 268
242struct radeon_encoder_int_tmds { 269struct radeon_encoder_int_tmds {
@@ -255,10 +282,15 @@ struct radeon_encoder_atom_dig {
255 struct radeon_native_mode native_mode; 282 struct radeon_native_mode native_mode;
256}; 283};
257 284
285struct radeon_encoder_atom_dac {
286 enum radeon_tv_std tv_std;
287};
288
258struct radeon_encoder { 289struct radeon_encoder {
259 struct drm_encoder base; 290 struct drm_encoder base;
260 uint32_t encoder_id; 291 uint32_t encoder_id;
261 uint32_t devices; 292 uint32_t devices;
293 uint32_t active_device;
262 uint32_t flags; 294 uint32_t flags;
263 uint32_t pixel_clock; 295 uint32_t pixel_clock;
264 enum radeon_rmx_type rmx_type; 296 enum radeon_rmx_type rmx_type;
@@ -276,8 +308,12 @@ struct radeon_connector {
276 uint32_t connector_id; 308 uint32_t connector_id;
277 uint32_t devices; 309 uint32_t devices;
278 struct radeon_i2c_chan *ddc_bus; 310 struct radeon_i2c_chan *ddc_bus;
279 int use_digital; 311 bool use_digital;
312 /* we need to mind the EDID between detect
313 and get modes due to analog/digital/tvencoder */
314 struct edid *edid;
280 void *con_priv; 315 void *con_priv;
316 bool dac_load_detect;
281}; 317};
282 318
283struct radeon_framebuffer { 319struct radeon_framebuffer {
@@ -310,6 +346,7 @@ struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, i
310struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 346struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
311extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); 347extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
312extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 348extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
349extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
313 350
314extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 351extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
315extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 352extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
@@ -337,16 +374,18 @@ extern bool radeon_atom_get_clock_info(struct drm_device *dev);
337extern bool radeon_combios_get_clock_info(struct drm_device *dev); 374extern bool radeon_combios_get_clock_info(struct drm_device *dev);
338extern struct radeon_encoder_atom_dig * 375extern struct radeon_encoder_atom_dig *
339radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 376radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
340extern struct radeon_encoder_int_tmds * 377bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
341radeon_atombios_get_tmds_info(struct radeon_encoder *encoder); 378 struct radeon_encoder_int_tmds *tmds);
379bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
380 struct radeon_encoder_int_tmds *tmds);
381bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
382 struct radeon_encoder_int_tmds *tmds);
342extern struct radeon_encoder_primary_dac * 383extern struct radeon_encoder_primary_dac *
343radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 384radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
344extern struct radeon_encoder_tv_dac * 385extern struct radeon_encoder_tv_dac *
345radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 386radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
346extern struct radeon_encoder_lvds * 387extern struct radeon_encoder_lvds *
347radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 388radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
348extern struct radeon_encoder_int_tmds *
349radeon_combios_get_tmds_info(struct radeon_encoder *encoder);
350extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 389extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
351extern struct radeon_encoder_tv_dac * 390extern struct radeon_encoder_tv_dac *
352radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 391radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
@@ -356,6 +395,8 @@ extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
356extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 395extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
357extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 396extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
358extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 397extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
398extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
399extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
359extern void 400extern void
360radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 401radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
361extern void 402extern void
@@ -396,6 +437,19 @@ extern int radeon_static_clocks_init(struct drm_device *dev);
396bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 437bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
397 struct drm_display_mode *mode, 438 struct drm_display_mode *mode,
398 struct drm_display_mode *adjusted_mode); 439 struct drm_display_mode *adjusted_mode);
399void atom_rv515_force_tv_scaler(struct radeon_device *rdev); 440void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
400 441
442/* legacy tv */
443void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
444 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
445 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
446void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
447 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
448 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
449void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
450 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
451 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
452void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
453 struct drm_display_mode *mode,
454 struct drm_display_mode *adjusted_mode);
401#endif 455#endif
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index b85fb83d7ae8..73af463b7a59 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -188,6 +188,7 @@ int radeon_object_kmap(struct radeon_object *robj, void **ptr)
188 if (ptr) { 188 if (ptr) {
189 *ptr = robj->kptr; 189 *ptr = robj->kptr;
190 } 190 }
191 radeon_object_check_tiling(robj, 0, 0);
191 return 0; 192 return 0;
192} 193}
193 194
@@ -200,6 +201,7 @@ void radeon_object_kunmap(struct radeon_object *robj)
200 } 201 }
201 robj->kptr = NULL; 202 robj->kptr = NULL;
202 spin_unlock(&robj->tobj.lock); 203 spin_unlock(&robj->tobj.lock);
204 radeon_object_check_tiling(robj, 0, 0);
203 ttm_bo_kunmap(&robj->kmap); 205 ttm_bo_kunmap(&robj->kmap);
204} 206}
205 207
@@ -369,6 +371,14 @@ void radeon_object_force_delete(struct radeon_device *rdev)
369 371
370int radeon_object_init(struct radeon_device *rdev) 372int radeon_object_init(struct radeon_device *rdev)
371{ 373{
374 /* Add an MTRR for the VRAM */
375 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
376 MTRR_TYPE_WRCOMB, 1);
377 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
378 rdev->mc.mc_vram_size >> 20,
379 (unsigned long long)rdev->mc.aper_size >> 20);
380 DRM_INFO("RAM width %dbits %cDR\n",
381 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
372 return radeon_ttm_init(rdev); 382 return radeon_ttm_init(rdev);
373} 383}
374 384
diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h
index 473e4775dc5a..10e8af6bb456 100644
--- a/drivers/gpu/drm/radeon/radeon_object.h
+++ b/drivers/gpu/drm/radeon/radeon_object.h
@@ -37,6 +37,7 @@
37 * TTM. 37 * TTM.
38 */ 38 */
39struct radeon_mman { 39struct radeon_mman {
40 struct ttm_bo_global_ref bo_global_ref;
40 struct ttm_global_reference mem_global_ref; 41 struct ttm_global_reference mem_global_ref;
41 bool mem_global_referenced; 42 bool mem_global_referenced;
42 struct ttm_bo_device bdev; 43 struct ttm_bo_device bdev;
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index 4df43f62c678..21da871a793c 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -1945,6 +1945,11 @@
1945# define RADEON_TXFORMAT_DXT1 (12 << 0) 1945# define RADEON_TXFORMAT_DXT1 (12 << 0)
1946# define RADEON_TXFORMAT_DXT23 (14 << 0) 1946# define RADEON_TXFORMAT_DXT23 (14 << 0)
1947# define RADEON_TXFORMAT_DXT45 (15 << 0) 1947# define RADEON_TXFORMAT_DXT45 (15 << 0)
1948# define RADEON_TXFORMAT_SHADOW16 (16 << 0)
1949# define RADEON_TXFORMAT_SHADOW32 (17 << 0)
1950# define RADEON_TXFORMAT_DUDV88 (18 << 0)
1951# define RADEON_TXFORMAT_LDUDV655 (19 << 0)
1952# define RADEON_TXFORMAT_LDUDUV8888 (20 << 0)
1948# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) 1953# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)
1949# define RADEON_TXFORMAT_FORMAT_SHIFT 0 1954# define RADEON_TXFORMAT_FORMAT_SHIFT 0
1950# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) 1955# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)
@@ -2203,7 +2208,7 @@
2203# define RADEON_ROP_ENABLE (1 << 6) 2208# define RADEON_ROP_ENABLE (1 << 6)
2204# define RADEON_STENCIL_ENABLE (1 << 7) 2209# define RADEON_STENCIL_ENABLE (1 << 7)
2205# define RADEON_Z_ENABLE (1 << 8) 2210# define RADEON_Z_ENABLE (1 << 8)
2206# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) 2211# define RADEON_DEPTHXY_OFFSET_ENABLE (1 << 9)
2207# define RADEON_RB3D_COLOR_FORMAT_SHIFT 10 2212# define RADEON_RB3D_COLOR_FORMAT_SHIFT 10
2208 2213
2209# define RADEON_COLOR_FORMAT_ARGB1555 3 2214# define RADEON_COLOR_FORMAT_ARGB1555 3
@@ -2773,7 +2778,12 @@
2773# define R200_TXFORMAT_DXT1 (12 << 0) 2778# define R200_TXFORMAT_DXT1 (12 << 0)
2774# define R200_TXFORMAT_DXT23 (14 << 0) 2779# define R200_TXFORMAT_DXT23 (14 << 0)
2775# define R200_TXFORMAT_DXT45 (15 << 0) 2780# define R200_TXFORMAT_DXT45 (15 << 0)
2781# define R200_TXFORMAT_DVDU88 (18 << 0)
2782# define R200_TXFORMAT_LDVDU655 (19 << 0)
2783# define R200_TXFORMAT_LDVDU8888 (20 << 0)
2784# define R200_TXFORMAT_GR1616 (21 << 0)
2776# define R200_TXFORMAT_ABGR8888 (22 << 0) 2785# define R200_TXFORMAT_ABGR8888 (22 << 0)
2786# define R200_TXFORMAT_BGR111110 (23 << 0)
2777# define R200_TXFORMAT_FORMAT_MASK (31 << 0) 2787# define R200_TXFORMAT_FORMAT_MASK (31 << 0)
2778# define R200_TXFORMAT_FORMAT_SHIFT 0 2788# define R200_TXFORMAT_FORMAT_SHIFT 0
2779# define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) 2789# define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6)
@@ -2818,6 +2828,13 @@
2818#define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */ 2828#define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */
2819#define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */ 2829#define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */
2820 2830
2831#define R200_PP_CUBIC_FACES_0 0x2c18
2832#define R200_PP_CUBIC_FACES_1 0x2c38
2833#define R200_PP_CUBIC_FACES_2 0x2c58
2834#define R200_PP_CUBIC_FACES_3 0x2c78
2835#define R200_PP_CUBIC_FACES_4 0x2c98
2836#define R200_PP_CUBIC_FACES_5 0x2cb8
2837
2821#define R200_PP_TXOFFSET_0 0x2d00 2838#define R200_PP_TXOFFSET_0 0x2d00
2822# define R200_TXO_ENDIAN_NO_SWAP (0 << 0) 2839# define R200_TXO_ENDIAN_NO_SWAP (0 << 0)
2823# define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) 2840# define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0)
@@ -2829,11 +2846,44 @@
2829# define R200_TXO_MICRO_TILE (1 << 3) 2846# define R200_TXO_MICRO_TILE (1 << 3)
2830# define R200_TXO_OFFSET_MASK 0xffffffe0 2847# define R200_TXO_OFFSET_MASK 0xffffffe0
2831# define R200_TXO_OFFSET_SHIFT 5 2848# define R200_TXO_OFFSET_SHIFT 5
2849#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
2850#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
2851#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
2852#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
2853#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
2854
2832#define R200_PP_TXOFFSET_1 0x2d18 2855#define R200_PP_TXOFFSET_1 0x2d18
2856#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
2857#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
2858#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
2859#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
2860#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
2861
2833#define R200_PP_TXOFFSET_2 0x2d30 2862#define R200_PP_TXOFFSET_2 0x2d30
2863#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
2864#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
2865#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
2866#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
2867#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
2868
2834#define R200_PP_TXOFFSET_3 0x2d48 2869#define R200_PP_TXOFFSET_3 0x2d48
2870#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
2871#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
2872#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
2873#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
2874#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
2835#define R200_PP_TXOFFSET_4 0x2d60 2875#define R200_PP_TXOFFSET_4 0x2d60
2876#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
2877#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
2878#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
2879#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
2880#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
2836#define R200_PP_TXOFFSET_5 0x2d78 2881#define R200_PP_TXOFFSET_5 0x2d78
2882#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
2883#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
2884#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
2885#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
2886#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
2837 2887
2838#define R200_PP_TFACTOR_0 0x2ee0 2888#define R200_PP_TFACTOR_0 0x2ee0
2839#define R200_PP_TFACTOR_1 0x2ee4 2889#define R200_PP_TFACTOR_1 0x2ee4
@@ -3175,6 +3225,11 @@
3175# define R200_FORCE_INORDER_PROC (1<<31) 3225# define R200_FORCE_INORDER_PROC (1<<31)
3176#define R200_PP_CNTL_X 0x2cc4 3226#define R200_PP_CNTL_X 0x2cc4
3177#define R200_PP_TXMULTI_CTL_0 0x2c1c 3227#define R200_PP_TXMULTI_CTL_0 0x2c1c
3228#define R200_PP_TXMULTI_CTL_1 0x2c3c
3229#define R200_PP_TXMULTI_CTL_2 0x2c5c
3230#define R200_PP_TXMULTI_CTL_3 0x2c7c
3231#define R200_PP_TXMULTI_CTL_4 0x2c9c
3232#define R200_PP_TXMULTI_CTL_5 0x2cbc
3178#define R200_SE_VTX_STATE_CNTL 0x2180 3233#define R200_SE_VTX_STATE_CNTL 0x2180
3179# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) 3234# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)
3180 3235
@@ -3200,6 +3255,24 @@
3200#define RADEON_CP_RB_WPTR 0x0714 3255#define RADEON_CP_RB_WPTR 0x0714
3201#define RADEON_CP_RB_RPTR_WR 0x071c 3256#define RADEON_CP_RB_RPTR_WR 0x071c
3202 3257
3258#define RADEON_SCRATCH_UMSK 0x0770
3259#define RADEON_SCRATCH_ADDR 0x0774
3260
3261#define R600_CP_RB_BASE 0xc100
3262#define R600_CP_RB_CNTL 0xc104
3263# define R600_RB_BUFSZ(x) ((x) << 0)
3264# define R600_RB_BLKSZ(x) ((x) << 8)
3265# define R600_RB_NO_UPDATE (1 << 27)
3266# define R600_RB_RPTR_WR_ENA (1 << 31)
3267#define R600_CP_RB_RPTR_WR 0xc108
3268#define R600_CP_RB_RPTR_ADDR 0xc10c
3269#define R600_CP_RB_RPTR_ADDR_HI 0xc110
3270#define R600_CP_RB_WPTR 0xc114
3271#define R600_CP_RB_WPTR_ADDR 0xc118
3272#define R600_CP_RB_WPTR_ADDR_HI 0xc11c
3273#define R600_CP_RB_RPTR 0x8700
3274#define R600_CP_RB_WPTR_DELAY 0x8704
3275
3203#define RADEON_CP_IB_BASE 0x0738 3276#define RADEON_CP_IB_BASE 0x0738
3204#define RADEON_CP_IB_BUFSZ 0x073c 3277#define RADEON_CP_IB_BUFSZ 0x073c
3205 3278
@@ -3407,7 +3480,9 @@
3407# define RADEON_RGB_CONVERT_BY_PASS (1 << 10) 3480# define RADEON_RGB_CONVERT_BY_PASS (1 << 10)
3408# define RADEON_UVRAM_READ_MARGIN_SHIFT 16 3481# define RADEON_UVRAM_READ_MARGIN_SHIFT 16
3409# define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20 3482# define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20
3410# define RADEON_TVOUT_SCALE_EN (1 << 26) 3483# define RADEON_RGB_ATTEN_SEL(x) ((x) << 24)
3484# define RADEON_TVOUT_SCALE_EN (1 << 26)
3485# define RADEON_RGB_ATTEN_VAL(x) ((x) << 28)
3411#define RADEON_TV_SYNC_CNTL 0x0808 3486#define RADEON_TV_SYNC_CNTL 0x0808
3412# define RADEON_SYNC_OE (1 << 0) 3487# define RADEON_SYNC_OE (1 << 0)
3413# define RADEON_SYNC_OUT (1 << 1) 3488# define RADEON_SYNC_OUT (1 << 1)
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 60d159308b88..747b4bffb84b 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -56,10 +56,12 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
56 set_bit(i, rdev->ib_pool.alloc_bm); 56 set_bit(i, rdev->ib_pool.alloc_bm);
57 rdev->ib_pool.ibs[i].length_dw = 0; 57 rdev->ib_pool.ibs[i].length_dw = 0;
58 *ib = &rdev->ib_pool.ibs[i]; 58 *ib = &rdev->ib_pool.ibs[i];
59 mutex_unlock(&rdev->ib_pool.mutex);
59 goto out; 60 goto out;
60 } 61 }
61 if (list_empty(&rdev->ib_pool.scheduled_ibs)) { 62 if (list_empty(&rdev->ib_pool.scheduled_ibs)) {
62 /* we go do nothings here */ 63 /* we go do nothings here */
64 mutex_unlock(&rdev->ib_pool.mutex);
63 DRM_ERROR("all IB allocated none scheduled.\n"); 65 DRM_ERROR("all IB allocated none scheduled.\n");
64 r = -EINVAL; 66 r = -EINVAL;
65 goto out; 67 goto out;
@@ -69,10 +71,13 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
69 struct radeon_ib, list); 71 struct radeon_ib, list);
70 if (nib->fence == NULL) { 72 if (nib->fence == NULL) {
71 /* we go do nothings here */ 73 /* we go do nothings here */
74 mutex_unlock(&rdev->ib_pool.mutex);
72 DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx); 75 DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx);
73 r = -EINVAL; 76 r = -EINVAL;
74 goto out; 77 goto out;
75 } 78 }
79 mutex_unlock(&rdev->ib_pool.mutex);
80
76 r = radeon_fence_wait(nib->fence, false); 81 r = radeon_fence_wait(nib->fence, false);
77 if (r) { 82 if (r) {
78 DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx, 83 DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx,
@@ -81,12 +86,17 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
81 goto out; 86 goto out;
82 } 87 }
83 radeon_fence_unref(&nib->fence); 88 radeon_fence_unref(&nib->fence);
89
84 nib->length_dw = 0; 90 nib->length_dw = 0;
91
92 /* scheduled list is accessed here */
93 mutex_lock(&rdev->ib_pool.mutex);
85 list_del(&nib->list); 94 list_del(&nib->list);
86 INIT_LIST_HEAD(&nib->list); 95 INIT_LIST_HEAD(&nib->list);
96 mutex_unlock(&rdev->ib_pool.mutex);
97
87 *ib = nib; 98 *ib = nib;
88out: 99out:
89 mutex_unlock(&rdev->ib_pool.mutex);
90 if (r) { 100 if (r) {
91 radeon_fence_unref(&fence); 101 radeon_fence_unref(&fence);
92 } else { 102 } else {
@@ -111,47 +121,36 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
111 } 121 }
112 list_del(&tmp->list); 122 list_del(&tmp->list);
113 INIT_LIST_HEAD(&tmp->list); 123 INIT_LIST_HEAD(&tmp->list);
114 if (tmp->fence) { 124 if (tmp->fence)
115 radeon_fence_unref(&tmp->fence); 125 radeon_fence_unref(&tmp->fence);
116 } 126
117 tmp->length_dw = 0; 127 tmp->length_dw = 0;
118 clear_bit(tmp->idx, rdev->ib_pool.alloc_bm); 128 clear_bit(tmp->idx, rdev->ib_pool.alloc_bm);
119 mutex_unlock(&rdev->ib_pool.mutex); 129 mutex_unlock(&rdev->ib_pool.mutex);
120} 130}
121 131
122static void radeon_ib_align(struct radeon_device *rdev, struct radeon_ib *ib)
123{
124 while ((ib->length_dw & rdev->cp.align_mask)) {
125 ib->ptr[ib->length_dw++] = PACKET2(0);
126 }
127}
128
129int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) 132int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
130{ 133{
131 int r = 0; 134 int r = 0;
132 135
133 mutex_lock(&rdev->ib_pool.mutex);
134 radeon_ib_align(rdev, ib);
135 if (!ib->length_dw || !rdev->cp.ready) { 136 if (!ib->length_dw || !rdev->cp.ready) {
136 /* TODO: Nothings in the ib we should report. */ 137 /* TODO: Nothings in the ib we should report. */
137 mutex_unlock(&rdev->ib_pool.mutex);
138 DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx); 138 DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx);
139 return -EINVAL; 139 return -EINVAL;
140 } 140 }
141
141 /* 64 dwords should be enough for fence too */ 142 /* 64 dwords should be enough for fence too */
142 r = radeon_ring_lock(rdev, 64); 143 r = radeon_ring_lock(rdev, 64);
143 if (r) { 144 if (r) {
144 DRM_ERROR("radeon: scheduling IB failled (%d).\n", r); 145 DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);
145 mutex_unlock(&rdev->ib_pool.mutex);
146 return r; 146 return r;
147 } 147 }
148 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); 148 radeon_ring_ib_execute(rdev, ib);
149 radeon_ring_write(rdev, ib->gpu_addr);
150 radeon_ring_write(rdev, ib->length_dw);
151 radeon_fence_emit(rdev, ib->fence); 149 radeon_fence_emit(rdev, ib->fence);
152 radeon_ring_unlock_commit(rdev); 150 mutex_lock(&rdev->ib_pool.mutex);
153 list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs); 151 list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs);
154 mutex_unlock(&rdev->ib_pool.mutex); 152 mutex_unlock(&rdev->ib_pool.mutex);
153 radeon_ring_unlock_commit(rdev);
155 return 0; 154 return 0;
156} 155}
157 156
@@ -162,6 +161,8 @@ int radeon_ib_pool_init(struct radeon_device *rdev)
162 int i; 161 int i;
163 int r = 0; 162 int r = 0;
164 163
164 if (rdev->ib_pool.robj)
165 return 0;
165 /* Allocate 1M object buffer */ 166 /* Allocate 1M object buffer */
166 INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs); 167 INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs);
167 r = radeon_object_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024, 168 r = radeon_object_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024,
@@ -215,69 +216,16 @@ void radeon_ib_pool_fini(struct radeon_device *rdev)
215 mutex_unlock(&rdev->ib_pool.mutex); 216 mutex_unlock(&rdev->ib_pool.mutex);
216} 217}
217 218
218int radeon_ib_test(struct radeon_device *rdev)
219{
220 struct radeon_ib *ib;
221 uint32_t scratch;
222 uint32_t tmp = 0;
223 unsigned i;
224 int r;
225
226 r = radeon_scratch_get(rdev, &scratch);
227 if (r) {
228 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
229 return r;
230 }
231 WREG32(scratch, 0xCAFEDEAD);
232 r = radeon_ib_get(rdev, &ib);
233 if (r) {
234 return r;
235 }
236 ib->ptr[0] = PACKET0(scratch, 0);
237 ib->ptr[1] = 0xDEADBEEF;
238 ib->ptr[2] = PACKET2(0);
239 ib->ptr[3] = PACKET2(0);
240 ib->ptr[4] = PACKET2(0);
241 ib->ptr[5] = PACKET2(0);
242 ib->ptr[6] = PACKET2(0);
243 ib->ptr[7] = PACKET2(0);
244 ib->length_dw = 8;
245 r = radeon_ib_schedule(rdev, ib);
246 if (r) {
247 radeon_scratch_free(rdev, scratch);
248 radeon_ib_free(rdev, &ib);
249 return r;
250 }
251 r = radeon_fence_wait(ib->fence, false);
252 if (r) {
253 return r;
254 }
255 for (i = 0; i < rdev->usec_timeout; i++) {
256 tmp = RREG32(scratch);
257 if (tmp == 0xDEADBEEF) {
258 break;
259 }
260 DRM_UDELAY(1);
261 }
262 if (i < rdev->usec_timeout) {
263 DRM_INFO("ib test succeeded in %u usecs\n", i);
264 } else {
265 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
266 scratch, tmp);
267 r = -EINVAL;
268 }
269 radeon_scratch_free(rdev, scratch);
270 radeon_ib_free(rdev, &ib);
271 return r;
272}
273
274 219
275/* 220/*
276 * Ring. 221 * Ring.
277 */ 222 */
278void radeon_ring_free_size(struct radeon_device *rdev) 223void radeon_ring_free_size(struct radeon_device *rdev)
279{ 224{
280 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 225 if (rdev->family >= CHIP_R600)
226 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
227 else
228 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
281 /* This works because ring_size is a power of 2 */ 229 /* This works because ring_size is a power of 2 */
282 rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4)); 230 rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
283 rdev->cp.ring_free_dw -= rdev->cp.wptr; 231 rdev->cp.ring_free_dw -= rdev->cp.wptr;
@@ -320,11 +268,10 @@ void radeon_ring_unlock_commit(struct radeon_device *rdev)
320 count_dw_pad = (rdev->cp.align_mask + 1) - 268 count_dw_pad = (rdev->cp.align_mask + 1) -
321 (rdev->cp.wptr & rdev->cp.align_mask); 269 (rdev->cp.wptr & rdev->cp.align_mask);
322 for (i = 0; i < count_dw_pad; i++) { 270 for (i = 0; i < count_dw_pad; i++) {
323 radeon_ring_write(rdev, PACKET2(0)); 271 radeon_ring_write(rdev, 2 << 30);
324 } 272 }
325 DRM_MEMORYBARRIER(); 273 DRM_MEMORYBARRIER();
326 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); 274 radeon_cp_commit(rdev);
327 (void)RREG32(RADEON_CP_RB_WPTR);
328 mutex_unlock(&rdev->cp.mutex); 275 mutex_unlock(&rdev->cp.mutex);
329} 276}
330 277
@@ -334,46 +281,6 @@ void radeon_ring_unlock_undo(struct radeon_device *rdev)
334 mutex_unlock(&rdev->cp.mutex); 281 mutex_unlock(&rdev->cp.mutex);
335} 282}
336 283
337int radeon_ring_test(struct radeon_device *rdev)
338{
339 uint32_t scratch;
340 uint32_t tmp = 0;
341 unsigned i;
342 int r;
343
344 r = radeon_scratch_get(rdev, &scratch);
345 if (r) {
346 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
347 return r;
348 }
349 WREG32(scratch, 0xCAFEDEAD);
350 r = radeon_ring_lock(rdev, 2);
351 if (r) {
352 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
353 radeon_scratch_free(rdev, scratch);
354 return r;
355 }
356 radeon_ring_write(rdev, PACKET0(scratch, 0));
357 radeon_ring_write(rdev, 0xDEADBEEF);
358 radeon_ring_unlock_commit(rdev);
359 for (i = 0; i < rdev->usec_timeout; i++) {
360 tmp = RREG32(scratch);
361 if (tmp == 0xDEADBEEF) {
362 break;
363 }
364 DRM_UDELAY(1);
365 }
366 if (i < rdev->usec_timeout) {
367 DRM_INFO("ring test succeeded in %d usecs\n", i);
368 } else {
369 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
370 scratch, tmp);
371 r = -EINVAL;
372 }
373 radeon_scratch_free(rdev, scratch);
374 return r;
375}
376
377int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size) 284int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
378{ 285{
379 int r; 286 int r;
diff --git a/drivers/gpu/drm/radeon/radeon_share.h b/drivers/gpu/drm/radeon/radeon_share.h
deleted file mode 100644
index 63a773578f17..000000000000
--- a/drivers/gpu/drm/radeon/radeon_share.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_SHARE_H__
29#define __RADEON_SHARE_H__
30
31void r100_vram_init_sizes(struct radeon_device *rdev);
32
33void rs690_line_buffer_adjust(struct radeon_device *rdev,
34 struct drm_display_mode *mode1,
35 struct drm_display_mode *mode2);
36
37void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
38
39#endif
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index 2882f40d5ec5..38537d971a3e 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -1546,7 +1546,7 @@ static void radeon_cp_dispatch_vertex(struct drm_device * dev,
1546 } while (i < nbox); 1546 } while (i < nbox);
1547} 1547}
1548 1548
1549static void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf) 1549void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf)
1550{ 1550{
1551 drm_radeon_private_t *dev_priv = dev->dev_private; 1551 drm_radeon_private_t *dev_priv = dev->dev_private;
1552 struct drm_radeon_master_private *master_priv = master->driver_priv; 1552 struct drm_radeon_master_private *master_priv = master->driver_priv;
@@ -2213,7 +2213,10 @@ static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *f
2213 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) 2213 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2214 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; 2214 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2215 2215
2216 radeon_cp_dispatch_swap(dev, file_priv->master); 2216 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2217 r600_cp_dispatch_swap(dev, file_priv);
2218 else
2219 radeon_cp_dispatch_swap(dev, file_priv->master);
2217 sarea_priv->ctx_owner = 0; 2220 sarea_priv->ctx_owner = 0;
2218 2221
2219 COMMIT_RING(); 2222 COMMIT_RING();
@@ -2412,7 +2415,10 @@ static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file
2412 RING_SPACE_TEST_WITH_RETURN(dev_priv); 2415 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2413 VB_AGE_TEST_WITH_RETURN(dev_priv); 2416 VB_AGE_TEST_WITH_RETURN(dev_priv);
2414 2417
2415 ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image); 2418 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2419 ret = r600_cp_dispatch_texture(dev, file_priv, tex, &image);
2420 else
2421 ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image);
2416 2422
2417 return ret; 2423 return ret;
2418} 2424}
@@ -2495,8 +2501,9 @@ static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_fil
2495 radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end); 2501 radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
2496 } 2502 }
2497 2503
2498 if (indirect->discard) 2504 if (indirect->discard) {
2499 radeon_cp_discard_buffer(dev, file_priv->master, buf); 2505 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2506 }
2500 2507
2501 COMMIT_RING(); 2508 COMMIT_RING();
2502 return 0; 2509 return 0;
@@ -3027,7 +3034,10 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
3027 value = GET_SCRATCH(dev_priv, 2); 3034 value = GET_SCRATCH(dev_priv, 2);
3028 break; 3035 break;
3029 case RADEON_PARAM_IRQ_NR: 3036 case RADEON_PARAM_IRQ_NR:
3030 value = drm_dev_to_irq(dev); 3037 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
3038 value = 0;
3039 else
3040 value = drm_dev_to_irq(dev);
3031 break; 3041 break;
3032 case RADEON_PARAM_GART_BASE: 3042 case RADEON_PARAM_GART_BASE:
3033 value = dev_priv->gart_vm_start; 3043 value = dev_priv->gart_vm_start;
@@ -3227,7 +3237,8 @@ struct drm_ioctl_desc radeon_ioctls[] = {
3227 DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH), 3237 DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH),
3228 DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH), 3238 DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH),
3229 DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH), 3239 DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH),
3230 DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH) 3240 DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH),
3241 DRM_IOCTL_DEF(DRM_RADEON_CS, r600_cs_legacy_ioctl, DRM_AUTH)
3231}; 3242};
3232 3243
3233int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); 3244int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 15c3531377ed..acd889c94549 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -35,11 +35,14 @@
35#include <ttm/ttm_module.h> 35#include <ttm/ttm_module.h>
36#include <drm/drmP.h> 36#include <drm/drmP.h>
37#include <drm/radeon_drm.h> 37#include <drm/radeon_drm.h>
38#include <linux/seq_file.h>
38#include "radeon_reg.h" 39#include "radeon_reg.h"
39#include "radeon.h" 40#include "radeon.h"
40 41
41#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 42#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
42 43
44static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
45
43static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) 46static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
44{ 47{
45 struct radeon_mman *mman; 48 struct radeon_mman *mman;
@@ -77,9 +80,25 @@ static int radeon_ttm_global_init(struct radeon_device *rdev)
77 global_ref->release = &radeon_ttm_mem_global_release; 80 global_ref->release = &radeon_ttm_mem_global_release;
78 r = ttm_global_item_ref(global_ref); 81 r = ttm_global_item_ref(global_ref);
79 if (r != 0) { 82 if (r != 0) {
80 DRM_ERROR("Failed referencing a global TTM memory object.\n"); 83 DRM_ERROR("Failed setting up TTM memory accounting "
84 "subsystem.\n");
85 return r;
86 }
87
88 rdev->mman.bo_global_ref.mem_glob =
89 rdev->mman.mem_global_ref.object;
90 global_ref = &rdev->mman.bo_global_ref.ref;
91 global_ref->global_type = TTM_GLOBAL_TTM_BO;
92 global_ref->size = sizeof(struct ttm_bo_global);
93 global_ref->init = &ttm_bo_global_init;
94 global_ref->release = &ttm_bo_global_release;
95 r = ttm_global_item_ref(global_ref);
96 if (r != 0) {
97 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
98 ttm_global_item_unref(&rdev->mman.mem_global_ref);
81 return r; 99 return r;
82 } 100 }
101
83 rdev->mman.mem_global_referenced = true; 102 rdev->mman.mem_global_referenced = true;
84 return 0; 103 return 0;
85} 104}
@@ -87,6 +106,7 @@ static int radeon_ttm_global_init(struct radeon_device *rdev)
87static void radeon_ttm_global_fini(struct radeon_device *rdev) 106static void radeon_ttm_global_fini(struct radeon_device *rdev)
88{ 107{
89 if (rdev->mman.mem_global_referenced) { 108 if (rdev->mman.mem_global_referenced) {
109 ttm_global_item_unref(&rdev->mman.bo_global_ref.ref);
90 ttm_global_item_unref(&rdev->mman.mem_global_ref); 110 ttm_global_item_unref(&rdev->mman.mem_global_ref);
91 rdev->mman.mem_global_referenced = false; 111 rdev->mman.mem_global_referenced = false;
92 } 112 }
@@ -286,9 +306,11 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
286 r = ttm_bo_move_ttm(bo, true, no_wait, new_mem); 306 r = ttm_bo_move_ttm(bo, true, no_wait, new_mem);
287out_cleanup: 307out_cleanup:
288 if (tmp_mem.mm_node) { 308 if (tmp_mem.mm_node) {
289 spin_lock(&rdev->mman.bdev.lru_lock); 309 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
310
311 spin_lock(&glob->lru_lock);
290 drm_mm_put_block(tmp_mem.mm_node); 312 drm_mm_put_block(tmp_mem.mm_node);
291 spin_unlock(&rdev->mman.bdev.lru_lock); 313 spin_unlock(&glob->lru_lock);
292 return r; 314 return r;
293 } 315 }
294 return r; 316 return r;
@@ -323,9 +345,11 @@ static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
323 } 345 }
324out_cleanup: 346out_cleanup:
325 if (tmp_mem.mm_node) { 347 if (tmp_mem.mm_node) {
326 spin_lock(&rdev->mman.bdev.lru_lock); 348 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
349
350 spin_lock(&glob->lru_lock);
327 drm_mm_put_block(tmp_mem.mm_node); 351 drm_mm_put_block(tmp_mem.mm_node);
328 spin_unlock(&rdev->mman.bdev.lru_lock); 352 spin_unlock(&glob->lru_lock);
329 return r; 353 return r;
330 } 354 }
331 return r; 355 return r;
@@ -352,9 +376,8 @@ static int radeon_bo_move(struct ttm_buffer_object *bo,
352 radeon_move_null(bo, new_mem); 376 radeon_move_null(bo, new_mem);
353 return 0; 377 return 0;
354 } 378 }
355 if (!rdev->cp.ready) { 379 if (!rdev->cp.ready || rdev->asic->copy == NULL) {
356 /* use memcpy */ 380 /* use memcpy */
357 DRM_ERROR("CP is not ready use memcpy.\n");
358 goto memcpy; 381 goto memcpy;
359 } 382 }
360 383
@@ -446,7 +469,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
446 } 469 }
447 /* No others user of address space so set it to 0 */ 470 /* No others user of address space so set it to 0 */
448 r = ttm_bo_device_init(&rdev->mman.bdev, 471 r = ttm_bo_device_init(&rdev->mman.bdev,
449 rdev->mman.mem_global_ref.object, 472 rdev->mman.bo_global_ref.ref.object,
450 &radeon_bo_driver, DRM_FILE_PAGE_OFFSET, 473 &radeon_bo_driver, DRM_FILE_PAGE_OFFSET,
451 rdev->need_dma32); 474 rdev->need_dma32);
452 if (r) { 475 if (r) {
@@ -471,7 +494,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
471 return r; 494 return r;
472 } 495 }
473 DRM_INFO("radeon: %uM of VRAM memory ready\n", 496 DRM_INFO("radeon: %uM of VRAM memory ready\n",
474 rdev->mc.real_vram_size / (1024 * 1024)); 497 (unsigned)rdev->mc.real_vram_size / (1024 * 1024));
475 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 0, 498 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 0,
476 ((rdev->mc.gtt_size) >> PAGE_SHIFT)); 499 ((rdev->mc.gtt_size) >> PAGE_SHIFT));
477 if (r) { 500 if (r) {
@@ -479,10 +502,16 @@ int radeon_ttm_init(struct radeon_device *rdev)
479 return r; 502 return r;
480 } 503 }
481 DRM_INFO("radeon: %uM of GTT memory ready.\n", 504 DRM_INFO("radeon: %uM of GTT memory ready.\n",
482 rdev->mc.gtt_size / (1024 * 1024)); 505 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
483 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { 506 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
484 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; 507 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
485 } 508 }
509
510 r = radeon_ttm_debugfs_init(rdev);
511 if (r) {
512 DRM_ERROR("Failed to init debugfs\n");
513 return r;
514 }
486 return 0; 515 return 0;
487} 516}
488 517
@@ -657,3 +686,50 @@ struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev)
657 gtt->bound = false; 686 gtt->bound = false;
658 return &gtt->backend; 687 return &gtt->backend;
659} 688}
689
690#define RADEON_DEBUGFS_MEM_TYPES 2
691
692static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES];
693static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES][32];
694
695#if defined(CONFIG_DEBUG_FS)
696static int radeon_mm_dump_table(struct seq_file *m, void *data)
697{
698 struct drm_info_node *node = (struct drm_info_node *)m->private;
699 struct drm_mm *mm = (struct drm_mm *)node->info_ent->data;
700 struct drm_device *dev = node->minor->dev;
701 struct radeon_device *rdev = dev->dev_private;
702 int ret;
703 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
704
705 spin_lock(&glob->lru_lock);
706 ret = drm_mm_dump_table(m, mm);
707 spin_unlock(&glob->lru_lock);
708 return ret;
709}
710#endif
711
712static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
713{
714 unsigned i;
715
716#if defined(CONFIG_DEBUG_FS)
717 for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) {
718 if (i == 0)
719 sprintf(radeon_mem_types_names[i], "radeon_vram_mm");
720 else
721 sprintf(radeon_mem_types_names[i], "radeon_gtt_mm");
722 radeon_mem_types_list[i].name = radeon_mem_types_names[i];
723 radeon_mem_types_list[i].show = &radeon_mm_dump_table;
724 radeon_mem_types_list[i].driver_features = 0;
725 if (i == 0)
726 radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_VRAM].manager;
727 else
728 radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_TT].manager;
729
730 }
731 return radeon_debugfs_add_files(rdev, radeon_mem_types_list, RADEON_DEBUGFS_MEM_TYPES);
732
733#endif
734 return 0;
735}
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r100 b/drivers/gpu/drm/radeon/reg_srcs/r100
new file mode 100644
index 000000000000..f7ee062f1184
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/r100
@@ -0,0 +1,105 @@
1r100 0x3294
20x1434 SRC_Y_X
30x1438 DST_Y_X
40x143C DST_HEIGHT_WIDTH
50x146C DP_GUI_MASTER_CNTL
60x1474 BRUSH_Y_X
70x1478 DP_BRUSH_BKGD_CLR
80x147C DP_BRUSH_FRGD_CLR
90x1480 BRUSH_DATA0
100x1484 BRUSH_DATA1
110x1598 DST_WIDTH_HEIGHT
120x15C0 CLR_CMP_CNTL
130x15C4 CLR_CMP_CLR_SRC
140x15C8 CLR_CMP_CLR_DST
150x15CC CLR_CMP_MSK
160x15D8 DP_SRC_FRGD_CLR
170x15DC DP_SRC_BKGD_CLR
180x1600 DST_LINE_START
190x1604 DST_LINE_END
200x1608 DST_LINE_PATCOUNT
210x16C0 DP_CNTL
220x16CC DP_WRITE_MSK
230x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
240x16E8 DEFAULT_SC_BOTTOM_RIGHT
250x16EC SC_TOP_LEFT
260x16F0 SC_BOTTOM_RIGHT
270x16F4 SRC_SC_BOTTOM_RIGHT
280x1714 DSTCACHE_CTLSTAT
290x1720 WAIT_UNTIL
300x172C RBBM_GUICNTL
310x1810 FOG_3D_TABLE_START
320x1814 FOG_3D_TABLE_END
330x1a14 FOG_TABLE_INDEX
340x1a18 FOG_TABLE_DATA
350x1c14 PP_MISC
360x1c18 PP_FOG_COLOR
370x1c1c RE_SOLID_COLOR
380x1c20 RB3D_BLENDCNTL
390x1c4c SE_CNTL
400x1c50 SE_COORD_FMT
410x1c60 PP_TXCBLEND_0
420x1c64 PP_TXABLEND_0
430x1c68 PP_TFACTOR_0
440x1c78 PP_TXCBLEND_1
450x1c7c PP_TXABLEND_1
460x1c80 PP_TFACTOR_1
470x1c90 PP_TXCBLEND_2
480x1c94 PP_TXABLEND_2
490x1c98 PP_TFACTOR_2
500x1cc8 RE_STIPPLE_ADDR
510x1ccc RE_STIPPLE_DATA
520x1cd0 RE_LINE_PATTERN
530x1cd4 RE_LINE_STATE
540x1d40 PP_BORDER_COLOR0
550x1d44 PP_BORDER_COLOR1
560x1d48 PP_BORDER_COLOR2
570x1d7c RB3D_STENCILREFMASK
580x1d80 RB3D_ROPCNTL
590x1d84 RB3D_PLANEMASK
600x1d98 VAP_VPORT_XSCALE
610x1d9C VAP_VPORT_XOFFSET
620x1da0 VAP_VPORT_YSCALE
630x1da4 VAP_VPORT_YOFFSET
640x1da8 VAP_VPORT_ZSCALE
650x1dac VAP_VPORT_ZOFFSET
660x1db0 SE_ZBIAS_FACTOR
670x1db4 SE_ZBIAS_CONSTANT
680x1db8 SE_LINE_WIDTH
690x2140 SE_CNTL_STATUS
700x2200 SE_TCL_VECTOR_INDX_REG
710x2204 SE_TCL_VECTOR_DATA_REG
720x2208 SE_TCL_SCALAR_INDX_REG
730x220c SE_TCL_SCALAR_DATA_REG
740x2210 SE_TCL_MATERIAL_EMISSIVE_RED
750x2214 SE_TCL_MATERIAL_EMISSIVE_GREEN
760x2218 SE_TCL_MATERIAL_EMISSIVE_BLUE
770x221c SE_TCL_MATERIAL_EMISSIVE_ALPHA
780x2220 SE_TCL_MATERIAL_AMBIENT_RED
790x2224 SE_TCL_MATERIAL_AMBIENT_GREEN
800x2228 SE_TCL_MATERIAL_AMBIENT_BLUE
810x222c SE_TCL_MATERIAL_AMBIENT_ALPHA
820x2230 SE_TCL_MATERIAL_DIFFUSE_RED
830x2234 SE_TCL_MATERIAL_DIFFUSE_GREEN
840x2238 SE_TCL_MATERIAL_DIFFUSE_BLUE
850x223c SE_TCL_MATERIAL_DIFFUSE_ALPHA
860x2240 SE_TCL_MATERIAL_SPECULAR_RED
870x2244 SE_TCL_MATERIAL_SPECULAR_GREEN
880x2248 SE_TCL_MATERIAL_SPECULAR_BLUE
890x224c SE_TCL_MATERIAL_SPECULAR_ALPHA
900x2250 SE_TCL_SHININESS
910x2254 SE_TCL_OUTPUT_VTX_FMT
920x2258 SE_TCL_OUTPUT_VTX_SEL
930x225c SE_TCL_MATRIX_SELECT_0
940x2260 SE_TCL_MATRIX_SELECT_1
950x2264 SE_TCL_UCP_VERT_BLEND_CNTL
960x2268 SE_TCL_TEXTURE_PROC_CTL
970x226c SE_TCL_LIGHT_MODEL_CTL
980x2270 SE_TCL_PER_LIGHT_CTL_0
990x2274 SE_TCL_PER_LIGHT_CTL_1
1000x2278 SE_TCL_PER_LIGHT_CTL_2
1010x227c SE_TCL_PER_LIGHT_CTL_3
1020x2284 SE_TCL_STATE_FLUSH
1030x26c0 RE_TOP_LEFT
1040x26c4 RE_MISC
1050x3290 RB3D_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r200 b/drivers/gpu/drm/radeon/reg_srcs/r200
new file mode 100644
index 000000000000..6021c8849a16
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/r200
@@ -0,0 +1,184 @@
1r200 0x3294
20x1434 SRC_Y_X
30x1438 DST_Y_X
40x143C DST_HEIGHT_WIDTH
50x146C DP_GUI_MASTER_CNTL
60x1474 BRUSH_Y_X
70x1478 DP_BRUSH_BKGD_CLR
80x147C DP_BRUSH_FRGD_CLR
90x1480 BRUSH_DATA0
100x1484 BRUSH_DATA1
110x1598 DST_WIDTH_HEIGHT
120x15C0 CLR_CMP_CNTL
130x15C4 CLR_CMP_CLR_SRC
140x15C8 CLR_CMP_CLR_DST
150x15CC CLR_CMP_MSK
160x15D8 DP_SRC_FRGD_CLR
170x15DC DP_SRC_BKGD_CLR
180x1600 DST_LINE_START
190x1604 DST_LINE_END
200x1608 DST_LINE_PATCOUNT
210x16C0 DP_CNTL
220x16CC DP_WRITE_MSK
230x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
240x16E8 DEFAULT_SC_BOTTOM_RIGHT
250x16EC SC_TOP_LEFT
260x16F0 SC_BOTTOM_RIGHT
270x16F4 SRC_SC_BOTTOM_RIGHT
280x1714 DSTCACHE_CTLSTAT
290x1720 WAIT_UNTIL
300x172C RBBM_GUICNTL
310x1c14 PP_MISC
320x1c18 PP_FOG_COLOR
330x1c1c RE_SOLID_COLOR
340x1c20 RB3D_BLENDCNTL
350x1c4c SE_CNTL
360x1c50 RE_CNTL
370x1cc8 RE_STIPPLE_ADDR
380x1ccc RE_STIPPLE_DATA
390x1cd0 RE_LINE_PATTERN
400x1cd4 RE_LINE_STATE
410x1cd8 RE_SCISSOR_TL_0
420x1cdc RE_SCISSOR_BR_0
430x1ce0 RE_SCISSOR_TL_1
440x1ce4 RE_SCISSOR_BR_1
450x1ce8 RE_SCISSOR_TL_2
460x1cec RE_SCISSOR_BR_2
470x1d60 RB3D_DEPTHXY_OFFSET
480x1d7c RB3D_STENCILREFMASK
490x1d80 RB3D_ROPCNTL
500x1d84 RB3D_PLANEMASK
510x1d98 VAP_VPORT_XSCALE
520x1d9c VAP_VPORT_XOFFSET
530x1da0 VAP_VPORT_YSCALE
540x1da4 VAP_VPORT_YOFFSET
550x1da8 VAP_VPORT_ZSCALE
560x1dac VAP_VPORT_ZOFFSET
570x1db0 SE_ZBIAS_FACTOR
580x1db4 SE_ZBIAS_CONSTANT
590x1db8 SE_LINE_WIDTH
600x2080 SE_VAP_CNTL
610x2090 SE_TCL_OUTPUT_VTX_FMT_0
620x2094 SE_TCL_OUTPUT_VTX_FMT_1
630x20b0 SE_VTE_CNTL
640x2140 SE_CNTL_STATUS
650x2180 SE_VTX_STATE_CNTL
660x2200 SE_TCL_VECTOR_INDX_REG
670x2204 SE_TCL_VECTOR_DATA_REG
680x2208 SE_TCL_SCALAR_INDX_REG
690x220c SE_TCL_SCALAR_DATA_REG
700x2230 SE_TCL_MATRIX_SEL_0
710x2234 SE_TCL_MATRIX_SEL_1
720x2238 SE_TCL_MATRIX_SEL_2
730x223c SE_TCL_MATRIX_SEL_3
740x2240 SE_TCL_MATRIX_SEL_4
750x2250 SE_TCL_OUTPUT_VTX_COMP_SEL
760x2254 SE_TCL_INPUT_VTX_VECTOR_ADDR_0
770x2258 SE_TCL_INPUT_VTX_VECTOR_ADDR_1
780x225c SE_TCL_INPUT_VTX_VECTOR_ADDR_2
790x2260 SE_TCL_INPUT_VTX_VECTOR_ADDR_3
800x2268 SE_TCL_LIGHT_MODEL_CTL_0
810x226c SE_TCL_LIGHT_MODEL_CTL_1
820x2270 SE_TCL_PER_LIGHT_CTL_0
830x2274 SE_TCL_PER_LIGHT_CTL_1
840x2278 SE_TCL_PER_LIGHT_CTL_2
850x227c SE_TCL_PER_LIGHT_CTL_3
860x2284 VAP_PVS_STATE_FLUSH_REG
870x22a8 SE_TCL_TEX_PROC_CTL_2
880x22ac SE_TCL_TEX_PROC_CTL_3
890x22b0 SE_TCL_TEX_PROC_CTL_0
900x22b4 SE_TCL_TEX_PROC_CTL_1
910x22b8 SE_TCL_TEX_CYL_WRAP_CTL
920x22c0 SE_TCL_UCP_VERT_BLEND_CNTL
930x22c4 SE_TCL_POINT_SPRITE_CNTL
940x2648 RE_POINTSIZE
950x26c0 RE_TOP_LEFT
960x26c4 RE_MISC
970x26f0 RE_AUX_SCISSOR_CNTL
980x2c14 PP_BORDER_COLOR_0
990x2c34 PP_BORDER_COLOR_1
1000x2c54 PP_BORDER_COLOR_2
1010x2c74 PP_BORDER_COLOR_3
1020x2c94 PP_BORDER_COLOR_4
1030x2cb4 PP_BORDER_COLOR_5
1040x2cc4 PP_CNTL_X
1050x2cf8 PP_TRI_PERF
1060x2cfc PP_PERF_CNTL
1070x2d9c PP_TAM_DEBUG3
1080x2ee0 PP_TFACTOR_0
1090x2ee4 PP_TFACTOR_1
1100x2ee8 PP_TFACTOR_2
1110x2eec PP_TFACTOR_3
1120x2ef0 PP_TFACTOR_4
1130x2ef4 PP_TFACTOR_5
1140x2ef8 PP_TFACTOR_6
1150x2efc PP_TFACTOR_7
1160x2f00 PP_TXCBLEND_0
1170x2f04 PP_TXCBLEND2_0
1180x2f08 PP_TXABLEND_0
1190x2f0c PP_TXABLEND2_0
1200x2f10 PP_TXCBLEND_1
1210x2f14 PP_TXCBLEND2_1
1220x2f18 PP_TXABLEND_1
1230x2f1c PP_TXABLEND2_1
1240x2f20 PP_TXCBLEND_2
1250x2f24 PP_TXCBLEND2_2
1260x2f28 PP_TXABLEND_2
1270x2f2c PP_TXABLEND2_2
1280x2f30 PP_TXCBLEND_3
1290x2f34 PP_TXCBLEND2_3
1300x2f38 PP_TXABLEND_3
1310x2f3c PP_TXABLEND2_3
1320x2f40 PP_TXCBLEND_4
1330x2f44 PP_TXCBLEND2_4
1340x2f48 PP_TXABLEND_4
1350x2f4c PP_TXABLEND2_4
1360x2f50 PP_TXCBLEND_5
1370x2f54 PP_TXCBLEND2_5
1380x2f58 PP_TXABLEND_5
1390x2f5c PP_TXABLEND2_5
1400x2f60 PP_TXCBLEND_6
1410x2f64 PP_TXCBLEND2_6
1420x2f68 PP_TXABLEND_6
1430x2f6c PP_TXABLEND2_6
1440x2f70 PP_TXCBLEND_7
1450x2f74 PP_TXCBLEND2_7
1460x2f78 PP_TXABLEND_7
1470x2f7c PP_TXABLEND2_7
1480x2f80 PP_TXCBLEND_8
1490x2f84 PP_TXCBLEND2_8
1500x2f88 PP_TXABLEND_8
1510x2f8c PP_TXABLEND2_8
1520x2f90 PP_TXCBLEND_9
1530x2f94 PP_TXCBLEND2_9
1540x2f98 PP_TXABLEND_9
1550x2f9c PP_TXABLEND2_9
1560x2fa0 PP_TXCBLEND_10
1570x2fa4 PP_TXCBLEND2_10
1580x2fa8 PP_TXABLEND_10
1590x2fac PP_TXABLEND2_10
1600x2fb0 PP_TXCBLEND_11
1610x2fb4 PP_TXCBLEND2_11
1620x2fb8 PP_TXABLEND_11
1630x2fbc PP_TXABLEND2_11
1640x2fc0 PP_TXCBLEND_12
1650x2fc4 PP_TXCBLEND2_12
1660x2fc8 PP_TXABLEND_12
1670x2fcc PP_TXABLEND2_12
1680x2fd0 PP_TXCBLEND_13
1690x2fd4 PP_TXCBLEND2_13
1700x2fd8 PP_TXABLEND_13
1710x2fdc PP_TXABLEND2_13
1720x2fe0 PP_TXCBLEND_14
1730x2fe4 PP_TXCBLEND2_14
1740x2fe8 PP_TXABLEND_14
1750x2fec PP_TXABLEND2_14
1760x2ff0 PP_TXCBLEND_15
1770x2ff4 PP_TXCBLEND2_15
1780x2ff8 PP_TXABLEND_15
1790x2ffc PP_TXABLEND2_15
1800x3218 RB3D_BLENCOLOR
1810x321c RB3D_ABLENDCNTL
1820x3220 RB3D_CBLENDCNTL
1830x3290 RB3D_ZPASS_DATA
184
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300
new file mode 100644
index 000000000000..19c4663fa9c6
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/r300
@@ -0,0 +1,729 @@
1r300 0x4f60
20x1434 SRC_Y_X
30x1438 DST_Y_X
40x143C DST_HEIGHT_WIDTH
50x146C DP_GUI_MASTER_CNTL
60x1474 BRUSH_Y_X
70x1478 DP_BRUSH_BKGD_CLR
80x147C DP_BRUSH_FRGD_CLR
90x1480 BRUSH_DATA0
100x1484 BRUSH_DATA1
110x1598 DST_WIDTH_HEIGHT
120x15C0 CLR_CMP_CNTL
130x15C4 CLR_CMP_CLR_SRC
140x15C8 CLR_CMP_CLR_DST
150x15CC CLR_CMP_MSK
160x15D8 DP_SRC_FRGD_CLR
170x15DC DP_SRC_BKGD_CLR
180x1600 DST_LINE_START
190x1604 DST_LINE_END
200x1608 DST_LINE_PATCOUNT
210x16C0 DP_CNTL
220x16CC DP_WRITE_MSK
230x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
240x16E8 DEFAULT_SC_BOTTOM_RIGHT
250x16EC SC_TOP_LEFT
260x16F0 SC_BOTTOM_RIGHT
270x16F4 SRC_SC_BOTTOM_RIGHT
280x1714 DSTCACHE_CTLSTAT
290x1720 WAIT_UNTIL
300x172C RBBM_GUICNTL
310x1D98 VAP_VPORT_XSCALE
320x1D9C VAP_VPORT_XOFFSET
330x1DA0 VAP_VPORT_YSCALE
340x1DA4 VAP_VPORT_YOFFSET
350x1DA8 VAP_VPORT_ZSCALE
360x1DAC VAP_VPORT_ZOFFSET
370x2080 VAP_CNTL
380x2090 VAP_OUT_VTX_FMT_0
390x2094 VAP_OUT_VTX_FMT_1
400x20B0 VAP_VTE_CNTL
410x2138 VAP_VF_MIN_VTX_INDX
420x2140 VAP_CNTL_STATUS
430x2150 VAP_PROG_STREAM_CNTL_0
440x2154 VAP_PROG_STREAM_CNTL_1
450x2158 VAP_PROG_STREAM_CNTL_2
460x215C VAP_PROG_STREAM_CNTL_3
470x2160 VAP_PROG_STREAM_CNTL_4
480x2164 VAP_PROG_STREAM_CNTL_5
490x2168 VAP_PROG_STREAM_CNTL_6
500x216C VAP_PROG_STREAM_CNTL_7
510x2180 VAP_VTX_STATE_CNTL
520x2184 VAP_VSM_VTX_ASSM
530x2188 VAP_VTX_STATE_IND_REG_0
540x218C VAP_VTX_STATE_IND_REG_1
550x2190 VAP_VTX_STATE_IND_REG_2
560x2194 VAP_VTX_STATE_IND_REG_3
570x2198 VAP_VTX_STATE_IND_REG_4
580x219C VAP_VTX_STATE_IND_REG_5
590x21A0 VAP_VTX_STATE_IND_REG_6
600x21A4 VAP_VTX_STATE_IND_REG_7
610x21A8 VAP_VTX_STATE_IND_REG_8
620x21AC VAP_VTX_STATE_IND_REG_9
630x21B0 VAP_VTX_STATE_IND_REG_10
640x21B4 VAP_VTX_STATE_IND_REG_11
650x21B8 VAP_VTX_STATE_IND_REG_12
660x21BC VAP_VTX_STATE_IND_REG_13
670x21C0 VAP_VTX_STATE_IND_REG_14
680x21C4 VAP_VTX_STATE_IND_REG_15
690x21DC VAP_PSC_SGN_NORM_CNTL
700x21E0 VAP_PROG_STREAM_CNTL_EXT_0
710x21E4 VAP_PROG_STREAM_CNTL_EXT_1
720x21E8 VAP_PROG_STREAM_CNTL_EXT_2
730x21EC VAP_PROG_STREAM_CNTL_EXT_3
740x21F0 VAP_PROG_STREAM_CNTL_EXT_4
750x21F4 VAP_PROG_STREAM_CNTL_EXT_5
760x21F8 VAP_PROG_STREAM_CNTL_EXT_6
770x21FC VAP_PROG_STREAM_CNTL_EXT_7
780x2200 VAP_PVS_VECTOR_INDX_REG
790x2204 VAP_PVS_VECTOR_DATA_REG
800x2208 VAP_PVS_VECTOR_DATA_REG_128
810x221C VAP_CLIP_CNTL
820x2220 VAP_GB_VERT_CLIP_ADJ
830x2224 VAP_GB_VERT_DISC_ADJ
840x2228 VAP_GB_HORZ_CLIP_ADJ
850x222C VAP_GB_HORZ_DISC_ADJ
860x2230 VAP_PVS_FLOW_CNTL_ADDRS_0
870x2234 VAP_PVS_FLOW_CNTL_ADDRS_1
880x2238 VAP_PVS_FLOW_CNTL_ADDRS_2
890x223C VAP_PVS_FLOW_CNTL_ADDRS_3
900x2240 VAP_PVS_FLOW_CNTL_ADDRS_4
910x2244 VAP_PVS_FLOW_CNTL_ADDRS_5
920x2248 VAP_PVS_FLOW_CNTL_ADDRS_6
930x224C VAP_PVS_FLOW_CNTL_ADDRS_7
940x2250 VAP_PVS_FLOW_CNTL_ADDRS_8
950x2254 VAP_PVS_FLOW_CNTL_ADDRS_9
960x2258 VAP_PVS_FLOW_CNTL_ADDRS_10
970x225C VAP_PVS_FLOW_CNTL_ADDRS_11
980x2260 VAP_PVS_FLOW_CNTL_ADDRS_12
990x2264 VAP_PVS_FLOW_CNTL_ADDRS_13
1000x2268 VAP_PVS_FLOW_CNTL_ADDRS_14
1010x226C VAP_PVS_FLOW_CNTL_ADDRS_15
1020x2284 VAP_PVS_STATE_FLUSH_REG
1030x2288 VAP_PVS_VTX_TIMEOUT_REG
1040x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
1050x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1
1060x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2
1070x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3
1080x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4
1090x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5
1100x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6
1110x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7
1120x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8
1130x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9
1140x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10
1150x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11
1160x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12
1170x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13
1180x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14
1190x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15
1200x22D0 VAP_PVS_CODE_CNTL_0
1210x22D4 VAP_PVS_CONST_CNTL
1220x22D8 VAP_PVS_CODE_CNTL_1
1230x22DC VAP_PVS_FLOW_CNTL_OPC
1240x342C RB2D_DSTCACHE_CTLSTAT
1250x4000 GB_VAP_RASTER_VTX_FMT_0
1260x4004 GB_VAP_RASTER_VTX_FMT_1
1270x4008 GB_ENABLE
1280x401C GB_SELECT
1290x4020 GB_AA_CONFIG
1300x4024 GB_FIFO_SIZE
1310x4100 TX_INVALTAGS
1320x4200 GA_POINT_S0
1330x4204 GA_POINT_T0
1340x4208 GA_POINT_S1
1350x420C GA_POINT_T1
1360x4214 GA_TRIANGLE_STIPPLE
1370x421C GA_POINT_SIZE
1380x4230 GA_POINT_MINMAX
1390x4234 GA_LINE_CNTL
1400x4238 GA_LINE_STIPPLE_CONFIG
1410x4260 GA_LINE_STIPPLE_VALUE
1420x4264 GA_LINE_S0
1430x4268 GA_LINE_S1
1440x4278 GA_COLOR_CONTROL
1450x427C GA_SOLID_RG
1460x4280 GA_SOLID_BA
1470x4288 GA_POLY_MODE
1480x428C GA_ROUND_MODE
1490x4290 GA_OFFSET
1500x4294 GA_FOG_SCALE
1510x4298 GA_FOG_OFFSET
1520x42A0 SU_TEX_WRAP
1530x42A4 SU_POLY_OFFSET_FRONT_SCALE
1540x42A8 SU_POLY_OFFSET_FRONT_OFFSET
1550x42AC SU_POLY_OFFSET_BACK_SCALE
1560x42B0 SU_POLY_OFFSET_BACK_OFFSET
1570x42B4 SU_POLY_OFFSET_ENABLE
1580x42B8 SU_CULL_MODE
1590x42C0 SU_DEPTH_SCALE
1600x42C4 SU_DEPTH_OFFSET
1610x42C8 SU_REG_DEST
1620x4300 RS_COUNT
1630x4304 RS_INST_COUNT
1640x4310 RS_IP_0
1650x4314 RS_IP_1
1660x4318 RS_IP_2
1670x431C RS_IP_3
1680x4320 RS_IP_4
1690x4324 RS_IP_5
1700x4328 RS_IP_6
1710x432C RS_IP_7
1720x4330 RS_INST_0
1730x4334 RS_INST_1
1740x4338 RS_INST_2
1750x433C RS_INST_3
1760x4340 RS_INST_4
1770x4344 RS_INST_5
1780x4348 RS_INST_6
1790x434C RS_INST_7
1800x4350 RS_INST_8
1810x4354 RS_INST_9
1820x4358 RS_INST_10
1830x435C RS_INST_11
1840x4360 RS_INST_12
1850x4364 RS_INST_13
1860x4368 RS_INST_14
1870x436C RS_INST_15
1880x43A4 SC_HYPERZ_EN
1890x43A8 SC_EDGERULE
1900x43B0 SC_CLIP_0_A
1910x43B4 SC_CLIP_0_B
1920x43B8 SC_CLIP_1_A
1930x43BC SC_CLIP_1_B
1940x43C0 SC_CLIP_2_A
1950x43C4 SC_CLIP_2_B
1960x43C8 SC_CLIP_3_A
1970x43CC SC_CLIP_3_B
1980x43D0 SC_CLIP_RULE
1990x43E0 SC_SCISSOR0
2000x43E8 SC_SCREENDOOR
2010x4440 TX_FILTER1_0
2020x4444 TX_FILTER1_1
2030x4448 TX_FILTER1_2
2040x444C TX_FILTER1_3
2050x4450 TX_FILTER1_4
2060x4454 TX_FILTER1_5
2070x4458 TX_FILTER1_6
2080x445C TX_FILTER1_7
2090x4460 TX_FILTER1_8
2100x4464 TX_FILTER1_9
2110x4468 TX_FILTER1_10
2120x446C TX_FILTER1_11
2130x4470 TX_FILTER1_12
2140x4474 TX_FILTER1_13
2150x4478 TX_FILTER1_14
2160x447C TX_FILTER1_15
2170x4580 TX_CHROMA_KEY_0
2180x4584 TX_CHROMA_KEY_1
2190x4588 TX_CHROMA_KEY_2
2200x458C TX_CHROMA_KEY_3
2210x4590 TX_CHROMA_KEY_4
2220x4594 TX_CHROMA_KEY_5
2230x4598 TX_CHROMA_KEY_6
2240x459C TX_CHROMA_KEY_7
2250x45A0 TX_CHROMA_KEY_8
2260x45A4 TX_CHROMA_KEY_9
2270x45A8 TX_CHROMA_KEY_10
2280x45AC TX_CHROMA_KEY_11
2290x45B0 TX_CHROMA_KEY_12
2300x45B4 TX_CHROMA_KEY_13
2310x45B8 TX_CHROMA_KEY_14
2320x45BC TX_CHROMA_KEY_15
2330x45C0 TX_BORDER_COLOR_0
2340x45C4 TX_BORDER_COLOR_1
2350x45C8 TX_BORDER_COLOR_2
2360x45CC TX_BORDER_COLOR_3
2370x45D0 TX_BORDER_COLOR_4
2380x45D4 TX_BORDER_COLOR_5
2390x45D8 TX_BORDER_COLOR_6
2400x45DC TX_BORDER_COLOR_7
2410x45E0 TX_BORDER_COLOR_8
2420x45E4 TX_BORDER_COLOR_9
2430x45E8 TX_BORDER_COLOR_10
2440x45EC TX_BORDER_COLOR_11
2450x45F0 TX_BORDER_COLOR_12
2460x45F4 TX_BORDER_COLOR_13
2470x45F8 TX_BORDER_COLOR_14
2480x45FC TX_BORDER_COLOR_15
2490x4600 US_CONFIG
2500x4604 US_PIXSIZE
2510x4608 US_CODE_OFFSET
2520x460C US_RESET
2530x4610 US_CODE_ADDR_0
2540x4614 US_CODE_ADDR_1
2550x4618 US_CODE_ADDR_2
2560x461C US_CODE_ADDR_3
2570x4620 US_TEX_INST_0
2580x4624 US_TEX_INST_1
2590x4628 US_TEX_INST_2
2600x462C US_TEX_INST_3
2610x4630 US_TEX_INST_4
2620x4634 US_TEX_INST_5
2630x4638 US_TEX_INST_6
2640x463C US_TEX_INST_7
2650x4640 US_TEX_INST_8
2660x4644 US_TEX_INST_9
2670x4648 US_TEX_INST_10
2680x464C US_TEX_INST_11
2690x4650 US_TEX_INST_12
2700x4654 US_TEX_INST_13
2710x4658 US_TEX_INST_14
2720x465C US_TEX_INST_15
2730x4660 US_TEX_INST_16
2740x4664 US_TEX_INST_17
2750x4668 US_TEX_INST_18
2760x466C US_TEX_INST_19
2770x4670 US_TEX_INST_20
2780x4674 US_TEX_INST_21
2790x4678 US_TEX_INST_22
2800x467C US_TEX_INST_23
2810x4680 US_TEX_INST_24
2820x4684 US_TEX_INST_25
2830x4688 US_TEX_INST_26
2840x468C US_TEX_INST_27
2850x4690 US_TEX_INST_28
2860x4694 US_TEX_INST_29
2870x4698 US_TEX_INST_30
2880x469C US_TEX_INST_31
2890x46A4 US_OUT_FMT_0
2900x46A8 US_OUT_FMT_1
2910x46AC US_OUT_FMT_2
2920x46B0 US_OUT_FMT_3
2930x46B4 US_W_FMT
2940x46C0 US_ALU_RGB_ADDR_0
2950x46C4 US_ALU_RGB_ADDR_1
2960x46C8 US_ALU_RGB_ADDR_2
2970x46CC US_ALU_RGB_ADDR_3
2980x46D0 US_ALU_RGB_ADDR_4
2990x46D4 US_ALU_RGB_ADDR_5
3000x46D8 US_ALU_RGB_ADDR_6
3010x46DC US_ALU_RGB_ADDR_7
3020x46E0 US_ALU_RGB_ADDR_8
3030x46E4 US_ALU_RGB_ADDR_9
3040x46E8 US_ALU_RGB_ADDR_10
3050x46EC US_ALU_RGB_ADDR_11
3060x46F0 US_ALU_RGB_ADDR_12
3070x46F4 US_ALU_RGB_ADDR_13
3080x46F8 US_ALU_RGB_ADDR_14
3090x46FC US_ALU_RGB_ADDR_15
3100x4700 US_ALU_RGB_ADDR_16
3110x4704 US_ALU_RGB_ADDR_17
3120x4708 US_ALU_RGB_ADDR_18
3130x470C US_ALU_RGB_ADDR_19
3140x4710 US_ALU_RGB_ADDR_20
3150x4714 US_ALU_RGB_ADDR_21
3160x4718 US_ALU_RGB_ADDR_22
3170x471C US_ALU_RGB_ADDR_23
3180x4720 US_ALU_RGB_ADDR_24
3190x4724 US_ALU_RGB_ADDR_25
3200x4728 US_ALU_RGB_ADDR_26
3210x472C US_ALU_RGB_ADDR_27
3220x4730 US_ALU_RGB_ADDR_28
3230x4734 US_ALU_RGB_ADDR_29
3240x4738 US_ALU_RGB_ADDR_30
3250x473C US_ALU_RGB_ADDR_31
3260x4740 US_ALU_RGB_ADDR_32
3270x4744 US_ALU_RGB_ADDR_33
3280x4748 US_ALU_RGB_ADDR_34
3290x474C US_ALU_RGB_ADDR_35
3300x4750 US_ALU_RGB_ADDR_36
3310x4754 US_ALU_RGB_ADDR_37
3320x4758 US_ALU_RGB_ADDR_38
3330x475C US_ALU_RGB_ADDR_39
3340x4760 US_ALU_RGB_ADDR_40
3350x4764 US_ALU_RGB_ADDR_41
3360x4768 US_ALU_RGB_ADDR_42
3370x476C US_ALU_RGB_ADDR_43
3380x4770 US_ALU_RGB_ADDR_44
3390x4774 US_ALU_RGB_ADDR_45
3400x4778 US_ALU_RGB_ADDR_46
3410x477C US_ALU_RGB_ADDR_47
3420x4780 US_ALU_RGB_ADDR_48
3430x4784 US_ALU_RGB_ADDR_49
3440x4788 US_ALU_RGB_ADDR_50
3450x478C US_ALU_RGB_ADDR_51
3460x4790 US_ALU_RGB_ADDR_52
3470x4794 US_ALU_RGB_ADDR_53
3480x4798 US_ALU_RGB_ADDR_54
3490x479C US_ALU_RGB_ADDR_55
3500x47A0 US_ALU_RGB_ADDR_56
3510x47A4 US_ALU_RGB_ADDR_57
3520x47A8 US_ALU_RGB_ADDR_58
3530x47AC US_ALU_RGB_ADDR_59
3540x47B0 US_ALU_RGB_ADDR_60
3550x47B4 US_ALU_RGB_ADDR_61
3560x47B8 US_ALU_RGB_ADDR_62
3570x47BC US_ALU_RGB_ADDR_63
3580x47C0 US_ALU_ALPHA_ADDR_0
3590x47C4 US_ALU_ALPHA_ADDR_1
3600x47C8 US_ALU_ALPHA_ADDR_2
3610x47CC US_ALU_ALPHA_ADDR_3
3620x47D0 US_ALU_ALPHA_ADDR_4
3630x47D4 US_ALU_ALPHA_ADDR_5
3640x47D8 US_ALU_ALPHA_ADDR_6
3650x47DC US_ALU_ALPHA_ADDR_7
3660x47E0 US_ALU_ALPHA_ADDR_8
3670x47E4 US_ALU_ALPHA_ADDR_9
3680x47E8 US_ALU_ALPHA_ADDR_10
3690x47EC US_ALU_ALPHA_ADDR_11
3700x47F0 US_ALU_ALPHA_ADDR_12
3710x47F4 US_ALU_ALPHA_ADDR_13
3720x47F8 US_ALU_ALPHA_ADDR_14
3730x47FC US_ALU_ALPHA_ADDR_15
3740x4800 US_ALU_ALPHA_ADDR_16
3750x4804 US_ALU_ALPHA_ADDR_17
3760x4808 US_ALU_ALPHA_ADDR_18
3770x480C US_ALU_ALPHA_ADDR_19
3780x4810 US_ALU_ALPHA_ADDR_20
3790x4814 US_ALU_ALPHA_ADDR_21
3800x4818 US_ALU_ALPHA_ADDR_22
3810x481C US_ALU_ALPHA_ADDR_23
3820x4820 US_ALU_ALPHA_ADDR_24
3830x4824 US_ALU_ALPHA_ADDR_25
3840x4828 US_ALU_ALPHA_ADDR_26
3850x482C US_ALU_ALPHA_ADDR_27
3860x4830 US_ALU_ALPHA_ADDR_28
3870x4834 US_ALU_ALPHA_ADDR_29
3880x4838 US_ALU_ALPHA_ADDR_30
3890x483C US_ALU_ALPHA_ADDR_31
3900x4840 US_ALU_ALPHA_ADDR_32
3910x4844 US_ALU_ALPHA_ADDR_33
3920x4848 US_ALU_ALPHA_ADDR_34
3930x484C US_ALU_ALPHA_ADDR_35
3940x4850 US_ALU_ALPHA_ADDR_36
3950x4854 US_ALU_ALPHA_ADDR_37
3960x4858 US_ALU_ALPHA_ADDR_38
3970x485C US_ALU_ALPHA_ADDR_39
3980x4860 US_ALU_ALPHA_ADDR_40
3990x4864 US_ALU_ALPHA_ADDR_41
4000x4868 US_ALU_ALPHA_ADDR_42
4010x486C US_ALU_ALPHA_ADDR_43
4020x4870 US_ALU_ALPHA_ADDR_44
4030x4874 US_ALU_ALPHA_ADDR_45
4040x4878 US_ALU_ALPHA_ADDR_46
4050x487C US_ALU_ALPHA_ADDR_47
4060x4880 US_ALU_ALPHA_ADDR_48
4070x4884 US_ALU_ALPHA_ADDR_49
4080x4888 US_ALU_ALPHA_ADDR_50
4090x488C US_ALU_ALPHA_ADDR_51
4100x4890 US_ALU_ALPHA_ADDR_52
4110x4894 US_ALU_ALPHA_ADDR_53
4120x4898 US_ALU_ALPHA_ADDR_54
4130x489C US_ALU_ALPHA_ADDR_55
4140x48A0 US_ALU_ALPHA_ADDR_56
4150x48A4 US_ALU_ALPHA_ADDR_57
4160x48A8 US_ALU_ALPHA_ADDR_58
4170x48AC US_ALU_ALPHA_ADDR_59
4180x48B0 US_ALU_ALPHA_ADDR_60
4190x48B4 US_ALU_ALPHA_ADDR_61
4200x48B8 US_ALU_ALPHA_ADDR_62
4210x48BC US_ALU_ALPHA_ADDR_63
4220x48C0 US_ALU_RGB_INST_0
4230x48C4 US_ALU_RGB_INST_1
4240x48C8 US_ALU_RGB_INST_2
4250x48CC US_ALU_RGB_INST_3
4260x48D0 US_ALU_RGB_INST_4
4270x48D4 US_ALU_RGB_INST_5
4280x48D8 US_ALU_RGB_INST_6
4290x48DC US_ALU_RGB_INST_7
4300x48E0 US_ALU_RGB_INST_8
4310x48E4 US_ALU_RGB_INST_9
4320x48E8 US_ALU_RGB_INST_10
4330x48EC US_ALU_RGB_INST_11
4340x48F0 US_ALU_RGB_INST_12
4350x48F4 US_ALU_RGB_INST_13
4360x48F8 US_ALU_RGB_INST_14
4370x48FC US_ALU_RGB_INST_15
4380x4900 US_ALU_RGB_INST_16
4390x4904 US_ALU_RGB_INST_17
4400x4908 US_ALU_RGB_INST_18
4410x490C US_ALU_RGB_INST_19
4420x4910 US_ALU_RGB_INST_20
4430x4914 US_ALU_RGB_INST_21
4440x4918 US_ALU_RGB_INST_22
4450x491C US_ALU_RGB_INST_23
4460x4920 US_ALU_RGB_INST_24
4470x4924 US_ALU_RGB_INST_25
4480x4928 US_ALU_RGB_INST_26
4490x492C US_ALU_RGB_INST_27
4500x4930 US_ALU_RGB_INST_28
4510x4934 US_ALU_RGB_INST_29
4520x4938 US_ALU_RGB_INST_30
4530x493C US_ALU_RGB_INST_31
4540x4940 US_ALU_RGB_INST_32
4550x4944 US_ALU_RGB_INST_33
4560x4948 US_ALU_RGB_INST_34
4570x494C US_ALU_RGB_INST_35
4580x4950 US_ALU_RGB_INST_36
4590x4954 US_ALU_RGB_INST_37
4600x4958 US_ALU_RGB_INST_38
4610x495C US_ALU_RGB_INST_39
4620x4960 US_ALU_RGB_INST_40
4630x4964 US_ALU_RGB_INST_41
4640x4968 US_ALU_RGB_INST_42
4650x496C US_ALU_RGB_INST_43
4660x4970 US_ALU_RGB_INST_44
4670x4974 US_ALU_RGB_INST_45
4680x4978 US_ALU_RGB_INST_46
4690x497C US_ALU_RGB_INST_47
4700x4980 US_ALU_RGB_INST_48
4710x4984 US_ALU_RGB_INST_49
4720x4988 US_ALU_RGB_INST_50
4730x498C US_ALU_RGB_INST_51
4740x4990 US_ALU_RGB_INST_52
4750x4994 US_ALU_RGB_INST_53
4760x4998 US_ALU_RGB_INST_54
4770x499C US_ALU_RGB_INST_55
4780x49A0 US_ALU_RGB_INST_56
4790x49A4 US_ALU_RGB_INST_57
4800x49A8 US_ALU_RGB_INST_58
4810x49AC US_ALU_RGB_INST_59
4820x49B0 US_ALU_RGB_INST_60
4830x49B4 US_ALU_RGB_INST_61
4840x49B8 US_ALU_RGB_INST_62
4850x49BC US_ALU_RGB_INST_63
4860x49C0 US_ALU_ALPHA_INST_0
4870x49C4 US_ALU_ALPHA_INST_1
4880x49C8 US_ALU_ALPHA_INST_2
4890x49CC US_ALU_ALPHA_INST_3
4900x49D0 US_ALU_ALPHA_INST_4
4910x49D4 US_ALU_ALPHA_INST_5
4920x49D8 US_ALU_ALPHA_INST_6
4930x49DC US_ALU_ALPHA_INST_7
4940x49E0 US_ALU_ALPHA_INST_8
4950x49E4 US_ALU_ALPHA_INST_9
4960x49E8 US_ALU_ALPHA_INST_10
4970x49EC US_ALU_ALPHA_INST_11
4980x49F0 US_ALU_ALPHA_INST_12
4990x49F4 US_ALU_ALPHA_INST_13
5000x49F8 US_ALU_ALPHA_INST_14
5010x49FC US_ALU_ALPHA_INST_15
5020x4A00 US_ALU_ALPHA_INST_16
5030x4A04 US_ALU_ALPHA_INST_17
5040x4A08 US_ALU_ALPHA_INST_18
5050x4A0C US_ALU_ALPHA_INST_19
5060x4A10 US_ALU_ALPHA_INST_20
5070x4A14 US_ALU_ALPHA_INST_21
5080x4A18 US_ALU_ALPHA_INST_22
5090x4A1C US_ALU_ALPHA_INST_23
5100x4A20 US_ALU_ALPHA_INST_24
5110x4A24 US_ALU_ALPHA_INST_25
5120x4A28 US_ALU_ALPHA_INST_26
5130x4A2C US_ALU_ALPHA_INST_27
5140x4A30 US_ALU_ALPHA_INST_28
5150x4A34 US_ALU_ALPHA_INST_29
5160x4A38 US_ALU_ALPHA_INST_30
5170x4A3C US_ALU_ALPHA_INST_31
5180x4A40 US_ALU_ALPHA_INST_32
5190x4A44 US_ALU_ALPHA_INST_33
5200x4A48 US_ALU_ALPHA_INST_34
5210x4A4C US_ALU_ALPHA_INST_35
5220x4A50 US_ALU_ALPHA_INST_36
5230x4A54 US_ALU_ALPHA_INST_37
5240x4A58 US_ALU_ALPHA_INST_38
5250x4A5C US_ALU_ALPHA_INST_39
5260x4A60 US_ALU_ALPHA_INST_40
5270x4A64 US_ALU_ALPHA_INST_41
5280x4A68 US_ALU_ALPHA_INST_42
5290x4A6C US_ALU_ALPHA_INST_43
5300x4A70 US_ALU_ALPHA_INST_44
5310x4A74 US_ALU_ALPHA_INST_45
5320x4A78 US_ALU_ALPHA_INST_46
5330x4A7C US_ALU_ALPHA_INST_47
5340x4A80 US_ALU_ALPHA_INST_48
5350x4A84 US_ALU_ALPHA_INST_49
5360x4A88 US_ALU_ALPHA_INST_50
5370x4A8C US_ALU_ALPHA_INST_51
5380x4A90 US_ALU_ALPHA_INST_52
5390x4A94 US_ALU_ALPHA_INST_53
5400x4A98 US_ALU_ALPHA_INST_54
5410x4A9C US_ALU_ALPHA_INST_55
5420x4AA0 US_ALU_ALPHA_INST_56
5430x4AA4 US_ALU_ALPHA_INST_57
5440x4AA8 US_ALU_ALPHA_INST_58
5450x4AAC US_ALU_ALPHA_INST_59
5460x4AB0 US_ALU_ALPHA_INST_60
5470x4AB4 US_ALU_ALPHA_INST_61
5480x4AB8 US_ALU_ALPHA_INST_62
5490x4ABC US_ALU_ALPHA_INST_63
5500x4BC0 FG_FOG_BLEND
5510x4BC4 FG_FOG_FACTOR
5520x4BC8 FG_FOG_COLOR_R
5530x4BCC FG_FOG_COLOR_G
5540x4BD0 FG_FOG_COLOR_B
5550x4BD4 FG_ALPHA_FUNC
5560x4BD8 FG_DEPTH_SRC
5570x4C00 US_ALU_CONST_R_0
5580x4C04 US_ALU_CONST_G_0
5590x4C08 US_ALU_CONST_B_0
5600x4C0C US_ALU_CONST_A_0
5610x4C10 US_ALU_CONST_R_1
5620x4C14 US_ALU_CONST_G_1
5630x4C18 US_ALU_CONST_B_1
5640x4C1C US_ALU_CONST_A_1
5650x4C20 US_ALU_CONST_R_2
5660x4C24 US_ALU_CONST_G_2
5670x4C28 US_ALU_CONST_B_2
5680x4C2C US_ALU_CONST_A_2
5690x4C30 US_ALU_CONST_R_3
5700x4C34 US_ALU_CONST_G_3
5710x4C38 US_ALU_CONST_B_3
5720x4C3C US_ALU_CONST_A_3
5730x4C40 US_ALU_CONST_R_4
5740x4C44 US_ALU_CONST_G_4
5750x4C48 US_ALU_CONST_B_4
5760x4C4C US_ALU_CONST_A_4
5770x4C50 US_ALU_CONST_R_5
5780x4C54 US_ALU_CONST_G_5
5790x4C58 US_ALU_CONST_B_5
5800x4C5C US_ALU_CONST_A_5
5810x4C60 US_ALU_CONST_R_6
5820x4C64 US_ALU_CONST_G_6
5830x4C68 US_ALU_CONST_B_6
5840x4C6C US_ALU_CONST_A_6
5850x4C70 US_ALU_CONST_R_7
5860x4C74 US_ALU_CONST_G_7
5870x4C78 US_ALU_CONST_B_7
5880x4C7C US_ALU_CONST_A_7
5890x4C80 US_ALU_CONST_R_8
5900x4C84 US_ALU_CONST_G_8
5910x4C88 US_ALU_CONST_B_8
5920x4C8C US_ALU_CONST_A_8
5930x4C90 US_ALU_CONST_R_9
5940x4C94 US_ALU_CONST_G_9
5950x4C98 US_ALU_CONST_B_9
5960x4C9C US_ALU_CONST_A_9
5970x4CA0 US_ALU_CONST_R_10
5980x4CA4 US_ALU_CONST_G_10
5990x4CA8 US_ALU_CONST_B_10
6000x4CAC US_ALU_CONST_A_10
6010x4CB0 US_ALU_CONST_R_11
6020x4CB4 US_ALU_CONST_G_11
6030x4CB8 US_ALU_CONST_B_11
6040x4CBC US_ALU_CONST_A_11
6050x4CC0 US_ALU_CONST_R_12
6060x4CC4 US_ALU_CONST_G_12
6070x4CC8 US_ALU_CONST_B_12
6080x4CCC US_ALU_CONST_A_12
6090x4CD0 US_ALU_CONST_R_13
6100x4CD4 US_ALU_CONST_G_13
6110x4CD8 US_ALU_CONST_B_13
6120x4CDC US_ALU_CONST_A_13
6130x4CE0 US_ALU_CONST_R_14
6140x4CE4 US_ALU_CONST_G_14
6150x4CE8 US_ALU_CONST_B_14
6160x4CEC US_ALU_CONST_A_14
6170x4CF0 US_ALU_CONST_R_15
6180x4CF4 US_ALU_CONST_G_15
6190x4CF8 US_ALU_CONST_B_15
6200x4CFC US_ALU_CONST_A_15
6210x4D00 US_ALU_CONST_R_16
6220x4D04 US_ALU_CONST_G_16
6230x4D08 US_ALU_CONST_B_16
6240x4D0C US_ALU_CONST_A_16
6250x4D10 US_ALU_CONST_R_17
6260x4D14 US_ALU_CONST_G_17
6270x4D18 US_ALU_CONST_B_17
6280x4D1C US_ALU_CONST_A_17
6290x4D20 US_ALU_CONST_R_18
6300x4D24 US_ALU_CONST_G_18
6310x4D28 US_ALU_CONST_B_18
6320x4D2C US_ALU_CONST_A_18
6330x4D30 US_ALU_CONST_R_19
6340x4D34 US_ALU_CONST_G_19
6350x4D38 US_ALU_CONST_B_19
6360x4D3C US_ALU_CONST_A_19
6370x4D40 US_ALU_CONST_R_20
6380x4D44 US_ALU_CONST_G_20
6390x4D48 US_ALU_CONST_B_20
6400x4D4C US_ALU_CONST_A_20
6410x4D50 US_ALU_CONST_R_21
6420x4D54 US_ALU_CONST_G_21
6430x4D58 US_ALU_CONST_B_21
6440x4D5C US_ALU_CONST_A_21
6450x4D60 US_ALU_CONST_R_22
6460x4D64 US_ALU_CONST_G_22
6470x4D68 US_ALU_CONST_B_22
6480x4D6C US_ALU_CONST_A_22
6490x4D70 US_ALU_CONST_R_23
6500x4D74 US_ALU_CONST_G_23
6510x4D78 US_ALU_CONST_B_23
6520x4D7C US_ALU_CONST_A_23
6530x4D80 US_ALU_CONST_R_24
6540x4D84 US_ALU_CONST_G_24
6550x4D88 US_ALU_CONST_B_24
6560x4D8C US_ALU_CONST_A_24
6570x4D90 US_ALU_CONST_R_25
6580x4D94 US_ALU_CONST_G_25
6590x4D98 US_ALU_CONST_B_25
6600x4D9C US_ALU_CONST_A_25
6610x4DA0 US_ALU_CONST_R_26
6620x4DA4 US_ALU_CONST_G_26
6630x4DA8 US_ALU_CONST_B_26
6640x4DAC US_ALU_CONST_A_26
6650x4DB0 US_ALU_CONST_R_27
6660x4DB4 US_ALU_CONST_G_27
6670x4DB8 US_ALU_CONST_B_27
6680x4DBC US_ALU_CONST_A_27
6690x4DC0 US_ALU_CONST_R_28
6700x4DC4 US_ALU_CONST_G_28
6710x4DC8 US_ALU_CONST_B_28
6720x4DCC US_ALU_CONST_A_28
6730x4DD0 US_ALU_CONST_R_29
6740x4DD4 US_ALU_CONST_G_29
6750x4DD8 US_ALU_CONST_B_29
6760x4DDC US_ALU_CONST_A_29
6770x4DE0 US_ALU_CONST_R_30
6780x4DE4 US_ALU_CONST_G_30
6790x4DE8 US_ALU_CONST_B_30
6800x4DEC US_ALU_CONST_A_30
6810x4DF0 US_ALU_CONST_R_31
6820x4DF4 US_ALU_CONST_G_31
6830x4DF8 US_ALU_CONST_B_31
6840x4DFC US_ALU_CONST_A_31
6850x4E04 RB3D_BLENDCNTL_R3
6860x4E08 RB3D_ABLENDCNTL_R3
6870x4E0C RB3D_COLOR_CHANNEL_MASK
6880x4E10 RB3D_CONSTANT_COLOR
6890x4E14 RB3D_COLOR_CLEAR_VALUE
6900x4E18 RB3D_ROPCNTL_R3
6910x4E1C RB3D_CLRCMP_FLIPE_R3
6920x4E20 RB3D_CLRCMP_CLR_R3
6930x4E24 RB3D_CLRCMP_MSK_R3
6940x4E48 RB3D_DEBUG_CTL
6950x4E4C RB3D_DSTCACHE_CTLSTAT_R3
6960x4E50 RB3D_DITHER_CTL
6970x4E54 RB3D_CMASK_OFFSET0
6980x4E58 RB3D_CMASK_OFFSET1
6990x4E5C RB3D_CMASK_OFFSET2
7000x4E60 RB3D_CMASK_OFFSET3
7010x4E64 RB3D_CMASK_PITCH0
7020x4E68 RB3D_CMASK_PITCH1
7030x4E6C RB3D_CMASK_PITCH2
7040x4E70 RB3D_CMASK_PITCH3
7050x4E74 RB3D_CMASK_WRINDEX
7060x4E78 RB3D_CMASK_DWORD
7070x4E7C RB3D_CMASK_RDINDEX
7080x4E80 RB3D_AARESOLVE_OFFSET
7090x4E84 RB3D_AARESOLVE_PITCH
7100x4E88 RB3D_AARESOLVE_CTL
7110x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
7120x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
7130x4F04 ZB_ZSTENCILCNTL
7140x4F08 ZB_STENCILREFMASK
7150x4F14 ZB_ZTOP
7160x4F18 ZB_ZCACHE_CTLSTAT
7170x4F1C ZB_BW_CNTL
7180x4F28 ZB_DEPTHCLEARVALUE
7190x4F30 ZB_ZMASK_OFFSET
7200x4F34 ZB_ZMASK_PITCH
7210x4F38 ZB_ZMASK_WRINDEX
7220x4F3C ZB_ZMASK_DWORD
7230x4F40 ZB_ZMASK_RDINDEX
7240x4F44 ZB_HIZ_OFFSET
7250x4F48 ZB_HIZ_WRINDEX
7260x4F4C ZB_HIZ_DWORD
7270x4F50 ZB_HIZ_RDINDEX
7280x4F54 ZB_HIZ_PITCH
7290x4F58 ZB_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rn50 b/drivers/gpu/drm/radeon/reg_srcs/rn50
new file mode 100644
index 000000000000..2687b6307260
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/rn50
@@ -0,0 +1,30 @@
1rn50 0x3294
20x1434 SRC_Y_X
30x1438 DST_Y_X
40x143C DST_HEIGHT_WIDTH
50x146C DP_GUI_MASTER_CNTL
60x1474 BRUSH_Y_X
70x1478 DP_BRUSH_BKGD_CLR
80x147C DP_BRUSH_FRGD_CLR
90x1480 BRUSH_DATA0
100x1484 BRUSH_DATA1
110x1598 DST_WIDTH_HEIGHT
120x15C0 CLR_CMP_CNTL
130x15C4 CLR_CMP_CLR_SRC
140x15C8 CLR_CMP_CLR_DST
150x15CC CLR_CMP_MSK
160x15D8 DP_SRC_FRGD_CLR
170x15DC DP_SRC_BKGD_CLR
180x1600 DST_LINE_START
190x1604 DST_LINE_END
200x1608 DST_LINE_PATCOUNT
210x16C0 DP_CNTL
220x16CC DP_WRITE_MSK
230x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
240x16E8 DEFAULT_SC_BOTTOM_RIGHT
250x16EC SC_TOP_LEFT
260x16F0 SC_BOTTOM_RIGHT
270x16F4 SRC_SC_BOTTOM_RIGHT
280x1714 DSTCACHE_CTLSTAT
290x1720 WAIT_UNTIL
300x172C RBBM_GUICNTL
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600
new file mode 100644
index 000000000000..8e3c0b807add
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/rs600
@@ -0,0 +1,729 @@
1rs600 0x6d40
20x1434 SRC_Y_X
30x1438 DST_Y_X
40x143C DST_HEIGHT_WIDTH
50x146C DP_GUI_MASTER_CNTL
60x1474 BRUSH_Y_X
70x1478 DP_BRUSH_BKGD_CLR
80x147C DP_BRUSH_FRGD_CLR
90x1480 BRUSH_DATA0
100x1484 BRUSH_DATA1
110x1598 DST_WIDTH_HEIGHT
120x15C0 CLR_CMP_CNTL
130x15C4 CLR_CMP_CLR_SRC
140x15C8 CLR_CMP_CLR_DST
150x15CC CLR_CMP_MSK
160x15D8 DP_SRC_FRGD_CLR
170x15DC DP_SRC_BKGD_CLR
180x1600 DST_LINE_START
190x1604 DST_LINE_END
200x1608 DST_LINE_PATCOUNT
210x16C0 DP_CNTL
220x16CC DP_WRITE_MSK
230x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
240x16E8 DEFAULT_SC_BOTTOM_RIGHT
250x16EC SC_TOP_LEFT
260x16F0 SC_BOTTOM_RIGHT
270x16F4 SRC_SC_BOTTOM_RIGHT
280x1714 DSTCACHE_CTLSTAT
290x1720 WAIT_UNTIL
300x172C RBBM_GUICNTL
310x1D98 VAP_VPORT_XSCALE
320x1D9C VAP_VPORT_XOFFSET
330x1DA0 VAP_VPORT_YSCALE
340x1DA4 VAP_VPORT_YOFFSET
350x1DA8 VAP_VPORT_ZSCALE
360x1DAC VAP_VPORT_ZOFFSET
370x2080 VAP_CNTL
380x2090 VAP_OUT_VTX_FMT_0
390x2094 VAP_OUT_VTX_FMT_1
400x20B0 VAP_VTE_CNTL
410x2138 VAP_VF_MIN_VTX_INDX
420x2140 VAP_CNTL_STATUS
430x2150 VAP_PROG_STREAM_CNTL_0
440x2154 VAP_PROG_STREAM_CNTL_1
450x2158 VAP_PROG_STREAM_CNTL_2
460x215C VAP_PROG_STREAM_CNTL_3
470x2160 VAP_PROG_STREAM_CNTL_4
480x2164 VAP_PROG_STREAM_CNTL_5
490x2168 VAP_PROG_STREAM_CNTL_6
500x216C VAP_PROG_STREAM_CNTL_7
510x2180 VAP_VTX_STATE_CNTL
520x2184 VAP_VSM_VTX_ASSM
530x2188 VAP_VTX_STATE_IND_REG_0
540x218C VAP_VTX_STATE_IND_REG_1
550x2190 VAP_VTX_STATE_IND_REG_2
560x2194 VAP_VTX_STATE_IND_REG_3
570x2198 VAP_VTX_STATE_IND_REG_4
580x219C VAP_VTX_STATE_IND_REG_5
590x21A0 VAP_VTX_STATE_IND_REG_6
600x21A4 VAP_VTX_STATE_IND_REG_7
610x21A8 VAP_VTX_STATE_IND_REG_8
620x21AC VAP_VTX_STATE_IND_REG_9
630x21B0 VAP_VTX_STATE_IND_REG_10
640x21B4 VAP_VTX_STATE_IND_REG_11
650x21B8 VAP_VTX_STATE_IND_REG_12
660x21BC VAP_VTX_STATE_IND_REG_13
670x21C0 VAP_VTX_STATE_IND_REG_14
680x21C4 VAP_VTX_STATE_IND_REG_15
690x21DC VAP_PSC_SGN_NORM_CNTL
700x21E0 VAP_PROG_STREAM_CNTL_EXT_0
710x21E4 VAP_PROG_STREAM_CNTL_EXT_1
720x21E8 VAP_PROG_STREAM_CNTL_EXT_2
730x21EC VAP_PROG_STREAM_CNTL_EXT_3
740x21F0 VAP_PROG_STREAM_CNTL_EXT_4
750x21F4 VAP_PROG_STREAM_CNTL_EXT_5
760x21F8 VAP_PROG_STREAM_CNTL_EXT_6
770x21FC VAP_PROG_STREAM_CNTL_EXT_7
780x2200 VAP_PVS_VECTOR_INDX_REG
790x2204 VAP_PVS_VECTOR_DATA_REG
800x2208 VAP_PVS_VECTOR_DATA_REG_128
810x221C VAP_CLIP_CNTL
820x2220 VAP_GB_VERT_CLIP_ADJ
830x2224 VAP_GB_VERT_DISC_ADJ
840x2228 VAP_GB_HORZ_CLIP_ADJ
850x222C VAP_GB_HORZ_DISC_ADJ
860x2230 VAP_PVS_FLOW_CNTL_ADDRS_0
870x2234 VAP_PVS_FLOW_CNTL_ADDRS_1
880x2238 VAP_PVS_FLOW_CNTL_ADDRS_2
890x223C VAP_PVS_FLOW_CNTL_ADDRS_3
900x2240 VAP_PVS_FLOW_CNTL_ADDRS_4
910x2244 VAP_PVS_FLOW_CNTL_ADDRS_5
920x2248 VAP_PVS_FLOW_CNTL_ADDRS_6
930x224C VAP_PVS_FLOW_CNTL_ADDRS_7
940x2250 VAP_PVS_FLOW_CNTL_ADDRS_8
950x2254 VAP_PVS_FLOW_CNTL_ADDRS_9
960x2258 VAP_PVS_FLOW_CNTL_ADDRS_10
970x225C VAP_PVS_FLOW_CNTL_ADDRS_11
980x2260 VAP_PVS_FLOW_CNTL_ADDRS_12
990x2264 VAP_PVS_FLOW_CNTL_ADDRS_13
1000x2268 VAP_PVS_FLOW_CNTL_ADDRS_14
1010x226C VAP_PVS_FLOW_CNTL_ADDRS_15
1020x2284 VAP_PVS_STATE_FLUSH_REG
1030x2288 VAP_PVS_VTX_TIMEOUT_REG
1040x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
1050x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1
1060x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2
1070x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3
1080x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4
1090x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5
1100x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6
1110x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7
1120x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8
1130x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9
1140x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10
1150x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11
1160x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12
1170x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13
1180x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14
1190x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15
1200x22D0 VAP_PVS_CODE_CNTL_0
1210x22D4 VAP_PVS_CONST_CNTL
1220x22D8 VAP_PVS_CODE_CNTL_1
1230x22DC VAP_PVS_FLOW_CNTL_OPC
1240x342C RB2D_DSTCACHE_CTLSTAT
1250x4000 GB_VAP_RASTER_VTX_FMT_0
1260x4004 GB_VAP_RASTER_VTX_FMT_1
1270x4008 GB_ENABLE
1280x401C GB_SELECT
1290x4020 GB_AA_CONFIG
1300x4024 GB_FIFO_SIZE
1310x4100 TX_INVALTAGS
1320x4200 GA_POINT_S0
1330x4204 GA_POINT_T0
1340x4208 GA_POINT_S1
1350x420C GA_POINT_T1
1360x4214 GA_TRIANGLE_STIPPLE
1370x421C GA_POINT_SIZE
1380x4230 GA_POINT_MINMAX
1390x4234 GA_LINE_CNTL
1400x4238 GA_LINE_STIPPLE_CONFIG
1410x4260 GA_LINE_STIPPLE_VALUE
1420x4264 GA_LINE_S0
1430x4268 GA_LINE_S1
1440x4278 GA_COLOR_CONTROL
1450x427C GA_SOLID_RG
1460x4280 GA_SOLID_BA
1470x4288 GA_POLY_MODE
1480x428C GA_ROUND_MODE
1490x4290 GA_OFFSET
1500x4294 GA_FOG_SCALE
1510x4298 GA_FOG_OFFSET
1520x42A0 SU_TEX_WRAP
1530x42A4 SU_POLY_OFFSET_FRONT_SCALE
1540x42A8 SU_POLY_OFFSET_FRONT_OFFSET
1550x42AC SU_POLY_OFFSET_BACK_SCALE
1560x42B0 SU_POLY_OFFSET_BACK_OFFSET
1570x42B4 SU_POLY_OFFSET_ENABLE
1580x42B8 SU_CULL_MODE
1590x42C0 SU_DEPTH_SCALE
1600x42C4 SU_DEPTH_OFFSET
1610x42C8 SU_REG_DEST
1620x4300 RS_COUNT
1630x4304 RS_INST_COUNT
1640x4310 RS_IP_0
1650x4314 RS_IP_1
1660x4318 RS_IP_2
1670x431C RS_IP_3
1680x4320 RS_IP_4
1690x4324 RS_IP_5
1700x4328 RS_IP_6
1710x432C RS_IP_7
1720x4330 RS_INST_0
1730x4334 RS_INST_1
1740x4338 RS_INST_2
1750x433C RS_INST_3
1760x4340 RS_INST_4
1770x4344 RS_INST_5
1780x4348 RS_INST_6
1790x434C RS_INST_7
1800x4350 RS_INST_8
1810x4354 RS_INST_9
1820x4358 RS_INST_10
1830x435C RS_INST_11
1840x4360 RS_INST_12
1850x4364 RS_INST_13
1860x4368 RS_INST_14
1870x436C RS_INST_15
1880x43A4 SC_HYPERZ_EN
1890x43A8 SC_EDGERULE
1900x43B0 SC_CLIP_0_A
1910x43B4 SC_CLIP_0_B
1920x43B8 SC_CLIP_1_A
1930x43BC SC_CLIP_1_B
1940x43C0 SC_CLIP_2_A
1950x43C4 SC_CLIP_2_B
1960x43C8 SC_CLIP_3_A
1970x43CC SC_CLIP_3_B
1980x43D0 SC_CLIP_RULE
1990x43E0 SC_SCISSOR0
2000x43E8 SC_SCREENDOOR
2010x4440 TX_FILTER1_0
2020x4444 TX_FILTER1_1
2030x4448 TX_FILTER1_2
2040x444C TX_FILTER1_3
2050x4450 TX_FILTER1_4
2060x4454 TX_FILTER1_5
2070x4458 TX_FILTER1_6
2080x445C TX_FILTER1_7
2090x4460 TX_FILTER1_8
2100x4464 TX_FILTER1_9
2110x4468 TX_FILTER1_10
2120x446C TX_FILTER1_11
2130x4470 TX_FILTER1_12
2140x4474 TX_FILTER1_13
2150x4478 TX_FILTER1_14
2160x447C TX_FILTER1_15
2170x4580 TX_CHROMA_KEY_0
2180x4584 TX_CHROMA_KEY_1
2190x4588 TX_CHROMA_KEY_2
2200x458C TX_CHROMA_KEY_3
2210x4590 TX_CHROMA_KEY_4
2220x4594 TX_CHROMA_KEY_5
2230x4598 TX_CHROMA_KEY_6
2240x459C TX_CHROMA_KEY_7
2250x45A0 TX_CHROMA_KEY_8
2260x45A4 TX_CHROMA_KEY_9
2270x45A8 TX_CHROMA_KEY_10
2280x45AC TX_CHROMA_KEY_11
2290x45B0 TX_CHROMA_KEY_12
2300x45B4 TX_CHROMA_KEY_13
2310x45B8 TX_CHROMA_KEY_14
2320x45BC TX_CHROMA_KEY_15
2330x45C0 TX_BORDER_COLOR_0
2340x45C4 TX_BORDER_COLOR_1
2350x45C8 TX_BORDER_COLOR_2
2360x45CC TX_BORDER_COLOR_3
2370x45D0 TX_BORDER_COLOR_4
2380x45D4 TX_BORDER_COLOR_5
2390x45D8 TX_BORDER_COLOR_6
2400x45DC TX_BORDER_COLOR_7
2410x45E0 TX_BORDER_COLOR_8
2420x45E4 TX_BORDER_COLOR_9
2430x45E8 TX_BORDER_COLOR_10
2440x45EC TX_BORDER_COLOR_11
2450x45F0 TX_BORDER_COLOR_12
2460x45F4 TX_BORDER_COLOR_13
2470x45F8 TX_BORDER_COLOR_14
2480x45FC TX_BORDER_COLOR_15
2490x4600 US_CONFIG
2500x4604 US_PIXSIZE
2510x4608 US_CODE_OFFSET
2520x460C US_RESET
2530x4610 US_CODE_ADDR_0
2540x4614 US_CODE_ADDR_1
2550x4618 US_CODE_ADDR_2
2560x461C US_CODE_ADDR_3
2570x4620 US_TEX_INST_0
2580x4624 US_TEX_INST_1
2590x4628 US_TEX_INST_2
2600x462C US_TEX_INST_3
2610x4630 US_TEX_INST_4
2620x4634 US_TEX_INST_5
2630x4638 US_TEX_INST_6
2640x463C US_TEX_INST_7
2650x4640 US_TEX_INST_8
2660x4644 US_TEX_INST_9
2670x4648 US_TEX_INST_10
2680x464C US_TEX_INST_11
2690x4650 US_TEX_INST_12
2700x4654 US_TEX_INST_13
2710x4658 US_TEX_INST_14
2720x465C US_TEX_INST_15
2730x4660 US_TEX_INST_16
2740x4664 US_TEX_INST_17
2750x4668 US_TEX_INST_18
2760x466C US_TEX_INST_19
2770x4670 US_TEX_INST_20
2780x4674 US_TEX_INST_21
2790x4678 US_TEX_INST_22
2800x467C US_TEX_INST_23
2810x4680 US_TEX_INST_24
2820x4684 US_TEX_INST_25
2830x4688 US_TEX_INST_26
2840x468C US_TEX_INST_27
2850x4690 US_TEX_INST_28
2860x4694 US_TEX_INST_29
2870x4698 US_TEX_INST_30
2880x469C US_TEX_INST_31
2890x46A4 US_OUT_FMT_0
2900x46A8 US_OUT_FMT_1
2910x46AC US_OUT_FMT_2
2920x46B0 US_OUT_FMT_3
2930x46B4 US_W_FMT
2940x46C0 US_ALU_RGB_ADDR_0
2950x46C4 US_ALU_RGB_ADDR_1
2960x46C8 US_ALU_RGB_ADDR_2
2970x46CC US_ALU_RGB_ADDR_3
2980x46D0 US_ALU_RGB_ADDR_4
2990x46D4 US_ALU_RGB_ADDR_5
3000x46D8 US_ALU_RGB_ADDR_6
3010x46DC US_ALU_RGB_ADDR_7
3020x46E0 US_ALU_RGB_ADDR_8
3030x46E4 US_ALU_RGB_ADDR_9
3040x46E8 US_ALU_RGB_ADDR_10
3050x46EC US_ALU_RGB_ADDR_11
3060x46F0 US_ALU_RGB_ADDR_12
3070x46F4 US_ALU_RGB_ADDR_13
3080x46F8 US_ALU_RGB_ADDR_14
3090x46FC US_ALU_RGB_ADDR_15
3100x4700 US_ALU_RGB_ADDR_16
3110x4704 US_ALU_RGB_ADDR_17
3120x4708 US_ALU_RGB_ADDR_18
3130x470C US_ALU_RGB_ADDR_19
3140x4710 US_ALU_RGB_ADDR_20
3150x4714 US_ALU_RGB_ADDR_21
3160x4718 US_ALU_RGB_ADDR_22
3170x471C US_ALU_RGB_ADDR_23
3180x4720 US_ALU_RGB_ADDR_24
3190x4724 US_ALU_RGB_ADDR_25
3200x4728 US_ALU_RGB_ADDR_26
3210x472C US_ALU_RGB_ADDR_27
3220x4730 US_ALU_RGB_ADDR_28
3230x4734 US_ALU_RGB_ADDR_29
3240x4738 US_ALU_RGB_ADDR_30
3250x473C US_ALU_RGB_ADDR_31
3260x4740 US_ALU_RGB_ADDR_32
3270x4744 US_ALU_RGB_ADDR_33
3280x4748 US_ALU_RGB_ADDR_34
3290x474C US_ALU_RGB_ADDR_35
3300x4750 US_ALU_RGB_ADDR_36
3310x4754 US_ALU_RGB_ADDR_37
3320x4758 US_ALU_RGB_ADDR_38
3330x475C US_ALU_RGB_ADDR_39
3340x4760 US_ALU_RGB_ADDR_40
3350x4764 US_ALU_RGB_ADDR_41
3360x4768 US_ALU_RGB_ADDR_42
3370x476C US_ALU_RGB_ADDR_43
3380x4770 US_ALU_RGB_ADDR_44
3390x4774 US_ALU_RGB_ADDR_45
3400x4778 US_ALU_RGB_ADDR_46
3410x477C US_ALU_RGB_ADDR_47
3420x4780 US_ALU_RGB_ADDR_48
3430x4784 US_ALU_RGB_ADDR_49
3440x4788 US_ALU_RGB_ADDR_50
3450x478C US_ALU_RGB_ADDR_51
3460x4790 US_ALU_RGB_ADDR_52
3470x4794 US_ALU_RGB_ADDR_53
3480x4798 US_ALU_RGB_ADDR_54
3490x479C US_ALU_RGB_ADDR_55
3500x47A0 US_ALU_RGB_ADDR_56
3510x47A4 US_ALU_RGB_ADDR_57
3520x47A8 US_ALU_RGB_ADDR_58
3530x47AC US_ALU_RGB_ADDR_59
3540x47B0 US_ALU_RGB_ADDR_60
3550x47B4 US_ALU_RGB_ADDR_61
3560x47B8 US_ALU_RGB_ADDR_62
3570x47BC US_ALU_RGB_ADDR_63
3580x47C0 US_ALU_ALPHA_ADDR_0
3590x47C4 US_ALU_ALPHA_ADDR_1
3600x47C8 US_ALU_ALPHA_ADDR_2
3610x47CC US_ALU_ALPHA_ADDR_3
3620x47D0 US_ALU_ALPHA_ADDR_4
3630x47D4 US_ALU_ALPHA_ADDR_5
3640x47D8 US_ALU_ALPHA_ADDR_6
3650x47DC US_ALU_ALPHA_ADDR_7
3660x47E0 US_ALU_ALPHA_ADDR_8
3670x47E4 US_ALU_ALPHA_ADDR_9
3680x47E8 US_ALU_ALPHA_ADDR_10
3690x47EC US_ALU_ALPHA_ADDR_11
3700x47F0 US_ALU_ALPHA_ADDR_12
3710x47F4 US_ALU_ALPHA_ADDR_13
3720x47F8 US_ALU_ALPHA_ADDR_14
3730x47FC US_ALU_ALPHA_ADDR_15
3740x4800 US_ALU_ALPHA_ADDR_16
3750x4804 US_ALU_ALPHA_ADDR_17
3760x4808 US_ALU_ALPHA_ADDR_18
3770x480C US_ALU_ALPHA_ADDR_19
3780x4810 US_ALU_ALPHA_ADDR_20
3790x4814 US_ALU_ALPHA_ADDR_21
3800x4818 US_ALU_ALPHA_ADDR_22
3810x481C US_ALU_ALPHA_ADDR_23
3820x4820 US_ALU_ALPHA_ADDR_24
3830x4824 US_ALU_ALPHA_ADDR_25
3840x4828 US_ALU_ALPHA_ADDR_26
3850x482C US_ALU_ALPHA_ADDR_27
3860x4830 US_ALU_ALPHA_ADDR_28
3870x4834 US_ALU_ALPHA_ADDR_29
3880x4838 US_ALU_ALPHA_ADDR_30
3890x483C US_ALU_ALPHA_ADDR_31
3900x4840 US_ALU_ALPHA_ADDR_32
3910x4844 US_ALU_ALPHA_ADDR_33
3920x4848 US_ALU_ALPHA_ADDR_34
3930x484C US_ALU_ALPHA_ADDR_35
3940x4850 US_ALU_ALPHA_ADDR_36
3950x4854 US_ALU_ALPHA_ADDR_37
3960x4858 US_ALU_ALPHA_ADDR_38
3970x485C US_ALU_ALPHA_ADDR_39
3980x4860 US_ALU_ALPHA_ADDR_40
3990x4864 US_ALU_ALPHA_ADDR_41
4000x4868 US_ALU_ALPHA_ADDR_42
4010x486C US_ALU_ALPHA_ADDR_43
4020x4870 US_ALU_ALPHA_ADDR_44
4030x4874 US_ALU_ALPHA_ADDR_45
4040x4878 US_ALU_ALPHA_ADDR_46
4050x487C US_ALU_ALPHA_ADDR_47
4060x4880 US_ALU_ALPHA_ADDR_48
4070x4884 US_ALU_ALPHA_ADDR_49
4080x4888 US_ALU_ALPHA_ADDR_50
4090x488C US_ALU_ALPHA_ADDR_51
4100x4890 US_ALU_ALPHA_ADDR_52
4110x4894 US_ALU_ALPHA_ADDR_53
4120x4898 US_ALU_ALPHA_ADDR_54
4130x489C US_ALU_ALPHA_ADDR_55
4140x48A0 US_ALU_ALPHA_ADDR_56
4150x48A4 US_ALU_ALPHA_ADDR_57
4160x48A8 US_ALU_ALPHA_ADDR_58
4170x48AC US_ALU_ALPHA_ADDR_59
4180x48B0 US_ALU_ALPHA_ADDR_60
4190x48B4 US_ALU_ALPHA_ADDR_61
4200x48B8 US_ALU_ALPHA_ADDR_62
4210x48BC US_ALU_ALPHA_ADDR_63
4220x48C0 US_ALU_RGB_INST_0
4230x48C4 US_ALU_RGB_INST_1
4240x48C8 US_ALU_RGB_INST_2
4250x48CC US_ALU_RGB_INST_3
4260x48D0 US_ALU_RGB_INST_4
4270x48D4 US_ALU_RGB_INST_5
4280x48D8 US_ALU_RGB_INST_6
4290x48DC US_ALU_RGB_INST_7
4300x48E0 US_ALU_RGB_INST_8
4310x48E4 US_ALU_RGB_INST_9
4320x48E8 US_ALU_RGB_INST_10
4330x48EC US_ALU_RGB_INST_11
4340x48F0 US_ALU_RGB_INST_12
4350x48F4 US_ALU_RGB_INST_13
4360x48F8 US_ALU_RGB_INST_14
4370x48FC US_ALU_RGB_INST_15
4380x4900 US_ALU_RGB_INST_16
4390x4904 US_ALU_RGB_INST_17
4400x4908 US_ALU_RGB_INST_18
4410x490C US_ALU_RGB_INST_19
4420x4910 US_ALU_RGB_INST_20
4430x4914 US_ALU_RGB_INST_21
4440x4918 US_ALU_RGB_INST_22
4450x491C US_ALU_RGB_INST_23
4460x4920 US_ALU_RGB_INST_24
4470x4924 US_ALU_RGB_INST_25
4480x4928 US_ALU_RGB_INST_26
4490x492C US_ALU_RGB_INST_27
4500x4930 US_ALU_RGB_INST_28
4510x4934 US_ALU_RGB_INST_29
4520x4938 US_ALU_RGB_INST_30
4530x493C US_ALU_RGB_INST_31
4540x4940 US_ALU_RGB_INST_32
4550x4944 US_ALU_RGB_INST_33
4560x4948 US_ALU_RGB_INST_34
4570x494C US_ALU_RGB_INST_35
4580x4950 US_ALU_RGB_INST_36
4590x4954 US_ALU_RGB_INST_37
4600x4958 US_ALU_RGB_INST_38
4610x495C US_ALU_RGB_INST_39
4620x4960 US_ALU_RGB_INST_40
4630x4964 US_ALU_RGB_INST_41
4640x4968 US_ALU_RGB_INST_42
4650x496C US_ALU_RGB_INST_43
4660x4970 US_ALU_RGB_INST_44
4670x4974 US_ALU_RGB_INST_45
4680x4978 US_ALU_RGB_INST_46
4690x497C US_ALU_RGB_INST_47
4700x4980 US_ALU_RGB_INST_48
4710x4984 US_ALU_RGB_INST_49
4720x4988 US_ALU_RGB_INST_50
4730x498C US_ALU_RGB_INST_51
4740x4990 US_ALU_RGB_INST_52
4750x4994 US_ALU_RGB_INST_53
4760x4998 US_ALU_RGB_INST_54
4770x499C US_ALU_RGB_INST_55
4780x49A0 US_ALU_RGB_INST_56
4790x49A4 US_ALU_RGB_INST_57
4800x49A8 US_ALU_RGB_INST_58
4810x49AC US_ALU_RGB_INST_59
4820x49B0 US_ALU_RGB_INST_60
4830x49B4 US_ALU_RGB_INST_61
4840x49B8 US_ALU_RGB_INST_62
4850x49BC US_ALU_RGB_INST_63
4860x49C0 US_ALU_ALPHA_INST_0
4870x49C4 US_ALU_ALPHA_INST_1
4880x49C8 US_ALU_ALPHA_INST_2
4890x49CC US_ALU_ALPHA_INST_3
4900x49D0 US_ALU_ALPHA_INST_4
4910x49D4 US_ALU_ALPHA_INST_5
4920x49D8 US_ALU_ALPHA_INST_6
4930x49DC US_ALU_ALPHA_INST_7
4940x49E0 US_ALU_ALPHA_INST_8
4950x49E4 US_ALU_ALPHA_INST_9
4960x49E8 US_ALU_ALPHA_INST_10
4970x49EC US_ALU_ALPHA_INST_11
4980x49F0 US_ALU_ALPHA_INST_12
4990x49F4 US_ALU_ALPHA_INST_13
5000x49F8 US_ALU_ALPHA_INST_14
5010x49FC US_ALU_ALPHA_INST_15
5020x4A00 US_ALU_ALPHA_INST_16
5030x4A04 US_ALU_ALPHA_INST_17
5040x4A08 US_ALU_ALPHA_INST_18
5050x4A0C US_ALU_ALPHA_INST_19
5060x4A10 US_ALU_ALPHA_INST_20
5070x4A14 US_ALU_ALPHA_INST_21
5080x4A18 US_ALU_ALPHA_INST_22
5090x4A1C US_ALU_ALPHA_INST_23
5100x4A20 US_ALU_ALPHA_INST_24
5110x4A24 US_ALU_ALPHA_INST_25
5120x4A28 US_ALU_ALPHA_INST_26
5130x4A2C US_ALU_ALPHA_INST_27
5140x4A30 US_ALU_ALPHA_INST_28
5150x4A34 US_ALU_ALPHA_INST_29
5160x4A38 US_ALU_ALPHA_INST_30
5170x4A3C US_ALU_ALPHA_INST_31
5180x4A40 US_ALU_ALPHA_INST_32
5190x4A44 US_ALU_ALPHA_INST_33
5200x4A48 US_ALU_ALPHA_INST_34
5210x4A4C US_ALU_ALPHA_INST_35
5220x4A50 US_ALU_ALPHA_INST_36
5230x4A54 US_ALU_ALPHA_INST_37
5240x4A58 US_ALU_ALPHA_INST_38
5250x4A5C US_ALU_ALPHA_INST_39
5260x4A60 US_ALU_ALPHA_INST_40
5270x4A64 US_ALU_ALPHA_INST_41
5280x4A68 US_ALU_ALPHA_INST_42
5290x4A6C US_ALU_ALPHA_INST_43
5300x4A70 US_ALU_ALPHA_INST_44
5310x4A74 US_ALU_ALPHA_INST_45
5320x4A78 US_ALU_ALPHA_INST_46
5330x4A7C US_ALU_ALPHA_INST_47
5340x4A80 US_ALU_ALPHA_INST_48
5350x4A84 US_ALU_ALPHA_INST_49
5360x4A88 US_ALU_ALPHA_INST_50
5370x4A8C US_ALU_ALPHA_INST_51
5380x4A90 US_ALU_ALPHA_INST_52
5390x4A94 US_ALU_ALPHA_INST_53
5400x4A98 US_ALU_ALPHA_INST_54
5410x4A9C US_ALU_ALPHA_INST_55
5420x4AA0 US_ALU_ALPHA_INST_56
5430x4AA4 US_ALU_ALPHA_INST_57
5440x4AA8 US_ALU_ALPHA_INST_58
5450x4AAC US_ALU_ALPHA_INST_59
5460x4AB0 US_ALU_ALPHA_INST_60
5470x4AB4 US_ALU_ALPHA_INST_61
5480x4AB8 US_ALU_ALPHA_INST_62
5490x4ABC US_ALU_ALPHA_INST_63
5500x4BC0 FG_FOG_BLEND
5510x4BC4 FG_FOG_FACTOR
5520x4BC8 FG_FOG_COLOR_R
5530x4BCC FG_FOG_COLOR_G
5540x4BD0 FG_FOG_COLOR_B
5550x4BD4 FG_ALPHA_FUNC
5560x4BD8 FG_DEPTH_SRC
5570x4C00 US_ALU_CONST_R_0
5580x4C04 US_ALU_CONST_G_0
5590x4C08 US_ALU_CONST_B_0
5600x4C0C US_ALU_CONST_A_0
5610x4C10 US_ALU_CONST_R_1
5620x4C14 US_ALU_CONST_G_1
5630x4C18 US_ALU_CONST_B_1
5640x4C1C US_ALU_CONST_A_1
5650x4C20 US_ALU_CONST_R_2
5660x4C24 US_ALU_CONST_G_2
5670x4C28 US_ALU_CONST_B_2
5680x4C2C US_ALU_CONST_A_2
5690x4C30 US_ALU_CONST_R_3
5700x4C34 US_ALU_CONST_G_3
5710x4C38 US_ALU_CONST_B_3
5720x4C3C US_ALU_CONST_A_3
5730x4C40 US_ALU_CONST_R_4
5740x4C44 US_ALU_CONST_G_4
5750x4C48 US_ALU_CONST_B_4
5760x4C4C US_ALU_CONST_A_4
5770x4C50 US_ALU_CONST_R_5
5780x4C54 US_ALU_CONST_G_5
5790x4C58 US_ALU_CONST_B_5
5800x4C5C US_ALU_CONST_A_5
5810x4C60 US_ALU_CONST_R_6
5820x4C64 US_ALU_CONST_G_6
5830x4C68 US_ALU_CONST_B_6
5840x4C6C US_ALU_CONST_A_6
5850x4C70 US_ALU_CONST_R_7
5860x4C74 US_ALU_CONST_G_7
5870x4C78 US_ALU_CONST_B_7
5880x4C7C US_ALU_CONST_A_7
5890x4C80 US_ALU_CONST_R_8
5900x4C84 US_ALU_CONST_G_8
5910x4C88 US_ALU_CONST_B_8
5920x4C8C US_ALU_CONST_A_8
5930x4C90 US_ALU_CONST_R_9
5940x4C94 US_ALU_CONST_G_9
5950x4C98 US_ALU_CONST_B_9
5960x4C9C US_ALU_CONST_A_9
5970x4CA0 US_ALU_CONST_R_10
5980x4CA4 US_ALU_CONST_G_10
5990x4CA8 US_ALU_CONST_B_10
6000x4CAC US_ALU_CONST_A_10
6010x4CB0 US_ALU_CONST_R_11
6020x4CB4 US_ALU_CONST_G_11
6030x4CB8 US_ALU_CONST_B_11
6040x4CBC US_ALU_CONST_A_11
6050x4CC0 US_ALU_CONST_R_12
6060x4CC4 US_ALU_CONST_G_12
6070x4CC8 US_ALU_CONST_B_12
6080x4CCC US_ALU_CONST_A_12
6090x4CD0 US_ALU_CONST_R_13
6100x4CD4 US_ALU_CONST_G_13
6110x4CD8 US_ALU_CONST_B_13
6120x4CDC US_ALU_CONST_A_13
6130x4CE0 US_ALU_CONST_R_14
6140x4CE4 US_ALU_CONST_G_14
6150x4CE8 US_ALU_CONST_B_14
6160x4CEC US_ALU_CONST_A_14
6170x4CF0 US_ALU_CONST_R_15
6180x4CF4 US_ALU_CONST_G_15
6190x4CF8 US_ALU_CONST_B_15
6200x4CFC US_ALU_CONST_A_15
6210x4D00 US_ALU_CONST_R_16
6220x4D04 US_ALU_CONST_G_16
6230x4D08 US_ALU_CONST_B_16
6240x4D0C US_ALU_CONST_A_16
6250x4D10 US_ALU_CONST_R_17
6260x4D14 US_ALU_CONST_G_17
6270x4D18 US_ALU_CONST_B_17
6280x4D1C US_ALU_CONST_A_17
6290x4D20 US_ALU_CONST_R_18
6300x4D24 US_ALU_CONST_G_18
6310x4D28 US_ALU_CONST_B_18
6320x4D2C US_ALU_CONST_A_18
6330x4D30 US_ALU_CONST_R_19
6340x4D34 US_ALU_CONST_G_19
6350x4D38 US_ALU_CONST_B_19
6360x4D3C US_ALU_CONST_A_19
6370x4D40 US_ALU_CONST_R_20
6380x4D44 US_ALU_CONST_G_20
6390x4D48 US_ALU_CONST_B_20
6400x4D4C US_ALU_CONST_A_20
6410x4D50 US_ALU_CONST_R_21
6420x4D54 US_ALU_CONST_G_21
6430x4D58 US_ALU_CONST_B_21
6440x4D5C US_ALU_CONST_A_21
6450x4D60 US_ALU_CONST_R_22
6460x4D64 US_ALU_CONST_G_22
6470x4D68 US_ALU_CONST_B_22
6480x4D6C US_ALU_CONST_A_22
6490x4D70 US_ALU_CONST_R_23
6500x4D74 US_ALU_CONST_G_23
6510x4D78 US_ALU_CONST_B_23
6520x4D7C US_ALU_CONST_A_23
6530x4D80 US_ALU_CONST_R_24
6540x4D84 US_ALU_CONST_G_24
6550x4D88 US_ALU_CONST_B_24
6560x4D8C US_ALU_CONST_A_24
6570x4D90 US_ALU_CONST_R_25
6580x4D94 US_ALU_CONST_G_25
6590x4D98 US_ALU_CONST_B_25
6600x4D9C US_ALU_CONST_A_25
6610x4DA0 US_ALU_CONST_R_26
6620x4DA4 US_ALU_CONST_G_26
6630x4DA8 US_ALU_CONST_B_26
6640x4DAC US_ALU_CONST_A_26
6650x4DB0 US_ALU_CONST_R_27
6660x4DB4 US_ALU_CONST_G_27
6670x4DB8 US_ALU_CONST_B_27
6680x4DBC US_ALU_CONST_A_27
6690x4DC0 US_ALU_CONST_R_28
6700x4DC4 US_ALU_CONST_G_28
6710x4DC8 US_ALU_CONST_B_28
6720x4DCC US_ALU_CONST_A_28
6730x4DD0 US_ALU_CONST_R_29
6740x4DD4 US_ALU_CONST_G_29
6750x4DD8 US_ALU_CONST_B_29
6760x4DDC US_ALU_CONST_A_29
6770x4DE0 US_ALU_CONST_R_30
6780x4DE4 US_ALU_CONST_G_30
6790x4DE8 US_ALU_CONST_B_30
6800x4DEC US_ALU_CONST_A_30
6810x4DF0 US_ALU_CONST_R_31
6820x4DF4 US_ALU_CONST_G_31
6830x4DF8 US_ALU_CONST_B_31
6840x4DFC US_ALU_CONST_A_31
6850x4E04 RB3D_BLENDCNTL_R3
6860x4E08 RB3D_ABLENDCNTL_R3
6870x4E0C RB3D_COLOR_CHANNEL_MASK
6880x4E10 RB3D_CONSTANT_COLOR
6890x4E14 RB3D_COLOR_CLEAR_VALUE
6900x4E18 RB3D_ROPCNTL_R3
6910x4E1C RB3D_CLRCMP_FLIPE_R3
6920x4E20 RB3D_CLRCMP_CLR_R3
6930x4E24 RB3D_CLRCMP_MSK_R3
6940x4E48 RB3D_DEBUG_CTL
6950x4E4C RB3D_DSTCACHE_CTLSTAT_R3
6960x4E50 RB3D_DITHER_CTL
6970x4E54 RB3D_CMASK_OFFSET0
6980x4E58 RB3D_CMASK_OFFSET1
6990x4E5C RB3D_CMASK_OFFSET2
7000x4E60 RB3D_CMASK_OFFSET3
7010x4E64 RB3D_CMASK_PITCH0
7020x4E68 RB3D_CMASK_PITCH1
7030x4E6C RB3D_CMASK_PITCH2
7040x4E70 RB3D_CMASK_PITCH3
7050x4E74 RB3D_CMASK_WRINDEX
7060x4E78 RB3D_CMASK_DWORD
7070x4E7C RB3D_CMASK_RDINDEX
7080x4E80 RB3D_AARESOLVE_OFFSET
7090x4E84 RB3D_AARESOLVE_PITCH
7100x4E88 RB3D_AARESOLVE_CTL
7110x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
7120x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
7130x4F04 ZB_ZSTENCILCNTL
7140x4F08 ZB_STENCILREFMASK
7150x4F14 ZB_ZTOP
7160x4F18 ZB_ZCACHE_CTLSTAT
7170x4F1C ZB_BW_CNTL
7180x4F28 ZB_DEPTHCLEARVALUE
7190x4F30 ZB_ZMASK_OFFSET
7200x4F34 ZB_ZMASK_PITCH
7210x4F38 ZB_ZMASK_WRINDEX
7220x4F3C ZB_ZMASK_DWORD
7230x4F40 ZB_ZMASK_RDINDEX
7240x4F44 ZB_HIZ_OFFSET
7250x4F48 ZB_HIZ_WRINDEX
7260x4F4C ZB_HIZ_DWORD
7270x4F50 ZB_HIZ_RDINDEX
7280x4F54 ZB_HIZ_PITCH
7290x4F58 ZB_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
new file mode 100644
index 000000000000..0102a0d5735c
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -0,0 +1,486 @@
1rv515 0x6d40
20x1434 SRC_Y_X
30x1438 DST_Y_X
40x143C DST_HEIGHT_WIDTH
50x146C DP_GUI_MASTER_CNTL
60x1474 BRUSH_Y_X
70x1478 DP_BRUSH_BKGD_CLR
80x147C DP_BRUSH_FRGD_CLR
90x1480 BRUSH_DATA0
100x1484 BRUSH_DATA1
110x1598 DST_WIDTH_HEIGHT
120x15C0 CLR_CMP_CNTL
130x15C4 CLR_CMP_CLR_SRC
140x15C8 CLR_CMP_CLR_DST
150x15CC CLR_CMP_MSK
160x15D8 DP_SRC_FRGD_CLR
170x15DC DP_SRC_BKGD_CLR
180x1600 DST_LINE_START
190x1604 DST_LINE_END
200x1608 DST_LINE_PATCOUNT
210x16C0 DP_CNTL
220x16CC DP_WRITE_MSK
230x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
240x16E8 DEFAULT_SC_BOTTOM_RIGHT
250x16EC SC_TOP_LEFT
260x16F0 SC_BOTTOM_RIGHT
270x16F4 SRC_SC_BOTTOM_RIGHT
280x1714 DSTCACHE_CTLSTAT
290x1720 WAIT_UNTIL
300x172C RBBM_GUICNTL
310x1D98 VAP_VPORT_XSCALE
320x1D9C VAP_VPORT_XOFFSET
330x1DA0 VAP_VPORT_YSCALE
340x1DA4 VAP_VPORT_YOFFSET
350x1DA8 VAP_VPORT_ZSCALE
360x1DAC VAP_VPORT_ZOFFSET
370x2080 VAP_CNTL
380x2090 VAP_OUT_VTX_FMT_0
390x2094 VAP_OUT_VTX_FMT_1
400x20B0 VAP_VTE_CNTL
410x2138 VAP_VF_MIN_VTX_INDX
420x2140 VAP_CNTL_STATUS
430x2150 VAP_PROG_STREAM_CNTL_0
440x2154 VAP_PROG_STREAM_CNTL_1
450x2158 VAP_PROG_STREAM_CNTL_2
460x215C VAP_PROG_STREAM_CNTL_3
470x2160 VAP_PROG_STREAM_CNTL_4
480x2164 VAP_PROG_STREAM_CNTL_5
490x2168 VAP_PROG_STREAM_CNTL_6
500x216C VAP_PROG_STREAM_CNTL_7
510x2180 VAP_VTX_STATE_CNTL
520x2184 VAP_VSM_VTX_ASSM
530x2188 VAP_VTX_STATE_IND_REG_0
540x218C VAP_VTX_STATE_IND_REG_1
550x2190 VAP_VTX_STATE_IND_REG_2
560x2194 VAP_VTX_STATE_IND_REG_3
570x2198 VAP_VTX_STATE_IND_REG_4
580x219C VAP_VTX_STATE_IND_REG_5
590x21A0 VAP_VTX_STATE_IND_REG_6
600x21A4 VAP_VTX_STATE_IND_REG_7
610x21A8 VAP_VTX_STATE_IND_REG_8
620x21AC VAP_VTX_STATE_IND_REG_9
630x21B0 VAP_VTX_STATE_IND_REG_10
640x21B4 VAP_VTX_STATE_IND_REG_11
650x21B8 VAP_VTX_STATE_IND_REG_12
660x21BC VAP_VTX_STATE_IND_REG_13
670x21C0 VAP_VTX_STATE_IND_REG_14
680x21C4 VAP_VTX_STATE_IND_REG_15
690x21DC VAP_PSC_SGN_NORM_CNTL
700x21E0 VAP_PROG_STREAM_CNTL_EXT_0
710x21E4 VAP_PROG_STREAM_CNTL_EXT_1
720x21E8 VAP_PROG_STREAM_CNTL_EXT_2
730x21EC VAP_PROG_STREAM_CNTL_EXT_3
740x21F0 VAP_PROG_STREAM_CNTL_EXT_4
750x21F4 VAP_PROG_STREAM_CNTL_EXT_5
760x21F8 VAP_PROG_STREAM_CNTL_EXT_6
770x21FC VAP_PROG_STREAM_CNTL_EXT_7
780x2200 VAP_PVS_VECTOR_INDX_REG
790x2204 VAP_PVS_VECTOR_DATA_REG
800x2208 VAP_PVS_VECTOR_DATA_REG_128
810x2218 VAP_TEX_TO_COLOR_CNTL
820x221C VAP_CLIP_CNTL
830x2220 VAP_GB_VERT_CLIP_ADJ
840x2224 VAP_GB_VERT_DISC_ADJ
850x2228 VAP_GB_HORZ_CLIP_ADJ
860x222C VAP_GB_HORZ_DISC_ADJ
870x2230 VAP_PVS_FLOW_CNTL_ADDRS_0
880x2234 VAP_PVS_FLOW_CNTL_ADDRS_1
890x2238 VAP_PVS_FLOW_CNTL_ADDRS_2
900x223C VAP_PVS_FLOW_CNTL_ADDRS_3
910x2240 VAP_PVS_FLOW_CNTL_ADDRS_4
920x2244 VAP_PVS_FLOW_CNTL_ADDRS_5
930x2248 VAP_PVS_FLOW_CNTL_ADDRS_6
940x224C VAP_PVS_FLOW_CNTL_ADDRS_7
950x2250 VAP_PVS_FLOW_CNTL_ADDRS_8
960x2254 VAP_PVS_FLOW_CNTL_ADDRS_9
970x2258 VAP_PVS_FLOW_CNTL_ADDRS_10
980x225C VAP_PVS_FLOW_CNTL_ADDRS_11
990x2260 VAP_PVS_FLOW_CNTL_ADDRS_12
1000x2264 VAP_PVS_FLOW_CNTL_ADDRS_13
1010x2268 VAP_PVS_FLOW_CNTL_ADDRS_14
1020x226C VAP_PVS_FLOW_CNTL_ADDRS_15
1030x2284 VAP_PVS_STATE_FLUSH_REG
1040x2288 VAP_PVS_VTX_TIMEOUT_REG
1050x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
1060x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1
1070x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2
1080x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3
1090x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4
1100x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5
1110x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6
1120x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7
1130x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8
1140x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9
1150x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10
1160x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11
1170x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12
1180x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13
1190x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14
1200x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15
1210x22D0 VAP_PVS_CODE_CNTL_0
1220x22D4 VAP_PVS_CONST_CNTL
1230x22D8 VAP_PVS_CODE_CNTL_1
1240x22DC VAP_PVS_FLOW_CNTL_OPC
1250x2500 VAP_PVS_FLOW_CNTL_ADDRS_LW_0
1260x2504 VAP_PVS_FLOW_CNTL_ADDRS_UW_0
1270x2508 VAP_PVS_FLOW_CNTL_ADDRS_LW_1
1280x250C VAP_PVS_FLOW_CNTL_ADDRS_UW_1
1290x2510 VAP_PVS_FLOW_CNTL_ADDRS_LW_2
1300x2514 VAP_PVS_FLOW_CNTL_ADDRS_UW_2
1310x2518 VAP_PVS_FLOW_CNTL_ADDRS_LW_3
1320x251C VAP_PVS_FLOW_CNTL_ADDRS_UW_3
1330x2520 VAP_PVS_FLOW_CNTL_ADDRS_LW_4
1340x2524 VAP_PVS_FLOW_CNTL_ADDRS_UW_4
1350x2528 VAP_PVS_FLOW_CNTL_ADDRS_LW_5
1360x252C VAP_PVS_FLOW_CNTL_ADDRS_UW_5
1370x2530 VAP_PVS_FLOW_CNTL_ADDRS_LW_6
1380x2534 VAP_PVS_FLOW_CNTL_ADDRS_UW_6
1390x2538 VAP_PVS_FLOW_CNTL_ADDRS_LW_7
1400x253C VAP_PVS_FLOW_CNTL_ADDRS_UW_7
1410x2540 VAP_PVS_FLOW_CNTL_ADDRS_LW_8
1420x2544 VAP_PVS_FLOW_CNTL_ADDRS_UW_8
1430x2548 VAP_PVS_FLOW_CNTL_ADDRS_LW_9
1440x254C VAP_PVS_FLOW_CNTL_ADDRS_UW_9
1450x2550 VAP_PVS_FLOW_CNTL_ADDRS_LW_10
1460x2554 VAP_PVS_FLOW_CNTL_ADDRS_UW_10
1470x2558 VAP_PVS_FLOW_CNTL_ADDRS_LW_11
1480x255C VAP_PVS_FLOW_CNTL_ADDRS_UW_11
1490x2560 VAP_PVS_FLOW_CNTL_ADDRS_LW_12
1500x2564 VAP_PVS_FLOW_CNTL_ADDRS_UW_12
1510x2568 VAP_PVS_FLOW_CNTL_ADDRS_LW_13
1520x256C VAP_PVS_FLOW_CNTL_ADDRS_UW_13
1530x2570 VAP_PVS_FLOW_CNTL_ADDRS_LW_14
1540x2574 VAP_PVS_FLOW_CNTL_ADDRS_UW_14
1550x2578 VAP_PVS_FLOW_CNTL_ADDRS_LW_15
1560x257C VAP_PVS_FLOW_CNTL_ADDRS_UW_15
1570x342C RB2D_DSTCACHE_CTLSTAT
1580x4000 GB_VAP_RASTER_VTX_FMT_0
1590x4004 GB_VAP_RASTER_VTX_FMT_1
1600x4008 GB_ENABLE
1610x401C GB_SELECT
1620x4020 GB_AA_CONFIG
1630x4024 GB_FIFO_SIZE
1640x4100 TX_INVALTAGS
1650x4200 GA_POINT_S0
1660x4204 GA_POINT_T0
1670x4208 GA_POINT_S1
1680x420C GA_POINT_T1
1690x4214 GA_TRIANGLE_STIPPLE
1700x421C GA_POINT_SIZE
1710x4230 GA_POINT_MINMAX
1720x4234 GA_LINE_CNTL
1730x4238 GA_LINE_STIPPLE_CONFIG
1740x4260 GA_LINE_STIPPLE_VALUE
1750x4264 GA_LINE_S0
1760x4268 GA_LINE_S1
1770x4278 GA_COLOR_CONTROL
1780x427C GA_SOLID_RG
1790x4280 GA_SOLID_BA
1800x4288 GA_POLY_MODE
1810x428C GA_ROUND_MODE
1820x4290 GA_OFFSET
1830x4294 GA_FOG_SCALE
1840x4298 GA_FOG_OFFSET
1850x42A0 SU_TEX_WRAP
1860x42A4 SU_POLY_OFFSET_FRONT_SCALE
1870x42A8 SU_POLY_OFFSET_FRONT_OFFSET
1880x42AC SU_POLY_OFFSET_BACK_SCALE
1890x42B0 SU_POLY_OFFSET_BACK_OFFSET
1900x42B4 SU_POLY_OFFSET_ENABLE
1910x42B8 SU_CULL_MODE
1920x42C0 SU_DEPTH_SCALE
1930x42C4 SU_DEPTH_OFFSET
1940x42C8 SU_REG_DEST
1950x4300 RS_COUNT
1960x4304 RS_INST_COUNT
1970x4074 RS_IP_0
1980x4078 RS_IP_1
1990x407C RS_IP_2
2000x4080 RS_IP_3
2010x4084 RS_IP_4
2020x4088 RS_IP_5
2030x408C RS_IP_6
2040x4090 RS_IP_7
2050x4094 RS_IP_8
2060x4098 RS_IP_9
2070x409C RS_IP_10
2080x40A0 RS_IP_11
2090x40A4 RS_IP_12
2100x40A8 RS_IP_13
2110x40AC RS_IP_14
2120x40B0 RS_IP_15
2130x4320 RS_INST_0
2140x4324 RS_INST_1
2150x4328 RS_INST_2
2160x432C RS_INST_3
2170x4330 RS_INST_4
2180x4334 RS_INST_5
2190x4338 RS_INST_6
2200x433C RS_INST_7
2210x4340 RS_INST_8
2220x4344 RS_INST_9
2230x4348 RS_INST_10
2240x434C RS_INST_11
2250x4350 RS_INST_12
2260x4354 RS_INST_13
2270x4358 RS_INST_14
2280x435C RS_INST_15
2290x43A4 SC_HYPERZ_EN
2300x43A8 SC_EDGERULE
2310x43B0 SC_CLIP_0_A
2320x43B4 SC_CLIP_0_B
2330x43B8 SC_CLIP_1_A
2340x43BC SC_CLIP_1_B
2350x43C0 SC_CLIP_2_A
2360x43C4 SC_CLIP_2_B
2370x43C8 SC_CLIP_3_A
2380x43CC SC_CLIP_3_B
2390x43D0 SC_CLIP_RULE
2400x43E0 SC_SCISSOR0
2410x43E8 SC_SCREENDOOR
2420x4440 TX_FILTER1_0
2430x4444 TX_FILTER1_1
2440x4448 TX_FILTER1_2
2450x444C TX_FILTER1_3
2460x4450 TX_FILTER1_4
2470x4454 TX_FILTER1_5
2480x4458 TX_FILTER1_6
2490x445C TX_FILTER1_7
2500x4460 TX_FILTER1_8
2510x4464 TX_FILTER1_9
2520x4468 TX_FILTER1_10
2530x446C TX_FILTER1_11
2540x4470 TX_FILTER1_12
2550x4474 TX_FILTER1_13
2560x4478 TX_FILTER1_14
2570x447C TX_FILTER1_15
2580x4580 TX_CHROMA_KEY_0
2590x4584 TX_CHROMA_KEY_1
2600x4588 TX_CHROMA_KEY_2
2610x458C TX_CHROMA_KEY_3
2620x4590 TX_CHROMA_KEY_4
2630x4594 TX_CHROMA_KEY_5
2640x4598 TX_CHROMA_KEY_6
2650x459C TX_CHROMA_KEY_7
2660x45A0 TX_CHROMA_KEY_8
2670x45A4 TX_CHROMA_KEY_9
2680x45A8 TX_CHROMA_KEY_10
2690x45AC TX_CHROMA_KEY_11
2700x45B0 TX_CHROMA_KEY_12
2710x45B4 TX_CHROMA_KEY_13
2720x45B8 TX_CHROMA_KEY_14
2730x45BC TX_CHROMA_KEY_15
2740x45C0 TX_BORDER_COLOR_0
2750x45C4 TX_BORDER_COLOR_1
2760x45C8 TX_BORDER_COLOR_2
2770x45CC TX_BORDER_COLOR_3
2780x45D0 TX_BORDER_COLOR_4
2790x45D4 TX_BORDER_COLOR_5
2800x45D8 TX_BORDER_COLOR_6
2810x45DC TX_BORDER_COLOR_7
2820x45E0 TX_BORDER_COLOR_8
2830x45E4 TX_BORDER_COLOR_9
2840x45E8 TX_BORDER_COLOR_10
2850x45EC TX_BORDER_COLOR_11
2860x45F0 TX_BORDER_COLOR_12
2870x45F4 TX_BORDER_COLOR_13
2880x45F8 TX_BORDER_COLOR_14
2890x45FC TX_BORDER_COLOR_15
2900x4250 GA_US_VECTOR_INDEX
2910x4254 GA_US_VECTOR_DATA
2920x4600 US_CONFIG
2930x4604 US_PIXSIZE
2940x4620 US_FC_BOOL_CONST
2950x4624 US_FC_CTRL
2960x4630 US_CODE_ADDR
2970x4634 US_CODE_RANGE
2980x4638 US_CODE_OFFSET
2990x46A4 US_OUT_FMT_0
3000x46A8 US_OUT_FMT_1
3010x46AC US_OUT_FMT_2
3020x46B0 US_OUT_FMT_3
3030x46B4 US_W_FMT
3040x4BC0 FG_FOG_BLEND
3050x4BC4 FG_FOG_FACTOR
3060x4BC8 FG_FOG_COLOR_R
3070x4BCC FG_FOG_COLOR_G
3080x4BD0 FG_FOG_COLOR_B
3090x4BD4 FG_ALPHA_FUNC
3100x4BD8 FG_DEPTH_SRC
3110x4C00 US_ALU_CONST_R_0
3120x4C04 US_ALU_CONST_G_0
3130x4C08 US_ALU_CONST_B_0
3140x4C0C US_ALU_CONST_A_0
3150x4C10 US_ALU_CONST_R_1
3160x4C14 US_ALU_CONST_G_1
3170x4C18 US_ALU_CONST_B_1
3180x4C1C US_ALU_CONST_A_1
3190x4C20 US_ALU_CONST_R_2
3200x4C24 US_ALU_CONST_G_2
3210x4C28 US_ALU_CONST_B_2
3220x4C2C US_ALU_CONST_A_2
3230x4C30 US_ALU_CONST_R_3
3240x4C34 US_ALU_CONST_G_3
3250x4C38 US_ALU_CONST_B_3
3260x4C3C US_ALU_CONST_A_3
3270x4C40 US_ALU_CONST_R_4
3280x4C44 US_ALU_CONST_G_4
3290x4C48 US_ALU_CONST_B_4
3300x4C4C US_ALU_CONST_A_4
3310x4C50 US_ALU_CONST_R_5
3320x4C54 US_ALU_CONST_G_5
3330x4C58 US_ALU_CONST_B_5
3340x4C5C US_ALU_CONST_A_5
3350x4C60 US_ALU_CONST_R_6
3360x4C64 US_ALU_CONST_G_6
3370x4C68 US_ALU_CONST_B_6
3380x4C6C US_ALU_CONST_A_6
3390x4C70 US_ALU_CONST_R_7
3400x4C74 US_ALU_CONST_G_7
3410x4C78 US_ALU_CONST_B_7
3420x4C7C US_ALU_CONST_A_7
3430x4C80 US_ALU_CONST_R_8
3440x4C84 US_ALU_CONST_G_8
3450x4C88 US_ALU_CONST_B_8
3460x4C8C US_ALU_CONST_A_8
3470x4C90 US_ALU_CONST_R_9
3480x4C94 US_ALU_CONST_G_9
3490x4C98 US_ALU_CONST_B_9
3500x4C9C US_ALU_CONST_A_9
3510x4CA0 US_ALU_CONST_R_10
3520x4CA4 US_ALU_CONST_G_10
3530x4CA8 US_ALU_CONST_B_10
3540x4CAC US_ALU_CONST_A_10
3550x4CB0 US_ALU_CONST_R_11
3560x4CB4 US_ALU_CONST_G_11
3570x4CB8 US_ALU_CONST_B_11
3580x4CBC US_ALU_CONST_A_11
3590x4CC0 US_ALU_CONST_R_12
3600x4CC4 US_ALU_CONST_G_12
3610x4CC8 US_ALU_CONST_B_12
3620x4CCC US_ALU_CONST_A_12
3630x4CD0 US_ALU_CONST_R_13
3640x4CD4 US_ALU_CONST_G_13
3650x4CD8 US_ALU_CONST_B_13
3660x4CDC US_ALU_CONST_A_13
3670x4CE0 US_ALU_CONST_R_14
3680x4CE4 US_ALU_CONST_G_14
3690x4CE8 US_ALU_CONST_B_14
3700x4CEC US_ALU_CONST_A_14
3710x4CF0 US_ALU_CONST_R_15
3720x4CF4 US_ALU_CONST_G_15
3730x4CF8 US_ALU_CONST_B_15
3740x4CFC US_ALU_CONST_A_15
3750x4D00 US_ALU_CONST_R_16
3760x4D04 US_ALU_CONST_G_16
3770x4D08 US_ALU_CONST_B_16
3780x4D0C US_ALU_CONST_A_16
3790x4D10 US_ALU_CONST_R_17
3800x4D14 US_ALU_CONST_G_17
3810x4D18 US_ALU_CONST_B_17
3820x4D1C US_ALU_CONST_A_17
3830x4D20 US_ALU_CONST_R_18
3840x4D24 US_ALU_CONST_G_18
3850x4D28 US_ALU_CONST_B_18
3860x4D2C US_ALU_CONST_A_18
3870x4D30 US_ALU_CONST_R_19
3880x4D34 US_ALU_CONST_G_19
3890x4D38 US_ALU_CONST_B_19
3900x4D3C US_ALU_CONST_A_19
3910x4D40 US_ALU_CONST_R_20
3920x4D44 US_ALU_CONST_G_20
3930x4D48 US_ALU_CONST_B_20
3940x4D4C US_ALU_CONST_A_20
3950x4D50 US_ALU_CONST_R_21
3960x4D54 US_ALU_CONST_G_21
3970x4D58 US_ALU_CONST_B_21
3980x4D5C US_ALU_CONST_A_21
3990x4D60 US_ALU_CONST_R_22
4000x4D64 US_ALU_CONST_G_22
4010x4D68 US_ALU_CONST_B_22
4020x4D6C US_ALU_CONST_A_22
4030x4D70 US_ALU_CONST_R_23
4040x4D74 US_ALU_CONST_G_23
4050x4D78 US_ALU_CONST_B_23
4060x4D7C US_ALU_CONST_A_23
4070x4D80 US_ALU_CONST_R_24
4080x4D84 US_ALU_CONST_G_24
4090x4D88 US_ALU_CONST_B_24
4100x4D8C US_ALU_CONST_A_24
4110x4D90 US_ALU_CONST_R_25
4120x4D94 US_ALU_CONST_G_25
4130x4D98 US_ALU_CONST_B_25
4140x4D9C US_ALU_CONST_A_25
4150x4DA0 US_ALU_CONST_R_26
4160x4DA4 US_ALU_CONST_G_26
4170x4DA8 US_ALU_CONST_B_26
4180x4DAC US_ALU_CONST_A_26
4190x4DB0 US_ALU_CONST_R_27
4200x4DB4 US_ALU_CONST_G_27
4210x4DB8 US_ALU_CONST_B_27
4220x4DBC US_ALU_CONST_A_27
4230x4DC0 US_ALU_CONST_R_28
4240x4DC4 US_ALU_CONST_G_28
4250x4DC8 US_ALU_CONST_B_28
4260x4DCC US_ALU_CONST_A_28
4270x4DD0 US_ALU_CONST_R_29
4280x4DD4 US_ALU_CONST_G_29
4290x4DD8 US_ALU_CONST_B_29
4300x4DDC US_ALU_CONST_A_29
4310x4DE0 US_ALU_CONST_R_30
4320x4DE4 US_ALU_CONST_G_30
4330x4DE8 US_ALU_CONST_B_30
4340x4DEC US_ALU_CONST_A_30
4350x4DF0 US_ALU_CONST_R_31
4360x4DF4 US_ALU_CONST_G_31
4370x4DF8 US_ALU_CONST_B_31
4380x4DFC US_ALU_CONST_A_31
4390x4E04 RB3D_BLENDCNTL_R3
4400x4E08 RB3D_ABLENDCNTL_R3
4410x4E0C RB3D_COLOR_CHANNEL_MASK
4420x4E10 RB3D_CONSTANT_COLOR
4430x4E14 RB3D_COLOR_CLEAR_VALUE
4440x4E18 RB3D_ROPCNTL_R3
4450x4E1C RB3D_CLRCMP_FLIPE_R3
4460x4E20 RB3D_CLRCMP_CLR_R3
4470x4E24 RB3D_CLRCMP_MSK_R3
4480x4E48 RB3D_DEBUG_CTL
4490x4E4C RB3D_DSTCACHE_CTLSTAT_R3
4500x4E50 RB3D_DITHER_CTL
4510x4E54 RB3D_CMASK_OFFSET0
4520x4E58 RB3D_CMASK_OFFSET1
4530x4E5C RB3D_CMASK_OFFSET2
4540x4E60 RB3D_CMASK_OFFSET3
4550x4E64 RB3D_CMASK_PITCH0
4560x4E68 RB3D_CMASK_PITCH1
4570x4E6C RB3D_CMASK_PITCH2
4580x4E70 RB3D_CMASK_PITCH3
4590x4E74 RB3D_CMASK_WRINDEX
4600x4E78 RB3D_CMASK_DWORD
4610x4E7C RB3D_CMASK_RDINDEX
4620x4E80 RB3D_AARESOLVE_OFFSET
4630x4E84 RB3D_AARESOLVE_PITCH
4640x4E88 RB3D_AARESOLVE_CTL
4650x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
4660x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
4670x4EF8 RB3D_CONSTANT_COLOR_AR
4680x4EFC RB3D_CONSTANT_COLOR_GB
4690x4F04 ZB_ZSTENCILCNTL
4700x4F08 ZB_STENCILREFMASK
4710x4F14 ZB_ZTOP
4720x4F18 ZB_ZCACHE_CTLSTAT
4730x4F1C ZB_BW_CNTL
4740x4F28 ZB_DEPTHCLEARVALUE
4750x4F30 ZB_ZMASK_OFFSET
4760x4F34 ZB_ZMASK_PITCH
4770x4F38 ZB_ZMASK_WRINDEX
4780x4F3C ZB_ZMASK_DWORD
4790x4F40 ZB_ZMASK_RDINDEX
4800x4F44 ZB_HIZ_OFFSET
4810x4F48 ZB_HIZ_WRINDEX
4820x4F4C ZB_HIZ_DWORD
4830x4F50 ZB_HIZ_RDINDEX
4840x4F54 ZB_HIZ_PITCH
4850x4F58 ZB_ZPASS_DATA
4860x4FD4 ZB_STENCILREFMASK_BF
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index b29affd9c5d8..a3fbdad938c7 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -29,7 +29,6 @@
29#include <drm/drmP.h> 29#include <drm/drmP.h>
30#include "radeon_reg.h" 30#include "radeon_reg.h"
31#include "radeon.h" 31#include "radeon.h"
32#include "radeon_share.h"
33 32
34/* rs400,rs480 depends on : */ 33/* rs400,rs480 depends on : */
35void r100_hdp_reset(struct radeon_device *rdev); 34void r100_hdp_reset(struct radeon_device *rdev);
@@ -63,7 +62,7 @@ void rs400_gart_adjust_size(struct radeon_device *rdev)
63 break; 62 break;
64 default: 63 default:
65 DRM_ERROR("Unable to use IGP GART size %uM\n", 64 DRM_ERROR("Unable to use IGP GART size %uM\n",
66 rdev->mc.gtt_size >> 20); 65 (unsigned)(rdev->mc.gtt_size >> 20));
67 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); 66 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
68 DRM_ERROR("Forcing to 32M GART size\n"); 67 DRM_ERROR("Forcing to 32M GART size\n");
69 rdev->mc.gtt_size = 32 * 1024 * 1024; 68 rdev->mc.gtt_size = 32 * 1024 * 1024;
@@ -93,20 +92,41 @@ void rs400_gart_tlb_flush(struct radeon_device *rdev)
93 WREG32_MC(RS480_GART_CACHE_CNTRL, 0); 92 WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
94} 93}
95 94
96int rs400_gart_enable(struct radeon_device *rdev) 95int rs400_gart_init(struct radeon_device *rdev)
97{ 96{
98 uint32_t size_reg;
99 uint32_t tmp;
100 int r; 97 int r;
101 98
99 if (rdev->gart.table.ram.ptr) {
100 WARN(1, "RS400 GART already initialized.\n");
101 return 0;
102 }
103 /* Check gart size */
104 switch(rdev->mc.gtt_size / (1024 * 1024)) {
105 case 32:
106 case 64:
107 case 128:
108 case 256:
109 case 512:
110 case 1024:
111 case 2048:
112 break;
113 default:
114 return -EINVAL;
115 }
102 /* Initialize common gart structure */ 116 /* Initialize common gart structure */
103 r = radeon_gart_init(rdev); 117 r = radeon_gart_init(rdev);
104 if (r) { 118 if (r)
105 return r; 119 return r;
106 } 120 if (rs400_debugfs_pcie_gart_info_init(rdev))
107 if (rs400_debugfs_pcie_gart_info_init(rdev)) {
108 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); 121 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
109 } 122 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
123 return radeon_gart_table_ram_alloc(rdev);
124}
125
126int rs400_gart_enable(struct radeon_device *rdev)
127{
128 uint32_t size_reg;
129 uint32_t tmp;
110 130
111 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 131 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
112 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 132 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
@@ -137,13 +157,6 @@ int rs400_gart_enable(struct radeon_device *rdev)
137 default: 157 default:
138 return -EINVAL; 158 return -EINVAL;
139 } 159 }
140 if (rdev->gart.table.ram.ptr == NULL) {
141 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
142 r = radeon_gart_table_ram_alloc(rdev);
143 if (r) {
144 return r;
145 }
146 }
147 /* It should be fine to program it to max value */ 160 /* It should be fine to program it to max value */
148 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 161 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
149 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); 162 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
@@ -202,6 +215,13 @@ void rs400_gart_disable(struct radeon_device *rdev)
202 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 215 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
203} 216}
204 217
218void rs400_gart_fini(struct radeon_device *rdev)
219{
220 rs400_gart_disable(rdev);
221 radeon_gart_table_ram_free(rdev);
222 radeon_gart_fini(rdev);
223}
224
205int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 225int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
206{ 226{
207 uint32_t entry; 227 uint32_t entry;
@@ -256,14 +276,12 @@ int rs400_mc_init(struct radeon_device *rdev)
256 (void)RREG32(RADEON_HOST_PATH_CNTL); 276 (void)RREG32(RADEON_HOST_PATH_CNTL);
257 WREG32(RADEON_HOST_PATH_CNTL, tmp); 277 WREG32(RADEON_HOST_PATH_CNTL, tmp);
258 (void)RREG32(RADEON_HOST_PATH_CNTL); 278 (void)RREG32(RADEON_HOST_PATH_CNTL);
279
259 return 0; 280 return 0;
260} 281}
261 282
262void rs400_mc_fini(struct radeon_device *rdev) 283void rs400_mc_fini(struct radeon_device *rdev)
263{ 284{
264 rs400_gart_disable(rdev);
265 radeon_gart_table_ram_free(rdev);
266 radeon_gart_fini(rdev);
267} 285}
268 286
269 287
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 02fd11aad6a2..0e791e26def3 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -28,6 +28,9 @@
28#include "drmP.h" 28#include "drmP.h"
29#include "radeon_reg.h" 29#include "radeon_reg.h"
30#include "radeon.h" 30#include "radeon.h"
31#include "avivod.h"
32
33#include "rs600_reg_safe.h"
31 34
32/* rs600 depends on : */ 35/* rs600 depends on : */
33void r100_hdp_reset(struct radeon_device *rdev); 36void r100_hdp_reset(struct radeon_device *rdev);
@@ -66,22 +69,35 @@ void rs600_gart_tlb_flush(struct radeon_device *rdev)
66 tmp = RREG32_MC(RS600_MC_PT0_CNTL); 69 tmp = RREG32_MC(RS600_MC_PT0_CNTL);
67} 70}
68 71
69int rs600_gart_enable(struct radeon_device *rdev) 72int rs600_gart_init(struct radeon_device *rdev)
70{ 73{
71 uint32_t tmp;
72 int i;
73 int r; 74 int r;
74 75
76 if (rdev->gart.table.vram.robj) {
77 WARN(1, "RS600 GART already initialized.\n");
78 return 0;
79 }
75 /* Initialize common gart structure */ 80 /* Initialize common gart structure */
76 r = radeon_gart_init(rdev); 81 r = radeon_gart_init(rdev);
77 if (r) { 82 if (r) {
78 return r; 83 return r;
79 } 84 }
80 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 85 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
81 r = radeon_gart_table_vram_alloc(rdev); 86 return radeon_gart_table_vram_alloc(rdev);
82 if (r) { 87}
83 return r; 88
89int rs600_gart_enable(struct radeon_device *rdev)
90{
91 uint32_t tmp;
92 int r, i;
93
94 if (rdev->gart.table.vram.robj == NULL) {
95 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
96 return -EINVAL;
84 } 97 }
98 r = radeon_gart_table_vram_pin(rdev);
99 if (r)
100 return r;
85 /* FIXME: setup default page */ 101 /* FIXME: setup default page */
86 WREG32_MC(RS600_MC_PT0_CNTL, 102 WREG32_MC(RS600_MC_PT0_CNTL,
87 (RS600_EFFECTIVE_L2_CACHE_SIZE(6) | 103 (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
@@ -136,8 +152,17 @@ void rs600_gart_disable(struct radeon_device *rdev)
136 tmp = RREG32_MC(RS600_MC_CNTL1); 152 tmp = RREG32_MC(RS600_MC_CNTL1);
137 tmp &= ~RS600_ENABLE_PAGE_TABLES; 153 tmp &= ~RS600_ENABLE_PAGE_TABLES;
138 WREG32_MC(RS600_MC_CNTL1, tmp); 154 WREG32_MC(RS600_MC_CNTL1, tmp);
139 radeon_object_kunmap(rdev->gart.table.vram.robj); 155 if (rdev->gart.table.vram.robj) {
140 radeon_object_unpin(rdev->gart.table.vram.robj); 156 radeon_object_kunmap(rdev->gart.table.vram.robj);
157 radeon_object_unpin(rdev->gart.table.vram.robj);
158 }
159}
160
161void rs600_gart_fini(struct radeon_device *rdev)
162{
163 rs600_gart_disable(rdev);
164 radeon_gart_table_vram_free(rdev);
165 radeon_gart_fini(rdev);
141} 166}
142 167
143#define R600_PTE_VALID (1 << 0) 168#define R600_PTE_VALID (1 << 0)
@@ -173,6 +198,8 @@ void rs600_mc_disable_clients(struct radeon_device *rdev)
173 "programming pipes. Bad things might happen.\n"); 198 "programming pipes. Bad things might happen.\n");
174 } 199 }
175 200
201 radeon_avivo_vga_render_disable(rdev);
202
176 tmp = RREG32(AVIVO_D1VGA_CONTROL); 203 tmp = RREG32(AVIVO_D1VGA_CONTROL);
177 WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 204 WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
178 tmp = RREG32(AVIVO_D2VGA_CONTROL); 205 tmp = RREG32(AVIVO_D2VGA_CONTROL);
@@ -233,9 +260,6 @@ int rs600_mc_init(struct radeon_device *rdev)
233 260
234void rs600_mc_fini(struct radeon_device *rdev) 261void rs600_mc_fini(struct radeon_device *rdev)
235{ 262{
236 rs600_gart_disable(rdev);
237 radeon_gart_table_vram_free(rdev);
238 radeon_gart_fini(rdev);
239} 263}
240 264
241 265
@@ -251,11 +275,9 @@ int rs600_irq_set(struct radeon_device *rdev)
251 tmp |= RADEON_SW_INT_ENABLE; 275 tmp |= RADEON_SW_INT_ENABLE;
252 } 276 }
253 if (rdev->irq.crtc_vblank_int[0]) { 277 if (rdev->irq.crtc_vblank_int[0]) {
254 tmp |= AVIVO_DISPLAY_INT_STATUS;
255 mode_int |= AVIVO_D1MODE_INT_MASK; 278 mode_int |= AVIVO_D1MODE_INT_MASK;
256 } 279 }
257 if (rdev->irq.crtc_vblank_int[1]) { 280 if (rdev->irq.crtc_vblank_int[1]) {
258 tmp |= AVIVO_DISPLAY_INT_STATUS;
259 mode_int |= AVIVO_D2MODE_INT_MASK; 281 mode_int |= AVIVO_D2MODE_INT_MASK;
260 } 282 }
261 WREG32(RADEON_GEN_INT_CNTL, tmp); 283 WREG32(RADEON_GEN_INT_CNTL, tmp);
@@ -410,64 +432,6 @@ void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
410 WREG32(RS600_MC_DATA, v); 432 WREG32(RS600_MC_DATA, v);
411} 433}
412 434
413static const unsigned rs600_reg_safe_bm[219] = {
414 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
415 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
416 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
417 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
418 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
419 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
420 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
421 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
422 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
423 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
424 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
425 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
426 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
427 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
428 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
429 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
430 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
431 0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
432 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
433 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
434 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
435 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
436 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
437 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
438 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
439 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
440 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
441 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
442 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
443 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
444 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
445 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
446 0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFF,
447 0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF,
448 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
449 0x00000000, 0x0000C100, 0x00000000, 0x00000000,
450 0x00000000, 0x00000000, 0x00000000, 0x00000000,
451 0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF,
452 0x00000000, 0x00000000, 0x00000000, 0x00000000,
453 0x0003FC01, 0xFFFFFCF8, 0xFF800B19, 0xFFFFFFFF,
454 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
455 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
456 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
457 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
458 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
459 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
460 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
461 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
462 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
463 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
464 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
465 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
466 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
467 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
468 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
469};
470
471int rs600_init(struct radeon_device *rdev) 435int rs600_init(struct radeon_device *rdev)
472{ 436{
473 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; 437 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 879882533e45..0f585ca8276d 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -94,9 +94,6 @@ int rs690_mc_init(struct radeon_device *rdev)
94 94
95void rs690_mc_fini(struct radeon_device *rdev) 95void rs690_mc_fini(struct radeon_device *rdev)
96{ 96{
97 rs400_gart_disable(rdev);
98 radeon_gart_table_ram_free(rdev);
99 radeon_gart_fini(rdev);
100} 97}
101 98
102 99
@@ -652,4 +649,3 @@ void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
652 WREG32(RS690_MC_DATA, v); 649 WREG32(RS690_MC_DATA, v);
653 WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); 650 WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
654} 651}
655
diff --git a/drivers/gpu/drm/radeon/rs780.c b/drivers/gpu/drm/radeon/rs780.c
deleted file mode 100644
index 0affcff81825..000000000000
--- a/drivers/gpu/drm/radeon/rs780.c
+++ /dev/null
@@ -1,102 +0,0 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "radeon_reg.h"
30#include "radeon.h"
31
32/* rs780 depends on : */
33void rs600_mc_disable_clients(struct radeon_device *rdev);
34
35/* This files gather functions specifics to:
36 * rs780
37 *
38 * Some of these functions might be used by newer ASICs.
39 */
40int rs780_mc_wait_for_idle(struct radeon_device *rdev);
41void rs780_gpu_init(struct radeon_device *rdev);
42
43
44/*
45 * MC
46 */
47int rs780_mc_init(struct radeon_device *rdev)
48{
49 rs780_gpu_init(rdev);
50 /* FIXME: implement */
51
52 rs600_mc_disable_clients(rdev);
53 if (rs780_mc_wait_for_idle(rdev)) {
54 printk(KERN_WARNING "Failed to wait MC idle while "
55 "programming pipes. Bad things might happen.\n");
56 }
57 return 0;
58}
59
60void rs780_mc_fini(struct radeon_device *rdev)
61{
62 /* FIXME: implement */
63}
64
65
66/*
67 * Global GPU functions
68 */
69void rs780_errata(struct radeon_device *rdev)
70{
71 rdev->pll_errata = 0;
72}
73
74int rs780_mc_wait_for_idle(struct radeon_device *rdev)
75{
76 /* FIXME: implement */
77 return 0;
78}
79
80void rs780_gpu_init(struct radeon_device *rdev)
81{
82 /* FIXME: implement */
83}
84
85
86/*
87 * VRAM info
88 */
89void rs780_vram_get_type(struct radeon_device *rdev)
90{
91 /* FIXME: implement */
92}
93
94void rs780_vram_info(struct radeon_device *rdev)
95{
96 rs780_vram_get_type(rdev);
97
98 /* FIXME: implement */
99 /* Could aper size report 0 ? */
100 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
101 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
102}
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 0566fb67e460..fd799748e7d8 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -27,18 +27,16 @@
27 */ 27 */
28#include <linux/seq_file.h> 28#include <linux/seq_file.h>
29#include "drmP.h" 29#include "drmP.h"
30#include "rv515r.h" 30#include "rv515d.h"
31#include "radeon.h" 31#include "radeon.h"
32#include "radeon_share.h"
33 32
33#include "rv515_reg_safe.h"
34/* rv515 depends on : */ 34/* rv515 depends on : */
35void r100_hdp_reset(struct radeon_device *rdev); 35void r100_hdp_reset(struct radeon_device *rdev);
36int r100_cp_reset(struct radeon_device *rdev); 36int r100_cp_reset(struct radeon_device *rdev);
37int r100_rb2d_reset(struct radeon_device *rdev); 37int r100_rb2d_reset(struct radeon_device *rdev);
38int r100_gui_wait_for_idle(struct radeon_device *rdev); 38int r100_gui_wait_for_idle(struct radeon_device *rdev);
39int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 39int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
40int rv370_pcie_gart_enable(struct radeon_device *rdev);
41void rv370_pcie_gart_disable(struct radeon_device *rdev);
42void r420_pipes_init(struct radeon_device *rdev); 40void r420_pipes_init(struct radeon_device *rdev);
43void rs600_mc_disable_clients(struct radeon_device *rdev); 41void rs600_mc_disable_clients(struct radeon_device *rdev);
44void rs600_disable_vga(struct radeon_device *rdev); 42void rs600_disable_vga(struct radeon_device *rdev);
@@ -126,9 +124,6 @@ int rv515_mc_init(struct radeon_device *rdev)
126 124
127void rv515_mc_fini(struct radeon_device *rdev) 125void rv515_mc_fini(struct radeon_device *rdev)
128{ 126{
129 rv370_pcie_gart_disable(rdev);
130 radeon_gart_table_vram_free(rdev);
131 radeon_gart_fini(rdev);
132} 127}
133 128
134 129
@@ -464,301 +459,244 @@ int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
464#endif 459#endif
465} 460}
466 461
467
468/* 462/*
469 * Asic initialization 463 * Asic initialization
470 */ 464 */
471static const unsigned r500_reg_safe_bm[219] = {
472 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
473 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
474 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
475 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
476 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
477 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
478 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
479 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
480 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
481 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
482 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
483 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
484 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
485 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
486 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
487 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
488 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
489 0xF0000038, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
490 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
491 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
492 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
493 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
494 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
495 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
496 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
497 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
498 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
499 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
500 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
501 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
502 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
503 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
504 0x1FFFFC78, 0xFFFFE000, 0xFFFFFFFE, 0xFFFFFFFF,
505 0x38CF8F50, 0xFFF88082, 0xFF0000FC, 0xFAE009FF,
506 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
507 0xFFFF8CFC, 0xFFFFC1FF, 0xFFFFFFFF, 0xFFFFFFFF,
508 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
509 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF,
510 0x00000000, 0x00000000, 0x00000000, 0x00000000,
511 0x0003FC01, 0x3FFFFCF8, 0xFF800B19, 0xFFDFFFFF,
512 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
513 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
514 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
515 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
516 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
517 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
518 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
519 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
520 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
521 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
522 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
523 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
524 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
525 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
526 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
527};
528
529int rv515_init(struct radeon_device *rdev) 465int rv515_init(struct radeon_device *rdev)
530{ 466{
531 rdev->config.r300.reg_safe_bm = r500_reg_safe_bm; 467 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
532 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r500_reg_safe_bm); 468 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
533 return 0; 469 return 0;
534} 470}
535 471
536void atom_rv515_force_tv_scaler(struct radeon_device *rdev) 472void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
537{ 473{
538 474 int index_reg = 0x6578 + crtc->crtc_offset;
539 WREG32(0x659C, 0x0); 475 int data_reg = 0x657c + crtc->crtc_offset;
540 WREG32(0x6594, 0x705); 476
541 WREG32(0x65A4, 0x10001); 477 WREG32(0x659C + crtc->crtc_offset, 0x0);
542 WREG32(0x65D8, 0x0); 478 WREG32(0x6594 + crtc->crtc_offset, 0x705);
543 WREG32(0x65B0, 0x0); 479 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
544 WREG32(0x65C0, 0x0); 480 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
545 WREG32(0x65D4, 0x0); 481 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
546 WREG32(0x6578, 0x0); 482 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
547 WREG32(0x657C, 0x841880A8); 483 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
548 WREG32(0x6578, 0x1); 484 WREG32(index_reg, 0x0);
549 WREG32(0x657C, 0x84208680); 485 WREG32(data_reg, 0x841880A8);
550 WREG32(0x6578, 0x2); 486 WREG32(index_reg, 0x1);
551 WREG32(0x657C, 0xBFF880B0); 487 WREG32(data_reg, 0x84208680);
552 WREG32(0x6578, 0x100); 488 WREG32(index_reg, 0x2);
553 WREG32(0x657C, 0x83D88088); 489 WREG32(data_reg, 0xBFF880B0);
554 WREG32(0x6578, 0x101); 490 WREG32(index_reg, 0x100);
555 WREG32(0x657C, 0x84608680); 491 WREG32(data_reg, 0x83D88088);
556 WREG32(0x6578, 0x102); 492 WREG32(index_reg, 0x101);
557 WREG32(0x657C, 0xBFF080D0); 493 WREG32(data_reg, 0x84608680);
558 WREG32(0x6578, 0x200); 494 WREG32(index_reg, 0x102);
559 WREG32(0x657C, 0x83988068); 495 WREG32(data_reg, 0xBFF080D0);
560 WREG32(0x6578, 0x201); 496 WREG32(index_reg, 0x200);
561 WREG32(0x657C, 0x84A08680); 497 WREG32(data_reg, 0x83988068);
562 WREG32(0x6578, 0x202); 498 WREG32(index_reg, 0x201);
563 WREG32(0x657C, 0xBFF080F8); 499 WREG32(data_reg, 0x84A08680);
564 WREG32(0x6578, 0x300); 500 WREG32(index_reg, 0x202);
565 WREG32(0x657C, 0x83588058); 501 WREG32(data_reg, 0xBFF080F8);
566 WREG32(0x6578, 0x301); 502 WREG32(index_reg, 0x300);
567 WREG32(0x657C, 0x84E08660); 503 WREG32(data_reg, 0x83588058);
568 WREG32(0x6578, 0x302); 504 WREG32(index_reg, 0x301);
569 WREG32(0x657C, 0xBFF88120); 505 WREG32(data_reg, 0x84E08660);
570 WREG32(0x6578, 0x400); 506 WREG32(index_reg, 0x302);
571 WREG32(0x657C, 0x83188040); 507 WREG32(data_reg, 0xBFF88120);
572 WREG32(0x6578, 0x401); 508 WREG32(index_reg, 0x400);
573 WREG32(0x657C, 0x85008660); 509 WREG32(data_reg, 0x83188040);
574 WREG32(0x6578, 0x402); 510 WREG32(index_reg, 0x401);
575 WREG32(0x657C, 0xBFF88150); 511 WREG32(data_reg, 0x85008660);
576 WREG32(0x6578, 0x500); 512 WREG32(index_reg, 0x402);
577 WREG32(0x657C, 0x82D88030); 513 WREG32(data_reg, 0xBFF88150);
578 WREG32(0x6578, 0x501); 514 WREG32(index_reg, 0x500);
579 WREG32(0x657C, 0x85408640); 515 WREG32(data_reg, 0x82D88030);
580 WREG32(0x6578, 0x502); 516 WREG32(index_reg, 0x501);
581 WREG32(0x657C, 0xBFF88180); 517 WREG32(data_reg, 0x85408640);
582 WREG32(0x6578, 0x600); 518 WREG32(index_reg, 0x502);
583 WREG32(0x657C, 0x82A08018); 519 WREG32(data_reg, 0xBFF88180);
584 WREG32(0x6578, 0x601); 520 WREG32(index_reg, 0x600);
585 WREG32(0x657C, 0x85808620); 521 WREG32(data_reg, 0x82A08018);
586 WREG32(0x6578, 0x602); 522 WREG32(index_reg, 0x601);
587 WREG32(0x657C, 0xBFF081B8); 523 WREG32(data_reg, 0x85808620);
588 WREG32(0x6578, 0x700); 524 WREG32(index_reg, 0x602);
589 WREG32(0x657C, 0x82608010); 525 WREG32(data_reg, 0xBFF081B8);
590 WREG32(0x6578, 0x701); 526 WREG32(index_reg, 0x700);
591 WREG32(0x657C, 0x85A08600); 527 WREG32(data_reg, 0x82608010);
592 WREG32(0x6578, 0x702); 528 WREG32(index_reg, 0x701);
593 WREG32(0x657C, 0x800081F0); 529 WREG32(data_reg, 0x85A08600);
594 WREG32(0x6578, 0x800); 530 WREG32(index_reg, 0x702);
595 WREG32(0x657C, 0x8228BFF8); 531 WREG32(data_reg, 0x800081F0);
596 WREG32(0x6578, 0x801); 532 WREG32(index_reg, 0x800);
597 WREG32(0x657C, 0x85E085E0); 533 WREG32(data_reg, 0x8228BFF8);
598 WREG32(0x6578, 0x802); 534 WREG32(index_reg, 0x801);
599 WREG32(0x657C, 0xBFF88228); 535 WREG32(data_reg, 0x85E085E0);
600 WREG32(0x6578, 0x10000); 536 WREG32(index_reg, 0x802);
601 WREG32(0x657C, 0x82A8BF00); 537 WREG32(data_reg, 0xBFF88228);
602 WREG32(0x6578, 0x10001); 538 WREG32(index_reg, 0x10000);
603 WREG32(0x657C, 0x82A08CC0); 539 WREG32(data_reg, 0x82A8BF00);
604 WREG32(0x6578, 0x10002); 540 WREG32(index_reg, 0x10001);
605 WREG32(0x657C, 0x8008BEF8); 541 WREG32(data_reg, 0x82A08CC0);
606 WREG32(0x6578, 0x10100); 542 WREG32(index_reg, 0x10002);
607 WREG32(0x657C, 0x81F0BF28); 543 WREG32(data_reg, 0x8008BEF8);
608 WREG32(0x6578, 0x10101); 544 WREG32(index_reg, 0x10100);
609 WREG32(0x657C, 0x83608CA0); 545 WREG32(data_reg, 0x81F0BF28);
610 WREG32(0x6578, 0x10102); 546 WREG32(index_reg, 0x10101);
611 WREG32(0x657C, 0x8018BED0); 547 WREG32(data_reg, 0x83608CA0);
612 WREG32(0x6578, 0x10200); 548 WREG32(index_reg, 0x10102);
613 WREG32(0x657C, 0x8148BF38); 549 WREG32(data_reg, 0x8018BED0);
614 WREG32(0x6578, 0x10201); 550 WREG32(index_reg, 0x10200);
615 WREG32(0x657C, 0x84408C80); 551 WREG32(data_reg, 0x8148BF38);
616 WREG32(0x6578, 0x10202); 552 WREG32(index_reg, 0x10201);
617 WREG32(0x657C, 0x8008BEB8); 553 WREG32(data_reg, 0x84408C80);
618 WREG32(0x6578, 0x10300); 554 WREG32(index_reg, 0x10202);
619 WREG32(0x657C, 0x80B0BF78); 555 WREG32(data_reg, 0x8008BEB8);
620 WREG32(0x6578, 0x10301); 556 WREG32(index_reg, 0x10300);
621 WREG32(0x657C, 0x85008C20); 557 WREG32(data_reg, 0x80B0BF78);
622 WREG32(0x6578, 0x10302); 558 WREG32(index_reg, 0x10301);
623 WREG32(0x657C, 0x8020BEA0); 559 WREG32(data_reg, 0x85008C20);
624 WREG32(0x6578, 0x10400); 560 WREG32(index_reg, 0x10302);
625 WREG32(0x657C, 0x8028BF90); 561 WREG32(data_reg, 0x8020BEA0);
626 WREG32(0x6578, 0x10401); 562 WREG32(index_reg, 0x10400);
627 WREG32(0x657C, 0x85E08BC0); 563 WREG32(data_reg, 0x8028BF90);
628 WREG32(0x6578, 0x10402); 564 WREG32(index_reg, 0x10401);
629 WREG32(0x657C, 0x8018BE90); 565 WREG32(data_reg, 0x85E08BC0);
630 WREG32(0x6578, 0x10500); 566 WREG32(index_reg, 0x10402);
631 WREG32(0x657C, 0xBFB8BFB0); 567 WREG32(data_reg, 0x8018BE90);
632 WREG32(0x6578, 0x10501); 568 WREG32(index_reg, 0x10500);
633 WREG32(0x657C, 0x86C08B40); 569 WREG32(data_reg, 0xBFB8BFB0);
634 WREG32(0x6578, 0x10502); 570 WREG32(index_reg, 0x10501);
635 WREG32(0x657C, 0x8010BE90); 571 WREG32(data_reg, 0x86C08B40);
636 WREG32(0x6578, 0x10600); 572 WREG32(index_reg, 0x10502);
637 WREG32(0x657C, 0xBF58BFC8); 573 WREG32(data_reg, 0x8010BE90);
638 WREG32(0x6578, 0x10601); 574 WREG32(index_reg, 0x10600);
639 WREG32(0x657C, 0x87A08AA0); 575 WREG32(data_reg, 0xBF58BFC8);
640 WREG32(0x6578, 0x10602); 576 WREG32(index_reg, 0x10601);
641 WREG32(0x657C, 0x8010BE98); 577 WREG32(data_reg, 0x87A08AA0);
642 WREG32(0x6578, 0x10700); 578 WREG32(index_reg, 0x10602);
643 WREG32(0x657C, 0xBF10BFF0); 579 WREG32(data_reg, 0x8010BE98);
644 WREG32(0x6578, 0x10701); 580 WREG32(index_reg, 0x10700);
645 WREG32(0x657C, 0x886089E0); 581 WREG32(data_reg, 0xBF10BFF0);
646 WREG32(0x6578, 0x10702); 582 WREG32(index_reg, 0x10701);
647 WREG32(0x657C, 0x8018BEB0); 583 WREG32(data_reg, 0x886089E0);
648 WREG32(0x6578, 0x10800); 584 WREG32(index_reg, 0x10702);
649 WREG32(0x657C, 0xBED8BFE8); 585 WREG32(data_reg, 0x8018BEB0);
650 WREG32(0x6578, 0x10801); 586 WREG32(index_reg, 0x10800);
651 WREG32(0x657C, 0x89408940); 587 WREG32(data_reg, 0xBED8BFE8);
652 WREG32(0x6578, 0x10802); 588 WREG32(index_reg, 0x10801);
653 WREG32(0x657C, 0xBFE8BED8); 589 WREG32(data_reg, 0x89408940);
654 WREG32(0x6578, 0x20000); 590 WREG32(index_reg, 0x10802);
655 WREG32(0x657C, 0x80008000); 591 WREG32(data_reg, 0xBFE8BED8);
656 WREG32(0x6578, 0x20001); 592 WREG32(index_reg, 0x20000);
657 WREG32(0x657C, 0x90008000); 593 WREG32(data_reg, 0x80008000);
658 WREG32(0x6578, 0x20002); 594 WREG32(index_reg, 0x20001);
659 WREG32(0x657C, 0x80008000); 595 WREG32(data_reg, 0x90008000);
660 WREG32(0x6578, 0x20003); 596 WREG32(index_reg, 0x20002);
661 WREG32(0x657C, 0x80008000); 597 WREG32(data_reg, 0x80008000);
662 WREG32(0x6578, 0x20100); 598 WREG32(index_reg, 0x20003);
663 WREG32(0x657C, 0x80108000); 599 WREG32(data_reg, 0x80008000);
664 WREG32(0x6578, 0x20101); 600 WREG32(index_reg, 0x20100);
665 WREG32(0x657C, 0x8FE0BF70); 601 WREG32(data_reg, 0x80108000);
666 WREG32(0x6578, 0x20102); 602 WREG32(index_reg, 0x20101);
667 WREG32(0x657C, 0xBFE880C0); 603 WREG32(data_reg, 0x8FE0BF70);
668 WREG32(0x6578, 0x20103); 604 WREG32(index_reg, 0x20102);
669 WREG32(0x657C, 0x80008000); 605 WREG32(data_reg, 0xBFE880C0);
670 WREG32(0x6578, 0x20200); 606 WREG32(index_reg, 0x20103);
671 WREG32(0x657C, 0x8018BFF8); 607 WREG32(data_reg, 0x80008000);
672 WREG32(0x6578, 0x20201); 608 WREG32(index_reg, 0x20200);
673 WREG32(0x657C, 0x8F80BF08); 609 WREG32(data_reg, 0x8018BFF8);
674 WREG32(0x6578, 0x20202); 610 WREG32(index_reg, 0x20201);
675 WREG32(0x657C, 0xBFD081A0); 611 WREG32(data_reg, 0x8F80BF08);
676 WREG32(0x6578, 0x20203); 612 WREG32(index_reg, 0x20202);
677 WREG32(0x657C, 0xBFF88000); 613 WREG32(data_reg, 0xBFD081A0);
678 WREG32(0x6578, 0x20300); 614 WREG32(index_reg, 0x20203);
679 WREG32(0x657C, 0x80188000); 615 WREG32(data_reg, 0xBFF88000);
680 WREG32(0x6578, 0x20301); 616 WREG32(index_reg, 0x20300);
681 WREG32(0x657C, 0x8EE0BEC0); 617 WREG32(data_reg, 0x80188000);
682 WREG32(0x6578, 0x20302); 618 WREG32(index_reg, 0x20301);
683 WREG32(0x657C, 0xBFB082A0); 619 WREG32(data_reg, 0x8EE0BEC0);
684 WREG32(0x6578, 0x20303); 620 WREG32(index_reg, 0x20302);
685 WREG32(0x657C, 0x80008000); 621 WREG32(data_reg, 0xBFB082A0);
686 WREG32(0x6578, 0x20400); 622 WREG32(index_reg, 0x20303);
687 WREG32(0x657C, 0x80188000); 623 WREG32(data_reg, 0x80008000);
688 WREG32(0x6578, 0x20401); 624 WREG32(index_reg, 0x20400);
689 WREG32(0x657C, 0x8E00BEA0); 625 WREG32(data_reg, 0x80188000);
690 WREG32(0x6578, 0x20402); 626 WREG32(index_reg, 0x20401);
691 WREG32(0x657C, 0xBF8883C0); 627 WREG32(data_reg, 0x8E00BEA0);
692 WREG32(0x6578, 0x20403); 628 WREG32(index_reg, 0x20402);
693 WREG32(0x657C, 0x80008000); 629 WREG32(data_reg, 0xBF8883C0);
694 WREG32(0x6578, 0x20500); 630 WREG32(index_reg, 0x20403);
695 WREG32(0x657C, 0x80188000); 631 WREG32(data_reg, 0x80008000);
696 WREG32(0x6578, 0x20501); 632 WREG32(index_reg, 0x20500);
697 WREG32(0x657C, 0x8D00BE90); 633 WREG32(data_reg, 0x80188000);
698 WREG32(0x6578, 0x20502); 634 WREG32(index_reg, 0x20501);
699 WREG32(0x657C, 0xBF588500); 635 WREG32(data_reg, 0x8D00BE90);
700 WREG32(0x6578, 0x20503); 636 WREG32(index_reg, 0x20502);
701 WREG32(0x657C, 0x80008008); 637 WREG32(data_reg, 0xBF588500);
702 WREG32(0x6578, 0x20600); 638 WREG32(index_reg, 0x20503);
703 WREG32(0x657C, 0x80188000); 639 WREG32(data_reg, 0x80008008);
704 WREG32(0x6578, 0x20601); 640 WREG32(index_reg, 0x20600);
705 WREG32(0x657C, 0x8BC0BE98); 641 WREG32(data_reg, 0x80188000);
706 WREG32(0x6578, 0x20602); 642 WREG32(index_reg, 0x20601);
707 WREG32(0x657C, 0xBF308660); 643 WREG32(data_reg, 0x8BC0BE98);
708 WREG32(0x6578, 0x20603); 644 WREG32(index_reg, 0x20602);
709 WREG32(0x657C, 0x80008008); 645 WREG32(data_reg, 0xBF308660);
710 WREG32(0x6578, 0x20700); 646 WREG32(index_reg, 0x20603);
711 WREG32(0x657C, 0x80108000); 647 WREG32(data_reg, 0x80008008);
712 WREG32(0x6578, 0x20701); 648 WREG32(index_reg, 0x20700);
713 WREG32(0x657C, 0x8A80BEB0); 649 WREG32(data_reg, 0x80108000);
714 WREG32(0x6578, 0x20702); 650 WREG32(index_reg, 0x20701);
715 WREG32(0x657C, 0xBF0087C0); 651 WREG32(data_reg, 0x8A80BEB0);
716 WREG32(0x6578, 0x20703); 652 WREG32(index_reg, 0x20702);
717 WREG32(0x657C, 0x80008008); 653 WREG32(data_reg, 0xBF0087C0);
718 WREG32(0x6578, 0x20800); 654 WREG32(index_reg, 0x20703);
719 WREG32(0x657C, 0x80108000); 655 WREG32(data_reg, 0x80008008);
720 WREG32(0x6578, 0x20801); 656 WREG32(index_reg, 0x20800);
721 WREG32(0x657C, 0x8920BED0); 657 WREG32(data_reg, 0x80108000);
722 WREG32(0x6578, 0x20802); 658 WREG32(index_reg, 0x20801);
723 WREG32(0x657C, 0xBED08920); 659 WREG32(data_reg, 0x8920BED0);
724 WREG32(0x6578, 0x20803); 660 WREG32(index_reg, 0x20802);
725 WREG32(0x657C, 0x80008010); 661 WREG32(data_reg, 0xBED08920);
726 WREG32(0x6578, 0x30000); 662 WREG32(index_reg, 0x20803);
727 WREG32(0x657C, 0x90008000); 663 WREG32(data_reg, 0x80008010);
728 WREG32(0x6578, 0x30001); 664 WREG32(index_reg, 0x30000);
729 WREG32(0x657C, 0x80008000); 665 WREG32(data_reg, 0x90008000);
730 WREG32(0x6578, 0x30100); 666 WREG32(index_reg, 0x30001);
731 WREG32(0x657C, 0x8FE0BF90); 667 WREG32(data_reg, 0x80008000);
732 WREG32(0x6578, 0x30101); 668 WREG32(index_reg, 0x30100);
733 WREG32(0x657C, 0xBFF880A0); 669 WREG32(data_reg, 0x8FE0BF90);
734 WREG32(0x6578, 0x30200); 670 WREG32(index_reg, 0x30101);
735 WREG32(0x657C, 0x8F60BF40); 671 WREG32(data_reg, 0xBFF880A0);
736 WREG32(0x6578, 0x30201); 672 WREG32(index_reg, 0x30200);
737 WREG32(0x657C, 0xBFE88180); 673 WREG32(data_reg, 0x8F60BF40);
738 WREG32(0x6578, 0x30300); 674 WREG32(index_reg, 0x30201);
739 WREG32(0x657C, 0x8EC0BF00); 675 WREG32(data_reg, 0xBFE88180);
740 WREG32(0x6578, 0x30301); 676 WREG32(index_reg, 0x30300);
741 WREG32(0x657C, 0xBFC88280); 677 WREG32(data_reg, 0x8EC0BF00);
742 WREG32(0x6578, 0x30400); 678 WREG32(index_reg, 0x30301);
743 WREG32(0x657C, 0x8DE0BEE0); 679 WREG32(data_reg, 0xBFC88280);
744 WREG32(0x6578, 0x30401); 680 WREG32(index_reg, 0x30400);
745 WREG32(0x657C, 0xBFA083A0); 681 WREG32(data_reg, 0x8DE0BEE0);
746 WREG32(0x6578, 0x30500); 682 WREG32(index_reg, 0x30401);
747 WREG32(0x657C, 0x8CE0BED0); 683 WREG32(data_reg, 0xBFA083A0);
748 WREG32(0x6578, 0x30501); 684 WREG32(index_reg, 0x30500);
749 WREG32(0x657C, 0xBF7884E0); 685 WREG32(data_reg, 0x8CE0BED0);
750 WREG32(0x6578, 0x30600); 686 WREG32(index_reg, 0x30501);
751 WREG32(0x657C, 0x8BA0BED8); 687 WREG32(data_reg, 0xBF7884E0);
752 WREG32(0x6578, 0x30601); 688 WREG32(index_reg, 0x30600);
753 WREG32(0x657C, 0xBF508640); 689 WREG32(data_reg, 0x8BA0BED8);
754 WREG32(0x6578, 0x30700); 690 WREG32(index_reg, 0x30601);
755 WREG32(0x657C, 0x8A60BEE8); 691 WREG32(data_reg, 0xBF508640);
756 WREG32(0x6578, 0x30701); 692 WREG32(index_reg, 0x30700);
757 WREG32(0x657C, 0xBF2087A0); 693 WREG32(data_reg, 0x8A60BEE8);
758 WREG32(0x6578, 0x30800); 694 WREG32(index_reg, 0x30701);
759 WREG32(0x657C, 0x8900BF00); 695 WREG32(data_reg, 0xBF2087A0);
760 WREG32(0x6578, 0x30801); 696 WREG32(index_reg, 0x30800);
761 WREG32(0x657C, 0xBF008900); 697 WREG32(data_reg, 0x8900BF00);
698 WREG32(index_reg, 0x30801);
699 WREG32(data_reg, 0xBF008900);
762} 700}
763 701
764struct rv515_watermark { 702struct rv515_watermark {
diff --git a/drivers/gpu/drm/radeon/rv515r.h b/drivers/gpu/drm/radeon/rv515d.h
index f3cf84039906..a65e17ec1c08 100644
--- a/drivers/gpu/drm/radeon/rv515r.h
+++ b/drivers/gpu/drm/radeon/rv515d.h
@@ -25,10 +25,12 @@
25 * Alex Deucher 25 * Alex Deucher
26 * Jerome Glisse 26 * Jerome Glisse
27 */ 27 */
28#ifndef RV515R_H 28#ifndef __RV515D_H__
29#define RV515R_H 29#define __RV515D_H__
30 30
31/* RV515 registers */ 31/*
32 * RV515 registers
33 */
32#define PCIE_INDEX 0x0030 34#define PCIE_INDEX 0x0030
33#define PCIE_DATA 0x0034 35#define PCIE_DATA 0x0034
34#define MC_IND_INDEX 0x0070 36#define MC_IND_INDEX 0x0070
@@ -166,5 +168,53 @@
166#define MC_GLOBW_INIT_LAT_MASK 0xF0000000 168#define MC_GLOBW_INIT_LAT_MASK 0xF0000000
167 169
168 170
171/*
172 * PM4 packet
173 */
174#define CP_PACKET0 0x00000000
175#define PACKET0_BASE_INDEX_SHIFT 0
176#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
177#define PACKET0_COUNT_SHIFT 16
178#define PACKET0_COUNT_MASK (0x3fff << 16)
179#define CP_PACKET1 0x40000000
180#define CP_PACKET2 0x80000000
181#define PACKET2_PAD_SHIFT 0
182#define PACKET2_PAD_MASK (0x3fffffff << 0)
183#define CP_PACKET3 0xC0000000
184#define PACKET3_IT_OPCODE_SHIFT 8
185#define PACKET3_IT_OPCODE_MASK (0xff << 8)
186#define PACKET3_COUNT_SHIFT 16
187#define PACKET3_COUNT_MASK (0x3fff << 16)
188/* PACKET3 op code */
189#define PACKET3_NOP 0x10
190#define PACKET3_3D_DRAW_VBUF 0x28
191#define PACKET3_3D_DRAW_IMMD 0x29
192#define PACKET3_3D_DRAW_INDX 0x2A
193#define PACKET3_3D_LOAD_VBPNTR 0x2F
194#define PACKET3_INDX_BUFFER 0x33
195#define PACKET3_3D_DRAW_VBUF_2 0x34
196#define PACKET3_3D_DRAW_IMMD_2 0x35
197#define PACKET3_3D_DRAW_INDX_2 0x36
198#define PACKET3_BITBLT_MULTI 0x9B
199
200#define PACKET0(reg, n) (CP_PACKET0 | \
201 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
202 REG_SET(PACKET0_COUNT, (n)))
203#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
204#define PACKET3(op, n) (CP_PACKET3 | \
205 REG_SET(PACKET3_IT_OPCODE, (op)) | \
206 REG_SET(PACKET3_COUNT, (n)))
207
208#define PACKET_TYPE0 0
209#define PACKET_TYPE1 1
210#define PACKET_TYPE2 2
211#define PACKET_TYPE3 3
212
213#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
214#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
215#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
216#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
217#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
218
169#endif 219#endif
170 220
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 21d8ffd57308..b574c73a5109 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -25,100 +25,1038 @@
25 * Alex Deucher 25 * Alex Deucher
26 * Jerome Glisse 26 * Jerome Glisse
27 */ 27 */
28#include <linux/firmware.h>
29#include <linux/platform_device.h>
28#include "drmP.h" 30#include "drmP.h"
29#include "radeon_reg.h"
30#include "radeon.h" 31#include "radeon.h"
32#include "radeon_drm.h"
33#include "rv770d.h"
34#include "avivod.h"
35#include "atom.h"
31 36
32/* rv770,rv730,rv710 depends on : */ 37#define R700_PFP_UCODE_SIZE 848
33void rs600_mc_disable_clients(struct radeon_device *rdev); 38#define R700_PM4_UCODE_SIZE 1360
34 39
35/* This files gather functions specifics to: 40static void rv770_gpu_init(struct radeon_device *rdev);
36 * rv770,rv730,rv710 41void rv770_fini(struct radeon_device *rdev);
37 *
38 * Some of these functions might be used by newer ASICs.
39 */
40int rv770_mc_wait_for_idle(struct radeon_device *rdev);
41void rv770_gpu_init(struct radeon_device *rdev);
42 42
43 43
44/* 44/*
45 * MC 45 * GART
46 */ 46 */
47int rv770_mc_init(struct radeon_device *rdev) 47int rv770_pcie_gart_enable(struct radeon_device *rdev)
48{ 48{
49 uint32_t tmp; 49 u32 tmp;
50 int r, i;
50 51
51 rv770_gpu_init(rdev); 52 if (rdev->gart.table.vram.robj == NULL) {
53 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
54 return -EINVAL;
55 }
56 r = radeon_gart_table_vram_pin(rdev);
57 if (r)
58 return r;
59 /* Setup L2 cache */
60 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
61 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
62 EFFECTIVE_L2_QUEUE_SIZE(7));
63 WREG32(VM_L2_CNTL2, 0);
64 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
65 /* Setup TLB control */
66 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
67 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
68 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
69 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
70 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
71 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
72 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
73 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
74 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
75 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
76 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
77 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
78 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
79 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
80 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
81 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
82 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
83 (u32)(rdev->dummy_page.addr >> 12));
84 for (i = 1; i < 7; i++)
85 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
52 86
53 /* setup the gart before changing location so we can ask to 87 r600_pcie_gart_tlb_flush(rdev);
54 * discard unmapped mc request 88 rdev->gart.ready = true;
55 */
56 /* FIXME: disable out of gart access */
57 tmp = rdev->mc.gtt_location / 4096;
58 tmp = REG_SET(R700_LOGICAL_PAGE_NUMBER, tmp);
59 WREG32(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp);
60 tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096;
61 tmp = REG_SET(R700_LOGICAL_PAGE_NUMBER, tmp);
62 WREG32(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp);
63
64 rs600_mc_disable_clients(rdev);
65 if (rv770_mc_wait_for_idle(rdev)) {
66 printk(KERN_WARNING "Failed to wait MC idle while "
67 "programming pipes. Bad things might happen.\n");
68 }
69
70 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
71 tmp = REG_SET(R700_MC_FB_TOP, tmp >> 24);
72 tmp |= REG_SET(R700_MC_FB_BASE, rdev->mc.vram_location >> 24);
73 WREG32(R700_MC_VM_FB_LOCATION, tmp);
74 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
75 tmp = REG_SET(R700_MC_AGP_TOP, tmp >> 22);
76 WREG32(R700_MC_VM_AGP_TOP, tmp);
77 tmp = REG_SET(R700_MC_AGP_BOT, rdev->mc.gtt_location >> 22);
78 WREG32(R700_MC_VM_AGP_BOT, tmp);
79 return 0; 89 return 0;
80} 90}
81 91
82void rv770_mc_fini(struct radeon_device *rdev) 92void rv770_pcie_gart_disable(struct radeon_device *rdev)
93{
94 u32 tmp;
95 int i;
96
97 /* Disable all tables */
98 for (i = 0; i < 7; i++)
99 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
100
101 /* Setup L2 cache */
102 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
103 EFFECTIVE_L2_QUEUE_SIZE(7));
104 WREG32(VM_L2_CNTL2, 0);
105 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
106 /* Setup TLB control */
107 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
108 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
109 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
110 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
111 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
112 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
113 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
114 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
115 if (rdev->gart.table.vram.robj) {
116 radeon_object_kunmap(rdev->gart.table.vram.robj);
117 radeon_object_unpin(rdev->gart.table.vram.robj);
118 }
119}
120
121void rv770_pcie_gart_fini(struct radeon_device *rdev)
83{ 122{
84 /* FIXME: implement */ 123 rv770_pcie_gart_disable(rdev);
124 radeon_gart_table_vram_free(rdev);
125 radeon_gart_fini(rdev);
85} 126}
86 127
87 128
88/* 129/*
89 * Global GPU functions 130 * MC
90 */ 131 */
91void rv770_errata(struct radeon_device *rdev) 132static void rv770_mc_resume(struct radeon_device *rdev)
92{ 133{
93 rdev->pll_errata = 0; 134 u32 d1vga_control, d2vga_control;
135 u32 vga_render_control, vga_hdp_control;
136 u32 d1crtc_control, d2crtc_control;
137 u32 new_d1grph_primary, new_d1grph_secondary;
138 u32 new_d2grph_primary, new_d2grph_secondary;
139 u64 old_vram_start;
140 u32 tmp;
141 int i, j;
142
143 /* Initialize HDP */
144 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
145 WREG32((0x2c14 + j), 0x00000000);
146 WREG32((0x2c18 + j), 0x00000000);
147 WREG32((0x2c1c + j), 0x00000000);
148 WREG32((0x2c20 + j), 0x00000000);
149 WREG32((0x2c24 + j), 0x00000000);
150 }
151 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
152
153 d1vga_control = RREG32(D1VGA_CONTROL);
154 d2vga_control = RREG32(D2VGA_CONTROL);
155 vga_render_control = RREG32(VGA_RENDER_CONTROL);
156 vga_hdp_control = RREG32(VGA_HDP_CONTROL);
157 d1crtc_control = RREG32(D1CRTC_CONTROL);
158 d2crtc_control = RREG32(D2CRTC_CONTROL);
159 old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
160 new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
161 new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
162 new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
163 new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
164 new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
165 new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
166 new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
167 new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
168
169 /* Stop all video */
170 WREG32(D1VGA_CONTROL, 0);
171 WREG32(D2VGA_CONTROL, 0);
172 WREG32(VGA_RENDER_CONTROL, 0);
173 WREG32(D1CRTC_UPDATE_LOCK, 1);
174 WREG32(D2CRTC_UPDATE_LOCK, 1);
175 WREG32(D1CRTC_CONTROL, 0);
176 WREG32(D2CRTC_CONTROL, 0);
177 WREG32(D1CRTC_UPDATE_LOCK, 0);
178 WREG32(D2CRTC_UPDATE_LOCK, 0);
179
180 mdelay(1);
181 if (r600_mc_wait_for_idle(rdev)) {
182 printk(KERN_WARNING "[drm] MC not idle !\n");
183 }
184
185 /* Lockout access through VGA aperture*/
186 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
187
188 /* Update configuration */
189 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
190 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
191 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
192 tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
193 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
194 WREG32(MC_VM_FB_LOCATION, tmp);
195 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
196 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
197 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
198 if (rdev->flags & RADEON_IS_AGP) {
199 WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
200 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
201 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
202 } else {
203 WREG32(MC_VM_AGP_BASE, 0);
204 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
205 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
206 }
207 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
208 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
209 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
210 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
211 WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
212
213 /* Unlock host access */
214 WREG32(VGA_HDP_CONTROL, vga_hdp_control);
215
216 mdelay(1);
217 if (r600_mc_wait_for_idle(rdev)) {
218 printk(KERN_WARNING "[drm] MC not idle !\n");
219 }
220
221 /* Restore video state */
222 WREG32(D1CRTC_UPDATE_LOCK, 1);
223 WREG32(D2CRTC_UPDATE_LOCK, 1);
224 WREG32(D1CRTC_CONTROL, d1crtc_control);
225 WREG32(D2CRTC_CONTROL, d2crtc_control);
226 WREG32(D1CRTC_UPDATE_LOCK, 0);
227 WREG32(D2CRTC_UPDATE_LOCK, 0);
228 WREG32(D1VGA_CONTROL, d1vga_control);
229 WREG32(D2VGA_CONTROL, d2vga_control);
230 WREG32(VGA_RENDER_CONTROL, vga_render_control);
231
232 /* we need to own VRAM, so turn off the VGA renderer here
233 * to stop it overwriting our objects */
234 radeon_avivo_vga_render_disable(rdev);
94} 235}
95 236
96int rv770_mc_wait_for_idle(struct radeon_device *rdev) 237
238/*
239 * CP.
240 */
241void r700_cp_stop(struct radeon_device *rdev)
97{ 242{
98 /* FIXME: implement */ 243 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
99 return 0;
100} 244}
101 245
102void rv770_gpu_init(struct radeon_device *rdev) 246
247static int rv770_cp_load_microcode(struct radeon_device *rdev)
103{ 248{
104 /* FIXME: implement */ 249 const __be32 *fw_data;
250 int i;
251
252 if (!rdev->me_fw || !rdev->pfp_fw)
253 return -EINVAL;
254
255 r700_cp_stop(rdev);
256 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
257
258 /* Reset cp */
259 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
260 RREG32(GRBM_SOFT_RESET);
261 mdelay(15);
262 WREG32(GRBM_SOFT_RESET, 0);
263
264 fw_data = (const __be32 *)rdev->pfp_fw->data;
265 WREG32(CP_PFP_UCODE_ADDR, 0);
266 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
267 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
268 WREG32(CP_PFP_UCODE_ADDR, 0);
269
270 fw_data = (const __be32 *)rdev->me_fw->data;
271 WREG32(CP_ME_RAM_WADDR, 0);
272 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
273 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
274
275 WREG32(CP_PFP_UCODE_ADDR, 0);
276 WREG32(CP_ME_RAM_WADDR, 0);
277 WREG32(CP_ME_RAM_RADDR, 0);
278 return 0;
105} 279}
106 280
107 281
108/* 282/*
109 * VRAM info 283 * Core functions
110 */ 284 */
111void rv770_vram_get_type(struct radeon_device *rdev) 285static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
286 u32 num_backends,
287 u32 backend_disable_mask)
288{
289 u32 backend_map = 0;
290 u32 enabled_backends_mask;
291 u32 enabled_backends_count;
292 u32 cur_pipe;
293 u32 swizzle_pipe[R7XX_MAX_PIPES];
294 u32 cur_backend;
295 u32 i;
296
297 if (num_tile_pipes > R7XX_MAX_PIPES)
298 num_tile_pipes = R7XX_MAX_PIPES;
299 if (num_tile_pipes < 1)
300 num_tile_pipes = 1;
301 if (num_backends > R7XX_MAX_BACKENDS)
302 num_backends = R7XX_MAX_BACKENDS;
303 if (num_backends < 1)
304 num_backends = 1;
305
306 enabled_backends_mask = 0;
307 enabled_backends_count = 0;
308 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
309 if (((backend_disable_mask >> i) & 1) == 0) {
310 enabled_backends_mask |= (1 << i);
311 ++enabled_backends_count;
312 }
313 if (enabled_backends_count == num_backends)
314 break;
315 }
316
317 if (enabled_backends_count == 0) {
318 enabled_backends_mask = 1;
319 enabled_backends_count = 1;
320 }
321
322 if (enabled_backends_count != num_backends)
323 num_backends = enabled_backends_count;
324
325 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
326 switch (num_tile_pipes) {
327 case 1:
328 swizzle_pipe[0] = 0;
329 break;
330 case 2:
331 swizzle_pipe[0] = 0;
332 swizzle_pipe[1] = 1;
333 break;
334 case 3:
335 swizzle_pipe[0] = 0;
336 swizzle_pipe[1] = 2;
337 swizzle_pipe[2] = 1;
338 break;
339 case 4:
340 swizzle_pipe[0] = 0;
341 swizzle_pipe[1] = 2;
342 swizzle_pipe[2] = 3;
343 swizzle_pipe[3] = 1;
344 break;
345 case 5:
346 swizzle_pipe[0] = 0;
347 swizzle_pipe[1] = 2;
348 swizzle_pipe[2] = 4;
349 swizzle_pipe[3] = 1;
350 swizzle_pipe[4] = 3;
351 break;
352 case 6:
353 swizzle_pipe[0] = 0;
354 swizzle_pipe[1] = 2;
355 swizzle_pipe[2] = 4;
356 swizzle_pipe[3] = 5;
357 swizzle_pipe[4] = 3;
358 swizzle_pipe[5] = 1;
359 break;
360 case 7:
361 swizzle_pipe[0] = 0;
362 swizzle_pipe[1] = 2;
363 swizzle_pipe[2] = 4;
364 swizzle_pipe[3] = 6;
365 swizzle_pipe[4] = 3;
366 swizzle_pipe[5] = 1;
367 swizzle_pipe[6] = 5;
368 break;
369 case 8:
370 swizzle_pipe[0] = 0;
371 swizzle_pipe[1] = 2;
372 swizzle_pipe[2] = 4;
373 swizzle_pipe[3] = 6;
374 swizzle_pipe[4] = 3;
375 swizzle_pipe[5] = 1;
376 swizzle_pipe[6] = 7;
377 swizzle_pipe[7] = 5;
378 break;
379 }
380
381 cur_backend = 0;
382 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
383 while (((1 << cur_backend) & enabled_backends_mask) == 0)
384 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
385
386 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
387
388 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
389 }
390
391 return backend_map;
392}
393
394static void rv770_gpu_init(struct radeon_device *rdev)
112{ 395{
113 /* FIXME: implement */ 396 int i, j, num_qd_pipes;
397 u32 sx_debug_1;
398 u32 smx_dc_ctl0;
399 u32 num_gs_verts_per_thread;
400 u32 vgt_gs_per_es;
401 u32 gs_prim_buffer_depth = 0;
402 u32 sq_ms_fifo_sizes;
403 u32 sq_config;
404 u32 sq_thread_resource_mgmt;
405 u32 hdp_host_path_cntl;
406 u32 sq_dyn_gpr_size_simd_ab_0;
407 u32 backend_map;
408 u32 gb_tiling_config = 0;
409 u32 cc_rb_backend_disable = 0;
410 u32 cc_gc_shader_pipe_config = 0;
411 u32 mc_arb_ramcfg;
412 u32 db_debug4;
413
414 /* setup chip specs */
415 switch (rdev->family) {
416 case CHIP_RV770:
417 rdev->config.rv770.max_pipes = 4;
418 rdev->config.rv770.max_tile_pipes = 8;
419 rdev->config.rv770.max_simds = 10;
420 rdev->config.rv770.max_backends = 4;
421 rdev->config.rv770.max_gprs = 256;
422 rdev->config.rv770.max_threads = 248;
423 rdev->config.rv770.max_stack_entries = 512;
424 rdev->config.rv770.max_hw_contexts = 8;
425 rdev->config.rv770.max_gs_threads = 16 * 2;
426 rdev->config.rv770.sx_max_export_size = 128;
427 rdev->config.rv770.sx_max_export_pos_size = 16;
428 rdev->config.rv770.sx_max_export_smx_size = 112;
429 rdev->config.rv770.sq_num_cf_insts = 2;
430
431 rdev->config.rv770.sx_num_of_sets = 7;
432 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
433 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
434 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
435 break;
436 case CHIP_RV730:
437 rdev->config.rv770.max_pipes = 2;
438 rdev->config.rv770.max_tile_pipes = 4;
439 rdev->config.rv770.max_simds = 8;
440 rdev->config.rv770.max_backends = 2;
441 rdev->config.rv770.max_gprs = 128;
442 rdev->config.rv770.max_threads = 248;
443 rdev->config.rv770.max_stack_entries = 256;
444 rdev->config.rv770.max_hw_contexts = 8;
445 rdev->config.rv770.max_gs_threads = 16 * 2;
446 rdev->config.rv770.sx_max_export_size = 256;
447 rdev->config.rv770.sx_max_export_pos_size = 32;
448 rdev->config.rv770.sx_max_export_smx_size = 224;
449 rdev->config.rv770.sq_num_cf_insts = 2;
450
451 rdev->config.rv770.sx_num_of_sets = 7;
452 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
453 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
454 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
455 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
456 rdev->config.rv770.sx_max_export_pos_size -= 16;
457 rdev->config.rv770.sx_max_export_smx_size += 16;
458 }
459 break;
460 case CHIP_RV710:
461 rdev->config.rv770.max_pipes = 2;
462 rdev->config.rv770.max_tile_pipes = 2;
463 rdev->config.rv770.max_simds = 2;
464 rdev->config.rv770.max_backends = 1;
465 rdev->config.rv770.max_gprs = 256;
466 rdev->config.rv770.max_threads = 192;
467 rdev->config.rv770.max_stack_entries = 256;
468 rdev->config.rv770.max_hw_contexts = 4;
469 rdev->config.rv770.max_gs_threads = 8 * 2;
470 rdev->config.rv770.sx_max_export_size = 128;
471 rdev->config.rv770.sx_max_export_pos_size = 16;
472 rdev->config.rv770.sx_max_export_smx_size = 112;
473 rdev->config.rv770.sq_num_cf_insts = 1;
474
475 rdev->config.rv770.sx_num_of_sets = 7;
476 rdev->config.rv770.sc_prim_fifo_size = 0x40;
477 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
478 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
479 break;
480 case CHIP_RV740:
481 rdev->config.rv770.max_pipes = 4;
482 rdev->config.rv770.max_tile_pipes = 4;
483 rdev->config.rv770.max_simds = 8;
484 rdev->config.rv770.max_backends = 4;
485 rdev->config.rv770.max_gprs = 256;
486 rdev->config.rv770.max_threads = 248;
487 rdev->config.rv770.max_stack_entries = 512;
488 rdev->config.rv770.max_hw_contexts = 8;
489 rdev->config.rv770.max_gs_threads = 16 * 2;
490 rdev->config.rv770.sx_max_export_size = 256;
491 rdev->config.rv770.sx_max_export_pos_size = 32;
492 rdev->config.rv770.sx_max_export_smx_size = 224;
493 rdev->config.rv770.sq_num_cf_insts = 2;
494
495 rdev->config.rv770.sx_num_of_sets = 7;
496 rdev->config.rv770.sc_prim_fifo_size = 0x100;
497 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
498 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
499
500 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
501 rdev->config.rv770.sx_max_export_pos_size -= 16;
502 rdev->config.rv770.sx_max_export_smx_size += 16;
503 }
504 break;
505 default:
506 break;
507 }
508
509 /* Initialize HDP */
510 j = 0;
511 for (i = 0; i < 32; i++) {
512 WREG32((0x2c14 + j), 0x00000000);
513 WREG32((0x2c18 + j), 0x00000000);
514 WREG32((0x2c1c + j), 0x00000000);
515 WREG32((0x2c20 + j), 0x00000000);
516 WREG32((0x2c24 + j), 0x00000000);
517 j += 0x18;
518 }
519
520 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
521
522 /* setup tiling, simd, pipe config */
523 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
524
525 switch (rdev->config.rv770.max_tile_pipes) {
526 case 1:
527 gb_tiling_config |= PIPE_TILING(0);
528 break;
529 case 2:
530 gb_tiling_config |= PIPE_TILING(1);
531 break;
532 case 4:
533 gb_tiling_config |= PIPE_TILING(2);
534 break;
535 case 8:
536 gb_tiling_config |= PIPE_TILING(3);
537 break;
538 default:
539 break;
540 }
541
542 if (rdev->family == CHIP_RV770)
543 gb_tiling_config |= BANK_TILING(1);
544 else
545 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK);
546
547 gb_tiling_config |= GROUP_SIZE(0);
548
549 if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) {
550 gb_tiling_config |= ROW_TILING(3);
551 gb_tiling_config |= SAMPLE_SPLIT(3);
552 } else {
553 gb_tiling_config |=
554 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
555 gb_tiling_config |=
556 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
557 }
558
559 gb_tiling_config |= BANK_SWAPS(1);
560
561 backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes,
562 rdev->config.rv770.max_backends,
563 (0xff << rdev->config.rv770.max_backends) & 0xff);
564 gb_tiling_config |= BACKEND_MAP(backend_map);
565
566 cc_gc_shader_pipe_config =
567 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
568 cc_gc_shader_pipe_config |=
569 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
570
571 cc_rb_backend_disable =
572 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
573
574 WREG32(GB_TILING_CONFIG, gb_tiling_config);
575 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
576 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
577
578 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
579 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
580 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
581
582 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
583 WREG32(CGTS_SYS_TCC_DISABLE, 0);
584 WREG32(CGTS_TCC_DISABLE, 0);
585 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
586 WREG32(CGTS_USER_TCC_DISABLE, 0);
587
588 num_qd_pipes =
589 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK);
590 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
591 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
592
593 /* set HW defaults for 3D engine */
594 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
595 ROQ_IB2_START(0x2b)));
596
597 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
598
599 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
600 SYNC_GRADIENT |
601 SYNC_WALKER |
602 SYNC_ALIGNER));
603
604 sx_debug_1 = RREG32(SX_DEBUG_1);
605 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
606 WREG32(SX_DEBUG_1, sx_debug_1);
607
608 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
609 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
610 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
611 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
612
613 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
614 GS_FLUSH_CTL(4) |
615 ACK_FLUSH_CTL(3) |
616 SYNC_FLUSH_CTL));
617
618 if (rdev->family == CHIP_RV770)
619 WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f));
620 else {
621 db_debug4 = RREG32(DB_DEBUG4);
622 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
623 WREG32(DB_DEBUG4, db_debug4);
624 }
625
626 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
627 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
628 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
629
630 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
631 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
632 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
633
634 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
635
636 WREG32(VGT_NUM_INSTANCES, 1);
637
638 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
639
640 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
641
642 WREG32(CP_PERFMON_CNTL, 0);
643
644 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
645 DONE_FIFO_HIWATER(0xe0) |
646 ALU_UPDATE_FIFO_HIWATER(0x8));
647 switch (rdev->family) {
648 case CHIP_RV770:
649 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
650 break;
651 case CHIP_RV730:
652 case CHIP_RV710:
653 case CHIP_RV740:
654 default:
655 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
656 break;
657 }
658 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
659
660 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
661 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
662 */
663 sq_config = RREG32(SQ_CONFIG);
664 sq_config &= ~(PS_PRIO(3) |
665 VS_PRIO(3) |
666 GS_PRIO(3) |
667 ES_PRIO(3));
668 sq_config |= (DX9_CONSTS |
669 VC_ENABLE |
670 EXPORT_SRC_C |
671 PS_PRIO(0) |
672 VS_PRIO(1) |
673 GS_PRIO(2) |
674 ES_PRIO(3));
675 if (rdev->family == CHIP_RV710)
676 /* no vertex cache */
677 sq_config &= ~VC_ENABLE;
678
679 WREG32(SQ_CONFIG, sq_config);
680
681 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
682 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
683 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
684
685 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
686 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
687
688 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
689 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
690 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
691 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
692 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
693 else
694 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
695 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
696
697 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
698 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
699
700 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
701 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
702
703 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
704 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
705 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
706 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
707
708 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
709 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
710 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
711 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
712 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
713 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
714 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
715 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
716
717 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
718 FORCE_EOV_MAX_REZ_CNT(255)));
719
720 if (rdev->family == CHIP_RV710)
721 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
722 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
723 else
724 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
725 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
726
727 switch (rdev->family) {
728 case CHIP_RV770:
729 case CHIP_RV730:
730 case CHIP_RV740:
731 gs_prim_buffer_depth = 384;
732 break;
733 case CHIP_RV710:
734 gs_prim_buffer_depth = 128;
735 break;
736 default:
737 break;
738 }
739
740 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
741 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
742 /* Max value for this is 256 */
743 if (vgt_gs_per_es > 256)
744 vgt_gs_per_es = 256;
745
746 WREG32(VGT_ES_PER_GS, 128);
747 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
748 WREG32(VGT_GS_PER_VS, 2);
749
750 /* more default values. 2D/3D driver should adjust as needed */
751 WREG32(VGT_GS_VERTEX_REUSE, 16);
752 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
753 WREG32(VGT_STRMOUT_EN, 0);
754 WREG32(SX_MISC, 0);
755 WREG32(PA_SC_MODE_CNTL, 0);
756 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
757 WREG32(PA_SC_AA_CONFIG, 0);
758 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
759 WREG32(PA_SC_LINE_STIPPLE, 0);
760 WREG32(SPI_INPUT_Z, 0);
761 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
762 WREG32(CB_COLOR7_FRAG, 0);
763
764 /* clear render buffer base addresses */
765 WREG32(CB_COLOR0_BASE, 0);
766 WREG32(CB_COLOR1_BASE, 0);
767 WREG32(CB_COLOR2_BASE, 0);
768 WREG32(CB_COLOR3_BASE, 0);
769 WREG32(CB_COLOR4_BASE, 0);
770 WREG32(CB_COLOR5_BASE, 0);
771 WREG32(CB_COLOR6_BASE, 0);
772 WREG32(CB_COLOR7_BASE, 0);
773
774 WREG32(TCP_CNTL, 0);
775
776 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
777 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
778
779 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
780
781 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
782 NUM_CLIP_SEQ(3)));
783
114} 784}
115 785
116void rv770_vram_info(struct radeon_device *rdev) 786int rv770_mc_init(struct radeon_device *rdev)
117{ 787{
118 rv770_vram_get_type(rdev); 788 fixed20_12 a;
789 u32 tmp;
790 int r;
119 791
120 /* FIXME: implement */ 792 /* Get VRAM informations */
793 /* FIXME: Don't know how to determine vram width, need to check
794 * vram_width usage
795 */
796 rdev->mc.vram_width = 128;
797 rdev->mc.vram_is_ddr = true;
121 /* Could aper size report 0 ? */ 798 /* Could aper size report 0 ? */
122 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 799 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
123 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 800 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
801 /* Setup GPU memory space */
802 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
803 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
804 if (rdev->flags & RADEON_IS_AGP) {
805 r = radeon_agp_init(rdev);
806 if (r)
807 return r;
808 /* gtt_size is setup by radeon_agp_init */
809 rdev->mc.gtt_location = rdev->mc.agp_base;
810 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
811 /* Try to put vram before or after AGP because we
812 * we want SYSTEM_APERTURE to cover both VRAM and
813 * AGP so that GPU can catch out of VRAM/AGP access
814 */
815 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
816 /* Enought place before */
817 rdev->mc.vram_location = rdev->mc.gtt_location -
818 rdev->mc.mc_vram_size;
819 } else if (tmp > rdev->mc.mc_vram_size) {
820 /* Enought place after */
821 rdev->mc.vram_location = rdev->mc.gtt_location +
822 rdev->mc.gtt_size;
823 } else {
824 /* Try to setup VRAM then AGP might not
825 * not work on some card
826 */
827 rdev->mc.vram_location = 0x00000000UL;
828 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
829 }
830 } else {
831 rdev->mc.vram_location = 0x00000000UL;
832 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
833 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
834 }
835 rdev->mc.vram_start = rdev->mc.vram_location;
836 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
837 rdev->mc.gtt_start = rdev->mc.gtt_location;
838 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
839 /* FIXME: we should enforce default clock in case GPU is not in
840 * default setup
841 */
842 a.full = rfixed_const(100);
843 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
844 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
845 return 0;
846}
847int rv770_gpu_reset(struct radeon_device *rdev)
848{
849 /* FIXME: implement any rv770 specific bits */
850 return r600_gpu_reset(rdev);
851}
852
853static int rv770_startup(struct radeon_device *rdev)
854{
855 int r;
856
857 radeon_gpu_reset(rdev);
858 rv770_mc_resume(rdev);
859 r = rv770_pcie_gart_enable(rdev);
860 if (r)
861 return r;
862 rv770_gpu_init(rdev);
863
864 r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
865 &rdev->r600_blit.shader_gpu_addr);
866 if (r) {
867 DRM_ERROR("failed to pin blit object %d\n", r);
868 return r;
869 }
870
871 r = radeon_ring_init(rdev, rdev->cp.ring_size);
872 if (r)
873 return r;
874 r = rv770_cp_load_microcode(rdev);
875 if (r)
876 return r;
877 r = r600_cp_resume(rdev);
878 if (r)
879 return r;
880 r = r600_wb_init(rdev);
881 if (r)
882 return r;
883 return 0;
884}
885
886int rv770_resume(struct radeon_device *rdev)
887{
888 int r;
889
890 if (radeon_gpu_reset(rdev)) {
891 /* FIXME: what do we want to do here ? */
892 }
893 /* post card */
894 if (rdev->is_atom_bios) {
895 atom_asic_init(rdev->mode_info.atom_context);
896 } else {
897 radeon_combios_asic_init(rdev->ddev);
898 }
899 /* Initialize clocks */
900 r = radeon_clocks_init(rdev);
901 if (r) {
902 return r;
903 }
904
905 r = rv770_startup(rdev);
906 if (r) {
907 DRM_ERROR("r600 startup failed on resume\n");
908 return r;
909 }
910
911 r = radeon_ib_test(rdev);
912 if (r) {
913 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
914 return r;
915 }
916 return r;
917
918}
919
920int rv770_suspend(struct radeon_device *rdev)
921{
922 /* FIXME: we should wait for ring to be empty */
923 r700_cp_stop(rdev);
924 rdev->cp.ready = false;
925 rv770_pcie_gart_disable(rdev);
926
927 /* unpin shaders bo */
928 radeon_object_unpin(rdev->r600_blit.shader_obj);
929 return 0;
930}
931
932/* Plan is to move initialization in that function and use
933 * helper function so that radeon_device_init pretty much
934 * do nothing more than calling asic specific function. This
935 * should also allow to remove a bunch of callback function
936 * like vram_info.
937 */
938int rv770_init(struct radeon_device *rdev)
939{
940 int r;
941
942 rdev->new_init_path = true;
943 r = radeon_dummy_page_init(rdev);
944 if (r)
945 return r;
946 /* This don't do much */
947 r = radeon_gem_init(rdev);
948 if (r)
949 return r;
950 /* Read BIOS */
951 if (!radeon_get_bios(rdev)) {
952 if (ASIC_IS_AVIVO(rdev))
953 return -EINVAL;
954 }
955 /* Must be an ATOMBIOS */
956 if (!rdev->is_atom_bios)
957 return -EINVAL;
958 r = radeon_atombios_init(rdev);
959 if (r)
960 return r;
961 /* Post card if necessary */
962 if (!r600_card_posted(rdev) && rdev->bios) {
963 DRM_INFO("GPU not posted. posting now...\n");
964 atom_asic_init(rdev->mode_info.atom_context);
965 }
966 /* Initialize scratch registers */
967 r600_scratch_init(rdev);
968 /* Initialize surface registers */
969 radeon_surface_init(rdev);
970 radeon_get_clock_info(rdev->ddev);
971 r = radeon_clocks_init(rdev);
972 if (r)
973 return r;
974 /* Fence driver */
975 r = radeon_fence_driver_init(rdev);
976 if (r)
977 return r;
978 r = rv770_mc_init(rdev);
979 if (r) {
980 if (rdev->flags & RADEON_IS_AGP) {
981 /* Retry with disabling AGP */
982 rv770_fini(rdev);
983 rdev->flags &= ~RADEON_IS_AGP;
984 return rv770_init(rdev);
985 }
986 return r;
987 }
988 /* Memory manager */
989 r = radeon_object_init(rdev);
990 if (r)
991 return r;
992 rdev->cp.ring_obj = NULL;
993 r600_ring_init(rdev, 1024 * 1024);
994
995 if (!rdev->me_fw || !rdev->pfp_fw) {
996 r = r600_cp_init_microcode(rdev);
997 if (r) {
998 DRM_ERROR("Failed to load firmware!\n");
999 return r;
1000 }
1001 }
1002
1003 r = r600_pcie_gart_init(rdev);
1004 if (r)
1005 return r;
1006
1007 rdev->accel_working = true;
1008 r = r600_blit_init(rdev);
1009 if (r) {
1010 DRM_ERROR("radeon: failled blitter (%d).\n", r);
1011 rdev->accel_working = false;
1012 }
1013
1014 r = rv770_startup(rdev);
1015 if (r) {
1016 if (rdev->flags & RADEON_IS_AGP) {
1017 /* Retry with disabling AGP */
1018 rv770_fini(rdev);
1019 rdev->flags &= ~RADEON_IS_AGP;
1020 return rv770_init(rdev);
1021 }
1022 rdev->accel_working = false;
1023 }
1024 if (rdev->accel_working) {
1025 r = radeon_ib_pool_init(rdev);
1026 if (r) {
1027 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
1028 rdev->accel_working = false;
1029 }
1030 r = radeon_ib_test(rdev);
1031 if (r) {
1032 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1033 rdev->accel_working = false;
1034 }
1035 }
1036 return 0;
1037}
1038
1039void rv770_fini(struct radeon_device *rdev)
1040{
1041 rv770_suspend(rdev);
1042
1043 r600_blit_fini(rdev);
1044 radeon_ring_fini(rdev);
1045 rv770_pcie_gart_fini(rdev);
1046 radeon_gem_fini(rdev);
1047 radeon_fence_driver_fini(rdev);
1048 radeon_clocks_fini(rdev);
1049#if __OS_HAS_AGP
1050 if (rdev->flags & RADEON_IS_AGP)
1051 radeon_agp_fini(rdev);
1052#endif
1053 radeon_object_fini(rdev);
1054 if (rdev->is_atom_bios) {
1055 radeon_atombios_fini(rdev);
1056 } else {
1057 radeon_combios_fini(rdev);
1058 }
1059 kfree(rdev->bios);
1060 rdev->bios = NULL;
1061 radeon_dummy_page_fini(rdev);
124} 1062}
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
new file mode 100644
index 000000000000..4b9c3d6396ff
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -0,0 +1,341 @@
1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 * Jerome Glisse
26 */
27#ifndef RV770_H
28#define RV770_H
29
30#define R7XX_MAX_SH_GPRS 256
31#define R7XX_MAX_TEMP_GPRS 16
32#define R7XX_MAX_SH_THREADS 256
33#define R7XX_MAX_SH_STACK_ENTRIES 4096
34#define R7XX_MAX_BACKENDS 8
35#define R7XX_MAX_BACKENDS_MASK 0xff
36#define R7XX_MAX_SIMDS 16
37#define R7XX_MAX_SIMDS_MASK 0xffff
38#define R7XX_MAX_PIPES 8
39#define R7XX_MAX_PIPES_MASK 0xff
40
41/* Registers */
42#define CB_COLOR0_BASE 0x28040
43#define CB_COLOR1_BASE 0x28044
44#define CB_COLOR2_BASE 0x28048
45#define CB_COLOR3_BASE 0x2804C
46#define CB_COLOR4_BASE 0x28050
47#define CB_COLOR5_BASE 0x28054
48#define CB_COLOR6_BASE 0x28058
49#define CB_COLOR7_BASE 0x2805C
50#define CB_COLOR7_FRAG 0x280FC
51
52#define CC_GC_SHADER_PIPE_CONFIG 0x8950
53#define CC_RB_BACKEND_DISABLE 0x98F4
54#define BACKEND_DISABLE(x) ((x) << 16)
55#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
56
57#define CGTS_SYS_TCC_DISABLE 0x3F90
58#define CGTS_TCC_DISABLE 0x9148
59#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
60#define CGTS_USER_TCC_DISABLE 0x914C
61
62#define CONFIG_MEMSIZE 0x5428
63
64#define CP_ME_CNTL 0x86D8
65#define CP_ME_HALT (1<<28)
66#define CP_PFP_HALT (1<<26)
67#define CP_ME_RAM_DATA 0xC160
68#define CP_ME_RAM_RADDR 0xC158
69#define CP_ME_RAM_WADDR 0xC15C
70#define CP_MEQ_THRESHOLDS 0x8764
71#define STQ_SPLIT(x) ((x) << 0)
72#define CP_PERFMON_CNTL 0x87FC
73#define CP_PFP_UCODE_ADDR 0xC150
74#define CP_PFP_UCODE_DATA 0xC154
75#define CP_QUEUE_THRESHOLDS 0x8760
76#define ROQ_IB1_START(x) ((x) << 0)
77#define ROQ_IB2_START(x) ((x) << 8)
78#define CP_RB_CNTL 0xC104
79#define RB_BUFSZ(x) ((x)<<0)
80#define RB_BLKSZ(x) ((x)<<8)
81#define RB_NO_UPDATE (1<<27)
82#define RB_RPTR_WR_ENA (1<<31)
83#define BUF_SWAP_32BIT (2 << 16)
84#define CP_RB_RPTR 0x8700
85#define CP_RB_RPTR_ADDR 0xC10C
86#define CP_RB_RPTR_ADDR_HI 0xC110
87#define CP_RB_RPTR_WR 0xC108
88#define CP_RB_WPTR 0xC114
89#define CP_RB_WPTR_ADDR 0xC118
90#define CP_RB_WPTR_ADDR_HI 0xC11C
91#define CP_RB_WPTR_DELAY 0x8704
92#define CP_SEM_WAIT_TIMER 0x85BC
93
94#define DB_DEBUG3 0x98B0
95#define DB_CLK_OFF_DELAY(x) ((x) << 11)
96#define DB_DEBUG4 0x9B8C
97#define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
98
99#define DCP_TILING_CONFIG 0x6CA0
100#define PIPE_TILING(x) ((x) << 1)
101#define BANK_TILING(x) ((x) << 4)
102#define GROUP_SIZE(x) ((x) << 6)
103#define ROW_TILING(x) ((x) << 8)
104#define BANK_SWAPS(x) ((x) << 11)
105#define SAMPLE_SPLIT(x) ((x) << 14)
106#define BACKEND_MAP(x) ((x) << 16)
107
108#define GB_TILING_CONFIG 0x98F0
109
110#define GC_USER_SHADER_PIPE_CONFIG 0x8954
111#define INACTIVE_QD_PIPES(x) ((x) << 8)
112#define INACTIVE_QD_PIPES_MASK 0x0000FF00
113#define INACTIVE_SIMDS(x) ((x) << 16)
114#define INACTIVE_SIMDS_MASK 0x00FF0000
115
116#define GRBM_CNTL 0x8000
117#define GRBM_READ_TIMEOUT(x) ((x) << 0)
118#define GRBM_SOFT_RESET 0x8020
119#define SOFT_RESET_CP (1<<0)
120#define GRBM_STATUS 0x8010
121#define CMDFIFO_AVAIL_MASK 0x0000000F
122#define GUI_ACTIVE (1<<31)
123#define GRBM_STATUS2 0x8014
124
125#define HDP_HOST_PATH_CNTL 0x2C00
126#define HDP_NONSURFACE_BASE 0x2C04
127#define HDP_NONSURFACE_INFO 0x2C08
128#define HDP_NONSURFACE_SIZE 0x2C0C
129#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
130#define HDP_TILING_CONFIG 0x2F3C
131
132#define MC_ARB_RAMCFG 0x2760
133#define NOOFBANK_SHIFT 0
134#define NOOFBANK_MASK 0x00000003
135#define NOOFRANK_SHIFT 2
136#define NOOFRANK_MASK 0x00000004
137#define NOOFROWS_SHIFT 3
138#define NOOFROWS_MASK 0x00000038
139#define NOOFCOLS_SHIFT 6
140#define NOOFCOLS_MASK 0x000000C0
141#define CHANSIZE_SHIFT 8
142#define CHANSIZE_MASK 0x00000100
143#define BURSTLENGTH_SHIFT 9
144#define BURSTLENGTH_MASK 0x00000200
145#define MC_VM_AGP_TOP 0x2028
146#define MC_VM_AGP_BOT 0x202C
147#define MC_VM_AGP_BASE 0x2030
148#define MC_VM_FB_LOCATION 0x2024
149#define MC_VM_MB_L1_TLB0_CNTL 0x2234
150#define MC_VM_MB_L1_TLB1_CNTL 0x2238
151#define MC_VM_MB_L1_TLB2_CNTL 0x223C
152#define MC_VM_MB_L1_TLB3_CNTL 0x2240
153#define ENABLE_L1_TLB (1 << 0)
154#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
155#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
156#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
157#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
158#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
159#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
160#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
161#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
162#define MC_VM_MD_L1_TLB0_CNTL 0x2654
163#define MC_VM_MD_L1_TLB1_CNTL 0x2658
164#define MC_VM_MD_L1_TLB2_CNTL 0x265C
165#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
166#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
167#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
168
169#define PA_CL_ENHANCE 0x8A14
170#define CLIP_VTX_REORDER_ENA (1 << 0)
171#define NUM_CLIP_SEQ(x) ((x) << 1)
172#define PA_SC_AA_CONFIG 0x28C04
173#define PA_SC_CLIPRECT_RULE 0x2820C
174#define PA_SC_EDGERULE 0x28230
175#define PA_SC_FIFO_SIZE 0x8BCC
176#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
177#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
178#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
179#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0)
180#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16)
181#define PA_SC_LINE_STIPPLE 0x28A0C
182#define PA_SC_LINE_STIPPLE_STATE 0x8B10
183#define PA_SC_MODE_CNTL 0x28A4C
184#define PA_SC_MULTI_CHIP_CNTL 0x8B20
185#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
186
187#define SCRATCH_REG0 0x8500
188#define SCRATCH_REG1 0x8504
189#define SCRATCH_REG2 0x8508
190#define SCRATCH_REG3 0x850C
191#define SCRATCH_REG4 0x8510
192#define SCRATCH_REG5 0x8514
193#define SCRATCH_REG6 0x8518
194#define SCRATCH_REG7 0x851C
195#define SCRATCH_UMSK 0x8540
196#define SCRATCH_ADDR 0x8544
197
198#define SMX_DC_CTL0 0xA020
199#define USE_HASH_FUNCTION (1 << 0)
200#define CACHE_DEPTH(x) ((x) << 1)
201#define FLUSH_ALL_ON_EVENT (1 << 10)
202#define STALL_ON_EVENT (1 << 11)
203#define SMX_EVENT_CTL 0xA02C
204#define ES_FLUSH_CTL(x) ((x) << 0)
205#define GS_FLUSH_CTL(x) ((x) << 3)
206#define ACK_FLUSH_CTL(x) ((x) << 6)
207#define SYNC_FLUSH_CTL (1 << 8)
208
209#define SPI_CONFIG_CNTL 0x9100
210#define GPR_WRITE_PRIORITY(x) ((x) << 0)
211#define DISABLE_INTERP_1 (1 << 5)
212#define SPI_CONFIG_CNTL_1 0x913C
213#define VTX_DONE_DELAY(x) ((x) << 0)
214#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
215#define SPI_INPUT_Z 0x286D8
216#define SPI_PS_IN_CONTROL_0 0x286CC
217#define NUM_INTERP(x) ((x)<<0)
218#define POSITION_ENA (1<<8)
219#define POSITION_CENTROID (1<<9)
220#define POSITION_ADDR(x) ((x)<<10)
221#define PARAM_GEN(x) ((x)<<15)
222#define PARAM_GEN_ADDR(x) ((x)<<19)
223#define BARYC_SAMPLE_CNTL(x) ((x)<<26)
224#define PERSP_GRADIENT_ENA (1<<28)
225#define LINEAR_GRADIENT_ENA (1<<29)
226#define POSITION_SAMPLE (1<<30)
227#define BARYC_AT_SAMPLE_ENA (1<<31)
228
229#define SQ_CONFIG 0x8C00
230#define VC_ENABLE (1 << 0)
231#define EXPORT_SRC_C (1 << 1)
232#define DX9_CONSTS (1 << 2)
233#define ALU_INST_PREFER_VECTOR (1 << 3)
234#define DX10_CLAMP (1 << 4)
235#define CLAUSE_SEQ_PRIO(x) ((x) << 8)
236#define PS_PRIO(x) ((x) << 24)
237#define VS_PRIO(x) ((x) << 26)
238#define GS_PRIO(x) ((x) << 28)
239#define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0
240#define SIMDA_RING0(x) ((x)<<0)
241#define SIMDA_RING1(x) ((x)<<8)
242#define SIMDB_RING0(x) ((x)<<16)
243#define SIMDB_RING1(x) ((x)<<24)
244#define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4
245#define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8
246#define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC
247#define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0
248#define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4
249#define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8
250#define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC
251#define ES_PRIO(x) ((x) << 30)
252#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
253#define NUM_PS_GPRS(x) ((x) << 0)
254#define NUM_VS_GPRS(x) ((x) << 16)
255#define DYN_GPR_ENABLE (1 << 27)
256#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
257#define SQ_GPR_RESOURCE_MGMT_2 0x8C08
258#define NUM_GS_GPRS(x) ((x) << 0)
259#define NUM_ES_GPRS(x) ((x) << 16)
260#define SQ_MS_FIFO_SIZES 0x8CF0
261#define CACHE_FIFO_SIZE(x) ((x) << 0)
262#define FETCH_FIFO_HIWATER(x) ((x) << 8)
263#define DONE_FIFO_HIWATER(x) ((x) << 16)
264#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
265#define SQ_STACK_RESOURCE_MGMT_1 0x8C10
266#define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
267#define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
268#define SQ_STACK_RESOURCE_MGMT_2 0x8C14
269#define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
270#define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
271#define SQ_THREAD_RESOURCE_MGMT 0x8C0C
272#define NUM_PS_THREADS(x) ((x) << 0)
273#define NUM_VS_THREADS(x) ((x) << 8)
274#define NUM_GS_THREADS(x) ((x) << 16)
275#define NUM_ES_THREADS(x) ((x) << 24)
276
277#define SX_DEBUG_1 0x9058
278#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
279#define SX_EXPORT_BUFFER_SIZES 0x900C
280#define COLOR_BUFFER_SIZE(x) ((x) << 0)
281#define POSITION_BUFFER_SIZE(x) ((x) << 8)
282#define SMX_BUFFER_SIZE(x) ((x) << 16)
283#define SX_MISC 0x28350
284
285#define TA_CNTL_AUX 0x9508
286#define DISABLE_CUBE_WRAP (1 << 0)
287#define DISABLE_CUBE_ANISO (1 << 1)
288#define SYNC_GRADIENT (1 << 24)
289#define SYNC_WALKER (1 << 25)
290#define SYNC_ALIGNER (1 << 26)
291#define BILINEAR_PRECISION_6_BIT (0 << 31)
292#define BILINEAR_PRECISION_8_BIT (1 << 31)
293
294#define TCP_CNTL 0x9610
295
296#define VGT_CACHE_INVALIDATION 0x88C4
297#define CACHE_INVALIDATION(x) ((x)<<0)
298#define VC_ONLY 0
299#define TC_ONLY 1
300#define VC_AND_TC 2
301#define AUTO_INVLD_EN(x) ((x) << 6)
302#define NO_AUTO 0
303#define ES_AUTO 1
304#define GS_AUTO 2
305#define ES_AND_GS_AUTO 3
306#define VGT_ES_PER_GS 0x88CC
307#define VGT_GS_PER_ES 0x88C8
308#define VGT_GS_PER_VS 0x88E8
309#define VGT_GS_VERTEX_REUSE 0x88D4
310#define VGT_NUM_INSTANCES 0x8974
311#define VGT_OUT_DEALLOC_CNTL 0x28C5C
312#define DEALLOC_DIST_MASK 0x0000007F
313#define VGT_STRMOUT_EN 0x28AB0
314#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
315#define VTX_REUSE_DEPTH_MASK 0x000000FF
316
317#define VM_CONTEXT0_CNTL 0x1410
318#define ENABLE_CONTEXT (1 << 0)
319#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
320#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
321#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
322#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
323#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
324#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
325#define VM_L2_CNTL 0x1400
326#define ENABLE_L2_CACHE (1 << 0)
327#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
328#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
329#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
330#define VM_L2_CNTL2 0x1404
331#define INVALIDATE_ALL_L1_TLBS (1 << 0)
332#define INVALIDATE_L2_CACHE (1 << 1)
333#define VM_L2_CNTL3 0x1408
334#define BANK_SELECT(x) ((x) << 0)
335#define CACHE_UPDATE_MODE(x) ((x) << 6)
336#define VM_L2_STATUS 0x140C
337#define L2_BUSY (1 << 0)
338
339#define WAIT_UNTIL 0x8040
340
341#endif
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index c2b0d710d10f..87c06252d464 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -44,6 +44,39 @@
44 44
45static int ttm_bo_setup_vm(struct ttm_buffer_object *bo); 45static int ttm_bo_setup_vm(struct ttm_buffer_object *bo);
46static int ttm_bo_swapout(struct ttm_mem_shrink *shrink); 46static int ttm_bo_swapout(struct ttm_mem_shrink *shrink);
47static void ttm_bo_global_kobj_release(struct kobject *kobj);
48
49static struct attribute ttm_bo_count = {
50 .name = "bo_count",
51 .mode = S_IRUGO
52};
53
54static ssize_t ttm_bo_global_show(struct kobject *kobj,
55 struct attribute *attr,
56 char *buffer)
57{
58 struct ttm_bo_global *glob =
59 container_of(kobj, struct ttm_bo_global, kobj);
60
61 return snprintf(buffer, PAGE_SIZE, "%lu\n",
62 (unsigned long) atomic_read(&glob->bo_count));
63}
64
65static struct attribute *ttm_bo_global_attrs[] = {
66 &ttm_bo_count,
67 NULL
68};
69
70static struct sysfs_ops ttm_bo_global_ops = {
71 .show = &ttm_bo_global_show
72};
73
74static struct kobj_type ttm_bo_glob_kobj_type = {
75 .release = &ttm_bo_global_kobj_release,
76 .sysfs_ops = &ttm_bo_global_ops,
77 .default_attrs = ttm_bo_global_attrs
78};
79
47 80
48static inline uint32_t ttm_bo_type_flags(unsigned type) 81static inline uint32_t ttm_bo_type_flags(unsigned type)
49{ 82{
@@ -66,10 +99,11 @@ static void ttm_bo_release_list(struct kref *list_kref)
66 99
67 if (bo->ttm) 100 if (bo->ttm)
68 ttm_tt_destroy(bo->ttm); 101 ttm_tt_destroy(bo->ttm);
102 atomic_dec(&bo->glob->bo_count);
69 if (bo->destroy) 103 if (bo->destroy)
70 bo->destroy(bo); 104 bo->destroy(bo);
71 else { 105 else {
72 ttm_mem_global_free(bdev->mem_glob, bo->acc_size, false); 106 ttm_mem_global_free(bdev->glob->mem_glob, bo->acc_size);
73 kfree(bo); 107 kfree(bo);
74 } 108 }
75} 109}
@@ -106,7 +140,7 @@ static void ttm_bo_add_to_lru(struct ttm_buffer_object *bo)
106 kref_get(&bo->list_kref); 140 kref_get(&bo->list_kref);
107 141
108 if (bo->ttm != NULL) { 142 if (bo->ttm != NULL) {
109 list_add_tail(&bo->swap, &bdev->swap_lru); 143 list_add_tail(&bo->swap, &bo->glob->swap_lru);
110 kref_get(&bo->list_kref); 144 kref_get(&bo->list_kref);
111 } 145 }
112 } 146 }
@@ -141,7 +175,7 @@ int ttm_bo_reserve_locked(struct ttm_buffer_object *bo,
141 bool interruptible, 175 bool interruptible,
142 bool no_wait, bool use_sequence, uint32_t sequence) 176 bool no_wait, bool use_sequence, uint32_t sequence)
143{ 177{
144 struct ttm_bo_device *bdev = bo->bdev; 178 struct ttm_bo_global *glob = bo->glob;
145 int ret; 179 int ret;
146 180
147 while (unlikely(atomic_cmpxchg(&bo->reserved, 0, 1) != 0)) { 181 while (unlikely(atomic_cmpxchg(&bo->reserved, 0, 1) != 0)) {
@@ -153,9 +187,9 @@ int ttm_bo_reserve_locked(struct ttm_buffer_object *bo,
153 if (no_wait) 187 if (no_wait)
154 return -EBUSY; 188 return -EBUSY;
155 189
156 spin_unlock(&bdev->lru_lock); 190 spin_unlock(&glob->lru_lock);
157 ret = ttm_bo_wait_unreserved(bo, interruptible); 191 ret = ttm_bo_wait_unreserved(bo, interruptible);
158 spin_lock(&bdev->lru_lock); 192 spin_lock(&glob->lru_lock);
159 193
160 if (unlikely(ret)) 194 if (unlikely(ret))
161 return ret; 195 return ret;
@@ -181,16 +215,16 @@ int ttm_bo_reserve(struct ttm_buffer_object *bo,
181 bool interruptible, 215 bool interruptible,
182 bool no_wait, bool use_sequence, uint32_t sequence) 216 bool no_wait, bool use_sequence, uint32_t sequence)
183{ 217{
184 struct ttm_bo_device *bdev = bo->bdev; 218 struct ttm_bo_global *glob = bo->glob;
185 int put_count = 0; 219 int put_count = 0;
186 int ret; 220 int ret;
187 221
188 spin_lock(&bdev->lru_lock); 222 spin_lock(&glob->lru_lock);
189 ret = ttm_bo_reserve_locked(bo, interruptible, no_wait, use_sequence, 223 ret = ttm_bo_reserve_locked(bo, interruptible, no_wait, use_sequence,
190 sequence); 224 sequence);
191 if (likely(ret == 0)) 225 if (likely(ret == 0))
192 put_count = ttm_bo_del_from_lru(bo); 226 put_count = ttm_bo_del_from_lru(bo);
193 spin_unlock(&bdev->lru_lock); 227 spin_unlock(&glob->lru_lock);
194 228
195 while (put_count--) 229 while (put_count--)
196 kref_put(&bo->list_kref, ttm_bo_ref_bug); 230 kref_put(&bo->list_kref, ttm_bo_ref_bug);
@@ -200,13 +234,13 @@ int ttm_bo_reserve(struct ttm_buffer_object *bo,
200 234
201void ttm_bo_unreserve(struct ttm_buffer_object *bo) 235void ttm_bo_unreserve(struct ttm_buffer_object *bo)
202{ 236{
203 struct ttm_bo_device *bdev = bo->bdev; 237 struct ttm_bo_global *glob = bo->glob;
204 238
205 spin_lock(&bdev->lru_lock); 239 spin_lock(&glob->lru_lock);
206 ttm_bo_add_to_lru(bo); 240 ttm_bo_add_to_lru(bo);
207 atomic_set(&bo->reserved, 0); 241 atomic_set(&bo->reserved, 0);
208 wake_up_all(&bo->event_queue); 242 wake_up_all(&bo->event_queue);
209 spin_unlock(&bdev->lru_lock); 243 spin_unlock(&glob->lru_lock);
210} 244}
211EXPORT_SYMBOL(ttm_bo_unreserve); 245EXPORT_SYMBOL(ttm_bo_unreserve);
212 246
@@ -217,6 +251,7 @@ EXPORT_SYMBOL(ttm_bo_unreserve);
217static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc) 251static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc)
218{ 252{
219 struct ttm_bo_device *bdev = bo->bdev; 253 struct ttm_bo_device *bdev = bo->bdev;
254 struct ttm_bo_global *glob = bo->glob;
220 int ret = 0; 255 int ret = 0;
221 uint32_t page_flags = 0; 256 uint32_t page_flags = 0;
222 257
@@ -232,14 +267,14 @@ static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc)
232 page_flags |= TTM_PAGE_FLAG_ZERO_ALLOC; 267 page_flags |= TTM_PAGE_FLAG_ZERO_ALLOC;
233 case ttm_bo_type_kernel: 268 case ttm_bo_type_kernel:
234 bo->ttm = ttm_tt_create(bdev, bo->num_pages << PAGE_SHIFT, 269 bo->ttm = ttm_tt_create(bdev, bo->num_pages << PAGE_SHIFT,
235 page_flags, bdev->dummy_read_page); 270 page_flags, glob->dummy_read_page);
236 if (unlikely(bo->ttm == NULL)) 271 if (unlikely(bo->ttm == NULL))
237 ret = -ENOMEM; 272 ret = -ENOMEM;
238 break; 273 break;
239 case ttm_bo_type_user: 274 case ttm_bo_type_user:
240 bo->ttm = ttm_tt_create(bdev, bo->num_pages << PAGE_SHIFT, 275 bo->ttm = ttm_tt_create(bdev, bo->num_pages << PAGE_SHIFT,
241 page_flags | TTM_PAGE_FLAG_USER, 276 page_flags | TTM_PAGE_FLAG_USER,
242 bdev->dummy_read_page); 277 glob->dummy_read_page);
243 if (unlikely(bo->ttm == NULL)) 278 if (unlikely(bo->ttm == NULL))
244 ret = -ENOMEM; 279 ret = -ENOMEM;
245 break; 280 break;
@@ -360,6 +395,7 @@ out_err:
360static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) 395static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
361{ 396{
362 struct ttm_bo_device *bdev = bo->bdev; 397 struct ttm_bo_device *bdev = bo->bdev;
398 struct ttm_bo_global *glob = bo->glob;
363 struct ttm_bo_driver *driver = bdev->driver; 399 struct ttm_bo_driver *driver = bdev->driver;
364 int ret; 400 int ret;
365 401
@@ -371,7 +407,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
371 407
372 spin_unlock(&bo->lock); 408 spin_unlock(&bo->lock);
373 409
374 spin_lock(&bdev->lru_lock); 410 spin_lock(&glob->lru_lock);
375 ret = ttm_bo_reserve_locked(bo, false, false, false, 0); 411 ret = ttm_bo_reserve_locked(bo, false, false, false, 0);
376 BUG_ON(ret); 412 BUG_ON(ret);
377 if (bo->ttm) 413 if (bo->ttm)
@@ -386,7 +422,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
386 bo->mem.mm_node = NULL; 422 bo->mem.mm_node = NULL;
387 } 423 }
388 put_count = ttm_bo_del_from_lru(bo); 424 put_count = ttm_bo_del_from_lru(bo);
389 spin_unlock(&bdev->lru_lock); 425 spin_unlock(&glob->lru_lock);
390 426
391 atomic_set(&bo->reserved, 0); 427 atomic_set(&bo->reserved, 0);
392 428
@@ -396,14 +432,14 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
396 return 0; 432 return 0;
397 } 433 }
398 434
399 spin_lock(&bdev->lru_lock); 435 spin_lock(&glob->lru_lock);
400 if (list_empty(&bo->ddestroy)) { 436 if (list_empty(&bo->ddestroy)) {
401 void *sync_obj = bo->sync_obj; 437 void *sync_obj = bo->sync_obj;
402 void *sync_obj_arg = bo->sync_obj_arg; 438 void *sync_obj_arg = bo->sync_obj_arg;
403 439
404 kref_get(&bo->list_kref); 440 kref_get(&bo->list_kref);
405 list_add_tail(&bo->ddestroy, &bdev->ddestroy); 441 list_add_tail(&bo->ddestroy, &bdev->ddestroy);
406 spin_unlock(&bdev->lru_lock); 442 spin_unlock(&glob->lru_lock);
407 spin_unlock(&bo->lock); 443 spin_unlock(&bo->lock);
408 444
409 if (sync_obj) 445 if (sync_obj)
@@ -413,7 +449,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
413 ret = 0; 449 ret = 0;
414 450
415 } else { 451 } else {
416 spin_unlock(&bdev->lru_lock); 452 spin_unlock(&glob->lru_lock);
417 spin_unlock(&bo->lock); 453 spin_unlock(&bo->lock);
418 ret = -EBUSY; 454 ret = -EBUSY;
419 } 455 }
@@ -428,11 +464,12 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
428 464
429static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) 465static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all)
430{ 466{
467 struct ttm_bo_global *glob = bdev->glob;
431 struct ttm_buffer_object *entry, *nentry; 468 struct ttm_buffer_object *entry, *nentry;
432 struct list_head *list, *next; 469 struct list_head *list, *next;
433 int ret; 470 int ret;
434 471
435 spin_lock(&bdev->lru_lock); 472 spin_lock(&glob->lru_lock);
436 list_for_each_safe(list, next, &bdev->ddestroy) { 473 list_for_each_safe(list, next, &bdev->ddestroy) {
437 entry = list_entry(list, struct ttm_buffer_object, ddestroy); 474 entry = list_entry(list, struct ttm_buffer_object, ddestroy);
438 nentry = NULL; 475 nentry = NULL;
@@ -449,16 +486,16 @@ static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all)
449 } 486 }
450 kref_get(&entry->list_kref); 487 kref_get(&entry->list_kref);
451 488
452 spin_unlock(&bdev->lru_lock); 489 spin_unlock(&glob->lru_lock);
453 ret = ttm_bo_cleanup_refs(entry, remove_all); 490 ret = ttm_bo_cleanup_refs(entry, remove_all);
454 kref_put(&entry->list_kref, ttm_bo_release_list); 491 kref_put(&entry->list_kref, ttm_bo_release_list);
455 492
456 spin_lock(&bdev->lru_lock); 493 spin_lock(&glob->lru_lock);
457 if (nentry) { 494 if (nentry) {
458 bool next_onlist = !list_empty(next); 495 bool next_onlist = !list_empty(next);
459 spin_unlock(&bdev->lru_lock); 496 spin_unlock(&glob->lru_lock);
460 kref_put(&nentry->list_kref, ttm_bo_release_list); 497 kref_put(&nentry->list_kref, ttm_bo_release_list);
461 spin_lock(&bdev->lru_lock); 498 spin_lock(&glob->lru_lock);
462 /* 499 /*
463 * Someone might have raced us and removed the 500 * Someone might have raced us and removed the
464 * next entry from the list. We don't bother restarting 501 * next entry from the list. We don't bother restarting
@@ -472,7 +509,7 @@ static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all)
472 break; 509 break;
473 } 510 }
474 ret = !list_empty(&bdev->ddestroy); 511 ret = !list_empty(&bdev->ddestroy);
475 spin_unlock(&bdev->lru_lock); 512 spin_unlock(&glob->lru_lock);
476 513
477 return ret; 514 return ret;
478} 515}
@@ -522,6 +559,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, unsigned mem_type,
522{ 559{
523 int ret = 0; 560 int ret = 0;
524 struct ttm_bo_device *bdev = bo->bdev; 561 struct ttm_bo_device *bdev = bo->bdev;
562 struct ttm_bo_global *glob = bo->glob;
525 struct ttm_mem_reg evict_mem; 563 struct ttm_mem_reg evict_mem;
526 uint32_t proposed_placement; 564 uint32_t proposed_placement;
527 565
@@ -570,12 +608,12 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, unsigned mem_type,
570 goto out; 608 goto out;
571 } 609 }
572 610
573 spin_lock(&bdev->lru_lock); 611 spin_lock(&glob->lru_lock);
574 if (evict_mem.mm_node) { 612 if (evict_mem.mm_node) {
575 drm_mm_put_block(evict_mem.mm_node); 613 drm_mm_put_block(evict_mem.mm_node);
576 evict_mem.mm_node = NULL; 614 evict_mem.mm_node = NULL;
577 } 615 }
578 spin_unlock(&bdev->lru_lock); 616 spin_unlock(&glob->lru_lock);
579 bo->evicted = true; 617 bo->evicted = true;
580out: 618out:
581 return ret; 619 return ret;
@@ -590,6 +628,7 @@ static int ttm_bo_mem_force_space(struct ttm_bo_device *bdev,
590 uint32_t mem_type, 628 uint32_t mem_type,
591 bool interruptible, bool no_wait) 629 bool interruptible, bool no_wait)
592{ 630{
631 struct ttm_bo_global *glob = bdev->glob;
593 struct drm_mm_node *node; 632 struct drm_mm_node *node;
594 struct ttm_buffer_object *entry; 633 struct ttm_buffer_object *entry;
595 struct ttm_mem_type_manager *man = &bdev->man[mem_type]; 634 struct ttm_mem_type_manager *man = &bdev->man[mem_type];
@@ -603,7 +642,7 @@ retry_pre_get:
603 if (unlikely(ret != 0)) 642 if (unlikely(ret != 0))
604 return ret; 643 return ret;
605 644
606 spin_lock(&bdev->lru_lock); 645 spin_lock(&glob->lru_lock);
607 do { 646 do {
608 node = drm_mm_search_free(&man->manager, num_pages, 647 node = drm_mm_search_free(&man->manager, num_pages,
609 mem->page_alignment, 1); 648 mem->page_alignment, 1);
@@ -624,7 +663,7 @@ retry_pre_get:
624 if (likely(ret == 0)) 663 if (likely(ret == 0))
625 put_count = ttm_bo_del_from_lru(entry); 664 put_count = ttm_bo_del_from_lru(entry);
626 665
627 spin_unlock(&bdev->lru_lock); 666 spin_unlock(&glob->lru_lock);
628 667
629 if (unlikely(ret != 0)) 668 if (unlikely(ret != 0))
630 return ret; 669 return ret;
@@ -640,21 +679,21 @@ retry_pre_get:
640 if (ret) 679 if (ret)
641 return ret; 680 return ret;
642 681
643 spin_lock(&bdev->lru_lock); 682 spin_lock(&glob->lru_lock);
644 } while (1); 683 } while (1);
645 684
646 if (!node) { 685 if (!node) {
647 spin_unlock(&bdev->lru_lock); 686 spin_unlock(&glob->lru_lock);
648 return -ENOMEM; 687 return -ENOMEM;
649 } 688 }
650 689
651 node = drm_mm_get_block_atomic(node, num_pages, mem->page_alignment); 690 node = drm_mm_get_block_atomic(node, num_pages, mem->page_alignment);
652 if (unlikely(!node)) { 691 if (unlikely(!node)) {
653 spin_unlock(&bdev->lru_lock); 692 spin_unlock(&glob->lru_lock);
654 goto retry_pre_get; 693 goto retry_pre_get;
655 } 694 }
656 695
657 spin_unlock(&bdev->lru_lock); 696 spin_unlock(&glob->lru_lock);
658 mem->mm_node = node; 697 mem->mm_node = node;
659 mem->mem_type = mem_type; 698 mem->mem_type = mem_type;
660 return 0; 699 return 0;
@@ -723,6 +762,7 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
723 bool interruptible, bool no_wait) 762 bool interruptible, bool no_wait)
724{ 763{
725 struct ttm_bo_device *bdev = bo->bdev; 764 struct ttm_bo_device *bdev = bo->bdev;
765 struct ttm_bo_global *glob = bo->glob;
726 struct ttm_mem_type_manager *man; 766 struct ttm_mem_type_manager *man;
727 767
728 uint32_t num_prios = bdev->driver->num_mem_type_prio; 768 uint32_t num_prios = bdev->driver->num_mem_type_prio;
@@ -762,20 +802,20 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
762 if (unlikely(ret)) 802 if (unlikely(ret))
763 return ret; 803 return ret;
764 804
765 spin_lock(&bdev->lru_lock); 805 spin_lock(&glob->lru_lock);
766 node = drm_mm_search_free(&man->manager, 806 node = drm_mm_search_free(&man->manager,
767 mem->num_pages, 807 mem->num_pages,
768 mem->page_alignment, 808 mem->page_alignment,
769 1); 809 1);
770 if (unlikely(!node)) { 810 if (unlikely(!node)) {
771 spin_unlock(&bdev->lru_lock); 811 spin_unlock(&glob->lru_lock);
772 break; 812 break;
773 } 813 }
774 node = drm_mm_get_block_atomic(node, 814 node = drm_mm_get_block_atomic(node,
775 mem->num_pages, 815 mem->num_pages,
776 mem-> 816 mem->
777 page_alignment); 817 page_alignment);
778 spin_unlock(&bdev->lru_lock); 818 spin_unlock(&glob->lru_lock);
779 } while (!node); 819 } while (!node);
780 } 820 }
781 if (node) 821 if (node)
@@ -848,7 +888,7 @@ int ttm_bo_move_buffer(struct ttm_buffer_object *bo,
848 uint32_t proposed_placement, 888 uint32_t proposed_placement,
849 bool interruptible, bool no_wait) 889 bool interruptible, bool no_wait)
850{ 890{
851 struct ttm_bo_device *bdev = bo->bdev; 891 struct ttm_bo_global *glob = bo->glob;
852 int ret = 0; 892 int ret = 0;
853 struct ttm_mem_reg mem; 893 struct ttm_mem_reg mem;
854 894
@@ -884,9 +924,9 @@ int ttm_bo_move_buffer(struct ttm_buffer_object *bo,
884 924
885out_unlock: 925out_unlock:
886 if (ret && mem.mm_node) { 926 if (ret && mem.mm_node) {
887 spin_lock(&bdev->lru_lock); 927 spin_lock(&glob->lru_lock);
888 drm_mm_put_block(mem.mm_node); 928 drm_mm_put_block(mem.mm_node);
889 spin_unlock(&bdev->lru_lock); 929 spin_unlock(&glob->lru_lock);
890 } 930 }
891 return ret; 931 return ret;
892} 932}
@@ -1022,6 +1062,7 @@ int ttm_buffer_object_init(struct ttm_bo_device *bdev,
1022 INIT_LIST_HEAD(&bo->ddestroy); 1062 INIT_LIST_HEAD(&bo->ddestroy);
1023 INIT_LIST_HEAD(&bo->swap); 1063 INIT_LIST_HEAD(&bo->swap);
1024 bo->bdev = bdev; 1064 bo->bdev = bdev;
1065 bo->glob = bdev->glob;
1025 bo->type = type; 1066 bo->type = type;
1026 bo->num_pages = num_pages; 1067 bo->num_pages = num_pages;
1027 bo->mem.mem_type = TTM_PL_SYSTEM; 1068 bo->mem.mem_type = TTM_PL_SYSTEM;
@@ -1034,6 +1075,7 @@ int ttm_buffer_object_init(struct ttm_bo_device *bdev,
1034 bo->seq_valid = false; 1075 bo->seq_valid = false;
1035 bo->persistant_swap_storage = persistant_swap_storage; 1076 bo->persistant_swap_storage = persistant_swap_storage;
1036 bo->acc_size = acc_size; 1077 bo->acc_size = acc_size;
1078 atomic_inc(&bo->glob->bo_count);
1037 1079
1038 ret = ttm_bo_check_placement(bo, flags, 0ULL); 1080 ret = ttm_bo_check_placement(bo, flags, 0ULL);
1039 if (unlikely(ret != 0)) 1081 if (unlikely(ret != 0))
@@ -1072,13 +1114,13 @@ out_err:
1072} 1114}
1073EXPORT_SYMBOL(ttm_buffer_object_init); 1115EXPORT_SYMBOL(ttm_buffer_object_init);
1074 1116
1075static inline size_t ttm_bo_size(struct ttm_bo_device *bdev, 1117static inline size_t ttm_bo_size(struct ttm_bo_global *glob,
1076 unsigned long num_pages) 1118 unsigned long num_pages)
1077{ 1119{
1078 size_t page_array_size = (num_pages * sizeof(void *) + PAGE_SIZE - 1) & 1120 size_t page_array_size = (num_pages * sizeof(void *) + PAGE_SIZE - 1) &
1079 PAGE_MASK; 1121 PAGE_MASK;
1080 1122
1081 return bdev->ttm_bo_size + 2 * page_array_size; 1123 return glob->ttm_bo_size + 2 * page_array_size;
1082} 1124}
1083 1125
1084int ttm_buffer_object_create(struct ttm_bo_device *bdev, 1126int ttm_buffer_object_create(struct ttm_bo_device *bdev,
@@ -1093,18 +1135,18 @@ int ttm_buffer_object_create(struct ttm_bo_device *bdev,
1093{ 1135{
1094 struct ttm_buffer_object *bo; 1136 struct ttm_buffer_object *bo;
1095 int ret; 1137 int ret;
1096 struct ttm_mem_global *mem_glob = bdev->mem_glob; 1138 struct ttm_mem_global *mem_glob = bdev->glob->mem_glob;
1097 1139
1098 size_t acc_size = 1140 size_t acc_size =
1099 ttm_bo_size(bdev, (size + PAGE_SIZE - 1) >> PAGE_SHIFT); 1141 ttm_bo_size(bdev->glob, (size + PAGE_SIZE - 1) >> PAGE_SHIFT);
1100 ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false, false); 1142 ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false);
1101 if (unlikely(ret != 0)) 1143 if (unlikely(ret != 0))
1102 return ret; 1144 return ret;
1103 1145
1104 bo = kzalloc(sizeof(*bo), GFP_KERNEL); 1146 bo = kzalloc(sizeof(*bo), GFP_KERNEL);
1105 1147
1106 if (unlikely(bo == NULL)) { 1148 if (unlikely(bo == NULL)) {
1107 ttm_mem_global_free(mem_glob, acc_size, false); 1149 ttm_mem_global_free(mem_glob, acc_size);
1108 return -ENOMEM; 1150 return -ENOMEM;
1109 } 1151 }
1110 1152
@@ -1150,6 +1192,7 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev,
1150 struct list_head *head, 1192 struct list_head *head,
1151 unsigned mem_type, bool allow_errors) 1193 unsigned mem_type, bool allow_errors)
1152{ 1194{
1195 struct ttm_bo_global *glob = bdev->glob;
1153 struct ttm_buffer_object *entry; 1196 struct ttm_buffer_object *entry;
1154 int ret; 1197 int ret;
1155 int put_count; 1198 int put_count;
@@ -1158,30 +1201,31 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev,
1158 * Can't use standard list traversal since we're unlocking. 1201 * Can't use standard list traversal since we're unlocking.
1159 */ 1202 */
1160 1203
1161 spin_lock(&bdev->lru_lock); 1204 spin_lock(&glob->lru_lock);
1162 1205
1163 while (!list_empty(head)) { 1206 while (!list_empty(head)) {
1164 entry = list_first_entry(head, struct ttm_buffer_object, lru); 1207 entry = list_first_entry(head, struct ttm_buffer_object, lru);
1165 kref_get(&entry->list_kref); 1208 kref_get(&entry->list_kref);
1166 ret = ttm_bo_reserve_locked(entry, false, false, false, 0); 1209 ret = ttm_bo_reserve_locked(entry, false, false, false, 0);
1167 put_count = ttm_bo_del_from_lru(entry); 1210 put_count = ttm_bo_del_from_lru(entry);
1168 spin_unlock(&bdev->lru_lock); 1211 spin_unlock(&glob->lru_lock);
1169 while (put_count--) 1212 while (put_count--)
1170 kref_put(&entry->list_kref, ttm_bo_ref_bug); 1213 kref_put(&entry->list_kref, ttm_bo_ref_bug);
1171 BUG_ON(ret); 1214 BUG_ON(ret);
1172 ret = ttm_bo_leave_list(entry, mem_type, allow_errors); 1215 ret = ttm_bo_leave_list(entry, mem_type, allow_errors);
1173 ttm_bo_unreserve(entry); 1216 ttm_bo_unreserve(entry);
1174 kref_put(&entry->list_kref, ttm_bo_release_list); 1217 kref_put(&entry->list_kref, ttm_bo_release_list);
1175 spin_lock(&bdev->lru_lock); 1218 spin_lock(&glob->lru_lock);
1176 } 1219 }
1177 1220
1178 spin_unlock(&bdev->lru_lock); 1221 spin_unlock(&glob->lru_lock);
1179 1222
1180 return 0; 1223 return 0;
1181} 1224}
1182 1225
1183int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type) 1226int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type)
1184{ 1227{
1228 struct ttm_bo_global *glob = bdev->glob;
1185 struct ttm_mem_type_manager *man; 1229 struct ttm_mem_type_manager *man;
1186 int ret = -EINVAL; 1230 int ret = -EINVAL;
1187 1231
@@ -1204,13 +1248,13 @@ int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type)
1204 if (mem_type > 0) { 1248 if (mem_type > 0) {
1205 ttm_bo_force_list_clean(bdev, &man->lru, mem_type, false); 1249 ttm_bo_force_list_clean(bdev, &man->lru, mem_type, false);
1206 1250
1207 spin_lock(&bdev->lru_lock); 1251 spin_lock(&glob->lru_lock);
1208 if (drm_mm_clean(&man->manager)) 1252 if (drm_mm_clean(&man->manager))
1209 drm_mm_takedown(&man->manager); 1253 drm_mm_takedown(&man->manager);
1210 else 1254 else
1211 ret = -EBUSY; 1255 ret = -EBUSY;
1212 1256
1213 spin_unlock(&bdev->lru_lock); 1257 spin_unlock(&glob->lru_lock);
1214 } 1258 }
1215 1259
1216 return ret; 1260 return ret;
@@ -1284,11 +1328,82 @@ int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned type,
1284} 1328}
1285EXPORT_SYMBOL(ttm_bo_init_mm); 1329EXPORT_SYMBOL(ttm_bo_init_mm);
1286 1330
1331static void ttm_bo_global_kobj_release(struct kobject *kobj)
1332{
1333 struct ttm_bo_global *glob =
1334 container_of(kobj, struct ttm_bo_global, kobj);
1335
1336 ttm_mem_unregister_shrink(glob->mem_glob, &glob->shrink);
1337 __free_page(glob->dummy_read_page);
1338 kfree(glob);
1339}
1340
1341void ttm_bo_global_release(struct ttm_global_reference *ref)
1342{
1343 struct ttm_bo_global *glob = ref->object;
1344
1345 kobject_del(&glob->kobj);
1346 kobject_put(&glob->kobj);
1347}
1348EXPORT_SYMBOL(ttm_bo_global_release);
1349
1350int ttm_bo_global_init(struct ttm_global_reference *ref)
1351{
1352 struct ttm_bo_global_ref *bo_ref =
1353 container_of(ref, struct ttm_bo_global_ref, ref);
1354 struct ttm_bo_global *glob = ref->object;
1355 int ret;
1356
1357 mutex_init(&glob->device_list_mutex);
1358 spin_lock_init(&glob->lru_lock);
1359 glob->mem_glob = bo_ref->mem_glob;
1360 glob->dummy_read_page = alloc_page(__GFP_ZERO | GFP_DMA32);
1361
1362 if (unlikely(glob->dummy_read_page == NULL)) {
1363 ret = -ENOMEM;
1364 goto out_no_drp;
1365 }
1366
1367 INIT_LIST_HEAD(&glob->swap_lru);
1368 INIT_LIST_HEAD(&glob->device_list);
1369
1370 ttm_mem_init_shrink(&glob->shrink, ttm_bo_swapout);
1371 ret = ttm_mem_register_shrink(glob->mem_glob, &glob->shrink);
1372 if (unlikely(ret != 0)) {
1373 printk(KERN_ERR TTM_PFX
1374 "Could not register buffer object swapout.\n");
1375 goto out_no_shrink;
1376 }
1377
1378 glob->ttm_bo_extra_size =
1379 ttm_round_pot(sizeof(struct ttm_tt)) +
1380 ttm_round_pot(sizeof(struct ttm_backend));
1381
1382 glob->ttm_bo_size = glob->ttm_bo_extra_size +
1383 ttm_round_pot(sizeof(struct ttm_buffer_object));
1384
1385 atomic_set(&glob->bo_count, 0);
1386
1387 kobject_init(&glob->kobj, &ttm_bo_glob_kobj_type);
1388 ret = kobject_add(&glob->kobj, ttm_get_kobj(), "buffer_objects");
1389 if (unlikely(ret != 0))
1390 kobject_put(&glob->kobj);
1391 return ret;
1392out_no_shrink:
1393 __free_page(glob->dummy_read_page);
1394out_no_drp:
1395 kfree(glob);
1396 return ret;
1397}
1398EXPORT_SYMBOL(ttm_bo_global_init);
1399
1400
1287int ttm_bo_device_release(struct ttm_bo_device *bdev) 1401int ttm_bo_device_release(struct ttm_bo_device *bdev)
1288{ 1402{
1289 int ret = 0; 1403 int ret = 0;
1290 unsigned i = TTM_NUM_MEM_TYPES; 1404 unsigned i = TTM_NUM_MEM_TYPES;
1291 struct ttm_mem_type_manager *man; 1405 struct ttm_mem_type_manager *man;
1406 struct ttm_bo_global *glob = bdev->glob;
1292 1407
1293 while (i--) { 1408 while (i--) {
1294 man = &bdev->man[i]; 1409 man = &bdev->man[i];
@@ -1304,100 +1419,74 @@ int ttm_bo_device_release(struct ttm_bo_device *bdev)
1304 } 1419 }
1305 } 1420 }
1306 1421
1422 mutex_lock(&glob->device_list_mutex);
1423 list_del(&bdev->device_list);
1424 mutex_unlock(&glob->device_list_mutex);
1425
1307 if (!cancel_delayed_work(&bdev->wq)) 1426 if (!cancel_delayed_work(&bdev->wq))
1308 flush_scheduled_work(); 1427 flush_scheduled_work();
1309 1428
1310 while (ttm_bo_delayed_delete(bdev, true)) 1429 while (ttm_bo_delayed_delete(bdev, true))
1311 ; 1430 ;
1312 1431
1313 spin_lock(&bdev->lru_lock); 1432 spin_lock(&glob->lru_lock);
1314 if (list_empty(&bdev->ddestroy)) 1433 if (list_empty(&bdev->ddestroy))
1315 TTM_DEBUG("Delayed destroy list was clean\n"); 1434 TTM_DEBUG("Delayed destroy list was clean\n");
1316 1435
1317 if (list_empty(&bdev->man[0].lru)) 1436 if (list_empty(&bdev->man[0].lru))
1318 TTM_DEBUG("Swap list was clean\n"); 1437 TTM_DEBUG("Swap list was clean\n");
1319 spin_unlock(&bdev->lru_lock); 1438 spin_unlock(&glob->lru_lock);
1320 1439
1321 ttm_mem_unregister_shrink(bdev->mem_glob, &bdev->shrink);
1322 BUG_ON(!drm_mm_clean(&bdev->addr_space_mm)); 1440 BUG_ON(!drm_mm_clean(&bdev->addr_space_mm));
1323 write_lock(&bdev->vm_lock); 1441 write_lock(&bdev->vm_lock);
1324 drm_mm_takedown(&bdev->addr_space_mm); 1442 drm_mm_takedown(&bdev->addr_space_mm);
1325 write_unlock(&bdev->vm_lock); 1443 write_unlock(&bdev->vm_lock);
1326 1444
1327 __free_page(bdev->dummy_read_page);
1328 return ret; 1445 return ret;
1329} 1446}
1330EXPORT_SYMBOL(ttm_bo_device_release); 1447EXPORT_SYMBOL(ttm_bo_device_release);
1331 1448
1332/*
1333 * This function is intended to be called on drm driver load.
1334 * If you decide to call it from firstopen, you must protect the call
1335 * from a potentially racing ttm_bo_driver_finish in lastclose.
1336 * (This may happen on X server restart).
1337 */
1338
1339int ttm_bo_device_init(struct ttm_bo_device *bdev, 1449int ttm_bo_device_init(struct ttm_bo_device *bdev,
1340 struct ttm_mem_global *mem_glob, 1450 struct ttm_bo_global *glob,
1341 struct ttm_bo_driver *driver, uint64_t file_page_offset, 1451 struct ttm_bo_driver *driver,
1452 uint64_t file_page_offset,
1342 bool need_dma32) 1453 bool need_dma32)
1343{ 1454{
1344 int ret = -EINVAL; 1455 int ret = -EINVAL;
1345 1456
1346 bdev->dummy_read_page = NULL;
1347 rwlock_init(&bdev->vm_lock); 1457 rwlock_init(&bdev->vm_lock);
1348 spin_lock_init(&bdev->lru_lock);
1349
1350 bdev->driver = driver; 1458 bdev->driver = driver;
1351 bdev->mem_glob = mem_glob;
1352 1459
1353 memset(bdev->man, 0, sizeof(bdev->man)); 1460 memset(bdev->man, 0, sizeof(bdev->man));
1354 1461
1355 bdev->dummy_read_page = alloc_page(__GFP_ZERO | GFP_DMA32);
1356 if (unlikely(bdev->dummy_read_page == NULL)) {
1357 ret = -ENOMEM;
1358 goto out_err0;
1359 }
1360
1361 /* 1462 /*
1362 * Initialize the system memory buffer type. 1463 * Initialize the system memory buffer type.
1363 * Other types need to be driver / IOCTL initialized. 1464 * Other types need to be driver / IOCTL initialized.
1364 */ 1465 */
1365 ret = ttm_bo_init_mm(bdev, TTM_PL_SYSTEM, 0, 0); 1466 ret = ttm_bo_init_mm(bdev, TTM_PL_SYSTEM, 0, 0);
1366 if (unlikely(ret != 0)) 1467 if (unlikely(ret != 0))
1367 goto out_err1; 1468 goto out_no_sys;
1368 1469
1369 bdev->addr_space_rb = RB_ROOT; 1470 bdev->addr_space_rb = RB_ROOT;
1370 ret = drm_mm_init(&bdev->addr_space_mm, file_page_offset, 0x10000000); 1471 ret = drm_mm_init(&bdev->addr_space_mm, file_page_offset, 0x10000000);
1371 if (unlikely(ret != 0)) 1472 if (unlikely(ret != 0))
1372 goto out_err2; 1473 goto out_no_addr_mm;
1373 1474
1374 INIT_DELAYED_WORK(&bdev->wq, ttm_bo_delayed_workqueue); 1475 INIT_DELAYED_WORK(&bdev->wq, ttm_bo_delayed_workqueue);
1375 bdev->nice_mode = true; 1476 bdev->nice_mode = true;
1376 INIT_LIST_HEAD(&bdev->ddestroy); 1477 INIT_LIST_HEAD(&bdev->ddestroy);
1377 INIT_LIST_HEAD(&bdev->swap_lru);
1378 bdev->dev_mapping = NULL; 1478 bdev->dev_mapping = NULL;
1479 bdev->glob = glob;
1379 bdev->need_dma32 = need_dma32; 1480 bdev->need_dma32 = need_dma32;
1380 ttm_mem_init_shrink(&bdev->shrink, ttm_bo_swapout);
1381 ret = ttm_mem_register_shrink(mem_glob, &bdev->shrink);
1382 if (unlikely(ret != 0)) {
1383 printk(KERN_ERR TTM_PFX
1384 "Could not register buffer object swapout.\n");
1385 goto out_err2;
1386 }
1387 1481
1388 bdev->ttm_bo_extra_size = 1482 mutex_lock(&glob->device_list_mutex);
1389 ttm_round_pot(sizeof(struct ttm_tt)) + 1483 list_add_tail(&bdev->device_list, &glob->device_list);
1390 ttm_round_pot(sizeof(struct ttm_backend)); 1484 mutex_unlock(&glob->device_list_mutex);
1391
1392 bdev->ttm_bo_size = bdev->ttm_bo_extra_size +
1393 ttm_round_pot(sizeof(struct ttm_buffer_object));
1394 1485
1395 return 0; 1486 return 0;
1396out_err2: 1487out_no_addr_mm:
1397 ttm_bo_clean_mm(bdev, 0); 1488 ttm_bo_clean_mm(bdev, 0);
1398out_err1: 1489out_no_sys:
1399 __free_page(bdev->dummy_read_page);
1400out_err0:
1401 return ret; 1490 return ret;
1402} 1491}
1403EXPORT_SYMBOL(ttm_bo_device_init); 1492EXPORT_SYMBOL(ttm_bo_device_init);
@@ -1647,21 +1736,21 @@ void ttm_bo_synccpu_write_release(struct ttm_buffer_object *bo)
1647 1736
1648static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) 1737static int ttm_bo_swapout(struct ttm_mem_shrink *shrink)
1649{ 1738{
1650 struct ttm_bo_device *bdev = 1739 struct ttm_bo_global *glob =
1651 container_of(shrink, struct ttm_bo_device, shrink); 1740 container_of(shrink, struct ttm_bo_global, shrink);
1652 struct ttm_buffer_object *bo; 1741 struct ttm_buffer_object *bo;
1653 int ret = -EBUSY; 1742 int ret = -EBUSY;
1654 int put_count; 1743 int put_count;
1655 uint32_t swap_placement = (TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM); 1744 uint32_t swap_placement = (TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM);
1656 1745
1657 spin_lock(&bdev->lru_lock); 1746 spin_lock(&glob->lru_lock);
1658 while (ret == -EBUSY) { 1747 while (ret == -EBUSY) {
1659 if (unlikely(list_empty(&bdev->swap_lru))) { 1748 if (unlikely(list_empty(&glob->swap_lru))) {
1660 spin_unlock(&bdev->lru_lock); 1749 spin_unlock(&glob->lru_lock);
1661 return -EBUSY; 1750 return -EBUSY;
1662 } 1751 }
1663 1752
1664 bo = list_first_entry(&bdev->swap_lru, 1753 bo = list_first_entry(&glob->swap_lru,
1665 struct ttm_buffer_object, swap); 1754 struct ttm_buffer_object, swap);
1666 kref_get(&bo->list_kref); 1755 kref_get(&bo->list_kref);
1667 1756
@@ -1673,16 +1762,16 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink)
1673 1762
1674 ret = ttm_bo_reserve_locked(bo, false, true, false, 0); 1763 ret = ttm_bo_reserve_locked(bo, false, true, false, 0);
1675 if (unlikely(ret == -EBUSY)) { 1764 if (unlikely(ret == -EBUSY)) {
1676 spin_unlock(&bdev->lru_lock); 1765 spin_unlock(&glob->lru_lock);
1677 ttm_bo_wait_unreserved(bo, false); 1766 ttm_bo_wait_unreserved(bo, false);
1678 kref_put(&bo->list_kref, ttm_bo_release_list); 1767 kref_put(&bo->list_kref, ttm_bo_release_list);
1679 spin_lock(&bdev->lru_lock); 1768 spin_lock(&glob->lru_lock);
1680 } 1769 }
1681 } 1770 }
1682 1771
1683 BUG_ON(ret != 0); 1772 BUG_ON(ret != 0);
1684 put_count = ttm_bo_del_from_lru(bo); 1773 put_count = ttm_bo_del_from_lru(bo);
1685 spin_unlock(&bdev->lru_lock); 1774 spin_unlock(&glob->lru_lock);
1686 1775
1687 while (put_count--) 1776 while (put_count--)
1688 kref_put(&bo->list_kref, ttm_bo_ref_bug); 1777 kref_put(&bo->list_kref, ttm_bo_ref_bug);
@@ -1736,6 +1825,6 @@ out:
1736 1825
1737void ttm_bo_swapout_all(struct ttm_bo_device *bdev) 1826void ttm_bo_swapout_all(struct ttm_bo_device *bdev)
1738{ 1827{
1739 while (ttm_bo_swapout(&bdev->shrink) == 0) 1828 while (ttm_bo_swapout(&bdev->glob->shrink) == 0)
1740 ; 1829 ;
1741} 1830}
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
index ad4ada07c6cf..c70927ecda21 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -41,9 +41,9 @@ void ttm_bo_free_old_node(struct ttm_buffer_object *bo)
41 struct ttm_mem_reg *old_mem = &bo->mem; 41 struct ttm_mem_reg *old_mem = &bo->mem;
42 42
43 if (old_mem->mm_node) { 43 if (old_mem->mm_node) {
44 spin_lock(&bo->bdev->lru_lock); 44 spin_lock(&bo->glob->lru_lock);
45 drm_mm_put_block(old_mem->mm_node); 45 drm_mm_put_block(old_mem->mm_node);
46 spin_unlock(&bo->bdev->lru_lock); 46 spin_unlock(&bo->glob->lru_lock);
47 } 47 }
48 old_mem->mm_node = NULL; 48 old_mem->mm_node = NULL;
49} 49}
diff --git a/drivers/gpu/drm/ttm/ttm_global.c b/drivers/gpu/drm/ttm/ttm_global.c
index 0b14eb1972b8..541744d00d3e 100644
--- a/drivers/gpu/drm/ttm/ttm_global.c
+++ b/drivers/gpu/drm/ttm/ttm_global.c
@@ -71,7 +71,7 @@ int ttm_global_item_ref(struct ttm_global_reference *ref)
71 71
72 mutex_lock(&item->mutex); 72 mutex_lock(&item->mutex);
73 if (item->refcount == 0) { 73 if (item->refcount == 0) {
74 item->object = kmalloc(ref->size, GFP_KERNEL); 74 item->object = kzalloc(ref->size, GFP_KERNEL);
75 if (unlikely(item->object == NULL)) { 75 if (unlikely(item->object == NULL)) {
76 ret = -ENOMEM; 76 ret = -ENOMEM;
77 goto out_err; 77 goto out_err;
@@ -89,7 +89,6 @@ int ttm_global_item_ref(struct ttm_global_reference *ref)
89 mutex_unlock(&item->mutex); 89 mutex_unlock(&item->mutex);
90 return 0; 90 return 0;
91out_err: 91out_err:
92 kfree(item->object);
93 mutex_unlock(&item->mutex); 92 mutex_unlock(&item->mutex);
94 item->object = NULL; 93 item->object = NULL;
95 return ret; 94 return ret;
@@ -105,7 +104,6 @@ void ttm_global_item_unref(struct ttm_global_reference *ref)
105 BUG_ON(ref->object != item->object); 104 BUG_ON(ref->object != item->object);
106 if (--item->refcount == 0) { 105 if (--item->refcount == 0) {
107 ref->release(ref); 106 ref->release(ref);
108 kfree(item->object);
109 item->object = NULL; 107 item->object = NULL;
110 } 108 }
111 mutex_unlock(&item->mutex); 109 mutex_unlock(&item->mutex);
diff --git a/drivers/gpu/drm/ttm/ttm_memory.c b/drivers/gpu/drm/ttm/ttm_memory.c
index 87323d4ff68d..072c281a6bb5 100644
--- a/drivers/gpu/drm/ttm/ttm_memory.c
+++ b/drivers/gpu/drm/ttm/ttm_memory.c
@@ -26,15 +26,180 @@
26 **************************************************************************/ 26 **************************************************************************/
27 27
28#include "ttm/ttm_memory.h" 28#include "ttm/ttm_memory.h"
29#include "ttm/ttm_module.h"
29#include <linux/spinlock.h> 30#include <linux/spinlock.h>
30#include <linux/sched.h> 31#include <linux/sched.h>
31#include <linux/wait.h> 32#include <linux/wait.h>
32#include <linux/mm.h> 33#include <linux/mm.h>
33#include <linux/module.h> 34#include <linux/module.h>
34 35
35#define TTM_PFX "[TTM] "
36#define TTM_MEMORY_ALLOC_RETRIES 4 36#define TTM_MEMORY_ALLOC_RETRIES 4
37 37
38struct ttm_mem_zone {
39 struct kobject kobj;
40 struct ttm_mem_global *glob;
41 const char *name;
42 uint64_t zone_mem;
43 uint64_t emer_mem;
44 uint64_t max_mem;
45 uint64_t swap_limit;
46 uint64_t used_mem;
47};
48
49static struct attribute ttm_mem_sys = {
50 .name = "zone_memory",
51 .mode = S_IRUGO
52};
53static struct attribute ttm_mem_emer = {
54 .name = "emergency_memory",
55 .mode = S_IRUGO | S_IWUSR
56};
57static struct attribute ttm_mem_max = {
58 .name = "available_memory",
59 .mode = S_IRUGO | S_IWUSR
60};
61static struct attribute ttm_mem_swap = {
62 .name = "swap_limit",
63 .mode = S_IRUGO | S_IWUSR
64};
65static struct attribute ttm_mem_used = {
66 .name = "used_memory",
67 .mode = S_IRUGO
68};
69
70static void ttm_mem_zone_kobj_release(struct kobject *kobj)
71{
72 struct ttm_mem_zone *zone =
73 container_of(kobj, struct ttm_mem_zone, kobj);
74
75 printk(KERN_INFO TTM_PFX
76 "Zone %7s: Used memory at exit: %llu kiB.\n",
77 zone->name, (unsigned long long) zone->used_mem >> 10);
78 kfree(zone);
79}
80
81static ssize_t ttm_mem_zone_show(struct kobject *kobj,
82 struct attribute *attr,
83 char *buffer)
84{
85 struct ttm_mem_zone *zone =
86 container_of(kobj, struct ttm_mem_zone, kobj);
87 uint64_t val = 0;
88
89 spin_lock(&zone->glob->lock);
90 if (attr == &ttm_mem_sys)
91 val = zone->zone_mem;
92 else if (attr == &ttm_mem_emer)
93 val = zone->emer_mem;
94 else if (attr == &ttm_mem_max)
95 val = zone->max_mem;
96 else if (attr == &ttm_mem_swap)
97 val = zone->swap_limit;
98 else if (attr == &ttm_mem_used)
99 val = zone->used_mem;
100 spin_unlock(&zone->glob->lock);
101
102 return snprintf(buffer, PAGE_SIZE, "%llu\n",
103 (unsigned long long) val >> 10);
104}
105
106static void ttm_check_swapping(struct ttm_mem_global *glob);
107
108static ssize_t ttm_mem_zone_store(struct kobject *kobj,
109 struct attribute *attr,
110 const char *buffer,
111 size_t size)
112{
113 struct ttm_mem_zone *zone =
114 container_of(kobj, struct ttm_mem_zone, kobj);
115 int chars;
116 unsigned long val;
117 uint64_t val64;
118
119 chars = sscanf(buffer, "%lu", &val);
120 if (chars == 0)
121 return size;
122
123 val64 = val;
124 val64 <<= 10;
125
126 spin_lock(&zone->glob->lock);
127 if (val64 > zone->zone_mem)
128 val64 = zone->zone_mem;
129 if (attr == &ttm_mem_emer) {
130 zone->emer_mem = val64;
131 if (zone->max_mem > val64)
132 zone->max_mem = val64;
133 } else if (attr == &ttm_mem_max) {
134 zone->max_mem = val64;
135 if (zone->emer_mem < val64)
136 zone->emer_mem = val64;
137 } else if (attr == &ttm_mem_swap)
138 zone->swap_limit = val64;
139 spin_unlock(&zone->glob->lock);
140
141 ttm_check_swapping(zone->glob);
142
143 return size;
144}
145
146static struct attribute *ttm_mem_zone_attrs[] = {
147 &ttm_mem_sys,
148 &ttm_mem_emer,
149 &ttm_mem_max,
150 &ttm_mem_swap,
151 &ttm_mem_used,
152 NULL
153};
154
155static struct sysfs_ops ttm_mem_zone_ops = {
156 .show = &ttm_mem_zone_show,
157 .store = &ttm_mem_zone_store
158};
159
160static struct kobj_type ttm_mem_zone_kobj_type = {
161 .release = &ttm_mem_zone_kobj_release,
162 .sysfs_ops = &ttm_mem_zone_ops,
163 .default_attrs = ttm_mem_zone_attrs,
164};
165
166static void ttm_mem_global_kobj_release(struct kobject *kobj)
167{
168 struct ttm_mem_global *glob =
169 container_of(kobj, struct ttm_mem_global, kobj);
170
171 kfree(glob);
172}
173
174static struct kobj_type ttm_mem_glob_kobj_type = {
175 .release = &ttm_mem_global_kobj_release,
176};
177
178static bool ttm_zones_above_swap_target(struct ttm_mem_global *glob,
179 bool from_wq, uint64_t extra)
180{
181 unsigned int i;
182 struct ttm_mem_zone *zone;
183 uint64_t target;
184
185 for (i = 0; i < glob->num_zones; ++i) {
186 zone = glob->zones[i];
187
188 if (from_wq)
189 target = zone->swap_limit;
190 else if (capable(CAP_SYS_ADMIN))
191 target = zone->emer_mem;
192 else
193 target = zone->max_mem;
194
195 target = (extra > target) ? 0ULL : target;
196
197 if (zone->used_mem > target)
198 return true;
199 }
200 return false;
201}
202
38/** 203/**
39 * At this point we only support a single shrink callback. 204 * At this point we only support a single shrink callback.
40 * Extend this if needed, perhaps using a linked list of callbacks. 205 * Extend this if needed, perhaps using a linked list of callbacks.
@@ -42,34 +207,17 @@
42 * many threads may try to swap out at any given time. 207 * many threads may try to swap out at any given time.
43 */ 208 */
44 209
45static void ttm_shrink(struct ttm_mem_global *glob, bool from_workqueue, 210static void ttm_shrink(struct ttm_mem_global *glob, bool from_wq,
46 uint64_t extra) 211 uint64_t extra)
47{ 212{
48 int ret; 213 int ret;
49 struct ttm_mem_shrink *shrink; 214 struct ttm_mem_shrink *shrink;
50 uint64_t target;
51 uint64_t total_target;
52 215
53 spin_lock(&glob->lock); 216 spin_lock(&glob->lock);
54 if (glob->shrink == NULL) 217 if (glob->shrink == NULL)
55 goto out; 218 goto out;
56 219
57 if (from_workqueue) { 220 while (ttm_zones_above_swap_target(glob, from_wq, extra)) {
58 target = glob->swap_limit;
59 total_target = glob->total_memory_swap_limit;
60 } else if (capable(CAP_SYS_ADMIN)) {
61 total_target = glob->emer_total_memory;
62 target = glob->emer_memory;
63 } else {
64 total_target = glob->max_total_memory;
65 target = glob->max_memory;
66 }
67
68 total_target = (extra >= total_target) ? 0 : total_target - extra;
69 target = (extra >= target) ? 0 : target - extra;
70
71 while (glob->used_memory > target ||
72 glob->used_total_memory > total_target) {
73 shrink = glob->shrink; 221 shrink = glob->shrink;
74 spin_unlock(&glob->lock); 222 spin_unlock(&glob->lock);
75 ret = shrink->do_shrink(shrink); 223 ret = shrink->do_shrink(shrink);
@@ -81,6 +229,8 @@ out:
81 spin_unlock(&glob->lock); 229 spin_unlock(&glob->lock);
82} 230}
83 231
232
233
84static void ttm_shrink_work(struct work_struct *work) 234static void ttm_shrink_work(struct work_struct *work)
85{ 235{
86 struct ttm_mem_global *glob = 236 struct ttm_mem_global *glob =
@@ -89,63 +239,198 @@ static void ttm_shrink_work(struct work_struct *work)
89 ttm_shrink(glob, true, 0ULL); 239 ttm_shrink(glob, true, 0ULL);
90} 240}
91 241
242static int ttm_mem_init_kernel_zone(struct ttm_mem_global *glob,
243 const struct sysinfo *si)
244{
245 struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL);
246 uint64_t mem;
247 int ret;
248
249 if (unlikely(!zone))
250 return -ENOMEM;
251
252 mem = si->totalram - si->totalhigh;
253 mem *= si->mem_unit;
254
255 zone->name = "kernel";
256 zone->zone_mem = mem;
257 zone->max_mem = mem >> 1;
258 zone->emer_mem = (mem >> 1) + (mem >> 2);
259 zone->swap_limit = zone->max_mem - (mem >> 3);
260 zone->used_mem = 0;
261 zone->glob = glob;
262 glob->zone_kernel = zone;
263 kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type);
264 ret = kobject_add(&zone->kobj, &glob->kobj, zone->name);
265 if (unlikely(ret != 0)) {
266 kobject_put(&zone->kobj);
267 return ret;
268 }
269 glob->zones[glob->num_zones++] = zone;
270 return 0;
271}
272
273#ifdef CONFIG_HIGHMEM
274static int ttm_mem_init_highmem_zone(struct ttm_mem_global *glob,
275 const struct sysinfo *si)
276{
277 struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL);
278 uint64_t mem;
279 int ret;
280
281 if (unlikely(!zone))
282 return -ENOMEM;
283
284 if (si->totalhigh == 0)
285 return 0;
286
287 mem = si->totalram;
288 mem *= si->mem_unit;
289
290 zone->name = "highmem";
291 zone->zone_mem = mem;
292 zone->max_mem = mem >> 1;
293 zone->emer_mem = (mem >> 1) + (mem >> 2);
294 zone->swap_limit = zone->max_mem - (mem >> 3);
295 zone->used_mem = 0;
296 zone->glob = glob;
297 glob->zone_highmem = zone;
298 kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type);
299 ret = kobject_add(&zone->kobj, &glob->kobj, zone->name);
300 if (unlikely(ret != 0)) {
301 kobject_put(&zone->kobj);
302 return ret;
303 }
304 glob->zones[glob->num_zones++] = zone;
305 return 0;
306}
307#else
308static int ttm_mem_init_dma32_zone(struct ttm_mem_global *glob,
309 const struct sysinfo *si)
310{
311 struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL);
312 uint64_t mem;
313 int ret;
314
315 if (unlikely(!zone))
316 return -ENOMEM;
317
318 mem = si->totalram;
319 mem *= si->mem_unit;
320
321 /**
322 * No special dma32 zone needed.
323 */
324
325 if (mem <= ((uint64_t) 1ULL << 32))
326 return 0;
327
328 /*
329 * Limit max dma32 memory to 4GB for now
330 * until we can figure out how big this
331 * zone really is.
332 */
333
334 mem = ((uint64_t) 1ULL << 32);
335 zone->name = "dma32";
336 zone->zone_mem = mem;
337 zone->max_mem = mem >> 1;
338 zone->emer_mem = (mem >> 1) + (mem >> 2);
339 zone->swap_limit = zone->max_mem - (mem >> 3);
340 zone->used_mem = 0;
341 zone->glob = glob;
342 glob->zone_dma32 = zone;
343 kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type);
344 ret = kobject_add(&zone->kobj, &glob->kobj, zone->name);
345 if (unlikely(ret != 0)) {
346 kobject_put(&zone->kobj);
347 return ret;
348 }
349 glob->zones[glob->num_zones++] = zone;
350 return 0;
351}
352#endif
353
92int ttm_mem_global_init(struct ttm_mem_global *glob) 354int ttm_mem_global_init(struct ttm_mem_global *glob)
93{ 355{
94 struct sysinfo si; 356 struct sysinfo si;
95 uint64_t mem; 357 int ret;
358 int i;
359 struct ttm_mem_zone *zone;
96 360
97 spin_lock_init(&glob->lock); 361 spin_lock_init(&glob->lock);
98 glob->swap_queue = create_singlethread_workqueue("ttm_swap"); 362 glob->swap_queue = create_singlethread_workqueue("ttm_swap");
99 INIT_WORK(&glob->work, ttm_shrink_work); 363 INIT_WORK(&glob->work, ttm_shrink_work);
100 init_waitqueue_head(&glob->queue); 364 init_waitqueue_head(&glob->queue);
365 kobject_init(&glob->kobj, &ttm_mem_glob_kobj_type);
366 ret = kobject_add(&glob->kobj,
367 ttm_get_kobj(),
368 "memory_accounting");
369 if (unlikely(ret != 0)) {
370 kobject_put(&glob->kobj);
371 return ret;
372 }
101 373
102 si_meminfo(&si); 374 si_meminfo(&si);
103 375
104 mem = si.totalram - si.totalhigh; 376 ret = ttm_mem_init_kernel_zone(glob, &si);
105 mem *= si.mem_unit; 377 if (unlikely(ret != 0))
106 378 goto out_no_zone;
107 glob->max_memory = mem >> 1; 379#ifdef CONFIG_HIGHMEM
108 glob->emer_memory = (mem >> 1) + (mem >> 2); 380 ret = ttm_mem_init_highmem_zone(glob, &si);
109 glob->swap_limit = glob->max_memory - (mem >> 3); 381 if (unlikely(ret != 0))
110 glob->used_memory = 0; 382 goto out_no_zone;
111 glob->used_total_memory = 0; 383#else
112 glob->shrink = NULL; 384 ret = ttm_mem_init_dma32_zone(glob, &si);
113 385 if (unlikely(ret != 0))
114 mem = si.totalram; 386 goto out_no_zone;
115 mem *= si.mem_unit; 387#endif
116 388 for (i = 0; i < glob->num_zones; ++i) {
117 glob->max_total_memory = mem >> 1; 389 zone = glob->zones[i];
118 glob->emer_total_memory = (mem >> 1) + (mem >> 2); 390 printk(KERN_INFO TTM_PFX
119 391 "Zone %7s: Available graphics memory: %llu kiB.\n",
120 glob->total_memory_swap_limit = glob->max_total_memory - (mem >> 3); 392 zone->name, (unsigned long long) zone->max_mem >> 10);
121 393 }
122 printk(KERN_INFO TTM_PFX "TTM available graphics memory: %llu MiB\n",
123 glob->max_total_memory >> 20);
124 printk(KERN_INFO TTM_PFX "TTM available object memory: %llu MiB\n",
125 glob->max_memory >> 20);
126
127 return 0; 394 return 0;
395out_no_zone:
396 ttm_mem_global_release(glob);
397 return ret;
128} 398}
129EXPORT_SYMBOL(ttm_mem_global_init); 399EXPORT_SYMBOL(ttm_mem_global_init);
130 400
131void ttm_mem_global_release(struct ttm_mem_global *glob) 401void ttm_mem_global_release(struct ttm_mem_global *glob)
132{ 402{
133 printk(KERN_INFO TTM_PFX "Used total memory is %llu bytes.\n", 403 unsigned int i;
134 (unsigned long long)glob->used_total_memory); 404 struct ttm_mem_zone *zone;
405
135 flush_workqueue(glob->swap_queue); 406 flush_workqueue(glob->swap_queue);
136 destroy_workqueue(glob->swap_queue); 407 destroy_workqueue(glob->swap_queue);
137 glob->swap_queue = NULL; 408 glob->swap_queue = NULL;
409 for (i = 0; i < glob->num_zones; ++i) {
410 zone = glob->zones[i];
411 kobject_del(&zone->kobj);
412 kobject_put(&zone->kobj);
413 }
414 kobject_del(&glob->kobj);
415 kobject_put(&glob->kobj);
138} 416}
139EXPORT_SYMBOL(ttm_mem_global_release); 417EXPORT_SYMBOL(ttm_mem_global_release);
140 418
141static inline void ttm_check_swapping(struct ttm_mem_global *glob) 419static void ttm_check_swapping(struct ttm_mem_global *glob)
142{ 420{
143 bool needs_swapping; 421 bool needs_swapping = false;
422 unsigned int i;
423 struct ttm_mem_zone *zone;
144 424
145 spin_lock(&glob->lock); 425 spin_lock(&glob->lock);
146 needs_swapping = (glob->used_memory > glob->swap_limit || 426 for (i = 0; i < glob->num_zones; ++i) {
147 glob->used_total_memory > 427 zone = glob->zones[i];
148 glob->total_memory_swap_limit); 428 if (zone->used_mem > zone->swap_limit) {
429 needs_swapping = true;
430 break;
431 }
432 }
433
149 spin_unlock(&glob->lock); 434 spin_unlock(&glob->lock);
150 435
151 if (unlikely(needs_swapping)) 436 if (unlikely(needs_swapping))
@@ -153,44 +438,60 @@ static inline void ttm_check_swapping(struct ttm_mem_global *glob)
153 438
154} 439}
155 440
156void ttm_mem_global_free(struct ttm_mem_global *glob, 441static void ttm_mem_global_free_zone(struct ttm_mem_global *glob,
157 uint64_t amount, bool himem) 442 struct ttm_mem_zone *single_zone,
443 uint64_t amount)
158{ 444{
445 unsigned int i;
446 struct ttm_mem_zone *zone;
447
159 spin_lock(&glob->lock); 448 spin_lock(&glob->lock);
160 glob->used_total_memory -= amount; 449 for (i = 0; i < glob->num_zones; ++i) {
161 if (!himem) 450 zone = glob->zones[i];
162 glob->used_memory -= amount; 451 if (single_zone && zone != single_zone)
163 wake_up_all(&glob->queue); 452 continue;
453 zone->used_mem -= amount;
454 }
164 spin_unlock(&glob->lock); 455 spin_unlock(&glob->lock);
165} 456}
166 457
458void ttm_mem_global_free(struct ttm_mem_global *glob,
459 uint64_t amount)
460{
461 return ttm_mem_global_free_zone(glob, NULL, amount);
462}
463
167static int ttm_mem_global_reserve(struct ttm_mem_global *glob, 464static int ttm_mem_global_reserve(struct ttm_mem_global *glob,
168 uint64_t amount, bool himem, bool reserve) 465 struct ttm_mem_zone *single_zone,
466 uint64_t amount, bool reserve)
169{ 467{
170 uint64_t limit; 468 uint64_t limit;
171 uint64_t lomem_limit;
172 int ret = -ENOMEM; 469 int ret = -ENOMEM;
470 unsigned int i;
471 struct ttm_mem_zone *zone;
173 472
174 spin_lock(&glob->lock); 473 spin_lock(&glob->lock);
474 for (i = 0; i < glob->num_zones; ++i) {
475 zone = glob->zones[i];
476 if (single_zone && zone != single_zone)
477 continue;
175 478
176 if (capable(CAP_SYS_ADMIN)) { 479 limit = (capable(CAP_SYS_ADMIN)) ?
177 limit = glob->emer_total_memory; 480 zone->emer_mem : zone->max_mem;
178 lomem_limit = glob->emer_memory;
179 } else {
180 limit = glob->max_total_memory;
181 lomem_limit = glob->max_memory;
182 }
183 481
184 if (unlikely(glob->used_total_memory + amount > limit)) 482 if (zone->used_mem > limit)
185 goto out_unlock; 483 goto out_unlock;
186 if (unlikely(!himem && glob->used_memory + amount > lomem_limit)) 484 }
187 goto out_unlock;
188 485
189 if (reserve) { 486 if (reserve) {
190 glob->used_total_memory += amount; 487 for (i = 0; i < glob->num_zones; ++i) {
191 if (!himem) 488 zone = glob->zones[i];
192 glob->used_memory += amount; 489 if (single_zone && zone != single_zone)
490 continue;
491 zone->used_mem += amount;
492 }
193 } 493 }
494
194 ret = 0; 495 ret = 0;
195out_unlock: 496out_unlock:
196 spin_unlock(&glob->lock); 497 spin_unlock(&glob->lock);
@@ -199,12 +500,17 @@ out_unlock:
199 return ret; 500 return ret;
200} 501}
201 502
202int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory, 503
203 bool no_wait, bool interruptible, bool himem) 504static int ttm_mem_global_alloc_zone(struct ttm_mem_global *glob,
505 struct ttm_mem_zone *single_zone,
506 uint64_t memory,
507 bool no_wait, bool interruptible)
204{ 508{
205 int count = TTM_MEMORY_ALLOC_RETRIES; 509 int count = TTM_MEMORY_ALLOC_RETRIES;
206 510
207 while (unlikely(ttm_mem_global_reserve(glob, memory, himem, true) 511 while (unlikely(ttm_mem_global_reserve(glob,
512 single_zone,
513 memory, true)
208 != 0)) { 514 != 0)) {
209 if (no_wait) 515 if (no_wait)
210 return -ENOMEM; 516 return -ENOMEM;
@@ -216,6 +522,56 @@ int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory,
216 return 0; 522 return 0;
217} 523}
218 524
525int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory,
526 bool no_wait, bool interruptible)
527{
528 /**
529 * Normal allocations of kernel memory are registered in
530 * all zones.
531 */
532
533 return ttm_mem_global_alloc_zone(glob, NULL, memory, no_wait,
534 interruptible);
535}
536
537int ttm_mem_global_alloc_page(struct ttm_mem_global *glob,
538 struct page *page,
539 bool no_wait, bool interruptible)
540{
541
542 struct ttm_mem_zone *zone = NULL;
543
544 /**
545 * Page allocations may be registed in a single zone
546 * only if highmem or !dma32.
547 */
548
549#ifdef CONFIG_HIGHMEM
550 if (PageHighMem(page) && glob->zone_highmem != NULL)
551 zone = glob->zone_highmem;
552#else
553 if (glob->zone_dma32 && page_to_pfn(page) > 0x00100000UL)
554 zone = glob->zone_kernel;
555#endif
556 return ttm_mem_global_alloc_zone(glob, zone, PAGE_SIZE, no_wait,
557 interruptible);
558}
559
560void ttm_mem_global_free_page(struct ttm_mem_global *glob, struct page *page)
561{
562 struct ttm_mem_zone *zone = NULL;
563
564#ifdef CONFIG_HIGHMEM
565 if (PageHighMem(page) && glob->zone_highmem != NULL)
566 zone = glob->zone_highmem;
567#else
568 if (glob->zone_dma32 && page_to_pfn(page) > 0x00100000UL)
569 zone = glob->zone_kernel;
570#endif
571 ttm_mem_global_free_zone(glob, zone, PAGE_SIZE);
572}
573
574
219size_t ttm_round_pot(size_t size) 575size_t ttm_round_pot(size_t size)
220{ 576{
221 if ((size & (size - 1)) == 0) 577 if ((size & (size - 1)) == 0)
diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
index 59ce8191d584..9a6edbfeaa9e 100644
--- a/drivers/gpu/drm/ttm/ttm_module.c
+++ b/drivers/gpu/drm/ttm/ttm_module.c
@@ -29,16 +29,72 @@
29 * Jerome Glisse 29 * Jerome Glisse
30 */ 30 */
31#include <linux/module.h> 31#include <linux/module.h>
32#include <ttm/ttm_module.h> 32#include <linux/device.h>
33#include <linux/sched.h>
34#include "ttm/ttm_module.h"
35#include "drm_sysfs.h"
36
37static DECLARE_WAIT_QUEUE_HEAD(exit_q);
38atomic_t device_released;
39
40static struct device_type ttm_drm_class_type = {
41 .name = "ttm",
42 /**
43 * Add pm ops here.
44 */
45};
46
47static void ttm_drm_class_device_release(struct device *dev)
48{
49 atomic_set(&device_released, 1);
50 wake_up_all(&exit_q);
51}
52
53static struct device ttm_drm_class_device = {
54 .type = &ttm_drm_class_type,
55 .release = &ttm_drm_class_device_release
56};
57
58struct kobject *ttm_get_kobj(void)
59{
60 struct kobject *kobj = &ttm_drm_class_device.kobj;
61 BUG_ON(kobj == NULL);
62 return kobj;
63}
33 64
34static int __init ttm_init(void) 65static int __init ttm_init(void)
35{ 66{
67 int ret;
68
69 ret = dev_set_name(&ttm_drm_class_device, "ttm");
70 if (unlikely(ret != 0))
71 return ret;
72
36 ttm_global_init(); 73 ttm_global_init();
74
75 atomic_set(&device_released, 0);
76 ret = drm_class_device_register(&ttm_drm_class_device);
77 if (unlikely(ret != 0))
78 goto out_no_dev_reg;
79
37 return 0; 80 return 0;
81out_no_dev_reg:
82 atomic_set(&device_released, 1);
83 wake_up_all(&exit_q);
84 ttm_global_release();
85 return ret;
38} 86}
39 87
40static void __exit ttm_exit(void) 88static void __exit ttm_exit(void)
41{ 89{
90 drm_class_device_unregister(&ttm_drm_class_device);
91
92 /**
93 * Refuse to unload until the TTM device is released.
94 * Not sure this is 100% needed.
95 */
96
97 wait_event(exit_q, atomic_read(&device_released) == 1);
42 ttm_global_release(); 98 ttm_global_release();
43} 99}
44 100
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index b8b6c4a5f983..a55ee1a56c16 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -34,76 +34,13 @@
34#include <linux/pagemap.h> 34#include <linux/pagemap.h>
35#include <linux/file.h> 35#include <linux/file.h>
36#include <linux/swap.h> 36#include <linux/swap.h>
37#include "drm_cache.h"
37#include "ttm/ttm_module.h" 38#include "ttm/ttm_module.h"
38#include "ttm/ttm_bo_driver.h" 39#include "ttm/ttm_bo_driver.h"
39#include "ttm/ttm_placement.h" 40#include "ttm/ttm_placement.h"
40 41
41static int ttm_tt_swapin(struct ttm_tt *ttm); 42static int ttm_tt_swapin(struct ttm_tt *ttm);
42 43
43#if defined(CONFIG_X86)
44static void ttm_tt_clflush_page(struct page *page)
45{
46 uint8_t *page_virtual;
47 unsigned int i;
48
49 if (unlikely(page == NULL))
50 return;
51
52 page_virtual = kmap_atomic(page, KM_USER0);
53
54 for (i = 0; i < PAGE_SIZE; i += boot_cpu_data.x86_clflush_size)
55 clflush(page_virtual + i);
56
57 kunmap_atomic(page_virtual, KM_USER0);
58}
59
60static void ttm_tt_cache_flush_clflush(struct page *pages[],
61 unsigned long num_pages)
62{
63 unsigned long i;
64
65 mb();
66 for (i = 0; i < num_pages; ++i)
67 ttm_tt_clflush_page(*pages++);
68 mb();
69}
70#elif !defined(__powerpc__)
71static void ttm_tt_ipi_handler(void *null)
72{
73 ;
74}
75#endif
76
77void ttm_tt_cache_flush(struct page *pages[], unsigned long num_pages)
78{
79
80#if defined(CONFIG_X86)
81 if (cpu_has_clflush) {
82 ttm_tt_cache_flush_clflush(pages, num_pages);
83 return;
84 }
85#elif defined(__powerpc__)
86 unsigned long i;
87
88 for (i = 0; i < num_pages; ++i) {
89 struct page *page = pages[i];
90 void *page_virtual;
91
92 if (unlikely(page == NULL))
93 continue;
94
95 page_virtual = kmap_atomic(page, KM_USER0);
96 flush_dcache_range((unsigned long) page_virtual,
97 (unsigned long) page_virtual + PAGE_SIZE);
98 kunmap_atomic(page_virtual, KM_USER0);
99 }
100#else
101 if (on_each_cpu(ttm_tt_ipi_handler, NULL, 1) != 0)
102 printk(KERN_ERR TTM_PFX
103 "Timed out waiting for drm cache flush.\n");
104#endif
105}
106
107/** 44/**
108 * Allocates storage for pointers to the pages that back the ttm. 45 * Allocates storage for pointers to the pages that back the ttm.
109 * 46 *
@@ -179,7 +116,7 @@ static void ttm_tt_free_user_pages(struct ttm_tt *ttm)
179 set_page_dirty_lock(page); 116 set_page_dirty_lock(page);
180 117
181 ttm->pages[i] = NULL; 118 ttm->pages[i] = NULL;
182 ttm_mem_global_free(ttm->bdev->mem_glob, PAGE_SIZE, false); 119 ttm_mem_global_free(ttm->glob->mem_glob, PAGE_SIZE);
183 put_page(page); 120 put_page(page);
184 } 121 }
185 ttm->state = tt_unpopulated; 122 ttm->state = tt_unpopulated;
@@ -190,8 +127,7 @@ static void ttm_tt_free_user_pages(struct ttm_tt *ttm)
190static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, int index) 127static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, int index)
191{ 128{
192 struct page *p; 129 struct page *p;
193 struct ttm_bo_device *bdev = ttm->bdev; 130 struct ttm_mem_global *mem_glob = ttm->glob->mem_glob;
194 struct ttm_mem_global *mem_glob = bdev->mem_glob;
195 int ret; 131 int ret;
196 132
197 while (NULL == (p = ttm->pages[index])) { 133 while (NULL == (p = ttm->pages[index])) {
@@ -200,21 +136,14 @@ static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, int index)
200 if (!p) 136 if (!p)
201 return NULL; 137 return NULL;
202 138
203 if (PageHighMem(p)) { 139 ret = ttm_mem_global_alloc_page(mem_glob, p, false, false);
204 ret = 140 if (unlikely(ret != 0))
205 ttm_mem_global_alloc(mem_glob, PAGE_SIZE, 141 goto out_err;
206 false, false, true); 142
207 if (unlikely(ret != 0)) 143 if (PageHighMem(p))
208 goto out_err;
209 ttm->pages[--ttm->first_himem_page] = p; 144 ttm->pages[--ttm->first_himem_page] = p;
210 } else { 145 else
211 ret =
212 ttm_mem_global_alloc(mem_glob, PAGE_SIZE,
213 false, false, false);
214 if (unlikely(ret != 0))
215 goto out_err;
216 ttm->pages[++ttm->last_lomem_page] = p; 146 ttm->pages[++ttm->last_lomem_page] = p;
217 }
218 } 147 }
219 return p; 148 return p;
220out_err: 149out_err:
@@ -310,7 +239,7 @@ static int ttm_tt_set_caching(struct ttm_tt *ttm,
310 } 239 }
311 240
312 if (ttm->caching_state == tt_cached) 241 if (ttm->caching_state == tt_cached)
313 ttm_tt_cache_flush(ttm->pages, ttm->num_pages); 242 drm_clflush_pages(ttm->pages, ttm->num_pages);
314 243
315 for (i = 0; i < ttm->num_pages; ++i) { 244 for (i = 0; i < ttm->num_pages; ++i) {
316 cur_page = ttm->pages[i]; 245 cur_page = ttm->pages[i];
@@ -368,8 +297,8 @@ static void ttm_tt_free_alloced_pages(struct ttm_tt *ttm)
368 printk(KERN_ERR TTM_PFX 297 printk(KERN_ERR TTM_PFX
369 "Erroneous page count. " 298 "Erroneous page count. "
370 "Leaking pages.\n"); 299 "Leaking pages.\n");
371 ttm_mem_global_free(ttm->bdev->mem_glob, PAGE_SIZE, 300 ttm_mem_global_free_page(ttm->glob->mem_glob,
372 PageHighMem(cur_page)); 301 cur_page);
373 __free_page(cur_page); 302 __free_page(cur_page);
374 } 303 }
375 } 304 }
@@ -414,7 +343,7 @@ int ttm_tt_set_user(struct ttm_tt *ttm,
414 struct mm_struct *mm = tsk->mm; 343 struct mm_struct *mm = tsk->mm;
415 int ret; 344 int ret;
416 int write = (ttm->page_flags & TTM_PAGE_FLAG_WRITE) != 0; 345 int write = (ttm->page_flags & TTM_PAGE_FLAG_WRITE) != 0;
417 struct ttm_mem_global *mem_glob = ttm->bdev->mem_glob; 346 struct ttm_mem_global *mem_glob = ttm->glob->mem_glob;
418 347
419 BUG_ON(num_pages != ttm->num_pages); 348 BUG_ON(num_pages != ttm->num_pages);
420 BUG_ON((ttm->page_flags & TTM_PAGE_FLAG_USER) == 0); 349 BUG_ON((ttm->page_flags & TTM_PAGE_FLAG_USER) == 0);
@@ -424,7 +353,7 @@ int ttm_tt_set_user(struct ttm_tt *ttm,
424 */ 353 */
425 354
426 ret = ttm_mem_global_alloc(mem_glob, num_pages * PAGE_SIZE, 355 ret = ttm_mem_global_alloc(mem_glob, num_pages * PAGE_SIZE,
427 false, false, false); 356 false, false);
428 if (unlikely(ret != 0)) 357 if (unlikely(ret != 0))
429 return ret; 358 return ret;
430 359
@@ -435,7 +364,7 @@ int ttm_tt_set_user(struct ttm_tt *ttm,
435 364
436 if (ret != num_pages && write) { 365 if (ret != num_pages && write) {
437 ttm_tt_free_user_pages(ttm); 366 ttm_tt_free_user_pages(ttm);
438 ttm_mem_global_free(mem_glob, num_pages * PAGE_SIZE, false); 367 ttm_mem_global_free(mem_glob, num_pages * PAGE_SIZE);
439 return -ENOMEM; 368 return -ENOMEM;
440 } 369 }
441 370
@@ -459,8 +388,7 @@ struct ttm_tt *ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
459 if (!ttm) 388 if (!ttm)
460 return NULL; 389 return NULL;
461 390
462 ttm->bdev = bdev; 391 ttm->glob = bdev->glob;
463
464 ttm->num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; 392 ttm->num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
465 ttm->first_himem_page = ttm->num_pages; 393 ttm->first_himem_page = ttm->num_pages;
466 ttm->last_lomem_page = -1; 394 ttm->last_lomem_page = -1;
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-29 03:35:21 -0400