diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600_blit_kms.c | 13 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600_blit_shaders.c | 10 |
3 files changed, 9 insertions, 21 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 9661a469f3bd..7c32a233b236 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -1783,6 +1783,13 @@ void r600_fence_ring_emit(struct radeon_device *rdev, | |||
1783 | struct radeon_fence *fence) | 1783 | struct radeon_fence *fence) |
1784 | { | 1784 | { |
1785 | /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */ | 1785 | /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */ |
1786 | |||
1787 | radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); | ||
1788 | radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); | ||
1789 | /* wait for 3D idle clean */ | ||
1790 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | ||
1791 | radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | ||
1792 | radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); | ||
1786 | /* Emit fence sequence & fire IRQ */ | 1793 | /* Emit fence sequence & fire IRQ */ |
1787 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | 1794 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
1788 | radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | 1795 | radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c index af1c3ca8a4cb..2d7d16e14f9e 100644 --- a/drivers/gpu/drm/radeon/r600_blit_kms.c +++ b/drivers/gpu/drm/radeon/r600_blit_kms.c | |||
@@ -403,8 +403,6 @@ set_default_state(struct radeon_device *rdev) | |||
403 | radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); | 403 | radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); |
404 | radeon_ring_write(rdev, dwords); | 404 | radeon_ring_write(rdev, dwords); |
405 | 405 | ||
406 | radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); | ||
407 | radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); | ||
408 | /* SQ config */ | 406 | /* SQ config */ |
409 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); | 407 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); |
410 | radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | 408 | radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
@@ -581,9 +579,9 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) | |||
581 | ring_size = num_loops * dwords_per_loop; | 579 | ring_size = num_loops * dwords_per_loop; |
582 | /* set default + shaders */ | 580 | /* set default + shaders */ |
583 | ring_size += 40; /* shaders + def state */ | 581 | ring_size += 40; /* shaders + def state */ |
584 | ring_size += 7; /* fence emit for VB IB */ | 582 | ring_size += 12; /* fence emit for VB IB */ |
585 | ring_size += 5; /* done copy */ | 583 | ring_size += 5; /* done copy */ |
586 | ring_size += 7; /* fence emit for done copy */ | 584 | ring_size += 12; /* fence emit for done copy */ |
587 | r = radeon_ring_lock(rdev, ring_size); | 585 | r = radeon_ring_lock(rdev, ring_size); |
588 | if (r) | 586 | if (r) |
589 | return r; | 587 | return r; |
@@ -597,13 +595,6 @@ void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence) | |||
597 | { | 595 | { |
598 | int r; | 596 | int r; |
599 | 597 | ||
600 | radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); | ||
601 | radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); | ||
602 | /* wait for 3D idle clean */ | ||
603 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | ||
604 | radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | ||
605 | radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); | ||
606 | |||
607 | if (rdev->r600_blit.vb_ib) | 598 | if (rdev->r600_blit.vb_ib) |
608 | r600_vb_ib_put(rdev); | 599 | r600_vb_ib_put(rdev); |
609 | 600 | ||
diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c index d745e815c2e8..a112c59f9d82 100644 --- a/drivers/gpu/drm/radeon/r600_blit_shaders.c +++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c | |||
@@ -9,11 +9,6 @@ const u32 r6xx_default_state[] = | |||
9 | 0xc0012800, | 9 | 0xc0012800, |
10 | 0x80000000, | 10 | 0x80000000, |
11 | 0x80000000, | 11 | 0x80000000, |
12 | 0xc0004600, | ||
13 | 0x00000016, | ||
14 | 0xc0016800, | ||
15 | 0x00000010, | ||
16 | 0x00028000, | ||
17 | 0xc0016800, | 12 | 0xc0016800, |
18 | 0x00000010, | 13 | 0x00000010, |
19 | 0x00008000, | 14 | 0x00008000, |
@@ -531,11 +526,6 @@ const u32 r7xx_default_state[] = | |||
531 | 0xc0012800, | 526 | 0xc0012800, |
532 | 0x80000000, | 527 | 0x80000000, |
533 | 0x80000000, | 528 | 0x80000000, |
534 | 0xc0004600, | ||
535 | 0x00000016, | ||
536 | 0xc0016800, | ||
537 | 0x00000010, | ||
538 | 0x00028000, | ||
539 | 0xc0016800, | 529 | 0xc0016800, |
540 | 0x00000010, | 530 | 0x00000010, |
541 | 0x00008000, | 531 | 0x00008000, |