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-rw-r--r--drivers/acpi/processor_idle.c39
-rw-r--r--drivers/net/Kconfig25
-rw-r--r--drivers/net/cxgb3/common.h15
-rw-r--r--drivers/net/cxgb3/cxgb3_main.c90
-rw-r--r--drivers/net/cxgb3/regs.h22
-rw-r--r--drivers/net/cxgb3/t3_hw.c15
-rw-r--r--drivers/net/cxgb3/xgmac.c133
-rw-r--r--drivers/net/ewrk3.c3
-rw-r--r--drivers/net/mv643xx_eth.c14
-rw-r--r--drivers/net/myri10ge/myri10ge.c22
-rw-r--r--drivers/net/pci-skeleton.c4
-rw-r--r--drivers/net/saa9730.c177
-rw-r--r--drivers/net/skge.c110
-rw-r--r--drivers/net/skge.h6
-rw-r--r--drivers/net/ucc_geth.c3
-rw-r--r--drivers/net/wireless/airo.c4
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx_radio.c14
-rw-r--r--drivers/serial/8250_pnp.c3
-rw-r--r--drivers/video/riva/fbdev.c4
19 files changed, 474 insertions, 229 deletions
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index 562124ed785e..cdf78943af4d 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -89,12 +89,6 @@ module_param(nocst, uint, 0000);
89static unsigned int bm_history __read_mostly = 89static unsigned int bm_history __read_mostly =
90 (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1)); 90 (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1));
91module_param(bm_history, uint, 0644); 91module_param(bm_history, uint, 0644);
92
93static unsigned use_ipi = 2;
94module_param(use_ipi, uint, 0644);
95MODULE_PARM_DESC(use_ipi, "IPI (vs. LAPIC) irqs for not waking up from C2/C3"
96 " machines. 0=apic, 1=ipi, 2=auto\n");
97
98/* -------------------------------------------------------------------------- 92/* --------------------------------------------------------------------------
99 Power Management 93 Power Management
100 -------------------------------------------------------------------------- */ 94 -------------------------------------------------------------------------- */
@@ -266,13 +260,15 @@ static void acpi_cstate_enter(struct acpi_processor_cx *cstate)
266 260
267/* 261/*
268 * Some BIOS implementations switch to C3 in the published C2 state. 262 * Some BIOS implementations switch to C3 in the published C2 state.
269 * This seems to be a common problem on AMD boxen and Intel Dothan/Banias 263 * This seems to be a common problem on AMD boxen, but other vendors
270 * Pentium M machines. 264 * are affected too. We pick the most conservative approach: we assume
265 * that the local APIC stops in both C2 and C3.
271 */ 266 */
272static void acpi_timer_check_state(int state, struct acpi_processor *pr, 267static void acpi_timer_check_state(int state, struct acpi_processor *pr,
273 struct acpi_processor_cx *cx) 268 struct acpi_processor_cx *cx)
274{ 269{
275 struct acpi_processor_power *pwr = &pr->power; 270 struct acpi_processor_power *pwr = &pr->power;
271 u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2;
276 272
277 /* 273 /*
278 * Check, if one of the previous states already marked the lapic 274 * Check, if one of the previous states already marked the lapic
@@ -281,17 +277,8 @@ static void acpi_timer_check_state(int state, struct acpi_processor *pr,
281 if (pwr->timer_broadcast_on_state < state) 277 if (pwr->timer_broadcast_on_state < state)
282 return; 278 return;
283 279
284 if (cx->type >= ACPI_STATE_C2) { 280 if (cx->type >= type)
285 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 281 pr->power.timer_broadcast_on_state = state;
286 pr->power.timer_broadcast_on_state = state;
287 else if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
288 boot_cpu_data.x86 == 6) &&
289 (boot_cpu_data.x86_model == 13 ||
290 boot_cpu_data.x86_model == 9))
291 {
292 pr->power.timer_broadcast_on_state = state;
293 }
294 }
295} 282}
296 283
297static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) 284static void acpi_propagate_timer_broadcast(struct acpi_processor *pr)
@@ -306,16 +293,10 @@ static void acpi_propagate_timer_broadcast(struct acpi_processor *pr)
306#else 293#else
307 cpumask_t mask = cpumask_of_cpu(pr->id); 294 cpumask_t mask = cpumask_of_cpu(pr->id);
308 295
309 if (use_ipi == 0) 296 if (pr->power.timer_broadcast_on_state < INT_MAX)
310 on_each_cpu(switch_APIC_timer_to_ipi, &mask, 1, 1); 297 on_each_cpu(switch_APIC_timer_to_ipi, &mask, 1, 1);
311 else if (use_ipi == 1) 298 else
312 on_each_cpu(switch_ipi_to_APIC_timer, &mask, 1, 1); 299 on_each_cpu(switch_ipi_to_APIC_timer, &mask, 1, 1);
313 else {
314 if (pr->power.timer_broadcast_on_state < INT_MAX)
315 on_each_cpu(switch_APIC_timer_to_ipi, &mask, 1, 1);
316 else
317 on_each_cpu(switch_ipi_to_APIC_timer, &mask, 1, 1);
318 }
319#endif 300#endif
320} 301}
321 302
@@ -1033,13 +1014,13 @@ static int acpi_processor_power_verify(struct acpi_processor *pr)
1033 1014
1034 case ACPI_STATE_C2: 1015 case ACPI_STATE_C2:
1035 acpi_processor_power_verify_c2(cx); 1016 acpi_processor_power_verify_c2(cx);
1036 if (cx->valid && use_ipi != 0 && use_ipi != 1) 1017 if (cx->valid)
1037 acpi_timer_check_state(i, pr, cx); 1018 acpi_timer_check_state(i, pr, cx);
1038 break; 1019 break;
1039 1020
1040 case ACPI_STATE_C3: 1021 case ACPI_STATE_C3:
1041 acpi_processor_power_verify_c3(pr, cx); 1022 acpi_processor_power_verify_c3(pr, cx);
1042 if (cx->valid && use_ipi != 0 && use_ipi != 1) 1023 if (cx->valid)
1043 acpi_timer_check_state(i, pr, cx); 1024 acpi_timer_check_state(i, pr, cx);
1044 break; 1025 break;
1045 } 1026 }
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 5ff0922e628c..c3f9f599f134 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2372,22 +2372,23 @@ config CHELSIO_T1_NAPI
2372 when the driver is receiving lots of packets from the card. 2372 when the driver is receiving lots of packets from the card.
2373 2373
2374config CHELSIO_T3 2374config CHELSIO_T3
2375 tristate "Chelsio Communications T3 10Gb Ethernet support" 2375 tristate "Chelsio Communications T3 10Gb Ethernet support"
2376 depends on PCI 2376 depends on PCI
2377 help 2377 select FW_LOADER
2378 This driver supports Chelsio T3-based gigabit and 10Gb Ethernet 2378 help
2379 adapters. 2379 This driver supports Chelsio T3-based gigabit and 10Gb Ethernet
2380 adapters.
2380 2381
2381 For general information about Chelsio and our products, visit 2382 For general information about Chelsio and our products, visit
2382 our website at <http://www.chelsio.com>. 2383 our website at <http://www.chelsio.com>.
2383 2384
2384 For customer support, please visit our customer support page at 2385 For customer support, please visit our customer support page at
2385 <http://www.chelsio.com/support.htm>. 2386 <http://www.chelsio.com/support.htm>.
2386 2387
2387 Please send feedback to <linux-bugs@chelsio.com>. 2388 Please send feedback to <linux-bugs@chelsio.com>.
2388 2389
2389 To compile this driver as a module, choose M here: the module 2390 To compile this driver as a module, choose M here: the module
2390 will be called cxgb3. 2391 will be called cxgb3.
2391 2392
2392config EHEA 2393config EHEA
2393 tristate "eHEA Ethernet support" 2394 tristate "eHEA Ethernet support"
diff --git a/drivers/net/cxgb3/common.h b/drivers/net/cxgb3/common.h
index e23deeb7d06d..85e5543cfb57 100644
--- a/drivers/net/cxgb3/common.h
+++ b/drivers/net/cxgb3/common.h
@@ -260,6 +260,10 @@ struct mac_stats {
260 unsigned long serdes_signal_loss; 260 unsigned long serdes_signal_loss;
261 unsigned long xaui_pcs_ctc_err; 261 unsigned long xaui_pcs_ctc_err;
262 unsigned long xaui_pcs_align_change; 262 unsigned long xaui_pcs_align_change;
263
264 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */
265 unsigned long num_resets; /* # times reset due to stuck TX */
266
263}; 267};
264 268
265struct tp_mib_stats { 269struct tp_mib_stats {
@@ -400,6 +404,12 @@ struct adapter_params {
400 unsigned int rev; /* chip revision */ 404 unsigned int rev; /* chip revision */
401}; 405};
402 406
407enum { /* chip revisions */
408 T3_REV_A = 0,
409 T3_REV_B = 2,
410 T3_REV_B2 = 3,
411};
412
403struct trace_params { 413struct trace_params {
404 u32 sip; 414 u32 sip;
405 u32 sip_mask; 415 u32 sip_mask;
@@ -465,6 +475,10 @@ struct cmac {
465 struct adapter *adapter; 475 struct adapter *adapter;
466 unsigned int offset; 476 unsigned int offset;
467 unsigned int nucast; /* # of address filters for unicast MACs */ 477 unsigned int nucast; /* # of address filters for unicast MACs */
478 unsigned int tcnt;
479 unsigned int xcnt;
480 unsigned int toggle_cnt;
481 unsigned int txen;
468 struct mac_stats stats; 482 struct mac_stats stats;
469}; 483};
470 484
@@ -666,6 +680,7 @@ int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
666int t3_mac_set_num_ucast(struct cmac *mac, int n); 680int t3_mac_set_num_ucast(struct cmac *mac, int n);
667const struct mac_stats *t3_mac_update_stats(struct cmac *mac); 681const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
668int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc); 682int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc);
683int t3b2_mac_watchdog_task(struct cmac *mac);
669 684
670void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode); 685void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode);
671int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 686int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
diff --git a/drivers/net/cxgb3/cxgb3_main.c b/drivers/net/cxgb3/cxgb3_main.c
index 7ff834e45d6b..d55383610559 100644
--- a/drivers/net/cxgb3/cxgb3_main.c
+++ b/drivers/net/cxgb3/cxgb3_main.c
@@ -42,6 +42,7 @@
42#include <linux/workqueue.h> 42#include <linux/workqueue.h>
43#include <linux/proc_fs.h> 43#include <linux/proc_fs.h>
44#include <linux/rtnetlink.h> 44#include <linux/rtnetlink.h>
45#include <linux/firmware.h>
45#include <asm/uaccess.h> 46#include <asm/uaccess.h>
46 47
47#include "common.h" 48#include "common.h"
@@ -707,6 +708,28 @@ static void bind_qsets(struct adapter *adap)
707 } 708 }
708} 709}
709 710
711#define FW_FNAME "t3fw-%d.%d.bin"
712
713static int upgrade_fw(struct adapter *adap)
714{
715 int ret;
716 char buf[64];
717 const struct firmware *fw;
718 struct device *dev = &adap->pdev->dev;
719
720 snprintf(buf, sizeof(buf), FW_FNAME, FW_VERSION_MAJOR,
721 FW_VERSION_MINOR);
722 ret = request_firmware(&fw, buf, dev);
723 if (ret < 0) {
724 dev_err(dev, "could not upgrade firmware: unable to load %s\n",
725 buf);
726 return ret;
727 }
728 ret = t3_load_fw(adap, fw->data, fw->size);
729 release_firmware(fw);
730 return ret;
731}
732
710/** 733/**
711 * cxgb_up - enable the adapter 734 * cxgb_up - enable the adapter
712 * @adapter: adapter being enabled 735 * @adapter: adapter being enabled
@@ -723,6 +746,8 @@ static int cxgb_up(struct adapter *adap)
723 746
724 if (!(adap->flags & FULL_INIT_DONE)) { 747 if (!(adap->flags & FULL_INIT_DONE)) {
725 err = t3_check_fw_version(adap); 748 err = t3_check_fw_version(adap);
749 if (err == -EINVAL)
750 err = upgrade_fw(adap);
726 if (err) 751 if (err)
727 goto out; 752 goto out;
728 753
@@ -1031,7 +1056,11 @@ static char stats_strings[][ETH_GSTRING_LEN] = {
1031 "VLANinsertions ", 1056 "VLANinsertions ",
1032 "TxCsumOffload ", 1057 "TxCsumOffload ",
1033 "RxCsumGood ", 1058 "RxCsumGood ",
1034 "RxDrops " 1059 "RxDrops ",
1060
1061 "CheckTXEnToggled ",
1062 "CheckResets ",
1063
1035}; 1064};
1036 1065
1037static int get_stats_count(struct net_device *dev) 1066static int get_stats_count(struct net_device *dev)
@@ -1145,6 +1174,9 @@ static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1145 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM); 1174 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM);
1146 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD); 1175 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD);
1147 *data++ = s->rx_cong_drops; 1176 *data++ = s->rx_cong_drops;
1177
1178 *data++ = s->num_toggled;
1179 *data++ = s->num_resets;
1148} 1180}
1149 1181
1150static inline void reg_block_dump(struct adapter *ap, void *buf, 1182static inline void reg_block_dump(struct adapter *ap, void *buf,
@@ -1362,23 +1394,27 @@ static int set_rx_csum(struct net_device *dev, u32 data)
1362 1394
1363static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e) 1395static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1364{ 1396{
1365 struct adapter *adapter = dev->priv; 1397 const struct adapter *adapter = dev->priv;
1398 const struct port_info *pi = netdev_priv(dev);
1399 const struct qset_params *q = &adapter->params.sge.qset[pi->first_qset];
1366 1400
1367 e->rx_max_pending = MAX_RX_BUFFERS; 1401 e->rx_max_pending = MAX_RX_BUFFERS;
1368 e->rx_mini_max_pending = 0; 1402 e->rx_mini_max_pending = 0;
1369 e->rx_jumbo_max_pending = MAX_RX_JUMBO_BUFFERS; 1403 e->rx_jumbo_max_pending = MAX_RX_JUMBO_BUFFERS;
1370 e->tx_max_pending = MAX_TXQ_ENTRIES; 1404 e->tx_max_pending = MAX_TXQ_ENTRIES;
1371 1405
1372 e->rx_pending = adapter->params.sge.qset[0].fl_size; 1406 e->rx_pending = q->fl_size;
1373 e->rx_mini_pending = adapter->params.sge.qset[0].rspq_size; 1407 e->rx_mini_pending = q->rspq_size;
1374 e->rx_jumbo_pending = adapter->params.sge.qset[0].jumbo_size; 1408 e->rx_jumbo_pending = q->jumbo_size;
1375 e->tx_pending = adapter->params.sge.qset[0].txq_size[0]; 1409 e->tx_pending = q->txq_size[0];
1376} 1410}
1377 1411
1378static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e) 1412static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1379{ 1413{
1380 int i; 1414 int i;
1415 struct qset_params *q;
1381 struct adapter *adapter = dev->priv; 1416 struct adapter *adapter = dev->priv;
1417 const struct port_info *pi = netdev_priv(dev);
1382 1418
1383 if (e->rx_pending > MAX_RX_BUFFERS || 1419 if (e->rx_pending > MAX_RX_BUFFERS ||
1384 e->rx_jumbo_pending > MAX_RX_JUMBO_BUFFERS || 1420 e->rx_jumbo_pending > MAX_RX_JUMBO_BUFFERS ||
@@ -1393,9 +1429,8 @@ static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1393 if (adapter->flags & FULL_INIT_DONE) 1429 if (adapter->flags & FULL_INIT_DONE)
1394 return -EBUSY; 1430 return -EBUSY;
1395 1431
1396 for (i = 0; i < SGE_QSETS; ++i) { 1432 q = &adapter->params.sge.qset[pi->first_qset];
1397 struct qset_params *q = &adapter->params.sge.qset[i]; 1433 for (i = 0; i < pi->nqsets; ++i, ++q) {
1398
1399 q->rspq_size = e->rx_mini_pending; 1434 q->rspq_size = e->rx_mini_pending;
1400 q->fl_size = e->rx_pending; 1435 q->fl_size = e->rx_pending;
1401 q->jumbo_size = e->rx_jumbo_pending; 1436 q->jumbo_size = e->rx_jumbo_pending;
@@ -2067,6 +2102,40 @@ static void check_link_status(struct adapter *adapter)
2067 } 2102 }
2068} 2103}
2069 2104
2105static void check_t3b2_mac(struct adapter *adapter)
2106{
2107 int i;
2108
2109 rtnl_lock(); /* synchronize with ifdown */
2110 for_each_port(adapter, i) {
2111 struct net_device *dev = adapter->port[i];
2112 struct port_info *p = netdev_priv(dev);
2113 int status;
2114
2115 if (!netif_running(dev))
2116 continue;
2117
2118 status = 0;
2119 if (netif_running(dev))
2120 status = t3b2_mac_watchdog_task(&p->mac);
2121 if (status == 1)
2122 p->mac.stats.num_toggled++;
2123 else if (status == 2) {
2124 struct cmac *mac = &p->mac;
2125
2126 t3_mac_set_mtu(mac, dev->mtu);
2127 t3_mac_set_address(mac, 0, dev->dev_addr);
2128 cxgb_set_rxmode(dev);
2129 t3_link_start(&p->phy, mac, &p->link_config);
2130 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
2131 t3_port_intr_enable(adapter, p->port_id);
2132 p->mac.stats.num_resets++;
2133 }
2134 }
2135 rtnl_unlock();
2136}
2137
2138
2070static void t3_adap_check_task(struct work_struct *work) 2139static void t3_adap_check_task(struct work_struct *work)
2071{ 2140{
2072 struct adapter *adapter = container_of(work, struct adapter, 2141 struct adapter *adapter = container_of(work, struct adapter,
@@ -2087,6 +2156,9 @@ static void t3_adap_check_task(struct work_struct *work)
2087 adapter->check_task_cnt = 0; 2156 adapter->check_task_cnt = 0;
2088 } 2157 }
2089 2158
2159 if (p->rev == T3_REV_B2)
2160 check_t3b2_mac(adapter);
2161
2090 /* Schedule the next check update if any port is active. */ 2162 /* Schedule the next check update if any port is active. */
2091 spin_lock(&adapter->work_lock); 2163 spin_lock(&adapter->work_lock);
2092 if (adapter->open_device_map & PORT_MASK) 2164 if (adapter->open_device_map & PORT_MASK)
diff --git a/drivers/net/cxgb3/regs.h b/drivers/net/cxgb3/regs.h
index b56c5f52bcdc..b38629a244d0 100644
--- a/drivers/net/cxgb3/regs.h
+++ b/drivers/net/cxgb3/regs.h
@@ -1206,6 +1206,14 @@
1206 1206
1207#define A_TP_RX_TRC_KEY0 0x120 1207#define A_TP_RX_TRC_KEY0 0x120
1208 1208
1209#define A_TP_TX_DROP_CNT_CH0 0x12d
1210
1211#define S_TXDROPCNTCH0RCVD 0
1212#define M_TXDROPCNTCH0RCVD 0xffff
1213#define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
1214#define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & \
1215 M_TXDROPCNTCH0RCVD)
1216
1209#define A_ULPRX_CTL 0x500 1217#define A_ULPRX_CTL 0x500
1210 1218
1211#define S_ROUND_ROBIN 4 1219#define S_ROUND_ROBIN 4
@@ -1834,6 +1842,8 @@
1834#define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN) 1842#define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
1835#define F_TXPAUSEEN V_TXPAUSEEN(1U) 1843#define F_TXPAUSEEN V_TXPAUSEEN(1U)
1836 1844
1845#define A_XGM_TX_PAUSE_QUANTA 0x808
1846
1837#define A_XGM_RX_CTRL 0x80c 1847#define A_XGM_RX_CTRL 0x80c
1838 1848
1839#define S_RXEN 0 1849#define S_RXEN 0
@@ -1920,6 +1930,11 @@
1920 1930
1921#define A_XGM_TXFIFO_CFG 0x888 1931#define A_XGM_TXFIFO_CFG 0x888
1922 1932
1933#define S_TXIPG 13
1934#define M_TXIPG 0xff
1935#define V_TXIPG(x) ((x) << S_TXIPG)
1936#define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG)
1937
1923#define S_TXFIFOTHRESH 4 1938#define S_TXFIFOTHRESH 4
1924#define M_TXFIFOTHRESH 0x1ff 1939#define M_TXFIFOTHRESH 0x1ff
1925 1940
@@ -2190,6 +2205,13 @@
2190 2205
2191#define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4 2206#define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4
2192 2207
2208#define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8
2209
2210#define S_TXSPI4SOPCNT 16
2211#define M_TXSPI4SOPCNT 0xffff
2212#define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT)
2213#define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT)
2214
2193#define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac 2215#define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac
2194 2216
2195#define XGMAC0_1_BASE_ADDR 0xa00 2217#define XGMAC0_1_BASE_ADDR 0xa00
diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c
index eaa7a2e89a30..791ed6dc1943 100644
--- a/drivers/net/cxgb3/t3_hw.c
+++ b/drivers/net/cxgb3/t3_hw.c
@@ -681,7 +681,8 @@ enum {
681 SF_ERASE_SECTOR = 0xd8, /* erase sector */ 681 SF_ERASE_SECTOR = 0xd8, /* erase sector */
682 682
683 FW_FLASH_BOOT_ADDR = 0x70000, /* start address of FW in flash */ 683 FW_FLASH_BOOT_ADDR = 0x70000, /* start address of FW in flash */
684 FW_VERS_ADDR = 0x77ffc /* flash address holding FW version */ 684 FW_VERS_ADDR = 0x77ffc, /* flash address holding FW version */
685 FW_MIN_SIZE = 8 /* at least version and csum */
685}; 686};
686 687
687/** 688/**
@@ -935,7 +936,7 @@ int t3_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size)
935 const u32 *p = (const u32 *)fw_data; 936 const u32 *p = (const u32 *)fw_data;
936 int ret, addr, fw_sector = FW_FLASH_BOOT_ADDR >> 16; 937 int ret, addr, fw_sector = FW_FLASH_BOOT_ADDR >> 16;
937 938
938 if (size & 3) 939 if ((size & 3) || size < FW_MIN_SIZE)
939 return -EINVAL; 940 return -EINVAL;
940 if (size > FW_VERS_ADDR + 8 - FW_FLASH_BOOT_ADDR) 941 if (size > FW_VERS_ADDR + 8 - FW_FLASH_BOOT_ADDR)
941 return -EFBIG; 942 return -EFBIG;
@@ -3243,15 +3244,17 @@ void early_hw_init(struct adapter *adapter, const struct adapter_info *ai)
3243} 3244}
3244 3245
3245/* 3246/*
3246 * Reset the adapter. PCIe cards lose their config space during reset, PCI-X 3247 * Reset the adapter.
3248 * Older PCIe cards lose their config space during reset, PCI-X
3247 * ones don't. 3249 * ones don't.
3248 */ 3250 */
3249int t3_reset_adapter(struct adapter *adapter) 3251int t3_reset_adapter(struct adapter *adapter)
3250{ 3252{
3251 int i; 3253 int i, save_and_restore_pcie =
3254 adapter->params.rev < T3_REV_B2 && is_pcie(adapter);
3252 uint16_t devid = 0; 3255 uint16_t devid = 0;
3253 3256
3254 if (is_pcie(adapter)) 3257 if (save_and_restore_pcie)
3255 pci_save_state(adapter->pdev); 3258 pci_save_state(adapter->pdev);
3256 t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE); 3259 t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE);
3257 3260
@@ -3269,7 +3272,7 @@ int t3_reset_adapter(struct adapter *adapter)
3269 if (devid != 0x1425) 3272 if (devid != 0x1425)
3270 return -1; 3273 return -1;
3271 3274
3272 if (is_pcie(adapter)) 3275 if (save_and_restore_pcie)
3273 pci_restore_state(adapter->pdev); 3276 pci_restore_state(adapter->pdev);
3274 return 0; 3277 return 0;
3275} 3278}
diff --git a/drivers/net/cxgb3/xgmac.c b/drivers/net/cxgb3/xgmac.c
index 907a272ae32d..2b42c13ba8e0 100644
--- a/drivers/net/cxgb3/xgmac.c
+++ b/drivers/net/cxgb3/xgmac.c
@@ -124,9 +124,6 @@ int t3_mac_reset(struct cmac *mac)
124 xaui_serdes_reset(mac); 124 xaui_serdes_reset(mac);
125 } 125 }
126 126
127 if (adap->params.rev > 0)
128 t3_write_reg(adap, A_XGM_PAUSE_TIMER + oft, 0xf000);
129
130 val = F_MAC_RESET_; 127 val = F_MAC_RESET_;
131 if (is_10G(adap)) 128 if (is_10G(adap))
132 val |= F_PCS_RESET_; 129 val |= F_PCS_RESET_;
@@ -145,6 +142,58 @@ int t3_mac_reset(struct cmac *mac)
145 return 0; 142 return 0;
146} 143}
147 144
145int t3b2_mac_reset(struct cmac *mac)
146{
147 struct adapter *adap = mac->adapter;
148 unsigned int oft = mac->offset;
149 u32 val;
150
151 if (!macidx(mac))
152 t3_set_reg_field(adap, A_MPS_CFG, F_PORT0ACTIVE, 0);
153 else
154 t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0);
155
156 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
157 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
158
159 msleep(10);
160
161 /* Check for xgm Rx fifo empty */
162 if (t3_wait_op_done(adap, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT + oft,
163 0x80000000, 1, 5, 2)) {
164 CH_ERR(adap, "MAC %d Rx fifo drain failed\n",
165 macidx(mac));
166 return -1;
167 }
168
169 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0);
170 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
171
172 val = F_MAC_RESET_;
173 if (is_10G(adap))
174 val |= F_PCS_RESET_;
175 else if (uses_xaui(adap))
176 val |= F_PCS_RESET_ | F_XG2G_RESET_;
177 else
178 val |= F_RGMII_RESET_ | F_XG2G_RESET_;
179 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
180 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
181 if ((val & F_PCS_RESET_) && adap->params.rev) {
182 msleep(1);
183 t3b_pcs_reset(mac);
184 }
185 t3_write_reg(adap, A_XGM_RX_CFG + oft,
186 F_DISPAUSEFRAMES | F_EN1536BFRAMES |
187 F_RMFCS | F_ENJUMBO | F_ENHASHMCAST);
188
189 if (!macidx(mac))
190 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT0ACTIVE);
191 else
192 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT1ACTIVE);
193
194 return 0;
195}
196
148/* 197/*
149 * Set the exact match register 'idx' to recognize the given Ethernet address. 198 * Set the exact match register 'idx' to recognize the given Ethernet address.
150 */ 199 */
@@ -251,9 +300,11 @@ int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
251 * Adjust the PAUSE frame watermarks. We always set the LWM, and the 300 * Adjust the PAUSE frame watermarks. We always set the LWM, and the
252 * HWM only if flow-control is enabled. 301 * HWM only if flow-control is enabled.
253 */ 302 */
254 hwm = max(MAC_RXFIFO_SIZE - 3 * mtu, MAC_RXFIFO_SIZE / 2U); 303 hwm = max_t(unsigned int, MAC_RXFIFO_SIZE - 3 * mtu,
255 hwm = min(hwm, 3 * MAC_RXFIFO_SIZE / 4 + 1024); 304 MAC_RXFIFO_SIZE * 38 / 100);
256 lwm = hwm - 1024; 305 hwm = min(hwm, MAC_RXFIFO_SIZE - 8192);
306 lwm = min(3 * (int)mtu, MAC_RXFIFO_SIZE / 4);
307
257 v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset); 308 v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
258 v &= ~V_RXFIFOPAUSELWM(M_RXFIFOPAUSELWM); 309 v &= ~V_RXFIFOPAUSELWM(M_RXFIFOPAUSELWM);
259 v |= V_RXFIFOPAUSELWM(lwm / 8); 310 v |= V_RXFIFOPAUSELWM(lwm / 8);
@@ -270,7 +321,15 @@ int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
270 thres = mtu > thres ? (mtu - thres + 7) / 8 : 0; 321 thres = mtu > thres ? (mtu - thres + 7) / 8 : 0;
271 thres = max(thres, 8U); /* need at least 8 */ 322 thres = max(thres, 8U); /* need at least 8 */
272 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset, 323 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset,
273 V_TXFIFOTHRESH(M_TXFIFOTHRESH), V_TXFIFOTHRESH(thres)); 324 V_TXFIFOTHRESH(M_TXFIFOTHRESH) | V_TXIPG(M_TXIPG),
325 V_TXFIFOTHRESH(thres) | V_TXIPG(1));
326
327 if (adap->params.rev > 0)
328 t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,
329 (hwm - lwm) * 4 / 8);
330 t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,
331 MAC_RXFIFO_SIZE * 4 * 8 / 512);
332
274 return 0; 333 return 0;
275} 334}
276 335
@@ -298,12 +357,6 @@ int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc)
298 V_PORTSPEED(M_PORTSPEED), val); 357 V_PORTSPEED(M_PORTSPEED), val);
299 } 358 }
300 359
301 val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
302 val &= ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM);
303 if (fc & PAUSE_TX)
304 val |= V_RXFIFOPAUSEHWM(G_RXFIFOPAUSELWM(val) + 128); /* +1KB */
305 t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
306
307 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN, 360 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
308 (fc & PAUSE_RX) ? F_TXPAUSEEN : 0); 361 (fc & PAUSE_RX) ? F_TXPAUSEEN : 0);
309 return 0; 362 return 0;
@@ -318,9 +371,17 @@ int t3_mac_enable(struct cmac *mac, int which)
318 if (which & MAC_DIRECTION_TX) { 371 if (which & MAC_DIRECTION_TX) {
319 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN); 372 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
320 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx); 373 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
321 t3_write_reg(adap, A_TP_PIO_DATA, 0xbf000001); 374 t3_write_reg(adap, A_TP_PIO_DATA, 0xc0ede401);
322 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE); 375 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
323 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx); 376 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
377
378 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx);
379 mac->tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
380 A_TP_PIO_DATA)));
381 mac->xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
382 A_XGM_TX_SPI4_SOP_EOP_CNT)));
383 mac->txen = F_TXEN;
384 mac->toggle_cnt = 0;
324 } 385 }
325 if (which & MAC_DIRECTION_RX) 386 if (which & MAC_DIRECTION_RX)
326 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN); 387 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
@@ -337,13 +398,50 @@ int t3_mac_disable(struct cmac *mac, int which)
337 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx); 398 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
338 t3_write_reg(adap, A_TP_PIO_DATA, 0xc000001f); 399 t3_write_reg(adap, A_TP_PIO_DATA, 0xc000001f);
339 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE); 400 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
340 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 0); 401 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
402 mac->txen = 0;
341 } 403 }
342 if (which & MAC_DIRECTION_RX) 404 if (which & MAC_DIRECTION_RX)
343 t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0); 405 t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
344 return 0; 406 return 0;
345} 407}
346 408
409int t3b2_mac_watchdog_task(struct cmac *mac)
410{
411 struct adapter *adap = mac->adapter;
412 unsigned int tcnt, xcnt;
413 int status;
414
415 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + macidx(mac));
416 tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap, A_TP_PIO_DATA)));
417 xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
418 A_XGM_TX_SPI4_SOP_EOP_CNT +
419 mac->offset)));
420
421 if (tcnt != mac->tcnt && xcnt == 0 && mac->xcnt == 0) {
422 if (mac->toggle_cnt > 4) {
423 t3b2_mac_reset(mac);
424 mac->toggle_cnt = 0;
425 status = 2;
426 } else {
427 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
428 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset);
429 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset,
430 mac->txen);
431 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset);
432 mac->toggle_cnt++;
433 status = 1;
434 }
435 } else {
436 mac->toggle_cnt = 0;
437 status = 0;
438 }
439 mac->tcnt = tcnt;
440 mac->xcnt = xcnt;
441
442 return status;
443}
444
347/* 445/*
348 * This function is called periodically to accumulate the current values of the 446 * This function is called periodically to accumulate the current values of the
349 * RMON counters into the port statistics. Since the packet counters are only 447 * RMON counters into the port statistics. Since the packet counters are only
@@ -375,6 +473,11 @@ const struct mac_stats *t3_mac_update_stats(struct cmac *mac)
375 RMON_UPDATE(mac, rx_too_long, RX_OVERSIZE_FRAMES); 473 RMON_UPDATE(mac, rx_too_long, RX_OVERSIZE_FRAMES);
376 mac->stats.rx_too_long += RMON_READ(mac, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT); 474 mac->stats.rx_too_long += RMON_READ(mac, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT);
377 475
476 v = RMON_READ(mac, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT);
477 if (mac->adapter->params.rev == T3_REV_B2)
478 v &= 0x7fffffff;
479 mac->stats.rx_too_long += v;
480
378 RMON_UPDATE(mac, rx_frames_64, RX_64B_FRAMES); 481 RMON_UPDATE(mac, rx_frames_64, RX_64B_FRAMES);
379 RMON_UPDATE(mac, rx_frames_65_127, RX_65_127B_FRAMES); 482 RMON_UPDATE(mac, rx_frames_65_127, RX_65_127B_FRAMES);
380 RMON_UPDATE(mac, rx_frames_128_255, RX_128_255B_FRAMES); 483 RMON_UPDATE(mac, rx_frames_128_255, RX_128_255B_FRAMES);
diff --git a/drivers/net/ewrk3.c b/drivers/net/ewrk3.c
index c8c41f0a47d6..714ea1176ec7 100644
--- a/drivers/net/ewrk3.c
+++ b/drivers/net/ewrk3.c
@@ -414,10 +414,9 @@ ewrk3_hw_init(struct net_device *dev, u_long iobase)
414 icr &= 0x70; 414 icr &= 0x70;
415 outb(icr, EWRK3_ICR); /* Disable all the IRQs */ 415 outb(icr, EWRK3_ICR); /* Disable all the IRQs */
416 416
417 if (nicsr == (CSR_TXD | CSR_RXD)) 417 if (nicsr != (CSR_TXD | CSR_RXD))
418 return -ENXIO; 418 return -ENXIO;
419 419
420
421 /* Check that the EEPROM is alive and well and not living on Pluto... */ 420 /* Check that the EEPROM is alive and well and not living on Pluto... */
422 for (chksum = 0, i = 0; i < EEPROM_MAX; i += 2) { 421 for (chksum = 0, i = 0; i < EEPROM_MAX; i += 2) {
423 union { 422 union {
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index 1ee27c360a4b..c9f55bc57edb 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -1516,9 +1516,23 @@ static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1516 return 0; 1516 return 0;
1517} 1517}
1518 1518
1519static void mv643xx_eth_shutdown(struct platform_device *pdev)
1520{
1521 struct net_device *dev = platform_get_drvdata(pdev);
1522 struct mv643xx_private *mp = netdev_priv(dev);
1523 unsigned int port_num = mp->port_num;
1524
1525 /* Mask all interrupts on ethernet port */
1526 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
1527 mv_read (MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
1528
1529 eth_port_reset(port_num);
1530}
1531
1519static struct platform_driver mv643xx_eth_driver = { 1532static struct platform_driver mv643xx_eth_driver = {
1520 .probe = mv643xx_eth_probe, 1533 .probe = mv643xx_eth_probe,
1521 .remove = mv643xx_eth_remove, 1534 .remove = mv643xx_eth_remove,
1535 .shutdown = mv643xx_eth_shutdown,
1522 .driver = { 1536 .driver = {
1523 .name = MV643XX_ETH_NAME, 1537 .name = MV643XX_ETH_NAME,
1524 }, 1538 },
diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c
index ac02b3b60f92..b05b20ef8c0a 100644
--- a/drivers/net/myri10ge/myri10ge.c
+++ b/drivers/net/myri10ge/myri10ge.c
@@ -71,7 +71,7 @@
71#include "myri10ge_mcp.h" 71#include "myri10ge_mcp.h"
72#include "myri10ge_mcp_gen_header.h" 72#include "myri10ge_mcp_gen_header.h"
73 73
74#define MYRI10GE_VERSION_STR "1.2.0" 74#define MYRI10GE_VERSION_STR "1.3.0-1.226"
75 75
76MODULE_DESCRIPTION("Myricom 10G driver (10GbE)"); 76MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77MODULE_AUTHOR("Maintainer: help@myri.com"); 77MODULE_AUTHOR("Maintainer: help@myri.com");
@@ -234,7 +234,7 @@ static int myri10ge_msi = 1; /* enable msi by default */
234module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR); 234module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
235MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n"); 235MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
236 236
237static int myri10ge_intr_coal_delay = 25; 237static int myri10ge_intr_coal_delay = 75;
238module_param(myri10ge_intr_coal_delay, int, S_IRUGO); 238module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
239MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n"); 239MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
240 240
@@ -279,7 +279,7 @@ static int myri10ge_fill_thresh = 256;
279module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR); 279module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
280MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n"); 280MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
281 281
282static int myri10ge_wcfifo = 1; 282static int myri10ge_wcfifo = 0;
283module_param(myri10ge_wcfifo, int, S_IRUGO); 283module_param(myri10ge_wcfifo, int, S_IRUGO);
284MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n"); 284MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
285 285
@@ -905,6 +905,14 @@ myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
905 (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE)) { 905 (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE)) {
906 /* we can use part of previous page */ 906 /* we can use part of previous page */
907 get_page(rx->page); 907 get_page(rx->page);
908#if MYRI10GE_ALLOC_SIZE > 4096
909 /* Firmware cannot cross 4K boundary.. */
910 if ((rx->page_offset >> 12) !=
911 ((rx->page_offset + bytes - 1) >> 12)) {
912 rx->page_offset =
913 (rx->page_offset + bytes) & ~4095;
914 }
915#endif
908 } else { 916 } else {
909 /* we need a new page */ 917 /* we need a new page */
910 page = 918 page =
@@ -2483,6 +2491,8 @@ static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2483 2491
2484#define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7 2492#define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
2485#define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa 2493#define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
2494#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST 0x140
2495#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST 0x142
2486 2496
2487static void myri10ge_select_firmware(struct myri10ge_priv *mgp) 2497static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2488{ 2498{
@@ -2514,6 +2524,12 @@ static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2514 ((bridge->vendor == PCI_VENDOR_ID_SERVERWORKS 2524 ((bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2515 && bridge->device == 2525 && bridge->device ==
2516 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE) 2526 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE)
2527 /* ServerWorks HT2100 */
2528 || (bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2529 && bridge->device >=
2530 PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST
2531 && bridge->device <=
2532 PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST)
2517 /* All Intel E5000 PCIE ports */ 2533 /* All Intel E5000 PCIE ports */
2518 || (bridge->vendor == PCI_VENDOR_ID_INTEL 2534 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2519 && bridge->device >= 2535 && bridge->device >=
diff --git a/drivers/net/pci-skeleton.c b/drivers/net/pci-skeleton.c
index 00ca0fdb837b..6ca4e4fa6b88 100644
--- a/drivers/net/pci-skeleton.c
+++ b/drivers/net/pci-skeleton.c
@@ -710,8 +710,8 @@ match:
710 tp->chipset, 710 tp->chipset,
711 rtl_chip_info[tp->chipset].name); 711 rtl_chip_info[tp->chipset].name);
712 712
713 i = register_netdev (dev); 713 rc = register_netdev (dev);
714 if (i) 714 if (rc)
715 goto err_out_unmap; 715 goto err_out_unmap;
716 716
717 DPRINTK ("EXIT, returning 0\n"); 717 DPRINTK ("EXIT, returning 0\n");
diff --git a/drivers/net/saa9730.c b/drivers/net/saa9730.c
index b269513cde45..143958f1ef0a 100644
--- a/drivers/net/saa9730.c
+++ b/drivers/net/saa9730.c
@@ -64,37 +64,37 @@ static unsigned int pci_irq_line;
64 64
65static void evm_saa9730_enable_lan_int(struct lan_saa9730_private *lp) 65static void evm_saa9730_enable_lan_int(struct lan_saa9730_private *lp)
66{ 66{
67 outl(readl(&lp->evm_saa9730_regs->InterruptBlock1) | EVM_LAN_INT, 67 writel(readl(&lp->evm_saa9730_regs->InterruptBlock1) | EVM_LAN_INT,
68 &lp->evm_saa9730_regs->InterruptBlock1); 68 &lp->evm_saa9730_regs->InterruptBlock1);
69 outl(readl(&lp->evm_saa9730_regs->InterruptStatus1) | EVM_LAN_INT, 69 writel(readl(&lp->evm_saa9730_regs->InterruptStatus1) | EVM_LAN_INT,
70 &lp->evm_saa9730_regs->InterruptStatus1); 70 &lp->evm_saa9730_regs->InterruptStatus1);
71 outl(readl(&lp->evm_saa9730_regs->InterruptEnable1) | EVM_LAN_INT | 71 writel(readl(&lp->evm_saa9730_regs->InterruptEnable1) | EVM_LAN_INT |
72 EVM_MASTER_EN, &lp->evm_saa9730_regs->InterruptEnable1); 72 EVM_MASTER_EN, &lp->evm_saa9730_regs->InterruptEnable1);
73} 73}
74 74
75static void evm_saa9730_disable_lan_int(struct lan_saa9730_private *lp) 75static void evm_saa9730_disable_lan_int(struct lan_saa9730_private *lp)
76{ 76{
77 outl(readl(&lp->evm_saa9730_regs->InterruptBlock1) & ~EVM_LAN_INT, 77 writel(readl(&lp->evm_saa9730_regs->InterruptBlock1) & ~EVM_LAN_INT,
78 &lp->evm_saa9730_regs->InterruptBlock1); 78 &lp->evm_saa9730_regs->InterruptBlock1);
79 outl(readl(&lp->evm_saa9730_regs->InterruptEnable1) & ~EVM_LAN_INT, 79 writel(readl(&lp->evm_saa9730_regs->InterruptEnable1) & ~EVM_LAN_INT,
80 &lp->evm_saa9730_regs->InterruptEnable1); 80 &lp->evm_saa9730_regs->InterruptEnable1);
81} 81}
82 82
83static void evm_saa9730_clear_lan_int(struct lan_saa9730_private *lp) 83static void evm_saa9730_clear_lan_int(struct lan_saa9730_private *lp)
84{ 84{
85 outl(EVM_LAN_INT, &lp->evm_saa9730_regs->InterruptStatus1); 85 writel(EVM_LAN_INT, &lp->evm_saa9730_regs->InterruptStatus1);
86} 86}
87 87
88static void evm_saa9730_block_lan_int(struct lan_saa9730_private *lp) 88static void evm_saa9730_block_lan_int(struct lan_saa9730_private *lp)
89{ 89{
90 outl(readl(&lp->evm_saa9730_regs->InterruptBlock1) & ~EVM_LAN_INT, 90 writel(readl(&lp->evm_saa9730_regs->InterruptBlock1) & ~EVM_LAN_INT,
91 &lp->evm_saa9730_regs->InterruptBlock1); 91 &lp->evm_saa9730_regs->InterruptBlock1);
92} 92}
93 93
94static void evm_saa9730_unblock_lan_int(struct lan_saa9730_private *lp) 94static void evm_saa9730_unblock_lan_int(struct lan_saa9730_private *lp)
95{ 95{
96 outl(readl(&lp->evm_saa9730_regs->InterruptBlock1) | EVM_LAN_INT, 96 writel(readl(&lp->evm_saa9730_regs->InterruptBlock1) | EVM_LAN_INT,
97 &lp->evm_saa9730_regs->InterruptBlock1); 97 &lp->evm_saa9730_regs->InterruptBlock1);
98} 98}
99 99
100static void __attribute_used__ show_saa9730_regs(struct lan_saa9730_private *lp) 100static void __attribute_used__ show_saa9730_regs(struct lan_saa9730_private *lp)
@@ -147,7 +147,7 @@ static void __attribute_used__ show_saa9730_regs(struct lan_saa9730_private *lp)
147 printk("lp->lan_saa9730_regs->RxStatus = %x\n", 147 printk("lp->lan_saa9730_regs->RxStatus = %x\n",
148 readl(&lp->lan_saa9730_regs->RxStatus)); 148 readl(&lp->lan_saa9730_regs->RxStatus));
149 for (i = 0; i < LAN_SAA9730_CAM_DWORDS; i++) { 149 for (i = 0; i < LAN_SAA9730_CAM_DWORDS; i++) {
150 outl(i, &lp->lan_saa9730_regs->CamAddress); 150 writel(i, &lp->lan_saa9730_regs->CamAddress);
151 printk("lp->lan_saa9730_regs->CamData = %x\n", 151 printk("lp->lan_saa9730_regs->CamData = %x\n",
152 readl(&lp->lan_saa9730_regs->CamData)); 152 readl(&lp->lan_saa9730_regs->CamData));
153 } 153 }
@@ -288,28 +288,27 @@ static int lan_saa9730_allocate_buffers(struct pci_dev *pdev,
288 * Set rx buffer A and rx buffer B to point to the first two buffer 288 * Set rx buffer A and rx buffer B to point to the first two buffer
289 * spaces. 289 * spaces.
290 */ 290 */
291 outl(lp->dma_addr + rxoffset, 291 writel(lp->dma_addr + rxoffset, &lp->lan_saa9730_regs->RxBuffA);
292 &lp->lan_saa9730_regs->RxBuffA); 292 writel(lp->dma_addr + rxoffset +
293 outl(lp->dma_addr + rxoffset + 293 LAN_SAA9730_PACKET_SIZE * LAN_SAA9730_RCV_Q_SIZE,
294 LAN_SAA9730_PACKET_SIZE * LAN_SAA9730_RCV_Q_SIZE, 294 &lp->lan_saa9730_regs->RxBuffB);
295 &lp->lan_saa9730_regs->RxBuffB);
296 295
297 /* 296 /*
298 * Set txm_buf_a and txm_buf_b to point to the first two buffer 297 * Set txm_buf_a and txm_buf_b to point to the first two buffer
299 * space 298 * space
300 */ 299 */
301 outl(lp->dma_addr + txoffset, 300 writel(lp->dma_addr + txoffset,
302 &lp->lan_saa9730_regs->TxBuffA); 301 &lp->lan_saa9730_regs->TxBuffA);
303 outl(lp->dma_addr + txoffset + 302 writel(lp->dma_addr + txoffset +
304 LAN_SAA9730_PACKET_SIZE * LAN_SAA9730_TXM_Q_SIZE, 303 LAN_SAA9730_PACKET_SIZE * LAN_SAA9730_TXM_Q_SIZE,
305 &lp->lan_saa9730_regs->TxBuffB); 304 &lp->lan_saa9730_regs->TxBuffB);
306 305
307 /* Set packet number */ 306 /* Set packet number */
308 outl((lp->DmaRcvPackets << PK_COUNT_RX_A_SHF) | 307 writel((lp->DmaRcvPackets << PK_COUNT_RX_A_SHF) |
309 (lp->DmaRcvPackets << PK_COUNT_RX_B_SHF) | 308 (lp->DmaRcvPackets << PK_COUNT_RX_B_SHF) |
310 (lp->DmaTxmPackets << PK_COUNT_TX_A_SHF) | 309 (lp->DmaTxmPackets << PK_COUNT_TX_A_SHF) |
311 (lp->DmaTxmPackets << PK_COUNT_TX_B_SHF), 310 (lp->DmaTxmPackets << PK_COUNT_TX_B_SHF),
312 &lp->lan_saa9730_regs->PacketCount); 311 &lp->lan_saa9730_regs->PacketCount);
313 312
314 return 0; 313 return 0;
315 314
@@ -326,10 +325,10 @@ static int lan_saa9730_cam_load(struct lan_saa9730_private *lp)
326 325
327 for (i = 0; i < LAN_SAA9730_CAM_DWORDS; i++) { 326 for (i = 0; i < LAN_SAA9730_CAM_DWORDS; i++) {
328 /* First set address to where data is written */ 327 /* First set address to where data is written */
329 outl(i, &lp->lan_saa9730_regs->CamAddress); 328 writel(i, &lp->lan_saa9730_regs->CamAddress);
330 outl((NetworkAddress[0] << 24) | (NetworkAddress[1] << 16) 329 writel((NetworkAddress[0] << 24) | (NetworkAddress[1] << 16) |
331 | (NetworkAddress[2] << 8) | NetworkAddress[3], 330 (NetworkAddress[2] << 8) | NetworkAddress[3],
332 &lp->lan_saa9730_regs->CamData); 331 &lp->lan_saa9730_regs->CamData);
333 NetworkAddress += 4; 332 NetworkAddress += 4;
334 } 333 }
335 return 0; 334 return 0;
@@ -365,8 +364,8 @@ static int lan_saa9730_mii_init(struct lan_saa9730_private *lp)
365 } 364 }
366 365
367 /* Now set the control and address register. */ 366 /* Now set the control and address register. */
368 outl(MD_CA_BUSY | PHY_STATUS | PHY_ADDRESS << MD_CA_PHY_SHF, 367 writel(MD_CA_BUSY | PHY_STATUS | PHY_ADDRESS << MD_CA_PHY_SHF,
369 &lp->lan_saa9730_regs->StationMgmtCtl); 368 &lp->lan_saa9730_regs->StationMgmtCtl);
370 369
371 /* check link status, spin here till station is not busy */ 370 /* check link status, spin here till station is not busy */
372 i = 0; 371 i = 0;
@@ -391,23 +390,23 @@ static int lan_saa9730_mii_init(struct lan_saa9730_private *lp)
391 /* Link is down, reset the PHY first. */ 390 /* Link is down, reset the PHY first. */
392 391
393 /* set PHY address = 'CONTROL' */ 392 /* set PHY address = 'CONTROL' */
394 outl(PHY_ADDRESS << MD_CA_PHY_SHF | MD_CA_WR | PHY_CONTROL, 393 writel(PHY_ADDRESS << MD_CA_PHY_SHF | MD_CA_WR | PHY_CONTROL,
395 &lp->lan_saa9730_regs->StationMgmtCtl); 394 &lp->lan_saa9730_regs->StationMgmtCtl);
396 395
397 /* Wait for 1 ms. */ 396 /* Wait for 1 ms. */
398 mdelay(1); 397 mdelay(1);
399 398
400 /* set 'CONTROL' = force reset and renegotiate */ 399 /* set 'CONTROL' = force reset and renegotiate */
401 outl(PHY_CONTROL_RESET | PHY_CONTROL_AUTO_NEG | 400 writel(PHY_CONTROL_RESET | PHY_CONTROL_AUTO_NEG |
402 PHY_CONTROL_RESTART_AUTO_NEG, 401 PHY_CONTROL_RESTART_AUTO_NEG,
403 &lp->lan_saa9730_regs->StationMgmtData); 402 &lp->lan_saa9730_regs->StationMgmtData);
404 403
405 /* Wait for 50 ms. */ 404 /* Wait for 50 ms. */
406 mdelay(50); 405 mdelay(50);
407 406
408 /* set 'BUSY' to start operation */ 407 /* set 'BUSY' to start operation */
409 outl(MD_CA_BUSY | PHY_ADDRESS << MD_CA_PHY_SHF | MD_CA_WR | 408 writel(MD_CA_BUSY | PHY_ADDRESS << MD_CA_PHY_SHF | MD_CA_WR |
410 PHY_CONTROL, &lp->lan_saa9730_regs->StationMgmtCtl); 409 PHY_CONTROL, &lp->lan_saa9730_regs->StationMgmtCtl);
411 410
412 /* await completion */ 411 /* await completion */
413 i = 0; 412 i = 0;
@@ -427,9 +426,9 @@ static int lan_saa9730_mii_init(struct lan_saa9730_private *lp)
427 426
428 for (l = 0; l < 2; l++) { 427 for (l = 0; l < 2; l++) {
429 /* set PHY address = 'STATUS' */ 428 /* set PHY address = 'STATUS' */
430 outl(MD_CA_BUSY | PHY_ADDRESS << MD_CA_PHY_SHF | 429 writel(MD_CA_BUSY | PHY_ADDRESS << MD_CA_PHY_SHF |
431 PHY_STATUS, 430 PHY_STATUS,
432 &lp->lan_saa9730_regs->StationMgmtCtl); 431 &lp->lan_saa9730_regs->StationMgmtCtl);
433 432
434 /* await completion */ 433 /* await completion */
435 i = 0; 434 i = 0;
@@ -462,35 +461,35 @@ static int lan_saa9730_mii_init(struct lan_saa9730_private *lp)
462static int lan_saa9730_control_init(struct lan_saa9730_private *lp) 461static int lan_saa9730_control_init(struct lan_saa9730_private *lp)
463{ 462{
464 /* Initialize DMA control register. */ 463 /* Initialize DMA control register. */
465 outl((LANMB_ANY << DMA_CTL_MAX_XFER_SHF) | 464 writel((LANMB_ANY << DMA_CTL_MAX_XFER_SHF) |
466 (LANEND_LITTLE << DMA_CTL_ENDIAN_SHF) | 465 (LANEND_LITTLE << DMA_CTL_ENDIAN_SHF) |
467 (LAN_SAA9730_RCV_Q_INT_THRESHOLD << DMA_CTL_RX_INT_COUNT_SHF) 466 (LAN_SAA9730_RCV_Q_INT_THRESHOLD << DMA_CTL_RX_INT_COUNT_SHF)
468 | DMA_CTL_RX_INT_TO_EN | DMA_CTL_RX_INT_EN | 467 | DMA_CTL_RX_INT_TO_EN | DMA_CTL_RX_INT_EN |
469 DMA_CTL_MAC_RX_INT_EN | DMA_CTL_MAC_TX_INT_EN, 468 DMA_CTL_MAC_RX_INT_EN | DMA_CTL_MAC_TX_INT_EN,
470 &lp->lan_saa9730_regs->LanDmaCtl); 469 &lp->lan_saa9730_regs->LanDmaCtl);
471 470
472 /* Initial MAC control register. */ 471 /* Initial MAC control register. */
473 outl((MACCM_MII << MAC_CONTROL_CONN_SHF) | MAC_CONTROL_FULL_DUP, 472 writel((MACCM_MII << MAC_CONTROL_CONN_SHF) | MAC_CONTROL_FULL_DUP,
474 &lp->lan_saa9730_regs->MacCtl); 473 &lp->lan_saa9730_regs->MacCtl);
475 474
476 /* Initialize CAM control register. */ 475 /* Initialize CAM control register. */
477 outl(CAM_CONTROL_COMP_EN | CAM_CONTROL_BROAD_ACC, 476 writel(CAM_CONTROL_COMP_EN | CAM_CONTROL_BROAD_ACC,
478 &lp->lan_saa9730_regs->CamCtl); 477 &lp->lan_saa9730_regs->CamCtl);
479 478
480 /* 479 /*
481 * Initialize CAM enable register, only turn on first entry, should 480 * Initialize CAM enable register, only turn on first entry, should
482 * contain own addr. 481 * contain own addr.
483 */ 482 */
484 outl(0x0001, &lp->lan_saa9730_regs->CamEnable); 483 writel(0x0001, &lp->lan_saa9730_regs->CamEnable);
485 484
486 /* Initialize Tx control register */ 485 /* Initialize Tx control register */
487 outl(TX_CTL_EN_COMP, &lp->lan_saa9730_regs->TxCtl); 486 writel(TX_CTL_EN_COMP, &lp->lan_saa9730_regs->TxCtl);
488 487
489 /* Initialize Rcv control register */ 488 /* Initialize Rcv control register */
490 outl(RX_CTL_STRIP_CRC, &lp->lan_saa9730_regs->RxCtl); 489 writel(RX_CTL_STRIP_CRC, &lp->lan_saa9730_regs->RxCtl);
491 490
492 /* Reset DMA engine */ 491 /* Reset DMA engine */
493 outl(DMA_TEST_SW_RESET, &lp->lan_saa9730_regs->DmaTest); 492 writel(DMA_TEST_SW_RESET, &lp->lan_saa9730_regs->DmaTest);
494 493
495 return 0; 494 return 0;
496} 495}
@@ -500,14 +499,14 @@ static int lan_saa9730_stop(struct lan_saa9730_private *lp)
500 int i; 499 int i;
501 500
502 /* Stop DMA first */ 501 /* Stop DMA first */
503 outl(readl(&lp->lan_saa9730_regs->LanDmaCtl) & 502 writel(readl(&lp->lan_saa9730_regs->LanDmaCtl) &
504 ~(DMA_CTL_EN_TX_DMA | DMA_CTL_EN_RX_DMA), 503 ~(DMA_CTL_EN_TX_DMA | DMA_CTL_EN_RX_DMA),
505 &lp->lan_saa9730_regs->LanDmaCtl); 504 &lp->lan_saa9730_regs->LanDmaCtl);
506 505
507 /* Set the SW Reset bits in DMA and MAC control registers */ 506 /* Set the SW Reset bits in DMA and MAC control registers */
508 outl(DMA_TEST_SW_RESET, &lp->lan_saa9730_regs->DmaTest); 507 writel(DMA_TEST_SW_RESET, &lp->lan_saa9730_regs->DmaTest);
509 outl(readl(&lp->lan_saa9730_regs->MacCtl) | MAC_CONTROL_RESET, 508 writel(readl(&lp->lan_saa9730_regs->MacCtl) | MAC_CONTROL_RESET,
510 &lp->lan_saa9730_regs->MacCtl); 509 &lp->lan_saa9730_regs->MacCtl);
511 510
512 /* 511 /*
513 * Wait for MAC reset to have finished. The reset bit is auto cleared 512 * Wait for MAC reset to have finished. The reset bit is auto cleared
@@ -532,8 +531,8 @@ static int lan_saa9730_dma_init(struct lan_saa9730_private *lp)
532 /* Stop lan controller. */ 531 /* Stop lan controller. */
533 lan_saa9730_stop(lp); 532 lan_saa9730_stop(lp);
534 533
535 outl(LAN_SAA9730_DEFAULT_TIME_OUT_CNT, 534 writel(LAN_SAA9730_DEFAULT_TIME_OUT_CNT,
536 &lp->lan_saa9730_regs->Timeout); 535 &lp->lan_saa9730_regs->Timeout);
537 536
538 return 0; 537 return 0;
539} 538}
@@ -552,19 +551,19 @@ static int lan_saa9730_start(struct lan_saa9730_private *lp)
552 lp->PendingTxmPacketIndex = 0; 551 lp->PendingTxmPacketIndex = 0;
553 lp->PendingTxmBufferIndex = 0; 552 lp->PendingTxmBufferIndex = 0;
554 553
555 outl(readl(&lp->lan_saa9730_regs->LanDmaCtl) | DMA_CTL_EN_TX_DMA | 554 writel(readl(&lp->lan_saa9730_regs->LanDmaCtl) | DMA_CTL_EN_TX_DMA |
556 DMA_CTL_EN_RX_DMA, &lp->lan_saa9730_regs->LanDmaCtl); 555 DMA_CTL_EN_RX_DMA, &lp->lan_saa9730_regs->LanDmaCtl);
557 556
558 /* For Tx, turn on MAC then DMA */ 557 /* For Tx, turn on MAC then DMA */
559 outl(readl(&lp->lan_saa9730_regs->TxCtl) | TX_CTL_TX_EN, 558 writel(readl(&lp->lan_saa9730_regs->TxCtl) | TX_CTL_TX_EN,
560 &lp->lan_saa9730_regs->TxCtl); 559 &lp->lan_saa9730_regs->TxCtl);
561 560
562 /* For Rx, turn on DMA then MAC */ 561 /* For Rx, turn on DMA then MAC */
563 outl(readl(&lp->lan_saa9730_regs->RxCtl) | RX_CTL_RX_EN, 562 writel(readl(&lp->lan_saa9730_regs->RxCtl) | RX_CTL_RX_EN,
564 &lp->lan_saa9730_regs->RxCtl); 563 &lp->lan_saa9730_regs->RxCtl);
565 564
566 /* Set Ok2Use to let hardware own the buffers. */ 565 /* Set Ok2Use to let hardware own the buffers. */
567 outl(OK2USE_RX_A | OK2USE_RX_B, &lp->lan_saa9730_regs->Ok2Use); 566 writel(OK2USE_RX_A | OK2USE_RX_B, &lp->lan_saa9730_regs->Ok2Use);
568 567
569 return 0; 568 return 0;
570} 569}
@@ -587,7 +586,7 @@ static int lan_saa9730_tx(struct net_device *dev)
587 printk("lan_saa9730_tx interrupt\n"); 586 printk("lan_saa9730_tx interrupt\n");
588 587
589 /* Clear interrupt. */ 588 /* Clear interrupt. */
590 outl(DMA_STATUS_MAC_TX_INT, &lp->lan_saa9730_regs->DmaStatus); 589 writel(DMA_STATUS_MAC_TX_INT, &lp->lan_saa9730_regs->DmaStatus);
591 590
592 while (1) { 591 while (1) {
593 pPacket = lp->TxmBuffer[lp->PendingTxmBufferIndex] 592 pPacket = lp->TxmBuffer[lp->PendingTxmBufferIndex]
@@ -660,8 +659,8 @@ static int lan_saa9730_rx(struct net_device *dev)
660 printk("lan_saa9730_rx interrupt\n"); 659 printk("lan_saa9730_rx interrupt\n");
661 660
662 /* Clear receive interrupts. */ 661 /* Clear receive interrupts. */
663 outl(DMA_STATUS_MAC_RX_INT | DMA_STATUS_RX_INT | 662 writel(DMA_STATUS_MAC_RX_INT | DMA_STATUS_RX_INT |
664 DMA_STATUS_RX_TO_INT, &lp->lan_saa9730_regs->DmaStatus); 663 DMA_STATUS_RX_TO_INT, &lp->lan_saa9730_regs->DmaStatus);
665 664
666 /* Address next packet */ 665 /* Address next packet */
667 BufferIndex = lp->NextRcvBufferIndex; 666 BufferIndex = lp->NextRcvBufferIndex;
@@ -725,8 +724,8 @@ static int lan_saa9730_rx(struct net_device *dev)
725 *pPacket = cpu_to_le32(RXSF_READY << RX_STAT_CTL_OWNER_SHF); 724 *pPacket = cpu_to_le32(RXSF_READY << RX_STAT_CTL_OWNER_SHF);
726 725
727 /* Make sure A or B is available to hardware as appropriate. */ 726 /* Make sure A or B is available to hardware as appropriate. */
728 outl(BufferIndex ? OK2USE_RX_B : OK2USE_RX_A, 727 writel(BufferIndex ? OK2USE_RX_B : OK2USE_RX_A,
729 &lp->lan_saa9730_regs->Ok2Use); 728 &lp->lan_saa9730_regs->Ok2Use);
730 729
731 /* Go to next packet in sequence. */ 730 /* Go to next packet in sequence. */
732 lp->NextRcvPacketIndex++; 731 lp->NextRcvPacketIndex++;
@@ -844,8 +843,8 @@ static int lan_saa9730_write(struct lan_saa9730_private *lp,
844 (len << TX_STAT_CTL_LENGTH_SHF)); 843 (len << TX_STAT_CTL_LENGTH_SHF));
845 844
846 /* Make sure A or B is available to hardware as appropriate. */ 845 /* Make sure A or B is available to hardware as appropriate. */
847 outl(BufferIndex ? OK2USE_TX_B : OK2USE_TX_A, 846 writel(BufferIndex ? OK2USE_TX_B : OK2USE_TX_A,
848 &lp->lan_saa9730_regs->Ok2Use); 847 &lp->lan_saa9730_regs->Ok2Use);
849 848
850 return 0; 849 return 0;
851} 850}
@@ -938,15 +937,15 @@ static void lan_saa9730_set_multicast(struct net_device *dev)
938 937
939 if (dev->flags & IFF_PROMISC) { 938 if (dev->flags & IFF_PROMISC) {
940 /* accept all packets */ 939 /* accept all packets */
941 outl(CAM_CONTROL_COMP_EN | CAM_CONTROL_STATION_ACC | 940 writel(CAM_CONTROL_COMP_EN | CAM_CONTROL_STATION_ACC |
942 CAM_CONTROL_GROUP_ACC | CAM_CONTROL_BROAD_ACC, 941 CAM_CONTROL_GROUP_ACC | CAM_CONTROL_BROAD_ACC,
943 &lp->lan_saa9730_regs->CamCtl); 942 &lp->lan_saa9730_regs->CamCtl);
944 } else { 943 } else {
945 if (dev->flags & IFF_ALLMULTI) { 944 if (dev->flags & IFF_ALLMULTI) {
946 /* accept all multicast packets */ 945 /* accept all multicast packets */
947 outl(CAM_CONTROL_COMP_EN | CAM_CONTROL_GROUP_ACC | 946 writel(CAM_CONTROL_COMP_EN | CAM_CONTROL_GROUP_ACC |
948 CAM_CONTROL_BROAD_ACC, 947 CAM_CONTROL_BROAD_ACC,
949 &lp->lan_saa9730_regs->CamCtl); 948 &lp->lan_saa9730_regs->CamCtl);
950 } else { 949 } else {
951 /* 950 /*
952 * Will handle the multicast stuff later. -carstenl 951 * Will handle the multicast stuff later. -carstenl
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index 8fecf1b817f7..39c6677dff5e 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -105,7 +105,8 @@ static const int txqaddr[] = { Q_XA1, Q_XA2 };
105static const int rxqaddr[] = { Q_R1, Q_R2 }; 105static const int rxqaddr[] = { Q_R1, Q_R2 };
106static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F }; 106static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F }; 107static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
108static const u32 irqmask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F }; 108static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
109static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
109 110
110static int skge_get_regs_len(struct net_device *dev) 111static int skge_get_regs_len(struct net_device *dev)
111{ 112{
@@ -671,7 +672,7 @@ static void skge_led(struct skge_port *skge, enum led_mode mode)
671 struct skge_hw *hw = skge->hw; 672 struct skge_hw *hw = skge->hw;
672 int port = skge->port; 673 int port = skge->port;
673 674
674 mutex_lock(&hw->phy_mutex); 675 spin_lock_bh(&hw->phy_lock);
675 if (hw->chip_id == CHIP_ID_GENESIS) { 676 if (hw->chip_id == CHIP_ID_GENESIS) {
676 switch (mode) { 677 switch (mode) {
677 case LED_MODE_OFF: 678 case LED_MODE_OFF:
@@ -742,7 +743,7 @@ static void skge_led(struct skge_port *skge, enum led_mode mode)
742 PHY_M_LED_MO_RX(MO_LED_ON)); 743 PHY_M_LED_MO_RX(MO_LED_ON));
743 } 744 }
744 } 745 }
745 mutex_unlock(&hw->phy_mutex); 746 spin_unlock_bh(&hw->phy_lock);
746} 747}
747 748
748/* blink LED's for finding board */ 749/* blink LED's for finding board */
@@ -1316,7 +1317,7 @@ static void xm_phy_init(struct skge_port *skge)
1316 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl); 1317 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1317 1318
1318 /* Poll PHY for status changes */ 1319 /* Poll PHY for status changes */
1319 schedule_delayed_work(&skge->link_thread, LINK_HZ); 1320 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1320} 1321}
1321 1322
1322static void xm_check_link(struct net_device *dev) 1323static void xm_check_link(struct net_device *dev)
@@ -1391,10 +1392,9 @@ static void xm_check_link(struct net_device *dev)
1391 * Since internal PHY is wired to a level triggered pin, can't 1392 * Since internal PHY is wired to a level triggered pin, can't
1392 * get an interrupt when carrier is detected. 1393 * get an interrupt when carrier is detected.
1393 */ 1394 */
1394static void xm_link_timer(struct work_struct *work) 1395static void xm_link_timer(unsigned long arg)
1395{ 1396{
1396 struct skge_port *skge = 1397 struct skge_port *skge = (struct skge_port *) arg;
1397 container_of(work, struct skge_port, link_thread.work);
1398 struct net_device *dev = skge->netdev; 1398 struct net_device *dev = skge->netdev;
1399 struct skge_hw *hw = skge->hw; 1399 struct skge_hw *hw = skge->hw;
1400 int port = skge->port; 1400 int port = skge->port;
@@ -1414,13 +1414,13 @@ static void xm_link_timer(struct work_struct *work)
1414 goto nochange; 1414 goto nochange;
1415 } 1415 }
1416 1416
1417 mutex_lock(&hw->phy_mutex); 1417 spin_lock(&hw->phy_lock);
1418 xm_check_link(dev); 1418 xm_check_link(dev);
1419 mutex_unlock(&hw->phy_mutex); 1419 spin_unlock(&hw->phy_lock);
1420 1420
1421nochange: 1421nochange:
1422 if (netif_running(dev)) 1422 if (netif_running(dev))
1423 schedule_delayed_work(&skge->link_thread, LINK_HZ); 1423 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1424} 1424}
1425 1425
1426static void genesis_mac_init(struct skge_hw *hw, int port) 1426static void genesis_mac_init(struct skge_hw *hw, int port)
@@ -2323,7 +2323,7 @@ static void skge_phy_reset(struct skge_port *skge)
2323 netif_stop_queue(skge->netdev); 2323 netif_stop_queue(skge->netdev);
2324 netif_carrier_off(skge->netdev); 2324 netif_carrier_off(skge->netdev);
2325 2325
2326 mutex_lock(&hw->phy_mutex); 2326 spin_lock_bh(&hw->phy_lock);
2327 if (hw->chip_id == CHIP_ID_GENESIS) { 2327 if (hw->chip_id == CHIP_ID_GENESIS) {
2328 genesis_reset(hw, port); 2328 genesis_reset(hw, port);
2329 genesis_mac_init(hw, port); 2329 genesis_mac_init(hw, port);
@@ -2331,7 +2331,7 @@ static void skge_phy_reset(struct skge_port *skge)
2331 yukon_reset(hw, port); 2331 yukon_reset(hw, port);
2332 yukon_init(hw, port); 2332 yukon_init(hw, port);
2333 } 2333 }
2334 mutex_unlock(&hw->phy_mutex); 2334 spin_unlock_bh(&hw->phy_lock);
2335 2335
2336 dev->set_multicast_list(dev); 2336 dev->set_multicast_list(dev);
2337} 2337}
@@ -2354,12 +2354,12 @@ static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2354 /* fallthru */ 2354 /* fallthru */
2355 case SIOCGMIIREG: { 2355 case SIOCGMIIREG: {
2356 u16 val = 0; 2356 u16 val = 0;
2357 mutex_lock(&hw->phy_mutex); 2357 spin_lock_bh(&hw->phy_lock);
2358 if (hw->chip_id == CHIP_ID_GENESIS) 2358 if (hw->chip_id == CHIP_ID_GENESIS)
2359 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); 2359 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2360 else 2360 else
2361 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); 2361 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2362 mutex_unlock(&hw->phy_mutex); 2362 spin_unlock_bh(&hw->phy_lock);
2363 data->val_out = val; 2363 data->val_out = val;
2364 break; 2364 break;
2365 } 2365 }
@@ -2368,14 +2368,14 @@ static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2368 if (!capable(CAP_NET_ADMIN)) 2368 if (!capable(CAP_NET_ADMIN))
2369 return -EPERM; 2369 return -EPERM;
2370 2370
2371 mutex_lock(&hw->phy_mutex); 2371 spin_lock_bh(&hw->phy_lock);
2372 if (hw->chip_id == CHIP_ID_GENESIS) 2372 if (hw->chip_id == CHIP_ID_GENESIS)
2373 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f, 2373 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2374 data->val_in); 2374 data->val_in);
2375 else 2375 else
2376 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f, 2376 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2377 data->val_in); 2377 data->val_in);
2378 mutex_unlock(&hw->phy_mutex); 2378 spin_unlock_bh(&hw->phy_lock);
2379 break; 2379 break;
2380 } 2380 }
2381 return err; 2381 return err;
@@ -2481,12 +2481,12 @@ static int skge_up(struct net_device *dev)
2481 goto free_rx_ring; 2481 goto free_rx_ring;
2482 2482
2483 /* Initialize MAC */ 2483 /* Initialize MAC */
2484 mutex_lock(&hw->phy_mutex); 2484 spin_lock_bh(&hw->phy_lock);
2485 if (hw->chip_id == CHIP_ID_GENESIS) 2485 if (hw->chip_id == CHIP_ID_GENESIS)
2486 genesis_mac_init(hw, port); 2486 genesis_mac_init(hw, port);
2487 else 2487 else
2488 yukon_mac_init(hw, port); 2488 yukon_mac_init(hw, port);
2489 mutex_unlock(&hw->phy_mutex); 2489 spin_unlock_bh(&hw->phy_lock);
2490 2490
2491 /* Configure RAMbuffers */ 2491 /* Configure RAMbuffers */
2492 chunk = hw->ram_size / ((hw->ports + 1)*2); 2492 chunk = hw->ram_size / ((hw->ports + 1)*2);
@@ -2504,6 +2504,11 @@ static int skge_up(struct net_device *dev)
2504 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); 2504 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2505 skge_led(skge, LED_MODE_ON); 2505 skge_led(skge, LED_MODE_ON);
2506 2506
2507 spin_lock_irq(&hw->hw_lock);
2508 hw->intr_mask |= portmask[port];
2509 skge_write32(hw, B0_IMSK, hw->intr_mask);
2510 spin_unlock_irq(&hw->hw_lock);
2511
2507 netif_poll_enable(dev); 2512 netif_poll_enable(dev);
2508 return 0; 2513 return 0;
2509 2514
@@ -2531,7 +2536,14 @@ static int skge_down(struct net_device *dev)
2531 2536
2532 netif_stop_queue(dev); 2537 netif_stop_queue(dev);
2533 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC) 2538 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2534 cancel_delayed_work(&skge->link_thread); 2539 del_timer_sync(&skge->link_timer);
2540
2541 netif_poll_disable(dev);
2542
2543 spin_lock_irq(&hw->hw_lock);
2544 hw->intr_mask &= ~portmask[port];
2545 skge_write32(hw, B0_IMSK, hw->intr_mask);
2546 spin_unlock_irq(&hw->hw_lock);
2535 2547
2536 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); 2548 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2537 if (hw->chip_id == CHIP_ID_GENESIS) 2549 if (hw->chip_id == CHIP_ID_GENESIS)
@@ -2575,8 +2587,10 @@ static int skge_down(struct net_device *dev)
2575 2587
2576 skge_led(skge, LED_MODE_OFF); 2588 skge_led(skge, LED_MODE_OFF);
2577 2589
2578 netif_poll_disable(dev); 2590 netif_tx_lock_bh(dev);
2579 skge_tx_clean(dev); 2591 skge_tx_clean(dev);
2592 netif_tx_unlock_bh(dev);
2593
2580 skge_rx_clean(skge); 2594 skge_rx_clean(skge);
2581 2595
2582 kfree(skge->rx_ring.start); 2596 kfree(skge->rx_ring.start);
@@ -2721,7 +2735,6 @@ static void skge_tx_clean(struct net_device *dev)
2721 struct skge_port *skge = netdev_priv(dev); 2735 struct skge_port *skge = netdev_priv(dev);
2722 struct skge_element *e; 2736 struct skge_element *e;
2723 2737
2724 netif_tx_lock_bh(dev);
2725 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) { 2738 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2726 struct skge_tx_desc *td = e->desc; 2739 struct skge_tx_desc *td = e->desc;
2727 skge_tx_free(skge, e, td->control); 2740 skge_tx_free(skge, e, td->control);
@@ -2730,7 +2743,6 @@ static void skge_tx_clean(struct net_device *dev)
2730 2743
2731 skge->tx_ring.to_clean = e; 2744 skge->tx_ring.to_clean = e;
2732 netif_wake_queue(dev); 2745 netif_wake_queue(dev);
2733 netif_tx_unlock_bh(dev);
2734} 2746}
2735 2747
2736static void skge_tx_timeout(struct net_device *dev) 2748static void skge_tx_timeout(struct net_device *dev)
@@ -3049,7 +3061,7 @@ static int skge_poll(struct net_device *dev, int *budget)
3049 3061
3050 spin_lock_irqsave(&hw->hw_lock, flags); 3062 spin_lock_irqsave(&hw->hw_lock, flags);
3051 __netif_rx_complete(dev); 3063 __netif_rx_complete(dev);
3052 hw->intr_mask |= irqmask[skge->port]; 3064 hw->intr_mask |= napimask[skge->port];
3053 skge_write32(hw, B0_IMSK, hw->intr_mask); 3065 skge_write32(hw, B0_IMSK, hw->intr_mask);
3054 skge_read32(hw, B0_IMSK); 3066 skge_read32(hw, B0_IMSK);
3055 spin_unlock_irqrestore(&hw->hw_lock, flags); 3067 spin_unlock_irqrestore(&hw->hw_lock, flags);
@@ -3160,28 +3172,29 @@ static void skge_error_irq(struct skge_hw *hw)
3160} 3172}
3161 3173
3162/* 3174/*
3163 * Interrupt from PHY are handled in work queue 3175 * Interrupt from PHY are handled in tasklet (softirq)
3164 * because accessing phy registers requires spin wait which might 3176 * because accessing phy registers requires spin wait which might
3165 * cause excess interrupt latency. 3177 * cause excess interrupt latency.
3166 */ 3178 */
3167static void skge_extirq(struct work_struct *work) 3179static void skge_extirq(unsigned long arg)
3168{ 3180{
3169 struct skge_hw *hw = container_of(work, struct skge_hw, phy_work); 3181 struct skge_hw *hw = (struct skge_hw *) arg;
3170 int port; 3182 int port;
3171 3183
3172 mutex_lock(&hw->phy_mutex);
3173 for (port = 0; port < hw->ports; port++) { 3184 for (port = 0; port < hw->ports; port++) {
3174 struct net_device *dev = hw->dev[port]; 3185 struct net_device *dev = hw->dev[port];
3175 struct skge_port *skge = netdev_priv(dev);
3176 3186
3177 if (netif_running(dev)) { 3187 if (netif_running(dev)) {
3188 struct skge_port *skge = netdev_priv(dev);
3189
3190 spin_lock(&hw->phy_lock);
3178 if (hw->chip_id != CHIP_ID_GENESIS) 3191 if (hw->chip_id != CHIP_ID_GENESIS)
3179 yukon_phy_intr(skge); 3192 yukon_phy_intr(skge);
3180 else if (hw->phy_type == SK_PHY_BCOM) 3193 else if (hw->phy_type == SK_PHY_BCOM)
3181 bcom_phy_intr(skge); 3194 bcom_phy_intr(skge);
3195 spin_unlock(&hw->phy_lock);
3182 } 3196 }
3183 } 3197 }
3184 mutex_unlock(&hw->phy_mutex);
3185 3198
3186 spin_lock_irq(&hw->hw_lock); 3199 spin_lock_irq(&hw->hw_lock);
3187 hw->intr_mask |= IS_EXT_REG; 3200 hw->intr_mask |= IS_EXT_REG;
@@ -3206,7 +3219,7 @@ static irqreturn_t skge_intr(int irq, void *dev_id)
3206 status &= hw->intr_mask; 3219 status &= hw->intr_mask;
3207 if (status & IS_EXT_REG) { 3220 if (status & IS_EXT_REG) {
3208 hw->intr_mask &= ~IS_EXT_REG; 3221 hw->intr_mask &= ~IS_EXT_REG;
3209 schedule_work(&hw->phy_work); 3222 tasklet_schedule(&hw->phy_task);
3210 } 3223 }
3211 3224
3212 if (status & (IS_XA1_F|IS_R1_F)) { 3225 if (status & (IS_XA1_F|IS_R1_F)) {
@@ -3282,23 +3295,28 @@ static int skge_set_mac_address(struct net_device *dev, void *p)
3282 3295
3283 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 3296 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3284 3297
3285 /* disable Rx */ 3298 if (!netif_running(dev)) {
3286 ctrl = gma_read16(hw, port, GM_GP_CTRL); 3299 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3287 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA); 3300 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3301 } else {
3302 /* disable Rx */
3303 spin_lock_bh(&hw->phy_lock);
3304 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3305 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3288 3306
3289 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); 3307 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3290 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); 3308 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3291 3309
3292 if (netif_running(dev)) {
3293 if (hw->chip_id == CHIP_ID_GENESIS) 3310 if (hw->chip_id == CHIP_ID_GENESIS)
3294 xm_outaddr(hw, port, XM_SA, dev->dev_addr); 3311 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3295 else { 3312 else {
3296 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); 3313 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3297 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); 3314 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3298 } 3315 }
3299 }
3300 3316
3301 gma_write16(hw, port, GM_GP_CTRL, ctrl); 3317 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3318 spin_unlock_bh(&hw->phy_lock);
3319 }
3302 3320
3303 return 0; 3321 return 0;
3304} 3322}
@@ -3413,10 +3431,9 @@ static int skge_reset(struct skge_hw *hw)
3413 else 3431 else
3414 hw->ram_size = t8 * 4096; 3432 hw->ram_size = t8 * 4096;
3415 3433
3416 hw->intr_mask = IS_HW_ERR | IS_PORT_1; 3434 hw->intr_mask = IS_HW_ERR;
3417 if (hw->ports > 1)
3418 hw->intr_mask |= IS_PORT_2;
3419 3435
3436 /* Use PHY IRQ for all but fiber based Genesis board */
3420 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)) 3437 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3421 hw->intr_mask |= IS_EXT_REG; 3438 hw->intr_mask |= IS_EXT_REG;
3422 3439
@@ -3484,14 +3501,12 @@ static int skge_reset(struct skge_hw *hw)
3484 3501
3485 skge_write32(hw, B0_IMSK, hw->intr_mask); 3502 skge_write32(hw, B0_IMSK, hw->intr_mask);
3486 3503
3487 mutex_lock(&hw->phy_mutex);
3488 for (i = 0; i < hw->ports; i++) { 3504 for (i = 0; i < hw->ports; i++) {
3489 if (hw->chip_id == CHIP_ID_GENESIS) 3505 if (hw->chip_id == CHIP_ID_GENESIS)
3490 genesis_reset(hw, i); 3506 genesis_reset(hw, i);
3491 else 3507 else
3492 yukon_reset(hw, i); 3508 yukon_reset(hw, i);
3493 } 3509 }
3494 mutex_unlock(&hw->phy_mutex);
3495 3510
3496 return 0; 3511 return 0;
3497} 3512}
@@ -3539,6 +3554,7 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3539 skge->netdev = dev; 3554 skge->netdev = dev;
3540 skge->hw = hw; 3555 skge->hw = hw;
3541 skge->msg_enable = netif_msg_init(debug, default_msg); 3556 skge->msg_enable = netif_msg_init(debug, default_msg);
3557
3542 skge->tx_ring.count = DEFAULT_TX_RING_SIZE; 3558 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3543 skge->rx_ring.count = DEFAULT_RX_RING_SIZE; 3559 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3544 3560
@@ -3555,7 +3571,7 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3555 skge->port = port; 3571 skge->port = port;
3556 3572
3557 /* Only used for Genesis XMAC */ 3573 /* Only used for Genesis XMAC */
3558 INIT_DELAYED_WORK(&skge->link_thread, xm_link_timer); 3574 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3559 3575
3560 if (hw->chip_id != CHIP_ID_GENESIS) { 3576 if (hw->chip_id != CHIP_ID_GENESIS) {
3561 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; 3577 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
@@ -3637,9 +3653,9 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3637 } 3653 }
3638 3654
3639 hw->pdev = pdev; 3655 hw->pdev = pdev;
3640 mutex_init(&hw->phy_mutex);
3641 INIT_WORK(&hw->phy_work, skge_extirq);
3642 spin_lock_init(&hw->hw_lock); 3656 spin_lock_init(&hw->hw_lock);
3657 spin_lock_init(&hw->phy_lock);
3658 tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
3643 3659
3644 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); 3660 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3645 if (!hw->regs) { 3661 if (!hw->regs) {
@@ -3725,6 +3741,8 @@ static void __devexit skge_remove(struct pci_dev *pdev)
3725 dev0 = hw->dev[0]; 3741 dev0 = hw->dev[0];
3726 unregister_netdev(dev0); 3742 unregister_netdev(dev0);
3727 3743
3744 tasklet_disable(&hw->phy_task);
3745
3728 spin_lock_irq(&hw->hw_lock); 3746 spin_lock_irq(&hw->hw_lock);
3729 hw->intr_mask = 0; 3747 hw->intr_mask = 0;
3730 skge_write32(hw, B0_IMSK, 0); 3748 skge_write32(hw, B0_IMSK, 0);
diff --git a/drivers/net/skge.h b/drivers/net/skge.h
index e9354dfa7e9a..86467ae74d45 100644
--- a/drivers/net/skge.h
+++ b/drivers/net/skge.h
@@ -2424,8 +2424,8 @@ struct skge_hw {
2424 u32 ram_size; 2424 u32 ram_size;
2425 u32 ram_offset; 2425 u32 ram_offset;
2426 u16 phy_addr; 2426 u16 phy_addr;
2427 struct work_struct phy_work; 2427 spinlock_t phy_lock;
2428 struct mutex phy_mutex; 2428 struct tasklet_struct phy_task;
2429}; 2429};
2430 2430
2431enum pause_control { 2431enum pause_control {
@@ -2457,7 +2457,7 @@ struct skge_port {
2457 2457
2458 struct net_device_stats net_stats; 2458 struct net_device_stats net_stats;
2459 2459
2460 struct delayed_work link_thread; 2460 struct timer_list link_timer;
2461 enum pause_control flow_control; 2461 enum pause_control flow_control;
2462 enum pause_status flow_status; 2462 enum pause_status flow_status;
2463 u8 rx_csum; 2463 u8 rx_csum;
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index dab88b958d6e..639e1e6913bf 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -3607,7 +3607,6 @@ static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3607 if (bd == ugeth->confBd[txQ]) { 3607 if (bd == ugeth->confBd[txQ]) {
3608 if (!netif_queue_stopped(dev)) 3608 if (!netif_queue_stopped(dev))
3609 netif_stop_queue(dev); 3609 netif_stop_queue(dev);
3610 return NETDEV_TX_BUSY;
3611 } 3610 }
3612 3611
3613 ugeth->txBd[txQ] = bd; 3612 ugeth->txBd[txQ] = bd;
@@ -3623,7 +3622,7 @@ static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3623 3622
3624 spin_unlock_irq(&ugeth->lock); 3623 spin_unlock_irq(&ugeth->lock);
3625 3624
3626 return NETDEV_TX_OK; 3625 return 0;
3627} 3626}
3628 3627
3629static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit) 3628static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
diff --git a/drivers/net/wireless/airo.c b/drivers/net/wireless/airo.c
index a8c2bfe26c27..2ada76a93cb6 100644
--- a/drivers/net/wireless/airo.c
+++ b/drivers/net/wireless/airo.c
@@ -2852,7 +2852,7 @@ static struct net_device *_init_airo_card( unsigned short irq, int port,
2852 if (rc) { 2852 if (rc) {
2853 airo_print_err(dev->name, "register interrupt %d failed, rc %d", 2853 airo_print_err(dev->name, "register interrupt %d failed, rc %d",
2854 irq, rc); 2854 irq, rc);
2855 goto err_out_unlink; 2855 goto err_out_nets;
2856 } 2856 }
2857 if (!is_pcmcia) { 2857 if (!is_pcmcia) {
2858 if (!request_region( dev->base_addr, 64, dev->name )) { 2858 if (!request_region( dev->base_addr, 64, dev->name )) {
@@ -2935,6 +2935,8 @@ err_out_res:
2935 release_region( dev->base_addr, 64 ); 2935 release_region( dev->base_addr, 64 );
2936err_out_irq: 2936err_out_irq:
2937 free_irq(dev->irq, dev); 2937 free_irq(dev->irq, dev);
2938err_out_nets:
2939 airo_networks_free(ai);
2938err_out_unlink: 2940err_out_unlink:
2939 del_airo_dev(dev); 2941 del_airo_dev(dev);
2940err_out_thr: 2942err_out_thr:
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_radio.c b/drivers/net/wireless/bcm43xx/bcm43xx_radio.c
index 32beb91b7164..ee1e7a2afc08 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_radio.c
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_radio.c
@@ -882,10 +882,10 @@ static void _stack_save(u32 *_stackptr, size_t *stackidx,
882{ 882{
883 u32 *stackptr = &(_stackptr[*stackidx]); 883 u32 *stackptr = &(_stackptr[*stackidx]);
884 884
885 assert((offset & 0xF000) == 0x0000); 885 assert((offset & 0xE000) == 0x0000);
886 assert((id & 0xF0) == 0x00); 886 assert((id & 0xF8) == 0x00);
887 *stackptr = offset; 887 *stackptr = offset;
888 *stackptr |= ((u32)id) << 12; 888 *stackptr |= ((u32)id) << 13;
889 *stackptr |= ((u32)value) << 16; 889 *stackptr |= ((u32)value) << 16;
890 (*stackidx)++; 890 (*stackidx)++;
891 assert(*stackidx < BCM43xx_INTERFSTACK_SIZE); 891 assert(*stackidx < BCM43xx_INTERFSTACK_SIZE);
@@ -896,12 +896,12 @@ static u16 _stack_restore(u32 *stackptr,
896{ 896{
897 size_t i; 897 size_t i;
898 898
899 assert((offset & 0xF000) == 0x0000); 899 assert((offset & 0xE000) == 0x0000);
900 assert((id & 0xF0) == 0x00); 900 assert((id & 0xF8) == 0x00);
901 for (i = 0; i < BCM43xx_INTERFSTACK_SIZE; i++, stackptr++) { 901 for (i = 0; i < BCM43xx_INTERFSTACK_SIZE; i++, stackptr++) {
902 if ((*stackptr & 0x00000FFF) != offset) 902 if ((*stackptr & 0x00001FFF) != offset)
903 continue; 903 continue;
904 if (((*stackptr & 0x0000F000) >> 12) != id) 904 if (((*stackptr & 0x00007000) >> 13) != id)
905 continue; 905 continue;
906 return ((*stackptr & 0xFFFF0000) >> 16); 906 return ((*stackptr & 0xFFFF0000) >> 16);
907 } 907 }
diff --git a/drivers/serial/8250_pnp.c b/drivers/serial/8250_pnp.c
index cde5db44abf6..301c8c0be9d7 100644
--- a/drivers/serial/8250_pnp.c
+++ b/drivers/serial/8250_pnp.c
@@ -340,6 +340,9 @@ static const struct pnp_device_id pnp_dev_table[] = {
340 { "FUJ02B8", 0 }, 340 { "FUJ02B8", 0 },
341 { "FUJ02B9", 0 }, 341 { "FUJ02B9", 0 },
342 { "FUJ02BC", 0 }, 342 { "FUJ02BC", 0 },
343 /* Fujitsu Wacom Tablet PC devices */
344 { "FUJ02E5", 0 },
345 { "FUJ02E6", 0 },
343 /* Rockwell's (PORALiNK) 33600 INT PNP */ 346 /* Rockwell's (PORALiNK) 33600 INT PNP */
344 { "WCI0003", 0 }, 347 { "WCI0003", 0 },
345 /* Unkown PnP modems */ 348 /* Unkown PnP modems */
diff --git a/drivers/video/riva/fbdev.c b/drivers/video/riva/fbdev.c
index 1d1c7c624d7f..d7ece8d17a2c 100644
--- a/drivers/video/riva/fbdev.c
+++ b/drivers/video/riva/fbdev.c
@@ -285,8 +285,6 @@ static const struct riva_regs reg_template = {
285#define MAX_LEVEL 0x534 285#define MAX_LEVEL 0x534
286#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX) 286#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
287 287
288static struct backlight_properties riva_bl_data;
289
290static int riva_bl_get_level_brightness(struct riva_par *par, 288static int riva_bl_get_level_brightness(struct riva_par *par,
291 int level) 289 int level)
292{ 290{
@@ -372,7 +370,7 @@ static void riva_bl_init(struct riva_par *par)
372 FB_BACKLIGHT_MAX); 370 FB_BACKLIGHT_MAX);
373 371
374 bd->props.max_brightness = FB_BACKLIGHT_LEVELS - 1; 372 bd->props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
375 bd->props.brightness = riva_bl_data.max_brightness; 373 bd->props.brightness = bd->props.max_brightness;
376 bd->props.power = FB_BLANK_UNBLANK; 374 bd->props.power = FB_BLANK_UNBLANK;
377 backlight_update_status(bd); 375 backlight_update_status(bd);
378 376
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-11 08:09:49 -0500