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-rw-r--r--drivers/pci/pci.c2
-rw-r--r--drivers/pci/probe.c17
-rw-r--r--drivers/pci/quirks.c2
-rw-r--r--drivers/pci/setup-bus.c79
-rw-r--r--drivers/pci/setup-res.c20
-rw-r--r--drivers/pnp/quirks.c5
-rw-r--r--drivers/pnp/resource.c8
-rw-r--r--drivers/pnp/support.c2
-rw-r--r--drivers/pnp/system.c2
9 files changed, 67 insertions, 70 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 557218222826..f0da1676d2be 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1713,7 +1713,7 @@ static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_n
1713 return 0; 1713 return 0;
1714 1714
1715err_out: 1715err_out:
1716 dev_warn(&pdev->dev, "BAR %d: can't reserve %pRt\n", bar, 1716 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
1717 &pdev->resource[bar]); 1717 &pdev->resource[bar]);
1718 return -EBUSY; 1718 return -EBUSY;
1719} 1719}
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 4842b09b7f3c..4c4aca53ae09 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -225,12 +225,13 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
225 if (!sz64) 225 if (!sz64)
226 goto fail; 226 goto fail;
227 227
228 res->flags |= IORESOURCE_MEM_64;
229
230 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { 228 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
231 dev_err(&dev->dev, "can't handle 64-bit BAR\n"); 229 dev_err(&dev->dev, "can't handle 64-bit BAR\n");
232 goto fail; 230 goto fail;
233 } else if ((sizeof(resource_size_t) < 8) && l) { 231 }
232
233 res->flags |= IORESOURCE_MEM_64;
234 if ((sizeof(resource_size_t) < 8) && l) {
234 /* Address above 32-bit boundary; disable the BAR */ 235 /* Address above 32-bit boundary; disable the BAR */
235 pci_write_config_dword(dev, pos, 0); 236 pci_write_config_dword(dev, pos, 0);
236 pci_write_config_dword(dev, pos + 4, 0); 237 pci_write_config_dword(dev, pos + 4, 0);
@@ -239,7 +240,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
239 } else { 240 } else {
240 res->start = l64; 241 res->start = l64;
241 res->end = l64 + sz64; 242 res->end = l64 + sz64;
242 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pRt\n", 243 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
243 pos, res); 244 pos, res);
244 } 245 }
245 } else { 246 } else {
@@ -251,7 +252,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
251 res->start = l; 252 res->start = l;
252 res->end = l + sz; 253 res->end = l + sz;
253 254
254 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pRt\n", pos, res); 255 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
255 } 256 }
256 257
257 out: 258 out:
@@ -319,7 +320,7 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
319 res->start = base; 320 res->start = base;
320 if (!res->end) 321 if (!res->end)
321 res->end = limit + 0xfff; 322 res->end = limit + 0xfff;
322 dev_printk(KERN_DEBUG, &dev->dev, "bridge window: %pRt\n", res); 323 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
323 } 324 }
324 325
325 res = child->resource[1]; 326 res = child->resource[1];
@@ -331,7 +332,7 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
331 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 332 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
332 res->start = base; 333 res->start = base;
333 res->end = limit + 0xfffff; 334 res->end = limit + 0xfffff;
334 dev_printk(KERN_DEBUG, &dev->dev, "bridge window: %pRt\n", res); 335 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
335 } 336 }
336 337
337 res = child->resource[2]; 338 res = child->resource[2];
@@ -370,7 +371,7 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
370 res->flags |= IORESOURCE_MEM_64; 371 res->flags |= IORESOURCE_MEM_64;
371 res->start = base; 372 res->start = base;
372 res->end = limit + 0xfffff; 373 res->end = limit + 0xfffff;
373 dev_printk(KERN_DEBUG, &dev->dev, "bridge window: %pRt\n", res); 374 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
374 } 375 }
375} 376}
376 377
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index c0c4537d66da..7cfa7c38d318 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -357,7 +357,7 @@ static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
357 pcibios_bus_to_resource(dev, res, &bus_region); 357 pcibios_bus_to_resource(dev, res, &bus_region);
358 358
359 pci_claim_resource(dev, nr); 359 pci_claim_resource(dev, nr);
360 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name); 360 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
361 } 361 }
362} 362}
363 363
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index ceb75333862b..ed6916bac675 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -71,53 +71,50 @@ static void pbus_assign_resources_sorted(const struct pci_bus *bus)
71void pci_setup_cardbus(struct pci_bus *bus) 71void pci_setup_cardbus(struct pci_bus *bus)
72{ 72{
73 struct pci_dev *bridge = bus->self; 73 struct pci_dev *bridge = bus->self;
74 struct resource *res;
74 struct pci_bus_region region; 75 struct pci_bus_region region;
75 76
76 dev_info(&bridge->dev, "CardBus bridge, secondary bus %04x:%02x\n", 77 dev_info(&bridge->dev, "CardBus bridge, secondary bus %04x:%02x\n",
77 pci_domain_nr(bus), bus->number); 78 pci_domain_nr(bus), bus->number);
78 79
79 pcibios_resource_to_bus(bridge, &region, bus->resource[0]); 80 res = bus->resource[0];
80 if (bus->resource[0]->flags & IORESOURCE_IO) { 81 pcibios_resource_to_bus(bridge, &region, res);
82 if (res->flags & IORESOURCE_IO) {
81 /* 83 /*
82 * The IO resource is allocated a range twice as large as it 84 * The IO resource is allocated a range twice as large as it
83 * would normally need. This allows us to set both IO regs. 85 * would normally need. This allows us to set both IO regs.
84 */ 86 */
85 dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n", 87 dev_info(&bridge->dev, " bridge window %pR\n", res);
86 (unsigned long)region.start,
87 (unsigned long)region.end);
88 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, 88 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
89 region.start); 89 region.start);
90 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, 90 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
91 region.end); 91 region.end);
92 } 92 }
93 93
94 pcibios_resource_to_bus(bridge, &region, bus->resource[1]); 94 res = bus->resource[1];
95 if (bus->resource[1]->flags & IORESOURCE_IO) { 95 pcibios_resource_to_bus(bridge, &region, res);
96 dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n", 96 if (res->flags & IORESOURCE_IO) {
97 (unsigned long)region.start, 97 dev_info(&bridge->dev, " bridge window %pR\n", res);
98 (unsigned long)region.end);
99 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, 98 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
100 region.start); 99 region.start);
101 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, 100 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
102 region.end); 101 region.end);
103 } 102 }
104 103
105 pcibios_resource_to_bus(bridge, &region, bus->resource[2]); 104 res = bus->resource[2];
106 if (bus->resource[2]->flags & IORESOURCE_MEM) { 105 pcibios_resource_to_bus(bridge, &region, res);
107 dev_info(&bridge->dev, " PREFETCH window: %#08lx-%#08lx\n", 106 if (res->flags & IORESOURCE_MEM) {
108 (unsigned long)region.start, 107 dev_info(&bridge->dev, " bridge window %pR\n", res);
109 (unsigned long)region.end);
110 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, 108 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
111 region.start); 109 region.start);
112 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, 110 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
113 region.end); 111 region.end);
114 } 112 }
115 113
116 pcibios_resource_to_bus(bridge, &region, bus->resource[3]); 114 res = bus->resource[3];
117 if (bus->resource[3]->flags & IORESOURCE_MEM) { 115 pcibios_resource_to_bus(bridge, &region, res);
118 dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n", 116 if (res->flags & IORESOURCE_MEM) {
119 (unsigned long)region.start, 117 dev_info(&bridge->dev, " bridge window %pR\n", res);
120 (unsigned long)region.end);
121 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, 118 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
122 region.start); 119 region.start);
123 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, 120 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
@@ -140,6 +137,7 @@ EXPORT_SYMBOL(pci_setup_cardbus);
140static void pci_setup_bridge(struct pci_bus *bus) 137static void pci_setup_bridge(struct pci_bus *bus)
141{ 138{
142 struct pci_dev *bridge = bus->self; 139 struct pci_dev *bridge = bus->self;
140 struct resource *res;
143 struct pci_bus_region region; 141 struct pci_bus_region region;
144 u32 l, bu, lu, io_upper16; 142 u32 l, bu, lu, io_upper16;
145 int pref_mem64; 143 int pref_mem64;
@@ -151,23 +149,22 @@ static void pci_setup_bridge(struct pci_bus *bus)
151 pci_domain_nr(bus), bus->number); 149 pci_domain_nr(bus), bus->number);
152 150
153 /* Set up the top and bottom of the PCI I/O segment for this bus. */ 151 /* Set up the top and bottom of the PCI I/O segment for this bus. */
154 pcibios_resource_to_bus(bridge, &region, bus->resource[0]); 152 res = bus->resource[0];
155 if (bus->resource[0]->flags & IORESOURCE_IO) { 153 pcibios_resource_to_bus(bridge, &region, res);
154 if (res->flags & IORESOURCE_IO) {
156 pci_read_config_dword(bridge, PCI_IO_BASE, &l); 155 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
157 l &= 0xffff0000; 156 l &= 0xffff0000;
158 l |= (region.start >> 8) & 0x00f0; 157 l |= (region.start >> 8) & 0x00f0;
159 l |= region.end & 0xf000; 158 l |= region.end & 0xf000;
160 /* Set up upper 16 bits of I/O base/limit. */ 159 /* Set up upper 16 bits of I/O base/limit. */
161 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); 160 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
162 dev_info(&bridge->dev, " IO window: %#04lx-%#04lx\n", 161 dev_info(&bridge->dev, " bridge window %pR\n", res);
163 (unsigned long)region.start,
164 (unsigned long)region.end);
165 } 162 }
166 else { 163 else {
167 /* Clear upper 16 bits of I/O base/limit. */ 164 /* Clear upper 16 bits of I/O base/limit. */
168 io_upper16 = 0; 165 io_upper16 = 0;
169 l = 0x00f0; 166 l = 0x00f0;
170 dev_info(&bridge->dev, " IO window: disabled\n"); 167 dev_info(&bridge->dev, " bridge window [io disabled]\n");
171 } 168 }
172 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ 169 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
173 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); 170 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
@@ -178,17 +175,16 @@ static void pci_setup_bridge(struct pci_bus *bus)
178 175
179 /* Set up the top and bottom of the PCI Memory segment 176 /* Set up the top and bottom of the PCI Memory segment
180 for this bus. */ 177 for this bus. */
181 pcibios_resource_to_bus(bridge, &region, bus->resource[1]); 178 res = bus->resource[1];
182 if (bus->resource[1]->flags & IORESOURCE_MEM) { 179 pcibios_resource_to_bus(bridge, &region, res);
180 if (res->flags & IORESOURCE_MEM) {
183 l = (region.start >> 16) & 0xfff0; 181 l = (region.start >> 16) & 0xfff0;
184 l |= region.end & 0xfff00000; 182 l |= region.end & 0xfff00000;
185 dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n", 183 dev_info(&bridge->dev, " bridge window %pR\n", res);
186 (unsigned long)region.start,
187 (unsigned long)region.end);
188 } 184 }
189 else { 185 else {
190 l = 0x0000fff0; 186 l = 0x0000fff0;
191 dev_info(&bridge->dev, " MEM window: disabled\n"); 187 dev_info(&bridge->dev, " bridge window [mem disabled]\n");
192 } 188 }
193 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); 189 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
194 190
@@ -200,24 +196,21 @@ static void pci_setup_bridge(struct pci_bus *bus)
200 /* Set up PREF base/limit. */ 196 /* Set up PREF base/limit. */
201 pref_mem64 = 0; 197 pref_mem64 = 0;
202 bu = lu = 0; 198 bu = lu = 0;
203 pcibios_resource_to_bus(bridge, &region, bus->resource[2]); 199 res = bus->resource[2];
204 if (bus->resource[2]->flags & IORESOURCE_PREFETCH) { 200 pcibios_resource_to_bus(bridge, &region, res);
205 int width = 8; 201 if (res->flags & IORESOURCE_PREFETCH) {
206 l = (region.start >> 16) & 0xfff0; 202 l = (region.start >> 16) & 0xfff0;
207 l |= region.end & 0xfff00000; 203 l |= region.end & 0xfff00000;
208 if (bus->resource[2]->flags & IORESOURCE_MEM_64) { 204 if (res->flags & IORESOURCE_MEM_64) {
209 pref_mem64 = 1; 205 pref_mem64 = 1;
210 bu = upper_32_bits(region.start); 206 bu = upper_32_bits(region.start);
211 lu = upper_32_bits(region.end); 207 lu = upper_32_bits(region.end);
212 width = 16;
213 } 208 }
214 dev_info(&bridge->dev, " PREFETCH window: %#0*llx-%#0*llx\n", 209 dev_info(&bridge->dev, " bridge window %pR\n", res);
215 width, (unsigned long long)region.start,
216 width, (unsigned long long)region.end);
217 } 210 }
218 else { 211 else {
219 l = 0x0000fff0; 212 l = 0x0000fff0;
220 dev_info(&bridge->dev, " PREFETCH window: disabled\n"); 213 dev_info(&bridge->dev, " bridge window [mem pref disabled]\n");
221 } 214 }
222 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); 215 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
223 216
@@ -391,7 +384,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
391 order = __ffs(align) - 20; 384 order = __ffs(align) - 20;
392 if (order > 11) { 385 if (order > 11) {
393 dev_warn(&dev->dev, "BAR %d: bad alignment %llx: " 386 dev_warn(&dev->dev, "BAR %d: bad alignment %llx: "
394 "%pRt\n", i, (unsigned long long)align, r); 387 "%pR\n", i, (unsigned long long)align, r);
395 r->flags = 0; 388 r->flags = 0;
396 continue; 389 continue;
397 } 390 }
@@ -582,7 +575,7 @@ static void pci_bus_dump_res(struct pci_bus *bus)
582 if (!res || !res->end) 575 if (!res || !res->end)
583 continue; 576 continue;
584 577
585 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pRt\n", i, res); 578 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
586 } 579 }
587} 580}
588 581
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
index 5e78f2096ce8..357ca5c54607 100644
--- a/drivers/pci/setup-res.c
+++ b/drivers/pci/setup-res.c
@@ -51,9 +51,11 @@ void pci_update_resource(struct pci_dev *dev, int resno)
51 51
52 pcibios_resource_to_bus(dev, &region, res); 52 pcibios_resource_to_bus(dev, &region, res);
53 53
54 dev_dbg(&dev->dev, "BAR %d: got %pRf (bus addr [%#llx-%#llx])\n", 54 dev_dbg(&dev->dev, "BAR %d: got res %pR bus [%#llx-%#llx] "
55 resno, res, (unsigned long long)region.start, 55 "flags %#lx\n", resno, res,
56 (unsigned long long)region.end); 56 (unsigned long long)region.start,
57 (unsigned long long)region.end,
58 (unsigned long)res->flags);
57 59
58 new = region.start | (res->flags & PCI_REGION_FLAG_MASK); 60 new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
59 if (res->flags & IORESOURCE_IO) 61 if (res->flags & IORESOURCE_IO)
@@ -89,8 +91,8 @@ void pci_update_resource(struct pci_dev *dev, int resno)
89 } 91 }
90 } 92 }
91 res->flags &= ~IORESOURCE_UNSET; 93 res->flags &= ~IORESOURCE_UNSET;
92 dev_dbg(&dev->dev, "BAR %d: moved to bus addr [%#llx-%#llx]\n", 94 dev_dbg(&dev->dev, "BAR %d: moved to %pR (bus addr [%#llx-%#llx])\n",
93 resno, (unsigned long long)region.start, 95 resno, res, (unsigned long long)region.start,
94 (unsigned long long)region.end); 96 (unsigned long long)region.end);
95} 97}
96 98
@@ -108,7 +110,7 @@ int pci_claim_resource(struct pci_dev *dev, int resource)
108 110
109 if (err) { 111 if (err) {
110 const char *dtype = resource < PCI_BRIDGE_RESOURCES ? "device" : "bridge"; 112 const char *dtype = resource < PCI_BRIDGE_RESOURCES ? "device" : "bridge";
111 dev_err(&dev->dev, "BAR %d: %s %s %pRt\n", 113 dev_err(&dev->dev, "BAR %d: %s of %s %pR\n",
112 resource, 114 resource,
113 root ? "address space collision on" : 115 root ? "address space collision on" :
114 "no parent found for", 116 "no parent found for",
@@ -179,7 +181,7 @@ int pci_assign_resource(struct pci_dev *dev, int resno)
179 181
180 align = pci_resource_alignment(dev, res); 182 align = pci_resource_alignment(dev, res);
181 if (!align) { 183 if (!align) {
182 dev_info(&dev->dev, "BAR %d: can't allocate %pRf " 184 dev_info(&dev->dev, "BAR %d: can't allocate %pR "
183 "(bogus alignment)\n", resno, res); 185 "(bogus alignment)\n", resno, res);
184 return -EINVAL; 186 return -EINVAL;
185 } 187 }
@@ -196,7 +198,7 @@ int pci_assign_resource(struct pci_dev *dev, int resno)
196 } 198 }
197 199
198 if (ret) 200 if (ret)
199 dev_info(&dev->dev, "BAR %d: can't allocate %pRt\n", 201 dev_info(&dev->dev, "BAR %d: can't allocate %pR\n",
200 resno, res); 202 resno, res);
201 203
202 return ret; 204 return ret;
@@ -222,7 +224,7 @@ void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
222 224
223 r_align = pci_resource_alignment(dev, r); 225 r_align = pci_resource_alignment(dev, r);
224 if (!r_align) { 226 if (!r_align) {
225 dev_warn(&dev->dev, "BAR %d: bogus alignment %pRf\n", 227 dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
226 i, r); 228 i, r);
227 continue; 229 continue;
228 } 230 }
diff --git a/drivers/pnp/quirks.c b/drivers/pnp/quirks.c
index 3a2031b25c3c..dfbd5a6cc58b 100644
--- a/drivers/pnp/quirks.c
+++ b/drivers/pnp/quirks.c
@@ -285,8 +285,9 @@ static void quirk_system_pci_resources(struct pnp_dev *dev)
285 * the PCI region, and that might prevent a PCI 285 * the PCI region, and that might prevent a PCI
286 * driver from requesting its resources. 286 * driver from requesting its resources.
287 */ 287 */
288 dev_warn(&dev->dev, "resource %pRt overlaps %s " 288 dev_warn(&dev->dev,
289 "BAR %d %pRt, disabling\n", res, 289 "disabling %pR because it overlaps "
290 "%s BAR %d %pR\n", res,
290 pci_name(pdev), i, &pdev->resource[i]); 291 pci_name(pdev), i, &pdev->resource[i]);
291 res->flags |= IORESOURCE_DISABLED; 292 res->flags |= IORESOURCE_DISABLED;
292 } 293 }
diff --git a/drivers/pnp/resource.c b/drivers/pnp/resource.c
index 18557d7bb0b9..64d0596bafb5 100644
--- a/drivers/pnp/resource.c
+++ b/drivers/pnp/resource.c
@@ -517,7 +517,7 @@ struct pnp_resource *pnp_add_irq_resource(struct pnp_dev *dev, int irq,
517 res->start = irq; 517 res->start = irq;
518 res->end = irq; 518 res->end = irq;
519 519
520 pnp_dbg(&dev->dev, " add %pRf\n", res); 520 pnp_dbg(&dev->dev, " add %pr\n", res);
521 return pnp_res; 521 return pnp_res;
522} 522}
523 523
@@ -538,7 +538,7 @@ struct pnp_resource *pnp_add_dma_resource(struct pnp_dev *dev, int dma,
538 res->start = dma; 538 res->start = dma;
539 res->end = dma; 539 res->end = dma;
540 540
541 pnp_dbg(&dev->dev, " add %pRf\n", res); 541 pnp_dbg(&dev->dev, " add %pr\n", res);
542 return pnp_res; 542 return pnp_res;
543} 543}
544 544
@@ -562,7 +562,7 @@ struct pnp_resource *pnp_add_io_resource(struct pnp_dev *dev,
562 res->start = start; 562 res->start = start;
563 res->end = end; 563 res->end = end;
564 564
565 pnp_dbg(&dev->dev, " add %pRf\n", res); 565 pnp_dbg(&dev->dev, " add %pr\n", res);
566 return pnp_res; 566 return pnp_res;
567} 567}
568 568
@@ -586,7 +586,7 @@ struct pnp_resource *pnp_add_mem_resource(struct pnp_dev *dev,
586 res->start = start; 586 res->start = start;
587 res->end = end; 587 res->end = end;
588 588
589 pnp_dbg(&dev->dev, " add %pRf\n", res); 589 pnp_dbg(&dev->dev, " add %pr\n", res);
590 return pnp_res; 590 return pnp_res;
591} 591}
592 592
diff --git a/drivers/pnp/support.c b/drivers/pnp/support.c
index 1f8a33b0abac..9585c1c1cc36 100644
--- a/drivers/pnp/support.c
+++ b/drivers/pnp/support.c
@@ -82,7 +82,7 @@ void dbg_pnp_show_resources(struct pnp_dev *dev, char *desc)
82 else { 82 else {
83 pnp_dbg(&dev->dev, "%s: current resources:\n", desc); 83 pnp_dbg(&dev->dev, "%s: current resources:\n", desc);
84 list_for_each_entry(pnp_res, &dev->resources, list) 84 list_for_each_entry(pnp_res, &dev->resources, list)
85 pnp_dbg(&dev->dev, "%pRf\n", &pnp_res->res); 85 pnp_dbg(&dev->dev, "%pr\n", &pnp_res->res);
86 } 86 }
87} 87}
88 88
diff --git a/drivers/pnp/system.c b/drivers/pnp/system.c
index 242d3a872011..49c1720df59a 100644
--- a/drivers/pnp/system.c
+++ b/drivers/pnp/system.c
@@ -48,7 +48,7 @@ static void reserve_range(struct pnp_dev *dev, struct resource *r, int port)
48 * example do reserve stuff they know about too, so we may well 48 * example do reserve stuff they know about too, so we may well
49 * have double reservations. 49 * have double reservations.
50 */ 50 */
51 dev_info(&dev->dev, "%pRt %s reserved\n", r, 51 dev_info(&dev->dev, "%pR %s reserved\n", r,
52 res ? "has been" : "could not be"); 52 res ? "has been" : "could not be");
53} 53}
54 54