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-rw-r--r--drivers/firewire/core-transaction.c14
-rw-r--r--drivers/firewire/ohci.c14
2 files changed, 24 insertions, 4 deletions
diff --git a/drivers/firewire/core-transaction.c b/drivers/firewire/core-transaction.c
index 2a390726fa76..8146133818dc 100644
--- a/drivers/firewire/core-transaction.c
+++ b/drivers/firewire/core-transaction.c
@@ -1115,6 +1115,17 @@ static void handle_registers(struct fw_card *card, struct fw_request *request,
1115 rcode = RCODE_TYPE_ERROR; 1115 rcode = RCODE_TYPE_ERROR;
1116 break; 1116 break;
1117 1117
1118 case CSR_BUSY_TIMEOUT:
1119 if (tcode == TCODE_READ_QUADLET_REQUEST)
1120 *data = cpu_to_be32(card->driver->
1121 read_csr_reg(card, CSR_BUSY_TIMEOUT));
1122 else if (tcode == TCODE_WRITE_QUADLET_REQUEST)
1123 card->driver->write_csr_reg(card, CSR_BUSY_TIMEOUT,
1124 be32_to_cpu(*data));
1125 else
1126 rcode = RCODE_TYPE_ERROR;
1127 break;
1128
1118 case CSR_BROADCAST_CHANNEL: 1129 case CSR_BROADCAST_CHANNEL:
1119 if (tcode == TCODE_READ_QUADLET_REQUEST) 1130 if (tcode == TCODE_READ_QUADLET_REQUEST)
1120 *data = cpu_to_be32(card->broadcast_channel); 1131 *data = cpu_to_be32(card->broadcast_channel);
@@ -1140,9 +1151,6 @@ static void handle_registers(struct fw_card *card, struct fw_request *request,
1140 BUG(); 1151 BUG();
1141 break; 1152 break;
1142 1153
1143 case CSR_BUSY_TIMEOUT:
1144 /* FIXME: Implement this. */
1145
1146 default: 1154 default:
1147 rcode = RCODE_ADDRESS_ERROR; 1155 rcode = RCODE_ADDRESS_ERROR;
1148 break; 1156 break;
diff --git a/drivers/firewire/ohci.c b/drivers/firewire/ohci.c
index 3d4badb7c79b..9c588fd01250 100644
--- a/drivers/firewire/ohci.c
+++ b/drivers/firewire/ohci.c
@@ -1731,7 +1731,8 @@ static int ohci_enable(struct fw_card *card,
1731 reg_write(ohci, OHCI1394_ATRetries, 1731 reg_write(ohci, OHCI1394_ATRetries,
1732 OHCI1394_MAX_AT_REQ_RETRIES | 1732 OHCI1394_MAX_AT_REQ_RETRIES |
1733 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 1733 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1734 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8)); 1734 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
1735 (200 << 16));
1735 1736
1736 seconds = lower_32_bits(get_seconds()); 1737 seconds = lower_32_bits(get_seconds());
1737 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25); 1738 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
@@ -2023,6 +2024,10 @@ static u32 ohci_read_csr_reg(struct fw_card *card, int csr_offset)
2023 spin_unlock_irqrestore(&ohci->lock, flags); 2024 spin_unlock_irqrestore(&ohci->lock, flags);
2024 return value; 2025 return value;
2025 2026
2027 case CSR_BUSY_TIMEOUT:
2028 value = reg_read(ohci, OHCI1394_ATRetries);
2029 return (value >> 4) & 0x0ffff00f;
2030
2026 default: 2031 default:
2027 WARN_ON(1); 2032 WARN_ON(1);
2028 return 0; 2033 return 0;
@@ -2053,6 +2058,13 @@ static void ohci_write_csr_reg(struct fw_card *card, int csr_offset, u32 value)
2053 spin_unlock_irqrestore(&ohci->lock, flags); 2058 spin_unlock_irqrestore(&ohci->lock, flags);
2054 break; 2059 break;
2055 2060
2061 case CSR_BUSY_TIMEOUT:
2062 value = (value & 0xf) | ((value & 0xf) << 4) |
2063 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2064 reg_write(ohci, OHCI1394_ATRetries, value);
2065 flush_writes(ohci);
2066 break;
2067
2056 default: 2068 default:
2057 WARN_ON(1); 2069 WARN_ON(1);
2058 break; 2070 break;