diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/mfd/sm501.c | 125 | ||||
-rw-r--r-- | drivers/video/sm501fb.c | 172 |
2 files changed, 153 insertions, 144 deletions
diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c index 5de3a760ea1e..558d5f3f6d02 100644 --- a/drivers/mfd/sm501.c +++ b/drivers/mfd/sm501.c | |||
@@ -133,10 +133,10 @@ static unsigned long decode_div(unsigned long pll2, unsigned long val, | |||
133 | 133 | ||
134 | static void sm501_dump_clk(struct sm501_devdata *sm) | 134 | static void sm501_dump_clk(struct sm501_devdata *sm) |
135 | { | 135 | { |
136 | unsigned long misct = readl(sm->regs + SM501_MISC_TIMING); | 136 | unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING); |
137 | unsigned long pm0 = readl(sm->regs + SM501_POWER_MODE_0_CLOCK); | 137 | unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK); |
138 | unsigned long pm1 = readl(sm->regs + SM501_POWER_MODE_1_CLOCK); | 138 | unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK); |
139 | unsigned long pmc = readl(sm->regs + SM501_POWER_MODE_CONTROL); | 139 | unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); |
140 | unsigned long sdclk0, sdclk1; | 140 | unsigned long sdclk0, sdclk1; |
141 | unsigned long pll2 = 0; | 141 | unsigned long pll2 = 0; |
142 | 142 | ||
@@ -193,29 +193,29 @@ static void sm501_dump_regs(struct sm501_devdata *sm) | |||
193 | void __iomem *regs = sm->regs; | 193 | void __iomem *regs = sm->regs; |
194 | 194 | ||
195 | dev_info(sm->dev, "System Control %08x\n", | 195 | dev_info(sm->dev, "System Control %08x\n", |
196 | readl(regs + SM501_SYSTEM_CONTROL)); | 196 | smc501_readl(regs + SM501_SYSTEM_CONTROL)); |
197 | dev_info(sm->dev, "Misc Control %08x\n", | 197 | dev_info(sm->dev, "Misc Control %08x\n", |
198 | readl(regs + SM501_MISC_CONTROL)); | 198 | smc501_readl(regs + SM501_MISC_CONTROL)); |
199 | dev_info(sm->dev, "GPIO Control Low %08x\n", | 199 | dev_info(sm->dev, "GPIO Control Low %08x\n", |
200 | readl(regs + SM501_GPIO31_0_CONTROL)); | 200 | smc501_readl(regs + SM501_GPIO31_0_CONTROL)); |
201 | dev_info(sm->dev, "GPIO Control Hi %08x\n", | 201 | dev_info(sm->dev, "GPIO Control Hi %08x\n", |
202 | readl(regs + SM501_GPIO63_32_CONTROL)); | 202 | smc501_readl(regs + SM501_GPIO63_32_CONTROL)); |
203 | dev_info(sm->dev, "DRAM Control %08x\n", | 203 | dev_info(sm->dev, "DRAM Control %08x\n", |
204 | readl(regs + SM501_DRAM_CONTROL)); | 204 | smc501_readl(regs + SM501_DRAM_CONTROL)); |
205 | dev_info(sm->dev, "Arbitration Ctrl %08x\n", | 205 | dev_info(sm->dev, "Arbitration Ctrl %08x\n", |
206 | readl(regs + SM501_ARBTRTN_CONTROL)); | 206 | smc501_readl(regs + SM501_ARBTRTN_CONTROL)); |
207 | dev_info(sm->dev, "Misc Timing %08x\n", | 207 | dev_info(sm->dev, "Misc Timing %08x\n", |
208 | readl(regs + SM501_MISC_TIMING)); | 208 | smc501_readl(regs + SM501_MISC_TIMING)); |
209 | } | 209 | } |
210 | 210 | ||
211 | static void sm501_dump_gate(struct sm501_devdata *sm) | 211 | static void sm501_dump_gate(struct sm501_devdata *sm) |
212 | { | 212 | { |
213 | dev_info(sm->dev, "CurrentGate %08x\n", | 213 | dev_info(sm->dev, "CurrentGate %08x\n", |
214 | readl(sm->regs + SM501_CURRENT_GATE)); | 214 | smc501_readl(sm->regs + SM501_CURRENT_GATE)); |
215 | dev_info(sm->dev, "CurrentClock %08x\n", | 215 | dev_info(sm->dev, "CurrentClock %08x\n", |
216 | readl(sm->regs + SM501_CURRENT_CLOCK)); | 216 | smc501_readl(sm->regs + SM501_CURRENT_CLOCK)); |
217 | dev_info(sm->dev, "PowerModeControl %08x\n", | 217 | dev_info(sm->dev, "PowerModeControl %08x\n", |
218 | readl(sm->regs + SM501_POWER_MODE_CONTROL)); | 218 | smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL)); |
219 | } | 219 | } |
220 | 220 | ||
221 | #else | 221 | #else |
@@ -231,7 +231,7 @@ static inline void sm501_dump_clk(struct sm501_devdata *sm) { } | |||
231 | 231 | ||
232 | static void sm501_sync_regs(struct sm501_devdata *sm) | 232 | static void sm501_sync_regs(struct sm501_devdata *sm) |
233 | { | 233 | { |
234 | readl(sm->regs); | 234 | smc501_readl(sm->regs); |
235 | } | 235 | } |
236 | 236 | ||
237 | static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay) | 237 | static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay) |
@@ -261,11 +261,11 @@ int sm501_misc_control(struct device *dev, | |||
261 | 261 | ||
262 | spin_lock_irqsave(&sm->reg_lock, save); | 262 | spin_lock_irqsave(&sm->reg_lock, save); |
263 | 263 | ||
264 | misc = readl(sm->regs + SM501_MISC_CONTROL); | 264 | misc = smc501_readl(sm->regs + SM501_MISC_CONTROL); |
265 | to = (misc & ~clear) | set; | 265 | to = (misc & ~clear) | set; |
266 | 266 | ||
267 | if (to != misc) { | 267 | if (to != misc) { |
268 | writel(to, sm->regs + SM501_MISC_CONTROL); | 268 | smc501_writel(to, sm->regs + SM501_MISC_CONTROL); |
269 | sm501_sync_regs(sm); | 269 | sm501_sync_regs(sm); |
270 | 270 | ||
271 | dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc); | 271 | dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc); |
@@ -294,11 +294,11 @@ unsigned long sm501_modify_reg(struct device *dev, | |||
294 | 294 | ||
295 | spin_lock_irqsave(&sm->reg_lock, save); | 295 | spin_lock_irqsave(&sm->reg_lock, save); |
296 | 296 | ||
297 | data = readl(sm->regs + reg); | 297 | data = smc501_readl(sm->regs + reg); |
298 | data |= set; | 298 | data |= set; |
299 | data &= ~clear; | 299 | data &= ~clear; |
300 | 300 | ||
301 | writel(data, sm->regs + reg); | 301 | smc501_writel(data, sm->regs + reg); |
302 | sm501_sync_regs(sm); | 302 | sm501_sync_regs(sm); |
303 | 303 | ||
304 | spin_unlock_irqrestore(&sm->reg_lock, save); | 304 | spin_unlock_irqrestore(&sm->reg_lock, save); |
@@ -322,9 +322,9 @@ int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to) | |||
322 | 322 | ||
323 | mutex_lock(&sm->clock_lock); | 323 | mutex_lock(&sm->clock_lock); |
324 | 324 | ||
325 | mode = readl(sm->regs + SM501_POWER_MODE_CONTROL); | 325 | mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); |
326 | gate = readl(sm->regs + SM501_CURRENT_GATE); | 326 | gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); |
327 | clock = readl(sm->regs + SM501_CURRENT_CLOCK); | 327 | clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); |
328 | 328 | ||
329 | mode &= 3; /* get current power mode */ | 329 | mode &= 3; /* get current power mode */ |
330 | 330 | ||
@@ -356,14 +356,14 @@ int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to) | |||
356 | 356 | ||
357 | switch (mode) { | 357 | switch (mode) { |
358 | case 1: | 358 | case 1: |
359 | writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); | 359 | smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); |
360 | writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); | 360 | smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); |
361 | mode = 0; | 361 | mode = 0; |
362 | break; | 362 | break; |
363 | case 2: | 363 | case 2: |
364 | case 0: | 364 | case 0: |
365 | writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); | 365 | smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); |
366 | writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); | 366 | smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); |
367 | mode = 1; | 367 | mode = 1; |
368 | break; | 368 | break; |
369 | 369 | ||
@@ -372,7 +372,7 @@ int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to) | |||
372 | goto already; | 372 | goto already; |
373 | } | 373 | } |
374 | 374 | ||
375 | writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); | 375 | smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); |
376 | sm501_sync_regs(sm); | 376 | sm501_sync_regs(sm); |
377 | 377 | ||
378 | dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", | 378 | dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", |
@@ -519,9 +519,9 @@ unsigned long sm501_set_clock(struct device *dev, | |||
519 | unsigned long req_freq) | 519 | unsigned long req_freq) |
520 | { | 520 | { |
521 | struct sm501_devdata *sm = dev_get_drvdata(dev); | 521 | struct sm501_devdata *sm = dev_get_drvdata(dev); |
522 | unsigned long mode = readl(sm->regs + SM501_POWER_MODE_CONTROL); | 522 | unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); |
523 | unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE); | 523 | unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); |
524 | unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK); | 524 | unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); |
525 | unsigned char reg; | 525 | unsigned char reg; |
526 | unsigned int pll_reg = 0; | 526 | unsigned int pll_reg = 0; |
527 | unsigned long sm501_freq; /* the actual frequency achieved */ | 527 | unsigned long sm501_freq; /* the actual frequency achieved */ |
@@ -592,9 +592,9 @@ unsigned long sm501_set_clock(struct device *dev, | |||
592 | 592 | ||
593 | mutex_lock(&sm->clock_lock); | 593 | mutex_lock(&sm->clock_lock); |
594 | 594 | ||
595 | mode = readl(sm->regs + SM501_POWER_MODE_CONTROL); | 595 | mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); |
596 | gate = readl(sm->regs + SM501_CURRENT_GATE); | 596 | gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); |
597 | clock = readl(sm->regs + SM501_CURRENT_CLOCK); | 597 | clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); |
598 | 598 | ||
599 | clock = clock & ~(0xFF << clksrc); | 599 | clock = clock & ~(0xFF << clksrc); |
600 | clock |= reg<<clksrc; | 600 | clock |= reg<<clksrc; |
@@ -603,14 +603,14 @@ unsigned long sm501_set_clock(struct device *dev, | |||
603 | 603 | ||
604 | switch (mode) { | 604 | switch (mode) { |
605 | case 1: | 605 | case 1: |
606 | writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); | 606 | smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); |
607 | writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); | 607 | smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); |
608 | mode = 0; | 608 | mode = 0; |
609 | break; | 609 | break; |
610 | case 2: | 610 | case 2: |
611 | case 0: | 611 | case 0: |
612 | writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); | 612 | smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); |
613 | writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); | 613 | smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); |
614 | mode = 1; | 614 | mode = 1; |
615 | break; | 615 | break; |
616 | 616 | ||
@@ -619,10 +619,11 @@ unsigned long sm501_set_clock(struct device *dev, | |||
619 | return -1; | 619 | return -1; |
620 | } | 620 | } |
621 | 621 | ||
622 | writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); | 622 | smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); |
623 | 623 | ||
624 | if (pll_reg) | 624 | if (pll_reg) |
625 | writel(pll_reg, sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL); | 625 | smc501_writel(pll_reg, |
626 | sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL); | ||
626 | 627 | ||
627 | sm501_sync_regs(sm); | 628 | sm501_sync_regs(sm); |
628 | 629 | ||
@@ -902,7 +903,7 @@ static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset) | |||
902 | struct sm501_gpio_chip *smgpio = to_sm501_gpio(chip); | 903 | struct sm501_gpio_chip *smgpio = to_sm501_gpio(chip); |
903 | unsigned long result; | 904 | unsigned long result; |
904 | 905 | ||
905 | result = readl(smgpio->regbase + SM501_GPIO_DATA_LOW); | 906 | result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW); |
906 | result >>= offset; | 907 | result >>= offset; |
907 | 908 | ||
908 | return result & 1UL; | 909 | return result & 1UL; |
@@ -915,13 +916,13 @@ static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip, | |||
915 | 916 | ||
916 | /* check and modify if this pin is not set as gpio. */ | 917 | /* check and modify if this pin is not set as gpio. */ |
917 | 918 | ||
918 | if (readl(smchip->control) & bit) { | 919 | if (smc501_readl(smchip->control) & bit) { |
919 | dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev, | 920 | dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev, |
920 | "changing mode of gpio, bit %08lx\n", bit); | 921 | "changing mode of gpio, bit %08lx\n", bit); |
921 | 922 | ||
922 | ctrl = readl(smchip->control); | 923 | ctrl = smc501_readl(smchip->control); |
923 | ctrl &= ~bit; | 924 | ctrl &= ~bit; |
924 | writel(ctrl, smchip->control); | 925 | smc501_writel(ctrl, smchip->control); |
925 | 926 | ||
926 | sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio)); | 927 | sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio)); |
927 | } | 928 | } |
@@ -942,10 +943,10 @@ static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |||
942 | 943 | ||
943 | spin_lock_irqsave(&smgpio->lock, save); | 944 | spin_lock_irqsave(&smgpio->lock, save); |
944 | 945 | ||
945 | val = readl(regs + SM501_GPIO_DATA_LOW) & ~bit; | 946 | val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit; |
946 | if (value) | 947 | if (value) |
947 | val |= bit; | 948 | val |= bit; |
948 | writel(val, regs); | 949 | smc501_writel(val, regs); |
949 | 950 | ||
950 | sm501_sync_regs(sm501_gpio_to_dev(smgpio)); | 951 | sm501_sync_regs(sm501_gpio_to_dev(smgpio)); |
951 | sm501_gpio_ensure_gpio(smchip, bit); | 952 | sm501_gpio_ensure_gpio(smchip, bit); |
@@ -967,8 +968,8 @@ static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset) | |||
967 | 968 | ||
968 | spin_lock_irqsave(&smgpio->lock, save); | 969 | spin_lock_irqsave(&smgpio->lock, save); |
969 | 970 | ||
970 | ddr = readl(regs + SM501_GPIO_DDR_LOW); | 971 | ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW); |
971 | writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW); | 972 | smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW); |
972 | 973 | ||
973 | sm501_sync_regs(sm501_gpio_to_dev(smgpio)); | 974 | sm501_sync_regs(sm501_gpio_to_dev(smgpio)); |
974 | sm501_gpio_ensure_gpio(smchip, bit); | 975 | sm501_gpio_ensure_gpio(smchip, bit); |
@@ -994,18 +995,18 @@ static int sm501_gpio_output(struct gpio_chip *chip, | |||
994 | 995 | ||
995 | spin_lock_irqsave(&smgpio->lock, save); | 996 | spin_lock_irqsave(&smgpio->lock, save); |
996 | 997 | ||
997 | val = readl(regs + SM501_GPIO_DATA_LOW); | 998 | val = smc501_readl(regs + SM501_GPIO_DATA_LOW); |
998 | if (value) | 999 | if (value) |
999 | val |= bit; | 1000 | val |= bit; |
1000 | else | 1001 | else |
1001 | val &= ~bit; | 1002 | val &= ~bit; |
1002 | writel(val, regs); | 1003 | smc501_writel(val, regs); |
1003 | 1004 | ||
1004 | ddr = readl(regs + SM501_GPIO_DDR_LOW); | 1005 | ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW); |
1005 | writel(ddr | bit, regs + SM501_GPIO_DDR_LOW); | 1006 | smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW); |
1006 | 1007 | ||
1007 | sm501_sync_regs(sm501_gpio_to_dev(smgpio)); | 1008 | sm501_sync_regs(sm501_gpio_to_dev(smgpio)); |
1008 | writel(val, regs + SM501_GPIO_DATA_LOW); | 1009 | smc501_writel(val, regs + SM501_GPIO_DATA_LOW); |
1009 | 1010 | ||
1010 | sm501_sync_regs(sm501_gpio_to_dev(smgpio)); | 1011 | sm501_sync_regs(sm501_gpio_to_dev(smgpio)); |
1011 | spin_unlock_irqrestore(&smgpio->lock, save); | 1012 | spin_unlock_irqrestore(&smgpio->lock, save); |
@@ -1231,7 +1232,7 @@ static ssize_t sm501_dbg_regs(struct device *dev, | |||
1231 | 1232 | ||
1232 | for (reg = 0x00; reg < 0x70; reg += 4) { | 1233 | for (reg = 0x00; reg < 0x70; reg += 4) { |
1233 | ret = sprintf(ptr, "%08x = %08x\n", | 1234 | ret = sprintf(ptr, "%08x = %08x\n", |
1234 | reg, readl(sm->regs + reg)); | 1235 | reg, smc501_readl(sm->regs + reg)); |
1235 | ptr += ret; | 1236 | ptr += ret; |
1236 | } | 1237 | } |
1237 | 1238 | ||
@@ -1255,10 +1256,10 @@ static inline void sm501_init_reg(struct sm501_devdata *sm, | |||
1255 | { | 1256 | { |
1256 | unsigned long tmp; | 1257 | unsigned long tmp; |
1257 | 1258 | ||
1258 | tmp = readl(sm->regs + reg); | 1259 | tmp = smc501_readl(sm->regs + reg); |
1259 | tmp &= ~r->mask; | 1260 | tmp &= ~r->mask; |
1260 | tmp |= r->set; | 1261 | tmp |= r->set; |
1261 | writel(tmp, sm->regs + reg); | 1262 | smc501_writel(tmp, sm->regs + reg); |
1262 | } | 1263 | } |
1263 | 1264 | ||
1264 | /* sm501_init_regs | 1265 | /* sm501_init_regs |
@@ -1299,7 +1300,7 @@ static void sm501_init_regs(struct sm501_devdata *sm, | |||
1299 | 1300 | ||
1300 | static int sm501_check_clocks(struct sm501_devdata *sm) | 1301 | static int sm501_check_clocks(struct sm501_devdata *sm) |
1301 | { | 1302 | { |
1302 | unsigned long pwrmode = readl(sm->regs + SM501_CURRENT_CLOCK); | 1303 | unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); |
1303 | unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC); | 1304 | unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC); |
1304 | unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC); | 1305 | unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC); |
1305 | 1306 | ||
@@ -1334,7 +1335,7 @@ static int __devinit sm501_init_dev(struct sm501_devdata *sm) | |||
1334 | 1335 | ||
1335 | INIT_LIST_HEAD(&sm->devices); | 1336 | INIT_LIST_HEAD(&sm->devices); |
1336 | 1337 | ||
1337 | devid = readl(sm->regs + SM501_DEVICEID); | 1338 | devid = smc501_readl(sm->regs + SM501_DEVICEID); |
1338 | 1339 | ||
1339 | if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) { | 1340 | if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) { |
1340 | dev_err(sm->dev, "incorrect device id %08lx\n", devid); | 1341 | dev_err(sm->dev, "incorrect device id %08lx\n", devid); |
@@ -1342,9 +1343,9 @@ static int __devinit sm501_init_dev(struct sm501_devdata *sm) | |||
1342 | } | 1343 | } |
1343 | 1344 | ||
1344 | /* disable irqs */ | 1345 | /* disable irqs */ |
1345 | writel(0, sm->regs + SM501_IRQ_MASK); | 1346 | smc501_writel(0, sm->regs + SM501_IRQ_MASK); |
1346 | 1347 | ||
1347 | dramctrl = readl(sm->regs + SM501_DRAM_CONTROL); | 1348 | dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL); |
1348 | mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7]; | 1349 | mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7]; |
1349 | 1350 | ||
1350 | dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n", | 1351 | dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n", |
@@ -1489,7 +1490,7 @@ static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state) | |||
1489 | struct sm501_devdata *sm = platform_get_drvdata(pdev); | 1490 | struct sm501_devdata *sm = platform_get_drvdata(pdev); |
1490 | 1491 | ||
1491 | sm->in_suspend = 1; | 1492 | sm->in_suspend = 1; |
1492 | sm->pm_misc = readl(sm->regs + SM501_MISC_CONTROL); | 1493 | sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL); |
1493 | 1494 | ||
1494 | sm501_dump_regs(sm); | 1495 | sm501_dump_regs(sm); |
1495 | 1496 | ||
@@ -1513,9 +1514,9 @@ static int sm501_plat_resume(struct platform_device *pdev) | |||
1513 | 1514 | ||
1514 | /* check to see if we are in the same state as when suspended */ | 1515 | /* check to see if we are in the same state as when suspended */ |
1515 | 1516 | ||
1516 | if (readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) { | 1517 | if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) { |
1517 | dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n"); | 1518 | dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n"); |
1518 | writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL); | 1519 | smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL); |
1519 | 1520 | ||
1520 | /* our suspend causes the controller state to change, | 1521 | /* our suspend causes the controller state to change, |
1521 | * either by something attempting setup, power loss, | 1522 | * either by something attempting setup, power loss, |
diff --git a/drivers/video/sm501fb.c b/drivers/video/sm501fb.c index bcb44a594ebc..5df406c87c50 100644 --- a/drivers/video/sm501fb.c +++ b/drivers/video/sm501fb.c | |||
@@ -117,7 +117,7 @@ static inline int v_total(struct fb_var_screeninfo *var) | |||
117 | 117 | ||
118 | static inline void sm501fb_sync_regs(struct sm501fb_info *info) | 118 | static inline void sm501fb_sync_regs(struct sm501fb_info *info) |
119 | { | 119 | { |
120 | readl(info->regs); | 120 | smc501_readl(info->regs); |
121 | } | 121 | } |
122 | 122 | ||
123 | /* sm501_alloc_mem | 123 | /* sm501_alloc_mem |
@@ -262,7 +262,7 @@ static void sm501fb_setup_gamma(struct sm501fb_info *fbi, | |||
262 | 262 | ||
263 | /* set gamma values */ | 263 | /* set gamma values */ |
264 | for (offset = 0; offset < 256 * 4; offset += 4) { | 264 | for (offset = 0; offset < 256 * 4; offset += 4) { |
265 | writel(value, fbi->regs + palette + offset); | 265 | smc501_writel(value, fbi->regs + palette + offset); |
266 | value += 0x010101; /* Advance RGB by 1,1,1.*/ | 266 | value += 0x010101; /* Advance RGB by 1,1,1.*/ |
267 | } | 267 | } |
268 | } | 268 | } |
@@ -476,7 +476,8 @@ static int sm501fb_set_par_common(struct fb_info *info, | |||
476 | 476 | ||
477 | /* set start of framebuffer to the screen */ | 477 | /* set start of framebuffer to the screen */ |
478 | 478 | ||
479 | writel(par->screen.sm_addr | SM501_ADDR_FLIP, fbi->regs + head_addr); | 479 | smc501_writel(par->screen.sm_addr | SM501_ADDR_FLIP, |
480 | fbi->regs + head_addr); | ||
480 | 481 | ||
481 | /* program CRT clock */ | 482 | /* program CRT clock */ |
482 | 483 | ||
@@ -519,7 +520,7 @@ static void sm501fb_set_par_geometry(struct fb_info *info, | |||
519 | reg = info->fix.line_length; | 520 | reg = info->fix.line_length; |
520 | reg |= ((var->xres * var->bits_per_pixel)/8) << 16; | 521 | reg |= ((var->xres * var->bits_per_pixel)/8) << 16; |
521 | 522 | ||
522 | writel(reg, fbi->regs + (par->head == HEAD_CRT ? | 523 | smc501_writel(reg, fbi->regs + (par->head == HEAD_CRT ? |
523 | SM501_DC_CRT_FB_OFFSET : SM501_DC_PANEL_FB_OFFSET)); | 524 | SM501_DC_CRT_FB_OFFSET : SM501_DC_PANEL_FB_OFFSET)); |
524 | 525 | ||
525 | /* program horizontal total */ | 526 | /* program horizontal total */ |
@@ -527,27 +528,27 @@ static void sm501fb_set_par_geometry(struct fb_info *info, | |||
527 | reg = (h_total(var) - 1) << 16; | 528 | reg = (h_total(var) - 1) << 16; |
528 | reg |= (var->xres - 1); | 529 | reg |= (var->xres - 1); |
529 | 530 | ||
530 | writel(reg, base + SM501_OFF_DC_H_TOT); | 531 | smc501_writel(reg, base + SM501_OFF_DC_H_TOT); |
531 | 532 | ||
532 | /* program horizontal sync */ | 533 | /* program horizontal sync */ |
533 | 534 | ||
534 | reg = var->hsync_len << 16; | 535 | reg = var->hsync_len << 16; |
535 | reg |= var->xres + var->right_margin - 1; | 536 | reg |= var->xres + var->right_margin - 1; |
536 | 537 | ||
537 | writel(reg, base + SM501_OFF_DC_H_SYNC); | 538 | smc501_writel(reg, base + SM501_OFF_DC_H_SYNC); |
538 | 539 | ||
539 | /* program vertical total */ | 540 | /* program vertical total */ |
540 | 541 | ||
541 | reg = (v_total(var) - 1) << 16; | 542 | reg = (v_total(var) - 1) << 16; |
542 | reg |= (var->yres - 1); | 543 | reg |= (var->yres - 1); |
543 | 544 | ||
544 | writel(reg, base + SM501_OFF_DC_V_TOT); | 545 | smc501_writel(reg, base + SM501_OFF_DC_V_TOT); |
545 | 546 | ||
546 | /* program vertical sync */ | 547 | /* program vertical sync */ |
547 | reg = var->vsync_len << 16; | 548 | reg = var->vsync_len << 16; |
548 | reg |= var->yres + var->lower_margin - 1; | 549 | reg |= var->yres + var->lower_margin - 1; |
549 | 550 | ||
550 | writel(reg, base + SM501_OFF_DC_V_SYNC); | 551 | smc501_writel(reg, base + SM501_OFF_DC_V_SYNC); |
551 | } | 552 | } |
552 | 553 | ||
553 | /* sm501fb_pan_crt | 554 | /* sm501fb_pan_crt |
@@ -566,15 +567,15 @@ static int sm501fb_pan_crt(struct fb_var_screeninfo *var, | |||
566 | 567 | ||
567 | xoffs = var->xoffset * bytes_pixel; | 568 | xoffs = var->xoffset * bytes_pixel; |
568 | 569 | ||
569 | reg = readl(fbi->regs + SM501_DC_CRT_CONTROL); | 570 | reg = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL); |
570 | 571 | ||
571 | reg &= ~SM501_DC_CRT_CONTROL_PIXEL_MASK; | 572 | reg &= ~SM501_DC_CRT_CONTROL_PIXEL_MASK; |
572 | reg |= ((xoffs & 15) / bytes_pixel) << 4; | 573 | reg |= ((xoffs & 15) / bytes_pixel) << 4; |
573 | writel(reg, fbi->regs + SM501_DC_CRT_CONTROL); | 574 | smc501_writel(reg, fbi->regs + SM501_DC_CRT_CONTROL); |
574 | 575 | ||
575 | reg = (par->screen.sm_addr + xoffs + | 576 | reg = (par->screen.sm_addr + xoffs + |
576 | var->yoffset * info->fix.line_length); | 577 | var->yoffset * info->fix.line_length); |
577 | writel(reg | SM501_ADDR_FLIP, fbi->regs + SM501_DC_CRT_FB_ADDR); | 578 | smc501_writel(reg | SM501_ADDR_FLIP, fbi->regs + SM501_DC_CRT_FB_ADDR); |
578 | 579 | ||
579 | sm501fb_sync_regs(fbi); | 580 | sm501fb_sync_regs(fbi); |
580 | return 0; | 581 | return 0; |
@@ -593,10 +594,10 @@ static int sm501fb_pan_pnl(struct fb_var_screeninfo *var, | |||
593 | unsigned long reg; | 594 | unsigned long reg; |
594 | 595 | ||
595 | reg = var->xoffset | (var->xres_virtual << 16); | 596 | reg = var->xoffset | (var->xres_virtual << 16); |
596 | writel(reg, fbi->regs + SM501_DC_PANEL_FB_WIDTH); | 597 | smc501_writel(reg, fbi->regs + SM501_DC_PANEL_FB_WIDTH); |
597 | 598 | ||
598 | reg = var->yoffset | (var->yres_virtual << 16); | 599 | reg = var->yoffset | (var->yres_virtual << 16); |
599 | writel(reg, fbi->regs + SM501_DC_PANEL_FB_HEIGHT); | 600 | smc501_writel(reg, fbi->regs + SM501_DC_PANEL_FB_HEIGHT); |
600 | 601 | ||
601 | sm501fb_sync_regs(fbi); | 602 | sm501fb_sync_regs(fbi); |
602 | return 0; | 603 | return 0; |
@@ -622,7 +623,7 @@ static int sm501fb_set_par_crt(struct fb_info *info) | |||
622 | /* enable CRT DAC - note 0 is on!*/ | 623 | /* enable CRT DAC - note 0 is on!*/ |
623 | sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER); | 624 | sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER); |
624 | 625 | ||
625 | control = readl(fbi->regs + SM501_DC_CRT_CONTROL); | 626 | control = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL); |
626 | 627 | ||
627 | control &= (SM501_DC_CRT_CONTROL_PIXEL_MASK | | 628 | control &= (SM501_DC_CRT_CONTROL_PIXEL_MASK | |
628 | SM501_DC_CRT_CONTROL_GAMMA | | 629 | SM501_DC_CRT_CONTROL_GAMMA | |
@@ -684,7 +685,7 @@ static int sm501fb_set_par_crt(struct fb_info *info) | |||
684 | out_update: | 685 | out_update: |
685 | dev_dbg(fbi->dev, "new control is %08lx\n", control); | 686 | dev_dbg(fbi->dev, "new control is %08lx\n", control); |
686 | 687 | ||
687 | writel(control, fbi->regs + SM501_DC_CRT_CONTROL); | 688 | smc501_writel(control, fbi->regs + SM501_DC_CRT_CONTROL); |
688 | sm501fb_sync_regs(fbi); | 689 | sm501fb_sync_regs(fbi); |
689 | 690 | ||
690 | return 0; | 691 | return 0; |
@@ -696,18 +697,18 @@ static void sm501fb_panel_power(struct sm501fb_info *fbi, int to) | |||
696 | void __iomem *ctrl_reg = fbi->regs + SM501_DC_PANEL_CONTROL; | 697 | void __iomem *ctrl_reg = fbi->regs + SM501_DC_PANEL_CONTROL; |
697 | struct sm501_platdata_fbsub *pd = fbi->pdata->fb_pnl; | 698 | struct sm501_platdata_fbsub *pd = fbi->pdata->fb_pnl; |
698 | 699 | ||
699 | control = readl(ctrl_reg); | 700 | control = smc501_readl(ctrl_reg); |
700 | 701 | ||
701 | if (to && (control & SM501_DC_PANEL_CONTROL_VDD) == 0) { | 702 | if (to && (control & SM501_DC_PANEL_CONTROL_VDD) == 0) { |
702 | /* enable panel power */ | 703 | /* enable panel power */ |
703 | 704 | ||
704 | control |= SM501_DC_PANEL_CONTROL_VDD; /* FPVDDEN */ | 705 | control |= SM501_DC_PANEL_CONTROL_VDD; /* FPVDDEN */ |
705 | writel(control, ctrl_reg); | 706 | smc501_writel(control, ctrl_reg); |
706 | sm501fb_sync_regs(fbi); | 707 | sm501fb_sync_regs(fbi); |
707 | mdelay(10); | 708 | mdelay(10); |
708 | 709 | ||
709 | control |= SM501_DC_PANEL_CONTROL_DATA; /* DATA */ | 710 | control |= SM501_DC_PANEL_CONTROL_DATA; /* DATA */ |
710 | writel(control, ctrl_reg); | 711 | smc501_writel(control, ctrl_reg); |
711 | sm501fb_sync_regs(fbi); | 712 | sm501fb_sync_regs(fbi); |
712 | mdelay(10); | 713 | mdelay(10); |
713 | 714 | ||
@@ -719,7 +720,7 @@ static void sm501fb_panel_power(struct sm501fb_info *fbi, int to) | |||
719 | else | 720 | else |
720 | control |= SM501_DC_PANEL_CONTROL_BIAS; | 721 | control |= SM501_DC_PANEL_CONTROL_BIAS; |
721 | 722 | ||
722 | writel(control, ctrl_reg); | 723 | smc501_writel(control, ctrl_reg); |
723 | sm501fb_sync_regs(fbi); | 724 | sm501fb_sync_regs(fbi); |
724 | mdelay(10); | 725 | mdelay(10); |
725 | } | 726 | } |
@@ -730,7 +731,7 @@ static void sm501fb_panel_power(struct sm501fb_info *fbi, int to) | |||
730 | else | 731 | else |
731 | control |= SM501_DC_PANEL_CONTROL_FPEN; | 732 | control |= SM501_DC_PANEL_CONTROL_FPEN; |
732 | 733 | ||
733 | writel(control, ctrl_reg); | 734 | smc501_writel(control, ctrl_reg); |
734 | sm501fb_sync_regs(fbi); | 735 | sm501fb_sync_regs(fbi); |
735 | mdelay(10); | 736 | mdelay(10); |
736 | } | 737 | } |
@@ -742,7 +743,7 @@ static void sm501fb_panel_power(struct sm501fb_info *fbi, int to) | |||
742 | else | 743 | else |
743 | control &= ~SM501_DC_PANEL_CONTROL_FPEN; | 744 | control &= ~SM501_DC_PANEL_CONTROL_FPEN; |
744 | 745 | ||
745 | writel(control, ctrl_reg); | 746 | smc501_writel(control, ctrl_reg); |
746 | sm501fb_sync_regs(fbi); | 747 | sm501fb_sync_regs(fbi); |
747 | mdelay(10); | 748 | mdelay(10); |
748 | } | 749 | } |
@@ -753,18 +754,18 @@ static void sm501fb_panel_power(struct sm501fb_info *fbi, int to) | |||
753 | else | 754 | else |
754 | control &= ~SM501_DC_PANEL_CONTROL_BIAS; | 755 | control &= ~SM501_DC_PANEL_CONTROL_BIAS; |
755 | 756 | ||
756 | writel(control, ctrl_reg); | 757 | smc501_writel(control, ctrl_reg); |
757 | sm501fb_sync_regs(fbi); | 758 | sm501fb_sync_regs(fbi); |
758 | mdelay(10); | 759 | mdelay(10); |
759 | } | 760 | } |
760 | 761 | ||
761 | control &= ~SM501_DC_PANEL_CONTROL_DATA; | 762 | control &= ~SM501_DC_PANEL_CONTROL_DATA; |
762 | writel(control, ctrl_reg); | 763 | smc501_writel(control, ctrl_reg); |
763 | sm501fb_sync_regs(fbi); | 764 | sm501fb_sync_regs(fbi); |
764 | mdelay(10); | 765 | mdelay(10); |
765 | 766 | ||
766 | control &= ~SM501_DC_PANEL_CONTROL_VDD; | 767 | control &= ~SM501_DC_PANEL_CONTROL_VDD; |
767 | writel(control, ctrl_reg); | 768 | smc501_writel(control, ctrl_reg); |
768 | sm501fb_sync_regs(fbi); | 769 | sm501fb_sync_regs(fbi); |
769 | mdelay(10); | 770 | mdelay(10); |
770 | } | 771 | } |
@@ -799,7 +800,7 @@ static int sm501fb_set_par_pnl(struct fb_info *info) | |||
799 | 800 | ||
800 | /* update control register */ | 801 | /* update control register */ |
801 | 802 | ||
802 | control = readl(fbi->regs + SM501_DC_PANEL_CONTROL); | 803 | control = smc501_readl(fbi->regs + SM501_DC_PANEL_CONTROL); |
803 | control &= (SM501_DC_PANEL_CONTROL_GAMMA | | 804 | control &= (SM501_DC_PANEL_CONTROL_GAMMA | |
804 | SM501_DC_PANEL_CONTROL_VDD | | 805 | SM501_DC_PANEL_CONTROL_VDD | |
805 | SM501_DC_PANEL_CONTROL_DATA | | 806 | SM501_DC_PANEL_CONTROL_DATA | |
@@ -833,16 +834,16 @@ static int sm501fb_set_par_pnl(struct fb_info *info) | |||
833 | BUG(); | 834 | BUG(); |
834 | } | 835 | } |
835 | 836 | ||
836 | writel(0x0, fbi->regs + SM501_DC_PANEL_PANNING_CONTROL); | 837 | smc501_writel(0x0, fbi->regs + SM501_DC_PANEL_PANNING_CONTROL); |
837 | 838 | ||
838 | /* panel plane top left and bottom right location */ | 839 | /* panel plane top left and bottom right location */ |
839 | 840 | ||
840 | writel(0x00, fbi->regs + SM501_DC_PANEL_TL_LOC); | 841 | smc501_writel(0x00, fbi->regs + SM501_DC_PANEL_TL_LOC); |
841 | 842 | ||
842 | reg = var->xres - 1; | 843 | reg = var->xres - 1; |
843 | reg |= (var->yres - 1) << 16; | 844 | reg |= (var->yres - 1) << 16; |
844 | 845 | ||
845 | writel(reg, fbi->regs + SM501_DC_PANEL_BR_LOC); | 846 | smc501_writel(reg, fbi->regs + SM501_DC_PANEL_BR_LOC); |
846 | 847 | ||
847 | /* program panel control register */ | 848 | /* program panel control register */ |
848 | 849 | ||
@@ -855,7 +856,7 @@ static int sm501fb_set_par_pnl(struct fb_info *info) | |||
855 | if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0) | 856 | if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0) |
856 | control |= SM501_DC_PANEL_CONTROL_VSP; | 857 | control |= SM501_DC_PANEL_CONTROL_VSP; |
857 | 858 | ||
858 | writel(control, fbi->regs + SM501_DC_PANEL_CONTROL); | 859 | smc501_writel(control, fbi->regs + SM501_DC_PANEL_CONTROL); |
859 | sm501fb_sync_regs(fbi); | 860 | sm501fb_sync_regs(fbi); |
860 | 861 | ||
861 | /* ensure the panel interface is not tristated at this point */ | 862 | /* ensure the panel interface is not tristated at this point */ |
@@ -924,7 +925,7 @@ static int sm501fb_setcolreg(unsigned regno, | |||
924 | val |= (green >> 8) << 8; | 925 | val |= (green >> 8) << 8; |
925 | val |= blue >> 8; | 926 | val |= blue >> 8; |
926 | 927 | ||
927 | writel(val, base + (regno * 4)); | 928 | smc501_writel(val, base + (regno * 4)); |
928 | } | 929 | } |
929 | 930 | ||
930 | break; | 931 | break; |
@@ -980,7 +981,7 @@ static int sm501fb_blank_crt(int blank_mode, struct fb_info *info) | |||
980 | 981 | ||
981 | dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info); | 982 | dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info); |
982 | 983 | ||
983 | ctrl = readl(fbi->regs + SM501_DC_CRT_CONTROL); | 984 | ctrl = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL); |
984 | 985 | ||
985 | switch (blank_mode) { | 986 | switch (blank_mode) { |
986 | case FB_BLANK_POWERDOWN: | 987 | case FB_BLANK_POWERDOWN: |
@@ -1004,7 +1005,7 @@ static int sm501fb_blank_crt(int blank_mode, struct fb_info *info) | |||
1004 | 1005 | ||
1005 | } | 1006 | } |
1006 | 1007 | ||
1007 | writel(ctrl, fbi->regs + SM501_DC_CRT_CONTROL); | 1008 | smc501_writel(ctrl, fbi->regs + SM501_DC_CRT_CONTROL); |
1008 | sm501fb_sync_regs(fbi); | 1009 | sm501fb_sync_regs(fbi); |
1009 | 1010 | ||
1010 | return 0; | 1011 | return 0; |
@@ -1041,12 +1042,14 @@ static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor) | |||
1041 | if (cursor->image.depth > 1) | 1042 | if (cursor->image.depth > 1) |
1042 | return -EINVAL; | 1043 | return -EINVAL; |
1043 | 1044 | ||
1044 | hwc_addr = readl(base + SM501_OFF_HWC_ADDR); | 1045 | hwc_addr = smc501_readl(base + SM501_OFF_HWC_ADDR); |
1045 | 1046 | ||
1046 | if (cursor->enable) | 1047 | if (cursor->enable) |
1047 | writel(hwc_addr | SM501_HWC_EN, base + SM501_OFF_HWC_ADDR); | 1048 | smc501_writel(hwc_addr | SM501_HWC_EN, |
1049 | base + SM501_OFF_HWC_ADDR); | ||
1048 | else | 1050 | else |
1049 | writel(hwc_addr & ~SM501_HWC_EN, base + SM501_OFF_HWC_ADDR); | 1051 | smc501_writel(hwc_addr & ~SM501_HWC_EN, |
1052 | base + SM501_OFF_HWC_ADDR); | ||
1050 | 1053 | ||
1051 | /* set data */ | 1054 | /* set data */ |
1052 | if (cursor->set & FB_CUR_SETPOS) { | 1055 | if (cursor->set & FB_CUR_SETPOS) { |
@@ -1060,7 +1063,7 @@ static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor) | |||
1060 | 1063 | ||
1061 | //y += cursor->image.height; | 1064 | //y += cursor->image.height; |
1062 | 1065 | ||
1063 | writel(x | (y << 16), base + SM501_OFF_HWC_LOC); | 1066 | smc501_writel(x | (y << 16), base + SM501_OFF_HWC_LOC); |
1064 | } | 1067 | } |
1065 | 1068 | ||
1066 | if (cursor->set & FB_CUR_SETCMAP) { | 1069 | if (cursor->set & FB_CUR_SETCMAP) { |
@@ -1080,8 +1083,8 @@ static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor) | |||
1080 | 1083 | ||
1081 | dev_dbg(fbi->dev, "fgcol %08lx, bgcol %08lx\n", fg, bg); | 1084 | dev_dbg(fbi->dev, "fgcol %08lx, bgcol %08lx\n", fg, bg); |
1082 | 1085 | ||
1083 | writel(bg, base + SM501_OFF_HWC_COLOR_1_2); | 1086 | smc501_writel(bg, base + SM501_OFF_HWC_COLOR_1_2); |
1084 | writel(fg, base + SM501_OFF_HWC_COLOR_3); | 1087 | smc501_writel(fg, base + SM501_OFF_HWC_COLOR_3); |
1085 | } | 1088 | } |
1086 | 1089 | ||
1087 | if (cursor->set & FB_CUR_SETSIZE || | 1090 | if (cursor->set & FB_CUR_SETSIZE || |
@@ -1102,7 +1105,7 @@ static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor) | |||
1102 | __func__, cursor->image.width, cursor->image.height); | 1105 | __func__, cursor->image.width, cursor->image.height); |
1103 | 1106 | ||
1104 | for (op = 0; op < (64*64*2)/8; op+=4) | 1107 | for (op = 0; op < (64*64*2)/8; op+=4) |
1105 | writel(0x0, dst + op); | 1108 | smc501_writel(0x0, dst + op); |
1106 | 1109 | ||
1107 | for (y = 0; y < cursor->image.height; y++) { | 1110 | for (y = 0; y < cursor->image.height; y++) { |
1108 | for (x = 0; x < cursor->image.width; x++) { | 1111 | for (x = 0; x < cursor->image.width; x++) { |
@@ -1141,7 +1144,7 @@ static ssize_t sm501fb_crtsrc_show(struct device *dev, | |||
1141 | struct sm501fb_info *info = dev_get_drvdata(dev); | 1144 | struct sm501fb_info *info = dev_get_drvdata(dev); |
1142 | unsigned long ctrl; | 1145 | unsigned long ctrl; |
1143 | 1146 | ||
1144 | ctrl = readl(info->regs + SM501_DC_CRT_CONTROL); | 1147 | ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL); |
1145 | ctrl &= SM501_DC_CRT_CONTROL_SEL; | 1148 | ctrl &= SM501_DC_CRT_CONTROL_SEL; |
1146 | 1149 | ||
1147 | return snprintf(buf, PAGE_SIZE, "%s\n", ctrl ? "crt" : "panel"); | 1150 | return snprintf(buf, PAGE_SIZE, "%s\n", ctrl ? "crt" : "panel"); |
@@ -1172,7 +1175,7 @@ static ssize_t sm501fb_crtsrc_store(struct device *dev, | |||
1172 | 1175 | ||
1173 | dev_info(dev, "setting crt source to head %d\n", head); | 1176 | dev_info(dev, "setting crt source to head %d\n", head); |
1174 | 1177 | ||
1175 | ctrl = readl(info->regs + SM501_DC_CRT_CONTROL); | 1178 | ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL); |
1176 | 1179 | ||
1177 | if (head == HEAD_CRT) { | 1180 | if (head == HEAD_CRT) { |
1178 | ctrl |= SM501_DC_CRT_CONTROL_SEL; | 1181 | ctrl |= SM501_DC_CRT_CONTROL_SEL; |
@@ -1184,7 +1187,7 @@ static ssize_t sm501fb_crtsrc_store(struct device *dev, | |||
1184 | ctrl &= ~SM501_DC_CRT_CONTROL_TE; | 1187 | ctrl &= ~SM501_DC_CRT_CONTROL_TE; |
1185 | } | 1188 | } |
1186 | 1189 | ||
1187 | writel(ctrl, info->regs + SM501_DC_CRT_CONTROL); | 1190 | smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL); |
1188 | sm501fb_sync_regs(info); | 1191 | sm501fb_sync_regs(info); |
1189 | 1192 | ||
1190 | return len; | 1193 | return len; |
@@ -1205,7 +1208,8 @@ static int sm501fb_show_regs(struct sm501fb_info *info, char *ptr, | |||
1205 | unsigned int reg; | 1208 | unsigned int reg; |
1206 | 1209 | ||
1207 | for (reg = start; reg < (len + start); reg += 4) | 1210 | for (reg = start; reg < (len + start); reg += 4) |
1208 | ptr += sprintf(ptr, "%08x = %08x\n", reg, readl(mem + reg)); | 1211 | ptr += sprintf(ptr, "%08x = %08x\n", reg, |
1212 | smc501_readl(mem + reg)); | ||
1209 | 1213 | ||
1210 | return ptr - buf; | 1214 | return ptr - buf; |
1211 | } | 1215 | } |
@@ -1257,7 +1261,7 @@ static int sm501fb_sync(struct fb_info *info) | |||
1257 | 1261 | ||
1258 | /* wait for the 2d engine to be ready */ | 1262 | /* wait for the 2d engine to be ready */ |
1259 | while ((count > 0) && | 1263 | while ((count > 0) && |
1260 | (readl(fbi->regs + SM501_SYSTEM_CONTROL) & | 1264 | (smc501_readl(fbi->regs + SM501_SYSTEM_CONTROL) & |
1261 | SM501_SYSCTRL_2D_ENGINE_STATUS) != 0) | 1265 | SM501_SYSCTRL_2D_ENGINE_STATUS) != 0) |
1262 | count--; | 1266 | count--; |
1263 | 1267 | ||
@@ -1312,45 +1316,46 @@ static void sm501fb_copyarea(struct fb_info *info, const struct fb_copyarea *are | |||
1312 | return; | 1316 | return; |
1313 | 1317 | ||
1314 | /* set the base addresses */ | 1318 | /* set the base addresses */ |
1315 | writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE); | 1319 | smc501_writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE); |
1316 | writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_DESTINATION_BASE); | 1320 | smc501_writel(par->screen.sm_addr, |
1321 | fbi->regs2d + SM501_2D_DESTINATION_BASE); | ||
1317 | 1322 | ||
1318 | /* set the window width */ | 1323 | /* set the window width */ |
1319 | writel((info->var.xres << 16) | info->var.xres, | 1324 | smc501_writel((info->var.xres << 16) | info->var.xres, |
1320 | fbi->regs2d + SM501_2D_WINDOW_WIDTH); | 1325 | fbi->regs2d + SM501_2D_WINDOW_WIDTH); |
1321 | 1326 | ||
1322 | /* set window stride */ | 1327 | /* set window stride */ |
1323 | writel((info->var.xres_virtual << 16) | info->var.xres_virtual, | 1328 | smc501_writel((info->var.xres_virtual << 16) | info->var.xres_virtual, |
1324 | fbi->regs2d + SM501_2D_PITCH); | 1329 | fbi->regs2d + SM501_2D_PITCH); |
1325 | 1330 | ||
1326 | /* set data format */ | 1331 | /* set data format */ |
1327 | switch (info->var.bits_per_pixel) { | 1332 | switch (info->var.bits_per_pixel) { |
1328 | case 8: | 1333 | case 8: |
1329 | writel(0, fbi->regs2d + SM501_2D_STRETCH); | 1334 | smc501_writel(0, fbi->regs2d + SM501_2D_STRETCH); |
1330 | break; | 1335 | break; |
1331 | case 16: | 1336 | case 16: |
1332 | writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH); | 1337 | smc501_writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH); |
1333 | break; | 1338 | break; |
1334 | case 32: | 1339 | case 32: |
1335 | writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH); | 1340 | smc501_writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH); |
1336 | break; | 1341 | break; |
1337 | } | 1342 | } |
1338 | 1343 | ||
1339 | /* 2d compare mask */ | 1344 | /* 2d compare mask */ |
1340 | writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK); | 1345 | smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK); |
1341 | 1346 | ||
1342 | /* 2d mask */ | 1347 | /* 2d mask */ |
1343 | writel(0xffffffff, fbi->regs2d + SM501_2D_MASK); | 1348 | smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_MASK); |
1344 | 1349 | ||
1345 | /* source and destination x y */ | 1350 | /* source and destination x y */ |
1346 | writel((sx << 16) | sy, fbi->regs2d + SM501_2D_SOURCE); | 1351 | smc501_writel((sx << 16) | sy, fbi->regs2d + SM501_2D_SOURCE); |
1347 | writel((dx << 16) | dy, fbi->regs2d + SM501_2D_DESTINATION); | 1352 | smc501_writel((dx << 16) | dy, fbi->regs2d + SM501_2D_DESTINATION); |
1348 | 1353 | ||
1349 | /* w/h */ | 1354 | /* w/h */ |
1350 | writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION); | 1355 | smc501_writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION); |
1351 | 1356 | ||
1352 | /* do area move */ | 1357 | /* do area move */ |
1353 | writel(0x800000cc | rtl, fbi->regs2d + SM501_2D_CONTROL); | 1358 | smc501_writel(0x800000cc | rtl, fbi->regs2d + SM501_2D_CONTROL); |
1354 | } | 1359 | } |
1355 | 1360 | ||
1356 | static void sm501fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | 1361 | static void sm501fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) |
@@ -1372,47 +1377,49 @@ static void sm501fb_fillrect(struct fb_info *info, const struct fb_fillrect *rec | |||
1372 | return; | 1377 | return; |
1373 | 1378 | ||
1374 | /* set the base addresses */ | 1379 | /* set the base addresses */ |
1375 | writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE); | 1380 | smc501_writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE); |
1376 | writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_DESTINATION_BASE); | 1381 | smc501_writel(par->screen.sm_addr, |
1382 | fbi->regs2d + SM501_2D_DESTINATION_BASE); | ||
1377 | 1383 | ||
1378 | /* set the window width */ | 1384 | /* set the window width */ |
1379 | writel((info->var.xres << 16) | info->var.xres, | 1385 | smc501_writel((info->var.xres << 16) | info->var.xres, |
1380 | fbi->regs2d + SM501_2D_WINDOW_WIDTH); | 1386 | fbi->regs2d + SM501_2D_WINDOW_WIDTH); |
1381 | 1387 | ||
1382 | /* set window stride */ | 1388 | /* set window stride */ |
1383 | writel((info->var.xres_virtual << 16) | info->var.xres_virtual, | 1389 | smc501_writel((info->var.xres_virtual << 16) | info->var.xres_virtual, |
1384 | fbi->regs2d + SM501_2D_PITCH); | 1390 | fbi->regs2d + SM501_2D_PITCH); |
1385 | 1391 | ||
1386 | /* set data format */ | 1392 | /* set data format */ |
1387 | switch (info->var.bits_per_pixel) { | 1393 | switch (info->var.bits_per_pixel) { |
1388 | case 8: | 1394 | case 8: |
1389 | writel(0, fbi->regs2d + SM501_2D_STRETCH); | 1395 | smc501_writel(0, fbi->regs2d + SM501_2D_STRETCH); |
1390 | break; | 1396 | break; |
1391 | case 16: | 1397 | case 16: |
1392 | writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH); | 1398 | smc501_writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH); |
1393 | break; | 1399 | break; |
1394 | case 32: | 1400 | case 32: |
1395 | writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH); | 1401 | smc501_writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH); |
1396 | break; | 1402 | break; |
1397 | } | 1403 | } |
1398 | 1404 | ||
1399 | /* 2d compare mask */ | 1405 | /* 2d compare mask */ |
1400 | writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK); | 1406 | smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK); |
1401 | 1407 | ||
1402 | /* 2d mask */ | 1408 | /* 2d mask */ |
1403 | writel(0xffffffff, fbi->regs2d + SM501_2D_MASK); | 1409 | smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_MASK); |
1404 | 1410 | ||
1405 | /* colour */ | 1411 | /* colour */ |
1406 | writel(rect->color, fbi->regs2d + SM501_2D_FOREGROUND); | 1412 | smc501_writel(rect->color, fbi->regs2d + SM501_2D_FOREGROUND); |
1407 | 1413 | ||
1408 | /* x y */ | 1414 | /* x y */ |
1409 | writel((rect->dx << 16) | rect->dy, fbi->regs2d + SM501_2D_DESTINATION); | 1415 | smc501_writel((rect->dx << 16) | rect->dy, |
1416 | fbi->regs2d + SM501_2D_DESTINATION); | ||
1410 | 1417 | ||
1411 | /* w/h */ | 1418 | /* w/h */ |
1412 | writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION); | 1419 | smc501_writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION); |
1413 | 1420 | ||
1414 | /* do rectangle fill */ | 1421 | /* do rectangle fill */ |
1415 | writel(0x800100cc, fbi->regs2d + SM501_2D_CONTROL); | 1422 | smc501_writel(0x800100cc, fbi->regs2d + SM501_2D_CONTROL); |
1416 | } | 1423 | } |
1417 | 1424 | ||
1418 | 1425 | ||
@@ -1470,11 +1477,12 @@ static int sm501_init_cursor(struct fb_info *fbi, unsigned int reg_base) | |||
1470 | 1477 | ||
1471 | /* initialise the colour registers */ | 1478 | /* initialise the colour registers */ |
1472 | 1479 | ||
1473 | writel(par->cursor.sm_addr, par->cursor_regs + SM501_OFF_HWC_ADDR); | 1480 | smc501_writel(par->cursor.sm_addr, |
1481 | par->cursor_regs + SM501_OFF_HWC_ADDR); | ||
1474 | 1482 | ||
1475 | writel(0x00, par->cursor_regs + SM501_OFF_HWC_LOC); | 1483 | smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_LOC); |
1476 | writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_1_2); | 1484 | smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_1_2); |
1477 | writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_3); | 1485 | smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_3); |
1478 | sm501fb_sync_regs(info); | 1486 | sm501fb_sync_regs(info); |
1479 | 1487 | ||
1480 | return 0; | 1488 | return 0; |
@@ -1581,7 +1589,7 @@ static int sm501fb_start(struct sm501fb_info *info, | |||
1581 | 1589 | ||
1582 | /* clear palette ram - undefined at power on */ | 1590 | /* clear palette ram - undefined at power on */ |
1583 | for (k = 0; k < (256 * 3); k++) | 1591 | for (k = 0; k < (256 * 3); k++) |
1584 | writel(0, info->regs + SM501_DC_PANEL_PALETTE + (k * 4)); | 1592 | smc501_writel(0, info->regs + SM501_DC_PANEL_PALETTE + (k * 4)); |
1585 | 1593 | ||
1586 | /* enable display controller */ | 1594 | /* enable display controller */ |
1587 | sm501_unit_power(dev->parent, SM501_GATE_DISPLAY, 1); | 1595 | sm501_unit_power(dev->parent, SM501_GATE_DISPLAY, 1); |
@@ -1649,20 +1657,20 @@ static int sm501fb_init_fb(struct fb_info *fb, | |||
1649 | switch (head) { | 1657 | switch (head) { |
1650 | case HEAD_CRT: | 1658 | case HEAD_CRT: |
1651 | pd = info->pdata->fb_crt; | 1659 | pd = info->pdata->fb_crt; |
1652 | ctrl = readl(info->regs + SM501_DC_CRT_CONTROL); | 1660 | ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL); |
1653 | enable = (ctrl & SM501_DC_CRT_CONTROL_ENABLE) ? 1 : 0; | 1661 | enable = (ctrl & SM501_DC_CRT_CONTROL_ENABLE) ? 1 : 0; |
1654 | 1662 | ||
1655 | /* ensure we set the correct source register */ | 1663 | /* ensure we set the correct source register */ |
1656 | if (info->pdata->fb_route != SM501_FB_CRT_PANEL) { | 1664 | if (info->pdata->fb_route != SM501_FB_CRT_PANEL) { |
1657 | ctrl |= SM501_DC_CRT_CONTROL_SEL; | 1665 | ctrl |= SM501_DC_CRT_CONTROL_SEL; |
1658 | writel(ctrl, info->regs + SM501_DC_CRT_CONTROL); | 1666 | smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL); |
1659 | } | 1667 | } |
1660 | 1668 | ||
1661 | break; | 1669 | break; |
1662 | 1670 | ||
1663 | case HEAD_PANEL: | 1671 | case HEAD_PANEL: |
1664 | pd = info->pdata->fb_pnl; | 1672 | pd = info->pdata->fb_pnl; |
1665 | ctrl = readl(info->regs + SM501_DC_PANEL_CONTROL); | 1673 | ctrl = smc501_readl(info->regs + SM501_DC_PANEL_CONTROL); |
1666 | enable = (ctrl & SM501_DC_PANEL_CONTROL_EN) ? 1 : 0; | 1674 | enable = (ctrl & SM501_DC_PANEL_CONTROL_EN) ? 1 : 0; |
1667 | break; | 1675 | break; |
1668 | 1676 | ||
@@ -1680,7 +1688,7 @@ static int sm501fb_init_fb(struct fb_info *fb, | |||
1680 | 1688 | ||
1681 | if (head == HEAD_CRT && info->pdata->fb_route == SM501_FB_CRT_PANEL) { | 1689 | if (head == HEAD_CRT && info->pdata->fb_route == SM501_FB_CRT_PANEL) { |
1682 | ctrl &= ~SM501_DC_CRT_CONTROL_SEL; | 1690 | ctrl &= ~SM501_DC_CRT_CONTROL_SEL; |
1683 | writel(ctrl, info->regs + SM501_DC_CRT_CONTROL); | 1691 | smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL); |
1684 | enable = 0; | 1692 | enable = 0; |
1685 | } | 1693 | } |
1686 | 1694 | ||
@@ -2085,7 +2093,7 @@ static int sm501fb_suspend(struct platform_device *pdev, pm_message_t state) | |||
2085 | struct sm501fb_info *info = platform_get_drvdata(pdev); | 2093 | struct sm501fb_info *info = platform_get_drvdata(pdev); |
2086 | 2094 | ||
2087 | /* store crt control to resume with */ | 2095 | /* store crt control to resume with */ |
2088 | info->pm_crt_ctrl = readl(info->regs + SM501_DC_CRT_CONTROL); | 2096 | info->pm_crt_ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL); |
2089 | 2097 | ||
2090 | sm501fb_suspend_fb(info, HEAD_CRT); | 2098 | sm501fb_suspend_fb(info, HEAD_CRT); |
2091 | sm501fb_suspend_fb(info, HEAD_PANEL); | 2099 | sm501fb_suspend_fb(info, HEAD_PANEL); |
@@ -2109,10 +2117,10 @@ static int sm501fb_resume(struct platform_device *pdev) | |||
2109 | 2117 | ||
2110 | /* restore the items we want to be saved for crt control */ | 2118 | /* restore the items we want to be saved for crt control */ |
2111 | 2119 | ||
2112 | crt_ctrl = readl(info->regs + SM501_DC_CRT_CONTROL); | 2120 | crt_ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL); |
2113 | crt_ctrl &= ~SM501_CRT_CTRL_SAVE; | 2121 | crt_ctrl &= ~SM501_CRT_CTRL_SAVE; |
2114 | crt_ctrl |= info->pm_crt_ctrl & SM501_CRT_CTRL_SAVE; | 2122 | crt_ctrl |= info->pm_crt_ctrl & SM501_CRT_CTRL_SAVE; |
2115 | writel(crt_ctrl, info->regs + SM501_DC_CRT_CONTROL); | 2123 | smc501_writel(crt_ctrl, info->regs + SM501_DC_CRT_CONTROL); |
2116 | 2124 | ||
2117 | sm501fb_resume_fb(info, HEAD_CRT); | 2125 | sm501fb_resume_fb(info, HEAD_CRT); |
2118 | sm501fb_resume_fb(info, HEAD_PANEL); | 2126 | sm501fb_resume_fb(info, HEAD_PANEL); |