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-rw-r--r--drivers/gpu/drm/ati_pcigart.c2
-rw-r--r--drivers/gpu/drm/drm_bufs.c33
-rw-r--r--drivers/gpu/drm/drm_crtc.c6
-rw-r--r--drivers/gpu/drm/drm_crtc_helper.c10
-rw-r--r--drivers/gpu/drm/drm_drv.c25
-rw-r--r--drivers/gpu/drm/drm_edid.c841
-rw-r--r--drivers/gpu/drm/drm_edid_modes.h380
-rw-r--r--drivers/gpu/drm/drm_fb_helper.c3
-rw-r--r--drivers/gpu/drm/drm_fops.c16
-rw-r--r--drivers/gpu/drm/drm_gem.c2
-rw-r--r--drivers/gpu/drm/drm_ioctl.c1
-rw-r--r--drivers/gpu/drm/drm_vm.c2
-rw-r--r--drivers/gpu/drm/i810/i810_dma.c30
-rw-r--r--drivers/gpu/drm/i830/i830_dma.c28
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c80
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c26
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c4
-rw-r--r--drivers/gpu/drm/i915/intel_display.c15
-rw-r--r--drivers/gpu/drm/i915/intel_fb.c4
-rw-r--r--drivers/gpu/drm/mga/mga_state.c26
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_channel.c24
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_display.c6
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_gem.c8
-rw-r--r--drivers/gpu/drm/nouveau/nv04_crtc.c12
-rw-r--r--drivers/gpu/drm/nouveau/nv50_crtc.c11
-rw-r--r--drivers/gpu/drm/r128/r128_state.c35
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c51
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c2
-rw-r--r--drivers/gpu/drm/radeon/r600_cp.c2
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c33
-rw-r--r--drivers/gpu/drm/radeon/radeon.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_agp.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c215
-rw-r--r--drivers/gpu/drm/radeon/radeon_clocks.c81
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c492
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c71
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_cursor.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c49
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c223
-rw-r--r--drivers/gpu/drm/radeon/radeon_fb.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c12
-rw-r--r--drivers/gpu/drm/radeon/radeon_i2c.c89
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq_kms.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c107
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c7
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h27
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c29
-rw-r--r--drivers/gpu/drm/radeon/radeon_state.c56
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rv5151
-rw-r--r--drivers/gpu/drm/savage/savage_bci.c8
-rw-r--r--drivers/gpu/drm/sis/sis_mm.c12
-rw-r--r--drivers/gpu/drm/via/via_dma.c28
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.c34
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_kms.c8
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c2
59 files changed, 1905 insertions, 1393 deletions
diff --git a/drivers/gpu/drm/ati_pcigart.c b/drivers/gpu/drm/ati_pcigart.c
index 17be051b7aa3..1c3649242208 100644
--- a/drivers/gpu/drm/ati_pcigart.c
+++ b/drivers/gpu/drm/ati_pcigart.c
@@ -152,7 +152,7 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga
152 /* we need to support large memory configurations */ 152 /* we need to support large memory configurations */
153 entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i], 153 entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
154 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 154 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
155 if (entry->busaddr[i] == 0) { 155 if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) {
156 DRM_ERROR("unable to map PCIGART pages!\n"); 156 DRM_ERROR("unable to map PCIGART pages!\n");
157 drm_ati_pcigart_cleanup(dev, gart_info); 157 drm_ati_pcigart_cleanup(dev, gart_info);
158 address = NULL; 158 address = NULL;
diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index a5c9ce93bbcb..3e257a50bf56 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -328,14 +328,13 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset,
328 return -EINVAL; 328 return -EINVAL;
329 } 329 }
330 330
331 list = kmalloc(sizeof(*list), GFP_KERNEL); 331 list = kzalloc(sizeof(*list), GFP_KERNEL);
332 if (!list) { 332 if (!list) {
333 if (map->type == _DRM_REGISTERS) 333 if (map->type == _DRM_REGISTERS)
334 iounmap(map->handle); 334 iounmap(map->handle);
335 kfree(map); 335 kfree(map);
336 return -EINVAL; 336 return -EINVAL;
337 } 337 }
338 memset(list, 0, sizeof(*list));
339 list->map = map; 338 list->map = map;
340 339
341 mutex_lock(&dev->struct_mutex); 340 mutex_lock(&dev->struct_mutex);
@@ -678,13 +677,12 @@ int drm_addbufs_agp(struct drm_device * dev, struct drm_buf_desc * request)
678 return -EINVAL; 677 return -EINVAL;
679 } 678 }
680 679
681 entry->buflist = kmalloc(count * sizeof(*entry->buflist), GFP_KERNEL); 680 entry->buflist = kzalloc(count * sizeof(*entry->buflist), GFP_KERNEL);
682 if (!entry->buflist) { 681 if (!entry->buflist) {
683 mutex_unlock(&dev->struct_mutex); 682 mutex_unlock(&dev->struct_mutex);
684 atomic_dec(&dev->buf_alloc); 683 atomic_dec(&dev->buf_alloc);
685 return -ENOMEM; 684 return -ENOMEM;
686 } 685 }
687 memset(entry->buflist, 0, count * sizeof(*entry->buflist));
688 686
689 entry->buf_size = size; 687 entry->buf_size = size;
690 entry->page_order = page_order; 688 entry->page_order = page_order;
@@ -708,7 +706,7 @@ int drm_addbufs_agp(struct drm_device * dev, struct drm_buf_desc * request)
708 buf->file_priv = NULL; 706 buf->file_priv = NULL;
709 707
710 buf->dev_priv_size = dev->driver->dev_priv_size; 708 buf->dev_priv_size = dev->driver->dev_priv_size;
711 buf->dev_private = kmalloc(buf->dev_priv_size, GFP_KERNEL); 709 buf->dev_private = kzalloc(buf->dev_priv_size, GFP_KERNEL);
712 if (!buf->dev_private) { 710 if (!buf->dev_private) {
713 /* Set count correctly so we free the proper amount. */ 711 /* Set count correctly so we free the proper amount. */
714 entry->buf_count = count; 712 entry->buf_count = count;
@@ -717,7 +715,6 @@ int drm_addbufs_agp(struct drm_device * dev, struct drm_buf_desc * request)
717 atomic_dec(&dev->buf_alloc); 715 atomic_dec(&dev->buf_alloc);
718 return -ENOMEM; 716 return -ENOMEM;
719 } 717 }
720 memset(buf->dev_private, 0, buf->dev_priv_size);
721 718
722 DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address); 719 DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address);
723 720
@@ -832,22 +829,20 @@ int drm_addbufs_pci(struct drm_device * dev, struct drm_buf_desc * request)
832 return -EINVAL; 829 return -EINVAL;
833 } 830 }
834 831
835 entry->buflist = kmalloc(count * sizeof(*entry->buflist), GFP_KERNEL); 832 entry->buflist = kzalloc(count * sizeof(*entry->buflist), GFP_KERNEL);
836 if (!entry->buflist) { 833 if (!entry->buflist) {
837 mutex_unlock(&dev->struct_mutex); 834 mutex_unlock(&dev->struct_mutex);
838 atomic_dec(&dev->buf_alloc); 835 atomic_dec(&dev->buf_alloc);
839 return -ENOMEM; 836 return -ENOMEM;
840 } 837 }
841 memset(entry->buflist, 0, count * sizeof(*entry->buflist));
842 838
843 entry->seglist = kmalloc(count * sizeof(*entry->seglist), GFP_KERNEL); 839 entry->seglist = kzalloc(count * sizeof(*entry->seglist), GFP_KERNEL);
844 if (!entry->seglist) { 840 if (!entry->seglist) {
845 kfree(entry->buflist); 841 kfree(entry->buflist);
846 mutex_unlock(&dev->struct_mutex); 842 mutex_unlock(&dev->struct_mutex);
847 atomic_dec(&dev->buf_alloc); 843 atomic_dec(&dev->buf_alloc);
848 return -ENOMEM; 844 return -ENOMEM;
849 } 845 }
850 memset(entry->seglist, 0, count * sizeof(*entry->seglist));
851 846
852 /* Keep the original pagelist until we know all the allocations 847 /* Keep the original pagelist until we know all the allocations
853 * have succeeded 848 * have succeeded
@@ -911,8 +906,8 @@ int drm_addbufs_pci(struct drm_device * dev, struct drm_buf_desc * request)
911 buf->file_priv = NULL; 906 buf->file_priv = NULL;
912 907
913 buf->dev_priv_size = dev->driver->dev_priv_size; 908 buf->dev_priv_size = dev->driver->dev_priv_size;
914 buf->dev_private = kmalloc(buf->dev_priv_size, 909 buf->dev_private = kzalloc(buf->dev_priv_size,
915 GFP_KERNEL); 910 GFP_KERNEL);
916 if (!buf->dev_private) { 911 if (!buf->dev_private) {
917 /* Set count correctly so we free the proper amount. */ 912 /* Set count correctly so we free the proper amount. */
918 entry->buf_count = count; 913 entry->buf_count = count;
@@ -923,7 +918,6 @@ int drm_addbufs_pci(struct drm_device * dev, struct drm_buf_desc * request)
923 atomic_dec(&dev->buf_alloc); 918 atomic_dec(&dev->buf_alloc);
924 return -ENOMEM; 919 return -ENOMEM;
925 } 920 }
926 memset(buf->dev_private, 0, buf->dev_priv_size);
927 921
928 DRM_DEBUG("buffer %d @ %p\n", 922 DRM_DEBUG("buffer %d @ %p\n",
929 entry->buf_count, buf->address); 923 entry->buf_count, buf->address);
@@ -1048,14 +1042,13 @@ static int drm_addbufs_sg(struct drm_device * dev, struct drm_buf_desc * request
1048 return -EINVAL; 1042 return -EINVAL;
1049 } 1043 }
1050 1044
1051 entry->buflist = kmalloc(count * sizeof(*entry->buflist), 1045 entry->buflist = kzalloc(count * sizeof(*entry->buflist),
1052 GFP_KERNEL); 1046 GFP_KERNEL);
1053 if (!entry->buflist) { 1047 if (!entry->buflist) {
1054 mutex_unlock(&dev->struct_mutex); 1048 mutex_unlock(&dev->struct_mutex);
1055 atomic_dec(&dev->buf_alloc); 1049 atomic_dec(&dev->buf_alloc);
1056 return -ENOMEM; 1050 return -ENOMEM;
1057 } 1051 }
1058 memset(entry->buflist, 0, count * sizeof(*entry->buflist));
1059 1052
1060 entry->buf_size = size; 1053 entry->buf_size = size;
1061 entry->page_order = page_order; 1054 entry->page_order = page_order;
@@ -1080,7 +1073,7 @@ static int drm_addbufs_sg(struct drm_device * dev, struct drm_buf_desc * request
1080 buf->file_priv = NULL; 1073 buf->file_priv = NULL;
1081 1074
1082 buf->dev_priv_size = dev->driver->dev_priv_size; 1075 buf->dev_priv_size = dev->driver->dev_priv_size;
1083 buf->dev_private = kmalloc(buf->dev_priv_size, GFP_KERNEL); 1076 buf->dev_private = kzalloc(buf->dev_priv_size, GFP_KERNEL);
1084 if (!buf->dev_private) { 1077 if (!buf->dev_private) {
1085 /* Set count correctly so we free the proper amount. */ 1078 /* Set count correctly so we free the proper amount. */
1086 entry->buf_count = count; 1079 entry->buf_count = count;
@@ -1090,8 +1083,6 @@ static int drm_addbufs_sg(struct drm_device * dev, struct drm_buf_desc * request
1090 return -ENOMEM; 1083 return -ENOMEM;
1091 } 1084 }
1092 1085
1093 memset(buf->dev_private, 0, buf->dev_priv_size);
1094
1095 DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address); 1086 DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address);
1096 1087
1097 offset += alignment; 1088 offset += alignment;
@@ -1209,14 +1200,13 @@ static int drm_addbufs_fb(struct drm_device * dev, struct drm_buf_desc * request
1209 return -EINVAL; 1200 return -EINVAL;
1210 } 1201 }
1211 1202
1212 entry->buflist = kmalloc(count * sizeof(*entry->buflist), 1203 entry->buflist = kzalloc(count * sizeof(*entry->buflist),
1213 GFP_KERNEL); 1204 GFP_KERNEL);
1214 if (!entry->buflist) { 1205 if (!entry->buflist) {
1215 mutex_unlock(&dev->struct_mutex); 1206 mutex_unlock(&dev->struct_mutex);
1216 atomic_dec(&dev->buf_alloc); 1207 atomic_dec(&dev->buf_alloc);
1217 return -ENOMEM; 1208 return -ENOMEM;
1218 } 1209 }
1219 memset(entry->buflist, 0, count * sizeof(*entry->buflist));
1220 1210
1221 entry->buf_size = size; 1211 entry->buf_size = size;
1222 entry->page_order = page_order; 1212 entry->page_order = page_order;
@@ -1240,7 +1230,7 @@ static int drm_addbufs_fb(struct drm_device * dev, struct drm_buf_desc * request
1240 buf->file_priv = NULL; 1230 buf->file_priv = NULL;
1241 1231
1242 buf->dev_priv_size = dev->driver->dev_priv_size; 1232 buf->dev_priv_size = dev->driver->dev_priv_size;
1243 buf->dev_private = kmalloc(buf->dev_priv_size, GFP_KERNEL); 1233 buf->dev_private = kzalloc(buf->dev_priv_size, GFP_KERNEL);
1244 if (!buf->dev_private) { 1234 if (!buf->dev_private) {
1245 /* Set count correctly so we free the proper amount. */ 1235 /* Set count correctly so we free the proper amount. */
1246 entry->buf_count = count; 1236 entry->buf_count = count;
@@ -1249,7 +1239,6 @@ static int drm_addbufs_fb(struct drm_device * dev, struct drm_buf_desc * request
1249 atomic_dec(&dev->buf_alloc); 1239 atomic_dec(&dev->buf_alloc);
1250 return -ENOMEM; 1240 return -ENOMEM;
1251 } 1241 }
1252 memset(buf->dev_private, 0, buf->dev_priv_size);
1253 1242
1254 DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address); 1243 DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address);
1255 1244
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 4c68f76993d8..37e0b4fa482a 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -1682,9 +1682,9 @@ int drm_mode_addfb(struct drm_device *dev,
1682 /* TODO setup destructor callback */ 1682 /* TODO setup destructor callback */
1683 1683
1684 fb = dev->mode_config.funcs->fb_create(dev, file_priv, r); 1684 fb = dev->mode_config.funcs->fb_create(dev, file_priv, r);
1685 if (!fb) { 1685 if (IS_ERR(fb)) {
1686 DRM_ERROR("could not create framebuffer\n"); 1686 DRM_ERROR("could not create framebuffer\n");
1687 ret = -EINVAL; 1687 ret = PTR_ERR(fb);
1688 goto out; 1688 goto out;
1689 } 1689 }
1690 1690
@@ -2541,7 +2541,7 @@ int drm_mode_gamma_set_ioctl(struct drm_device *dev,
2541 goto out; 2541 goto out;
2542 } 2542 }
2543 2543
2544 crtc->funcs->gamma_set(crtc, r_base, g_base, b_base, crtc->gamma_size); 2544 crtc->funcs->gamma_set(crtc, r_base, g_base, b_base, 0, crtc->gamma_size);
2545 2545
2546out: 2546out:
2547 mutex_unlock(&dev->mode_config.mutex); 2547 mutex_unlock(&dev->mode_config.mutex);
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index 11fe9c870d17..7b1eb2fcf616 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -817,12 +817,12 @@ int drm_helper_resume_force_mode(struct drm_device *dev)
817 if (encoder_funcs->dpms) 817 if (encoder_funcs->dpms)
818 (*encoder_funcs->dpms) (encoder, 818 (*encoder_funcs->dpms) (encoder,
819 drm_helper_choose_encoder_dpms(encoder)); 819 drm_helper_choose_encoder_dpms(encoder));
820
821 crtc_funcs = crtc->helper_private;
822 if (crtc_funcs->dpms)
823 (*crtc_funcs->dpms) (crtc,
824 drm_helper_choose_crtc_dpms(crtc));
825 } 820 }
821
822 crtc_funcs = crtc->helper_private;
823 if (crtc_funcs->dpms)
824 (*crtc_funcs->dpms) (crtc,
825 drm_helper_choose_crtc_dpms(crtc));
826 } 826 }
827 } 827 }
828 /* disable the unused connectors while restoring the modesetting */ 828 /* disable the unused connectors while restoring the modesetting */
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 90288ec7c284..84da748555bc 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -55,6 +55,9 @@
55static int drm_version(struct drm_device *dev, void *data, 55static int drm_version(struct drm_device *dev, void *data,
56 struct drm_file *file_priv); 56 struct drm_file *file_priv);
57 57
58#define DRM_IOCTL_DEF(ioctl, _func, _flags) \
59 [DRM_IOCTL_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, .cmd_drv = 0}
60
58/** Ioctl table */ 61/** Ioctl table */
59static struct drm_ioctl_desc drm_ioctls[] = { 62static struct drm_ioctl_desc drm_ioctls[] = {
60 DRM_IOCTL_DEF(DRM_IOCTL_VERSION, drm_version, 0), 63 DRM_IOCTL_DEF(DRM_IOCTL_VERSION, drm_version, 0),
@@ -421,6 +424,7 @@ long drm_ioctl(struct file *filp,
421 int retcode = -EINVAL; 424 int retcode = -EINVAL;
422 char stack_kdata[128]; 425 char stack_kdata[128];
423 char *kdata = NULL; 426 char *kdata = NULL;
427 unsigned int usize, asize;
424 428
425 dev = file_priv->minor->dev; 429 dev = file_priv->minor->dev;
426 atomic_inc(&dev->ioctl_count); 430 atomic_inc(&dev->ioctl_count);
@@ -436,11 +440,18 @@ long drm_ioctl(struct file *filp,
436 ((nr < DRM_COMMAND_BASE) || (nr >= DRM_COMMAND_END))) 440 ((nr < DRM_COMMAND_BASE) || (nr >= DRM_COMMAND_END)))
437 goto err_i1; 441 goto err_i1;
438 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) && 442 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) &&
439 (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) 443 (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
444 u32 drv_size;
440 ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE]; 445 ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE];
446 drv_size = _IOC_SIZE(ioctl->cmd_drv);
447 usize = asize = _IOC_SIZE(cmd);
448 if (drv_size > asize)
449 asize = drv_size;
450 }
441 else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) { 451 else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) {
442 ioctl = &drm_ioctls[nr]; 452 ioctl = &drm_ioctls[nr];
443 cmd = ioctl->cmd; 453 cmd = ioctl->cmd;
454 usize = asize = _IOC_SIZE(cmd);
444 } else 455 } else
445 goto err_i1; 456 goto err_i1;
446 457
@@ -460,10 +471,10 @@ long drm_ioctl(struct file *filp,
460 retcode = -EACCES; 471 retcode = -EACCES;
461 } else { 472 } else {
462 if (cmd & (IOC_IN | IOC_OUT)) { 473 if (cmd & (IOC_IN | IOC_OUT)) {
463 if (_IOC_SIZE(cmd) <= sizeof(stack_kdata)) { 474 if (asize <= sizeof(stack_kdata)) {
464 kdata = stack_kdata; 475 kdata = stack_kdata;
465 } else { 476 } else {
466 kdata = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL); 477 kdata = kmalloc(asize, GFP_KERNEL);
467 if (!kdata) { 478 if (!kdata) {
468 retcode = -ENOMEM; 479 retcode = -ENOMEM;
469 goto err_i1; 480 goto err_i1;
@@ -473,11 +484,13 @@ long drm_ioctl(struct file *filp,
473 484
474 if (cmd & IOC_IN) { 485 if (cmd & IOC_IN) {
475 if (copy_from_user(kdata, (void __user *)arg, 486 if (copy_from_user(kdata, (void __user *)arg,
476 _IOC_SIZE(cmd)) != 0) { 487 usize) != 0) {
477 retcode = -EFAULT; 488 retcode = -EFAULT;
478 goto err_i1; 489 goto err_i1;
479 } 490 }
480 } 491 } else
492 memset(kdata, 0, usize);
493
481 if (ioctl->flags & DRM_UNLOCKED) 494 if (ioctl->flags & DRM_UNLOCKED)
482 retcode = func(dev, kdata, file_priv); 495 retcode = func(dev, kdata, file_priv);
483 else { 496 else {
@@ -488,7 +501,7 @@ long drm_ioctl(struct file *filp,
488 501
489 if (cmd & IOC_OUT) { 502 if (cmd & IOC_OUT) {
490 if (copy_to_user((void __user *)arg, kdata, 503 if (copy_to_user((void __user *)arg, kdata,
491 _IOC_SIZE(cmd)) != 0) 504 usize) != 0)
492 retcode = -EFAULT; 505 retcode = -EFAULT;
493 } 506 }
494 } 507 }
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index ea1d57291b0e..6ac405534620 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -33,6 +33,11 @@
33#include <linux/i2c-algo-bit.h> 33#include <linux/i2c-algo-bit.h>
34#include "drmP.h" 34#include "drmP.h"
35#include "drm_edid.h" 35#include "drm_edid.h"
36#include "drm_edid_modes.h"
37
38#define version_greater(edid, maj, min) \
39 (((edid)->version > (maj)) || \
40 ((edid)->version == (maj) && (edid)->revision > (min)))
36 41
37#define EDID_EST_TIMINGS 16 42#define EDID_EST_TIMINGS 16
38#define EDID_STD_TIMINGS 8 43#define EDID_STD_TIMINGS 8
@@ -62,6 +67,13 @@
62/* use +hsync +vsync for detailed mode */ 67/* use +hsync +vsync for detailed mode */
63#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 68#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
64 69
70struct detailed_mode_closure {
71 struct drm_connector *connector;
72 struct edid *edid;
73 bool preferred;
74 u32 quirks;
75 int modes;
76};
65 77
66#define LEVEL_DMT 0 78#define LEVEL_DMT 0
67#define LEVEL_GTF 1 79#define LEVEL_GTF 1
@@ -375,7 +387,6 @@ static u32 edid_get_quirks(struct edid *edid)
375#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 387#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
376#define MODE_REFRESH_DIFF(m,r) (abs((m)->vrefresh - target_refresh)) 388#define MODE_REFRESH_DIFF(m,r) (abs((m)->vrefresh - target_refresh))
377 389
378
379/** 390/**
380 * edid_fixup_preferred - set preferred modes based on quirk list 391 * edid_fixup_preferred - set preferred modes based on quirk list
381 * @connector: has mode list to fix up 392 * @connector: has mode list to fix up
@@ -422,245 +433,6 @@ static void edid_fixup_preferred(struct drm_connector *connector,
422 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 433 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
423} 434}
424 435
425/*
426 * Add the Autogenerated from the DMT spec.
427 * This table is copied from xfree86/modes/xf86EdidModes.c.
428 * But the mode with Reduced blank feature is deleted.
429 */
430static struct drm_display_mode drm_dmt_modes[] = {
431 /* 640x350@85Hz */
432 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
433 736, 832, 0, 350, 382, 385, 445, 0,
434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
435 /* 640x400@85Hz */
436 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
437 736, 832, 0, 400, 401, 404, 445, 0,
438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
439 /* 720x400@85Hz */
440 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
441 828, 936, 0, 400, 401, 404, 446, 0,
442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
443 /* 640x480@60Hz */
444 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
445 752, 800, 0, 480, 489, 492, 525, 0,
446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
447 /* 640x480@72Hz */
448 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
449 704, 832, 0, 480, 489, 492, 520, 0,
450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
451 /* 640x480@75Hz */
452 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
453 720, 840, 0, 480, 481, 484, 500, 0,
454 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
455 /* 640x480@85Hz */
456 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
457 752, 832, 0, 480, 481, 484, 509, 0,
458 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
459 /* 800x600@56Hz */
460 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
461 896, 1024, 0, 600, 601, 603, 625, 0,
462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
463 /* 800x600@60Hz */
464 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
465 968, 1056, 0, 600, 601, 605, 628, 0,
466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
467 /* 800x600@72Hz */
468 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
469 976, 1040, 0, 600, 637, 643, 666, 0,
470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
471 /* 800x600@75Hz */
472 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
473 896, 1056, 0, 600, 601, 604, 625, 0,
474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
475 /* 800x600@85Hz */
476 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
477 896, 1048, 0, 600, 601, 604, 631, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
479 /* 848x480@60Hz */
480 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
481 976, 1088, 0, 480, 486, 494, 517, 0,
482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
483 /* 1024x768@43Hz, interlace */
484 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
485 1208, 1264, 0, 768, 768, 772, 817, 0,
486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
487 DRM_MODE_FLAG_INTERLACE) },
488 /* 1024x768@60Hz */
489 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
490 1184, 1344, 0, 768, 771, 777, 806, 0,
491 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
492 /* 1024x768@70Hz */
493 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
494 1184, 1328, 0, 768, 771, 777, 806, 0,
495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
496 /* 1024x768@75Hz */
497 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
498 1136, 1312, 0, 768, 769, 772, 800, 0,
499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
500 /* 1024x768@85Hz */
501 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
502 1168, 1376, 0, 768, 769, 772, 808, 0,
503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
504 /* 1152x864@75Hz */
505 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
506 1344, 1600, 0, 864, 865, 868, 900, 0,
507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
508 /* 1280x768@60Hz */
509 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
510 1472, 1664, 0, 768, 771, 778, 798, 0,
511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
512 /* 1280x768@75Hz */
513 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
514 1488, 1696, 0, 768, 771, 778, 805, 0,
515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
516 /* 1280x768@85Hz */
517 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
518 1496, 1712, 0, 768, 771, 778, 809, 0,
519 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
520 /* 1280x800@60Hz */
521 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
522 1480, 1680, 0, 800, 803, 809, 831, 0,
523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
524 /* 1280x800@75Hz */
525 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
526 1488, 1696, 0, 800, 803, 809, 838, 0,
527 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
528 /* 1280x800@85Hz */
529 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
530 1496, 1712, 0, 800, 803, 809, 843, 0,
531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
532 /* 1280x960@60Hz */
533 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
534 1488, 1800, 0, 960, 961, 964, 1000, 0,
535 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
536 /* 1280x960@85Hz */
537 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
538 1504, 1728, 0, 960, 961, 964, 1011, 0,
539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
540 /* 1280x1024@60Hz */
541 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
542 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
543 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
544 /* 1280x1024@75Hz */
545 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
546 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
548 /* 1280x1024@85Hz */
549 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
550 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
552 /* 1360x768@60Hz */
553 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
554 1536, 1792, 0, 768, 771, 777, 795, 0,
555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
556 /* 1440x1050@60Hz */
557 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
558 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
559 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
560 /* 1440x1050@75Hz */
561 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
562 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
564 /* 1440x1050@85Hz */
565 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
566 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
567 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
568 /* 1440x900@60Hz */
569 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
570 1672, 1904, 0, 900, 903, 909, 934, 0,
571 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
572 /* 1440x900@75Hz */
573 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
574 1688, 1936, 0, 900, 903, 909, 942, 0,
575 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
576 /* 1440x900@85Hz */
577 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
578 1696, 1952, 0, 900, 903, 909, 948, 0,
579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
580 /* 1600x1200@60Hz */
581 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
582 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
584 /* 1600x1200@65Hz */
585 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
586 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
588 /* 1600x1200@70Hz */
589 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
590 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
592 /* 1600x1200@75Hz */
593 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
594 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
596 /* 1600x1200@85Hz */
597 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
598 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
600 /* 1680x1050@60Hz */
601 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
602 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
604 /* 1680x1050@75Hz */
605 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
606 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
608 /* 1680x1050@85Hz */
609 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
610 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
611 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
612 /* 1792x1344@60Hz */
613 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
614 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
616 /* 1729x1344@75Hz */
617 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
618 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
619 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
620 /* 1853x1392@60Hz */
621 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
622 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
624 /* 1856x1392@75Hz */
625 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
626 2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
627 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
628 /* 1920x1200@60Hz */
629 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
630 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
632 /* 1920x1200@75Hz */
633 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
634 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
636 /* 1920x1200@85Hz */
637 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
638 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
640 /* 1920x1440@60Hz */
641 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
642 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
643 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
644 /* 1920x1440@75Hz */
645 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
646 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
647 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
648 /* 2560x1600@60Hz */
649 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
650 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
651 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
652 /* 2560x1600@75HZ */
653 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
654 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
655 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
656 /* 2560x1600@85HZ */
657 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
658 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
659 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
660};
661static const int drm_num_dmt_modes =
662 sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
663
664struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 436struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
665 int hsize, int vsize, int fresh) 437 int hsize, int vsize, int fresh)
666{ 438{
@@ -685,6 +457,46 @@ EXPORT_SYMBOL(drm_mode_find_dmt);
685typedef void detailed_cb(struct detailed_timing *timing, void *closure); 457typedef void detailed_cb(struct detailed_timing *timing, void *closure);
686 458
687static void 459static void
460cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
461{
462 int i, n = 0;
463 u8 rev = ext[0x01], d = ext[0x02];
464 u8 *det_base = ext + d;
465
466 switch (rev) {
467 case 0:
468 /* can't happen */
469 return;
470 case 1:
471 /* have to infer how many blocks we have, check pixel clock */
472 for (i = 0; i < 6; i++)
473 if (det_base[18*i] || det_base[18*i+1])
474 n++;
475 break;
476 default:
477 /* explicit count */
478 n = min(ext[0x03] & 0x0f, 6);
479 break;
480 }
481
482 for (i = 0; i < n; i++)
483 cb((struct detailed_timing *)(det_base + 18 * i), closure);
484}
485
486static void
487vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
488{
489 unsigned int i, n = min((int)ext[0x02], 6);
490 u8 *det_base = ext + 5;
491
492 if (ext[0x01] != 1)
493 return; /* unknown version */
494
495 for (i = 0; i < n; i++)
496 cb((struct detailed_timing *)(det_base + 18 * i), closure);
497}
498
499static void
688drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 500drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
689{ 501{
690 int i; 502 int i;
@@ -696,7 +508,19 @@ drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
696 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 508 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
697 cb(&(edid->detailed_timings[i]), closure); 509 cb(&(edid->detailed_timings[i]), closure);
698 510
699 /* XXX extension block walk */ 511 for (i = 1; i <= raw_edid[0x7e]; i++) {
512 u8 *ext = raw_edid + (i * EDID_LENGTH);
513 switch (*ext) {
514 case CEA_EXT:
515 cea_for_each_detailed_block(ext, cb, closure);
516 break;
517 case VTB_EXT:
518 vtb_for_each_detailed_block(ext, cb, closure);
519 break;
520 default:
521 break;
522 }
523 }
700} 524}
701 525
702static void 526static void
@@ -1049,117 +873,6 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1049 return mode; 873 return mode;
1050} 874}
1051 875
1052/*
1053 * Detailed mode info for the EDID "established modes" data to use.
1054 */
1055static struct drm_display_mode edid_est_modes[] = {
1056 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
1057 968, 1056, 0, 600, 601, 605, 628, 0,
1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
1059 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
1060 896, 1024, 0, 600, 601, 603, 625, 0,
1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
1062 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
1063 720, 840, 0, 480, 481, 484, 500, 0,
1064 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
1065 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
1066 704, 832, 0, 480, 489, 491, 520, 0,
1067 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
1068 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
1069 768, 864, 0, 480, 483, 486, 525, 0,
1070 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
1071 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
1072 752, 800, 0, 480, 490, 492, 525, 0,
1073 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
1074 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
1075 846, 900, 0, 400, 421, 423, 449, 0,
1076 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
1077 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
1078 846, 900, 0, 400, 412, 414, 449, 0,
1079 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
1080 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
1081 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
1083 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
1084 1136, 1312, 0, 768, 769, 772, 800, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
1086 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
1087 1184, 1328, 0, 768, 771, 777, 806, 0,
1088 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
1089 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
1090 1184, 1344, 0, 768, 771, 777, 806, 0,
1091 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
1092 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
1093 1208, 1264, 0, 768, 768, 776, 817, 0,
1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
1095 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
1096 928, 1152, 0, 624, 625, 628, 667, 0,
1097 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
1098 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
1099 896, 1056, 0, 600, 601, 604, 625, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
1101 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
1102 976, 1040, 0, 600, 637, 643, 666, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
1104 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
1105 1344, 1600, 0, 864, 865, 868, 900, 0,
1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
1107};
1108
1109/**
1110 * add_established_modes - get est. modes from EDID and add them
1111 * @edid: EDID block to scan
1112 *
1113 * Each EDID block contains a bitmap of the supported "established modes" list
1114 * (defined above). Tease them out and add them to the global modes list.
1115 */
1116static int add_established_modes(struct drm_connector *connector, struct edid *edid)
1117{
1118 struct drm_device *dev = connector->dev;
1119 unsigned long est_bits = edid->established_timings.t1 |
1120 (edid->established_timings.t2 << 8) |
1121 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
1122 int i, modes = 0;
1123
1124 for (i = 0; i <= EDID_EST_TIMINGS; i++)
1125 if (est_bits & (1<<i)) {
1126 struct drm_display_mode *newmode;
1127 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
1128 if (newmode) {
1129 drm_mode_probed_add(connector, newmode);
1130 modes++;
1131 }
1132 }
1133
1134 return modes;
1135}
1136
1137/**
1138 * add_standard_modes - get std. modes from EDID and add them
1139 * @edid: EDID block to scan
1140 *
1141 * Standard modes can be calculated using the CVT standard. Grab them from
1142 * @edid, calculate them, and add them to the list.
1143 */
1144static int add_standard_modes(struct drm_connector *connector, struct edid *edid)
1145{
1146 int i, modes = 0;
1147
1148 for (i = 0; i < EDID_STD_TIMINGS; i++) {
1149 struct drm_display_mode *newmode;
1150
1151 newmode = drm_mode_std(connector, edid,
1152 &edid->standard_timings[i],
1153 edid->revision);
1154 if (newmode) {
1155 drm_mode_probed_add(connector, newmode);
1156 modes++;
1157 }
1158 }
1159
1160 return modes;
1161}
1162
1163static bool 876static bool
1164mode_is_rb(struct drm_display_mode *mode) 877mode_is_rb(struct drm_display_mode *mode)
1165{ 878{
@@ -1269,114 +982,33 @@ drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
1269 return modes; 982 return modes;
1270} 983}
1271 984
1272static int drm_cvt_modes(struct drm_connector *connector, 985static void
1273 struct detailed_timing *timing) 986do_inferred_modes(struct detailed_timing *timing, void *c)
1274{ 987{
1275 int i, j, modes = 0; 988 struct detailed_mode_closure *closure = c;
1276 struct drm_display_mode *newmode; 989 struct detailed_non_pixel *data = &timing->data.other_data;
1277 struct drm_device *dev = connector->dev; 990 int gtf = (closure->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF);
1278 struct cvt_timing *cvt;
1279 const int rates[] = { 60, 85, 75, 60, 50 };
1280 const u8 empty[3] = { 0, 0, 0 };
1281
1282 for (i = 0; i < 4; i++) {
1283 int uninitialized_var(width), height;
1284 cvt = &(timing->data.other_data.data.cvt[i]);
1285 991
1286 if (!memcmp(cvt->code, empty, 3)) 992 if (gtf && data->type == EDID_DETAIL_MONITOR_RANGE)
1287 continue; 993 closure->modes += drm_gtf_modes_for_range(closure->connector,
994 closure->edid,
995 timing);
996}
1288 997
1289 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 998static int
1290 switch (cvt->code[1] & 0x0c) { 999add_inferred_modes(struct drm_connector *connector, struct edid *edid)
1291 case 0x00: 1000{
1292 width = height * 4 / 3; 1001 struct detailed_mode_closure closure = {
1293 break; 1002 connector, edid, 0, 0, 0
1294 case 0x04: 1003 };
1295 width = height * 16 / 9;
1296 break;
1297 case 0x08:
1298 width = height * 16 / 10;
1299 break;
1300 case 0x0c:
1301 width = height * 15 / 9;
1302 break;
1303 }
1304 1004
1305 for (j = 1; j < 5; j++) { 1005 if (version_greater(edid, 1, 0))
1306 if (cvt->code[2] & (1 << j)) { 1006 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
1307 newmode = drm_cvt_mode(dev, width, height, 1007 &closure);
1308 rates[j], j == 0,
1309 false, false);
1310 if (newmode) {
1311 drm_mode_probed_add(connector, newmode);
1312 modes++;
1313 }
1314 }
1315 }
1316 }
1317 1008
1318 return modes; 1009 return closure.modes;
1319} 1010}
1320 1011
1321static const struct {
1322 short w;
1323 short h;
1324 short r;
1325 short rb;
1326} est3_modes[] = {
1327 /* byte 6 */
1328 { 640, 350, 85, 0 },
1329 { 640, 400, 85, 0 },
1330 { 720, 400, 85, 0 },
1331 { 640, 480, 85, 0 },
1332 { 848, 480, 60, 0 },
1333 { 800, 600, 85, 0 },
1334 { 1024, 768, 85, 0 },
1335 { 1152, 864, 75, 0 },
1336 /* byte 7 */
1337 { 1280, 768, 60, 1 },
1338 { 1280, 768, 60, 0 },
1339 { 1280, 768, 75, 0 },
1340 { 1280, 768, 85, 0 },
1341 { 1280, 960, 60, 0 },
1342 { 1280, 960, 85, 0 },
1343 { 1280, 1024, 60, 0 },
1344 { 1280, 1024, 85, 0 },
1345 /* byte 8 */
1346 { 1360, 768, 60, 0 },
1347 { 1440, 900, 60, 1 },
1348 { 1440, 900, 60, 0 },
1349 { 1440, 900, 75, 0 },
1350 { 1440, 900, 85, 0 },
1351 { 1400, 1050, 60, 1 },
1352 { 1400, 1050, 60, 0 },
1353 { 1400, 1050, 75, 0 },
1354 /* byte 9 */
1355 { 1400, 1050, 85, 0 },
1356 { 1680, 1050, 60, 1 },
1357 { 1680, 1050, 60, 0 },
1358 { 1680, 1050, 75, 0 },
1359 { 1680, 1050, 85, 0 },
1360 { 1600, 1200, 60, 0 },
1361 { 1600, 1200, 65, 0 },
1362 { 1600, 1200, 70, 0 },
1363 /* byte 10 */
1364 { 1600, 1200, 75, 0 },
1365 { 1600, 1200, 85, 0 },
1366 { 1792, 1344, 60, 0 },
1367 { 1792, 1344, 85, 0 },
1368 { 1856, 1392, 60, 0 },
1369 { 1856, 1392, 75, 0 },
1370 { 1920, 1200, 60, 1 },
1371 { 1920, 1200, 60, 0 },
1372 /* byte 11 */
1373 { 1920, 1200, 75, 0 },
1374 { 1920, 1200, 85, 0 },
1375 { 1920, 1440, 60, 0 },
1376 { 1920, 1440, 75, 0 },
1377};
1378static const int num_est3_modes = sizeof(est3_modes) / sizeof(est3_modes[0]);
1379
1380static int 1012static int
1381drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 1013drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
1382{ 1014{
@@ -1406,37 +1038,63 @@ drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
1406 return modes; 1038 return modes;
1407} 1039}
1408 1040
1409static int add_detailed_modes(struct drm_connector *connector, 1041static void
1410 struct detailed_timing *timing, 1042do_established_modes(struct detailed_timing *timing, void *c)
1411 struct edid *edid, u32 quirks, int preferred)
1412{ 1043{
1413 int i, modes = 0; 1044 struct detailed_mode_closure *closure = c;
1414 struct detailed_non_pixel *data = &timing->data.other_data; 1045 struct detailed_non_pixel *data = &timing->data.other_data;
1415 int gtf = (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF);
1416 struct drm_display_mode *newmode;
1417 struct drm_device *dev = connector->dev;
1418 1046
1419 if (timing->pixel_clock) { 1047 if (data->type == EDID_DETAIL_EST_TIMINGS)
1420 newmode = drm_mode_detailed(dev, edid, timing, quirks); 1048 closure->modes += drm_est3_modes(closure->connector, timing);
1421 if (!newmode) 1049}
1422 return 0;
1423 1050
1424 if (preferred) 1051/**
1425 newmode->type |= DRM_MODE_TYPE_PREFERRED; 1052 * add_established_modes - get est. modes from EDID and add them
1053 * @edid: EDID block to scan
1054 *
1055 * Each EDID block contains a bitmap of the supported "established modes" list
1056 * (defined above). Tease them out and add them to the global modes list.
1057 */
1058static int
1059add_established_modes(struct drm_connector *connector, struct edid *edid)
1060{
1061 struct drm_device *dev = connector->dev;
1062 unsigned long est_bits = edid->established_timings.t1 |
1063 (edid->established_timings.t2 << 8) |
1064 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
1065 int i, modes = 0;
1066 struct detailed_mode_closure closure = {
1067 connector, edid, 0, 0, 0
1068 };
1426 1069
1427 drm_mode_probed_add(connector, newmode); 1070 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
1428 return 1; 1071 if (est_bits & (1<<i)) {
1072 struct drm_display_mode *newmode;
1073 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
1074 if (newmode) {
1075 drm_mode_probed_add(connector, newmode);
1076 modes++;
1077 }
1078 }
1429 } 1079 }
1430 1080
1431 /* other timing types */ 1081 if (version_greater(edid, 1, 0))
1432 switch (data->type) { 1082 drm_for_each_detailed_block((u8 *)edid,
1433 case EDID_DETAIL_MONITOR_RANGE: 1083 do_established_modes, &closure);
1434 if (gtf) 1084
1435 modes += drm_gtf_modes_for_range(connector, edid, 1085 return modes + closure.modes;
1436 timing); 1086}
1437 break; 1087
1438 case EDID_DETAIL_STD_MODES: 1088static void
1439 /* Six modes per detailed section */ 1089do_standard_modes(struct detailed_timing *timing, void *c)
1090{
1091 struct detailed_mode_closure *closure = c;
1092 struct detailed_non_pixel *data = &timing->data.other_data;
1093 struct drm_connector *connector = closure->connector;
1094 struct edid *edid = closure->edid;
1095
1096 if (data->type == EDID_DETAIL_STD_MODES) {
1097 int i;
1440 for (i = 0; i < 6; i++) { 1098 for (i = 0; i < 6; i++) {
1441 struct std_timing *std; 1099 struct std_timing *std;
1442 struct drm_display_mode *newmode; 1100 struct drm_display_mode *newmode;
@@ -1446,108 +1104,169 @@ static int add_detailed_modes(struct drm_connector *connector,
1446 edid->revision); 1104 edid->revision);
1447 if (newmode) { 1105 if (newmode) {
1448 drm_mode_probed_add(connector, newmode); 1106 drm_mode_probed_add(connector, newmode);
1449 modes++; 1107 closure->modes++;
1450 } 1108 }
1451 } 1109 }
1452 break;
1453 case EDID_DETAIL_CVT_3BYTE:
1454 modes += drm_cvt_modes(connector, timing);
1455 break;
1456 case EDID_DETAIL_EST_TIMINGS:
1457 modes += drm_est3_modes(connector, timing);
1458 break;
1459 default:
1460 break;
1461 } 1110 }
1462
1463 return modes;
1464} 1111}
1465 1112
1466/** 1113/**
1467 * add_detailed_info - get detailed mode info from EDID data 1114 * add_standard_modes - get std. modes from EDID and add them
1468 * @connector: attached connector
1469 * @edid: EDID block to scan 1115 * @edid: EDID block to scan
1470 * @quirks: quirks to apply
1471 * 1116 *
1472 * Some of the detailed timing sections may contain mode information. Grab 1117 * Standard modes can be calculated using the appropriate standard (DMT,
1473 * it and add it to the list. 1118 * GTF or CVT. Grab them from @edid and add them to the list.
1474 */ 1119 */
1475static int add_detailed_info(struct drm_connector *connector, 1120static int
1476 struct edid *edid, u32 quirks) 1121add_standard_modes(struct drm_connector *connector, struct edid *edid)
1477{ 1122{
1478 int i, modes = 0; 1123 int i, modes = 0;
1124 struct detailed_mode_closure closure = {
1125 connector, edid, 0, 0, 0
1126 };
1127
1128 for (i = 0; i < EDID_STD_TIMINGS; i++) {
1129 struct drm_display_mode *newmode;
1130
1131 newmode = drm_mode_std(connector, edid,
1132 &edid->standard_timings[i],
1133 edid->revision);
1134 if (newmode) {
1135 drm_mode_probed_add(connector, newmode);
1136 modes++;
1137 }
1138 }
1139
1140 if (version_greater(edid, 1, 0))
1141 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
1142 &closure);
1143
1144 /* XXX should also look for standard codes in VTB blocks */
1145
1146 return modes + closure.modes;
1147}
1479 1148
1480 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) { 1149static int drm_cvt_modes(struct drm_connector *connector,
1481 struct detailed_timing *timing = &edid->detailed_timings[i]; 1150 struct detailed_timing *timing)
1482 int preferred = (i == 0); 1151{
1152 int i, j, modes = 0;
1153 struct drm_display_mode *newmode;
1154 struct drm_device *dev = connector->dev;
1155 struct cvt_timing *cvt;
1156 const int rates[] = { 60, 85, 75, 60, 50 };
1157 const u8 empty[3] = { 0, 0, 0 };
1483 1158
1484 if (preferred && edid->version == 1 && edid->revision < 4) 1159 for (i = 0; i < 4; i++) {
1485 preferred = (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 1160 int uninitialized_var(width), height;
1161 cvt = &(timing->data.other_data.data.cvt[i]);
1486 1162
1487 /* In 1.0, only timings are allowed */ 1163 if (!memcmp(cvt->code, empty, 3))
1488 if (!timing->pixel_clock && edid->version == 1 &&
1489 edid->revision == 0)
1490 continue; 1164 continue;
1491 1165
1492 modes += add_detailed_modes(connector, timing, edid, quirks, 1166 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
1493 preferred); 1167 switch (cvt->code[1] & 0x0c) {
1168 case 0x00:
1169 width = height * 4 / 3;
1170 break;
1171 case 0x04:
1172 width = height * 16 / 9;
1173 break;
1174 case 0x08:
1175 width = height * 16 / 10;
1176 break;
1177 case 0x0c:
1178 width = height * 15 / 9;
1179 break;
1180 }
1181
1182 for (j = 1; j < 5; j++) {
1183 if (cvt->code[2] & (1 << j)) {
1184 newmode = drm_cvt_mode(dev, width, height,
1185 rates[j], j == 0,
1186 false, false);
1187 if (newmode) {
1188 drm_mode_probed_add(connector, newmode);
1189 modes++;
1190 }
1191 }
1192 }
1494 } 1193 }
1495 1194
1496 return modes; 1195 return modes;
1497} 1196}
1498 1197
1499/** 1198static void
1500 * add_detailed_mode_eedid - get detailed mode info from addtional timing 1199do_cvt_mode(struct detailed_timing *timing, void *c)
1501 * EDID block
1502 * @connector: attached connector
1503 * @edid: EDID block to scan(It is only to get addtional timing EDID block)
1504 * @quirks: quirks to apply
1505 *
1506 * Some of the detailed timing sections may contain mode information. Grab
1507 * it and add it to the list.
1508 */
1509static int add_detailed_info_eedid(struct drm_connector *connector,
1510 struct edid *edid, u32 quirks)
1511{ 1200{
1512 int i, modes = 0; 1201 struct detailed_mode_closure *closure = c;
1513 char *edid_ext = NULL; 1202 struct detailed_non_pixel *data = &timing->data.other_data;
1514 struct detailed_timing *timing;
1515 int start_offset, end_offset;
1516 1203
1517 if (edid->version == 1 && edid->revision < 3) 1204 if (data->type == EDID_DETAIL_CVT_3BYTE)
1518 return 0; 1205 closure->modes += drm_cvt_modes(closure->connector, timing);
1519 if (!edid->extensions) 1206}
1520 return 0;
1521 1207
1522 /* Find CEA extension */ 1208static int
1523 for (i = 0; i < edid->extensions; i++) { 1209add_cvt_modes(struct drm_connector *connector, struct edid *edid)
1524 edid_ext = (char *)edid + EDID_LENGTH * (i + 1); 1210{
1525 if (edid_ext[0] == 0x02) 1211 struct detailed_mode_closure closure = {
1526 break; 1212 connector, edid, 0, 0, 0
1527 } 1213 };
1528 1214
1529 if (i == edid->extensions) 1215 if (version_greater(edid, 1, 2))
1530 return 0; 1216 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
1531 1217
1532 /* Get the start offset of detailed timing block */ 1218 /* XXX should also look for CVT codes in VTB blocks */
1533 start_offset = edid_ext[2];
1534 if (start_offset == 0) {
1535 /* If the start_offset is zero, it means that neither detailed
1536 * info nor data block exist. In such case it is also
1537 * unnecessary to parse the detailed timing info.
1538 */
1539 return 0;
1540 }
1541 1219
1542 end_offset = EDID_LENGTH; 1220 return closure.modes;
1543 end_offset -= sizeof(struct detailed_timing); 1221}
1544 for (i = start_offset; i < end_offset; 1222
1545 i += sizeof(struct detailed_timing)) { 1223static void
1546 timing = (struct detailed_timing *)(edid_ext + i); 1224do_detailed_mode(struct detailed_timing *timing, void *c)
1547 modes += add_detailed_modes(connector, timing, edid, quirks, 0); 1225{
1226 struct detailed_mode_closure *closure = c;
1227 struct drm_display_mode *newmode;
1228
1229 if (timing->pixel_clock) {
1230 newmode = drm_mode_detailed(closure->connector->dev,
1231 closure->edid, timing,
1232 closure->quirks);
1233 if (!newmode)
1234 return;
1235
1236 if (closure->preferred)
1237 newmode->type |= DRM_MODE_TYPE_PREFERRED;
1238
1239 drm_mode_probed_add(closure->connector, newmode);
1240 closure->modes++;
1241 closure->preferred = 0;
1548 } 1242 }
1243}
1549 1244
1550 return modes; 1245/*
1246 * add_detailed_modes - Add modes from detailed timings
1247 * @connector: attached connector
1248 * @edid: EDID block to scan
1249 * @quirks: quirks to apply
1250 */
1251static int
1252add_detailed_modes(struct drm_connector *connector, struct edid *edid,
1253 u32 quirks)
1254{
1255 struct detailed_mode_closure closure = {
1256 connector,
1257 edid,
1258 1,
1259 quirks,
1260 0
1261 };
1262
1263 if (closure.preferred && !version_greater(edid, 1, 3))
1264 closure.preferred =
1265 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
1266
1267 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
1268
1269 return closure.modes;
1551} 1270}
1552 1271
1553#define HDMI_IDENTIFIER 0x000C03 1272#define HDMI_IDENTIFIER 0x000C03
@@ -1643,35 +1362,21 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
1643 * - established timing codes 1362 * - established timing codes
1644 * - modes inferred from GTF or CVT range information 1363 * - modes inferred from GTF or CVT range information
1645 * 1364 *
1646 * We don't quite implement this yet, but we're close. 1365 * We get this pretty much right.
1647 * 1366 *
1648 * XXX order for additional mode types in extension blocks? 1367 * XXX order for additional mode types in extension blocks?
1649 */ 1368 */
1650 num_modes += add_detailed_info(connector, edid, quirks); 1369 num_modes += add_detailed_modes(connector, edid, quirks);
1651 num_modes += add_detailed_info_eedid(connector, edid, quirks); 1370 num_modes += add_cvt_modes(connector, edid);
1652 num_modes += add_standard_modes(connector, edid); 1371 num_modes += add_standard_modes(connector, edid);
1653 num_modes += add_established_modes(connector, edid); 1372 num_modes += add_established_modes(connector, edid);
1373 num_modes += add_inferred_modes(connector, edid);
1654 1374
1655 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 1375 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
1656 edid_fixup_preferred(connector, quirks); 1376 edid_fixup_preferred(connector, quirks);
1657 1377
1658 connector->display_info.serration_vsync = (edid->input & DRM_EDID_INPUT_SERRATION_VSYNC) ? 1 : 0;
1659 connector->display_info.sync_on_green = (edid->input & DRM_EDID_INPUT_SYNC_ON_GREEN) ? 1 : 0;
1660 connector->display_info.composite_sync = (edid->input & DRM_EDID_INPUT_COMPOSITE_SYNC) ? 1 : 0;
1661 connector->display_info.separate_syncs = (edid->input & DRM_EDID_INPUT_SEPARATE_SYNCS) ? 1 : 0;
1662 connector->display_info.blank_to_black = (edid->input & DRM_EDID_INPUT_BLANK_TO_BLACK) ? 1 : 0;
1663 connector->display_info.video_level = (edid->input & DRM_EDID_INPUT_VIDEO_LEVEL) >> 5;
1664 connector->display_info.digital = (edid->input & DRM_EDID_INPUT_DIGITAL) ? 1 : 0;
1665 connector->display_info.width_mm = edid->width_cm * 10; 1378 connector->display_info.width_mm = edid->width_cm * 10;
1666 connector->display_info.height_mm = edid->height_cm * 10; 1379 connector->display_info.height_mm = edid->height_cm * 10;
1667 connector->display_info.gamma = edid->gamma;
1668 connector->display_info.gtf_supported = (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) ? 1 : 0;
1669 connector->display_info.standard_color = (edid->features & DRM_EDID_FEATURE_STANDARD_COLOR) ? 1 : 0;
1670 connector->display_info.display_type = (edid->features & DRM_EDID_FEATURE_DISPLAY_TYPE) >> 3;
1671 connector->display_info.active_off_supported = (edid->features & DRM_EDID_FEATURE_PM_ACTIVE_OFF) ? 1 : 0;
1672 connector->display_info.suspend_supported = (edid->features & DRM_EDID_FEATURE_PM_SUSPEND) ? 1 : 0;
1673 connector->display_info.standby_supported = (edid->features & DRM_EDID_FEATURE_PM_STANDBY) ? 1 : 0;
1674 connector->display_info.gamma = edid->gamma;
1675 1380
1676 return num_modes; 1381 return num_modes;
1677} 1382}
diff --git a/drivers/gpu/drm/drm_edid_modes.h b/drivers/gpu/drm/drm_edid_modes.h
new file mode 100644
index 000000000000..6eb7592e152f
--- /dev/null
+++ b/drivers/gpu/drm/drm_edid_modes.h
@@ -0,0 +1,380 @@
1/*
2 * Copyright (c) 2007-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
4 * Copyright 2010 Red Hat, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sub license,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26#include <linux/kernel.h>
27#include "drmP.h"
28#include "drm_edid.h"
29
30/*
31 * Autogenerated from the DMT spec.
32 * This table is copied from xfree86/modes/xf86EdidModes.c.
33 * But the mode with Reduced blank feature is deleted.
34 */
35static struct drm_display_mode drm_dmt_modes[] = {
36 /* 640x350@85Hz */
37 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
38 736, 832, 0, 350, 382, 385, 445, 0,
39 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
40 /* 640x400@85Hz */
41 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
42 736, 832, 0, 400, 401, 404, 445, 0,
43 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
44 /* 720x400@85Hz */
45 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
46 828, 936, 0, 400, 401, 404, 446, 0,
47 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
48 /* 640x480@60Hz */
49 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
50 752, 800, 0, 480, 489, 492, 525, 0,
51 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
52 /* 640x480@72Hz */
53 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
54 704, 832, 0, 480, 489, 492, 520, 0,
55 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
56 /* 640x480@75Hz */
57 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
58 720, 840, 0, 480, 481, 484, 500, 0,
59 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
60 /* 640x480@85Hz */
61 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
62 752, 832, 0, 480, 481, 484, 509, 0,
63 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
64 /* 800x600@56Hz */
65 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
66 896, 1024, 0, 600, 601, 603, 625, 0,
67 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
68 /* 800x600@60Hz */
69 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
70 968, 1056, 0, 600, 601, 605, 628, 0,
71 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
72 /* 800x600@72Hz */
73 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
74 976, 1040, 0, 600, 637, 643, 666, 0,
75 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
76 /* 800x600@75Hz */
77 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
78 896, 1056, 0, 600, 601, 604, 625, 0,
79 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
80 /* 800x600@85Hz */
81 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
82 896, 1048, 0, 600, 601, 604, 631, 0,
83 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
84 /* 848x480@60Hz */
85 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
86 976, 1088, 0, 480, 486, 494, 517, 0,
87 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
88 /* 1024x768@43Hz, interlace */
89 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
90 1208, 1264, 0, 768, 768, 772, 817, 0,
91 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
92 DRM_MODE_FLAG_INTERLACE) },
93 /* 1024x768@60Hz */
94 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
95 1184, 1344, 0, 768, 771, 777, 806, 0,
96 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
97 /* 1024x768@70Hz */
98 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
99 1184, 1328, 0, 768, 771, 777, 806, 0,
100 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
101 /* 1024x768@75Hz */
102 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
103 1136, 1312, 0, 768, 769, 772, 800, 0,
104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
105 /* 1024x768@85Hz */
106 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
107 1168, 1376, 0, 768, 769, 772, 808, 0,
108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
109 /* 1152x864@75Hz */
110 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
111 1344, 1600, 0, 864, 865, 868, 900, 0,
112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
113 /* 1280x768@60Hz */
114 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
115 1472, 1664, 0, 768, 771, 778, 798, 0,
116 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
117 /* 1280x768@75Hz */
118 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
119 1488, 1696, 0, 768, 771, 778, 805, 0,
120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
121 /* 1280x768@85Hz */
122 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
123 1496, 1712, 0, 768, 771, 778, 809, 0,
124 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
125 /* 1280x800@60Hz */
126 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
127 1480, 1680, 0, 800, 803, 809, 831, 0,
128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
129 /* 1280x800@75Hz */
130 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
131 1488, 1696, 0, 800, 803, 809, 838, 0,
132 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
133 /* 1280x800@85Hz */
134 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
135 1496, 1712, 0, 800, 803, 809, 843, 0,
136 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
137 /* 1280x960@60Hz */
138 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
139 1488, 1800, 0, 960, 961, 964, 1000, 0,
140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
141 /* 1280x960@85Hz */
142 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
143 1504, 1728, 0, 960, 961, 964, 1011, 0,
144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
145 /* 1280x1024@60Hz */
146 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
147 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
149 /* 1280x1024@75Hz */
150 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
151 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
153 /* 1280x1024@85Hz */
154 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
155 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
157 /* 1360x768@60Hz */
158 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
159 1536, 1792, 0, 768, 771, 777, 795, 0,
160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
161 /* 1440x1050@60Hz */
162 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
163 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
164 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
165 /* 1440x1050@75Hz */
166 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
167 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
168 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
169 /* 1440x1050@85Hz */
170 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
171 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
172 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
173 /* 1440x900@60Hz */
174 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
175 1672, 1904, 0, 900, 903, 909, 934, 0,
176 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
177 /* 1440x900@75Hz */
178 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
179 1688, 1936, 0, 900, 903, 909, 942, 0,
180 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
181 /* 1440x900@85Hz */
182 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
183 1696, 1952, 0, 900, 903, 909, 948, 0,
184 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
185 /* 1600x1200@60Hz */
186 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
187 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
189 /* 1600x1200@65Hz */
190 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
191 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
193 /* 1600x1200@70Hz */
194 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
195 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
197 /* 1600x1200@75Hz */
198 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
199 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
201 /* 1600x1200@85Hz */
202 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
203 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
205 /* 1680x1050@60Hz */
206 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
207 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
208 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
209 /* 1680x1050@75Hz */
210 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
211 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
212 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
213 /* 1680x1050@85Hz */
214 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
215 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
216 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
217 /* 1792x1344@60Hz */
218 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
219 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
221 /* 1729x1344@75Hz */
222 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
223 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
224 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
225 /* 1853x1392@60Hz */
226 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
227 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
228 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
229 /* 1856x1392@75Hz */
230 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
231 2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
233 /* 1920x1200@60Hz */
234 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
235 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
237 /* 1920x1200@75Hz */
238 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
239 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
241 /* 1920x1200@85Hz */
242 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
243 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
245 /* 1920x1440@60Hz */
246 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
247 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
249 /* 1920x1440@75Hz */
250 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
251 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
253 /* 2560x1600@60Hz */
254 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
255 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
257 /* 2560x1600@75HZ */
258 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
259 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
261 /* 2560x1600@85HZ */
262 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
263 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
265};
266static const int drm_num_dmt_modes =
267 sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
268
269static struct drm_display_mode edid_est_modes[] = {
270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
271 968, 1056, 0, 600, 601, 605, 628, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
274 896, 1024, 0, 600, 601, 603, 625, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
276 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
277 720, 840, 0, 480, 481, 484, 500, 0,
278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
279 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
280 704, 832, 0, 480, 489, 491, 520, 0,
281 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
282 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
283 768, 864, 0, 480, 483, 486, 525, 0,
284 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
285 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
286 752, 800, 0, 480, 490, 492, 525, 0,
287 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
288 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
289 846, 900, 0, 400, 421, 423, 449, 0,
290 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
291 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
292 846, 900, 0, 400, 412, 414, 449, 0,
293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
294 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
295 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
297 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
298 1136, 1312, 0, 768, 769, 772, 800, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
300 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
301 1184, 1328, 0, 768, 771, 777, 806, 0,
302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
304 1184, 1344, 0, 768, 771, 777, 806, 0,
305 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
306 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
307 1208, 1264, 0, 768, 768, 776, 817, 0,
308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
309 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
310 928, 1152, 0, 624, 625, 628, 667, 0,
311 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
312 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
313 896, 1056, 0, 600, 601, 604, 625, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
315 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
316 976, 1040, 0, 600, 637, 643, 666, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
318 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
319 1344, 1600, 0, 864, 865, 868, 900, 0,
320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
321};
322
323static const struct {
324 short w;
325 short h;
326 short r;
327 short rb;
328} est3_modes[] = {
329 /* byte 6 */
330 { 640, 350, 85, 0 },
331 { 640, 400, 85, 0 },
332 { 720, 400, 85, 0 },
333 { 640, 480, 85, 0 },
334 { 848, 480, 60, 0 },
335 { 800, 600, 85, 0 },
336 { 1024, 768, 85, 0 },
337 { 1152, 864, 75, 0 },
338 /* byte 7 */
339 { 1280, 768, 60, 1 },
340 { 1280, 768, 60, 0 },
341 { 1280, 768, 75, 0 },
342 { 1280, 768, 85, 0 },
343 { 1280, 960, 60, 0 },
344 { 1280, 960, 85, 0 },
345 { 1280, 1024, 60, 0 },
346 { 1280, 1024, 85, 0 },
347 /* byte 8 */
348 { 1360, 768, 60, 0 },
349 { 1440, 900, 60, 1 },
350 { 1440, 900, 60, 0 },
351 { 1440, 900, 75, 0 },
352 { 1440, 900, 85, 0 },
353 { 1400, 1050, 60, 1 },
354 { 1400, 1050, 60, 0 },
355 { 1400, 1050, 75, 0 },
356 /* byte 9 */
357 { 1400, 1050, 85, 0 },
358 { 1680, 1050, 60, 1 },
359 { 1680, 1050, 60, 0 },
360 { 1680, 1050, 75, 0 },
361 { 1680, 1050, 85, 0 },
362 { 1600, 1200, 60, 0 },
363 { 1600, 1200, 65, 0 },
364 { 1600, 1200, 70, 0 },
365 /* byte 10 */
366 { 1600, 1200, 75, 0 },
367 { 1600, 1200, 85, 0 },
368 { 1792, 1344, 60, 0 },
369 { 1792, 1344, 85, 0 },
370 { 1856, 1392, 60, 0 },
371 { 1856, 1392, 75, 0 },
372 { 1920, 1200, 60, 1 },
373 { 1920, 1200, 60, 0 },
374 /* byte 11 */
375 { 1920, 1200, 75, 0 },
376 { 1920, 1200, 85, 0 },
377 { 1920, 1440, 60, 0 },
378 { 1920, 1440, 75, 0 },
379};
380static const int num_est3_modes = sizeof(est3_modes) / sizeof(est3_modes[0]);
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 719662034bbf..cef8d8da5952 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -94,10 +94,11 @@ static bool drm_fb_helper_connector_parse_command_line(struct drm_fb_helper_conn
94 int i; 94 int i;
95 enum drm_connector_force force = DRM_FORCE_UNSPECIFIED; 95 enum drm_connector_force force = DRM_FORCE_UNSPECIFIED;
96 struct drm_fb_helper_cmdline_mode *cmdline_mode; 96 struct drm_fb_helper_cmdline_mode *cmdline_mode;
97 struct drm_connector *connector = fb_helper_conn->connector; 97 struct drm_connector *connector;
98 98
99 if (!fb_helper_conn) 99 if (!fb_helper_conn)
100 return false; 100 return false;
101 connector = fb_helper_conn->connector;
101 102
102 cmdline_mode = &fb_helper_conn->cmdline_mode; 103 cmdline_mode = &fb_helper_conn->cmdline_mode;
103 if (!mode_option) 104 if (!mode_option)
diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
index 41dfaae41159..b744dad5c237 100644
--- a/drivers/gpu/drm/drm_fops.c
+++ b/drivers/gpu/drm/drm_fops.c
@@ -136,15 +136,9 @@ int drm_open(struct inode *inode, struct file *filp)
136 retcode = drm_open_helper(inode, filp, dev); 136 retcode = drm_open_helper(inode, filp, dev);
137 if (!retcode) { 137 if (!retcode) {
138 atomic_inc(&dev->counts[_DRM_STAT_OPENS]); 138 atomic_inc(&dev->counts[_DRM_STAT_OPENS]);
139 spin_lock(&dev->count_lock); 139 if (!dev->open_count++)
140 if (!dev->open_count++) {
141 spin_unlock(&dev->count_lock);
142 retcode = drm_setup(dev); 140 retcode = drm_setup(dev);
143 goto out;
144 }
145 spin_unlock(&dev->count_lock);
146 } 141 }
147out:
148 if (!retcode) { 142 if (!retcode) {
149 mutex_lock(&dev->struct_mutex); 143 mutex_lock(&dev->struct_mutex);
150 if (minor->type == DRM_MINOR_LEGACY) { 144 if (minor->type == DRM_MINOR_LEGACY) {
@@ -571,18 +565,14 @@ int drm_release(struct inode *inode, struct file *filp)
571 */ 565 */
572 566
573 atomic_inc(&dev->counts[_DRM_STAT_CLOSES]); 567 atomic_inc(&dev->counts[_DRM_STAT_CLOSES]);
574 spin_lock(&dev->count_lock);
575 if (!--dev->open_count) { 568 if (!--dev->open_count) {
576 if (atomic_read(&dev->ioctl_count)) { 569 if (atomic_read(&dev->ioctl_count)) {
577 DRM_ERROR("Device busy: %d\n", 570 DRM_ERROR("Device busy: %d\n",
578 atomic_read(&dev->ioctl_count)); 571 atomic_read(&dev->ioctl_count));
579 retcode = -EBUSY; 572 retcode = -EBUSY;
580 goto out; 573 } else
581 } 574 retcode = drm_lastclose(dev);
582 retcode = drm_lastclose(dev);
583 } 575 }
584out:
585 spin_unlock(&dev->count_lock);
586 mutex_unlock(&drm_global_mutex); 576 mutex_unlock(&drm_global_mutex);
587 577
588 return retcode; 578 return retcode;
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 4f1b86714489..bf92d07510df 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -322,7 +322,7 @@ drm_gem_flink_ioctl(struct drm_device *dev, void *data,
322 322
323 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 323 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
324 if (obj == NULL) 324 if (obj == NULL)
325 return -EBADF; 325 return -ENOENT;
326 326
327again: 327again:
328 if (idr_pre_get(&dev->object_name_idr, GFP_KERNEL) == 0) { 328 if (idr_pre_get(&dev->object_name_idr, GFP_KERNEL) == 0) {
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 7b03b197fc00..47db4df37a69 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -392,6 +392,7 @@ int drm_setversion(struct drm_device *dev, void *data, struct drm_file *file_pri
392 if (sv->drm_di_minor >= 1) { 392 if (sv->drm_di_minor >= 1) {
393 /* 393 /*
394 * Version 1.1 includes tying of DRM to specific device 394 * Version 1.1 includes tying of DRM to specific device
395 * Version 1.4 has proper PCI domain support
395 */ 396 */
396 retcode = drm_set_busid(dev, file_priv); 397 retcode = drm_set_busid(dev, file_priv);
397 if (retcode) 398 if (retcode)
diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c
index 3778360eceea..fda67468e603 100644
--- a/drivers/gpu/drm/drm_vm.c
+++ b/drivers/gpu/drm/drm_vm.c
@@ -138,7 +138,7 @@ static int drm_do_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
138 break; 138 break;
139 } 139 }
140 140
141 if (!agpmem) 141 if (&agpmem->head == &dev->agp->memory)
142 goto vm_fault_error; 142 goto vm_fault_error;
143 143
144 /* 144 /*
diff --git a/drivers/gpu/drm/i810/i810_dma.c b/drivers/gpu/drm/i810/i810_dma.c
index 0e6c131313d9..61b4caf220fa 100644
--- a/drivers/gpu/drm/i810/i810_dma.c
+++ b/drivers/gpu/drm/i810/i810_dma.c
@@ -1255,21 +1255,21 @@ long i810_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1255} 1255}
1256 1256
1257struct drm_ioctl_desc i810_ioctls[] = { 1257struct drm_ioctl_desc i810_ioctls[] = {
1258 DRM_IOCTL_DEF(DRM_I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 1258 DRM_IOCTL_DEF_DRV(I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1259 DRM_IOCTL_DEF(DRM_I810_VERTEX, i810_dma_vertex, DRM_AUTH|DRM_UNLOCKED), 1259 DRM_IOCTL_DEF_DRV(I810_VERTEX, i810_dma_vertex, DRM_AUTH|DRM_UNLOCKED),
1260 DRM_IOCTL_DEF(DRM_I810_CLEAR, i810_clear_bufs, DRM_AUTH|DRM_UNLOCKED), 1260 DRM_IOCTL_DEF_DRV(I810_CLEAR, i810_clear_bufs, DRM_AUTH|DRM_UNLOCKED),
1261 DRM_IOCTL_DEF(DRM_I810_FLUSH, i810_flush_ioctl, DRM_AUTH|DRM_UNLOCKED), 1261 DRM_IOCTL_DEF_DRV(I810_FLUSH, i810_flush_ioctl, DRM_AUTH|DRM_UNLOCKED),
1262 DRM_IOCTL_DEF(DRM_I810_GETAGE, i810_getage, DRM_AUTH|DRM_UNLOCKED), 1262 DRM_IOCTL_DEF_DRV(I810_GETAGE, i810_getage, DRM_AUTH|DRM_UNLOCKED),
1263 DRM_IOCTL_DEF(DRM_I810_GETBUF, i810_getbuf, DRM_AUTH|DRM_UNLOCKED), 1263 DRM_IOCTL_DEF_DRV(I810_GETBUF, i810_getbuf, DRM_AUTH|DRM_UNLOCKED),
1264 DRM_IOCTL_DEF(DRM_I810_SWAP, i810_swap_bufs, DRM_AUTH|DRM_UNLOCKED), 1264 DRM_IOCTL_DEF_DRV(I810_SWAP, i810_swap_bufs, DRM_AUTH|DRM_UNLOCKED),
1265 DRM_IOCTL_DEF(DRM_I810_COPY, i810_copybuf, DRM_AUTH|DRM_UNLOCKED), 1265 DRM_IOCTL_DEF_DRV(I810_COPY, i810_copybuf, DRM_AUTH|DRM_UNLOCKED),
1266 DRM_IOCTL_DEF(DRM_I810_DOCOPY, i810_docopy, DRM_AUTH|DRM_UNLOCKED), 1266 DRM_IOCTL_DEF_DRV(I810_DOCOPY, i810_docopy, DRM_AUTH|DRM_UNLOCKED),
1267 DRM_IOCTL_DEF(DRM_I810_OV0INFO, i810_ov0_info, DRM_AUTH|DRM_UNLOCKED), 1267 DRM_IOCTL_DEF_DRV(I810_OV0INFO, i810_ov0_info, DRM_AUTH|DRM_UNLOCKED),
1268 DRM_IOCTL_DEF(DRM_I810_FSTATUS, i810_fstatus, DRM_AUTH|DRM_UNLOCKED), 1268 DRM_IOCTL_DEF_DRV(I810_FSTATUS, i810_fstatus, DRM_AUTH|DRM_UNLOCKED),
1269 DRM_IOCTL_DEF(DRM_I810_OV0FLIP, i810_ov0_flip, DRM_AUTH|DRM_UNLOCKED), 1269 DRM_IOCTL_DEF_DRV(I810_OV0FLIP, i810_ov0_flip, DRM_AUTH|DRM_UNLOCKED),
1270 DRM_IOCTL_DEF(DRM_I810_MC, i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 1270 DRM_IOCTL_DEF_DRV(I810_MC, i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1271 DRM_IOCTL_DEF(DRM_I810_RSTATUS, i810_rstatus, DRM_AUTH|DRM_UNLOCKED), 1271 DRM_IOCTL_DEF_DRV(I810_RSTATUS, i810_rstatus, DRM_AUTH|DRM_UNLOCKED),
1272 DRM_IOCTL_DEF(DRM_I810_FLIP, i810_flip_bufs, DRM_AUTH|DRM_UNLOCKED), 1272 DRM_IOCTL_DEF_DRV(I810_FLIP, i810_flip_bufs, DRM_AUTH|DRM_UNLOCKED),
1273}; 1273};
1274 1274
1275int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls); 1275int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);
diff --git a/drivers/gpu/drm/i830/i830_dma.c b/drivers/gpu/drm/i830/i830_dma.c
index 5168862c9227..671aa18415ac 100644
--- a/drivers/gpu/drm/i830/i830_dma.c
+++ b/drivers/gpu/drm/i830/i830_dma.c
@@ -1524,20 +1524,20 @@ long i830_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1524} 1524}
1525 1525
1526struct drm_ioctl_desc i830_ioctls[] = { 1526struct drm_ioctl_desc i830_ioctls[] = {
1527 DRM_IOCTL_DEF(DRM_I830_INIT, i830_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 1527 DRM_IOCTL_DEF_DRV(I830_INIT, i830_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1528 DRM_IOCTL_DEF(DRM_I830_VERTEX, i830_dma_vertex, DRM_AUTH|DRM_UNLOCKED), 1528 DRM_IOCTL_DEF_DRV(I830_VERTEX, i830_dma_vertex, DRM_AUTH|DRM_UNLOCKED),
1529 DRM_IOCTL_DEF(DRM_I830_CLEAR, i830_clear_bufs, DRM_AUTH|DRM_UNLOCKED), 1529 DRM_IOCTL_DEF_DRV(I830_CLEAR, i830_clear_bufs, DRM_AUTH|DRM_UNLOCKED),
1530 DRM_IOCTL_DEF(DRM_I830_FLUSH, i830_flush_ioctl, DRM_AUTH|DRM_UNLOCKED), 1530 DRM_IOCTL_DEF_DRV(I830_FLUSH, i830_flush_ioctl, DRM_AUTH|DRM_UNLOCKED),
1531 DRM_IOCTL_DEF(DRM_I830_GETAGE, i830_getage, DRM_AUTH|DRM_UNLOCKED), 1531 DRM_IOCTL_DEF_DRV(I830_GETAGE, i830_getage, DRM_AUTH|DRM_UNLOCKED),
1532 DRM_IOCTL_DEF(DRM_I830_GETBUF, i830_getbuf, DRM_AUTH|DRM_UNLOCKED), 1532 DRM_IOCTL_DEF_DRV(I830_GETBUF, i830_getbuf, DRM_AUTH|DRM_UNLOCKED),
1533 DRM_IOCTL_DEF(DRM_I830_SWAP, i830_swap_bufs, DRM_AUTH|DRM_UNLOCKED), 1533 DRM_IOCTL_DEF_DRV(I830_SWAP, i830_swap_bufs, DRM_AUTH|DRM_UNLOCKED),
1534 DRM_IOCTL_DEF(DRM_I830_COPY, i830_copybuf, DRM_AUTH|DRM_UNLOCKED), 1534 DRM_IOCTL_DEF_DRV(I830_COPY, i830_copybuf, DRM_AUTH|DRM_UNLOCKED),
1535 DRM_IOCTL_DEF(DRM_I830_DOCOPY, i830_docopy, DRM_AUTH|DRM_UNLOCKED), 1535 DRM_IOCTL_DEF_DRV(I830_DOCOPY, i830_docopy, DRM_AUTH|DRM_UNLOCKED),
1536 DRM_IOCTL_DEF(DRM_I830_FLIP, i830_flip_bufs, DRM_AUTH|DRM_UNLOCKED), 1536 DRM_IOCTL_DEF_DRV(I830_FLIP, i830_flip_bufs, DRM_AUTH|DRM_UNLOCKED),
1537 DRM_IOCTL_DEF(DRM_I830_IRQ_EMIT, i830_irq_emit, DRM_AUTH|DRM_UNLOCKED), 1537 DRM_IOCTL_DEF_DRV(I830_IRQ_EMIT, i830_irq_emit, DRM_AUTH|DRM_UNLOCKED),
1538 DRM_IOCTL_DEF(DRM_I830_IRQ_WAIT, i830_irq_wait, DRM_AUTH|DRM_UNLOCKED), 1538 DRM_IOCTL_DEF_DRV(I830_IRQ_WAIT, i830_irq_wait, DRM_AUTH|DRM_UNLOCKED),
1539 DRM_IOCTL_DEF(DRM_I830_GETPARAM, i830_getparam, DRM_AUTH|DRM_UNLOCKED), 1539 DRM_IOCTL_DEF_DRV(I830_GETPARAM, i830_getparam, DRM_AUTH|DRM_UNLOCKED),
1540 DRM_IOCTL_DEF(DRM_I830_SETPARAM, i830_setparam, DRM_AUTH|DRM_UNLOCKED), 1540 DRM_IOCTL_DEF_DRV(I830_SETPARAM, i830_setparam, DRM_AUTH|DRM_UNLOCKED),
1541}; 1541};
1542 1542
1543int i830_max_ioctl = DRM_ARRAY_SIZE(i830_ioctls); 1543int i830_max_ioctl = DRM_ARRAY_SIZE(i830_ioctls);
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index f19ffe87af3c..a2d3509c393b 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -2360,46 +2360,46 @@ void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
2360} 2360}
2361 2361
2362struct drm_ioctl_desc i915_ioctls[] = { 2362struct drm_ioctl_desc i915_ioctls[] = {
2363 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 2363 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2364 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), 2364 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2365 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), 2365 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2366 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), 2366 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2367 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), 2367 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2368 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), 2368 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2369 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), 2369 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2370 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 2370 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2371 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH), 2371 DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2372 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH), 2372 DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2373 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 2373 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2374 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), 2374 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2375 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), 2375 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2376 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), 2376 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2377 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), 2377 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2378 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), 2378 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2379 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 2379 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2380 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 2380 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2381 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), 2381 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2382 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED), 2382 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2383 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), 2383 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2384 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), 2384 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2385 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), 2385 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2386 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED), 2386 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2387 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 2387 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2388 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 2388 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2389 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED), 2389 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2390 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED), 2390 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2391 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED), 2391 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2392 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED), 2392 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2393 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED), 2393 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2394 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED), 2394 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2395 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED), 2395 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2396 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED), 2396 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2397 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED), 2397 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2398 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED), 2398 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2399 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), 2399 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2400 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED), 2400 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2401 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), 2401 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2402 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), 2402 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2403}; 2403};
2404 2404
2405int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); 2405int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2a4ed7ca8b4e..0758c7802e6b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -456,7 +456,7 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
456 456
457 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 457 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
458 if (obj == NULL) 458 if (obj == NULL)
459 return -EBADF; 459 return -ENOENT;
460 obj_priv = to_intel_bo(obj); 460 obj_priv = to_intel_bo(obj);
461 461
462 /* Bounds check source. 462 /* Bounds check source.
@@ -919,7 +919,7 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
919 919
920 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 920 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
921 if (obj == NULL) 921 if (obj == NULL)
922 return -EBADF; 922 return -ENOENT;
923 obj_priv = to_intel_bo(obj); 923 obj_priv = to_intel_bo(obj);
924 924
925 /* Bounds check destination. 925 /* Bounds check destination.
@@ -1002,7 +1002,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1002 1002
1003 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 1003 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1004 if (obj == NULL) 1004 if (obj == NULL)
1005 return -EBADF; 1005 return -ENOENT;
1006 obj_priv = to_intel_bo(obj); 1006 obj_priv = to_intel_bo(obj);
1007 1007
1008 mutex_lock(&dev->struct_mutex); 1008 mutex_lock(&dev->struct_mutex);
@@ -1060,7 +1060,7 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1060 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 1060 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1061 if (obj == NULL) { 1061 if (obj == NULL) {
1062 mutex_unlock(&dev->struct_mutex); 1062 mutex_unlock(&dev->struct_mutex);
1063 return -EBADF; 1063 return -ENOENT;
1064 } 1064 }
1065 1065
1066#if WATCH_BUF 1066#if WATCH_BUF
@@ -1099,7 +1099,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1099 1099
1100 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 1100 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1101 if (obj == NULL) 1101 if (obj == NULL)
1102 return -EBADF; 1102 return -ENOENT;
1103 1103
1104 offset = args->offset; 1104 offset = args->offset;
1105 1105
@@ -1373,7 +1373,7 @@ i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1373 1373
1374 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 1374 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1375 if (obj == NULL) 1375 if (obj == NULL)
1376 return -EBADF; 1376 return -ENOENT;
1377 1377
1378 mutex_lock(&dev->struct_mutex); 1378 mutex_lock(&dev->struct_mutex);
1379 1379
@@ -3364,7 +3364,7 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3364 reloc->target_handle); 3364 reloc->target_handle);
3365 if (target_obj == NULL) { 3365 if (target_obj == NULL) {
3366 i915_gem_object_unpin(obj); 3366 i915_gem_object_unpin(obj);
3367 return -EBADF; 3367 return -ENOENT;
3368 } 3368 }
3369 target_obj_priv = to_intel_bo(target_obj); 3369 target_obj_priv = to_intel_bo(target_obj);
3370 3370
@@ -3781,7 +3781,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3781 exec_list[i].handle, i); 3781 exec_list[i].handle, i);
3782 /* prevent error path from reading uninitialized data */ 3782 /* prevent error path from reading uninitialized data */
3783 args->buffer_count = i + 1; 3783 args->buffer_count = i + 1;
3784 ret = -EBADF; 3784 ret = -ENOENT;
3785 goto err; 3785 goto err;
3786 } 3786 }
3787 3787
@@ -3791,7 +3791,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3791 object_list[i]); 3791 object_list[i]);
3792 /* prevent error path from reading uninitialized data */ 3792 /* prevent error path from reading uninitialized data */
3793 args->buffer_count = i + 1; 3793 args->buffer_count = i + 1;
3794 ret = -EBADF; 3794 ret = -EINVAL;
3795 goto err; 3795 goto err;
3796 } 3796 }
3797 obj_priv->in_execbuffer = true; 3797 obj_priv->in_execbuffer = true;
@@ -4265,7 +4265,7 @@ i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4265 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", 4265 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4266 args->handle); 4266 args->handle);
4267 mutex_unlock(&dev->struct_mutex); 4267 mutex_unlock(&dev->struct_mutex);
4268 return -EBADF; 4268 return -ENOENT;
4269 } 4269 }
4270 obj_priv = to_intel_bo(obj); 4270 obj_priv = to_intel_bo(obj);
4271 4271
@@ -4321,7 +4321,7 @@ i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4321 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", 4321 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4322 args->handle); 4322 args->handle);
4323 mutex_unlock(&dev->struct_mutex); 4323 mutex_unlock(&dev->struct_mutex);
4324 return -EBADF; 4324 return -ENOENT;
4325 } 4325 }
4326 4326
4327 obj_priv = to_intel_bo(obj); 4327 obj_priv = to_intel_bo(obj);
@@ -4355,7 +4355,7 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4355 if (obj == NULL) { 4355 if (obj == NULL) {
4356 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", 4356 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4357 args->handle); 4357 args->handle);
4358 return -EBADF; 4358 return -ENOENT;
4359 } 4359 }
4360 4360
4361 mutex_lock(&dev->struct_mutex); 4361 mutex_lock(&dev->struct_mutex);
@@ -4408,7 +4408,7 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4408 if (obj == NULL) { 4408 if (obj == NULL) {
4409 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", 4409 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4410 args->handle); 4410 args->handle);
4411 return -EBADF; 4411 return -ENOENT;
4412 } 4412 }
4413 4413
4414 mutex_lock(&dev->struct_mutex); 4414 mutex_lock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 155719e4d16f..710eca70b323 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -275,7 +275,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
275 275
276 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 276 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
277 if (obj == NULL) 277 if (obj == NULL)
278 return -EINVAL; 278 return -ENOENT;
279 obj_priv = to_intel_bo(obj); 279 obj_priv = to_intel_bo(obj);
280 280
281 if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) { 281 if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) {
@@ -362,7 +362,7 @@ i915_gem_get_tiling(struct drm_device *dev, void *data,
362 362
363 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 363 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
364 if (obj == NULL) 364 if (obj == NULL)
365 return -EINVAL; 365 return -ENOENT;
366 obj_priv = to_intel_bo(obj); 366 obj_priv = to_intel_bo(obj);
367 367
368 mutex_lock(&dev->struct_mutex); 368 mutex_lock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ae1718549eec..6bb5ffc76ced 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4330,15 +4330,12 @@ void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4330} 4330}
4331 4331
4332static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 4332static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4333 u16 *blue, uint32_t size) 4333 u16 *blue, uint32_t start, uint32_t size)
4334{ 4334{
4335 int end = (start + size > 256) ? 256 : start + size, i;
4335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4336 int i;
4337
4338 if (size != 256)
4339 return;
4340 4337
4341 for (i = 0; i < 256; i++) { 4338 for (i = start; i < end; i++) {
4342 intel_crtc->lut_r[i] = red[i] >> 8; 4339 intel_crtc->lut_r[i] = red[i] >> 8;
4343 intel_crtc->lut_g[i] = green[i] >> 8; 4340 intel_crtc->lut_g[i] = green[i] >> 8;
4344 intel_crtc->lut_b[i] = blue[i] >> 8; 4341 intel_crtc->lut_b[i] = blue[i] >> 8;
@@ -5312,18 +5309,18 @@ intel_user_framebuffer_create(struct drm_device *dev,
5312 5309
5313 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle); 5310 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5314 if (!obj) 5311 if (!obj)
5315 return NULL; 5312 return ERR_PTR(-ENOENT);
5316 5313
5317 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 5314 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5318 if (!intel_fb) 5315 if (!intel_fb)
5319 return NULL; 5316 return ERR_PTR(-ENOMEM);
5320 5317
5321 ret = intel_framebuffer_init(dev, intel_fb, 5318 ret = intel_framebuffer_init(dev, intel_fb,
5322 mode_cmd, obj); 5319 mode_cmd, obj);
5323 if (ret) { 5320 if (ret) {
5324 drm_gem_object_unreference_unlocked(obj); 5321 drm_gem_object_unreference_unlocked(obj);
5325 kfree(intel_fb); 5322 kfree(intel_fb);
5326 return NULL; 5323 return ERR_PTR(ret);
5327 } 5324 }
5328 5325
5329 return &intel_fb->base; 5326 return &intel_fb->base;
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 3e18c9e7729b..1d2d67ce4a84 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -119,7 +119,9 @@ static int intelfb_create(struct intel_fbdev *ifbdev,
119 119
120 info->par = ifbdev; 120 info->par = ifbdev;
121 121
122 intel_framebuffer_init(dev, &ifbdev->ifb, &mode_cmd, fbo); 122 ret = intel_framebuffer_init(dev, &ifbdev->ifb, &mode_cmd, fbo);
123 if (ret)
124 goto out_unpin;
123 125
124 fb = &ifbdev->ifb.base; 126 fb = &ifbdev->ifb.base;
125 127
diff --git a/drivers/gpu/drm/mga/mga_state.c b/drivers/gpu/drm/mga/mga_state.c
index fff82045c427..9ce2827f8c00 100644
--- a/drivers/gpu/drm/mga/mga_state.c
+++ b/drivers/gpu/drm/mga/mga_state.c
@@ -1085,19 +1085,19 @@ file_priv)
1085} 1085}
1086 1086
1087struct drm_ioctl_desc mga_ioctls[] = { 1087struct drm_ioctl_desc mga_ioctls[] = {
1088 DRM_IOCTL_DEF(DRM_MGA_INIT, mga_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1088 DRM_IOCTL_DEF_DRV(MGA_INIT, mga_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1089 DRM_IOCTL_DEF(DRM_MGA_FLUSH, mga_dma_flush, DRM_AUTH), 1089 DRM_IOCTL_DEF_DRV(MGA_FLUSH, mga_dma_flush, DRM_AUTH),
1090 DRM_IOCTL_DEF(DRM_MGA_RESET, mga_dma_reset, DRM_AUTH), 1090 DRM_IOCTL_DEF_DRV(MGA_RESET, mga_dma_reset, DRM_AUTH),
1091 DRM_IOCTL_DEF(DRM_MGA_SWAP, mga_dma_swap, DRM_AUTH), 1091 DRM_IOCTL_DEF_DRV(MGA_SWAP, mga_dma_swap, DRM_AUTH),
1092 DRM_IOCTL_DEF(DRM_MGA_CLEAR, mga_dma_clear, DRM_AUTH), 1092 DRM_IOCTL_DEF_DRV(MGA_CLEAR, mga_dma_clear, DRM_AUTH),
1093 DRM_IOCTL_DEF(DRM_MGA_VERTEX, mga_dma_vertex, DRM_AUTH), 1093 DRM_IOCTL_DEF_DRV(MGA_VERTEX, mga_dma_vertex, DRM_AUTH),
1094 DRM_IOCTL_DEF(DRM_MGA_INDICES, mga_dma_indices, DRM_AUTH), 1094 DRM_IOCTL_DEF_DRV(MGA_INDICES, mga_dma_indices, DRM_AUTH),
1095 DRM_IOCTL_DEF(DRM_MGA_ILOAD, mga_dma_iload, DRM_AUTH), 1095 DRM_IOCTL_DEF_DRV(MGA_ILOAD, mga_dma_iload, DRM_AUTH),
1096 DRM_IOCTL_DEF(DRM_MGA_BLIT, mga_dma_blit, DRM_AUTH), 1096 DRM_IOCTL_DEF_DRV(MGA_BLIT, mga_dma_blit, DRM_AUTH),
1097 DRM_IOCTL_DEF(DRM_MGA_GETPARAM, mga_getparam, DRM_AUTH), 1097 DRM_IOCTL_DEF_DRV(MGA_GETPARAM, mga_getparam, DRM_AUTH),
1098 DRM_IOCTL_DEF(DRM_MGA_SET_FENCE, mga_set_fence, DRM_AUTH), 1098 DRM_IOCTL_DEF_DRV(MGA_SET_FENCE, mga_set_fence, DRM_AUTH),
1099 DRM_IOCTL_DEF(DRM_MGA_WAIT_FENCE, mga_wait_fence, DRM_AUTH), 1099 DRM_IOCTL_DEF_DRV(MGA_WAIT_FENCE, mga_wait_fence, DRM_AUTH),
1100 DRM_IOCTL_DEF(DRM_MGA_DMA_BOOTSTRAP, mga_dma_bootstrap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1100 DRM_IOCTL_DEF_DRV(MGA_DMA_BOOTSTRAP, mga_dma_bootstrap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1101}; 1101};
1102 1102
1103int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls); 1103int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls);
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 90fdcda332be..0480f064f2c1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -426,18 +426,18 @@ nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
426 ***********************************/ 426 ***********************************/
427 427
428struct drm_ioctl_desc nouveau_ioctls[] = { 428struct drm_ioctl_desc nouveau_ioctls[] = {
429 DRM_IOCTL_DEF(DRM_NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH), 429 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH),
430 DRM_IOCTL_DEF(DRM_NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 430 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
431 DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH), 431 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH),
432 DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_AUTH), 432 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_AUTH),
433 DRM_IOCTL_DEF(DRM_NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_AUTH), 433 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_AUTH),
434 DRM_IOCTL_DEF(DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH), 434 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH),
435 DRM_IOCTL_DEF(DRM_NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH), 435 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH),
436 DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH), 436 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH),
437 DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH), 437 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH),
438 DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH), 438 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH),
439 DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH), 439 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH),
440 DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH), 440 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH),
441}; 441};
442 442
443int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls); 443int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 74e6b4ed12c0..2e11fd65b4dd 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -84,16 +84,16 @@ nouveau_user_framebuffer_create(struct drm_device *dev,
84 84
85 gem = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); 85 gem = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
86 if (!gem) 86 if (!gem)
87 return NULL; 87 return ERR_PTR(-ENOENT);
88 88
89 nouveau_fb = kzalloc(sizeof(struct nouveau_framebuffer), GFP_KERNEL); 89 nouveau_fb = kzalloc(sizeof(struct nouveau_framebuffer), GFP_KERNEL);
90 if (!nouveau_fb) 90 if (!nouveau_fb)
91 return NULL; 91 return ERR_PTR(-ENOMEM);
92 92
93 ret = nouveau_framebuffer_init(dev, nouveau_fb, mode_cmd, nouveau_gem_object(gem)); 93 ret = nouveau_framebuffer_init(dev, nouveau_fb, mode_cmd, nouveau_gem_object(gem));
94 if (ret) { 94 if (ret) {
95 drm_gem_object_unreference(gem); 95 drm_gem_object_unreference(gem);
96 return NULL; 96 return ERR_PTR(ret);
97 } 97 }
98 98
99 return &nouveau_fb->base; 99 return &nouveau_fb->base;
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 93711dfcafc1..581c67cd7b24 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -284,7 +284,7 @@ retry:
284 if (!gem) { 284 if (!gem) {
285 NV_ERROR(dev, "Unknown handle 0x%08x\n", b->handle); 285 NV_ERROR(dev, "Unknown handle 0x%08x\n", b->handle);
286 validate_fini(op, NULL); 286 validate_fini(op, NULL);
287 return -EINVAL; 287 return -ENOENT;
288 } 288 }
289 nvbo = gem->driver_private; 289 nvbo = gem->driver_private;
290 290
@@ -777,7 +777,7 @@ nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data,
777 777
778 gem = drm_gem_object_lookup(dev, file_priv, req->handle); 778 gem = drm_gem_object_lookup(dev, file_priv, req->handle);
779 if (!gem) 779 if (!gem)
780 return ret; 780 return -ENOENT;
781 nvbo = nouveau_gem_object(gem); 781 nvbo = nouveau_gem_object(gem);
782 782
783 if (nvbo->cpu_filp) { 783 if (nvbo->cpu_filp) {
@@ -815,7 +815,7 @@ nouveau_gem_ioctl_cpu_fini(struct drm_device *dev, void *data,
815 815
816 gem = drm_gem_object_lookup(dev, file_priv, req->handle); 816 gem = drm_gem_object_lookup(dev, file_priv, req->handle);
817 if (!gem) 817 if (!gem)
818 return ret; 818 return -ENOENT;
819 nvbo = nouveau_gem_object(gem); 819 nvbo = nouveau_gem_object(gem);
820 820
821 if (nvbo->cpu_filp != file_priv) 821 if (nvbo->cpu_filp != file_priv)
@@ -840,7 +840,7 @@ nouveau_gem_ioctl_info(struct drm_device *dev, void *data,
840 840
841 gem = drm_gem_object_lookup(dev, file_priv, req->handle); 841 gem = drm_gem_object_lookup(dev, file_priv, req->handle);
842 if (!gem) 842 if (!gem)
843 return -EINVAL; 843 return -ENOENT;
844 844
845 ret = nouveau_gem_info(gem, req); 845 ret = nouveau_gem_info(gem, req);
846 drm_gem_object_unreference_unlocked(gem); 846 drm_gem_object_unreference_unlocked(gem);
diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
index 08c7e073edce..497df8765f28 100644
--- a/drivers/gpu/drm/nouveau/nv04_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
@@ -742,15 +742,13 @@ nv_crtc_gamma_load(struct drm_crtc *crtc)
742} 742}
743 743
744static void 744static void
745nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t size) 745nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start,
746 uint32_t size)
746{ 747{
748 int end = (start + size > 256) ? 256 : start + size, i;
747 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 749 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
748 int i;
749
750 if (size != 256)
751 return;
752 750
753 for (i = 0; i < 256; i++) { 751 for (i = start; i < end; i++) {
754 nv_crtc->lut.r[i] = r[i]; 752 nv_crtc->lut.r[i] = r[i];
755 nv_crtc->lut.g[i] = g[i]; 753 nv_crtc->lut.g[i] = g[i];
756 nv_crtc->lut.b[i] = b[i]; 754 nv_crtc->lut.b[i] = b[i];
@@ -917,7 +915,7 @@ nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
917 915
918 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); 916 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
919 if (!gem) 917 if (!gem)
920 return -EINVAL; 918 return -ENOENT;
921 cursor = nouveau_gem_object(gem); 919 cursor = nouveau_gem_object(gem);
922 920
923 ret = nouveau_bo_map(cursor); 921 ret = nouveau_bo_map(cursor);
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
index a438e56a5286..bfd4ca2fe7ef 100644
--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -365,7 +365,7 @@ nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
365 365
366 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); 366 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
367 if (!gem) 367 if (!gem)
368 return -EINVAL; 368 return -ENOENT;
369 cursor = nouveau_gem_object(gem); 369 cursor = nouveau_gem_object(gem);
370 370
371 ret = nouveau_bo_map(cursor); 371 ret = nouveau_bo_map(cursor);
@@ -398,15 +398,12 @@ nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
398 398
399static void 399static void
400nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, 400nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
401 uint32_t size) 401 uint32_t start, uint32_t size)
402{ 402{
403 int end = (start + size > 256) ? 256 : start + size, i;
403 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 404 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
404 int i;
405 405
406 if (size != 256) 406 for (i = start; i < end; i++) {
407 return;
408
409 for (i = 0; i < 256; i++) {
410 nv_crtc->lut.r[i] = r[i]; 407 nv_crtc->lut.r[i] = r[i];
411 nv_crtc->lut.g[i] = g[i]; 408 nv_crtc->lut.g[i] = g[i];
412 nv_crtc->lut.b[i] = b[i]; 409 nv_crtc->lut.b[i] = b[i];
diff --git a/drivers/gpu/drm/r128/r128_state.c b/drivers/gpu/drm/r128/r128_state.c
index 077af1f2f9b4..a9e33ce65918 100644
--- a/drivers/gpu/drm/r128/r128_state.c
+++ b/drivers/gpu/drm/r128/r128_state.c
@@ -1639,30 +1639,29 @@ void r128_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
1639 r128_do_cleanup_pageflip(dev); 1639 r128_do_cleanup_pageflip(dev);
1640 } 1640 }
1641} 1641}
1642
1643void r128_driver_lastclose(struct drm_device *dev) 1642void r128_driver_lastclose(struct drm_device *dev)
1644{ 1643{
1645 r128_do_cleanup_cce(dev); 1644 r128_do_cleanup_cce(dev);
1646} 1645}
1647 1646
1648struct drm_ioctl_desc r128_ioctls[] = { 1647struct drm_ioctl_desc r128_ioctls[] = {
1649 DRM_IOCTL_DEF(DRM_R128_INIT, r128_cce_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1648 DRM_IOCTL_DEF_DRV(R128_INIT, r128_cce_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1650 DRM_IOCTL_DEF(DRM_R128_CCE_START, r128_cce_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1649 DRM_IOCTL_DEF_DRV(R128_CCE_START, r128_cce_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1651 DRM_IOCTL_DEF(DRM_R128_CCE_STOP, r128_cce_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1650 DRM_IOCTL_DEF_DRV(R128_CCE_STOP, r128_cce_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1652 DRM_IOCTL_DEF(DRM_R128_CCE_RESET, r128_cce_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1651 DRM_IOCTL_DEF_DRV(R128_CCE_RESET, r128_cce_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1653 DRM_IOCTL_DEF(DRM_R128_CCE_IDLE, r128_cce_idle, DRM_AUTH), 1652 DRM_IOCTL_DEF_DRV(R128_CCE_IDLE, r128_cce_idle, DRM_AUTH),
1654 DRM_IOCTL_DEF(DRM_R128_RESET, r128_engine_reset, DRM_AUTH), 1653 DRM_IOCTL_DEF_DRV(R128_RESET, r128_engine_reset, DRM_AUTH),
1655 DRM_IOCTL_DEF(DRM_R128_FULLSCREEN, r128_fullscreen, DRM_AUTH), 1654 DRM_IOCTL_DEF_DRV(R128_FULLSCREEN, r128_fullscreen, DRM_AUTH),
1656 DRM_IOCTL_DEF(DRM_R128_SWAP, r128_cce_swap, DRM_AUTH), 1655 DRM_IOCTL_DEF_DRV(R128_SWAP, r128_cce_swap, DRM_AUTH),
1657 DRM_IOCTL_DEF(DRM_R128_FLIP, r128_cce_flip, DRM_AUTH), 1656 DRM_IOCTL_DEF_DRV(R128_FLIP, r128_cce_flip, DRM_AUTH),
1658 DRM_IOCTL_DEF(DRM_R128_CLEAR, r128_cce_clear, DRM_AUTH), 1657 DRM_IOCTL_DEF_DRV(R128_CLEAR, r128_cce_clear, DRM_AUTH),
1659 DRM_IOCTL_DEF(DRM_R128_VERTEX, r128_cce_vertex, DRM_AUTH), 1658 DRM_IOCTL_DEF_DRV(R128_VERTEX, r128_cce_vertex, DRM_AUTH),
1660 DRM_IOCTL_DEF(DRM_R128_INDICES, r128_cce_indices, DRM_AUTH), 1659 DRM_IOCTL_DEF_DRV(R128_INDICES, r128_cce_indices, DRM_AUTH),
1661 DRM_IOCTL_DEF(DRM_R128_BLIT, r128_cce_blit, DRM_AUTH), 1660 DRM_IOCTL_DEF_DRV(R128_BLIT, r128_cce_blit, DRM_AUTH),
1662 DRM_IOCTL_DEF(DRM_R128_DEPTH, r128_cce_depth, DRM_AUTH), 1661 DRM_IOCTL_DEF_DRV(R128_DEPTH, r128_cce_depth, DRM_AUTH),
1663 DRM_IOCTL_DEF(DRM_R128_STIPPLE, r128_cce_stipple, DRM_AUTH), 1662 DRM_IOCTL_DEF_DRV(R128_STIPPLE, r128_cce_stipple, DRM_AUTH),
1664 DRM_IOCTL_DEF(DRM_R128_INDIRECT, r128_cce_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1663 DRM_IOCTL_DEF_DRV(R128_INDIRECT, r128_cce_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1665 DRM_IOCTL_DEF(DRM_R128_GETPARAM, r128_getparam, DRM_AUTH), 1664 DRM_IOCTL_DEF_DRV(R128_GETPARAM, r128_getparam, DRM_AUTH),
1666}; 1665};
1667 1666
1668int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls); 1667int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls);
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 12ad512bd3d3..577239a24fd5 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -471,6 +471,8 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
471 struct radeon_encoder *radeon_encoder = NULL; 471 struct radeon_encoder *radeon_encoder = NULL;
472 u32 adjusted_clock = mode->clock; 472 u32 adjusted_clock = mode->clock;
473 int encoder_mode = 0; 473 int encoder_mode = 0;
474 u32 dp_clock = mode->clock;
475 int bpc = 8;
474 476
475 /* reset the pll flags */ 477 /* reset the pll flags */
476 pll->flags = 0; 478 pll->flags = 0;
@@ -513,6 +515,17 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
513 if (encoder->crtc == crtc) { 515 if (encoder->crtc == crtc) {
514 radeon_encoder = to_radeon_encoder(encoder); 516 radeon_encoder = to_radeon_encoder(encoder);
515 encoder_mode = atombios_get_encoder_mode(encoder); 517 encoder_mode = atombios_get_encoder_mode(encoder);
518 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
519 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
520 if (connector) {
521 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
522 struct radeon_connector_atom_dig *dig_connector =
523 radeon_connector->con_priv;
524
525 dp_clock = dig_connector->dp_clock;
526 }
527 }
528
516 if (ASIC_IS_AVIVO(rdev)) { 529 if (ASIC_IS_AVIVO(rdev)) {
517 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 530 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
518 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 531 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
@@ -555,6 +568,14 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
555 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 568 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
556 args.v1.ucTransmitterID = radeon_encoder->encoder_id; 569 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
557 args.v1.ucEncodeMode = encoder_mode; 570 args.v1.ucEncodeMode = encoder_mode;
571 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
572 /* may want to enable SS on DP eventually */
573 /* args.v1.ucConfig |=
574 ADJUST_DISPLAY_CONFIG_SS_ENABLE;*/
575 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
576 args.v1.ucConfig |=
577 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
578 }
558 579
559 atom_execute_table(rdev->mode_info.atom_context, 580 atom_execute_table(rdev->mode_info.atom_context,
560 index, (uint32_t *)&args); 581 index, (uint32_t *)&args);
@@ -568,10 +589,20 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
568 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 589 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
569 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 590 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
570 591
571 if (encoder_mode == ATOM_ENCODER_MODE_DP) 592 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
593 /* may want to enable SS on DP/eDP eventually */
594 /*args.v3.sInput.ucDispPllConfig |=
595 DISPPLL_CONFIG_SS_ENABLE;*/
572 args.v3.sInput.ucDispPllConfig |= 596 args.v3.sInput.ucDispPllConfig |=
573 DISPPLL_CONFIG_COHERENT_MODE; 597 DISPPLL_CONFIG_COHERENT_MODE;
574 else { 598 /* 16200 or 27000 */
599 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
600 } else {
601 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
602 /* deep color support */
603 args.v3.sInput.usPixelClock =
604 cpu_to_le16((mode->clock * bpc / 8) / 10);
605 }
575 if (dig->coherent_mode) 606 if (dig->coherent_mode)
576 args.v3.sInput.ucDispPllConfig |= 607 args.v3.sInput.ucDispPllConfig |=
577 DISPPLL_CONFIG_COHERENT_MODE; 608 DISPPLL_CONFIG_COHERENT_MODE;
@@ -580,13 +611,19 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
580 DISPPLL_CONFIG_DUAL_LINK; 611 DISPPLL_CONFIG_DUAL_LINK;
581 } 612 }
582 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 613 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
583 /* may want to enable SS on DP/eDP eventually */ 614 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
584 /*args.v3.sInput.ucDispPllConfig |= 615 /* may want to enable SS on DP/eDP eventually */
585 DISPPLL_CONFIG_SS_ENABLE;*/ 616 /*args.v3.sInput.ucDispPllConfig |=
586 if (encoder_mode == ATOM_ENCODER_MODE_DP) 617 DISPPLL_CONFIG_SS_ENABLE;*/
587 args.v3.sInput.ucDispPllConfig |= 618 args.v3.sInput.ucDispPllConfig |=
588 DISPPLL_CONFIG_COHERENT_MODE; 619 DISPPLL_CONFIG_COHERENT_MODE;
589 else { 620 /* 16200 or 27000 */
621 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
622 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
623 /* want to enable SS on LVDS eventually */
624 /*args.v3.sInput.ucDispPllConfig |=
625 DISPPLL_CONFIG_SS_ENABLE;*/
626 } else {
590 if (mode->clock > 165000) 627 if (mode->clock > 165000)
591 args.v3.sInput.ucDispPllConfig |= 628 args.v3.sInput.ucDispPllConfig |=
592 DISPPLL_CONFIG_DUAL_LINK; 629 DISPPLL_CONFIG_DUAL_LINK;
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 36e0d4b545e6..4e7778d44b8d 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -610,7 +610,7 @@ void dp_link_train(struct drm_encoder *encoder,
610 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; 610 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
611 else 611 else
612 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; 612 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
613 if (dig_connector->linkb) 613 if (dig->linkb)
614 enc_id |= ATOM_DP_CONFIG_LINK_B; 614 enc_id |= ATOM_DP_CONFIG_LINK_B;
615 else 615 else
616 enc_id |= ATOM_DP_CONFIG_LINK_A; 616 enc_id |= ATOM_DP_CONFIG_LINK_A;
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index 68e6f4349309..4f4cd8b286d5 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -200,7 +200,7 @@ int r600_page_table_init(struct drm_device *dev)
200 entry->pagelist[i], 0, 200 entry->pagelist[i], 0,
201 PAGE_SIZE, 201 PAGE_SIZE,
202 PCI_DMA_BIDIRECTIONAL); 202 PCI_DMA_BIDIRECTIONAL);
203 if (entry->busaddr[i] == 0) { 203 if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) {
204 DRM_ERROR("unable to map PCIGART pages!\n"); 204 DRM_ERROR("unable to map PCIGART pages!\n");
205 r600_page_table_cleanup(dev, gart_info); 205 r600_page_table_cleanup(dev, gart_info);
206 goto done; 206 goto done;
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index c3ea212e0c3c..d8864949e387 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -133,6 +133,7 @@ static inline int r600_bpe_from_format(u32 *bpe, u32 format)
133 case V_038004_FMT_GB_GR: 133 case V_038004_FMT_GB_GR:
134 case V_038004_FMT_BG_RG: 134 case V_038004_FMT_BG_RG:
135 case V_038004_COLOR_INVALID: 135 case V_038004_COLOR_INVALID:
136 default:
136 *bpe = 16; 137 *bpe = 16;
137 return -EINVAL; 138 return -EINVAL;
138 } 139 }
@@ -174,7 +175,7 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
174 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n"); 175 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
175 return -EINVAL; 176 return -EINVAL;
176 } 177 }
177 size = radeon_bo_size(track->cb_color_bo[i]); 178 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
178 if (r600_bpe_from_format(&bpe, G_0280A0_FORMAT(track->cb_color_info[i]))) { 179 if (r600_bpe_from_format(&bpe, G_0280A0_FORMAT(track->cb_color_info[i]))) {
179 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", 180 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
180 __func__, __LINE__, G_0280A0_FORMAT(track->cb_color_info[i]), 181 __func__, __LINE__, G_0280A0_FORMAT(track->cb_color_info[i]),
@@ -327,7 +328,6 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
327 dev_warn(p->dev, "z/stencil buffer size not set\n"); 328 dev_warn(p->dev, "z/stencil buffer size not set\n");
328 return -EINVAL; 329 return -EINVAL;
329 } 330 }
330 printk_once(KERN_WARNING "You have old & broken userspace please consider updating mesa\n");
331 tmp = radeon_bo_size(track->db_bo) - track->db_offset; 331 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
332 tmp = (tmp / bpe) >> 6; 332 tmp = (tmp / bpe) >> 6;
333 if (!tmp) { 333 if (!tmp) {
@@ -882,8 +882,6 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
882 return -EINVAL; 882 return -EINVAL;
883 } 883 }
884 ib[idx] = track->cb_color_base_last[tmp]; 884 ib[idx] = track->cb_color_base_last[tmp];
885 printk_once(KERN_WARNING "You have old & broken userspace "
886 "please consider updating mesa & xf86-video-ati\n");
887 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp]; 885 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
888 } else { 886 } else {
889 r = r600_cs_packet_next_reloc(p, &reloc); 887 r = r600_cs_packet_next_reloc(p, &reloc);
@@ -910,8 +908,6 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
910 return -EINVAL; 908 return -EINVAL;
911 } 909 }
912 ib[idx] = track->cb_color_base_last[tmp]; 910 ib[idx] = track->cb_color_base_last[tmp];
913 printk_once(KERN_WARNING "You have old & broken userspace "
914 "please consider updating mesa & xf86-video-ati\n");
915 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp]; 911 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
916 } else { 912 } else {
917 r = r600_cs_packet_next_reloc(p, &reloc); 913 r = r600_cs_packet_next_reloc(p, &reloc);
@@ -938,7 +934,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
938 return -EINVAL; 934 return -EINVAL;
939 } 935 }
940 tmp = (reg - CB_COLOR0_BASE) / 4; 936 tmp = (reg - CB_COLOR0_BASE) / 4;
941 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); 937 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
942 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 938 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
943 track->cb_color_base_last[tmp] = ib[idx]; 939 track->cb_color_base_last[tmp] = ib[idx];
944 track->cb_color_bo[tmp] = reloc->robj; 940 track->cb_color_bo[tmp] = reloc->robj;
@@ -950,7 +946,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
950 "0x%04X\n", reg); 946 "0x%04X\n", reg);
951 return -EINVAL; 947 return -EINVAL;
952 } 948 }
953 track->db_offset = radeon_get_ib_value(p, idx); 949 track->db_offset = radeon_get_ib_value(p, idx) << 8;
954 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 950 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
955 track->db_bo = reloc->robj; 951 track->db_bo = reloc->robj;
956 break; 952 break;
@@ -1055,10 +1051,10 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels
1055 } 1051 }
1056 *l0_size = ALIGN((w0 * bpe), pitch_align) * h0 * d0; 1052 *l0_size = ALIGN((w0 * bpe), pitch_align) * h0 * d0;
1057 *mipmap_size = offset; 1053 *mipmap_size = offset;
1058 if (!blevel)
1059 *mipmap_size -= *l0_size;
1060 if (!nlevels) 1054 if (!nlevels)
1061 *mipmap_size = *l0_size; 1055 *mipmap_size = *l0_size;
1056 if (!blevel)
1057 *mipmap_size -= *l0_size;
1062} 1058}
1063 1059
1064/** 1060/**
@@ -1165,14 +1161,14 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i
1165 (pitch_align * bpe), 1161 (pitch_align * bpe),
1166 &l0_size, &mipmap_size); 1162 &l0_size, &mipmap_size);
1167 /* using get ib will give us the offset into the texture bo */ 1163 /* using get ib will give us the offset into the texture bo */
1168 word0 = radeon_get_ib_value(p, idx + 2); 1164 word0 = radeon_get_ib_value(p, idx + 2) << 8;
1169 if ((l0_size + word0) > radeon_bo_size(texture)) { 1165 if ((l0_size + word0) > radeon_bo_size(texture)) {
1170 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n", 1166 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
1171 w0, h0, bpe, word0, l0_size, radeon_bo_size(texture)); 1167 w0, h0, bpe, word0, l0_size, radeon_bo_size(texture));
1172 return -EINVAL; 1168 return -EINVAL;
1173 } 1169 }
1174 /* using get ib will give us the offset into the mipmap bo */ 1170 /* using get ib will give us the offset into the mipmap bo */
1175 word0 = radeon_get_ib_value(p, idx + 3); 1171 word0 = radeon_get_ib_value(p, idx + 3) << 8;
1176 if ((mipmap_size + word0) > radeon_bo_size(mipmap)) { 1172 if ((mipmap_size + word0) > radeon_bo_size(mipmap)) {
1177 dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n", 1173 dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1178 w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture)); 1174 w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));
@@ -1366,7 +1362,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1366 } 1362 }
1367 for (i = 0; i < (pkt->count / 7); i++) { 1363 for (i = 0; i < (pkt->count / 7); i++) {
1368 struct radeon_bo *texture, *mipmap; 1364 struct radeon_bo *texture, *mipmap;
1369 u32 size, offset; 1365 u32 size, offset, base_offset, mip_offset;
1370 1366
1371 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { 1367 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1372 case SQ_TEX_VTX_VALID_TEXTURE: 1368 case SQ_TEX_VTX_VALID_TEXTURE:
@@ -1376,7 +1372,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1376 DRM_ERROR("bad SET_RESOURCE\n"); 1372 DRM_ERROR("bad SET_RESOURCE\n");
1377 return -EINVAL; 1373 return -EINVAL;
1378 } 1374 }
1379 ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1375 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1380 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1376 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1381 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); 1377 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1382 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1378 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
@@ -1388,12 +1384,14 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1388 DRM_ERROR("bad SET_RESOURCE\n"); 1384 DRM_ERROR("bad SET_RESOURCE\n");
1389 return -EINVAL; 1385 return -EINVAL;
1390 } 1386 }
1391 ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1387 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1392 mipmap = reloc->robj; 1388 mipmap = reloc->robj;
1393 r = r600_check_texture_resource(p, idx+(i*7)+1, 1389 r = r600_check_texture_resource(p, idx+(i*7)+1,
1394 texture, mipmap, reloc->lobj.tiling_flags); 1390 texture, mipmap, reloc->lobj.tiling_flags);
1395 if (r) 1391 if (r)
1396 return r; 1392 return r;
1393 ib[idx+1+(i*7)+2] += base_offset;
1394 ib[idx+1+(i*7)+3] += mip_offset;
1397 break; 1395 break;
1398 case SQ_TEX_VTX_VALID_BUFFER: 1396 case SQ_TEX_VTX_VALID_BUFFER:
1399 /* vtx base */ 1397 /* vtx base */
@@ -1403,10 +1401,11 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1403 return -EINVAL; 1401 return -EINVAL;
1404 } 1402 }
1405 offset = radeon_get_ib_value(p, idx+1+(i*7)+0); 1403 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1406 size = radeon_get_ib_value(p, idx+1+(i*7)+1); 1404 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
1407 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { 1405 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1408 /* force size to size of the buffer */ 1406 /* force size to size of the buffer */
1409 dev_warn(p->dev, "vbo resource seems too big for the bo\n"); 1407 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
1408 size + offset, radeon_bo_size(reloc->robj));
1410 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj); 1409 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
1411 } 1410 }
1412 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff); 1411 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 3cd1c470b777..3dfcfa3ca425 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1100,6 +1100,8 @@ struct radeon_device {
1100 struct notifier_block acpi_nb; 1100 struct notifier_block acpi_nb;
1101 /* only one userspace can use Hyperz features at a time */ 1101 /* only one userspace can use Hyperz features at a time */
1102 struct drm_file *hyperz_filp; 1102 struct drm_file *hyperz_filp;
1103 /* i2c buses */
1104 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1103}; 1105};
1104 1106
1105int radeon_device_init(struct radeon_device *rdev, 1107int radeon_device_init(struct radeon_device *rdev,
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c
index f40dfb77f9b1..bd2f33e5c91a 100644
--- a/drivers/gpu/drm/radeon/radeon_agp.c
+++ b/drivers/gpu/drm/radeon/radeon_agp.c
@@ -156,7 +156,13 @@ int radeon_agp_init(struct radeon_device *rdev)
156 } 156 }
157 157
158 mode.mode = info.mode; 158 mode.mode = info.mode;
159 agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode; 159 /* chips with the agp to pcie bridge don't have the AGP_STATUS register
160 * Just use the whatever mode the host sets up.
161 */
162 if (rdev->family <= CHIP_RV350)
163 agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
164 else
165 agp_status = mode.mode;
160 is_v3 = !!(agp_status & RADEON_AGPv3_MODE); 166 is_v3 = !!(agp_status & RADEON_AGPv3_MODE);
161 167
162 if (is_v3) { 168 if (is_v3) {
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 646f96f97c77..a21bf88e8c2d 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -733,6 +733,7 @@ static struct radeon_asic evergreen_asic = {
733 .set_engine_clock = &radeon_atom_set_engine_clock, 733 .set_engine_clock = &radeon_atom_set_engine_clock,
734 .get_memory_clock = &radeon_atom_get_memory_clock, 734 .get_memory_clock = &radeon_atom_get_memory_clock,
735 .set_memory_clock = &radeon_atom_set_memory_clock, 735 .set_memory_clock = &radeon_atom_set_memory_clock,
736 .get_pcie_lanes = NULL,
736 .set_pcie_lanes = NULL, 737 .set_pcie_lanes = NULL,
737 .set_clock_gating = NULL, 738 .set_clock_gating = NULL,
738 .set_surface_reg = r600_set_surface_reg, 739 .set_surface_reg = r600_set_surface_reg,
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 3bc2bcdf5308..61141981880d 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -32,11 +32,11 @@
32 32
33/* from radeon_encoder.c */ 33/* from radeon_encoder.c */
34extern uint32_t 34extern uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, 35radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac); 36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev); 37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void 38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, 39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device); 40 uint32_t supported_device);
41 41
42/* from radeon_connector.c */ 42/* from radeon_connector.c */
@@ -46,13 +46,14 @@ radeon_add_atom_connector(struct drm_device *dev,
46 uint32_t supported_device, 46 uint32_t supported_device,
47 int connector_type, 47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus, 48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info, 49 uint32_t igp_lane_info,
50 uint16_t connector_object_id, 50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd); 51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
52 53
53/* from radeon_legacy_encoder.c */ 54/* from radeon_legacy_encoder.c */
54extern void 55extern void
55radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, 56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
56 uint32_t supported_device); 57 uint32_t supported_device);
57 58
58union atom_supported_devices { 59union atom_supported_devices {
@@ -114,7 +115,8 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_dev
114 115
115 i2c.i2c_id = gpio->sucI2cId.ucAccess; 116 i2c.i2c_id = gpio->sucI2cId.ucAccess;
116 117
117 i2c.valid = true; 118 if (i2c.mask_clk_reg)
119 i2c.valid = true;
118 break; 120 break;
119 } 121 }
120 } 122 }
@@ -123,6 +125,66 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_dev
123 return i2c; 125 return i2c;
124} 126}
125 127
128void radeon_atombios_i2c_init(struct radeon_device *rdev)
129{
130 struct atom_context *ctx = rdev->mode_info.atom_context;
131 ATOM_GPIO_I2C_ASSIGMENT *gpio;
132 struct radeon_i2c_bus_rec i2c;
133 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
134 struct _ATOM_GPIO_I2C_INFO *i2c_info;
135 uint16_t data_offset, size;
136 int i, num_indices;
137 char stmp[32];
138
139 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
140
141 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
142 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
143
144 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
145 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
146
147 for (i = 0; i < num_indices; i++) {
148 gpio = &i2c_info->asGPIO_Info[i];
149 i2c.valid = false;
150 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
151 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
152 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
153 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
154 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
155 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
156 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
157 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
158 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
159 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
160 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
161 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
162 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
163 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
164 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
165 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
166
167 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
168 i2c.hw_capable = true;
169 else
170 i2c.hw_capable = false;
171
172 if (gpio->sucI2cId.ucAccess == 0xa0)
173 i2c.mm_i2c = true;
174 else
175 i2c.mm_i2c = false;
176
177 i2c.i2c_id = gpio->sucI2cId.ucAccess;
178
179 if (i2c.mask_clk_reg) {
180 i2c.valid = true;
181 sprintf(stmp, "0x%x", i2c.i2c_id);
182 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
183 }
184 }
185 }
186}
187
126static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev, 188static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
127 u8 id) 189 u8 id)
128{ 190{
@@ -164,6 +226,8 @@ static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device
164 struct radeon_hpd hpd; 226 struct radeon_hpd hpd;
165 u32 reg; 227 u32 reg;
166 228
229 memset(&hpd, 0, sizeof(struct radeon_hpd));
230
167 if (ASIC_IS_DCE4(rdev)) 231 if (ASIC_IS_DCE4(rdev))
168 reg = EVERGREEN_DC_GPIO_HPD_A; 232 reg = EVERGREEN_DC_GPIO_HPD_A;
169 else 233 else
@@ -206,6 +270,7 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
206 uint16_t *line_mux, 270 uint16_t *line_mux,
207 struct radeon_hpd *hpd) 271 struct radeon_hpd *hpd)
208{ 272{
273 struct radeon_device *rdev = dev->dev_private;
209 274
210 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ 275 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
211 if ((dev->pdev->device == 0x791e) && 276 if ((dev->pdev->device == 0x791e) &&
@@ -308,13 +373,22 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
308 } 373 }
309 } 374 }
310 375
311 /* Acer laptop reports DVI-D as DVI-I */ 376 /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
312 if ((dev->pdev->device == 0x95c4) && 377 if ((dev->pdev->device == 0x95c4) &&
313 (dev->pdev->subsystem_vendor == 0x1025) && 378 (dev->pdev->subsystem_vendor == 0x1025) &&
314 (dev->pdev->subsystem_device == 0x013c)) { 379 (dev->pdev->subsystem_device == 0x013c)) {
380 struct radeon_gpio_rec gpio;
381
315 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && 382 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
316 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) 383 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
384 gpio = radeon_lookup_gpio(rdev, 6);
385 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
317 *connector_type = DRM_MODE_CONNECTOR_DVID; 386 *connector_type = DRM_MODE_CONNECTOR_DVID;
387 } else if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
388 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
389 gpio = radeon_lookup_gpio(rdev, 7);
390 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
391 }
318 } 392 }
319 393
320 /* XFX Pine Group device rv730 reports no VGA DDC lines 394 /* XFX Pine Group device rv730 reports no VGA DDC lines
@@ -399,13 +473,14 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
399 u16 size, data_offset; 473 u16 size, data_offset;
400 u8 frev, crev; 474 u8 frev, crev;
401 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 475 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
476 ATOM_OBJECT_TABLE *router_obj;
402 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 477 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
403 ATOM_OBJECT_HEADER *obj_header; 478 ATOM_OBJECT_HEADER *obj_header;
404 int i, j, path_size, device_support; 479 int i, j, k, path_size, device_support;
405 int connector_type; 480 int connector_type;
406 u16 igp_lane_info, conn_id, connector_object_id; 481 u16 igp_lane_info, conn_id, connector_object_id;
407 bool linkb;
408 struct radeon_i2c_bus_rec ddc_bus; 482 struct radeon_i2c_bus_rec ddc_bus;
483 struct radeon_router router;
409 struct radeon_gpio_rec gpio; 484 struct radeon_gpio_rec gpio;
410 struct radeon_hpd hpd; 485 struct radeon_hpd hpd;
411 486
@@ -415,6 +490,8 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
415 if (crev < 2) 490 if (crev < 2)
416 return false; 491 return false;
417 492
493 router.valid = false;
494
418 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 495 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
419 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 496 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
420 (ctx->bios + data_offset + 497 (ctx->bios + data_offset +
@@ -422,6 +499,9 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
422 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 499 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
423 (ctx->bios + data_offset + 500 (ctx->bios + data_offset +
424 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 501 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
502 router_obj = (ATOM_OBJECT_TABLE *)
503 (ctx->bios + data_offset +
504 le16_to_cpu(obj_header->usRouterObjectTableOffset));
425 device_support = le16_to_cpu(obj_header->usDeviceSupport); 505 device_support = le16_to_cpu(obj_header->usDeviceSupport);
426 506
427 path_size = 0; 507 path_size = 0;
@@ -431,7 +511,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
431 addr += path_size; 511 addr += path_size;
432 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 512 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
433 path_size += le16_to_cpu(path->usSize); 513 path_size += le16_to_cpu(path->usSize);
434 linkb = false; 514
435 if (device_support & le16_to_cpu(path->usDeviceTag)) { 515 if (device_support & le16_to_cpu(path->usDeviceTag)) {
436 uint8_t con_obj_id, con_obj_num, con_obj_type; 516 uint8_t con_obj_id, con_obj_num, con_obj_type;
437 517
@@ -508,33 +588,83 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
508 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 588 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
509 continue; 589 continue;
510 590
511 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); 591 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
512 j++) { 592 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
513 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
514 593
515 enc_obj_id = 594 grph_obj_id =
516 (le16_to_cpu(path->usGraphicObjIds[j]) & 595 (le16_to_cpu(path->usGraphicObjIds[j]) &
517 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 596 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
518 enc_obj_num = 597 grph_obj_num =
519 (le16_to_cpu(path->usGraphicObjIds[j]) & 598 (le16_to_cpu(path->usGraphicObjIds[j]) &
520 ENUM_ID_MASK) >> ENUM_ID_SHIFT; 599 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
521 enc_obj_type = 600 grph_obj_type =
522 (le16_to_cpu(path->usGraphicObjIds[j]) & 601 (le16_to_cpu(path->usGraphicObjIds[j]) &
523 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 602 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
524 603
525 /* FIXME: add support for router objects */ 604 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
526 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 605 u16 encoder_obj = le16_to_cpu(path->usGraphicObjIds[j]);
527 if (enc_obj_num == 2)
528 linkb = true;
529 else
530 linkb = false;
531 606
532 radeon_add_atom_encoder(dev, 607 radeon_add_atom_encoder(dev,
533 enc_obj_id, 608 encoder_obj,
534 le16_to_cpu 609 le16_to_cpu
535 (path-> 610 (path->
536 usDeviceTag)); 611 usDeviceTag));
537 612
613 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
614 router.valid = false;
615 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
616 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[j].usObjectID);
617 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
618 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
619 (ctx->bios + data_offset +
620 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
621 ATOM_I2C_RECORD *i2c_record;
622 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
623 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
624 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
625 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
626 (ctx->bios + data_offset +
627 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
628 int enum_id;
629
630 router.router_id = router_obj_id;
631 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
632 enum_id++) {
633 if (le16_to_cpu(path->usConnObjectId) ==
634 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
635 break;
636 }
637
638 while (record->ucRecordType > 0 &&
639 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
640 switch (record->ucRecordType) {
641 case ATOM_I2C_RECORD_TYPE:
642 i2c_record =
643 (ATOM_I2C_RECORD *)
644 record;
645 i2c_config =
646 (ATOM_I2C_ID_CONFIG_ACCESS *)
647 &i2c_record->sucI2cId;
648 router.i2c_info =
649 radeon_lookup_i2c_gpio(rdev,
650 i2c_config->
651 ucAccess);
652 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
653 break;
654 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
655 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
656 record;
657 router.valid = true;
658 router.mux_type = ddc_path->ucMuxType;
659 router.mux_control_pin = ddc_path->ucMuxControlPin;
660 router.mux_state = ddc_path->ucMuxState[enum_id];
661 break;
662 }
663 record = (ATOM_COMMON_RECORD_HEADER *)
664 ((char *)record + record->ucRecordSize);
665 }
666 }
667 }
538 } 668 }
539 } 669 }
540 670
@@ -612,9 +742,10 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
612 le16_to_cpu(path-> 742 le16_to_cpu(path->
613 usDeviceTag), 743 usDeviceTag),
614 connector_type, &ddc_bus, 744 connector_type, &ddc_bus,
615 linkb, igp_lane_info, 745 igp_lane_info,
616 connector_object_id, 746 connector_object_id,
617 &hpd); 747 &hpd,
748 &router);
618 749
619 } 750 }
620 } 751 }
@@ -691,6 +822,9 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
691 int i, j, max_device; 822 int i, j, max_device;
692 struct bios_connector *bios_connectors; 823 struct bios_connector *bios_connectors;
693 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; 824 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
825 struct radeon_router router;
826
827 router.valid = false;
694 828
695 bios_connectors = kzalloc(bc_size, GFP_KERNEL); 829 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
696 if (!bios_connectors) 830 if (!bios_connectors)
@@ -797,13 +931,13 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
797 931
798 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) 932 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
799 radeon_add_atom_encoder(dev, 933 radeon_add_atom_encoder(dev,
800 radeon_get_encoder_id(dev, 934 radeon_get_encoder_enum(dev,
801 (1 << i), 935 (1 << i),
802 dac), 936 dac),
803 (1 << i)); 937 (1 << i));
804 else 938 else
805 radeon_add_legacy_encoder(dev, 939 radeon_add_legacy_encoder(dev,
806 radeon_get_encoder_id(dev, 940 radeon_get_encoder_enum(dev,
807 (1 << i), 941 (1 << i),
808 dac), 942 dac),
809 (1 << i)); 943 (1 << i));
@@ -860,9 +994,10 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
860 bios_connectors[i]. 994 bios_connectors[i].
861 connector_type, 995 connector_type,
862 &bios_connectors[i].ddc_bus, 996 &bios_connectors[i].ddc_bus,
863 false, 0, 997 0,
864 connector_object_id, 998 connector_object_id,
865 &bios_connectors[i].hpd); 999 &bios_connectors[i].hpd,
1000 &router);
866 } 1001 }
867 } 1002 }
868 1003
@@ -1046,7 +1181,7 @@ bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1046 return true; 1181 return true;
1047 break; 1182 break;
1048 case 2: 1183 case 2:
1049 if (igp_info->info_2.ucMemoryType & 0x0f) 1184 if (igp_info->info_2.ulBootUpSidePortClock)
1050 return true; 1185 return true;
1051 break; 1186 break;
1052 default: 1187 default:
@@ -1168,6 +1303,7 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1168 union lvds_info *lvds_info; 1303 union lvds_info *lvds_info;
1169 uint8_t frev, crev; 1304 uint8_t frev, crev;
1170 struct radeon_encoder_atom_dig *lvds = NULL; 1305 struct radeon_encoder_atom_dig *lvds = NULL;
1306 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1171 1307
1172 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1308 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1173 &frev, &crev, &data_offset)) { 1309 &frev, &crev, &data_offset)) {
@@ -1231,6 +1367,12 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1231 } 1367 }
1232 1368
1233 encoder->native_mode = lvds->native_mode; 1369 encoder->native_mode = lvds->native_mode;
1370
1371 if (encoder_enum == 2)
1372 lvds->linkb = true;
1373 else
1374 lvds->linkb = false;
1375
1234 } 1376 }
1235 return lvds; 1377 return lvds;
1236} 1378}
@@ -1521,7 +1663,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1521 thermal_controller_names[power_info->info.ucOverdriveThermalController], 1663 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1522 power_info->info.ucOverdriveControllerAddress >> 1); 1664 power_info->info.ucOverdriveControllerAddress >> 1);
1523 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); 1665 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1524 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal"); 1666 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1525 if (rdev->pm.i2c_bus) { 1667 if (rdev->pm.i2c_bus) {
1526 struct i2c_board_info info = { }; 1668 struct i2c_board_info info = { };
1527 const char *name = thermal_controller_names[power_info->info. 1669 const char *name = thermal_controller_names[power_info->info.
@@ -1814,7 +1956,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1814 (controller->ucFanParameters & 1956 (controller->ucFanParameters &
1815 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 1957 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1816 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); 1958 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
1817 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal"); 1959 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1818 if (rdev->pm.i2c_bus) { 1960 if (rdev->pm.i2c_bus) {
1819 struct i2c_board_info info = { }; 1961 struct i2c_board_info info = { };
1820 const char *name = pp_lib_thermal_controller_names[controller->ucType]; 1962 const char *name = pp_lib_thermal_controller_names[controller->ucType];
@@ -1927,6 +2069,11 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1927 rdev->pm.power_state[state_index].type = 2069 rdev->pm.power_state[state_index].type =
1928 POWER_STATE_TYPE_PERFORMANCE; 2070 POWER_STATE_TYPE_PERFORMANCE;
1929 break; 2071 break;
2072 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2073 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2074 rdev->pm.power_state[state_index].type =
2075 POWER_STATE_TYPE_PERFORMANCE;
2076 break;
1930 } 2077 }
1931 rdev->pm.power_state[state_index].flags = 0; 2078 rdev->pm.power_state[state_index].flags = 0;
1932 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) 2079 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index f64936cc4dd9..14448a740ba6 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -91,6 +91,85 @@ uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
91 return mclk; 91 return mclk;
92} 92}
93 93
94#ifdef CONFIG_OF
95/*
96 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
97 * tree. Hopefully, ATI OF driver is kind enough to fill these
98 */
99static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
100{
101 struct radeon_device *rdev = dev->dev_private;
102 struct device_node *dp = rdev->pdev->dev.of_node;
103 const u32 *val;
104 struct radeon_pll *p1pll = &rdev->clock.p1pll;
105 struct radeon_pll *p2pll = &rdev->clock.p2pll;
106 struct radeon_pll *spll = &rdev->clock.spll;
107 struct radeon_pll *mpll = &rdev->clock.mpll;
108
109 if (dp == NULL)
110 return false;
111 val = of_get_property(dp, "ATY,RefCLK", NULL);
112 if (!val || !*val) {
113 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
114 return false;
115 }
116 p1pll->reference_freq = p2pll->reference_freq = (*val) / 10;
117 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
118 if (p1pll->reference_div < 2)
119 p1pll->reference_div = 12;
120 p2pll->reference_div = p1pll->reference_div;
121
122 /* These aren't in the device-tree */
123 if (rdev->family >= CHIP_R420) {
124 p1pll->pll_in_min = 100;
125 p1pll->pll_in_max = 1350;
126 p1pll->pll_out_min = 20000;
127 p1pll->pll_out_max = 50000;
128 p2pll->pll_in_min = 100;
129 p2pll->pll_in_max = 1350;
130 p2pll->pll_out_min = 20000;
131 p2pll->pll_out_max = 50000;
132 } else {
133 p1pll->pll_in_min = 40;
134 p1pll->pll_in_max = 500;
135 p1pll->pll_out_min = 12500;
136 p1pll->pll_out_max = 35000;
137 p2pll->pll_in_min = 40;
138 p2pll->pll_in_max = 500;
139 p2pll->pll_out_min = 12500;
140 p2pll->pll_out_max = 35000;
141 }
142
143 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
144 spll->reference_div = mpll->reference_div =
145 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
146 RADEON_M_SPLL_REF_DIV_MASK;
147
148 val = of_get_property(dp, "ATY,SCLK", NULL);
149 if (val && *val)
150 rdev->clock.default_sclk = (*val) / 10;
151 else
152 rdev->clock.default_sclk =
153 radeon_legacy_get_engine_clock(rdev);
154
155 val = of_get_property(dp, "ATY,MCLK", NULL);
156 if (val && *val)
157 rdev->clock.default_mclk = (*val) / 10;
158 else
159 rdev->clock.default_mclk =
160 radeon_legacy_get_memory_clock(rdev);
161
162 DRM_INFO("Using device-tree clock info\n");
163
164 return true;
165}
166#else
167static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
168{
169 return false;
170}
171#endif /* CONFIG_OF */
172
94void radeon_get_clock_info(struct drm_device *dev) 173void radeon_get_clock_info(struct drm_device *dev)
95{ 174{
96 struct radeon_device *rdev = dev->dev_private; 175 struct radeon_device *rdev = dev->dev_private;
@@ -105,6 +184,8 @@ void radeon_get_clock_info(struct drm_device *dev)
105 ret = radeon_atom_get_clock_info(dev); 184 ret = radeon_atom_get_clock_info(dev);
106 else 185 else
107 ret = radeon_combios_get_clock_info(dev); 186 ret = radeon_combios_get_clock_info(dev);
187 if (!ret)
188 ret = radeon_read_clocks_OF(dev);
108 189
109 if (ret) { 190 if (ret) {
110 if (p1pll->reference_div < 2) { 191 if (p1pll->reference_div < 2) {
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 5e1474cde4b4..bd74e428bd14 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -39,8 +39,8 @@
39 39
40/* from radeon_encoder.c */ 40/* from radeon_encoder.c */
41extern uint32_t 41extern uint32_t
42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, 42radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac); 43 uint8_t dac);
44extern void radeon_link_encoder_connector(struct drm_device *dev); 44extern void radeon_link_encoder_connector(struct drm_device *dev);
45 45
46/* from radeon_connector.c */ 46/* from radeon_connector.c */
@@ -55,7 +55,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
55 55
56/* from radeon_legacy_encoder.c */ 56/* from radeon_legacy_encoder.c */
57extern void 57extern void
58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, 58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
59 uint32_t supported_device); 59 uint32_t supported_device);
60 60
61/* old legacy ATI BIOS routines */ 61/* old legacy ATI BIOS routines */
@@ -480,9 +480,66 @@ radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
480} 480}
481 481
482static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 482static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
483 int ddc_line) 483 enum radeon_combios_ddc ddc,
484 u32 clk_mask,
485 u32 data_mask)
484{ 486{
485 struct radeon_i2c_bus_rec i2c; 487 struct radeon_i2c_bus_rec i2c;
488 int ddc_line = 0;
489
490 /* ddc id = mask reg
491 * DDC_NONE_DETECTED = none
492 * DDC_DVI = RADEON_GPIO_DVI_DDC
493 * DDC_VGA = RADEON_GPIO_VGA_DDC
494 * DDC_LCD = RADEON_GPIOPAD_MASK
495 * DDC_GPIO = RADEON_MDGPIO_MASK
496 * r1xx/r2xx
497 * DDC_MONID = RADEON_GPIO_MONID
498 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
499 * r3xx
500 * DDC_MONID = RADEON_GPIO_MONID
501 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
502 * rs3xx/rs4xx
503 * DDC_MONID = RADEON_GPIOPAD_MASK
504 * DDC_CRT2 = RADEON_GPIO_MONID
505 */
506 switch (ddc) {
507 case DDC_NONE_DETECTED:
508 default:
509 ddc_line = 0;
510 break;
511 case DDC_DVI:
512 ddc_line = RADEON_GPIO_DVI_DDC;
513 break;
514 case DDC_VGA:
515 ddc_line = RADEON_GPIO_VGA_DDC;
516 break;
517 case DDC_LCD:
518 ddc_line = RADEON_GPIOPAD_MASK;
519 break;
520 case DDC_GPIO:
521 ddc_line = RADEON_MDGPIO_MASK;
522 break;
523 case DDC_MONID:
524 if (rdev->family == CHIP_RS300 ||
525 rdev->family == CHIP_RS400 ||
526 rdev->family == CHIP_RS480)
527 ddc_line = RADEON_GPIOPAD_MASK;
528 else
529 ddc_line = RADEON_GPIO_MONID;
530 break;
531 case DDC_CRT2:
532 if (rdev->family == CHIP_RS300 ||
533 rdev->family == CHIP_RS400 ||
534 rdev->family == CHIP_RS480)
535 ddc_line = RADEON_GPIO_MONID;
536 else if (rdev->family >= CHIP_R300) {
537 ddc_line = RADEON_GPIO_DVI_DDC;
538 ddc = DDC_DVI;
539 } else
540 ddc_line = RADEON_GPIO_CRT2_DDC;
541 break;
542 }
486 543
487 if (ddc_line == RADEON_GPIOPAD_MASK) { 544 if (ddc_line == RADEON_GPIOPAD_MASK) {
488 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 545 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
@@ -503,15 +560,6 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
503 i2c.y_clk_reg = RADEON_MDGPIO_Y; 560 i2c.y_clk_reg = RADEON_MDGPIO_Y;
504 i2c.y_data_reg = RADEON_MDGPIO_Y; 561 i2c.y_data_reg = RADEON_MDGPIO_Y;
505 } else { 562 } else {
506 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
507 i2c.mask_data_mask = RADEON_GPIO_EN_0;
508 i2c.a_clk_mask = RADEON_GPIO_A_1;
509 i2c.a_data_mask = RADEON_GPIO_A_0;
510 i2c.en_clk_mask = RADEON_GPIO_EN_1;
511 i2c.en_data_mask = RADEON_GPIO_EN_0;
512 i2c.y_clk_mask = RADEON_GPIO_Y_1;
513 i2c.y_data_mask = RADEON_GPIO_Y_0;
514
515 i2c.mask_clk_reg = ddc_line; 563 i2c.mask_clk_reg = ddc_line;
516 i2c.mask_data_reg = ddc_line; 564 i2c.mask_data_reg = ddc_line;
517 i2c.a_clk_reg = ddc_line; 565 i2c.a_clk_reg = ddc_line;
@@ -522,6 +570,26 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
522 i2c.y_data_reg = ddc_line; 570 i2c.y_data_reg = ddc_line;
523 } 571 }
524 572
573 if (clk_mask && data_mask) {
574 i2c.mask_clk_mask = clk_mask;
575 i2c.mask_data_mask = data_mask;
576 i2c.a_clk_mask = clk_mask;
577 i2c.a_data_mask = data_mask;
578 i2c.en_clk_mask = clk_mask;
579 i2c.en_data_mask = data_mask;
580 i2c.y_clk_mask = clk_mask;
581 i2c.y_data_mask = data_mask;
582 } else {
583 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
584 i2c.mask_data_mask = RADEON_GPIO_EN_0;
585 i2c.a_clk_mask = RADEON_GPIO_A_1;
586 i2c.a_data_mask = RADEON_GPIO_A_0;
587 i2c.en_clk_mask = RADEON_GPIO_EN_1;
588 i2c.en_data_mask = RADEON_GPIO_EN_0;
589 i2c.y_clk_mask = RADEON_GPIO_Y_1;
590 i2c.y_data_mask = RADEON_GPIO_Y_0;
591 }
592
525 switch (rdev->family) { 593 switch (rdev->family) {
526 case CHIP_R100: 594 case CHIP_R100:
527 case CHIP_RV100: 595 case CHIP_RV100:
@@ -599,7 +667,8 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
599 break; 667 break;
600 } 668 }
601 i2c.mm_i2c = false; 669 i2c.mm_i2c = false;
602 i2c.i2c_id = 0; 670
671 i2c.i2c_id = ddc;
603 i2c.hpd = RADEON_HPD_NONE; 672 i2c.hpd = RADEON_HPD_NONE;
604 673
605 if (ddc_line) 674 if (ddc_line)
@@ -610,6 +679,62 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
610 return i2c; 679 return i2c;
611} 680}
612 681
682void radeon_combios_i2c_init(struct radeon_device *rdev)
683{
684 struct drm_device *dev = rdev->ddev;
685 struct radeon_i2c_bus_rec i2c;
686
687
688 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
689 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
690
691 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
692 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
693
694 i2c.valid = true;
695 i2c.hw_capable = true;
696 i2c.mm_i2c = true;
697 i2c.i2c_id = 0xa0;
698 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
699
700 if (rdev->family == CHIP_RS300 ||
701 rdev->family == CHIP_RS400 ||
702 rdev->family == CHIP_RS480) {
703 u16 offset;
704 u8 id, blocks, clk, data;
705 int i;
706
707 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
708 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
709
710 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
711 if (offset) {
712 blocks = RBIOS8(offset + 2);
713 for (i = 0; i < blocks; i++) {
714 id = RBIOS8(offset + 3 + (i * 5) + 0);
715 if (id == 136) {
716 clk = RBIOS8(offset + 3 + (i * 5) + 3);
717 data = RBIOS8(offset + 3 + (i * 5) + 4);
718 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
719 clk, data);
720 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
721 break;
722 }
723 }
724 }
725
726 } else if (rdev->family >= CHIP_R300) {
727 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
728 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
729 } else {
730 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
731 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
732
733 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
734 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
735 }
736}
737
613bool radeon_combios_get_clock_info(struct drm_device *dev) 738bool radeon_combios_get_clock_info(struct drm_device *dev)
614{ 739{
615 struct radeon_device *rdev = dev->dev_private; 740 struct radeon_device *rdev = dev->dev_private;
@@ -1247,8 +1372,8 @@ bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1247 struct radeon_i2c_bus_rec i2c_bus; 1372 struct radeon_i2c_bus_rec i2c_bus;
1248 1373
1249 /* default for macs */ 1374 /* default for macs */
1250 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1375 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1251 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1376 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1252 1377
1253 /* XXX some macs have duallink chips */ 1378 /* XXX some macs have duallink chips */
1254 switch (rdev->mode_info.connector_table) { 1379 switch (rdev->mode_info.connector_table) {
@@ -1269,47 +1394,16 @@ bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder
1269 struct drm_device *dev = encoder->base.dev; 1394 struct drm_device *dev = encoder->base.dev;
1270 struct radeon_device *rdev = dev->dev_private; 1395 struct radeon_device *rdev = dev->dev_private;
1271 uint16_t offset; 1396 uint16_t offset;
1272 uint8_t ver, id, blocks, clk, data; 1397 uint8_t ver;
1273 int i;
1274 enum radeon_combios_ddc gpio; 1398 enum radeon_combios_ddc gpio;
1275 struct radeon_i2c_bus_rec i2c_bus; 1399 struct radeon_i2c_bus_rec i2c_bus;
1276 1400
1277 tmds->i2c_bus = NULL; 1401 tmds->i2c_bus = NULL;
1278 if (rdev->flags & RADEON_IS_IGP) { 1402 if (rdev->flags & RADEON_IS_IGP) {
1279 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 1403 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1280 if (offset) { 1404 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1281 ver = RBIOS8(offset); 1405 tmds->dvo_chip = DVO_SIL164;
1282 DRM_INFO("GPIO Table revision: %d\n", ver); 1406 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1283 blocks = RBIOS8(offset + 2);
1284 for (i = 0; i < blocks; i++) {
1285 id = RBIOS8(offset + 3 + (i * 5) + 0);
1286 if (id == 136) {
1287 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1288 data = RBIOS8(offset + 3 + (i * 5) + 4);
1289 i2c_bus.valid = true;
1290 i2c_bus.mask_clk_mask = (1 << clk);
1291 i2c_bus.mask_data_mask = (1 << data);
1292 i2c_bus.a_clk_mask = (1 << clk);
1293 i2c_bus.a_data_mask = (1 << data);
1294 i2c_bus.en_clk_mask = (1 << clk);
1295 i2c_bus.en_data_mask = (1 << data);
1296 i2c_bus.y_clk_mask = (1 << clk);
1297 i2c_bus.y_data_mask = (1 << data);
1298 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1299 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1300 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1301 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1302 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1303 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1304 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1305 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1306 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1307 tmds->dvo_chip = DVO_SIL164;
1308 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1309 break;
1310 }
1311 }
1312 }
1313 } else { 1407 } else {
1314 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1408 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1315 if (offset) { 1409 if (offset) {
@@ -1318,37 +1412,15 @@ bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder
1318 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1412 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1319 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1413 tmds->slave_addr >>= 1; /* 7 bit addressing */
1320 gpio = RBIOS8(offset + 4 + 3); 1414 gpio = RBIOS8(offset + 4 + 3);
1321 switch (gpio) { 1415 if (gpio == DDC_LCD) {
1322 case DDC_MONID: 1416 /* MM i2c */
1323 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1324 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1325 break;
1326 case DDC_DVI:
1327 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1328 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1329 break;
1330 case DDC_VGA:
1331 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1332 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1333 break;
1334 case DDC_CRT2:
1335 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1336 if (rdev->family >= CHIP_R300)
1337 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1338 else
1339 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1340 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1341 break;
1342 case DDC_LCD: /* MM i2c */
1343 i2c_bus.valid = true; 1417 i2c_bus.valid = true;
1344 i2c_bus.hw_capable = true; 1418 i2c_bus.hw_capable = true;
1345 i2c_bus.mm_i2c = true; 1419 i2c_bus.mm_i2c = true;
1346 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1420 i2c_bus.i2c_id = 0xa0;
1347 break; 1421 } else
1348 default: 1422 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1349 DRM_ERROR("Unsupported gpio %d\n", gpio); 1423 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1350 break;
1351 }
1352 } 1424 }
1353 } 1425 }
1354 1426
@@ -1430,10 +1502,10 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1430 /* these are the most common settings */ 1502 /* these are the most common settings */
1431 if (rdev->flags & RADEON_SINGLE_CRTC) { 1503 if (rdev->flags & RADEON_SINGLE_CRTC) {
1432 /* VGA - primary dac */ 1504 /* VGA - primary dac */
1433 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1505 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1434 hpd.hpd = RADEON_HPD_NONE; 1506 hpd.hpd = RADEON_HPD_NONE;
1435 radeon_add_legacy_encoder(dev, 1507 radeon_add_legacy_encoder(dev,
1436 radeon_get_encoder_id(dev, 1508 radeon_get_encoder_enum(dev,
1437 ATOM_DEVICE_CRT1_SUPPORT, 1509 ATOM_DEVICE_CRT1_SUPPORT,
1438 1), 1510 1),
1439 ATOM_DEVICE_CRT1_SUPPORT); 1511 ATOM_DEVICE_CRT1_SUPPORT);
@@ -1445,10 +1517,10 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1445 &hpd); 1517 &hpd);
1446 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1518 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1447 /* LVDS */ 1519 /* LVDS */
1448 ddc_i2c = combios_setup_i2c_bus(rdev, 0); 1520 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1449 hpd.hpd = RADEON_HPD_NONE; 1521 hpd.hpd = RADEON_HPD_NONE;
1450 radeon_add_legacy_encoder(dev, 1522 radeon_add_legacy_encoder(dev,
1451 radeon_get_encoder_id(dev, 1523 radeon_get_encoder_enum(dev,
1452 ATOM_DEVICE_LCD1_SUPPORT, 1524 ATOM_DEVICE_LCD1_SUPPORT,
1453 0), 1525 0),
1454 ATOM_DEVICE_LCD1_SUPPORT); 1526 ATOM_DEVICE_LCD1_SUPPORT);
@@ -1460,10 +1532,10 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1460 &hpd); 1532 &hpd);
1461 1533
1462 /* VGA - primary dac */ 1534 /* VGA - primary dac */
1463 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1535 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1464 hpd.hpd = RADEON_HPD_NONE; 1536 hpd.hpd = RADEON_HPD_NONE;
1465 radeon_add_legacy_encoder(dev, 1537 radeon_add_legacy_encoder(dev,
1466 radeon_get_encoder_id(dev, 1538 radeon_get_encoder_enum(dev,
1467 ATOM_DEVICE_CRT1_SUPPORT, 1539 ATOM_DEVICE_CRT1_SUPPORT,
1468 1), 1540 1),
1469 ATOM_DEVICE_CRT1_SUPPORT); 1541 ATOM_DEVICE_CRT1_SUPPORT);
@@ -1475,15 +1547,15 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1475 &hpd); 1547 &hpd);
1476 } else { 1548 } else {
1477 /* DVI-I - tv dac, int tmds */ 1549 /* DVI-I - tv dac, int tmds */
1478 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1550 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1479 hpd.hpd = RADEON_HPD_1; 1551 hpd.hpd = RADEON_HPD_1;
1480 radeon_add_legacy_encoder(dev, 1552 radeon_add_legacy_encoder(dev,
1481 radeon_get_encoder_id(dev, 1553 radeon_get_encoder_enum(dev,
1482 ATOM_DEVICE_DFP1_SUPPORT, 1554 ATOM_DEVICE_DFP1_SUPPORT,
1483 0), 1555 0),
1484 ATOM_DEVICE_DFP1_SUPPORT); 1556 ATOM_DEVICE_DFP1_SUPPORT);
1485 radeon_add_legacy_encoder(dev, 1557 radeon_add_legacy_encoder(dev,
1486 radeon_get_encoder_id(dev, 1558 radeon_get_encoder_enum(dev,
1487 ATOM_DEVICE_CRT2_SUPPORT, 1559 ATOM_DEVICE_CRT2_SUPPORT,
1488 2), 1560 2),
1489 ATOM_DEVICE_CRT2_SUPPORT); 1561 ATOM_DEVICE_CRT2_SUPPORT);
@@ -1496,10 +1568,10 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1496 &hpd); 1568 &hpd);
1497 1569
1498 /* VGA - primary dac */ 1570 /* VGA - primary dac */
1499 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1571 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1500 hpd.hpd = RADEON_HPD_NONE; 1572 hpd.hpd = RADEON_HPD_NONE;
1501 radeon_add_legacy_encoder(dev, 1573 radeon_add_legacy_encoder(dev,
1502 radeon_get_encoder_id(dev, 1574 radeon_get_encoder_enum(dev,
1503 ATOM_DEVICE_CRT1_SUPPORT, 1575 ATOM_DEVICE_CRT1_SUPPORT,
1504 1), 1576 1),
1505 ATOM_DEVICE_CRT1_SUPPORT); 1577 ATOM_DEVICE_CRT1_SUPPORT);
@@ -1516,7 +1588,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1516 ddc_i2c.valid = false; 1588 ddc_i2c.valid = false;
1517 hpd.hpd = RADEON_HPD_NONE; 1589 hpd.hpd = RADEON_HPD_NONE;
1518 radeon_add_legacy_encoder(dev, 1590 radeon_add_legacy_encoder(dev,
1519 radeon_get_encoder_id(dev, 1591 radeon_get_encoder_enum(dev,
1520 ATOM_DEVICE_TV1_SUPPORT, 1592 ATOM_DEVICE_TV1_SUPPORT,
1521 2), 1593 2),
1522 ATOM_DEVICE_TV1_SUPPORT); 1594 ATOM_DEVICE_TV1_SUPPORT);
@@ -1532,10 +1604,10 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1532 DRM_INFO("Connector Table: %d (ibook)\n", 1604 DRM_INFO("Connector Table: %d (ibook)\n",
1533 rdev->mode_info.connector_table); 1605 rdev->mode_info.connector_table);
1534 /* LVDS */ 1606 /* LVDS */
1535 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1607 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1536 hpd.hpd = RADEON_HPD_NONE; 1608 hpd.hpd = RADEON_HPD_NONE;
1537 radeon_add_legacy_encoder(dev, 1609 radeon_add_legacy_encoder(dev,
1538 radeon_get_encoder_id(dev, 1610 radeon_get_encoder_enum(dev,
1539 ATOM_DEVICE_LCD1_SUPPORT, 1611 ATOM_DEVICE_LCD1_SUPPORT,
1540 0), 1612 0),
1541 ATOM_DEVICE_LCD1_SUPPORT); 1613 ATOM_DEVICE_LCD1_SUPPORT);
@@ -1544,10 +1616,10 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1544 CONNECTOR_OBJECT_ID_LVDS, 1616 CONNECTOR_OBJECT_ID_LVDS,
1545 &hpd); 1617 &hpd);
1546 /* VGA - TV DAC */ 1618 /* VGA - TV DAC */
1547 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1619 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1548 hpd.hpd = RADEON_HPD_NONE; 1620 hpd.hpd = RADEON_HPD_NONE;
1549 radeon_add_legacy_encoder(dev, 1621 radeon_add_legacy_encoder(dev,
1550 radeon_get_encoder_id(dev, 1622 radeon_get_encoder_enum(dev,
1551 ATOM_DEVICE_CRT2_SUPPORT, 1623 ATOM_DEVICE_CRT2_SUPPORT,
1552 2), 1624 2),
1553 ATOM_DEVICE_CRT2_SUPPORT); 1625 ATOM_DEVICE_CRT2_SUPPORT);
@@ -1559,7 +1631,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1559 ddc_i2c.valid = false; 1631 ddc_i2c.valid = false;
1560 hpd.hpd = RADEON_HPD_NONE; 1632 hpd.hpd = RADEON_HPD_NONE;
1561 radeon_add_legacy_encoder(dev, 1633 radeon_add_legacy_encoder(dev,
1562 radeon_get_encoder_id(dev, 1634 radeon_get_encoder_enum(dev,
1563 ATOM_DEVICE_TV1_SUPPORT, 1635 ATOM_DEVICE_TV1_SUPPORT,
1564 2), 1636 2),
1565 ATOM_DEVICE_TV1_SUPPORT); 1637 ATOM_DEVICE_TV1_SUPPORT);
@@ -1573,10 +1645,10 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1573 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1645 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1574 rdev->mode_info.connector_table); 1646 rdev->mode_info.connector_table);
1575 /* LVDS */ 1647 /* LVDS */
1576 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1648 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1577 hpd.hpd = RADEON_HPD_NONE; 1649 hpd.hpd = RADEON_HPD_NONE;
1578 radeon_add_legacy_encoder(dev, 1650 radeon_add_legacy_encoder(dev,
1579 radeon_get_encoder_id(dev, 1651 radeon_get_encoder_enum(dev,
1580 ATOM_DEVICE_LCD1_SUPPORT, 1652 ATOM_DEVICE_LCD1_SUPPORT,
1581 0), 1653 0),
1582 ATOM_DEVICE_LCD1_SUPPORT); 1654 ATOM_DEVICE_LCD1_SUPPORT);
@@ -1585,15 +1657,15 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1585 CONNECTOR_OBJECT_ID_LVDS, 1657 CONNECTOR_OBJECT_ID_LVDS,
1586 &hpd); 1658 &hpd);
1587 /* DVI-I - primary dac, ext tmds */ 1659 /* DVI-I - primary dac, ext tmds */
1588 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1660 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1589 hpd.hpd = RADEON_HPD_2; /* ??? */ 1661 hpd.hpd = RADEON_HPD_2; /* ??? */
1590 radeon_add_legacy_encoder(dev, 1662 radeon_add_legacy_encoder(dev,
1591 radeon_get_encoder_id(dev, 1663 radeon_get_encoder_enum(dev,
1592 ATOM_DEVICE_DFP2_SUPPORT, 1664 ATOM_DEVICE_DFP2_SUPPORT,
1593 0), 1665 0),
1594 ATOM_DEVICE_DFP2_SUPPORT); 1666 ATOM_DEVICE_DFP2_SUPPORT);
1595 radeon_add_legacy_encoder(dev, 1667 radeon_add_legacy_encoder(dev,
1596 radeon_get_encoder_id(dev, 1668 radeon_get_encoder_enum(dev,
1597 ATOM_DEVICE_CRT1_SUPPORT, 1669 ATOM_DEVICE_CRT1_SUPPORT,
1598 1), 1670 1),
1599 ATOM_DEVICE_CRT1_SUPPORT); 1671 ATOM_DEVICE_CRT1_SUPPORT);
@@ -1608,7 +1680,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1608 ddc_i2c.valid = false; 1680 ddc_i2c.valid = false;
1609 hpd.hpd = RADEON_HPD_NONE; 1681 hpd.hpd = RADEON_HPD_NONE;
1610 radeon_add_legacy_encoder(dev, 1682 radeon_add_legacy_encoder(dev,
1611 radeon_get_encoder_id(dev, 1683 radeon_get_encoder_enum(dev,
1612 ATOM_DEVICE_TV1_SUPPORT, 1684 ATOM_DEVICE_TV1_SUPPORT,
1613 2), 1685 2),
1614 ATOM_DEVICE_TV1_SUPPORT); 1686 ATOM_DEVICE_TV1_SUPPORT);
@@ -1622,10 +1694,10 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1622 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1694 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1623 rdev->mode_info.connector_table); 1695 rdev->mode_info.connector_table);
1624 /* LVDS */ 1696 /* LVDS */
1625 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1697 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1626 hpd.hpd = RADEON_HPD_NONE; 1698 hpd.hpd = RADEON_HPD_NONE;
1627 radeon_add_legacy_encoder(dev, 1699 radeon_add_legacy_encoder(dev,
1628 radeon_get_encoder_id(dev, 1700 radeon_get_encoder_enum(dev,
1629 ATOM_DEVICE_LCD1_SUPPORT, 1701 ATOM_DEVICE_LCD1_SUPPORT,
1630 0), 1702 0),
1631 ATOM_DEVICE_LCD1_SUPPORT); 1703 ATOM_DEVICE_LCD1_SUPPORT);
@@ -1634,15 +1706,15 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1634 CONNECTOR_OBJECT_ID_LVDS, 1706 CONNECTOR_OBJECT_ID_LVDS,
1635 &hpd); 1707 &hpd);
1636 /* DVI-I - primary dac, int tmds */ 1708 /* DVI-I - primary dac, int tmds */
1637 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1709 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1638 hpd.hpd = RADEON_HPD_1; /* ??? */ 1710 hpd.hpd = RADEON_HPD_1; /* ??? */
1639 radeon_add_legacy_encoder(dev, 1711 radeon_add_legacy_encoder(dev,
1640 radeon_get_encoder_id(dev, 1712 radeon_get_encoder_enum(dev,
1641 ATOM_DEVICE_DFP1_SUPPORT, 1713 ATOM_DEVICE_DFP1_SUPPORT,
1642 0), 1714 0),
1643 ATOM_DEVICE_DFP1_SUPPORT); 1715 ATOM_DEVICE_DFP1_SUPPORT);
1644 radeon_add_legacy_encoder(dev, 1716 radeon_add_legacy_encoder(dev,
1645 radeon_get_encoder_id(dev, 1717 radeon_get_encoder_enum(dev,
1646 ATOM_DEVICE_CRT1_SUPPORT, 1718 ATOM_DEVICE_CRT1_SUPPORT,
1647 1), 1719 1),
1648 ATOM_DEVICE_CRT1_SUPPORT); 1720 ATOM_DEVICE_CRT1_SUPPORT);
@@ -1656,7 +1728,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1656 ddc_i2c.valid = false; 1728 ddc_i2c.valid = false;
1657 hpd.hpd = RADEON_HPD_NONE; 1729 hpd.hpd = RADEON_HPD_NONE;
1658 radeon_add_legacy_encoder(dev, 1730 radeon_add_legacy_encoder(dev,
1659 radeon_get_encoder_id(dev, 1731 radeon_get_encoder_enum(dev,
1660 ATOM_DEVICE_TV1_SUPPORT, 1732 ATOM_DEVICE_TV1_SUPPORT,
1661 2), 1733 2),
1662 ATOM_DEVICE_TV1_SUPPORT); 1734 ATOM_DEVICE_TV1_SUPPORT);
@@ -1670,10 +1742,10 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1670 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1742 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1671 rdev->mode_info.connector_table); 1743 rdev->mode_info.connector_table);
1672 /* LVDS */ 1744 /* LVDS */
1673 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1745 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1674 hpd.hpd = RADEON_HPD_NONE; 1746 hpd.hpd = RADEON_HPD_NONE;
1675 radeon_add_legacy_encoder(dev, 1747 radeon_add_legacy_encoder(dev,
1676 radeon_get_encoder_id(dev, 1748 radeon_get_encoder_enum(dev,
1677 ATOM_DEVICE_LCD1_SUPPORT, 1749 ATOM_DEVICE_LCD1_SUPPORT,
1678 0), 1750 0),
1679 ATOM_DEVICE_LCD1_SUPPORT); 1751 ATOM_DEVICE_LCD1_SUPPORT);
@@ -1682,10 +1754,10 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1682 CONNECTOR_OBJECT_ID_LVDS, 1754 CONNECTOR_OBJECT_ID_LVDS,
1683 &hpd); 1755 &hpd);
1684 /* VGA - primary dac */ 1756 /* VGA - primary dac */
1685 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1757 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1686 hpd.hpd = RADEON_HPD_NONE; 1758 hpd.hpd = RADEON_HPD_NONE;
1687 radeon_add_legacy_encoder(dev, 1759 radeon_add_legacy_encoder(dev,
1688 radeon_get_encoder_id(dev, 1760 radeon_get_encoder_enum(dev,
1689 ATOM_DEVICE_CRT1_SUPPORT, 1761 ATOM_DEVICE_CRT1_SUPPORT,
1690 1), 1762 1),
1691 ATOM_DEVICE_CRT1_SUPPORT); 1763 ATOM_DEVICE_CRT1_SUPPORT);
@@ -1697,7 +1769,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1697 ddc_i2c.valid = false; 1769 ddc_i2c.valid = false;
1698 hpd.hpd = RADEON_HPD_NONE; 1770 hpd.hpd = RADEON_HPD_NONE;
1699 radeon_add_legacy_encoder(dev, 1771 radeon_add_legacy_encoder(dev,
1700 radeon_get_encoder_id(dev, 1772 radeon_get_encoder_enum(dev,
1701 ATOM_DEVICE_TV1_SUPPORT, 1773 ATOM_DEVICE_TV1_SUPPORT,
1702 2), 1774 2),
1703 ATOM_DEVICE_TV1_SUPPORT); 1775 ATOM_DEVICE_TV1_SUPPORT);
@@ -1711,15 +1783,15 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1711 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1783 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1712 rdev->mode_info.connector_table); 1784 rdev->mode_info.connector_table);
1713 /* DVI-I - tv dac, ext tmds */ 1785 /* DVI-I - tv dac, ext tmds */
1714 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1786 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1715 hpd.hpd = RADEON_HPD_2; /* ??? */ 1787 hpd.hpd = RADEON_HPD_2; /* ??? */
1716 radeon_add_legacy_encoder(dev, 1788 radeon_add_legacy_encoder(dev,
1717 radeon_get_encoder_id(dev, 1789 radeon_get_encoder_enum(dev,
1718 ATOM_DEVICE_DFP2_SUPPORT, 1790 ATOM_DEVICE_DFP2_SUPPORT,
1719 0), 1791 0),
1720 ATOM_DEVICE_DFP2_SUPPORT); 1792 ATOM_DEVICE_DFP2_SUPPORT);
1721 radeon_add_legacy_encoder(dev, 1793 radeon_add_legacy_encoder(dev,
1722 radeon_get_encoder_id(dev, 1794 radeon_get_encoder_enum(dev,
1723 ATOM_DEVICE_CRT2_SUPPORT, 1795 ATOM_DEVICE_CRT2_SUPPORT,
1724 2), 1796 2),
1725 ATOM_DEVICE_CRT2_SUPPORT); 1797 ATOM_DEVICE_CRT2_SUPPORT);
@@ -1734,7 +1806,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1734 ddc_i2c.valid = false; 1806 ddc_i2c.valid = false;
1735 hpd.hpd = RADEON_HPD_NONE; 1807 hpd.hpd = RADEON_HPD_NONE;
1736 radeon_add_legacy_encoder(dev, 1808 radeon_add_legacy_encoder(dev,
1737 radeon_get_encoder_id(dev, 1809 radeon_get_encoder_enum(dev,
1738 ATOM_DEVICE_TV1_SUPPORT, 1810 ATOM_DEVICE_TV1_SUPPORT,
1739 2), 1811 2),
1740 ATOM_DEVICE_TV1_SUPPORT); 1812 ATOM_DEVICE_TV1_SUPPORT);
@@ -1748,15 +1820,15 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1748 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1820 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1749 rdev->mode_info.connector_table); 1821 rdev->mode_info.connector_table);
1750 /* DVI-I - tv dac, int tmds */ 1822 /* DVI-I - tv dac, int tmds */
1751 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1823 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1752 hpd.hpd = RADEON_HPD_1; /* ??? */ 1824 hpd.hpd = RADEON_HPD_1; /* ??? */
1753 radeon_add_legacy_encoder(dev, 1825 radeon_add_legacy_encoder(dev,
1754 radeon_get_encoder_id(dev, 1826 radeon_get_encoder_enum(dev,
1755 ATOM_DEVICE_DFP1_SUPPORT, 1827 ATOM_DEVICE_DFP1_SUPPORT,
1756 0), 1828 0),
1757 ATOM_DEVICE_DFP1_SUPPORT); 1829 ATOM_DEVICE_DFP1_SUPPORT);
1758 radeon_add_legacy_encoder(dev, 1830 radeon_add_legacy_encoder(dev,
1759 radeon_get_encoder_id(dev, 1831 radeon_get_encoder_enum(dev,
1760 ATOM_DEVICE_CRT2_SUPPORT, 1832 ATOM_DEVICE_CRT2_SUPPORT,
1761 2), 1833 2),
1762 ATOM_DEVICE_CRT2_SUPPORT); 1834 ATOM_DEVICE_CRT2_SUPPORT);
@@ -1770,7 +1842,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1770 ddc_i2c.valid = false; 1842 ddc_i2c.valid = false;
1771 hpd.hpd = RADEON_HPD_NONE; 1843 hpd.hpd = RADEON_HPD_NONE;
1772 radeon_add_legacy_encoder(dev, 1844 radeon_add_legacy_encoder(dev,
1773 radeon_get_encoder_id(dev, 1845 radeon_get_encoder_enum(dev,
1774 ATOM_DEVICE_TV1_SUPPORT, 1846 ATOM_DEVICE_TV1_SUPPORT,
1775 2), 1847 2),
1776 ATOM_DEVICE_TV1_SUPPORT); 1848 ATOM_DEVICE_TV1_SUPPORT);
@@ -1784,10 +1856,10 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1784 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1856 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1785 rdev->mode_info.connector_table); 1857 rdev->mode_info.connector_table);
1786 /* DVI-D - int tmds */ 1858 /* DVI-D - int tmds */
1787 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1859 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1788 hpd.hpd = RADEON_HPD_1; /* ??? */ 1860 hpd.hpd = RADEON_HPD_1; /* ??? */
1789 radeon_add_legacy_encoder(dev, 1861 radeon_add_legacy_encoder(dev,
1790 radeon_get_encoder_id(dev, 1862 radeon_get_encoder_enum(dev,
1791 ATOM_DEVICE_DFP1_SUPPORT, 1863 ATOM_DEVICE_DFP1_SUPPORT,
1792 0), 1864 0),
1793 ATOM_DEVICE_DFP1_SUPPORT); 1865 ATOM_DEVICE_DFP1_SUPPORT);
@@ -1796,10 +1868,10 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1796 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1868 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1797 &hpd); 1869 &hpd);
1798 /* VGA - tv dac */ 1870 /* VGA - tv dac */
1799 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1871 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1800 hpd.hpd = RADEON_HPD_NONE; 1872 hpd.hpd = RADEON_HPD_NONE;
1801 radeon_add_legacy_encoder(dev, 1873 radeon_add_legacy_encoder(dev,
1802 radeon_get_encoder_id(dev, 1874 radeon_get_encoder_enum(dev,
1803 ATOM_DEVICE_CRT2_SUPPORT, 1875 ATOM_DEVICE_CRT2_SUPPORT,
1804 2), 1876 2),
1805 ATOM_DEVICE_CRT2_SUPPORT); 1877 ATOM_DEVICE_CRT2_SUPPORT);
@@ -1811,7 +1883,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1811 ddc_i2c.valid = false; 1883 ddc_i2c.valid = false;
1812 hpd.hpd = RADEON_HPD_NONE; 1884 hpd.hpd = RADEON_HPD_NONE;
1813 radeon_add_legacy_encoder(dev, 1885 radeon_add_legacy_encoder(dev,
1814 radeon_get_encoder_id(dev, 1886 radeon_get_encoder_enum(dev,
1815 ATOM_DEVICE_TV1_SUPPORT, 1887 ATOM_DEVICE_TV1_SUPPORT,
1816 2), 1888 2),
1817 ATOM_DEVICE_TV1_SUPPORT); 1889 ATOM_DEVICE_TV1_SUPPORT);
@@ -1825,10 +1897,10 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1825 DRM_INFO("Connector Table: %d (emac)\n", 1897 DRM_INFO("Connector Table: %d (emac)\n",
1826 rdev->mode_info.connector_table); 1898 rdev->mode_info.connector_table);
1827 /* VGA - primary dac */ 1899 /* VGA - primary dac */
1828 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1900 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1829 hpd.hpd = RADEON_HPD_NONE; 1901 hpd.hpd = RADEON_HPD_NONE;
1830 radeon_add_legacy_encoder(dev, 1902 radeon_add_legacy_encoder(dev,
1831 radeon_get_encoder_id(dev, 1903 radeon_get_encoder_enum(dev,
1832 ATOM_DEVICE_CRT1_SUPPORT, 1904 ATOM_DEVICE_CRT1_SUPPORT,
1833 1), 1905 1),
1834 ATOM_DEVICE_CRT1_SUPPORT); 1906 ATOM_DEVICE_CRT1_SUPPORT);
@@ -1837,10 +1909,10 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1837 CONNECTOR_OBJECT_ID_VGA, 1909 CONNECTOR_OBJECT_ID_VGA,
1838 &hpd); 1910 &hpd);
1839 /* VGA - tv dac */ 1911 /* VGA - tv dac */
1840 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1912 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1841 hpd.hpd = RADEON_HPD_NONE; 1913 hpd.hpd = RADEON_HPD_NONE;
1842 radeon_add_legacy_encoder(dev, 1914 radeon_add_legacy_encoder(dev,
1843 radeon_get_encoder_id(dev, 1915 radeon_get_encoder_enum(dev,
1844 ATOM_DEVICE_CRT2_SUPPORT, 1916 ATOM_DEVICE_CRT2_SUPPORT,
1845 2), 1917 2),
1846 ATOM_DEVICE_CRT2_SUPPORT); 1918 ATOM_DEVICE_CRT2_SUPPORT);
@@ -1852,7 +1924,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1852 ddc_i2c.valid = false; 1924 ddc_i2c.valid = false;
1853 hpd.hpd = RADEON_HPD_NONE; 1925 hpd.hpd = RADEON_HPD_NONE;
1854 radeon_add_legacy_encoder(dev, 1926 radeon_add_legacy_encoder(dev,
1855 radeon_get_encoder_id(dev, 1927 radeon_get_encoder_enum(dev,
1856 ATOM_DEVICE_TV1_SUPPORT, 1928 ATOM_DEVICE_TV1_SUPPORT,
1857 2), 1929 2),
1858 ATOM_DEVICE_TV1_SUPPORT); 1930 ATOM_DEVICE_TV1_SUPPORT);
@@ -1866,10 +1938,10 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1866 DRM_INFO("Connector Table: %d (rn50-power)\n", 1938 DRM_INFO("Connector Table: %d (rn50-power)\n",
1867 rdev->mode_info.connector_table); 1939 rdev->mode_info.connector_table);
1868 /* VGA - primary dac */ 1940 /* VGA - primary dac */
1869 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1941 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1870 hpd.hpd = RADEON_HPD_NONE; 1942 hpd.hpd = RADEON_HPD_NONE;
1871 radeon_add_legacy_encoder(dev, 1943 radeon_add_legacy_encoder(dev,
1872 radeon_get_encoder_id(dev, 1944 radeon_get_encoder_enum(dev,
1873 ATOM_DEVICE_CRT1_SUPPORT, 1945 ATOM_DEVICE_CRT1_SUPPORT,
1874 1), 1946 1),
1875 ATOM_DEVICE_CRT1_SUPPORT); 1947 ATOM_DEVICE_CRT1_SUPPORT);
@@ -1877,10 +1949,10 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1877 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1949 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1878 CONNECTOR_OBJECT_ID_VGA, 1950 CONNECTOR_OBJECT_ID_VGA,
1879 &hpd); 1951 &hpd);
1880 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1952 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1881 hpd.hpd = RADEON_HPD_NONE; 1953 hpd.hpd = RADEON_HPD_NONE;
1882 radeon_add_legacy_encoder(dev, 1954 radeon_add_legacy_encoder(dev,
1883 radeon_get_encoder_id(dev, 1955 radeon_get_encoder_enum(dev,
1884 ATOM_DEVICE_CRT2_SUPPORT, 1956 ATOM_DEVICE_CRT2_SUPPORT,
1885 2), 1957 2),
1886 ATOM_DEVICE_CRT2_SUPPORT); 1958 ATOM_DEVICE_CRT2_SUPPORT);
@@ -1907,31 +1979,6 @@ static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1907 struct radeon_i2c_bus_rec *ddc_i2c, 1979 struct radeon_i2c_bus_rec *ddc_i2c,
1908 struct radeon_hpd *hpd) 1980 struct radeon_hpd *hpd)
1909{ 1981{
1910 struct radeon_device *rdev = dev->dev_private;
1911
1912 /* XPRESS DDC quirks */
1913 if ((rdev->family == CHIP_RS400 ||
1914 rdev->family == CHIP_RS480) &&
1915 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1916 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1917 else if ((rdev->family == CHIP_RS400 ||
1918 rdev->family == CHIP_RS480) &&
1919 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1920 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
1921 ddc_i2c->mask_clk_mask = (0x20 << 8);
1922 ddc_i2c->mask_data_mask = 0x80;
1923 ddc_i2c->a_clk_mask = (0x20 << 8);
1924 ddc_i2c->a_data_mask = 0x80;
1925 ddc_i2c->en_clk_mask = (0x20 << 8);
1926 ddc_i2c->en_data_mask = 0x80;
1927 ddc_i2c->y_clk_mask = (0x20 << 8);
1928 ddc_i2c->y_data_mask = 0x80;
1929 }
1930
1931 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1932 if ((rdev->family >= CHIP_R300) &&
1933 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1934 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1935 1982
1936 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 1983 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1937 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 1984 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
@@ -2035,27 +2082,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2035 connector = (tmp >> 12) & 0xf; 2082 connector = (tmp >> 12) & 0xf;
2036 2083
2037 ddc_type = (tmp >> 8) & 0xf; 2084 ddc_type = (tmp >> 8) & 0xf;
2038 switch (ddc_type) { 2085 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2039 case DDC_MONID:
2040 ddc_i2c =
2041 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
2042 break;
2043 case DDC_DVI:
2044 ddc_i2c =
2045 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2046 break;
2047 case DDC_VGA:
2048 ddc_i2c =
2049 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2050 break;
2051 case DDC_CRT2:
2052 ddc_i2c =
2053 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
2054 break;
2055 default:
2056 ddc_i2c.valid = false;
2057 break;
2058 }
2059 2086
2060 switch (connector) { 2087 switch (connector) {
2061 case CONNECTOR_PROPRIETARY_LEGACY: 2088 case CONNECTOR_PROPRIETARY_LEGACY:
@@ -2082,7 +2109,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2082 else 2109 else
2083 devices = ATOM_DEVICE_DFP1_SUPPORT; 2110 devices = ATOM_DEVICE_DFP1_SUPPORT;
2084 radeon_add_legacy_encoder(dev, 2111 radeon_add_legacy_encoder(dev,
2085 radeon_get_encoder_id 2112 radeon_get_encoder_enum
2086 (dev, devices, 0), 2113 (dev, devices, 0),
2087 devices); 2114 devices);
2088 radeon_add_legacy_connector(dev, i, devices, 2115 radeon_add_legacy_connector(dev, i, devices,
@@ -2096,7 +2123,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2096 if (tmp & 0x1) { 2123 if (tmp & 0x1) {
2097 devices = ATOM_DEVICE_CRT2_SUPPORT; 2124 devices = ATOM_DEVICE_CRT2_SUPPORT;
2098 radeon_add_legacy_encoder(dev, 2125 radeon_add_legacy_encoder(dev,
2099 radeon_get_encoder_id 2126 radeon_get_encoder_enum
2100 (dev, 2127 (dev,
2101 ATOM_DEVICE_CRT2_SUPPORT, 2128 ATOM_DEVICE_CRT2_SUPPORT,
2102 2), 2129 2),
@@ -2104,7 +2131,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2104 } else { 2131 } else {
2105 devices = ATOM_DEVICE_CRT1_SUPPORT; 2132 devices = ATOM_DEVICE_CRT1_SUPPORT;
2106 radeon_add_legacy_encoder(dev, 2133 radeon_add_legacy_encoder(dev,
2107 radeon_get_encoder_id 2134 radeon_get_encoder_enum
2108 (dev, 2135 (dev,
2109 ATOM_DEVICE_CRT1_SUPPORT, 2136 ATOM_DEVICE_CRT1_SUPPORT,
2110 1), 2137 1),
@@ -2124,7 +2151,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2124 if (tmp & 0x1) { 2151 if (tmp & 0x1) {
2125 devices |= ATOM_DEVICE_CRT2_SUPPORT; 2152 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2126 radeon_add_legacy_encoder(dev, 2153 radeon_add_legacy_encoder(dev,
2127 radeon_get_encoder_id 2154 radeon_get_encoder_enum
2128 (dev, 2155 (dev,
2129 ATOM_DEVICE_CRT2_SUPPORT, 2156 ATOM_DEVICE_CRT2_SUPPORT,
2130 2), 2157 2),
@@ -2132,7 +2159,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2132 } else { 2159 } else {
2133 devices |= ATOM_DEVICE_CRT1_SUPPORT; 2160 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2134 radeon_add_legacy_encoder(dev, 2161 radeon_add_legacy_encoder(dev,
2135 radeon_get_encoder_id 2162 radeon_get_encoder_enum
2136 (dev, 2163 (dev,
2137 ATOM_DEVICE_CRT1_SUPPORT, 2164 ATOM_DEVICE_CRT1_SUPPORT,
2138 1), 2165 1),
@@ -2141,7 +2168,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2141 if ((tmp >> 4) & 0x1) { 2168 if ((tmp >> 4) & 0x1) {
2142 devices |= ATOM_DEVICE_DFP2_SUPPORT; 2169 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2143 radeon_add_legacy_encoder(dev, 2170 radeon_add_legacy_encoder(dev,
2144 radeon_get_encoder_id 2171 radeon_get_encoder_enum
2145 (dev, 2172 (dev,
2146 ATOM_DEVICE_DFP2_SUPPORT, 2173 ATOM_DEVICE_DFP2_SUPPORT,
2147 0), 2174 0),
@@ -2150,7 +2177,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2150 } else { 2177 } else {
2151 devices |= ATOM_DEVICE_DFP1_SUPPORT; 2178 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2152 radeon_add_legacy_encoder(dev, 2179 radeon_add_legacy_encoder(dev,
2153 radeon_get_encoder_id 2180 radeon_get_encoder_enum
2154 (dev, 2181 (dev,
2155 ATOM_DEVICE_DFP1_SUPPORT, 2182 ATOM_DEVICE_DFP1_SUPPORT,
2156 0), 2183 0),
@@ -2175,7 +2202,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2175 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2202 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2176 } 2203 }
2177 radeon_add_legacy_encoder(dev, 2204 radeon_add_legacy_encoder(dev,
2178 radeon_get_encoder_id 2205 radeon_get_encoder_enum
2179 (dev, devices, 0), 2206 (dev, devices, 0),
2180 devices); 2207 devices);
2181 radeon_add_legacy_connector(dev, i, devices, 2208 radeon_add_legacy_connector(dev, i, devices,
@@ -2188,7 +2215,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2188 case CONNECTOR_CTV_LEGACY: 2215 case CONNECTOR_CTV_LEGACY:
2189 case CONNECTOR_STV_LEGACY: 2216 case CONNECTOR_STV_LEGACY:
2190 radeon_add_legacy_encoder(dev, 2217 radeon_add_legacy_encoder(dev,
2191 radeon_get_encoder_id 2218 radeon_get_encoder_enum
2192 (dev, 2219 (dev,
2193 ATOM_DEVICE_TV1_SUPPORT, 2220 ATOM_DEVICE_TV1_SUPPORT,
2194 2), 2221 2),
@@ -2215,17 +2242,17 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2215 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); 2242 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2216 2243
2217 radeon_add_legacy_encoder(dev, 2244 radeon_add_legacy_encoder(dev,
2218 radeon_get_encoder_id(dev, 2245 radeon_get_encoder_enum(dev,
2219 ATOM_DEVICE_CRT1_SUPPORT, 2246 ATOM_DEVICE_CRT1_SUPPORT,
2220 1), 2247 1),
2221 ATOM_DEVICE_CRT1_SUPPORT); 2248 ATOM_DEVICE_CRT1_SUPPORT);
2222 radeon_add_legacy_encoder(dev, 2249 radeon_add_legacy_encoder(dev,
2223 radeon_get_encoder_id(dev, 2250 radeon_get_encoder_enum(dev,
2224 ATOM_DEVICE_DFP1_SUPPORT, 2251 ATOM_DEVICE_DFP1_SUPPORT,
2225 0), 2252 0),
2226 ATOM_DEVICE_DFP1_SUPPORT); 2253 ATOM_DEVICE_DFP1_SUPPORT);
2227 2254
2228 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 2255 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2229 hpd.hpd = RADEON_HPD_1; 2256 hpd.hpd = RADEON_HPD_1;
2230 radeon_add_legacy_connector(dev, 2257 radeon_add_legacy_connector(dev,
2231 0, 2258 0,
@@ -2241,11 +2268,11 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2241 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); 2268 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2242 if (crt_info) { 2269 if (crt_info) {
2243 radeon_add_legacy_encoder(dev, 2270 radeon_add_legacy_encoder(dev,
2244 radeon_get_encoder_id(dev, 2271 radeon_get_encoder_enum(dev,
2245 ATOM_DEVICE_CRT1_SUPPORT, 2272 ATOM_DEVICE_CRT1_SUPPORT,
2246 1), 2273 1),
2247 ATOM_DEVICE_CRT1_SUPPORT); 2274 ATOM_DEVICE_CRT1_SUPPORT);
2248 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 2275 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2249 hpd.hpd = RADEON_HPD_NONE; 2276 hpd.hpd = RADEON_HPD_NONE;
2250 radeon_add_legacy_connector(dev, 2277 radeon_add_legacy_connector(dev,
2251 0, 2278 0,
@@ -2270,7 +2297,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2270 COMBIOS_LCD_DDC_INFO_TABLE); 2297 COMBIOS_LCD_DDC_INFO_TABLE);
2271 2298
2272 radeon_add_legacy_encoder(dev, 2299 radeon_add_legacy_encoder(dev,
2273 radeon_get_encoder_id(dev, 2300 radeon_get_encoder_enum(dev,
2274 ATOM_DEVICE_LCD1_SUPPORT, 2301 ATOM_DEVICE_LCD1_SUPPORT,
2275 0), 2302 0),
2276 ATOM_DEVICE_LCD1_SUPPORT); 2303 ATOM_DEVICE_LCD1_SUPPORT);
@@ -2278,70 +2305,25 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2278 if (lcd_ddc_info) { 2305 if (lcd_ddc_info) {
2279 ddc_type = RBIOS8(lcd_ddc_info + 2); 2306 ddc_type = RBIOS8(lcd_ddc_info + 2);
2280 switch (ddc_type) { 2307 switch (ddc_type) {
2281 case DDC_MONID:
2282 ddc_i2c =
2283 combios_setup_i2c_bus
2284 (rdev, RADEON_GPIO_MONID);
2285 break;
2286 case DDC_DVI:
2287 ddc_i2c =
2288 combios_setup_i2c_bus
2289 (rdev, RADEON_GPIO_DVI_DDC);
2290 break;
2291 case DDC_VGA:
2292 ddc_i2c =
2293 combios_setup_i2c_bus
2294 (rdev, RADEON_GPIO_VGA_DDC);
2295 break;
2296 case DDC_CRT2:
2297 ddc_i2c =
2298 combios_setup_i2c_bus
2299 (rdev, RADEON_GPIO_CRT2_DDC);
2300 break;
2301 case DDC_LCD: 2308 case DDC_LCD:
2302 ddc_i2c = 2309 ddc_i2c =
2303 combios_setup_i2c_bus 2310 combios_setup_i2c_bus(rdev,
2304 (rdev, RADEON_GPIOPAD_MASK); 2311 DDC_LCD,
2305 ddc_i2c.mask_clk_mask = 2312 RBIOS32(lcd_ddc_info + 3),
2306 RBIOS32(lcd_ddc_info + 3); 2313 RBIOS32(lcd_ddc_info + 7));
2307 ddc_i2c.mask_data_mask = 2314 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2308 RBIOS32(lcd_ddc_info + 7);
2309 ddc_i2c.a_clk_mask =
2310 RBIOS32(lcd_ddc_info + 3);
2311 ddc_i2c.a_data_mask =
2312 RBIOS32(lcd_ddc_info + 7);
2313 ddc_i2c.en_clk_mask =
2314 RBIOS32(lcd_ddc_info + 3);
2315 ddc_i2c.en_data_mask =
2316 RBIOS32(lcd_ddc_info + 7);
2317 ddc_i2c.y_clk_mask =
2318 RBIOS32(lcd_ddc_info + 3);
2319 ddc_i2c.y_data_mask =
2320 RBIOS32(lcd_ddc_info + 7);
2321 break; 2315 break;
2322 case DDC_GPIO: 2316 case DDC_GPIO:
2323 ddc_i2c = 2317 ddc_i2c =
2324 combios_setup_i2c_bus 2318 combios_setup_i2c_bus(rdev,
2325 (rdev, RADEON_MDGPIO_MASK); 2319 DDC_GPIO,
2326 ddc_i2c.mask_clk_mask = 2320 RBIOS32(lcd_ddc_info + 3),
2327 RBIOS32(lcd_ddc_info + 3); 2321 RBIOS32(lcd_ddc_info + 7));
2328 ddc_i2c.mask_data_mask = 2322 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2329 RBIOS32(lcd_ddc_info + 7);
2330 ddc_i2c.a_clk_mask =
2331 RBIOS32(lcd_ddc_info + 3);
2332 ddc_i2c.a_data_mask =
2333 RBIOS32(lcd_ddc_info + 7);
2334 ddc_i2c.en_clk_mask =
2335 RBIOS32(lcd_ddc_info + 3);
2336 ddc_i2c.en_data_mask =
2337 RBIOS32(lcd_ddc_info + 7);
2338 ddc_i2c.y_clk_mask =
2339 RBIOS32(lcd_ddc_info + 3);
2340 ddc_i2c.y_data_mask =
2341 RBIOS32(lcd_ddc_info + 7);
2342 break; 2323 break;
2343 default: 2324 default:
2344 ddc_i2c.valid = false; 2325 ddc_i2c =
2326 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2345 break; 2327 break;
2346 } 2328 }
2347 DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); 2329 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
@@ -2369,7 +2351,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2369 hpd.hpd = RADEON_HPD_NONE; 2351 hpd.hpd = RADEON_HPD_NONE;
2370 ddc_i2c.valid = false; 2352 ddc_i2c.valid = false;
2371 radeon_add_legacy_encoder(dev, 2353 radeon_add_legacy_encoder(dev,
2372 radeon_get_encoder_id 2354 radeon_get_encoder_enum
2373 (dev, 2355 (dev,
2374 ATOM_DEVICE_TV1_SUPPORT, 2356 ATOM_DEVICE_TV1_SUPPORT,
2375 2), 2357 2),
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 2395c8600cf4..31a09cd279ab 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -518,8 +518,6 @@ static void radeon_connector_destroy(struct drm_connector *connector)
518{ 518{
519 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 519 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
520 520
521 if (radeon_connector->ddc_bus)
522 radeon_i2c_destroy(radeon_connector->ddc_bus);
523 if (radeon_connector->edid) 521 if (radeon_connector->edid)
524 kfree(radeon_connector->edid); 522 kfree(radeon_connector->edid);
525 kfree(radeon_connector->con_priv); 523 kfree(radeon_connector->con_priv);
@@ -955,8 +953,6 @@ static void radeon_dp_connector_destroy(struct drm_connector *connector)
955 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 953 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
956 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; 954 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
957 955
958 if (radeon_connector->ddc_bus)
959 radeon_i2c_destroy(radeon_connector->ddc_bus);
960 if (radeon_connector->edid) 956 if (radeon_connector->edid)
961 kfree(radeon_connector->edid); 957 kfree(radeon_connector->edid);
962 if (radeon_dig_connector->dp_i2c_bus) 958 if (radeon_dig_connector->dp_i2c_bus)
@@ -981,24 +977,25 @@ static enum drm_connector_status radeon_dp_detect(struct drm_connector *connecto
981 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 977 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
982 enum drm_connector_status ret = connector_status_disconnected; 978 enum drm_connector_status ret = connector_status_disconnected;
983 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; 979 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
984 u8 sink_type;
985 980
986 if (radeon_connector->edid) { 981 if (radeon_connector->edid) {
987 kfree(radeon_connector->edid); 982 kfree(radeon_connector->edid);
988 radeon_connector->edid = NULL; 983 radeon_connector->edid = NULL;
989 } 984 }
990 985
991 sink_type = radeon_dp_getsinktype(radeon_connector); 986 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
992 if ((sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 987 /* eDP is always DP */
993 (sink_type == CONNECTOR_OBJECT_ID_eDP)) { 988 radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
994 if (radeon_dp_getdpcd(radeon_connector)) { 989 if (radeon_dp_getdpcd(radeon_connector))
995 radeon_dig_connector->dp_sink_type = sink_type;
996 ret = connector_status_connected; 990 ret = connector_status_connected;
997 }
998 } else { 991 } else {
999 if (radeon_ddc_probe(radeon_connector)) { 992 radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector);
1000 radeon_dig_connector->dp_sink_type = sink_type; 993 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1001 ret = connector_status_connected; 994 if (radeon_dp_getdpcd(radeon_connector))
995 ret = connector_status_connected;
996 } else {
997 if (radeon_ddc_probe(radeon_connector))
998 ret = connector_status_connected;
1002 } 999 }
1003 } 1000 }
1004 1001
@@ -1041,10 +1038,10 @@ radeon_add_atom_connector(struct drm_device *dev,
1041 uint32_t supported_device, 1038 uint32_t supported_device,
1042 int connector_type, 1039 int connector_type,
1043 struct radeon_i2c_bus_rec *i2c_bus, 1040 struct radeon_i2c_bus_rec *i2c_bus,
1044 bool linkb,
1045 uint32_t igp_lane_info, 1041 uint32_t igp_lane_info,
1046 uint16_t connector_object_id, 1042 uint16_t connector_object_id,
1047 struct radeon_hpd *hpd) 1043 struct radeon_hpd *hpd,
1044 struct radeon_router *router)
1048{ 1045{
1049 struct radeon_device *rdev = dev->dev_private; 1046 struct radeon_device *rdev = dev->dev_private;
1050 struct drm_connector *connector; 1047 struct drm_connector *connector;
@@ -1069,6 +1066,11 @@ radeon_add_atom_connector(struct drm_device *dev,
1069 radeon_connector->shared_ddc = true; 1066 radeon_connector->shared_ddc = true;
1070 shared_ddc = true; 1067 shared_ddc = true;
1071 } 1068 }
1069 if (radeon_connector->router_bus && router->valid &&
1070 (radeon_connector->router.router_id == router->router_id)) {
1071 radeon_connector->shared_ddc = false;
1072 shared_ddc = false;
1073 }
1072 } 1074 }
1073 } 1075 }
1074 1076
@@ -1083,12 +1085,18 @@ radeon_add_atom_connector(struct drm_device *dev,
1083 radeon_connector->shared_ddc = shared_ddc; 1085 radeon_connector->shared_ddc = shared_ddc;
1084 radeon_connector->connector_object_id = connector_object_id; 1086 radeon_connector->connector_object_id = connector_object_id;
1085 radeon_connector->hpd = *hpd; 1087 radeon_connector->hpd = *hpd;
1088 radeon_connector->router = *router;
1089 if (router->valid) {
1090 radeon_connector->router_bus = radeon_i2c_lookup(rdev, &router->i2c_info);
1091 if (!radeon_connector->router_bus)
1092 goto failed;
1093 }
1086 switch (connector_type) { 1094 switch (connector_type) {
1087 case DRM_MODE_CONNECTOR_VGA: 1095 case DRM_MODE_CONNECTOR_VGA:
1088 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); 1096 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
1089 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); 1097 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
1090 if (i2c_bus->valid) { 1098 if (i2c_bus->valid) {
1091 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "VGA"); 1099 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1092 if (!radeon_connector->ddc_bus) 1100 if (!radeon_connector->ddc_bus)
1093 goto failed; 1101 goto failed;
1094 } 1102 }
@@ -1104,7 +1112,7 @@ radeon_add_atom_connector(struct drm_device *dev,
1104 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); 1112 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
1105 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); 1113 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
1106 if (i2c_bus->valid) { 1114 if (i2c_bus->valid) {
1107 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); 1115 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1108 if (!radeon_connector->ddc_bus) 1116 if (!radeon_connector->ddc_bus)
1109 goto failed; 1117 goto failed;
1110 } 1118 }
@@ -1120,13 +1128,12 @@ radeon_add_atom_connector(struct drm_device *dev,
1120 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); 1128 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1121 if (!radeon_dig_connector) 1129 if (!radeon_dig_connector)
1122 goto failed; 1130 goto failed;
1123 radeon_dig_connector->linkb = linkb;
1124 radeon_dig_connector->igp_lane_info = igp_lane_info; 1131 radeon_dig_connector->igp_lane_info = igp_lane_info;
1125 radeon_connector->con_priv = radeon_dig_connector; 1132 radeon_connector->con_priv = radeon_dig_connector;
1126 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); 1133 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
1127 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); 1134 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
1128 if (i2c_bus->valid) { 1135 if (i2c_bus->valid) {
1129 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); 1136 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1130 if (!radeon_connector->ddc_bus) 1137 if (!radeon_connector->ddc_bus)
1131 goto failed; 1138 goto failed;
1132 } 1139 }
@@ -1150,13 +1157,12 @@ radeon_add_atom_connector(struct drm_device *dev,
1150 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); 1157 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1151 if (!radeon_dig_connector) 1158 if (!radeon_dig_connector)
1152 goto failed; 1159 goto failed;
1153 radeon_dig_connector->linkb = linkb;
1154 radeon_dig_connector->igp_lane_info = igp_lane_info; 1160 radeon_dig_connector->igp_lane_info = igp_lane_info;
1155 radeon_connector->con_priv = radeon_dig_connector; 1161 radeon_connector->con_priv = radeon_dig_connector;
1156 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); 1162 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
1157 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); 1163 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
1158 if (i2c_bus->valid) { 1164 if (i2c_bus->valid) {
1159 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "HDMI"); 1165 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1160 if (!radeon_connector->ddc_bus) 1166 if (!radeon_connector->ddc_bus)
1161 goto failed; 1167 goto failed;
1162 } 1168 }
@@ -1174,7 +1180,6 @@ radeon_add_atom_connector(struct drm_device *dev,
1174 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); 1180 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1175 if (!radeon_dig_connector) 1181 if (!radeon_dig_connector)
1176 goto failed; 1182 goto failed;
1177 radeon_dig_connector->linkb = linkb;
1178 radeon_dig_connector->igp_lane_info = igp_lane_info; 1183 radeon_dig_connector->igp_lane_info = igp_lane_info;
1179 radeon_connector->con_priv = radeon_dig_connector; 1184 radeon_connector->con_priv = radeon_dig_connector;
1180 drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type); 1185 drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type);
@@ -1187,10 +1192,7 @@ radeon_add_atom_connector(struct drm_device *dev,
1187 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch"); 1192 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch");
1188 if (!radeon_dig_connector->dp_i2c_bus) 1193 if (!radeon_dig_connector->dp_i2c_bus)
1189 goto failed; 1194 goto failed;
1190 if (connector_type == DRM_MODE_CONNECTOR_eDP) 1195 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1191 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "eDP");
1192 else
1193 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DP");
1194 if (!radeon_connector->ddc_bus) 1196 if (!radeon_connector->ddc_bus)
1195 goto failed; 1197 goto failed;
1196 } 1198 }
@@ -1224,13 +1226,12 @@ radeon_add_atom_connector(struct drm_device *dev,
1224 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); 1226 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1225 if (!radeon_dig_connector) 1227 if (!radeon_dig_connector)
1226 goto failed; 1228 goto failed;
1227 radeon_dig_connector->linkb = linkb;
1228 radeon_dig_connector->igp_lane_info = igp_lane_info; 1229 radeon_dig_connector->igp_lane_info = igp_lane_info;
1229 radeon_connector->con_priv = radeon_dig_connector; 1230 radeon_connector->con_priv = radeon_dig_connector;
1230 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); 1231 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
1231 drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); 1232 drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs);
1232 if (i2c_bus->valid) { 1233 if (i2c_bus->valid) {
1233 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "LVDS"); 1234 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1234 if (!radeon_connector->ddc_bus) 1235 if (!radeon_connector->ddc_bus)
1235 goto failed; 1236 goto failed;
1236 } 1237 }
@@ -1252,8 +1253,6 @@ radeon_add_atom_connector(struct drm_device *dev,
1252 return; 1253 return;
1253 1254
1254failed: 1255failed:
1255 if (radeon_connector->ddc_bus)
1256 radeon_i2c_destroy(radeon_connector->ddc_bus);
1257 drm_connector_cleanup(connector); 1256 drm_connector_cleanup(connector);
1258 kfree(connector); 1257 kfree(connector);
1259} 1258}
@@ -1300,7 +1299,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
1300 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); 1299 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
1301 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); 1300 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
1302 if (i2c_bus->valid) { 1301 if (i2c_bus->valid) {
1303 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "VGA"); 1302 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1304 if (!radeon_connector->ddc_bus) 1303 if (!radeon_connector->ddc_bus)
1305 goto failed; 1304 goto failed;
1306 } 1305 }
@@ -1316,7 +1315,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
1316 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); 1315 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
1317 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); 1316 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
1318 if (i2c_bus->valid) { 1317 if (i2c_bus->valid) {
1319 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); 1318 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1320 if (!radeon_connector->ddc_bus) 1319 if (!radeon_connector->ddc_bus)
1321 goto failed; 1320 goto failed;
1322 } 1321 }
@@ -1332,7 +1331,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
1332 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); 1331 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
1333 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); 1332 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
1334 if (i2c_bus->valid) { 1333 if (i2c_bus->valid) {
1335 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); 1334 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1336 if (!radeon_connector->ddc_bus) 1335 if (!radeon_connector->ddc_bus)
1337 goto failed; 1336 goto failed;
1338 } 1337 }
@@ -1372,7 +1371,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
1372 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); 1371 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
1373 drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); 1372 drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs);
1374 if (i2c_bus->valid) { 1373 if (i2c_bus->valid) {
1375 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "LVDS"); 1374 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1376 if (!radeon_connector->ddc_bus) 1375 if (!radeon_connector->ddc_bus)
1377 goto failed; 1376 goto failed;
1378 } 1377 }
@@ -1393,8 +1392,6 @@ radeon_add_legacy_connector(struct drm_device *dev,
1393 return; 1392 return;
1394 1393
1395failed: 1394failed:
1396 if (radeon_connector->ddc_bus)
1397 radeon_i2c_destroy(radeon_connector->ddc_bus);
1398 drm_connector_cleanup(connector); 1395 drm_connector_cleanup(connector);
1399 kfree(connector); 1396 kfree(connector);
1400} 1397}
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index ae0fb7356e62..fcc79b5d22d1 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -72,7 +72,7 @@ int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
72 if (p->relocs[i].gobj == NULL) { 72 if (p->relocs[i].gobj == NULL) {
73 DRM_ERROR("gem object lookup failed 0x%x\n", 73 DRM_ERROR("gem object lookup failed 0x%x\n",
74 r->handle); 74 r->handle);
75 return -EINVAL; 75 return -ENOENT;
76 } 76 }
77 p->relocs_ptr[i] = &p->relocs[i]; 77 p->relocs_ptr[i] = &p->relocs[i];
78 p->relocs[i].robj = p->relocs[i].gobj->driver_private; 78 p->relocs[i].robj = p->relocs[i].gobj->driver_private;
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
index 4eb67c0e0996..5731fc9b1ae3 100644
--- a/drivers/gpu/drm/radeon/radeon_cursor.c
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
@@ -170,7 +170,7 @@ int radeon_crtc_cursor_set(struct drm_crtc *crtc,
170 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 170 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
171 if (!obj) { 171 if (!obj) {
172 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id); 172 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
173 return -EINVAL; 173 return -ENOENT;
174 } 174 }
175 175
176 ret = radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &gpu_addr); 176 ret = radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index a64811a94519..69b3c2291e92 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -199,7 +199,7 @@ void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64
199 mc->mc_vram_size = mc->aper_size; 199 mc->mc_vram_size = mc->aper_size;
200 } 200 }
201 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 201 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
202 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) { 202 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
203 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 203 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
204 mc->real_vram_size = mc->aper_size; 204 mc->real_vram_size = mc->aper_size;
205 mc->mc_vram_size = mc->aper_size; 205 mc->mc_vram_size = mc->aper_size;
@@ -347,7 +347,8 @@ int radeon_dummy_page_init(struct radeon_device *rdev)
347 return -ENOMEM; 347 return -ENOMEM;
348 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, 348 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
349 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 349 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
350 if (!rdev->dummy_page.addr) { 350 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
351 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
351 __free_page(rdev->dummy_page.page); 352 __free_page(rdev->dummy_page.page);
352 rdev->dummy_page.page = NULL; 353 rdev->dummy_page.page = NULL;
353 return -ENOMEM; 354 return -ENOMEM;
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 74dac9635d70..6dd434ad2429 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -161,17 +161,13 @@ void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
161} 161}
162 162
163static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 163static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
164 u16 *blue, uint32_t size) 164 u16 *blue, uint32_t start, uint32_t size)
165{ 165{
166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
167 int i; 167 int end = (start + size > 256) ? 256 : start + size, i;
168
169 if (size != 256) {
170 return;
171 }
172 168
173 /* userspace palettes are always correct as is */ 169 /* userspace palettes are always correct as is */
174 for (i = 0; i < 256; i++) { 170 for (i = start; i < end; i++) {
175 radeon_crtc->lut_r[i] = red[i] >> 6; 171 radeon_crtc->lut_r[i] = red[i] >> 6;
176 radeon_crtc->lut_g[i] = green[i] >> 6; 172 radeon_crtc->lut_g[i] = green[i] >> 6;
177 radeon_crtc->lut_b[i] = blue[i] >> 6; 173 radeon_crtc->lut_b[i] = blue[i] >> 6;
@@ -319,6 +315,10 @@ static void radeon_print_display_setup(struct drm_device *dev)
319 radeon_connector->ddc_bus->rec.en_data_reg, 315 radeon_connector->ddc_bus->rec.en_data_reg,
320 radeon_connector->ddc_bus->rec.y_clk_reg, 316 radeon_connector->ddc_bus->rec.y_clk_reg,
321 radeon_connector->ddc_bus->rec.y_data_reg); 317 radeon_connector->ddc_bus->rec.y_data_reg);
318 if (radeon_connector->router_bus)
319 DRM_INFO(" DDC Router 0x%x/0x%x\n",
320 radeon_connector->router.mux_control_pin,
321 radeon_connector->router.mux_state);
322 } else { 322 } else {
323 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 323 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
324 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 324 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
@@ -395,6 +395,10 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
395 struct radeon_device *rdev = dev->dev_private; 395 struct radeon_device *rdev = dev->dev_private;
396 int ret = 0; 396 int ret = 0;
397 397
398 /* on hw with routers, select right port */
399 if (radeon_connector->router.valid)
400 radeon_router_select_port(radeon_connector);
401
398 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 402 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
399 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { 403 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
400 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 404 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
@@ -425,6 +429,10 @@ static int radeon_ddc_dump(struct drm_connector *connector)
425 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 429 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
426 int ret = 0; 430 int ret = 0;
427 431
432 /* on hw with routers, select right port */
433 if (radeon_connector->router.valid)
434 radeon_router_select_port(radeon_connector);
435
428 if (!radeon_connector->ddc_bus) 436 if (!radeon_connector->ddc_bus)
429 return -1; 437 return -1;
430 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); 438 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
@@ -876,13 +884,12 @@ radeon_user_framebuffer_create(struct drm_device *dev,
876 if (obj == NULL) { 884 if (obj == NULL) {
877 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 885 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
878 "can't create framebuffer\n", mode_cmd->handle); 886 "can't create framebuffer\n", mode_cmd->handle);
879 return NULL; 887 return ERR_PTR(-ENOENT);
880 } 888 }
881 889
882 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 890 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
883 if (radeon_fb == NULL) { 891 if (radeon_fb == NULL)
884 return NULL; 892 return ERR_PTR(-ENOMEM);
885 }
886 893
887 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 894 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
888 895
@@ -1040,6 +1047,9 @@ int radeon_modeset_init(struct radeon_device *rdev)
1040 return ret; 1047 return ret;
1041 } 1048 }
1042 1049
1050 /* init i2c buses */
1051 radeon_i2c_init(rdev);
1052
1043 /* check combios for a valid hardcoded EDID - Sun servers */ 1053 /* check combios for a valid hardcoded EDID - Sun servers */
1044 if (!rdev->is_atom_bios) { 1054 if (!rdev->is_atom_bios) {
1045 /* check for hardcoded EDID in BIOS */ 1055 /* check for hardcoded EDID in BIOS */
@@ -1080,6 +1090,20 @@ void radeon_modeset_fini(struct radeon_device *rdev)
1080 drm_mode_config_cleanup(rdev->ddev); 1090 drm_mode_config_cleanup(rdev->ddev);
1081 rdev->mode_info.mode_config_initialized = false; 1091 rdev->mode_info.mode_config_initialized = false;
1082 } 1092 }
1093 /* free i2c buses */
1094 radeon_i2c_fini(rdev);
1095}
1096
1097static bool is_hdtv_mode(struct drm_display_mode *mode)
1098{
1099 /* try and guess if this is a tv or a monitor */
1100 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1101 (mode->vdisplay == 576) || /* 576p */
1102 (mode->vdisplay == 720) || /* 720p */
1103 (mode->vdisplay == 1080)) /* 1080p */
1104 return true;
1105 else
1106 return false;
1083} 1107}
1084 1108
1085bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1109bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
@@ -1129,7 +1153,8 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1129 if (ASIC_IS_AVIVO(rdev) && 1153 if (ASIC_IS_AVIVO(rdev) &&
1130 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1154 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1131 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1155 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1132 drm_detect_hdmi_monitor(radeon_connector->edid)))) { 1156 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1157 is_hdtv_mode(mode)))) {
1133 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1158 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1134 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1159 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1135 radeon_crtc->rmx_type = RMX_FULL; 1160 radeon_crtc->rmx_type = RMX_FULL;
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 263c8098d7dd..2c293e8304d6 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -81,7 +81,7 @@ void radeon_setup_encoder_clones(struct drm_device *dev)
81} 81}
82 82
83uint32_t 83uint32_t
84radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac) 84radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
85{ 85{
86 struct radeon_device *rdev = dev->dev_private; 86 struct radeon_device *rdev = dev->dev_private;
87 uint32_t ret = 0; 87 uint32_t ret = 0;
@@ -97,59 +97,59 @@ radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t
97 if ((rdev->family == CHIP_RS300) || 97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) || 98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480)) 99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; 100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
101 else if (ASIC_IS_AVIVO(rdev)) 101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; 102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
103 else 103 else
104 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1; 104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
105 break; 105 break;
106 case 2: /* dac b */ 106 case 2: /* dac b */
107 if (ASIC_IS_AVIVO(rdev)) 107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; 108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
109 else { 109 else {
110 /*if (rdev->family == CHIP_R200) 110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; 111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
112 else*/ 112 else*/
113 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; 113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
114 } 114 }
115 break; 115 break;
116 case 3: /* external dac */ 116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev)) 117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; 118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
119 else 119 else
120 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; 120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
121 break; 121 break;
122 } 122 }
123 break; 123 break;
124 case ATOM_DEVICE_LCD1_SUPPORT: 124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev)) 125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; 126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
127 else 127 else
128 ret = ENCODER_OBJECT_ID_INTERNAL_LVDS; 128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
129 break; 129 break;
130 case ATOM_DEVICE_DFP1_SUPPORT: 130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) || 131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) || 132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480)) 133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; 134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
135 else if (ASIC_IS_AVIVO(rdev)) 135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; 136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
137 else 137 else
138 ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1; 138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
139 break; 139 break;
140 case ATOM_DEVICE_LCD2_SUPPORT: 140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT: 141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) || 142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) || 143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740)) 144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_OBJECT_ID_INTERNAL_DDI; 145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
146 else if (ASIC_IS_AVIVO(rdev)) 146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; 147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
148 else 148 else
149 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; 149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
150 break; 150 break;
151 case ATOM_DEVICE_DFP3_SUPPORT: 151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; 152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
153 break; 153 break;
154 } 154 }
155 155
@@ -228,32 +228,6 @@ radeon_get_connector_for_encoder(struct drm_encoder *encoder)
228 return NULL; 228 return NULL;
229} 229}
230 230
231static struct radeon_connector_atom_dig *
232radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
233{
234 struct drm_device *dev = encoder->dev;
235 struct radeon_device *rdev = dev->dev_private;
236 struct drm_connector *connector;
237 struct radeon_connector *radeon_connector;
238 struct radeon_connector_atom_dig *dig_connector;
239
240 if (!rdev->is_atom_bios)
241 return NULL;
242
243 connector = radeon_get_connector_for_encoder(encoder);
244 if (!connector)
245 return NULL;
246
247 radeon_connector = to_radeon_connector(connector);
248
249 if (!radeon_connector->con_priv)
250 return NULL;
251
252 dig_connector = radeon_connector->con_priv;
253
254 return dig_connector;
255}
256
257void radeon_panel_mode_fixup(struct drm_encoder *encoder, 231void radeon_panel_mode_fixup(struct drm_encoder *encoder,
258 struct drm_display_mode *adjusted_mode) 232 struct drm_display_mode *adjusted_mode)
259{ 233{
@@ -512,14 +486,12 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
512 struct radeon_device *rdev = dev->dev_private; 486 struct radeon_device *rdev = dev->dev_private;
513 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 487 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
514 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 488 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
515 struct radeon_connector_atom_dig *dig_connector =
516 radeon_get_atom_connector_priv_from_encoder(encoder);
517 union lvds_encoder_control args; 489 union lvds_encoder_control args;
518 int index = 0; 490 int index = 0;
519 int hdmi_detected = 0; 491 int hdmi_detected = 0;
520 uint8_t frev, crev; 492 uint8_t frev, crev;
521 493
522 if (!dig || !dig_connector) 494 if (!dig)
523 return; 495 return;
524 496
525 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 497 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
@@ -562,7 +534,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
562 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) 534 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
563 args.v1.ucMisc |= (1 << 1); 535 args.v1.ucMisc |= (1 << 1);
564 } else { 536 } else {
565 if (dig_connector->linkb) 537 if (dig->linkb)
566 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 538 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
567 if (radeon_encoder->pixel_clock > 165000) 539 if (radeon_encoder->pixel_clock > 165000)
568 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 540 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
@@ -601,7 +573,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
601 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 573 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
602 } 574 }
603 } else { 575 } else {
604 if (dig_connector->linkb) 576 if (dig->linkb)
605 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 577 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
606 if (radeon_encoder->pixel_clock > 165000) 578 if (radeon_encoder->pixel_clock > 165000)
607 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 579 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
@@ -623,6 +595,8 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
623int 595int
624atombios_get_encoder_mode(struct drm_encoder *encoder) 596atombios_get_encoder_mode(struct drm_encoder *encoder)
625{ 597{
598 struct drm_device *dev = encoder->dev;
599 struct radeon_device *rdev = dev->dev_private;
626 struct drm_connector *connector; 600 struct drm_connector *connector;
627 struct radeon_connector *radeon_connector; 601 struct radeon_connector *radeon_connector;
628 struct radeon_connector_atom_dig *dig_connector; 602 struct radeon_connector_atom_dig *dig_connector;
@@ -636,9 +610,13 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
636 switch (connector->connector_type) { 610 switch (connector->connector_type) {
637 case DRM_MODE_CONNECTOR_DVII: 611 case DRM_MODE_CONNECTOR_DVII:
638 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 612 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
639 if (drm_detect_hdmi_monitor(radeon_connector->edid)) 613 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
640 return ATOM_ENCODER_MODE_HDMI; 614 /* fix me */
641 else if (radeon_connector->use_digital) 615 if (ASIC_IS_DCE4(rdev))
616 return ATOM_ENCODER_MODE_DVI;
617 else
618 return ATOM_ENCODER_MODE_HDMI;
619 } else if (radeon_connector->use_digital)
642 return ATOM_ENCODER_MODE_DVI; 620 return ATOM_ENCODER_MODE_DVI;
643 else 621 else
644 return ATOM_ENCODER_MODE_CRT; 622 return ATOM_ENCODER_MODE_CRT;
@@ -646,9 +624,13 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
646 case DRM_MODE_CONNECTOR_DVID: 624 case DRM_MODE_CONNECTOR_DVID:
647 case DRM_MODE_CONNECTOR_HDMIA: 625 case DRM_MODE_CONNECTOR_HDMIA:
648 default: 626 default:
649 if (drm_detect_hdmi_monitor(radeon_connector->edid)) 627 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
650 return ATOM_ENCODER_MODE_HDMI; 628 /* fix me */
651 else 629 if (ASIC_IS_DCE4(rdev))
630 return ATOM_ENCODER_MODE_DVI;
631 else
632 return ATOM_ENCODER_MODE_HDMI;
633 } else
652 return ATOM_ENCODER_MODE_DVI; 634 return ATOM_ENCODER_MODE_DVI;
653 break; 635 break;
654 case DRM_MODE_CONNECTOR_LVDS: 636 case DRM_MODE_CONNECTOR_LVDS:
@@ -660,9 +642,13 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
660 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 642 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
661 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 643 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
662 return ATOM_ENCODER_MODE_DP; 644 return ATOM_ENCODER_MODE_DP;
663 else if (drm_detect_hdmi_monitor(radeon_connector->edid)) 645 else if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
664 return ATOM_ENCODER_MODE_HDMI; 646 /* fix me */
665 else 647 if (ASIC_IS_DCE4(rdev))
648 return ATOM_ENCODER_MODE_DVI;
649 else
650 return ATOM_ENCODER_MODE_HDMI;
651 } else
666 return ATOM_ENCODER_MODE_DVI; 652 return ATOM_ENCODER_MODE_DVI;
667 break; 653 break;
668 case DRM_MODE_CONNECTOR_DVIA: 654 case DRM_MODE_CONNECTOR_DVIA:
@@ -729,13 +715,24 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
729 struct radeon_device *rdev = dev->dev_private; 715 struct radeon_device *rdev = dev->dev_private;
730 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 716 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
731 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 717 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
732 struct radeon_connector_atom_dig *dig_connector = 718 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
733 radeon_get_atom_connector_priv_from_encoder(encoder);
734 union dig_encoder_control args; 719 union dig_encoder_control args;
735 int index = 0; 720 int index = 0;
736 uint8_t frev, crev; 721 uint8_t frev, crev;
722 int dp_clock = 0;
723 int dp_lane_count = 0;
724
725 if (connector) {
726 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
727 struct radeon_connector_atom_dig *dig_connector =
728 radeon_connector->con_priv;
737 729
738 if (!dig || !dig_connector) 730 dp_clock = dig_connector->dp_clock;
731 dp_lane_count = dig_connector->dp_lane_count;
732 }
733
734 /* no dig encoder assigned */
735 if (dig->dig_encoder == -1)
739 return; 736 return;
740 737
741 memset(&args, 0, sizeof(args)); 738 memset(&args, 0, sizeof(args));
@@ -757,9 +754,9 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
757 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 754 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
758 755
759 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) { 756 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
760 if (dig_connector->dp_clock == 270000) 757 if (dp_clock == 270000)
761 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 758 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
762 args.v1.ucLaneNum = dig_connector->dp_lane_count; 759 args.v1.ucLaneNum = dp_lane_count;
763 } else if (radeon_encoder->pixel_clock > 165000) 760 } else if (radeon_encoder->pixel_clock > 165000)
764 args.v1.ucLaneNum = 8; 761 args.v1.ucLaneNum = 8;
765 else 762 else
@@ -781,7 +778,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
781 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 778 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
782 break; 779 break;
783 } 780 }
784 if (dig_connector->linkb) 781 if (dig->linkb)
785 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 782 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
786 else 783 else
787 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 784 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
@@ -804,38 +801,47 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
804 struct radeon_device *rdev = dev->dev_private; 801 struct radeon_device *rdev = dev->dev_private;
805 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 802 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
806 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 803 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
807 struct radeon_connector_atom_dig *dig_connector = 804 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
808 radeon_get_atom_connector_priv_from_encoder(encoder);
809 struct drm_connector *connector;
810 struct radeon_connector *radeon_connector;
811 union dig_transmitter_control args; 805 union dig_transmitter_control args;
812 int index = 0; 806 int index = 0;
813 uint8_t frev, crev; 807 uint8_t frev, crev;
814 bool is_dp = false; 808 bool is_dp = false;
815 int pll_id = 0; 809 int pll_id = 0;
810 int dp_clock = 0;
811 int dp_lane_count = 0;
812 int connector_object_id = 0;
813 int igp_lane_info = 0;
816 814
817 if (!dig || !dig_connector) 815 if (connector) {
818 return; 816 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
817 struct radeon_connector_atom_dig *dig_connector =
818 radeon_connector->con_priv;
819 819
820 connector = radeon_get_connector_for_encoder(encoder); 820 dp_clock = dig_connector->dp_clock;
821 radeon_connector = to_radeon_connector(connector); 821 dp_lane_count = dig_connector->dp_lane_count;
822 connector_object_id =
823 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
824 igp_lane_info = dig_connector->igp_lane_info;
825 }
826
827 /* no dig encoder assigned */
828 if (dig->dig_encoder == -1)
829 return;
822 830
823 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) 831 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
824 is_dp = true; 832 is_dp = true;
825 833
826 memset(&args, 0, sizeof(args)); 834 memset(&args, 0, sizeof(args));
827 835
828 if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev)) 836 switch (radeon_encoder->encoder_id) {
837 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
838 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
839 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
829 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 840 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
830 else { 841 break;
831 switch (radeon_encoder->encoder_id) { 842 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
832 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 843 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
833 index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); 844 break;
834 break;
835 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
836 index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
837 break;
838 }
839 } 845 }
840 846
841 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 847 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
@@ -843,14 +849,14 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
843 849
844 args.v1.ucAction = action; 850 args.v1.ucAction = action;
845 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 851 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
846 args.v1.usInitInfo = radeon_connector->connector_object_id; 852 args.v1.usInitInfo = connector_object_id;
847 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 853 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
848 args.v1.asMode.ucLaneSel = lane_num; 854 args.v1.asMode.ucLaneSel = lane_num;
849 args.v1.asMode.ucLaneSet = lane_set; 855 args.v1.asMode.ucLaneSet = lane_set;
850 } else { 856 } else {
851 if (is_dp) 857 if (is_dp)
852 args.v1.usPixelClock = 858 args.v1.usPixelClock =
853 cpu_to_le16(dig_connector->dp_clock / 10); 859 cpu_to_le16(dp_clock / 10);
854 else if (radeon_encoder->pixel_clock > 165000) 860 else if (radeon_encoder->pixel_clock > 165000)
855 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 861 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
856 else 862 else
@@ -858,13 +864,13 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
858 } 864 }
859 if (ASIC_IS_DCE4(rdev)) { 865 if (ASIC_IS_DCE4(rdev)) {
860 if (is_dp) 866 if (is_dp)
861 args.v3.ucLaneNum = dig_connector->dp_lane_count; 867 args.v3.ucLaneNum = dp_lane_count;
862 else if (radeon_encoder->pixel_clock > 165000) 868 else if (radeon_encoder->pixel_clock > 165000)
863 args.v3.ucLaneNum = 8; 869 args.v3.ucLaneNum = 8;
864 else 870 else
865 args.v3.ucLaneNum = 4; 871 args.v3.ucLaneNum = 4;
866 872
867 if (dig_connector->linkb) { 873 if (dig->linkb) {
868 args.v3.acConfig.ucLinkSel = 1; 874 args.v3.acConfig.ucLinkSel = 1;
869 args.v3.acConfig.ucEncoderSel = 1; 875 args.v3.acConfig.ucEncoderSel = 1;
870 } 876 }
@@ -904,7 +910,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
904 } 910 }
905 } else if (ASIC_IS_DCE32(rdev)) { 911 } else if (ASIC_IS_DCE32(rdev)) {
906 args.v2.acConfig.ucEncoderSel = dig->dig_encoder; 912 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
907 if (dig_connector->linkb) 913 if (dig->linkb)
908 args.v2.acConfig.ucLinkSel = 1; 914 args.v2.acConfig.ucLinkSel = 1;
909 915
910 switch (radeon_encoder->encoder_id) { 916 switch (radeon_encoder->encoder_id) {
@@ -938,23 +944,23 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
938 if ((rdev->flags & RADEON_IS_IGP) && 944 if ((rdev->flags & RADEON_IS_IGP) &&
939 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 945 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
940 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) { 946 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
941 if (dig_connector->igp_lane_info & 0x1) 947 if (igp_lane_info & 0x1)
942 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 948 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
943 else if (dig_connector->igp_lane_info & 0x2) 949 else if (igp_lane_info & 0x2)
944 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 950 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
945 else if (dig_connector->igp_lane_info & 0x4) 951 else if (igp_lane_info & 0x4)
946 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 952 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
947 else if (dig_connector->igp_lane_info & 0x8) 953 else if (igp_lane_info & 0x8)
948 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 954 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
949 } else { 955 } else {
950 if (dig_connector->igp_lane_info & 0x3) 956 if (igp_lane_info & 0x3)
951 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 957 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
952 else if (dig_connector->igp_lane_info & 0xc) 958 else if (igp_lane_info & 0xc)
953 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 959 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
954 } 960 }
955 } 961 }
956 962
957 if (dig_connector->linkb) 963 if (dig->linkb)
958 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 964 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
959 else 965 else
960 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 966 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
@@ -1072,8 +1078,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1072 if (is_dig) { 1078 if (is_dig) {
1073 switch (mode) { 1079 switch (mode) {
1074 case DRM_MODE_DPMS_ON: 1080 case DRM_MODE_DPMS_ON:
1075 if (!ASIC_IS_DCE4(rdev)) 1081 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1076 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1077 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { 1082 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1078 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1083 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1079 1084
@@ -1085,8 +1090,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1085 case DRM_MODE_DPMS_STANDBY: 1090 case DRM_MODE_DPMS_STANDBY:
1086 case DRM_MODE_DPMS_SUSPEND: 1091 case DRM_MODE_DPMS_SUSPEND:
1087 case DRM_MODE_DPMS_OFF: 1092 case DRM_MODE_DPMS_OFF:
1088 if (!ASIC_IS_DCE4(rdev)) 1093 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1089 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1090 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { 1094 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1091 if (ASIC_IS_DCE4(rdev)) 1095 if (ASIC_IS_DCE4(rdev))
1092 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF); 1096 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
@@ -1290,24 +1294,22 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1290 uint32_t dig_enc_in_use = 0; 1294 uint32_t dig_enc_in_use = 0;
1291 1295
1292 if (ASIC_IS_DCE4(rdev)) { 1296 if (ASIC_IS_DCE4(rdev)) {
1293 struct radeon_connector_atom_dig *dig_connector = 1297 dig = radeon_encoder->enc_priv;
1294 radeon_get_atom_connector_priv_from_encoder(encoder);
1295
1296 switch (radeon_encoder->encoder_id) { 1298 switch (radeon_encoder->encoder_id) {
1297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1299 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1298 if (dig_connector->linkb) 1300 if (dig->linkb)
1299 return 1; 1301 return 1;
1300 else 1302 else
1301 return 0; 1303 return 0;
1302 break; 1304 break;
1303 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1304 if (dig_connector->linkb) 1306 if (dig->linkb)
1305 return 3; 1307 return 3;
1306 else 1308 else
1307 return 2; 1309 return 2;
1308 break; 1310 break;
1309 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1311 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1310 if (dig_connector->linkb) 1312 if (dig->linkb)
1311 return 5; 1313 return 5;
1312 else 1314 else
1313 return 4; 1315 return 4;
@@ -1641,6 +1643,7 @@ radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1641struct radeon_encoder_atom_dig * 1643struct radeon_encoder_atom_dig *
1642radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 1644radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1643{ 1645{
1646 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1644 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 1647 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1645 1648
1646 if (!dig) 1649 if (!dig)
@@ -1650,11 +1653,16 @@ radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1650 dig->coherent_mode = true; 1653 dig->coherent_mode = true;
1651 dig->dig_encoder = -1; 1654 dig->dig_encoder = -1;
1652 1655
1656 if (encoder_enum == 2)
1657 dig->linkb = true;
1658 else
1659 dig->linkb = false;
1660
1653 return dig; 1661 return dig;
1654} 1662}
1655 1663
1656void 1664void
1657radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) 1665radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1658{ 1666{
1659 struct radeon_device *rdev = dev->dev_private; 1667 struct radeon_device *rdev = dev->dev_private;
1660 struct drm_encoder *encoder; 1668 struct drm_encoder *encoder;
@@ -1663,7 +1671,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
1663 /* see if we already added it */ 1671 /* see if we already added it */
1664 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1672 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1665 radeon_encoder = to_radeon_encoder(encoder); 1673 radeon_encoder = to_radeon_encoder(encoder);
1666 if (radeon_encoder->encoder_id == encoder_id) { 1674 if (radeon_encoder->encoder_enum == encoder_enum) {
1667 radeon_encoder->devices |= supported_device; 1675 radeon_encoder->devices |= supported_device;
1668 return; 1676 return;
1669 } 1677 }
@@ -1691,7 +1699,8 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
1691 1699
1692 radeon_encoder->enc_priv = NULL; 1700 radeon_encoder->enc_priv = NULL;
1693 1701
1694 radeon_encoder->encoder_id = encoder_id; 1702 radeon_encoder->encoder_enum = encoder_enum;
1703 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1695 radeon_encoder->devices = supported_device; 1704 radeon_encoder->devices = supported_device;
1696 radeon_encoder->rmx_type = RMX_OFF; 1705 radeon_encoder->rmx_type = RMX_OFF;
1697 radeon_encoder->underscan_type = UNDERSCAN_OFF; 1706 radeon_encoder->underscan_type = UNDERSCAN_OFF;
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index dc1634bb0c11..11f4f30ded5d 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -118,7 +118,7 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
118 aligned_size = ALIGN(size, PAGE_SIZE); 118 aligned_size = ALIGN(size, PAGE_SIZE);
119 ret = radeon_gem_object_create(rdev, aligned_size, 0, 119 ret = radeon_gem_object_create(rdev, aligned_size, 0,
120 RADEON_GEM_DOMAIN_VRAM, 120 RADEON_GEM_DOMAIN_VRAM,
121 false, ttm_bo_type_kernel, 121 false, true,
122 &gobj); 122 &gobj);
123 if (ret) { 123 if (ret) {
124 printk(KERN_ERR "failed to allocate framebuffer (%d)\n", 124 printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index a72a3ee5d69b..c578f265b24c 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -226,7 +226,7 @@ int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
226 /* just do a BO wait for now */ 226 /* just do a BO wait for now */
227 gobj = drm_gem_object_lookup(dev, filp, args->handle); 227 gobj = drm_gem_object_lookup(dev, filp, args->handle);
228 if (gobj == NULL) { 228 if (gobj == NULL) {
229 return -EINVAL; 229 return -ENOENT;
230 } 230 }
231 robj = gobj->driver_private; 231 robj = gobj->driver_private;
232 232
@@ -245,7 +245,7 @@ int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
245 245
246 gobj = drm_gem_object_lookup(dev, filp, args->handle); 246 gobj = drm_gem_object_lookup(dev, filp, args->handle);
247 if (gobj == NULL) { 247 if (gobj == NULL) {
248 return -EINVAL; 248 return -ENOENT;
249 } 249 }
250 robj = gobj->driver_private; 250 robj = gobj->driver_private;
251 args->addr_ptr = radeon_bo_mmap_offset(robj); 251 args->addr_ptr = radeon_bo_mmap_offset(robj);
@@ -264,7 +264,7 @@ int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
264 264
265 gobj = drm_gem_object_lookup(dev, filp, args->handle); 265 gobj = drm_gem_object_lookup(dev, filp, args->handle);
266 if (gobj == NULL) { 266 if (gobj == NULL) {
267 return -EINVAL; 267 return -ENOENT;
268 } 268 }
269 robj = gobj->driver_private; 269 robj = gobj->driver_private;
270 r = radeon_bo_wait(robj, &cur_placement, true); 270 r = radeon_bo_wait(robj, &cur_placement, true);
@@ -294,7 +294,7 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
294 294
295 gobj = drm_gem_object_lookup(dev, filp, args->handle); 295 gobj = drm_gem_object_lookup(dev, filp, args->handle);
296 if (gobj == NULL) { 296 if (gobj == NULL) {
297 return -EINVAL; 297 return -ENOENT;
298 } 298 }
299 robj = gobj->driver_private; 299 robj = gobj->driver_private;
300 r = radeon_bo_wait(robj, NULL, false); 300 r = radeon_bo_wait(robj, NULL, false);
@@ -316,7 +316,7 @@ int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
316 DRM_DEBUG("%d \n", args->handle); 316 DRM_DEBUG("%d \n", args->handle);
317 gobj = drm_gem_object_lookup(dev, filp, args->handle); 317 gobj = drm_gem_object_lookup(dev, filp, args->handle);
318 if (gobj == NULL) 318 if (gobj == NULL)
319 return -EINVAL; 319 return -ENOENT;
320 robj = gobj->driver_private; 320 robj = gobj->driver_private;
321 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); 321 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch);
322 drm_gem_object_unreference_unlocked(gobj); 322 drm_gem_object_unreference_unlocked(gobj);
@@ -334,7 +334,7 @@ int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
334 DRM_DEBUG("\n"); 334 DRM_DEBUG("\n");
335 gobj = drm_gem_object_lookup(dev, filp, args->handle); 335 gobj = drm_gem_object_lookup(dev, filp, args->handle);
336 if (gobj == NULL) 336 if (gobj == NULL)
337 return -EINVAL; 337 return -ENOENT;
338 rbo = gobj->driver_private; 338 rbo = gobj->driver_private;
339 r = radeon_bo_reserve(rbo, false); 339 r = radeon_bo_reserve(rbo, false);
340 if (unlikely(r != 0)) 340 if (unlikely(r != 0))
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index 5def6f5dff38..0416804d8f30 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -52,6 +52,10 @@ bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
52 } 52 }
53 }; 53 };
54 54
55 /* on hw with routers, select right port */
56 if (radeon_connector->router.valid)
57 radeon_router_select_port(radeon_connector);
58
55 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); 59 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
56 if (ret == 2) 60 if (ret == 2)
57 return true; 61 return true;
@@ -95,6 +99,13 @@ static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
95 } 99 }
96 } 100 }
97 101
102 /* switch the pads to ddc mode */
103 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
104 temp = RREG32(rec->mask_clk_reg);
105 temp &= ~(1 << 16);
106 WREG32(rec->mask_clk_reg, temp);
107 }
108
98 /* clear the output pin values */ 109 /* clear the output pin values */
99 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 110 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
100 WREG32(rec->a_clk_reg, temp); 111 WREG32(rec->a_clk_reg, temp);
@@ -960,6 +971,59 @@ void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
960 kfree(i2c); 971 kfree(i2c);
961} 972}
962 973
974/* Add the default buses */
975void radeon_i2c_init(struct radeon_device *rdev)
976{
977 if (rdev->is_atom_bios)
978 radeon_atombios_i2c_init(rdev);
979 else
980 radeon_combios_i2c_init(rdev);
981}
982
983/* remove all the buses */
984void radeon_i2c_fini(struct radeon_device *rdev)
985{
986 int i;
987
988 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
989 if (rdev->i2c_bus[i]) {
990 radeon_i2c_destroy(rdev->i2c_bus[i]);
991 rdev->i2c_bus[i] = NULL;
992 }
993 }
994}
995
996/* Add additional buses */
997void radeon_i2c_add(struct radeon_device *rdev,
998 struct radeon_i2c_bus_rec *rec,
999 const char *name)
1000{
1001 struct drm_device *dev = rdev->ddev;
1002 int i;
1003
1004 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1005 if (!rdev->i2c_bus[i]) {
1006 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1007 return;
1008 }
1009 }
1010}
1011
1012/* looks up bus based on id */
1013struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1014 struct radeon_i2c_bus_rec *i2c_bus)
1015{
1016 int i;
1017
1018 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1019 if (rdev->i2c_bus[i] &&
1020 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1021 return rdev->i2c_bus[i];
1022 }
1023 }
1024 return NULL;
1025}
1026
963struct drm_encoder *radeon_best_encoder(struct drm_connector *connector) 1027struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
964{ 1028{
965 return NULL; 1029 return NULL;
@@ -1020,3 +1084,28 @@ void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1020 addr, val); 1084 addr, val);
1021} 1085}
1022 1086
1087/* router switching */
1088void radeon_router_select_port(struct radeon_connector *radeon_connector)
1089{
1090 u8 val;
1091
1092 if (!radeon_connector->router.valid)
1093 return;
1094
1095 radeon_i2c_get_byte(radeon_connector->router_bus,
1096 radeon_connector->router.i2c_addr,
1097 0x3, &val);
1098 val &= radeon_connector->router.mux_control_pin;
1099 radeon_i2c_put_byte(radeon_connector->router_bus,
1100 radeon_connector->router.i2c_addr,
1101 0x3, val);
1102 radeon_i2c_get_byte(radeon_connector->router_bus,
1103 radeon_connector->router.i2c_addr,
1104 0x1, &val);
1105 val &= radeon_connector->router.mux_control_pin;
1106 val |= radeon_connector->router.mux_state;
1107 radeon_i2c_put_byte(radeon_connector->router_bus,
1108 radeon_connector->router.i2c_addr,
1109 0x1, val);
1110}
1111
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 059bfa4098d7..a108c7ed14f5 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -121,11 +121,12 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
121 * chips. Disable MSI on them for now. 121 * chips. Disable MSI on them for now.
122 */ 122 */
123 if ((rdev->family >= CHIP_RV380) && 123 if ((rdev->family >= CHIP_RV380) &&
124 (!(rdev->flags & RADEON_IS_IGP))) { 124 (!(rdev->flags & RADEON_IS_IGP)) &&
125 (!(rdev->flags & RADEON_IS_AGP))) {
125 int ret = pci_enable_msi(rdev->pdev); 126 int ret = pci_enable_msi(rdev->pdev);
126 if (!ret) { 127 if (!ret) {
127 rdev->msi_enabled = 1; 128 rdev->msi_enabled = 1;
128 DRM_INFO("radeon: using MSI.\n"); 129 dev_info(rdev->dev, "radeon: using MSI.\n");
129 } 130 }
130 } 131 }
131 rdev->irq.installed = true; 132 rdev->irq.installed = true;
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index ddcd3b13f151..5eee3c41d124 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -112,7 +112,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
112 112
113 info = data; 113 info = data;
114 value_ptr = (uint32_t *)((unsigned long)info->value); 114 value_ptr = (uint32_t *)((unsigned long)info->value);
115 value = *value_ptr; 115 if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
116 return -EFAULT;
117
116 switch (info->request) { 118 switch (info->request) {
117 case RADEON_INFO_DEVICE_ID: 119 case RADEON_INFO_DEVICE_ID:
118 value = dev->pci_device; 120 value = dev->pci_device;
@@ -159,14 +161,29 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
159 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 161 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
160 return -EINVAL; 162 return -EINVAL;
161 } 163 }
164 break;
162 case RADEON_INFO_WANT_HYPERZ: 165 case RADEON_INFO_WANT_HYPERZ:
166 /* The "value" here is both an input and output parameter.
167 * If the input value is 1, filp requests hyper-z access.
168 * If the input value is 0, filp revokes its hyper-z access.
169 *
170 * When returning, the value is 1 if filp owns hyper-z access,
171 * 0 otherwise. */
172 if (value >= 2) {
173 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
174 return -EINVAL;
175 }
163 mutex_lock(&dev->struct_mutex); 176 mutex_lock(&dev->struct_mutex);
164 if (rdev->hyperz_filp) 177 if (value == 1) {
165 value = 0; 178 /* wants hyper-z */
166 else { 179 if (!rdev->hyperz_filp)
167 rdev->hyperz_filp = filp; 180 rdev->hyperz_filp = filp;
168 value = 1; 181 } else if (value == 0) {
182 /* revokes hyper-z */
183 if (rdev->hyperz_filp == filp)
184 rdev->hyperz_filp = NULL;
169 } 185 }
186 value = rdev->hyperz_filp == filp ? 1 : 0;
170 mutex_unlock(&dev->struct_mutex); 187 mutex_unlock(&dev->struct_mutex);
171 break; 188 break;
172 default: 189 default:
@@ -307,45 +324,45 @@ KMS_INVALID_IOCTL(radeon_surface_free_kms)
307 324
308 325
309struct drm_ioctl_desc radeon_ioctls_kms[] = { 326struct drm_ioctl_desc radeon_ioctls_kms[] = {
310 DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 327 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
311 DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 328 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
312 DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 329 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
313 DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 330 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
314 DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), 331 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
315 DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), 332 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
316 DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), 333 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
317 DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), 334 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
318 DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), 335 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
319 DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), 336 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
320 DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), 337 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
321 DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), 338 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
322 DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), 339 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
323 DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), 340 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
324 DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 341 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
325 DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), 342 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
326 DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), 343 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
327 DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), 344 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
328 DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), 345 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
329 DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), 346 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
330 DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), 347 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
331 DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 348 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
332 DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), 349 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
333 DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), 350 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
334 DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), 351 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
335 DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), 352 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
336 DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), 353 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
337 /* KMS */ 354 /* KMS */
338 DRM_IOCTL_DEF(DRM_RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED), 355 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
339 DRM_IOCTL_DEF(DRM_RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED), 356 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
340 DRM_IOCTL_DEF(DRM_RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED), 357 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
341 DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED), 358 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
342 DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), 359 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
343 DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), 360 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
344 DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED), 361 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
345 DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED), 362 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
346 DRM_IOCTL_DEF(DRM_RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED), 363 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
347 DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), 364 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
348 DRM_IOCTL_DEF(DRM_RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), 365 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
349 DRM_IOCTL_DEF(DRM_RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), 366 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
350}; 367};
351int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); 368int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 989df519a1e4..305049afde15 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -272,7 +272,7 @@ static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
272 if (!ref_div) 272 if (!ref_div)
273 return 1; 273 return 1;
274 274
275 vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div; 275 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
276 276
277 /* 277 /*
278 * This is horribly crude: the VCO frequency range is divided into 278 * This is horribly crude: the VCO frequency range is divided into
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index b8149cbc0c70..0b8397000f4c 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -1345,7 +1345,7 @@ static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct ra
1345} 1345}
1346 1346
1347void 1347void
1348radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) 1348radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1349{ 1349{
1350 struct radeon_device *rdev = dev->dev_private; 1350 struct radeon_device *rdev = dev->dev_private;
1351 struct drm_encoder *encoder; 1351 struct drm_encoder *encoder;
@@ -1354,7 +1354,7 @@ radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t
1354 /* see if we already added it */ 1354 /* see if we already added it */
1355 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1355 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1356 radeon_encoder = to_radeon_encoder(encoder); 1356 radeon_encoder = to_radeon_encoder(encoder);
1357 if (radeon_encoder->encoder_id == encoder_id) { 1357 if (radeon_encoder->encoder_enum == encoder_enum) {
1358 radeon_encoder->devices |= supported_device; 1358 radeon_encoder->devices |= supported_device;
1359 return; 1359 return;
1360 } 1360 }
@@ -1374,7 +1374,8 @@ radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t
1374 1374
1375 radeon_encoder->enc_priv = NULL; 1375 radeon_encoder->enc_priv = NULL;
1376 1376
1377 radeon_encoder->encoder_id = encoder_id; 1377 radeon_encoder->encoder_enum = encoder_enum;
1378 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1378 radeon_encoder->devices = supported_device; 1379 radeon_encoder->devices = supported_device;
1379 radeon_encoder->rmx_type = RMX_OFF; 1380 radeon_encoder->rmx_type = RMX_OFF;
1380 1381
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 71aea4037e90..8f93e2b4b0c8 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -82,6 +82,8 @@ enum radeon_hpd_id {
82 RADEON_HPD_NONE = 0xff, 82 RADEON_HPD_NONE = 0xff,
83}; 83};
84 84
85#define RADEON_MAX_I2C_BUS 16
86
85/* radeon gpio-based i2c 87/* radeon gpio-based i2c
86 * 1. "mask" reg and bits 88 * 1. "mask" reg and bits
87 * grabs the gpio pins for software use 89 * grabs the gpio pins for software use
@@ -340,6 +342,7 @@ struct radeon_atom_ss {
340}; 342};
341 343
342struct radeon_encoder_atom_dig { 344struct radeon_encoder_atom_dig {
345 bool linkb;
343 /* atom dig */ 346 /* atom dig */
344 bool coherent_mode; 347 bool coherent_mode;
345 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */ 348 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
@@ -358,6 +361,7 @@ struct radeon_encoder_atom_dac {
358 361
359struct radeon_encoder { 362struct radeon_encoder {
360 struct drm_encoder base; 363 struct drm_encoder base;
364 uint32_t encoder_enum;
361 uint32_t encoder_id; 365 uint32_t encoder_id;
362 uint32_t devices; 366 uint32_t devices;
363 uint32_t active_device; 367 uint32_t active_device;
@@ -376,7 +380,6 @@ struct radeon_encoder {
376 380
377struct radeon_connector_atom_dig { 381struct radeon_connector_atom_dig {
378 uint32_t igp_lane_info; 382 uint32_t igp_lane_info;
379 bool linkb;
380 /* displayport */ 383 /* displayport */
381 struct radeon_i2c_chan *dp_i2c_bus; 384 struct radeon_i2c_chan *dp_i2c_bus;
382 u8 dpcd[8]; 385 u8 dpcd[8];
@@ -398,6 +401,16 @@ struct radeon_hpd {
398 struct radeon_gpio_rec gpio; 401 struct radeon_gpio_rec gpio;
399}; 402};
400 403
404struct radeon_router {
405 bool valid;
406 u32 router_id;
407 struct radeon_i2c_bus_rec i2c_info;
408 u8 i2c_addr;
409 u8 mux_type;
410 u8 mux_control_pin;
411 u8 mux_state;
412};
413
401struct radeon_connector { 414struct radeon_connector {
402 struct drm_connector base; 415 struct drm_connector base;
403 uint32_t connector_id; 416 uint32_t connector_id;
@@ -413,6 +426,8 @@ struct radeon_connector {
413 bool dac_load_detect; 426 bool dac_load_detect;
414 uint16_t connector_object_id; 427 uint16_t connector_object_id;
415 struct radeon_hpd hpd; 428 struct radeon_hpd hpd;
429 struct radeon_router router;
430 struct radeon_i2c_chan *router_bus;
416}; 431};
417 432
418struct radeon_framebuffer { 433struct radeon_framebuffer {
@@ -445,6 +460,15 @@ extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
445extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 460extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
446 uint8_t write_byte, uint8_t *read_byte); 461 uint8_t write_byte, uint8_t *read_byte);
447 462
463extern void radeon_i2c_init(struct radeon_device *rdev);
464extern void radeon_i2c_fini(struct radeon_device *rdev);
465extern void radeon_combios_i2c_init(struct radeon_device *rdev);
466extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
467extern void radeon_i2c_add(struct radeon_device *rdev,
468 struct radeon_i2c_bus_rec *rec,
469 const char *name);
470extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
471 struct radeon_i2c_bus_rec *i2c_bus);
448extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 472extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
449 struct radeon_i2c_bus_rec *rec, 473 struct radeon_i2c_bus_rec *rec,
450 const char *name); 474 const char *name);
@@ -460,6 +484,7 @@ extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
460 u8 slave_addr, 484 u8 slave_addr,
461 u8 addr, 485 u8 addr,
462 u8 val); 486 u8 val);
487extern void radeon_router_select_port(struct radeon_connector *radeon_connector);
463extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); 488extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
464extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 489extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
465 490
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 95f8b3a3c43d..477ba673e1b4 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -226,6 +226,11 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev)
226{ 226{
227 int i; 227 int i;
228 228
229 /* no need to take locks, etc. if nothing's going to change */
230 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
231 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
232 return;
233
229 mutex_lock(&rdev->ddev->struct_mutex); 234 mutex_lock(&rdev->ddev->struct_mutex);
230 mutex_lock(&rdev->vram_mutex); 235 mutex_lock(&rdev->vram_mutex);
231 mutex_lock(&rdev->cp.mutex); 236 mutex_lock(&rdev->cp.mutex);
@@ -472,9 +477,9 @@ static const struct attribute_group hwmon_attrgroup = {
472 .attrs = hwmon_attributes, 477 .attrs = hwmon_attributes,
473}; 478};
474 479
475static void radeon_hwmon_init(struct radeon_device *rdev) 480static int radeon_hwmon_init(struct radeon_device *rdev)
476{ 481{
477 int err; 482 int err = 0;
478 483
479 rdev->pm.int_hwmon_dev = NULL; 484 rdev->pm.int_hwmon_dev = NULL;
480 485
@@ -483,15 +488,26 @@ static void radeon_hwmon_init(struct radeon_device *rdev)
483 case THERMAL_TYPE_RV770: 488 case THERMAL_TYPE_RV770:
484 case THERMAL_TYPE_EVERGREEN: 489 case THERMAL_TYPE_EVERGREEN:
485 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev); 490 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
491 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
492 err = PTR_ERR(rdev->pm.int_hwmon_dev);
493 dev_err(rdev->dev,
494 "Unable to register hwmon device: %d\n", err);
495 break;
496 }
486 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev); 497 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
487 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj, 498 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
488 &hwmon_attrgroup); 499 &hwmon_attrgroup);
489 if (err) 500 if (err) {
490 DRM_ERROR("Unable to create hwmon sysfs file: %d\n", err); 501 dev_err(rdev->dev,
502 "Unable to create hwmon sysfs file: %d\n", err);
503 hwmon_device_unregister(rdev->dev);
504 }
491 break; 505 break;
492 default: 506 default:
493 break; 507 break;
494 } 508 }
509
510 return err;
495} 511}
496 512
497static void radeon_hwmon_fini(struct radeon_device *rdev) 513static void radeon_hwmon_fini(struct radeon_device *rdev)
@@ -540,6 +556,7 @@ void radeon_pm_resume(struct radeon_device *rdev)
540int radeon_pm_init(struct radeon_device *rdev) 556int radeon_pm_init(struct radeon_device *rdev)
541{ 557{
542 int ret; 558 int ret;
559
543 /* default to profile method */ 560 /* default to profile method */
544 rdev->pm.pm_method = PM_METHOD_PROFILE; 561 rdev->pm.pm_method = PM_METHOD_PROFILE;
545 rdev->pm.profile = PM_PROFILE_DEFAULT; 562 rdev->pm.profile = PM_PROFILE_DEFAULT;
@@ -561,7 +578,9 @@ int radeon_pm_init(struct radeon_device *rdev)
561 } 578 }
562 579
563 /* set up the internal thermal sensor if applicable */ 580 /* set up the internal thermal sensor if applicable */
564 radeon_hwmon_init(rdev); 581 ret = radeon_hwmon_init(rdev);
582 if (ret)
583 return ret;
565 if (rdev->pm.num_power_states > 1) { 584 if (rdev->pm.num_power_states > 1) {
566 /* where's the best place to put these? */ 585 /* where's the best place to put these? */
567 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 586 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index b3ba44c0a818..4ae5a3d1074e 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -3228,34 +3228,34 @@ void radeon_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
3228} 3228}
3229 3229
3230struct drm_ioctl_desc radeon_ioctls[] = { 3230struct drm_ioctl_desc radeon_ioctls[] = {
3231 DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 3231 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3232 DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 3232 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3233 DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 3233 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3234 DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 3234 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3235 DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle, DRM_AUTH), 3235 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle, DRM_AUTH),
3236 DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume, DRM_AUTH), 3236 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume, DRM_AUTH),
3237 DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset, DRM_AUTH), 3237 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset, DRM_AUTH),
3238 DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen, DRM_AUTH), 3238 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen, DRM_AUTH),
3239 DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap, DRM_AUTH), 3239 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap, DRM_AUTH),
3240 DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear, DRM_AUTH), 3240 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear, DRM_AUTH),
3241 DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex, DRM_AUTH), 3241 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex, DRM_AUTH),
3242 DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices, DRM_AUTH), 3242 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices, DRM_AUTH),
3243 DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH), 3243 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH),
3244 DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH), 3244 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH),
3245 DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 3245 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3246 DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH), 3246 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH),
3247 DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH), 3247 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH),
3248 DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH), 3248 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH),
3249 DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip, DRM_AUTH), 3249 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip, DRM_AUTH),
3250 DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc, DRM_AUTH), 3250 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc, DRM_AUTH),
3251 DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free, DRM_AUTH), 3251 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free, DRM_AUTH),
3252 DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 3252 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3253 DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit, DRM_AUTH), 3253 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit, DRM_AUTH),
3254 DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH), 3254 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH),
3255 DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH), 3255 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH),
3256 DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH), 3256 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH),
3257 DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH), 3257 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH),
3258 DRM_IOCTL_DEF(DRM_RADEON_CS, r600_cs_legacy_ioctl, DRM_AUTH) 3258 DRM_IOCTL_DEF_DRV(RADEON_CS, r600_cs_legacy_ioctl, DRM_AUTH)
3259}; 3259};
3260 3260
3261int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); 3261int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
index 8293855f5f0d..b3f9f1d92005 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rv515
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -316,6 +316,7 @@ rv515 0x6d40
3160x4BD0 FG_FOG_COLOR_B 3160x4BD0 FG_FOG_COLOR_B
3170x4BD4 FG_ALPHA_FUNC 3170x4BD4 FG_ALPHA_FUNC
3180x4BD8 FG_DEPTH_SRC 3180x4BD8 FG_DEPTH_SRC
3190x4BE0 FG_ALPHA_VALUE
3190x4C00 US_ALU_CONST_R_0 3200x4C00 US_ALU_CONST_R_0
3200x4C04 US_ALU_CONST_G_0 3210x4C04 US_ALU_CONST_G_0
3210x4C08 US_ALU_CONST_B_0 3220x4C08 US_ALU_CONST_B_0
diff --git a/drivers/gpu/drm/savage/savage_bci.c b/drivers/gpu/drm/savage/savage_bci.c
index f576232846c3..6756c97899f1 100644
--- a/drivers/gpu/drm/savage/savage_bci.c
+++ b/drivers/gpu/drm/savage/savage_bci.c
@@ -1082,10 +1082,10 @@ void savage_reclaim_buffers(struct drm_device *dev, struct drm_file *file_priv)
1082} 1082}
1083 1083
1084struct drm_ioctl_desc savage_ioctls[] = { 1084struct drm_ioctl_desc savage_ioctls[] = {
1085 DRM_IOCTL_DEF(DRM_SAVAGE_BCI_INIT, savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1085 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_INIT, savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1086 DRM_IOCTL_DEF(DRM_SAVAGE_BCI_CMDBUF, savage_bci_cmdbuf, DRM_AUTH), 1086 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_CMDBUF, savage_bci_cmdbuf, DRM_AUTH),
1087 DRM_IOCTL_DEF(DRM_SAVAGE_BCI_EVENT_EMIT, savage_bci_event_emit, DRM_AUTH), 1087 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_EVENT_EMIT, savage_bci_event_emit, DRM_AUTH),
1088 DRM_IOCTL_DEF(DRM_SAVAGE_BCI_EVENT_WAIT, savage_bci_event_wait, DRM_AUTH), 1088 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_EVENT_WAIT, savage_bci_event_wait, DRM_AUTH),
1089}; 1089};
1090 1090
1091int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls); 1091int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls);
diff --git a/drivers/gpu/drm/sis/sis_mm.c b/drivers/gpu/drm/sis/sis_mm.c
index 07d0f2979cac..7fe2b63412ce 100644
--- a/drivers/gpu/drm/sis/sis_mm.c
+++ b/drivers/gpu/drm/sis/sis_mm.c
@@ -320,12 +320,12 @@ void sis_reclaim_buffers_locked(struct drm_device *dev,
320} 320}
321 321
322struct drm_ioctl_desc sis_ioctls[] = { 322struct drm_ioctl_desc sis_ioctls[] = {
323 DRM_IOCTL_DEF(DRM_SIS_FB_ALLOC, sis_fb_alloc, DRM_AUTH), 323 DRM_IOCTL_DEF_DRV(SIS_FB_ALLOC, sis_fb_alloc, DRM_AUTH),
324 DRM_IOCTL_DEF(DRM_SIS_FB_FREE, sis_drm_free, DRM_AUTH), 324 DRM_IOCTL_DEF_DRV(SIS_FB_FREE, sis_drm_free, DRM_AUTH),
325 DRM_IOCTL_DEF(DRM_SIS_AGP_INIT, sis_ioctl_agp_init, DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY), 325 DRM_IOCTL_DEF_DRV(SIS_AGP_INIT, sis_ioctl_agp_init, DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
326 DRM_IOCTL_DEF(DRM_SIS_AGP_ALLOC, sis_ioctl_agp_alloc, DRM_AUTH), 326 DRM_IOCTL_DEF_DRV(SIS_AGP_ALLOC, sis_ioctl_agp_alloc, DRM_AUTH),
327 DRM_IOCTL_DEF(DRM_SIS_AGP_FREE, sis_drm_free, DRM_AUTH), 327 DRM_IOCTL_DEF_DRV(SIS_AGP_FREE, sis_drm_free, DRM_AUTH),
328 DRM_IOCTL_DEF(DRM_SIS_FB_INIT, sis_fb_init, DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY), 328 DRM_IOCTL_DEF_DRV(SIS_FB_INIT, sis_fb_init, DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
329}; 329};
330 330
331int sis_max_ioctl = DRM_ARRAY_SIZE(sis_ioctls); 331int sis_max_ioctl = DRM_ARRAY_SIZE(sis_ioctls);
diff --git a/drivers/gpu/drm/via/via_dma.c b/drivers/gpu/drm/via/via_dma.c
index 68dda74a50ae..cc0ffa9abd00 100644
--- a/drivers/gpu/drm/via/via_dma.c
+++ b/drivers/gpu/drm/via/via_dma.c
@@ -722,20 +722,20 @@ static int via_cmdbuf_size(struct drm_device *dev, void *data, struct drm_file *
722} 722}
723 723
724struct drm_ioctl_desc via_ioctls[] = { 724struct drm_ioctl_desc via_ioctls[] = {
725 DRM_IOCTL_DEF(DRM_VIA_ALLOCMEM, via_mem_alloc, DRM_AUTH), 725 DRM_IOCTL_DEF_DRV(VIA_ALLOCMEM, via_mem_alloc, DRM_AUTH),
726 DRM_IOCTL_DEF(DRM_VIA_FREEMEM, via_mem_free, DRM_AUTH), 726 DRM_IOCTL_DEF_DRV(VIA_FREEMEM, via_mem_free, DRM_AUTH),
727 DRM_IOCTL_DEF(DRM_VIA_AGP_INIT, via_agp_init, DRM_AUTH|DRM_MASTER), 727 DRM_IOCTL_DEF_DRV(VIA_AGP_INIT, via_agp_init, DRM_AUTH|DRM_MASTER),
728 DRM_IOCTL_DEF(DRM_VIA_FB_INIT, via_fb_init, DRM_AUTH|DRM_MASTER), 728 DRM_IOCTL_DEF_DRV(VIA_FB_INIT, via_fb_init, DRM_AUTH|DRM_MASTER),
729 DRM_IOCTL_DEF(DRM_VIA_MAP_INIT, via_map_init, DRM_AUTH|DRM_MASTER), 729 DRM_IOCTL_DEF_DRV(VIA_MAP_INIT, via_map_init, DRM_AUTH|DRM_MASTER),
730 DRM_IOCTL_DEF(DRM_VIA_DEC_FUTEX, via_decoder_futex, DRM_AUTH), 730 DRM_IOCTL_DEF_DRV(VIA_DEC_FUTEX, via_decoder_futex, DRM_AUTH),
731 DRM_IOCTL_DEF(DRM_VIA_DMA_INIT, via_dma_init, DRM_AUTH), 731 DRM_IOCTL_DEF_DRV(VIA_DMA_INIT, via_dma_init, DRM_AUTH),
732 DRM_IOCTL_DEF(DRM_VIA_CMDBUFFER, via_cmdbuffer, DRM_AUTH), 732 DRM_IOCTL_DEF_DRV(VIA_CMDBUFFER, via_cmdbuffer, DRM_AUTH),
733 DRM_IOCTL_DEF(DRM_VIA_FLUSH, via_flush_ioctl, DRM_AUTH), 733 DRM_IOCTL_DEF_DRV(VIA_FLUSH, via_flush_ioctl, DRM_AUTH),
734 DRM_IOCTL_DEF(DRM_VIA_PCICMD, via_pci_cmdbuffer, DRM_AUTH), 734 DRM_IOCTL_DEF_DRV(VIA_PCICMD, via_pci_cmdbuffer, DRM_AUTH),
735 DRM_IOCTL_DEF(DRM_VIA_CMDBUF_SIZE, via_cmdbuf_size, DRM_AUTH), 735 DRM_IOCTL_DEF_DRV(VIA_CMDBUF_SIZE, via_cmdbuf_size, DRM_AUTH),
736 DRM_IOCTL_DEF(DRM_VIA_WAIT_IRQ, via_wait_irq, DRM_AUTH), 736 DRM_IOCTL_DEF_DRV(VIA_WAIT_IRQ, via_wait_irq, DRM_AUTH),
737 DRM_IOCTL_DEF(DRM_VIA_DMA_BLIT, via_dma_blit, DRM_AUTH), 737 DRM_IOCTL_DEF_DRV(VIA_DMA_BLIT, via_dma_blit, DRM_AUTH),
738 DRM_IOCTL_DEF(DRM_VIA_BLIT_SYNC, via_dma_blit_sync, DRM_AUTH) 738 DRM_IOCTL_DEF_DRV(VIA_BLIT_SYNC, via_dma_blit_sync, DRM_AUTH)
739}; 739};
740 740
741int via_max_ioctl = DRM_ARRAY_SIZE(via_ioctls); 741int via_max_ioctl = DRM_ARRAY_SIZE(via_ioctls);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 9dd395b90216..72ec2e2b6e97 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -99,47 +99,47 @@
99 */ 99 */
100 100
101#define VMW_IOCTL_DEF(ioctl, func, flags) \ 101#define VMW_IOCTL_DEF(ioctl, func, flags) \
102 [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func} 102 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
103 103
104/** 104/**
105 * Ioctl definitions. 105 * Ioctl definitions.
106 */ 106 */
107 107
108static struct drm_ioctl_desc vmw_ioctls[] = { 108static struct drm_ioctl_desc vmw_ioctls[] = {
109 VMW_IOCTL_DEF(DRM_IOCTL_VMW_GET_PARAM, vmw_getparam_ioctl, 109 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
110 DRM_AUTH | DRM_UNLOCKED), 110 DRM_AUTH | DRM_UNLOCKED),
111 VMW_IOCTL_DEF(DRM_IOCTL_VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, 111 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
112 DRM_AUTH | DRM_UNLOCKED), 112 DRM_AUTH | DRM_UNLOCKED),
113 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, 113 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
114 DRM_AUTH | DRM_UNLOCKED), 114 DRM_AUTH | DRM_UNLOCKED),
115 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CURSOR_BYPASS, 115 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
116 vmw_kms_cursor_bypass_ioctl, 116 vmw_kms_cursor_bypass_ioctl,
117 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 117 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
118 118
119 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CONTROL_STREAM, vmw_overlay_ioctl, 119 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
120 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 120 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
121 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 121 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
122 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 122 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
123 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 123 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
124 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 124 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
125 125
126 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 126 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
127 DRM_AUTH | DRM_UNLOCKED), 127 DRM_AUTH | DRM_UNLOCKED),
128 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 128 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
129 DRM_AUTH | DRM_UNLOCKED), 129 DRM_AUTH | DRM_UNLOCKED),
130 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 130 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
131 DRM_AUTH | DRM_UNLOCKED), 131 DRM_AUTH | DRM_UNLOCKED),
132 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 132 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
133 DRM_AUTH | DRM_UNLOCKED), 133 DRM_AUTH | DRM_UNLOCKED),
134 VMW_IOCTL_DEF(DRM_IOCTL_VMW_REF_SURFACE, vmw_surface_reference_ioctl, 134 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
135 DRM_AUTH | DRM_UNLOCKED), 135 DRM_AUTH | DRM_UNLOCKED),
136 VMW_IOCTL_DEF(DRM_IOCTL_VMW_EXECBUF, vmw_execbuf_ioctl, 136 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
137 DRM_AUTH | DRM_UNLOCKED), 137 DRM_AUTH | DRM_UNLOCKED),
138 VMW_IOCTL_DEF(DRM_IOCTL_VMW_FIFO_DEBUG, vmw_fifo_debug_ioctl, 138 VMW_IOCTL_DEF(VMW_FIFO_DEBUG, vmw_fifo_debug_ioctl,
139 DRM_AUTH | DRM_ROOT_ONLY | DRM_MASTER | DRM_UNLOCKED), 139 DRM_AUTH | DRM_ROOT_ONLY | DRM_MASTER | DRM_UNLOCKED),
140 VMW_IOCTL_DEF(DRM_IOCTL_VMW_FENCE_WAIT, vmw_fence_wait_ioctl, 140 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_wait_ioctl,
141 DRM_AUTH | DRM_UNLOCKED), 141 DRM_AUTH | DRM_UNLOCKED),
142 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UPDATE_LAYOUT, vmw_kms_update_layout_ioctl, 142 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, vmw_kms_update_layout_ioctl,
143 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED) 143 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED)
144}; 144};
145 145
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 437ac786277a..64d7f47df868 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -737,7 +737,7 @@ static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
737 737
738 if (ret) { 738 if (ret) {
739 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret); 739 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
740 return NULL; 740 return ERR_PTR(ret);
741 } 741 }
742 return &vfb->base; 742 return &vfb->base;
743 743
@@ -747,7 +747,7 @@ try_dmabuf:
747 ret = vmw_user_dmabuf_lookup(tfile, mode_cmd->handle, &bo); 747 ret = vmw_user_dmabuf_lookup(tfile, mode_cmd->handle, &bo);
748 if (ret) { 748 if (ret) {
749 DRM_ERROR("failed to find buffer: %i\n", ret); 749 DRM_ERROR("failed to find buffer: %i\n", ret);
750 return NULL; 750 return ERR_PTR(-ENOENT);
751 } 751 }
752 752
753 ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb, 753 ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
@@ -758,7 +758,7 @@ try_dmabuf:
758 758
759 if (ret) { 759 if (ret) {
760 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret); 760 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
761 return NULL; 761 return ERR_PTR(ret);
762 } 762 }
763 763
764 return &vfb->base; 764 return &vfb->base;
@@ -768,7 +768,7 @@ err_not_scanout:
768 /* vmw_user_surface_lookup takes one ref */ 768 /* vmw_user_surface_lookup takes one ref */
769 vmw_surface_unreference(&surface); 769 vmw_surface_unreference(&surface);
770 770
771 return NULL; 771 return ERR_PTR(-EINVAL);
772} 772}
773 773
774static struct drm_mode_config_funcs vmw_kms_funcs = { 774static struct drm_mode_config_funcs vmw_kms_funcs = {
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
index cfaf690a5b2f..2ff5cf78235f 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
@@ -79,7 +79,7 @@ static void vmw_ldu_crtc_restore(struct drm_crtc *crtc)
79 79
80static void vmw_ldu_crtc_gamma_set(struct drm_crtc *crtc, 80static void vmw_ldu_crtc_gamma_set(struct drm_crtc *crtc,
81 u16 *r, u16 *g, u16 *b, 81 u16 *r, u16 *g, u16 *b,
82 uint32_t size) 82 uint32_t start, uint32_t size)
83{ 83{
84} 84}
85 85
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 00:42:04 -0500