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-rw-r--r--drivers/net/tg3.c46
-rw-r--r--drivers/net/tg3.h4
2 files changed, 50 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 1c680ff51013..afcc593108ce 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1162,6 +1162,52 @@ static void tg3_mdio_fini(struct tg3 *tp)
1162 } 1162 }
1163} 1163}
1164 1164
1165static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1166{
1167 int err;
1168
1169 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1170 if (err)
1171 goto done;
1172
1173 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1174 if (err)
1175 goto done;
1176
1177 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1178 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1179 if (err)
1180 goto done;
1181
1182 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1183
1184done:
1185 return err;
1186}
1187
1188static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1189{
1190 int err;
1191
1192 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1193 if (err)
1194 goto done;
1195
1196 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1197 if (err)
1198 goto done;
1199
1200 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1201 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1202 if (err)
1203 goto done;
1204
1205 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1206
1207done:
1208 return err;
1209}
1210
1165/* tp->lock is held. */ 1211/* tp->lock is held. */
1166static inline void tg3_generate_fw_event(struct tg3 *tp) 1212static inline void tg3_generate_fw_event(struct tg3 *tp)
1167{ 1213{
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 89553c42fd08..99fc30680217 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2061,6 +2061,10 @@
2061#define MII_TG3_CTRL_AS_MASTER 0x0800 2061#define MII_TG3_CTRL_AS_MASTER 0x0800
2062#define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000 2062#define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
2063 2063
2064#define MII_TG3_MMD_CTRL 0x0d /* MMD Access Control register */
2065#define MII_TG3_MMD_CTRL_DATA_NOINC 0x4000
2066#define MII_TG3_MMD_ADDRESS 0x0e /* MMD Address Data register */
2067
2064#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */ 2068#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
2065#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001 2069#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
2066#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002 2070#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002