diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/staging/et131x/et1310_address_map.h | 34 | ||||
-rw-r--r-- | drivers/staging/et131x/et1310_tx.c | 19 |
2 files changed, 17 insertions, 36 deletions
diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index 6c69a15dbbe5..6294d3814e72 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h | |||
@@ -173,31 +173,15 @@ typedef struct _GLOBAL_t { /* Location: */ | |||
173 | /* START OF TXDMA REGISTER ADDRESS MAP */ | 173 | /* START OF TXDMA REGISTER ADDRESS MAP */ |
174 | 174 | ||
175 | /* | 175 | /* |
176 | * structure for txdma control status reg in txdma address map | 176 | * txdma control status reg at address 0x1000 |
177 | * located at address 0x1000 | ||
178 | */ | 177 | */ |
179 | typedef union _TXDMA_CSR_t { | 178 | |
180 | u32 value; | 179 | #define ET_TXDMA_CSR_HALT 0x00000001 |
181 | struct { | 180 | #define ET_TXDMA_DROP_TLP 0x00000002 |
182 | #ifdef _BIT_FIELDS_HTOL | 181 | #define ET_TXDMA_CACHE_THRS 0x000000F0 |
183 | u32 unused2:19; /* bits 13-31 */ | 182 | #define ET_TXDMA_CACHE_SHIFT 4 |
184 | u32 traffic_class:4; /* bits 9-12 */ | 183 | #define ET_TXDMA_SNGL_EPKT 0x00000100 |
185 | u32 sngl_epkt_mode:1; /* bit 8 */ | 184 | #define ET_TXDMA_CLASS 0x00001E00 |
186 | u32 cache_thrshld:4; /* bits 4-7 */ | ||
187 | u32 unused1:2; /* bits 2-3 */ | ||
188 | u32 drop_TLP_disable:1; /* bit 1 */ | ||
189 | u32 halt:1; /* bit 0 */ | ||
190 | #else | ||
191 | u32 halt:1; /* bit 0 */ | ||
192 | u32 drop_TLP_disable:1; /* bit 1 */ | ||
193 | u32 unused1:2; /* bits 2-3 */ | ||
194 | u32 cache_thrshld:4; /* bits 4-7 */ | ||
195 | u32 sngl_epkt_mode:1; /* bit 8 */ | ||
196 | u32 traffic_class:4; /* bits 9-12 */ | ||
197 | u32 unused2:19; /* bits 13-31 */ | ||
198 | #endif | ||
199 | } bits; | ||
200 | } TXDMA_CSR_t, *PTXDMA_CSR_t; | ||
201 | 185 | ||
202 | /* | 186 | /* |
203 | * structure for txdma packet ring base address hi reg in txdma address map | 187 | * structure for txdma packet ring base address hi reg in txdma address map |
@@ -274,7 +258,7 @@ extern inline void add_10bit(u32 *v, int n) | |||
274 | * Located at address 0x1000 | 258 | * Located at address 0x1000 |
275 | */ | 259 | */ |
276 | typedef struct _TXDMA_t { /* Location: */ | 260 | typedef struct _TXDMA_t { /* Location: */ |
277 | TXDMA_CSR_t csr; /* 0x1000 */ | 261 | u32 csr; /* 0x1000 */ |
278 | u32 pr_base_hi; /* 0x1004 */ | 262 | u32 pr_base_hi; /* 0x1004 */ |
279 | u32 pr_base_lo; /* 0x1008 */ | 263 | u32 pr_base_lo; /* 0x1008 */ |
280 | TXDMA_PR_NUM_DES_t pr_num_des; /* 0x100C */ | 264 | TXDMA_PR_NUM_DES_t pr_num_des; /* 0x100C */ |
diff --git a/drivers/staging/et131x/et1310_tx.c b/drivers/staging/et131x/et1310_tx.c index 387a697c4af8..94f7752e2ccc 100644 --- a/drivers/staging/et131x/et1310_tx.c +++ b/drivers/staging/et131x/et1310_tx.c | |||
@@ -267,7 +267,8 @@ void ConfigTxDmaRegs(struct et131x_adapter *etdev) | |||
267 | void et131x_tx_dma_disable(struct et131x_adapter *etdev) | 267 | void et131x_tx_dma_disable(struct et131x_adapter *etdev) |
268 | { | 268 | { |
269 | /* Setup the tramsmit dma configuration register */ | 269 | /* Setup the tramsmit dma configuration register */ |
270 | writel(0x101, &etdev->regs->txdma.csr.value); | 270 | writel(ET_TXDMA_CSR_HALT|ET_TXDMA_SNGL_EPKT, |
271 | &etdev->regs->txdma.csr); | ||
271 | } | 272 | } |
272 | 273 | ||
273 | /** | 274 | /** |
@@ -278,20 +279,16 @@ void et131x_tx_dma_disable(struct et131x_adapter *etdev) | |||
278 | */ | 279 | */ |
279 | void et131x_tx_dma_enable(struct et131x_adapter *etdev) | 280 | void et131x_tx_dma_enable(struct et131x_adapter *etdev) |
280 | { | 281 | { |
281 | if (etdev->RegistryPhyLoopbk) { | 282 | u32 csr = ET_TXDMA_SNGL_EPKT; |
283 | if (etdev->RegistryPhyLoopbk) | ||
282 | /* TxDMA is disabled for loopback operation. */ | 284 | /* TxDMA is disabled for loopback operation. */ |
283 | writel(0x101, &etdev->regs->txdma.csr.value); | 285 | csr |= ET_TXDMA_CSR_HALT; |
284 | } else { | 286 | else |
285 | TXDMA_CSR_t csr = { 0 }; | ||
286 | |||
287 | /* Setup the transmit dma configuration register for normal | 287 | /* Setup the transmit dma configuration register for normal |
288 | * operation | 288 | * operation |
289 | */ | 289 | */ |
290 | csr.bits.sngl_epkt_mode = 1; | 290 | csr |= PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT; |
291 | csr.bits.halt = 0; | 291 | writel(csr, &etdev->regs->txdma.csr); |
292 | csr.bits.cache_thrshld = PARM_DMA_CACHE_DEF; | ||
293 | writel(csr.value, &etdev->regs->txdma.csr.value); | ||
294 | } | ||
295 | } | 292 | } |
296 | 293 | ||
297 | /** | 294 | /** |