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-rw-r--r--drivers/i2c/busses/i2c-sh_mobile.c39
-rw-r--r--drivers/input/keyboard/sh_keysc.c3
-rw-r--r--drivers/media/video/sh_mobile_ceu_camera.c41
-rw-r--r--drivers/rtc/rtc-ds1302.c69
-rw-r--r--drivers/rtc/rtc-sh.c97
-rw-r--r--drivers/serial/sh-sci.c8
-rw-r--r--drivers/serial/sh-sci.h17
-rw-r--r--drivers/sh/intc.c71
-rw-r--r--drivers/uio/uio_pdrv_genirq.c54
-rw-r--r--drivers/usb/gadget/Kconfig28
-rw-r--r--drivers/usb/gadget/Makefile1
-rw-r--r--drivers/usb/gadget/gadget_chips.h8
-rw-r--r--drivers/usb/gadget/m66592-udc.c286
-rw-r--r--drivers/usb/gadget/m66592-udc.h90
-rw-r--r--drivers/usb/gadget/r8a66597-udc.c1689
-rw-r--r--drivers/usb/gadget/r8a66597-udc.h256
-rw-r--r--drivers/usb/host/Kconfig7
-rw-r--r--drivers/usb/host/r8a66597-hcd.c210
-rw-r--r--drivers/usb/host/r8a66597.h440
-rw-r--r--drivers/video/Kconfig2
-rw-r--r--drivers/video/sh_mobile_lcdcfb.c292
21 files changed, 2776 insertions, 932 deletions
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index 820487d0d5c7..86a9d4e81472 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -28,6 +28,7 @@
28#include <linux/interrupt.h> 28#include <linux/interrupt.h>
29#include <linux/i2c.h> 29#include <linux/i2c.h>
30#include <linux/err.h> 30#include <linux/err.h>
31#include <linux/pm_runtime.h>
31#include <linux/clk.h> 32#include <linux/clk.h>
32#include <linux/io.h> 33#include <linux/io.h>
33 34
@@ -165,7 +166,8 @@ static void activate_ch(struct sh_mobile_i2c_data *pd)
165 u_int32_t denom; 166 u_int32_t denom;
166 u_int32_t tmp; 167 u_int32_t tmp;
167 168
168 /* Make sure the clock is enabled */ 169 /* Wake up device and enable clock */
170 pm_runtime_get_sync(pd->dev);
169 clk_enable(pd->clk); 171 clk_enable(pd->clk);
170 172
171 /* Get clock rate after clock is enabled */ 173 /* Get clock rate after clock is enabled */
@@ -213,8 +215,9 @@ static void deactivate_ch(struct sh_mobile_i2c_data *pd)
213 /* Disable channel */ 215 /* Disable channel */
214 iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd)); 216 iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
215 217
216 /* Disable clock */ 218 /* Disable clock and mark device as idle */
217 clk_disable(pd->clk); 219 clk_disable(pd->clk);
220 pm_runtime_put_sync(pd->dev);
218} 221}
219 222
220static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, 223static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
@@ -572,6 +575,19 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
572 goto err_irq; 575 goto err_irq;
573 } 576 }
574 577
578 /* Enable Runtime PM for this device.
579 *
580 * Also tell the Runtime PM core to ignore children
581 * for this device since it is valid for us to suspend
582 * this I2C master driver even though the slave devices
583 * on the I2C bus may not be suspended.
584 *
585 * The state of the I2C hardware bus is unaffected by
586 * the Runtime PM state.
587 */
588 pm_suspend_ignore_children(&dev->dev, true);
589 pm_runtime_enable(&dev->dev);
590
575 /* setup the private data */ 591 /* setup the private data */
576 adap = &pd->adap; 592 adap = &pd->adap;
577 i2c_set_adapdata(adap, pd); 593 i2c_set_adapdata(adap, pd);
@@ -614,14 +630,33 @@ static int sh_mobile_i2c_remove(struct platform_device *dev)
614 iounmap(pd->reg); 630 iounmap(pd->reg);
615 sh_mobile_i2c_hook_irqs(dev, 0); 631 sh_mobile_i2c_hook_irqs(dev, 0);
616 clk_put(pd->clk); 632 clk_put(pd->clk);
633 pm_runtime_disable(&dev->dev);
617 kfree(pd); 634 kfree(pd);
618 return 0; 635 return 0;
619} 636}
620 637
638static int sh_mobile_i2c_runtime_nop(struct device *dev)
639{
640 /* Runtime PM callback shared between ->runtime_suspend()
641 * and ->runtime_resume(). Simply returns success.
642 *
643 * This driver re-initializes all registers after
644 * pm_runtime_get_sync() anyway so there is no need
645 * to save and restore registers here.
646 */
647 return 0;
648}
649
650static struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
651 .runtime_suspend = sh_mobile_i2c_runtime_nop,
652 .runtime_resume = sh_mobile_i2c_runtime_nop,
653};
654
621static struct platform_driver sh_mobile_i2c_driver = { 655static struct platform_driver sh_mobile_i2c_driver = {
622 .driver = { 656 .driver = {
623 .name = "i2c-sh_mobile", 657 .name = "i2c-sh_mobile",
624 .owner = THIS_MODULE, 658 .owner = THIS_MODULE,
659 .pm = &sh_mobile_i2c_dev_pm_ops,
625 }, 660 },
626 .probe = sh_mobile_i2c_probe, 661 .probe = sh_mobile_i2c_probe,
627 .remove = sh_mobile_i2c_remove, 662 .remove = sh_mobile_i2c_remove,
diff --git a/drivers/input/keyboard/sh_keysc.c b/drivers/input/keyboard/sh_keysc.c
index 0714bf2c28fc..887af79b7bff 100644
--- a/drivers/input/keyboard/sh_keysc.c
+++ b/drivers/input/keyboard/sh_keysc.c
@@ -80,6 +80,9 @@ static irqreturn_t sh_keysc_isr(int irq, void *dev_id)
80 iowrite16(KYCR2_IRQ_LEVEL | (keyin_set << 8), 80 iowrite16(KYCR2_IRQ_LEVEL | (keyin_set << 8),
81 priv->iomem_base + KYCR2_OFFS); 81 priv->iomem_base + KYCR2_OFFS);
82 82
83 if (pdata->kycr2_delay)
84 udelay(pdata->kycr2_delay);
85
83 keys ^= ~0; 86 keys ^= ~0;
84 keys &= (1 << (sh_keysc_mode[pdata->mode].keyin * 87 keys &= (1 << (sh_keysc_mode[pdata->mode].keyin *
85 sh_keysc_mode[pdata->mode].keyout)) - 1; 88 sh_keysc_mode[pdata->mode].keyout)) - 1;
diff --git a/drivers/media/video/sh_mobile_ceu_camera.c b/drivers/media/video/sh_mobile_ceu_camera.c
index e86878deea71..61c47b824083 100644
--- a/drivers/media/video/sh_mobile_ceu_camera.c
+++ b/drivers/media/video/sh_mobile_ceu_camera.c
@@ -30,7 +30,7 @@
30#include <linux/device.h> 30#include <linux/device.h>
31#include <linux/platform_device.h> 31#include <linux/platform_device.h>
32#include <linux/videodev2.h> 32#include <linux/videodev2.h>
33#include <linux/clk.h> 33#include <linux/pm_runtime.h>
34 34
35#include <media/v4l2-common.h> 35#include <media/v4l2-common.h>
36#include <media/v4l2-dev.h> 36#include <media/v4l2-dev.h>
@@ -86,7 +86,6 @@ struct sh_mobile_ceu_dev {
86 86
87 unsigned int irq; 87 unsigned int irq;
88 void __iomem *base; 88 void __iomem *base;
89 struct clk *clk;
90 unsigned long video_limit; 89 unsigned long video_limit;
91 90
92 /* lock used to protect videobuf */ 91 /* lock used to protect videobuf */
@@ -361,7 +360,7 @@ static int sh_mobile_ceu_add_device(struct soc_camera_device *icd)
361 if (ret) 360 if (ret)
362 goto err; 361 goto err;
363 362
364 clk_enable(pcdev->clk); 363 pm_runtime_get_sync(ici->dev);
365 364
366 ceu_write(pcdev, CAPSR, 1 << 16); /* reset */ 365 ceu_write(pcdev, CAPSR, 1 << 16); /* reset */
367 while (ceu_read(pcdev, CSTSR) & 1) 366 while (ceu_read(pcdev, CSTSR) & 1)
@@ -395,7 +394,7 @@ static void sh_mobile_ceu_remove_device(struct soc_camera_device *icd)
395 } 394 }
396 spin_unlock_irqrestore(&pcdev->lock, flags); 395 spin_unlock_irqrestore(&pcdev->lock, flags);
397 396
398 clk_disable(pcdev->clk); 397 pm_runtime_put_sync(ici->dev);
399 398
400 icd->ops->release(icd); 399 icd->ops->release(icd);
401 400
@@ -798,7 +797,6 @@ static int sh_mobile_ceu_probe(struct platform_device *pdev)
798 struct sh_mobile_ceu_dev *pcdev; 797 struct sh_mobile_ceu_dev *pcdev;
799 struct resource *res; 798 struct resource *res;
800 void __iomem *base; 799 void __iomem *base;
801 char clk_name[8];
802 unsigned int irq; 800 unsigned int irq;
803 int err = 0; 801 int err = 0;
804 802
@@ -862,13 +860,9 @@ static int sh_mobile_ceu_probe(struct platform_device *pdev)
862 goto exit_release_mem; 860 goto exit_release_mem;
863 } 861 }
864 862
865 snprintf(clk_name, sizeof(clk_name), "ceu%d", pdev->id); 863 pm_suspend_ignore_children(&pdev->dev, true);
866 pcdev->clk = clk_get(&pdev->dev, clk_name); 864 pm_runtime_enable(&pdev->dev);
867 if (IS_ERR(pcdev->clk)) { 865 pm_runtime_resume(&pdev->dev);
868 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
869 err = PTR_ERR(pcdev->clk);
870 goto exit_free_irq;
871 }
872 866
873 pcdev->ici.priv = pcdev; 867 pcdev->ici.priv = pcdev;
874 pcdev->ici.dev = &pdev->dev; 868 pcdev->ici.dev = &pdev->dev;
@@ -878,12 +872,10 @@ static int sh_mobile_ceu_probe(struct platform_device *pdev)
878 872
879 err = soc_camera_host_register(&pcdev->ici); 873 err = soc_camera_host_register(&pcdev->ici);
880 if (err) 874 if (err)
881 goto exit_free_clk; 875 goto exit_free_irq;
882 876
883 return 0; 877 return 0;
884 878
885exit_free_clk:
886 clk_put(pcdev->clk);
887exit_free_irq: 879exit_free_irq:
888 free_irq(pcdev->irq, pcdev); 880 free_irq(pcdev->irq, pcdev);
889exit_release_mem: 881exit_release_mem:
@@ -904,7 +896,6 @@ static int sh_mobile_ceu_remove(struct platform_device *pdev)
904 struct sh_mobile_ceu_dev, ici); 896 struct sh_mobile_ceu_dev, ici);
905 897
906 soc_camera_host_unregister(soc_host); 898 soc_camera_host_unregister(soc_host);
907 clk_put(pcdev->clk);
908 free_irq(pcdev->irq, pcdev); 899 free_irq(pcdev->irq, pcdev);
909 if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) 900 if (platform_get_resource(pdev, IORESOURCE_MEM, 1))
910 dma_release_declared_memory(&pdev->dev); 901 dma_release_declared_memory(&pdev->dev);
@@ -913,9 +904,27 @@ static int sh_mobile_ceu_remove(struct platform_device *pdev)
913 return 0; 904 return 0;
914} 905}
915 906
907static int sh_mobile_ceu_runtime_nop(struct device *dev)
908{
909 /* Runtime PM callback shared between ->runtime_suspend()
910 * and ->runtime_resume(). Simply returns success.
911 *
912 * This driver re-initializes all registers after
913 * pm_runtime_get_sync() anyway so there is no need
914 * to save and restore registers here.
915 */
916 return 0;
917}
918
919static struct dev_pm_ops sh_mobile_ceu_dev_pm_ops = {
920 .runtime_suspend = sh_mobile_ceu_runtime_nop,
921 .runtime_resume = sh_mobile_ceu_runtime_nop,
922};
923
916static struct platform_driver sh_mobile_ceu_driver = { 924static struct platform_driver sh_mobile_ceu_driver = {
917 .driver = { 925 .driver = {
918 .name = "sh_mobile_ceu", 926 .name = "sh_mobile_ceu",
927 .pm = &sh_mobile_ceu_dev_pm_ops,
919 }, 928 },
920 .probe = sh_mobile_ceu_probe, 929 .probe = sh_mobile_ceu_probe,
921 .remove = sh_mobile_ceu_remove, 930 .remove = sh_mobile_ceu_remove,
diff --git a/drivers/rtc/rtc-ds1302.c b/drivers/rtc/rtc-ds1302.c
index 184556620778..d490628b64da 100644
--- a/drivers/rtc/rtc-ds1302.c
+++ b/drivers/rtc/rtc-ds1302.c
@@ -1,26 +1,25 @@
1/* 1/*
2 * Dallas DS1302 RTC Support 2 * Dallas DS1302 RTC Support
3 * 3 *
4 * Copyright (C) 2002 David McCullough 4 * Copyright (C) 2002 David McCullough
5 * Copyright (C) 2003 - 2007 Paul Mundt 5 * Copyright (C) 2003 - 2007 Paul Mundt
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
8 * License version 2. See the file "COPYING" in the main directory of 8 * License version 2. See the file "COPYING" in the main directory of
9 * this archive for more details. 9 * this archive for more details.
10 */ 10 */
11
11#include <linux/init.h> 12#include <linux/init.h>
12#include <linux/module.h> 13#include <linux/module.h>
13#include <linux/kernel.h> 14#include <linux/kernel.h>
14#include <linux/platform_device.h> 15#include <linux/platform_device.h>
15#include <linux/time.h>
16#include <linux/rtc.h> 16#include <linux/rtc.h>
17#include <linux/spinlock.h>
18#include <linux/io.h> 17#include <linux/io.h>
19#include <linux/bcd.h> 18#include <linux/bcd.h>
20#include <asm/rtc.h> 19#include <asm/rtc.h>
21 20
22#define DRV_NAME "rtc-ds1302" 21#define DRV_NAME "rtc-ds1302"
23#define DRV_VERSION "0.1.0" 22#define DRV_VERSION "0.1.1"
24 23
25#define RTC_CMD_READ 0x81 /* Read command */ 24#define RTC_CMD_READ 0x81 /* Read command */
26#define RTC_CMD_WRITE 0x80 /* Write command */ 25#define RTC_CMD_WRITE 0x80 /* Write command */
@@ -47,11 +46,6 @@
47#error "Add support for your platform" 46#error "Add support for your platform"
48#endif 47#endif
49 48
50struct ds1302_rtc {
51 struct rtc_device *rtc_dev;
52 spinlock_t lock;
53};
54
55static void ds1302_sendbits(unsigned int val) 49static void ds1302_sendbits(unsigned int val)
56{ 50{
57 int i; 51 int i;
@@ -103,10 +97,6 @@ static void ds1302_writebyte(unsigned int addr, unsigned int val)
103 97
104static int ds1302_rtc_read_time(struct device *dev, struct rtc_time *tm) 98static int ds1302_rtc_read_time(struct device *dev, struct rtc_time *tm)
105{ 99{
106 struct ds1302_rtc *rtc = dev_get_drvdata(dev);
107
108 spin_lock_irq(&rtc->lock);
109
110 tm->tm_sec = bcd2bin(ds1302_readbyte(RTC_ADDR_SEC)); 100 tm->tm_sec = bcd2bin(ds1302_readbyte(RTC_ADDR_SEC));
111 tm->tm_min = bcd2bin(ds1302_readbyte(RTC_ADDR_MIN)); 101 tm->tm_min = bcd2bin(ds1302_readbyte(RTC_ADDR_MIN));
112 tm->tm_hour = bcd2bin(ds1302_readbyte(RTC_ADDR_HOUR)); 102 tm->tm_hour = bcd2bin(ds1302_readbyte(RTC_ADDR_HOUR));
@@ -118,26 +108,17 @@ static int ds1302_rtc_read_time(struct device *dev, struct rtc_time *tm)
118 if (tm->tm_year < 70) 108 if (tm->tm_year < 70)
119 tm->tm_year += 100; 109 tm->tm_year += 100;
120 110
121 spin_unlock_irq(&rtc->lock);
122
123 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 111 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
124 "mday=%d, mon=%d, year=%d, wday=%d\n", 112 "mday=%d, mon=%d, year=%d, wday=%d\n",
125 __func__, 113 __func__,
126 tm->tm_sec, tm->tm_min, tm->tm_hour, 114 tm->tm_sec, tm->tm_min, tm->tm_hour,
127 tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday); 115 tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
128 116
129 if (rtc_valid_tm(tm) < 0) 117 return rtc_valid_tm(tm);
130 dev_err(dev, "invalid date\n");
131
132 return 0;
133} 118}
134 119
135static int ds1302_rtc_set_time(struct device *dev, struct rtc_time *tm) 120static int ds1302_rtc_set_time(struct device *dev, struct rtc_time *tm)
136{ 121{
137 struct ds1302_rtc *rtc = dev_get_drvdata(dev);
138
139 spin_lock_irq(&rtc->lock);
140
141 /* Stop RTC */ 122 /* Stop RTC */
142 ds1302_writebyte(RTC_ADDR_SEC, ds1302_readbyte(RTC_ADDR_SEC) | 0x80); 123 ds1302_writebyte(RTC_ADDR_SEC, ds1302_readbyte(RTC_ADDR_SEC) | 0x80);
143 124
@@ -152,8 +133,6 @@ static int ds1302_rtc_set_time(struct device *dev, struct rtc_time *tm)
152 /* Start RTC */ 133 /* Start RTC */
153 ds1302_writebyte(RTC_ADDR_SEC, ds1302_readbyte(RTC_ADDR_SEC) & ~0x80); 134 ds1302_writebyte(RTC_ADDR_SEC, ds1302_readbyte(RTC_ADDR_SEC) & ~0x80);
154 135
155 spin_unlock_irq(&rtc->lock);
156
157 return 0; 136 return 0;
158} 137}
159 138
@@ -170,9 +149,7 @@ static int ds1302_rtc_ioctl(struct device *dev, unsigned int cmd,
170 if (copy_from_user(&tcs_val, (int __user *)arg, sizeof(int))) 149 if (copy_from_user(&tcs_val, (int __user *)arg, sizeof(int)))
171 return -EFAULT; 150 return -EFAULT;
172 151
173 spin_lock_irq(&rtc->lock);
174 ds1302_writebyte(RTC_ADDR_TCR, (0xa0 | tcs_val * 0xf)); 152 ds1302_writebyte(RTC_ADDR_TCR, (0xa0 | tcs_val * 0xf));
175 spin_unlock_irq(&rtc->lock);
176 return 0; 153 return 0;
177 } 154 }
178#endif 155#endif
@@ -187,10 +164,9 @@ static struct rtc_class_ops ds1302_rtc_ops = {
187 .ioctl = ds1302_rtc_ioctl, 164 .ioctl = ds1302_rtc_ioctl,
188}; 165};
189 166
190static int __devinit ds1302_rtc_probe(struct platform_device *pdev) 167static int __init ds1302_rtc_probe(struct platform_device *pdev)
191{ 168{
192 struct ds1302_rtc *rtc; 169 struct rtc_device *rtc;
193 int ret;
194 170
195 /* Reset */ 171 /* Reset */
196 set_dp(get_dp() & ~(RTC_RESET | RTC_IODATA | RTC_SCLK)); 172 set_dp(get_dp() & ~(RTC_RESET | RTC_IODATA | RTC_SCLK));
@@ -200,37 +176,23 @@ static int __devinit ds1302_rtc_probe(struct platform_device *pdev)
200 if (ds1302_readbyte(RTC_ADDR_RAM0) != 0x42) 176 if (ds1302_readbyte(RTC_ADDR_RAM0) != 0x42)
201 return -ENODEV; 177 return -ENODEV;
202 178
203 rtc = kzalloc(sizeof(struct ds1302_rtc), GFP_KERNEL); 179 rtc = rtc_device_register("ds1302", &pdev->dev,
204 if (unlikely(!rtc))
205 return -ENOMEM;
206
207 spin_lock_init(&rtc->lock);
208 rtc->rtc_dev = rtc_device_register("ds1302", &pdev->dev,
209 &ds1302_rtc_ops, THIS_MODULE); 180 &ds1302_rtc_ops, THIS_MODULE);
210 if (IS_ERR(rtc->rtc_dev)) { 181 if (IS_ERR(rtc))
211 ret = PTR_ERR(rtc->rtc_dev); 182 return PTR_ERR(rtc);
212 goto out;
213 }
214 183
215 platform_set_drvdata(pdev, rtc); 184 platform_set_drvdata(pdev, rtc);
216 185
217 return 0; 186 return 0;
218out:
219 kfree(rtc);
220 return ret;
221} 187}
222 188
223static int __devexit ds1302_rtc_remove(struct platform_device *pdev) 189static int __devexit ds1302_rtc_remove(struct platform_device *pdev)
224{ 190{
225 struct ds1302_rtc *rtc = platform_get_drvdata(pdev); 191 struct rtc_device *rtc = platform_get_drvdata(pdev);
226
227 if (likely(rtc->rtc_dev))
228 rtc_device_unregister(rtc->rtc_dev);
229 192
193 rtc_device_unregister(rtc);
230 platform_set_drvdata(pdev, NULL); 194 platform_set_drvdata(pdev, NULL);
231 195
232 kfree(rtc);
233
234 return 0; 196 return 0;
235} 197}
236 198
@@ -239,13 +201,12 @@ static struct platform_driver ds1302_platform_driver = {
239 .name = DRV_NAME, 201 .name = DRV_NAME,
240 .owner = THIS_MODULE, 202 .owner = THIS_MODULE,
241 }, 203 },
242 .probe = ds1302_rtc_probe, 204 .remove = __exit_p(ds1302_rtc_remove),
243 .remove = __devexit_p(ds1302_rtc_remove),
244}; 205};
245 206
246static int __init ds1302_rtc_init(void) 207static int __init ds1302_rtc_init(void)
247{ 208{
248 return platform_driver_register(&ds1302_platform_driver); 209 return platform_driver_probe(&ds1302_platform_driver, ds1302_rtc_probe);
249} 210}
250 211
251static void __exit ds1302_rtc_exit(void) 212static void __exit ds1302_rtc_exit(void)
diff --git a/drivers/rtc/rtc-sh.c b/drivers/rtc/rtc-sh.c
index d7310adb7152..e6ed5404bca0 100644
--- a/drivers/rtc/rtc-sh.c
+++ b/drivers/rtc/rtc-sh.c
@@ -29,7 +29,7 @@
29#include <asm/rtc.h> 29#include <asm/rtc.h>
30 30
31#define DRV_NAME "sh-rtc" 31#define DRV_NAME "sh-rtc"
32#define DRV_VERSION "0.2.2" 32#define DRV_VERSION "0.2.3"
33 33
34#define RTC_REG(r) ((r) * rtc_reg_size) 34#define RTC_REG(r) ((r) * rtc_reg_size)
35 35
@@ -215,7 +215,7 @@ static irqreturn_t sh_rtc_shared(int irq, void *dev_id)
215 return IRQ_RETVAL(ret); 215 return IRQ_RETVAL(ret);
216} 216}
217 217
218static inline void sh_rtc_setpie(struct device *dev, unsigned int enable) 218static int sh_rtc_irq_set_state(struct device *dev, int enable)
219{ 219{
220 struct sh_rtc *rtc = dev_get_drvdata(dev); 220 struct sh_rtc *rtc = dev_get_drvdata(dev);
221 unsigned int tmp; 221 unsigned int tmp;
@@ -225,17 +225,22 @@ static inline void sh_rtc_setpie(struct device *dev, unsigned int enable)
225 tmp = readb(rtc->regbase + RCR2); 225 tmp = readb(rtc->regbase + RCR2);
226 226
227 if (enable) { 227 if (enable) {
228 rtc->periodic_freq |= PF_KOU;
228 tmp &= ~RCR2_PEF; /* Clear PES bit */ 229 tmp &= ~RCR2_PEF; /* Clear PES bit */
229 tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */ 230 tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */
230 } else 231 } else {
232 rtc->periodic_freq &= ~PF_KOU;
231 tmp &= ~(RCR2_PESMASK | RCR2_PEF); 233 tmp &= ~(RCR2_PESMASK | RCR2_PEF);
234 }
232 235
233 writeb(tmp, rtc->regbase + RCR2); 236 writeb(tmp, rtc->regbase + RCR2);
234 237
235 spin_unlock_irq(&rtc->lock); 238 spin_unlock_irq(&rtc->lock);
239
240 return 0;
236} 241}
237 242
238static inline int sh_rtc_setfreq(struct device *dev, unsigned int freq) 243static int sh_rtc_irq_set_freq(struct device *dev, int freq)
239{ 244{
240 struct sh_rtc *rtc = dev_get_drvdata(dev); 245 struct sh_rtc *rtc = dev_get_drvdata(dev);
241 int tmp, ret = 0; 246 int tmp, ret = 0;
@@ -278,10 +283,8 @@ static inline int sh_rtc_setfreq(struct device *dev, unsigned int freq)
278 ret = -ENOTSUPP; 283 ret = -ENOTSUPP;
279 } 284 }
280 285
281 if (ret == 0) { 286 if (ret == 0)
282 rtc->periodic_freq |= tmp; 287 rtc->periodic_freq |= tmp;
283 rtc->rtc_dev->irq_freq = freq;
284 }
285 288
286 spin_unlock_irq(&rtc->lock); 289 spin_unlock_irq(&rtc->lock);
287 return ret; 290 return ret;
@@ -346,10 +349,6 @@ static int sh_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
346 unsigned int ret = 0; 349 unsigned int ret = 0;
347 350
348 switch (cmd) { 351 switch (cmd) {
349 case RTC_PIE_OFF:
350 case RTC_PIE_ON:
351 sh_rtc_setpie(dev, cmd == RTC_PIE_ON);
352 break;
353 case RTC_AIE_OFF: 352 case RTC_AIE_OFF:
354 case RTC_AIE_ON: 353 case RTC_AIE_ON:
355 sh_rtc_setaie(dev, cmd == RTC_AIE_ON); 354 sh_rtc_setaie(dev, cmd == RTC_AIE_ON);
@@ -362,13 +361,6 @@ static int sh_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
362 rtc->periodic_freq |= PF_OXS; 361 rtc->periodic_freq |= PF_OXS;
363 sh_rtc_setcie(dev, 1); 362 sh_rtc_setcie(dev, 1);
364 break; 363 break;
365 case RTC_IRQP_READ:
366 ret = put_user(rtc->rtc_dev->irq_freq,
367 (unsigned long __user *)arg);
368 break;
369 case RTC_IRQP_SET:
370 ret = sh_rtc_setfreq(dev, arg);
371 break;
372 default: 364 default:
373 ret = -ENOIOCTLCMD; 365 ret = -ENOIOCTLCMD;
374 } 366 }
@@ -602,28 +594,6 @@ static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
602 return 0; 594 return 0;
603} 595}
604 596
605static int sh_rtc_irq_set_state(struct device *dev, int enabled)
606{
607 struct platform_device *pdev = to_platform_device(dev);
608 struct sh_rtc *rtc = platform_get_drvdata(pdev);
609
610 if (enabled) {
611 rtc->periodic_freq |= PF_KOU;
612 return sh_rtc_ioctl(dev, RTC_PIE_ON, 0);
613 } else {
614 rtc->periodic_freq &= ~PF_KOU;
615 return sh_rtc_ioctl(dev, RTC_PIE_OFF, 0);
616 }
617}
618
619static int sh_rtc_irq_set_freq(struct device *dev, int freq)
620{
621 if (!is_power_of_2(freq))
622 return -EINVAL;
623
624 return sh_rtc_ioctl(dev, RTC_IRQP_SET, freq);
625}
626
627static struct rtc_class_ops sh_rtc_ops = { 597static struct rtc_class_ops sh_rtc_ops = {
628 .ioctl = sh_rtc_ioctl, 598 .ioctl = sh_rtc_ioctl,
629 .read_time = sh_rtc_read_time, 599 .read_time = sh_rtc_read_time,
@@ -635,7 +605,7 @@ static struct rtc_class_ops sh_rtc_ops = {
635 .proc = sh_rtc_proc, 605 .proc = sh_rtc_proc,
636}; 606};
637 607
638static int __devinit sh_rtc_probe(struct platform_device *pdev) 608static int __init sh_rtc_probe(struct platform_device *pdev)
639{ 609{
640 struct sh_rtc *rtc; 610 struct sh_rtc *rtc;
641 struct resource *res; 611 struct resource *res;
@@ -702,13 +672,6 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
702 672
703 clk_enable(rtc->clk); 673 clk_enable(rtc->clk);
704 674
705 rtc->rtc_dev = rtc_device_register("sh", &pdev->dev,
706 &sh_rtc_ops, THIS_MODULE);
707 if (IS_ERR(rtc->rtc_dev)) {
708 ret = PTR_ERR(rtc->rtc_dev);
709 goto err_unmap;
710 }
711
712 rtc->capabilities = RTC_DEF_CAPABILITIES; 675 rtc->capabilities = RTC_DEF_CAPABILITIES;
713 if (pdev->dev.platform_data) { 676 if (pdev->dev.platform_data) {
714 struct sh_rtc_platform_info *pinfo = pdev->dev.platform_data; 677 struct sh_rtc_platform_info *pinfo = pdev->dev.platform_data;
@@ -720,10 +683,6 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
720 rtc->capabilities |= pinfo->capabilities; 683 rtc->capabilities |= pinfo->capabilities;
721 } 684 }
722 685
723 rtc->rtc_dev->max_user_freq = 256;
724
725 platform_set_drvdata(pdev, rtc);
726
727 if (rtc->carry_irq <= 0) { 686 if (rtc->carry_irq <= 0) {
728 /* register shared periodic/carry/alarm irq */ 687 /* register shared periodic/carry/alarm irq */
729 ret = request_irq(rtc->periodic_irq, sh_rtc_shared, 688 ret = request_irq(rtc->periodic_irq, sh_rtc_shared,
@@ -767,13 +726,26 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
767 } 726 }
768 } 727 }
769 728
729 platform_set_drvdata(pdev, rtc);
730
770 /* everything disabled by default */ 731 /* everything disabled by default */
771 rtc->periodic_freq = 0; 732 sh_rtc_irq_set_freq(&pdev->dev, 0);
772 rtc->rtc_dev->irq_freq = 0; 733 sh_rtc_irq_set_state(&pdev->dev, 0);
773 sh_rtc_setpie(&pdev->dev, 0);
774 sh_rtc_setaie(&pdev->dev, 0); 734 sh_rtc_setaie(&pdev->dev, 0);
775 sh_rtc_setcie(&pdev->dev, 0); 735 sh_rtc_setcie(&pdev->dev, 0);
776 736
737 rtc->rtc_dev = rtc_device_register("sh", &pdev->dev,
738 &sh_rtc_ops, THIS_MODULE);
739 if (IS_ERR(rtc->rtc_dev)) {
740 ret = PTR_ERR(rtc->rtc_dev);
741 free_irq(rtc->periodic_irq, rtc);
742 free_irq(rtc->carry_irq, rtc);
743 free_irq(rtc->alarm_irq, rtc);
744 goto err_unmap;
745 }
746
747 rtc->rtc_dev->max_user_freq = 256;
748
777 /* reset rtc to epoch 0 if time is invalid */ 749 /* reset rtc to epoch 0 if time is invalid */
778 if (rtc_read_time(rtc->rtc_dev, &r) < 0) { 750 if (rtc_read_time(rtc->rtc_dev, &r) < 0) {
779 rtc_time_to_tm(0, &r); 751 rtc_time_to_tm(0, &r);
@@ -795,14 +767,13 @@ err_badres:
795 return ret; 767 return ret;
796} 768}
797 769
798static int __devexit sh_rtc_remove(struct platform_device *pdev) 770static int __exit sh_rtc_remove(struct platform_device *pdev)
799{ 771{
800 struct sh_rtc *rtc = platform_get_drvdata(pdev); 772 struct sh_rtc *rtc = platform_get_drvdata(pdev);
801 773
802 if (likely(rtc->rtc_dev)) 774 rtc_device_unregister(rtc->rtc_dev);
803 rtc_device_unregister(rtc->rtc_dev); 775 sh_rtc_irq_set_state(&pdev->dev, 0);
804 776
805 sh_rtc_setpie(&pdev->dev, 0);
806 sh_rtc_setaie(&pdev->dev, 0); 777 sh_rtc_setaie(&pdev->dev, 0);
807 sh_rtc_setcie(&pdev->dev, 0); 778 sh_rtc_setcie(&pdev->dev, 0);
808 779
@@ -813,9 +784,8 @@ static int __devexit sh_rtc_remove(struct platform_device *pdev)
813 free_irq(rtc->alarm_irq, rtc); 784 free_irq(rtc->alarm_irq, rtc);
814 } 785 }
815 786
816 release_resource(rtc->res);
817
818 iounmap(rtc->regbase); 787 iounmap(rtc->regbase);
788 release_resource(rtc->res);
819 789
820 clk_disable(rtc->clk); 790 clk_disable(rtc->clk);
821 clk_put(rtc->clk); 791 clk_put(rtc->clk);
@@ -867,13 +837,12 @@ static struct platform_driver sh_rtc_platform_driver = {
867 .owner = THIS_MODULE, 837 .owner = THIS_MODULE,
868 .pm = &sh_rtc_dev_pm_ops, 838 .pm = &sh_rtc_dev_pm_ops,
869 }, 839 },
870 .probe = sh_rtc_probe, 840 .remove = __exit_p(sh_rtc_remove),
871 .remove = __devexit_p(sh_rtc_remove),
872}; 841};
873 842
874static int __init sh_rtc_init(void) 843static int __init sh_rtc_init(void)
875{ 844{
876 return platform_driver_register(&sh_rtc_platform_driver); 845 return platform_driver_probe(&sh_rtc_platform_driver, sh_rtc_probe);
877} 846}
878 847
879static void __exit sh_rtc_exit(void) 848static void __exit sh_rtc_exit(void)
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index 8e2feb563347..32dc2fc50e6b 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -272,7 +272,8 @@ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
272 __raw_writew(data, PSCR); 272 __raw_writew(data, PSCR);
273 } 273 }
274} 274}
275#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 275#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
276 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
276 defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 277 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
277 defined(CONFIG_CPU_SUBTYPE_SH7785) || \ 278 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
278 defined(CONFIG_CPU_SUBTYPE_SH7786) || \ 279 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
@@ -662,10 +663,11 @@ static irqreturn_t sci_rx_interrupt(int irq, void *port)
662static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 663static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
663{ 664{
664 struct uart_port *port = ptr; 665 struct uart_port *port = ptr;
666 unsigned long flags;
665 667
666 spin_lock_irq(&port->lock); 668 spin_lock_irqsave(&port->lock, flags);
667 sci_transmit_chars(port); 669 sci_transmit_chars(port);
668 spin_unlock_irq(&port->lock); 670 spin_unlock_irqrestore(&port->lock, flags);
669 671
670 return IRQ_HANDLED; 672 return IRQ_HANDLED;
671} 673}
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 38072c15b845..3e2fcf93b42e 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -112,6 +112,13 @@
112#elif defined(CONFIG_H8S2678) 112#elif defined(CONFIG_H8S2678)
113# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 113# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
114# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 114# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
115#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
116# define SCSPTR0 0xfe4b0020
117# define SCSPTR1 0xfe4b0020
118# define SCSPTR2 0xfe4b0020
119# define SCIF_ORER 0x0001
120# define SCSCR_INIT(port) 0x38
121# define SCIF_ONLY
115#elif defined(CONFIG_CPU_SUBTYPE_SH7763) 122#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
116# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 123# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
117# define SCSPTR1 0xffe08024 /* 16 bit SCIF */ 124# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
@@ -562,6 +569,16 @@ static inline int sci_rxd_in(struct uart_port *port)
562 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ 569 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
563 return 1; 570 return 1;
564} 571}
572#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
573static inline int sci_rxd_in(struct uart_port *port)
574{
575 if (port->mapbase == 0xfe4b0000)
576 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0;
577 if (port->mapbase == 0xfe4c0000)
578 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0;
579 if (port->mapbase == 0xfe4d0000)
580 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0;
581}
565#elif defined(CONFIG_CPU_SUBTYPE_SH7760) 582#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
566static inline int sci_rxd_in(struct uart_port *port) 583static inline int sci_rxd_in(struct uart_port *port)
567{ 584{
diff --git a/drivers/sh/intc.c b/drivers/sh/intc.c
index 3dd231a643b5..559b5fe9dc0f 100644
--- a/drivers/sh/intc.c
+++ b/drivers/sh/intc.c
@@ -77,7 +77,7 @@ static unsigned long ack_handle[NR_IRQS];
77static inline struct intc_desc_int *get_intc_desc(unsigned int irq) 77static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
78{ 78{
79 struct irq_chip *chip = get_irq_chip(irq); 79 struct irq_chip *chip = get_irq_chip(irq);
80 return (void *)((char *)chip - offsetof(struct intc_desc_int, chip)); 80 return container_of(chip, struct intc_desc_int, chip);
81} 81}
82 82
83static inline unsigned int set_field(unsigned int value, 83static inline unsigned int set_field(unsigned int value,
@@ -95,16 +95,19 @@ static inline unsigned int set_field(unsigned int value,
95static void write_8(unsigned long addr, unsigned long h, unsigned long data) 95static void write_8(unsigned long addr, unsigned long h, unsigned long data)
96{ 96{
97 __raw_writeb(set_field(0, data, h), addr); 97 __raw_writeb(set_field(0, data, h), addr);
98 (void)__raw_readb(addr); /* Defeat write posting */
98} 99}
99 100
100static void write_16(unsigned long addr, unsigned long h, unsigned long data) 101static void write_16(unsigned long addr, unsigned long h, unsigned long data)
101{ 102{
102 __raw_writew(set_field(0, data, h), addr); 103 __raw_writew(set_field(0, data, h), addr);
104 (void)__raw_readw(addr); /* Defeat write posting */
103} 105}
104 106
105static void write_32(unsigned long addr, unsigned long h, unsigned long data) 107static void write_32(unsigned long addr, unsigned long h, unsigned long data)
106{ 108{
107 __raw_writel(set_field(0, data, h), addr); 109 __raw_writel(set_field(0, data, h), addr);
110 (void)__raw_readl(addr); /* Defeat write posting */
108} 111}
109 112
110static void modify_8(unsigned long addr, unsigned long h, unsigned long data) 113static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
@@ -112,6 +115,7 @@ static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
112 unsigned long flags; 115 unsigned long flags;
113 local_irq_save(flags); 116 local_irq_save(flags);
114 __raw_writeb(set_field(__raw_readb(addr), data, h), addr); 117 __raw_writeb(set_field(__raw_readb(addr), data, h), addr);
118 (void)__raw_readb(addr); /* Defeat write posting */
115 local_irq_restore(flags); 119 local_irq_restore(flags);
116} 120}
117 121
@@ -120,6 +124,7 @@ static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
120 unsigned long flags; 124 unsigned long flags;
121 local_irq_save(flags); 125 local_irq_save(flags);
122 __raw_writew(set_field(__raw_readw(addr), data, h), addr); 126 __raw_writew(set_field(__raw_readw(addr), data, h), addr);
127 (void)__raw_readw(addr); /* Defeat write posting */
123 local_irq_restore(flags); 128 local_irq_restore(flags);
124} 129}
125 130
@@ -128,6 +133,7 @@ static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
128 unsigned long flags; 133 unsigned long flags;
129 local_irq_save(flags); 134 local_irq_save(flags);
130 __raw_writel(set_field(__raw_readl(addr), data, h), addr); 135 __raw_writel(set_field(__raw_readl(addr), data, h), addr);
136 (void)__raw_readl(addr); /* Defeat write posting */
131 local_irq_restore(flags); 137 local_irq_restore(flags);
132} 138}
133 139
@@ -657,16 +663,9 @@ static unsigned int __init save_reg(struct intc_desc_int *d,
657 return 0; 663 return 0;
658} 664}
659 665
660static unsigned char *intc_evt2irq_table; 666static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
661
662unsigned int intc_evt2irq(unsigned int vector)
663{ 667{
664 unsigned int irq = evt2irq(vector); 668 generic_handle_irq((unsigned int)get_irq_data(irq));
665
666 if (intc_evt2irq_table && intc_evt2irq_table[irq])
667 irq = intc_evt2irq_table[irq];
668
669 return irq;
670} 669}
671 670
672void __init register_intc_controller(struct intc_desc *desc) 671void __init register_intc_controller(struct intc_desc *desc)
@@ -739,50 +738,48 @@ void __init register_intc_controller(struct intc_desc *desc)
739 738
740 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ 739 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
741 740
742 /* keep the first vector only if same enum is used multiple times */ 741 /* register the vectors one by one */
743 for (i = 0; i < desc->nr_vectors; i++) { 742 for (i = 0; i < desc->nr_vectors; i++) {
744 struct intc_vect *vect = desc->vectors + i; 743 struct intc_vect *vect = desc->vectors + i;
745 int first_irq = evt2irq(vect->vect); 744 unsigned int irq = evt2irq(vect->vect);
745 struct irq_desc *irq_desc;
746 746
747 if (!vect->enum_id) 747 if (!vect->enum_id)
748 continue; 748 continue;
749 749
750 irq_desc = irq_to_desc_alloc_node(irq, numa_node_id());
751 if (unlikely(!irq_desc)) {
752 pr_info("can't get irq_desc for %d\n", irq);
753 continue;
754 }
755
756 intc_register_irq(desc, d, vect->enum_id, irq);
757
750 for (k = i + 1; k < desc->nr_vectors; k++) { 758 for (k = i + 1; k < desc->nr_vectors; k++) {
751 struct intc_vect *vect2 = desc->vectors + k; 759 struct intc_vect *vect2 = desc->vectors + k;
760 unsigned int irq2 = evt2irq(vect2->vect);
752 761
753 if (vect->enum_id != vect2->enum_id) 762 if (vect->enum_id != vect2->enum_id)
754 continue; 763 continue;
755 764
756 vect2->enum_id = 0; 765 /*
757 766 * In the case of multi-evt handling and sparse
758 if (!intc_evt2irq_table) 767 * IRQ support, each vector still needs to have
759 intc_evt2irq_table = kzalloc(NR_IRQS, GFP_NOWAIT); 768 * its own backing irq_desc.
760 769 */
761 if (!intc_evt2irq_table) { 770 irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id());
762 pr_warning("intc: cannot allocate evt2irq!\n"); 771 if (unlikely(!irq_desc)) {
772 pr_info("can't get irq_desc for %d\n", irq2);
763 continue; 773 continue;
764 } 774 }
765 775
766 intc_evt2irq_table[evt2irq(vect2->vect)] = first_irq; 776 vect2->enum_id = 0;
767 }
768 }
769
770 /* register the vectors one by one */
771 for (i = 0; i < desc->nr_vectors; i++) {
772 struct intc_vect *vect = desc->vectors + i;
773 unsigned int irq = evt2irq(vect->vect);
774 struct irq_desc *irq_desc;
775
776 if (!vect->enum_id)
777 continue;
778 777
779 irq_desc = irq_to_desc_alloc_node(irq, numa_node_id()); 778 /* redirect this interrupts to the first one */
780 if (unlikely(!irq_desc)) { 779 set_irq_chip_and_handler_name(irq2, &d->chip,
781 printk(KERN_INFO "can not get irq_desc for %d\n", irq); 780 intc_redirect_irq, "redirect");
782 continue; 781 set_irq_data(irq2, (void *)irq);
783 } 782 }
784
785 intc_register_irq(desc, d, vect->enum_id, irq);
786 } 783 }
787} 784}
788 785
diff --git a/drivers/uio/uio_pdrv_genirq.c b/drivers/uio/uio_pdrv_genirq.c
index 3f06818cf9fa..02347c57357d 100644
--- a/drivers/uio/uio_pdrv_genirq.c
+++ b/drivers/uio/uio_pdrv_genirq.c
@@ -20,6 +20,7 @@
20#include <linux/bitops.h> 20#include <linux/bitops.h>
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/stringify.h> 22#include <linux/stringify.h>
23#include <linux/pm_runtime.h>
23 24
24#define DRIVER_NAME "uio_pdrv_genirq" 25#define DRIVER_NAME "uio_pdrv_genirq"
25 26
@@ -27,8 +28,27 @@ struct uio_pdrv_genirq_platdata {
27 struct uio_info *uioinfo; 28 struct uio_info *uioinfo;
28 spinlock_t lock; 29 spinlock_t lock;
29 unsigned long flags; 30 unsigned long flags;
31 struct platform_device *pdev;
30}; 32};
31 33
34static int uio_pdrv_genirq_open(struct uio_info *info, struct inode *inode)
35{
36 struct uio_pdrv_genirq_platdata *priv = info->priv;
37
38 /* Wait until the Runtime PM code has woken up the device */
39 pm_runtime_get_sync(&priv->pdev->dev);
40 return 0;
41}
42
43static int uio_pdrv_genirq_release(struct uio_info *info, struct inode *inode)
44{
45 struct uio_pdrv_genirq_platdata *priv = info->priv;
46
47 /* Tell the Runtime PM code that the device has become idle */
48 pm_runtime_put_sync(&priv->pdev->dev);
49 return 0;
50}
51
32static irqreturn_t uio_pdrv_genirq_handler(int irq, struct uio_info *dev_info) 52static irqreturn_t uio_pdrv_genirq_handler(int irq, struct uio_info *dev_info)
33{ 53{
34 struct uio_pdrv_genirq_platdata *priv = dev_info->priv; 54 struct uio_pdrv_genirq_platdata *priv = dev_info->priv;
@@ -97,6 +117,7 @@ static int uio_pdrv_genirq_probe(struct platform_device *pdev)
97 priv->uioinfo = uioinfo; 117 priv->uioinfo = uioinfo;
98 spin_lock_init(&priv->lock); 118 spin_lock_init(&priv->lock);
99 priv->flags = 0; /* interrupt is enabled to begin with */ 119 priv->flags = 0; /* interrupt is enabled to begin with */
120 priv->pdev = pdev;
100 121
101 uiomem = &uioinfo->mem[0]; 122 uiomem = &uioinfo->mem[0];
102 123
@@ -136,8 +157,17 @@ static int uio_pdrv_genirq_probe(struct platform_device *pdev)
136 uioinfo->irq_flags |= IRQF_DISABLED; 157 uioinfo->irq_flags |= IRQF_DISABLED;
137 uioinfo->handler = uio_pdrv_genirq_handler; 158 uioinfo->handler = uio_pdrv_genirq_handler;
138 uioinfo->irqcontrol = uio_pdrv_genirq_irqcontrol; 159 uioinfo->irqcontrol = uio_pdrv_genirq_irqcontrol;
160 uioinfo->open = uio_pdrv_genirq_open;
161 uioinfo->release = uio_pdrv_genirq_release;
139 uioinfo->priv = priv; 162 uioinfo->priv = priv;
140 163
164 /* Enable Runtime PM for this device:
165 * The device starts in suspended state to allow the hardware to be
166 * turned off by default. The Runtime PM bus code should power on the
167 * hardware and enable clocks at open().
168 */
169 pm_runtime_enable(&pdev->dev);
170
141 ret = uio_register_device(&pdev->dev, priv->uioinfo); 171 ret = uio_register_device(&pdev->dev, priv->uioinfo);
142 if (ret) { 172 if (ret) {
143 dev_err(&pdev->dev, "unable to register uio device\n"); 173 dev_err(&pdev->dev, "unable to register uio device\n");
@@ -157,16 +187,40 @@ static int uio_pdrv_genirq_remove(struct platform_device *pdev)
157 struct uio_pdrv_genirq_platdata *priv = platform_get_drvdata(pdev); 187 struct uio_pdrv_genirq_platdata *priv = platform_get_drvdata(pdev);
158 188
159 uio_unregister_device(priv->uioinfo); 189 uio_unregister_device(priv->uioinfo);
190 pm_runtime_disable(&pdev->dev);
160 kfree(priv); 191 kfree(priv);
161 return 0; 192 return 0;
162} 193}
163 194
195static int uio_pdrv_genirq_runtime_nop(struct device *dev)
196{
197 /* Runtime PM callback shared between ->runtime_suspend()
198 * and ->runtime_resume(). Simply returns success.
199 *
200 * In this driver pm_runtime_get_sync() and pm_runtime_put_sync()
201 * are used at open() and release() time. This allows the
202 * Runtime PM code to turn off power to the device while the
203 * device is unused, ie before open() and after release().
204 *
205 * This Runtime PM callback does not need to save or restore
206 * any registers since user space is responsbile for hardware
207 * register reinitialization after open().
208 */
209 return 0;
210}
211
212static struct dev_pm_ops uio_pdrv_genirq_dev_pm_ops = {
213 .runtime_suspend = uio_pdrv_genirq_runtime_nop,
214 .runtime_resume = uio_pdrv_genirq_runtime_nop,
215};
216
164static struct platform_driver uio_pdrv_genirq = { 217static struct platform_driver uio_pdrv_genirq = {
165 .probe = uio_pdrv_genirq_probe, 218 .probe = uio_pdrv_genirq_probe,
166 .remove = uio_pdrv_genirq_remove, 219 .remove = uio_pdrv_genirq_remove,
167 .driver = { 220 .driver = {
168 .name = DRIVER_NAME, 221 .name = DRIVER_NAME,
169 .owner = THIS_MODULE, 222 .owner = THIS_MODULE,
223 .pm = &uio_pdrv_genirq_dev_pm_ops,
170 }, 224 },
171}; 225};
172 226
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 7f8e83a954ac..9f986b417c5b 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -251,6 +251,24 @@ config USB_PXA25X_SMALL
251 default y if USB_ETH 251 default y if USB_ETH
252 default y if USB_G_SERIAL 252 default y if USB_G_SERIAL
253 253
254config USB_GADGET_R8A66597
255 boolean "Renesas R8A66597 USB Peripheral Controller"
256 select USB_GADGET_DUALSPEED
257 help
258 R8A66597 is a discrete USB host and peripheral controller chip that
259 supports both full and high speed USB 2.0 data transfers.
260 It has nine configurable endpoints, and endpoint zero.
261
262 Say "y" to link the driver statically, or "m" to build a
263 dynamically linked module called "r8a66597_udc" and force all
264 gadget drivers to also be dynamically linked.
265
266config USB_R8A66597
267 tristate
268 depends on USB_GADGET_R8A66597
269 default USB_GADGET
270 select USB_GADGET_SELECTED
271
254config USB_GADGET_PXA27X 272config USB_GADGET_PXA27X
255 boolean "PXA 27x" 273 boolean "PXA 27x"
256 depends on ARCH_PXA && (PXA27x || PXA3xx) 274 depends on ARCH_PXA && (PXA27x || PXA3xx)
@@ -360,16 +378,6 @@ config USB_M66592
360 default USB_GADGET 378 default USB_GADGET
361 select USB_GADGET_SELECTED 379 select USB_GADGET_SELECTED
362 380
363config SUPERH_BUILT_IN_M66592
364 boolean "Enable SuperH built-in USB like the M66592"
365 depends on USB_GADGET_M66592 && CPU_SUBTYPE_SH7722
366 help
367 SH7722 has USB like the M66592.
368
369 The transfer rate is very slow when use "Ethernet Gadget".
370 However, this problem is improved if change a value of
371 NET_IP_ALIGN to 4.
372
373# 381#
374# Controllers available only in discrete form (and all PCI controllers) 382# Controllers available only in discrete form (and all PCI controllers)
375# 383#
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index e6017e6bf6da..9d7b87c52e9f 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -23,6 +23,7 @@ ifeq ($(CONFIG_ARCH_MXC),y)
23fsl_usb2_udc-objs += fsl_mx3_udc.o 23fsl_usb2_udc-objs += fsl_mx3_udc.o
24endif 24endif
25obj-$(CONFIG_USB_M66592) += m66592-udc.o 25obj-$(CONFIG_USB_M66592) += m66592-udc.o
26obj-$(CONFIG_USB_R8A66597) += r8a66597-udc.o
26obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o 27obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o
27obj-$(CONFIG_USB_CI13XXX) += ci13xxx_udc.o 28obj-$(CONFIG_USB_CI13XXX) += ci13xxx_udc.o
28obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o 29obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index 8e0e9a0b7364..f2d270b202f2 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -173,6 +173,12 @@
173// CONFIG_USB_GADGET_AU1X00 173// CONFIG_USB_GADGET_AU1X00
174// ... 174// ...
175 175
176#ifdef CONFIG_USB_GADGET_R8A66597
177#define gadget_is_r8a66597(g) !strcmp("r8a66597_udc", (g)->name)
178#else
179#define gadget_is_r8a66597(g) 0
180#endif
181
176 182
177/** 183/**
178 * usb_gadget_controller_number - support bcdDevice id convention 184 * usb_gadget_controller_number - support bcdDevice id convention
@@ -239,6 +245,8 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
239 return 0x23; 245 return 0x23;
240 else if (gadget_is_langwell(gadget)) 246 else if (gadget_is_langwell(gadget))
241 return 0x24; 247 return 0x24;
248 else if (gadget_is_r8a66597(gadget))
249 return 0x25;
242 return -ENOENT; 250 return -ENOENT;
243} 251}
244 252
diff --git a/drivers/usb/gadget/m66592-udc.c b/drivers/usb/gadget/m66592-udc.c
index 43dcf9e1af6b..a8c8543d1b08 100644
--- a/drivers/usb/gadget/m66592-udc.c
+++ b/drivers/usb/gadget/m66592-udc.c
@@ -25,44 +25,18 @@
25#include <linux/delay.h> 25#include <linux/delay.h>
26#include <linux/io.h> 26#include <linux/io.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28 28#include <linux/err.h>
29#include <linux/usb/ch9.h> 29#include <linux/usb/ch9.h>
30#include <linux/usb/gadget.h> 30#include <linux/usb/gadget.h>
31 31
32#include "m66592-udc.h" 32#include "m66592-udc.h"
33 33
34
35MODULE_DESCRIPTION("M66592 USB gadget driver"); 34MODULE_DESCRIPTION("M66592 USB gadget driver");
36MODULE_LICENSE("GPL"); 35MODULE_LICENSE("GPL");
37MODULE_AUTHOR("Yoshihiro Shimoda"); 36MODULE_AUTHOR("Yoshihiro Shimoda");
38MODULE_ALIAS("platform:m66592_udc"); 37MODULE_ALIAS("platform:m66592_udc");
39 38
40#define DRIVER_VERSION "18 Oct 2007" 39#define DRIVER_VERSION "21 July 2009"
41
42/* module parameters */
43#if defined(CONFIG_SUPERH_BUILT_IN_M66592)
44static unsigned short endian = M66592_LITTLE;
45module_param(endian, ushort, 0644);
46MODULE_PARM_DESC(endian, "data endian: big=0, little=0 (default=0)");
47#else
48static unsigned short clock = M66592_XTAL24;
49module_param(clock, ushort, 0644);
50MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0 "
51 "(default=16384)");
52
53static unsigned short vif = M66592_LDRV;
54module_param(vif, ushort, 0644);
55MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0 (default=32768)");
56
57static unsigned short endian;
58module_param(endian, ushort, 0644);
59MODULE_PARM_DESC(endian, "data endian: big=256, little=0 (default=0)");
60
61static unsigned short irq_sense = M66592_INTL;
62module_param(irq_sense, ushort, 0644);
63MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=2, falling edge=0 "
64 "(default=2)");
65#endif
66 40
67static const char udc_name[] = "m66592_udc"; 41static const char udc_name[] = "m66592_udc";
68static const char *m66592_ep_name[] = { 42static const char *m66592_ep_name[] = {
@@ -244,6 +218,7 @@ static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
244static inline void pipe_change(struct m66592 *m66592, u16 pipenum) 218static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
245{ 219{
246 struct m66592_ep *ep = m66592->pipenum2ep[pipenum]; 220 struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
221 unsigned short mbw;
247 222
248 if (ep->use_dma) 223 if (ep->use_dma)
249 return; 224 return;
@@ -252,7 +227,12 @@ static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
252 227
253 ndelay(450); 228 ndelay(450);
254 229
255 m66592_bset(m66592, M66592_MBW, ep->fifosel); 230 if (m66592->pdata->on_chip)
231 mbw = M66592_MBW_32;
232 else
233 mbw = M66592_MBW_16;
234
235 m66592_bset(m66592, mbw, ep->fifosel);
256} 236}
257 237
258static int pipe_buffer_setting(struct m66592 *m66592, 238static int pipe_buffer_setting(struct m66592 *m66592,
@@ -276,24 +256,27 @@ static int pipe_buffer_setting(struct m66592 *m66592,
276 buf_bsize = 0; 256 buf_bsize = 0;
277 break; 257 break;
278 case M66592_BULK: 258 case M66592_BULK:
279 bufnum = m66592->bi_bufnum + 259 /* isochronous pipes may be used as bulk pipes */
280 (info->pipe - M66592_BASE_PIPENUM_BULK) * 16; 260 if (info->pipe > M66592_BASE_PIPENUM_BULK)
281 m66592->bi_bufnum += 16; 261 bufnum = info->pipe - M66592_BASE_PIPENUM_BULK;
262 else
263 bufnum = info->pipe - M66592_BASE_PIPENUM_ISOC;
264
265 bufnum = M66592_BASE_BUFNUM + (bufnum * 16);
282 buf_bsize = 7; 266 buf_bsize = 7;
283 pipecfg |= M66592_DBLB; 267 pipecfg |= M66592_DBLB;
284 if (!info->dir_in) 268 if (!info->dir_in)
285 pipecfg |= M66592_SHTNAK; 269 pipecfg |= M66592_SHTNAK;
286 break; 270 break;
287 case M66592_ISO: 271 case M66592_ISO:
288 bufnum = m66592->bi_bufnum + 272 bufnum = M66592_BASE_BUFNUM +
289 (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16; 273 (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
290 m66592->bi_bufnum += 16;
291 buf_bsize = 7; 274 buf_bsize = 7;
292 break; 275 break;
293 } 276 }
294 if (m66592->bi_bufnum > M66592_MAX_BUFNUM) { 277
295 pr_err("m66592 pipe memory is insufficient(%d)\n", 278 if (buf_bsize && ((bufnum + 16) >= M66592_MAX_BUFNUM)) {
296 m66592->bi_bufnum); 279 pr_err("m66592 pipe memory is insufficient\n");
297 return -ENOMEM; 280 return -ENOMEM;
298 } 281 }
299 282
@@ -313,17 +296,6 @@ static void pipe_buffer_release(struct m66592 *m66592,
313 if (info->pipe == 0) 296 if (info->pipe == 0)
314 return; 297 return;
315 298
316 switch (info->type) {
317 case M66592_BULK:
318 if (is_bulk_pipe(info->pipe))
319 m66592->bi_bufnum -= 16;
320 break;
321 case M66592_ISO:
322 if (is_isoc_pipe(info->pipe))
323 m66592->bi_bufnum -= 16;
324 break;
325 }
326
327 if (is_bulk_pipe(info->pipe)) { 299 if (is_bulk_pipe(info->pipe)) {
328 m66592->bulk--; 300 m66592->bulk--;
329 } else if (is_interrupt_pipe(info->pipe)) 301 } else if (is_interrupt_pipe(info->pipe))
@@ -340,6 +312,7 @@ static void pipe_buffer_release(struct m66592 *m66592,
340static void pipe_initialize(struct m66592_ep *ep) 312static void pipe_initialize(struct m66592_ep *ep)
341{ 313{
342 struct m66592 *m66592 = ep->m66592; 314 struct m66592 *m66592 = ep->m66592;
315 unsigned short mbw;
343 316
344 m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel); 317 m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
345 318
@@ -351,7 +324,12 @@ static void pipe_initialize(struct m66592_ep *ep)
351 324
352 ndelay(450); 325 ndelay(450);
353 326
354 m66592_bset(m66592, M66592_MBW, ep->fifosel); 327 if (m66592->pdata->on_chip)
328 mbw = M66592_MBW_32;
329 else
330 mbw = M66592_MBW_16;
331
332 m66592_bset(m66592, mbw, ep->fifosel);
355 } 333 }
356} 334}
357 335
@@ -367,15 +345,13 @@ static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
367 ep->fifosel = M66592_D0FIFOSEL; 345 ep->fifosel = M66592_D0FIFOSEL;
368 ep->fifoctr = M66592_D0FIFOCTR; 346 ep->fifoctr = M66592_D0FIFOCTR;
369 ep->fifotrn = M66592_D0FIFOTRN; 347 ep->fifotrn = M66592_D0FIFOTRN;
370#if !defined(CONFIG_SUPERH_BUILT_IN_M66592) 348 } else if (!m66592->pdata->on_chip && m66592->num_dma == 1) {
371 } else if (m66592->num_dma == 1) {
372 m66592->num_dma++; 349 m66592->num_dma++;
373 ep->use_dma = 1; 350 ep->use_dma = 1;
374 ep->fifoaddr = M66592_D1FIFO; 351 ep->fifoaddr = M66592_D1FIFO;
375 ep->fifosel = M66592_D1FIFOSEL; 352 ep->fifosel = M66592_D1FIFOSEL;
376 ep->fifoctr = M66592_D1FIFOCTR; 353 ep->fifoctr = M66592_D1FIFOCTR;
377 ep->fifotrn = M66592_D1FIFOTRN; 354 ep->fifotrn = M66592_D1FIFOTRN;
378#endif
379 } else { 355 } else {
380 ep->use_dma = 0; 356 ep->use_dma = 0;
381 ep->fifoaddr = M66592_CFIFO; 357 ep->fifoaddr = M66592_CFIFO;
@@ -620,76 +596,120 @@ static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
620 } 596 }
621} 597}
622 598
623#if defined(CONFIG_SUPERH_BUILT_IN_M66592)
624static void init_controller(struct m66592 *m66592) 599static void init_controller(struct m66592 *m66592)
625{ 600{
626 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */ 601 unsigned int endian;
627 m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
628 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
629 m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
630 602
631 /* This is a workaound for SH7722 2nd cut */ 603 if (m66592->pdata->on_chip) {
632 m66592_bset(m66592, 0x8000, M66592_DVSTCTR); 604 if (m66592->pdata->endian)
633 m66592_bset(m66592, 0x1000, M66592_TESTMODE); 605 endian = 0; /* big endian */
634 m66592_bclr(m66592, 0x8000, M66592_DVSTCTR); 606 else
607 endian = M66592_LITTLE; /* little endian */
635 608
636 m66592_bset(m66592, M66592_INTL, M66592_INTENB1); 609 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
610 m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
611 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
612 m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
637 613
638 m66592_write(m66592, 0, M66592_CFBCFG); 614 /* This is a workaound for SH7722 2nd cut */
639 m66592_write(m66592, 0, M66592_D0FBCFG); 615 m66592_bset(m66592, 0x8000, M66592_DVSTCTR);
640 m66592_bset(m66592, endian, M66592_CFBCFG); 616 m66592_bset(m66592, 0x1000, M66592_TESTMODE);
641 m66592_bset(m66592, endian, M66592_D0FBCFG); 617 m66592_bclr(m66592, 0x8000, M66592_DVSTCTR);
642}
643#else /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
644static void init_controller(struct m66592 *m66592)
645{
646 m66592_bset(m66592, (vif & M66592_LDRV) | (endian & M66592_BIGEND),
647 M66592_PINCFG);
648 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
649 m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL, M66592_SYSCFG);
650 618
651 m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG); 619 m66592_bset(m66592, M66592_INTL, M66592_INTENB1);
652 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG); 620
653 m66592_bset(m66592, M66592_USBE, M66592_SYSCFG); 621 m66592_write(m66592, 0, M66592_CFBCFG);
622 m66592_write(m66592, 0, M66592_D0FBCFG);
623 m66592_bset(m66592, endian, M66592_CFBCFG);
624 m66592_bset(m66592, endian, M66592_D0FBCFG);
625 } else {
626 unsigned int clock, vif, irq_sense;
627
628 if (m66592->pdata->endian)
629 endian = M66592_BIGEND; /* big endian */
630 else
631 endian = 0; /* little endian */
632
633 if (m66592->pdata->vif)
634 vif = M66592_LDRV; /* 3.3v */
635 else
636 vif = 0; /* 1.5v */
637
638 switch (m66592->pdata->xtal) {
639 case M66592_PLATDATA_XTAL_12MHZ:
640 clock = M66592_XTAL12;
641 break;
642 case M66592_PLATDATA_XTAL_24MHZ:
643 clock = M66592_XTAL24;
644 break;
645 case M66592_PLATDATA_XTAL_48MHZ:
646 clock = M66592_XTAL48;
647 break;
648 default:
649 pr_warning("m66592-udc: xtal configuration error\n");
650 clock = 0;
651 }
652
653 switch (m66592->irq_trigger) {
654 case IRQF_TRIGGER_LOW:
655 irq_sense = M66592_INTL;
656 break;
657 case IRQF_TRIGGER_FALLING:
658 irq_sense = 0;
659 break;
660 default:
661 pr_warning("m66592-udc: irq trigger config error\n");
662 irq_sense = 0;
663 }
654 664
655 m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG); 665 m66592_bset(m66592,
666 (vif & M66592_LDRV) | (endian & M66592_BIGEND),
667 M66592_PINCFG);
668 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
669 m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL,
670 M66592_SYSCFG);
671 m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
672 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
673 m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
674
675 m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
656 676
657 msleep(3); 677 msleep(3);
658 678
659 m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG); 679 m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
660 680
661 msleep(1); 681 msleep(1);
662 682
663 m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG); 683 m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
664 684
665 m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1); 685 m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
666 m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR, 686 m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
667 M66592_DMA0CFG); 687 M66592_DMA0CFG);
688 }
668} 689}
669#endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
670 690
671static void disable_controller(struct m66592 *m66592) 691static void disable_controller(struct m66592 *m66592)
672{ 692{
673#if !defined(CONFIG_SUPERH_BUILT_IN_M66592) 693 if (!m66592->pdata->on_chip) {
674 m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG); 694 m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
675 udelay(1); 695 udelay(1);
676 m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG); 696 m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
677 udelay(1); 697 udelay(1);
678 m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG); 698 m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
679 udelay(1); 699 udelay(1);
680 m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG); 700 m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
681#endif 701 }
682} 702}
683 703
684static void m66592_start_xclock(struct m66592 *m66592) 704static void m66592_start_xclock(struct m66592 *m66592)
685{ 705{
686#if !defined(CONFIG_SUPERH_BUILT_IN_M66592)
687 u16 tmp; 706 u16 tmp;
688 707
689 tmp = m66592_read(m66592, M66592_SYSCFG); 708 if (!m66592->pdata->on_chip) {
690 if (!(tmp & M66592_XCKE)) 709 tmp = m66592_read(m66592, M66592_SYSCFG);
691 m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG); 710 if (!(tmp & M66592_XCKE))
692#endif 711 m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
712 }
693} 713}
694 714
695/*-------------------------------------------------------------------------*/ 715/*-------------------------------------------------------------------------*/
@@ -1177,8 +1197,7 @@ static irqreturn_t m66592_irq(int irq, void *_m66592)
1177 intsts0 = m66592_read(m66592, M66592_INTSTS0); 1197 intsts0 = m66592_read(m66592, M66592_INTSTS0);
1178 intenb0 = m66592_read(m66592, M66592_INTENB0); 1198 intenb0 = m66592_read(m66592, M66592_INTENB0);
1179 1199
1180#if defined(CONFIG_SUPERH_BUILT_IN_M66592) 1200 if (m66592->pdata->on_chip && !intsts0 && !intenb0) {
1181 if (!intsts0 && !intenb0) {
1182 /* 1201 /*
1183 * When USB clock stops, it cannot read register. Even if a 1202 * When USB clock stops, it cannot read register. Even if a
1184 * clock stops, the interrupt occurs. So this driver turn on 1203 * clock stops, the interrupt occurs. So this driver turn on
@@ -1188,7 +1207,6 @@ static irqreturn_t m66592_irq(int irq, void *_m66592)
1188 intsts0 = m66592_read(m66592, M66592_INTSTS0); 1207 intsts0 = m66592_read(m66592, M66592_INTSTS0);
1189 intenb0 = m66592_read(m66592, M66592_INTENB0); 1208 intenb0 = m66592_read(m66592, M66592_INTENB0);
1190 } 1209 }
1191#endif
1192 1210
1193 savepipe = m66592_read(m66592, M66592_CFIFOSEL); 1211 savepipe = m66592_read(m66592, M66592_CFIFOSEL);
1194 1212
@@ -1534,9 +1552,11 @@ static int __exit m66592_remove(struct platform_device *pdev)
1534 iounmap(m66592->reg); 1552 iounmap(m66592->reg);
1535 free_irq(platform_get_irq(pdev, 0), m66592); 1553 free_irq(platform_get_irq(pdev, 0), m66592);
1536 m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req); 1554 m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1537#if defined(CONFIG_SUPERH_BUILT_IN_M66592) && defined(CONFIG_HAVE_CLK) 1555#ifdef CONFIG_HAVE_CLK
1538 clk_disable(m66592->clk); 1556 if (m66592->pdata->on_chip) {
1539 clk_put(m66592->clk); 1557 clk_disable(m66592->clk);
1558 clk_put(m66592->clk);
1559 }
1540#endif 1560#endif
1541 kfree(m66592); 1561 kfree(m66592);
1542 return 0; 1562 return 0;
@@ -1548,11 +1568,10 @@ static void nop_completion(struct usb_ep *ep, struct usb_request *r)
1548 1568
1549static int __init m66592_probe(struct platform_device *pdev) 1569static int __init m66592_probe(struct platform_device *pdev)
1550{ 1570{
1551 struct resource *res; 1571 struct resource *res, *ires;
1552 int irq;
1553 void __iomem *reg = NULL; 1572 void __iomem *reg = NULL;
1554 struct m66592 *m66592 = NULL; 1573 struct m66592 *m66592 = NULL;
1555#if defined(CONFIG_SUPERH_BUILT_IN_M66592) && defined(CONFIG_HAVE_CLK) 1574#ifdef CONFIG_HAVE_CLK
1556 char clk_name[8]; 1575 char clk_name[8];
1557#endif 1576#endif
1558 int ret = 0; 1577 int ret = 0;
@@ -1565,10 +1584,11 @@ static int __init m66592_probe(struct platform_device *pdev)
1565 goto clean_up; 1584 goto clean_up;
1566 } 1585 }
1567 1586
1568 irq = platform_get_irq(pdev, 0); 1587 ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1569 if (irq < 0) { 1588 if (!ires) {
1570 ret = -ENODEV; 1589 ret = -ENODEV;
1571 pr_err("platform_get_irq error.\n"); 1590 dev_err(&pdev->dev,
1591 "platform_get_resource IORESOURCE_IRQ error.\n");
1572 goto clean_up; 1592 goto clean_up;
1573 } 1593 }
1574 1594
@@ -1579,6 +1599,12 @@ static int __init m66592_probe(struct platform_device *pdev)
1579 goto clean_up; 1599 goto clean_up;
1580 } 1600 }
1581 1601
1602 if (pdev->dev.platform_data == NULL) {
1603 dev_err(&pdev->dev, "no platform data\n");
1604 ret = -ENODEV;
1605 goto clean_up;
1606 }
1607
1582 /* initialize ucd */ 1608 /* initialize ucd */
1583 m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL); 1609 m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
1584 if (m66592 == NULL) { 1610 if (m66592 == NULL) {
@@ -1586,6 +1612,9 @@ static int __init m66592_probe(struct platform_device *pdev)
1586 goto clean_up; 1612 goto clean_up;
1587 } 1613 }
1588 1614
1615 m66592->pdata = pdev->dev.platform_data;
1616 m66592->irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
1617
1589 spin_lock_init(&m66592->lock); 1618 spin_lock_init(&m66592->lock);
1590 dev_set_drvdata(&pdev->dev, m66592); 1619 dev_set_drvdata(&pdev->dev, m66592);
1591 1620
@@ -1603,24 +1632,25 @@ static int __init m66592_probe(struct platform_device *pdev)
1603 m66592->timer.data = (unsigned long)m66592; 1632 m66592->timer.data = (unsigned long)m66592;
1604 m66592->reg = reg; 1633 m66592->reg = reg;
1605 1634
1606 m66592->bi_bufnum = M66592_BASE_BUFNUM; 1635 ret = request_irq(ires->start, m66592_irq, IRQF_DISABLED | IRQF_SHARED,
1607
1608 ret = request_irq(irq, m66592_irq, IRQF_DISABLED | IRQF_SHARED,
1609 udc_name, m66592); 1636 udc_name, m66592);
1610 if (ret < 0) { 1637 if (ret < 0) {
1611 pr_err("request_irq error (%d)\n", ret); 1638 pr_err("request_irq error (%d)\n", ret);
1612 goto clean_up; 1639 goto clean_up;
1613 } 1640 }
1614 1641
1615#if defined(CONFIG_SUPERH_BUILT_IN_M66592) && defined(CONFIG_HAVE_CLK) 1642#ifdef CONFIG_HAVE_CLK
1616 snprintf(clk_name, sizeof(clk_name), "usbf%d", pdev->id); 1643 if (m66592->pdata->on_chip) {
1617 m66592->clk = clk_get(&pdev->dev, clk_name); 1644 snprintf(clk_name, sizeof(clk_name), "usbf%d", pdev->id);
1618 if (IS_ERR(m66592->clk)) { 1645 m66592->clk = clk_get(&pdev->dev, clk_name);
1619 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name); 1646 if (IS_ERR(m66592->clk)) {
1620 ret = PTR_ERR(m66592->clk); 1647 dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
1621 goto clean_up2; 1648 clk_name);
1649 ret = PTR_ERR(m66592->clk);
1650 goto clean_up2;
1651 }
1652 clk_enable(m66592->clk);
1622 } 1653 }
1623 clk_enable(m66592->clk);
1624#endif 1654#endif
1625 INIT_LIST_HEAD(&m66592->gadget.ep_list); 1655 INIT_LIST_HEAD(&m66592->gadget.ep_list);
1626 m66592->gadget.ep0 = &m66592->ep[0].ep; 1656 m66592->gadget.ep0 = &m66592->ep[0].ep;
@@ -1662,12 +1692,14 @@ static int __init m66592_probe(struct platform_device *pdev)
1662 return 0; 1692 return 0;
1663 1693
1664clean_up3: 1694clean_up3:
1665#if defined(CONFIG_SUPERH_BUILT_IN_M66592) && defined(CONFIG_HAVE_CLK) 1695#ifdef CONFIG_HAVE_CLK
1666 clk_disable(m66592->clk); 1696 if (m66592->pdata->on_chip) {
1667 clk_put(m66592->clk); 1697 clk_disable(m66592->clk);
1698 clk_put(m66592->clk);
1699 }
1668clean_up2: 1700clean_up2:
1669#endif 1701#endif
1670 free_irq(irq, m66592); 1702 free_irq(ires->start, m66592);
1671clean_up: 1703clean_up:
1672 if (m66592) { 1704 if (m66592) {
1673 if (m66592->ep0_req) 1705 if (m66592->ep0_req)
diff --git a/drivers/usb/gadget/m66592-udc.h b/drivers/usb/gadget/m66592-udc.h
index 286ce07e7960..8b960deed680 100644
--- a/drivers/usb/gadget/m66592-udc.h
+++ b/drivers/usb/gadget/m66592-udc.h
@@ -23,10 +23,12 @@
23#ifndef __M66592_UDC_H__ 23#ifndef __M66592_UDC_H__
24#define __M66592_UDC_H__ 24#define __M66592_UDC_H__
25 25
26#if defined(CONFIG_SUPERH_BUILT_IN_M66592) && defined(CONFIG_HAVE_CLK) 26#ifdef CONFIG_HAVE_CLK
27#include <linux/clk.h> 27#include <linux/clk.h>
28#endif 28#endif
29 29
30#include <linux/usb/m66592.h>
31
30#define M66592_SYSCFG 0x00 32#define M66592_SYSCFG 0x00
31#define M66592_XTAL 0xC000 /* b15-14: Crystal selection */ 33#define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
32#define M66592_XTAL48 0x8000 /* 48MHz */ 34#define M66592_XTAL48 0x8000 /* 48MHz */
@@ -76,11 +78,11 @@
76#define M66592_P_TST_J 0x0001 /* PERI TEST J */ 78#define M66592_P_TST_J 0x0001 /* PERI TEST J */
77#define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */ 79#define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */
78 80
79#if defined(CONFIG_SUPERH_BUILT_IN_M66592) 81/* built-in registers */
80#define M66592_CFBCFG 0x0A 82#define M66592_CFBCFG 0x0A
81#define M66592_D0FBCFG 0x0C 83#define M66592_D0FBCFG 0x0C
82#define M66592_LITTLE 0x0100 /* b8: Little endian mode */ 84#define M66592_LITTLE 0x0100 /* b8: Little endian mode */
83#else 85/* external chip case */
84#define M66592_PINCFG 0x0A 86#define M66592_PINCFG 0x0A
85#define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */ 87#define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */
86#define M66592_BIGEND 0x0100 /* b8: Big endian mode */ 88#define M66592_BIGEND 0x0100 /* b8: Big endian mode */
@@ -100,8 +102,8 @@
100#define M66592_PKTM 0x0020 /* b5: Packet mode */ 102#define M66592_PKTM 0x0020 /* b5: Packet mode */
101#define M66592_DENDE 0x0010 /* b4: Dend enable */ 103#define M66592_DENDE 0x0010 /* b4: Dend enable */
102#define M66592_OBUS 0x0004 /* b2: OUTbus mode */ 104#define M66592_OBUS 0x0004 /* b2: OUTbus mode */
103#endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
104 105
106/* common case */
105#define M66592_CFIFO 0x10 107#define M66592_CFIFO 0x10
106#define M66592_D0FIFO 0x14 108#define M66592_D0FIFO 0x14
107#define M66592_D1FIFO 0x18 109#define M66592_D1FIFO 0x18
@@ -113,13 +115,9 @@
113#define M66592_REW 0x4000 /* b14: Buffer rewind */ 115#define M66592_REW 0x4000 /* b14: Buffer rewind */
114#define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */ 116#define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */
115#define M66592_DREQE 0x1000 /* b12: DREQ output enable */ 117#define M66592_DREQE 0x1000 /* b12: DREQ output enable */
116#if defined(CONFIG_SUPERH_BUILT_IN_M66592) 118#define M66592_MBW_8 0x0000 /* 8bit */
117#define M66592_MBW 0x0800 /* b11: Maximum bit width for FIFO */ 119#define M66592_MBW_16 0x0400 /* 16bit */
118#else 120#define M66592_MBW_32 0x0800 /* 32bit */
119#define M66592_MBW 0x0400 /* b10: Maximum bit width for FIFO */
120#define M66592_MBW_8 0x0000 /* 8bit */
121#define M66592_MBW_16 0x0400 /* 16bit */
122#endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
123#define M66592_TRENB 0x0200 /* b9: Transaction counter enable */ 121#define M66592_TRENB 0x0200 /* b9: Transaction counter enable */
124#define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */ 122#define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */
125#define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */ 123#define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */
@@ -480,9 +478,11 @@ struct m66592_ep {
480struct m66592 { 478struct m66592 {
481 spinlock_t lock; 479 spinlock_t lock;
482 void __iomem *reg; 480 void __iomem *reg;
483#if defined(CONFIG_SUPERH_BUILT_IN_M66592) && defined(CONFIG_HAVE_CLK) 481#ifdef CONFIG_HAVE_CLK
484 struct clk *clk; 482 struct clk *clk;
485#endif 483#endif
484 struct m66592_platdata *pdata;
485 unsigned long irq_trigger;
486 486
487 struct usb_gadget gadget; 487 struct usb_gadget gadget;
488 struct usb_gadget_driver *driver; 488 struct usb_gadget_driver *driver;
@@ -506,7 +506,6 @@ struct m66592 {
506 int interrupt; 506 int interrupt;
507 int isochronous; 507 int isochronous;
508 int num_dma; 508 int num_dma;
509 int bi_bufnum; /* bulk and isochronous's bufnum */
510}; 509};
511 510
512#define gadget_to_m66592(_gadget) container_of(_gadget, struct m66592, gadget) 511#define gadget_to_m66592(_gadget) container_of(_gadget, struct m66592, gadget)
@@ -547,13 +546,13 @@ static inline void m66592_read_fifo(struct m66592 *m66592,
547{ 546{
548 unsigned long fifoaddr = (unsigned long)m66592->reg + offset; 547 unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
549 548
550#if defined(CONFIG_SUPERH_BUILT_IN_M66592) 549 if (m66592->pdata->on_chip) {
551 len = (len + 3) / 4; 550 len = (len + 3) / 4;
552 insl(fifoaddr, buf, len); 551 insl(fifoaddr, buf, len);
553#else 552 } else {
554 len = (len + 1) / 2; 553 len = (len + 1) / 2;
555 insw(fifoaddr, buf, len); 554 insw(fifoaddr, buf, len);
556#endif 555 }
557} 556}
558 557
559static inline void m66592_write(struct m66592 *m66592, u16 val, 558static inline void m66592_write(struct m66592 *m66592, u16 val,
@@ -567,33 +566,34 @@ static inline void m66592_write_fifo(struct m66592 *m66592,
567 void *buf, unsigned long len) 566 void *buf, unsigned long len)
568{ 567{
569 unsigned long fifoaddr = (unsigned long)m66592->reg + offset; 568 unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
570#if defined(CONFIG_SUPERH_BUILT_IN_M66592) 569
571 unsigned long count; 570 if (m66592->pdata->on_chip) {
572 unsigned char *pb; 571 unsigned long count;
573 int i; 572 unsigned char *pb;
574 573 int i;
575 count = len / 4; 574
576 outsl(fifoaddr, buf, count); 575 count = len / 4;
577 576 outsl(fifoaddr, buf, count);
578 if (len & 0x00000003) { 577
579 pb = buf + count * 4; 578 if (len & 0x00000003) {
580 for (i = 0; i < (len & 0x00000003); i++) { 579 pb = buf + count * 4;
581 if (m66592_read(m66592, M66592_CFBCFG)) /* little */ 580 for (i = 0; i < (len & 0x00000003); i++) {
582 outb(pb[i], fifoaddr + (3 - i)); 581 if (m66592_read(m66592, M66592_CFBCFG)) /* le */
583 else 582 outb(pb[i], fifoaddr + (3 - i));
584 outb(pb[i], fifoaddr + i); 583 else
584 outb(pb[i], fifoaddr + i);
585 }
586 }
587 } else {
588 unsigned long odd = len & 0x0001;
589
590 len = len / 2;
591 outsw(fifoaddr, buf, len);
592 if (odd) {
593 unsigned char *p = buf + len*2;
594 outb(*p, fifoaddr);
585 } 595 }
586 } 596 }
587#else
588 unsigned long odd = len & 0x0001;
589
590 len = len / 2;
591 outsw(fifoaddr, buf, len);
592 if (odd) {
593 unsigned char *p = buf + len*2;
594 outb(*p, fifoaddr);
595 }
596#endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
597} 597}
598 598
599static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat, 599static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat,
diff --git a/drivers/usb/gadget/r8a66597-udc.c b/drivers/usb/gadget/r8a66597-udc.c
new file mode 100644
index 000000000000..e220fb8091a3
--- /dev/null
+++ b/drivers/usb/gadget/r8a66597-udc.c
@@ -0,0 +1,1689 @@
1/*
2 * R8A66597 UDC (USB gadget)
3 *
4 * Copyright (C) 2006-2009 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/platform_device.h>
28#include <linux/clk.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
33#include "r8a66597-udc.h"
34
35#define DRIVER_VERSION "2009-08-18"
36
37static const char udc_name[] = "r8a66597_udc";
38static const char *r8a66597_ep_name[] = {
39 "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7",
40 "ep8", "ep9",
41};
42
43static void disable_controller(struct r8a66597 *r8a66597);
44static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req);
45static void irq_packet_write(struct r8a66597_ep *ep,
46 struct r8a66597_request *req);
47static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
48 gfp_t gfp_flags);
49
50static void transfer_complete(struct r8a66597_ep *ep,
51 struct r8a66597_request *req, int status);
52
53/*-------------------------------------------------------------------------*/
54static inline u16 get_usb_speed(struct r8a66597 *r8a66597)
55{
56 return r8a66597_read(r8a66597, DVSTCTR0) & RHST;
57}
58
59static void enable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
60 unsigned long reg)
61{
62 u16 tmp;
63
64 tmp = r8a66597_read(r8a66597, INTENB0);
65 r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
66 INTENB0);
67 r8a66597_bset(r8a66597, (1 << pipenum), reg);
68 r8a66597_write(r8a66597, tmp, INTENB0);
69}
70
71static void disable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
72 unsigned long reg)
73{
74 u16 tmp;
75
76 tmp = r8a66597_read(r8a66597, INTENB0);
77 r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
78 INTENB0);
79 r8a66597_bclr(r8a66597, (1 << pipenum), reg);
80 r8a66597_write(r8a66597, tmp, INTENB0);
81}
82
83static void r8a66597_usb_connect(struct r8a66597 *r8a66597)
84{
85 r8a66597_bset(r8a66597, CTRE, INTENB0);
86 r8a66597_bset(r8a66597, BEMPE | BRDYE, INTENB0);
87
88 r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
89}
90
91static void r8a66597_usb_disconnect(struct r8a66597 *r8a66597)
92__releases(r8a66597->lock)
93__acquires(r8a66597->lock)
94{
95 r8a66597_bclr(r8a66597, CTRE, INTENB0);
96 r8a66597_bclr(r8a66597, BEMPE | BRDYE, INTENB0);
97 r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
98
99 r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
100 spin_unlock(&r8a66597->lock);
101 r8a66597->driver->disconnect(&r8a66597->gadget);
102 spin_lock(&r8a66597->lock);
103
104 disable_controller(r8a66597);
105 INIT_LIST_HEAD(&r8a66597->ep[0].queue);
106}
107
108static inline u16 control_reg_get_pid(struct r8a66597 *r8a66597, u16 pipenum)
109{
110 u16 pid = 0;
111 unsigned long offset;
112
113 if (pipenum == 0)
114 pid = r8a66597_read(r8a66597, DCPCTR) & PID;
115 else if (pipenum < R8A66597_MAX_NUM_PIPE) {
116 offset = get_pipectr_addr(pipenum);
117 pid = r8a66597_read(r8a66597, offset) & PID;
118 } else
119 printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
120
121 return pid;
122}
123
124static inline void control_reg_set_pid(struct r8a66597 *r8a66597, u16 pipenum,
125 u16 pid)
126{
127 unsigned long offset;
128
129 if (pipenum == 0)
130 r8a66597_mdfy(r8a66597, pid, PID, DCPCTR);
131 else if (pipenum < R8A66597_MAX_NUM_PIPE) {
132 offset = get_pipectr_addr(pipenum);
133 r8a66597_mdfy(r8a66597, pid, PID, offset);
134 } else
135 printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
136}
137
138static inline void pipe_start(struct r8a66597 *r8a66597, u16 pipenum)
139{
140 control_reg_set_pid(r8a66597, pipenum, PID_BUF);
141}
142
143static inline void pipe_stop(struct r8a66597 *r8a66597, u16 pipenum)
144{
145 control_reg_set_pid(r8a66597, pipenum, PID_NAK);
146}
147
148static inline void pipe_stall(struct r8a66597 *r8a66597, u16 pipenum)
149{
150 control_reg_set_pid(r8a66597, pipenum, PID_STALL);
151}
152
153static inline u16 control_reg_get(struct r8a66597 *r8a66597, u16 pipenum)
154{
155 u16 ret = 0;
156 unsigned long offset;
157
158 if (pipenum == 0)
159 ret = r8a66597_read(r8a66597, DCPCTR);
160 else if (pipenum < R8A66597_MAX_NUM_PIPE) {
161 offset = get_pipectr_addr(pipenum);
162 ret = r8a66597_read(r8a66597, offset);
163 } else
164 printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
165
166 return ret;
167}
168
169static inline void control_reg_sqclr(struct r8a66597 *r8a66597, u16 pipenum)
170{
171 unsigned long offset;
172
173 pipe_stop(r8a66597, pipenum);
174
175 if (pipenum == 0)
176 r8a66597_bset(r8a66597, SQCLR, DCPCTR);
177 else if (pipenum < R8A66597_MAX_NUM_PIPE) {
178 offset = get_pipectr_addr(pipenum);
179 r8a66597_bset(r8a66597, SQCLR, offset);
180 } else
181 printk(KERN_ERR "unexpect pipe num(%d)\n", pipenum);
182}
183
184static inline int get_buffer_size(struct r8a66597 *r8a66597, u16 pipenum)
185{
186 u16 tmp;
187 int size;
188
189 if (pipenum == 0) {
190 tmp = r8a66597_read(r8a66597, DCPCFG);
191 if ((tmp & R8A66597_CNTMD) != 0)
192 size = 256;
193 else {
194 tmp = r8a66597_read(r8a66597, DCPMAXP);
195 size = tmp & MAXP;
196 }
197 } else {
198 r8a66597_write(r8a66597, pipenum, PIPESEL);
199 tmp = r8a66597_read(r8a66597, PIPECFG);
200 if ((tmp & R8A66597_CNTMD) != 0) {
201 tmp = r8a66597_read(r8a66597, PIPEBUF);
202 size = ((tmp >> 10) + 1) * 64;
203 } else {
204 tmp = r8a66597_read(r8a66597, PIPEMAXP);
205 size = tmp & MXPS;
206 }
207 }
208
209 return size;
210}
211
212static inline unsigned short mbw_value(struct r8a66597 *r8a66597)
213{
214 if (r8a66597->pdata->on_chip)
215 return MBW_32;
216 else
217 return MBW_16;
218}
219
220static inline void pipe_change(struct r8a66597 *r8a66597, u16 pipenum)
221{
222 struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
223
224 if (ep->use_dma)
225 return;
226
227 r8a66597_mdfy(r8a66597, pipenum, CURPIPE, ep->fifosel);
228
229 ndelay(450);
230
231 r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
232}
233
234static int pipe_buffer_setting(struct r8a66597 *r8a66597,
235 struct r8a66597_pipe_info *info)
236{
237 u16 bufnum = 0, buf_bsize = 0;
238 u16 pipecfg = 0;
239
240 if (info->pipe == 0)
241 return -EINVAL;
242
243 r8a66597_write(r8a66597, info->pipe, PIPESEL);
244
245 if (info->dir_in)
246 pipecfg |= R8A66597_DIR;
247 pipecfg |= info->type;
248 pipecfg |= info->epnum;
249 switch (info->type) {
250 case R8A66597_INT:
251 bufnum = 4 + (info->pipe - R8A66597_BASE_PIPENUM_INT);
252 buf_bsize = 0;
253 break;
254 case R8A66597_BULK:
255 /* isochronous pipes may be used as bulk pipes */
256 if (info->pipe > R8A66597_BASE_PIPENUM_BULK)
257 bufnum = info->pipe - R8A66597_BASE_PIPENUM_BULK;
258 else
259 bufnum = info->pipe - R8A66597_BASE_PIPENUM_ISOC;
260
261 bufnum = R8A66597_BASE_BUFNUM + (bufnum * 16);
262 buf_bsize = 7;
263 pipecfg |= R8A66597_DBLB;
264 if (!info->dir_in)
265 pipecfg |= R8A66597_SHTNAK;
266 break;
267 case R8A66597_ISO:
268 bufnum = R8A66597_BASE_BUFNUM +
269 (info->pipe - R8A66597_BASE_PIPENUM_ISOC) * 16;
270 buf_bsize = 7;
271 break;
272 }
273
274 if (buf_bsize && ((bufnum + 16) >= R8A66597_MAX_BUFNUM)) {
275 pr_err(KERN_ERR "r8a66597 pipe memory is insufficient\n");
276 return -ENOMEM;
277 }
278
279 r8a66597_write(r8a66597, pipecfg, PIPECFG);
280 r8a66597_write(r8a66597, (buf_bsize << 10) | (bufnum), PIPEBUF);
281 r8a66597_write(r8a66597, info->maxpacket, PIPEMAXP);
282 if (info->interval)
283 info->interval--;
284 r8a66597_write(r8a66597, info->interval, PIPEPERI);
285
286 return 0;
287}
288
289static void pipe_buffer_release(struct r8a66597 *r8a66597,
290 struct r8a66597_pipe_info *info)
291{
292 if (info->pipe == 0)
293 return;
294
295 if (is_bulk_pipe(info->pipe))
296 r8a66597->bulk--;
297 else if (is_interrupt_pipe(info->pipe))
298 r8a66597->interrupt--;
299 else if (is_isoc_pipe(info->pipe)) {
300 r8a66597->isochronous--;
301 if (info->type == R8A66597_BULK)
302 r8a66597->bulk--;
303 } else
304 printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n",
305 info->pipe);
306}
307
308static void pipe_initialize(struct r8a66597_ep *ep)
309{
310 struct r8a66597 *r8a66597 = ep->r8a66597;
311
312 r8a66597_mdfy(r8a66597, 0, CURPIPE, ep->fifosel);
313
314 r8a66597_write(r8a66597, ACLRM, ep->pipectr);
315 r8a66597_write(r8a66597, 0, ep->pipectr);
316 r8a66597_write(r8a66597, SQCLR, ep->pipectr);
317 if (ep->use_dma) {
318 r8a66597_mdfy(r8a66597, ep->pipenum, CURPIPE, ep->fifosel);
319
320 ndelay(450);
321
322 r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
323 }
324}
325
326static void r8a66597_ep_setting(struct r8a66597 *r8a66597,
327 struct r8a66597_ep *ep,
328 const struct usb_endpoint_descriptor *desc,
329 u16 pipenum, int dma)
330{
331 ep->use_dma = 0;
332 ep->fifoaddr = CFIFO;
333 ep->fifosel = CFIFOSEL;
334 ep->fifoctr = CFIFOCTR;
335 ep->fifotrn = 0;
336
337 ep->pipectr = get_pipectr_addr(pipenum);
338 ep->pipenum = pipenum;
339 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
340 r8a66597->pipenum2ep[pipenum] = ep;
341 r8a66597->epaddr2ep[desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK]
342 = ep;
343 INIT_LIST_HEAD(&ep->queue);
344}
345
346static void r8a66597_ep_release(struct r8a66597_ep *ep)
347{
348 struct r8a66597 *r8a66597 = ep->r8a66597;
349 u16 pipenum = ep->pipenum;
350
351 if (pipenum == 0)
352 return;
353
354 if (ep->use_dma)
355 r8a66597->num_dma--;
356 ep->pipenum = 0;
357 ep->busy = 0;
358 ep->use_dma = 0;
359}
360
361static int alloc_pipe_config(struct r8a66597_ep *ep,
362 const struct usb_endpoint_descriptor *desc)
363{
364 struct r8a66597 *r8a66597 = ep->r8a66597;
365 struct r8a66597_pipe_info info;
366 int dma = 0;
367 unsigned char *counter;
368 int ret;
369
370 ep->desc = desc;
371
372 if (ep->pipenum) /* already allocated pipe */
373 return 0;
374
375 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
376 case USB_ENDPOINT_XFER_BULK:
377 if (r8a66597->bulk >= R8A66597_MAX_NUM_BULK) {
378 if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
379 printk(KERN_ERR "bulk pipe is insufficient\n");
380 return -ENODEV;
381 } else {
382 info.pipe = R8A66597_BASE_PIPENUM_ISOC
383 + r8a66597->isochronous;
384 counter = &r8a66597->isochronous;
385 }
386 } else {
387 info.pipe = R8A66597_BASE_PIPENUM_BULK + r8a66597->bulk;
388 counter = &r8a66597->bulk;
389 }
390 info.type = R8A66597_BULK;
391 dma = 1;
392 break;
393 case USB_ENDPOINT_XFER_INT:
394 if (r8a66597->interrupt >= R8A66597_MAX_NUM_INT) {
395 printk(KERN_ERR "interrupt pipe is insufficient\n");
396 return -ENODEV;
397 }
398 info.pipe = R8A66597_BASE_PIPENUM_INT + r8a66597->interrupt;
399 info.type = R8A66597_INT;
400 counter = &r8a66597->interrupt;
401 break;
402 case USB_ENDPOINT_XFER_ISOC:
403 if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
404 printk(KERN_ERR "isochronous pipe is insufficient\n");
405 return -ENODEV;
406 }
407 info.pipe = R8A66597_BASE_PIPENUM_ISOC + r8a66597->isochronous;
408 info.type = R8A66597_ISO;
409 counter = &r8a66597->isochronous;
410 break;
411 default:
412 printk(KERN_ERR "unexpect xfer type\n");
413 return -EINVAL;
414 }
415 ep->type = info.type;
416
417 info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
418 info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
419 info.interval = desc->bInterval;
420 if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
421 info.dir_in = 1;
422 else
423 info.dir_in = 0;
424
425 ret = pipe_buffer_setting(r8a66597, &info);
426 if (ret < 0) {
427 printk(KERN_ERR "pipe_buffer_setting fail\n");
428 return ret;
429 }
430
431 (*counter)++;
432 if ((counter == &r8a66597->isochronous) && info.type == R8A66597_BULK)
433 r8a66597->bulk++;
434
435 r8a66597_ep_setting(r8a66597, ep, desc, info.pipe, dma);
436 pipe_initialize(ep);
437
438 return 0;
439}
440
441static int free_pipe_config(struct r8a66597_ep *ep)
442{
443 struct r8a66597 *r8a66597 = ep->r8a66597;
444 struct r8a66597_pipe_info info;
445
446 info.pipe = ep->pipenum;
447 info.type = ep->type;
448 pipe_buffer_release(r8a66597, &info);
449 r8a66597_ep_release(ep);
450
451 return 0;
452}
453
454/*-------------------------------------------------------------------------*/
455static void pipe_irq_enable(struct r8a66597 *r8a66597, u16 pipenum)
456{
457 enable_irq_ready(r8a66597, pipenum);
458 enable_irq_nrdy(r8a66597, pipenum);
459}
460
461static void pipe_irq_disable(struct r8a66597 *r8a66597, u16 pipenum)
462{
463 disable_irq_ready(r8a66597, pipenum);
464 disable_irq_nrdy(r8a66597, pipenum);
465}
466
467/* if complete is true, gadget driver complete function is not call */
468static void control_end(struct r8a66597 *r8a66597, unsigned ccpl)
469{
470 r8a66597->ep[0].internal_ccpl = ccpl;
471 pipe_start(r8a66597, 0);
472 r8a66597_bset(r8a66597, CCPL, DCPCTR);
473}
474
475static void start_ep0_write(struct r8a66597_ep *ep,
476 struct r8a66597_request *req)
477{
478 struct r8a66597 *r8a66597 = ep->r8a66597;
479
480 pipe_change(r8a66597, ep->pipenum);
481 r8a66597_mdfy(r8a66597, ISEL, (ISEL | CURPIPE), CFIFOSEL);
482 r8a66597_write(r8a66597, BCLR, ep->fifoctr);
483 if (req->req.length == 0) {
484 r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
485 pipe_start(r8a66597, 0);
486 transfer_complete(ep, req, 0);
487 } else {
488 r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
489 irq_ep0_write(ep, req);
490 }
491}
492
493static void start_packet_write(struct r8a66597_ep *ep,
494 struct r8a66597_request *req)
495{
496 struct r8a66597 *r8a66597 = ep->r8a66597;
497 u16 tmp;
498
499 pipe_change(r8a66597, ep->pipenum);
500 disable_irq_empty(r8a66597, ep->pipenum);
501 pipe_start(r8a66597, ep->pipenum);
502
503 tmp = r8a66597_read(r8a66597, ep->fifoctr);
504 if (unlikely((tmp & FRDY) == 0))
505 pipe_irq_enable(r8a66597, ep->pipenum);
506 else
507 irq_packet_write(ep, req);
508}
509
510static void start_packet_read(struct r8a66597_ep *ep,
511 struct r8a66597_request *req)
512{
513 struct r8a66597 *r8a66597 = ep->r8a66597;
514 u16 pipenum = ep->pipenum;
515
516 if (ep->pipenum == 0) {
517 r8a66597_mdfy(r8a66597, 0, (ISEL | CURPIPE), CFIFOSEL);
518 r8a66597_write(r8a66597, BCLR, ep->fifoctr);
519 pipe_start(r8a66597, pipenum);
520 pipe_irq_enable(r8a66597, pipenum);
521 } else {
522 if (ep->use_dma) {
523 r8a66597_bset(r8a66597, TRCLR, ep->fifosel);
524 pipe_change(r8a66597, pipenum);
525 r8a66597_bset(r8a66597, TRENB, ep->fifosel);
526 r8a66597_write(r8a66597,
527 (req->req.length + ep->ep.maxpacket - 1)
528 / ep->ep.maxpacket,
529 ep->fifotrn);
530 }
531 pipe_start(r8a66597, pipenum); /* trigger once */
532 pipe_irq_enable(r8a66597, pipenum);
533 }
534}
535
536static void start_packet(struct r8a66597_ep *ep, struct r8a66597_request *req)
537{
538 if (ep->desc->bEndpointAddress & USB_DIR_IN)
539 start_packet_write(ep, req);
540 else
541 start_packet_read(ep, req);
542}
543
544static void start_ep0(struct r8a66597_ep *ep, struct r8a66597_request *req)
545{
546 u16 ctsq;
547
548 ctsq = r8a66597_read(ep->r8a66597, INTSTS0) & CTSQ;
549
550 switch (ctsq) {
551 case CS_RDDS:
552 start_ep0_write(ep, req);
553 break;
554 case CS_WRDS:
555 start_packet_read(ep, req);
556 break;
557
558 case CS_WRND:
559 control_end(ep->r8a66597, 0);
560 break;
561 default:
562 printk(KERN_ERR "start_ep0: unexpect ctsq(%x)\n", ctsq);
563 break;
564 }
565}
566
567static void init_controller(struct r8a66597 *r8a66597)
568{
569 u16 vif = r8a66597->pdata->vif ? LDRV : 0;
570 u16 irq_sense = r8a66597->irq_sense_low ? INTL : 0;
571 u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
572
573 if (r8a66597->pdata->on_chip) {
574 r8a66597_bset(r8a66597, 0x04, SYSCFG1);
575 r8a66597_bset(r8a66597, HSE, SYSCFG0);
576
577 r8a66597_bclr(r8a66597, USBE, SYSCFG0);
578 r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
579 r8a66597_bset(r8a66597, USBE, SYSCFG0);
580
581 r8a66597_bset(r8a66597, SCKE, SYSCFG0);
582
583 r8a66597_bset(r8a66597, irq_sense, INTENB1);
584 r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
585 DMA0CFG);
586 } else {
587 r8a66597_bset(r8a66597, vif | endian, PINCFG);
588 r8a66597_bset(r8a66597, HSE, SYSCFG0); /* High spd */
589 r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata),
590 XTAL, SYSCFG0);
591
592 r8a66597_bclr(r8a66597, USBE, SYSCFG0);
593 r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
594 r8a66597_bset(r8a66597, USBE, SYSCFG0);
595
596 r8a66597_bset(r8a66597, XCKE, SYSCFG0);
597
598 msleep(3);
599
600 r8a66597_bset(r8a66597, PLLC, SYSCFG0);
601
602 msleep(1);
603
604 r8a66597_bset(r8a66597, SCKE, SYSCFG0);
605
606 r8a66597_bset(r8a66597, irq_sense, INTENB1);
607 r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
608 DMA0CFG);
609 }
610}
611
612static void disable_controller(struct r8a66597 *r8a66597)
613{
614 if (r8a66597->pdata->on_chip) {
615 r8a66597_bset(r8a66597, SCKE, SYSCFG0);
616
617 /* disable interrupts */
618 r8a66597_write(r8a66597, 0, INTENB0);
619 r8a66597_write(r8a66597, 0, INTENB1);
620 r8a66597_write(r8a66597, 0, BRDYENB);
621 r8a66597_write(r8a66597, 0, BEMPENB);
622 r8a66597_write(r8a66597, 0, NRDYENB);
623
624 /* clear status */
625 r8a66597_write(r8a66597, 0, BRDYSTS);
626 r8a66597_write(r8a66597, 0, NRDYSTS);
627 r8a66597_write(r8a66597, 0, BEMPSTS);
628
629 r8a66597_bclr(r8a66597, USBE, SYSCFG0);
630 r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
631
632 } else {
633 r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
634 udelay(1);
635 r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
636 udelay(1);
637 udelay(1);
638 r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
639 }
640}
641
642static void r8a66597_start_xclock(struct r8a66597 *r8a66597)
643{
644 u16 tmp;
645
646 if (!r8a66597->pdata->on_chip) {
647 tmp = r8a66597_read(r8a66597, SYSCFG0);
648 if (!(tmp & XCKE))
649 r8a66597_bset(r8a66597, XCKE, SYSCFG0);
650 }
651}
652
653static struct r8a66597_request *get_request_from_ep(struct r8a66597_ep *ep)
654{
655 return list_entry(ep->queue.next, struct r8a66597_request, queue);
656}
657
658/*-------------------------------------------------------------------------*/
659static void transfer_complete(struct r8a66597_ep *ep,
660 struct r8a66597_request *req, int status)
661__releases(r8a66597->lock)
662__acquires(r8a66597->lock)
663{
664 int restart = 0;
665
666 if (unlikely(ep->pipenum == 0)) {
667 if (ep->internal_ccpl) {
668 ep->internal_ccpl = 0;
669 return;
670 }
671 }
672
673 list_del_init(&req->queue);
674 if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
675 req->req.status = -ESHUTDOWN;
676 else
677 req->req.status = status;
678
679 if (!list_empty(&ep->queue))
680 restart = 1;
681
682 spin_unlock(&ep->r8a66597->lock);
683 req->req.complete(&ep->ep, &req->req);
684 spin_lock(&ep->r8a66597->lock);
685
686 if (restart) {
687 req = get_request_from_ep(ep);
688 if (ep->desc)
689 start_packet(ep, req);
690 }
691}
692
693static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req)
694{
695 int i;
696 u16 tmp;
697 unsigned bufsize;
698 size_t size;
699 void *buf;
700 u16 pipenum = ep->pipenum;
701 struct r8a66597 *r8a66597 = ep->r8a66597;
702
703 pipe_change(r8a66597, pipenum);
704 r8a66597_bset(r8a66597, ISEL, ep->fifosel);
705
706 i = 0;
707 do {
708 tmp = r8a66597_read(r8a66597, ep->fifoctr);
709 if (i++ > 100000) {
710 printk(KERN_ERR "pipe0 is busy. maybe cpu i/o bus"
711 "conflict. please power off this controller.");
712 return;
713 }
714 ndelay(1);
715 } while ((tmp & FRDY) == 0);
716
717 /* prepare parameters */
718 bufsize = get_buffer_size(r8a66597, pipenum);
719 buf = req->req.buf + req->req.actual;
720 size = min(bufsize, req->req.length - req->req.actual);
721
722 /* write fifo */
723 if (req->req.buf) {
724 if (size > 0)
725 r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
726 if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
727 r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
728 }
729
730 /* update parameters */
731 req->req.actual += size;
732
733 /* check transfer finish */
734 if ((!req->req.zero && (req->req.actual == req->req.length))
735 || (size % ep->ep.maxpacket)
736 || (size == 0)) {
737 disable_irq_ready(r8a66597, pipenum);
738 disable_irq_empty(r8a66597, pipenum);
739 } else {
740 disable_irq_ready(r8a66597, pipenum);
741 enable_irq_empty(r8a66597, pipenum);
742 }
743 pipe_start(r8a66597, pipenum);
744}
745
746static void irq_packet_write(struct r8a66597_ep *ep,
747 struct r8a66597_request *req)
748{
749 u16 tmp;
750 unsigned bufsize;
751 size_t size;
752 void *buf;
753 u16 pipenum = ep->pipenum;
754 struct r8a66597 *r8a66597 = ep->r8a66597;
755
756 pipe_change(r8a66597, pipenum);
757 tmp = r8a66597_read(r8a66597, ep->fifoctr);
758 if (unlikely((tmp & FRDY) == 0)) {
759 pipe_stop(r8a66597, pipenum);
760 pipe_irq_disable(r8a66597, pipenum);
761 printk(KERN_ERR "write fifo not ready. pipnum=%d\n", pipenum);
762 return;
763 }
764
765 /* prepare parameters */
766 bufsize = get_buffer_size(r8a66597, pipenum);
767 buf = req->req.buf + req->req.actual;
768 size = min(bufsize, req->req.length - req->req.actual);
769
770 /* write fifo */
771 if (req->req.buf) {
772 r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
773 if ((size == 0)
774 || ((size % ep->ep.maxpacket) != 0)
775 || ((bufsize != ep->ep.maxpacket)
776 && (bufsize > size)))
777 r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
778 }
779
780 /* update parameters */
781 req->req.actual += size;
782 /* check transfer finish */
783 if ((!req->req.zero && (req->req.actual == req->req.length))
784 || (size % ep->ep.maxpacket)
785 || (size == 0)) {
786 disable_irq_ready(r8a66597, pipenum);
787 enable_irq_empty(r8a66597, pipenum);
788 } else {
789 disable_irq_empty(r8a66597, pipenum);
790 pipe_irq_enable(r8a66597, pipenum);
791 }
792}
793
794static void irq_packet_read(struct r8a66597_ep *ep,
795 struct r8a66597_request *req)
796{
797 u16 tmp;
798 int rcv_len, bufsize, req_len;
799 int size;
800 void *buf;
801 u16 pipenum = ep->pipenum;
802 struct r8a66597 *r8a66597 = ep->r8a66597;
803 int finish = 0;
804
805 pipe_change(r8a66597, pipenum);
806 tmp = r8a66597_read(r8a66597, ep->fifoctr);
807 if (unlikely((tmp & FRDY) == 0)) {
808 req->req.status = -EPIPE;
809 pipe_stop(r8a66597, pipenum);
810 pipe_irq_disable(r8a66597, pipenum);
811 printk(KERN_ERR "read fifo not ready");
812 return;
813 }
814
815 /* prepare parameters */
816 rcv_len = tmp & DTLN;
817 bufsize = get_buffer_size(r8a66597, pipenum);
818
819 buf = req->req.buf + req->req.actual;
820 req_len = req->req.length - req->req.actual;
821 if (rcv_len < bufsize)
822 size = min(rcv_len, req_len);
823 else
824 size = min(bufsize, req_len);
825
826 /* update parameters */
827 req->req.actual += size;
828
829 /* check transfer finish */
830 if ((!req->req.zero && (req->req.actual == req->req.length))
831 || (size % ep->ep.maxpacket)
832 || (size == 0)) {
833 pipe_stop(r8a66597, pipenum);
834 pipe_irq_disable(r8a66597, pipenum);
835 finish = 1;
836 }
837
838 /* read fifo */
839 if (req->req.buf) {
840 if (size == 0)
841 r8a66597_write(r8a66597, BCLR, ep->fifoctr);
842 else
843 r8a66597_read_fifo(r8a66597, ep->fifoaddr, buf, size);
844
845 }
846
847 if ((ep->pipenum != 0) && finish)
848 transfer_complete(ep, req, 0);
849}
850
851static void irq_pipe_ready(struct r8a66597 *r8a66597, u16 status, u16 enb)
852{
853 u16 check;
854 u16 pipenum;
855 struct r8a66597_ep *ep;
856 struct r8a66597_request *req;
857
858 if ((status & BRDY0) && (enb & BRDY0)) {
859 r8a66597_write(r8a66597, ~BRDY0, BRDYSTS);
860 r8a66597_mdfy(r8a66597, 0, CURPIPE, CFIFOSEL);
861
862 ep = &r8a66597->ep[0];
863 req = get_request_from_ep(ep);
864 irq_packet_read(ep, req);
865 } else {
866 for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
867 check = 1 << pipenum;
868 if ((status & check) && (enb & check)) {
869 r8a66597_write(r8a66597, ~check, BRDYSTS);
870 ep = r8a66597->pipenum2ep[pipenum];
871 req = get_request_from_ep(ep);
872 if (ep->desc->bEndpointAddress & USB_DIR_IN)
873 irq_packet_write(ep, req);
874 else
875 irq_packet_read(ep, req);
876 }
877 }
878 }
879}
880
881static void irq_pipe_empty(struct r8a66597 *r8a66597, u16 status, u16 enb)
882{
883 u16 tmp;
884 u16 check;
885 u16 pipenum;
886 struct r8a66597_ep *ep;
887 struct r8a66597_request *req;
888
889 if ((status & BEMP0) && (enb & BEMP0)) {
890 r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
891
892 ep = &r8a66597->ep[0];
893 req = get_request_from_ep(ep);
894 irq_ep0_write(ep, req);
895 } else {
896 for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
897 check = 1 << pipenum;
898 if ((status & check) && (enb & check)) {
899 r8a66597_write(r8a66597, ~check, BEMPSTS);
900 tmp = control_reg_get(r8a66597, pipenum);
901 if ((tmp & INBUFM) == 0) {
902 disable_irq_empty(r8a66597, pipenum);
903 pipe_irq_disable(r8a66597, pipenum);
904 pipe_stop(r8a66597, pipenum);
905 ep = r8a66597->pipenum2ep[pipenum];
906 req = get_request_from_ep(ep);
907 if (!list_empty(&ep->queue))
908 transfer_complete(ep, req, 0);
909 }
910 }
911 }
912 }
913}
914
915static void get_status(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
916__releases(r8a66597->lock)
917__acquires(r8a66597->lock)
918{
919 struct r8a66597_ep *ep;
920 u16 pid;
921 u16 status = 0;
922 u16 w_index = le16_to_cpu(ctrl->wIndex);
923
924 switch (ctrl->bRequestType & USB_RECIP_MASK) {
925 case USB_RECIP_DEVICE:
926 status = 1 << USB_DEVICE_SELF_POWERED;
927 break;
928 case USB_RECIP_INTERFACE:
929 status = 0;
930 break;
931 case USB_RECIP_ENDPOINT:
932 ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
933 pid = control_reg_get_pid(r8a66597, ep->pipenum);
934 if (pid == PID_STALL)
935 status = 1 << USB_ENDPOINT_HALT;
936 else
937 status = 0;
938 break;
939 default:
940 pipe_stall(r8a66597, 0);
941 return; /* exit */
942 }
943
944 r8a66597->ep0_data = cpu_to_le16(status);
945 r8a66597->ep0_req->buf = &r8a66597->ep0_data;
946 r8a66597->ep0_req->length = 2;
947 /* AV: what happens if we get called again before that gets through? */
948 spin_unlock(&r8a66597->lock);
949 r8a66597_queue(r8a66597->gadget.ep0, r8a66597->ep0_req, GFP_KERNEL);
950 spin_lock(&r8a66597->lock);
951}
952
953static void clear_feature(struct r8a66597 *r8a66597,
954 struct usb_ctrlrequest *ctrl)
955{
956 switch (ctrl->bRequestType & USB_RECIP_MASK) {
957 case USB_RECIP_DEVICE:
958 control_end(r8a66597, 1);
959 break;
960 case USB_RECIP_INTERFACE:
961 control_end(r8a66597, 1);
962 break;
963 case USB_RECIP_ENDPOINT: {
964 struct r8a66597_ep *ep;
965 struct r8a66597_request *req;
966 u16 w_index = le16_to_cpu(ctrl->wIndex);
967
968 ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
969 if (!ep->wedge) {
970 pipe_stop(r8a66597, ep->pipenum);
971 control_reg_sqclr(r8a66597, ep->pipenum);
972 spin_unlock(&r8a66597->lock);
973 usb_ep_clear_halt(&ep->ep);
974 spin_lock(&r8a66597->lock);
975 }
976
977 control_end(r8a66597, 1);
978
979 req = get_request_from_ep(ep);
980 if (ep->busy) {
981 ep->busy = 0;
982 if (list_empty(&ep->queue))
983 break;
984 start_packet(ep, req);
985 } else if (!list_empty(&ep->queue))
986 pipe_start(r8a66597, ep->pipenum);
987 }
988 break;
989 default:
990 pipe_stall(r8a66597, 0);
991 break;
992 }
993}
994
995static void set_feature(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
996{
997
998 switch (ctrl->bRequestType & USB_RECIP_MASK) {
999 case USB_RECIP_DEVICE:
1000 control_end(r8a66597, 1);
1001 break;
1002 case USB_RECIP_INTERFACE:
1003 control_end(r8a66597, 1);
1004 break;
1005 case USB_RECIP_ENDPOINT: {
1006 struct r8a66597_ep *ep;
1007 u16 w_index = le16_to_cpu(ctrl->wIndex);
1008
1009 ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
1010 pipe_stall(r8a66597, ep->pipenum);
1011
1012 control_end(r8a66597, 1);
1013 }
1014 break;
1015 default:
1016 pipe_stall(r8a66597, 0);
1017 break;
1018 }
1019}
1020
1021/* if return value is true, call class driver's setup() */
1022static int setup_packet(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
1023{
1024 u16 *p = (u16 *)ctrl;
1025 unsigned long offset = USBREQ;
1026 int i, ret = 0;
1027
1028 /* read fifo */
1029 r8a66597_write(r8a66597, ~VALID, INTSTS0);
1030
1031 for (i = 0; i < 4; i++)
1032 p[i] = r8a66597_read(r8a66597, offset + i*2);
1033
1034 /* check request */
1035 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1036 switch (ctrl->bRequest) {
1037 case USB_REQ_GET_STATUS:
1038 get_status(r8a66597, ctrl);
1039 break;
1040 case USB_REQ_CLEAR_FEATURE:
1041 clear_feature(r8a66597, ctrl);
1042 break;
1043 case USB_REQ_SET_FEATURE:
1044 set_feature(r8a66597, ctrl);
1045 break;
1046 default:
1047 ret = 1;
1048 break;
1049 }
1050 } else
1051 ret = 1;
1052 return ret;
1053}
1054
1055static void r8a66597_update_usb_speed(struct r8a66597 *r8a66597)
1056{
1057 u16 speed = get_usb_speed(r8a66597);
1058
1059 switch (speed) {
1060 case HSMODE:
1061 r8a66597->gadget.speed = USB_SPEED_HIGH;
1062 break;
1063 case FSMODE:
1064 r8a66597->gadget.speed = USB_SPEED_FULL;
1065 break;
1066 default:
1067 r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
1068 printk(KERN_ERR "USB speed unknown\n");
1069 }
1070}
1071
1072static void irq_device_state(struct r8a66597 *r8a66597)
1073{
1074 u16 dvsq;
1075
1076 dvsq = r8a66597_read(r8a66597, INTSTS0) & DVSQ;
1077 r8a66597_write(r8a66597, ~DVST, INTSTS0);
1078
1079 if (dvsq == DS_DFLT) {
1080 /* bus reset */
1081 r8a66597->driver->disconnect(&r8a66597->gadget);
1082 r8a66597_update_usb_speed(r8a66597);
1083 }
1084 if (r8a66597->old_dvsq == DS_CNFG && dvsq != DS_CNFG)
1085 r8a66597_update_usb_speed(r8a66597);
1086 if ((dvsq == DS_CNFG || dvsq == DS_ADDS)
1087 && r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
1088 r8a66597_update_usb_speed(r8a66597);
1089
1090 r8a66597->old_dvsq = dvsq;
1091}
1092
1093static void irq_control_stage(struct r8a66597 *r8a66597)
1094__releases(r8a66597->lock)
1095__acquires(r8a66597->lock)
1096{
1097 struct usb_ctrlrequest ctrl;
1098 u16 ctsq;
1099
1100 ctsq = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
1101 r8a66597_write(r8a66597, ~CTRT, INTSTS0);
1102
1103 switch (ctsq) {
1104 case CS_IDST: {
1105 struct r8a66597_ep *ep;
1106 struct r8a66597_request *req;
1107 ep = &r8a66597->ep[0];
1108 req = get_request_from_ep(ep);
1109 transfer_complete(ep, req, 0);
1110 }
1111 break;
1112
1113 case CS_RDDS:
1114 case CS_WRDS:
1115 case CS_WRND:
1116 if (setup_packet(r8a66597, &ctrl)) {
1117 spin_unlock(&r8a66597->lock);
1118 if (r8a66597->driver->setup(&r8a66597->gadget, &ctrl)
1119 < 0)
1120 pipe_stall(r8a66597, 0);
1121 spin_lock(&r8a66597->lock);
1122 }
1123 break;
1124 case CS_RDSS:
1125 case CS_WRSS:
1126 control_end(r8a66597, 0);
1127 break;
1128 default:
1129 printk(KERN_ERR "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
1130 break;
1131 }
1132}
1133
1134static irqreturn_t r8a66597_irq(int irq, void *_r8a66597)
1135{
1136 struct r8a66597 *r8a66597 = _r8a66597;
1137 u16 intsts0;
1138 u16 intenb0;
1139 u16 brdysts, nrdysts, bempsts;
1140 u16 brdyenb, nrdyenb, bempenb;
1141 u16 savepipe;
1142 u16 mask0;
1143
1144 spin_lock(&r8a66597->lock);
1145
1146 intsts0 = r8a66597_read(r8a66597, INTSTS0);
1147 intenb0 = r8a66597_read(r8a66597, INTENB0);
1148
1149 savepipe = r8a66597_read(r8a66597, CFIFOSEL);
1150
1151 mask0 = intsts0 & intenb0;
1152 if (mask0) {
1153 brdysts = r8a66597_read(r8a66597, BRDYSTS);
1154 nrdysts = r8a66597_read(r8a66597, NRDYSTS);
1155 bempsts = r8a66597_read(r8a66597, BEMPSTS);
1156 brdyenb = r8a66597_read(r8a66597, BRDYENB);
1157 nrdyenb = r8a66597_read(r8a66597, NRDYENB);
1158 bempenb = r8a66597_read(r8a66597, BEMPENB);
1159
1160 if (mask0 & VBINT) {
1161 r8a66597_write(r8a66597, 0xffff & ~VBINT,
1162 INTSTS0);
1163 r8a66597_start_xclock(r8a66597);
1164
1165 /* start vbus sampling */
1166 r8a66597->old_vbus = r8a66597_read(r8a66597, INTSTS0)
1167 & VBSTS;
1168 r8a66597->scount = R8A66597_MAX_SAMPLING;
1169
1170 mod_timer(&r8a66597->timer,
1171 jiffies + msecs_to_jiffies(50));
1172 }
1173 if (intsts0 & DVSQ)
1174 irq_device_state(r8a66597);
1175
1176 if ((intsts0 & BRDY) && (intenb0 & BRDYE)
1177 && (brdysts & brdyenb))
1178 irq_pipe_ready(r8a66597, brdysts, brdyenb);
1179 if ((intsts0 & BEMP) && (intenb0 & BEMPE)
1180 && (bempsts & bempenb))
1181 irq_pipe_empty(r8a66597, bempsts, bempenb);
1182
1183 if (intsts0 & CTRT)
1184 irq_control_stage(r8a66597);
1185 }
1186
1187 r8a66597_write(r8a66597, savepipe, CFIFOSEL);
1188
1189 spin_unlock(&r8a66597->lock);
1190 return IRQ_HANDLED;
1191}
1192
1193static void r8a66597_timer(unsigned long _r8a66597)
1194{
1195 struct r8a66597 *r8a66597 = (struct r8a66597 *)_r8a66597;
1196 unsigned long flags;
1197 u16 tmp;
1198
1199 spin_lock_irqsave(&r8a66597->lock, flags);
1200 tmp = r8a66597_read(r8a66597, SYSCFG0);
1201 if (r8a66597->scount > 0) {
1202 tmp = r8a66597_read(r8a66597, INTSTS0) & VBSTS;
1203 if (tmp == r8a66597->old_vbus) {
1204 r8a66597->scount--;
1205 if (r8a66597->scount == 0) {
1206 if (tmp == VBSTS)
1207 r8a66597_usb_connect(r8a66597);
1208 else
1209 r8a66597_usb_disconnect(r8a66597);
1210 } else {
1211 mod_timer(&r8a66597->timer,
1212 jiffies + msecs_to_jiffies(50));
1213 }
1214 } else {
1215 r8a66597->scount = R8A66597_MAX_SAMPLING;
1216 r8a66597->old_vbus = tmp;
1217 mod_timer(&r8a66597->timer,
1218 jiffies + msecs_to_jiffies(50));
1219 }
1220 }
1221 spin_unlock_irqrestore(&r8a66597->lock, flags);
1222}
1223
1224/*-------------------------------------------------------------------------*/
1225static int r8a66597_enable(struct usb_ep *_ep,
1226 const struct usb_endpoint_descriptor *desc)
1227{
1228 struct r8a66597_ep *ep;
1229
1230 ep = container_of(_ep, struct r8a66597_ep, ep);
1231 return alloc_pipe_config(ep, desc);
1232}
1233
1234static int r8a66597_disable(struct usb_ep *_ep)
1235{
1236 struct r8a66597_ep *ep;
1237 struct r8a66597_request *req;
1238 unsigned long flags;
1239
1240 ep = container_of(_ep, struct r8a66597_ep, ep);
1241 BUG_ON(!ep);
1242
1243 while (!list_empty(&ep->queue)) {
1244 req = get_request_from_ep(ep);
1245 spin_lock_irqsave(&ep->r8a66597->lock, flags);
1246 transfer_complete(ep, req, -ECONNRESET);
1247 spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
1248 }
1249
1250 pipe_irq_disable(ep->r8a66597, ep->pipenum);
1251 return free_pipe_config(ep);
1252}
1253
1254static struct usb_request *r8a66597_alloc_request(struct usb_ep *_ep,
1255 gfp_t gfp_flags)
1256{
1257 struct r8a66597_request *req;
1258
1259 req = kzalloc(sizeof(struct r8a66597_request), gfp_flags);
1260 if (!req)
1261 return NULL;
1262
1263 INIT_LIST_HEAD(&req->queue);
1264
1265 return &req->req;
1266}
1267
1268static void r8a66597_free_request(struct usb_ep *_ep, struct usb_request *_req)
1269{
1270 struct r8a66597_request *req;
1271
1272 req = container_of(_req, struct r8a66597_request, req);
1273 kfree(req);
1274}
1275
1276static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
1277 gfp_t gfp_flags)
1278{
1279 struct r8a66597_ep *ep;
1280 struct r8a66597_request *req;
1281 unsigned long flags;
1282 int request = 0;
1283
1284 ep = container_of(_ep, struct r8a66597_ep, ep);
1285 req = container_of(_req, struct r8a66597_request, req);
1286
1287 if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
1288 return -ESHUTDOWN;
1289
1290 spin_lock_irqsave(&ep->r8a66597->lock, flags);
1291
1292 if (list_empty(&ep->queue))
1293 request = 1;
1294
1295 list_add_tail(&req->queue, &ep->queue);
1296 req->req.actual = 0;
1297 req->req.status = -EINPROGRESS;
1298
1299 if (ep->desc == NULL) /* control */
1300 start_ep0(ep, req);
1301 else {
1302 if (request && !ep->busy)
1303 start_packet(ep, req);
1304 }
1305
1306 spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
1307
1308 return 0;
1309}
1310
1311static int r8a66597_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1312{
1313 struct r8a66597_ep *ep;
1314 struct r8a66597_request *req;
1315 unsigned long flags;
1316
1317 ep = container_of(_ep, struct r8a66597_ep, ep);
1318 req = container_of(_req, struct r8a66597_request, req);
1319
1320 spin_lock_irqsave(&ep->r8a66597->lock, flags);
1321 if (!list_empty(&ep->queue))
1322 transfer_complete(ep, req, -ECONNRESET);
1323 spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
1324
1325 return 0;
1326}
1327
1328static int r8a66597_set_halt(struct usb_ep *_ep, int value)
1329{
1330 struct r8a66597_ep *ep;
1331 struct r8a66597_request *req;
1332 unsigned long flags;
1333 int ret = 0;
1334
1335 ep = container_of(_ep, struct r8a66597_ep, ep);
1336 req = get_request_from_ep(ep);
1337
1338 spin_lock_irqsave(&ep->r8a66597->lock, flags);
1339 if (!list_empty(&ep->queue)) {
1340 ret = -EAGAIN;
1341 goto out;
1342 }
1343 if (value) {
1344 ep->busy = 1;
1345 pipe_stall(ep->r8a66597, ep->pipenum);
1346 } else {
1347 ep->busy = 0;
1348 ep->wedge = 0;
1349 pipe_stop(ep->r8a66597, ep->pipenum);
1350 }
1351
1352out:
1353 spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
1354 return ret;
1355}
1356
1357static int r8a66597_set_wedge(struct usb_ep *_ep)
1358{
1359 struct r8a66597_ep *ep;
1360 unsigned long flags;
1361
1362 ep = container_of(_ep, struct r8a66597_ep, ep);
1363
1364 if (!ep || !ep->desc)
1365 return -EINVAL;
1366
1367 spin_lock_irqsave(&ep->r8a66597->lock, flags);
1368 ep->wedge = 1;
1369 spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
1370
1371 return usb_ep_set_halt(_ep);
1372}
1373
1374static void r8a66597_fifo_flush(struct usb_ep *_ep)
1375{
1376 struct r8a66597_ep *ep;
1377 unsigned long flags;
1378
1379 ep = container_of(_ep, struct r8a66597_ep, ep);
1380 spin_lock_irqsave(&ep->r8a66597->lock, flags);
1381 if (list_empty(&ep->queue) && !ep->busy) {
1382 pipe_stop(ep->r8a66597, ep->pipenum);
1383 r8a66597_bclr(ep->r8a66597, BCLR, ep->fifoctr);
1384 }
1385 spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
1386}
1387
1388static struct usb_ep_ops r8a66597_ep_ops = {
1389 .enable = r8a66597_enable,
1390 .disable = r8a66597_disable,
1391
1392 .alloc_request = r8a66597_alloc_request,
1393 .free_request = r8a66597_free_request,
1394
1395 .queue = r8a66597_queue,
1396 .dequeue = r8a66597_dequeue,
1397
1398 .set_halt = r8a66597_set_halt,
1399 .set_wedge = r8a66597_set_wedge,
1400 .fifo_flush = r8a66597_fifo_flush,
1401};
1402
1403/*-------------------------------------------------------------------------*/
1404static struct r8a66597 *the_controller;
1405
1406int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1407{
1408 struct r8a66597 *r8a66597 = the_controller;
1409 int retval;
1410
1411 if (!driver
1412 || driver->speed != USB_SPEED_HIGH
1413 || !driver->bind
1414 || !driver->setup)
1415 return -EINVAL;
1416 if (!r8a66597)
1417 return -ENODEV;
1418 if (r8a66597->driver)
1419 return -EBUSY;
1420
1421 /* hook up the driver */
1422 driver->driver.bus = NULL;
1423 r8a66597->driver = driver;
1424 r8a66597->gadget.dev.driver = &driver->driver;
1425
1426 retval = device_add(&r8a66597->gadget.dev);
1427 if (retval) {
1428 printk(KERN_ERR "device_add error (%d)\n", retval);
1429 goto error;
1430 }
1431
1432 retval = driver->bind(&r8a66597->gadget);
1433 if (retval) {
1434 printk(KERN_ERR "bind to driver error (%d)\n", retval);
1435 device_del(&r8a66597->gadget.dev);
1436 goto error;
1437 }
1438
1439 r8a66597_bset(r8a66597, VBSE, INTENB0);
1440 if (r8a66597_read(r8a66597, INTSTS0) & VBSTS) {
1441 r8a66597_start_xclock(r8a66597);
1442 /* start vbus sampling */
1443 r8a66597->old_vbus = r8a66597_read(r8a66597,
1444 INTSTS0) & VBSTS;
1445 r8a66597->scount = R8A66597_MAX_SAMPLING;
1446 mod_timer(&r8a66597->timer, jiffies + msecs_to_jiffies(50));
1447 }
1448
1449 return 0;
1450
1451error:
1452 r8a66597->driver = NULL;
1453 r8a66597->gadget.dev.driver = NULL;
1454
1455 return retval;
1456}
1457EXPORT_SYMBOL(usb_gadget_register_driver);
1458
1459int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1460{
1461 struct r8a66597 *r8a66597 = the_controller;
1462 unsigned long flags;
1463
1464 if (driver != r8a66597->driver || !driver->unbind)
1465 return -EINVAL;
1466
1467 spin_lock_irqsave(&r8a66597->lock, flags);
1468 if (r8a66597->gadget.speed != USB_SPEED_UNKNOWN)
1469 r8a66597_usb_disconnect(r8a66597);
1470 spin_unlock_irqrestore(&r8a66597->lock, flags);
1471
1472 r8a66597_bclr(r8a66597, VBSE, INTENB0);
1473
1474 driver->unbind(&r8a66597->gadget);
1475
1476 init_controller(r8a66597);
1477 disable_controller(r8a66597);
1478
1479 device_del(&r8a66597->gadget.dev);
1480 r8a66597->driver = NULL;
1481 return 0;
1482}
1483EXPORT_SYMBOL(usb_gadget_unregister_driver);
1484
1485/*-------------------------------------------------------------------------*/
1486static int r8a66597_get_frame(struct usb_gadget *_gadget)
1487{
1488 struct r8a66597 *r8a66597 = gadget_to_r8a66597(_gadget);
1489 return r8a66597_read(r8a66597, FRMNUM) & 0x03FF;
1490}
1491
1492static struct usb_gadget_ops r8a66597_gadget_ops = {
1493 .get_frame = r8a66597_get_frame,
1494};
1495
1496static int __exit r8a66597_remove(struct platform_device *pdev)
1497{
1498 struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
1499
1500 del_timer_sync(&r8a66597->timer);
1501 iounmap((void *)r8a66597->reg);
1502 free_irq(platform_get_irq(pdev, 0), r8a66597);
1503 r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
1504#ifdef CONFIG_HAVE_CLK
1505 if (r8a66597->pdata->on_chip) {
1506 clk_disable(r8a66597->clk);
1507 clk_put(r8a66597->clk);
1508 }
1509#endif
1510 kfree(r8a66597);
1511 return 0;
1512}
1513
1514static void nop_completion(struct usb_ep *ep, struct usb_request *r)
1515{
1516}
1517
1518static int __init r8a66597_probe(struct platform_device *pdev)
1519{
1520#ifdef CONFIG_HAVE_CLK
1521 char clk_name[8];
1522#endif
1523 struct resource *res, *ires;
1524 int irq;
1525 void __iomem *reg = NULL;
1526 struct r8a66597 *r8a66597 = NULL;
1527 int ret = 0;
1528 int i;
1529 unsigned long irq_trigger;
1530
1531 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1532 if (!res) {
1533 ret = -ENODEV;
1534 printk(KERN_ERR "platform_get_resource error.\n");
1535 goto clean_up;
1536 }
1537
1538 ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1539 irq = ires->start;
1540 irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
1541
1542 if (irq < 0) {
1543 ret = -ENODEV;
1544 printk(KERN_ERR "platform_get_irq error.\n");
1545 goto clean_up;
1546 }
1547
1548 reg = ioremap(res->start, resource_size(res));
1549 if (reg == NULL) {
1550 ret = -ENOMEM;
1551 printk(KERN_ERR "ioremap error.\n");
1552 goto clean_up;
1553 }
1554
1555 /* initialize ucd */
1556 r8a66597 = kzalloc(sizeof(struct r8a66597), GFP_KERNEL);
1557 if (r8a66597 == NULL) {
1558 printk(KERN_ERR "kzalloc error\n");
1559 goto clean_up;
1560 }
1561
1562 spin_lock_init(&r8a66597->lock);
1563 dev_set_drvdata(&pdev->dev, r8a66597);
1564 r8a66597->pdata = pdev->dev.platform_data;
1565 r8a66597->irq_sense_low = irq_trigger == IRQF_TRIGGER_LOW;
1566
1567 r8a66597->gadget.ops = &r8a66597_gadget_ops;
1568 device_initialize(&r8a66597->gadget.dev);
1569 dev_set_name(&r8a66597->gadget.dev, "gadget");
1570 r8a66597->gadget.is_dualspeed = 1;
1571 r8a66597->gadget.dev.parent = &pdev->dev;
1572 r8a66597->gadget.dev.dma_mask = pdev->dev.dma_mask;
1573 r8a66597->gadget.dev.release = pdev->dev.release;
1574 r8a66597->gadget.name = udc_name;
1575
1576 init_timer(&r8a66597->timer);
1577 r8a66597->timer.function = r8a66597_timer;
1578 r8a66597->timer.data = (unsigned long)r8a66597;
1579 r8a66597->reg = (unsigned long)reg;
1580
1581#ifdef CONFIG_HAVE_CLK
1582 if (r8a66597->pdata->on_chip) {
1583 snprintf(clk_name, sizeof(clk_name), "usb%d", pdev->id);
1584 r8a66597->clk = clk_get(&pdev->dev, clk_name);
1585 if (IS_ERR(r8a66597->clk)) {
1586 dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
1587 clk_name);
1588 ret = PTR_ERR(r8a66597->clk);
1589 goto clean_up;
1590 }
1591 clk_enable(r8a66597->clk);
1592 }
1593#endif
1594
1595 disable_controller(r8a66597); /* make sure controller is disabled */
1596
1597 ret = request_irq(irq, r8a66597_irq, IRQF_DISABLED | IRQF_SHARED,
1598 udc_name, r8a66597);
1599 if (ret < 0) {
1600 printk(KERN_ERR "request_irq error (%d)\n", ret);
1601 goto clean_up2;
1602 }
1603
1604 INIT_LIST_HEAD(&r8a66597->gadget.ep_list);
1605 r8a66597->gadget.ep0 = &r8a66597->ep[0].ep;
1606 INIT_LIST_HEAD(&r8a66597->gadget.ep0->ep_list);
1607 for (i = 0; i < R8A66597_MAX_NUM_PIPE; i++) {
1608 struct r8a66597_ep *ep = &r8a66597->ep[i];
1609
1610 if (i != 0) {
1611 INIT_LIST_HEAD(&r8a66597->ep[i].ep.ep_list);
1612 list_add_tail(&r8a66597->ep[i].ep.ep_list,
1613 &r8a66597->gadget.ep_list);
1614 }
1615 ep->r8a66597 = r8a66597;
1616 INIT_LIST_HEAD(&ep->queue);
1617 ep->ep.name = r8a66597_ep_name[i];
1618 ep->ep.ops = &r8a66597_ep_ops;
1619 ep->ep.maxpacket = 512;
1620 }
1621 r8a66597->ep[0].ep.maxpacket = 64;
1622 r8a66597->ep[0].pipenum = 0;
1623 r8a66597->ep[0].fifoaddr = CFIFO;
1624 r8a66597->ep[0].fifosel = CFIFOSEL;
1625 r8a66597->ep[0].fifoctr = CFIFOCTR;
1626 r8a66597->ep[0].fifotrn = 0;
1627 r8a66597->ep[0].pipectr = get_pipectr_addr(0);
1628 r8a66597->pipenum2ep[0] = &r8a66597->ep[0];
1629 r8a66597->epaddr2ep[0] = &r8a66597->ep[0];
1630
1631 the_controller = r8a66597;
1632
1633 r8a66597->ep0_req = r8a66597_alloc_request(&r8a66597->ep[0].ep,
1634 GFP_KERNEL);
1635 if (r8a66597->ep0_req == NULL)
1636 goto clean_up3;
1637 r8a66597->ep0_req->complete = nop_completion;
1638
1639 init_controller(r8a66597);
1640
1641 dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
1642 return 0;
1643
1644clean_up3:
1645 free_irq(irq, r8a66597);
1646clean_up2:
1647#ifdef CONFIG_HAVE_CLK
1648 if (r8a66597->pdata->on_chip) {
1649 clk_disable(r8a66597->clk);
1650 clk_put(r8a66597->clk);
1651 }
1652#endif
1653clean_up:
1654 if (r8a66597) {
1655 if (r8a66597->ep0_req)
1656 r8a66597_free_request(&r8a66597->ep[0].ep,
1657 r8a66597->ep0_req);
1658 kfree(r8a66597);
1659 }
1660 if (reg)
1661 iounmap(reg);
1662
1663 return ret;
1664}
1665
1666/*-------------------------------------------------------------------------*/
1667static struct platform_driver r8a66597_driver = {
1668 .remove = __exit_p(r8a66597_remove),
1669 .driver = {
1670 .name = (char *) udc_name,
1671 },
1672};
1673
1674static int __init r8a66597_udc_init(void)
1675{
1676 return platform_driver_probe(&r8a66597_driver, r8a66597_probe);
1677}
1678module_init(r8a66597_udc_init);
1679
1680static void __exit r8a66597_udc_cleanup(void)
1681{
1682 platform_driver_unregister(&r8a66597_driver);
1683}
1684module_exit(r8a66597_udc_cleanup);
1685
1686MODULE_DESCRIPTION("R8A66597 USB gadget driver");
1687MODULE_LICENSE("GPL");
1688MODULE_AUTHOR("Yoshihiro Shimoda");
1689
diff --git a/drivers/usb/gadget/r8a66597-udc.h b/drivers/usb/gadget/r8a66597-udc.h
new file mode 100644
index 000000000000..03087e7b9190
--- /dev/null
+++ b/drivers/usb/gadget/r8a66597-udc.h
@@ -0,0 +1,256 @@
1/*
2 * R8A66597 UDC
3 *
4 * Copyright (C) 2007-2009 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22
23#ifndef __R8A66597_H__
24#define __R8A66597_H__
25
26#ifdef CONFIG_HAVE_CLK
27#include <linux/clk.h>
28#endif
29
30#include <linux/usb/r8a66597.h>
31
32#define R8A66597_MAX_SAMPLING 10
33
34#define R8A66597_MAX_NUM_PIPE 8
35#define R8A66597_MAX_NUM_BULK 3
36#define R8A66597_MAX_NUM_ISOC 2
37#define R8A66597_MAX_NUM_INT 2
38
39#define R8A66597_BASE_PIPENUM_BULK 3
40#define R8A66597_BASE_PIPENUM_ISOC 1
41#define R8A66597_BASE_PIPENUM_INT 6
42
43#define R8A66597_BASE_BUFNUM 6
44#define R8A66597_MAX_BUFNUM 0x4F
45
46#define is_bulk_pipe(pipenum) \
47 ((pipenum >= R8A66597_BASE_PIPENUM_BULK) && \
48 (pipenum < (R8A66597_BASE_PIPENUM_BULK + R8A66597_MAX_NUM_BULK)))
49#define is_interrupt_pipe(pipenum) \
50 ((pipenum >= R8A66597_BASE_PIPENUM_INT) && \
51 (pipenum < (R8A66597_BASE_PIPENUM_INT + R8A66597_MAX_NUM_INT)))
52#define is_isoc_pipe(pipenum) \
53 ((pipenum >= R8A66597_BASE_PIPENUM_ISOC) && \
54 (pipenum < (R8A66597_BASE_PIPENUM_ISOC + R8A66597_MAX_NUM_ISOC)))
55
56struct r8a66597_pipe_info {
57 u16 pipe;
58 u16 epnum;
59 u16 maxpacket;
60 u16 type;
61 u16 interval;
62 u16 dir_in;
63};
64
65struct r8a66597_request {
66 struct usb_request req;
67 struct list_head queue;
68};
69
70struct r8a66597_ep {
71 struct usb_ep ep;
72 struct r8a66597 *r8a66597;
73
74 struct list_head queue;
75 unsigned busy:1;
76 unsigned wedge:1;
77 unsigned internal_ccpl:1; /* use only control */
78
79 /* this member can able to after r8a66597_enable */
80 unsigned use_dma:1;
81 u16 pipenum;
82 u16 type;
83 const struct usb_endpoint_descriptor *desc;
84 /* register address */
85 unsigned char fifoaddr;
86 unsigned char fifosel;
87 unsigned char fifoctr;
88 unsigned char fifotrn;
89 unsigned char pipectr;
90};
91
92struct r8a66597 {
93 spinlock_t lock;
94 unsigned long reg;
95
96#ifdef CONFIG_HAVE_CLK
97 struct clk *clk;
98#endif
99 struct r8a66597_platdata *pdata;
100
101 struct usb_gadget gadget;
102 struct usb_gadget_driver *driver;
103
104 struct r8a66597_ep ep[R8A66597_MAX_NUM_PIPE];
105 struct r8a66597_ep *pipenum2ep[R8A66597_MAX_NUM_PIPE];
106 struct r8a66597_ep *epaddr2ep[16];
107
108 struct timer_list timer;
109 struct usb_request *ep0_req; /* for internal request */
110 u16 ep0_data; /* for internal request */
111 u16 old_vbus;
112 u16 scount;
113 u16 old_dvsq;
114
115 /* pipe config */
116 unsigned char bulk;
117 unsigned char interrupt;
118 unsigned char isochronous;
119 unsigned char num_dma;
120
121 unsigned irq_sense_low:1;
122};
123
124#define gadget_to_r8a66597(_gadget) \
125 container_of(_gadget, struct r8a66597, gadget)
126#define r8a66597_to_gadget(r8a66597) (&r8a66597->gadget)
127
128static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
129{
130 return inw(r8a66597->reg + offset);
131}
132
133static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
134 unsigned long offset, u16 *buf,
135 int len)
136{
137 if (r8a66597->pdata->on_chip) {
138 unsigned long fifoaddr = r8a66597->reg + offset;
139 unsigned long count;
140 union {
141 unsigned long dword;
142 unsigned char byte[4];
143 } data;
144 unsigned char *pb;
145 int i;
146
147 count = len / 4;
148 insl(fifoaddr, buf, count);
149
150 if (len & 0x00000003) {
151 data.dword = inl(fifoaddr);
152 pb = (unsigned char *)buf + count * 4;
153 for (i = 0; i < (len & 0x00000003); i++)
154 pb[i] = data.byte[i];
155 }
156 } else {
157 len = (len + 1) / 2;
158 insw(r8a66597->reg + offset, buf, len);
159 }
160}
161
162static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
163 unsigned long offset)
164{
165 outw(val, r8a66597->reg + offset);
166}
167
168static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
169 unsigned long offset, u16 *buf,
170 int len)
171{
172 unsigned long fifoaddr = r8a66597->reg + offset;
173
174 if (r8a66597->pdata->on_chip) {
175 unsigned long count;
176 unsigned char *pb;
177 int i;
178
179 count = len / 4;
180 outsl(fifoaddr, buf, count);
181
182 if (len & 0x00000003) {
183 pb = (unsigned char *)buf + count * 4;
184 for (i = 0; i < (len & 0x00000003); i++) {
185 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
186 outb(pb[i], fifoaddr + i);
187 else
188 outb(pb[i], fifoaddr + 3 - i);
189 }
190 }
191 } else {
192 int odd = len & 0x0001;
193
194 len = len / 2;
195 outsw(fifoaddr, buf, len);
196 if (unlikely(odd)) {
197 buf = &buf[len];
198 outb((unsigned char)*buf, fifoaddr);
199 }
200 }
201}
202
203static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
204 u16 val, u16 pat, unsigned long offset)
205{
206 u16 tmp;
207 tmp = r8a66597_read(r8a66597, offset);
208 tmp = tmp & (~pat);
209 tmp = tmp | val;
210 r8a66597_write(r8a66597, tmp, offset);
211}
212
213static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
214{
215 u16 clock = 0;
216
217 switch (pdata->xtal) {
218 case R8A66597_PLATDATA_XTAL_12MHZ:
219 clock = XTAL12;
220 break;
221 case R8A66597_PLATDATA_XTAL_24MHZ:
222 clock = XTAL24;
223 break;
224 case R8A66597_PLATDATA_XTAL_48MHZ:
225 clock = XTAL48;
226 break;
227 default:
228 printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
229 break;
230 }
231
232 return clock;
233}
234
235#define r8a66597_bclr(r8a66597, val, offset) \
236 r8a66597_mdfy(r8a66597, 0, val, offset)
237#define r8a66597_bset(r8a66597, val, offset) \
238 r8a66597_mdfy(r8a66597, val, 0, offset)
239
240#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
241
242#define enable_irq_ready(r8a66597, pipenum) \
243 enable_pipe_irq(r8a66597, pipenum, BRDYENB)
244#define disable_irq_ready(r8a66597, pipenum) \
245 disable_pipe_irq(r8a66597, pipenum, BRDYENB)
246#define enable_irq_empty(r8a66597, pipenum) \
247 enable_pipe_irq(r8a66597, pipenum, BEMPENB)
248#define disable_irq_empty(r8a66597, pipenum) \
249 disable_pipe_irq(r8a66597, pipenum, BEMPENB)
250#define enable_irq_nrdy(r8a66597, pipenum) \
251 enable_pipe_irq(r8a66597, pipenum, NRDYENB)
252#define disable_irq_nrdy(r8a66597, pipenum) \
253 disable_pipe_irq(r8a66597, pipenum, NRDYENB)
254
255#endif /* __R8A66597_H__ */
256
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 1a920c70b5a1..f21ca7d27a43 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -336,13 +336,6 @@ config USB_R8A66597_HCD
336 To compile this driver as a module, choose M here: the 336 To compile this driver as a module, choose M here: the
337 module will be called r8a66597-hcd. 337 module will be called r8a66597-hcd.
338 338
339config SUPERH_ON_CHIP_R8A66597
340 boolean "Enable SuperH on-chip R8A66597 USB"
341 depends on USB_R8A66597_HCD && (CPU_SUBTYPE_SH7366 || CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7724)
342 help
343 This driver enables support for the on-chip R8A66597 in the
344 SH7366, SH7723 and SH7724 processors.
345
346config USB_WHCI_HCD 339config USB_WHCI_HCD
347 tristate "Wireless USB Host Controller Interface (WHCI) driver (EXPERIMENTAL)" 340 tristate "Wireless USB Host Controller Interface (WHCI) driver (EXPERIMENTAL)"
348 depends on EXPERIMENTAL 341 depends on EXPERIMENTAL
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
index e18f74946e68..749b53742828 100644
--- a/drivers/usb/host/r8a66597-hcd.c
+++ b/drivers/usb/host/r8a66597-hcd.c
@@ -91,43 +91,43 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597)
91 u16 tmp; 91 u16 tmp;
92 int i = 0; 92 int i = 0;
93 93
94#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) 94 if (r8a66597->pdata->on_chip) {
95#if defined(CONFIG_HAVE_CLK) 95#ifdef CONFIG_HAVE_CLK
96 clk_enable(r8a66597->clk); 96 clk_enable(r8a66597->clk);
97#endif 97#endif
98 do { 98 do {
99 r8a66597_write(r8a66597, SCKE, SYSCFG0); 99 r8a66597_write(r8a66597, SCKE, SYSCFG0);
100 tmp = r8a66597_read(r8a66597, SYSCFG0); 100 tmp = r8a66597_read(r8a66597, SYSCFG0);
101 if (i++ > 1000) { 101 if (i++ > 1000) {
102 printk(KERN_ERR "r8a66597: register access fail.\n"); 102 printk(KERN_ERR "r8a66597: reg access fail.\n");
103 return -ENXIO; 103 return -ENXIO;
104 } 104 }
105 } while ((tmp & SCKE) != SCKE); 105 } while ((tmp & SCKE) != SCKE);
106 r8a66597_write(r8a66597, 0x04, 0x02); 106 r8a66597_write(r8a66597, 0x04, 0x02);
107#else 107 } else {
108 do { 108 do {
109 r8a66597_write(r8a66597, USBE, SYSCFG0); 109 r8a66597_write(r8a66597, USBE, SYSCFG0);
110 tmp = r8a66597_read(r8a66597, SYSCFG0); 110 tmp = r8a66597_read(r8a66597, SYSCFG0);
111 if (i++ > 1000) { 111 if (i++ > 1000) {
112 printk(KERN_ERR "r8a66597: register access fail.\n"); 112 printk(KERN_ERR "r8a66597: reg access fail.\n");
113 return -ENXIO; 113 return -ENXIO;
114 } 114 }
115 } while ((tmp & USBE) != USBE); 115 } while ((tmp & USBE) != USBE);
116 r8a66597_bclr(r8a66597, USBE, SYSCFG0); 116 r8a66597_bclr(r8a66597, USBE, SYSCFG0);
117 r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata), XTAL, 117 r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata),
118 SYSCFG0); 118 XTAL, SYSCFG0);
119 119
120 i = 0; 120 i = 0;
121 r8a66597_bset(r8a66597, XCKE, SYSCFG0); 121 r8a66597_bset(r8a66597, XCKE, SYSCFG0);
122 do { 122 do {
123 msleep(1); 123 msleep(1);
124 tmp = r8a66597_read(r8a66597, SYSCFG0); 124 tmp = r8a66597_read(r8a66597, SYSCFG0);
125 if (i++ > 500) { 125 if (i++ > 500) {
126 printk(KERN_ERR "r8a66597: register access fail.\n"); 126 printk(KERN_ERR "r8a66597: reg access fail.\n");
127 return -ENXIO; 127 return -ENXIO;
128 } 128 }
129 } while ((tmp & SCKE) != SCKE); 129 } while ((tmp & SCKE) != SCKE);
130#endif /* #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) */ 130 }
131 131
132 return 0; 132 return 0;
133} 133}
@@ -136,15 +136,16 @@ static void r8a66597_clock_disable(struct r8a66597 *r8a66597)
136{ 136{
137 r8a66597_bclr(r8a66597, SCKE, SYSCFG0); 137 r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
138 udelay(1); 138 udelay(1);
139#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) 139
140#if defined(CONFIG_HAVE_CLK) 140 if (r8a66597->pdata->on_chip) {
141 clk_disable(r8a66597->clk); 141#ifdef CONFIG_HAVE_CLK
142#endif 142 clk_disable(r8a66597->clk);
143#else
144 r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
145 r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
146 r8a66597_bclr(r8a66597, USBE, SYSCFG0);
147#endif 143#endif
144 } else {
145 r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
146 r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
147 r8a66597_bclr(r8a66597, USBE, SYSCFG0);
148 }
148} 149}
149 150
150static void r8a66597_enable_port(struct r8a66597 *r8a66597, int port) 151static void r8a66597_enable_port(struct r8a66597 *r8a66597, int port)
@@ -205,7 +206,7 @@ static int enable_controller(struct r8a66597 *r8a66597)
205 206
206 r8a66597_bset(r8a66597, SIGNE | SACKE, INTENB1); 207 r8a66597_bset(r8a66597, SIGNE | SACKE, INTENB1);
207 208
208 for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++) 209 for (port = 0; port < r8a66597->max_root_hub; port++)
209 r8a66597_enable_port(r8a66597, port); 210 r8a66597_enable_port(r8a66597, port);
210 211
211 return 0; 212 return 0;
@@ -218,7 +219,7 @@ static void disable_controller(struct r8a66597 *r8a66597)
218 r8a66597_write(r8a66597, 0, INTENB0); 219 r8a66597_write(r8a66597, 0, INTENB0);
219 r8a66597_write(r8a66597, 0, INTSTS0); 220 r8a66597_write(r8a66597, 0, INTSTS0);
220 221
221 for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++) 222 for (port = 0; port < r8a66597->max_root_hub; port++)
222 r8a66597_disable_port(r8a66597, port); 223 r8a66597_disable_port(r8a66597, port);
223 224
224 r8a66597_clock_disable(r8a66597); 225 r8a66597_clock_disable(r8a66597);
@@ -249,11 +250,12 @@ static int is_hub_limit(char *devpath)
249 return ((strlen(devpath) >= 4) ? 1 : 0); 250 return ((strlen(devpath) >= 4) ? 1 : 0);
250} 251}
251 252
252static void get_port_number(char *devpath, u16 *root_port, u16 *hub_port) 253static void get_port_number(struct r8a66597 *r8a66597,
254 char *devpath, u16 *root_port, u16 *hub_port)
253{ 255{
254 if (root_port) { 256 if (root_port) {
255 *root_port = (devpath[0] & 0x0F) - 1; 257 *root_port = (devpath[0] & 0x0F) - 1;
256 if (*root_port >= R8A66597_MAX_ROOT_HUB) 258 if (*root_port >= r8a66597->max_root_hub)
257 printk(KERN_ERR "r8a66597: Illegal root port number.\n"); 259 printk(KERN_ERR "r8a66597: Illegal root port number.\n");
258 } 260 }
259 if (hub_port) 261 if (hub_port)
@@ -355,7 +357,8 @@ static int make_r8a66597_device(struct r8a66597 *r8a66597,
355 INIT_LIST_HEAD(&dev->device_list); 357 INIT_LIST_HEAD(&dev->device_list);
356 list_add_tail(&dev->device_list, &r8a66597->child_device); 358 list_add_tail(&dev->device_list, &r8a66597->child_device);
357 359
358 get_port_number(urb->dev->devpath, &dev->root_port, &dev->hub_port); 360 get_port_number(r8a66597, urb->dev->devpath,
361 &dev->root_port, &dev->hub_port);
359 if (!is_child_device(urb->dev->devpath)) 362 if (!is_child_device(urb->dev->devpath))
360 r8a66597->root_hub[dev->root_port].dev = dev; 363 r8a66597->root_hub[dev->root_port].dev = dev;
361 364
@@ -420,7 +423,7 @@ static void free_usb_address(struct r8a66597 *r8a66597,
420 list_del(&dev->device_list); 423 list_del(&dev->device_list);
421 kfree(dev); 424 kfree(dev);
422 425
423 for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++) { 426 for (port = 0; port < r8a66597->max_root_hub; port++) {
424 if (r8a66597->root_hub[port].dev == dev) { 427 if (r8a66597->root_hub[port].dev == dev) {
425 r8a66597->root_hub[port].dev = NULL; 428 r8a66597->root_hub[port].dev = NULL;
426 break; 429 break;
@@ -495,10 +498,20 @@ static void r8a66597_pipe_toggle(struct r8a66597 *r8a66597,
495 r8a66597_bset(r8a66597, SQCLR, pipe->pipectr); 498 r8a66597_bset(r8a66597, SQCLR, pipe->pipectr);
496} 499}
497 500
501static inline unsigned short mbw_value(struct r8a66597 *r8a66597)
502{
503 if (r8a66597->pdata->on_chip)
504 return MBW_32;
505 else
506 return MBW_16;
507}
508
498/* this function must be called with interrupt disabled */ 509/* this function must be called with interrupt disabled */
499static inline void cfifo_change(struct r8a66597 *r8a66597, u16 pipenum) 510static inline void cfifo_change(struct r8a66597 *r8a66597, u16 pipenum)
500{ 511{
501 r8a66597_mdfy(r8a66597, MBW | pipenum, MBW | CURPIPE, CFIFOSEL); 512 unsigned short mbw = mbw_value(r8a66597);
513
514 r8a66597_mdfy(r8a66597, mbw | pipenum, mbw | CURPIPE, CFIFOSEL);
502 r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, pipenum); 515 r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, pipenum);
503} 516}
504 517
@@ -506,11 +519,13 @@ static inline void cfifo_change(struct r8a66597 *r8a66597, u16 pipenum)
506static inline void fifo_change_from_pipe(struct r8a66597 *r8a66597, 519static inline void fifo_change_from_pipe(struct r8a66597 *r8a66597,
507 struct r8a66597_pipe *pipe) 520 struct r8a66597_pipe *pipe)
508{ 521{
522 unsigned short mbw = mbw_value(r8a66597);
523
509 cfifo_change(r8a66597, 0); 524 cfifo_change(r8a66597, 0);
510 r8a66597_mdfy(r8a66597, MBW | 0, MBW | CURPIPE, D0FIFOSEL); 525 r8a66597_mdfy(r8a66597, mbw | 0, mbw | CURPIPE, D0FIFOSEL);
511 r8a66597_mdfy(r8a66597, MBW | 0, MBW | CURPIPE, D1FIFOSEL); 526 r8a66597_mdfy(r8a66597, mbw | 0, mbw | CURPIPE, D1FIFOSEL);
512 527
513 r8a66597_mdfy(r8a66597, MBW | pipe->info.pipenum, MBW | CURPIPE, 528 r8a66597_mdfy(r8a66597, mbw | pipe->info.pipenum, mbw | CURPIPE,
514 pipe->fifosel); 529 pipe->fifosel);
515 r8a66597_reg_wait(r8a66597, pipe->fifosel, CURPIPE, pipe->info.pipenum); 530 r8a66597_reg_wait(r8a66597, pipe->fifosel, CURPIPE, pipe->info.pipenum);
516} 531}
@@ -742,9 +757,13 @@ static void enable_r8a66597_pipe_dma(struct r8a66597 *r8a66597,
742 struct r8a66597_pipe *pipe, 757 struct r8a66597_pipe *pipe,
743 struct urb *urb) 758 struct urb *urb)
744{ 759{
745#if !defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
746 int i; 760 int i;
747 struct r8a66597_pipe_info *info = &pipe->info; 761 struct r8a66597_pipe_info *info = &pipe->info;
762 unsigned short mbw = mbw_value(r8a66597);
763
764 /* pipe dma is only for external controlles */
765 if (r8a66597->pdata->on_chip)
766 return;
748 767
749 if ((pipe->info.pipenum != 0) && (info->type != R8A66597_INT)) { 768 if ((pipe->info.pipenum != 0) && (info->type != R8A66597_INT)) {
750 for (i = 0; i < R8A66597_MAX_DMA_CHANNEL; i++) { 769 for (i = 0; i < R8A66597_MAX_DMA_CHANNEL; i++) {
@@ -763,8 +782,8 @@ static void enable_r8a66597_pipe_dma(struct r8a66597 *r8a66597,
763 set_pipe_reg_addr(pipe, i); 782 set_pipe_reg_addr(pipe, i);
764 783
765 cfifo_change(r8a66597, 0); 784 cfifo_change(r8a66597, 0);
766 r8a66597_mdfy(r8a66597, MBW | pipe->info.pipenum, 785 r8a66597_mdfy(r8a66597, mbw | pipe->info.pipenum,
767 MBW | CURPIPE, pipe->fifosel); 786 mbw | CURPIPE, pipe->fifosel);
768 787
769 r8a66597_reg_wait(r8a66597, pipe->fifosel, CURPIPE, 788 r8a66597_reg_wait(r8a66597, pipe->fifosel, CURPIPE,
770 pipe->info.pipenum); 789 pipe->info.pipenum);
@@ -772,7 +791,6 @@ static void enable_r8a66597_pipe_dma(struct r8a66597 *r8a66597,
772 break; 791 break;
773 } 792 }
774 } 793 }
775#endif /* #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) */
776} 794}
777 795
778/* this function must be called with interrupt disabled */ 796/* this function must be called with interrupt disabled */
@@ -1769,7 +1787,7 @@ static void r8a66597_timer(unsigned long _r8a66597)
1769 1787
1770 spin_lock_irqsave(&r8a66597->lock, flags); 1788 spin_lock_irqsave(&r8a66597->lock, flags);
1771 1789
1772 for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++) 1790 for (port = 0; port < r8a66597->max_root_hub; port++)
1773 r8a66597_root_hub_control(r8a66597, port); 1791 r8a66597_root_hub_control(r8a66597, port);
1774 1792
1775 spin_unlock_irqrestore(&r8a66597->lock, flags); 1793 spin_unlock_irqrestore(&r8a66597->lock, flags);
@@ -1807,7 +1825,7 @@ static void set_address_zero(struct r8a66597 *r8a66597, struct urb *urb)
1807 u16 root_port, hub_port; 1825 u16 root_port, hub_port;
1808 1826
1809 if (usb_address == 0) { 1827 if (usb_address == 0) {
1810 get_port_number(urb->dev->devpath, 1828 get_port_number(r8a66597, urb->dev->devpath,
1811 &root_port, &hub_port); 1829 &root_port, &hub_port);
1812 set_devadd_reg(r8a66597, 0, 1830 set_devadd_reg(r8a66597, 0,
1813 get_r8a66597_usb_speed(urb->dev->speed), 1831 get_r8a66597_usb_speed(urb->dev->speed),
@@ -2082,7 +2100,7 @@ static int r8a66597_hub_status_data(struct usb_hcd *hcd, char *buf)
2082 2100
2083 *buf = 0; /* initialize (no change) */ 2101 *buf = 0; /* initialize (no change) */
2084 2102
2085 for (i = 0; i < R8A66597_MAX_ROOT_HUB; i++) { 2103 for (i = 0; i < r8a66597->max_root_hub; i++) {
2086 if (r8a66597->root_hub[i].port & 0xffff0000) 2104 if (r8a66597->root_hub[i].port & 0xffff0000)
2087 *buf |= 1 << (i + 1); 2105 *buf |= 1 << (i + 1);
2088 } 2106 }
@@ -2097,11 +2115,11 @@ static void r8a66597_hub_descriptor(struct r8a66597 *r8a66597,
2097{ 2115{
2098 desc->bDescriptorType = 0x29; 2116 desc->bDescriptorType = 0x29;
2099 desc->bHubContrCurrent = 0; 2117 desc->bHubContrCurrent = 0;
2100 desc->bNbrPorts = R8A66597_MAX_ROOT_HUB; 2118 desc->bNbrPorts = r8a66597->max_root_hub;
2101 desc->bDescLength = 9; 2119 desc->bDescLength = 9;
2102 desc->bPwrOn2PwrGood = 0; 2120 desc->bPwrOn2PwrGood = 0;
2103 desc->wHubCharacteristics = cpu_to_le16(0x0011); 2121 desc->wHubCharacteristics = cpu_to_le16(0x0011);
2104 desc->bitmap[0] = ((1 << R8A66597_MAX_ROOT_HUB) - 1) << 1; 2122 desc->bitmap[0] = ((1 << r8a66597->max_root_hub) - 1) << 1;
2105 desc->bitmap[1] = ~0; 2123 desc->bitmap[1] = ~0;
2106} 2124}
2107 2125
@@ -2129,7 +2147,7 @@ static int r8a66597_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
2129 } 2147 }
2130 break; 2148 break;
2131 case ClearPortFeature: 2149 case ClearPortFeature:
2132 if (wIndex > R8A66597_MAX_ROOT_HUB) 2150 if (wIndex > r8a66597->max_root_hub)
2133 goto error; 2151 goto error;
2134 if (wLength != 0) 2152 if (wLength != 0)
2135 goto error; 2153 goto error;
@@ -2162,12 +2180,12 @@ static int r8a66597_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
2162 *buf = 0x00; 2180 *buf = 0x00;
2163 break; 2181 break;
2164 case GetPortStatus: 2182 case GetPortStatus:
2165 if (wIndex > R8A66597_MAX_ROOT_HUB) 2183 if (wIndex > r8a66597->max_root_hub)
2166 goto error; 2184 goto error;
2167 *(__le32 *)buf = cpu_to_le32(rh->port); 2185 *(__le32 *)buf = cpu_to_le32(rh->port);
2168 break; 2186 break;
2169 case SetPortFeature: 2187 case SetPortFeature:
2170 if (wIndex > R8A66597_MAX_ROOT_HUB) 2188 if (wIndex > r8a66597->max_root_hub)
2171 goto error; 2189 goto error;
2172 if (wLength != 0) 2190 if (wLength != 0)
2173 goto error; 2191 goto error;
@@ -2216,7 +2234,7 @@ static int r8a66597_bus_suspend(struct usb_hcd *hcd)
2216 2234
2217 dbg("%s", __func__); 2235 dbg("%s", __func__);
2218 2236
2219 for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++) { 2237 for (port = 0; port < r8a66597->max_root_hub; port++) {
2220 struct r8a66597_root_hub *rh = &r8a66597->root_hub[port]; 2238 struct r8a66597_root_hub *rh = &r8a66597->root_hub[port];
2221 unsigned long dvstctr_reg = get_dvstctr_reg(port); 2239 unsigned long dvstctr_reg = get_dvstctr_reg(port);
2222 2240
@@ -2247,7 +2265,7 @@ static int r8a66597_bus_resume(struct usb_hcd *hcd)
2247 2265
2248 dbg("%s", __func__); 2266 dbg("%s", __func__);
2249 2267
2250 for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++) { 2268 for (port = 0; port < r8a66597->max_root_hub; port++) {
2251 struct r8a66597_root_hub *rh = &r8a66597->root_hub[port]; 2269 struct r8a66597_root_hub *rh = &r8a66597->root_hub[port];
2252 unsigned long dvstctr_reg = get_dvstctr_reg(port); 2270 unsigned long dvstctr_reg = get_dvstctr_reg(port);
2253 2271
@@ -2305,16 +2323,16 @@ static struct hc_driver r8a66597_hc_driver = {
2305}; 2323};
2306 2324
2307#if defined(CONFIG_PM) 2325#if defined(CONFIG_PM)
2308static int r8a66597_suspend(struct platform_device *pdev, pm_message_t state) 2326static int r8a66597_suspend(struct device *dev)
2309{ 2327{
2310 struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev); 2328 struct r8a66597 *r8a66597 = dev_get_drvdata(dev);
2311 int port; 2329 int port;
2312 2330
2313 dbg("%s", __func__); 2331 dbg("%s", __func__);
2314 2332
2315 disable_controller(r8a66597); 2333 disable_controller(r8a66597);
2316 2334
2317 for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++) { 2335 for (port = 0; port < r8a66597->max_root_hub; port++) {
2318 struct r8a66597_root_hub *rh = &r8a66597->root_hub[port]; 2336 struct r8a66597_root_hub *rh = &r8a66597->root_hub[port];
2319 2337
2320 rh->port = 0x00000000; 2338 rh->port = 0x00000000;
@@ -2323,9 +2341,9 @@ static int r8a66597_suspend(struct platform_device *pdev, pm_message_t state)
2323 return 0; 2341 return 0;
2324} 2342}
2325 2343
2326static int r8a66597_resume(struct platform_device *pdev) 2344static int r8a66597_resume(struct device *dev)
2327{ 2345{
2328 struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev); 2346 struct r8a66597 *r8a66597 = dev_get_drvdata(dev);
2329 struct usb_hcd *hcd = r8a66597_to_hcd(r8a66597); 2347 struct usb_hcd *hcd = r8a66597_to_hcd(r8a66597);
2330 2348
2331 dbg("%s", __func__); 2349 dbg("%s", __func__);
@@ -2335,9 +2353,17 @@ static int r8a66597_resume(struct platform_device *pdev)
2335 2353
2336 return 0; 2354 return 0;
2337} 2355}
2356
2357static struct dev_pm_ops r8a66597_dev_pm_ops = {
2358 .suspend = r8a66597_suspend,
2359 .resume = r8a66597_resume,
2360 .poweroff = r8a66597_suspend,
2361 .restore = r8a66597_resume,
2362};
2363
2364#define R8A66597_DEV_PM_OPS (&r8a66597_dev_pm_ops)
2338#else /* if defined(CONFIG_PM) */ 2365#else /* if defined(CONFIG_PM) */
2339#define r8a66597_suspend NULL 2366#define R8A66597_DEV_PM_OPS NULL
2340#define r8a66597_resume NULL
2341#endif 2367#endif
2342 2368
2343static int __init_or_module r8a66597_remove(struct platform_device *pdev) 2369static int __init_or_module r8a66597_remove(struct platform_device *pdev)
@@ -2348,8 +2374,9 @@ static int __init_or_module r8a66597_remove(struct platform_device *pdev)
2348 del_timer_sync(&r8a66597->rh_timer); 2374 del_timer_sync(&r8a66597->rh_timer);
2349 usb_remove_hcd(hcd); 2375 usb_remove_hcd(hcd);
2350 iounmap((void *)r8a66597->reg); 2376 iounmap((void *)r8a66597->reg);
2351#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) && defined(CONFIG_HAVE_CLK) 2377#ifdef CONFIG_HAVE_CLK
2352 clk_put(r8a66597->clk); 2378 if (r8a66597->pdata->on_chip)
2379 clk_put(r8a66597->clk);
2353#endif 2380#endif
2354 usb_put_hcd(hcd); 2381 usb_put_hcd(hcd);
2355 return 0; 2382 return 0;
@@ -2357,7 +2384,7 @@ static int __init_or_module r8a66597_remove(struct platform_device *pdev)
2357 2384
2358static int __devinit r8a66597_probe(struct platform_device *pdev) 2385static int __devinit r8a66597_probe(struct platform_device *pdev)
2359{ 2386{
2360#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) && defined(CONFIG_HAVE_CLK) 2387#ifdef CONFIG_HAVE_CLK
2361 char clk_name[8]; 2388 char clk_name[8];
2362#endif 2389#endif
2363 struct resource *res = NULL, *ires; 2390 struct resource *res = NULL, *ires;
@@ -2419,15 +2446,20 @@ static int __devinit r8a66597_probe(struct platform_device *pdev)
2419 r8a66597->pdata = pdev->dev.platform_data; 2446 r8a66597->pdata = pdev->dev.platform_data;
2420 r8a66597->irq_sense_low = irq_trigger == IRQF_TRIGGER_LOW; 2447 r8a66597->irq_sense_low = irq_trigger == IRQF_TRIGGER_LOW;
2421 2448
2422#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) && defined(CONFIG_HAVE_CLK) 2449 if (r8a66597->pdata->on_chip) {
2423 snprintf(clk_name, sizeof(clk_name), "usb%d", pdev->id); 2450#ifdef CONFIG_HAVE_CLK
2424 r8a66597->clk = clk_get(&pdev->dev, clk_name); 2451 snprintf(clk_name, sizeof(clk_name), "usb%d", pdev->id);
2425 if (IS_ERR(r8a66597->clk)) { 2452 r8a66597->clk = clk_get(&pdev->dev, clk_name);
2426 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name); 2453 if (IS_ERR(r8a66597->clk)) {
2427 ret = PTR_ERR(r8a66597->clk); 2454 dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
2428 goto clean_up2; 2455 clk_name);
2429 } 2456 ret = PTR_ERR(r8a66597->clk);
2457 goto clean_up2;
2458 }
2430#endif 2459#endif
2460 r8a66597->max_root_hub = 1;
2461 } else
2462 r8a66597->max_root_hub = 2;
2431 2463
2432 spin_lock_init(&r8a66597->lock); 2464 spin_lock_init(&r8a66597->lock);
2433 init_timer(&r8a66597->rh_timer); 2465 init_timer(&r8a66597->rh_timer);
@@ -2457,8 +2489,9 @@ static int __devinit r8a66597_probe(struct platform_device *pdev)
2457 return 0; 2489 return 0;
2458 2490
2459clean_up3: 2491clean_up3:
2460#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) && defined(CONFIG_HAVE_CLK) 2492#ifdef CONFIG_HAVE_CLK
2461 clk_put(r8a66597->clk); 2493 if (r8a66597->pdata->on_chip)
2494 clk_put(r8a66597->clk);
2462clean_up2: 2495clean_up2:
2463#endif 2496#endif
2464 usb_put_hcd(hcd); 2497 usb_put_hcd(hcd);
@@ -2473,11 +2506,10 @@ clean_up:
2473static struct platform_driver r8a66597_driver = { 2506static struct platform_driver r8a66597_driver = {
2474 .probe = r8a66597_probe, 2507 .probe = r8a66597_probe,
2475 .remove = r8a66597_remove, 2508 .remove = r8a66597_remove,
2476 .suspend = r8a66597_suspend,
2477 .resume = r8a66597_resume,
2478 .driver = { 2509 .driver = {
2479 .name = (char *) hcd_name, 2510 .name = (char *) hcd_name,
2480 .owner = THIS_MODULE, 2511 .owner = THIS_MODULE,
2512 .pm = R8A66597_DEV_PM_OPS,
2481 }, 2513 },
2482}; 2514};
2483 2515
diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h
index d72680b433f9..228e3fb23854 100644
--- a/drivers/usb/host/r8a66597.h
+++ b/drivers/usb/host/r8a66597.h
@@ -26,390 +26,16 @@
26#ifndef __R8A66597_H__ 26#ifndef __R8A66597_H__
27#define __R8A66597_H__ 27#define __R8A66597_H__
28 28
29#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) && defined(CONFIG_HAVE_CLK) 29#ifdef CONFIG_HAVE_CLK
30#include <linux/clk.h> 30#include <linux/clk.h>
31#endif 31#endif
32 32
33#include <linux/usb/r8a66597.h> 33#include <linux/usb/r8a66597.h>
34 34
35#define SYSCFG0 0x00
36#define SYSCFG1 0x02
37#define SYSSTS0 0x04
38#define SYSSTS1 0x06
39#define DVSTCTR0 0x08
40#define DVSTCTR1 0x0A
41#define TESTMODE 0x0C
42#define PINCFG 0x0E
43#define DMA0CFG 0x10
44#define DMA1CFG 0x12
45#define CFIFO 0x14
46#define D0FIFO 0x18
47#define D1FIFO 0x1C
48#define CFIFOSEL 0x20
49#define CFIFOCTR 0x22
50#define CFIFOSIE 0x24
51#define D0FIFOSEL 0x28
52#define D0FIFOCTR 0x2A
53#define D1FIFOSEL 0x2C
54#define D1FIFOCTR 0x2E
55#define INTENB0 0x30
56#define INTENB1 0x32
57#define INTENB2 0x34
58#define BRDYENB 0x36
59#define NRDYENB 0x38
60#define BEMPENB 0x3A
61#define SOFCFG 0x3C
62#define INTSTS0 0x40
63#define INTSTS1 0x42
64#define INTSTS2 0x44
65#define BRDYSTS 0x46
66#define NRDYSTS 0x48
67#define BEMPSTS 0x4A
68#define FRMNUM 0x4C
69#define UFRMNUM 0x4E
70#define USBADDR 0x50
71#define USBREQ 0x54
72#define USBVAL 0x56
73#define USBINDX 0x58
74#define USBLENG 0x5A
75#define DCPCFG 0x5C
76#define DCPMAXP 0x5E
77#define DCPCTR 0x60
78#define PIPESEL 0x64
79#define PIPECFG 0x68
80#define PIPEBUF 0x6A
81#define PIPEMAXP 0x6C
82#define PIPEPERI 0x6E
83#define PIPE1CTR 0x70
84#define PIPE2CTR 0x72
85#define PIPE3CTR 0x74
86#define PIPE4CTR 0x76
87#define PIPE5CTR 0x78
88#define PIPE6CTR 0x7A
89#define PIPE7CTR 0x7C
90#define PIPE8CTR 0x7E
91#define PIPE9CTR 0x80
92#define PIPE1TRE 0x90
93#define PIPE1TRN 0x92
94#define PIPE2TRE 0x94
95#define PIPE2TRN 0x96
96#define PIPE3TRE 0x98
97#define PIPE3TRN 0x9A
98#define PIPE4TRE 0x9C
99#define PIPE4TRN 0x9E
100#define PIPE5TRE 0xA0
101#define PIPE5TRN 0xA2
102#define DEVADD0 0xD0
103#define DEVADD1 0xD2
104#define DEVADD2 0xD4
105#define DEVADD3 0xD6
106#define DEVADD4 0xD8
107#define DEVADD5 0xDA
108#define DEVADD6 0xDC
109#define DEVADD7 0xDE
110#define DEVADD8 0xE0
111#define DEVADD9 0xE2
112#define DEVADDA 0xE4
113
114/* System Configuration Control Register */
115#define XTAL 0xC000 /* b15-14: Crystal selection */
116#define XTAL48 0x8000 /* 48MHz */
117#define XTAL24 0x4000 /* 24MHz */
118#define XTAL12 0x0000 /* 12MHz */
119#define XCKE 0x2000 /* b13: External clock enable */
120#define PLLC 0x0800 /* b11: PLL control */
121#define SCKE 0x0400 /* b10: USB clock enable */
122#define PCSDIS 0x0200 /* b9: not CS wakeup */
123#define LPSME 0x0100 /* b8: Low power sleep mode */
124#define HSE 0x0080 /* b7: Hi-speed enable */
125#define DCFM 0x0040 /* b6: Controller function select */
126#define DRPD 0x0020 /* b5: D+/- pull down control */
127#define DPRPU 0x0010 /* b4: D+ pull up control */
128#define USBE 0x0001 /* b0: USB module operation enable */
129
130/* System Configuration Status Register */
131#define OVCBIT 0x8000 /* b15-14: Over-current bit */
132#define OVCMON 0xC000 /* b15-14: Over-current monitor */
133#define SOFEA 0x0020 /* b5: SOF monitor */
134#define IDMON 0x0004 /* b3: ID-pin monitor */
135#define LNST 0x0003 /* b1-0: D+, D- line status */
136#define SE1 0x0003 /* SE1 */
137#define FS_KSTS 0x0002 /* Full-Speed K State */
138#define FS_JSTS 0x0001 /* Full-Speed J State */
139#define LS_JSTS 0x0002 /* Low-Speed J State */
140#define LS_KSTS 0x0001 /* Low-Speed K State */
141#define SE0 0x0000 /* SE0 */
142
143/* Device State Control Register */
144#define EXTLP0 0x0400 /* b10: External port */
145#define VBOUT 0x0200 /* b9: VBUS output */
146#define WKUP 0x0100 /* b8: Remote wakeup */
147#define RWUPE 0x0080 /* b7: Remote wakeup sense */
148#define USBRST 0x0040 /* b6: USB reset enable */
149#define RESUME 0x0020 /* b5: Resume enable */
150#define UACT 0x0010 /* b4: USB bus enable */
151#define RHST 0x0007 /* b1-0: Reset handshake status */
152#define HSPROC 0x0004 /* HS handshake is processing */
153#define HSMODE 0x0003 /* Hi-Speed mode */
154#define FSMODE 0x0002 /* Full-Speed mode */
155#define LSMODE 0x0001 /* Low-Speed mode */
156#define UNDECID 0x0000 /* Undecided */
157
158/* Test Mode Register */
159#define UTST 0x000F /* b3-0: Test select */
160#define H_TST_PACKET 0x000C /* HOST TEST Packet */
161#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
162#define H_TST_K 0x000A /* HOST TEST K */
163#define H_TST_J 0x0009 /* HOST TEST J */
164#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
165#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
166#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
167#define P_TST_K 0x0002 /* PERI TEST K */
168#define P_TST_J 0x0001 /* PERI TEST J */
169#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
170
171/* Data Pin Configuration Register */
172#define LDRV 0x8000 /* b15: Drive Current Adjust */
173#define VIF1 0x0000 /* VIF = 1.8V */
174#define VIF3 0x8000 /* VIF = 3.3V */
175#define INTA 0x0001 /* b1: USB INT-pin active */
176
177/* DMAx Pin Configuration Register */
178#define DREQA 0x4000 /* b14: Dreq active select */
179#define BURST 0x2000 /* b13: Burst mode */
180#define DACKA 0x0400 /* b10: Dack active select */
181#define DFORM 0x0380 /* b9-7: DMA mode select */
182#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
183#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
184#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
185#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
186#define DENDA 0x0040 /* b6: Dend active select */
187#define PKTM 0x0020 /* b5: Packet mode */
188#define DENDE 0x0010 /* b4: Dend enable */
189#define OBUS 0x0004 /* b2: OUTbus mode */
190
191/* CFIFO/DxFIFO Port Select Register */
192#define RCNT 0x8000 /* b15: Read count mode */
193#define REW 0x4000 /* b14: Buffer rewind */
194#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
195#define DREQE 0x1000 /* b12: DREQ output enable */
196#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
197#define MBW 0x0800
198#else
199#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
200#endif
201#define MBW_8 0x0000 /* 8bit */
202#define MBW_16 0x0400 /* 16bit */
203#define BIGEND 0x0100 /* b8: Big endian mode */
204#define BYTE_LITTLE 0x0000 /* little dendian */
205#define BYTE_BIG 0x0100 /* big endifan */
206#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
207#define CURPIPE 0x000F /* b2-0: PIPE select */
208
209/* CFIFO/DxFIFO Port Control Register */
210#define BVAL 0x8000 /* b15: Buffer valid flag */
211#define BCLR 0x4000 /* b14: Buffer clear */
212#define FRDY 0x2000 /* b13: FIFO ready */
213#define DTLN 0x0FFF /* b11-0: FIFO received data length */
214
215/* Interrupt Enable Register 0 */
216#define VBSE 0x8000 /* b15: VBUS interrupt */
217#define RSME 0x4000 /* b14: Resume interrupt */
218#define SOFE 0x2000 /* b13: Frame update interrupt */
219#define DVSE 0x1000 /* b12: Device state transition interrupt */
220#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
221#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
222#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
223#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
224
225/* Interrupt Enable Register 1 */
226#define OVRCRE 0x8000 /* b15: Over-current interrupt */
227#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
228#define DTCHE 0x1000 /* b12: Detach sense interrupt */
229#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
230#define EOFERRE 0x0040 /* b6: EOF error interrupt */
231#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
232#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
233
234/* BRDY Interrupt Enable/Status Register */
235#define BRDY9 0x0200 /* b9: PIPE9 */
236#define BRDY8 0x0100 /* b8: PIPE8 */
237#define BRDY7 0x0080 /* b7: PIPE7 */
238#define BRDY6 0x0040 /* b6: PIPE6 */
239#define BRDY5 0x0020 /* b5: PIPE5 */
240#define BRDY4 0x0010 /* b4: PIPE4 */
241#define BRDY3 0x0008 /* b3: PIPE3 */
242#define BRDY2 0x0004 /* b2: PIPE2 */
243#define BRDY1 0x0002 /* b1: PIPE1 */
244#define BRDY0 0x0001 /* b1: PIPE0 */
245
246/* NRDY Interrupt Enable/Status Register */
247#define NRDY9 0x0200 /* b9: PIPE9 */
248#define NRDY8 0x0100 /* b8: PIPE8 */
249#define NRDY7 0x0080 /* b7: PIPE7 */
250#define NRDY6 0x0040 /* b6: PIPE6 */
251#define NRDY5 0x0020 /* b5: PIPE5 */
252#define NRDY4 0x0010 /* b4: PIPE4 */
253#define NRDY3 0x0008 /* b3: PIPE3 */
254#define NRDY2 0x0004 /* b2: PIPE2 */
255#define NRDY1 0x0002 /* b1: PIPE1 */
256#define NRDY0 0x0001 /* b1: PIPE0 */
257
258/* BEMP Interrupt Enable/Status Register */
259#define BEMP9 0x0200 /* b9: PIPE9 */
260#define BEMP8 0x0100 /* b8: PIPE8 */
261#define BEMP7 0x0080 /* b7: PIPE7 */
262#define BEMP6 0x0040 /* b6: PIPE6 */
263#define BEMP5 0x0020 /* b5: PIPE5 */
264#define BEMP4 0x0010 /* b4: PIPE4 */
265#define BEMP3 0x0008 /* b3: PIPE3 */
266#define BEMP2 0x0004 /* b2: PIPE2 */
267#define BEMP1 0x0002 /* b1: PIPE1 */
268#define BEMP0 0x0001 /* b0: PIPE0 */
269
270/* SOF Pin Configuration Register */
271#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
272#define BRDYM 0x0040 /* b6: BRDY clear timing */
273#define INTL 0x0020 /* b5: Interrupt sense select */
274#define EDGESTS 0x0010 /* b4: */
275#define SOFMODE 0x000C /* b3-2: SOF pin select */
276#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
277#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
278#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
279
280/* Interrupt Status Register 0 */
281#define VBINT 0x8000 /* b15: VBUS interrupt */
282#define RESM 0x4000 /* b14: Resume interrupt */
283#define SOFR 0x2000 /* b13: SOF frame update interrupt */
284#define DVST 0x1000 /* b12: Device state transition interrupt */
285#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
286#define BEMP 0x0400 /* b10: Buffer empty interrupt */
287#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
288#define BRDY 0x0100 /* b8: Buffer ready interrupt */
289#define VBSTS 0x0080 /* b7: VBUS input port */
290#define DVSQ 0x0070 /* b6-4: Device state */
291#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
292#define DS_SPD_ADDR 0x0060 /* Suspend Address */
293#define DS_SPD_DFLT 0x0050 /* Suspend Default */
294#define DS_SPD_POWR 0x0040 /* Suspend Powered */
295#define DS_SUSP 0x0040 /* Suspend */
296#define DS_CNFG 0x0030 /* Configured */
297#define DS_ADDS 0x0020 /* Address */
298#define DS_DFLT 0x0010 /* Default */
299#define DS_POWR 0x0000 /* Powered */
300#define DVSQS 0x0030 /* b5-4: Device state */
301#define VALID 0x0008 /* b3: Setup packet detected flag */
302#define CTSQ 0x0007 /* b2-0: Control transfer stage */
303#define CS_SQER 0x0006 /* Sequence error */
304#define CS_WRND 0x0005 /* Control write nodata status stage */
305#define CS_WRSS 0x0004 /* Control write status stage */
306#define CS_WRDS 0x0003 /* Control write data stage */
307#define CS_RDSS 0x0002 /* Control read status stage */
308#define CS_RDDS 0x0001 /* Control read data stage */
309#define CS_IDST 0x0000 /* Idle or setup stage */
310
311/* Interrupt Status Register 1 */
312#define OVRCR 0x8000 /* b15: Over-current interrupt */
313#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
314#define DTCH 0x1000 /* b12: Detach sense interrupt */
315#define ATTCH 0x0800 /* b11: Attach sense interrupt */
316#define EOFERR 0x0040 /* b6: EOF-error interrupt */
317#define SIGN 0x0020 /* b5: Setup ignore interrupt */
318#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
319
320/* Frame Number Register */
321#define OVRN 0x8000 /* b15: Overrun error */
322#define CRCE 0x4000 /* b14: Received data error */
323#define FRNM 0x07FF /* b10-0: Frame number */
324
325/* Micro Frame Number Register */
326#define UFRNM 0x0007 /* b2-0: Micro frame number */
327
328/* Default Control Pipe Maxpacket Size Register */
329/* Pipe Maxpacket Size Register */
330#define DEVSEL 0xF000 /* b15-14: Device address select */
331#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
332
333/* Default Control Pipe Control Register */
334#define BSTS 0x8000 /* b15: Buffer status */
335#define SUREQ 0x4000 /* b14: Send USB request */
336#define CSCLR 0x2000 /* b13: complete-split status clear */
337#define CSSTS 0x1000 /* b12: complete-split status */
338#define SUREQCLR 0x0800 /* b11: stop setup request */
339#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
340#define SQSET 0x0080 /* b7: Sequence toggle bit set */
341#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
342#define PBUSY 0x0020 /* b5: pipe busy */
343#define PINGE 0x0010 /* b4: ping enable */
344#define CCPL 0x0004 /* b2: Enable control transfer complete */
345#define PID 0x0003 /* b1-0: Response PID */
346#define PID_STALL11 0x0003 /* STALL */
347#define PID_STALL 0x0002 /* STALL */
348#define PID_BUF 0x0001 /* BUF */
349#define PID_NAK 0x0000 /* NAK */
350
351/* Pipe Window Select Register */
352#define PIPENM 0x0007 /* b2-0: Pipe select */
353
354/* Pipe Configuration Register */
355#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
356#define R8A66597_ISO 0xC000 /* Isochronous */
357#define R8A66597_INT 0x8000 /* Interrupt */
358#define R8A66597_BULK 0x4000 /* Bulk */
359#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
360#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
361#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
362#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
363#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
364#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
365
366/* Pipe Buffer Configuration Register */
367#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
368#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
369#define PIPE0BUF 256
370#define PIPExBUF 64
371
372/* Pipe Maxpacket Size Register */
373#define MXPS 0x07FF /* b10-0: Maxpacket size */
374
375/* Pipe Cycle Configuration Register */
376#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
377#define IITV 0x0007 /* b2-0: Isochronous interval */
378
379/* Pipex Control Register */
380#define BSTS 0x8000 /* b15: Buffer status */
381#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
382#define CSCLR 0x2000 /* b13: complete-split status clear */
383#define CSSTS 0x1000 /* b12: complete-split status */
384#define ATREPM 0x0400 /* b10: Auto repeat mode */
385#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
386#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
387#define SQSET 0x0080 /* b7: Sequence toggle bit set */
388#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
389#define PBUSY 0x0020 /* b5: pipe busy */
390#define PID 0x0003 /* b1-0: Response PID */
391
392/* PIPExTRE */
393#define TRENB 0x0200 /* b9: Transaction counter enable */
394#define TRCLR 0x0100 /* b8: Transaction counter clear */
395
396/* PIPExTRN */
397#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
398
399/* DEVADDx */
400#define UPPHUB 0x7800
401#define HUBPORT 0x0700
402#define USBSPD 0x00C0
403#define RTPORT 0x0001
404
405#define R8A66597_MAX_NUM_PIPE 10 35#define R8A66597_MAX_NUM_PIPE 10
406#define R8A66597_BUF_BSIZE 8 36#define R8A66597_BUF_BSIZE 8
407#define R8A66597_MAX_DEVICE 10 37#define R8A66597_MAX_DEVICE 10
408#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
409#define R8A66597_MAX_ROOT_HUB 1
410#else
411#define R8A66597_MAX_ROOT_HUB 2 38#define R8A66597_MAX_ROOT_HUB 2
412#endif
413#define R8A66597_MAX_SAMPLING 5 39#define R8A66597_MAX_SAMPLING 5
414#define R8A66597_RH_POLL_TIME 10 40#define R8A66597_RH_POLL_TIME 10
415#define R8A66597_MAX_DMA_CHANNEL 2 41#define R8A66597_MAX_DMA_CHANNEL 2
@@ -487,7 +113,7 @@ struct r8a66597_root_hub {
487struct r8a66597 { 113struct r8a66597 {
488 spinlock_t lock; 114 spinlock_t lock;
489 unsigned long reg; 115 unsigned long reg;
490#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) && defined(CONFIG_HAVE_CLK) 116#ifdef CONFIG_HAVE_CLK
491 struct clk *clk; 117 struct clk *clk;
492#endif 118#endif
493 struct r8a66597_platdata *pdata; 119 struct r8a66597_platdata *pdata;
@@ -504,6 +130,7 @@ struct r8a66597 {
504 unsigned short interval_map; 130 unsigned short interval_map;
505 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE]; 131 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
506 unsigned char dma_map; 132 unsigned char dma_map;
133 unsigned int max_root_hub;
507 134
508 struct list_head child_device; 135 struct list_head child_device;
509 unsigned long child_connect_map[4]; 136 unsigned long child_connect_map[4];
@@ -550,21 +177,22 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
550 unsigned long offset, u16 *buf, 177 unsigned long offset, u16 *buf,
551 int len) 178 int len)
552{ 179{
553#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
554 unsigned long fifoaddr = r8a66597->reg + offset; 180 unsigned long fifoaddr = r8a66597->reg + offset;
555 unsigned long count; 181 unsigned long count;
556 182
557 count = len / 4; 183 if (r8a66597->pdata->on_chip) {
558 insl(fifoaddr, buf, count); 184 count = len / 4;
185 insl(fifoaddr, buf, count);
559 186
560 if (len & 0x00000003) { 187 if (len & 0x00000003) {
561 unsigned long tmp = inl(fifoaddr); 188 unsigned long tmp = inl(fifoaddr);
562 memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03); 189 memcpy((unsigned char *)buf + count * 4, &tmp,
190 len & 0x03);
191 }
192 } else {
193 len = (len + 1) / 2;
194 insw(fifoaddr, buf, len);
563 } 195 }
564#else
565 len = (len + 1) / 2;
566 insw(r8a66597->reg + offset, buf, len);
567#endif
568} 196}
569 197
570static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, 198static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
@@ -578,33 +206,33 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
578 int len) 206 int len)
579{ 207{
580 unsigned long fifoaddr = r8a66597->reg + offset; 208 unsigned long fifoaddr = r8a66597->reg + offset;
581#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
582 unsigned long count; 209 unsigned long count;
583 unsigned char *pb; 210 unsigned char *pb;
584 int i; 211 int i;
585 212
586 count = len / 4; 213 if (r8a66597->pdata->on_chip) {
587 outsl(fifoaddr, buf, count); 214 count = len / 4;
215 outsl(fifoaddr, buf, count);
216
217 if (len & 0x00000003) {
218 pb = (unsigned char *)buf + count * 4;
219 for (i = 0; i < (len & 0x00000003); i++) {
220 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
221 outb(pb[i], fifoaddr + i);
222 else
223 outb(pb[i], fifoaddr + 3 - i);
224 }
225 }
226 } else {
227 int odd = len & 0x0001;
588 228
589 if (len & 0x00000003) { 229 len = len / 2;
590 pb = (unsigned char *)buf + count * 4; 230 outsw(fifoaddr, buf, len);
591 for (i = 0; i < (len & 0x00000003); i++) { 231 if (unlikely(odd)) {
592 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND) 232 buf = &buf[len];
593 outb(pb[i], fifoaddr + i); 233 outb((unsigned char)*buf, fifoaddr);
594 else
595 outb(pb[i], fifoaddr + 3 - i);
596 } 234 }
597 } 235 }
598#else
599 int odd = len & 0x0001;
600
601 len = len / 2;
602 outsw(fifoaddr, buf, len);
603 if (unlikely(odd)) {
604 buf = &buf[len];
605 outb((unsigned char)*buf, fifoaddr);
606 }
607#endif
608} 236}
609 237
610static inline void r8a66597_mdfy(struct r8a66597 *r8a66597, 238static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index cef3e1d9b92e..11af4cb8924e 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1869,7 +1869,7 @@ config FB_W100
1869 1869
1870config FB_SH_MOBILE_LCDC 1870config FB_SH_MOBILE_LCDC
1871 tristate "SuperH Mobile LCDC framebuffer support" 1871 tristate "SuperH Mobile LCDC framebuffer support"
1872 depends on FB && SUPERH 1872 depends on FB && SUPERH && HAVE_CLK
1873 select FB_SYS_FILLRECT 1873 select FB_SYS_FILLRECT
1874 select FB_SYS_COPYAREA 1874 select FB_SYS_COPYAREA
1875 select FB_SYS_IMAGEBLIT 1875 select FB_SYS_IMAGEBLIT
diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c
index 07f22b625632..3ad5157f9899 100644
--- a/drivers/video/sh_mobile_lcdcfb.c
+++ b/drivers/video/sh_mobile_lcdcfb.c
@@ -14,6 +14,7 @@
14#include <linux/mm.h> 14#include <linux/mm.h>
15#include <linux/fb.h> 15#include <linux/fb.h>
16#include <linux/clk.h> 16#include <linux/clk.h>
17#include <linux/pm_runtime.h>
17#include <linux/platform_device.h> 18#include <linux/platform_device.h>
18#include <linux/dma-mapping.h> 19#include <linux/dma-mapping.h>
19#include <linux/interrupt.h> 20#include <linux/interrupt.h>
@@ -22,35 +23,8 @@
22#include <asm/atomic.h> 23#include <asm/atomic.h>
23 24
24#define PALETTE_NR 16 25#define PALETTE_NR 16
25 26#define SIDE_B_OFFSET 0x1000
26struct sh_mobile_lcdc_priv; 27#define MIRROR_OFFSET 0x2000
27struct sh_mobile_lcdc_chan {
28 struct sh_mobile_lcdc_priv *lcdc;
29 unsigned long *reg_offs;
30 unsigned long ldmt1r_value;
31 unsigned long enabled; /* ME and SE in LDCNT2R */
32 struct sh_mobile_lcdc_chan_cfg cfg;
33 u32 pseudo_palette[PALETTE_NR];
34 struct fb_info *info;
35 dma_addr_t dma_handle;
36 struct fb_deferred_io defio;
37 struct scatterlist *sglist;
38 unsigned long frame_end;
39 wait_queue_head_t frame_end_wait;
40};
41
42struct sh_mobile_lcdc_priv {
43 void __iomem *base;
44 int irq;
45#ifdef CONFIG_HAVE_CLK
46 atomic_t clk_usecnt;
47 struct clk *dot_clk;
48 struct clk *clk;
49#endif
50 unsigned long lddckr;
51 struct sh_mobile_lcdc_chan ch[2];
52 int started;
53};
54 28
55/* shared registers */ 29/* shared registers */
56#define _LDDCKR 0x410 30#define _LDDCKR 0x410
@@ -59,17 +33,30 @@ struct sh_mobile_lcdc_priv {
59#define _LDSR 0x46c 33#define _LDSR 0x46c
60#define _LDCNT1R 0x470 34#define _LDCNT1R 0x470
61#define _LDCNT2R 0x474 35#define _LDCNT2R 0x474
36#define _LDRCNTR 0x478
62#define _LDDDSR 0x47c 37#define _LDDDSR 0x47c
63#define _LDDWD0R 0x800 38#define _LDDWD0R 0x800
64#define _LDDRDR 0x840 39#define _LDDRDR 0x840
65#define _LDDWAR 0x900 40#define _LDDWAR 0x900
66#define _LDDRAR 0x904 41#define _LDDRAR 0x904
67 42
43/* shared registers and their order for context save/restore */
44static int lcdc_shared_regs[] = {
45 _LDDCKR,
46 _LDDCKSTPR,
47 _LDINTR,
48 _LDDDSR,
49 _LDCNT1R,
50 _LDCNT2R,
51};
52#define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
53
68/* per-channel registers */ 54/* per-channel registers */
69enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R, 55enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
70 LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR }; 56 LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR,
57 NR_CH_REGS };
71 58
72static unsigned long lcdc_offs_mainlcd[] = { 59static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
73 [LDDCKPAT1R] = 0x400, 60 [LDDCKPAT1R] = 0x400,
74 [LDDCKPAT2R] = 0x404, 61 [LDDCKPAT2R] = 0x404,
75 [LDMT1R] = 0x418, 62 [LDMT1R] = 0x418,
@@ -87,7 +74,7 @@ static unsigned long lcdc_offs_mainlcd[] = {
87 [LDPMR] = 0x460, 74 [LDPMR] = 0x460,
88}; 75};
89 76
90static unsigned long lcdc_offs_sublcd[] = { 77static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
91 [LDDCKPAT1R] = 0x408, 78 [LDDCKPAT1R] = 0x408,
92 [LDDCKPAT2R] = 0x40c, 79 [LDDCKPAT2R] = 0x40c,
93 [LDMT1R] = 0x600, 80 [LDMT1R] = 0x600,
@@ -110,12 +97,80 @@ static unsigned long lcdc_offs_sublcd[] = {
110#define DISPLAY_BEU 0x00000008 97#define DISPLAY_BEU 0x00000008
111#define LCDC_ENABLE 0x00000001 98#define LCDC_ENABLE 0x00000001
112#define LDINTR_FE 0x00000400 99#define LDINTR_FE 0x00000400
100#define LDINTR_VSE 0x00000200
101#define LDINTR_VEE 0x00000100
113#define LDINTR_FS 0x00000004 102#define LDINTR_FS 0x00000004
103#define LDINTR_VSS 0x00000002
104#define LDINTR_VES 0x00000001
105#define LDRCNTR_SRS 0x00020000
106#define LDRCNTR_SRC 0x00010000
107#define LDRCNTR_MRS 0x00000002
108#define LDRCNTR_MRC 0x00000001
109
110struct sh_mobile_lcdc_priv;
111struct sh_mobile_lcdc_chan {
112 struct sh_mobile_lcdc_priv *lcdc;
113 unsigned long *reg_offs;
114 unsigned long ldmt1r_value;
115 unsigned long enabled; /* ME and SE in LDCNT2R */
116 struct sh_mobile_lcdc_chan_cfg cfg;
117 u32 pseudo_palette[PALETTE_NR];
118 unsigned long saved_ch_regs[NR_CH_REGS];
119 struct fb_info *info;
120 dma_addr_t dma_handle;
121 struct fb_deferred_io defio;
122 struct scatterlist *sglist;
123 unsigned long frame_end;
124 unsigned long pan_offset;
125 unsigned long new_pan_offset;
126 wait_queue_head_t frame_end_wait;
127};
128
129struct sh_mobile_lcdc_priv {
130 void __iomem *base;
131 int irq;
132 atomic_t hw_usecnt;
133 struct device *dev;
134 struct clk *dot_clk;
135 unsigned long lddckr;
136 struct sh_mobile_lcdc_chan ch[2];
137 unsigned long saved_shared_regs[NR_SHARED_REGS];
138 int started;
139};
140
141static bool banked(int reg_nr)
142{
143 switch (reg_nr) {
144 case LDMT1R:
145 case LDMT2R:
146 case LDMT3R:
147 case LDDFR:
148 case LDSM1R:
149 case LDSA1R:
150 case LDMLSR:
151 case LDHCNR:
152 case LDHSYNR:
153 case LDVLNR:
154 case LDVSYNR:
155 return true;
156 }
157 return false;
158}
114 159
115static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan, 160static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
116 int reg_nr, unsigned long data) 161 int reg_nr, unsigned long data)
117{ 162{
118 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]); 163 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
164 if (banked(reg_nr))
165 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
166 SIDE_B_OFFSET);
167}
168
169static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
170 int reg_nr, unsigned long data)
171{
172 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
173 MIRROR_OFFSET);
119} 174}
120 175
121static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan, 176static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
@@ -156,6 +211,7 @@ static void lcdc_sys_write_index(void *handle, unsigned long data)
156 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000); 211 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
157 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0); 212 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
158 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0)); 213 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
214 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
159} 215}
160 216
161static void lcdc_sys_write_data(void *handle, unsigned long data) 217static void lcdc_sys_write_data(void *handle, unsigned long data)
@@ -165,6 +221,7 @@ static void lcdc_sys_write_data(void *handle, unsigned long data)
165 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000); 221 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
166 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0); 222 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
167 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0)); 223 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
224 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
168} 225}
169 226
170static unsigned long lcdc_sys_read_data(void *handle) 227static unsigned long lcdc_sys_read_data(void *handle)
@@ -175,8 +232,9 @@ static unsigned long lcdc_sys_read_data(void *handle)
175 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0); 232 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
176 lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0)); 233 lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
177 udelay(1); 234 udelay(1);
235 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
178 236
179 return lcdc_read(ch->lcdc, _LDDRDR) & 0xffff; 237 return lcdc_read(ch->lcdc, _LDDRDR) & 0x3ffff;
180} 238}
181 239
182struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = { 240struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
@@ -185,11 +243,10 @@ struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
185 lcdc_sys_read_data, 243 lcdc_sys_read_data,
186}; 244};
187 245
188#ifdef CONFIG_HAVE_CLK
189static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv) 246static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
190{ 247{
191 if (atomic_inc_and_test(&priv->clk_usecnt)) { 248 if (atomic_inc_and_test(&priv->hw_usecnt)) {
192 clk_enable(priv->clk); 249 pm_runtime_get_sync(priv->dev);
193 if (priv->dot_clk) 250 if (priv->dot_clk)
194 clk_enable(priv->dot_clk); 251 clk_enable(priv->dot_clk);
195 } 252 }
@@ -197,16 +254,12 @@ static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
197 254
198static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv) 255static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
199{ 256{
200 if (atomic_sub_return(1, &priv->clk_usecnt) == -1) { 257 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
201 if (priv->dot_clk) 258 if (priv->dot_clk)
202 clk_disable(priv->dot_clk); 259 clk_disable(priv->dot_clk);
203 clk_disable(priv->clk); 260 pm_runtime_put(priv->dev);
204 } 261 }
205} 262}
206#else
207static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv) {}
208static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv) {}
209#endif
210 263
211static int sh_mobile_lcdc_sginit(struct fb_info *info, 264static int sh_mobile_lcdc_sginit(struct fb_info *info,
212 struct list_head *pagelist) 265 struct list_head *pagelist)
@@ -255,30 +308,52 @@ static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
255 struct sh_mobile_lcdc_priv *priv = data; 308 struct sh_mobile_lcdc_priv *priv = data;
256 struct sh_mobile_lcdc_chan *ch; 309 struct sh_mobile_lcdc_chan *ch;
257 unsigned long tmp; 310 unsigned long tmp;
311 unsigned long ldintr;
258 int is_sub; 312 int is_sub;
259 int k; 313 int k;
260 314
261 /* acknowledge interrupt */ 315 /* acknowledge interrupt */
262 tmp = lcdc_read(priv, _LDINTR); 316 ldintr = tmp = lcdc_read(priv, _LDINTR);
263 tmp &= 0xffffff00; /* mask in high 24 bits */ 317 /*
264 tmp |= 0x000000ff ^ LDINTR_FS; /* status in low 8 */ 318 * disable further VSYNC End IRQs, preserve all other enabled IRQs,
319 * write 0 to bits 0-6 to ack all triggered IRQs.
320 */
321 tmp &= 0xffffff00 & ~LDINTR_VEE;
265 lcdc_write(priv, _LDINTR, tmp); 322 lcdc_write(priv, _LDINTR, tmp);
266 323
267 /* figure out if this interrupt is for main or sub lcd */ 324 /* figure out if this interrupt is for main or sub lcd */
268 is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0; 325 is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0;
269 326
270 /* wake up channel and disable clocks*/ 327 /* wake up channel and disable clocks */
271 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { 328 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
272 ch = &priv->ch[k]; 329 ch = &priv->ch[k];
273 330
274 if (!ch->enabled) 331 if (!ch->enabled)
275 continue; 332 continue;
276 333
277 if (is_sub == lcdc_chan_is_sublcd(ch)) { 334 /* Frame Start */
278 ch->frame_end = 1; 335 if (ldintr & LDINTR_FS) {
279 wake_up(&ch->frame_end_wait); 336 if (is_sub == lcdc_chan_is_sublcd(ch)) {
337 ch->frame_end = 1;
338 wake_up(&ch->frame_end_wait);
280 339
281 sh_mobile_lcdc_clk_off(priv); 340 sh_mobile_lcdc_clk_off(priv);
341 }
342 }
343
344 /* VSYNC End */
345 if (ldintr & LDINTR_VES) {
346 unsigned long ldrcntr = lcdc_read(priv, _LDRCNTR);
347 /* Set the source address for the next refresh */
348 lcdc_write_chan_mirror(ch, LDSA1R, ch->dma_handle +
349 ch->new_pan_offset);
350 if (lcdc_chan_is_sublcd(ch))
351 lcdc_write(ch->lcdc, _LDRCNTR,
352 ldrcntr ^ LDRCNTR_SRS);
353 else
354 lcdc_write(ch->lcdc, _LDRCNTR,
355 ldrcntr ^ LDRCNTR_MRS);
356 ch->pan_offset = ch->new_pan_offset;
282 } 357 }
283 } 358 }
284 359
@@ -520,7 +595,6 @@ static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
520 board_cfg = &ch->cfg.board_cfg; 595 board_cfg = &ch->cfg.board_cfg;
521 if (board_cfg->display_off) 596 if (board_cfg->display_off)
522 board_cfg->display_off(board_cfg->board_data); 597 board_cfg->display_off(board_cfg->board_data);
523
524 } 598 }
525 599
526 /* stop the lcdc */ 600 /* stop the lcdc */
@@ -579,9 +653,6 @@ static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
579 int clock_source, 653 int clock_source,
580 struct sh_mobile_lcdc_priv *priv) 654 struct sh_mobile_lcdc_priv *priv)
581{ 655{
582#ifdef CONFIG_HAVE_CLK
583 char clk_name[8];
584#endif
585 char *str; 656 char *str;
586 int icksel; 657 int icksel;
587 658
@@ -595,25 +666,21 @@ static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
595 666
596 priv->lddckr = icksel << 16; 667 priv->lddckr = icksel << 16;
597 668
598#ifdef CONFIG_HAVE_CLK
599 atomic_set(&priv->clk_usecnt, -1);
600 snprintf(clk_name, sizeof(clk_name), "lcdc%d", pdev->id);
601 priv->clk = clk_get(&pdev->dev, clk_name);
602 if (IS_ERR(priv->clk)) {
603 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
604 return PTR_ERR(priv->clk);
605 }
606
607 if (str) { 669 if (str) {
608 priv->dot_clk = clk_get(&pdev->dev, str); 670 priv->dot_clk = clk_get(&pdev->dev, str);
609 if (IS_ERR(priv->dot_clk)) { 671 if (IS_ERR(priv->dot_clk)) {
610 dev_err(&pdev->dev, "cannot get dot clock %s\n", str); 672 dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
611 clk_put(priv->clk);
612 return PTR_ERR(priv->dot_clk); 673 return PTR_ERR(priv->dot_clk);
613 } 674 }
614 } 675 }
615#endif 676 atomic_set(&priv->hw_usecnt, -1);
616 677
678 /* Runtime PM support involves two step for this driver:
679 * 1) Enable Runtime PM
680 * 2) Force Runtime PM Resume since hardware is accessed from probe()
681 */
682 pm_runtime_enable(priv->dev);
683 pm_runtime_resume(priv->dev);
617 return 0; 684 return 0;
618} 685}
619 686
@@ -646,6 +713,9 @@ static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
646 .type = FB_TYPE_PACKED_PIXELS, 713 .type = FB_TYPE_PACKED_PIXELS,
647 .visual = FB_VISUAL_TRUECOLOR, 714 .visual = FB_VISUAL_TRUECOLOR,
648 .accel = FB_ACCEL_NONE, 715 .accel = FB_ACCEL_NONE,
716 .xpanstep = 0,
717 .ypanstep = 1,
718 .ywrapstep = 0,
649}; 719};
650 720
651static void sh_mobile_lcdc_fillrect(struct fb_info *info, 721static void sh_mobile_lcdc_fillrect(struct fb_info *info,
@@ -669,13 +739,38 @@ static void sh_mobile_lcdc_imageblit(struct fb_info *info,
669 sh_mobile_lcdc_deferred_io_touch(info); 739 sh_mobile_lcdc_deferred_io_touch(info);
670} 740}
671 741
742static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
743 struct fb_info *info)
744{
745 struct sh_mobile_lcdc_chan *ch = info->par;
746
747 if (info->var.xoffset == var->xoffset &&
748 info->var.yoffset == var->yoffset)
749 return 0; /* No change, do nothing */
750
751 ch->new_pan_offset = (var->yoffset * info->fix.line_length) +
752 (var->xoffset * (info->var.bits_per_pixel / 8));
753
754 if (ch->new_pan_offset != ch->pan_offset) {
755 unsigned long ldintr;
756 ldintr = lcdc_read(ch->lcdc, _LDINTR);
757 ldintr |= LDINTR_VEE;
758 lcdc_write(ch->lcdc, _LDINTR, ldintr);
759 sh_mobile_lcdc_deferred_io_touch(info);
760 }
761
762 return 0;
763}
764
672static struct fb_ops sh_mobile_lcdc_ops = { 765static struct fb_ops sh_mobile_lcdc_ops = {
766 .owner = THIS_MODULE,
673 .fb_setcolreg = sh_mobile_lcdc_setcolreg, 767 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
674 .fb_read = fb_sys_read, 768 .fb_read = fb_sys_read,
675 .fb_write = fb_sys_write, 769 .fb_write = fb_sys_write,
676 .fb_fillrect = sh_mobile_lcdc_fillrect, 770 .fb_fillrect = sh_mobile_lcdc_fillrect,
677 .fb_copyarea = sh_mobile_lcdc_copyarea, 771 .fb_copyarea = sh_mobile_lcdc_copyarea,
678 .fb_imageblit = sh_mobile_lcdc_imageblit, 772 .fb_imageblit = sh_mobile_lcdc_imageblit,
773 .fb_pan_display = sh_mobile_fb_pan_display,
679}; 774};
680 775
681static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp) 776static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
@@ -731,9 +826,59 @@ static int sh_mobile_lcdc_resume(struct device *dev)
731 return sh_mobile_lcdc_start(platform_get_drvdata(pdev)); 826 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
732} 827}
733 828
829static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
830{
831 struct platform_device *pdev = to_platform_device(dev);
832 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
833 struct sh_mobile_lcdc_chan *ch;
834 int k, n;
835
836 /* save per-channel registers */
837 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
838 ch = &p->ch[k];
839 if (!ch->enabled)
840 continue;
841 for (n = 0; n < NR_CH_REGS; n++)
842 ch->saved_ch_regs[n] = lcdc_read_chan(ch, n);
843 }
844
845 /* save shared registers */
846 for (n = 0; n < NR_SHARED_REGS; n++)
847 p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]);
848
849 /* turn off LCDC hardware */
850 lcdc_write(p, _LDCNT1R, 0);
851 return 0;
852}
853
854static int sh_mobile_lcdc_runtime_resume(struct device *dev)
855{
856 struct platform_device *pdev = to_platform_device(dev);
857 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
858 struct sh_mobile_lcdc_chan *ch;
859 int k, n;
860
861 /* restore per-channel registers */
862 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
863 ch = &p->ch[k];
864 if (!ch->enabled)
865 continue;
866 for (n = 0; n < NR_CH_REGS; n++)
867 lcdc_write_chan(ch, n, ch->saved_ch_regs[n]);
868 }
869
870 /* restore shared registers */
871 for (n = 0; n < NR_SHARED_REGS; n++)
872 lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]);
873
874 return 0;
875}
876
734static struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = { 877static struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
735 .suspend = sh_mobile_lcdc_suspend, 878 .suspend = sh_mobile_lcdc_suspend,
736 .resume = sh_mobile_lcdc_resume, 879 .resume = sh_mobile_lcdc_resume,
880 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
881 .runtime_resume = sh_mobile_lcdc_runtime_resume,
737}; 882};
738 883
739static int sh_mobile_lcdc_remove(struct platform_device *pdev); 884static int sh_mobile_lcdc_remove(struct platform_device *pdev);
@@ -778,6 +923,7 @@ static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
778 } 923 }
779 924
780 priv->irq = i; 925 priv->irq = i;
926 priv->dev = &pdev->dev;
781 platform_set_drvdata(pdev, priv); 927 platform_set_drvdata(pdev, priv);
782 pdata = pdev->dev.platform_data; 928 pdata = pdev->dev.platform_data;
783 929
@@ -792,6 +938,8 @@ static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
792 goto err1; 938 goto err1;
793 } 939 }
794 init_waitqueue_head(&priv->ch[i].frame_end_wait); 940 init_waitqueue_head(&priv->ch[i].frame_end_wait);
941 priv->ch[j].pan_offset = 0;
942 priv->ch[j].new_pan_offset = 0;
795 943
796 switch (pdata->ch[i].chan) { 944 switch (pdata->ch[i].chan) {
797 case LCDC_CHAN_MAINLCD: 945 case LCDC_CHAN_MAINLCD:
@@ -834,7 +982,9 @@ static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
834 info = priv->ch[i].info; 982 info = priv->ch[i].info;
835 info->fbops = &sh_mobile_lcdc_ops; 983 info->fbops = &sh_mobile_lcdc_ops;
836 info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres; 984 info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres;
837 info->var.yres = info->var.yres_virtual = cfg->lcd_cfg.yres; 985 info->var.yres = cfg->lcd_cfg.yres;
986 /* Default Y virtual resolution is 2x panel size */
987 info->var.yres_virtual = info->var.yres * 2;
838 info->var.width = cfg->lcd_size_cfg.width; 988 info->var.width = cfg->lcd_size_cfg.width;
839 info->var.height = cfg->lcd_size_cfg.height; 989 info->var.height = cfg->lcd_size_cfg.height;
840 info->var.activate = FB_ACTIVATE_NOW; 990 info->var.activate = FB_ACTIVATE_NOW;
@@ -844,7 +994,8 @@ static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
844 994
845 info->fix = sh_mobile_lcdc_fix; 995 info->fix = sh_mobile_lcdc_fix;
846 info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8); 996 info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8);
847 info->fix.smem_len = info->fix.line_length * cfg->lcd_cfg.yres; 997 info->fix.smem_len = info->fix.line_length *
998 info->var.yres_virtual;
848 999
849 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len, 1000 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
850 &priv->ch[i].dma_handle, GFP_KERNEL); 1001 &priv->ch[i].dma_handle, GFP_KERNEL);
@@ -947,11 +1098,10 @@ static int sh_mobile_lcdc_remove(struct platform_device *pdev)
947 framebuffer_release(info); 1098 framebuffer_release(info);
948 } 1099 }
949 1100
950#ifdef CONFIG_HAVE_CLK
951 if (priv->dot_clk) 1101 if (priv->dot_clk)
952 clk_put(priv->dot_clk); 1102 clk_put(priv->dot_clk);
953 clk_put(priv->clk); 1103
954#endif 1104 pm_runtime_disable(priv->dev);
955 1105
956 if (priv->base) 1106 if (priv->base)
957 iounmap(priv->base); 1107 iounmap(priv->base);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-25 06:24:08 -0400