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-rw-r--r--drivers/char/hvc_console.c12
-rw-r--r--drivers/char/hvsi.c4
-rw-r--r--drivers/i2c/busses/i2c-mpc.c69
-rw-r--r--drivers/input/serio/i8042-io.h5
-rw-r--r--drivers/mtd/maps/Kconfig2
-rw-r--r--drivers/mtd/maps/redwood.c43
-rw-r--r--drivers/net/Kconfig2
-rw-r--r--drivers/net/smc91x.h37
-rw-r--r--drivers/serial/mpc52xx_uart.c145
-rw-r--r--drivers/video/Kconfig1
-rw-r--r--drivers/video/fsl-diu-fb.c137
-rw-r--r--drivers/video/fsl-diu-fb.h223
-rw-r--r--drivers/video/xilinxfb.c2
13 files changed, 294 insertions, 388 deletions
diff --git a/drivers/char/hvc_console.c b/drivers/char/hvc_console.c
index 35cca4c7fb18..fa27d1676ee5 100644
--- a/drivers/char/hvc_console.c
+++ b/drivers/char/hvc_console.c
@@ -194,7 +194,7 @@ static int __init hvc_console_setup(struct console *co, char *options)
194 return 0; 194 return 0;
195} 195}
196 196
197static struct console hvc_con_driver = { 197static struct console hvc_console = {
198 .name = "hvc", 198 .name = "hvc",
199 .write = hvc_console_print, 199 .write = hvc_console_print,
200 .device = hvc_console_device, 200 .device = hvc_console_device,
@@ -220,7 +220,7 @@ static struct console hvc_con_driver = {
220 */ 220 */
221static int __init hvc_console_init(void) 221static int __init hvc_console_init(void)
222{ 222{
223 register_console(&hvc_con_driver); 223 register_console(&hvc_console);
224 return 0; 224 return 0;
225} 225}
226console_initcall(hvc_console_init); 226console_initcall(hvc_console_init);
@@ -276,8 +276,8 @@ int hvc_instantiate(uint32_t vtermno, int index, const struct hv_ops *ops)
276 * now (setup won't fail at this point). It's ok to just 276 * now (setup won't fail at this point). It's ok to just
277 * call register again if previously .setup failed. 277 * call register again if previously .setup failed.
278 */ 278 */
279 if (index == hvc_con_driver.index) 279 if (index == hvc_console.index)
280 register_console(&hvc_con_driver); 280 register_console(&hvc_console);
281 281
282 return 0; 282 return 0;
283} 283}
@@ -641,7 +641,7 @@ int hvc_poll(struct hvc_struct *hp)
641 } 641 }
642 for (i = 0; i < n; ++i) { 642 for (i = 0; i < n; ++i) {
643#ifdef CONFIG_MAGIC_SYSRQ 643#ifdef CONFIG_MAGIC_SYSRQ
644 if (hp->index == hvc_con_driver.index) { 644 if (hp->index == hvc_console.index) {
645 /* Handle the SysRq Hack */ 645 /* Handle the SysRq Hack */
646 /* XXX should support a sequence */ 646 /* XXX should support a sequence */
647 if (buf[i] == '\x0f') { /* ^O */ 647 if (buf[i] == '\x0f') { /* ^O */
@@ -909,7 +909,7 @@ static void __exit hvc_exit(void)
909 tty_unregister_driver(hvc_driver); 909 tty_unregister_driver(hvc_driver);
910 /* return tty_struct instances allocated in hvc_init(). */ 910 /* return tty_struct instances allocated in hvc_init(). */
911 put_tty_driver(hvc_driver); 911 put_tty_driver(hvc_driver);
912 unregister_console(&hvc_con_driver); 912 unregister_console(&hvc_console);
913 } 913 }
914} 914}
915module_exit(hvc_exit); 915module_exit(hvc_exit);
diff --git a/drivers/char/hvsi.c b/drivers/char/hvsi.c
index d4b14ff1c4c1..1f4b6de65a2d 100644
--- a/drivers/char/hvsi.c
+++ b/drivers/char/hvsi.c
@@ -1255,7 +1255,7 @@ static int __init hvsi_console_setup(struct console *console, char *options)
1255 return 0; 1255 return 0;
1256} 1256}
1257 1257
1258static struct console hvsi_con_driver = { 1258static struct console hvsi_console = {
1259 .name = "hvsi", 1259 .name = "hvsi",
1260 .write = hvsi_console_print, 1260 .write = hvsi_console_print,
1261 .device = hvsi_console_device, 1261 .device = hvsi_console_device,
@@ -1308,7 +1308,7 @@ static int __init hvsi_console_init(void)
1308 } 1308 }
1309 1309
1310 if (hvsi_count) 1310 if (hvsi_count)
1311 register_console(&hvsi_con_driver); 1311 register_console(&hvsi_console);
1312 return 0; 1312 return 0;
1313} 1313}
1314console_initcall(hvsi_console_init); 1314console_initcall(hvsi_console_init);
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index df00eb1f11f9..54247d475fc3 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -63,6 +63,7 @@ struct mpc_i2c {
63 wait_queue_head_t queue; 63 wait_queue_head_t queue;
64 struct i2c_adapter adap; 64 struct i2c_adapter adap;
65 int irq; 65 int irq;
66 u32 real_clk;
66}; 67};
67 68
68struct mpc_i2c_divider { 69struct mpc_i2c_divider {
@@ -96,20 +97,23 @@ static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
96/* Sometimes 9th clock pulse isn't generated, and slave doesn't release 97/* Sometimes 9th clock pulse isn't generated, and slave doesn't release
97 * the bus, because it wants to send ACK. 98 * the bus, because it wants to send ACK.
98 * Following sequence of enabling/disabling and sending start/stop generates 99 * Following sequence of enabling/disabling and sending start/stop generates
99 * the pulse, so it's all OK. 100 * the 9 pulses, so it's all OK.
100 */ 101 */
101static void mpc_i2c_fixup(struct mpc_i2c *i2c) 102static void mpc_i2c_fixup(struct mpc_i2c *i2c)
102{ 103{
103 writeccr(i2c, 0); 104 int k;
104 udelay(30); 105 u32 delay_val = 1000000 / i2c->real_clk + 1;
105 writeccr(i2c, CCR_MEN); 106
106 udelay(30); 107 if (delay_val < 2)
107 writeccr(i2c, CCR_MSTA | CCR_MTX); 108 delay_val = 2;
108 udelay(30); 109
109 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN); 110 for (k = 9; k; k--) {
110 udelay(30); 111 writeccr(i2c, 0);
111 writeccr(i2c, CCR_MEN); 112 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
112 udelay(30); 113 udelay(delay_val);
114 writeccr(i2c, CCR_MEN);
115 udelay(delay_val << 1);
116 }
113} 117}
114 118
115static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing) 119static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
@@ -190,15 +194,18 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] __devinitconst = {
190}; 194};
191 195
192static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, 196static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
193 int prescaler) 197 int prescaler, u32 *real_clk)
194{ 198{
195 const struct mpc_i2c_divider *div = NULL; 199 const struct mpc_i2c_divider *div = NULL;
196 unsigned int pvr = mfspr(SPRN_PVR); 200 unsigned int pvr = mfspr(SPRN_PVR);
197 u32 divider; 201 u32 divider;
198 int i; 202 int i;
199 203
200 if (clock == MPC_I2C_CLOCK_LEGACY) 204 if (clock == MPC_I2C_CLOCK_LEGACY) {
205 /* see below - default fdr = 0x3f -> div = 2048 */
206 *real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
201 return -EINVAL; 207 return -EINVAL;
208 }
202 209
203 /* Determine divider value */ 210 /* Determine divider value */
204 divider = mpc5xxx_get_bus_frequency(node) / clock; 211 divider = mpc5xxx_get_bus_frequency(node) / clock;
@@ -216,7 +223,8 @@ static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
216 break; 223 break;
217 } 224 }
218 225
219 return div ? (int)div->fdr : -EINVAL; 226 *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
227 return (int)div->fdr;
220} 228}
221 229
222static void __devinit mpc_i2c_setup_52xx(struct device_node *node, 230static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
@@ -231,13 +239,14 @@ static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
231 return; 239 return;
232 } 240 }
233 241
234 ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler); 242 ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk);
235 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */ 243 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
236 244
237 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); 245 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
238 246
239 if (ret >= 0) 247 if (ret >= 0)
240 dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr); 248 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
249 fdr);
241} 250}
242#else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */ 251#else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
243static void __devinit mpc_i2c_setup_52xx(struct device_node *node, 252static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
@@ -334,14 +343,17 @@ static u32 __devinit mpc_i2c_get_sec_cfg_8xxx(void)
334} 343}
335 344
336static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, 345static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
337 u32 prescaler) 346 u32 prescaler, u32 *real_clk)
338{ 347{
339 const struct mpc_i2c_divider *div = NULL; 348 const struct mpc_i2c_divider *div = NULL;
340 u32 divider; 349 u32 divider;
341 int i; 350 int i;
342 351
343 if (clock == MPC_I2C_CLOCK_LEGACY) 352 if (clock == MPC_I2C_CLOCK_LEGACY) {
353 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
354 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
344 return -EINVAL; 355 return -EINVAL;
356 }
345 357
346 /* Determine proper divider value */ 358 /* Determine proper divider value */
347 if (of_device_is_compatible(node, "fsl,mpc8544-i2c")) 359 if (of_device_is_compatible(node, "fsl,mpc8544-i2c"))
@@ -364,6 +376,7 @@ static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
364 break; 376 break;
365 } 377 }
366 378
379 *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
367 return div ? (int)div->fdr : -EINVAL; 380 return div ? (int)div->fdr : -EINVAL;
368} 381}
369 382
@@ -380,7 +393,7 @@ static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
380 return; 393 return;
381 } 394 }
382 395
383 ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler); 396 ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk);
384 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */ 397 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
385 398
386 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); 399 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
@@ -388,7 +401,7 @@ static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
388 401
389 if (ret >= 0) 402 if (ret >= 0)
390 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n", 403 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
391 clock, fdr >> 8, fdr & 0xff); 404 i2c->real_clk, fdr >> 8, fdr & 0xff);
392} 405}
393 406
394#else /* !CONFIG_FSL_SOC */ 407#else /* !CONFIG_FSL_SOC */
@@ -500,10 +513,14 @@ static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
500 return -EINTR; 513 return -EINTR;
501 } 514 }
502 if (time_after(jiffies, orig_jiffies + HZ)) { 515 if (time_after(jiffies, orig_jiffies + HZ)) {
516 u8 status = readb(i2c->base + MPC_I2C_SR);
517
503 dev_dbg(i2c->dev, "timeout\n"); 518 dev_dbg(i2c->dev, "timeout\n");
504 if (readb(i2c->base + MPC_I2C_SR) == 519 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
505 (CSR_MCF | CSR_MBB | CSR_RXAK)) 520 writeb(status & ~CSR_MAL,
521 i2c->base + MPC_I2C_SR);
506 mpc_i2c_fixup(i2c); 522 mpc_i2c_fixup(i2c);
523 }
507 return -EIO; 524 return -EIO;
508 } 525 }
509 schedule(); 526 schedule();
@@ -595,6 +612,14 @@ static int __devinit fsl_i2c_probe(struct of_device *op,
595 mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock, 0); 612 mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock, 0);
596 } 613 }
597 614
615 prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
616 if (prop && plen == sizeof(u32)) {
617 mpc_ops.timeout = *prop * HZ / 1000000;
618 if (mpc_ops.timeout < 5)
619 mpc_ops.timeout = 5;
620 }
621 dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
622
598 dev_set_drvdata(&op->dev, i2c); 623 dev_set_drvdata(&op->dev, i2c);
599 624
600 i2c->adap = mpc_ops; 625 i2c->adap = mpc_ops;
diff --git a/drivers/input/serio/i8042-io.h b/drivers/input/serio/i8042-io.h
index 847f4aad7ed5..5d48bb66aa73 100644
--- a/drivers/input/serio/i8042-io.h
+++ b/drivers/input/serio/i8042-io.h
@@ -27,6 +27,11 @@
27#include <asm/irq.h> 27#include <asm/irq.h>
28#elif defined(CONFIG_SH_CAYMAN) 28#elif defined(CONFIG_SH_CAYMAN)
29#include <asm/irq.h> 29#include <asm/irq.h>
30#elif defined(CONFIG_PPC)
31extern int of_i8042_kbd_irq;
32extern int of_i8042_aux_irq;
33# define I8042_KBD_IRQ of_i8042_kbd_irq
34# define I8042_AUX_IRQ of_i8042_aux_irq
30#else 35#else
31# define I8042_KBD_IRQ 1 36# define I8042_KBD_IRQ 1
32# define I8042_AUX_IRQ 12 37# define I8042_AUX_IRQ 12
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index f22bc9f05ddb..6629d09f3b38 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -321,7 +321,7 @@ config MTD_CFI_FLAGADM
321 321
322config MTD_REDWOOD 322config MTD_REDWOOD
323 tristate "CFI Flash devices mapped on IBM Redwood" 323 tristate "CFI Flash devices mapped on IBM Redwood"
324 depends on MTD_CFI && ( REDWOOD_4 || REDWOOD_5 || REDWOOD_6 ) 324 depends on MTD_CFI
325 help 325 help
326 This enables access routines for the flash chips on the IBM 326 This enables access routines for the flash chips on the IBM
327 Redwood board. If you have one of these boards and would like to 327 Redwood board. If you have one of these boards and would like to
diff --git a/drivers/mtd/maps/redwood.c b/drivers/mtd/maps/redwood.c
index 933c0b63b016..d2c9db00db0c 100644
--- a/drivers/mtd/maps/redwood.c
+++ b/drivers/mtd/maps/redwood.c
@@ -22,8 +22,6 @@
22 22
23#include <asm/io.h> 23#include <asm/io.h>
24 24
25#if !defined (CONFIG_REDWOOD_6)
26
27#define WINDOW_ADDR 0xffc00000 25#define WINDOW_ADDR 0xffc00000
28#define WINDOW_SIZE 0x00400000 26#define WINDOW_SIZE 0x00400000
29 27
@@ -69,47 +67,6 @@ static struct mtd_partition redwood_flash_partitions[] = {
69 } 67 }
70}; 68};
71 69
72#else /* CONFIG_REDWOOD_6 */
73/* FIXME: the window is bigger - armin */
74#define WINDOW_ADDR 0xff800000
75#define WINDOW_SIZE 0x00800000
76
77#define RW_PART0_OF 0
78#define RW_PART0_SZ 0x400000 /* 4 MiB data */
79#define RW_PART1_OF RW_PART0_OF + RW_PART0_SZ
80#define RW_PART1_SZ 0x10000 /* 64K VPD */
81#define RW_PART2_OF RW_PART1_OF + RW_PART1_SZ
82#define RW_PART2_SZ 0x400000 - (0x10000 + 0x20000)
83#define RW_PART3_OF RW_PART2_OF + RW_PART2_SZ
84#define RW_PART3_SZ 0x20000
85
86static struct mtd_partition redwood_flash_partitions[] = {
87 {
88 .name = "Redwood filesystem",
89 .offset = RW_PART0_OF,
90 .size = RW_PART0_SZ
91 },
92 {
93 .name = "Redwood OpenBIOS Vital Product Data",
94 .offset = RW_PART1_OF,
95 .size = RW_PART1_SZ,
96 .mask_flags = MTD_WRITEABLE /* force read-only */
97 },
98 {
99 .name = "Redwood kernel",
100 .offset = RW_PART2_OF,
101 .size = RW_PART2_SZ
102 },
103 {
104 .name = "Redwood OpenBIOS",
105 .offset = RW_PART3_OF,
106 .size = RW_PART3_SZ,
107 .mask_flags = MTD_WRITEABLE /* force read-only */
108 }
109};
110
111#endif /* CONFIG_REDWOOD_6 */
112
113struct map_info redwood_flash_map = { 70struct map_info redwood_flash_map = {
114 .name = "IBM Redwood", 71 .name = "IBM Redwood",
115 .size = WINDOW_SIZE, 72 .size = WINDOW_SIZE,
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 23c13180ff14..5a6895320b48 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -914,7 +914,7 @@ config SMC91X
914 tristate "SMC 91C9x/91C1xxx support" 914 tristate "SMC 91C9x/91C1xxx support"
915 select CRC32 915 select CRC32
916 select MII 916 select MII
917 depends on ARM || REDWOOD_5 || REDWOOD_6 || M32R || SUPERH || \ 917 depends on ARM || M32R || SUPERH || \
918 MIPS || BLACKFIN || MN10300 || COLDFIRE 918 MIPS || BLACKFIN || MN10300 || COLDFIRE
919 help 919 help
920 This is a driver for SMC's 91x series of Ethernet chipsets, 920 This is a driver for SMC's 91x series of Ethernet chipsets,
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index 8d2772cc42f2..ee747919a766 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -83,43 +83,6 @@ static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
83 } 83 }
84} 84}
85 85
86#elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
87
88/* We can only do 16-bit reads and writes in the static memory space. */
89#define SMC_CAN_USE_8BIT 0
90#define SMC_CAN_USE_16BIT 1
91#define SMC_CAN_USE_32BIT 0
92#define SMC_NOWAIT 1
93
94#define SMC_IO_SHIFT 0
95
96#define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
97#define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
98#define SMC_insw(a, r, p, l) \
99 do { \
100 unsigned long __port = (a) + (r); \
101 u16 *__p = (u16 *)(p); \
102 int __l = (l); \
103 insw(__port, __p, __l); \
104 while (__l > 0) { \
105 *__p = swab16(*__p); \
106 __p++; \
107 __l--; \
108 } \
109 } while (0)
110#define SMC_outsw(a, r, p, l) \
111 do { \
112 unsigned long __port = (a) + (r); \
113 u16 *__p = (u16 *)(p); \
114 int __l = (l); \
115 while (__l > 0) { \
116 /* Believe it or not, the swab isn't needed. */ \
117 outw( /* swab16 */ (*__p++), __port); \
118 __l--; \
119 } \
120 } while (0)
121#define SMC_IRQ_FLAGS (0)
122
123#elif defined(CONFIG_SA1100_PLEB) 86#elif defined(CONFIG_SA1100_PLEB)
124/* We can only do 16-bit reads and writes in the static memory space. */ 87/* We can only do 16-bit reads and writes in the static memory space. */
125#define SMC_CAN_USE_8BIT 1 88#define SMC_CAN_USE_8BIT 1
diff --git a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c
index 84a35f699016..1a88b363005c 100644
--- a/drivers/serial/mpc52xx_uart.c
+++ b/drivers/serial/mpc52xx_uart.c
@@ -113,7 +113,9 @@ struct psc_ops {
113 unsigned char (*read_char)(struct uart_port *port); 113 unsigned char (*read_char)(struct uart_port *port);
114 void (*cw_disable_ints)(struct uart_port *port); 114 void (*cw_disable_ints)(struct uart_port *port);
115 void (*cw_restore_ints)(struct uart_port *port); 115 void (*cw_restore_ints)(struct uart_port *port);
116 unsigned long (*getuartclk)(void *p); 116 unsigned int (*set_baudrate)(struct uart_port *port,
117 struct ktermios *new,
118 struct ktermios *old);
117 int (*clock)(struct uart_port *port, int enable); 119 int (*clock)(struct uart_port *port, int enable);
118 int (*fifoc_init)(void); 120 int (*fifoc_init)(void);
119 void (*fifoc_uninit)(void); 121 void (*fifoc_uninit)(void);
@@ -121,6 +123,16 @@ struct psc_ops {
121 irqreturn_t (*handle_irq)(struct uart_port *port); 123 irqreturn_t (*handle_irq)(struct uart_port *port);
122}; 124};
123 125
126/* setting the prescaler and divisor reg is common for all chips */
127static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
128 u16 prescaler, unsigned int divisor)
129{
130 /* select prescaler */
131 out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
132 out_8(&psc->ctur, divisor >> 8);
133 out_8(&psc->ctlr, divisor & 0xff);
134}
135
124#ifdef CONFIG_PPC_MPC52xx 136#ifdef CONFIG_PPC_MPC52xx
125#define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1)) 137#define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
126static void mpc52xx_psc_fifo_init(struct uart_port *port) 138static void mpc52xx_psc_fifo_init(struct uart_port *port)
@@ -128,9 +140,6 @@ static void mpc52xx_psc_fifo_init(struct uart_port *port)
128 struct mpc52xx_psc __iomem *psc = PSC(port); 140 struct mpc52xx_psc __iomem *psc = PSC(port);
129 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port); 141 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
130 142
131 /* /32 prescaler */
132 out_be16(&psc->mpc52xx_psc_clock_select, 0xdd00);
133
134 out_8(&fifo->rfcntl, 0x00); 143 out_8(&fifo->rfcntl, 0x00);
135 out_be16(&fifo->rfalarm, 0x1ff); 144 out_be16(&fifo->rfalarm, 0x1ff);
136 out_8(&fifo->tfcntl, 0x07); 145 out_8(&fifo->tfcntl, 0x07);
@@ -219,15 +228,47 @@ static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
219 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 228 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
220} 229}
221 230
222/* Search for bus-frequency property in this node or a parent */ 231static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
223static unsigned long mpc52xx_getuartclk(void *p) 232 struct ktermios *new,
233 struct ktermios *old)
224{ 234{
225 /* 235 unsigned int baud;
226 * 5200 UARTs have a / 32 prescaler 236 unsigned int divisor;
227 * but the generic serial code assumes 16 237
228 * so return ipb freq / 2 238 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
229 */ 239 baud = uart_get_baud_rate(port, new, old,
230 return mpc5xxx_get_bus_frequency(p) / 2; 240 port->uartclk / (32 * 0xffff) + 1,
241 port->uartclk / 32);
242 divisor = (port->uartclk + 16 * baud) / (32 * baud);
243
244 /* enable the /32 prescaler and set the divisor */
245 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
246 return baud;
247}
248
249static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
250 struct ktermios *new,
251 struct ktermios *old)
252{
253 unsigned int baud;
254 unsigned int divisor;
255 u16 prescaler;
256
257 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
258 * ipb freq */
259 baud = uart_get_baud_rate(port, new, old,
260 port->uartclk / (32 * 0xffff) + 1,
261 port->uartclk / 4);
262 divisor = (port->uartclk + 2 * baud) / (4 * baud);
263
264 /* select the proper prescaler and set the divisor */
265 if (divisor > 0xffff) {
266 divisor = (divisor + 4) / 8;
267 prescaler = 0xdd00; /* /32 */
268 } else
269 prescaler = 0xff00; /* /4 */
270 mpc52xx_set_divisor(PSC(port), prescaler, divisor);
271 return baud;
231} 272}
232 273
233static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np) 274static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
@@ -258,7 +299,28 @@ static struct psc_ops mpc52xx_psc_ops = {
258 .read_char = mpc52xx_psc_read_char, 299 .read_char = mpc52xx_psc_read_char,
259 .cw_disable_ints = mpc52xx_psc_cw_disable_ints, 300 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
260 .cw_restore_ints = mpc52xx_psc_cw_restore_ints, 301 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
261 .getuartclk = mpc52xx_getuartclk, 302 .set_baudrate = mpc5200_psc_set_baudrate,
303 .get_irq = mpc52xx_psc_get_irq,
304 .handle_irq = mpc52xx_psc_handle_irq,
305};
306
307static struct psc_ops mpc5200b_psc_ops = {
308 .fifo_init = mpc52xx_psc_fifo_init,
309 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
310 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
311 .rx_rdy = mpc52xx_psc_rx_rdy,
312 .tx_rdy = mpc52xx_psc_tx_rdy,
313 .tx_empty = mpc52xx_psc_tx_empty,
314 .stop_rx = mpc52xx_psc_stop_rx,
315 .start_tx = mpc52xx_psc_start_tx,
316 .stop_tx = mpc52xx_psc_stop_tx,
317 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
318 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
319 .write_char = mpc52xx_psc_write_char,
320 .read_char = mpc52xx_psc_read_char,
321 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
322 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
323 .set_baudrate = mpc5200b_psc_set_baudrate,
262 .get_irq = mpc52xx_psc_get_irq, 324 .get_irq = mpc52xx_psc_get_irq,
263 .handle_irq = mpc52xx_psc_handle_irq, 325 .handle_irq = mpc52xx_psc_handle_irq,
264}; 326};
@@ -392,9 +454,35 @@ static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
392 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f); 454 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
393} 455}
394 456
395static unsigned long mpc512x_getuartclk(void *p) 457static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
458 struct ktermios *new,
459 struct ktermios *old)
396{ 460{
397 return mpc5xxx_get_bus_frequency(p); 461 unsigned int baud;
462 unsigned int divisor;
463
464 /*
465 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
466 * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
467 * Furthermore, it states that "After reset, the prescaler by 10
468 * for the UART mode is selected", but the reset register value is
469 * 0x0000 which means a /32 prescaler. This is wrong.
470 *
471 * In reality using /32 prescaler doesn't work, as it is not supported!
472 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
473 * Chapter 4.1 PSC in UART Mode.
474 * Calculate with a /16 prescaler here.
475 */
476
477 /* uartclk contains the ips freq */
478 baud = uart_get_baud_rate(port, new, old,
479 port->uartclk / (16 * 0xffff) + 1,
480 port->uartclk / 16);
481 divisor = (port->uartclk + 8 * baud) / (16 * baud);
482
483 /* enable the /16 prescaler and set the divisor */
484 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
485 return baud;
398} 486}
399 487
400/* Init PSC FIFO Controller */ 488/* Init PSC FIFO Controller */
@@ -498,7 +586,7 @@ static struct psc_ops mpc512x_psc_ops = {
498 .read_char = mpc512x_psc_read_char, 586 .read_char = mpc512x_psc_read_char,
499 .cw_disable_ints = mpc512x_psc_cw_disable_ints, 587 .cw_disable_ints = mpc512x_psc_cw_disable_ints,
500 .cw_restore_ints = mpc512x_psc_cw_restore_ints, 588 .cw_restore_ints = mpc512x_psc_cw_restore_ints,
501 .getuartclk = mpc512x_getuartclk, 589 .set_baudrate = mpc512x_psc_set_baudrate,
502 .clock = mpc512x_psc_clock, 590 .clock = mpc512x_psc_clock,
503 .fifoc_init = mpc512x_psc_fifoc_init, 591 .fifoc_init = mpc512x_psc_fifoc_init,
504 .fifoc_uninit = mpc512x_psc_fifoc_uninit, 592 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
@@ -666,8 +754,8 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
666 struct mpc52xx_psc __iomem *psc = PSC(port); 754 struct mpc52xx_psc __iomem *psc = PSC(port);
667 unsigned long flags; 755 unsigned long flags;
668 unsigned char mr1, mr2; 756 unsigned char mr1, mr2;
669 unsigned short ctr; 757 unsigned int j;
670 unsigned int j, baud, quot; 758 unsigned int baud;
671 759
672 /* Prepare what we're gonna write */ 760 /* Prepare what we're gonna write */
673 mr1 = 0; 761 mr1 = 0;
@@ -704,16 +792,9 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
704 mr2 |= MPC52xx_PSC_MODE_TXCTS; 792 mr2 |= MPC52xx_PSC_MODE_TXCTS;
705 } 793 }
706 794
707 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
708 quot = uart_get_divisor(port, baud);
709 ctr = quot & 0xffff;
710
711 /* Get the lock */ 795 /* Get the lock */
712 spin_lock_irqsave(&port->lock, flags); 796 spin_lock_irqsave(&port->lock, flags);
713 797
714 /* Update the per-port timeout */
715 uart_update_timeout(port, new->c_cflag, baud);
716
717 /* Do our best to flush TX & RX, so we don't lose anything */ 798 /* Do our best to flush TX & RX, so we don't lose anything */
718 /* But we don't wait indefinitely ! */ 799 /* But we don't wait indefinitely ! */
719 j = 5000000; /* Maximum wait */ 800 j = 5000000; /* Maximum wait */
@@ -737,8 +818,10 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
737 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); 818 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
738 out_8(&psc->mode, mr1); 819 out_8(&psc->mode, mr1);
739 out_8(&psc->mode, mr2); 820 out_8(&psc->mode, mr2);
740 out_8(&psc->ctur, ctr >> 8); 821 baud = psc_ops->set_baudrate(port, new, old);
741 out_8(&psc->ctlr, ctr & 0xff); 822
823 /* Update the per-port timeout */
824 uart_update_timeout(port, new->c_cflag, baud);
742 825
743 if (UART_ENABLE_MS(port, new->c_cflag)) 826 if (UART_ENABLE_MS(port, new->c_cflag))
744 mpc52xx_uart_enable_ms(port); 827 mpc52xx_uart_enable_ms(port);
@@ -1118,7 +1201,7 @@ mpc52xx_console_setup(struct console *co, char *options)
1118 return ret; 1201 return ret;
1119 } 1202 }
1120 1203
1121 uartclk = psc_ops->getuartclk(np); 1204 uartclk = mpc5xxx_get_bus_frequency(np);
1122 if (uartclk == 0) { 1205 if (uartclk == 0) {
1123 pr_debug("Could not find uart clock frequency!\n"); 1206 pr_debug("Could not find uart clock frequency!\n");
1124 return -EINVAL; 1207 return -EINVAL;
@@ -1201,6 +1284,7 @@ static struct uart_driver mpc52xx_uart_driver = {
1201 1284
1202static struct of_device_id mpc52xx_uart_of_match[] = { 1285static struct of_device_id mpc52xx_uart_of_match[] = {
1203#ifdef CONFIG_PPC_MPC52xx 1286#ifdef CONFIG_PPC_MPC52xx
1287 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1204 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, 1288 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1205 /* binding used by old lite5200 device trees: */ 1289 /* binding used by old lite5200 device trees: */
1206 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, 1290 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
@@ -1233,7 +1317,10 @@ mpc52xx_uart_of_probe(struct of_device *op, const struct of_device_id *match)
1233 pr_debug("Found %s assigned to ttyPSC%x\n", 1317 pr_debug("Found %s assigned to ttyPSC%x\n",
1234 mpc52xx_uart_nodes[idx]->full_name, idx); 1318 mpc52xx_uart_nodes[idx]->full_name, idx);
1235 1319
1236 uartclk = psc_ops->getuartclk(op->dev.of_node); 1320 /* set the uart clock to the input clock of the psc, the different
1321 * prescalers are taken into account in the set_baudrate() methods
1322 * of the respective chip */
1323 uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node);
1237 if (uartclk == 0) { 1324 if (uartclk == 0) {
1238 dev_dbg(&op->dev, "Could not find uart clock frequency!\n"); 1325 dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1239 return -EINVAL; 1326 return -EINVAL;
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 9e711a1d0d97..7b11ea68c80e 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1871,6 +1871,7 @@ config FB_MBX_DEBUG
1871config FB_FSL_DIU 1871config FB_FSL_DIU
1872 tristate "Freescale DIU framebuffer support" 1872 tristate "Freescale DIU framebuffer support"
1873 depends on FB && FSL_SOC 1873 depends on FB && FSL_SOC
1874 select FB_MODE_HELPERS
1874 select FB_CFB_FILLRECT 1875 select FB_CFB_FILLRECT
1875 select FB_CFB_COPYAREA 1876 select FB_CFB_COPYAREA
1876 select FB_CFB_IMAGEBLIT 1877 select FB_CFB_IMAGEBLIT
diff --git a/drivers/video/fsl-diu-fb.c b/drivers/video/fsl-diu-fb.c
index 27455ce298b7..e38ad2224540 100644
--- a/drivers/video/fsl-diu-fb.c
+++ b/drivers/video/fsl-diu-fb.c
@@ -34,7 +34,8 @@
34#include <linux/of_platform.h> 34#include <linux/of_platform.h>
35 35
36#include <sysdev/fsl_soc.h> 36#include <sysdev/fsl_soc.h>
37#include "fsl-diu-fb.h" 37#include <linux/fsl-diu-fb.h>
38#include "edid.h"
38 39
39/* 40/*
40 * These parameters give default parameters 41 * These parameters give default parameters
@@ -217,6 +218,7 @@ struct mfb_info {
217 int x_aoi_d; /* aoi display x offset to physical screen */ 218 int x_aoi_d; /* aoi display x offset to physical screen */
218 int y_aoi_d; /* aoi display y offset to physical screen */ 219 int y_aoi_d; /* aoi display y offset to physical screen */
219 struct fsl_diu_data *parent; 220 struct fsl_diu_data *parent;
221 u8 *edid_data;
220}; 222};
221 223
222 224
@@ -317,6 +319,17 @@ static void fsl_diu_free(void *virt, size_t size)
317 free_pages_exact(virt, size); 319 free_pages_exact(virt, size);
318} 320}
319 321
322/*
323 * Workaround for failed writing desc register of planes.
324 * Needed with MPC5121 DIU rev 2.0 silicon.
325 */
326void wr_reg_wa(u32 *reg, u32 val)
327{
328 do {
329 out_be32(reg, val);
330 } while (in_be32(reg) != val);
331}
332
320static int fsl_diu_enable_panel(struct fb_info *info) 333static int fsl_diu_enable_panel(struct fb_info *info)
321{ 334{
322 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par; 335 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
@@ -330,7 +343,7 @@ static int fsl_diu_enable_panel(struct fb_info *info)
330 switch (mfbi->index) { 343 switch (mfbi->index) {
331 case 0: /* plane 0 */ 344 case 0: /* plane 0 */
332 if (hw->desc[0] != ad->paddr) 345 if (hw->desc[0] != ad->paddr)
333 out_be32(&hw->desc[0], ad->paddr); 346 wr_reg_wa(&hw->desc[0], ad->paddr);
334 break; 347 break;
335 case 1: /* plane 1 AOI 0 */ 348 case 1: /* plane 1 AOI 0 */
336 cmfbi = machine_data->fsl_diu_info[2]->par; 349 cmfbi = machine_data->fsl_diu_info[2]->par;
@@ -340,7 +353,7 @@ static int fsl_diu_enable_panel(struct fb_info *info)
340 cpu_to_le32(cmfbi->ad->paddr); 353 cpu_to_le32(cmfbi->ad->paddr);
341 else 354 else
342 ad->next_ad = 0; 355 ad->next_ad = 0;
343 out_be32(&hw->desc[1], ad->paddr); 356 wr_reg_wa(&hw->desc[1], ad->paddr);
344 } 357 }
345 break; 358 break;
346 case 3: /* plane 2 AOI 0 */ 359 case 3: /* plane 2 AOI 0 */
@@ -351,14 +364,14 @@ static int fsl_diu_enable_panel(struct fb_info *info)
351 cpu_to_le32(cmfbi->ad->paddr); 364 cpu_to_le32(cmfbi->ad->paddr);
352 else 365 else
353 ad->next_ad = 0; 366 ad->next_ad = 0;
354 out_be32(&hw->desc[2], ad->paddr); 367 wr_reg_wa(&hw->desc[2], ad->paddr);
355 } 368 }
356 break; 369 break;
357 case 2: /* plane 1 AOI 1 */ 370 case 2: /* plane 1 AOI 1 */
358 pmfbi = machine_data->fsl_diu_info[1]->par; 371 pmfbi = machine_data->fsl_diu_info[1]->par;
359 ad->next_ad = 0; 372 ad->next_ad = 0;
360 if (hw->desc[1] == machine_data->dummy_ad->paddr) 373 if (hw->desc[1] == machine_data->dummy_ad->paddr)
361 out_be32(&hw->desc[1], ad->paddr); 374 wr_reg_wa(&hw->desc[1], ad->paddr);
362 else /* AOI0 open */ 375 else /* AOI0 open */
363 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr); 376 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
364 break; 377 break;
@@ -366,7 +379,7 @@ static int fsl_diu_enable_panel(struct fb_info *info)
366 pmfbi = machine_data->fsl_diu_info[3]->par; 379 pmfbi = machine_data->fsl_diu_info[3]->par;
367 ad->next_ad = 0; 380 ad->next_ad = 0;
368 if (hw->desc[2] == machine_data->dummy_ad->paddr) 381 if (hw->desc[2] == machine_data->dummy_ad->paddr)
369 out_be32(&hw->desc[2], ad->paddr); 382 wr_reg_wa(&hw->desc[2], ad->paddr);
370 else /* AOI0 was open */ 383 else /* AOI0 was open */
371 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr); 384 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
372 break; 385 break;
@@ -390,27 +403,24 @@ static int fsl_diu_disable_panel(struct fb_info *info)
390 switch (mfbi->index) { 403 switch (mfbi->index) {
391 case 0: /* plane 0 */ 404 case 0: /* plane 0 */
392 if (hw->desc[0] != machine_data->dummy_ad->paddr) 405 if (hw->desc[0] != machine_data->dummy_ad->paddr)
393 out_be32(&hw->desc[0], 406 wr_reg_wa(&hw->desc[0], machine_data->dummy_ad->paddr);
394 machine_data->dummy_ad->paddr);
395 break; 407 break;
396 case 1: /* plane 1 AOI 0 */ 408 case 1: /* plane 1 AOI 0 */
397 cmfbi = machine_data->fsl_diu_info[2]->par; 409 cmfbi = machine_data->fsl_diu_info[2]->par;
398 if (cmfbi->count > 0) /* AOI1 is open */ 410 if (cmfbi->count > 0) /* AOI1 is open */
399 out_be32(&hw->desc[1], cmfbi->ad->paddr); 411 wr_reg_wa(&hw->desc[1], cmfbi->ad->paddr);
400 /* move AOI1 to the first */ 412 /* move AOI1 to the first */
401 else /* AOI1 was closed */ 413 else /* AOI1 was closed */
402 out_be32(&hw->desc[1], 414 wr_reg_wa(&hw->desc[1], machine_data->dummy_ad->paddr);
403 machine_data->dummy_ad->paddr);
404 /* close AOI 0 */ 415 /* close AOI 0 */
405 break; 416 break;
406 case 3: /* plane 2 AOI 0 */ 417 case 3: /* plane 2 AOI 0 */
407 cmfbi = machine_data->fsl_diu_info[4]->par; 418 cmfbi = machine_data->fsl_diu_info[4]->par;
408 if (cmfbi->count > 0) /* AOI1 is open */ 419 if (cmfbi->count > 0) /* AOI1 is open */
409 out_be32(&hw->desc[2], cmfbi->ad->paddr); 420 wr_reg_wa(&hw->desc[2], cmfbi->ad->paddr);
410 /* move AOI1 to the first */ 421 /* move AOI1 to the first */
411 else /* AOI1 was closed */ 422 else /* AOI1 was closed */
412 out_be32(&hw->desc[2], 423 wr_reg_wa(&hw->desc[2], machine_data->dummy_ad->paddr);
413 machine_data->dummy_ad->paddr);
414 /* close AOI 0 */ 424 /* close AOI 0 */
415 break; 425 break;
416 case 2: /* plane 1 AOI 1 */ 426 case 2: /* plane 1 AOI 1 */
@@ -421,7 +431,7 @@ static int fsl_diu_disable_panel(struct fb_info *info)
421 /* AOI0 is open, must be the first */ 431 /* AOI0 is open, must be the first */
422 pmfbi->ad->next_ad = 0; 432 pmfbi->ad->next_ad = 0;
423 } else /* AOI1 is the first in the chain */ 433 } else /* AOI1 is the first in the chain */
424 out_be32(&hw->desc[1], machine_data->dummy_ad->paddr); 434 wr_reg_wa(&hw->desc[1], machine_data->dummy_ad->paddr);
425 /* close AOI 1 */ 435 /* close AOI 1 */
426 break; 436 break;
427 case 4: /* plane 2 AOI 1 */ 437 case 4: /* plane 2 AOI 1 */
@@ -432,7 +442,7 @@ static int fsl_diu_disable_panel(struct fb_info *info)
432 /* AOI0 is open, must be the first */ 442 /* AOI0 is open, must be the first */
433 pmfbi->ad->next_ad = 0; 443 pmfbi->ad->next_ad = 0;
434 } else /* AOI1 is the first in the chain */ 444 } else /* AOI1 is the first in the chain */
435 out_be32(&hw->desc[2], machine_data->dummy_ad->paddr); 445 wr_reg_wa(&hw->desc[2], machine_data->dummy_ad->paddr);
436 /* close AOI 1 */ 446 /* close AOI 1 */
437 break; 447 break;
438 default: 448 default:
@@ -1100,6 +1110,10 @@ static int fsl_diu_open(struct fb_info *info, int user)
1100 struct mfb_info *mfbi = info->par; 1110 struct mfb_info *mfbi = info->par;
1101 int res = 0; 1111 int res = 0;
1102 1112
1113 /* free boot splash memory on first /dev/fb0 open */
1114 if (!mfbi->index && diu_ops.release_bootmem)
1115 diu_ops.release_bootmem();
1116
1103 spin_lock(&diu_lock); 1117 spin_lock(&diu_lock);
1104 mfbi->count++; 1118 mfbi->count++;
1105 if (mfbi->count == 1) { 1119 if (mfbi->count == 1) {
@@ -1173,18 +1187,30 @@ static int __devinit install_fb(struct fb_info *info)
1173 int rc; 1187 int rc;
1174 struct mfb_info *mfbi = info->par; 1188 struct mfb_info *mfbi = info->par;
1175 const char *aoi_mode, *init_aoi_mode = "320x240"; 1189 const char *aoi_mode, *init_aoi_mode = "320x240";
1190 struct fb_videomode *db = fsl_diu_mode_db;
1191 unsigned int dbsize = ARRAY_SIZE(fsl_diu_mode_db);
1192 int has_default_mode = 1;
1176 1193
1177 if (init_fbinfo(info)) 1194 if (init_fbinfo(info))
1178 return -EINVAL; 1195 return -EINVAL;
1179 1196
1180 if (mfbi->index == 0) /* plane 0 */ 1197 if (mfbi->index == 0) { /* plane 0 */
1198 if (mfbi->edid_data) {
1199 /* Now build modedb from EDID */
1200 fb_edid_to_monspecs(mfbi->edid_data, &info->monspecs);
1201 fb_videomode_to_modelist(info->monspecs.modedb,
1202 info->monspecs.modedb_len,
1203 &info->modelist);
1204 db = info->monspecs.modedb;
1205 dbsize = info->monspecs.modedb_len;
1206 }
1181 aoi_mode = fb_mode; 1207 aoi_mode = fb_mode;
1182 else 1208 } else {
1183 aoi_mode = init_aoi_mode; 1209 aoi_mode = init_aoi_mode;
1210 }
1184 pr_debug("mode used = %s\n", aoi_mode); 1211 pr_debug("mode used = %s\n", aoi_mode);
1185 rc = fb_find_mode(&info->var, info, aoi_mode, fsl_diu_mode_db, 1212 rc = fb_find_mode(&info->var, info, aoi_mode, db, dbsize,
1186 ARRAY_SIZE(fsl_diu_mode_db), &fsl_diu_default_mode, default_bpp); 1213 &fsl_diu_default_mode, default_bpp);
1187
1188 switch (rc) { 1214 switch (rc) {
1189 case 1: 1215 case 1:
1190 pr_debug("using mode specified in @mode\n"); 1216 pr_debug("using mode specified in @mode\n");
@@ -1202,10 +1228,50 @@ static int __devinit install_fb(struct fb_info *info)
1202 default: 1228 default:
1203 pr_debug("rc = %d\n", rc); 1229 pr_debug("rc = %d\n", rc);
1204 pr_debug("failed to find mode\n"); 1230 pr_debug("failed to find mode\n");
1205 return -EINVAL; 1231 /*
1232 * For plane 0 we continue and look into
1233 * driver's internal modedb.
1234 */
1235 if (mfbi->index == 0 && mfbi->edid_data)
1236 has_default_mode = 0;
1237 else
1238 return -EINVAL;
1206 break; 1239 break;
1207 } 1240 }
1208 1241
1242 if (!has_default_mode) {
1243 rc = fb_find_mode(&info->var, info, aoi_mode, fsl_diu_mode_db,
1244 ARRAY_SIZE(fsl_diu_mode_db),
1245 &fsl_diu_default_mode,
1246 default_bpp);
1247 if (rc > 0 && rc < 5)
1248 has_default_mode = 1;
1249 }
1250
1251 /* Still not found, use preferred mode from database if any */
1252 if (!has_default_mode && info->monspecs.modedb) {
1253 struct fb_monspecs *specs = &info->monspecs;
1254 struct fb_videomode *modedb = &specs->modedb[0];
1255
1256 /*
1257 * Get preferred timing. If not found,
1258 * first mode in database will be used.
1259 */
1260 if (specs->misc & FB_MISC_1ST_DETAIL) {
1261 int i;
1262
1263 for (i = 0; i < specs->modedb_len; i++) {
1264 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1265 modedb = &specs->modedb[i];
1266 break;
1267 }
1268 }
1269 }
1270
1271 info->var.bits_per_pixel = default_bpp;
1272 fb_videomode_to_var(&info->var, modedb);
1273 }
1274
1209 pr_debug("xres_virtual %d\n", info->var.xres_virtual); 1275 pr_debug("xres_virtual %d\n", info->var.xres_virtual);
1210 pr_debug("bits_per_pixel %d\n", info->var.bits_per_pixel); 1276 pr_debug("bits_per_pixel %d\n", info->var.bits_per_pixel);
1211 1277
@@ -1244,6 +1310,9 @@ static void uninstall_fb(struct fb_info *info)
1244 if (!mfbi->registered) 1310 if (!mfbi->registered)
1245 return; 1311 return;
1246 1312
1313 if (mfbi->index == 0)
1314 kfree(mfbi->edid_data);
1315
1247 unregister_framebuffer(info); 1316 unregister_framebuffer(info);
1248 unmap_video_memory(info); 1317 unmap_video_memory(info);
1249 if (&info->cmap) 1318 if (&info->cmap)
@@ -1427,6 +1496,7 @@ static int __devinit fsl_diu_probe(struct of_device *ofdev,
1427 int ret, i, error = 0; 1496 int ret, i, error = 0;
1428 struct resource res; 1497 struct resource res;
1429 struct fsl_diu_data *machine_data; 1498 struct fsl_diu_data *machine_data;
1499 int diu_mode;
1430 1500
1431 machine_data = kzalloc(sizeof(struct fsl_diu_data), GFP_KERNEL); 1501 machine_data = kzalloc(sizeof(struct fsl_diu_data), GFP_KERNEL);
1432 if (!machine_data) 1502 if (!machine_data)
@@ -1443,6 +1513,17 @@ static int __devinit fsl_diu_probe(struct of_device *ofdev,
1443 mfbi = machine_data->fsl_diu_info[i]->par; 1513 mfbi = machine_data->fsl_diu_info[i]->par;
1444 memcpy(mfbi, &mfb_template[i], sizeof(struct mfb_info)); 1514 memcpy(mfbi, &mfb_template[i], sizeof(struct mfb_info));
1445 mfbi->parent = machine_data; 1515 mfbi->parent = machine_data;
1516
1517 if (mfbi->index == 0) {
1518 const u8 *prop;
1519 int len;
1520
1521 /* Get EDID */
1522 prop = of_get_property(np, "edid", &len);
1523 if (prop && len == EDID_LENGTH)
1524 mfbi->edid_data = kmemdup(prop, EDID_LENGTH,
1525 GFP_KERNEL);
1526 }
1446 } 1527 }
1447 1528
1448 ret = of_address_to_resource(np, 0, &res); 1529 ret = of_address_to_resource(np, 0, &res);
@@ -1463,7 +1544,9 @@ static int __devinit fsl_diu_probe(struct of_device *ofdev,
1463 goto error2; 1544 goto error2;
1464 } 1545 }
1465 1546
1466 out_be32(&dr.diu_reg->diu_mode, 0); /* disable DIU anyway*/ 1547 diu_mode = in_be32(&dr.diu_reg->diu_mode);
1548 if (diu_mode != MFB_MODE1)
1549 out_be32(&dr.diu_reg->diu_mode, 0); /* disable DIU */
1467 1550
1468 /* Get the IRQ of the DIU */ 1551 /* Get the IRQ of the DIU */
1469 machine_data->irq = irq_of_parse_and_map(np, 0); 1552 machine_data->irq = irq_of_parse_and_map(np, 0);
@@ -1511,7 +1594,13 @@ static int __devinit fsl_diu_probe(struct of_device *ofdev,
1511 machine_data->dummy_ad->offset_xyd = 0; 1594 machine_data->dummy_ad->offset_xyd = 0;
1512 machine_data->dummy_ad->next_ad = 0; 1595 machine_data->dummy_ad->next_ad = 0;
1513 1596
1514 out_be32(&dr.diu_reg->desc[0], machine_data->dummy_ad->paddr); 1597 /*
1598 * Let DIU display splash screen if it was pre-initialized
1599 * by the bootloader, set dummy area descriptor otherwise.
1600 */
1601 if (diu_mode != MFB_MODE1)
1602 out_be32(&dr.diu_reg->desc[0], machine_data->dummy_ad->paddr);
1603
1515 out_be32(&dr.diu_reg->desc[1], machine_data->dummy_ad->paddr); 1604 out_be32(&dr.diu_reg->desc[1], machine_data->dummy_ad->paddr);
1516 out_be32(&dr.diu_reg->desc[2], machine_data->dummy_ad->paddr); 1605 out_be32(&dr.diu_reg->desc[2], machine_data->dummy_ad->paddr);
1517 1606
diff --git a/drivers/video/fsl-diu-fb.h b/drivers/video/fsl-diu-fb.h
deleted file mode 100644
index fc295d7ea463..000000000000
--- a/drivers/video/fsl-diu-fb.h
+++ /dev/null
@@ -1,223 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Freescale DIU Frame Buffer device driver
5 *
6 * Authors: Hongjun Chen <hong-jun.chen@freescale.com>
7 * Paul Widmer <paul.widmer@freescale.com>
8 * Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
9 * York Sun <yorksun@freescale.com>
10 *
11 * Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19
20#ifndef __FSL_DIU_FB_H__
21#define __FSL_DIU_FB_H__
22
23/* Arbitrary threshold to determine the allocation method
24 * See mpc8610fb_set_par(), map_video_memory(), and unmap_video_memory()
25 */
26#define MEM_ALLOC_THRESHOLD (1024*768*4+32)
27/* Minimum value that the pixel clock can be set to in pico seconds
28 * This is determined by platform clock/3 where the minimum platform
29 * clock is 533MHz. This gives 5629 pico seconds.
30 */
31#define MIN_PIX_CLK 5629
32#define MAX_PIX_CLK 96096
33
34#include <linux/types.h>
35
36struct mfb_alpha {
37 int enable;
38 int alpha;
39};
40
41struct mfb_chroma_key {
42 int enable;
43 __u8 red_max;
44 __u8 green_max;
45 __u8 blue_max;
46 __u8 red_min;
47 __u8 green_min;
48 __u8 blue_min;
49};
50
51struct aoi_display_offset {
52 int x_aoi_d;
53 int y_aoi_d;
54};
55
56#define MFB_SET_CHROMA_KEY _IOW('M', 1, struct mfb_chroma_key)
57#define MFB_WAIT_FOR_VSYNC _IOW('F', 0x20, u_int32_t)
58#define MFB_SET_BRIGHTNESS _IOW('M', 3, __u8)
59
60#define MFB_SET_ALPHA 0x80014d00
61#define MFB_GET_ALPHA 0x40014d00
62#define MFB_SET_AOID 0x80084d04
63#define MFB_GET_AOID 0x40084d04
64#define MFB_SET_PIXFMT 0x80014d08
65#define MFB_GET_PIXFMT 0x40014d08
66
67#define FBIOGET_GWINFO 0x46E0
68#define FBIOPUT_GWINFO 0x46E1
69
70#ifdef __KERNEL__
71#include <linux/spinlock.h>
72
73/*
74 * These are the fields of area descriptor(in DDR memory) for every plane
75 */
76struct diu_ad {
77 /* Word 0(32-bit) in DDR memory */
78/* __u16 comp; */
79/* __u16 pixel_s:2; */
80/* __u16 pallete:1; */
81/* __u16 red_c:2; */
82/* __u16 green_c:2; */
83/* __u16 blue_c:2; */
84/* __u16 alpha_c:3; */
85/* __u16 byte_f:1; */
86/* __u16 res0:3; */
87
88 __be32 pix_fmt; /* hard coding pixel format */
89
90 /* Word 1(32-bit) in DDR memory */
91 __le32 addr;
92
93 /* Word 2(32-bit) in DDR memory */
94/* __u32 delta_xs:11; */
95/* __u32 res1:1; */
96/* __u32 delta_ys:11; */
97/* __u32 res2:1; */
98/* __u32 g_alpha:8; */
99 __le32 src_size_g_alpha;
100
101 /* Word 3(32-bit) in DDR memory */
102/* __u32 delta_xi:11; */
103/* __u32 res3:5; */
104/* __u32 delta_yi:11; */
105/* __u32 res4:3; */
106/* __u32 flip:2; */
107 __le32 aoi_size;
108
109 /* Word 4(32-bit) in DDR memory */
110 /*__u32 offset_xi:11;
111 __u32 res5:5;
112 __u32 offset_yi:11;
113 __u32 res6:5;
114 */
115 __le32 offset_xyi;
116
117 /* Word 5(32-bit) in DDR memory */
118 /*__u32 offset_xd:11;
119 __u32 res7:5;
120 __u32 offset_yd:11;
121 __u32 res8:5; */
122 __le32 offset_xyd;
123
124
125 /* Word 6(32-bit) in DDR memory */
126 __u8 ckmax_r;
127 __u8 ckmax_g;
128 __u8 ckmax_b;
129 __u8 res9;
130
131 /* Word 7(32-bit) in DDR memory */
132 __u8 ckmin_r;
133 __u8 ckmin_g;
134 __u8 ckmin_b;
135 __u8 res10;
136/* __u32 res10:8; */
137
138 /* Word 8(32-bit) in DDR memory */
139 __le32 next_ad;
140
141 /* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
142 __u32 paddr;
143} __attribute__ ((packed));
144
145/* DIU register map */
146struct diu {
147 __be32 desc[3];
148 __be32 gamma;
149 __be32 pallete;
150 __be32 cursor;
151 __be32 curs_pos;
152 __be32 diu_mode;
153 __be32 bgnd;
154 __be32 bgnd_wb;
155 __be32 disp_size;
156 __be32 wb_size;
157 __be32 wb_mem_addr;
158 __be32 hsyn_para;
159 __be32 vsyn_para;
160 __be32 syn_pol;
161 __be32 thresholds;
162 __be32 int_status;
163 __be32 int_mask;
164 __be32 colorbar[8];
165 __be32 filling;
166 __be32 plut;
167} __attribute__ ((packed));
168
169struct diu_hw {
170 struct diu *diu_reg;
171 spinlock_t reg_lock;
172
173 __u32 mode; /* DIU operation mode */
174};
175
176struct diu_addr {
177 __u8 __iomem *vaddr; /* Virtual address */
178 dma_addr_t paddr; /* Physical address */
179 __u32 offset;
180};
181
182struct diu_pool {
183 struct diu_addr ad;
184 struct diu_addr gamma;
185 struct diu_addr pallete;
186 struct diu_addr cursor;
187};
188
189#define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of DIU */
190#define INT_LCDC 64 /* DIU interrupt number */
191
192#define FSL_AOI_NUM 6 /* 5 AOIs and one dummy AOI */
193 /* 1 for plane 0, 2 for plane 1&2 each */
194
195/* Minimum X and Y resolutions */
196#define MIN_XRES 64
197#define MIN_YRES 64
198
199/* HW cursor parameters */
200#define MAX_CURS 32
201
202/* Modes of operation of DIU */
203#define MFB_MODE0 0 /* DIU off */
204#define MFB_MODE1 1 /* All three planes output to display */
205#define MFB_MODE2 2 /* Plane 1 to display, planes 2+3 written back*/
206#define MFB_MODE3 3 /* All three planes written back to memory */
207#define MFB_MODE4 4 /* Color bar generation */
208
209/* INT_STATUS/INT_MASK field descriptions */
210#define INT_VSYNC 0x01 /* Vsync interrupt */
211#define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */
212#define INT_UNDRUN 0x04 /* Under run exception interrupt */
213#define INT_PARERR 0x08 /* Display parameters error interrupt */
214#define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */
215
216/* Panels'operation modes */
217#define MFB_TYPE_OUTPUT 0 /* Panel output to display */
218#define MFB_TYPE_OFF 1 /* Panel off */
219#define MFB_TYPE_WB 2 /* Panel written back to memory */
220#define MFB_TYPE_TEST 3 /* Panel generate color bar */
221
222#endif /* __KERNEL__ */
223#endif /* __FSL_DIU_FB_H__ */
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index 574dc54e12d4..29b5daacc217 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -485,6 +485,8 @@ static int __devexit xilinxfb_of_remove(struct of_device *op)
485/* Match table for of_platform binding */ 485/* Match table for of_platform binding */
486static struct of_device_id xilinxfb_of_match[] __devinitdata = { 486static struct of_device_id xilinxfb_of_match[] __devinitdata = {
487 { .compatible = "xlnx,xps-tft-1.00.a", }, 487 { .compatible = "xlnx,xps-tft-1.00.a", },
488 { .compatible = "xlnx,xps-tft-2.00.a", },
489 { .compatible = "xlnx,xps-tft-2.01.a", },
488 { .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", }, 490 { .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", },
489 { .compatible = "xlnx,plb-dvi-cntlr-ref-1.00.c", }, 491 { .compatible = "xlnx,plb-dvi-cntlr-ref-1.00.c", },
490 {}, 492 {},
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 08:40:16 -0500