3 files changed, 28 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 90414ae86afc..409826da3099 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1045,6 +1045,8 @@ void i915_gem_clflush_object(struct drm_gem_object *obj);
 int i915_gem_object_set_domain(struct drm_gem_object *obj,
                                uint32_t read_domains,
                                uint32_t write_domain);
+int i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
+                              bool interruptible);
 int i915_gem_init_ringbuffer(struct drm_device *dev);
 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index eba9b1615228..951e3d463113 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2907,6 +2907,20 @@ i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
         return 0;
 }
 
+int
+i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
+                          bool interruptible)
+{
+        if (!obj->active)
+                return 0;
+
+        if (obj->base.write_domain & I915_GEM_GPU_DOMAINS)
+                i915_gem_flush_ring(obj->base.dev, NULL, obj->ring,
+                                    0, obj->base.write_domain);
+
+        return i915_gem_object_wait_rendering(&obj->base, interruptible);
+}
+
 /**
  * Moves a single object to the CPU read, and possibly write domain.
  *
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 48d8fd686ea9..bee24b1a58e8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1611,6 +1611,18 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 
                 wait_event(dev_priv->pending_flip_queue,
                            atomic_read(&obj_priv->pending_flip) == 0);
+
+                /* Big Hammer, we also need to ensure that any pending
+                 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
+                 * current scanout is retired before unpinning the old
+                 * framebuffer.
+                 */
+                ret = i915_gem_object_flush_gpu(obj_priv, false);
+                if (ret) {
+                        i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
+                        mutex_unlock(&dev->struct_mutex);
+                        return ret;
+                }
         }
 
         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,