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-rw-r--r--drivers/clk/versatile/clk-vexpress.c3
-rw-r--r--drivers/clocksource/nomadik-mtu.c11
-rw-r--r--drivers/cpufreq/Makefile2
-rw-r--r--drivers/cpufreq/dbx500-cpufreq.c (renamed from drivers/cpufreq/db8500-cpufreq.c)101
-rw-r--r--drivers/dma/coh901318.c1302
-rw-r--r--drivers/dma/coh901318.h (renamed from drivers/dma/coh901318_lli.h)35
-rw-r--r--drivers/dma/coh901318_lli.c4
-rw-r--r--drivers/mfd/db8500-prcmu.c4
-rw-r--r--drivers/mtd/nand/omap2.c4
-rw-r--r--drivers/mtd/onenand/omap2.c4
10 files changed, 1352 insertions, 118 deletions
diff --git a/drivers/clk/versatile/clk-vexpress.c b/drivers/clk/versatile/clk-vexpress.c
index f889f2f07b37..82b45aad8ccf 100644
--- a/drivers/clk/versatile/clk-vexpress.c
+++ b/drivers/clk/versatile/clk-vexpress.c
@@ -11,6 +11,7 @@
11 * Copyright (C) 2012 ARM Limited 11 * Copyright (C) 2012 ARM Limited
12 */ 12 */
13 13
14#include <linux/amba/sp810.h>
14#include <linux/clkdev.h> 15#include <linux/clkdev.h>
15#include <linux/clk-provider.h> 16#include <linux/clk-provider.h>
16#include <linux/err.h> 17#include <linux/err.h>
@@ -18,8 +19,6 @@
18#include <linux/of_address.h> 19#include <linux/of_address.h>
19#include <linux/vexpress.h> 20#include <linux/vexpress.h>
20 21
21#include <asm/hardware/sp810.h>
22
23static struct clk *vexpress_sp810_timerclken[4]; 22static struct clk *vexpress_sp810_timerclken[4];
24static DEFINE_SPINLOCK(vexpress_sp810_lock); 23static DEFINE_SPINLOCK(vexpress_sp810_lock);
25 24
diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c
index 025afc6dd324..435e54d55bbd 100644
--- a/drivers/clocksource/nomadik-mtu.c
+++ b/drivers/clocksource/nomadik-mtu.c
@@ -15,6 +15,7 @@
15#include <linux/clocksource.h> 15#include <linux/clocksource.h>
16#include <linux/clk.h> 16#include <linux/clk.h>
17#include <linux/jiffies.h> 17#include <linux/jiffies.h>
18#include <linux/delay.h>
18#include <linux/err.h> 19#include <linux/err.h>
19#include <linux/platform_data/clocksource-nomadik-mtu.h> 20#include <linux/platform_data/clocksource-nomadik-mtu.h>
20#include <asm/mach/time.h> 21#include <asm/mach/time.h>
@@ -64,6 +65,7 @@ static void __iomem *mtu_base;
64static bool clkevt_periodic; 65static bool clkevt_periodic;
65static u32 clk_prescale; 66static u32 clk_prescale;
66static u32 nmdk_cycle; /* write-once */ 67static u32 nmdk_cycle; /* write-once */
68static struct delay_timer mtu_delay_timer;
67 69
68#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK 70#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
69/* 71/*
@@ -80,6 +82,11 @@ static u32 notrace nomadik_read_sched_clock(void)
80} 82}
81#endif 83#endif
82 84
85static unsigned long nmdk_timer_read_current_timer(void)
86{
87 return ~readl_relaxed(mtu_base + MTU_VAL(0));
88}
89
83/* Clockevent device: use one-shot mode */ 90/* Clockevent device: use one-shot mode */
84static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev) 91static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
85{ 92{
@@ -234,4 +241,8 @@ void __init nmdk_timer_init(void __iomem *base, int irq)
234 setup_irq(irq, &nmdk_timer_irq); 241 setup_irq(irq, &nmdk_timer_irq);
235 nmdk_clkevt.cpumask = cpumask_of(0); 242 nmdk_clkevt.cpumask = cpumask_of(0);
236 clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU); 243 clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
244
245 mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
246 mtu_delay_timer.freq = rate;
247 register_current_timer_delay(&mtu_delay_timer);
237} 248}
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 5399c45ac311..863fd1865d45 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -44,7 +44,7 @@ obj-$(CONFIG_X86_INTEL_PSTATE) += intel_pstate.o
44 44
45################################################################################## 45##################################################################################
46# ARM SoC drivers 46# ARM SoC drivers
47obj-$(CONFIG_UX500_SOC_DB8500) += db8500-cpufreq.o 47obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o
48obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o 48obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o
49obj-$(CONFIG_ARM_S3C64XX_CPUFREQ) += s3c64xx-cpufreq.o 49obj-$(CONFIG_ARM_S3C64XX_CPUFREQ) += s3c64xx-cpufreq.o
50obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o 50obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o
diff --git a/drivers/cpufreq/db8500-cpufreq.c b/drivers/cpufreq/dbx500-cpufreq.c
index 48a1988149d8..72f0c3efa76e 100644
--- a/drivers/cpufreq/db8500-cpufreq.c
+++ b/drivers/cpufreq/dbx500-cpufreq.c
@@ -1,13 +1,13 @@
1/* 1/*
2 * Copyright (C) STMicroelectronics 2009 2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010 3 * Copyright (C) ST-Ericsson SA 2010-2012
4 * 4 *
5 * License Terms: GNU General Public License v2 5 * License Terms: GNU General Public License v2
6 * Author: Sundar Iyer <sundar.iyer@stericsson.com> 6 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
7 * Author: Martin Persson <martin.persson@stericsson.com> 7 * Author: Martin Persson <martin.persson@stericsson.com>
8 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> 8 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
9 *
10 */ 9 */
10
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/cpufreq.h> 13#include <linux/cpufreq.h>
@@ -19,22 +19,23 @@
19static struct cpufreq_frequency_table *freq_table; 19static struct cpufreq_frequency_table *freq_table;
20static struct clk *armss_clk; 20static struct clk *armss_clk;
21 21
22static struct freq_attr *db8500_cpufreq_attr[] = { 22static struct freq_attr *dbx500_cpufreq_attr[] = {
23 &cpufreq_freq_attr_scaling_available_freqs, 23 &cpufreq_freq_attr_scaling_available_freqs,
24 NULL, 24 NULL,
25}; 25};
26 26
27static int db8500_cpufreq_verify_speed(struct cpufreq_policy *policy) 27static int dbx500_cpufreq_verify_speed(struct cpufreq_policy *policy)
28{ 28{
29 return cpufreq_frequency_table_verify(policy, freq_table); 29 return cpufreq_frequency_table_verify(policy, freq_table);
30} 30}
31 31
32static int db8500_cpufreq_target(struct cpufreq_policy *policy, 32static int dbx500_cpufreq_target(struct cpufreq_policy *policy,
33 unsigned int target_freq, 33 unsigned int target_freq,
34 unsigned int relation) 34 unsigned int relation)
35{ 35{
36 struct cpufreq_freqs freqs; 36 struct cpufreq_freqs freqs;
37 unsigned int idx; 37 unsigned int idx;
38 int ret;
38 39
39 /* scale the target frequency to one of the extremes supported */ 40 /* scale the target frequency to one of the extremes supported */
40 if (target_freq < policy->cpuinfo.min_freq) 41 if (target_freq < policy->cpuinfo.min_freq)
@@ -43,10 +44,9 @@ static int db8500_cpufreq_target(struct cpufreq_policy *policy,
43 target_freq = policy->cpuinfo.max_freq; 44 target_freq = policy->cpuinfo.max_freq;
44 45
45 /* Lookup the next frequency */ 46 /* Lookup the next frequency */
46 if (cpufreq_frequency_table_target 47 if (cpufreq_frequency_table_target(policy, freq_table, target_freq,
47 (policy, freq_table, target_freq, relation, &idx)) { 48 relation, &idx))
48 return -EINVAL; 49 return -EINVAL;
49 }
50 50
51 freqs.old = policy->cur; 51 freqs.old = policy->cur;
52 freqs.new = freq_table[idx].frequency; 52 freqs.new = freq_table[idx].frequency;
@@ -59,9 +59,12 @@ static int db8500_cpufreq_target(struct cpufreq_policy *policy,
59 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 59 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
60 60
61 /* update armss clk frequency */ 61 /* update armss clk frequency */
62 if (clk_set_rate(armss_clk, freq_table[idx].frequency * 1000)) { 62 ret = clk_set_rate(armss_clk, freqs.new * 1000);
63 pr_err("db8500-cpufreq: Failed to update armss clk\n"); 63
64 return -EINVAL; 64 if (ret) {
65 pr_err("dbx500-cpufreq: Failed to set armss_clk to %d Hz: error %d\n",
66 freqs.new * 1000, ret);
67 return ret;
65 } 68 }
66 69
67 /* post change notification */ 70 /* post change notification */
@@ -71,7 +74,7 @@ static int db8500_cpufreq_target(struct cpufreq_policy *policy,
71 return 0; 74 return 0;
72} 75}
73 76
74static unsigned int db8500_cpufreq_getspeed(unsigned int cpu) 77static unsigned int dbx500_cpufreq_getspeed(unsigned int cpu)
75{ 78{
76 int i = 0; 79 int i = 0;
77 unsigned long freq = clk_get_rate(armss_clk) / 1000; 80 unsigned long freq = clk_get_rate(armss_clk) / 1000;
@@ -83,40 +86,26 @@ static unsigned int db8500_cpufreq_getspeed(unsigned int cpu)
83 } 86 }
84 87
85 /* We could not find a corresponding frequency. */ 88 /* We could not find a corresponding frequency. */
86 pr_err("db8500-cpufreq: Failed to find cpufreq speed\n"); 89 pr_err("dbx500-cpufreq: Failed to find cpufreq speed\n");
87 return 0; 90 return 0;
88} 91}
89 92
90static int __cpuinit db8500_cpufreq_init(struct cpufreq_policy *policy) 93static int __cpuinit dbx500_cpufreq_init(struct cpufreq_policy *policy)
91{ 94{
92 int i = 0;
93 int res; 95 int res;
94 96
95 armss_clk = clk_get(NULL, "armss");
96 if (IS_ERR(armss_clk)) {
97 pr_err("db8500-cpufreq : Failed to get armss clk\n");
98 return PTR_ERR(armss_clk);
99 }
100
101 pr_info("db8500-cpufreq : Available frequencies:\n");
102 while (freq_table[i].frequency != CPUFREQ_TABLE_END) {
103 pr_info(" %d Mhz\n", freq_table[i].frequency/1000);
104 i++;
105 }
106
107 /* get policy fields based on the table */ 97 /* get policy fields based on the table */
108 res = cpufreq_frequency_table_cpuinfo(policy, freq_table); 98 res = cpufreq_frequency_table_cpuinfo(policy, freq_table);
109 if (!res) 99 if (!res)
110 cpufreq_frequency_table_get_attr(freq_table, policy->cpu); 100 cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
111 else { 101 else {
112 pr_err("db8500-cpufreq : Failed to read policy table\n"); 102 pr_err("dbx500-cpufreq: Failed to read policy table\n");
113 clk_put(armss_clk);
114 return res; 103 return res;
115 } 104 }
116 105
117 policy->min = policy->cpuinfo.min_freq; 106 policy->min = policy->cpuinfo.min_freq;
118 policy->max = policy->cpuinfo.max_freq; 107 policy->max = policy->cpuinfo.max_freq;
119 policy->cur = db8500_cpufreq_getspeed(policy->cpu); 108 policy->cur = dbx500_cpufreq_getspeed(policy->cpu);
120 policy->governor = CPUFREQ_DEFAULT_GOVERNOR; 109 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
121 110
122 /* 111 /*
@@ -132,42 +121,54 @@ static int __cpuinit db8500_cpufreq_init(struct cpufreq_policy *policy)
132 return 0; 121 return 0;
133} 122}
134 123
135static struct cpufreq_driver db8500_cpufreq_driver = { 124static struct cpufreq_driver dbx500_cpufreq_driver = {
136 .flags = CPUFREQ_STICKY, 125 .flags = CPUFREQ_STICKY | CPUFREQ_CONST_LOOPS,
137 .verify = db8500_cpufreq_verify_speed, 126 .verify = dbx500_cpufreq_verify_speed,
138 .target = db8500_cpufreq_target, 127 .target = dbx500_cpufreq_target,
139 .get = db8500_cpufreq_getspeed, 128 .get = dbx500_cpufreq_getspeed,
140 .init = db8500_cpufreq_init, 129 .init = dbx500_cpufreq_init,
141 .name = "DB8500", 130 .name = "DBX500",
142 .attr = db8500_cpufreq_attr, 131 .attr = dbx500_cpufreq_attr,
143}; 132};
144 133
145static int db8500_cpufreq_probe(struct platform_device *pdev) 134static int dbx500_cpufreq_probe(struct platform_device *pdev)
146{ 135{
147 freq_table = dev_get_platdata(&pdev->dev); 136 int i = 0;
148 137
138 freq_table = dev_get_platdata(&pdev->dev);
149 if (!freq_table) { 139 if (!freq_table) {
150 pr_err("db8500-cpufreq: Failed to fetch cpufreq table\n"); 140 pr_err("dbx500-cpufreq: Failed to fetch cpufreq table\n");
151 return -ENODEV; 141 return -ENODEV;
152 } 142 }
153 143
154 return cpufreq_register_driver(&db8500_cpufreq_driver); 144 armss_clk = clk_get(&pdev->dev, "armss");
145 if (IS_ERR(armss_clk)) {
146 pr_err("dbx500-cpufreq: Failed to get armss clk\n");
147 return PTR_ERR(armss_clk);
148 }
149
150 pr_info("dbx500-cpufreq: Available frequencies:\n");
151 while (freq_table[i].frequency != CPUFREQ_TABLE_END) {
152 pr_info(" %d Mhz\n", freq_table[i].frequency/1000);
153 i++;
154 }
155
156 return cpufreq_register_driver(&dbx500_cpufreq_driver);
155} 157}
156 158
157static struct platform_driver db8500_cpufreq_plat_driver = { 159static struct platform_driver dbx500_cpufreq_plat_driver = {
158 .driver = { 160 .driver = {
159 .name = "cpufreq-u8500", 161 .name = "cpufreq-ux500",
160 .owner = THIS_MODULE, 162 .owner = THIS_MODULE,
161 }, 163 },
162 .probe = db8500_cpufreq_probe, 164 .probe = dbx500_cpufreq_probe,
163}; 165};
164 166
165static int __init db8500_cpufreq_register(void) 167static int __init dbx500_cpufreq_register(void)
166{ 168{
167 pr_info("cpufreq for DB8500 started\n"); 169 return platform_driver_register(&dbx500_cpufreq_plat_driver);
168 return platform_driver_register(&db8500_cpufreq_plat_driver);
169} 170}
170device_initcall(db8500_cpufreq_register); 171device_initcall(dbx500_cpufreq_register);
171 172
172MODULE_LICENSE("GPL v2"); 173MODULE_LICENSE("GPL v2");
173MODULE_DESCRIPTION("cpufreq driver for DB8500"); 174MODULE_DESCRIPTION("cpufreq driver for DBX500");
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index aa384e53b7ac..a2f079aca550 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -21,11 +21,1241 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/uaccess.h> 22#include <linux/uaccess.h>
23#include <linux/debugfs.h> 23#include <linux/debugfs.h>
24#include <mach/coh901318.h> 24#include <linux/platform_data/dma-coh901318.h>
25 25
26#include "coh901318_lli.h" 26#include "coh901318.h"
27#include "dmaengine.h" 27#include "dmaengine.h"
28 28
29#define COH901318_MOD32_MASK (0x1F)
30#define COH901318_WORD_MASK (0xFFFFFFFF)
31/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
32#define COH901318_INT_STATUS1 (0x0000)
33#define COH901318_INT_STATUS2 (0x0004)
34/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
35#define COH901318_TC_INT_STATUS1 (0x0008)
36#define COH901318_TC_INT_STATUS2 (0x000C)
37/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
38#define COH901318_TC_INT_CLEAR1 (0x0010)
39#define COH901318_TC_INT_CLEAR2 (0x0014)
40/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
41#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
42#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
43/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
44#define COH901318_BE_INT_STATUS1 (0x0020)
45#define COH901318_BE_INT_STATUS2 (0x0024)
46/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
47#define COH901318_BE_INT_CLEAR1 (0x0028)
48#define COH901318_BE_INT_CLEAR2 (0x002C)
49/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
50#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
51#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
52
53/*
54 * CX_CFG - Channel Configuration Registers 32bit (R/W)
55 */
56#define COH901318_CX_CFG (0x0100)
57#define COH901318_CX_CFG_SPACING (0x04)
58/* Channel enable activates tha dma job */
59#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
60#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
61/* Request Mode */
62#define COH901318_CX_CFG_RM_MASK (0x00000006)
63#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
64#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
65#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
66#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
67#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
68/* Linked channel request field. RM must == 11 */
69#define COH901318_CX_CFG_LCRF_SHIFT 3
70#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
71#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
72/* Terminal Counter Interrupt Request Mask */
73#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
74#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
75/* Bus Error interrupt Mask */
76#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
77#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
78
79/*
80 * CX_STAT - Channel Status Registers 32bit (R/-)
81 */
82#define COH901318_CX_STAT (0x0200)
83#define COH901318_CX_STAT_SPACING (0x04)
84#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
85#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
86#define COH901318_CX_STAT_ACTIVE (0x00000002)
87#define COH901318_CX_STAT_ENABLED (0x00000001)
88
89/*
90 * CX_CTRL - Channel Control Registers 32bit (R/W)
91 */
92#define COH901318_CX_CTRL (0x0400)
93#define COH901318_CX_CTRL_SPACING (0x10)
94/* Transfer Count Enable */
95#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
96#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
97/* Transfer Count Value 0 - 4095 */
98#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
99/* Burst count */
100#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
101#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
102#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
103#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
104#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
105#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
106#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
107#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
108#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
109/* Source bus size */
110#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
111#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
112#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
113#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
114/* Source address increment */
115#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
116#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
117/* Destination Bus Size */
118#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
119#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
120#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
121#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
122/* Destination address increment */
123#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
124#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
125/* Master Mode (Master2 is only connected to MSL) */
126#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
127#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
128#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
129#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
130#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
131/* Terminal Count flag to PER enable */
132#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
133#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
134/* Terminal Count flags to CPU enable */
135#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
136#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
137/* Hand shake to peripheral */
138#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
139#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
140#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
141#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
142/* DMA mode */
143#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
144#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
145#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
146#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
147/* Primary Request Data Destination */
148#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
149#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
150#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
151
152/*
153 * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
154 */
155#define COH901318_CX_SRC_ADDR (0x0404)
156#define COH901318_CX_SRC_ADDR_SPACING (0x10)
157
158/*
159 * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
160 */
161#define COH901318_CX_DST_ADDR (0x0408)
162#define COH901318_CX_DST_ADDR_SPACING (0x10)
163
164/*
165 * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
166 */
167#define COH901318_CX_LNK_ADDR (0x040C)
168#define COH901318_CX_LNK_ADDR_SPACING (0x10)
169#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
170
171/**
172 * struct coh901318_params - parameters for DMAC configuration
173 * @config: DMA config register
174 * @ctrl_lli_last: DMA control register for the last lli in the list
175 * @ctrl_lli: DMA control register for an lli
176 * @ctrl_lli_chained: DMA control register for a chained lli
177 */
178struct coh901318_params {
179 u32 config;
180 u32 ctrl_lli_last;
181 u32 ctrl_lli;
182 u32 ctrl_lli_chained;
183};
184
185/**
186 * struct coh_dma_channel - dma channel base
187 * @name: ascii name of dma channel
188 * @number: channel id number
189 * @desc_nbr_max: number of preallocated descriptors
190 * @priority_high: prio of channel, 0 low otherwise high.
191 * @param: configuration parameters
192 */
193struct coh_dma_channel {
194 const char name[32];
195 const int number;
196 const int desc_nbr_max;
197 const int priority_high;
198 const struct coh901318_params param;
199};
200
201/**
202 * struct powersave - DMA power save structure
203 * @lock: lock protecting data in this struct
204 * @started_channels: bit mask indicating active dma channels
205 */
206struct powersave {
207 spinlock_t lock;
208 u64 started_channels;
209};
210
211/* points out all dma slave channels.
212 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
213 * Select all channels from A to B, end of list is marked with -1,-1
214 */
215static int dma_slave_channels[] = {
216 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
217 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
218
219/* points out all dma memcpy channels. */
220static int dma_memcpy_channels[] = {
221 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
222
223#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
224 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
225 COH901318_CX_CFG_LCR_DISABLE | \
226 COH901318_CX_CFG_TC_IRQ_ENABLE | \
227 COH901318_CX_CFG_BE_IRQ_ENABLE)
228#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
229 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
230 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
231 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
232 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
233 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
234 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
235 COH901318_CX_CTRL_TCP_DISABLE | \
236 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
237 COH901318_CX_CTRL_HSP_DISABLE | \
238 COH901318_CX_CTRL_HSS_DISABLE | \
239 COH901318_CX_CTRL_DDMA_LEGACY | \
240 COH901318_CX_CTRL_PRDD_SOURCE)
241#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
242 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
243 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
244 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
245 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
246 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
247 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
248 COH901318_CX_CTRL_TCP_DISABLE | \
249 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
250 COH901318_CX_CTRL_HSP_DISABLE | \
251 COH901318_CX_CTRL_HSS_DISABLE | \
252 COH901318_CX_CTRL_DDMA_LEGACY | \
253 COH901318_CX_CTRL_PRDD_SOURCE)
254#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
255 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
256 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
257 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
258 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
259 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
260 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
261 COH901318_CX_CTRL_TCP_DISABLE | \
262 COH901318_CX_CTRL_TC_IRQ_ENABLE | \
263 COH901318_CX_CTRL_HSP_DISABLE | \
264 COH901318_CX_CTRL_HSS_DISABLE | \
265 COH901318_CX_CTRL_DDMA_LEGACY | \
266 COH901318_CX_CTRL_PRDD_SOURCE)
267
268const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
269 {
270 .number = U300_DMA_MSL_TX_0,
271 .name = "MSL TX 0",
272 .priority_high = 0,
273 },
274 {
275 .number = U300_DMA_MSL_TX_1,
276 .name = "MSL TX 1",
277 .priority_high = 0,
278 .param.config = COH901318_CX_CFG_CH_DISABLE |
279 COH901318_CX_CFG_LCR_DISABLE |
280 COH901318_CX_CFG_TC_IRQ_ENABLE |
281 COH901318_CX_CFG_BE_IRQ_ENABLE,
282 .param.ctrl_lli_chained = 0 |
283 COH901318_CX_CTRL_TC_ENABLE |
284 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
285 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
286 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
287 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
288 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
289 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
290 COH901318_CX_CTRL_TCP_DISABLE |
291 COH901318_CX_CTRL_TC_IRQ_DISABLE |
292 COH901318_CX_CTRL_HSP_ENABLE |
293 COH901318_CX_CTRL_HSS_DISABLE |
294 COH901318_CX_CTRL_DDMA_LEGACY |
295 COH901318_CX_CTRL_PRDD_SOURCE,
296 .param.ctrl_lli = 0 |
297 COH901318_CX_CTRL_TC_ENABLE |
298 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
299 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
300 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
301 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
302 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
303 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
304 COH901318_CX_CTRL_TCP_ENABLE |
305 COH901318_CX_CTRL_TC_IRQ_DISABLE |
306 COH901318_CX_CTRL_HSP_ENABLE |
307 COH901318_CX_CTRL_HSS_DISABLE |
308 COH901318_CX_CTRL_DDMA_LEGACY |
309 COH901318_CX_CTRL_PRDD_SOURCE,
310 .param.ctrl_lli_last = 0 |
311 COH901318_CX_CTRL_TC_ENABLE |
312 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
313 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
314 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
315 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
316 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
317 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
318 COH901318_CX_CTRL_TCP_ENABLE |
319 COH901318_CX_CTRL_TC_IRQ_ENABLE |
320 COH901318_CX_CTRL_HSP_ENABLE |
321 COH901318_CX_CTRL_HSS_DISABLE |
322 COH901318_CX_CTRL_DDMA_LEGACY |
323 COH901318_CX_CTRL_PRDD_SOURCE,
324 },
325 {
326 .number = U300_DMA_MSL_TX_2,
327 .name = "MSL TX 2",
328 .priority_high = 0,
329 .param.config = COH901318_CX_CFG_CH_DISABLE |
330 COH901318_CX_CFG_LCR_DISABLE |
331 COH901318_CX_CFG_TC_IRQ_ENABLE |
332 COH901318_CX_CFG_BE_IRQ_ENABLE,
333 .param.ctrl_lli_chained = 0 |
334 COH901318_CX_CTRL_TC_ENABLE |
335 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
336 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
337 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
338 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
339 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
340 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
341 COH901318_CX_CTRL_TCP_DISABLE |
342 COH901318_CX_CTRL_TC_IRQ_DISABLE |
343 COH901318_CX_CTRL_HSP_ENABLE |
344 COH901318_CX_CTRL_HSS_DISABLE |
345 COH901318_CX_CTRL_DDMA_LEGACY |
346 COH901318_CX_CTRL_PRDD_SOURCE,
347 .param.ctrl_lli = 0 |
348 COH901318_CX_CTRL_TC_ENABLE |
349 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
350 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
351 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
352 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
353 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
354 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
355 COH901318_CX_CTRL_TCP_ENABLE |
356 COH901318_CX_CTRL_TC_IRQ_DISABLE |
357 COH901318_CX_CTRL_HSP_ENABLE |
358 COH901318_CX_CTRL_HSS_DISABLE |
359 COH901318_CX_CTRL_DDMA_LEGACY |
360 COH901318_CX_CTRL_PRDD_SOURCE,
361 .param.ctrl_lli_last = 0 |
362 COH901318_CX_CTRL_TC_ENABLE |
363 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
364 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
365 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
366 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
367 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
368 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
369 COH901318_CX_CTRL_TCP_ENABLE |
370 COH901318_CX_CTRL_TC_IRQ_ENABLE |
371 COH901318_CX_CTRL_HSP_ENABLE |
372 COH901318_CX_CTRL_HSS_DISABLE |
373 COH901318_CX_CTRL_DDMA_LEGACY |
374 COH901318_CX_CTRL_PRDD_SOURCE,
375 .desc_nbr_max = 10,
376 },
377 {
378 .number = U300_DMA_MSL_TX_3,
379 .name = "MSL TX 3",
380 .priority_high = 0,
381 .param.config = COH901318_CX_CFG_CH_DISABLE |
382 COH901318_CX_CFG_LCR_DISABLE |
383 COH901318_CX_CFG_TC_IRQ_ENABLE |
384 COH901318_CX_CFG_BE_IRQ_ENABLE,
385 .param.ctrl_lli_chained = 0 |
386 COH901318_CX_CTRL_TC_ENABLE |
387 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
388 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
389 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
390 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
391 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
392 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
393 COH901318_CX_CTRL_TCP_DISABLE |
394 COH901318_CX_CTRL_TC_IRQ_DISABLE |
395 COH901318_CX_CTRL_HSP_ENABLE |
396 COH901318_CX_CTRL_HSS_DISABLE |
397 COH901318_CX_CTRL_DDMA_LEGACY |
398 COH901318_CX_CTRL_PRDD_SOURCE,
399 .param.ctrl_lli = 0 |
400 COH901318_CX_CTRL_TC_ENABLE |
401 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
402 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
403 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
404 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
405 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
406 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
407 COH901318_CX_CTRL_TCP_ENABLE |
408 COH901318_CX_CTRL_TC_IRQ_DISABLE |
409 COH901318_CX_CTRL_HSP_ENABLE |
410 COH901318_CX_CTRL_HSS_DISABLE |
411 COH901318_CX_CTRL_DDMA_LEGACY |
412 COH901318_CX_CTRL_PRDD_SOURCE,
413 .param.ctrl_lli_last = 0 |
414 COH901318_CX_CTRL_TC_ENABLE |
415 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
416 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
417 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
418 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
419 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
420 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
421 COH901318_CX_CTRL_TCP_ENABLE |
422 COH901318_CX_CTRL_TC_IRQ_ENABLE |
423 COH901318_CX_CTRL_HSP_ENABLE |
424 COH901318_CX_CTRL_HSS_DISABLE |
425 COH901318_CX_CTRL_DDMA_LEGACY |
426 COH901318_CX_CTRL_PRDD_SOURCE,
427 },
428 {
429 .number = U300_DMA_MSL_TX_4,
430 .name = "MSL TX 4",
431 .priority_high = 0,
432 .param.config = COH901318_CX_CFG_CH_DISABLE |
433 COH901318_CX_CFG_LCR_DISABLE |
434 COH901318_CX_CFG_TC_IRQ_ENABLE |
435 COH901318_CX_CFG_BE_IRQ_ENABLE,
436 .param.ctrl_lli_chained = 0 |
437 COH901318_CX_CTRL_TC_ENABLE |
438 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
439 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
440 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
441 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
442 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
443 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
444 COH901318_CX_CTRL_TCP_DISABLE |
445 COH901318_CX_CTRL_TC_IRQ_DISABLE |
446 COH901318_CX_CTRL_HSP_ENABLE |
447 COH901318_CX_CTRL_HSS_DISABLE |
448 COH901318_CX_CTRL_DDMA_LEGACY |
449 COH901318_CX_CTRL_PRDD_SOURCE,
450 .param.ctrl_lli = 0 |
451 COH901318_CX_CTRL_TC_ENABLE |
452 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
453 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
454 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
455 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
456 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
457 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
458 COH901318_CX_CTRL_TCP_ENABLE |
459 COH901318_CX_CTRL_TC_IRQ_DISABLE |
460 COH901318_CX_CTRL_HSP_ENABLE |
461 COH901318_CX_CTRL_HSS_DISABLE |
462 COH901318_CX_CTRL_DDMA_LEGACY |
463 COH901318_CX_CTRL_PRDD_SOURCE,
464 .param.ctrl_lli_last = 0 |
465 COH901318_CX_CTRL_TC_ENABLE |
466 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
467 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
468 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
469 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
470 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
471 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
472 COH901318_CX_CTRL_TCP_ENABLE |
473 COH901318_CX_CTRL_TC_IRQ_ENABLE |
474 COH901318_CX_CTRL_HSP_ENABLE |
475 COH901318_CX_CTRL_HSS_DISABLE |
476 COH901318_CX_CTRL_DDMA_LEGACY |
477 COH901318_CX_CTRL_PRDD_SOURCE,
478 },
479 {
480 .number = U300_DMA_MSL_TX_5,
481 .name = "MSL TX 5",
482 .priority_high = 0,
483 },
484 {
485 .number = U300_DMA_MSL_TX_6,
486 .name = "MSL TX 6",
487 .priority_high = 0,
488 },
489 {
490 .number = U300_DMA_MSL_RX_0,
491 .name = "MSL RX 0",
492 .priority_high = 0,
493 },
494 {
495 .number = U300_DMA_MSL_RX_1,
496 .name = "MSL RX 1",
497 .priority_high = 0,
498 .param.config = COH901318_CX_CFG_CH_DISABLE |
499 COH901318_CX_CFG_LCR_DISABLE |
500 COH901318_CX_CFG_TC_IRQ_ENABLE |
501 COH901318_CX_CFG_BE_IRQ_ENABLE,
502 .param.ctrl_lli_chained = 0 |
503 COH901318_CX_CTRL_TC_ENABLE |
504 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
505 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
506 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
507 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
508 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
509 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
510 COH901318_CX_CTRL_TCP_DISABLE |
511 COH901318_CX_CTRL_TC_IRQ_DISABLE |
512 COH901318_CX_CTRL_HSP_ENABLE |
513 COH901318_CX_CTRL_HSS_DISABLE |
514 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
515 COH901318_CX_CTRL_PRDD_DEST,
516 .param.ctrl_lli = 0,
517 .param.ctrl_lli_last = 0 |
518 COH901318_CX_CTRL_TC_ENABLE |
519 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
520 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
521 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
522 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
523 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
524 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
525 COH901318_CX_CTRL_TCP_DISABLE |
526 COH901318_CX_CTRL_TC_IRQ_ENABLE |
527 COH901318_CX_CTRL_HSP_ENABLE |
528 COH901318_CX_CTRL_HSS_DISABLE |
529 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
530 COH901318_CX_CTRL_PRDD_DEST,
531 },
532 {
533 .number = U300_DMA_MSL_RX_2,
534 .name = "MSL RX 2",
535 .priority_high = 0,
536 .param.config = COH901318_CX_CFG_CH_DISABLE |
537 COH901318_CX_CFG_LCR_DISABLE |
538 COH901318_CX_CFG_TC_IRQ_ENABLE |
539 COH901318_CX_CFG_BE_IRQ_ENABLE,
540 .param.ctrl_lli_chained = 0 |
541 COH901318_CX_CTRL_TC_ENABLE |
542 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
543 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
544 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
545 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
546 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
547 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
548 COH901318_CX_CTRL_TCP_DISABLE |
549 COH901318_CX_CTRL_TC_IRQ_DISABLE |
550 COH901318_CX_CTRL_HSP_ENABLE |
551 COH901318_CX_CTRL_HSS_DISABLE |
552 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
553 COH901318_CX_CTRL_PRDD_DEST,
554 .param.ctrl_lli = 0 |
555 COH901318_CX_CTRL_TC_ENABLE |
556 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
557 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
558 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
559 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
560 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
561 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
562 COH901318_CX_CTRL_TCP_DISABLE |
563 COH901318_CX_CTRL_TC_IRQ_ENABLE |
564 COH901318_CX_CTRL_HSP_ENABLE |
565 COH901318_CX_CTRL_HSS_DISABLE |
566 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
567 COH901318_CX_CTRL_PRDD_DEST,
568 .param.ctrl_lli_last = 0 |
569 COH901318_CX_CTRL_TC_ENABLE |
570 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
571 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
572 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
573 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
574 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
575 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
576 COH901318_CX_CTRL_TCP_DISABLE |
577 COH901318_CX_CTRL_TC_IRQ_ENABLE |
578 COH901318_CX_CTRL_HSP_ENABLE |
579 COH901318_CX_CTRL_HSS_DISABLE |
580 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
581 COH901318_CX_CTRL_PRDD_DEST,
582 },
583 {
584 .number = U300_DMA_MSL_RX_3,
585 .name = "MSL RX 3",
586 .priority_high = 0,
587 .param.config = COH901318_CX_CFG_CH_DISABLE |
588 COH901318_CX_CFG_LCR_DISABLE |
589 COH901318_CX_CFG_TC_IRQ_ENABLE |
590 COH901318_CX_CFG_BE_IRQ_ENABLE,
591 .param.ctrl_lli_chained = 0 |
592 COH901318_CX_CTRL_TC_ENABLE |
593 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
594 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
595 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
596 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
597 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
598 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
599 COH901318_CX_CTRL_TCP_DISABLE |
600 COH901318_CX_CTRL_TC_IRQ_DISABLE |
601 COH901318_CX_CTRL_HSP_ENABLE |
602 COH901318_CX_CTRL_HSS_DISABLE |
603 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
604 COH901318_CX_CTRL_PRDD_DEST,
605 .param.ctrl_lli = 0 |
606 COH901318_CX_CTRL_TC_ENABLE |
607 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
608 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
609 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
610 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
611 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
612 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
613 COH901318_CX_CTRL_TCP_DISABLE |
614 COH901318_CX_CTRL_TC_IRQ_ENABLE |
615 COH901318_CX_CTRL_HSP_ENABLE |
616 COH901318_CX_CTRL_HSS_DISABLE |
617 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
618 COH901318_CX_CTRL_PRDD_DEST,
619 .param.ctrl_lli_last = 0 |
620 COH901318_CX_CTRL_TC_ENABLE |
621 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
622 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
623 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
624 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
625 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
626 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
627 COH901318_CX_CTRL_TCP_DISABLE |
628 COH901318_CX_CTRL_TC_IRQ_ENABLE |
629 COH901318_CX_CTRL_HSP_ENABLE |
630 COH901318_CX_CTRL_HSS_DISABLE |
631 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
632 COH901318_CX_CTRL_PRDD_DEST,
633 },
634 {
635 .number = U300_DMA_MSL_RX_4,
636 .name = "MSL RX 4",
637 .priority_high = 0,
638 .param.config = COH901318_CX_CFG_CH_DISABLE |
639 COH901318_CX_CFG_LCR_DISABLE |
640 COH901318_CX_CFG_TC_IRQ_ENABLE |
641 COH901318_CX_CFG_BE_IRQ_ENABLE,
642 .param.ctrl_lli_chained = 0 |
643 COH901318_CX_CTRL_TC_ENABLE |
644 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
645 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
646 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
647 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
648 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
649 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
650 COH901318_CX_CTRL_TCP_DISABLE |
651 COH901318_CX_CTRL_TC_IRQ_DISABLE |
652 COH901318_CX_CTRL_HSP_ENABLE |
653 COH901318_CX_CTRL_HSS_DISABLE |
654 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
655 COH901318_CX_CTRL_PRDD_DEST,
656 .param.ctrl_lli = 0 |
657 COH901318_CX_CTRL_TC_ENABLE |
658 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
659 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
660 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
661 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
662 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
663 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
664 COH901318_CX_CTRL_TCP_DISABLE |
665 COH901318_CX_CTRL_TC_IRQ_ENABLE |
666 COH901318_CX_CTRL_HSP_ENABLE |
667 COH901318_CX_CTRL_HSS_DISABLE |
668 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
669 COH901318_CX_CTRL_PRDD_DEST,
670 .param.ctrl_lli_last = 0 |
671 COH901318_CX_CTRL_TC_ENABLE |
672 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
673 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
674 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
675 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
676 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
677 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
678 COH901318_CX_CTRL_TCP_DISABLE |
679 COH901318_CX_CTRL_TC_IRQ_ENABLE |
680 COH901318_CX_CTRL_HSP_ENABLE |
681 COH901318_CX_CTRL_HSS_DISABLE |
682 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
683 COH901318_CX_CTRL_PRDD_DEST,
684 },
685 {
686 .number = U300_DMA_MSL_RX_5,
687 .name = "MSL RX 5",
688 .priority_high = 0,
689 .param.config = COH901318_CX_CFG_CH_DISABLE |
690 COH901318_CX_CFG_LCR_DISABLE |
691 COH901318_CX_CFG_TC_IRQ_ENABLE |
692 COH901318_CX_CFG_BE_IRQ_ENABLE,
693 .param.ctrl_lli_chained = 0 |
694 COH901318_CX_CTRL_TC_ENABLE |
695 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
696 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
697 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
698 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
699 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
700 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
701 COH901318_CX_CTRL_TCP_DISABLE |
702 COH901318_CX_CTRL_TC_IRQ_DISABLE |
703 COH901318_CX_CTRL_HSP_ENABLE |
704 COH901318_CX_CTRL_HSS_DISABLE |
705 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
706 COH901318_CX_CTRL_PRDD_DEST,
707 .param.ctrl_lli = 0 |
708 COH901318_CX_CTRL_TC_ENABLE |
709 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
710 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
711 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
712 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
713 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
714 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
715 COH901318_CX_CTRL_TCP_DISABLE |
716 COH901318_CX_CTRL_TC_IRQ_ENABLE |
717 COH901318_CX_CTRL_HSP_ENABLE |
718 COH901318_CX_CTRL_HSS_DISABLE |
719 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
720 COH901318_CX_CTRL_PRDD_DEST,
721 .param.ctrl_lli_last = 0 |
722 COH901318_CX_CTRL_TC_ENABLE |
723 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
724 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
725 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
726 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
727 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
728 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
729 COH901318_CX_CTRL_TCP_DISABLE |
730 COH901318_CX_CTRL_TC_IRQ_ENABLE |
731 COH901318_CX_CTRL_HSP_ENABLE |
732 COH901318_CX_CTRL_HSS_DISABLE |
733 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
734 COH901318_CX_CTRL_PRDD_DEST,
735 },
736 {
737 .number = U300_DMA_MSL_RX_6,
738 .name = "MSL RX 6",
739 .priority_high = 0,
740 },
741 /*
742 * Don't set up device address, burst count or size of src
743 * or dst bus for this peripheral - handled by PrimeCell
744 * DMA extension.
745 */
746 {
747 .number = U300_DMA_MMCSD_RX_TX,
748 .name = "MMCSD RX TX",
749 .priority_high = 0,
750 .param.config = COH901318_CX_CFG_CH_DISABLE |
751 COH901318_CX_CFG_LCR_DISABLE |
752 COH901318_CX_CFG_TC_IRQ_ENABLE |
753 COH901318_CX_CFG_BE_IRQ_ENABLE,
754 .param.ctrl_lli_chained = 0 |
755 COH901318_CX_CTRL_TC_ENABLE |
756 COH901318_CX_CTRL_MASTER_MODE_M1RW |
757 COH901318_CX_CTRL_TCP_ENABLE |
758 COH901318_CX_CTRL_TC_IRQ_DISABLE |
759 COH901318_CX_CTRL_HSP_ENABLE |
760 COH901318_CX_CTRL_HSS_DISABLE |
761 COH901318_CX_CTRL_DDMA_LEGACY,
762 .param.ctrl_lli = 0 |
763 COH901318_CX_CTRL_TC_ENABLE |
764 COH901318_CX_CTRL_MASTER_MODE_M1RW |
765 COH901318_CX_CTRL_TCP_ENABLE |
766 COH901318_CX_CTRL_TC_IRQ_DISABLE |
767 COH901318_CX_CTRL_HSP_ENABLE |
768 COH901318_CX_CTRL_HSS_DISABLE |
769 COH901318_CX_CTRL_DDMA_LEGACY,
770 .param.ctrl_lli_last = 0 |
771 COH901318_CX_CTRL_TC_ENABLE |
772 COH901318_CX_CTRL_MASTER_MODE_M1RW |
773 COH901318_CX_CTRL_TCP_DISABLE |
774 COH901318_CX_CTRL_TC_IRQ_ENABLE |
775 COH901318_CX_CTRL_HSP_ENABLE |
776 COH901318_CX_CTRL_HSS_DISABLE |
777 COH901318_CX_CTRL_DDMA_LEGACY,
778
779 },
780 {
781 .number = U300_DMA_MSPRO_TX,
782 .name = "MSPRO TX",
783 .priority_high = 0,
784 },
785 {
786 .number = U300_DMA_MSPRO_RX,
787 .name = "MSPRO RX",
788 .priority_high = 0,
789 },
790 /*
791 * Don't set up device address, burst count or size of src
792 * or dst bus for this peripheral - handled by PrimeCell
793 * DMA extension.
794 */
795 {
796 .number = U300_DMA_UART0_TX,
797 .name = "UART0 TX",
798 .priority_high = 0,
799 .param.config = COH901318_CX_CFG_CH_DISABLE |
800 COH901318_CX_CFG_LCR_DISABLE |
801 COH901318_CX_CFG_TC_IRQ_ENABLE |
802 COH901318_CX_CFG_BE_IRQ_ENABLE,
803 .param.ctrl_lli_chained = 0 |
804 COH901318_CX_CTRL_TC_ENABLE |
805 COH901318_CX_CTRL_MASTER_MODE_M1RW |
806 COH901318_CX_CTRL_TCP_ENABLE |
807 COH901318_CX_CTRL_TC_IRQ_DISABLE |
808 COH901318_CX_CTRL_HSP_ENABLE |
809 COH901318_CX_CTRL_HSS_DISABLE |
810 COH901318_CX_CTRL_DDMA_LEGACY,
811 .param.ctrl_lli = 0 |
812 COH901318_CX_CTRL_TC_ENABLE |
813 COH901318_CX_CTRL_MASTER_MODE_M1RW |
814 COH901318_CX_CTRL_TCP_ENABLE |
815 COH901318_CX_CTRL_TC_IRQ_ENABLE |
816 COH901318_CX_CTRL_HSP_ENABLE |
817 COH901318_CX_CTRL_HSS_DISABLE |
818 COH901318_CX_CTRL_DDMA_LEGACY,
819 .param.ctrl_lli_last = 0 |
820 COH901318_CX_CTRL_TC_ENABLE |
821 COH901318_CX_CTRL_MASTER_MODE_M1RW |
822 COH901318_CX_CTRL_TCP_ENABLE |
823 COH901318_CX_CTRL_TC_IRQ_ENABLE |
824 COH901318_CX_CTRL_HSP_ENABLE |
825 COH901318_CX_CTRL_HSS_DISABLE |
826 COH901318_CX_CTRL_DDMA_LEGACY,
827 },
828 {
829 .number = U300_DMA_UART0_RX,
830 .name = "UART0 RX",
831 .priority_high = 0,
832 .param.config = COH901318_CX_CFG_CH_DISABLE |
833 COH901318_CX_CFG_LCR_DISABLE |
834 COH901318_CX_CFG_TC_IRQ_ENABLE |
835 COH901318_CX_CFG_BE_IRQ_ENABLE,
836 .param.ctrl_lli_chained = 0 |
837 COH901318_CX_CTRL_TC_ENABLE |
838 COH901318_CX_CTRL_MASTER_MODE_M1RW |
839 COH901318_CX_CTRL_TCP_ENABLE |
840 COH901318_CX_CTRL_TC_IRQ_DISABLE |
841 COH901318_CX_CTRL_HSP_ENABLE |
842 COH901318_CX_CTRL_HSS_DISABLE |
843 COH901318_CX_CTRL_DDMA_LEGACY,
844 .param.ctrl_lli = 0 |
845 COH901318_CX_CTRL_TC_ENABLE |
846 COH901318_CX_CTRL_MASTER_MODE_M1RW |
847 COH901318_CX_CTRL_TCP_ENABLE |
848 COH901318_CX_CTRL_TC_IRQ_ENABLE |
849 COH901318_CX_CTRL_HSP_ENABLE |
850 COH901318_CX_CTRL_HSS_DISABLE |
851 COH901318_CX_CTRL_DDMA_LEGACY,
852 .param.ctrl_lli_last = 0 |
853 COH901318_CX_CTRL_TC_ENABLE |
854 COH901318_CX_CTRL_MASTER_MODE_M1RW |
855 COH901318_CX_CTRL_TCP_ENABLE |
856 COH901318_CX_CTRL_TC_IRQ_ENABLE |
857 COH901318_CX_CTRL_HSP_ENABLE |
858 COH901318_CX_CTRL_HSS_DISABLE |
859 COH901318_CX_CTRL_DDMA_LEGACY,
860 },
861 {
862 .number = U300_DMA_APEX_TX,
863 .name = "APEX TX",
864 .priority_high = 0,
865 },
866 {
867 .number = U300_DMA_APEX_RX,
868 .name = "APEX RX",
869 .priority_high = 0,
870 },
871 {
872 .number = U300_DMA_PCM_I2S0_TX,
873 .name = "PCM I2S0 TX",
874 .priority_high = 1,
875 .param.config = COH901318_CX_CFG_CH_DISABLE |
876 COH901318_CX_CFG_LCR_DISABLE |
877 COH901318_CX_CFG_TC_IRQ_ENABLE |
878 COH901318_CX_CFG_BE_IRQ_ENABLE,
879 .param.ctrl_lli_chained = 0 |
880 COH901318_CX_CTRL_TC_ENABLE |
881 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
882 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
883 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
884 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
885 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
886 COH901318_CX_CTRL_MASTER_MODE_M1RW |
887 COH901318_CX_CTRL_TCP_DISABLE |
888 COH901318_CX_CTRL_TC_IRQ_DISABLE |
889 COH901318_CX_CTRL_HSP_ENABLE |
890 COH901318_CX_CTRL_HSS_DISABLE |
891 COH901318_CX_CTRL_DDMA_LEGACY |
892 COH901318_CX_CTRL_PRDD_SOURCE,
893 .param.ctrl_lli = 0 |
894 COH901318_CX_CTRL_TC_ENABLE |
895 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
896 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
897 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
898 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
899 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
900 COH901318_CX_CTRL_MASTER_MODE_M1RW |
901 COH901318_CX_CTRL_TCP_ENABLE |
902 COH901318_CX_CTRL_TC_IRQ_DISABLE |
903 COH901318_CX_CTRL_HSP_ENABLE |
904 COH901318_CX_CTRL_HSS_DISABLE |
905 COH901318_CX_CTRL_DDMA_LEGACY |
906 COH901318_CX_CTRL_PRDD_SOURCE,
907 .param.ctrl_lli_last = 0 |
908 COH901318_CX_CTRL_TC_ENABLE |
909 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
910 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
911 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
912 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
913 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
914 COH901318_CX_CTRL_MASTER_MODE_M1RW |
915 COH901318_CX_CTRL_TCP_ENABLE |
916 COH901318_CX_CTRL_TC_IRQ_DISABLE |
917 COH901318_CX_CTRL_HSP_ENABLE |
918 COH901318_CX_CTRL_HSS_DISABLE |
919 COH901318_CX_CTRL_DDMA_LEGACY |
920 COH901318_CX_CTRL_PRDD_SOURCE,
921 },
922 {
923 .number = U300_DMA_PCM_I2S0_RX,
924 .name = "PCM I2S0 RX",
925 .priority_high = 1,
926 .param.config = COH901318_CX_CFG_CH_DISABLE |
927 COH901318_CX_CFG_LCR_DISABLE |
928 COH901318_CX_CFG_TC_IRQ_ENABLE |
929 COH901318_CX_CFG_BE_IRQ_ENABLE,
930 .param.ctrl_lli_chained = 0 |
931 COH901318_CX_CTRL_TC_ENABLE |
932 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
933 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
934 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
935 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
936 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
937 COH901318_CX_CTRL_MASTER_MODE_M1RW |
938 COH901318_CX_CTRL_TCP_DISABLE |
939 COH901318_CX_CTRL_TC_IRQ_DISABLE |
940 COH901318_CX_CTRL_HSP_ENABLE |
941 COH901318_CX_CTRL_HSS_DISABLE |
942 COH901318_CX_CTRL_DDMA_LEGACY |
943 COH901318_CX_CTRL_PRDD_DEST,
944 .param.ctrl_lli = 0 |
945 COH901318_CX_CTRL_TC_ENABLE |
946 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
947 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
948 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
949 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
950 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
951 COH901318_CX_CTRL_MASTER_MODE_M1RW |
952 COH901318_CX_CTRL_TCP_ENABLE |
953 COH901318_CX_CTRL_TC_IRQ_DISABLE |
954 COH901318_CX_CTRL_HSP_ENABLE |
955 COH901318_CX_CTRL_HSS_DISABLE |
956 COH901318_CX_CTRL_DDMA_LEGACY |
957 COH901318_CX_CTRL_PRDD_DEST,
958 .param.ctrl_lli_last = 0 |
959 COH901318_CX_CTRL_TC_ENABLE |
960 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
961 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
962 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
963 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
964 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
965 COH901318_CX_CTRL_MASTER_MODE_M1RW |
966 COH901318_CX_CTRL_TCP_ENABLE |
967 COH901318_CX_CTRL_TC_IRQ_ENABLE |
968 COH901318_CX_CTRL_HSP_ENABLE |
969 COH901318_CX_CTRL_HSS_DISABLE |
970 COH901318_CX_CTRL_DDMA_LEGACY |
971 COH901318_CX_CTRL_PRDD_DEST,
972 },
973 {
974 .number = U300_DMA_PCM_I2S1_TX,
975 .name = "PCM I2S1 TX",
976 .priority_high = 1,
977 .param.config = COH901318_CX_CFG_CH_DISABLE |
978 COH901318_CX_CFG_LCR_DISABLE |
979 COH901318_CX_CFG_TC_IRQ_ENABLE |
980 COH901318_CX_CFG_BE_IRQ_ENABLE,
981 .param.ctrl_lli_chained = 0 |
982 COH901318_CX_CTRL_TC_ENABLE |
983 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
984 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
985 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
986 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
987 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
988 COH901318_CX_CTRL_MASTER_MODE_M1RW |
989 COH901318_CX_CTRL_TCP_DISABLE |
990 COH901318_CX_CTRL_TC_IRQ_DISABLE |
991 COH901318_CX_CTRL_HSP_ENABLE |
992 COH901318_CX_CTRL_HSS_DISABLE |
993 COH901318_CX_CTRL_DDMA_LEGACY |
994 COH901318_CX_CTRL_PRDD_SOURCE,
995 .param.ctrl_lli = 0 |
996 COH901318_CX_CTRL_TC_ENABLE |
997 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
998 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
999 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1000 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1001 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1002 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1003 COH901318_CX_CTRL_TCP_ENABLE |
1004 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1005 COH901318_CX_CTRL_HSP_ENABLE |
1006 COH901318_CX_CTRL_HSS_DISABLE |
1007 COH901318_CX_CTRL_DDMA_LEGACY |
1008 COH901318_CX_CTRL_PRDD_SOURCE,
1009 .param.ctrl_lli_last = 0 |
1010 COH901318_CX_CTRL_TC_ENABLE |
1011 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1012 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1013 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1014 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1015 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1016 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1017 COH901318_CX_CTRL_TCP_ENABLE |
1018 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1019 COH901318_CX_CTRL_HSP_ENABLE |
1020 COH901318_CX_CTRL_HSS_DISABLE |
1021 COH901318_CX_CTRL_DDMA_LEGACY |
1022 COH901318_CX_CTRL_PRDD_SOURCE,
1023 },
1024 {
1025 .number = U300_DMA_PCM_I2S1_RX,
1026 .name = "PCM I2S1 RX",
1027 .priority_high = 1,
1028 .param.config = COH901318_CX_CFG_CH_DISABLE |
1029 COH901318_CX_CFG_LCR_DISABLE |
1030 COH901318_CX_CFG_TC_IRQ_ENABLE |
1031 COH901318_CX_CFG_BE_IRQ_ENABLE,
1032 .param.ctrl_lli_chained = 0 |
1033 COH901318_CX_CTRL_TC_ENABLE |
1034 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1035 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1036 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1037 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1038 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1039 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1040 COH901318_CX_CTRL_TCP_DISABLE |
1041 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1042 COH901318_CX_CTRL_HSP_ENABLE |
1043 COH901318_CX_CTRL_HSS_DISABLE |
1044 COH901318_CX_CTRL_DDMA_LEGACY |
1045 COH901318_CX_CTRL_PRDD_DEST,
1046 .param.ctrl_lli = 0 |
1047 COH901318_CX_CTRL_TC_ENABLE |
1048 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1049 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1050 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1051 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1052 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1053 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1054 COH901318_CX_CTRL_TCP_ENABLE |
1055 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1056 COH901318_CX_CTRL_HSP_ENABLE |
1057 COH901318_CX_CTRL_HSS_DISABLE |
1058 COH901318_CX_CTRL_DDMA_LEGACY |
1059 COH901318_CX_CTRL_PRDD_DEST,
1060 .param.ctrl_lli_last = 0 |
1061 COH901318_CX_CTRL_TC_ENABLE |
1062 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1063 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1064 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1065 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1066 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1067 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1068 COH901318_CX_CTRL_TCP_ENABLE |
1069 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1070 COH901318_CX_CTRL_HSP_ENABLE |
1071 COH901318_CX_CTRL_HSS_DISABLE |
1072 COH901318_CX_CTRL_DDMA_LEGACY |
1073 COH901318_CX_CTRL_PRDD_DEST,
1074 },
1075 {
1076 .number = U300_DMA_XGAM_CDI,
1077 .name = "XGAM CDI",
1078 .priority_high = 0,
1079 },
1080 {
1081 .number = U300_DMA_XGAM_PDI,
1082 .name = "XGAM PDI",
1083 .priority_high = 0,
1084 },
1085 /*
1086 * Don't set up device address, burst count or size of src
1087 * or dst bus for this peripheral - handled by PrimeCell
1088 * DMA extension.
1089 */
1090 {
1091 .number = U300_DMA_SPI_TX,
1092 .name = "SPI TX",
1093 .priority_high = 0,
1094 .param.config = COH901318_CX_CFG_CH_DISABLE |
1095 COH901318_CX_CFG_LCR_DISABLE |
1096 COH901318_CX_CFG_TC_IRQ_ENABLE |
1097 COH901318_CX_CFG_BE_IRQ_ENABLE,
1098 .param.ctrl_lli_chained = 0 |
1099 COH901318_CX_CTRL_TC_ENABLE |
1100 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1101 COH901318_CX_CTRL_TCP_DISABLE |
1102 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1103 COH901318_CX_CTRL_HSP_ENABLE |
1104 COH901318_CX_CTRL_HSS_DISABLE |
1105 COH901318_CX_CTRL_DDMA_LEGACY,
1106 .param.ctrl_lli = 0 |
1107 COH901318_CX_CTRL_TC_ENABLE |
1108 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1109 COH901318_CX_CTRL_TCP_DISABLE |
1110 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1111 COH901318_CX_CTRL_HSP_ENABLE |
1112 COH901318_CX_CTRL_HSS_DISABLE |
1113 COH901318_CX_CTRL_DDMA_LEGACY,
1114 .param.ctrl_lli_last = 0 |
1115 COH901318_CX_CTRL_TC_ENABLE |
1116 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1117 COH901318_CX_CTRL_TCP_DISABLE |
1118 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1119 COH901318_CX_CTRL_HSP_ENABLE |
1120 COH901318_CX_CTRL_HSS_DISABLE |
1121 COH901318_CX_CTRL_DDMA_LEGACY,
1122 },
1123 {
1124 .number = U300_DMA_SPI_RX,
1125 .name = "SPI RX",
1126 .priority_high = 0,
1127 .param.config = COH901318_CX_CFG_CH_DISABLE |
1128 COH901318_CX_CFG_LCR_DISABLE |
1129 COH901318_CX_CFG_TC_IRQ_ENABLE |
1130 COH901318_CX_CFG_BE_IRQ_ENABLE,
1131 .param.ctrl_lli_chained = 0 |
1132 COH901318_CX_CTRL_TC_ENABLE |
1133 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1134 COH901318_CX_CTRL_TCP_DISABLE |
1135 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1136 COH901318_CX_CTRL_HSP_ENABLE |
1137 COH901318_CX_CTRL_HSS_DISABLE |
1138 COH901318_CX_CTRL_DDMA_LEGACY,
1139 .param.ctrl_lli = 0 |
1140 COH901318_CX_CTRL_TC_ENABLE |
1141 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1142 COH901318_CX_CTRL_TCP_DISABLE |
1143 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1144 COH901318_CX_CTRL_HSP_ENABLE |
1145 COH901318_CX_CTRL_HSS_DISABLE |
1146 COH901318_CX_CTRL_DDMA_LEGACY,
1147 .param.ctrl_lli_last = 0 |
1148 COH901318_CX_CTRL_TC_ENABLE |
1149 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1150 COH901318_CX_CTRL_TCP_DISABLE |
1151 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1152 COH901318_CX_CTRL_HSP_ENABLE |
1153 COH901318_CX_CTRL_HSS_DISABLE |
1154 COH901318_CX_CTRL_DDMA_LEGACY,
1155
1156 },
1157 {
1158 .number = U300_DMA_GENERAL_PURPOSE_0,
1159 .name = "GENERAL 00",
1160 .priority_high = 0,
1161
1162 .param.config = flags_memcpy_config,
1163 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1164 .param.ctrl_lli = flags_memcpy_lli,
1165 .param.ctrl_lli_last = flags_memcpy_lli_last,
1166 },
1167 {
1168 .number = U300_DMA_GENERAL_PURPOSE_1,
1169 .name = "GENERAL 01",
1170 .priority_high = 0,
1171
1172 .param.config = flags_memcpy_config,
1173 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1174 .param.ctrl_lli = flags_memcpy_lli,
1175 .param.ctrl_lli_last = flags_memcpy_lli_last,
1176 },
1177 {
1178 .number = U300_DMA_GENERAL_PURPOSE_2,
1179 .name = "GENERAL 02",
1180 .priority_high = 0,
1181
1182 .param.config = flags_memcpy_config,
1183 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1184 .param.ctrl_lli = flags_memcpy_lli,
1185 .param.ctrl_lli_last = flags_memcpy_lli_last,
1186 },
1187 {
1188 .number = U300_DMA_GENERAL_PURPOSE_3,
1189 .name = "GENERAL 03",
1190 .priority_high = 0,
1191
1192 .param.config = flags_memcpy_config,
1193 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1194 .param.ctrl_lli = flags_memcpy_lli,
1195 .param.ctrl_lli_last = flags_memcpy_lli_last,
1196 },
1197 {
1198 .number = U300_DMA_GENERAL_PURPOSE_4,
1199 .name = "GENERAL 04",
1200 .priority_high = 0,
1201
1202 .param.config = flags_memcpy_config,
1203 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1204 .param.ctrl_lli = flags_memcpy_lli,
1205 .param.ctrl_lli_last = flags_memcpy_lli_last,
1206 },
1207 {
1208 .number = U300_DMA_GENERAL_PURPOSE_5,
1209 .name = "GENERAL 05",
1210 .priority_high = 0,
1211
1212 .param.config = flags_memcpy_config,
1213 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1214 .param.ctrl_lli = flags_memcpy_lli,
1215 .param.ctrl_lli_last = flags_memcpy_lli_last,
1216 },
1217 {
1218 .number = U300_DMA_GENERAL_PURPOSE_6,
1219 .name = "GENERAL 06",
1220 .priority_high = 0,
1221
1222 .param.config = flags_memcpy_config,
1223 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1224 .param.ctrl_lli = flags_memcpy_lli,
1225 .param.ctrl_lli_last = flags_memcpy_lli_last,
1226 },
1227 {
1228 .number = U300_DMA_GENERAL_PURPOSE_7,
1229 .name = "GENERAL 07",
1230 .priority_high = 0,
1231
1232 .param.config = flags_memcpy_config,
1233 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1234 .param.ctrl_lli = flags_memcpy_lli,
1235 .param.ctrl_lli_last = flags_memcpy_lli_last,
1236 },
1237 {
1238 .number = U300_DMA_GENERAL_PURPOSE_8,
1239 .name = "GENERAL 08",
1240 .priority_high = 0,
1241
1242 .param.config = flags_memcpy_config,
1243 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1244 .param.ctrl_lli = flags_memcpy_lli,
1245 .param.ctrl_lli_last = flags_memcpy_lli_last,
1246 },
1247 {
1248 .number = U300_DMA_UART1_TX,
1249 .name = "UART1 TX",
1250 .priority_high = 0,
1251 },
1252 {
1253 .number = U300_DMA_UART1_RX,
1254 .name = "UART1 RX",
1255 .priority_high = 0,
1256 }
1257};
1258
29#define COHC_2_DEV(cohc) (&cohc->chan.dev->device) 1259#define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
30 1260
31#ifdef VERBOSE_DEBUG 1261#ifdef VERBOSE_DEBUG
@@ -54,7 +1284,6 @@ struct coh901318_base {
54 struct dma_device dma_slave; 1284 struct dma_device dma_slave;
55 struct dma_device dma_memcpy; 1285 struct dma_device dma_memcpy;
56 struct coh901318_chan *chans; 1286 struct coh901318_chan *chans;
57 struct coh901318_platform *platform;
58}; 1287};
59 1288
60struct coh901318_chan { 1289struct coh901318_chan {
@@ -75,8 +1304,8 @@ struct coh901318_chan {
75 unsigned long nbr_active_done; 1304 unsigned long nbr_active_done;
76 unsigned long busy; 1305 unsigned long busy;
77 1306
78 u32 runtime_addr; 1307 u32 addr;
79 u32 runtime_ctrl; 1308 u32 ctrl;
80 1309
81 struct coh901318_base *base; 1310 struct coh901318_base *base;
82}; 1311};
@@ -122,7 +1351,7 @@ static int coh901318_debugfs_read(struct file *file, char __user *buf,
122 1351
123 tmp += sprintf(tmp, "DMA -- enabled dma channels\n"); 1352 tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
124 1353
125 for (i = 0; i < debugfs_dma_base->platform->max_channels; i++) 1354 for (i = 0; i < U300_DMA_CHANNELS; i++)
126 if (started_channels & (1 << i)) 1355 if (started_channels & (1 << i))
127 tmp += sprintf(tmp, "channel %d\n", i); 1356 tmp += sprintf(tmp, "channel %d\n", i);
128 1357
@@ -187,25 +1416,16 @@ static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
187 return container_of(chan, struct coh901318_chan, chan); 1416 return container_of(chan, struct coh901318_chan, chan);
188} 1417}
189 1418
190static inline dma_addr_t
191cohc_dev_addr(struct coh901318_chan *cohc)
192{
193 /* Runtime supplied address will take precedence */
194 if (cohc->runtime_addr)
195 return cohc->runtime_addr;
196 return cohc->base->platform->chan_conf[cohc->id].dev_addr;
197}
198
199static inline const struct coh901318_params * 1419static inline const struct coh901318_params *
200cohc_chan_param(struct coh901318_chan *cohc) 1420cohc_chan_param(struct coh901318_chan *cohc)
201{ 1421{
202 return &cohc->base->platform->chan_conf[cohc->id].param; 1422 return &chan_config[cohc->id].param;
203} 1423}
204 1424
205static inline const struct coh_dma_channel * 1425static inline const struct coh_dma_channel *
206cohc_chan_conf(struct coh901318_chan *cohc) 1426cohc_chan_conf(struct coh901318_chan *cohc)
207{ 1427{
208 return &cohc->base->platform->chan_conf[cohc->id]; 1428 return &chan_config[cohc->id];
209} 1429}
210 1430
211static void enable_powersave(struct coh901318_chan *cohc) 1431static void enable_powersave(struct coh901318_chan *cohc)
@@ -217,12 +1437,6 @@ static void enable_powersave(struct coh901318_chan *cohc)
217 1437
218 pm->started_channels &= ~(1ULL << cohc->id); 1438 pm->started_channels &= ~(1ULL << cohc->id);
219 1439
220 if (!pm->started_channels) {
221 /* DMA no longer intends to access memory */
222 cohc->base->platform->access_memory_state(cohc->base->dev,
223 false);
224 }
225
226 spin_unlock_irqrestore(&pm->lock, flags); 1440 spin_unlock_irqrestore(&pm->lock, flags);
227} 1441}
228static void disable_powersave(struct coh901318_chan *cohc) 1442static void disable_powersave(struct coh901318_chan *cohc)
@@ -232,12 +1446,6 @@ static void disable_powersave(struct coh901318_chan *cohc)
232 1446
233 spin_lock_irqsave(&pm->lock, flags); 1447 spin_lock_irqsave(&pm->lock, flags);
234 1448
235 if (!pm->started_channels) {
236 /* DMA intends to access memory */
237 cohc->base->platform->access_memory_state(cohc->base->dev,
238 true);
239 }
240
241 pm->started_channels |= (1ULL << cohc->id); 1449 pm->started_channels |= (1ULL << cohc->id);
242 1450
243 spin_unlock_irqrestore(&pm->lock, flags); 1451 spin_unlock_irqrestore(&pm->lock, flags);
@@ -596,7 +1804,7 @@ static int coh901318_config(struct coh901318_chan *cohc,
596 if (param) 1804 if (param)
597 p = param; 1805 p = param;
598 else 1806 else
599 p = &cohc->base->platform->chan_conf[channel].param; 1807 p = cohc_chan_param(cohc);
600 1808
601 /* Clear any pending BE or TC interrupt */ 1809 /* Clear any pending BE or TC interrupt */
602 if (channel < 32) { 1810 if (channel < 32) {
@@ -1052,9 +2260,9 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1052 * sure the bits you set per peripheral channel are 2260 * sure the bits you set per peripheral channel are
1053 * cleared in the default config from the platform. 2261 * cleared in the default config from the platform.
1054 */ 2262 */
1055 ctrl_chained |= cohc->runtime_ctrl; 2263 ctrl_chained |= cohc->ctrl;
1056 ctrl_last |= cohc->runtime_ctrl; 2264 ctrl_last |= cohc->ctrl;
1057 ctrl |= cohc->runtime_ctrl; 2265 ctrl |= cohc->ctrl;
1058 2266
1059 if (direction == DMA_MEM_TO_DEV) { 2267 if (direction == DMA_MEM_TO_DEV) {
1060 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE | 2268 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
@@ -1103,7 +2311,7 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1103 2311
1104 /* initiate allocated lli list */ 2312 /* initiate allocated lli list */
1105 ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len, 2313 ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
1106 cohc_dev_addr(cohc), 2314 cohc->addr,
1107 ctrl_chained, 2315 ctrl_chained,
1108 ctrl, 2316 ctrl,
1109 ctrl_last, 2317 ctrl_last,
@@ -1244,7 +2452,7 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
1244 dma_addr_t addr; 2452 dma_addr_t addr;
1245 enum dma_slave_buswidth addr_width; 2453 enum dma_slave_buswidth addr_width;
1246 u32 maxburst; 2454 u32 maxburst;
1247 u32 runtime_ctrl = 0; 2455 u32 ctrl = 0;
1248 int i = 0; 2456 int i = 0;
1249 2457
1250 /* We only support mem to per or per to mem transfers */ 2458 /* We only support mem to per or per to mem transfers */
@@ -1265,7 +2473,7 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
1265 addr_width); 2473 addr_width);
1266 switch (addr_width) { 2474 switch (addr_width) {
1267 case DMA_SLAVE_BUSWIDTH_1_BYTE: 2475 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1268 runtime_ctrl |= 2476 ctrl |=
1269 COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS | 2477 COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
1270 COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS; 2478 COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
1271 2479
@@ -1277,7 +2485,7 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
1277 2485
1278 break; 2486 break;
1279 case DMA_SLAVE_BUSWIDTH_2_BYTES: 2487 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1280 runtime_ctrl |= 2488 ctrl |=
1281 COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS | 2489 COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
1282 COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS; 2490 COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
1283 2491
@@ -1290,7 +2498,7 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
1290 break; 2498 break;
1291 case DMA_SLAVE_BUSWIDTH_4_BYTES: 2499 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1292 /* Direction doesn't matter here, it's 32/32 bits */ 2500 /* Direction doesn't matter here, it's 32/32 bits */
1293 runtime_ctrl |= 2501 ctrl |=
1294 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 2502 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1295 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS; 2503 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
1296 2504
@@ -1307,13 +2515,13 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
1307 return; 2515 return;
1308 } 2516 }
1309 2517
1310 runtime_ctrl |= burst_sizes[i].reg; 2518 ctrl |= burst_sizes[i].reg;
1311 dev_dbg(COHC_2_DEV(cohc), 2519 dev_dbg(COHC_2_DEV(cohc),
1312 "selected burst size %d bytes for address width %d bytes, maxburst %d\n", 2520 "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
1313 burst_sizes[i].burst_8bit, addr_width, maxburst); 2521 burst_sizes[i].burst_8bit, addr_width, maxburst);
1314 2522
1315 cohc->runtime_addr = addr; 2523 cohc->addr = addr;
1316 cohc->runtime_ctrl = runtime_ctrl; 2524 cohc->ctrl = ctrl;
1317} 2525}
1318 2526
1319static int 2527static int
@@ -1431,7 +2639,6 @@ void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
1431static int __init coh901318_probe(struct platform_device *pdev) 2639static int __init coh901318_probe(struct platform_device *pdev)
1432{ 2640{
1433 int err = 0; 2641 int err = 0;
1434 struct coh901318_platform *pdata;
1435 struct coh901318_base *base; 2642 struct coh901318_base *base;
1436 int irq; 2643 int irq;
1437 struct resource *io; 2644 struct resource *io;
@@ -1447,13 +2654,9 @@ static int __init coh901318_probe(struct platform_device *pdev)
1447 pdev->dev.driver->name) == NULL) 2654 pdev->dev.driver->name) == NULL)
1448 return -ENOMEM; 2655 return -ENOMEM;
1449 2656
1450 pdata = pdev->dev.platform_data;
1451 if (!pdata)
1452 return -ENODEV;
1453
1454 base = devm_kzalloc(&pdev->dev, 2657 base = devm_kzalloc(&pdev->dev,
1455 ALIGN(sizeof(struct coh901318_base), 4) + 2658 ALIGN(sizeof(struct coh901318_base), 4) +
1456 pdata->max_channels * 2659 U300_DMA_CHANNELS *
1457 sizeof(struct coh901318_chan), 2660 sizeof(struct coh901318_chan),
1458 GFP_KERNEL); 2661 GFP_KERNEL);
1459 if (!base) 2662 if (!base)
@@ -1466,7 +2669,6 @@ static int __init coh901318_probe(struct platform_device *pdev)
1466 return -ENOMEM; 2669 return -ENOMEM;
1467 2670
1468 base->dev = &pdev->dev; 2671 base->dev = &pdev->dev;
1469 base->platform = pdata;
1470 spin_lock_init(&base->pm.lock); 2672 spin_lock_init(&base->pm.lock);
1471 base->pm.started_channels = 0; 2673 base->pm.started_channels = 0;
1472 2674
@@ -1488,7 +2690,7 @@ static int __init coh901318_probe(struct platform_device *pdev)
1488 return err; 2690 return err;
1489 2691
1490 /* init channels for device transfers */ 2692 /* init channels for device transfers */
1491 coh901318_base_init(&base->dma_slave, base->platform->chans_slave, 2693 coh901318_base_init(&base->dma_slave, dma_slave_channels,
1492 base); 2694 base);
1493 2695
1494 dma_cap_zero(base->dma_slave.cap_mask); 2696 dma_cap_zero(base->dma_slave.cap_mask);
@@ -1508,7 +2710,7 @@ static int __init coh901318_probe(struct platform_device *pdev)
1508 goto err_register_slave; 2710 goto err_register_slave;
1509 2711
1510 /* init channels for memcpy */ 2712 /* init channels for memcpy */
1511 coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy, 2713 coh901318_base_init(&base->dma_memcpy, dma_memcpy_channels,
1512 base); 2714 base);
1513 2715
1514 dma_cap_zero(base->dma_memcpy.cap_mask); 2716 dma_cap_zero(base->dma_memcpy.cap_mask);
diff --git a/drivers/dma/coh901318_lli.h b/drivers/dma/coh901318.h
index abff3714fdda..95ce1e2123ec 100644
--- a/drivers/dma/coh901318_lli.h
+++ b/drivers/dma/coh901318.h
@@ -1,16 +1,15 @@
1/* 1/*
2 * driver/dma/coh901318_lli.h 2 * Copyright (C) 2007-2013 ST-Ericsson
3 *
4 * Copyright (C) 2007-2009 ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2 3 * License terms: GNU General Public License (GPL) version 2
6 * Support functions for handling lli for coh901318 4 * DMA driver for COH 901 318
7 * Author: Per Friden <per.friden@stericsson.com> 5 * Author: Per Friden <per.friden@stericsson.com>
8 */ 6 */
9 7
10#ifndef COH901318_LLI_H 8#ifndef COH901318_H
11#define COH901318_LLI_H 9#define COH901318_H
12 10
13#include <mach/coh901318.h> 11#define MAX_DMA_PACKET_SIZE_SHIFT 11
12#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
14 13
15struct device; 14struct device;
16 15
@@ -24,7 +23,25 @@ struct coh901318_pool {
24#endif 23#endif
25}; 24};
26 25
27struct device; 26/**
27 * struct coh901318_lli - linked list item for DMAC
28 * @control: control settings for DMAC
29 * @src_addr: transfer source address
30 * @dst_addr: transfer destination address
31 * @link_addr: physical address to next lli
32 * @virt_link_addr: virtual address of next lli (only used by pool_free)
33 * @phy_this: physical address of current lli (only used by pool_free)
34 */
35struct coh901318_lli {
36 u32 control;
37 dma_addr_t src_addr;
38 dma_addr_t dst_addr;
39 dma_addr_t link_addr;
40
41 void *virt_link_addr;
42 dma_addr_t phy_this;
43};
44
28/** 45/**
29 * coh901318_pool_create() - Creates an dma pool for lli:s 46 * coh901318_pool_create() - Creates an dma pool for lli:s
30 * @pool: pool handle 47 * @pool: pool handle
@@ -121,4 +138,4 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
121 u32 ctrl, u32 ctrl_last, 138 u32 ctrl, u32 ctrl_last,
122 enum dma_transfer_direction dir, u32 ctrl_irq_mask); 139 enum dma_transfer_direction dir, u32 ctrl_irq_mask);
123 140
124#endif /* COH901318_LLI_H */ 141#endif /* COH901318_H */
diff --git a/drivers/dma/coh901318_lli.c b/drivers/dma/coh901318_lli.c
index 780e0429b38c..3e96610e18e2 100644
--- a/drivers/dma/coh901318_lli.c
+++ b/drivers/dma/coh901318_lli.c
@@ -11,9 +11,9 @@
11#include <linux/memory.h> 11#include <linux/memory.h>
12#include <linux/gfp.h> 12#include <linux/gfp.h>
13#include <linux/dmapool.h> 13#include <linux/dmapool.h>
14#include <mach/coh901318.h> 14#include <linux/dmaengine.h>
15 15
16#include "coh901318_lli.h" 16#include "coh901318.h"
17 17
18#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG)) 18#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
19#define DEBUGFS_POOL_COUNTER_RESET(pool) (pool->debugfs_pool_counter = 0) 19#define DEBUGFS_POOL_COUNTER_RESET(pool) (pool->debugfs_pool_counter = 0)
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 1192518e1aca..a2bacf95b59e 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -3102,8 +3102,8 @@ static struct mfd_cell db8500_prcmu_devs[] = {
3102 .pdata_size = sizeof(db8500_regulators), 3102 .pdata_size = sizeof(db8500_regulators),
3103 }, 3103 },
3104 { 3104 {
3105 .name = "cpufreq-u8500", 3105 .name = "cpufreq-ux500",
3106 .of_compatible = "stericsson,cpufreq-u8500", 3106 .of_compatible = "stericsson,cpufreq-ux500",
3107 .platform_data = &db8500_cpufreq_table, 3107 .platform_data = &db8500_cpufreq_table,
3108 .pdata_size = sizeof(db8500_cpufreq_table), 3108 .pdata_size = sizeof(db8500_cpufreq_table),
3109 }, 3109 },
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 0002d5e94f0d..1d333497cfcb 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1332,6 +1332,7 @@ static int omap_nand_probe(struct platform_device *pdev)
1332 dma_cap_mask_t mask; 1332 dma_cap_mask_t mask;
1333 unsigned sig; 1333 unsigned sig;
1334 struct resource *res; 1334 struct resource *res;
1335 struct mtd_part_parser_data ppdata = {};
1335 1336
1336 pdata = pdev->dev.platform_data; 1337 pdata = pdev->dev.platform_data;
1337 if (pdata == NULL) { 1338 if (pdata == NULL) {
@@ -1557,7 +1558,8 @@ static int omap_nand_probe(struct platform_device *pdev)
1557 goto out_release_mem_region; 1558 goto out_release_mem_region;
1558 } 1559 }
1559 1560
1560 mtd_device_parse_register(&info->mtd, NULL, NULL, pdata->parts, 1561 ppdata.of_node = pdata->of_node;
1562 mtd_device_parse_register(&info->mtd, NULL, &ppdata, pdata->parts,
1561 pdata->nr_parts); 1563 pdata->nr_parts);
1562 1564
1563 platform_set_drvdata(pdev, &info->mtd); 1565 platform_set_drvdata(pdev, &info->mtd);
diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 065f3fe02a2f..eec2aedb4ab8 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -637,6 +637,7 @@ static int omap2_onenand_probe(struct platform_device *pdev)
637 struct onenand_chip *this; 637 struct onenand_chip *this;
638 int r; 638 int r;
639 struct resource *res; 639 struct resource *res;
640 struct mtd_part_parser_data ppdata = {};
640 641
641 pdata = pdev->dev.platform_data; 642 pdata = pdev->dev.platform_data;
642 if (pdata == NULL) { 643 if (pdata == NULL) {
@@ -767,7 +768,8 @@ static int omap2_onenand_probe(struct platform_device *pdev)
767 if ((r = onenand_scan(&c->mtd, 1)) < 0) 768 if ((r = onenand_scan(&c->mtd, 1)) < 0)
768 goto err_release_regulator; 769 goto err_release_regulator;
769 770
770 r = mtd_device_parse_register(&c->mtd, NULL, NULL, 771 ppdata.of_node = pdata->of_node;
772 r = mtd_device_parse_register(&c->mtd, NULL, &ppdata,
771 pdata ? pdata->parts : NULL, 773 pdata ? pdata->parts : NULL,
772 pdata ? pdata->nr_parts : 0); 774 pdata ? pdata->nr_parts : 0);
773 if (r) 775 if (r)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 05:52:18 -0500