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-rw-r--r--drivers/clk/spear/Makefile2
-rw-r--r--drivers/clk/spear/spear1310_clock.c1106
-rw-r--r--drivers/clk/spear/spear1340_clock.c964
-rw-r--r--drivers/gpio/gpio-samsung.c11
-rw-r--r--drivers/pinctrl/spear/Kconfig10
-rw-r--r--drivers/pinctrl/spear/Makefile2
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.h251
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear1310.c2198
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear1340.c1989
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear3xx.c103
-rw-r--r--drivers/spi/Kconfig2
11 files changed, 6534 insertions, 104 deletions
diff --git a/drivers/clk/spear/Makefile b/drivers/clk/spear/Makefile
index 335886049c83..cdb425d3b8ee 100644
--- a/drivers/clk/spear/Makefile
+++ b/drivers/clk/spear/Makefile
@@ -6,3 +6,5 @@ obj-y += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
6 6
7obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx_clock.o 7obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx_clock.o
8obj-$(CONFIG_ARCH_SPEAR6XX) += spear6xx_clock.o 8obj-$(CONFIG_ARCH_SPEAR6XX) += spear6xx_clock.o
9obj-$(CONFIG_MACH_SPEAR1310) += spear1310_clock.o
10obj-$(CONFIG_MACH_SPEAR1340) += spear1340_clock.o
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
new file mode 100644
index 000000000000..42b68df9aeef
--- /dev/null
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -0,0 +1,1106 @@
1/*
2 * arch/arm/mach-spear13xx/spear1310_clock.c
3 *
4 * SPEAr1310 machine clock framework source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/clk.h>
15#include <linux/clkdev.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/of_platform.h>
19#include <linux/spinlock_types.h>
20#include <mach/spear.h>
21#include "clk.h"
22
23/* PLL related registers and bit values */
24#define SPEAR1310_PLL_CFG (VA_MISC_BASE + 0x210)
25 /* PLL_CFG bit values */
26 #define SPEAR1310_CLCD_SYNT_CLK_MASK 1
27 #define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31
28 #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2
29 #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT 29
30 #define SPEAR1310_RAS_SYNT_CLK_MASK 2
31 #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT 27
32 #define SPEAR1310_PLL_CLK_MASK 2
33 #define SPEAR1310_PLL3_CLK_SHIFT 24
34 #define SPEAR1310_PLL2_CLK_SHIFT 22
35 #define SPEAR1310_PLL1_CLK_SHIFT 20
36
37#define SPEAR1310_PLL1_CTR (VA_MISC_BASE + 0x214)
38#define SPEAR1310_PLL1_FRQ (VA_MISC_BASE + 0x218)
39#define SPEAR1310_PLL2_CTR (VA_MISC_BASE + 0x220)
40#define SPEAR1310_PLL2_FRQ (VA_MISC_BASE + 0x224)
41#define SPEAR1310_PLL3_CTR (VA_MISC_BASE + 0x22C)
42#define SPEAR1310_PLL3_FRQ (VA_MISC_BASE + 0x230)
43#define SPEAR1310_PLL4_CTR (VA_MISC_BASE + 0x238)
44#define SPEAR1310_PLL4_FRQ (VA_MISC_BASE + 0x23C)
45#define SPEAR1310_PERIP_CLK_CFG (VA_MISC_BASE + 0x244)
46 /* PERIP_CLK_CFG bit values */
47 #define SPEAR1310_GPT_OSC24_VAL 0
48 #define SPEAR1310_GPT_APB_VAL 1
49 #define SPEAR1310_GPT_CLK_MASK 1
50 #define SPEAR1310_GPT3_CLK_SHIFT 11
51 #define SPEAR1310_GPT2_CLK_SHIFT 10
52 #define SPEAR1310_GPT1_CLK_SHIFT 9
53 #define SPEAR1310_GPT0_CLK_SHIFT 8
54 #define SPEAR1310_UART_CLK_PLL5_VAL 0
55 #define SPEAR1310_UART_CLK_OSC24_VAL 1
56 #define SPEAR1310_UART_CLK_SYNT_VAL 2
57 #define SPEAR1310_UART_CLK_MASK 2
58 #define SPEAR1310_UART_CLK_SHIFT 4
59
60 #define SPEAR1310_AUX_CLK_PLL5_VAL 0
61 #define SPEAR1310_AUX_CLK_SYNT_VAL 1
62 #define SPEAR1310_CLCD_CLK_MASK 2
63 #define SPEAR1310_CLCD_CLK_SHIFT 2
64 #define SPEAR1310_C3_CLK_MASK 1
65 #define SPEAR1310_C3_CLK_SHIFT 1
66
67#define SPEAR1310_GMAC_CLK_CFG (VA_MISC_BASE + 0x248)
68 #define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3
69 #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4
70 #define SPEAR1310_GMAC_PHY_CLK_MASK 1
71 #define SPEAR1310_GMAC_PHY_CLK_SHIFT 3
72 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2
73 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1
74
75#define SPEAR1310_I2S_CLK_CFG (VA_MISC_BASE + 0x24C)
76 /* I2S_CLK_CFG register mask */
77 #define SPEAR1310_I2S_SCLK_X_MASK 0x1F
78 #define SPEAR1310_I2S_SCLK_X_SHIFT 27
79 #define SPEAR1310_I2S_SCLK_Y_MASK 0x1F
80 #define SPEAR1310_I2S_SCLK_Y_SHIFT 22
81 #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT 21
82 #define SPEAR1310_I2S_SCLK_SYNTH_ENB 20
83 #define SPEAR1310_I2S_PRS1_CLK_X_MASK 0xFF
84 #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT 12
85 #define SPEAR1310_I2S_PRS1_CLK_Y_MASK 0xFF
86 #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT 4
87 #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT 3
88 #define SPEAR1310_I2S_REF_SEL_MASK 1
89 #define SPEAR1310_I2S_REF_SHIFT 2
90 #define SPEAR1310_I2S_SRC_CLK_MASK 2
91 #define SPEAR1310_I2S_SRC_CLK_SHIFT 0
92
93#define SPEAR1310_C3_CLK_SYNT (VA_MISC_BASE + 0x250)
94#define SPEAR1310_UART_CLK_SYNT (VA_MISC_BASE + 0x254)
95#define SPEAR1310_GMAC_CLK_SYNT (VA_MISC_BASE + 0x258)
96#define SPEAR1310_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x25C)
97#define SPEAR1310_CFXD_CLK_SYNT (VA_MISC_BASE + 0x260)
98#define SPEAR1310_ADC_CLK_SYNT (VA_MISC_BASE + 0x264)
99#define SPEAR1310_AMBA_CLK_SYNT (VA_MISC_BASE + 0x268)
100#define SPEAR1310_CLCD_CLK_SYNT (VA_MISC_BASE + 0x270)
101#define SPEAR1310_RAS_CLK_SYNT0 (VA_MISC_BASE + 0x280)
102#define SPEAR1310_RAS_CLK_SYNT1 (VA_MISC_BASE + 0x288)
103#define SPEAR1310_RAS_CLK_SYNT2 (VA_MISC_BASE + 0x290)
104#define SPEAR1310_RAS_CLK_SYNT3 (VA_MISC_BASE + 0x298)
105 /* Check Fractional synthesizer reg masks */
106
107#define SPEAR1310_PERIP1_CLK_ENB (VA_MISC_BASE + 0x300)
108 /* PERIP1_CLK_ENB register masks */
109 #define SPEAR1310_RTC_CLK_ENB 31
110 #define SPEAR1310_ADC_CLK_ENB 30
111 #define SPEAR1310_C3_CLK_ENB 29
112 #define SPEAR1310_JPEG_CLK_ENB 28
113 #define SPEAR1310_CLCD_CLK_ENB 27
114 #define SPEAR1310_DMA_CLK_ENB 25
115 #define SPEAR1310_GPIO1_CLK_ENB 24
116 #define SPEAR1310_GPIO0_CLK_ENB 23
117 #define SPEAR1310_GPT1_CLK_ENB 22
118 #define SPEAR1310_GPT0_CLK_ENB 21
119 #define SPEAR1310_I2S0_CLK_ENB 20
120 #define SPEAR1310_I2S1_CLK_ENB 19
121 #define SPEAR1310_I2C0_CLK_ENB 18
122 #define SPEAR1310_SSP_CLK_ENB 17
123 #define SPEAR1310_UART_CLK_ENB 15
124 #define SPEAR1310_PCIE_SATA_2_CLK_ENB 14
125 #define SPEAR1310_PCIE_SATA_1_CLK_ENB 13
126 #define SPEAR1310_PCIE_SATA_0_CLK_ENB 12
127 #define SPEAR1310_UOC_CLK_ENB 11
128 #define SPEAR1310_UHC1_CLK_ENB 10
129 #define SPEAR1310_UHC0_CLK_ENB 9
130 #define SPEAR1310_GMAC_CLK_ENB 8
131 #define SPEAR1310_CFXD_CLK_ENB 7
132 #define SPEAR1310_SDHCI_CLK_ENB 6
133 #define SPEAR1310_SMI_CLK_ENB 5
134 #define SPEAR1310_FSMC_CLK_ENB 4
135 #define SPEAR1310_SYSRAM0_CLK_ENB 3
136 #define SPEAR1310_SYSRAM1_CLK_ENB 2
137 #define SPEAR1310_SYSROM_CLK_ENB 1
138 #define SPEAR1310_BUS_CLK_ENB 0
139
140#define SPEAR1310_PERIP2_CLK_ENB (VA_MISC_BASE + 0x304)
141 /* PERIP2_CLK_ENB register masks */
142 #define SPEAR1310_THSENS_CLK_ENB 8
143 #define SPEAR1310_I2S_REF_PAD_CLK_ENB 7
144 #define SPEAR1310_ACP_CLK_ENB 6
145 #define SPEAR1310_GPT3_CLK_ENB 5
146 #define SPEAR1310_GPT2_CLK_ENB 4
147 #define SPEAR1310_KBD_CLK_ENB 3
148 #define SPEAR1310_CPU_DBG_CLK_ENB 2
149 #define SPEAR1310_DDR_CORE_CLK_ENB 1
150 #define SPEAR1310_DDR_CTRL_CLK_ENB 0
151
152#define SPEAR1310_RAS_CLK_ENB (VA_MISC_BASE + 0x310)
153 /* RAS_CLK_ENB register masks */
154 #define SPEAR1310_SYNT3_CLK_ENB 17
155 #define SPEAR1310_SYNT2_CLK_ENB 16
156 #define SPEAR1310_SYNT1_CLK_ENB 15
157 #define SPEAR1310_SYNT0_CLK_ENB 14
158 #define SPEAR1310_PCLK3_CLK_ENB 13
159 #define SPEAR1310_PCLK2_CLK_ENB 12
160 #define SPEAR1310_PCLK1_CLK_ENB 11
161 #define SPEAR1310_PCLK0_CLK_ENB 10
162 #define SPEAR1310_PLL3_CLK_ENB 9
163 #define SPEAR1310_PLL2_CLK_ENB 8
164 #define SPEAR1310_C125M_PAD_CLK_ENB 7
165 #define SPEAR1310_C30M_CLK_ENB 6
166 #define SPEAR1310_C48M_CLK_ENB 5
167 #define SPEAR1310_OSC_25M_CLK_ENB 4
168 #define SPEAR1310_OSC_32K_CLK_ENB 3
169 #define SPEAR1310_OSC_24M_CLK_ENB 2
170 #define SPEAR1310_PCLK_CLK_ENB 1
171 #define SPEAR1310_ACLK_CLK_ENB 0
172
173/* RAS Area Control Register */
174#define SPEAR1310_RAS_CTRL_REG0 (VA_SPEAR1310_RAS_BASE + 0x000)
175 #define SPEAR1310_SSP1_CLK_MASK 3
176 #define SPEAR1310_SSP1_CLK_SHIFT 26
177 #define SPEAR1310_TDM_CLK_MASK 1
178 #define SPEAR1310_TDM2_CLK_SHIFT 24
179 #define SPEAR1310_TDM1_CLK_SHIFT 23
180 #define SPEAR1310_I2C_CLK_MASK 1
181 #define SPEAR1310_I2C7_CLK_SHIFT 22
182 #define SPEAR1310_I2C6_CLK_SHIFT 21
183 #define SPEAR1310_I2C5_CLK_SHIFT 20
184 #define SPEAR1310_I2C4_CLK_SHIFT 19
185 #define SPEAR1310_I2C3_CLK_SHIFT 18
186 #define SPEAR1310_I2C2_CLK_SHIFT 17
187 #define SPEAR1310_I2C1_CLK_SHIFT 16
188 #define SPEAR1310_GPT64_CLK_MASK 1
189 #define SPEAR1310_GPT64_CLK_SHIFT 15
190 #define SPEAR1310_RAS_UART_CLK_MASK 1
191 #define SPEAR1310_UART5_CLK_SHIFT 14
192 #define SPEAR1310_UART4_CLK_SHIFT 13
193 #define SPEAR1310_UART3_CLK_SHIFT 12
194 #define SPEAR1310_UART2_CLK_SHIFT 11
195 #define SPEAR1310_UART1_CLK_SHIFT 10
196 #define SPEAR1310_PCI_CLK_MASK 1
197 #define SPEAR1310_PCI_CLK_SHIFT 0
198
199#define SPEAR1310_RAS_CTRL_REG1 (VA_SPEAR1310_RAS_BASE + 0x004)
200 #define SPEAR1310_PHY_CLK_MASK 0x3
201 #define SPEAR1310_RMII_PHY_CLK_SHIFT 0
202 #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2
203
204#define SPEAR1310_RAS_SW_CLK_CTRL (VA_SPEAR1310_RAS_BASE + 0x0148)
205 #define SPEAR1310_CAN1_CLK_ENB 25
206 #define SPEAR1310_CAN0_CLK_ENB 24
207 #define SPEAR1310_GPT64_CLK_ENB 23
208 #define SPEAR1310_SSP1_CLK_ENB 22
209 #define SPEAR1310_I2C7_CLK_ENB 21
210 #define SPEAR1310_I2C6_CLK_ENB 20
211 #define SPEAR1310_I2C5_CLK_ENB 19
212 #define SPEAR1310_I2C4_CLK_ENB 18
213 #define SPEAR1310_I2C3_CLK_ENB 17
214 #define SPEAR1310_I2C2_CLK_ENB 16
215 #define SPEAR1310_I2C1_CLK_ENB 15
216 #define SPEAR1310_UART5_CLK_ENB 14
217 #define SPEAR1310_UART4_CLK_ENB 13
218 #define SPEAR1310_UART3_CLK_ENB 12
219 #define SPEAR1310_UART2_CLK_ENB 11
220 #define SPEAR1310_UART1_CLK_ENB 10
221 #define SPEAR1310_RS485_1_CLK_ENB 9
222 #define SPEAR1310_RS485_0_CLK_ENB 8
223 #define SPEAR1310_TDM2_CLK_ENB 7
224 #define SPEAR1310_TDM1_CLK_ENB 6
225 #define SPEAR1310_PCI_CLK_ENB 5
226 #define SPEAR1310_GMII_CLK_ENB 4
227 #define SPEAR1310_MII2_CLK_ENB 3
228 #define SPEAR1310_MII1_CLK_ENB 2
229 #define SPEAR1310_MII0_CLK_ENB 1
230 #define SPEAR1310_ESRAM_CLK_ENB 0
231
232static DEFINE_SPINLOCK(_lock);
233
234/* pll rate configuration table, in ascending order of rates */
235static struct pll_rate_tbl pll_rtbl[] = {
236 /* PCLK 24MHz */
237 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
238 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
239 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
240 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
241 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
242 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
243 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
244};
245
246/* vco-pll4 rate configuration table, in ascending order of rates */
247static struct pll_rate_tbl pll4_rtbl[] = {
248 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
249 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
250 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
251 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
252};
253
254/* aux rate configuration table, in ascending order of rates */
255static struct aux_rate_tbl aux_rtbl[] = {
256 /* For VCO1div2 = 500 MHz */
257 {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
258 {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
259 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
260 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
261 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
262 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
263};
264
265/* gmac rate configuration table, in ascending order of rates */
266static struct aux_rate_tbl gmac_rtbl[] = {
267 /* For gmac phy input clk */
268 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
269 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
270 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
271 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
272};
273
274/* clcd rate configuration table, in ascending order of rates */
275static struct frac_rate_tbl clcd_rtbl[] = {
276 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
277 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
278 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
279 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
280 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
281 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
282 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
283 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
284 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
285 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
286};
287
288/* i2s prescaler1 masks */
289static struct aux_clk_masks i2s_prs1_masks = {
290 .eq_sel_mask = AUX_EQ_SEL_MASK,
291 .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT,
292 .eq1_mask = AUX_EQ1_SEL,
293 .eq2_mask = AUX_EQ2_SEL,
294 .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK,
295 .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT,
296 .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK,
297 .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT,
298};
299
300/* i2s sclk (bit clock) syynthesizers masks */
301static struct aux_clk_masks i2s_sclk_masks = {
302 .eq_sel_mask = AUX_EQ_SEL_MASK,
303 .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT,
304 .eq1_mask = AUX_EQ1_SEL,
305 .eq2_mask = AUX_EQ2_SEL,
306 .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK,
307 .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT,
308 .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK,
309 .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT,
310 .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB,
311};
312
313/* i2s prs1 aux rate configuration table, in ascending order of rates */
314static struct aux_rate_tbl i2s_prs1_rtbl[] = {
315 /* For parent clk = 49.152 MHz */
316 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
317};
318
319/* i2s sclk aux rate configuration table, in ascending order of rates */
320static struct aux_rate_tbl i2s_sclk_rtbl[] = {
321 /* For i2s_ref_clk = 12.288MHz */
322 {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
323 {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
324};
325
326/* adc rate configuration table, in ascending order of rates */
327/* possible adc range is 2.5 MHz to 20 MHz. */
328static struct aux_rate_tbl adc_rtbl[] = {
329 /* For ahb = 166.67 MHz */
330 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
331 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
332 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
333 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
334};
335
336/* General synth rate configuration table, in ascending order of rates */
337static struct frac_rate_tbl gen_rtbl[] = {
338 /* For vco1div4 = 250 MHz */
339 {.div = 0x14000}, /* 25 MHz */
340 {.div = 0x0A000}, /* 50 MHz */
341 {.div = 0x05000}, /* 100 MHz */
342 {.div = 0x02000}, /* 250 MHz */
343};
344
345/* clock parents */
346static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
347static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
348static const char *uart0_parents[] = { "pll5_clk", "uart_synth_gate_clk", };
349static const char *c3_parents[] = { "pll5_clk", "c3_synth_gate_clk", };
350static const char *gmac_phy_input_parents[] = { "gmii_125m_pad_clk", "pll2_clk",
351 "osc_25m_clk", };
352static const char *gmac_phy_parents[] = { "gmac_phy_input_mux_clk",
353 "gmac_phy_synth_gate_clk", };
354static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
355static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_synth_clk", };
356static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk",
357 "i2s_src_pad_clk", };
358static const char *i2s_ref_parents[] = { "i2s_src_mux_clk", "i2s_prs1_clk", };
359static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
360 "pll3_clk", };
361static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
362 "pll2_clk", };
363static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none",
364 "ras_pll2_clk", "ras_synth0_clk", };
365static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk",
366 "ras_pll2_clk", "ras_synth0_clk", };
367static const char *uart_parents[] = { "ras_apb_clk", "gen_synth3_clk", };
368static const char *i2c_parents[] = { "ras_apb_clk", "gen_synth1_clk", };
369static const char *ssp1_parents[] = { "ras_apb_clk", "gen_synth1_clk",
370 "ras_plclk0_clk", };
371static const char *pci_parents[] = { "ras_pll3_clk", "gen_synth2_clk", };
372static const char *tdm_parents[] = { "ras_pll3_clk", "gen_synth1_clk", };
373
374void __init spear1310_clk_init(void)
375{
376 struct clk *clk, *clk1;
377
378 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
379 clk_register_clkdev(clk, "apb_pclk", NULL);
380
381 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
382 32000);
383 clk_register_clkdev(clk, "osc_32k_clk", NULL);
384
385 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
386 24000000);
387 clk_register_clkdev(clk, "osc_24m_clk", NULL);
388
389 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
390 25000000);
391 clk_register_clkdev(clk, "osc_25m_clk", NULL);
392
393 clk = clk_register_fixed_rate(NULL, "gmii_125m_pad_clk", NULL,
394 CLK_IS_ROOT, 125000000);
395 clk_register_clkdev(clk, "gmii_125m_pad_clk", NULL);
396
397 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
398 CLK_IS_ROOT, 12288000);
399 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
400
401 /* clock derived from 32 KHz osc clk */
402 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
403 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0,
404 &_lock);
405 clk_register_clkdev(clk, NULL, "fc900000.rtc");
406
407 /* clock derived from 24 or 25 MHz osc clk */
408 /* vco-pll */
409 clk = clk_register_mux(NULL, "vco1_mux_clk", vco_parents,
410 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
411 SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
412 &_lock);
413 clk_register_clkdev(clk, "vco1_mux_clk", NULL);
414 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mux_clk",
415 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
416 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
417 clk_register_clkdev(clk, "vco1_clk", NULL);
418 clk_register_clkdev(clk1, "pll1_clk", NULL);
419
420 clk = clk_register_mux(NULL, "vco2_mux_clk", vco_parents,
421 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
422 SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
423 &_lock);
424 clk_register_clkdev(clk, "vco2_mux_clk", NULL);
425 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mux_clk",
426 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
427 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
428 clk_register_clkdev(clk, "vco2_clk", NULL);
429 clk_register_clkdev(clk1, "pll2_clk", NULL);
430
431 clk = clk_register_mux(NULL, "vco3_mux_clk", vco_parents,
432 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
433 SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
434 &_lock);
435 clk_register_clkdev(clk, "vco3_mux_clk", NULL);
436 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mux_clk",
437 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
438 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
439 clk_register_clkdev(clk, "vco3_clk", NULL);
440 clk_register_clkdev(clk1, "pll3_clk", NULL);
441
442 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
443 0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl,
444 ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
445 clk_register_clkdev(clk, "vco4_clk", NULL);
446 clk_register_clkdev(clk1, "pll4_clk", NULL);
447
448 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
449 48000000);
450 clk_register_clkdev(clk, "pll5_clk", NULL);
451
452 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
453 25000000);
454 clk_register_clkdev(clk, "pll6_clk", NULL);
455
456 /* vco div n clocks */
457 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
458 2);
459 clk_register_clkdev(clk, "vco1div2_clk", NULL);
460
461 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
462 4);
463 clk_register_clkdev(clk, "vco1div4_clk", NULL);
464
465 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
466 2);
467 clk_register_clkdev(clk, "vco2div2_clk", NULL);
468
469 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
470 2);
471 clk_register_clkdev(clk, "vco3div2_clk", NULL);
472
473 /* peripherals */
474 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
475 128);
476 clk = clk_register_gate(NULL, "thermal_gate_clk", "thermal_clk", 0,
477 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0,
478 &_lock);
479 clk_register_clkdev(clk, NULL, "spear_thermal");
480
481 /* clock derived from pll4 clk */
482 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
483 1);
484 clk_register_clkdev(clk, "ddr_clk", NULL);
485
486 /* clock derived from pll1 clk */
487 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 2);
488 clk_register_clkdev(clk, "cpu_clk", NULL);
489
490 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
491 2);
492 clk_register_clkdev(clk, NULL, "ec800620.wdt");
493
494 clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
495 6);
496 clk_register_clkdev(clk, "ahb_clk", NULL);
497
498 clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1,
499 12);
500 clk_register_clkdev(clk, "apb_clk", NULL);
501
502 /* gpt clocks */
503 clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt_parents,
504 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
505 SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
506 &_lock);
507 clk_register_clkdev(clk, "gpt0_mux_clk", NULL);
508 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mux_clk", 0,
509 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
510 &_lock);
511 clk_register_clkdev(clk, NULL, "gpt0");
512
513 clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt_parents,
514 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
515 SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
516 &_lock);
517 clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
518 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
519 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
520 &_lock);
521 clk_register_clkdev(clk, NULL, "gpt1");
522
523 clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt_parents,
524 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
525 SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
526 &_lock);
527 clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
528 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
529 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
530 &_lock);
531 clk_register_clkdev(clk, NULL, "gpt2");
532
533 clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt_parents,
534 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
535 SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
536 &_lock);
537 clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
538 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
539 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
540 &_lock);
541 clk_register_clkdev(clk, NULL, "gpt3");
542
543 /* others */
544 clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
545 "vco1div2_clk", 0, SPEAR1310_UART_CLK_SYNT, NULL,
546 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
547 clk_register_clkdev(clk, "uart_synth_clk", NULL);
548 clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
549
550 clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
551 ARRAY_SIZE(uart0_parents), 0, SPEAR1310_PERIP_CLK_CFG,
552 SPEAR1310_UART_CLK_SHIFT, SPEAR1310_UART_CLK_MASK, 0,
553 &_lock);
554 clk_register_clkdev(clk, "uart0_mux_clk", NULL);
555
556 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mux_clk", 0,
557 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UART_CLK_ENB, 0,
558 &_lock);
559 clk_register_clkdev(clk, NULL, "e0000000.serial");
560
561 clk = clk_register_aux("sdhci_synth_clk", "sdhci_synth_gate_clk",
562 "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
563 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
564 clk_register_clkdev(clk, "sdhci_synth_clk", NULL);
565 clk_register_clkdev(clk1, "sdhci_synth_gate_clk", NULL);
566
567 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_synth_gate_clk", 0,
568 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SDHCI_CLK_ENB, 0,
569 &_lock);
570 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
571
572 clk = clk_register_aux("cfxd_synth_clk", "cfxd_synth_gate_clk",
573 "vco1div2_clk", 0, SPEAR1310_CFXD_CLK_SYNT, NULL,
574 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
575 clk_register_clkdev(clk, "cfxd_synth_clk", NULL);
576 clk_register_clkdev(clk1, "cfxd_synth_gate_clk", NULL);
577
578 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_synth_gate_clk", 0,
579 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CFXD_CLK_ENB, 0,
580 &_lock);
581 clk_register_clkdev(clk, NULL, "b2800000.cf");
582 clk_register_clkdev(clk, NULL, "arasan_xd");
583
584 clk = clk_register_aux("c3_synth_clk", "c3_synth_gate_clk",
585 "vco1div2_clk", 0, SPEAR1310_C3_CLK_SYNT, NULL,
586 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
587 clk_register_clkdev(clk, "c3_synth_clk", NULL);
588 clk_register_clkdev(clk1, "c3_synth_gate_clk", NULL);
589
590 clk = clk_register_mux(NULL, "c3_mux_clk", c3_parents,
591 ARRAY_SIZE(c3_parents), 0, SPEAR1310_PERIP_CLK_CFG,
592 SPEAR1310_C3_CLK_SHIFT, SPEAR1310_C3_CLK_MASK, 0,
593 &_lock);
594 clk_register_clkdev(clk, "c3_mux_clk", NULL);
595
596 clk = clk_register_gate(NULL, "c3_clk", "c3_mux_clk", 0,
597 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
598 &_lock);
599 clk_register_clkdev(clk, NULL, "c3");
600
601 /* gmac */
602 clk = clk_register_mux(NULL, "gmac_phy_input_mux_clk",
603 gmac_phy_input_parents,
604 ARRAY_SIZE(gmac_phy_input_parents), 0,
605 SPEAR1310_GMAC_CLK_CFG,
606 SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
607 SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
608 clk_register_clkdev(clk, "gmac_phy_input_mux_clk", NULL);
609
610 clk = clk_register_aux("gmac_phy_synth_clk", "gmac_phy_synth_gate_clk",
611 "gmac_phy_input_mux_clk", 0, SPEAR1310_GMAC_CLK_SYNT,
612 NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
613 clk_register_clkdev(clk, "gmac_phy_synth_clk", NULL);
614 clk_register_clkdev(clk1, "gmac_phy_synth_gate_clk", NULL);
615
616 clk = clk_register_mux(NULL, "gmac_phy_mux_clk", gmac_phy_parents,
617 ARRAY_SIZE(gmac_phy_parents), 0,
618 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
619 SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
620 clk_register_clkdev(clk, NULL, "stmmacphy.0");
621
622 /* clcd */
623 clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents,
624 ARRAY_SIZE(clcd_synth_parents), 0,
625 SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT,
626 SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
627 clk_register_clkdev(clk, "clcd_synth_mux_clk", NULL);
628
629 clk = clk_register_frac("clcd_synth_clk", "clcd_synth_mux_clk", 0,
630 SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
631 ARRAY_SIZE(clcd_rtbl), &_lock);
632 clk_register_clkdev(clk, "clcd_synth_clk", NULL);
633
634 clk = clk_register_mux(NULL, "clcd_pixel_mux_clk", clcd_pixel_parents,
635 ARRAY_SIZE(clcd_pixel_parents), 0,
636 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
637 SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
638 clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
639
640 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mux_clk", 0,
641 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
642 &_lock);
643 clk_register_clkdev(clk, "clcd_clk", NULL);
644
645 /* i2s */
646 clk = clk_register_mux(NULL, "i2s_src_mux_clk", i2s_src_parents,
647 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG,
648 SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK,
649 0, &_lock);
650 clk_register_clkdev(clk, "i2s_src_clk", NULL);
651
652 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mux_clk", 0,
653 SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
654 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
655 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
656
657 clk = clk_register_mux(NULL, "i2s_ref_mux_clk", i2s_ref_parents,
658 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1310_I2S_CLK_CFG,
659 SPEAR1310_I2S_REF_SHIFT, SPEAR1310_I2S_REF_SEL_MASK, 0,
660 &_lock);
661 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
662
663 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mux_clk", 0,
664 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
665 0, &_lock);
666 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
667
668 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gate_clk",
669 "i2s_ref_pad_clk", 0, SPEAR1310_I2S_CLK_CFG,
670 &i2s_sclk_masks, i2s_sclk_rtbl,
671 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
672 clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
673 clk_register_clkdev(clk1, "i2s_sclk_gate_clk", NULL);
674
675 /* clock derived from ahb clk */
676 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
677 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0,
678 &_lock);
679 clk_register_clkdev(clk, NULL, "e0280000.i2c");
680
681 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
682 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0,
683 &_lock);
684 clk_register_clkdev(clk, NULL, "ea800000.dma");
685 clk_register_clkdev(clk, NULL, "eb000000.dma");
686
687 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0,
688 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0,
689 &_lock);
690 clk_register_clkdev(clk, NULL, "b2000000.jpeg");
691
692 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
693 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0,
694 &_lock);
695 clk_register_clkdev(clk, NULL, "e2000000.eth");
696
697 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
698 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0,
699 &_lock);
700 clk_register_clkdev(clk, NULL, "b0000000.flash");
701
702 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
703 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0,
704 &_lock);
705 clk_register_clkdev(clk, NULL, "ea000000.flash");
706
707 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
708 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0,
709 &_lock);
710 clk_register_clkdev(clk, "usbh.0_clk", NULL);
711
712 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
713 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0,
714 &_lock);
715 clk_register_clkdev(clk, "usbh.1_clk", NULL);
716
717 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
718 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0,
719 &_lock);
720 clk_register_clkdev(clk, NULL, "uoc");
721
722 clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
723 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
724 0, &_lock);
725 clk_register_clkdev(clk, NULL, "dw_pcie.0");
726 clk_register_clkdev(clk, NULL, "ahci.0");
727
728 clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
729 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
730 0, &_lock);
731 clk_register_clkdev(clk, NULL, "dw_pcie.1");
732 clk_register_clkdev(clk, NULL, "ahci.1");
733
734 clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
735 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
736 0, &_lock);
737 clk_register_clkdev(clk, NULL, "dw_pcie.2");
738 clk_register_clkdev(clk, NULL, "ahci.2");
739
740 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
741 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0,
742 &_lock);
743 clk_register_clkdev(clk, "sysram0_clk", NULL);
744
745 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
746 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0,
747 &_lock);
748 clk_register_clkdev(clk, "sysram1_clk", NULL);
749
750 clk = clk_register_aux("adc_synth_clk", "adc_synth_gate_clk", "ahb_clk",
751 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
752 ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
753 clk_register_clkdev(clk, "adc_synth_clk", NULL);
754 clk_register_clkdev(clk1, "adc_synth_gate_clk", NULL);
755
756 clk = clk_register_gate(NULL, "adc_clk", "adc_synth_gate_clk", 0,
757 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0,
758 &_lock);
759 clk_register_clkdev(clk, NULL, "adc_clk");
760
761 /* clock derived from apb clk */
762 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
763 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0,
764 &_lock);
765 clk_register_clkdev(clk, NULL, "e0100000.spi");
766
767 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
768 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0,
769 &_lock);
770 clk_register_clkdev(clk, NULL, "e0600000.gpio");
771
772 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
773 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0,
774 &_lock);
775 clk_register_clkdev(clk, NULL, "e0680000.gpio");
776
777 clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0,
778 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0,
779 &_lock);
780 clk_register_clkdev(clk, NULL, "e0180000.i2s");
781
782 clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0,
783 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0,
784 &_lock);
785 clk_register_clkdev(clk, NULL, "e0200000.i2s");
786
787 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
788 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0,
789 &_lock);
790 clk_register_clkdev(clk, NULL, "e0300000.kbd");
791
792 /* RAS clks */
793 clk = clk_register_mux(NULL, "gen_synth0_1_mux_clk",
794 gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents),
795 0, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
796 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
797 clk_register_clkdev(clk, "gen_synth0_1_clk", NULL);
798
799 clk = clk_register_mux(NULL, "gen_synth2_3_mux_clk",
800 gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents),
801 0, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
802 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
803 clk_register_clkdev(clk, "gen_synth2_3_clk", NULL);
804
805 clk = clk_register_frac("gen_synth0_clk", "gen_synth0_1_clk", 0,
806 SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
807 &_lock);
808 clk_register_clkdev(clk, "gen_synth0_clk", NULL);
809
810 clk = clk_register_frac("gen_synth1_clk", "gen_synth0_1_clk", 0,
811 SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
812 &_lock);
813 clk_register_clkdev(clk, "gen_synth1_clk", NULL);
814
815 clk = clk_register_frac("gen_synth2_clk", "gen_synth2_3_clk", 0,
816 SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
817 &_lock);
818 clk_register_clkdev(clk, "gen_synth2_clk", NULL);
819
820 clk = clk_register_frac("gen_synth3_clk", "gen_synth2_3_clk", 0,
821 SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
822 &_lock);
823 clk_register_clkdev(clk, "gen_synth3_clk", NULL);
824
825 clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0,
826 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0,
827 &_lock);
828 clk_register_clkdev(clk, "ras_osc_24m_clk", NULL);
829
830 clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0,
831 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0,
832 &_lock);
833 clk_register_clkdev(clk, "ras_osc_25m_clk", NULL);
834
835 clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0,
836 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0,
837 &_lock);
838 clk_register_clkdev(clk, "ras_osc_32k_clk", NULL);
839
840 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
841 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0,
842 &_lock);
843 clk_register_clkdev(clk, "ras_pll2_clk", NULL);
844
845 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
846 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0,
847 &_lock);
848 clk_register_clkdev(clk, "ras_pll3_clk", NULL);
849
850 clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_125m_pad_clk", 0,
851 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0,
852 &_lock);
853 clk_register_clkdev(clk, "ras_tx125_clk", NULL);
854
855 clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0,
856 30000000);
857 clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0,
858 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0,
859 &_lock);
860 clk_register_clkdev(clk, "ras_30m_clk", NULL);
861
862 clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0,
863 48000000);
864 clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0,
865 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0,
866 &_lock);
867 clk_register_clkdev(clk, "ras_48m_clk", NULL);
868
869 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0,
870 SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0,
871 &_lock);
872 clk_register_clkdev(clk, "ras_ahb_clk", NULL);
873
874 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0,
875 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0,
876 &_lock);
877 clk_register_clkdev(clk, "ras_apb_clk", NULL);
878
879 clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT,
880 50000000);
881
882 clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT,
883 50000000);
884
885 clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0,
886 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0,
887 &_lock);
888 clk_register_clkdev(clk, NULL, "c_can_platform.0");
889
890 clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0,
891 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0,
892 &_lock);
893 clk_register_clkdev(clk, NULL, "c_can_platform.1");
894
895 clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0,
896 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0,
897 &_lock);
898 clk_register_clkdev(clk, NULL, "5c400000.eth");
899
900 clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0,
901 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0,
902 &_lock);
903 clk_register_clkdev(clk, NULL, "5c500000.eth");
904
905 clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0,
906 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0,
907 &_lock);
908 clk_register_clkdev(clk, NULL, "5c600000.eth");
909
910 clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0,
911 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0,
912 &_lock);
913 clk_register_clkdev(clk, NULL, "5c700000.eth");
914
915 clk = clk_register_mux(NULL, "smii_rgmii_phy_mux_clk",
916 smii_rgmii_phy_parents,
917 ARRAY_SIZE(smii_rgmii_phy_parents), 0,
918 SPEAR1310_RAS_CTRL_REG1,
919 SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
920 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
921 clk_register_clkdev(clk, NULL, "stmmacphy.1");
922 clk_register_clkdev(clk, NULL, "stmmacphy.2");
923 clk_register_clkdev(clk, NULL, "stmmacphy.4");
924
925 clk = clk_register_mux(NULL, "rmii_phy_mux_clk", rmii_phy_parents,
926 ARRAY_SIZE(rmii_phy_parents), 0,
927 SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
928 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
929 clk_register_clkdev(clk, NULL, "stmmacphy.3");
930
931 clk = clk_register_mux(NULL, "uart1_mux_clk", uart_parents,
932 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
933 SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
934 0, &_lock);
935 clk_register_clkdev(clk, "uart1_mux_clk", NULL);
936
937 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mux_clk", 0,
938 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0,
939 &_lock);
940 clk_register_clkdev(clk, NULL, "5c800000.serial");
941
942 clk = clk_register_mux(NULL, "uart2_mux_clk", uart_parents,
943 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
944 SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
945 0, &_lock);
946 clk_register_clkdev(clk, "uart2_mux_clk", NULL);
947
948 clk = clk_register_gate(NULL, "uart2_clk", "uart2_mux_clk", 0,
949 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0,
950 &_lock);
951 clk_register_clkdev(clk, NULL, "5c900000.serial");
952
953 clk = clk_register_mux(NULL, "uart3_mux_clk", uart_parents,
954 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
955 SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
956 0, &_lock);
957 clk_register_clkdev(clk, "uart3_mux_clk", NULL);
958
959 clk = clk_register_gate(NULL, "uart3_clk", "uart3_mux_clk", 0,
960 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0,
961 &_lock);
962 clk_register_clkdev(clk, NULL, "5ca00000.serial");
963
964 clk = clk_register_mux(NULL, "uart4_mux_clk", uart_parents,
965 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
966 SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
967 0, &_lock);
968 clk_register_clkdev(clk, "uart4_mux_clk", NULL);
969
970 clk = clk_register_gate(NULL, "uart4_clk", "uart4_mux_clk", 0,
971 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0,
972 &_lock);
973 clk_register_clkdev(clk, NULL, "5cb00000.serial");
974
975 clk = clk_register_mux(NULL, "uart5_mux_clk", uart_parents,
976 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
977 SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
978 0, &_lock);
979 clk_register_clkdev(clk, "uart5_mux_clk", NULL);
980
981 clk = clk_register_gate(NULL, "uart5_clk", "uart5_mux_clk", 0,
982 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0,
983 &_lock);
984 clk_register_clkdev(clk, NULL, "5cc00000.serial");
985
986 clk = clk_register_mux(NULL, "i2c1_mux_clk", i2c_parents,
987 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
988 SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
989 &_lock);
990 clk_register_clkdev(clk, "i2c1_mux_clk", NULL);
991
992 clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mux_clk", 0,
993 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0,
994 &_lock);
995 clk_register_clkdev(clk, NULL, "5cd00000.i2c");
996
997 clk = clk_register_mux(NULL, "i2c2_mux_clk", i2c_parents,
998 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
999 SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1000 &_lock);
1001 clk_register_clkdev(clk, "i2c2_mux_clk", NULL);
1002
1003 clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mux_clk", 0,
1004 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0,
1005 &_lock);
1006 clk_register_clkdev(clk, NULL, "5ce00000.i2c");
1007
1008 clk = clk_register_mux(NULL, "i2c3_mux_clk", i2c_parents,
1009 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1010 SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1011 &_lock);
1012 clk_register_clkdev(clk, "i2c3_mux_clk", NULL);
1013
1014 clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mux_clk", 0,
1015 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0,
1016 &_lock);
1017 clk_register_clkdev(clk, NULL, "5cf00000.i2c");
1018
1019 clk = clk_register_mux(NULL, "i2c4_mux_clk", i2c_parents,
1020 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1021 SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1022 &_lock);
1023 clk_register_clkdev(clk, "i2c4_mux_clk", NULL);
1024
1025 clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mux_clk", 0,
1026 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0,
1027 &_lock);
1028 clk_register_clkdev(clk, NULL, "5d000000.i2c");
1029
1030 clk = clk_register_mux(NULL, "i2c5_mux_clk", i2c_parents,
1031 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1032 SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1033 &_lock);
1034 clk_register_clkdev(clk, "i2c5_mux_clk", NULL);
1035
1036 clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mux_clk", 0,
1037 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0,
1038 &_lock);
1039 clk_register_clkdev(clk, NULL, "5d100000.i2c");
1040
1041 clk = clk_register_mux(NULL, "i2c6_mux_clk", i2c_parents,
1042 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1043 SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1044 &_lock);
1045 clk_register_clkdev(clk, "i2c6_mux_clk", NULL);
1046
1047 clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mux_clk", 0,
1048 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0,
1049 &_lock);
1050 clk_register_clkdev(clk, NULL, "5d200000.i2c");
1051
1052 clk = clk_register_mux(NULL, "i2c7_mux_clk", i2c_parents,
1053 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1054 SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1055 &_lock);
1056 clk_register_clkdev(clk, "i2c7_mux_clk", NULL);
1057
1058 clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mux_clk", 0,
1059 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0,
1060 &_lock);
1061 clk_register_clkdev(clk, NULL, "5d300000.i2c");
1062
1063 clk = clk_register_mux(NULL, "ssp1_mux_clk", ssp1_parents,
1064 ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1065 SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0,
1066 &_lock);
1067 clk_register_clkdev(clk, "ssp1_mux_clk", NULL);
1068
1069 clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mux_clk", 0,
1070 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0,
1071 &_lock);
1072 clk_register_clkdev(clk, NULL, "5d400000.spi");
1073
1074 clk = clk_register_mux(NULL, "pci_mux_clk", pci_parents,
1075 ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1076 SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0,
1077 &_lock);
1078 clk_register_clkdev(clk, "pci_mux_clk", NULL);
1079
1080 clk = clk_register_gate(NULL, "pci_clk", "pci_mux_clk", 0,
1081 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0,
1082 &_lock);
1083 clk_register_clkdev(clk, NULL, "pci");
1084
1085 clk = clk_register_mux(NULL, "tdm1_mux_clk", tdm_parents,
1086 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1087 SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1088 &_lock);
1089 clk_register_clkdev(clk, "tdm1_mux_clk", NULL);
1090
1091 clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mux_clk", 0,
1092 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0,
1093 &_lock);
1094 clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
1095
1096 clk = clk_register_mux(NULL, "tdm2_mux_clk", tdm_parents,
1097 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1098 SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1099 &_lock);
1100 clk_register_clkdev(clk, "tdm2_mux_clk", NULL);
1101
1102 clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mux_clk", 0,
1103 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0,
1104 &_lock);
1105 clk_register_clkdev(clk, NULL, "tdm_hdlc.1");
1106}
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
new file mode 100644
index 000000000000..f130919d5bf8
--- /dev/null
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -0,0 +1,964 @@
1/*
2 * arch/arm/mach-spear13xx/spear1340_clock.c
3 *
4 * SPEAr1340 machine clock framework source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/clk.h>
15#include <linux/clkdev.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/of_platform.h>
19#include <linux/spinlock_types.h>
20#include <mach/spear.h>
21#include "clk.h"
22
23/* Clock Configuration Registers */
24#define SPEAR1340_SYS_CLK_CTRL (VA_MISC_BASE + 0x200)
25 #define SPEAR1340_HCLK_SRC_SEL_SHIFT 27
26 #define SPEAR1340_HCLK_SRC_SEL_MASK 1
27 #define SPEAR1340_SCLK_SRC_SEL_SHIFT 23
28 #define SPEAR1340_SCLK_SRC_SEL_MASK 3
29
30/* PLL related registers and bit values */
31#define SPEAR1340_PLL_CFG (VA_MISC_BASE + 0x210)
32 /* PLL_CFG bit values */
33 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1
34 #define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31
35 #define SPEAR1340_GEN_SYNT2_3_CLK_SHIFT 29
36 #define SPEAR1340_GEN_SYNT_CLK_MASK 2
37 #define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT 27
38 #define SPEAR1340_PLL_CLK_MASK 2
39 #define SPEAR1340_PLL3_CLK_SHIFT 24
40 #define SPEAR1340_PLL2_CLK_SHIFT 22
41 #define SPEAR1340_PLL1_CLK_SHIFT 20
42
43#define SPEAR1340_PLL1_CTR (VA_MISC_BASE + 0x214)
44#define SPEAR1340_PLL1_FRQ (VA_MISC_BASE + 0x218)
45#define SPEAR1340_PLL2_CTR (VA_MISC_BASE + 0x220)
46#define SPEAR1340_PLL2_FRQ (VA_MISC_BASE + 0x224)
47#define SPEAR1340_PLL3_CTR (VA_MISC_BASE + 0x22C)
48#define SPEAR1340_PLL3_FRQ (VA_MISC_BASE + 0x230)
49#define SPEAR1340_PLL4_CTR (VA_MISC_BASE + 0x238)
50#define SPEAR1340_PLL4_FRQ (VA_MISC_BASE + 0x23C)
51#define SPEAR1340_PERIP_CLK_CFG (VA_MISC_BASE + 0x244)
52 /* PERIP_CLK_CFG bit values */
53 #define SPEAR1340_SPDIF_CLK_MASK 1
54 #define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15
55 #define SPEAR1340_SPDIF_IN_CLK_SHIFT 14
56 #define SPEAR1340_GPT3_CLK_SHIFT 13
57 #define SPEAR1340_GPT2_CLK_SHIFT 12
58 #define SPEAR1340_GPT_CLK_MASK 1
59 #define SPEAR1340_GPT1_CLK_SHIFT 9
60 #define SPEAR1340_GPT0_CLK_SHIFT 8
61 #define SPEAR1340_UART_CLK_MASK 2
62 #define SPEAR1340_UART1_CLK_SHIFT 6
63 #define SPEAR1340_UART0_CLK_SHIFT 4
64 #define SPEAR1340_CLCD_CLK_MASK 2
65 #define SPEAR1340_CLCD_CLK_SHIFT 2
66 #define SPEAR1340_C3_CLK_MASK 1
67 #define SPEAR1340_C3_CLK_SHIFT 1
68
69#define SPEAR1340_GMAC_CLK_CFG (VA_MISC_BASE + 0x248)
70 #define SPEAR1340_GMAC_PHY_CLK_MASK 1
71 #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2
72 #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2
73 #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0
74
75#define SPEAR1340_I2S_CLK_CFG (VA_MISC_BASE + 0x24C)
76 /* I2S_CLK_CFG register mask */
77 #define SPEAR1340_I2S_SCLK_X_MASK 0x1F
78 #define SPEAR1340_I2S_SCLK_X_SHIFT 27
79 #define SPEAR1340_I2S_SCLK_Y_MASK 0x1F
80 #define SPEAR1340_I2S_SCLK_Y_SHIFT 22
81 #define SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT 21
82 #define SPEAR1340_I2S_SCLK_SYNTH_ENB 20
83 #define SPEAR1340_I2S_PRS1_CLK_X_MASK 0xFF
84 #define SPEAR1340_I2S_PRS1_CLK_X_SHIFT 12
85 #define SPEAR1340_I2S_PRS1_CLK_Y_MASK 0xFF
86 #define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT 4
87 #define SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT 3
88 #define SPEAR1340_I2S_REF_SEL_MASK 1
89 #define SPEAR1340_I2S_REF_SHIFT 2
90 #define SPEAR1340_I2S_SRC_CLK_MASK 2
91 #define SPEAR1340_I2S_SRC_CLK_SHIFT 0
92
93#define SPEAR1340_C3_CLK_SYNT (VA_MISC_BASE + 0x250)
94#define SPEAR1340_UART0_CLK_SYNT (VA_MISC_BASE + 0x254)
95#define SPEAR1340_UART1_CLK_SYNT (VA_MISC_BASE + 0x258)
96#define SPEAR1340_GMAC_CLK_SYNT (VA_MISC_BASE + 0x25C)
97#define SPEAR1340_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x260)
98#define SPEAR1340_CFXD_CLK_SYNT (VA_MISC_BASE + 0x264)
99#define SPEAR1340_ADC_CLK_SYNT (VA_MISC_BASE + 0x270)
100#define SPEAR1340_AMBA_CLK_SYNT (VA_MISC_BASE + 0x274)
101#define SPEAR1340_CLCD_CLK_SYNT (VA_MISC_BASE + 0x27C)
102#define SPEAR1340_SYS_CLK_SYNT (VA_MISC_BASE + 0x284)
103#define SPEAR1340_GEN_CLK_SYNT0 (VA_MISC_BASE + 0x28C)
104#define SPEAR1340_GEN_CLK_SYNT1 (VA_MISC_BASE + 0x294)
105#define SPEAR1340_GEN_CLK_SYNT2 (VA_MISC_BASE + 0x29C)
106#define SPEAR1340_GEN_CLK_SYNT3 (VA_MISC_BASE + 0x304)
107#define SPEAR1340_PERIP1_CLK_ENB (VA_MISC_BASE + 0x30C)
108 #define SPEAR1340_RTC_CLK_ENB 31
109 #define SPEAR1340_ADC_CLK_ENB 30
110 #define SPEAR1340_C3_CLK_ENB 29
111 #define SPEAR1340_CLCD_CLK_ENB 27
112 #define SPEAR1340_DMA_CLK_ENB 25
113 #define SPEAR1340_GPIO1_CLK_ENB 24
114 #define SPEAR1340_GPIO0_CLK_ENB 23
115 #define SPEAR1340_GPT1_CLK_ENB 22
116 #define SPEAR1340_GPT0_CLK_ENB 21
117 #define SPEAR1340_I2S_PLAY_CLK_ENB 20
118 #define SPEAR1340_I2S_REC_CLK_ENB 19
119 #define SPEAR1340_I2C0_CLK_ENB 18
120 #define SPEAR1340_SSP_CLK_ENB 17
121 #define SPEAR1340_UART0_CLK_ENB 15
122 #define SPEAR1340_PCIE_SATA_CLK_ENB 12
123 #define SPEAR1340_UOC_CLK_ENB 11
124 #define SPEAR1340_UHC1_CLK_ENB 10
125 #define SPEAR1340_UHC0_CLK_ENB 9
126 #define SPEAR1340_GMAC_CLK_ENB 8
127 #define SPEAR1340_CFXD_CLK_ENB 7
128 #define SPEAR1340_SDHCI_CLK_ENB 6
129 #define SPEAR1340_SMI_CLK_ENB 5
130 #define SPEAR1340_FSMC_CLK_ENB 4
131 #define SPEAR1340_SYSRAM0_CLK_ENB 3
132 #define SPEAR1340_SYSRAM1_CLK_ENB 2
133 #define SPEAR1340_SYSROM_CLK_ENB 1
134 #define SPEAR1340_BUS_CLK_ENB 0
135
136#define SPEAR1340_PERIP2_CLK_ENB (VA_MISC_BASE + 0x310)
137 #define SPEAR1340_THSENS_CLK_ENB 8
138 #define SPEAR1340_I2S_REF_PAD_CLK_ENB 7
139 #define SPEAR1340_ACP_CLK_ENB 6
140 #define SPEAR1340_GPT3_CLK_ENB 5
141 #define SPEAR1340_GPT2_CLK_ENB 4
142 #define SPEAR1340_KBD_CLK_ENB 3
143 #define SPEAR1340_CPU_DBG_CLK_ENB 2
144 #define SPEAR1340_DDR_CORE_CLK_ENB 1
145 #define SPEAR1340_DDR_CTRL_CLK_ENB 0
146
147#define SPEAR1340_PERIP3_CLK_ENB (VA_MISC_BASE + 0x314)
148 #define SPEAR1340_PLGPIO_CLK_ENB 18
149 #define SPEAR1340_VIDEO_DEC_CLK_ENB 16
150 #define SPEAR1340_VIDEO_ENC_CLK_ENB 15
151 #define SPEAR1340_SPDIF_OUT_CLK_ENB 13
152 #define SPEAR1340_SPDIF_IN_CLK_ENB 12
153 #define SPEAR1340_VIDEO_IN_CLK_ENB 11
154 #define SPEAR1340_CAM0_CLK_ENB 10
155 #define SPEAR1340_CAM1_CLK_ENB 9
156 #define SPEAR1340_CAM2_CLK_ENB 8
157 #define SPEAR1340_CAM3_CLK_ENB 7
158 #define SPEAR1340_MALI_CLK_ENB 6
159 #define SPEAR1340_CEC0_CLK_ENB 5
160 #define SPEAR1340_CEC1_CLK_ENB 4
161 #define SPEAR1340_PWM_CLK_ENB 3
162 #define SPEAR1340_I2C1_CLK_ENB 2
163 #define SPEAR1340_UART1_CLK_ENB 1
164
165static DEFINE_SPINLOCK(_lock);
166
167/* pll rate configuration table, in ascending order of rates */
168static struct pll_rate_tbl pll_rtbl[] = {
169 /* PCLK 24MHz */
170 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
171 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
172 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
173 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
174 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
175 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
176 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
177 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
178};
179
180/* vco-pll4 rate configuration table, in ascending order of rates */
181static struct pll_rate_tbl pll4_rtbl[] = {
182 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
183 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
184 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
185 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
186};
187
188/*
189 * All below entries generate 166 MHz for
190 * different values of vco1div2
191 */
192static struct frac_rate_tbl amba_synth_rtbl[] = {
193 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
194 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
195 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
196 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
197 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
198};
199
200/*
201 * Synthesizer Clock derived from vcodiv2. This clock is one of the
202 * possible clocks to feed cpu directly.
203 * We can program this synthesizer to make cpu run on different clock
204 * frequencies.
205 * Following table provides configuration values to let cpu run on 200,
206 * 250, 332, 400 or 500 MHz considering different possibilites of input
207 * (vco1div2) clock.
208 *
209 * --------------------------------------------------------------------
210 * vco1div2(Mhz) fout(Mhz) cpuclk = fout/2 div
211 * --------------------------------------------------------------------
212 * 400 200 100 0x04000
213 * 400 250 125 0x03333
214 * 400 332 166 0x0268D
215 * 400 400 200 0x02000
216 * --------------------------------------------------------------------
217 * 500 200 100 0x05000
218 * 500 250 125 0x04000
219 * 500 332 166 0x03031
220 * 500 400 200 0x02800
221 * 500 500 250 0x02000
222 * --------------------------------------------------------------------
223 * 664 200 100 0x06a38
224 * 664 250 125 0x054FD
225 * 664 332 166 0x04000
226 * 664 400 200 0x0351E
227 * 664 500 250 0x02A7E
228 * --------------------------------------------------------------------
229 * 800 200 100 0x08000
230 * 800 250 125 0x06666
231 * 800 332 166 0x04D18
232 * 800 400 200 0x04000
233 * 800 500 250 0x03333
234 * --------------------------------------------------------------------
235 * sys rate configuration table is in descending order of divisor.
236 */
237static struct frac_rate_tbl sys_synth_rtbl[] = {
238 {.div = 0x08000},
239 {.div = 0x06a38},
240 {.div = 0x06666},
241 {.div = 0x054FD},
242 {.div = 0x05000},
243 {.div = 0x04D18},
244 {.div = 0x04000},
245 {.div = 0x0351E},
246 {.div = 0x03333},
247 {.div = 0x03031},
248 {.div = 0x02A7E},
249 {.div = 0x02800},
250 {.div = 0x0268D},
251 {.div = 0x02000},
252};
253
254/* aux rate configuration table, in ascending order of rates */
255static struct aux_rate_tbl aux_rtbl[] = {
256 /* For VCO1div2 = 500 MHz */
257 {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
258 {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
259 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
260 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
261 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
262 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
263};
264
265/* gmac rate configuration table, in ascending order of rates */
266static struct aux_rate_tbl gmac_rtbl[] = {
267 /* For gmac phy input clk */
268 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
269 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
270 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
271 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
272};
273
274/* clcd rate configuration table, in ascending order of rates */
275static struct frac_rate_tbl clcd_rtbl[] = {
276 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
277 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
278 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
279 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
280 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
281 {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
282 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
283 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
284 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
285 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
286 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
287 {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
288 {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
289};
290
291/* i2s prescaler1 masks */
292static struct aux_clk_masks i2s_prs1_masks = {
293 .eq_sel_mask = AUX_EQ_SEL_MASK,
294 .eq_sel_shift = SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT,
295 .eq1_mask = AUX_EQ1_SEL,
296 .eq2_mask = AUX_EQ2_SEL,
297 .xscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_X_MASK,
298 .xscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_X_SHIFT,
299 .yscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_Y_MASK,
300 .yscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_Y_SHIFT,
301};
302
303/* i2s sclk (bit clock) syynthesizers masks */
304static struct aux_clk_masks i2s_sclk_masks = {
305 .eq_sel_mask = AUX_EQ_SEL_MASK,
306 .eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT,
307 .eq1_mask = AUX_EQ1_SEL,
308 .eq2_mask = AUX_EQ2_SEL,
309 .xscale_sel_mask = SPEAR1340_I2S_SCLK_X_MASK,
310 .xscale_sel_shift = SPEAR1340_I2S_SCLK_X_SHIFT,
311 .yscale_sel_mask = SPEAR1340_I2S_SCLK_Y_MASK,
312 .yscale_sel_shift = SPEAR1340_I2S_SCLK_Y_SHIFT,
313 .enable_bit = SPEAR1340_I2S_SCLK_SYNTH_ENB,
314};
315
316/* i2s prs1 aux rate configuration table, in ascending order of rates */
317static struct aux_rate_tbl i2s_prs1_rtbl[] = {
318 /* For parent clk = 49.152 MHz */
319 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
320 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
321 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
322 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
323
324 /*
325 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
326 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
327 */
328 {.xscale = 1, .yscale = 3, .eq = 0},
329
330 /* For parent clk = 49.152 MHz */
331 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
332 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/
333};
334
335/* i2s sclk aux rate configuration table, in ascending order of rates */
336static struct aux_rate_tbl i2s_sclk_rtbl[] = {
337 /* For sclk = ref_clk * x/2/y */
338 {.xscale = 1, .yscale = 4, .eq = 0},
339 {.xscale = 1, .yscale = 2, .eq = 0},
340};
341
342/* adc rate configuration table, in ascending order of rates */
343/* possible adc range is 2.5 MHz to 20 MHz. */
344static struct aux_rate_tbl adc_rtbl[] = {
345 /* For ahb = 166.67 MHz */
346 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
347 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
348 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
349 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
350};
351
352/* General synth rate configuration table, in ascending order of rates */
353static struct frac_rate_tbl gen_rtbl[] = {
354 /* For vco1div4 = 250 MHz */
355 {.div = 0x1624E}, /* 22.5792 MHz */
356 {.div = 0x14585}, /* 24.576 MHz */
357 {.div = 0x14000}, /* 25 MHz */
358 {.div = 0x0B127}, /* 45.1584 MHz */
359 {.div = 0x0A000}, /* 50 MHz */
360 {.div = 0x061A8}, /* 81.92 MHz */
361 {.div = 0x05000}, /* 100 MHz */
362 {.div = 0x02800}, /* 200 MHz */
363 {.div = 0x02620}, /* 210 MHz */
364 {.div = 0x02460}, /* 220 MHz */
365 {.div = 0x022C0}, /* 230 MHz */
366 {.div = 0x02160}, /* 240 MHz */
367 {.div = 0x02000}, /* 250 MHz */
368};
369
370/* clock parents */
371static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
372static const char *sys_parents[] = { "none", "pll1_clk", "none", "none",
373 "sys_synth_clk", "none", "pll2_clk", "pll3_clk", };
374static const char *ahb_parents[] = { "cpu_div3_clk", "amba_synth_clk", };
375static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
376static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
377 "uart0_synth_gate_clk", };
378static const char *uart1_parents[] = { "pll5_clk", "osc_24m_clk",
379 "uart1_synth_gate_clk", };
380static const char *c3_parents[] = { "pll5_clk", "c3_synth_gate_clk", };
381static const char *gmac_phy_input_parents[] = { "gmii_125m_pad_clk", "pll2_clk",
382 "osc_25m_clk", };
383static const char *gmac_phy_parents[] = { "gmac_phy_input_mux_clk",
384 "gmac_phy_synth_gate_clk", };
385static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
386static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_synth_clk", };
387static const char *i2s_src_parents[] = { "vco1div2_clk", "pll2_clk", "pll3_clk",
388 "i2s_src_pad_clk", };
389static const char *i2s_ref_parents[] = { "i2s_src_mux_clk", "i2s_prs1_clk", };
390static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_synth2_clk",
391};
392static const char *spdif_in_parents[] = { "pll2_clk", "gen_synth3_clk", };
393
394static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
395 "pll3_clk", };
396static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
397 "pll2_clk", };
398
399void __init spear1340_clk_init(void)
400{
401 struct clk *clk, *clk1;
402
403 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
404 clk_register_clkdev(clk, "apb_pclk", NULL);
405
406 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
407 32000);
408 clk_register_clkdev(clk, "osc_32k_clk", NULL);
409
410 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
411 24000000);
412 clk_register_clkdev(clk, "osc_24m_clk", NULL);
413
414 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
415 25000000);
416 clk_register_clkdev(clk, "osc_25m_clk", NULL);
417
418 clk = clk_register_fixed_rate(NULL, "gmii_125m_pad_clk", NULL,
419 CLK_IS_ROOT, 125000000);
420 clk_register_clkdev(clk, "gmii_125m_pad_clk", NULL);
421
422 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
423 CLK_IS_ROOT, 12288000);
424 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
425
426 /* clock derived from 32 KHz osc clk */
427 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
428 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0,
429 &_lock);
430 clk_register_clkdev(clk, NULL, "fc900000.rtc");
431
432 /* clock derived from 24 or 25 MHz osc clk */
433 /* vco-pll */
434 clk = clk_register_mux(NULL, "vco1_mux_clk", vco_parents,
435 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
436 SPEAR1340_PLL1_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
437 &_lock);
438 clk_register_clkdev(clk, "vco1_mux_clk", NULL);
439 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mux_clk",
440 0, SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
441 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
442 clk_register_clkdev(clk, "vco1_clk", NULL);
443 clk_register_clkdev(clk1, "pll1_clk", NULL);
444
445 clk = clk_register_mux(NULL, "vco2_mux_clk", vco_parents,
446 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
447 SPEAR1340_PLL2_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
448 &_lock);
449 clk_register_clkdev(clk, "vco2_mux_clk", NULL);
450 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mux_clk",
451 0, SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
452 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
453 clk_register_clkdev(clk, "vco2_clk", NULL);
454 clk_register_clkdev(clk1, "pll2_clk", NULL);
455
456 clk = clk_register_mux(NULL, "vco3_mux_clk", vco_parents,
457 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
458 SPEAR1340_PLL3_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
459 &_lock);
460 clk_register_clkdev(clk, "vco3_mux_clk", NULL);
461 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mux_clk",
462 0, SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
463 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
464 clk_register_clkdev(clk, "vco3_clk", NULL);
465 clk_register_clkdev(clk1, "pll3_clk", NULL);
466
467 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
468 0, SPEAR1340_PLL4_CTR, SPEAR1340_PLL4_FRQ, pll4_rtbl,
469 ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
470 clk_register_clkdev(clk, "vco4_clk", NULL);
471 clk_register_clkdev(clk1, "pll4_clk", NULL);
472
473 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
474 48000000);
475 clk_register_clkdev(clk, "pll5_clk", NULL);
476
477 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
478 25000000);
479 clk_register_clkdev(clk, "pll6_clk", NULL);
480
481 /* vco div n clocks */
482 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
483 2);
484 clk_register_clkdev(clk, "vco1div2_clk", NULL);
485
486 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
487 4);
488 clk_register_clkdev(clk, "vco1div4_clk", NULL);
489
490 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
491 2);
492 clk_register_clkdev(clk, "vco2div2_clk", NULL);
493
494 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
495 2);
496 clk_register_clkdev(clk, "vco3div2_clk", NULL);
497
498 /* peripherals */
499 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
500 128);
501 clk = clk_register_gate(NULL, "thermal_gate_clk", "thermal_clk", 0,
502 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0,
503 &_lock);
504 clk_register_clkdev(clk, NULL, "spear_thermal");
505
506 /* clock derived from pll4 clk */
507 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
508 1);
509 clk_register_clkdev(clk, "ddr_clk", NULL);
510
511 /* clock derived from pll1 clk */
512 clk = clk_register_frac("sys_synth_clk", "vco1div2_clk", 0,
513 SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl,
514 ARRAY_SIZE(sys_synth_rtbl), &_lock);
515 clk_register_clkdev(clk, "sys_synth_clk", NULL);
516
517 clk = clk_register_frac("amba_synth_clk", "vco1div2_clk", 0,
518 SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl,
519 ARRAY_SIZE(amba_synth_rtbl), &_lock);
520 clk_register_clkdev(clk, "amba_synth_clk", NULL);
521
522 clk = clk_register_mux(NULL, "sys_mux_clk", sys_parents,
523 ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL,
524 SPEAR1340_SCLK_SRC_SEL_SHIFT,
525 SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
526 clk_register_clkdev(clk, "sys_clk", NULL);
527
528 clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mux_clk", 0, 1,
529 2);
530 clk_register_clkdev(clk, "cpu_clk", NULL);
531
532 clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1,
533 3);
534 clk_register_clkdev(clk, "cpu_div3_clk", NULL);
535
536 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
537 2);
538 clk_register_clkdev(clk, NULL, "ec800620.wdt");
539
540 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
541 ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL,
542 SPEAR1340_HCLK_SRC_SEL_SHIFT,
543 SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock);
544 clk_register_clkdev(clk, "ahb_clk", NULL);
545
546 clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
547 2);
548 clk_register_clkdev(clk, "apb_clk", NULL);
549
550 /* gpt clocks */
551 clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt_parents,
552 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
553 SPEAR1340_GPT0_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
554 &_lock);
555 clk_register_clkdev(clk, "gpt0_mux_clk", NULL);
556 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mux_clk", 0,
557 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
558 &_lock);
559 clk_register_clkdev(clk, NULL, "gpt0");
560
561 clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt_parents,
562 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
563 SPEAR1340_GPT1_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
564 &_lock);
565 clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
566 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
567 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
568 &_lock);
569 clk_register_clkdev(clk, NULL, "gpt1");
570
571 clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt_parents,
572 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
573 SPEAR1340_GPT2_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
574 &_lock);
575 clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
576 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
577 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
578 &_lock);
579 clk_register_clkdev(clk, NULL, "gpt2");
580
581 clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt_parents,
582 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
583 SPEAR1340_GPT3_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
584 &_lock);
585 clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
586 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
587 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
588 &_lock);
589 clk_register_clkdev(clk, NULL, "gpt3");
590
591 /* others */
592 clk = clk_register_aux("uart0_synth_clk", "uart0_synth_gate_clk",
593 "vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL,
594 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
595 clk_register_clkdev(clk, "uart0_synth_clk", NULL);
596 clk_register_clkdev(clk1, "uart0_synth_gate_clk", NULL);
597
598 clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
599 ARRAY_SIZE(uart0_parents), 0, SPEAR1340_PERIP_CLK_CFG,
600 SPEAR1340_UART0_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
601 &_lock);
602 clk_register_clkdev(clk, "uart0_mux_clk", NULL);
603
604 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mux_clk", 0,
605 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART0_CLK_ENB, 0,
606 &_lock);
607 clk_register_clkdev(clk, NULL, "e0000000.serial");
608
609 clk = clk_register_aux("uart1_synth_clk", "uart1_synth_gate_clk",
610 "vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL,
611 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
612 clk_register_clkdev(clk, "uart1_synth_clk", NULL);
613 clk_register_clkdev(clk1, "uart1_synth_gate_clk", NULL);
614
615 clk = clk_register_mux(NULL, "uart1_mux_clk", uart1_parents,
616 ARRAY_SIZE(uart1_parents), 0, SPEAR1340_PERIP_CLK_CFG,
617 SPEAR1340_UART1_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
618 &_lock);
619 clk_register_clkdev(clk, "uart1_mux_clk", NULL);
620
621 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mux_clk", 0,
622 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
623 &_lock);
624 clk_register_clkdev(clk, NULL, "b4100000.serial");
625
626 clk = clk_register_aux("sdhci_synth_clk", "sdhci_synth_gate_clk",
627 "vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL,
628 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
629 clk_register_clkdev(clk, "sdhci_synth_clk", NULL);
630 clk_register_clkdev(clk1, "sdhci_synth_gate_clk", NULL);
631
632 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_synth_gate_clk", 0,
633 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SDHCI_CLK_ENB, 0,
634 &_lock);
635 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
636
637 clk = clk_register_aux("cfxd_synth_clk", "cfxd_synth_gate_clk",
638 "vco1div2_clk", 0, SPEAR1340_CFXD_CLK_SYNT, NULL,
639 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
640 clk_register_clkdev(clk, "cfxd_synth_clk", NULL);
641 clk_register_clkdev(clk1, "cfxd_synth_gate_clk", NULL);
642
643 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_synth_gate_clk", 0,
644 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CFXD_CLK_ENB, 0,
645 &_lock);
646 clk_register_clkdev(clk, NULL, "b2800000.cf");
647 clk_register_clkdev(clk, NULL, "arasan_xd");
648
649 clk = clk_register_aux("c3_synth_clk", "c3_synth_gate_clk",
650 "vco1div2_clk", 0, SPEAR1340_C3_CLK_SYNT, NULL,
651 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
652 clk_register_clkdev(clk, "c3_synth_clk", NULL);
653 clk_register_clkdev(clk1, "c3_synth_gate_clk", NULL);
654
655 clk = clk_register_mux(NULL, "c3_mux_clk", c3_parents,
656 ARRAY_SIZE(c3_parents), 0, SPEAR1340_PERIP_CLK_CFG,
657 SPEAR1340_C3_CLK_SHIFT, SPEAR1340_C3_CLK_MASK, 0,
658 &_lock);
659 clk_register_clkdev(clk, "c3_mux_clk", NULL);
660
661 clk = clk_register_gate(NULL, "c3_clk", "c3_mux_clk", 0,
662 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0,
663 &_lock);
664 clk_register_clkdev(clk, NULL, "c3");
665
666 /* gmac */
667 clk = clk_register_mux(NULL, "gmac_phy_input_mux_clk",
668 gmac_phy_input_parents,
669 ARRAY_SIZE(gmac_phy_input_parents), 0,
670 SPEAR1340_GMAC_CLK_CFG,
671 SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
672 SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
673 clk_register_clkdev(clk, "gmac_phy_input_mux_clk", NULL);
674
675 clk = clk_register_aux("gmac_phy_synth_clk", "gmac_phy_synth_gate_clk",
676 "gmac_phy_input_mux_clk", 0, SPEAR1340_GMAC_CLK_SYNT,
677 NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
678 clk_register_clkdev(clk, "gmac_phy_synth_clk", NULL);
679 clk_register_clkdev(clk1, "gmac_phy_synth_gate_clk", NULL);
680
681 clk = clk_register_mux(NULL, "gmac_phy_mux_clk", gmac_phy_parents,
682 ARRAY_SIZE(gmac_phy_parents), 0,
683 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
684 SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
685 clk_register_clkdev(clk, NULL, "stmmacphy.0");
686
687 /* clcd */
688 clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents,
689 ARRAY_SIZE(clcd_synth_parents), 0,
690 SPEAR1340_CLCD_CLK_SYNT, SPEAR1340_CLCD_SYNT_CLK_SHIFT,
691 SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
692 clk_register_clkdev(clk, "clcd_synth_mux_clk", NULL);
693
694 clk = clk_register_frac("clcd_synth_clk", "clcd_synth_mux_clk", 0,
695 SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl,
696 ARRAY_SIZE(clcd_rtbl), &_lock);
697 clk_register_clkdev(clk, "clcd_synth_clk", NULL);
698
699 clk = clk_register_mux(NULL, "clcd_pixel_mux_clk", clcd_pixel_parents,
700 ARRAY_SIZE(clcd_pixel_parents), 0,
701 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
702 SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
703 clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
704
705 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mux_clk", 0,
706 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0,
707 &_lock);
708 clk_register_clkdev(clk, "clcd_clk", NULL);
709
710 /* i2s */
711 clk = clk_register_mux(NULL, "i2s_src_mux_clk", i2s_src_parents,
712 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG,
713 SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK,
714 0, &_lock);
715 clk_register_clkdev(clk, "i2s_src_clk", NULL);
716
717 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mux_clk", 0,
718 SPEAR1340_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
719 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
720 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
721
722 clk = clk_register_mux(NULL, "i2s_ref_mux_clk", i2s_ref_parents,
723 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1340_I2S_CLK_CFG,
724 SPEAR1340_I2S_REF_SHIFT, SPEAR1340_I2S_REF_SEL_MASK, 0,
725 &_lock);
726 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
727
728 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mux_clk", 0,
729 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB,
730 0, &_lock);
731 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
732
733 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gate_clk",
734 "i2s_ref_mux_clk", 0, SPEAR1340_I2S_CLK_CFG,
735 &i2s_sclk_masks, i2s_sclk_rtbl,
736 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
737 clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
738 clk_register_clkdev(clk1, "i2s_sclk_gate_clk", NULL);
739
740 /* clock derived from ahb clk */
741 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
742 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C0_CLK_ENB, 0,
743 &_lock);
744 clk_register_clkdev(clk, NULL, "e0280000.i2c");
745
746 clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0,
747 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
748 &_lock);
749 clk_register_clkdev(clk, NULL, "b4000000.i2c");
750
751 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
752 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_DMA_CLK_ENB, 0,
753 &_lock);
754 clk_register_clkdev(clk, NULL, "ea800000.dma");
755 clk_register_clkdev(clk, NULL, "eb000000.dma");
756
757 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
758 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GMAC_CLK_ENB, 0,
759 &_lock);
760 clk_register_clkdev(clk, NULL, "e2000000.eth");
761
762 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
763 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_FSMC_CLK_ENB, 0,
764 &_lock);
765 clk_register_clkdev(clk, NULL, "b0000000.flash");
766
767 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
768 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SMI_CLK_ENB, 0,
769 &_lock);
770 clk_register_clkdev(clk, NULL, "ea000000.flash");
771
772 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
773 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0,
774 &_lock);
775 clk_register_clkdev(clk, "usbh.0_clk", NULL);
776
777 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
778 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0,
779 &_lock);
780 clk_register_clkdev(clk, "usbh.1_clk", NULL);
781
782 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
783 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0,
784 &_lock);
785 clk_register_clkdev(clk, NULL, "uoc");
786
787 clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
788 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
789 0, &_lock);
790 clk_register_clkdev(clk, NULL, "dw_pcie");
791 clk_register_clkdev(clk, NULL, "ahci");
792
793 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
794 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0,
795 &_lock);
796 clk_register_clkdev(clk, "sysram0_clk", NULL);
797
798 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
799 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM1_CLK_ENB, 0,
800 &_lock);
801 clk_register_clkdev(clk, "sysram1_clk", NULL);
802
803 clk = clk_register_aux("adc_synth_clk", "adc_synth_gate_clk", "ahb_clk",
804 0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl,
805 ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
806 clk_register_clkdev(clk, "adc_synth_clk", NULL);
807 clk_register_clkdev(clk1, "adc_synth_gate_clk", NULL);
808
809 clk = clk_register_gate(NULL, "adc_clk", "adc_synth_gate_clk", 0,
810 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_ADC_CLK_ENB, 0,
811 &_lock);
812 clk_register_clkdev(clk, NULL, "adc_clk");
813
814 /* clock derived from apb clk */
815 clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0,
816 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SSP_CLK_ENB, 0,
817 &_lock);
818 clk_register_clkdev(clk, NULL, "e0100000.spi");
819
820 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
821 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO0_CLK_ENB, 0,
822 &_lock);
823 clk_register_clkdev(clk, NULL, "e0600000.gpio");
824
825 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
826 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO1_CLK_ENB, 0,
827 &_lock);
828 clk_register_clkdev(clk, NULL, "e0680000.gpio");
829
830 clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0,
831 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0,
832 &_lock);
833 clk_register_clkdev(clk, NULL, "b2400000.i2s");
834
835 clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0,
836 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0,
837 &_lock);
838 clk_register_clkdev(clk, NULL, "b2000000.i2s");
839
840 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
841 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0,
842 &_lock);
843 clk_register_clkdev(clk, NULL, "e0300000.kbd");
844
845 /* RAS clks */
846 clk = clk_register_mux(NULL, "gen_synth0_1_mux_clk",
847 gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents),
848 0, SPEAR1340_PLL_CFG, SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
849 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
850 clk_register_clkdev(clk, "gen_synth0_1_clk", NULL);
851
852 clk = clk_register_mux(NULL, "gen_synth2_3_mux_clk",
853 gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents),
854 0, SPEAR1340_PLL_CFG, SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
855 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
856 clk_register_clkdev(clk, "gen_synth2_3_clk", NULL);
857
858 clk = clk_register_frac("gen_synth0_clk", "gen_synth0_1_clk", 0,
859 SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
860 &_lock);
861 clk_register_clkdev(clk, "gen_synth0_clk", NULL);
862
863 clk = clk_register_frac("gen_synth1_clk", "gen_synth0_1_clk", 0,
864 SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
865 &_lock);
866 clk_register_clkdev(clk, "gen_synth1_clk", NULL);
867
868 clk = clk_register_frac("gen_synth2_clk", "gen_synth2_3_clk", 0,
869 SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
870 &_lock);
871 clk_register_clkdev(clk, "gen_synth2_clk", NULL);
872
873 clk = clk_register_frac("gen_synth3_clk", "gen_synth2_3_clk", 0,
874 SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
875 &_lock);
876 clk_register_clkdev(clk, "gen_synth3_clk", NULL);
877
878 clk = clk_register_gate(NULL, "mali_clk", "gen_synth3_clk", 0,
879 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_MALI_CLK_ENB, 0,
880 &_lock);
881 clk_register_clkdev(clk, NULL, "mali");
882
883 clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0,
884 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC0_CLK_ENB, 0,
885 &_lock);
886 clk_register_clkdev(clk, NULL, "spear_cec.0");
887
888 clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0,
889 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC1_CLK_ENB, 0,
890 &_lock);
891 clk_register_clkdev(clk, NULL, "spear_cec.1");
892
893 clk = clk_register_mux(NULL, "spdif_out_mux_clk", spdif_out_parents,
894 ARRAY_SIZE(spdif_out_parents), 0,
895 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
896 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
897 clk_register_clkdev(clk, "spdif_out_mux_clk", NULL);
898
899 clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mux_clk", 0,
900 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_OUT_CLK_ENB,
901 0, &_lock);
902 clk_register_clkdev(clk, NULL, "spdif-out");
903
904 clk = clk_register_mux(NULL, "spdif_in_mux_clk", spdif_in_parents,
905 ARRAY_SIZE(spdif_in_parents), 0,
906 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
907 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
908 clk_register_clkdev(clk, "spdif_in_mux_clk", NULL);
909
910 clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mux_clk", 0,
911 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_IN_CLK_ENB, 0,
912 &_lock);
913 clk_register_clkdev(clk, NULL, "spdif-in");
914
915 clk = clk_register_gate(NULL, "acp_clk", "acp_mux_clk", 0,
916 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
917 &_lock);
918 clk_register_clkdev(clk, NULL, "acp_clk");
919
920 clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mux_clk", 0,
921 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
922 &_lock);
923 clk_register_clkdev(clk, NULL, "plgpio");
924
925 clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mux_clk", 0,
926 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
927 0, &_lock);
928 clk_register_clkdev(clk, NULL, "video_dec");
929
930 clk = clk_register_gate(NULL, "video_enc_clk", "video_enc_mux_clk", 0,
931 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
932 0, &_lock);
933 clk_register_clkdev(clk, NULL, "video_enc");
934
935 clk = clk_register_gate(NULL, "video_in_clk", "video_in_mux_clk", 0,
936 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
937 &_lock);
938 clk_register_clkdev(clk, NULL, "spear_vip");
939
940 clk = clk_register_gate(NULL, "cam0_clk", "cam0_mux_clk", 0,
941 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
942 &_lock);
943 clk_register_clkdev(clk, NULL, "spear_camif.0");
944
945 clk = clk_register_gate(NULL, "cam1_clk", "cam1_mux_clk", 0,
946 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
947 &_lock);
948 clk_register_clkdev(clk, NULL, "spear_camif.1");
949
950 clk = clk_register_gate(NULL, "cam2_clk", "cam2_mux_clk", 0,
951 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
952 &_lock);
953 clk_register_clkdev(clk, NULL, "spear_camif.2");
954
955 clk = clk_register_gate(NULL, "cam3_clk", "cam3_mux_clk", 0,
956 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
957 &_lock);
958 clk_register_clkdev(clk, NULL, "spear_camif.3");
959
960 clk = clk_register_gate(NULL, "pwm_clk", "pwm_mux_clk", 0,
961 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0,
962 &_lock);
963 clk_register_clkdev(clk, NULL, "pwm");
964}
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 421f6af0f995..7bb00448e13d 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2454,6 +2454,12 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
2454 }, 2454 },
2455 }, { 2455 }, {
2456 .chip = { 2456 .chip = {
2457 .base = EXYNOS5_GPC4(0),
2458 .ngpio = EXYNOS5_GPIO_C4_NR,
2459 .label = "GPC4",
2460 },
2461 }, {
2462 .chip = {
2457 .base = EXYNOS5_GPD0(0), 2463 .base = EXYNOS5_GPD0(0),
2458 .ngpio = EXYNOS5_GPIO_D0_NR, 2464 .ngpio = EXYNOS5_GPIO_D0_NR,
2459 .label = "GPD0", 2465 .label = "GPD0",
@@ -2826,8 +2832,11 @@ static __init void exynos5_gpiolib_init(void)
2826 goto err_ioremap1; 2832 goto err_ioremap1;
2827 } 2833 }
2828 2834
2835 /* need to set base address for gpc4 */
2836 exonys5_gpios_1[11].base = gpio_base1 + 0x2E0;
2837
2829 /* need to set base address for gpx */ 2838 /* need to set base address for gpx */
2830 chip = &exynos5_gpios_1[20]; 2839 chip = &exynos5_gpios_1[21];
2831 gpx_base = gpio_base1 + 0xC00; 2840 gpx_base = gpio_base1 + 0xC00;
2832 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20) 2841 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2833 chip->base = gpx_base; 2842 chip->base = gpx_base;
diff --git a/drivers/pinctrl/spear/Kconfig b/drivers/pinctrl/spear/Kconfig
index 6a2596b4f359..91558791e766 100644
--- a/drivers/pinctrl/spear/Kconfig
+++ b/drivers/pinctrl/spear/Kconfig
@@ -31,4 +31,14 @@ config PINCTRL_SPEAR320
31 depends on MACH_SPEAR320 31 depends on MACH_SPEAR320
32 select PINCTRL_SPEAR3XX 32 select PINCTRL_SPEAR3XX
33 33
34config PINCTRL_SPEAR1310
35 bool "ST Microelectronics SPEAr1310 SoC pin controller driver"
36 depends on MACH_SPEAR1310
37 select PINCTRL_SPEAR
38
39config PINCTRL_SPEAR1340
40 bool "ST Microelectronics SPEAr1340 SoC pin controller driver"
41 depends on MACH_SPEAR1340
42 select PINCTRL_SPEAR
43
34endif 44endif
diff --git a/drivers/pinctrl/spear/Makefile b/drivers/pinctrl/spear/Makefile
index 15dcb85da22d..b28a7ba22443 100644
--- a/drivers/pinctrl/spear/Makefile
+++ b/drivers/pinctrl/spear/Makefile
@@ -5,3 +5,5 @@ obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o
5obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o 5obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o
6obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o 6obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o
7obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o 7obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o
8obj-$(CONFIG_PINCTRL_SPEAR1310) += pinctrl-spear1310.o
9obj-$(CONFIG_PINCTRL_SPEAR1340) += pinctrl-spear1340.o
diff --git a/drivers/pinctrl/spear/pinctrl-spear.h b/drivers/pinctrl/spear/pinctrl-spear.h
index 47a6b5b72f90..9155783bb47f 100644
--- a/drivers/pinctrl/spear/pinctrl-spear.h
+++ b/drivers/pinctrl/spear/pinctrl-spear.h
@@ -139,4 +139,255 @@ void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
139int __devinit spear_pinctrl_probe(struct platform_device *pdev, 139int __devinit spear_pinctrl_probe(struct platform_device *pdev,
140 struct spear_pinctrl_machdata *machdata); 140 struct spear_pinctrl_machdata *machdata);
141int __devexit spear_pinctrl_remove(struct platform_device *pdev); 141int __devexit spear_pinctrl_remove(struct platform_device *pdev);
142
143#define SPEAR_PIN_0_TO_101 \
144 PINCTRL_PIN(0, "PLGPIO0"), \
145 PINCTRL_PIN(1, "PLGPIO1"), \
146 PINCTRL_PIN(2, "PLGPIO2"), \
147 PINCTRL_PIN(3, "PLGPIO3"), \
148 PINCTRL_PIN(4, "PLGPIO4"), \
149 PINCTRL_PIN(5, "PLGPIO5"), \
150 PINCTRL_PIN(6, "PLGPIO6"), \
151 PINCTRL_PIN(7, "PLGPIO7"), \
152 PINCTRL_PIN(8, "PLGPIO8"), \
153 PINCTRL_PIN(9, "PLGPIO9"), \
154 PINCTRL_PIN(10, "PLGPIO10"), \
155 PINCTRL_PIN(11, "PLGPIO11"), \
156 PINCTRL_PIN(12, "PLGPIO12"), \
157 PINCTRL_PIN(13, "PLGPIO13"), \
158 PINCTRL_PIN(14, "PLGPIO14"), \
159 PINCTRL_PIN(15, "PLGPIO15"), \
160 PINCTRL_PIN(16, "PLGPIO16"), \
161 PINCTRL_PIN(17, "PLGPIO17"), \
162 PINCTRL_PIN(18, "PLGPIO18"), \
163 PINCTRL_PIN(19, "PLGPIO19"), \
164 PINCTRL_PIN(20, "PLGPIO20"), \
165 PINCTRL_PIN(21, "PLGPIO21"), \
166 PINCTRL_PIN(22, "PLGPIO22"), \
167 PINCTRL_PIN(23, "PLGPIO23"), \
168 PINCTRL_PIN(24, "PLGPIO24"), \
169 PINCTRL_PIN(25, "PLGPIO25"), \
170 PINCTRL_PIN(26, "PLGPIO26"), \
171 PINCTRL_PIN(27, "PLGPIO27"), \
172 PINCTRL_PIN(28, "PLGPIO28"), \
173 PINCTRL_PIN(29, "PLGPIO29"), \
174 PINCTRL_PIN(30, "PLGPIO30"), \
175 PINCTRL_PIN(31, "PLGPIO31"), \
176 PINCTRL_PIN(32, "PLGPIO32"), \
177 PINCTRL_PIN(33, "PLGPIO33"), \
178 PINCTRL_PIN(34, "PLGPIO34"), \
179 PINCTRL_PIN(35, "PLGPIO35"), \
180 PINCTRL_PIN(36, "PLGPIO36"), \
181 PINCTRL_PIN(37, "PLGPIO37"), \
182 PINCTRL_PIN(38, "PLGPIO38"), \
183 PINCTRL_PIN(39, "PLGPIO39"), \
184 PINCTRL_PIN(40, "PLGPIO40"), \
185 PINCTRL_PIN(41, "PLGPIO41"), \
186 PINCTRL_PIN(42, "PLGPIO42"), \
187 PINCTRL_PIN(43, "PLGPIO43"), \
188 PINCTRL_PIN(44, "PLGPIO44"), \
189 PINCTRL_PIN(45, "PLGPIO45"), \
190 PINCTRL_PIN(46, "PLGPIO46"), \
191 PINCTRL_PIN(47, "PLGPIO47"), \
192 PINCTRL_PIN(48, "PLGPIO48"), \
193 PINCTRL_PIN(49, "PLGPIO49"), \
194 PINCTRL_PIN(50, "PLGPIO50"), \
195 PINCTRL_PIN(51, "PLGPIO51"), \
196 PINCTRL_PIN(52, "PLGPIO52"), \
197 PINCTRL_PIN(53, "PLGPIO53"), \
198 PINCTRL_PIN(54, "PLGPIO54"), \
199 PINCTRL_PIN(55, "PLGPIO55"), \
200 PINCTRL_PIN(56, "PLGPIO56"), \
201 PINCTRL_PIN(57, "PLGPIO57"), \
202 PINCTRL_PIN(58, "PLGPIO58"), \
203 PINCTRL_PIN(59, "PLGPIO59"), \
204 PINCTRL_PIN(60, "PLGPIO60"), \
205 PINCTRL_PIN(61, "PLGPIO61"), \
206 PINCTRL_PIN(62, "PLGPIO62"), \
207 PINCTRL_PIN(63, "PLGPIO63"), \
208 PINCTRL_PIN(64, "PLGPIO64"), \
209 PINCTRL_PIN(65, "PLGPIO65"), \
210 PINCTRL_PIN(66, "PLGPIO66"), \
211 PINCTRL_PIN(67, "PLGPIO67"), \
212 PINCTRL_PIN(68, "PLGPIO68"), \
213 PINCTRL_PIN(69, "PLGPIO69"), \
214 PINCTRL_PIN(70, "PLGPIO70"), \
215 PINCTRL_PIN(71, "PLGPIO71"), \
216 PINCTRL_PIN(72, "PLGPIO72"), \
217 PINCTRL_PIN(73, "PLGPIO73"), \
218 PINCTRL_PIN(74, "PLGPIO74"), \
219 PINCTRL_PIN(75, "PLGPIO75"), \
220 PINCTRL_PIN(76, "PLGPIO76"), \
221 PINCTRL_PIN(77, "PLGPIO77"), \
222 PINCTRL_PIN(78, "PLGPIO78"), \
223 PINCTRL_PIN(79, "PLGPIO79"), \
224 PINCTRL_PIN(80, "PLGPIO80"), \
225 PINCTRL_PIN(81, "PLGPIO81"), \
226 PINCTRL_PIN(82, "PLGPIO82"), \
227 PINCTRL_PIN(83, "PLGPIO83"), \
228 PINCTRL_PIN(84, "PLGPIO84"), \
229 PINCTRL_PIN(85, "PLGPIO85"), \
230 PINCTRL_PIN(86, "PLGPIO86"), \
231 PINCTRL_PIN(87, "PLGPIO87"), \
232 PINCTRL_PIN(88, "PLGPIO88"), \
233 PINCTRL_PIN(89, "PLGPIO89"), \
234 PINCTRL_PIN(90, "PLGPIO90"), \
235 PINCTRL_PIN(91, "PLGPIO91"), \
236 PINCTRL_PIN(92, "PLGPIO92"), \
237 PINCTRL_PIN(93, "PLGPIO93"), \
238 PINCTRL_PIN(94, "PLGPIO94"), \
239 PINCTRL_PIN(95, "PLGPIO95"), \
240 PINCTRL_PIN(96, "PLGPIO96"), \
241 PINCTRL_PIN(97, "PLGPIO97"), \
242 PINCTRL_PIN(98, "PLGPIO98"), \
243 PINCTRL_PIN(99, "PLGPIO99"), \
244 PINCTRL_PIN(100, "PLGPIO100"), \
245 PINCTRL_PIN(101, "PLGPIO101")
246
247#define SPEAR_PIN_102_TO_245 \
248 PINCTRL_PIN(102, "PLGPIO102"), \
249 PINCTRL_PIN(103, "PLGPIO103"), \
250 PINCTRL_PIN(104, "PLGPIO104"), \
251 PINCTRL_PIN(105, "PLGPIO105"), \
252 PINCTRL_PIN(106, "PLGPIO106"), \
253 PINCTRL_PIN(107, "PLGPIO107"), \
254 PINCTRL_PIN(108, "PLGPIO108"), \
255 PINCTRL_PIN(109, "PLGPIO109"), \
256 PINCTRL_PIN(110, "PLGPIO110"), \
257 PINCTRL_PIN(111, "PLGPIO111"), \
258 PINCTRL_PIN(112, "PLGPIO112"), \
259 PINCTRL_PIN(113, "PLGPIO113"), \
260 PINCTRL_PIN(114, "PLGPIO114"), \
261 PINCTRL_PIN(115, "PLGPIO115"), \
262 PINCTRL_PIN(116, "PLGPIO116"), \
263 PINCTRL_PIN(117, "PLGPIO117"), \
264 PINCTRL_PIN(118, "PLGPIO118"), \
265 PINCTRL_PIN(119, "PLGPIO119"), \
266 PINCTRL_PIN(120, "PLGPIO120"), \
267 PINCTRL_PIN(121, "PLGPIO121"), \
268 PINCTRL_PIN(122, "PLGPIO122"), \
269 PINCTRL_PIN(123, "PLGPIO123"), \
270 PINCTRL_PIN(124, "PLGPIO124"), \
271 PINCTRL_PIN(125, "PLGPIO125"), \
272 PINCTRL_PIN(126, "PLGPIO126"), \
273 PINCTRL_PIN(127, "PLGPIO127"), \
274 PINCTRL_PIN(128, "PLGPIO128"), \
275 PINCTRL_PIN(129, "PLGPIO129"), \
276 PINCTRL_PIN(130, "PLGPIO130"), \
277 PINCTRL_PIN(131, "PLGPIO131"), \
278 PINCTRL_PIN(132, "PLGPIO132"), \
279 PINCTRL_PIN(133, "PLGPIO133"), \
280 PINCTRL_PIN(134, "PLGPIO134"), \
281 PINCTRL_PIN(135, "PLGPIO135"), \
282 PINCTRL_PIN(136, "PLGPIO136"), \
283 PINCTRL_PIN(137, "PLGPIO137"), \
284 PINCTRL_PIN(138, "PLGPIO138"), \
285 PINCTRL_PIN(139, "PLGPIO139"), \
286 PINCTRL_PIN(140, "PLGPIO140"), \
287 PINCTRL_PIN(141, "PLGPIO141"), \
288 PINCTRL_PIN(142, "PLGPIO142"), \
289 PINCTRL_PIN(143, "PLGPIO143"), \
290 PINCTRL_PIN(144, "PLGPIO144"), \
291 PINCTRL_PIN(145, "PLGPIO145"), \
292 PINCTRL_PIN(146, "PLGPIO146"), \
293 PINCTRL_PIN(147, "PLGPIO147"), \
294 PINCTRL_PIN(148, "PLGPIO148"), \
295 PINCTRL_PIN(149, "PLGPIO149"), \
296 PINCTRL_PIN(150, "PLGPIO150"), \
297 PINCTRL_PIN(151, "PLGPIO151"), \
298 PINCTRL_PIN(152, "PLGPIO152"), \
299 PINCTRL_PIN(153, "PLGPIO153"), \
300 PINCTRL_PIN(154, "PLGPIO154"), \
301 PINCTRL_PIN(155, "PLGPIO155"), \
302 PINCTRL_PIN(156, "PLGPIO156"), \
303 PINCTRL_PIN(157, "PLGPIO157"), \
304 PINCTRL_PIN(158, "PLGPIO158"), \
305 PINCTRL_PIN(159, "PLGPIO159"), \
306 PINCTRL_PIN(160, "PLGPIO160"), \
307 PINCTRL_PIN(161, "PLGPIO161"), \
308 PINCTRL_PIN(162, "PLGPIO162"), \
309 PINCTRL_PIN(163, "PLGPIO163"), \
310 PINCTRL_PIN(164, "PLGPIO164"), \
311 PINCTRL_PIN(165, "PLGPIO165"), \
312 PINCTRL_PIN(166, "PLGPIO166"), \
313 PINCTRL_PIN(167, "PLGPIO167"), \
314 PINCTRL_PIN(168, "PLGPIO168"), \
315 PINCTRL_PIN(169, "PLGPIO169"), \
316 PINCTRL_PIN(170, "PLGPIO170"), \
317 PINCTRL_PIN(171, "PLGPIO171"), \
318 PINCTRL_PIN(172, "PLGPIO172"), \
319 PINCTRL_PIN(173, "PLGPIO173"), \
320 PINCTRL_PIN(174, "PLGPIO174"), \
321 PINCTRL_PIN(175, "PLGPIO175"), \
322 PINCTRL_PIN(176, "PLGPIO176"), \
323 PINCTRL_PIN(177, "PLGPIO177"), \
324 PINCTRL_PIN(178, "PLGPIO178"), \
325 PINCTRL_PIN(179, "PLGPIO179"), \
326 PINCTRL_PIN(180, "PLGPIO180"), \
327 PINCTRL_PIN(181, "PLGPIO181"), \
328 PINCTRL_PIN(182, "PLGPIO182"), \
329 PINCTRL_PIN(183, "PLGPIO183"), \
330 PINCTRL_PIN(184, "PLGPIO184"), \
331 PINCTRL_PIN(185, "PLGPIO185"), \
332 PINCTRL_PIN(186, "PLGPIO186"), \
333 PINCTRL_PIN(187, "PLGPIO187"), \
334 PINCTRL_PIN(188, "PLGPIO188"), \
335 PINCTRL_PIN(189, "PLGPIO189"), \
336 PINCTRL_PIN(190, "PLGPIO190"), \
337 PINCTRL_PIN(191, "PLGPIO191"), \
338 PINCTRL_PIN(192, "PLGPIO192"), \
339 PINCTRL_PIN(193, "PLGPIO193"), \
340 PINCTRL_PIN(194, "PLGPIO194"), \
341 PINCTRL_PIN(195, "PLGPIO195"), \
342 PINCTRL_PIN(196, "PLGPIO196"), \
343 PINCTRL_PIN(197, "PLGPIO197"), \
344 PINCTRL_PIN(198, "PLGPIO198"), \
345 PINCTRL_PIN(199, "PLGPIO199"), \
346 PINCTRL_PIN(200, "PLGPIO200"), \
347 PINCTRL_PIN(201, "PLGPIO201"), \
348 PINCTRL_PIN(202, "PLGPIO202"), \
349 PINCTRL_PIN(203, "PLGPIO203"), \
350 PINCTRL_PIN(204, "PLGPIO204"), \
351 PINCTRL_PIN(205, "PLGPIO205"), \
352 PINCTRL_PIN(206, "PLGPIO206"), \
353 PINCTRL_PIN(207, "PLGPIO207"), \
354 PINCTRL_PIN(208, "PLGPIO208"), \
355 PINCTRL_PIN(209, "PLGPIO209"), \
356 PINCTRL_PIN(210, "PLGPIO210"), \
357 PINCTRL_PIN(211, "PLGPIO211"), \
358 PINCTRL_PIN(212, "PLGPIO212"), \
359 PINCTRL_PIN(213, "PLGPIO213"), \
360 PINCTRL_PIN(214, "PLGPIO214"), \
361 PINCTRL_PIN(215, "PLGPIO215"), \
362 PINCTRL_PIN(216, "PLGPIO216"), \
363 PINCTRL_PIN(217, "PLGPIO217"), \
364 PINCTRL_PIN(218, "PLGPIO218"), \
365 PINCTRL_PIN(219, "PLGPIO219"), \
366 PINCTRL_PIN(220, "PLGPIO220"), \
367 PINCTRL_PIN(221, "PLGPIO221"), \
368 PINCTRL_PIN(222, "PLGPIO222"), \
369 PINCTRL_PIN(223, "PLGPIO223"), \
370 PINCTRL_PIN(224, "PLGPIO224"), \
371 PINCTRL_PIN(225, "PLGPIO225"), \
372 PINCTRL_PIN(226, "PLGPIO226"), \
373 PINCTRL_PIN(227, "PLGPIO227"), \
374 PINCTRL_PIN(228, "PLGPIO228"), \
375 PINCTRL_PIN(229, "PLGPIO229"), \
376 PINCTRL_PIN(230, "PLGPIO230"), \
377 PINCTRL_PIN(231, "PLGPIO231"), \
378 PINCTRL_PIN(232, "PLGPIO232"), \
379 PINCTRL_PIN(233, "PLGPIO233"), \
380 PINCTRL_PIN(234, "PLGPIO234"), \
381 PINCTRL_PIN(235, "PLGPIO235"), \
382 PINCTRL_PIN(236, "PLGPIO236"), \
383 PINCTRL_PIN(237, "PLGPIO237"), \
384 PINCTRL_PIN(238, "PLGPIO238"), \
385 PINCTRL_PIN(239, "PLGPIO239"), \
386 PINCTRL_PIN(240, "PLGPIO240"), \
387 PINCTRL_PIN(241, "PLGPIO241"), \
388 PINCTRL_PIN(242, "PLGPIO242"), \
389 PINCTRL_PIN(243, "PLGPIO243"), \
390 PINCTRL_PIN(244, "PLGPIO244"), \
391 PINCTRL_PIN(245, "PLGPIO245")
392
142#endif /* __PINMUX_SPEAR_H__ */ 393#endif /* __PINMUX_SPEAR_H__ */
diff --git a/drivers/pinctrl/spear/pinctrl-spear1310.c b/drivers/pinctrl/spear/pinctrl-spear1310.c
new file mode 100644
index 000000000000..fff168be7f00
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear1310.c
@@ -0,0 +1,2198 @@
1/*
2 * Driver for the ST Microelectronics SPEAr1310 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear.h"
18
19#define DRIVER_NAME "spear1310-pinmux"
20
21/* pins */
22static const struct pinctrl_pin_desc spear1310_pins[] = {
23 SPEAR_PIN_0_TO_101,
24 SPEAR_PIN_102_TO_245,
25};
26
27/* registers */
28#define PERIP_CFG 0x32C
29 #define MCIF_SEL_SHIFT 3
30 #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT)
31 #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT)
32 #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT)
33 #define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT)
34
35#define PCIE_SATA_CFG 0x3A4
36 #define PCIE_SATA2_SEL_PCIE (0 << 31)
37 #define PCIE_SATA1_SEL_PCIE (0 << 30)
38 #define PCIE_SATA0_SEL_PCIE (0 << 29)
39 #define PCIE_SATA2_SEL_SATA (1 << 31)
40 #define PCIE_SATA1_SEL_SATA (1 << 30)
41 #define PCIE_SATA0_SEL_SATA (1 << 29)
42 #define SATA2_CFG_TX_CLK_EN (1 << 27)
43 #define SATA2_CFG_RX_CLK_EN (1 << 26)
44 #define SATA2_CFG_POWERUP_RESET (1 << 25)
45 #define SATA2_CFG_PM_CLK_EN (1 << 24)
46 #define SATA1_CFG_TX_CLK_EN (1 << 23)
47 #define SATA1_CFG_RX_CLK_EN (1 << 22)
48 #define SATA1_CFG_POWERUP_RESET (1 << 21)
49 #define SATA1_CFG_PM_CLK_EN (1 << 20)
50 #define SATA0_CFG_TX_CLK_EN (1 << 19)
51 #define SATA0_CFG_RX_CLK_EN (1 << 18)
52 #define SATA0_CFG_POWERUP_RESET (1 << 17)
53 #define SATA0_CFG_PM_CLK_EN (1 << 16)
54 #define PCIE2_CFG_DEVICE_PRESENT (1 << 11)
55 #define PCIE2_CFG_POWERUP_RESET (1 << 10)
56 #define PCIE2_CFG_CORE_CLK_EN (1 << 9)
57 #define PCIE2_CFG_AUX_CLK_EN (1 << 8)
58 #define PCIE1_CFG_DEVICE_PRESENT (1 << 7)
59 #define PCIE1_CFG_POWERUP_RESET (1 << 6)
60 #define PCIE1_CFG_CORE_CLK_EN (1 << 5)
61 #define PCIE1_CFG_AUX_CLK_EN (1 << 4)
62 #define PCIE0_CFG_DEVICE_PRESENT (1 << 3)
63 #define PCIE0_CFG_POWERUP_RESET (1 << 2)
64 #define PCIE0_CFG_CORE_CLK_EN (1 << 1)
65 #define PCIE0_CFG_AUX_CLK_EN (1 << 0)
66
67#define PAD_FUNCTION_EN_0 0x650
68 #define PMX_UART0_MASK (1 << 1)
69 #define PMX_I2C0_MASK (1 << 2)
70 #define PMX_I2S0_MASK (1 << 3)
71 #define PMX_SSP0_MASK (1 << 4)
72 #define PMX_CLCD1_MASK (1 << 5)
73 #define PMX_EGPIO00_MASK (1 << 6)
74 #define PMX_EGPIO01_MASK (1 << 7)
75 #define PMX_EGPIO02_MASK (1 << 8)
76 #define PMX_EGPIO03_MASK (1 << 9)
77 #define PMX_EGPIO04_MASK (1 << 10)
78 #define PMX_EGPIO05_MASK (1 << 11)
79 #define PMX_EGPIO06_MASK (1 << 12)
80 #define PMX_EGPIO07_MASK (1 << 13)
81 #define PMX_EGPIO08_MASK (1 << 14)
82 #define PMX_EGPIO09_MASK (1 << 15)
83 #define PMX_SMI_MASK (1 << 16)
84 #define PMX_NAND8_MASK (1 << 17)
85 #define PMX_GMIICLK_MASK (1 << 18)
86 #define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19)
87 #define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20)
88 #define PMX_GMIID47_MASK (1 << 21)
89 #define PMX_MDC_MDIO_MASK (1 << 22)
90 #define PMX_MCI_DATA8_15_MASK (1 << 23)
91 #define PMX_NFAD23_MASK (1 << 24)
92 #define PMX_NFAD24_MASK (1 << 25)
93 #define PMX_NFAD25_MASK (1 << 26)
94 #define PMX_NFCE3_MASK (1 << 27)
95 #define PMX_NFWPRT3_MASK (1 << 28)
96 #define PMX_NFRSTPWDWN0_MASK (1 << 29)
97 #define PMX_NFRSTPWDWN1_MASK (1 << 30)
98 #define PMX_NFRSTPWDWN2_MASK (1 << 31)
99
100#define PAD_FUNCTION_EN_1 0x654
101 #define PMX_NFRSTPWDWN3_MASK (1 << 0)
102 #define PMX_SMINCS2_MASK (1 << 1)
103 #define PMX_SMINCS3_MASK (1 << 2)
104 #define PMX_CLCD2_MASK (1 << 3)
105 #define PMX_KBD_ROWCOL68_MASK (1 << 4)
106 #define PMX_EGPIO10_MASK (1 << 5)
107 #define PMX_EGPIO11_MASK (1 << 6)
108 #define PMX_EGPIO12_MASK (1 << 7)
109 #define PMX_EGPIO13_MASK (1 << 8)
110 #define PMX_EGPIO14_MASK (1 << 9)
111 #define PMX_EGPIO15_MASK (1 << 10)
112 #define PMX_UART0_MODEM_MASK (1 << 11)
113 #define PMX_GPT0_TMR0_MASK (1 << 12)
114 #define PMX_GPT0_TMR1_MASK (1 << 13)
115 #define PMX_GPT1_TMR0_MASK (1 << 14)
116 #define PMX_GPT1_TMR1_MASK (1 << 15)
117 #define PMX_I2S1_MASK (1 << 16)
118 #define PMX_KBD_ROWCOL25_MASK (1 << 17)
119 #define PMX_NFIO8_15_MASK (1 << 18)
120 #define PMX_KBD_COL1_MASK (1 << 19)
121 #define PMX_NFCE1_MASK (1 << 20)
122 #define PMX_KBD_COL0_MASK (1 << 21)
123 #define PMX_NFCE2_MASK (1 << 22)
124 #define PMX_KBD_ROW1_MASK (1 << 23)
125 #define PMX_NFWPRT1_MASK (1 << 24)
126 #define PMX_KBD_ROW0_MASK (1 << 25)
127 #define PMX_NFWPRT2_MASK (1 << 26)
128 #define PMX_MCIDATA0_MASK (1 << 27)
129 #define PMX_MCIDATA1_MASK (1 << 28)
130 #define PMX_MCIDATA2_MASK (1 << 29)
131 #define PMX_MCIDATA3_MASK (1 << 30)
132 #define PMX_MCIDATA4_MASK (1 << 31)
133
134#define PAD_FUNCTION_EN_2 0x658
135 #define PMX_MCIDATA5_MASK (1 << 0)
136 #define PMX_MCIDATA6_MASK (1 << 1)
137 #define PMX_MCIDATA7_MASK (1 << 2)
138 #define PMX_MCIDATA1SD_MASK (1 << 3)
139 #define PMX_MCIDATA2SD_MASK (1 << 4)
140 #define PMX_MCIDATA3SD_MASK (1 << 5)
141 #define PMX_MCIADDR0ALE_MASK (1 << 6)
142 #define PMX_MCIADDR1CLECLK_MASK (1 << 7)
143 #define PMX_MCIADDR2_MASK (1 << 8)
144 #define PMX_MCICECF_MASK (1 << 9)
145 #define PMX_MCICEXD_MASK (1 << 10)
146 #define PMX_MCICESDMMC_MASK (1 << 11)
147 #define PMX_MCICDCF1_MASK (1 << 12)
148 #define PMX_MCICDCF2_MASK (1 << 13)
149 #define PMX_MCICDXD_MASK (1 << 14)
150 #define PMX_MCICDSDMMC_MASK (1 << 15)
151 #define PMX_MCIDATADIR_MASK (1 << 16)
152 #define PMX_MCIDMARQWP_MASK (1 << 17)
153 #define PMX_MCIIORDRE_MASK (1 << 18)
154 #define PMX_MCIIOWRWE_MASK (1 << 19)
155 #define PMX_MCIRESETCF_MASK (1 << 20)
156 #define PMX_MCICS0CE_MASK (1 << 21)
157 #define PMX_MCICFINTR_MASK (1 << 22)
158 #define PMX_MCIIORDY_MASK (1 << 23)
159 #define PMX_MCICS1_MASK (1 << 24)
160 #define PMX_MCIDMAACK_MASK (1 << 25)
161 #define PMX_MCISDCMD_MASK (1 << 26)
162 #define PMX_MCILEDS_MASK (1 << 27)
163 #define PMX_TOUCH_XY_MASK (1 << 28)
164 #define PMX_SSP0_CS0_MASK (1 << 29)
165 #define PMX_SSP0_CS1_2_MASK (1 << 30)
166
167/* combined macros */
168#define PMX_GMII_MASK (PMX_GMIICLK_MASK | \
169 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
170 PMX_RXCLK_RDV_TXEN_D03_MASK | \
171 PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK)
172
173#define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \
174 PMX_EGPIO02_MASK | \
175 PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \
176 PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \
177 PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \
178 PMX_EGPIO09_MASK)
179#define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \
180 PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \
181 PMX_EGPIO14_MASK | PMX_EGPIO15_MASK)
182
183#define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
184 PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \
185 PMX_KBD_COL1_MASK)
186
187#define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \
188 PMX_NFAD24_MASK | PMX_NFAD25_MASK | \
189 PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \
190 PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \
191 PMX_NFCE3_MASK)
192#define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK
193
194#define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK)
195#define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \
196 PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \
197 PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
198 PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
199
200#define PMX_MCIFALL_1_MASK 0xF8000000
201#define PMX_MCIFALL_2_MASK 0x0FFFFFFF
202
203#define PMX_PCI_REG1_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \
204 PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
205 PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \
206 PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \
207 PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \
208 PMX_NFCE2_MASK)
209#define PMX_PCI_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
210 PMX_SSP0_CS1_2_MASK)
211
212#define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK)
213#define PMX_RGMII_REG0_MASK (PMX_MCI_DATA8_15_MASK | \
214 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
215 PMX_GMIID47_MASK)
216#define PMX_RGMII_REG1_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\
217 PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \
218 PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK)
219#define PMX_RGMII_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
220 PMX_SSP0_CS1_2_MASK)
221
222#define PCIE_CFG_VAL(x) (PCIE_SATA##x##_SEL_PCIE | \
223 PCIE##x##_CFG_AUX_CLK_EN | \
224 PCIE##x##_CFG_CORE_CLK_EN | \
225 PCIE##x##_CFG_POWERUP_RESET | \
226 PCIE##x##_CFG_DEVICE_PRESENT)
227#define SATA_CFG_VAL(x) (PCIE_SATA##x##_SEL_SATA | \
228 SATA##x##_CFG_PM_CLK_EN | \
229 SATA##x##_CFG_POWERUP_RESET | \
230 SATA##x##_CFG_RX_CLK_EN | \
231 SATA##x##_CFG_TX_CLK_EN)
232
233/* Pad multiplexing for i2c0 device */
234static const unsigned i2c0_pins[] = { 102, 103 };
235static struct spear_muxreg i2c0_muxreg[] = {
236 {
237 .reg = PAD_FUNCTION_EN_0,
238 .mask = PMX_I2C0_MASK,
239 .val = PMX_I2C0_MASK,
240 },
241};
242
243static struct spear_modemux i2c0_modemux[] = {
244 {
245 .muxregs = i2c0_muxreg,
246 .nmuxregs = ARRAY_SIZE(i2c0_muxreg),
247 },
248};
249
250static struct spear_pingroup i2c0_pingroup = {
251 .name = "i2c0_grp",
252 .pins = i2c0_pins,
253 .npins = ARRAY_SIZE(i2c0_pins),
254 .modemuxs = i2c0_modemux,
255 .nmodemuxs = ARRAY_SIZE(i2c0_modemux),
256};
257
258static const char *const i2c0_grps[] = { "i2c0_grp" };
259static struct spear_function i2c0_function = {
260 .name = "i2c0",
261 .groups = i2c0_grps,
262 .ngroups = ARRAY_SIZE(i2c0_grps),
263};
264
265/* Pad multiplexing for ssp0 device */
266static const unsigned ssp0_pins[] = { 109, 110, 111, 112 };
267static struct spear_muxreg ssp0_muxreg[] = {
268 {
269 .reg = PAD_FUNCTION_EN_0,
270 .mask = PMX_SSP0_MASK,
271 .val = PMX_SSP0_MASK,
272 },
273};
274
275static struct spear_modemux ssp0_modemux[] = {
276 {
277 .muxregs = ssp0_muxreg,
278 .nmuxregs = ARRAY_SIZE(ssp0_muxreg),
279 },
280};
281
282static struct spear_pingroup ssp0_pingroup = {
283 .name = "ssp0_grp",
284 .pins = ssp0_pins,
285 .npins = ARRAY_SIZE(ssp0_pins),
286 .modemuxs = ssp0_modemux,
287 .nmodemuxs = ARRAY_SIZE(ssp0_modemux),
288};
289
290/* Pad multiplexing for ssp0_cs0 device */
291static const unsigned ssp0_cs0_pins[] = { 96 };
292static struct spear_muxreg ssp0_cs0_muxreg[] = {
293 {
294 .reg = PAD_FUNCTION_EN_2,
295 .mask = PMX_SSP0_CS0_MASK,
296 .val = PMX_SSP0_CS0_MASK,
297 },
298};
299
300static struct spear_modemux ssp0_cs0_modemux[] = {
301 {
302 .muxregs = ssp0_cs0_muxreg,
303 .nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg),
304 },
305};
306
307static struct spear_pingroup ssp0_cs0_pingroup = {
308 .name = "ssp0_cs0_grp",
309 .pins = ssp0_cs0_pins,
310 .npins = ARRAY_SIZE(ssp0_cs0_pins),
311 .modemuxs = ssp0_cs0_modemux,
312 .nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux),
313};
314
315/* ssp0_cs1_2 device */
316static const unsigned ssp0_cs1_2_pins[] = { 94, 95 };
317static struct spear_muxreg ssp0_cs1_2_muxreg[] = {
318 {
319 .reg = PAD_FUNCTION_EN_2,
320 .mask = PMX_SSP0_CS1_2_MASK,
321 .val = PMX_SSP0_CS1_2_MASK,
322 },
323};
324
325static struct spear_modemux ssp0_cs1_2_modemux[] = {
326 {
327 .muxregs = ssp0_cs1_2_muxreg,
328 .nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg),
329 },
330};
331
332static struct spear_pingroup ssp0_cs1_2_pingroup = {
333 .name = "ssp0_cs1_2_grp",
334 .pins = ssp0_cs1_2_pins,
335 .npins = ARRAY_SIZE(ssp0_cs1_2_pins),
336 .modemuxs = ssp0_cs1_2_modemux,
337 .nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux),
338};
339
340static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp",
341 "ssp0_cs1_2_grp" };
342static struct spear_function ssp0_function = {
343 .name = "ssp0",
344 .groups = ssp0_grps,
345 .ngroups = ARRAY_SIZE(ssp0_grps),
346};
347
348/* Pad multiplexing for i2s0 device */
349static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 };
350static struct spear_muxreg i2s0_muxreg[] = {
351 {
352 .reg = PAD_FUNCTION_EN_0,
353 .mask = PMX_I2S0_MASK,
354 .val = PMX_I2S0_MASK,
355 },
356};
357
358static struct spear_modemux i2s0_modemux[] = {
359 {
360 .muxregs = i2s0_muxreg,
361 .nmuxregs = ARRAY_SIZE(i2s0_muxreg),
362 },
363};
364
365static struct spear_pingroup i2s0_pingroup = {
366 .name = "i2s0_grp",
367 .pins = i2s0_pins,
368 .npins = ARRAY_SIZE(i2s0_pins),
369 .modemuxs = i2s0_modemux,
370 .nmodemuxs = ARRAY_SIZE(i2s0_modemux),
371};
372
373static const char *const i2s0_grps[] = { "i2s0_grp" };
374static struct spear_function i2s0_function = {
375 .name = "i2s0",
376 .groups = i2s0_grps,
377 .ngroups = ARRAY_SIZE(i2s0_grps),
378};
379
380/* Pad multiplexing for i2s1 device */
381static const unsigned i2s1_pins[] = { 0, 1, 2, 3 };
382static struct spear_muxreg i2s1_muxreg[] = {
383 {
384 .reg = PAD_FUNCTION_EN_1,
385 .mask = PMX_I2S1_MASK,
386 .val = PMX_I2S1_MASK,
387 },
388};
389
390static struct spear_modemux i2s1_modemux[] = {
391 {
392 .muxregs = i2s1_muxreg,
393 .nmuxregs = ARRAY_SIZE(i2s1_muxreg),
394 },
395};
396
397static struct spear_pingroup i2s1_pingroup = {
398 .name = "i2s1_grp",
399 .pins = i2s1_pins,
400 .npins = ARRAY_SIZE(i2s1_pins),
401 .modemuxs = i2s1_modemux,
402 .nmodemuxs = ARRAY_SIZE(i2s1_modemux),
403};
404
405static const char *const i2s1_grps[] = { "i2s1_grp" };
406static struct spear_function i2s1_function = {
407 .name = "i2s1",
408 .groups = i2s1_grps,
409 .ngroups = ARRAY_SIZE(i2s1_grps),
410};
411
412/* Pad multiplexing for clcd device */
413static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120,
414 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
415 135, 136, 137, 138, 139, 140, 141, 142 };
416static struct spear_muxreg clcd_muxreg[] = {
417 {
418 .reg = PAD_FUNCTION_EN_0,
419 .mask = PMX_CLCD1_MASK,
420 .val = PMX_CLCD1_MASK,
421 },
422};
423
424static struct spear_modemux clcd_modemux[] = {
425 {
426 .muxregs = clcd_muxreg,
427 .nmuxregs = ARRAY_SIZE(clcd_muxreg),
428 },
429};
430
431static struct spear_pingroup clcd_pingroup = {
432 .name = "clcd_grp",
433 .pins = clcd_pins,
434 .npins = ARRAY_SIZE(clcd_pins),
435 .modemuxs = clcd_modemux,
436 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
437};
438
439static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37,
440 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 };
441static struct spear_muxreg clcd_high_res_muxreg[] = {
442 {
443 .reg = PAD_FUNCTION_EN_1,
444 .mask = PMX_CLCD2_MASK,
445 .val = PMX_CLCD2_MASK,
446 },
447};
448
449static struct spear_modemux clcd_high_res_modemux[] = {
450 {
451 .muxregs = clcd_high_res_muxreg,
452 .nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg),
453 },
454};
455
456static struct spear_pingroup clcd_high_res_pingroup = {
457 .name = "clcd_high_res_grp",
458 .pins = clcd_high_res_pins,
459 .npins = ARRAY_SIZE(clcd_high_res_pins),
460 .modemuxs = clcd_high_res_modemux,
461 .nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux),
462};
463
464static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res" };
465static struct spear_function clcd_function = {
466 .name = "clcd",
467 .groups = clcd_grps,
468 .ngroups = ARRAY_SIZE(clcd_grps),
469};
470
471static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145,
472 146, 147, 148, 149, 150, 151, 152 };
473static struct spear_muxreg arm_gpio_muxreg[] = {
474 {
475 .reg = PAD_FUNCTION_EN_0,
476 .mask = PMX_EGPIO_0_GRP_MASK,
477 .val = PMX_EGPIO_0_GRP_MASK,
478 }, {
479 .reg = PAD_FUNCTION_EN_1,
480 .mask = PMX_EGPIO_1_GRP_MASK,
481 .val = PMX_EGPIO_1_GRP_MASK,
482 },
483};
484
485static struct spear_modemux arm_gpio_modemux[] = {
486 {
487 .muxregs = arm_gpio_muxreg,
488 .nmuxregs = ARRAY_SIZE(arm_gpio_muxreg),
489 },
490};
491
492static struct spear_pingroup arm_gpio_pingroup = {
493 .name = "arm_gpio_grp",
494 .pins = arm_gpio_pins,
495 .npins = ARRAY_SIZE(arm_gpio_pins),
496 .modemuxs = arm_gpio_modemux,
497 .nmodemuxs = ARRAY_SIZE(arm_gpio_modemux),
498};
499
500static const char *const arm_gpio_grps[] = { "arm_gpio_grp" };
501static struct spear_function arm_gpio_function = {
502 .name = "arm_gpio",
503 .groups = arm_gpio_grps,
504 .ngroups = ARRAY_SIZE(arm_gpio_grps),
505};
506
507/* Pad multiplexing for smi 2 chips device */
508static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 };
509static struct spear_muxreg smi_2_chips_muxreg[] = {
510 {
511 .reg = PAD_FUNCTION_EN_0,
512 .mask = PMX_SMI_MASK,
513 .val = PMX_SMI_MASK,
514 },
515};
516
517static struct spear_modemux smi_2_chips_modemux[] = {
518 {
519 .muxregs = smi_2_chips_muxreg,
520 .nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg),
521 },
522};
523
524static struct spear_pingroup smi_2_chips_pingroup = {
525 .name = "smi_2_chips_grp",
526 .pins = smi_2_chips_pins,
527 .npins = ARRAY_SIZE(smi_2_chips_pins),
528 .modemuxs = smi_2_chips_modemux,
529 .nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux),
530};
531
532static const unsigned smi_4_chips_pins[] = { 54, 55 };
533static struct spear_muxreg smi_4_chips_muxreg[] = {
534 {
535 .reg = PAD_FUNCTION_EN_0,
536 .mask = PMX_SMI_MASK,
537 .val = PMX_SMI_MASK,
538 }, {
539 .reg = PAD_FUNCTION_EN_1,
540 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
541 .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
542 },
543};
544
545static struct spear_modemux smi_4_chips_modemux[] = {
546 {
547 .muxregs = smi_4_chips_muxreg,
548 .nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg),
549 },
550};
551
552static struct spear_pingroup smi_4_chips_pingroup = {
553 .name = "smi_4_chips_grp",
554 .pins = smi_4_chips_pins,
555 .npins = ARRAY_SIZE(smi_4_chips_pins),
556 .modemuxs = smi_4_chips_modemux,
557 .nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux),
558};
559
560static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" };
561static struct spear_function smi_function = {
562 .name = "smi",
563 .groups = smi_grps,
564 .ngroups = ARRAY_SIZE(smi_grps),
565};
566
567/* Pad multiplexing for gmii device */
568static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180,
569 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194,
570 195, 196, 197, 198, 199, 200 };
571static struct spear_muxreg gmii_muxreg[] = {
572 {
573 .reg = PAD_FUNCTION_EN_0,
574 .mask = PMX_GMII_MASK,
575 .val = PMX_GMII_MASK,
576 },
577};
578
579static struct spear_modemux gmii_modemux[] = {
580 {
581 .muxregs = gmii_muxreg,
582 .nmuxregs = ARRAY_SIZE(gmii_muxreg),
583 },
584};
585
586static struct spear_pingroup gmii_pingroup = {
587 .name = "gmii_grp",
588 .pins = gmii_pins,
589 .npins = ARRAY_SIZE(gmii_pins),
590 .modemuxs = gmii_modemux,
591 .nmodemuxs = ARRAY_SIZE(gmii_modemux),
592};
593
594static const char *const gmii_grps[] = { "gmii_grp" };
595static struct spear_function gmii_function = {
596 .name = "gmii",
597 .groups = gmii_grps,
598 .ngroups = ARRAY_SIZE(gmii_grps),
599};
600
601/* Pad multiplexing for rgmii device */
602static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
603 28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175,
604 180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 };
605static struct spear_muxreg rgmii_muxreg[] = {
606 {
607 .reg = PAD_FUNCTION_EN_0,
608 .mask = PMX_RGMII_REG0_MASK,
609 .val = 0,
610 }, {
611 .reg = PAD_FUNCTION_EN_1,
612 .mask = PMX_RGMII_REG1_MASK,
613 .val = 0,
614 }, {
615 .reg = PAD_FUNCTION_EN_2,
616 .mask = PMX_RGMII_REG2_MASK,
617 .val = 0,
618 },
619};
620
621static struct spear_modemux rgmii_modemux[] = {
622 {
623 .muxregs = rgmii_muxreg,
624 .nmuxregs = ARRAY_SIZE(rgmii_muxreg),
625 },
626};
627
628static struct spear_pingroup rgmii_pingroup = {
629 .name = "rgmii_grp",
630 .pins = rgmii_pins,
631 .npins = ARRAY_SIZE(rgmii_pins),
632 .modemuxs = rgmii_modemux,
633 .nmodemuxs = ARRAY_SIZE(rgmii_modemux),
634};
635
636static const char *const rgmii_grps[] = { "rgmii_grp" };
637static struct spear_function rgmii_function = {
638 .name = "rgmii",
639 .groups = rgmii_grps,
640 .ngroups = ARRAY_SIZE(rgmii_grps),
641};
642
643/* Pad multiplexing for smii_0_1_2 device */
644static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
645 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
646 51, 52, 53, 54, 55 };
647static struct spear_muxreg smii_0_1_2_muxreg[] = {
648 {
649 .reg = PAD_FUNCTION_EN_1,
650 .mask = PMX_SMII_0_1_2_MASK,
651 .val = 0,
652 },
653};
654
655static struct spear_modemux smii_0_1_2_modemux[] = {
656 {
657 .muxregs = smii_0_1_2_muxreg,
658 .nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg),
659 },
660};
661
662static struct spear_pingroup smii_0_1_2_pingroup = {
663 .name = "smii_0_1_2_grp",
664 .pins = smii_0_1_2_pins,
665 .npins = ARRAY_SIZE(smii_0_1_2_pins),
666 .modemuxs = smii_0_1_2_modemux,
667 .nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux),
668};
669
670static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" };
671static struct spear_function smii_0_1_2_function = {
672 .name = "smii_0_1_2",
673 .groups = smii_0_1_2_grps,
674 .ngroups = ARRAY_SIZE(smii_0_1_2_grps),
675};
676
677/* Pad multiplexing for ras_mii_txclk device */
678static const unsigned ras_mii_txclk_pins[] = { 98, 99 };
679static struct spear_muxreg ras_mii_txclk_muxreg[] = {
680 {
681 .reg = PAD_FUNCTION_EN_1,
682 .mask = PMX_NFCE2_MASK,
683 .val = 0,
684 },
685};
686
687static struct spear_modemux ras_mii_txclk_modemux[] = {
688 {
689 .muxregs = ras_mii_txclk_muxreg,
690 .nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg),
691 },
692};
693
694static struct spear_pingroup ras_mii_txclk_pingroup = {
695 .name = "ras_mii_txclk_grp",
696 .pins = ras_mii_txclk_pins,
697 .npins = ARRAY_SIZE(ras_mii_txclk_pins),
698 .modemuxs = ras_mii_txclk_modemux,
699 .nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux),
700};
701
702static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" };
703static struct spear_function ras_mii_txclk_function = {
704 .name = "ras_mii_txclk",
705 .groups = ras_mii_txclk_grps,
706 .ngroups = ARRAY_SIZE(ras_mii_txclk_grps),
707};
708
709/* Pad multiplexing for nand 8bit device (cs0 only) */
710static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64,
711 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82,
712 83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169,
713 170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211,
714 212 };
715static struct spear_muxreg nand_8bit_muxreg[] = {
716 {
717 .reg = PAD_FUNCTION_EN_0,
718 .mask = PMX_NAND8BIT_0_MASK,
719 .val = PMX_NAND8BIT_0_MASK,
720 }, {
721 .reg = PAD_FUNCTION_EN_1,
722 .mask = PMX_NAND8BIT_1_MASK,
723 .val = PMX_NAND8BIT_1_MASK,
724 },
725};
726
727static struct spear_modemux nand_8bit_modemux[] = {
728 {
729 .muxregs = nand_8bit_muxreg,
730 .nmuxregs = ARRAY_SIZE(nand_8bit_muxreg),
731 },
732};
733
734static struct spear_pingroup nand_8bit_pingroup = {
735 .name = "nand_8bit_grp",
736 .pins = nand_8bit_pins,
737 .npins = ARRAY_SIZE(nand_8bit_pins),
738 .modemuxs = nand_8bit_modemux,
739 .nmodemuxs = ARRAY_SIZE(nand_8bit_modemux),
740};
741
742/* Pad multiplexing for nand 16bit device */
743static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209,
744 210 };
745static struct spear_muxreg nand_16bit_muxreg[] = {
746 {
747 .reg = PAD_FUNCTION_EN_1,
748 .mask = PMX_NAND16BIT_1_MASK,
749 .val = PMX_NAND16BIT_1_MASK,
750 },
751};
752
753static struct spear_modemux nand_16bit_modemux[] = {
754 {
755 .muxregs = nand_16bit_muxreg,
756 .nmuxregs = ARRAY_SIZE(nand_16bit_muxreg),
757 },
758};
759
760static struct spear_pingroup nand_16bit_pingroup = {
761 .name = "nand_16bit_grp",
762 .pins = nand_16bit_pins,
763 .npins = ARRAY_SIZE(nand_16bit_pins),
764 .modemuxs = nand_16bit_modemux,
765 .nmodemuxs = ARRAY_SIZE(nand_16bit_modemux),
766};
767
768/* Pad multiplexing for nand 4 chips */
769static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 };
770static struct spear_muxreg nand_4_chips_muxreg[] = {
771 {
772 .reg = PAD_FUNCTION_EN_1,
773 .mask = PMX_NAND_4CHIPS_MASK,
774 .val = PMX_NAND_4CHIPS_MASK,
775 },
776};
777
778static struct spear_modemux nand_4_chips_modemux[] = {
779 {
780 .muxregs = nand_4_chips_muxreg,
781 .nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg),
782 },
783};
784
785static struct spear_pingroup nand_4_chips_pingroup = {
786 .name = "nand_4_chips_grp",
787 .pins = nand_4_chips_pins,
788 .npins = ARRAY_SIZE(nand_4_chips_pins),
789 .modemuxs = nand_4_chips_modemux,
790 .nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux),
791};
792
793static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp",
794 "nand_4_chips_grp" };
795static struct spear_function nand_function = {
796 .name = "nand",
797 .groups = nand_grps,
798 .ngroups = ARRAY_SIZE(nand_grps),
799};
800
801/* Pad multiplexing for keyboard_6x6 device */
802static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207,
803 208, 209, 210, 211, 212 };
804static struct spear_muxreg keyboard_6x6_muxreg[] = {
805 {
806 .reg = PAD_FUNCTION_EN_1,
807 .mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK |
808 PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK |
809 PMX_NFWPRT2_MASK,
810 .val = PMX_KEYBOARD_6X6_MASK,
811 },
812};
813
814static struct spear_modemux keyboard_6x6_modemux[] = {
815 {
816 .muxregs = keyboard_6x6_muxreg,
817 .nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg),
818 },
819};
820
821static struct spear_pingroup keyboard_6x6_pingroup = {
822 .name = "keyboard_6x6_grp",
823 .pins = keyboard_6x6_pins,
824 .npins = ARRAY_SIZE(keyboard_6x6_pins),
825 .modemuxs = keyboard_6x6_modemux,
826 .nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux),
827};
828
829/* Pad multiplexing for keyboard_rowcol6_8 device */
830static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 };
831static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = {
832 {
833 .reg = PAD_FUNCTION_EN_1,
834 .mask = PMX_KBD_ROWCOL68_MASK,
835 .val = PMX_KBD_ROWCOL68_MASK,
836 },
837};
838
839static struct spear_modemux keyboard_rowcol6_8_modemux[] = {
840 {
841 .muxregs = keyboard_rowcol6_8_muxreg,
842 .nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg),
843 },
844};
845
846static struct spear_pingroup keyboard_rowcol6_8_pingroup = {
847 .name = "keyboard_rowcol6_8_grp",
848 .pins = keyboard_rowcol6_8_pins,
849 .npins = ARRAY_SIZE(keyboard_rowcol6_8_pins),
850 .modemuxs = keyboard_rowcol6_8_modemux,
851 .nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux),
852};
853
854static const char *const keyboard_grps[] = { "keyboard_6x6_grp",
855 "keyboard_rowcol6_8_grp" };
856static struct spear_function keyboard_function = {
857 .name = "keyboard",
858 .groups = keyboard_grps,
859 .ngroups = ARRAY_SIZE(keyboard_grps),
860};
861
862/* Pad multiplexing for uart0 device */
863static const unsigned uart0_pins[] = { 100, 101 };
864static struct spear_muxreg uart0_muxreg[] = {
865 {
866 .reg = PAD_FUNCTION_EN_0,
867 .mask = PMX_UART0_MASK,
868 .val = PMX_UART0_MASK,
869 },
870};
871
872static struct spear_modemux uart0_modemux[] = {
873 {
874 .muxregs = uart0_muxreg,
875 .nmuxregs = ARRAY_SIZE(uart0_muxreg),
876 },
877};
878
879static struct spear_pingroup uart0_pingroup = {
880 .name = "uart0_grp",
881 .pins = uart0_pins,
882 .npins = ARRAY_SIZE(uart0_pins),
883 .modemuxs = uart0_modemux,
884 .nmodemuxs = ARRAY_SIZE(uart0_modemux),
885};
886
887/* Pad multiplexing for uart0_modem device */
888static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 };
889static struct spear_muxreg uart0_modem_muxreg[] = {
890 {
891 .reg = PAD_FUNCTION_EN_1,
892 .mask = PMX_UART0_MODEM_MASK,
893 .val = PMX_UART0_MODEM_MASK,
894 },
895};
896
897static struct spear_modemux uart0_modem_modemux[] = {
898 {
899 .muxregs = uart0_modem_muxreg,
900 .nmuxregs = ARRAY_SIZE(uart0_modem_muxreg),
901 },
902};
903
904static struct spear_pingroup uart0_modem_pingroup = {
905 .name = "uart0_modem_grp",
906 .pins = uart0_modem_pins,
907 .npins = ARRAY_SIZE(uart0_modem_pins),
908 .modemuxs = uart0_modem_modemux,
909 .nmodemuxs = ARRAY_SIZE(uart0_modem_modemux),
910};
911
912static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" };
913static struct spear_function uart0_function = {
914 .name = "uart0",
915 .groups = uart0_grps,
916 .ngroups = ARRAY_SIZE(uart0_grps),
917};
918
919/* Pad multiplexing for gpt0_tmr0 device */
920static const unsigned gpt0_tmr0_pins[] = { 10, 11 };
921static struct spear_muxreg gpt0_tmr0_muxreg[] = {
922 {
923 .reg = PAD_FUNCTION_EN_1,
924 .mask = PMX_GPT0_TMR0_MASK,
925 .val = PMX_GPT0_TMR0_MASK,
926 },
927};
928
929static struct spear_modemux gpt0_tmr0_modemux[] = {
930 {
931 .muxregs = gpt0_tmr0_muxreg,
932 .nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg),
933 },
934};
935
936static struct spear_pingroup gpt0_tmr0_pingroup = {
937 .name = "gpt0_tmr0_grp",
938 .pins = gpt0_tmr0_pins,
939 .npins = ARRAY_SIZE(gpt0_tmr0_pins),
940 .modemuxs = gpt0_tmr0_modemux,
941 .nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux),
942};
943
944/* Pad multiplexing for gpt0_tmr1 device */
945static const unsigned gpt0_tmr1_pins[] = { 8, 9 };
946static struct spear_muxreg gpt0_tmr1_muxreg[] = {
947 {
948 .reg = PAD_FUNCTION_EN_1,
949 .mask = PMX_GPT0_TMR1_MASK,
950 .val = PMX_GPT0_TMR1_MASK,
951 },
952};
953
954static struct spear_modemux gpt0_tmr1_modemux[] = {
955 {
956 .muxregs = gpt0_tmr1_muxreg,
957 .nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg),
958 },
959};
960
961static struct spear_pingroup gpt0_tmr1_pingroup = {
962 .name = "gpt0_tmr1_grp",
963 .pins = gpt0_tmr1_pins,
964 .npins = ARRAY_SIZE(gpt0_tmr1_pins),
965 .modemuxs = gpt0_tmr1_modemux,
966 .nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux),
967};
968
969static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" };
970static struct spear_function gpt0_function = {
971 .name = "gpt0",
972 .groups = gpt0_grps,
973 .ngroups = ARRAY_SIZE(gpt0_grps),
974};
975
976/* Pad multiplexing for gpt1_tmr0 device */
977static const unsigned gpt1_tmr0_pins[] = { 6, 7 };
978static struct spear_muxreg gpt1_tmr0_muxreg[] = {
979 {
980 .reg = PAD_FUNCTION_EN_1,
981 .mask = PMX_GPT1_TMR0_MASK,
982 .val = PMX_GPT1_TMR0_MASK,
983 },
984};
985
986static struct spear_modemux gpt1_tmr0_modemux[] = {
987 {
988 .muxregs = gpt1_tmr0_muxreg,
989 .nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg),
990 },
991};
992
993static struct spear_pingroup gpt1_tmr0_pingroup = {
994 .name = "gpt1_tmr0_grp",
995 .pins = gpt1_tmr0_pins,
996 .npins = ARRAY_SIZE(gpt1_tmr0_pins),
997 .modemuxs = gpt1_tmr0_modemux,
998 .nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux),
999};
1000
1001/* Pad multiplexing for gpt1_tmr1 device */
1002static const unsigned gpt1_tmr1_pins[] = { 4, 5 };
1003static struct spear_muxreg gpt1_tmr1_muxreg[] = {
1004 {
1005 .reg = PAD_FUNCTION_EN_1,
1006 .mask = PMX_GPT1_TMR1_MASK,
1007 .val = PMX_GPT1_TMR1_MASK,
1008 },
1009};
1010
1011static struct spear_modemux gpt1_tmr1_modemux[] = {
1012 {
1013 .muxregs = gpt1_tmr1_muxreg,
1014 .nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg),
1015 },
1016};
1017
1018static struct spear_pingroup gpt1_tmr1_pingroup = {
1019 .name = "gpt1_tmr1_grp",
1020 .pins = gpt1_tmr1_pins,
1021 .npins = ARRAY_SIZE(gpt1_tmr1_pins),
1022 .modemuxs = gpt1_tmr1_modemux,
1023 .nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux),
1024};
1025
1026static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" };
1027static struct spear_function gpt1_function = {
1028 .name = "gpt1",
1029 .groups = gpt1_grps,
1030 .ngroups = ARRAY_SIZE(gpt1_grps),
1031};
1032
1033/* Pad multiplexing for mcif device */
1034static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214,
1035 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
1036 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242,
1037 243, 244, 245 };
1038#define MCIF_MUXREG \
1039 { \
1040 .reg = PAD_FUNCTION_EN_0, \
1041 .mask = PMX_MCI_DATA8_15_MASK, \
1042 .val = PMX_MCI_DATA8_15_MASK, \
1043 }, { \
1044 .reg = PAD_FUNCTION_EN_1, \
1045 .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
1046 PMX_NFWPRT2_MASK, \
1047 .val = PMX_MCIFALL_1_MASK, \
1048 }, { \
1049 .reg = PAD_FUNCTION_EN_2, \
1050 .mask = PMX_MCIFALL_2_MASK, \
1051 .val = PMX_MCIFALL_2_MASK, \
1052 }
1053
1054/* sdhci device */
1055static struct spear_muxreg sdhci_muxreg[] = {
1056 MCIF_MUXREG,
1057 {
1058 .reg = PERIP_CFG,
1059 .mask = MCIF_SEL_MASK,
1060 .val = MCIF_SEL_SD,
1061 },
1062};
1063
1064static struct spear_modemux sdhci_modemux[] = {
1065 {
1066 .muxregs = sdhci_muxreg,
1067 .nmuxregs = ARRAY_SIZE(sdhci_muxreg),
1068 },
1069};
1070
1071static struct spear_pingroup sdhci_pingroup = {
1072 .name = "sdhci_grp",
1073 .pins = mcif_pins,
1074 .npins = ARRAY_SIZE(mcif_pins),
1075 .modemuxs = sdhci_modemux,
1076 .nmodemuxs = ARRAY_SIZE(sdhci_modemux),
1077};
1078
1079static const char *const sdhci_grps[] = { "sdhci_grp" };
1080static struct spear_function sdhci_function = {
1081 .name = "sdhci",
1082 .groups = sdhci_grps,
1083 .ngroups = ARRAY_SIZE(sdhci_grps),
1084};
1085
1086/* cf device */
1087static struct spear_muxreg cf_muxreg[] = {
1088 MCIF_MUXREG,
1089 {
1090 .reg = PERIP_CFG,
1091 .mask = MCIF_SEL_MASK,
1092 .val = MCIF_SEL_CF,
1093 },
1094};
1095
1096static struct spear_modemux cf_modemux[] = {
1097 {
1098 .muxregs = cf_muxreg,
1099 .nmuxregs = ARRAY_SIZE(cf_muxreg),
1100 },
1101};
1102
1103static struct spear_pingroup cf_pingroup = {
1104 .name = "cf_grp",
1105 .pins = mcif_pins,
1106 .npins = ARRAY_SIZE(mcif_pins),
1107 .modemuxs = cf_modemux,
1108 .nmodemuxs = ARRAY_SIZE(cf_modemux),
1109};
1110
1111static const char *const cf_grps[] = { "cf_grp" };
1112static struct spear_function cf_function = {
1113 .name = "cf",
1114 .groups = cf_grps,
1115 .ngroups = ARRAY_SIZE(cf_grps),
1116};
1117
1118/* xd device */
1119static struct spear_muxreg xd_muxreg[] = {
1120 MCIF_MUXREG,
1121 {
1122 .reg = PERIP_CFG,
1123 .mask = MCIF_SEL_MASK,
1124 .val = MCIF_SEL_XD,
1125 },
1126};
1127
1128static struct spear_modemux xd_modemux[] = {
1129 {
1130 .muxregs = xd_muxreg,
1131 .nmuxregs = ARRAY_SIZE(xd_muxreg),
1132 },
1133};
1134
1135static struct spear_pingroup xd_pingroup = {
1136 .name = "xd_grp",
1137 .pins = mcif_pins,
1138 .npins = ARRAY_SIZE(mcif_pins),
1139 .modemuxs = xd_modemux,
1140 .nmodemuxs = ARRAY_SIZE(xd_modemux),
1141};
1142
1143static const char *const xd_grps[] = { "xd_grp" };
1144static struct spear_function xd_function = {
1145 .name = "xd",
1146 .groups = xd_grps,
1147 .ngroups = ARRAY_SIZE(xd_grps),
1148};
1149
1150/* Pad multiplexing for touch_xy device */
1151static const unsigned touch_xy_pins[] = { 97 };
1152static struct spear_muxreg touch_xy_muxreg[] = {
1153 {
1154 .reg = PAD_FUNCTION_EN_2,
1155 .mask = PMX_TOUCH_XY_MASK,
1156 .val = PMX_TOUCH_XY_MASK,
1157 },
1158};
1159
1160static struct spear_modemux touch_xy_modemux[] = {
1161 {
1162 .muxregs = touch_xy_muxreg,
1163 .nmuxregs = ARRAY_SIZE(touch_xy_muxreg),
1164 },
1165};
1166
1167static struct spear_pingroup touch_xy_pingroup = {
1168 .name = "touch_xy_grp",
1169 .pins = touch_xy_pins,
1170 .npins = ARRAY_SIZE(touch_xy_pins),
1171 .modemuxs = touch_xy_modemux,
1172 .nmodemuxs = ARRAY_SIZE(touch_xy_modemux),
1173};
1174
1175static const char *const touch_xy_grps[] = { "touch_xy_grp" };
1176static struct spear_function touch_xy_function = {
1177 .name = "touchscreen",
1178 .groups = touch_xy_grps,
1179 .ngroups = ARRAY_SIZE(touch_xy_grps),
1180};
1181
1182/* Pad multiplexing for uart1 device */
1183/* Muxed with I2C */
1184static const unsigned uart1_dis_i2c_pins[] = { 102, 103 };
1185static struct spear_muxreg uart1_dis_i2c_muxreg[] = {
1186 {
1187 .reg = PAD_FUNCTION_EN_0,
1188 .mask = PMX_I2C0_MASK,
1189 .val = 0,
1190 },
1191};
1192
1193static struct spear_modemux uart1_dis_i2c_modemux[] = {
1194 {
1195 .muxregs = uart1_dis_i2c_muxreg,
1196 .nmuxregs = ARRAY_SIZE(uart1_dis_i2c_muxreg),
1197 },
1198};
1199
1200static struct spear_pingroup uart_1_dis_i2c_pingroup = {
1201 .name = "uart1_disable_i2c_grp",
1202 .pins = uart1_dis_i2c_pins,
1203 .npins = ARRAY_SIZE(uart1_dis_i2c_pins),
1204 .modemuxs = uart1_dis_i2c_modemux,
1205 .nmodemuxs = ARRAY_SIZE(uart1_dis_i2c_modemux),
1206};
1207
1208/* Muxed with SD/MMC */
1209static const unsigned uart1_dis_sd_pins[] = { 214, 215 };
1210static struct spear_muxreg uart1_dis_sd_muxreg[] = {
1211 {
1212 .reg = PAD_FUNCTION_EN_1,
1213 .mask = PMX_MCIDATA1_MASK |
1214 PMX_MCIDATA2_MASK,
1215 .val = 0,
1216 },
1217};
1218
1219static struct spear_modemux uart1_dis_sd_modemux[] = {
1220 {
1221 .muxregs = uart1_dis_sd_muxreg,
1222 .nmuxregs = ARRAY_SIZE(uart1_dis_sd_muxreg),
1223 },
1224};
1225
1226static struct spear_pingroup uart_1_dis_sd_pingroup = {
1227 .name = "uart1_disable_sd_grp",
1228 .pins = uart1_dis_sd_pins,
1229 .npins = ARRAY_SIZE(uart1_dis_sd_pins),
1230 .modemuxs = uart1_dis_sd_modemux,
1231 .nmodemuxs = ARRAY_SIZE(uart1_dis_sd_modemux),
1232};
1233
1234static const char *const uart1_grps[] = { "uart1_disable_i2c_grp",
1235 "uart1_disable_sd_grp" };
1236static struct spear_function uart1_function = {
1237 .name = "uart1",
1238 .groups = uart1_grps,
1239 .ngroups = ARRAY_SIZE(uart1_grps),
1240};
1241
1242/* Pad multiplexing for uart2_3 device */
1243static const unsigned uart2_3_pins[] = { 104, 105, 106, 107 };
1244static struct spear_muxreg uart2_3_muxreg[] = {
1245 {
1246 .reg = PAD_FUNCTION_EN_0,
1247 .mask = PMX_I2S0_MASK,
1248 .val = 0,
1249 },
1250};
1251
1252static struct spear_modemux uart2_3_modemux[] = {
1253 {
1254 .muxregs = uart2_3_muxreg,
1255 .nmuxregs = ARRAY_SIZE(uart2_3_muxreg),
1256 },
1257};
1258
1259static struct spear_pingroup uart_2_3_pingroup = {
1260 .name = "uart2_3_grp",
1261 .pins = uart2_3_pins,
1262 .npins = ARRAY_SIZE(uart2_3_pins),
1263 .modemuxs = uart2_3_modemux,
1264 .nmodemuxs = ARRAY_SIZE(uart2_3_modemux),
1265};
1266
1267static const char *const uart2_3_grps[] = { "uart2_3_grp" };
1268static struct spear_function uart2_3_function = {
1269 .name = "uart2_3",
1270 .groups = uart2_3_grps,
1271 .ngroups = ARRAY_SIZE(uart2_3_grps),
1272};
1273
1274/* Pad multiplexing for uart4 device */
1275static const unsigned uart4_pins[] = { 108, 113 };
1276static struct spear_muxreg uart4_muxreg[] = {
1277 {
1278 .reg = PAD_FUNCTION_EN_0,
1279 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1280 .val = 0,
1281 },
1282};
1283
1284static struct spear_modemux uart4_modemux[] = {
1285 {
1286 .muxregs = uart4_muxreg,
1287 .nmuxregs = ARRAY_SIZE(uart4_muxreg),
1288 },
1289};
1290
1291static struct spear_pingroup uart_4_pingroup = {
1292 .name = "uart4_grp",
1293 .pins = uart4_pins,
1294 .npins = ARRAY_SIZE(uart4_pins),
1295 .modemuxs = uart4_modemux,
1296 .nmodemuxs = ARRAY_SIZE(uart4_modemux),
1297};
1298
1299static const char *const uart4_grps[] = { "uart4_grp" };
1300static struct spear_function uart4_function = {
1301 .name = "uart4",
1302 .groups = uart4_grps,
1303 .ngroups = ARRAY_SIZE(uart4_grps),
1304};
1305
1306/* Pad multiplexing for uart5 device */
1307static const unsigned uart5_pins[] = { 114, 115 };
1308static struct spear_muxreg uart5_muxreg[] = {
1309 {
1310 .reg = PAD_FUNCTION_EN_0,
1311 .mask = PMX_CLCD1_MASK,
1312 .val = 0,
1313 },
1314};
1315
1316static struct spear_modemux uart5_modemux[] = {
1317 {
1318 .muxregs = uart5_muxreg,
1319 .nmuxregs = ARRAY_SIZE(uart5_muxreg),
1320 },
1321};
1322
1323static struct spear_pingroup uart_5_pingroup = {
1324 .name = "uart5_grp",
1325 .pins = uart5_pins,
1326 .npins = ARRAY_SIZE(uart5_pins),
1327 .modemuxs = uart5_modemux,
1328 .nmodemuxs = ARRAY_SIZE(uart5_modemux),
1329};
1330
1331static const char *const uart5_grps[] = { "uart5_grp" };
1332static struct spear_function uart5_function = {
1333 .name = "uart5",
1334 .groups = uart5_grps,
1335 .ngroups = ARRAY_SIZE(uart5_grps),
1336};
1337
1338/* Pad multiplexing for rs485_0_1_tdm_0_1 device */
1339static const unsigned rs485_0_1_tdm_0_1_pins[] = { 116, 117, 118, 119, 120, 121,
1340 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
1341 136, 137 };
1342static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = {
1343 {
1344 .reg = PAD_FUNCTION_EN_0,
1345 .mask = PMX_CLCD1_MASK,
1346 .val = 0,
1347 },
1348};
1349
1350static struct spear_modemux rs485_0_1_tdm_0_1_modemux[] = {
1351 {
1352 .muxregs = rs485_0_1_tdm_0_1_muxreg,
1353 .nmuxregs = ARRAY_SIZE(rs485_0_1_tdm_0_1_muxreg),
1354 },
1355};
1356
1357static struct spear_pingroup rs485_0_1_tdm_0_1_pingroup = {
1358 .name = "rs485_0_1_tdm_0_1_grp",
1359 .pins = rs485_0_1_tdm_0_1_pins,
1360 .npins = ARRAY_SIZE(rs485_0_1_tdm_0_1_pins),
1361 .modemuxs = rs485_0_1_tdm_0_1_modemux,
1362 .nmodemuxs = ARRAY_SIZE(rs485_0_1_tdm_0_1_modemux),
1363};
1364
1365static const char *const rs485_0_1_tdm_0_1_grps[] = { "rs485_0_1_tdm_0_1_grp" };
1366static struct spear_function rs485_0_1_tdm_0_1_function = {
1367 .name = "rs485_0_1_tdm_0_1",
1368 .groups = rs485_0_1_tdm_0_1_grps,
1369 .ngroups = ARRAY_SIZE(rs485_0_1_tdm_0_1_grps),
1370};
1371
1372/* Pad multiplexing for i2c_1_2 device */
1373static const unsigned i2c_1_2_pins[] = { 138, 139, 140, 141 };
1374static struct spear_muxreg i2c_1_2_muxreg[] = {
1375 {
1376 .reg = PAD_FUNCTION_EN_0,
1377 .mask = PMX_CLCD1_MASK,
1378 .val = 0,
1379 },
1380};
1381
1382static struct spear_modemux i2c_1_2_modemux[] = {
1383 {
1384 .muxregs = i2c_1_2_muxreg,
1385 .nmuxregs = ARRAY_SIZE(i2c_1_2_muxreg),
1386 },
1387};
1388
1389static struct spear_pingroup i2c_1_2_pingroup = {
1390 .name = "i2c_1_2_grp",
1391 .pins = i2c_1_2_pins,
1392 .npins = ARRAY_SIZE(i2c_1_2_pins),
1393 .modemuxs = i2c_1_2_modemux,
1394 .nmodemuxs = ARRAY_SIZE(i2c_1_2_modemux),
1395};
1396
1397static const char *const i2c_1_2_grps[] = { "i2c_1_2_grp" };
1398static struct spear_function i2c_1_2_function = {
1399 .name = "i2c_1_2",
1400 .groups = i2c_1_2_grps,
1401 .ngroups = ARRAY_SIZE(i2c_1_2_grps),
1402};
1403
1404/* Pad multiplexing for i2c3_dis_smi_clcd device */
1405/* Muxed with SMI & CLCD */
1406static const unsigned i2c3_dis_smi_clcd_pins[] = { 142, 153 };
1407static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = {
1408 {
1409 .reg = PAD_FUNCTION_EN_0,
1410 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
1411 .val = 0,
1412 },
1413};
1414
1415static struct spear_modemux i2c3_dis_smi_clcd_modemux[] = {
1416 {
1417 .muxregs = i2c3_dis_smi_clcd_muxreg,
1418 .nmuxregs = ARRAY_SIZE(i2c3_dis_smi_clcd_muxreg),
1419 },
1420};
1421
1422static struct spear_pingroup i2c3_dis_smi_clcd_pingroup = {
1423 .name = "i2c3_dis_smi_clcd_grp",
1424 .pins = i2c3_dis_smi_clcd_pins,
1425 .npins = ARRAY_SIZE(i2c3_dis_smi_clcd_pins),
1426 .modemuxs = i2c3_dis_smi_clcd_modemux,
1427 .nmodemuxs = ARRAY_SIZE(i2c3_dis_smi_clcd_modemux),
1428};
1429
1430/* Pad multiplexing for i2c3_dis_sd_i2s0 device */
1431/* Muxed with SD/MMC & I2S1 */
1432static const unsigned i2c3_dis_sd_i2s0_pins[] = { 0, 216 };
1433static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = {
1434 {
1435 .reg = PAD_FUNCTION_EN_1,
1436 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1437 .val = 0,
1438 },
1439};
1440
1441static struct spear_modemux i2c3_dis_sd_i2s0_modemux[] = {
1442 {
1443 .muxregs = i2c3_dis_sd_i2s0_muxreg,
1444 .nmuxregs = ARRAY_SIZE(i2c3_dis_sd_i2s0_muxreg),
1445 },
1446};
1447
1448static struct spear_pingroup i2c3_dis_sd_i2s0_pingroup = {
1449 .name = "i2c3_dis_sd_i2s0_grp",
1450 .pins = i2c3_dis_sd_i2s0_pins,
1451 .npins = ARRAY_SIZE(i2c3_dis_sd_i2s0_pins),
1452 .modemuxs = i2c3_dis_sd_i2s0_modemux,
1453 .nmodemuxs = ARRAY_SIZE(i2c3_dis_sd_i2s0_modemux),
1454};
1455
1456static const char *const i2c3_grps[] = { "i2c3_dis_smi_clcd_grp",
1457 "i2c3_dis_sd_i2s0_grp" };
1458static struct spear_function i2c3_unction = {
1459 .name = "i2c3_i2s1",
1460 .groups = i2c3_grps,
1461 .ngroups = ARRAY_SIZE(i2c3_grps),
1462};
1463
1464/* Pad multiplexing for i2c_4_5_dis_smi device */
1465/* Muxed with SMI */
1466static const unsigned i2c_4_5_dis_smi_pins[] = { 154, 155, 156, 157 };
1467static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = {
1468 {
1469 .reg = PAD_FUNCTION_EN_0,
1470 .mask = PMX_SMI_MASK,
1471 .val = 0,
1472 },
1473};
1474
1475static struct spear_modemux i2c_4_5_dis_smi_modemux[] = {
1476 {
1477 .muxregs = i2c_4_5_dis_smi_muxreg,
1478 .nmuxregs = ARRAY_SIZE(i2c_4_5_dis_smi_muxreg),
1479 },
1480};
1481
1482static struct spear_pingroup i2c_4_5_dis_smi_pingroup = {
1483 .name = "i2c_4_5_dis_smi_grp",
1484 .pins = i2c_4_5_dis_smi_pins,
1485 .npins = ARRAY_SIZE(i2c_4_5_dis_smi_pins),
1486 .modemuxs = i2c_4_5_dis_smi_modemux,
1487 .nmodemuxs = ARRAY_SIZE(i2c_4_5_dis_smi_modemux),
1488};
1489
1490/* Pad multiplexing for i2c4_dis_sd device */
1491/* Muxed with SD/MMC */
1492static const unsigned i2c4_dis_sd_pins[] = { 217, 218 };
1493static struct spear_muxreg i2c4_dis_sd_muxreg[] = {
1494 {
1495 .reg = PAD_FUNCTION_EN_1,
1496 .mask = PMX_MCIDATA4_MASK,
1497 .val = 0,
1498 }, {
1499 .reg = PAD_FUNCTION_EN_2,
1500 .mask = PMX_MCIDATA5_MASK,
1501 .val = 0,
1502 },
1503};
1504
1505static struct spear_modemux i2c4_dis_sd_modemux[] = {
1506 {
1507 .muxregs = i2c4_dis_sd_muxreg,
1508 .nmuxregs = ARRAY_SIZE(i2c4_dis_sd_muxreg),
1509 },
1510};
1511
1512static struct spear_pingroup i2c4_dis_sd_pingroup = {
1513 .name = "i2c4_dis_sd_grp",
1514 .pins = i2c4_dis_sd_pins,
1515 .npins = ARRAY_SIZE(i2c4_dis_sd_pins),
1516 .modemuxs = i2c4_dis_sd_modemux,
1517 .nmodemuxs = ARRAY_SIZE(i2c4_dis_sd_modemux),
1518};
1519
1520/* Pad multiplexing for i2c5_dis_sd device */
1521/* Muxed with SD/MMC */
1522static const unsigned i2c5_dis_sd_pins[] = { 219, 220 };
1523static struct spear_muxreg i2c5_dis_sd_muxreg[] = {
1524 {
1525 .reg = PAD_FUNCTION_EN_2,
1526 .mask = PMX_MCIDATA6_MASK |
1527 PMX_MCIDATA7_MASK,
1528 .val = 0,
1529 },
1530};
1531
1532static struct spear_modemux i2c5_dis_sd_modemux[] = {
1533 {
1534 .muxregs = i2c5_dis_sd_muxreg,
1535 .nmuxregs = ARRAY_SIZE(i2c5_dis_sd_muxreg),
1536 },
1537};
1538
1539static struct spear_pingroup i2c5_dis_sd_pingroup = {
1540 .name = "i2c5_dis_sd_grp",
1541 .pins = i2c5_dis_sd_pins,
1542 .npins = ARRAY_SIZE(i2c5_dis_sd_pins),
1543 .modemuxs = i2c5_dis_sd_modemux,
1544 .nmodemuxs = ARRAY_SIZE(i2c5_dis_sd_modemux),
1545};
1546
1547static const char *const i2c_4_5_grps[] = { "i2c5_dis_sd_grp",
1548 "i2c4_dis_sd_grp", "i2c_4_5_dis_smi_grp" };
1549static struct spear_function i2c_4_5_function = {
1550 .name = "i2c_4_5",
1551 .groups = i2c_4_5_grps,
1552 .ngroups = ARRAY_SIZE(i2c_4_5_grps),
1553};
1554
1555/* Pad multiplexing for i2c_6_7_dis_kbd device */
1556/* Muxed with KBD */
1557static const unsigned i2c_6_7_dis_kbd_pins[] = { 207, 208, 209, 210 };
1558static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = {
1559 {
1560 .reg = PAD_FUNCTION_EN_1,
1561 .mask = PMX_KBD_ROWCOL25_MASK,
1562 .val = 0,
1563 },
1564};
1565
1566static struct spear_modemux i2c_6_7_dis_kbd_modemux[] = {
1567 {
1568 .muxregs = i2c_6_7_dis_kbd_muxreg,
1569 .nmuxregs = ARRAY_SIZE(i2c_6_7_dis_kbd_muxreg),
1570 },
1571};
1572
1573static struct spear_pingroup i2c_6_7_dis_kbd_pingroup = {
1574 .name = "i2c_6_7_dis_kbd_grp",
1575 .pins = i2c_6_7_dis_kbd_pins,
1576 .npins = ARRAY_SIZE(i2c_6_7_dis_kbd_pins),
1577 .modemuxs = i2c_6_7_dis_kbd_modemux,
1578 .nmodemuxs = ARRAY_SIZE(i2c_6_7_dis_kbd_modemux),
1579};
1580
1581/* Pad multiplexing for i2c6_dis_sd device */
1582/* Muxed with SD/MMC */
1583static const unsigned i2c6_dis_sd_pins[] = { 236, 237 };
1584static struct spear_muxreg i2c6_dis_sd_muxreg[] = {
1585 {
1586 .reg = PAD_FUNCTION_EN_2,
1587 .mask = PMX_MCIIORDRE_MASK |
1588 PMX_MCIIOWRWE_MASK,
1589 .val = 0,
1590 },
1591};
1592
1593static struct spear_modemux i2c6_dis_sd_modemux[] = {
1594 {
1595 .muxregs = i2c6_dis_sd_muxreg,
1596 .nmuxregs = ARRAY_SIZE(i2c6_dis_sd_muxreg),
1597 },
1598};
1599
1600static struct spear_pingroup i2c6_dis_sd_pingroup = {
1601 .name = "i2c6_dis_sd_grp",
1602 .pins = i2c6_dis_sd_pins,
1603 .npins = ARRAY_SIZE(i2c6_dis_sd_pins),
1604 .modemuxs = i2c6_dis_sd_modemux,
1605 .nmodemuxs = ARRAY_SIZE(i2c6_dis_sd_modemux),
1606};
1607
1608/* Pad multiplexing for i2c7_dis_sd device */
1609static const unsigned i2c7_dis_sd_pins[] = { 238, 239 };
1610static struct spear_muxreg i2c7_dis_sd_muxreg[] = {
1611 {
1612 .reg = PAD_FUNCTION_EN_2,
1613 .mask = PMX_MCIRESETCF_MASK |
1614 PMX_MCICS0CE_MASK,
1615 .val = 0,
1616 },
1617};
1618
1619static struct spear_modemux i2c7_dis_sd_modemux[] = {
1620 {
1621 .muxregs = i2c7_dis_sd_muxreg,
1622 .nmuxregs = ARRAY_SIZE(i2c7_dis_sd_muxreg),
1623 },
1624};
1625
1626static struct spear_pingroup i2c7_dis_sd_pingroup = {
1627 .name = "i2c7_dis_sd_grp",
1628 .pins = i2c7_dis_sd_pins,
1629 .npins = ARRAY_SIZE(i2c7_dis_sd_pins),
1630 .modemuxs = i2c7_dis_sd_modemux,
1631 .nmodemuxs = ARRAY_SIZE(i2c7_dis_sd_modemux),
1632};
1633
1634static const char *const i2c_6_7_grps[] = { "i2c6_dis_sd_grp",
1635 "i2c7_dis_sd_grp", "i2c_6_7_dis_kbd_grp" };
1636static struct spear_function i2c_6_7_function = {
1637 .name = "i2c_6_7",
1638 .groups = i2c_6_7_grps,
1639 .ngroups = ARRAY_SIZE(i2c_6_7_grps),
1640};
1641
1642/* Pad multiplexing for can0_dis_nor device */
1643/* Muxed with NOR */
1644static const unsigned can0_dis_nor_pins[] = { 56, 57 };
1645static struct spear_muxreg can0_dis_nor_muxreg[] = {
1646 {
1647 .reg = PAD_FUNCTION_EN_0,
1648 .mask = PMX_NFRSTPWDWN2_MASK,
1649 .val = 0,
1650 }, {
1651 .reg = PAD_FUNCTION_EN_1,
1652 .mask = PMX_NFRSTPWDWN3_MASK,
1653 .val = 0,
1654 },
1655};
1656
1657static struct spear_modemux can0_dis_nor_modemux[] = {
1658 {
1659 .muxregs = can0_dis_nor_muxreg,
1660 .nmuxregs = ARRAY_SIZE(can0_dis_nor_muxreg),
1661 },
1662};
1663
1664static struct spear_pingroup can0_dis_nor_pingroup = {
1665 .name = "can0_dis_nor_grp",
1666 .pins = can0_dis_nor_pins,
1667 .npins = ARRAY_SIZE(can0_dis_nor_pins),
1668 .modemuxs = can0_dis_nor_modemux,
1669 .nmodemuxs = ARRAY_SIZE(can0_dis_nor_modemux),
1670};
1671
1672/* Pad multiplexing for can0_dis_sd device */
1673/* Muxed with SD/MMC */
1674static const unsigned can0_dis_sd_pins[] = { 240, 241 };
1675static struct spear_muxreg can0_dis_sd_muxreg[] = {
1676 {
1677 .reg = PAD_FUNCTION_EN_2,
1678 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1679 .val = 0,
1680 },
1681};
1682
1683static struct spear_modemux can0_dis_sd_modemux[] = {
1684 {
1685 .muxregs = can0_dis_sd_muxreg,
1686 .nmuxregs = ARRAY_SIZE(can0_dis_sd_muxreg),
1687 },
1688};
1689
1690static struct spear_pingroup can0_dis_sd_pingroup = {
1691 .name = "can0_dis_sd_grp",
1692 .pins = can0_dis_sd_pins,
1693 .npins = ARRAY_SIZE(can0_dis_sd_pins),
1694 .modemuxs = can0_dis_sd_modemux,
1695 .nmodemuxs = ARRAY_SIZE(can0_dis_sd_modemux),
1696};
1697
1698static const char *const can0_grps[] = { "can0_dis_nor_grp", "can0_dis_sd_grp"
1699};
1700static struct spear_function can0_function = {
1701 .name = "can0",
1702 .groups = can0_grps,
1703 .ngroups = ARRAY_SIZE(can0_grps),
1704};
1705
1706/* Pad multiplexing for can1_dis_sd device */
1707/* Muxed with SD/MMC */
1708static const unsigned can1_dis_sd_pins[] = { 242, 243 };
1709static struct spear_muxreg can1_dis_sd_muxreg[] = {
1710 {
1711 .reg = PAD_FUNCTION_EN_2,
1712 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1713 .val = 0,
1714 },
1715};
1716
1717static struct spear_modemux can1_dis_sd_modemux[] = {
1718 {
1719 .muxregs = can1_dis_sd_muxreg,
1720 .nmuxregs = ARRAY_SIZE(can1_dis_sd_muxreg),
1721 },
1722};
1723
1724static struct spear_pingroup can1_dis_sd_pingroup = {
1725 .name = "can1_dis_sd_grp",
1726 .pins = can1_dis_sd_pins,
1727 .npins = ARRAY_SIZE(can1_dis_sd_pins),
1728 .modemuxs = can1_dis_sd_modemux,
1729 .nmodemuxs = ARRAY_SIZE(can1_dis_sd_modemux),
1730};
1731
1732/* Pad multiplexing for can1_dis_kbd device */
1733/* Muxed with KBD */
1734static const unsigned can1_dis_kbd_pins[] = { 201, 202 };
1735static struct spear_muxreg can1_dis_kbd_muxreg[] = {
1736 {
1737 .reg = PAD_FUNCTION_EN_1,
1738 .mask = PMX_KBD_ROWCOL25_MASK,
1739 .val = 0,
1740 },
1741};
1742
1743static struct spear_modemux can1_dis_kbd_modemux[] = {
1744 {
1745 .muxregs = can1_dis_kbd_muxreg,
1746 .nmuxregs = ARRAY_SIZE(can1_dis_kbd_muxreg),
1747 },
1748};
1749
1750static struct spear_pingroup can1_dis_kbd_pingroup = {
1751 .name = "can1_dis_kbd_grp",
1752 .pins = can1_dis_kbd_pins,
1753 .npins = ARRAY_SIZE(can1_dis_kbd_pins),
1754 .modemuxs = can1_dis_kbd_modemux,
1755 .nmodemuxs = ARRAY_SIZE(can1_dis_kbd_modemux),
1756};
1757
1758static const char *const can1_grps[] = { "can1_dis_sd_grp", "can1_dis_kbd_grp"
1759};
1760static struct spear_function can1_function = {
1761 .name = "can1",
1762 .groups = can1_grps,
1763 .ngroups = ARRAY_SIZE(can1_grps),
1764};
1765
1766/* Pad multiplexing for pci device */
1767static const unsigned pci_sata_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
1768 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
1769 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
1770 55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 };
1771#define PCI_SATA_MUXREG \
1772 { \
1773 .reg = PAD_FUNCTION_EN_0, \
1774 .mask = PMX_MCI_DATA8_15_MASK, \
1775 .val = 0, \
1776 }, { \
1777 .reg = PAD_FUNCTION_EN_1, \
1778 .mask = PMX_PCI_REG1_MASK, \
1779 .val = 0, \
1780 }, { \
1781 .reg = PAD_FUNCTION_EN_2, \
1782 .mask = PMX_PCI_REG2_MASK, \
1783 .val = 0, \
1784 }
1785
1786/* pad multiplexing for pcie0 device */
1787static struct spear_muxreg pcie0_muxreg[] = {
1788 PCI_SATA_MUXREG,
1789 {
1790 .reg = PCIE_SATA_CFG,
1791 .mask = PCIE_CFG_VAL(0),
1792 .val = PCIE_CFG_VAL(0),
1793 },
1794};
1795
1796static struct spear_modemux pcie0_modemux[] = {
1797 {
1798 .muxregs = pcie0_muxreg,
1799 .nmuxregs = ARRAY_SIZE(pcie0_muxreg),
1800 },
1801};
1802
1803static struct spear_pingroup pcie0_pingroup = {
1804 .name = "pcie0_grp",
1805 .pins = pci_sata_pins,
1806 .npins = ARRAY_SIZE(pci_sata_pins),
1807 .modemuxs = pcie0_modemux,
1808 .nmodemuxs = ARRAY_SIZE(pcie0_modemux),
1809};
1810
1811/* pad multiplexing for pcie1 device */
1812static struct spear_muxreg pcie1_muxreg[] = {
1813 PCI_SATA_MUXREG,
1814 {
1815 .reg = PCIE_SATA_CFG,
1816 .mask = PCIE_CFG_VAL(1),
1817 .val = PCIE_CFG_VAL(1),
1818 },
1819};
1820
1821static struct spear_modemux pcie1_modemux[] = {
1822 {
1823 .muxregs = pcie1_muxreg,
1824 .nmuxregs = ARRAY_SIZE(pcie1_muxreg),
1825 },
1826};
1827
1828static struct spear_pingroup pcie1_pingroup = {
1829 .name = "pcie1_grp",
1830 .pins = pci_sata_pins,
1831 .npins = ARRAY_SIZE(pci_sata_pins),
1832 .modemuxs = pcie1_modemux,
1833 .nmodemuxs = ARRAY_SIZE(pcie1_modemux),
1834};
1835
1836/* pad multiplexing for pcie2 device */
1837static struct spear_muxreg pcie2_muxreg[] = {
1838 PCI_SATA_MUXREG,
1839 {
1840 .reg = PCIE_SATA_CFG,
1841 .mask = PCIE_CFG_VAL(2),
1842 .val = PCIE_CFG_VAL(2),
1843 },
1844};
1845
1846static struct spear_modemux pcie2_modemux[] = {
1847 {
1848 .muxregs = pcie2_muxreg,
1849 .nmuxregs = ARRAY_SIZE(pcie2_muxreg),
1850 },
1851};
1852
1853static struct spear_pingroup pcie2_pingroup = {
1854 .name = "pcie2_grp",
1855 .pins = pci_sata_pins,
1856 .npins = ARRAY_SIZE(pci_sata_pins),
1857 .modemuxs = pcie2_modemux,
1858 .nmodemuxs = ARRAY_SIZE(pcie2_modemux),
1859};
1860
1861static const char *const pci_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp" };
1862static struct spear_function pci_function = {
1863 .name = "pci",
1864 .groups = pci_grps,
1865 .ngroups = ARRAY_SIZE(pci_grps),
1866};
1867
1868/* pad multiplexing for sata0 device */
1869static struct spear_muxreg sata0_muxreg[] = {
1870 PCI_SATA_MUXREG,
1871 {
1872 .reg = PCIE_SATA_CFG,
1873 .mask = SATA_CFG_VAL(0),
1874 .val = SATA_CFG_VAL(0),
1875 },
1876};
1877
1878static struct spear_modemux sata0_modemux[] = {
1879 {
1880 .muxregs = sata0_muxreg,
1881 .nmuxregs = ARRAY_SIZE(sata0_muxreg),
1882 },
1883};
1884
1885static struct spear_pingroup sata0_pingroup = {
1886 .name = "sata0_grp",
1887 .pins = pci_sata_pins,
1888 .npins = ARRAY_SIZE(pci_sata_pins),
1889 .modemuxs = sata0_modemux,
1890 .nmodemuxs = ARRAY_SIZE(sata0_modemux),
1891};
1892
1893/* pad multiplexing for sata1 device */
1894static struct spear_muxreg sata1_muxreg[] = {
1895 PCI_SATA_MUXREG,
1896 {
1897 .reg = PCIE_SATA_CFG,
1898 .mask = SATA_CFG_VAL(1),
1899 .val = SATA_CFG_VAL(1),
1900 },
1901};
1902
1903static struct spear_modemux sata1_modemux[] = {
1904 {
1905 .muxregs = sata1_muxreg,
1906 .nmuxregs = ARRAY_SIZE(sata1_muxreg),
1907 },
1908};
1909
1910static struct spear_pingroup sata1_pingroup = {
1911 .name = "sata1_grp",
1912 .pins = pci_sata_pins,
1913 .npins = ARRAY_SIZE(pci_sata_pins),
1914 .modemuxs = sata1_modemux,
1915 .nmodemuxs = ARRAY_SIZE(sata1_modemux),
1916};
1917
1918/* pad multiplexing for sata2 device */
1919static struct spear_muxreg sata2_muxreg[] = {
1920 PCI_SATA_MUXREG,
1921 {
1922 .reg = PCIE_SATA_CFG,
1923 .mask = SATA_CFG_VAL(2),
1924 .val = SATA_CFG_VAL(2),
1925 },
1926};
1927
1928static struct spear_modemux sata2_modemux[] = {
1929 {
1930 .muxregs = sata2_muxreg,
1931 .nmuxregs = ARRAY_SIZE(sata2_muxreg),
1932 },
1933};
1934
1935static struct spear_pingroup sata2_pingroup = {
1936 .name = "sata2_grp",
1937 .pins = pci_sata_pins,
1938 .npins = ARRAY_SIZE(pci_sata_pins),
1939 .modemuxs = sata2_modemux,
1940 .nmodemuxs = ARRAY_SIZE(sata2_modemux),
1941};
1942
1943static const char *const sata_grps[] = { "sata0_grp", "sata1_grp", "sata2_grp"
1944};
1945static struct spear_function sata_function = {
1946 .name = "sata",
1947 .groups = sata_grps,
1948 .ngroups = ARRAY_SIZE(sata_grps),
1949};
1950
1951/* Pad multiplexing for ssp1_dis_kbd device */
1952static const unsigned ssp1_dis_kbd_pins[] = { 203, 204, 205, 206 };
1953static struct spear_muxreg ssp1_dis_kbd_muxreg[] = {
1954 {
1955 .reg = PAD_FUNCTION_EN_1,
1956 .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
1957 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
1958 PMX_NFCE2_MASK,
1959 .val = 0,
1960 },
1961};
1962
1963static struct spear_modemux ssp1_dis_kbd_modemux[] = {
1964 {
1965 .muxregs = ssp1_dis_kbd_muxreg,
1966 .nmuxregs = ARRAY_SIZE(ssp1_dis_kbd_muxreg),
1967 },
1968};
1969
1970static struct spear_pingroup ssp1_dis_kbd_pingroup = {
1971 .name = "ssp1_dis_kbd_grp",
1972 .pins = ssp1_dis_kbd_pins,
1973 .npins = ARRAY_SIZE(ssp1_dis_kbd_pins),
1974 .modemuxs = ssp1_dis_kbd_modemux,
1975 .nmodemuxs = ARRAY_SIZE(ssp1_dis_kbd_modemux),
1976};
1977
1978/* Pad multiplexing for ssp1_dis_sd device */
1979static const unsigned ssp1_dis_sd_pins[] = { 224, 226, 227, 228 };
1980static struct spear_muxreg ssp1_dis_sd_muxreg[] = {
1981 {
1982 .reg = PAD_FUNCTION_EN_2,
1983 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
1984 PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
1985 .val = 0,
1986 },
1987};
1988
1989static struct spear_modemux ssp1_dis_sd_modemux[] = {
1990 {
1991 .muxregs = ssp1_dis_sd_muxreg,
1992 .nmuxregs = ARRAY_SIZE(ssp1_dis_sd_muxreg),
1993 },
1994};
1995
1996static struct spear_pingroup ssp1_dis_sd_pingroup = {
1997 .name = "ssp1_dis_sd_grp",
1998 .pins = ssp1_dis_sd_pins,
1999 .npins = ARRAY_SIZE(ssp1_dis_sd_pins),
2000 .modemuxs = ssp1_dis_sd_modemux,
2001 .nmodemuxs = ARRAY_SIZE(ssp1_dis_sd_modemux),
2002};
2003
2004static const char *const ssp1_grps[] = { "ssp1_dis_kbd_grp",
2005 "ssp1_dis_sd_grp" };
2006static struct spear_function ssp1_function = {
2007 .name = "ssp1",
2008 .groups = ssp1_grps,
2009 .ngroups = ARRAY_SIZE(ssp1_grps),
2010};
2011
2012/* Pad multiplexing for gpt64 device */
2013static const unsigned gpt64_pins[] = { 230, 231, 232, 245 };
2014static struct spear_muxreg gpt64_muxreg[] = {
2015 {
2016 .reg = PAD_FUNCTION_EN_2,
2017 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2018 | PMX_MCILEDS_MASK,
2019 .val = 0,
2020 },
2021};
2022
2023static struct spear_modemux gpt64_modemux[] = {
2024 {
2025 .muxregs = gpt64_muxreg,
2026 .nmuxregs = ARRAY_SIZE(gpt64_muxreg),
2027 },
2028};
2029
2030static struct spear_pingroup gpt64_pingroup = {
2031 .name = "gpt64_grp",
2032 .pins = gpt64_pins,
2033 .npins = ARRAY_SIZE(gpt64_pins),
2034 .modemuxs = gpt64_modemux,
2035 .nmodemuxs = ARRAY_SIZE(gpt64_modemux),
2036};
2037
2038static const char *const gpt64_grps[] = { "gpt64_grp" };
2039static struct spear_function gpt64_function = {
2040 .name = "gpt64",
2041 .groups = gpt64_grps,
2042 .ngroups = ARRAY_SIZE(gpt64_grps),
2043};
2044
2045/* pingroups */
2046static struct spear_pingroup *spear1310_pingroups[] = {
2047 &i2c0_pingroup,
2048 &ssp0_pingroup,
2049 &i2s0_pingroup,
2050 &i2s1_pingroup,
2051 &clcd_pingroup,
2052 &clcd_high_res_pingroup,
2053 &arm_gpio_pingroup,
2054 &smi_2_chips_pingroup,
2055 &smi_4_chips_pingroup,
2056 &gmii_pingroup,
2057 &rgmii_pingroup,
2058 &smii_0_1_2_pingroup,
2059 &ras_mii_txclk_pingroup,
2060 &nand_8bit_pingroup,
2061 &nand_16bit_pingroup,
2062 &nand_4_chips_pingroup,
2063 &keyboard_6x6_pingroup,
2064 &keyboard_rowcol6_8_pingroup,
2065 &uart0_pingroup,
2066 &uart0_modem_pingroup,
2067 &gpt0_tmr0_pingroup,
2068 &gpt0_tmr1_pingroup,
2069 &gpt1_tmr0_pingroup,
2070 &gpt1_tmr1_pingroup,
2071 &sdhci_pingroup,
2072 &cf_pingroup,
2073 &xd_pingroup,
2074 &touch_xy_pingroup,
2075 &ssp0_cs0_pingroup,
2076 &ssp0_cs1_2_pingroup,
2077 &uart_1_dis_i2c_pingroup,
2078 &uart_1_dis_sd_pingroup,
2079 &uart_2_3_pingroup,
2080 &uart_4_pingroup,
2081 &uart_5_pingroup,
2082 &rs485_0_1_tdm_0_1_pingroup,
2083 &i2c_1_2_pingroup,
2084 &i2c3_dis_smi_clcd_pingroup,
2085 &i2c3_dis_sd_i2s0_pingroup,
2086 &i2c_4_5_dis_smi_pingroup,
2087 &i2c4_dis_sd_pingroup,
2088 &i2c5_dis_sd_pingroup,
2089 &i2c_6_7_dis_kbd_pingroup,
2090 &i2c6_dis_sd_pingroup,
2091 &i2c7_dis_sd_pingroup,
2092 &can0_dis_nor_pingroup,
2093 &can0_dis_sd_pingroup,
2094 &can1_dis_sd_pingroup,
2095 &can1_dis_kbd_pingroup,
2096 &pcie0_pingroup,
2097 &pcie1_pingroup,
2098 &pcie2_pingroup,
2099 &sata0_pingroup,
2100 &sata1_pingroup,
2101 &sata2_pingroup,
2102 &ssp1_dis_kbd_pingroup,
2103 &ssp1_dis_sd_pingroup,
2104 &gpt64_pingroup,
2105};
2106
2107/* functions */
2108static struct spear_function *spear1310_functions[] = {
2109 &i2c0_function,
2110 &ssp0_function,
2111 &i2s0_function,
2112 &i2s1_function,
2113 &clcd_function,
2114 &arm_gpio_function,
2115 &smi_function,
2116 &gmii_function,
2117 &rgmii_function,
2118 &smii_0_1_2_function,
2119 &ras_mii_txclk_function,
2120 &nand_function,
2121 &keyboard_function,
2122 &uart0_function,
2123 &gpt0_function,
2124 &gpt1_function,
2125 &sdhci_function,
2126 &cf_function,
2127 &xd_function,
2128 &touch_xy_function,
2129 &uart1_function,
2130 &uart2_3_function,
2131 &uart4_function,
2132 &uart5_function,
2133 &rs485_0_1_tdm_0_1_function,
2134 &i2c_1_2_function,
2135 &i2c3_unction,
2136 &i2c_4_5_function,
2137 &i2c_6_7_function,
2138 &can0_function,
2139 &can1_function,
2140 &pci_function,
2141 &sata_function,
2142 &ssp1_function,
2143 &gpt64_function,
2144};
2145
2146static struct spear_pinctrl_machdata spear1310_machdata = {
2147 .pins = spear1310_pins,
2148 .npins = ARRAY_SIZE(spear1310_pins),
2149 .groups = spear1310_pingroups,
2150 .ngroups = ARRAY_SIZE(spear1310_pingroups),
2151 .functions = spear1310_functions,
2152 .nfunctions = ARRAY_SIZE(spear1310_functions),
2153 .modes_supported = false,
2154};
2155
2156static struct of_device_id spear1310_pinctrl_of_match[] __devinitdata = {
2157 {
2158 .compatible = "st,spear1310-pinmux",
2159 },
2160 {},
2161};
2162
2163static int __devinit spear1310_pinctrl_probe(struct platform_device *pdev)
2164{
2165 return spear_pinctrl_probe(pdev, &spear1310_machdata);
2166}
2167
2168static int __devexit spear1310_pinctrl_remove(struct platform_device *pdev)
2169{
2170 return spear_pinctrl_remove(pdev);
2171}
2172
2173static struct platform_driver spear1310_pinctrl_driver = {
2174 .driver = {
2175 .name = DRIVER_NAME,
2176 .owner = THIS_MODULE,
2177 .of_match_table = spear1310_pinctrl_of_match,
2178 },
2179 .probe = spear1310_pinctrl_probe,
2180 .remove = __devexit_p(spear1310_pinctrl_remove),
2181};
2182
2183static int __init spear1310_pinctrl_init(void)
2184{
2185 return platform_driver_register(&spear1310_pinctrl_driver);
2186}
2187arch_initcall(spear1310_pinctrl_init);
2188
2189static void __exit spear1310_pinctrl_exit(void)
2190{
2191 platform_driver_unregister(&spear1310_pinctrl_driver);
2192}
2193module_exit(spear1310_pinctrl_exit);
2194
2195MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
2196MODULE_DESCRIPTION("ST Microelectronics SPEAr1310 pinctrl driver");
2197MODULE_LICENSE("GPL v2");
2198MODULE_DEVICE_TABLE(of, spear1310_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear1340.c b/drivers/pinctrl/spear/pinctrl-spear1340.c
new file mode 100644
index 000000000000..a8ab2a6f51bf
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear1340.c
@@ -0,0 +1,1989 @@
1/*
2 * Driver for the ST Microelectronics SPEAr1340 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear.h"
18
19#define DRIVER_NAME "spear1340-pinmux"
20
21/* pins */
22static const struct pinctrl_pin_desc spear1340_pins[] = {
23 SPEAR_PIN_0_TO_101,
24 SPEAR_PIN_102_TO_245,
25 PINCTRL_PIN(246, "PLGPIO246"),
26 PINCTRL_PIN(247, "PLGPIO247"),
27 PINCTRL_PIN(248, "PLGPIO248"),
28 PINCTRL_PIN(249, "PLGPIO249"),
29 PINCTRL_PIN(250, "PLGPIO250"),
30 PINCTRL_PIN(251, "PLGPIO251"),
31};
32
33/* In SPEAr1340 there are two levels of pad muxing */
34/* - pads as gpio OR peripherals */
35#define PAD_FUNCTION_EN_1 0x668
36#define PAD_FUNCTION_EN_2 0x66C
37#define PAD_FUNCTION_EN_3 0x670
38#define PAD_FUNCTION_EN_4 0x674
39#define PAD_FUNCTION_EN_5 0x690
40#define PAD_FUNCTION_EN_6 0x694
41#define PAD_FUNCTION_EN_7 0x698
42#define PAD_FUNCTION_EN_8 0x69C
43
44/* - If peripherals, then primary OR alternate peripheral */
45#define PAD_SHARED_IP_EN_1 0x6A0
46#define PAD_SHARED_IP_EN_2 0x6A4
47
48/*
49 * Macro's for first level of pmx - pads as gpio OR peripherals. There are 8
50 * registers with 32 bits each for handling gpio pads, register 8 has only 26
51 * relevant bits.
52 */
53/* macro's for making pads as gpio's */
54#define PADS_AS_GPIO_REG0_MASK 0xFFFFFFFE
55#define PADS_AS_GPIO_REGS_MASK 0xFFFFFFFF
56#define PADS_AS_GPIO_REG7_MASK 0x07FFFFFF
57
58/* macro's for making pads as peripherals */
59#define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK 0x00000FFE
60#define UART0_ENH_AND_GPT_REG0_MASK 0x0003F000
61#define PWM1_AND_KBD_COL5_REG0_MASK 0x00040000
62#define I2C1_REG0_MASK 0x01080000
63#define SPDIF_IN_REG0_MASK 0x00100000
64#define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK 0x00400000
65#define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK 0x00800000
66#define PWM0_AND_SSP0_CS1_REG0_MASK 0x02000000
67#define VIP_AND_CAM3_REG0_MASK 0xFC200000
68#define VIP_AND_CAM3_REG1_MASK 0x0000000F
69#define VIP_REG1_MASK 0x00001EF0
70#define VIP_AND_CAM2_REG1_MASK 0x007FE100
71#define VIP_AND_CAM1_REG1_MASK 0xFF800000
72#define VIP_AND_CAM1_REG2_MASK 0x00000003
73#define VIP_AND_CAM0_REG2_MASK 0x00001FFC
74#define SMI_REG2_MASK 0x0021E000
75#define SSP0_REG2_MASK 0x001E0000
76#define TS_AND_SSP0_CS2_REG2_MASK 0x00400000
77#define UART0_REG2_MASK 0x01800000
78#define UART1_REG2_MASK 0x06000000
79#define I2S_IN_REG2_MASK 0xF8000000
80#define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK 0x000001FE
81#define I2S_OUT_REG3_MASK 0x000001EF
82#define I2S_IN_REG3_MASK 0x00000010
83#define GMAC_REG3_MASK 0xFFFFFE00
84#define GMAC_REG4_MASK 0x0000001F
85#define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK 0x7FFFFF20
86#define SSP0_CS3_REG4_MASK 0x00000020
87#define I2C0_REG4_MASK 0x000000C0
88#define CEC0_REG4_MASK 0x00000100
89#define CEC1_REG4_MASK 0x00000200
90#define SPDIF_OUT_REG4_MASK 0x00000400
91#define CLCD_REG4_MASK 0x7FFFF800
92#define CLCD_AND_ARM_TRACE_REG4_MASK 0x80000000
93#define CLCD_AND_ARM_TRACE_REG5_MASK 0xFFFFFFFF
94#define CLCD_AND_ARM_TRACE_REG6_MASK 0x00000001
95#define FSMC_PNOR_AND_MCIF_REG6_MASK 0x073FFFFE
96#define MCIF_REG6_MASK 0xF8C00000
97#define MCIF_REG7_MASK 0x000043FF
98#define FSMC_8BIT_REG7_MASK 0x07FFBC00
99
100/* other registers */
101#define PERIP_CFG 0x42C
102 /* PERIP_CFG register masks */
103 #define SSP_CS_CTL_HW 0
104 #define SSP_CS_CTL_SW 1
105 #define SSP_CS_CTL_MASK 1
106 #define SSP_CS_CTL_SHIFT 21
107 #define SSP_CS_VAL_MASK 1
108 #define SSP_CS_VAL_SHIFT 20
109 #define SSP_CS_SEL_CS0 0
110 #define SSP_CS_SEL_CS1 1
111 #define SSP_CS_SEL_CS2 2
112 #define SSP_CS_SEL_MASK 3
113 #define SSP_CS_SEL_SHIFT 18
114
115 #define I2S_CHNL_2_0 (0)
116 #define I2S_CHNL_3_1 (1)
117 #define I2S_CHNL_5_1 (2)
118 #define I2S_CHNL_7_1 (3)
119 #define I2S_CHNL_PLAY_SHIFT (4)
120 #define I2S_CHNL_PLAY_MASK (3 << 4)
121 #define I2S_CHNL_REC_SHIFT (6)
122 #define I2S_CHNL_REC_MASK (3 << 6)
123
124 #define SPDIF_OUT_ENB_MASK (1 << 2)
125 #define SPDIF_OUT_ENB_SHIFT 2
126
127 #define MCIF_SEL_SD 1
128 #define MCIF_SEL_CF 2
129 #define MCIF_SEL_XD 3
130 #define MCIF_SEL_MASK 3
131 #define MCIF_SEL_SHIFT 0
132
133#define GMAC_CLK_CFG 0x248
134 #define GMAC_PHY_IF_GMII_VAL (0 << 3)
135 #define GMAC_PHY_IF_RGMII_VAL (1 << 3)
136 #define GMAC_PHY_IF_SGMII_VAL (2 << 3)
137 #define GMAC_PHY_IF_RMII_VAL (4 << 3)
138 #define GMAC_PHY_IF_SEL_MASK (7 << 3)
139 #define GMAC_PHY_INPUT_ENB_VAL 0
140 #define GMAC_PHY_SYNT_ENB_VAL 1
141 #define GMAC_PHY_CLK_MASK 1
142 #define GMAC_PHY_CLK_SHIFT 2
143 #define GMAC_PHY_125M_PAD_VAL 0
144 #define GMAC_PHY_PLL2_VAL 1
145 #define GMAC_PHY_OSC3_VAL 2
146 #define GMAC_PHY_INPUT_CLK_MASK 3
147 #define GMAC_PHY_INPUT_CLK_SHIFT 0
148
149#define PCIE_SATA_CFG 0x424
150 /* PCIE CFG MASks */
151 #define PCIE_CFG_DEVICE_PRESENT (1 << 11)
152 #define PCIE_CFG_POWERUP_RESET (1 << 10)
153 #define PCIE_CFG_CORE_CLK_EN (1 << 9)
154 #define PCIE_CFG_AUX_CLK_EN (1 << 8)
155 #define SATA_CFG_TX_CLK_EN (1 << 4)
156 #define SATA_CFG_RX_CLK_EN (1 << 3)
157 #define SATA_CFG_POWERUP_RESET (1 << 2)
158 #define SATA_CFG_PM_CLK_EN (1 << 1)
159 #define PCIE_SATA_SEL_PCIE (0)
160 #define PCIE_SATA_SEL_SATA (1)
161 #define SATA_PCIE_CFG_MASK 0xF1F
162 #define PCIE_CFG_VAL (PCIE_SATA_SEL_PCIE | PCIE_CFG_AUX_CLK_EN | \
163 PCIE_CFG_CORE_CLK_EN | PCIE_CFG_POWERUP_RESET |\
164 PCIE_CFG_DEVICE_PRESENT)
165 #define SATA_CFG_VAL (PCIE_SATA_SEL_SATA | SATA_CFG_PM_CLK_EN | \
166 SATA_CFG_POWERUP_RESET | SATA_CFG_RX_CLK_EN | \
167 SATA_CFG_TX_CLK_EN)
168
169/* Macro's for second level of pmx - pads as primary OR alternate peripheral */
170/* Write 0 to enable FSMC_16_BIT */
171#define KBD_ROW_COL_MASK (1 << 0)
172
173/* Write 0 to enable UART0_ENH */
174#define GPT_MASK (1 << 1) /* Only clk & cpt */
175
176/* Write 0 to enable PWM1 */
177#define KBD_COL5_MASK (1 << 2)
178
179/* Write 0 to enable PWM2 */
180#define GPT0_TMR0_CPT_MASK (1 << 3) /* Only clk & cpt */
181
182/* Write 0 to enable PWM3 */
183#define GPT0_TMR1_CLK_MASK (1 << 4) /* Only clk & cpt */
184
185/* Write 0 to enable PWM0 */
186#define SSP0_CS1_MASK (1 << 5)
187
188/* Write 0 to enable VIP */
189#define CAM3_MASK (1 << 6)
190
191/* Write 0 to enable VIP */
192#define CAM2_MASK (1 << 7)
193
194/* Write 0 to enable VIP */
195#define CAM1_MASK (1 << 8)
196
197/* Write 0 to enable VIP */
198#define CAM0_MASK (1 << 9)
199
200/* Write 0 to enable TS */
201#define SSP0_CS2_MASK (1 << 10)
202
203/* Write 0 to enable FSMC PNOR */
204#define MCIF_MASK (1 << 11)
205
206/* Write 0 to enable CLCD */
207#define ARM_TRACE_MASK (1 << 12)
208
209/* Write 0 to enable I2S, SSP0_CS2, CEC0, 1, SPDIF out, CLCD */
210#define MIPHY_DBG_MASK (1 << 13)
211
212/*
213 * Pad multiplexing for making all pads as gpio's. This is done to override the
214 * values passed from bootloader and start from scratch.
215 */
216static const unsigned pads_as_gpio_pins[] = { 251 };
217static struct spear_muxreg pads_as_gpio_muxreg[] = {
218 {
219 .reg = PAD_FUNCTION_EN_1,
220 .mask = PADS_AS_GPIO_REG0_MASK,
221 .val = 0x0,
222 }, {
223 .reg = PAD_FUNCTION_EN_2,
224 .mask = PADS_AS_GPIO_REGS_MASK,
225 .val = 0x0,
226 }, {
227 .reg = PAD_FUNCTION_EN_3,
228 .mask = PADS_AS_GPIO_REGS_MASK,
229 .val = 0x0,
230 }, {
231 .reg = PAD_FUNCTION_EN_4,
232 .mask = PADS_AS_GPIO_REGS_MASK,
233 .val = 0x0,
234 }, {
235 .reg = PAD_FUNCTION_EN_5,
236 .mask = PADS_AS_GPIO_REGS_MASK,
237 .val = 0x0,
238 }, {
239 .reg = PAD_FUNCTION_EN_6,
240 .mask = PADS_AS_GPIO_REGS_MASK,
241 .val = 0x0,
242 }, {
243 .reg = PAD_FUNCTION_EN_7,
244 .mask = PADS_AS_GPIO_REGS_MASK,
245 .val = 0x0,
246 }, {
247 .reg = PAD_FUNCTION_EN_8,
248 .mask = PADS_AS_GPIO_REG7_MASK,
249 .val = 0x0,
250 },
251};
252
253static struct spear_modemux pads_as_gpio_modemux[] = {
254 {
255 .muxregs = pads_as_gpio_muxreg,
256 .nmuxregs = ARRAY_SIZE(pads_as_gpio_muxreg),
257 },
258};
259
260static struct spear_pingroup pads_as_gpio_pingroup = {
261 .name = "pads_as_gpio_grp",
262 .pins = pads_as_gpio_pins,
263 .npins = ARRAY_SIZE(pads_as_gpio_pins),
264 .modemuxs = pads_as_gpio_modemux,
265 .nmodemuxs = ARRAY_SIZE(pads_as_gpio_modemux),
266};
267
268static const char *const pads_as_gpio_grps[] = { "pads_as_gpio_grp" };
269static struct spear_function pads_as_gpio_function = {
270 .name = "pads_as_gpio",
271 .groups = pads_as_gpio_grps,
272 .ngroups = ARRAY_SIZE(pads_as_gpio_grps),
273};
274
275/* Pad multiplexing for fsmc_8bit device */
276static const unsigned fsmc_8bit_pins[] = { 233, 234, 235, 236, 238, 239, 240,
277 241, 242, 243, 244, 245, 246, 247, 248, 249 };
278static struct spear_muxreg fsmc_8bit_muxreg[] = {
279 {
280 .reg = PAD_FUNCTION_EN_8,
281 .mask = FSMC_8BIT_REG7_MASK,
282 .val = FSMC_8BIT_REG7_MASK,
283 }
284};
285
286static struct spear_modemux fsmc_8bit_modemux[] = {
287 {
288 .muxregs = fsmc_8bit_muxreg,
289 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
290 },
291};
292
293static struct spear_pingroup fsmc_8bit_pingroup = {
294 .name = "fsmc_8bit_grp",
295 .pins = fsmc_8bit_pins,
296 .npins = ARRAY_SIZE(fsmc_8bit_pins),
297 .modemuxs = fsmc_8bit_modemux,
298 .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
299};
300
301/* Pad multiplexing for fsmc_16bit device */
302static const unsigned fsmc_16bit_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };
303static struct spear_muxreg fsmc_16bit_muxreg[] = {
304 {
305 .reg = PAD_SHARED_IP_EN_1,
306 .mask = KBD_ROW_COL_MASK,
307 .val = 0,
308 }, {
309 .reg = PAD_FUNCTION_EN_1,
310 .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
311 .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
312 },
313};
314
315static struct spear_modemux fsmc_16bit_modemux[] = {
316 {
317 .muxregs = fsmc_16bit_muxreg,
318 .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
319 },
320};
321
322static struct spear_pingroup fsmc_16bit_pingroup = {
323 .name = "fsmc_16bit_grp",
324 .pins = fsmc_16bit_pins,
325 .npins = ARRAY_SIZE(fsmc_16bit_pins),
326 .modemuxs = fsmc_16bit_modemux,
327 .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
328};
329
330/* pad multiplexing for fsmc_pnor device */
331static const unsigned fsmc_pnor_pins[] = { 192, 193, 194, 195, 196, 197, 198,
332 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212,
333 215, 216, 217 };
334static struct spear_muxreg fsmc_pnor_muxreg[] = {
335 {
336 .reg = PAD_SHARED_IP_EN_1,
337 .mask = MCIF_MASK,
338 .val = 0,
339 }, {
340 .reg = PAD_FUNCTION_EN_7,
341 .mask = FSMC_PNOR_AND_MCIF_REG6_MASK,
342 .val = FSMC_PNOR_AND_MCIF_REG6_MASK,
343 },
344};
345
346static struct spear_modemux fsmc_pnor_modemux[] = {
347 {
348 .muxregs = fsmc_pnor_muxreg,
349 .nmuxregs = ARRAY_SIZE(fsmc_pnor_muxreg),
350 },
351};
352
353static struct spear_pingroup fsmc_pnor_pingroup = {
354 .name = "fsmc_pnor_grp",
355 .pins = fsmc_pnor_pins,
356 .npins = ARRAY_SIZE(fsmc_pnor_pins),
357 .modemuxs = fsmc_pnor_modemux,
358 .nmodemuxs = ARRAY_SIZE(fsmc_pnor_modemux),
359};
360
361static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp",
362 "fsmc_pnor_grp" };
363static struct spear_function fsmc_function = {
364 .name = "fsmc",
365 .groups = fsmc_grps,
366 .ngroups = ARRAY_SIZE(fsmc_grps),
367};
368
369/* pad multiplexing for keyboard rows-cols device */
370static const unsigned keyboard_row_col_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
371 10 };
372static struct spear_muxreg keyboard_row_col_muxreg[] = {
373 {
374 .reg = PAD_SHARED_IP_EN_1,
375 .mask = KBD_ROW_COL_MASK,
376 .val = KBD_ROW_COL_MASK,
377 }, {
378 .reg = PAD_FUNCTION_EN_1,
379 .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
380 .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
381 },
382};
383
384static struct spear_modemux keyboard_row_col_modemux[] = {
385 {
386 .muxregs = keyboard_row_col_muxreg,
387 .nmuxregs = ARRAY_SIZE(keyboard_row_col_muxreg),
388 },
389};
390
391static struct spear_pingroup keyboard_row_col_pingroup = {
392 .name = "keyboard_row_col_grp",
393 .pins = keyboard_row_col_pins,
394 .npins = ARRAY_SIZE(keyboard_row_col_pins),
395 .modemuxs = keyboard_row_col_modemux,
396 .nmodemuxs = ARRAY_SIZE(keyboard_row_col_modemux),
397};
398
399/* pad multiplexing for keyboard col5 device */
400static const unsigned keyboard_col5_pins[] = { 17 };
401static struct spear_muxreg keyboard_col5_muxreg[] = {
402 {
403 .reg = PAD_SHARED_IP_EN_1,
404 .mask = KBD_COL5_MASK,
405 .val = KBD_COL5_MASK,
406 }, {
407 .reg = PAD_FUNCTION_EN_1,
408 .mask = PWM1_AND_KBD_COL5_REG0_MASK,
409 .val = PWM1_AND_KBD_COL5_REG0_MASK,
410 },
411};
412
413static struct spear_modemux keyboard_col5_modemux[] = {
414 {
415 .muxregs = keyboard_col5_muxreg,
416 .nmuxregs = ARRAY_SIZE(keyboard_col5_muxreg),
417 },
418};
419
420static struct spear_pingroup keyboard_col5_pingroup = {
421 .name = "keyboard_col5_grp",
422 .pins = keyboard_col5_pins,
423 .npins = ARRAY_SIZE(keyboard_col5_pins),
424 .modemuxs = keyboard_col5_modemux,
425 .nmodemuxs = ARRAY_SIZE(keyboard_col5_modemux),
426};
427
428static const char *const keyboard_grps[] = { "keyboard_row_col_grp",
429 "keyboard_col5_grp" };
430static struct spear_function keyboard_function = {
431 .name = "keyboard",
432 .groups = keyboard_grps,
433 .ngroups = ARRAY_SIZE(keyboard_grps),
434};
435
436/* pad multiplexing for spdif_in device */
437static const unsigned spdif_in_pins[] = { 19 };
438static struct spear_muxreg spdif_in_muxreg[] = {
439 {
440 .reg = PAD_FUNCTION_EN_1,
441 .mask = SPDIF_IN_REG0_MASK,
442 .val = SPDIF_IN_REG0_MASK,
443 },
444};
445
446static struct spear_modemux spdif_in_modemux[] = {
447 {
448 .muxregs = spdif_in_muxreg,
449 .nmuxregs = ARRAY_SIZE(spdif_in_muxreg),
450 },
451};
452
453static struct spear_pingroup spdif_in_pingroup = {
454 .name = "spdif_in_grp",
455 .pins = spdif_in_pins,
456 .npins = ARRAY_SIZE(spdif_in_pins),
457 .modemuxs = spdif_in_modemux,
458 .nmodemuxs = ARRAY_SIZE(spdif_in_modemux),
459};
460
461static const char *const spdif_in_grps[] = { "spdif_in_grp" };
462static struct spear_function spdif_in_function = {
463 .name = "spdif_in",
464 .groups = spdif_in_grps,
465 .ngroups = ARRAY_SIZE(spdif_in_grps),
466};
467
468/* pad multiplexing for spdif_out device */
469static const unsigned spdif_out_pins[] = { 137 };
470static struct spear_muxreg spdif_out_muxreg[] = {
471 {
472 .reg = PAD_FUNCTION_EN_5,
473 .mask = SPDIF_OUT_REG4_MASK,
474 .val = SPDIF_OUT_REG4_MASK,
475 }, {
476 .reg = PERIP_CFG,
477 .mask = SPDIF_OUT_ENB_MASK,
478 .val = SPDIF_OUT_ENB_MASK,
479 }
480};
481
482static struct spear_modemux spdif_out_modemux[] = {
483 {
484 .muxregs = spdif_out_muxreg,
485 .nmuxregs = ARRAY_SIZE(spdif_out_muxreg),
486 },
487};
488
489static struct spear_pingroup spdif_out_pingroup = {
490 .name = "spdif_out_grp",
491 .pins = spdif_out_pins,
492 .npins = ARRAY_SIZE(spdif_out_pins),
493 .modemuxs = spdif_out_modemux,
494 .nmodemuxs = ARRAY_SIZE(spdif_out_modemux),
495};
496
497static const char *const spdif_out_grps[] = { "spdif_out_grp" };
498static struct spear_function spdif_out_function = {
499 .name = "spdif_out",
500 .groups = spdif_out_grps,
501 .ngroups = ARRAY_SIZE(spdif_out_grps),
502};
503
504/* pad multiplexing for gpt_0_1 device */
505static const unsigned gpt_0_1_pins[] = { 11, 12, 13, 14, 15, 16, 21, 22 };
506static struct spear_muxreg gpt_0_1_muxreg[] = {
507 {
508 .reg = PAD_SHARED_IP_EN_1,
509 .mask = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
510 .val = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
511 }, {
512 .reg = PAD_FUNCTION_EN_1,
513 .mask = UART0_ENH_AND_GPT_REG0_MASK |
514 PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
515 PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
516 .val = UART0_ENH_AND_GPT_REG0_MASK |
517 PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
518 PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
519 },
520};
521
522static struct spear_modemux gpt_0_1_modemux[] = {
523 {
524 .muxregs = gpt_0_1_muxreg,
525 .nmuxregs = ARRAY_SIZE(gpt_0_1_muxreg),
526 },
527};
528
529static struct spear_pingroup gpt_0_1_pingroup = {
530 .name = "gpt_0_1_grp",
531 .pins = gpt_0_1_pins,
532 .npins = ARRAY_SIZE(gpt_0_1_pins),
533 .modemuxs = gpt_0_1_modemux,
534 .nmodemuxs = ARRAY_SIZE(gpt_0_1_modemux),
535};
536
537static const char *const gpt_0_1_grps[] = { "gpt_0_1_grp" };
538static struct spear_function gpt_0_1_function = {
539 .name = "gpt_0_1",
540 .groups = gpt_0_1_grps,
541 .ngroups = ARRAY_SIZE(gpt_0_1_grps),
542};
543
544/* pad multiplexing for pwm0 device */
545static const unsigned pwm0_pins[] = { 24 };
546static struct spear_muxreg pwm0_muxreg[] = {
547 {
548 .reg = PAD_SHARED_IP_EN_1,
549 .mask = SSP0_CS1_MASK,
550 .val = 0,
551 }, {
552 .reg = PAD_FUNCTION_EN_1,
553 .mask = PWM0_AND_SSP0_CS1_REG0_MASK,
554 .val = PWM0_AND_SSP0_CS1_REG0_MASK,
555 },
556};
557
558static struct spear_modemux pwm0_modemux[] = {
559 {
560 .muxregs = pwm0_muxreg,
561 .nmuxregs = ARRAY_SIZE(pwm0_muxreg),
562 },
563};
564
565static struct spear_pingroup pwm0_pingroup = {
566 .name = "pwm0_grp",
567 .pins = pwm0_pins,
568 .npins = ARRAY_SIZE(pwm0_pins),
569 .modemuxs = pwm0_modemux,
570 .nmodemuxs = ARRAY_SIZE(pwm0_modemux),
571};
572
573/* pad multiplexing for pwm1 device */
574static const unsigned pwm1_pins[] = { 17 };
575static struct spear_muxreg pwm1_muxreg[] = {
576 {
577 .reg = PAD_SHARED_IP_EN_1,
578 .mask = KBD_COL5_MASK,
579 .val = 0,
580 }, {
581 .reg = PAD_FUNCTION_EN_1,
582 .mask = PWM1_AND_KBD_COL5_REG0_MASK,
583 .val = PWM1_AND_KBD_COL5_REG0_MASK,
584 },
585};
586
587static struct spear_modemux pwm1_modemux[] = {
588 {
589 .muxregs = pwm1_muxreg,
590 .nmuxregs = ARRAY_SIZE(pwm1_muxreg),
591 },
592};
593
594static struct spear_pingroup pwm1_pingroup = {
595 .name = "pwm1_grp",
596 .pins = pwm1_pins,
597 .npins = ARRAY_SIZE(pwm1_pins),
598 .modemuxs = pwm1_modemux,
599 .nmodemuxs = ARRAY_SIZE(pwm1_modemux),
600};
601
602/* pad multiplexing for pwm2 device */
603static const unsigned pwm2_pins[] = { 21 };
604static struct spear_muxreg pwm2_muxreg[] = {
605 {
606 .reg = PAD_SHARED_IP_EN_1,
607 .mask = GPT0_TMR0_CPT_MASK,
608 .val = 0,
609 }, {
610 .reg = PAD_FUNCTION_EN_1,
611 .mask = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
612 .val = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
613 },
614};
615
616static struct spear_modemux pwm2_modemux[] = {
617 {
618 .muxregs = pwm2_muxreg,
619 .nmuxregs = ARRAY_SIZE(pwm2_muxreg),
620 },
621};
622
623static struct spear_pingroup pwm2_pingroup = {
624 .name = "pwm2_grp",
625 .pins = pwm2_pins,
626 .npins = ARRAY_SIZE(pwm2_pins),
627 .modemuxs = pwm2_modemux,
628 .nmodemuxs = ARRAY_SIZE(pwm2_modemux),
629};
630
631/* pad multiplexing for pwm3 device */
632static const unsigned pwm3_pins[] = { 22 };
633static struct spear_muxreg pwm3_muxreg[] = {
634 {
635 .reg = PAD_SHARED_IP_EN_1,
636 .mask = GPT0_TMR1_CLK_MASK,
637 .val = 0,
638 }, {
639 .reg = PAD_FUNCTION_EN_1,
640 .mask = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
641 .val = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
642 },
643};
644
645static struct spear_modemux pwm3_modemux[] = {
646 {
647 .muxregs = pwm3_muxreg,
648 .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
649 },
650};
651
652static struct spear_pingroup pwm3_pingroup = {
653 .name = "pwm3_grp",
654 .pins = pwm3_pins,
655 .npins = ARRAY_SIZE(pwm3_pins),
656 .modemuxs = pwm3_modemux,
657 .nmodemuxs = ARRAY_SIZE(pwm3_modemux),
658};
659
660static const char *const pwm_grps[] = { "pwm0_grp", "pwm1_grp", "pwm2_grp",
661 "pwm3_grp" };
662static struct spear_function pwm_function = {
663 .name = "pwm",
664 .groups = pwm_grps,
665 .ngroups = ARRAY_SIZE(pwm_grps),
666};
667
668/* pad multiplexing for vip_mux device */
669static const unsigned vip_mux_pins[] = { 35, 36, 37, 38, 40, 41, 42, 43 };
670static struct spear_muxreg vip_mux_muxreg[] = {
671 {
672 .reg = PAD_FUNCTION_EN_2,
673 .mask = VIP_REG1_MASK,
674 .val = VIP_REG1_MASK,
675 },
676};
677
678static struct spear_modemux vip_mux_modemux[] = {
679 {
680 .muxregs = vip_mux_muxreg,
681 .nmuxregs = ARRAY_SIZE(vip_mux_muxreg),
682 },
683};
684
685static struct spear_pingroup vip_mux_pingroup = {
686 .name = "vip_mux_grp",
687 .pins = vip_mux_pins,
688 .npins = ARRAY_SIZE(vip_mux_pins),
689 .modemuxs = vip_mux_modemux,
690 .nmodemuxs = ARRAY_SIZE(vip_mux_modemux),
691};
692
693/* pad multiplexing for vip_mux_cam0 (disables cam0) device */
694static const unsigned vip_mux_cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72,
695 73, 74, 75 };
696static struct spear_muxreg vip_mux_cam0_muxreg[] = {
697 {
698 .reg = PAD_SHARED_IP_EN_1,
699 .mask = CAM0_MASK,
700 .val = 0,
701 }, {
702 .reg = PAD_FUNCTION_EN_3,
703 .mask = VIP_AND_CAM0_REG2_MASK,
704 .val = VIP_AND_CAM0_REG2_MASK,
705 },
706};
707
708static struct spear_modemux vip_mux_cam0_modemux[] = {
709 {
710 .muxregs = vip_mux_cam0_muxreg,
711 .nmuxregs = ARRAY_SIZE(vip_mux_cam0_muxreg),
712 },
713};
714
715static struct spear_pingroup vip_mux_cam0_pingroup = {
716 .name = "vip_mux_cam0_grp",
717 .pins = vip_mux_cam0_pins,
718 .npins = ARRAY_SIZE(vip_mux_cam0_pins),
719 .modemuxs = vip_mux_cam0_modemux,
720 .nmodemuxs = ARRAY_SIZE(vip_mux_cam0_modemux),
721};
722
723/* pad multiplexing for vip_mux_cam1 (disables cam1) device */
724static const unsigned vip_mux_cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61,
725 62, 63, 64 };
726static struct spear_muxreg vip_mux_cam1_muxreg[] = {
727 {
728 .reg = PAD_SHARED_IP_EN_1,
729 .mask = CAM1_MASK,
730 .val = 0,
731 }, {
732 .reg = PAD_FUNCTION_EN_2,
733 .mask = VIP_AND_CAM1_REG1_MASK,
734 .val = VIP_AND_CAM1_REG1_MASK,
735 }, {
736 .reg = PAD_FUNCTION_EN_3,
737 .mask = VIP_AND_CAM1_REG2_MASK,
738 .val = VIP_AND_CAM1_REG2_MASK,
739 },
740};
741
742static struct spear_modemux vip_mux_cam1_modemux[] = {
743 {
744 .muxregs = vip_mux_cam1_muxreg,
745 .nmuxregs = ARRAY_SIZE(vip_mux_cam1_muxreg),
746 },
747};
748
749static struct spear_pingroup vip_mux_cam1_pingroup = {
750 .name = "vip_mux_cam1_grp",
751 .pins = vip_mux_cam1_pins,
752 .npins = ARRAY_SIZE(vip_mux_cam1_pins),
753 .modemuxs = vip_mux_cam1_modemux,
754 .nmodemuxs = ARRAY_SIZE(vip_mux_cam1_modemux),
755};
756
757/* pad multiplexing for vip_mux_cam2 (disables cam2) device */
758static const unsigned vip_mux_cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50,
759 51, 52, 53 };
760static struct spear_muxreg vip_mux_cam2_muxreg[] = {
761 {
762 .reg = PAD_SHARED_IP_EN_1,
763 .mask = CAM2_MASK,
764 .val = 0,
765 }, {
766 .reg = PAD_FUNCTION_EN_2,
767 .mask = VIP_AND_CAM2_REG1_MASK,
768 .val = VIP_AND_CAM2_REG1_MASK,
769 },
770};
771
772static struct spear_modemux vip_mux_cam2_modemux[] = {
773 {
774 .muxregs = vip_mux_cam2_muxreg,
775 .nmuxregs = ARRAY_SIZE(vip_mux_cam2_muxreg),
776 },
777};
778
779static struct spear_pingroup vip_mux_cam2_pingroup = {
780 .name = "vip_mux_cam2_grp",
781 .pins = vip_mux_cam2_pins,
782 .npins = ARRAY_SIZE(vip_mux_cam2_pins),
783 .modemuxs = vip_mux_cam2_modemux,
784 .nmodemuxs = ARRAY_SIZE(vip_mux_cam2_modemux),
785};
786
787/* pad multiplexing for vip_mux_cam3 (disables cam3) device */
788static const unsigned vip_mux_cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31,
789 32, 33, 34 };
790static struct spear_muxreg vip_mux_cam3_muxreg[] = {
791 {
792 .reg = PAD_SHARED_IP_EN_1,
793 .mask = CAM3_MASK,
794 .val = 0,
795 }, {
796 .reg = PAD_FUNCTION_EN_1,
797 .mask = VIP_AND_CAM3_REG0_MASK,
798 .val = VIP_AND_CAM3_REG0_MASK,
799 }, {
800 .reg = PAD_FUNCTION_EN_2,
801 .mask = VIP_AND_CAM3_REG1_MASK,
802 .val = VIP_AND_CAM3_REG1_MASK,
803 },
804};
805
806static struct spear_modemux vip_mux_cam3_modemux[] = {
807 {
808 .muxregs = vip_mux_cam3_muxreg,
809 .nmuxregs = ARRAY_SIZE(vip_mux_cam3_muxreg),
810 },
811};
812
813static struct spear_pingroup vip_mux_cam3_pingroup = {
814 .name = "vip_mux_cam3_grp",
815 .pins = vip_mux_cam3_pins,
816 .npins = ARRAY_SIZE(vip_mux_cam3_pins),
817 .modemuxs = vip_mux_cam3_modemux,
818 .nmodemuxs = ARRAY_SIZE(vip_mux_cam3_modemux),
819};
820
821static const char *const vip_grps[] = { "vip_mux_grp", "vip_mux_cam0_grp" ,
822 "vip_mux_cam1_grp" , "vip_mux_cam2_grp", "vip_mux_cam3_grp" };
823static struct spear_function vip_function = {
824 .name = "vip",
825 .groups = vip_grps,
826 .ngroups = ARRAY_SIZE(vip_grps),
827};
828
829/* pad multiplexing for cam0 device */
830static const unsigned cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75
831};
832static struct spear_muxreg cam0_muxreg[] = {
833 {
834 .reg = PAD_SHARED_IP_EN_1,
835 .mask = CAM0_MASK,
836 .val = CAM0_MASK,
837 }, {
838 .reg = PAD_FUNCTION_EN_3,
839 .mask = VIP_AND_CAM0_REG2_MASK,
840 .val = VIP_AND_CAM0_REG2_MASK,
841 },
842};
843
844static struct spear_modemux cam0_modemux[] = {
845 {
846 .muxregs = cam0_muxreg,
847 .nmuxregs = ARRAY_SIZE(cam0_muxreg),
848 },
849};
850
851static struct spear_pingroup cam0_pingroup = {
852 .name = "cam0_grp",
853 .pins = cam0_pins,
854 .npins = ARRAY_SIZE(cam0_pins),
855 .modemuxs = cam0_modemux,
856 .nmodemuxs = ARRAY_SIZE(cam0_modemux),
857};
858
859static const char *const cam0_grps[] = { "cam0_grp" };
860static struct spear_function cam0_function = {
861 .name = "cam0",
862 .groups = cam0_grps,
863 .ngroups = ARRAY_SIZE(cam0_grps),
864};
865
866/* pad multiplexing for cam1 device */
867static const unsigned cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
868};
869static struct spear_muxreg cam1_muxreg[] = {
870 {
871 .reg = PAD_SHARED_IP_EN_1,
872 .mask = CAM1_MASK,
873 .val = CAM1_MASK,
874 }, {
875 .reg = PAD_FUNCTION_EN_2,
876 .mask = VIP_AND_CAM1_REG1_MASK,
877 .val = VIP_AND_CAM1_REG1_MASK,
878 }, {
879 .reg = PAD_FUNCTION_EN_3,
880 .mask = VIP_AND_CAM1_REG2_MASK,
881 .val = VIP_AND_CAM1_REG2_MASK,
882 },
883};
884
885static struct spear_modemux cam1_modemux[] = {
886 {
887 .muxregs = cam1_muxreg,
888 .nmuxregs = ARRAY_SIZE(cam1_muxreg),
889 },
890};
891
892static struct spear_pingroup cam1_pingroup = {
893 .name = "cam1_grp",
894 .pins = cam1_pins,
895 .npins = ARRAY_SIZE(cam1_pins),
896 .modemuxs = cam1_modemux,
897 .nmodemuxs = ARRAY_SIZE(cam1_modemux),
898};
899
900static const char *const cam1_grps[] = { "cam1_grp" };
901static struct spear_function cam1_function = {
902 .name = "cam1",
903 .groups = cam1_grps,
904 .ngroups = ARRAY_SIZE(cam1_grps),
905};
906
907/* pad multiplexing for cam2 device */
908static const unsigned cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53
909};
910static struct spear_muxreg cam2_muxreg[] = {
911 {
912 .reg = PAD_SHARED_IP_EN_1,
913 .mask = CAM2_MASK,
914 .val = CAM2_MASK,
915 }, {
916 .reg = PAD_FUNCTION_EN_2,
917 .mask = VIP_AND_CAM2_REG1_MASK,
918 .val = VIP_AND_CAM2_REG1_MASK,
919 },
920};
921
922static struct spear_modemux cam2_modemux[] = {
923 {
924 .muxregs = cam2_muxreg,
925 .nmuxregs = ARRAY_SIZE(cam2_muxreg),
926 },
927};
928
929static struct spear_pingroup cam2_pingroup = {
930 .name = "cam2_grp",
931 .pins = cam2_pins,
932 .npins = ARRAY_SIZE(cam2_pins),
933 .modemuxs = cam2_modemux,
934 .nmodemuxs = ARRAY_SIZE(cam2_modemux),
935};
936
937static const char *const cam2_grps[] = { "cam2_grp" };
938static struct spear_function cam2_function = {
939 .name = "cam2",
940 .groups = cam2_grps,
941 .ngroups = ARRAY_SIZE(cam2_grps),
942};
943
944/* pad multiplexing for cam3 device */
945static const unsigned cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34
946};
947static struct spear_muxreg cam3_muxreg[] = {
948 {
949 .reg = PAD_SHARED_IP_EN_1,
950 .mask = CAM3_MASK,
951 .val = CAM3_MASK,
952 }, {
953 .reg = PAD_FUNCTION_EN_1,
954 .mask = VIP_AND_CAM3_REG0_MASK,
955 .val = VIP_AND_CAM3_REG0_MASK,
956 }, {
957 .reg = PAD_FUNCTION_EN_2,
958 .mask = VIP_AND_CAM3_REG1_MASK,
959 .val = VIP_AND_CAM3_REG1_MASK,
960 },
961};
962
963static struct spear_modemux cam3_modemux[] = {
964 {
965 .muxregs = cam3_muxreg,
966 .nmuxregs = ARRAY_SIZE(cam3_muxreg),
967 },
968};
969
970static struct spear_pingroup cam3_pingroup = {
971 .name = "cam3_grp",
972 .pins = cam3_pins,
973 .npins = ARRAY_SIZE(cam3_pins),
974 .modemuxs = cam3_modemux,
975 .nmodemuxs = ARRAY_SIZE(cam3_modemux),
976};
977
978static const char *const cam3_grps[] = { "cam3_grp" };
979static struct spear_function cam3_function = {
980 .name = "cam3",
981 .groups = cam3_grps,
982 .ngroups = ARRAY_SIZE(cam3_grps),
983};
984
985/* pad multiplexing for smi device */
986static const unsigned smi_pins[] = { 76, 77, 78, 79, 84 };
987static struct spear_muxreg smi_muxreg[] = {
988 {
989 .reg = PAD_FUNCTION_EN_3,
990 .mask = SMI_REG2_MASK,
991 .val = SMI_REG2_MASK,
992 },
993};
994
995static struct spear_modemux smi_modemux[] = {
996 {
997 .muxregs = smi_muxreg,
998 .nmuxregs = ARRAY_SIZE(smi_muxreg),
999 },
1000};
1001
1002static struct spear_pingroup smi_pingroup = {
1003 .name = "smi_grp",
1004 .pins = smi_pins,
1005 .npins = ARRAY_SIZE(smi_pins),
1006 .modemuxs = smi_modemux,
1007 .nmodemuxs = ARRAY_SIZE(smi_modemux),
1008};
1009
1010static const char *const smi_grps[] = { "smi_grp" };
1011static struct spear_function smi_function = {
1012 .name = "smi",
1013 .groups = smi_grps,
1014 .ngroups = ARRAY_SIZE(smi_grps),
1015};
1016
1017/* pad multiplexing for ssp0 device */
1018static const unsigned ssp0_pins[] = { 80, 81, 82, 83 };
1019static struct spear_muxreg ssp0_muxreg[] = {
1020 {
1021 .reg = PAD_FUNCTION_EN_3,
1022 .mask = SSP0_REG2_MASK,
1023 .val = SSP0_REG2_MASK,
1024 },
1025};
1026
1027static struct spear_modemux ssp0_modemux[] = {
1028 {
1029 .muxregs = ssp0_muxreg,
1030 .nmuxregs = ARRAY_SIZE(ssp0_muxreg),
1031 },
1032};
1033
1034static struct spear_pingroup ssp0_pingroup = {
1035 .name = "ssp0_grp",
1036 .pins = ssp0_pins,
1037 .npins = ARRAY_SIZE(ssp0_pins),
1038 .modemuxs = ssp0_modemux,
1039 .nmodemuxs = ARRAY_SIZE(ssp0_modemux),
1040};
1041
1042/* pad multiplexing for ssp0_cs1 device */
1043static const unsigned ssp0_cs1_pins[] = { 24 };
1044static struct spear_muxreg ssp0_cs1_muxreg[] = {
1045 {
1046 .reg = PAD_SHARED_IP_EN_1,
1047 .mask = SSP0_CS1_MASK,
1048 .val = SSP0_CS1_MASK,
1049 }, {
1050 .reg = PAD_FUNCTION_EN_1,
1051 .mask = PWM0_AND_SSP0_CS1_REG0_MASK,
1052 .val = PWM0_AND_SSP0_CS1_REG0_MASK,
1053 },
1054};
1055
1056static struct spear_modemux ssp0_cs1_modemux[] = {
1057 {
1058 .muxregs = ssp0_cs1_muxreg,
1059 .nmuxregs = ARRAY_SIZE(ssp0_cs1_muxreg),
1060 },
1061};
1062
1063static struct spear_pingroup ssp0_cs1_pingroup = {
1064 .name = "ssp0_cs1_grp",
1065 .pins = ssp0_cs1_pins,
1066 .npins = ARRAY_SIZE(ssp0_cs1_pins),
1067 .modemuxs = ssp0_cs1_modemux,
1068 .nmodemuxs = ARRAY_SIZE(ssp0_cs1_modemux),
1069};
1070
1071/* pad multiplexing for ssp0_cs2 device */
1072static const unsigned ssp0_cs2_pins[] = { 85 };
1073static struct spear_muxreg ssp0_cs2_muxreg[] = {
1074 {
1075 .reg = PAD_SHARED_IP_EN_1,
1076 .mask = SSP0_CS2_MASK,
1077 .val = SSP0_CS2_MASK,
1078 }, {
1079 .reg = PAD_FUNCTION_EN_3,
1080 .mask = TS_AND_SSP0_CS2_REG2_MASK,
1081 .val = TS_AND_SSP0_CS2_REG2_MASK,
1082 },
1083};
1084
1085static struct spear_modemux ssp0_cs2_modemux[] = {
1086 {
1087 .muxregs = ssp0_cs2_muxreg,
1088 .nmuxregs = ARRAY_SIZE(ssp0_cs2_muxreg),
1089 },
1090};
1091
1092static struct spear_pingroup ssp0_cs2_pingroup = {
1093 .name = "ssp0_cs2_grp",
1094 .pins = ssp0_cs2_pins,
1095 .npins = ARRAY_SIZE(ssp0_cs2_pins),
1096 .modemuxs = ssp0_cs2_modemux,
1097 .nmodemuxs = ARRAY_SIZE(ssp0_cs2_modemux),
1098};
1099
1100/* pad multiplexing for ssp0_cs3 device */
1101static const unsigned ssp0_cs3_pins[] = { 132 };
1102static struct spear_muxreg ssp0_cs3_muxreg[] = {
1103 {
1104 .reg = PAD_FUNCTION_EN_5,
1105 .mask = SSP0_CS3_REG4_MASK,
1106 .val = SSP0_CS3_REG4_MASK,
1107 },
1108};
1109
1110static struct spear_modemux ssp0_cs3_modemux[] = {
1111 {
1112 .muxregs = ssp0_cs3_muxreg,
1113 .nmuxregs = ARRAY_SIZE(ssp0_cs3_muxreg),
1114 },
1115};
1116
1117static struct spear_pingroup ssp0_cs3_pingroup = {
1118 .name = "ssp0_cs3_grp",
1119 .pins = ssp0_cs3_pins,
1120 .npins = ARRAY_SIZE(ssp0_cs3_pins),
1121 .modemuxs = ssp0_cs3_modemux,
1122 .nmodemuxs = ARRAY_SIZE(ssp0_cs3_modemux),
1123};
1124
1125static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs1_grp",
1126 "ssp0_cs2_grp", "ssp0_cs3_grp" };
1127static struct spear_function ssp0_function = {
1128 .name = "ssp0",
1129 .groups = ssp0_grps,
1130 .ngroups = ARRAY_SIZE(ssp0_grps),
1131};
1132
1133/* pad multiplexing for uart0 device */
1134static const unsigned uart0_pins[] = { 86, 87 };
1135static struct spear_muxreg uart0_muxreg[] = {
1136 {
1137 .reg = PAD_FUNCTION_EN_3,
1138 .mask = UART0_REG2_MASK,
1139 .val = UART0_REG2_MASK,
1140 },
1141};
1142
1143static struct spear_modemux uart0_modemux[] = {
1144 {
1145 .muxregs = uart0_muxreg,
1146 .nmuxregs = ARRAY_SIZE(uart0_muxreg),
1147 },
1148};
1149
1150static struct spear_pingroup uart0_pingroup = {
1151 .name = "uart0_grp",
1152 .pins = uart0_pins,
1153 .npins = ARRAY_SIZE(uart0_pins),
1154 .modemuxs = uart0_modemux,
1155 .nmodemuxs = ARRAY_SIZE(uart0_modemux),
1156};
1157
1158/* pad multiplexing for uart0_enh device */
1159static const unsigned uart0_enh_pins[] = { 11, 12, 13, 14, 15, 16 };
1160static struct spear_muxreg uart0_enh_muxreg[] = {
1161 {
1162 .reg = PAD_SHARED_IP_EN_1,
1163 .mask = GPT_MASK,
1164 .val = 0,
1165 }, {
1166 .reg = PAD_FUNCTION_EN_1,
1167 .mask = UART0_ENH_AND_GPT_REG0_MASK,
1168 .val = UART0_ENH_AND_GPT_REG0_MASK,
1169 },
1170};
1171
1172static struct spear_modemux uart0_enh_modemux[] = {
1173 {
1174 .muxregs = uart0_enh_muxreg,
1175 .nmuxregs = ARRAY_SIZE(uart0_enh_muxreg),
1176 },
1177};
1178
1179static struct spear_pingroup uart0_enh_pingroup = {
1180 .name = "uart0_enh_grp",
1181 .pins = uart0_enh_pins,
1182 .npins = ARRAY_SIZE(uart0_enh_pins),
1183 .modemuxs = uart0_enh_modemux,
1184 .nmodemuxs = ARRAY_SIZE(uart0_enh_modemux),
1185};
1186
1187static const char *const uart0_grps[] = { "uart0_grp", "uart0_enh_grp" };
1188static struct spear_function uart0_function = {
1189 .name = "uart0",
1190 .groups = uart0_grps,
1191 .ngroups = ARRAY_SIZE(uart0_grps),
1192};
1193
1194/* pad multiplexing for uart1 device */
1195static const unsigned uart1_pins[] = { 88, 89 };
1196static struct spear_muxreg uart1_muxreg[] = {
1197 {
1198 .reg = PAD_FUNCTION_EN_3,
1199 .mask = UART1_REG2_MASK,
1200 .val = UART1_REG2_MASK,
1201 },
1202};
1203
1204static struct spear_modemux uart1_modemux[] = {
1205 {
1206 .muxregs = uart1_muxreg,
1207 .nmuxregs = ARRAY_SIZE(uart1_muxreg),
1208 },
1209};
1210
1211static struct spear_pingroup uart1_pingroup = {
1212 .name = "uart1_grp",
1213 .pins = uart1_pins,
1214 .npins = ARRAY_SIZE(uart1_pins),
1215 .modemuxs = uart1_modemux,
1216 .nmodemuxs = ARRAY_SIZE(uart1_modemux),
1217};
1218
1219static const char *const uart1_grps[] = { "uart1_grp" };
1220static struct spear_function uart1_function = {
1221 .name = "uart1",
1222 .groups = uart1_grps,
1223 .ngroups = ARRAY_SIZE(uart1_grps),
1224};
1225
1226/* pad multiplexing for i2s_in device */
1227static const unsigned i2s_in_pins[] = { 90, 91, 92, 93, 94, 99 };
1228static struct spear_muxreg i2s_in_muxreg[] = {
1229 {
1230 .reg = PAD_FUNCTION_EN_3,
1231 .mask = I2S_IN_REG2_MASK,
1232 .val = I2S_IN_REG2_MASK,
1233 }, {
1234 .reg = PAD_FUNCTION_EN_4,
1235 .mask = I2S_IN_REG3_MASK,
1236 .val = I2S_IN_REG3_MASK,
1237 },
1238};
1239
1240static struct spear_modemux i2s_in_modemux[] = {
1241 {
1242 .muxregs = i2s_in_muxreg,
1243 .nmuxregs = ARRAY_SIZE(i2s_in_muxreg),
1244 },
1245};
1246
1247static struct spear_pingroup i2s_in_pingroup = {
1248 .name = "i2s_in_grp",
1249 .pins = i2s_in_pins,
1250 .npins = ARRAY_SIZE(i2s_in_pins),
1251 .modemuxs = i2s_in_modemux,
1252 .nmodemuxs = ARRAY_SIZE(i2s_in_modemux),
1253};
1254
1255/* pad multiplexing for i2s_out device */
1256static const unsigned i2s_out_pins[] = { 95, 96, 97, 98, 100, 101, 102, 103 };
1257static struct spear_muxreg i2s_out_muxreg[] = {
1258 {
1259 .reg = PAD_FUNCTION_EN_4,
1260 .mask = I2S_OUT_REG3_MASK,
1261 .val = I2S_OUT_REG3_MASK,
1262 },
1263};
1264
1265static struct spear_modemux i2s_out_modemux[] = {
1266 {
1267 .muxregs = i2s_out_muxreg,
1268 .nmuxregs = ARRAY_SIZE(i2s_out_muxreg),
1269 },
1270};
1271
1272static struct spear_pingroup i2s_out_pingroup = {
1273 .name = "i2s_out_grp",
1274 .pins = i2s_out_pins,
1275 .npins = ARRAY_SIZE(i2s_out_pins),
1276 .modemuxs = i2s_out_modemux,
1277 .nmodemuxs = ARRAY_SIZE(i2s_out_modemux),
1278};
1279
1280static const char *const i2s_grps[] = { "i2s_in_grp", "i2s_out_grp" };
1281static struct spear_function i2s_function = {
1282 .name = "i2s",
1283 .groups = i2s_grps,
1284 .ngroups = ARRAY_SIZE(i2s_grps),
1285};
1286
1287/* pad multiplexing for gmac device */
1288static const unsigned gmac_pins[] = { 104, 105, 106, 107, 108, 109, 110, 111,
1289 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125,
1290 126, 127, 128, 129, 130, 131 };
1291#define GMAC_MUXREG \
1292 { \
1293 .reg = PAD_FUNCTION_EN_4, \
1294 .mask = GMAC_REG3_MASK, \
1295 .val = GMAC_REG3_MASK, \
1296 }, { \
1297 .reg = PAD_FUNCTION_EN_5, \
1298 .mask = GMAC_REG4_MASK, \
1299 .val = GMAC_REG4_MASK, \
1300 }
1301
1302/* pad multiplexing for gmii device */
1303static struct spear_muxreg gmii_muxreg[] = {
1304 GMAC_MUXREG,
1305 {
1306 .reg = GMAC_CLK_CFG,
1307 .mask = GMAC_PHY_IF_SEL_MASK,
1308 .val = GMAC_PHY_IF_GMII_VAL,
1309 },
1310};
1311
1312static struct spear_modemux gmii_modemux[] = {
1313 {
1314 .muxregs = gmii_muxreg,
1315 .nmuxregs = ARRAY_SIZE(gmii_muxreg),
1316 },
1317};
1318
1319static struct spear_pingroup gmii_pingroup = {
1320 .name = "gmii_grp",
1321 .pins = gmac_pins,
1322 .npins = ARRAY_SIZE(gmac_pins),
1323 .modemuxs = gmii_modemux,
1324 .nmodemuxs = ARRAY_SIZE(gmii_modemux),
1325};
1326
1327/* pad multiplexing for rgmii device */
1328static struct spear_muxreg rgmii_muxreg[] = {
1329 GMAC_MUXREG,
1330 {
1331 .reg = GMAC_CLK_CFG,
1332 .mask = GMAC_PHY_IF_SEL_MASK,
1333 .val = GMAC_PHY_IF_RGMII_VAL,
1334 },
1335};
1336
1337static struct spear_modemux rgmii_modemux[] = {
1338 {
1339 .muxregs = rgmii_muxreg,
1340 .nmuxregs = ARRAY_SIZE(rgmii_muxreg),
1341 },
1342};
1343
1344static struct spear_pingroup rgmii_pingroup = {
1345 .name = "rgmii_grp",
1346 .pins = gmac_pins,
1347 .npins = ARRAY_SIZE(gmac_pins),
1348 .modemuxs = rgmii_modemux,
1349 .nmodemuxs = ARRAY_SIZE(rgmii_modemux),
1350};
1351
1352/* pad multiplexing for rmii device */
1353static struct spear_muxreg rmii_muxreg[] = {
1354 GMAC_MUXREG,
1355 {
1356 .reg = GMAC_CLK_CFG,
1357 .mask = GMAC_PHY_IF_SEL_MASK,
1358 .val = GMAC_PHY_IF_RMII_VAL,
1359 },
1360};
1361
1362static struct spear_modemux rmii_modemux[] = {
1363 {
1364 .muxregs = rmii_muxreg,
1365 .nmuxregs = ARRAY_SIZE(rmii_muxreg),
1366 },
1367};
1368
1369static struct spear_pingroup rmii_pingroup = {
1370 .name = "rmii_grp",
1371 .pins = gmac_pins,
1372 .npins = ARRAY_SIZE(gmac_pins),
1373 .modemuxs = rmii_modemux,
1374 .nmodemuxs = ARRAY_SIZE(rmii_modemux),
1375};
1376
1377/* pad multiplexing for sgmii device */
1378static struct spear_muxreg sgmii_muxreg[] = {
1379 GMAC_MUXREG,
1380 {
1381 .reg = GMAC_CLK_CFG,
1382 .mask = GMAC_PHY_IF_SEL_MASK,
1383 .val = GMAC_PHY_IF_SGMII_VAL,
1384 },
1385};
1386
1387static struct spear_modemux sgmii_modemux[] = {
1388 {
1389 .muxregs = sgmii_muxreg,
1390 .nmuxregs = ARRAY_SIZE(sgmii_muxreg),
1391 },
1392};
1393
1394static struct spear_pingroup sgmii_pingroup = {
1395 .name = "sgmii_grp",
1396 .pins = gmac_pins,
1397 .npins = ARRAY_SIZE(gmac_pins),
1398 .modemuxs = sgmii_modemux,
1399 .nmodemuxs = ARRAY_SIZE(sgmii_modemux),
1400};
1401
1402static const char *const gmac_grps[] = { "gmii_grp", "rgmii_grp", "rmii_grp",
1403 "sgmii_grp" };
1404static struct spear_function gmac_function = {
1405 .name = "gmac",
1406 .groups = gmac_grps,
1407 .ngroups = ARRAY_SIZE(gmac_grps),
1408};
1409
1410/* pad multiplexing for i2c0 device */
1411static const unsigned i2c0_pins[] = { 133, 134 };
1412static struct spear_muxreg i2c0_muxreg[] = {
1413 {
1414 .reg = PAD_FUNCTION_EN_5,
1415 .mask = I2C0_REG4_MASK,
1416 .val = I2C0_REG4_MASK,
1417 },
1418};
1419
1420static struct spear_modemux i2c0_modemux[] = {
1421 {
1422 .muxregs = i2c0_muxreg,
1423 .nmuxregs = ARRAY_SIZE(i2c0_muxreg),
1424 },
1425};
1426
1427static struct spear_pingroup i2c0_pingroup = {
1428 .name = "i2c0_grp",
1429 .pins = i2c0_pins,
1430 .npins = ARRAY_SIZE(i2c0_pins),
1431 .modemuxs = i2c0_modemux,
1432 .nmodemuxs = ARRAY_SIZE(i2c0_modemux),
1433};
1434
1435static const char *const i2c0_grps[] = { "i2c0_grp" };
1436static struct spear_function i2c0_function = {
1437 .name = "i2c0",
1438 .groups = i2c0_grps,
1439 .ngroups = ARRAY_SIZE(i2c0_grps),
1440};
1441
1442/* pad multiplexing for i2c1 device */
1443static const unsigned i2c1_pins[] = { 18, 23 };
1444static struct spear_muxreg i2c1_muxreg[] = {
1445 {
1446 .reg = PAD_FUNCTION_EN_1,
1447 .mask = I2C1_REG0_MASK,
1448 .val = I2C1_REG0_MASK,
1449 },
1450};
1451
1452static struct spear_modemux i2c1_modemux[] = {
1453 {
1454 .muxregs = i2c1_muxreg,
1455 .nmuxregs = ARRAY_SIZE(i2c1_muxreg),
1456 },
1457};
1458
1459static struct spear_pingroup i2c1_pingroup = {
1460 .name = "i2c1_grp",
1461 .pins = i2c1_pins,
1462 .npins = ARRAY_SIZE(i2c1_pins),
1463 .modemuxs = i2c1_modemux,
1464 .nmodemuxs = ARRAY_SIZE(i2c1_modemux),
1465};
1466
1467static const char *const i2c1_grps[] = { "i2c1_grp" };
1468static struct spear_function i2c1_function = {
1469 .name = "i2c1",
1470 .groups = i2c1_grps,
1471 .ngroups = ARRAY_SIZE(i2c1_grps),
1472};
1473
1474/* pad multiplexing for cec0 device */
1475static const unsigned cec0_pins[] = { 135 };
1476static struct spear_muxreg cec0_muxreg[] = {
1477 {
1478 .reg = PAD_FUNCTION_EN_5,
1479 .mask = CEC0_REG4_MASK,
1480 .val = CEC0_REG4_MASK,
1481 },
1482};
1483
1484static struct spear_modemux cec0_modemux[] = {
1485 {
1486 .muxregs = cec0_muxreg,
1487 .nmuxregs = ARRAY_SIZE(cec0_muxreg),
1488 },
1489};
1490
1491static struct spear_pingroup cec0_pingroup = {
1492 .name = "cec0_grp",
1493 .pins = cec0_pins,
1494 .npins = ARRAY_SIZE(cec0_pins),
1495 .modemuxs = cec0_modemux,
1496 .nmodemuxs = ARRAY_SIZE(cec0_modemux),
1497};
1498
1499static const char *const cec0_grps[] = { "cec0_grp" };
1500static struct spear_function cec0_function = {
1501 .name = "cec0",
1502 .groups = cec0_grps,
1503 .ngroups = ARRAY_SIZE(cec0_grps),
1504};
1505
1506/* pad multiplexing for cec1 device */
1507static const unsigned cec1_pins[] = { 136 };
1508static struct spear_muxreg cec1_muxreg[] = {
1509 {
1510 .reg = PAD_FUNCTION_EN_5,
1511 .mask = CEC1_REG4_MASK,
1512 .val = CEC1_REG4_MASK,
1513 },
1514};
1515
1516static struct spear_modemux cec1_modemux[] = {
1517 {
1518 .muxregs = cec1_muxreg,
1519 .nmuxregs = ARRAY_SIZE(cec1_muxreg),
1520 },
1521};
1522
1523static struct spear_pingroup cec1_pingroup = {
1524 .name = "cec1_grp",
1525 .pins = cec1_pins,
1526 .npins = ARRAY_SIZE(cec1_pins),
1527 .modemuxs = cec1_modemux,
1528 .nmodemuxs = ARRAY_SIZE(cec1_modemux),
1529};
1530
1531static const char *const cec1_grps[] = { "cec1_grp" };
1532static struct spear_function cec1_function = {
1533 .name = "cec1",
1534 .groups = cec1_grps,
1535 .ngroups = ARRAY_SIZE(cec1_grps),
1536};
1537
1538/* pad multiplexing for mcif devices */
1539static const unsigned mcif_pins[] = { 193, 194, 195, 196, 197, 198, 199, 200,
1540 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214,
1541 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
1542 229, 230, 231, 232, 237 };
1543#define MCIF_MUXREG \
1544 { \
1545 .reg = PAD_SHARED_IP_EN_1, \
1546 .mask = MCIF_MASK, \
1547 .val = MCIF_MASK, \
1548 }, { \
1549 .reg = PAD_FUNCTION_EN_7, \
1550 .mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
1551 .val = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
1552 }, { \
1553 .reg = PAD_FUNCTION_EN_8, \
1554 .mask = MCIF_REG7_MASK, \
1555 .val = MCIF_REG7_MASK, \
1556 }
1557
1558/* Pad multiplexing for sdhci device */
1559static struct spear_muxreg sdhci_muxreg[] = {
1560 MCIF_MUXREG,
1561 {
1562 .reg = PERIP_CFG,
1563 .mask = MCIF_SEL_MASK,
1564 .val = MCIF_SEL_SD,
1565 },
1566};
1567
1568static struct spear_modemux sdhci_modemux[] = {
1569 {
1570 .muxregs = sdhci_muxreg,
1571 .nmuxregs = ARRAY_SIZE(sdhci_muxreg),
1572 },
1573};
1574
1575static struct spear_pingroup sdhci_pingroup = {
1576 .name = "sdhci_grp",
1577 .pins = mcif_pins,
1578 .npins = ARRAY_SIZE(mcif_pins),
1579 .modemuxs = sdhci_modemux,
1580 .nmodemuxs = ARRAY_SIZE(sdhci_modemux),
1581};
1582
1583static const char *const sdhci_grps[] = { "sdhci_grp" };
1584static struct spear_function sdhci_function = {
1585 .name = "sdhci",
1586 .groups = sdhci_grps,
1587 .ngroups = ARRAY_SIZE(sdhci_grps),
1588};
1589
1590/* Pad multiplexing for cf device */
1591static struct spear_muxreg cf_muxreg[] = {
1592 MCIF_MUXREG,
1593 {
1594 .reg = PERIP_CFG,
1595 .mask = MCIF_SEL_MASK,
1596 .val = MCIF_SEL_CF,
1597 },
1598};
1599
1600static struct spear_modemux cf_modemux[] = {
1601 {
1602 .muxregs = cf_muxreg,
1603 .nmuxregs = ARRAY_SIZE(cf_muxreg),
1604 },
1605};
1606
1607static struct spear_pingroup cf_pingroup = {
1608 .name = "cf_grp",
1609 .pins = mcif_pins,
1610 .npins = ARRAY_SIZE(mcif_pins),
1611 .modemuxs = cf_modemux,
1612 .nmodemuxs = ARRAY_SIZE(cf_modemux),
1613};
1614
1615static const char *const cf_grps[] = { "cf_grp" };
1616static struct spear_function cf_function = {
1617 .name = "cf",
1618 .groups = cf_grps,
1619 .ngroups = ARRAY_SIZE(cf_grps),
1620};
1621
1622/* Pad multiplexing for xd device */
1623static struct spear_muxreg xd_muxreg[] = {
1624 MCIF_MUXREG,
1625 {
1626 .reg = PERIP_CFG,
1627 .mask = MCIF_SEL_MASK,
1628 .val = MCIF_SEL_XD,
1629 },
1630};
1631
1632static struct spear_modemux xd_modemux[] = {
1633 {
1634 .muxregs = xd_muxreg,
1635 .nmuxregs = ARRAY_SIZE(xd_muxreg),
1636 },
1637};
1638
1639static struct spear_pingroup xd_pingroup = {
1640 .name = "xd_grp",
1641 .pins = mcif_pins,
1642 .npins = ARRAY_SIZE(mcif_pins),
1643 .modemuxs = xd_modemux,
1644 .nmodemuxs = ARRAY_SIZE(xd_modemux),
1645};
1646
1647static const char *const xd_grps[] = { "xd_grp" };
1648static struct spear_function xd_function = {
1649 .name = "xd",
1650 .groups = xd_grps,
1651 .ngroups = ARRAY_SIZE(xd_grps),
1652};
1653
1654/* pad multiplexing for clcd device */
1655static const unsigned clcd_pins[] = { 138, 139, 140, 141, 142, 143, 144, 145,
1656 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159,
1657 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,
1658 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187,
1659 188, 189, 190, 191 };
1660static struct spear_muxreg clcd_muxreg[] = {
1661 {
1662 .reg = PAD_SHARED_IP_EN_1,
1663 .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
1664 .val = 0,
1665 }, {
1666 .reg = PAD_FUNCTION_EN_5,
1667 .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
1668 .val = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
1669 }, {
1670 .reg = PAD_FUNCTION_EN_6,
1671 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1672 .val = CLCD_AND_ARM_TRACE_REG5_MASK,
1673 }, {
1674 .reg = PAD_FUNCTION_EN_7,
1675 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1676 .val = CLCD_AND_ARM_TRACE_REG6_MASK,
1677 },
1678};
1679
1680static struct spear_modemux clcd_modemux[] = {
1681 {
1682 .muxregs = clcd_muxreg,
1683 .nmuxregs = ARRAY_SIZE(clcd_muxreg),
1684 },
1685};
1686
1687static struct spear_pingroup clcd_pingroup = {
1688 .name = "clcd_grp",
1689 .pins = clcd_pins,
1690 .npins = ARRAY_SIZE(clcd_pins),
1691 .modemuxs = clcd_modemux,
1692 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
1693};
1694
1695static const char *const clcd_grps[] = { "clcd_grp" };
1696static struct spear_function clcd_function = {
1697 .name = "clcd",
1698 .groups = clcd_grps,
1699 .ngroups = ARRAY_SIZE(clcd_grps),
1700};
1701
1702/* pad multiplexing for arm_trace device */
1703static const unsigned arm_trace_pins[] = { 158, 159, 160, 161, 162, 163, 164,
1704 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178,
1705 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192,
1706 193, 194, 195, 196, 197, 198, 199, 200 };
1707static struct spear_muxreg arm_trace_muxreg[] = {
1708 {
1709 .reg = PAD_SHARED_IP_EN_1,
1710 .mask = ARM_TRACE_MASK,
1711 .val = ARM_TRACE_MASK,
1712 }, {
1713 .reg = PAD_FUNCTION_EN_5,
1714 .mask = CLCD_AND_ARM_TRACE_REG4_MASK,
1715 .val = CLCD_AND_ARM_TRACE_REG4_MASK,
1716 }, {
1717 .reg = PAD_FUNCTION_EN_6,
1718 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1719 .val = CLCD_AND_ARM_TRACE_REG5_MASK,
1720 }, {
1721 .reg = PAD_FUNCTION_EN_7,
1722 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1723 .val = CLCD_AND_ARM_TRACE_REG6_MASK,
1724 },
1725};
1726
1727static struct spear_modemux arm_trace_modemux[] = {
1728 {
1729 .muxregs = arm_trace_muxreg,
1730 .nmuxregs = ARRAY_SIZE(arm_trace_muxreg),
1731 },
1732};
1733
1734static struct spear_pingroup arm_trace_pingroup = {
1735 .name = "arm_trace_grp",
1736 .pins = arm_trace_pins,
1737 .npins = ARRAY_SIZE(arm_trace_pins),
1738 .modemuxs = arm_trace_modemux,
1739 .nmodemuxs = ARRAY_SIZE(arm_trace_modemux),
1740};
1741
1742static const char *const arm_trace_grps[] = { "arm_trace_grp" };
1743static struct spear_function arm_trace_function = {
1744 .name = "arm_trace",
1745 .groups = arm_trace_grps,
1746 .ngroups = ARRAY_SIZE(arm_trace_grps),
1747};
1748
1749/* pad multiplexing for miphy_dbg device */
1750static const unsigned miphy_dbg_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103,
1751 132, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
1752 148, 149, 150, 151, 152, 153, 154, 155, 156, 157 };
1753static struct spear_muxreg miphy_dbg_muxreg[] = {
1754 {
1755 .reg = PAD_SHARED_IP_EN_1,
1756 .mask = MIPHY_DBG_MASK,
1757 .val = MIPHY_DBG_MASK,
1758 }, {
1759 .reg = PAD_FUNCTION_EN_5,
1760 .mask = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
1761 .val = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
1762 },
1763};
1764
1765static struct spear_modemux miphy_dbg_modemux[] = {
1766 {
1767 .muxregs = miphy_dbg_muxreg,
1768 .nmuxregs = ARRAY_SIZE(miphy_dbg_muxreg),
1769 },
1770};
1771
1772static struct spear_pingroup miphy_dbg_pingroup = {
1773 .name = "miphy_dbg_grp",
1774 .pins = miphy_dbg_pins,
1775 .npins = ARRAY_SIZE(miphy_dbg_pins),
1776 .modemuxs = miphy_dbg_modemux,
1777 .nmodemuxs = ARRAY_SIZE(miphy_dbg_modemux),
1778};
1779
1780static const char *const miphy_dbg_grps[] = { "miphy_dbg_grp" };
1781static struct spear_function miphy_dbg_function = {
1782 .name = "miphy_dbg",
1783 .groups = miphy_dbg_grps,
1784 .ngroups = ARRAY_SIZE(miphy_dbg_grps),
1785};
1786
1787/* pad multiplexing for pcie device */
1788static const unsigned pcie_pins[] = { 250 };
1789static struct spear_muxreg pcie_muxreg[] = {
1790 {
1791 .reg = PCIE_SATA_CFG,
1792 .mask = SATA_PCIE_CFG_MASK,
1793 .val = PCIE_CFG_VAL,
1794 },
1795};
1796
1797static struct spear_modemux pcie_modemux[] = {
1798 {
1799 .muxregs = pcie_muxreg,
1800 .nmuxregs = ARRAY_SIZE(pcie_muxreg),
1801 },
1802};
1803
1804static struct spear_pingroup pcie_pingroup = {
1805 .name = "pcie_grp",
1806 .pins = pcie_pins,
1807 .npins = ARRAY_SIZE(pcie_pins),
1808 .modemuxs = pcie_modemux,
1809 .nmodemuxs = ARRAY_SIZE(pcie_modemux),
1810};
1811
1812static const char *const pcie_grps[] = { "pcie_grp" };
1813static struct spear_function pcie_function = {
1814 .name = "pcie",
1815 .groups = pcie_grps,
1816 .ngroups = ARRAY_SIZE(pcie_grps),
1817};
1818
1819/* pad multiplexing for sata device */
1820static const unsigned sata_pins[] = { 250 };
1821static struct spear_muxreg sata_muxreg[] = {
1822 {
1823 .reg = PCIE_SATA_CFG,
1824 .mask = SATA_PCIE_CFG_MASK,
1825 .val = SATA_CFG_VAL,
1826 },
1827};
1828
1829static struct spear_modemux sata_modemux[] = {
1830 {
1831 .muxregs = sata_muxreg,
1832 .nmuxregs = ARRAY_SIZE(sata_muxreg),
1833 },
1834};
1835
1836static struct spear_pingroup sata_pingroup = {
1837 .name = "sata_grp",
1838 .pins = sata_pins,
1839 .npins = ARRAY_SIZE(sata_pins),
1840 .modemuxs = sata_modemux,
1841 .nmodemuxs = ARRAY_SIZE(sata_modemux),
1842};
1843
1844static const char *const sata_grps[] = { "sata_grp" };
1845static struct spear_function sata_function = {
1846 .name = "sata",
1847 .groups = sata_grps,
1848 .ngroups = ARRAY_SIZE(sata_grps),
1849};
1850
1851/* pingroups */
1852static struct spear_pingroup *spear1340_pingroups[] = {
1853 &pads_as_gpio_pingroup,
1854 &fsmc_8bit_pingroup,
1855 &fsmc_16bit_pingroup,
1856 &fsmc_pnor_pingroup,
1857 &keyboard_row_col_pingroup,
1858 &keyboard_col5_pingroup,
1859 &spdif_in_pingroup,
1860 &spdif_out_pingroup,
1861 &gpt_0_1_pingroup,
1862 &pwm0_pingroup,
1863 &pwm1_pingroup,
1864 &pwm2_pingroup,
1865 &pwm3_pingroup,
1866 &vip_mux_pingroup,
1867 &vip_mux_cam0_pingroup,
1868 &vip_mux_cam1_pingroup,
1869 &vip_mux_cam2_pingroup,
1870 &vip_mux_cam3_pingroup,
1871 &cam0_pingroup,
1872 &cam1_pingroup,
1873 &cam2_pingroup,
1874 &cam3_pingroup,
1875 &smi_pingroup,
1876 &ssp0_pingroup,
1877 &ssp0_cs1_pingroup,
1878 &ssp0_cs2_pingroup,
1879 &ssp0_cs3_pingroup,
1880 &uart0_pingroup,
1881 &uart0_enh_pingroup,
1882 &uart1_pingroup,
1883 &i2s_in_pingroup,
1884 &i2s_out_pingroup,
1885 &gmii_pingroup,
1886 &rgmii_pingroup,
1887 &rmii_pingroup,
1888 &sgmii_pingroup,
1889 &i2c0_pingroup,
1890 &i2c1_pingroup,
1891 &cec0_pingroup,
1892 &cec1_pingroup,
1893 &sdhci_pingroup,
1894 &cf_pingroup,
1895 &xd_pingroup,
1896 &clcd_pingroup,
1897 &arm_trace_pingroup,
1898 &miphy_dbg_pingroup,
1899 &pcie_pingroup,
1900 &sata_pingroup,
1901};
1902
1903/* functions */
1904static struct spear_function *spear1340_functions[] = {
1905 &pads_as_gpio_function,
1906 &fsmc_function,
1907 &keyboard_function,
1908 &spdif_in_function,
1909 &spdif_out_function,
1910 &gpt_0_1_function,
1911 &pwm_function,
1912 &vip_function,
1913 &cam0_function,
1914 &cam1_function,
1915 &cam2_function,
1916 &cam3_function,
1917 &smi_function,
1918 &ssp0_function,
1919 &uart0_function,
1920 &uart1_function,
1921 &i2s_function,
1922 &gmac_function,
1923 &i2c0_function,
1924 &i2c1_function,
1925 &cec0_function,
1926 &cec1_function,
1927 &sdhci_function,
1928 &cf_function,
1929 &xd_function,
1930 &clcd_function,
1931 &arm_trace_function,
1932 &miphy_dbg_function,
1933 &pcie_function,
1934 &sata_function,
1935};
1936
1937static struct spear_pinctrl_machdata spear1340_machdata = {
1938 .pins = spear1340_pins,
1939 .npins = ARRAY_SIZE(spear1340_pins),
1940 .groups = spear1340_pingroups,
1941 .ngroups = ARRAY_SIZE(spear1340_pingroups),
1942 .functions = spear1340_functions,
1943 .nfunctions = ARRAY_SIZE(spear1340_functions),
1944 .modes_supported = false,
1945};
1946
1947static struct of_device_id spear1340_pinctrl_of_match[] __devinitdata = {
1948 {
1949 .compatible = "st,spear1340-pinmux",
1950 },
1951 {},
1952};
1953
1954static int __devinit spear1340_pinctrl_probe(struct platform_device *pdev)
1955{
1956 return spear_pinctrl_probe(pdev, &spear1340_machdata);
1957}
1958
1959static int __devexit spear1340_pinctrl_remove(struct platform_device *pdev)
1960{
1961 return spear_pinctrl_remove(pdev);
1962}
1963
1964static struct platform_driver spear1340_pinctrl_driver = {
1965 .driver = {
1966 .name = DRIVER_NAME,
1967 .owner = THIS_MODULE,
1968 .of_match_table = spear1340_pinctrl_of_match,
1969 },
1970 .probe = spear1340_pinctrl_probe,
1971 .remove = __devexit_p(spear1340_pinctrl_remove),
1972};
1973
1974static int __init spear1340_pinctrl_init(void)
1975{
1976 return platform_driver_register(&spear1340_pinctrl_driver);
1977}
1978arch_initcall(spear1340_pinctrl_init);
1979
1980static void __exit spear1340_pinctrl_exit(void)
1981{
1982 platform_driver_unregister(&spear1340_pinctrl_driver);
1983}
1984module_exit(spear1340_pinctrl_exit);
1985
1986MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
1987MODULE_DESCRIPTION("ST Microelectronics SPEAr1340 pinctrl driver");
1988MODULE_LICENSE("GPL v2");
1989MODULE_DEVICE_TABLE(of, spear1340_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.c b/drivers/pinctrl/spear/pinctrl-spear3xx.c
index 832049a8b1c9..91c883bc46a6 100644
--- a/drivers/pinctrl/spear/pinctrl-spear3xx.c
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.c
@@ -15,108 +15,7 @@
15 15
16/* pins */ 16/* pins */
17static const struct pinctrl_pin_desc spear3xx_pins[] = { 17static const struct pinctrl_pin_desc spear3xx_pins[] = {
18 PINCTRL_PIN(0, "PLGPIO0"), 18 SPEAR_PIN_0_TO_101,
19 PINCTRL_PIN(1, "PLGPIO1"),
20 PINCTRL_PIN(2, "PLGPIO2"),
21 PINCTRL_PIN(3, "PLGPIO3"),
22 PINCTRL_PIN(4, "PLGPIO4"),
23 PINCTRL_PIN(5, "PLGPIO5"),
24 PINCTRL_PIN(6, "PLGPIO6"),
25 PINCTRL_PIN(7, "PLGPIO7"),
26 PINCTRL_PIN(8, "PLGPIO8"),
27 PINCTRL_PIN(9, "PLGPIO9"),
28 PINCTRL_PIN(10, "PLGPIO10"),
29 PINCTRL_PIN(11, "PLGPIO11"),
30 PINCTRL_PIN(12, "PLGPIO12"),
31 PINCTRL_PIN(13, "PLGPIO13"),
32 PINCTRL_PIN(14, "PLGPIO14"),
33 PINCTRL_PIN(15, "PLGPIO15"),
34 PINCTRL_PIN(16, "PLGPIO16"),
35 PINCTRL_PIN(17, "PLGPIO17"),
36 PINCTRL_PIN(18, "PLGPIO18"),
37 PINCTRL_PIN(19, "PLGPIO19"),
38 PINCTRL_PIN(20, "PLGPIO20"),
39 PINCTRL_PIN(21, "PLGPIO21"),
40 PINCTRL_PIN(22, "PLGPIO22"),
41 PINCTRL_PIN(23, "PLGPIO23"),
42 PINCTRL_PIN(24, "PLGPIO24"),
43 PINCTRL_PIN(25, "PLGPIO25"),
44 PINCTRL_PIN(26, "PLGPIO26"),
45 PINCTRL_PIN(27, "PLGPIO27"),
46 PINCTRL_PIN(28, "PLGPIO28"),
47 PINCTRL_PIN(29, "PLGPIO29"),
48 PINCTRL_PIN(30, "PLGPIO30"),
49 PINCTRL_PIN(31, "PLGPIO31"),
50 PINCTRL_PIN(32, "PLGPIO32"),
51 PINCTRL_PIN(33, "PLGPIO33"),
52 PINCTRL_PIN(34, "PLGPIO34"),
53 PINCTRL_PIN(35, "PLGPIO35"),
54 PINCTRL_PIN(36, "PLGPIO36"),
55 PINCTRL_PIN(37, "PLGPIO37"),
56 PINCTRL_PIN(38, "PLGPIO38"),
57 PINCTRL_PIN(39, "PLGPIO39"),
58 PINCTRL_PIN(40, "PLGPIO40"),
59 PINCTRL_PIN(41, "PLGPIO41"),
60 PINCTRL_PIN(42, "PLGPIO42"),
61 PINCTRL_PIN(43, "PLGPIO43"),
62 PINCTRL_PIN(44, "PLGPIO44"),
63 PINCTRL_PIN(45, "PLGPIO45"),
64 PINCTRL_PIN(46, "PLGPIO46"),
65 PINCTRL_PIN(47, "PLGPIO47"),
66 PINCTRL_PIN(48, "PLGPIO48"),
67 PINCTRL_PIN(49, "PLGPIO49"),
68 PINCTRL_PIN(50, "PLGPIO50"),
69 PINCTRL_PIN(51, "PLGPIO51"),
70 PINCTRL_PIN(52, "PLGPIO52"),
71 PINCTRL_PIN(53, "PLGPIO53"),
72 PINCTRL_PIN(54, "PLGPIO54"),
73 PINCTRL_PIN(55, "PLGPIO55"),
74 PINCTRL_PIN(56, "PLGPIO56"),
75 PINCTRL_PIN(57, "PLGPIO57"),
76 PINCTRL_PIN(58, "PLGPIO58"),
77 PINCTRL_PIN(59, "PLGPIO59"),
78 PINCTRL_PIN(60, "PLGPIO60"),
79 PINCTRL_PIN(61, "PLGPIO61"),
80 PINCTRL_PIN(62, "PLGPIO62"),
81 PINCTRL_PIN(63, "PLGPIO63"),
82 PINCTRL_PIN(64, "PLGPIO64"),
83 PINCTRL_PIN(65, "PLGPIO65"),
84 PINCTRL_PIN(66, "PLGPIO66"),
85 PINCTRL_PIN(67, "PLGPIO67"),
86 PINCTRL_PIN(68, "PLGPIO68"),
87 PINCTRL_PIN(69, "PLGPIO69"),
88 PINCTRL_PIN(70, "PLGPIO70"),
89 PINCTRL_PIN(71, "PLGPIO71"),
90 PINCTRL_PIN(72, "PLGPIO72"),
91 PINCTRL_PIN(73, "PLGPIO73"),
92 PINCTRL_PIN(74, "PLGPIO74"),
93 PINCTRL_PIN(75, "PLGPIO75"),
94 PINCTRL_PIN(76, "PLGPIO76"),
95 PINCTRL_PIN(77, "PLGPIO77"),
96 PINCTRL_PIN(78, "PLGPIO78"),
97 PINCTRL_PIN(79, "PLGPIO79"),
98 PINCTRL_PIN(80, "PLGPIO80"),
99 PINCTRL_PIN(81, "PLGPIO81"),
100 PINCTRL_PIN(82, "PLGPIO82"),
101 PINCTRL_PIN(83, "PLGPIO83"),
102 PINCTRL_PIN(84, "PLGPIO84"),
103 PINCTRL_PIN(85, "PLGPIO85"),
104 PINCTRL_PIN(86, "PLGPIO86"),
105 PINCTRL_PIN(87, "PLGPIO87"),
106 PINCTRL_PIN(88, "PLGPIO88"),
107 PINCTRL_PIN(89, "PLGPIO89"),
108 PINCTRL_PIN(90, "PLGPIO90"),
109 PINCTRL_PIN(91, "PLGPIO91"),
110 PINCTRL_PIN(92, "PLGPIO92"),
111 PINCTRL_PIN(93, "PLGPIO93"),
112 PINCTRL_PIN(94, "PLGPIO94"),
113 PINCTRL_PIN(95, "PLGPIO95"),
114 PINCTRL_PIN(96, "PLGPIO96"),
115 PINCTRL_PIN(97, "PLGPIO97"),
116 PINCTRL_PIN(98, "PLGPIO98"),
117 PINCTRL_PIN(99, "PLGPIO99"),
118 PINCTRL_PIN(100, "PLGPIO100"),
119 PINCTRL_PIN(101, "PLGPIO101"),
120}; 19};
121 20
122/* firda_pins */ 21/* firda_pins */
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 00c024039c97..cd2fe350e724 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -311,7 +311,7 @@ config SPI_S3C24XX_FIQ
311 311
312config SPI_S3C64XX 312config SPI_S3C64XX
313 tristate "Samsung S3C64XX series type SPI" 313 tristate "Samsung S3C64XX series type SPI"
314 depends on (ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS) 314 depends on (ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
315 select S3C64XX_DMA if ARCH_S3C64XX 315 select S3C64XX_DMA if ARCH_S3C64XX
316 help 316 help
317 SPI driver for Samsung S3C64XX and newer SoCs. 317 SPI driver for Samsung S3C64XX and newer SoCs.
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 13:32:05 -0400