diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/evergreend.h | 2 |
2 files changed, 7 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index c20eac3379e6..864e853cc0ec 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -1578,7 +1578,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) | |||
1578 | u32 sq_stack_resource_mgmt_2; | 1578 | u32 sq_stack_resource_mgmt_2; |
1579 | u32 sq_stack_resource_mgmt_3; | 1579 | u32 sq_stack_resource_mgmt_3; |
1580 | u32 vgt_cache_invalidation; | 1580 | u32 vgt_cache_invalidation; |
1581 | u32 hdp_host_path_cntl; | 1581 | u32 hdp_host_path_cntl, tmp; |
1582 | int i, j, num_shader_engines, ps_thread_count; | 1582 | int i, j, num_shader_engines, ps_thread_count; |
1583 | 1583 | ||
1584 | switch (rdev->family) { | 1584 | switch (rdev->family) { |
@@ -2138,6 +2138,10 @@ static void evergreen_gpu_init(struct radeon_device *rdev) | |||
2138 | for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4) | 2138 | for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4) |
2139 | WREG32(i, 0); | 2139 | WREG32(i, 0); |
2140 | 2140 | ||
2141 | tmp = RREG32(HDP_MISC_CNTL); | ||
2142 | tmp |= HDP_FLUSH_INVALIDATE_CACHE; | ||
2143 | WREG32(HDP_MISC_CNTL, tmp); | ||
2144 | |||
2141 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); | 2145 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); |
2142 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); | 2146 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); |
2143 | 2147 | ||
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index 94533849927e..75b57e394f2b 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h | |||
@@ -64,6 +64,8 @@ | |||
64 | #define GB_BACKEND_MAP 0x98FC | 64 | #define GB_BACKEND_MAP 0x98FC |
65 | #define DMIF_ADDR_CONFIG 0xBD4 | 65 | #define DMIF_ADDR_CONFIG 0xBD4 |
66 | #define HDP_ADDR_CONFIG 0x2F48 | 66 | #define HDP_ADDR_CONFIG 0x2F48 |
67 | #define HDP_MISC_CNTL 0x2F4C | ||
68 | #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) | ||
67 | 69 | ||
68 | #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 | 70 | #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 |
69 | #define GC_USER_RB_BACKEND_DISABLE 0x9B7C | 71 | #define GC_USER_RB_BACKEND_DISABLE 0x9B7C |