aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpio/Kconfig4
-rw-r--r--drivers/gpio/Makefile1
-rw-r--r--drivers/gpio/gpio-s3c64xx.c289
3 files changed, 294 insertions, 0 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 5654e1b082af..6368730a2e58 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -139,6 +139,10 @@ config GPIO_S3C24XX
139 def_bool y 139 def_bool y
140 depends on PLAT_S3C24XX 140 depends on PLAT_S3C24XX
141 141
142config GPIO_S3C64XX
143 def_bool y
144 depends on ARCH_S3C64XX
145
142config GPIO_S5PC100 146config GPIO_S5PC100
143 def_bool y 147 def_bool y
144 depends on CPU_S5PC100 148 depends on CPU_S5PC100
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index c7f1c00986c9..8c1fb23285cb 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
41 41
42obj-$(CONFIG_GPIO_PLAT_SAMSUNG) += gpio-plat-samsung.o 42obj-$(CONFIG_GPIO_PLAT_SAMSUNG) += gpio-plat-samsung.o
43obj-$(CONFIG_GPIO_S3C24XX) += gpio-s3c24xx.o 43obj-$(CONFIG_GPIO_S3C24XX) += gpio-s3c24xx.o
44obj-$(CONFIG_GPIO_S3C64XX) += gpio-s3c64xx.o
44obj-$(CONFIG_GPIO_S5PC100) += gpio-s5pc100.o 45obj-$(CONFIG_GPIO_S5PC100) += gpio-s5pc100.o
45obj-$(CONFIG_GPIO_S5PV210) += gpio-s5pv210.o 46obj-$(CONFIG_GPIO_S5PV210) += gpio-s5pv210.o
46 47
diff --git a/drivers/gpio/gpio-s3c64xx.c b/drivers/gpio/gpio-s3c64xx.c
new file mode 100644
index 000000000000..b4f1c8204f03
--- /dev/null
+++ b/drivers/gpio/gpio-s3c64xx.c
@@ -0,0 +1,289 @@
1/*
2 * Copyright 2008 Openmoko, Inc.
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C64XX - GPIOlib support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18
19#include <mach/map.h>
20
21#include <plat/gpio-core.h>
22#include <plat/gpio-cfg.h>
23#include <plat/gpio-cfg-helpers.h>
24#include <mach/regs-gpio.h>
25
26/* GPIO bank summary:
27 *
28 * Bank GPIOs Style SlpCon ExtInt Group
29 * A 8 4Bit Yes 1
30 * B 7 4Bit Yes 1
31 * C 8 4Bit Yes 2
32 * D 5 4Bit Yes 3
33 * E 5 4Bit Yes None
34 * F 16 2Bit Yes 4 [1]
35 * G 7 4Bit Yes 5
36 * H 10 4Bit[2] Yes 6
37 * I 16 2Bit Yes None
38 * J 12 2Bit Yes None
39 * K 16 4Bit[2] No None
40 * L 15 4Bit[2] No None
41 * M 6 4Bit No IRQ_EINT
42 * N 16 2Bit No IRQ_EINT
43 * O 16 2Bit Yes 7
44 * P 15 2Bit Yes 8
45 * Q 9 2Bit Yes 9
46 *
47 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
48 * [2] BANK has two control registers, GPxCON0 and GPxCON1
49 */
50
51static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
52 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
53 .get_config = s3c_gpio_getcfg_s3c64xx_4bit,
54 .set_pull = s3c_gpio_setpull_updown,
55 .get_pull = s3c_gpio_getpull_updown,
56};
57
58static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
59 .cfg_eint = 7,
60 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
61 .get_config = s3c_gpio_getcfg_s3c64xx_4bit,
62 .set_pull = s3c_gpio_setpull_updown,
63 .get_pull = s3c_gpio_getpull_updown,
64};
65
66static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
67 .cfg_eint = 3,
68 .get_config = s3c_gpio_getcfg_s3c64xx_4bit,
69 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
70 .set_pull = s3c_gpio_setpull_updown,
71 .get_pull = s3c_gpio_getpull_updown,
72};
73
74static int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
75{
76 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
77}
78
79static struct s3c_gpio_chip gpio_4bit[] = {
80 {
81 .base = S3C64XX_GPA_BASE,
82 .config = &gpio_4bit_cfg_eint0111,
83 .chip = {
84 .base = S3C64XX_GPA(0),
85 .ngpio = S3C64XX_GPIO_A_NR,
86 .label = "GPA",
87 },
88 }, {
89 .base = S3C64XX_GPB_BASE,
90 .config = &gpio_4bit_cfg_eint0111,
91 .chip = {
92 .base = S3C64XX_GPB(0),
93 .ngpio = S3C64XX_GPIO_B_NR,
94 .label = "GPB",
95 },
96 }, {
97 .base = S3C64XX_GPC_BASE,
98 .config = &gpio_4bit_cfg_eint0111,
99 .chip = {
100 .base = S3C64XX_GPC(0),
101 .ngpio = S3C64XX_GPIO_C_NR,
102 .label = "GPC",
103 },
104 }, {
105 .base = S3C64XX_GPD_BASE,
106 .config = &gpio_4bit_cfg_eint0111,
107 .chip = {
108 .base = S3C64XX_GPD(0),
109 .ngpio = S3C64XX_GPIO_D_NR,
110 .label = "GPD",
111 },
112 }, {
113 .base = S3C64XX_GPE_BASE,
114 .config = &gpio_4bit_cfg_noint,
115 .chip = {
116 .base = S3C64XX_GPE(0),
117 .ngpio = S3C64XX_GPIO_E_NR,
118 .label = "GPE",
119 },
120 }, {
121 .base = S3C64XX_GPG_BASE,
122 .config = &gpio_4bit_cfg_eint0111,
123 .chip = {
124 .base = S3C64XX_GPG(0),
125 .ngpio = S3C64XX_GPIO_G_NR,
126 .label = "GPG",
127 },
128 }, {
129 .base = S3C64XX_GPM_BASE,
130 .config = &gpio_4bit_cfg_eint0011,
131 .chip = {
132 .base = S3C64XX_GPM(0),
133 .ngpio = S3C64XX_GPIO_M_NR,
134 .label = "GPM",
135 .to_irq = s3c64xx_gpio2int_gpm,
136 },
137 },
138};
139
140static int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
141{
142 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
143}
144
145static struct s3c_gpio_chip gpio_4bit2[] = {
146 {
147 .base = S3C64XX_GPH_BASE + 0x4,
148 .config = &gpio_4bit_cfg_eint0111,
149 .chip = {
150 .base = S3C64XX_GPH(0),
151 .ngpio = S3C64XX_GPIO_H_NR,
152 .label = "GPH",
153 },
154 }, {
155 .base = S3C64XX_GPK_BASE + 0x4,
156 .config = &gpio_4bit_cfg_noint,
157 .chip = {
158 .base = S3C64XX_GPK(0),
159 .ngpio = S3C64XX_GPIO_K_NR,
160 .label = "GPK",
161 },
162 }, {
163 .base = S3C64XX_GPL_BASE + 0x4,
164 .config = &gpio_4bit_cfg_eint0011,
165 .chip = {
166 .base = S3C64XX_GPL(0),
167 .ngpio = S3C64XX_GPIO_L_NR,
168 .label = "GPL",
169 .to_irq = s3c64xx_gpio2int_gpl,
170 },
171 },
172};
173
174static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
175 .set_config = s3c_gpio_setcfg_s3c24xx,
176 .get_config = s3c_gpio_getcfg_s3c24xx,
177 .set_pull = s3c_gpio_setpull_updown,
178 .get_pull = s3c_gpio_getpull_updown,
179};
180
181static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
182 .cfg_eint = 2,
183 .set_config = s3c_gpio_setcfg_s3c24xx,
184 .get_config = s3c_gpio_getcfg_s3c24xx,
185 .set_pull = s3c_gpio_setpull_updown,
186 .get_pull = s3c_gpio_getpull_updown,
187};
188
189static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
190 .cfg_eint = 3,
191 .set_config = s3c_gpio_setcfg_s3c24xx,
192 .get_config = s3c_gpio_getcfg_s3c24xx,
193 .set_pull = s3c_gpio_setpull_updown,
194 .get_pull = s3c_gpio_getpull_updown,
195};
196
197static struct s3c_gpio_chip gpio_2bit[] = {
198 {
199 .base = S3C64XX_GPF_BASE,
200 .config = &gpio_2bit_cfg_eint11,
201 .chip = {
202 .base = S3C64XX_GPF(0),
203 .ngpio = S3C64XX_GPIO_F_NR,
204 .label = "GPF",
205 },
206 }, {
207 .base = S3C64XX_GPI_BASE,
208 .config = &gpio_2bit_cfg_noint,
209 .chip = {
210 .base = S3C64XX_GPI(0),
211 .ngpio = S3C64XX_GPIO_I_NR,
212 .label = "GPI",
213 },
214 }, {
215 .base = S3C64XX_GPJ_BASE,
216 .config = &gpio_2bit_cfg_noint,
217 .chip = {
218 .base = S3C64XX_GPJ(0),
219 .ngpio = S3C64XX_GPIO_J_NR,
220 .label = "GPJ",
221 },
222 }, {
223 .base = S3C64XX_GPN_BASE,
224 .irq_base = IRQ_EINT(0),
225 .config = &gpio_2bit_cfg_eint10,
226 .chip = {
227 .base = S3C64XX_GPN(0),
228 .ngpio = S3C64XX_GPIO_N_NR,
229 .label = "GPN",
230 .to_irq = samsung_gpiolib_to_irq,
231 },
232 }, {
233 .base = S3C64XX_GPO_BASE,
234 .config = &gpio_2bit_cfg_eint11,
235 .chip = {
236 .base = S3C64XX_GPO(0),
237 .ngpio = S3C64XX_GPIO_O_NR,
238 .label = "GPO",
239 },
240 }, {
241 .base = S3C64XX_GPP_BASE,
242 .config = &gpio_2bit_cfg_eint11,
243 .chip = {
244 .base = S3C64XX_GPP(0),
245 .ngpio = S3C64XX_GPIO_P_NR,
246 .label = "GPP",
247 },
248 }, {
249 .base = S3C64XX_GPQ_BASE,
250 .config = &gpio_2bit_cfg_eint11,
251 .chip = {
252 .base = S3C64XX_GPQ(0),
253 .ngpio = S3C64XX_GPIO_Q_NR,
254 .label = "GPQ",
255 },
256 },
257};
258
259static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
260{
261 chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
262}
263
264static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
265 int nr_chips,
266 void (*fn)(struct s3c_gpio_chip *))
267{
268 for (; nr_chips > 0; nr_chips--, chips++) {
269 if (fn)
270 (fn)(chips);
271 s3c_gpiolib_add(chips);
272 }
273}
274
275static __init int s3c64xx_gpiolib_init(void)
276{
277 s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
278 samsung_gpiolib_add_4bit);
279
280 s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
281 samsung_gpiolib_add_4bit2);
282
283 s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
284 s3c64xx_gpiolib_add_2bit);
285
286 return 0;
287}
288
289core_initcall(s3c64xx_gpiolib_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 18:26:33 -0400