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-rw-r--r--drivers/bcma/scan.c6
-rw-r--r--drivers/net/wireless/ath/ath6kl/cfg80211.c208
-rw-r--r--drivers/net/wireless/ath/ath6kl/cfg80211.h2
-rw-r--r--drivers/net/wireless/ath/ath6kl/core.h38
-rw-r--r--drivers/net/wireless/ath/ath6kl/htc_mbox.c2
-rw-r--r--drivers/net/wireless/ath/ath6kl/init.c28
-rw-r--r--drivers/net/wireless/ath/ath6kl/main.c27
-rw-r--r--drivers/net/wireless/ath/ath6kl/target.h1
-rw-r--r--drivers/net/wireless/ath/ath6kl/txrx.c48
-rw-r--r--drivers/net/wireless/ath/ath6kl/wmi.c148
-rw-r--r--drivers/net/wireless/ath/ath6kl/wmi.h58
-rw-r--r--drivers/net/wireless/ath/ath9k/ani.c489
-rw-r--r--drivers/net/wireless/ath/ath9k/ani.h32
-rw-r--r--drivers/net/wireless/ath/ath9k/ar5008_phy.c176
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_hw.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_mci.c21
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.c44
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h53
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h882
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9340_initvals.h755
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h7
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9485_initvals.h1404
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h772
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/gpio.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/htc.h4
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_beacon.c10
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_gpio.c122
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_init.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_main.c78
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_txrx.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h13
-rw-r--r--drivers/net/wireless/ath/ath9k/link.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c36
-rw-r--r--drivers/net/wireless/ath/ath9k/mci.c17
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h4
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c12
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c2
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h8
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c29
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c2
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c500
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c17
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/channel.c1226
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/channel.h4
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c2
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/main.c36
-rw-r--r--drivers/net/wireless/brcm80211/include/brcm_hw_ids.h1
-rw-r--r--drivers/net/wireless/iwlegacy/common.c7
-rw-r--r--drivers/net/wireless/iwlwifi/dvm/agn.h2
-rw-r--r--drivers/net/wireless/iwlwifi/dvm/dev.h2
-rw-r--r--drivers/net/wireless/iwlwifi/dvm/devices.c13
-rw-r--r--drivers/net/wireless/iwlwifi/dvm/lib.c2
-rw-r--r--drivers/net/wireless/iwlwifi/dvm/mac80211.c55
-rw-r--r--drivers/net/wireless/iwlwifi/dvm/main.c29
-rw-r--r--drivers/net/wireless/iwlwifi/dvm/scan.c47
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-eeprom-parse.c3
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-notif-wait.c5
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-op-mode.h16
-rw-r--r--drivers/net/wireless/iwlwifi/pcie/rx.c30
-rw-r--r--drivers/net/wireless/iwlwifi/pcie/trans.c19
-rw-r--r--drivers/net/wireless/mac80211_hwsim.c10
-rw-r--r--drivers/net/wireless/mwifiex/cfg80211.c65
-rw-r--r--drivers/net/wireless/mwifiex/cmdevt.c7
-rw-r--r--drivers/net/wireless/mwifiex/fw.h23
-rw-r--r--drivers/net/wireless/mwifiex/ie.c55
-rw-r--r--drivers/net/wireless/mwifiex/init.c1
-rw-r--r--drivers/net/wireless/mwifiex/ioctl.h10
-rw-r--r--drivers/net/wireless/mwifiex/main.c3
-rw-r--r--drivers/net/wireless/mwifiex/main.h8
-rw-r--r--drivers/net/wireless/mwifiex/scan.c25
-rw-r--r--drivers/net/wireless/mwifiex/sta_cmd.c23
-rw-r--r--drivers/net/wireless/mwifiex/sta_cmdresp.c27
-rw-r--r--drivers/net/wireless/mwifiex/sta_ioctl.c3
-rw-r--r--drivers/net/wireless/mwifiex/uap_cmd.c303
-rw-r--r--drivers/net/wireless/rt2x00/Kconfig8
-rw-r--r--drivers/net/wireless/rt2x00/rt2800.h173
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c350
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c82
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.h1
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.c1
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00.h1
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.c9
-rw-r--r--drivers/net/wireless/rtl818x/rtl8180/dev.c2
-rw-r--r--drivers/net/wireless/rtlwifi/cam.c5
-rw-r--r--drivers/net/wireless/rtlwifi/pci.c17
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/phy.c3
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/sw.c1
-rw-r--r--drivers/net/wireless/ti/wl1251/cmd.c9
-rw-r--r--drivers/net/wireless/ti/wl1251/main.c67
-rw-r--r--drivers/net/wireless/ti/wl1251/wl1251.h1
-rw-r--r--drivers/net/wireless/ti/wl12xx/cmd.c16
-rw-r--r--drivers/net/wireless/ti/wl12xx/main.c350
-rw-r--r--drivers/net/wireless/ti/wl18xx/acx.h34
-rw-r--r--drivers/net/wireless/ti/wl18xx/io.c39
-rw-r--r--drivers/net/wireless/ti/wl18xx/io.h4
-rw-r--r--drivers/net/wireless/ti/wl18xx/main.c365
-rw-r--r--drivers/net/wireless/ti/wlcore/acx.c8
-rw-r--r--drivers/net/wireless/ti/wlcore/acx.h5
-rw-r--r--drivers/net/wireless/ti/wlcore/boot.c84
-rw-r--r--drivers/net/wireless/ti/wlcore/cmd.c77
-rw-r--r--drivers/net/wireless/ti/wlcore/cmd.h21
-rw-r--r--drivers/net/wireless/ti/wlcore/conf.h8
-rw-r--r--drivers/net/wireless/ti/wlcore/debugfs.c255
-rw-r--r--drivers/net/wireless/ti/wlcore/event.c15
-rw-r--r--drivers/net/wireless/ti/wlcore/hw_ops.h12
-rw-r--r--drivers/net/wireless/ti/wlcore/ini.h22
-rw-r--r--drivers/net/wireless/ti/wlcore/init.c43
-rw-r--r--drivers/net/wireless/ti/wlcore/io.c55
-rw-r--r--drivers/net/wireless/ti/wlcore/io.h144
-rw-r--r--drivers/net/wireless/ti/wlcore/main.c348
-rw-r--r--drivers/net/wireless/ti/wlcore/ps.c16
-rw-r--r--drivers/net/wireless/ti/wlcore/rx.c41
-rw-r--r--drivers/net/wireless/ti/wlcore/rx.h10
-rw-r--r--drivers/net/wireless/ti/wlcore/sdio.c50
-rw-r--r--drivers/net/wireless/ti/wlcore/spi.c14
-rw-r--r--drivers/net/wireless/ti/wlcore/testmode.c14
-rw-r--r--drivers/net/wireless/ti/wlcore/tx.c86
-rw-r--r--drivers/net/wireless/ti/wlcore/tx.h4
-rw-r--r--drivers/net/wireless/ti/wlcore/wlcore.h24
-rw-r--r--drivers/net/wireless/ti/wlcore/wlcore_i.h9
123 files changed, 5019 insertions, 6019 deletions
diff --git a/drivers/bcma/scan.c b/drivers/bcma/scan.c
index 5ed0718fc660..a3420585d942 100644
--- a/drivers/bcma/scan.c
+++ b/drivers/bcma/scan.c
@@ -28,6 +28,12 @@ static const struct bcma_device_id_name bcma_arm_device_names[] = {
28 28
29static const struct bcma_device_id_name bcma_bcm_device_names[] = { 29static const struct bcma_device_id_name bcma_bcm_device_names[] = {
30 { BCMA_CORE_OOB_ROUTER, "OOB Router" }, 30 { BCMA_CORE_OOB_ROUTER, "OOB Router" },
31 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
32 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
33 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
34 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
35 { BCMA_CORE_ALTA, "ALTA (I2S)" },
36 { BCMA_CORE_4706_MAC_GBIT_COMMON, "BCM4706 GBit MAC Common" },
31 { BCMA_CORE_INVALID, "Invalid" }, 37 { BCMA_CORE_INVALID, "Invalid" },
32 { BCMA_CORE_CHIPCOMMON, "ChipCommon" }, 38 { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
33 { BCMA_CORE_ILINE20, "ILine 20" }, 39 { BCMA_CORE_ILINE20, "ILine 20" },
diff --git a/drivers/net/wireless/ath/ath6kl/cfg80211.c b/drivers/net/wireless/ath/ath6kl/cfg80211.c
index f27e9732951d..fd7dbd4609df 100644
--- a/drivers/net/wireless/ath/ath6kl/cfg80211.c
+++ b/drivers/net/wireless/ath/ath6kl/cfg80211.c
@@ -53,6 +53,11 @@
53 53
54#define DEFAULT_BG_SCAN_PERIOD 60 54#define DEFAULT_BG_SCAN_PERIOD 60
55 55
56struct ath6kl_cfg80211_match_probe_ssid {
57 struct cfg80211_ssid ssid;
58 u8 flag;
59};
60
56static struct ieee80211_rate ath6kl_rates[] = { 61static struct ieee80211_rate ath6kl_rates[] = {
57 RATETAB_ENT(10, 0x1, 0), 62 RATETAB_ENT(10, 0x1, 0),
58 RATETAB_ENT(20, 0x2, 0), 63 RATETAB_ENT(20, 0x2, 0),
@@ -576,6 +581,9 @@ static int ath6kl_cfg80211_connect(struct wiphy *wiphy, struct net_device *dev,
576 581
577 vif->nw_type = vif->next_mode; 582 vif->nw_type = vif->next_mode;
578 583
584 /* enable enhanced bmiss detection if applicable */
585 ath6kl_cfg80211_sta_bmiss_enhance(vif, true);
586
579 if (vif->wdev.iftype == NL80211_IFTYPE_P2P_CLIENT) 587 if (vif->wdev.iftype == NL80211_IFTYPE_P2P_CLIENT)
580 nw_subtype = SUBTYPE_P2PCLIENT; 588 nw_subtype = SUBTYPE_P2PCLIENT;
581 589
@@ -852,20 +860,6 @@ void ath6kl_cfg80211_disconnect_event(struct ath6kl_vif *vif, u8 reason,
852 } 860 }
853 } 861 }
854 862
855 /*
856 * Send a disconnect command to target when a disconnect event is
857 * received with reason code other than 3 (DISCONNECT_CMD - disconnect
858 * request from host) to make the firmware stop trying to connect even
859 * after giving disconnect event. There will be one more disconnect
860 * event for this disconnect command with reason code DISCONNECT_CMD
861 * which will be notified to cfg80211.
862 */
863
864 if (reason != DISCONNECT_CMD) {
865 ath6kl_wmi_disconnect_cmd(ar->wmi, vif->fw_vif_idx);
866 return;
867 }
868
869 clear_bit(CONNECT_PEND, &vif->flags); 863 clear_bit(CONNECT_PEND, &vif->flags);
870 864
871 if (vif->sme_state == SME_CONNECTING) { 865 if (vif->sme_state == SME_CONNECTING) {
@@ -875,32 +869,96 @@ void ath6kl_cfg80211_disconnect_event(struct ath6kl_vif *vif, u8 reason,
875 WLAN_STATUS_UNSPECIFIED_FAILURE, 869 WLAN_STATUS_UNSPECIFIED_FAILURE,
876 GFP_KERNEL); 870 GFP_KERNEL);
877 } else if (vif->sme_state == SME_CONNECTED) { 871 } else if (vif->sme_state == SME_CONNECTED) {
878 cfg80211_disconnected(vif->ndev, reason, 872 cfg80211_disconnected(vif->ndev, proto_reason,
879 NULL, 0, GFP_KERNEL); 873 NULL, 0, GFP_KERNEL);
880 } 874 }
881 875
882 vif->sme_state = SME_DISCONNECTED; 876 vif->sme_state = SME_DISCONNECTED;
877
878 /*
879 * Send a disconnect command to target when a disconnect event is
880 * received with reason code other than 3 (DISCONNECT_CMD - disconnect
881 * request from host) to make the firmware stop trying to connect even
882 * after giving disconnect event. There will be one more disconnect
883 * event for this disconnect command with reason code DISCONNECT_CMD
884 * which won't be notified to cfg80211.
885 */
886 if (reason != DISCONNECT_CMD)
887 ath6kl_wmi_disconnect_cmd(ar->wmi, vif->fw_vif_idx);
883} 888}
884 889
885static int ath6kl_set_probed_ssids(struct ath6kl *ar, 890static int ath6kl_set_probed_ssids(struct ath6kl *ar,
886 struct ath6kl_vif *vif, 891 struct ath6kl_vif *vif,
887 struct cfg80211_ssid *ssids, int n_ssids) 892 struct cfg80211_ssid *ssids, int n_ssids,
893 struct cfg80211_match_set *match_set,
894 int n_match_ssid)
888{ 895{
889 u8 i; 896 u8 i, j, index_to_add, ssid_found = false;
897 struct ath6kl_cfg80211_match_probe_ssid ssid_list[MAX_PROBED_SSIDS];
898
899 memset(ssid_list, 0, sizeof(ssid_list));
890 900
891 if (n_ssids > MAX_PROBED_SSID_INDEX) 901 if (n_ssids > MAX_PROBED_SSIDS ||
902 n_match_ssid > MAX_PROBED_SSIDS)
892 return -EINVAL; 903 return -EINVAL;
893 904
894 for (i = 0; i < n_ssids; i++) { 905 for (i = 0; i < n_ssids; i++) {
906 memcpy(ssid_list[i].ssid.ssid,
907 ssids[i].ssid,
908 ssids[i].ssid_len);
909 ssid_list[i].ssid.ssid_len = ssids[i].ssid_len;
910
911 if (ssids[i].ssid_len)
912 ssid_list[i].flag = SPECIFIC_SSID_FLAG;
913 else
914 ssid_list[i].flag = ANY_SSID_FLAG;
915
916 if (n_match_ssid == 0)
917 ssid_list[i].flag |= MATCH_SSID_FLAG;
918 }
919
920 index_to_add = i;
921
922 for (i = 0; i < n_match_ssid; i++) {
923 ssid_found = false;
924
925 for (j = 0; j < n_ssids; j++) {
926 if ((match_set[i].ssid.ssid_len ==
927 ssid_list[j].ssid.ssid_len) &&
928 (!memcmp(ssid_list[j].ssid.ssid,
929 match_set[i].ssid.ssid,
930 match_set[i].ssid.ssid_len))) {
931 ssid_list[j].flag |= MATCH_SSID_FLAG;
932 ssid_found = true;
933 break;
934 }
935 }
936
937 if (ssid_found)
938 continue;
939
940 if (index_to_add >= MAX_PROBED_SSIDS)
941 continue;
942
943 ssid_list[index_to_add].ssid.ssid_len =
944 match_set[i].ssid.ssid_len;
945 memcpy(ssid_list[index_to_add].ssid.ssid,
946 match_set[i].ssid.ssid,
947 match_set[i].ssid.ssid_len);
948 ssid_list[index_to_add].flag |= MATCH_SSID_FLAG;
949 index_to_add++;
950 }
951
952 for (i = 0; i < index_to_add; i++) {
895 ath6kl_wmi_probedssid_cmd(ar->wmi, vif->fw_vif_idx, i, 953 ath6kl_wmi_probedssid_cmd(ar->wmi, vif->fw_vif_idx, i,
896 ssids[i].ssid_len ? 954 ssid_list[i].flag,
897 SPECIFIC_SSID_FLAG : ANY_SSID_FLAG, 955 ssid_list[i].ssid.ssid_len,
898 ssids[i].ssid_len, 956 ssid_list[i].ssid.ssid);
899 ssids[i].ssid); 957
900 } 958 }
901 959
902 /* Make sure no old entries are left behind */ 960 /* Make sure no old entries are left behind */
903 for (i = n_ssids; i < MAX_PROBED_SSID_INDEX; i++) { 961 for (i = index_to_add; i < MAX_PROBED_SSIDS; i++) {
904 ath6kl_wmi_probedssid_cmd(ar->wmi, vif->fw_vif_idx, i, 962 ath6kl_wmi_probedssid_cmd(ar->wmi, vif->fw_vif_idx, i,
905 DISABLE_SSID_FLAG, 0, NULL); 963 DISABLE_SSID_FLAG, 0, NULL);
906 } 964 }
@@ -934,7 +992,7 @@ static int ath6kl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
934 } 992 }
935 993
936 ret = ath6kl_set_probed_ssids(ar, vif, request->ssids, 994 ret = ath6kl_set_probed_ssids(ar, vif, request->ssids,
937 request->n_ssids); 995 request->n_ssids, NULL, 0);
938 if (ret < 0) 996 if (ret < 0)
939 return ret; 997 return ret;
940 998
@@ -943,7 +1001,7 @@ static int ath6kl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
943 WMI_FRAME_PROBE_REQ, 1001 WMI_FRAME_PROBE_REQ,
944 request->ie, request->ie_len); 1002 request->ie, request->ie_len);
945 if (ret) { 1003 if (ret) {
946 ath6kl_err("failed to set Probe Request appie for scan"); 1004 ath6kl_err("failed to set Probe Request appie for scan\n");
947 return ret; 1005 return ret;
948 } 1006 }
949 1007
@@ -1512,6 +1570,9 @@ static int ath6kl_cfg80211_change_iface(struct wiphy *wiphy,
1512 } 1570 }
1513 } 1571 }
1514 1572
1573 /* need to clean up enhanced bmiss detection fw state */
1574 ath6kl_cfg80211_sta_bmiss_enhance(vif, false);
1575
1515set_iface_type: 1576set_iface_type:
1516 switch (type) { 1577 switch (type) {
1517 case NL80211_IFTYPE_STATION: 1578 case NL80211_IFTYPE_STATION:
@@ -2074,7 +2135,9 @@ static int ath6kl_wow_suspend(struct ath6kl *ar, struct cfg80211_wowlan *wow)
2074 if (wow && (wow->n_patterns > WOW_MAX_FILTERS_PER_LIST)) 2135 if (wow && (wow->n_patterns > WOW_MAX_FILTERS_PER_LIST))
2075 return -EINVAL; 2136 return -EINVAL;
2076 2137
2077 if (!test_bit(NETDEV_MCAST_ALL_ON, &vif->flags)) { 2138 if (!test_bit(NETDEV_MCAST_ALL_ON, &vif->flags) &&
2139 test_bit(ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER,
2140 ar->fw_capabilities)) {
2078 ret = ath6kl_wmi_mcast_filter_cmd(vif->ar->wmi, 2141 ret = ath6kl_wmi_mcast_filter_cmd(vif->ar->wmi,
2079 vif->fw_vif_idx, false); 2142 vif->fw_vif_idx, false);
2080 if (ret) 2143 if (ret)
@@ -2209,7 +2272,9 @@ static int ath6kl_wow_resume(struct ath6kl *ar)
2209 2272
2210 ar->state = ATH6KL_STATE_ON; 2273 ar->state = ATH6KL_STATE_ON;
2211 2274
2212 if (!test_bit(NETDEV_MCAST_ALL_OFF, &vif->flags)) { 2275 if (!test_bit(NETDEV_MCAST_ALL_OFF, &vif->flags) &&
2276 test_bit(ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER,
2277 ar->fw_capabilities)) {
2213 ret = ath6kl_wmi_mcast_filter_cmd(vif->ar->wmi, 2278 ret = ath6kl_wmi_mcast_filter_cmd(vif->ar->wmi,
2214 vif->fw_vif_idx, true); 2279 vif->fw_vif_idx, true);
2215 if (ret) 2280 if (ret)
@@ -2475,7 +2540,7 @@ void ath6kl_check_wow_status(struct ath6kl *ar)
2475static int ath6kl_set_htcap(struct ath6kl_vif *vif, enum ieee80211_band band, 2540static int ath6kl_set_htcap(struct ath6kl_vif *vif, enum ieee80211_band band,
2476 bool ht_enable) 2541 bool ht_enable)
2477{ 2542{
2478 struct ath6kl_htcap *htcap = &vif->htcap; 2543 struct ath6kl_htcap *htcap = &vif->htcap[band];
2479 2544
2480 if (htcap->ht_enable == ht_enable) 2545 if (htcap->ht_enable == ht_enable)
2481 return 0; 2546 return 0;
@@ -2585,6 +2650,30 @@ static int ath6kl_set_ies(struct ath6kl_vif *vif,
2585 return 0; 2650 return 0;
2586} 2651}
2587 2652
2653void ath6kl_cfg80211_sta_bmiss_enhance(struct ath6kl_vif *vif, bool enable)
2654{
2655 int err;
2656
2657 if (WARN_ON(!test_bit(WMI_READY, &vif->ar->flag)))
2658 return;
2659
2660 if (vif->nw_type != INFRA_NETWORK)
2661 return;
2662
2663 if (!test_bit(ATH6KL_FW_CAPABILITY_BMISS_ENHANCE,
2664 vif->ar->fw_capabilities))
2665 return;
2666
2667 ath6kl_dbg(ATH6KL_DBG_WLAN_CFG, "%s fw bmiss enhance\n",
2668 enable ? "enable" : "disable");
2669
2670 err = ath6kl_wmi_sta_bmiss_enhance_cmd(vif->ar->wmi,
2671 vif->fw_vif_idx, enable);
2672 if (err)
2673 ath6kl_err("failed to %s enhanced bmiss detection: %d\n",
2674 enable ? "enable" : "disable", err);
2675}
2676
2588static int ath6kl_get_rsn_capab(struct cfg80211_beacon_data *beacon, 2677static int ath6kl_get_rsn_capab(struct cfg80211_beacon_data *beacon,
2589 u8 *rsn_capab) 2678 u8 *rsn_capab)
2590{ 2679{
@@ -2665,9 +2754,15 @@ static int ath6kl_start_ap(struct wiphy *wiphy, struct net_device *dev,
2665 2754
2666 /* TODO: 2755 /* TODO:
2667 * info->interval 2756 * info->interval
2668 * info->dtim_period
2669 */ 2757 */
2670 2758
2759 ret = ath6kl_wmi_ap_set_dtim_cmd(ar->wmi, vif->fw_vif_idx,
2760 info->dtim_period);
2761
2762 /* ignore error, just print a warning and continue normally */
2763 if (ret)
2764 ath6kl_warn("Failed to set dtim_period in beacon: %d\n", ret);
2765
2671 if (info->beacon.head == NULL) 2766 if (info->beacon.head == NULL)
2672 return -EINVAL; 2767 return -EINVAL;
2673 mgmt = (struct ieee80211_mgmt *) info->beacon.head; 2768 mgmt = (struct ieee80211_mgmt *) info->beacon.head;
@@ -3131,10 +3226,24 @@ static int ath6kl_cfg80211_sscan_start(struct wiphy *wiphy,
3131 ath6kl_cfg80211_scan_complete_event(vif, true); 3226 ath6kl_cfg80211_scan_complete_event(vif, true);
3132 3227
3133 ret = ath6kl_set_probed_ssids(ar, vif, request->ssids, 3228 ret = ath6kl_set_probed_ssids(ar, vif, request->ssids,
3134 request->n_ssids); 3229 request->n_ssids,
3230 request->match_sets,
3231 request->n_match_sets);
3135 if (ret < 0) 3232 if (ret < 0)
3136 return ret; 3233 return ret;
3137 3234
3235 if (!request->n_match_sets) {
3236 ret = ath6kl_wmi_bssfilter_cmd(ar->wmi, vif->fw_vif_idx,
3237 ALL_BSS_FILTER, 0);
3238 if (ret < 0)
3239 return ret;
3240 } else {
3241 ret = ath6kl_wmi_bssfilter_cmd(ar->wmi, vif->fw_vif_idx,
3242 MATCHED_SSID_FILTER, 0);
3243 if (ret < 0)
3244 return ret;
3245 }
3246
3138 /* fw uses seconds, also make sure that it's >0 */ 3247 /* fw uses seconds, also make sure that it's >0 */
3139 interval = max_t(u16, 1, request->interval / 1000); 3248 interval = max_t(u16, 1, request->interval / 1000);
3140 3249
@@ -3156,7 +3265,7 @@ static int ath6kl_cfg80211_sscan_start(struct wiphy *wiphy,
3156 WMI_FRAME_PROBE_REQ, 3265 WMI_FRAME_PROBE_REQ,
3157 request->ie, request->ie_len); 3266 request->ie, request->ie_len);
3158 if (ret) { 3267 if (ret) {
3159 ath6kl_warn("Failed to set probe request IE for scheduled scan: %d", 3268 ath6kl_warn("Failed to set probe request IE for scheduled scan: %d\n",
3160 ret); 3269 ret);
3161 return ret; 3270 return ret;
3162 } 3271 }
@@ -3188,6 +3297,18 @@ static int ath6kl_cfg80211_sscan_stop(struct wiphy *wiphy,
3188 return 0; 3297 return 0;
3189} 3298}
3190 3299
3300static int ath6kl_cfg80211_set_bitrate(struct wiphy *wiphy,
3301 struct net_device *dev,
3302 const u8 *addr,
3303 const struct cfg80211_bitrate_mask *mask)
3304{
3305 struct ath6kl *ar = ath6kl_priv(dev);
3306 struct ath6kl_vif *vif = netdev_priv(dev);
3307
3308 return ath6kl_wmi_set_bitrate_mask(ar->wmi, vif->fw_vif_idx,
3309 mask);
3310}
3311
3191static const struct ieee80211_txrx_stypes 3312static const struct ieee80211_txrx_stypes
3192ath6kl_mgmt_stypes[NUM_NL80211_IFTYPES] = { 3313ath6kl_mgmt_stypes[NUM_NL80211_IFTYPES] = {
3193 [NL80211_IFTYPE_STATION] = { 3314 [NL80211_IFTYPE_STATION] = {
@@ -3253,6 +3374,7 @@ static struct cfg80211_ops ath6kl_cfg80211_ops = {
3253 .mgmt_frame_register = ath6kl_mgmt_frame_register, 3374 .mgmt_frame_register = ath6kl_mgmt_frame_register,
3254 .sched_scan_start = ath6kl_cfg80211_sscan_start, 3375 .sched_scan_start = ath6kl_cfg80211_sscan_start,
3255 .sched_scan_stop = ath6kl_cfg80211_sscan_stop, 3376 .sched_scan_stop = ath6kl_cfg80211_sscan_stop,
3377 .set_bitrate_mask = ath6kl_cfg80211_set_bitrate,
3256}; 3378};
3257 3379
3258void ath6kl_cfg80211_stop(struct ath6kl_vif *vif) 3380void ath6kl_cfg80211_stop(struct ath6kl_vif *vif)
@@ -3380,7 +3502,8 @@ struct net_device *ath6kl_interface_add(struct ath6kl *ar, char *name,
3380 vif->listen_intvl_t = ATH6KL_DEFAULT_LISTEN_INTVAL; 3502 vif->listen_intvl_t = ATH6KL_DEFAULT_LISTEN_INTVAL;
3381 vif->bmiss_time_t = ATH6KL_DEFAULT_BMISS_TIME; 3503 vif->bmiss_time_t = ATH6KL_DEFAULT_BMISS_TIME;
3382 vif->bg_scan_period = 0; 3504 vif->bg_scan_period = 0;
3383 vif->htcap.ht_enable = true; 3505 vif->htcap[IEEE80211_BAND_2GHZ].ht_enable = true;
3506 vif->htcap[IEEE80211_BAND_5GHZ].ht_enable = true;
3384 3507
3385 memcpy(ndev->dev_addr, ar->mac_addr, ETH_ALEN); 3508 memcpy(ndev->dev_addr, ar->mac_addr, ETH_ALEN);
3386 if (fw_vif_idx != 0) 3509 if (fw_vif_idx != 0)
@@ -3440,7 +3563,13 @@ int ath6kl_cfg80211_init(struct ath6kl *ar)
3440 } 3563 }
3441 3564
3442 /* max num of ssids that can be probed during scanning */ 3565 /* max num of ssids that can be probed during scanning */
3443 wiphy->max_scan_ssids = MAX_PROBED_SSID_INDEX; 3566 wiphy->max_scan_ssids = MAX_PROBED_SSIDS;
3567
3568 /* max num of ssids that can be matched after scan */
3569 if (test_bit(ATH6KL_FW_CAPABILITY_SCHED_SCAN_MATCH_LIST,
3570 ar->fw_capabilities))
3571 wiphy->max_match_sets = MAX_PROBED_SSIDS;
3572
3444 wiphy->max_scan_ie_len = 1000; /* FIX: what is correct limit? */ 3573 wiphy->max_scan_ie_len = 1000; /* FIX: what is correct limit? */
3445 switch (ar->hw.cap) { 3574 switch (ar->hw.cap) {
3446 case WMI_11AN_CAP: 3575 case WMI_11AN_CAP:
@@ -3477,6 +3606,17 @@ int ath6kl_cfg80211_init(struct ath6kl *ar)
3477 ath6kl_band_5ghz.ht_cap.cap = 0; 3606 ath6kl_band_5ghz.ht_cap.cap = 0;
3478 ath6kl_band_5ghz.ht_cap.ht_supported = false; 3607 ath6kl_band_5ghz.ht_cap.ht_supported = false;
3479 } 3608 }
3609
3610 if (ar->hw.flags & ATH6KL_HW_FLAG_64BIT_RATES) {
3611 ath6kl_band_2ghz.ht_cap.mcs.rx_mask[0] = 0xff;
3612 ath6kl_band_5ghz.ht_cap.mcs.rx_mask[0] = 0xff;
3613 ath6kl_band_2ghz.ht_cap.mcs.rx_mask[1] = 0xff;
3614 ath6kl_band_5ghz.ht_cap.mcs.rx_mask[1] = 0xff;
3615 } else {
3616 ath6kl_band_2ghz.ht_cap.mcs.rx_mask[0] = 0xff;
3617 ath6kl_band_5ghz.ht_cap.mcs.rx_mask[0] = 0xff;
3618 }
3619
3480 if (band_2gig) 3620 if (band_2gig)
3481 wiphy->bands[IEEE80211_BAND_2GHZ] = &ath6kl_band_2ghz; 3621 wiphy->bands[IEEE80211_BAND_2GHZ] = &ath6kl_band_2ghz;
3482 if (band_5gig) 3622 if (band_5gig)
@@ -3497,7 +3637,7 @@ int ath6kl_cfg80211_init(struct ath6kl *ar)
3497 wiphy->wowlan.pattern_min_len = 1; 3637 wiphy->wowlan.pattern_min_len = 1;
3498 wiphy->wowlan.pattern_max_len = WOW_PATTERN_SIZE; 3638 wiphy->wowlan.pattern_max_len = WOW_PATTERN_SIZE;
3499 3639
3500 wiphy->max_sched_scan_ssids = MAX_PROBED_SSID_INDEX; 3640 wiphy->max_sched_scan_ssids = MAX_PROBED_SSIDS;
3501 3641
3502 ar->wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM | 3642 ar->wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM |
3503 WIPHY_FLAG_HAVE_AP_SME | 3643 WIPHY_FLAG_HAVE_AP_SME |
diff --git a/drivers/net/wireless/ath/ath6kl/cfg80211.h b/drivers/net/wireless/ath/ath6kl/cfg80211.h
index 5ea8cbb79f43..b992046a1b0e 100644
--- a/drivers/net/wireless/ath/ath6kl/cfg80211.h
+++ b/drivers/net/wireless/ath/ath6kl/cfg80211.h
@@ -62,5 +62,7 @@ void ath6kl_cfg80211_cleanup(struct ath6kl *ar);
62 62
63struct ath6kl *ath6kl_cfg80211_create(void); 63struct ath6kl *ath6kl_cfg80211_create(void);
64void ath6kl_cfg80211_destroy(struct ath6kl *ar); 64void ath6kl_cfg80211_destroy(struct ath6kl *ar);
65/* TODO: remove this once ath6kl_vif_cleanup() is moved to cfg80211.c */
66void ath6kl_cfg80211_sta_bmiss_enhance(struct ath6kl_vif *vif, bool enable);
65 67
66#endif /* ATH6KL_CFG80211_H */ 68#endif /* ATH6KL_CFG80211_H */
diff --git a/drivers/net/wireless/ath/ath6kl/core.h b/drivers/net/wireless/ath/ath6kl/core.h
index 8443b2a4133e..d38a31de344c 100644
--- a/drivers/net/wireless/ath/ath6kl/core.h
+++ b/drivers/net/wireless/ath/ath6kl/core.h
@@ -100,6 +100,21 @@ enum ath6kl_fw_capability {
100 /* Firmware has support to override rsn cap of rsn ie */ 100 /* Firmware has support to override rsn cap of rsn ie */
101 ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE, 101 ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE,
102 102
103 /*
104 * Multicast support in WOW and host awake mode.
105 * Allow all multicast in host awake mode.
106 * Apply multicast filter in WOW mode.
107 */
108 ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER,
109
110 /* Firmware supports enhanced bmiss detection */
111 ATH6KL_FW_CAPABILITY_BMISS_ENHANCE,
112
113 /*
114 * FW supports matching of ssid in schedule scan
115 */
116 ATH6KL_FW_CAPABILITY_SCHED_SCAN_MATCH_LIST,
117
103 /* this needs to be last */ 118 /* this needs to be last */
104 ATH6KL_FW_CAPABILITY_MAX, 119 ATH6KL_FW_CAPABILITY_MAX,
105}; 120};
@@ -112,6 +127,10 @@ struct ath6kl_fw_ie {
112 u8 data[0]; 127 u8 data[0];
113}; 128};
114 129
130enum ath6kl_hw_flags {
131 ATH6KL_HW_FLAG_64BIT_RATES = BIT(0),
132};
133
115#define ATH6KL_FW_API2_FILE "fw-2.bin" 134#define ATH6KL_FW_API2_FILE "fw-2.bin"
116#define ATH6KL_FW_API3_FILE "fw-3.bin" 135#define ATH6KL_FW_API3_FILE "fw-3.bin"
117 136
@@ -196,7 +215,7 @@ struct ath6kl_fw_ie {
196 215
197#define AGGR_NUM_OF_FREE_NETBUFS 16 216#define AGGR_NUM_OF_FREE_NETBUFS 16
198 217
199#define AGGR_RX_TIMEOUT 400 /* in ms */ 218#define AGGR_RX_TIMEOUT 100 /* in ms */
200 219
201#define WMI_TIMEOUT (2 * HZ) 220#define WMI_TIMEOUT (2 * HZ)
202 221
@@ -245,7 +264,6 @@ struct skb_hold_q {
245 264
246struct rxtid { 265struct rxtid {
247 bool aggr; 266 bool aggr;
248 bool progress;
249 bool timer_mon; 267 bool timer_mon;
250 u16 win_sz; 268 u16 win_sz;
251 u16 seq_next; 269 u16 seq_next;
@@ -254,9 +272,15 @@ struct rxtid {
254 struct sk_buff_head q; 272 struct sk_buff_head q;
255 273
256 /* 274 /*
257 * FIXME: No clue what this should protect. Apparently it should 275 * lock mainly protects seq_next and hold_q. Movement of seq_next
258 * protect some of the fields above but they are also accessed 276 * needs to be protected between aggr_timeout() and
259 * without taking the lock. 277 * aggr_process_recv_frm(). hold_q will be holding the pending
278 * reorder frames and it's access should also be protected.
279 * Some of the other fields like hold_q_sz, win_sz and aggr are
280 * initialized/reset when receiving addba/delba req, also while
281 * deleting aggr state all the pending buffers are flushed before
282 * resetting these fields, so there should not be any race in accessing
283 * these fields.
260 */ 284 */
261 spinlock_t lock; 285 spinlock_t lock;
262}; 286};
@@ -541,7 +565,7 @@ struct ath6kl_vif {
541 struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1]; 565 struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1];
542 struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1]; 566 struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1];
543 struct aggr_info *aggr_cntxt; 567 struct aggr_info *aggr_cntxt;
544 struct ath6kl_htcap htcap; 568 struct ath6kl_htcap htcap[IEEE80211_NUM_BANDS];
545 569
546 struct timer_list disconnect_timer; 570 struct timer_list disconnect_timer;
547 struct timer_list sched_scan_timer; 571 struct timer_list sched_scan_timer;
@@ -684,6 +708,8 @@ struct ath6kl {
684 u32 testscript_addr; 708 u32 testscript_addr;
685 enum wmi_phy_cap cap; 709 enum wmi_phy_cap cap;
686 710
711 u32 flags;
712
687 struct ath6kl_hw_fw { 713 struct ath6kl_hw_fw {
688 const char *dir; 714 const char *dir;
689 const char *otp; 715 const char *otp;
diff --git a/drivers/net/wireless/ath/ath6kl/htc_mbox.c b/drivers/net/wireless/ath/ath6kl/htc_mbox.c
index 2798624d3a9d..cd0e1ba410d6 100644
--- a/drivers/net/wireless/ath/ath6kl/htc_mbox.c
+++ b/drivers/net/wireless/ath/ath6kl/htc_mbox.c
@@ -1309,7 +1309,7 @@ static int ath6kl_htc_rx_packet(struct htc_target *target,
1309 } 1309 }
1310 1310
1311 ath6kl_dbg(ATH6KL_DBG_HTC, 1311 ath6kl_dbg(ATH6KL_DBG_HTC,
1312 "htc rx 0x%p hdr x%x len %d mbox 0x%x\n", 1312 "htc rx 0x%p hdr 0x%x len %d mbox 0x%x\n",
1313 packet, packet->info.rx.exp_hdr, 1313 packet, packet->info.rx.exp_hdr,
1314 padded_len, dev->ar->mbox_info.htc_addr); 1314 padded_len, dev->ar->mbox_info.htc_addr);
1315 1315
diff --git a/drivers/net/wireless/ath/ath6kl/init.c b/drivers/net/wireless/ath/ath6kl/init.c
index 7eb0515f458a..f90b5db741cf 100644
--- a/drivers/net/wireless/ath/ath6kl/init.c
+++ b/drivers/net/wireless/ath/ath6kl/init.c
@@ -42,6 +42,7 @@ static const struct ath6kl_hw hw_list[] = {
42 .reserved_ram_size = 6912, 42 .reserved_ram_size = 6912,
43 .refclk_hz = 26000000, 43 .refclk_hz = 26000000,
44 .uarttx_pin = 8, 44 .uarttx_pin = 8,
45 .flags = 0,
45 46
46 /* hw2.0 needs override address hardcoded */ 47 /* hw2.0 needs override address hardcoded */
47 .app_start_override_addr = 0x944C00, 48 .app_start_override_addr = 0x944C00,
@@ -67,6 +68,7 @@ static const struct ath6kl_hw hw_list[] = {
67 .refclk_hz = 26000000, 68 .refclk_hz = 26000000,
68 .uarttx_pin = 8, 69 .uarttx_pin = 8,
69 .testscript_addr = 0x57ef74, 70 .testscript_addr = 0x57ef74,
71 .flags = 0,
70 72
71 .fw = { 73 .fw = {
72 .dir = AR6003_HW_2_1_1_FW_DIR, 74 .dir = AR6003_HW_2_1_1_FW_DIR,
@@ -91,6 +93,7 @@ static const struct ath6kl_hw hw_list[] = {
91 .board_addr = 0x433900, 93 .board_addr = 0x433900,
92 .refclk_hz = 26000000, 94 .refclk_hz = 26000000,
93 .uarttx_pin = 11, 95 .uarttx_pin = 11,
96 .flags = ATH6KL_HW_FLAG_64BIT_RATES,
94 97
95 .fw = { 98 .fw = {
96 .dir = AR6004_HW_1_0_FW_DIR, 99 .dir = AR6004_HW_1_0_FW_DIR,
@@ -110,6 +113,7 @@ static const struct ath6kl_hw hw_list[] = {
110 .board_addr = 0x43d400, 113 .board_addr = 0x43d400,
111 .refclk_hz = 40000000, 114 .refclk_hz = 40000000,
112 .uarttx_pin = 11, 115 .uarttx_pin = 11,
116 .flags = ATH6KL_HW_FLAG_64BIT_RATES,
113 117
114 .fw = { 118 .fw = {
115 .dir = AR6004_HW_1_1_FW_DIR, 119 .dir = AR6004_HW_1_1_FW_DIR,
@@ -129,6 +133,7 @@ static const struct ath6kl_hw hw_list[] = {
129 .board_addr = 0x435c00, 133 .board_addr = 0x435c00,
130 .refclk_hz = 40000000, 134 .refclk_hz = 40000000,
131 .uarttx_pin = 11, 135 .uarttx_pin = 11,
136 .flags = ATH6KL_HW_FLAG_64BIT_RATES,
132 137
133 .fw = { 138 .fw = {
134 .dir = AR6004_HW_1_2_FW_DIR, 139 .dir = AR6004_HW_1_2_FW_DIR,
@@ -938,6 +943,14 @@ static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
938 } 943 }
939 944
940 switch (ie_id) { 945 switch (ie_id) {
946 case ATH6KL_FW_IE_FW_VERSION:
947 strlcpy(ar->wiphy->fw_version, data,
948 sizeof(ar->wiphy->fw_version));
949
950 ath6kl_dbg(ATH6KL_DBG_BOOT,
951 "found fw version %s\n",
952 ar->wiphy->fw_version);
953 break;
941 case ATH6KL_FW_IE_OTP_IMAGE: 954 case ATH6KL_FW_IE_OTP_IMAGE:
942 ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n", 955 ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n",
943 ie_len); 956 ie_len);
@@ -991,9 +1004,6 @@ static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
991 ar->hw.reserved_ram_size); 1004 ar->hw.reserved_ram_size);
992 break; 1005 break;
993 case ATH6KL_FW_IE_CAPABILITIES: 1006 case ATH6KL_FW_IE_CAPABILITIES:
994 if (ie_len < DIV_ROUND_UP(ATH6KL_FW_CAPABILITY_MAX, 8))
995 break;
996
997 ath6kl_dbg(ATH6KL_DBG_BOOT, 1007 ath6kl_dbg(ATH6KL_DBG_BOOT,
998 "found firmware capabilities ie (%zd B)\n", 1008 "found firmware capabilities ie (%zd B)\n",
999 ie_len); 1009 ie_len);
@@ -1002,6 +1012,9 @@ static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
1002 index = i / 8; 1012 index = i / 8;
1003 bit = i % 8; 1013 bit = i % 8;
1004 1014
1015 if (index == ie_len)
1016 break;
1017
1005 if (data[index] & (1 << bit)) 1018 if (data[index] & (1 << bit))
1006 __set_bit(i, ar->fw_capabilities); 1019 __set_bit(i, ar->fw_capabilities);
1007 } 1020 }
@@ -1392,6 +1405,12 @@ static int ath6kl_init_upload(struct ath6kl *ar)
1392 ar->version.target_ver == AR6003_HW_2_1_1_VERSION) { 1405 ar->version.target_ver == AR6003_HW_2_1_1_VERSION) {
1393 ath6kl_err("temporary war to avoid sdio crc error\n"); 1406 ath6kl_err("temporary war to avoid sdio crc error\n");
1394 1407
1408 param = 0x28;
1409 address = GPIO_BASE_ADDRESS + GPIO_PIN9_ADDRESS;
1410 status = ath6kl_bmi_reg_write(ar, address, param);
1411 if (status)
1412 return status;
1413
1395 param = 0x20; 1414 param = 0x20;
1396 1415
1397 address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS; 1416 address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
@@ -1659,6 +1678,9 @@ void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready)
1659 cfg80211_scan_done(vif->scan_req, true); 1678 cfg80211_scan_done(vif->scan_req, true);
1660 vif->scan_req = NULL; 1679 vif->scan_req = NULL;
1661 } 1680 }
1681
1682 /* need to clean up enhanced bmiss detection fw state */
1683 ath6kl_cfg80211_sta_bmiss_enhance(vif, false);
1662} 1684}
1663 1685
1664void ath6kl_stop_txrx(struct ath6kl *ar) 1686void ath6kl_stop_txrx(struct ath6kl *ar)
diff --git a/drivers/net/wireless/ath/ath6kl/main.c b/drivers/net/wireless/ath/ath6kl/main.c
index b836f2795114..c189e28e86a9 100644
--- a/drivers/net/wireless/ath/ath6kl/main.c
+++ b/drivers/net/wireless/ath/ath6kl/main.c
@@ -554,20 +554,24 @@ void ath6kl_ready_event(void *devt, u8 *datap, u32 sw_ver, u32 abi_ver,
554 struct ath6kl *ar = devt; 554 struct ath6kl *ar = devt;
555 555
556 memcpy(ar->mac_addr, datap, ETH_ALEN); 556 memcpy(ar->mac_addr, datap, ETH_ALEN);
557 ath6kl_dbg(ATH6KL_DBG_TRC, "%s: mac addr = %pM\n", 557
558 __func__, ar->mac_addr); 558 ath6kl_dbg(ATH6KL_DBG_BOOT,
559 "ready event mac addr %pM sw_ver 0x%x abi_ver 0x%x cap 0x%x\n",
560 ar->mac_addr, sw_ver, abi_ver, cap);
559 561
560 ar->version.wlan_ver = sw_ver; 562 ar->version.wlan_ver = sw_ver;
561 ar->version.abi_ver = abi_ver; 563 ar->version.abi_ver = abi_ver;
562 ar->hw.cap = cap; 564 ar->hw.cap = cap;
563 565
564 snprintf(ar->wiphy->fw_version, 566 if (strlen(ar->wiphy->fw_version) == 0) {
565 sizeof(ar->wiphy->fw_version), 567 snprintf(ar->wiphy->fw_version,
566 "%u.%u.%u.%u", 568 sizeof(ar->wiphy->fw_version),
567 (ar->version.wlan_ver & 0xf0000000) >> 28, 569 "%u.%u.%u.%u",
568 (ar->version.wlan_ver & 0x0f000000) >> 24, 570 (ar->version.wlan_ver & 0xf0000000) >> 28,
569 (ar->version.wlan_ver & 0x00ff0000) >> 16, 571 (ar->version.wlan_ver & 0x0f000000) >> 24,
570 (ar->version.wlan_ver & 0x0000ffff)); 572 (ar->version.wlan_ver & 0x00ff0000) >> 16,
573 (ar->version.wlan_ver & 0x0000ffff));
574 }
571 575
572 /* indicate to the waiting thread that the ready event was received */ 576 /* indicate to the waiting thread that the ready event was received */
573 set_bit(WMI_READY, &ar->flag); 577 set_bit(WMI_READY, &ar->flag);
@@ -1166,7 +1170,10 @@ static void ath6kl_set_multicast_list(struct net_device *ndev)
1166 else 1170 else
1167 clear_bit(NETDEV_MCAST_ALL_ON, &vif->flags); 1171 clear_bit(NETDEV_MCAST_ALL_ON, &vif->flags);
1168 1172
1169 mc_all_on = mc_all_on || (vif->ar->state == ATH6KL_STATE_ON); 1173 if (test_bit(ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER,
1174 vif->ar->fw_capabilities)) {
1175 mc_all_on = mc_all_on || (vif->ar->state == ATH6KL_STATE_ON);
1176 }
1170 1177
1171 if (!(ndev->flags & IFF_MULTICAST)) { 1178 if (!(ndev->flags & IFF_MULTICAST)) {
1172 mc_all_on = false; 1179 mc_all_on = false;
diff --git a/drivers/net/wireless/ath/ath6kl/target.h b/drivers/net/wireless/ath/ath6kl/target.h
index 78e0ef4567a5..a98c12ba70c1 100644
--- a/drivers/net/wireless/ath/ath6kl/target.h
+++ b/drivers/net/wireless/ath/ath6kl/target.h
@@ -45,6 +45,7 @@
45#define LPO_CAL_ENABLE_S 20 45#define LPO_CAL_ENABLE_S 20
46#define LPO_CAL_ENABLE 0x00100000 46#define LPO_CAL_ENABLE 0x00100000
47 47
48#define GPIO_PIN9_ADDRESS 0x0000004c
48#define GPIO_PIN10_ADDRESS 0x00000050 49#define GPIO_PIN10_ADDRESS 0x00000050
49#define GPIO_PIN11_ADDRESS 0x00000054 50#define GPIO_PIN11_ADDRESS 0x00000054
50#define GPIO_PIN12_ADDRESS 0x00000058 51#define GPIO_PIN12_ADDRESS 0x00000058
diff --git a/drivers/net/wireless/ath/ath6kl/txrx.c b/drivers/net/wireless/ath/ath6kl/txrx.c
index 67206aedea6c..7dfa0fd86d7b 100644
--- a/drivers/net/wireless/ath/ath6kl/txrx.c
+++ b/drivers/net/wireless/ath/ath6kl/txrx.c
@@ -1036,6 +1036,7 @@ static void aggr_deque_frms(struct aggr_info_conn *agg_conn, u8 tid,
1036 rxtid = &agg_conn->rx_tid[tid]; 1036 rxtid = &agg_conn->rx_tid[tid];
1037 stats = &agg_conn->stat[tid]; 1037 stats = &agg_conn->stat[tid];
1038 1038
1039 spin_lock_bh(&rxtid->lock);
1039 idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz); 1040 idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz);
1040 1041
1041 /* 1042 /*
@@ -1054,8 +1055,6 @@ static void aggr_deque_frms(struct aggr_info_conn *agg_conn, u8 tid,
1054 seq_end = seq_no ? seq_no : rxtid->seq_next; 1055 seq_end = seq_no ? seq_no : rxtid->seq_next;
1055 idx_end = AGGR_WIN_IDX(seq_end, rxtid->hold_q_sz); 1056 idx_end = AGGR_WIN_IDX(seq_end, rxtid->hold_q_sz);
1056 1057
1057 spin_lock_bh(&rxtid->lock);
1058
1059 do { 1058 do {
1060 node = &rxtid->hold_q[idx]; 1059 node = &rxtid->hold_q[idx];
1061 if ((order == 1) && (!node->skb)) 1060 if ((order == 1) && (!node->skb))
@@ -1127,11 +1126,13 @@ static bool aggr_process_recv_frm(struct aggr_info_conn *agg_conn, u8 tid,
1127 ((end > extended_end) && (cur > extended_end) && 1126 ((end > extended_end) && (cur > extended_end) &&
1128 (cur < end))) { 1127 (cur < end))) {
1129 aggr_deque_frms(agg_conn, tid, 0, 0); 1128 aggr_deque_frms(agg_conn, tid, 0, 0);
1129 spin_lock_bh(&rxtid->lock);
1130 if (cur >= rxtid->hold_q_sz - 1) 1130 if (cur >= rxtid->hold_q_sz - 1)
1131 rxtid->seq_next = cur - (rxtid->hold_q_sz - 1); 1131 rxtid->seq_next = cur - (rxtid->hold_q_sz - 1);
1132 else 1132 else
1133 rxtid->seq_next = ATH6KL_MAX_SEQ_NO - 1133 rxtid->seq_next = ATH6KL_MAX_SEQ_NO -
1134 (rxtid->hold_q_sz - 2 - cur); 1134 (rxtid->hold_q_sz - 2 - cur);
1135 spin_unlock_bh(&rxtid->lock);
1135 } else { 1136 } else {
1136 /* 1137 /*
1137 * Dequeue only those frames that are outside the 1138 * Dequeue only those frames that are outside the
@@ -1185,25 +1186,25 @@ static bool aggr_process_recv_frm(struct aggr_info_conn *agg_conn, u8 tid,
1185 aggr_deque_frms(agg_conn, tid, 0, 1); 1186 aggr_deque_frms(agg_conn, tid, 0, 1);
1186 1187
1187 if (agg_conn->timer_scheduled) 1188 if (agg_conn->timer_scheduled)
1188 rxtid->progress = true; 1189 return is_queued;
1189 else 1190
1190 for (idx = 0 ; idx < rxtid->hold_q_sz; idx++) { 1191 spin_lock_bh(&rxtid->lock);
1191 if (rxtid->hold_q[idx].skb) { 1192 for (idx = 0 ; idx < rxtid->hold_q_sz; idx++) {
1192 /* 1193 if (rxtid->hold_q[idx].skb) {
1193 * There is a frame in the queue and no 1194 /*
1194 * timer so start a timer to ensure that 1195 * There is a frame in the queue and no
1195 * the frame doesn't remain stuck 1196 * timer so start a timer to ensure that
1196 * forever. 1197 * the frame doesn't remain stuck
1197 */ 1198 * forever.
1198 agg_conn->timer_scheduled = true; 1199 */
1199 mod_timer(&agg_conn->timer, 1200 agg_conn->timer_scheduled = true;
1200 (jiffies + 1201 mod_timer(&agg_conn->timer,
1201 HZ * (AGGR_RX_TIMEOUT) / 1000)); 1202 (jiffies + (HZ * AGGR_RX_TIMEOUT) / 1000));
1202 rxtid->progress = false; 1203 rxtid->timer_mon = true;
1203 rxtid->timer_mon = true; 1204 break;
1204 break;
1205 }
1206 } 1205 }
1206 }
1207 spin_unlock_bh(&rxtid->lock);
1207 1208
1208 return is_queued; 1209 return is_queued;
1209} 1210}
@@ -1608,7 +1609,7 @@ static void aggr_timeout(unsigned long arg)
1608 rxtid = &aggr_conn->rx_tid[i]; 1609 rxtid = &aggr_conn->rx_tid[i];
1609 stats = &aggr_conn->stat[i]; 1610 stats = &aggr_conn->stat[i];
1610 1611
1611 if (!rxtid->aggr || !rxtid->timer_mon || rxtid->progress) 1612 if (!rxtid->aggr || !rxtid->timer_mon)
1612 continue; 1613 continue;
1613 1614
1614 stats->num_timeouts++; 1615 stats->num_timeouts++;
@@ -1626,14 +1627,15 @@ static void aggr_timeout(unsigned long arg)
1626 rxtid = &aggr_conn->rx_tid[i]; 1627 rxtid = &aggr_conn->rx_tid[i];
1627 1628
1628 if (rxtid->aggr && rxtid->hold_q) { 1629 if (rxtid->aggr && rxtid->hold_q) {
1630 spin_lock_bh(&rxtid->lock);
1629 for (j = 0; j < rxtid->hold_q_sz; j++) { 1631 for (j = 0; j < rxtid->hold_q_sz; j++) {
1630 if (rxtid->hold_q[j].skb) { 1632 if (rxtid->hold_q[j].skb) {
1631 aggr_conn->timer_scheduled = true; 1633 aggr_conn->timer_scheduled = true;
1632 rxtid->timer_mon = true; 1634 rxtid->timer_mon = true;
1633 rxtid->progress = false;
1634 break; 1635 break;
1635 } 1636 }
1636 } 1637 }
1638 spin_unlock_bh(&rxtid->lock);
1637 1639
1638 if (j >= rxtid->hold_q_sz) 1640 if (j >= rxtid->hold_q_sz)
1639 rxtid->timer_mon = false; 1641 rxtid->timer_mon = false;
@@ -1660,7 +1662,6 @@ static void aggr_delete_tid_state(struct aggr_info_conn *aggr_conn, u8 tid)
1660 aggr_deque_frms(aggr_conn, tid, 0, 0); 1662 aggr_deque_frms(aggr_conn, tid, 0, 0);
1661 1663
1662 rxtid->aggr = false; 1664 rxtid->aggr = false;
1663 rxtid->progress = false;
1664 rxtid->timer_mon = false; 1665 rxtid->timer_mon = false;
1665 rxtid->win_sz = 0; 1666 rxtid->win_sz = 0;
1666 rxtid->seq_next = 0; 1667 rxtid->seq_next = 0;
@@ -1739,7 +1740,6 @@ void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info,
1739 for (i = 0; i < NUM_OF_TIDS; i++) { 1740 for (i = 0; i < NUM_OF_TIDS; i++) {
1740 rxtid = &aggr_conn->rx_tid[i]; 1741 rxtid = &aggr_conn->rx_tid[i];
1741 rxtid->aggr = false; 1742 rxtid->aggr = false;
1742 rxtid->progress = false;
1743 rxtid->timer_mon = false; 1743 rxtid->timer_mon = false;
1744 skb_queue_head_init(&rxtid->q); 1744 skb_queue_head_init(&rxtid->q);
1745 spin_lock_init(&rxtid->lock); 1745 spin_lock_init(&rxtid->lock);
diff --git a/drivers/net/wireless/ath/ath6kl/wmi.c b/drivers/net/wireless/ath/ath6kl/wmi.c
index ee8ec2394c2c..a6caa673e8ad 100644
--- a/drivers/net/wireless/ath/ath6kl/wmi.c
+++ b/drivers/net/wireless/ath/ath6kl/wmi.c
@@ -743,7 +743,6 @@ int ath6kl_wmi_force_roam_cmd(struct wmi *wmi, const u8 *bssid)
743 return -ENOMEM; 743 return -ENOMEM;
744 744
745 cmd = (struct roam_ctrl_cmd *) skb->data; 745 cmd = (struct roam_ctrl_cmd *) skb->data;
746 memset(cmd, 0, sizeof(*cmd));
747 746
748 memcpy(cmd->info.bssid, bssid, ETH_ALEN); 747 memcpy(cmd->info.bssid, bssid, ETH_ALEN);
749 cmd->roam_ctrl = WMI_FORCE_ROAM; 748 cmd->roam_ctrl = WMI_FORCE_ROAM;
@@ -753,6 +752,22 @@ int ath6kl_wmi_force_roam_cmd(struct wmi *wmi, const u8 *bssid)
753 NO_SYNC_WMIFLAG); 752 NO_SYNC_WMIFLAG);
754} 753}
755 754
755int ath6kl_wmi_ap_set_dtim_cmd(struct wmi *wmi, u8 if_idx, u32 dtim_period)
756{
757 struct sk_buff *skb;
758 struct set_dtim_cmd *cmd;
759
760 skb = ath6kl_wmi_get_new_buf(sizeof(*cmd));
761 if (!skb)
762 return -ENOMEM;
763
764 cmd = (struct set_dtim_cmd *) skb->data;
765
766 cmd->dtim_period = cpu_to_le32(dtim_period);
767 return ath6kl_wmi_cmd_send(wmi, if_idx, skb,
768 WMI_AP_SET_DTIM_CMDID, NO_SYNC_WMIFLAG);
769}
770
756int ath6kl_wmi_set_roam_mode_cmd(struct wmi *wmi, enum wmi_roam_mode mode) 771int ath6kl_wmi_set_roam_mode_cmd(struct wmi *wmi, enum wmi_roam_mode mode)
757{ 772{
758 struct sk_buff *skb; 773 struct sk_buff *skb;
@@ -763,7 +778,6 @@ int ath6kl_wmi_set_roam_mode_cmd(struct wmi *wmi, enum wmi_roam_mode mode)
763 return -ENOMEM; 778 return -ENOMEM;
764 779
765 cmd = (struct roam_ctrl_cmd *) skb->data; 780 cmd = (struct roam_ctrl_cmd *) skb->data;
766 memset(cmd, 0, sizeof(*cmd));
767 781
768 cmd->info.roam_mode = mode; 782 cmd->info.roam_mode = mode;
769 cmd->roam_ctrl = WMI_SET_ROAM_MODE; 783 cmd->roam_ctrl = WMI_SET_ROAM_MODE;
@@ -1995,7 +2009,7 @@ int ath6kl_wmi_probedssid_cmd(struct wmi *wmi, u8 if_idx, u8 index, u8 flag,
1995 struct wmi_probed_ssid_cmd *cmd; 2009 struct wmi_probed_ssid_cmd *cmd;
1996 int ret; 2010 int ret;
1997 2011
1998 if (index > MAX_PROBED_SSID_INDEX) 2012 if (index >= MAX_PROBED_SSIDS)
1999 return -EINVAL; 2013 return -EINVAL;
2000 2014
2001 if (ssid_len > sizeof(cmd->ssid)) 2015 if (ssid_len > sizeof(cmd->ssid))
@@ -2599,6 +2613,115 @@ static void ath6kl_wmi_relinquish_implicit_pstream_credits(struct wmi *wmi)
2599 spin_unlock_bh(&wmi->lock); 2613 spin_unlock_bh(&wmi->lock);
2600} 2614}
2601 2615
2616static int ath6kl_set_bitrate_mask64(struct wmi *wmi, u8 if_idx,
2617 const struct cfg80211_bitrate_mask *mask)
2618{
2619 struct sk_buff *skb;
2620 int ret, mode, band;
2621 u64 mcsrate, ratemask[IEEE80211_NUM_BANDS];
2622 struct wmi_set_tx_select_rates64_cmd *cmd;
2623
2624 memset(&ratemask, 0, sizeof(ratemask));
2625 for (band = 0; band < IEEE80211_NUM_BANDS; band++) {
2626 /* copy legacy rate mask */
2627 ratemask[band] = mask->control[band].legacy;
2628 if (band == IEEE80211_BAND_5GHZ)
2629 ratemask[band] =
2630 mask->control[band].legacy << 4;
2631
2632 /* copy mcs rate mask */
2633 mcsrate = mask->control[band].mcs[1];
2634 mcsrate <<= 8;
2635 mcsrate |= mask->control[band].mcs[0];
2636 ratemask[band] |= mcsrate << 12;
2637 ratemask[band] |= mcsrate << 28;
2638 }
2639
2640 ath6kl_dbg(ATH6KL_DBG_WMI,
2641 "Ratemask 64 bit: 2.4:%llx 5:%llx\n",
2642 ratemask[0], ratemask[1]);
2643
2644 skb = ath6kl_wmi_get_new_buf(sizeof(*cmd) * WMI_RATES_MODE_MAX);
2645 if (!skb)
2646 return -ENOMEM;
2647
2648 cmd = (struct wmi_set_tx_select_rates64_cmd *) skb->data;
2649 for (mode = 0; mode < WMI_RATES_MODE_MAX; mode++) {
2650 /* A mode operate in 5GHZ band */
2651 if (mode == WMI_RATES_MODE_11A ||
2652 mode == WMI_RATES_MODE_11A_HT20 ||
2653 mode == WMI_RATES_MODE_11A_HT40)
2654 band = IEEE80211_BAND_5GHZ;
2655 else
2656 band = IEEE80211_BAND_2GHZ;
2657 cmd->ratemask[mode] = cpu_to_le64(ratemask[band]);
2658 }
2659
2660 ret = ath6kl_wmi_cmd_send(wmi, if_idx, skb,
2661 WMI_SET_TX_SELECT_RATES_CMDID,
2662 NO_SYNC_WMIFLAG);
2663 return ret;
2664}
2665
2666static int ath6kl_set_bitrate_mask32(struct wmi *wmi, u8 if_idx,
2667 const struct cfg80211_bitrate_mask *mask)
2668{
2669 struct sk_buff *skb;
2670 int ret, mode, band;
2671 u32 mcsrate, ratemask[IEEE80211_NUM_BANDS];
2672 struct wmi_set_tx_select_rates32_cmd *cmd;
2673
2674 memset(&ratemask, 0, sizeof(ratemask));
2675 for (band = 0; band < IEEE80211_NUM_BANDS; band++) {
2676 /* copy legacy rate mask */
2677 ratemask[band] = mask->control[band].legacy;
2678 if (band == IEEE80211_BAND_5GHZ)
2679 ratemask[band] =
2680 mask->control[band].legacy << 4;
2681
2682 /* copy mcs rate mask */
2683 mcsrate = mask->control[band].mcs[0];
2684 ratemask[band] |= mcsrate << 12;
2685 ratemask[band] |= mcsrate << 20;
2686 }
2687
2688 ath6kl_dbg(ATH6KL_DBG_WMI,
2689 "Ratemask 32 bit: 2.4:%x 5:%x\n",
2690 ratemask[0], ratemask[1]);
2691
2692 skb = ath6kl_wmi_get_new_buf(sizeof(*cmd) * WMI_RATES_MODE_MAX);
2693 if (!skb)
2694 return -ENOMEM;
2695
2696 cmd = (struct wmi_set_tx_select_rates32_cmd *) skb->data;
2697 for (mode = 0; mode < WMI_RATES_MODE_MAX; mode++) {
2698 /* A mode operate in 5GHZ band */
2699 if (mode == WMI_RATES_MODE_11A ||
2700 mode == WMI_RATES_MODE_11A_HT20 ||
2701 mode == WMI_RATES_MODE_11A_HT40)
2702 band = IEEE80211_BAND_5GHZ;
2703 else
2704 band = IEEE80211_BAND_2GHZ;
2705 cmd->ratemask[mode] = cpu_to_le32(ratemask[band]);
2706 }
2707
2708 ret = ath6kl_wmi_cmd_send(wmi, if_idx, skb,
2709 WMI_SET_TX_SELECT_RATES_CMDID,
2710 NO_SYNC_WMIFLAG);
2711 return ret;
2712}
2713
2714int ath6kl_wmi_set_bitrate_mask(struct wmi *wmi, u8 if_idx,
2715 const struct cfg80211_bitrate_mask *mask)
2716{
2717 struct ath6kl *ar = wmi->parent_dev;
2718
2719 if (ar->hw.flags & ATH6KL_HW_FLAG_64BIT_RATES)
2720 return ath6kl_set_bitrate_mask64(wmi, if_idx, mask);
2721 else
2722 return ath6kl_set_bitrate_mask32(wmi, if_idx, mask);
2723}
2724
2602int ath6kl_wmi_set_host_sleep_mode_cmd(struct wmi *wmi, u8 if_idx, 2725int ath6kl_wmi_set_host_sleep_mode_cmd(struct wmi *wmi, u8 if_idx,
2603 enum ath6kl_host_mode host_mode) 2726 enum ath6kl_host_mode host_mode)
2604{ 2727{
@@ -2997,6 +3120,25 @@ int ath6kl_wmi_add_del_mcast_filter_cmd(struct wmi *wmi, u8 if_idx,
2997 return ret; 3120 return ret;
2998} 3121}
2999 3122
3123int ath6kl_wmi_sta_bmiss_enhance_cmd(struct wmi *wmi, u8 if_idx, bool enhance)
3124{
3125 struct sk_buff *skb;
3126 struct wmi_sta_bmiss_enhance_cmd *cmd;
3127 int ret;
3128
3129 skb = ath6kl_wmi_get_new_buf(sizeof(*cmd));
3130 if (!skb)
3131 return -ENOMEM;
3132
3133 cmd = (struct wmi_sta_bmiss_enhance_cmd *) skb->data;
3134 cmd->enable = enhance ? 1 : 0;
3135
3136 ret = ath6kl_wmi_cmd_send(wmi, if_idx, skb,
3137 WMI_STA_BMISS_ENHANCE_CMDID,
3138 NO_SYNC_WMIFLAG);
3139 return ret;
3140}
3141
3000s32 ath6kl_wmi_get_rate(s8 rate_index) 3142s32 ath6kl_wmi_get_rate(s8 rate_index)
3001{ 3143{
3002 if (rate_index == RATE_AUTO) 3144 if (rate_index == RATE_AUTO)
diff --git a/drivers/net/wireless/ath/ath6kl/wmi.h b/drivers/net/wireless/ath/ath6kl/wmi.h
index 9076bec3a2ba..43339aca585d 100644
--- a/drivers/net/wireless/ath/ath6kl/wmi.h
+++ b/drivers/net/wireless/ath/ath6kl/wmi.h
@@ -624,6 +624,10 @@ enum wmi_cmd_id {
624 WMI_SEND_MGMT_CMDID, 624 WMI_SEND_MGMT_CMDID,
625 WMI_BEGIN_SCAN_CMDID, 625 WMI_BEGIN_SCAN_CMDID,
626 626
627 WMI_SET_BLACK_LIST,
628 WMI_SET_MCASTRATE,
629
630 WMI_STA_BMISS_ENHANCE_CMDID,
627}; 631};
628 632
629enum wmi_mgmt_frame_type { 633enum wmi_mgmt_frame_type {
@@ -960,6 +964,9 @@ enum wmi_bss_filter {
960 /* beacons matching probed ssid */ 964 /* beacons matching probed ssid */
961 PROBED_SSID_FILTER, 965 PROBED_SSID_FILTER,
962 966
967 /* beacons matching matched ssid */
968 MATCHED_SSID_FILTER,
969
963 /* marker only */ 970 /* marker only */
964 LAST_BSS_FILTER, 971 LAST_BSS_FILTER,
965}; 972};
@@ -978,7 +985,7 @@ struct wmi_bss_filter_cmd {
978} __packed; 985} __packed;
979 986
980/* WMI_SET_PROBED_SSID_CMDID */ 987/* WMI_SET_PROBED_SSID_CMDID */
981#define MAX_PROBED_SSID_INDEX 9 988#define MAX_PROBED_SSIDS 16
982 989
983enum wmi_ssid_flag { 990enum wmi_ssid_flag {
984 /* disables entry */ 991 /* disables entry */
@@ -989,10 +996,13 @@ enum wmi_ssid_flag {
989 996
990 /* probes for any ssid */ 997 /* probes for any ssid */
991 ANY_SSID_FLAG = 0x02, 998 ANY_SSID_FLAG = 0x02,
999
1000 /* match for ssid */
1001 MATCH_SSID_FLAG = 0x08,
992}; 1002};
993 1003
994struct wmi_probed_ssid_cmd { 1004struct wmi_probed_ssid_cmd {
995 /* 0 to MAX_PROBED_SSID_INDEX */ 1005 /* 0 to MAX_PROBED_SSIDS - 1 */
996 u8 entry_index; 1006 u8 entry_index;
997 1007
998 /* see, enum wmi_ssid_flg */ 1008 /* see, enum wmi_ssid_flg */
@@ -1017,6 +1027,11 @@ struct wmi_bmiss_time_cmd {
1017 __le16 num_beacons; 1027 __le16 num_beacons;
1018}; 1028};
1019 1029
1030/* WMI_STA_ENHANCE_BMISS_CMDID */
1031struct wmi_sta_bmiss_enhance_cmd {
1032 u8 enable;
1033} __packed;
1034
1020/* WMI_SET_POWER_MODE_CMDID */ 1035/* WMI_SET_POWER_MODE_CMDID */
1021enum wmi_power_mode { 1036enum wmi_power_mode {
1022 REC_POWER = 0x01, 1037 REC_POWER = 0x01,
@@ -1048,6 +1063,36 @@ struct wmi_power_params_cmd {
1048 __le16 ps_fail_event_policy; 1063 __le16 ps_fail_event_policy;
1049} __packed; 1064} __packed;
1050 1065
1066/*
1067 * Ratemask for below modes should be passed
1068 * to WMI_SET_TX_SELECT_RATES_CMDID.
1069 * AR6003 has 32 bit mask for each modes.
1070 * First 12 bits for legacy rates, 13 to 20
1071 * bits for HT 20 rates and 21 to 28 bits for
1072 * HT 40 rates
1073 */
1074enum wmi_mode_phy {
1075 WMI_RATES_MODE_11A = 0,
1076 WMI_RATES_MODE_11G,
1077 WMI_RATES_MODE_11B,
1078 WMI_RATES_MODE_11GONLY,
1079 WMI_RATES_MODE_11A_HT20,
1080 WMI_RATES_MODE_11G_HT20,
1081 WMI_RATES_MODE_11A_HT40,
1082 WMI_RATES_MODE_11G_HT40,
1083 WMI_RATES_MODE_MAX
1084};
1085
1086/* WMI_SET_TX_SELECT_RATES_CMDID */
1087struct wmi_set_tx_select_rates32_cmd {
1088 __le32 ratemask[WMI_RATES_MODE_MAX];
1089} __packed;
1090
1091/* WMI_SET_TX_SELECT_RATES_CMDID */
1092struct wmi_set_tx_select_rates64_cmd {
1093 __le64 ratemask[WMI_RATES_MODE_MAX];
1094} __packed;
1095
1051/* WMI_SET_DISC_TIMEOUT_CMDID */ 1096/* WMI_SET_DISC_TIMEOUT_CMDID */
1052struct wmi_disc_timeout_cmd { 1097struct wmi_disc_timeout_cmd {
1053 /* seconds */ 1098 /* seconds */
@@ -1572,6 +1617,10 @@ struct roam_ctrl_cmd {
1572 u8 roam_ctrl; 1617 u8 roam_ctrl;
1573} __packed; 1618} __packed;
1574 1619
1620struct set_dtim_cmd {
1621 __le32 dtim_period;
1622} __packed;
1623
1575/* BSS INFO HDR version 2.0 */ 1624/* BSS INFO HDR version 2.0 */
1576struct wmi_bss_info_hdr2 { 1625struct wmi_bss_info_hdr2 {
1577 __le16 ch; /* frequency in MHz */ 1626 __le16 ch; /* frequency in MHz */
@@ -2532,6 +2581,8 @@ int ath6kl_wmi_set_ip_cmd(struct wmi *wmi, u8 if_idx,
2532 __be32 ips0, __be32 ips1); 2581 __be32 ips0, __be32 ips1);
2533int ath6kl_wmi_set_host_sleep_mode_cmd(struct wmi *wmi, u8 if_idx, 2582int ath6kl_wmi_set_host_sleep_mode_cmd(struct wmi *wmi, u8 if_idx,
2534 enum ath6kl_host_mode host_mode); 2583 enum ath6kl_host_mode host_mode);
2584int ath6kl_wmi_set_bitrate_mask(struct wmi *wmi, u8 if_idx,
2585 const struct cfg80211_bitrate_mask *mask);
2535int ath6kl_wmi_set_wow_mode_cmd(struct wmi *wmi, u8 if_idx, 2586int ath6kl_wmi_set_wow_mode_cmd(struct wmi *wmi, u8 if_idx,
2536 enum ath6kl_wow_mode wow_mode, 2587 enum ath6kl_wow_mode wow_mode,
2537 u32 filter, u16 host_req_delay); 2588 u32 filter, u16 host_req_delay);
@@ -2542,11 +2593,14 @@ int ath6kl_wmi_add_wow_pattern_cmd(struct wmi *wmi, u8 if_idx,
2542int ath6kl_wmi_del_wow_pattern_cmd(struct wmi *wmi, u8 if_idx, 2593int ath6kl_wmi_del_wow_pattern_cmd(struct wmi *wmi, u8 if_idx,
2543 u16 list_id, u16 filter_id); 2594 u16 list_id, u16 filter_id);
2544int ath6kl_wmi_set_roam_lrssi_cmd(struct wmi *wmi, u8 lrssi); 2595int ath6kl_wmi_set_roam_lrssi_cmd(struct wmi *wmi, u8 lrssi);
2596int ath6kl_wmi_ap_set_dtim_cmd(struct wmi *wmi, u8 if_idx, u32 dtim_period);
2545int ath6kl_wmi_force_roam_cmd(struct wmi *wmi, const u8 *bssid); 2597int ath6kl_wmi_force_roam_cmd(struct wmi *wmi, const u8 *bssid);
2546int ath6kl_wmi_set_roam_mode_cmd(struct wmi *wmi, enum wmi_roam_mode mode); 2598int ath6kl_wmi_set_roam_mode_cmd(struct wmi *wmi, enum wmi_roam_mode mode);
2547int ath6kl_wmi_mcast_filter_cmd(struct wmi *wmi, u8 if_idx, bool mc_all_on); 2599int ath6kl_wmi_mcast_filter_cmd(struct wmi *wmi, u8 if_idx, bool mc_all_on);
2548int ath6kl_wmi_add_del_mcast_filter_cmd(struct wmi *wmi, u8 if_idx, 2600int ath6kl_wmi_add_del_mcast_filter_cmd(struct wmi *wmi, u8 if_idx,
2549 u8 *filter, bool add_filter); 2601 u8 *filter, bool add_filter);
2602int ath6kl_wmi_sta_bmiss_enhance_cmd(struct wmi *wmi, u8 if_idx, bool enable);
2603
2550/* AP mode uAPSD */ 2604/* AP mode uAPSD */
2551int ath6kl_wmi_ap_set_apsd(struct wmi *wmi, u8 if_idx, u8 enable); 2605int ath6kl_wmi_ap_set_apsd(struct wmi *wmi, u8 if_idx, u8 enable);
2552 2606
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index b4c77f9d7470..ff007f500feb 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -104,11 +104,6 @@ static const struct ani_cck_level_entry cck_level_table[] = {
104#define ATH9K_ANI_CCK_DEF_LEVEL \ 104#define ATH9K_ANI_CCK_DEF_LEVEL \
105 2 /* default level - matches the INI settings */ 105 2 /* default level - matches the INI settings */
106 106
107static bool use_new_ani(struct ath_hw *ah)
108{
109 return AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani;
110}
111
112static void ath9k_hw_update_mibstats(struct ath_hw *ah, 107static void ath9k_hw_update_mibstats(struct ath_hw *ah,
113 struct ath9k_mib_stats *stats) 108 struct ath9k_mib_stats *stats)
114{ 109{
@@ -122,8 +117,6 @@ static void ath9k_hw_update_mibstats(struct ath_hw *ah,
122static void ath9k_ani_restart(struct ath_hw *ah) 117static void ath9k_ani_restart(struct ath_hw *ah)
123{ 118{
124 struct ar5416AniState *aniState; 119 struct ar5416AniState *aniState;
125 struct ath_common *common = ath9k_hw_common(ah);
126 u32 ofdm_base = 0, cck_base = 0;
127 120
128 if (!DO_ANI(ah)) 121 if (!DO_ANI(ah))
129 return; 122 return;
@@ -131,18 +124,10 @@ static void ath9k_ani_restart(struct ath_hw *ah)
131 aniState = &ah->curchan->ani; 124 aniState = &ah->curchan->ani;
132 aniState->listenTime = 0; 125 aniState->listenTime = 0;
133 126
134 if (!use_new_ani(ah)) {
135 ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
136 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
137 }
138
139 ath_dbg(common, ANI, "Writing ofdmbase=%u cckbase=%u\n",
140 ofdm_base, cck_base);
141
142 ENABLE_REGWRITE_BUFFER(ah); 127 ENABLE_REGWRITE_BUFFER(ah);
143 128
144 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base); 129 REG_WRITE(ah, AR_PHY_ERR_1, 0);
145 REG_WRITE(ah, AR_PHY_ERR_2, cck_base); 130 REG_WRITE(ah, AR_PHY_ERR_2, 0);
146 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 131 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
147 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 132 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
148 133
@@ -154,129 +139,23 @@ static void ath9k_ani_restart(struct ath_hw *ah)
154 aniState->cckPhyErrCount = 0; 139 aniState->cckPhyErrCount = 0;
155} 140}
156 141
157static void ath9k_hw_ani_ofdm_err_trigger_old(struct ath_hw *ah)
158{
159 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
160 struct ar5416AniState *aniState;
161 int32_t rssi;
162
163 aniState = &ah->curchan->ani;
164
165 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
166 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
167 aniState->noiseImmunityLevel + 1)) {
168 return;
169 }
170 }
171
172 if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
173 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
174 aniState->spurImmunityLevel + 1)) {
175 return;
176 }
177 }
178
179 if (ah->opmode == NL80211_IFTYPE_AP) {
180 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
181 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
182 aniState->firstepLevel + 1);
183 }
184 return;
185 }
186 rssi = BEACON_RSSI(ah);
187 if (rssi > aniState->rssiThrHigh) {
188 if (!aniState->ofdmWeakSigDetectOff) {
189 if (ath9k_hw_ani_control(ah,
190 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
191 false)) {
192 ath9k_hw_ani_control(ah,
193 ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
194 return;
195 }
196 }
197 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
198 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
199 aniState->firstepLevel + 1);
200 return;
201 }
202 } else if (rssi > aniState->rssiThrLow) {
203 if (aniState->ofdmWeakSigDetectOff)
204 ath9k_hw_ani_control(ah,
205 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
206 true);
207 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
208 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
209 aniState->firstepLevel + 1);
210 return;
211 } else {
212 if ((conf->channel->band == IEEE80211_BAND_2GHZ) &&
213 !conf_is_ht(conf)) {
214 if (!aniState->ofdmWeakSigDetectOff)
215 ath9k_hw_ani_control(ah,
216 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
217 false);
218 if (aniState->firstepLevel > 0)
219 ath9k_hw_ani_control(ah,
220 ATH9K_ANI_FIRSTEP_LEVEL, 0);
221 return;
222 }
223 }
224}
225
226static void ath9k_hw_ani_cck_err_trigger_old(struct ath_hw *ah)
227{
228 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
229 struct ar5416AniState *aniState;
230 int32_t rssi;
231
232 aniState = &ah->curchan->ani;
233 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
234 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
235 aniState->noiseImmunityLevel + 1)) {
236 return;
237 }
238 }
239 if (ah->opmode == NL80211_IFTYPE_AP) {
240 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
241 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
242 aniState->firstepLevel + 1);
243 }
244 return;
245 }
246 rssi = BEACON_RSSI(ah);
247 if (rssi > aniState->rssiThrLow) {
248 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
249 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
250 aniState->firstepLevel + 1);
251 } else {
252 if ((conf->channel->band == IEEE80211_BAND_2GHZ) &&
253 !conf_is_ht(conf)) {
254 if (aniState->firstepLevel > 0)
255 ath9k_hw_ani_control(ah,
256 ATH9K_ANI_FIRSTEP_LEVEL, 0);
257 }
258 }
259}
260
261/* Adjust the OFDM Noise Immunity Level */ 142/* Adjust the OFDM Noise Immunity Level */
262static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel) 143static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel,
144 bool scan)
263{ 145{
264 struct ar5416AniState *aniState = &ah->curchan->ani; 146 struct ar5416AniState *aniState = &ah->curchan->ani;
265 struct ath_common *common = ath9k_hw_common(ah); 147 struct ath_common *common = ath9k_hw_common(ah);
266 const struct ani_ofdm_level_entry *entry_ofdm; 148 const struct ani_ofdm_level_entry *entry_ofdm;
267 const struct ani_cck_level_entry *entry_cck; 149 const struct ani_cck_level_entry *entry_cck;
268 150 bool weak_sig;
269 aniState->noiseFloor = BEACON_RSSI(ah);
270 151
271 ath_dbg(common, ANI, "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", 152 ath_dbg(common, ANI, "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
272 aniState->ofdmNoiseImmunityLevel, 153 aniState->ofdmNoiseImmunityLevel,
273 immunityLevel, aniState->noiseFloor, 154 immunityLevel, BEACON_RSSI(ah),
274 aniState->rssiThrLow, aniState->rssiThrHigh); 155 aniState->rssiThrLow, aniState->rssiThrHigh);
275 156
276 if (aniState->update_ani) 157 if (!scan)
277 aniState->ofdmNoiseImmunityLevel = 158 aniState->ofdmNoiseImmunityLevel = immunityLevel;
278 (immunityLevel > ATH9K_ANI_OFDM_DEF_LEVEL) ?
279 immunityLevel : ATH9K_ANI_OFDM_DEF_LEVEL;
280 159
281 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel]; 160 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
282 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel]; 161 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
@@ -292,12 +171,22 @@ static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
292 ATH9K_ANI_FIRSTEP_LEVEL, 171 ATH9K_ANI_FIRSTEP_LEVEL,
293 entry_ofdm->fir_step_level); 172 entry_ofdm->fir_step_level);
294 173
295 if ((aniState->noiseFloor >= aniState->rssiThrHigh) && 174 weak_sig = entry_ofdm->ofdm_weak_signal_on;
296 (!aniState->ofdmWeakSigDetectOff != 175 if (ah->opmode == NL80211_IFTYPE_STATION &&
297 entry_ofdm->ofdm_weak_signal_on)) { 176 BEACON_RSSI(ah) <= aniState->rssiThrHigh)
177 weak_sig = true;
178
179 if (aniState->ofdmWeakSigDetect != weak_sig)
298 ath9k_hw_ani_control(ah, 180 ath9k_hw_ani_control(ah,
299 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, 181 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
300 entry_ofdm->ofdm_weak_signal_on); 182 entry_ofdm->ofdm_weak_signal_on);
183
184 if (aniState->ofdmNoiseImmunityLevel >= ATH9K_ANI_OFDM_DEF_LEVEL) {
185 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH;
186 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI;
187 } else {
188 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI;
189 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW;
301 } 190 }
302} 191}
303 192
@@ -308,43 +197,35 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
308 if (!DO_ANI(ah)) 197 if (!DO_ANI(ah))
309 return; 198 return;
310 199
311 if (!use_new_ani(ah)) {
312 ath9k_hw_ani_ofdm_err_trigger_old(ah);
313 return;
314 }
315
316 aniState = &ah->curchan->ani; 200 aniState = &ah->curchan->ani;
317 201
318 if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL) 202 if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL)
319 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1); 203 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1, false);
320} 204}
321 205
322/* 206/*
323 * Set the ANI settings to match an CCK level. 207 * Set the ANI settings to match an CCK level.
324 */ 208 */
325static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel) 209static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel,
210 bool scan)
326{ 211{
327 struct ar5416AniState *aniState = &ah->curchan->ani; 212 struct ar5416AniState *aniState = &ah->curchan->ani;
328 struct ath_common *common = ath9k_hw_common(ah); 213 struct ath_common *common = ath9k_hw_common(ah);
329 const struct ani_ofdm_level_entry *entry_ofdm; 214 const struct ani_ofdm_level_entry *entry_ofdm;
330 const struct ani_cck_level_entry *entry_cck; 215 const struct ani_cck_level_entry *entry_cck;
331 216
332 aniState->noiseFloor = BEACON_RSSI(ah);
333 ath_dbg(common, ANI, "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", 217 ath_dbg(common, ANI, "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
334 aniState->cckNoiseImmunityLevel, immunityLevel, 218 aniState->cckNoiseImmunityLevel, immunityLevel,
335 aniState->noiseFloor, aniState->rssiThrLow, 219 BEACON_RSSI(ah), aniState->rssiThrLow,
336 aniState->rssiThrHigh); 220 aniState->rssiThrHigh);
337 221
338 if ((ah->opmode == NL80211_IFTYPE_STATION || 222 if (ah->opmode == NL80211_IFTYPE_STATION &&
339 ah->opmode == NL80211_IFTYPE_ADHOC) && 223 BEACON_RSSI(ah) <= aniState->rssiThrLow &&
340 aniState->noiseFloor <= aniState->rssiThrLow &&
341 immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI) 224 immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI)
342 immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI; 225 immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI;
343 226
344 if (aniState->update_ani) 227 if (!scan)
345 aniState->cckNoiseImmunityLevel = 228 aniState->cckNoiseImmunityLevel = immunityLevel;
346 (immunityLevel > ATH9K_ANI_CCK_DEF_LEVEL) ?
347 immunityLevel : ATH9K_ANI_CCK_DEF_LEVEL;
348 229
349 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel]; 230 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
350 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel]; 231 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
@@ -359,7 +240,7 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
359 if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah)) 240 if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah))
360 return; 241 return;
361 242
362 if (aniState->mrcCCKOff == entry_cck->mrc_cck_on) 243 if (aniState->mrcCCK != entry_cck->mrc_cck_on)
363 ath9k_hw_ani_control(ah, 244 ath9k_hw_ani_control(ah,
364 ATH9K_ANI_MRC_CCK, 245 ATH9K_ANI_MRC_CCK,
365 entry_cck->mrc_cck_on); 246 entry_cck->mrc_cck_on);
@@ -372,68 +253,11 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
372 if (!DO_ANI(ah)) 253 if (!DO_ANI(ah))
373 return; 254 return;
374 255
375 if (!use_new_ani(ah)) {
376 ath9k_hw_ani_cck_err_trigger_old(ah);
377 return;
378 }
379
380 aniState = &ah->curchan->ani; 256 aniState = &ah->curchan->ani;
381 257
382 if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL) 258 if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL)
383 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1); 259 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1,
384} 260 false);
385
386static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah)
387{
388 struct ar5416AniState *aniState;
389 int32_t rssi;
390
391 aniState = &ah->curchan->ani;
392
393 if (ah->opmode == NL80211_IFTYPE_AP) {
394 if (aniState->firstepLevel > 0) {
395 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
396 aniState->firstepLevel - 1))
397 return;
398 }
399 } else {
400 rssi = BEACON_RSSI(ah);
401 if (rssi > aniState->rssiThrHigh) {
402 /* XXX: Handle me */
403 } else if (rssi > aniState->rssiThrLow) {
404 if (aniState->ofdmWeakSigDetectOff) {
405 if (ath9k_hw_ani_control(ah,
406 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
407 true))
408 return;
409 }
410 if (aniState->firstepLevel > 0) {
411 if (ath9k_hw_ani_control(ah,
412 ATH9K_ANI_FIRSTEP_LEVEL,
413 aniState->firstepLevel - 1))
414 return;
415 }
416 } else {
417 if (aniState->firstepLevel > 0) {
418 if (ath9k_hw_ani_control(ah,
419 ATH9K_ANI_FIRSTEP_LEVEL,
420 aniState->firstepLevel - 1))
421 return;
422 }
423 }
424 }
425
426 if (aniState->spurImmunityLevel > 0) {
427 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
428 aniState->spurImmunityLevel - 1))
429 return;
430 }
431
432 if (aniState->noiseImmunityLevel > 0) {
433 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
434 aniState->noiseImmunityLevel - 1);
435 return;
436 }
437} 261}
438 262
439/* 263/*
@@ -446,87 +270,18 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
446 270
447 aniState = &ah->curchan->ani; 271 aniState = &ah->curchan->ani;
448 272
449 if (!use_new_ani(ah)) {
450 ath9k_hw_ani_lower_immunity_old(ah);
451 return;
452 }
453
454 /* lower OFDM noise immunity */ 273 /* lower OFDM noise immunity */
455 if (aniState->ofdmNoiseImmunityLevel > 0 && 274 if (aniState->ofdmNoiseImmunityLevel > 0 &&
456 (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) { 275 (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) {
457 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1); 276 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1,
277 false);
458 return; 278 return;
459 } 279 }
460 280
461 /* lower CCK noise immunity */ 281 /* lower CCK noise immunity */
462 if (aniState->cckNoiseImmunityLevel > 0) 282 if (aniState->cckNoiseImmunityLevel > 0)
463 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1); 283 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1,
464} 284 false);
465
466static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
467{
468 struct ar5416AniState *aniState;
469 struct ath9k_channel *chan = ah->curchan;
470 struct ath_common *common = ath9k_hw_common(ah);
471
472 if (!DO_ANI(ah))
473 return;
474
475 aniState = &ah->curchan->ani;
476
477 if (ah->opmode != NL80211_IFTYPE_STATION
478 && ah->opmode != NL80211_IFTYPE_ADHOC) {
479 ath_dbg(common, ANI, "Reset ANI state opmode %u\n", ah->opmode);
480 ah->stats.ast_ani_reset++;
481
482 if (ah->opmode == NL80211_IFTYPE_AP) {
483 /*
484 * ath9k_hw_ani_control() will only process items set on
485 * ah->ani_function
486 */
487 if (IS_CHAN_2GHZ(chan))
488 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
489 ATH9K_ANI_FIRSTEP_LEVEL);
490 else
491 ah->ani_function = 0;
492 }
493
494 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
495 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
496 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
497 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
498 !ATH9K_ANI_USE_OFDM_WEAK_SIG);
499 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
500 ATH9K_ANI_CCK_WEAK_SIG_THR);
501
502 ath9k_ani_restart(ah);
503 return;
504 }
505
506 if (aniState->noiseImmunityLevel != 0)
507 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
508 aniState->noiseImmunityLevel);
509 if (aniState->spurImmunityLevel != 0)
510 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
511 aniState->spurImmunityLevel);
512 if (aniState->ofdmWeakSigDetectOff)
513 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
514 !aniState->ofdmWeakSigDetectOff);
515 if (aniState->cckWeakSigThreshold)
516 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
517 aniState->cckWeakSigThreshold);
518 if (aniState->firstepLevel != 0)
519 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
520 aniState->firstepLevel);
521
522 ath9k_ani_restart(ah);
523
524 ENABLE_REGWRITE_BUFFER(ah);
525
526 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
527 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
528
529 REGWRITE_BUFFER_FLUSH(ah);
530} 285}
531 286
532/* 287/*
@@ -539,13 +294,11 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
539 struct ar5416AniState *aniState = &ah->curchan->ani; 294 struct ar5416AniState *aniState = &ah->curchan->ani;
540 struct ath9k_channel *chan = ah->curchan; 295 struct ath9k_channel *chan = ah->curchan;
541 struct ath_common *common = ath9k_hw_common(ah); 296 struct ath_common *common = ath9k_hw_common(ah);
297 int ofdm_nil, cck_nil;
542 298
543 if (!DO_ANI(ah)) 299 if (!DO_ANI(ah))
544 return; 300 return;
545 301
546 if (!use_new_ani(ah))
547 return ath9k_ani_reset_old(ah, is_scanning);
548
549 BUG_ON(aniState == NULL); 302 BUG_ON(aniState == NULL);
550 ah->stats.ast_ani_reset++; 303 ah->stats.ast_ani_reset++;
551 304
@@ -563,6 +316,11 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
563 /* always allow mode (on/off) to be controlled */ 316 /* always allow mode (on/off) to be controlled */
564 ah->ani_function |= ATH9K_ANI_MODE; 317 ah->ani_function |= ATH9K_ANI_MODE;
565 318
319 ofdm_nil = max_t(int, ATH9K_ANI_OFDM_DEF_LEVEL,
320 aniState->ofdmNoiseImmunityLevel);
321 cck_nil = max_t(int, ATH9K_ANI_CCK_DEF_LEVEL,
322 aniState->cckNoiseImmunityLevel);
323
566 if (is_scanning || 324 if (is_scanning ||
567 (ah->opmode != NL80211_IFTYPE_STATION && 325 (ah->opmode != NL80211_IFTYPE_STATION &&
568 ah->opmode != NL80211_IFTYPE_ADHOC)) { 326 ah->opmode != NL80211_IFTYPE_ADHOC)) {
@@ -585,9 +343,8 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
585 aniState->ofdmNoiseImmunityLevel, 343 aniState->ofdmNoiseImmunityLevel,
586 aniState->cckNoiseImmunityLevel); 344 aniState->cckNoiseImmunityLevel);
587 345
588 aniState->update_ani = false; 346 ofdm_nil = ATH9K_ANI_OFDM_DEF_LEVEL;
589 ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL); 347 cck_nil = ATH9K_ANI_CCK_DEF_LEVEL;
590 ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL);
591 } 348 }
592 } else { 349 } else {
593 /* 350 /*
@@ -601,13 +358,9 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
601 is_scanning, 358 is_scanning,
602 aniState->ofdmNoiseImmunityLevel, 359 aniState->ofdmNoiseImmunityLevel,
603 aniState->cckNoiseImmunityLevel); 360 aniState->cckNoiseImmunityLevel);
604
605 aniState->update_ani = true;
606 ath9k_hw_set_ofdm_nil(ah,
607 aniState->ofdmNoiseImmunityLevel);
608 ath9k_hw_set_cck_nil(ah,
609 aniState->cckNoiseImmunityLevel);
610 } 361 }
362 ath9k_hw_set_ofdm_nil(ah, ofdm_nil, is_scanning);
363 ath9k_hw_set_cck_nil(ah, cck_nil, is_scanning);
611 364
612 /* 365 /*
613 * enable phy counters if hw supports or if not, enable phy 366 * enable phy counters if hw supports or if not, enable phy
@@ -627,9 +380,6 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
627{ 380{
628 struct ath_common *common = ath9k_hw_common(ah); 381 struct ath_common *common = ath9k_hw_common(ah);
629 struct ar5416AniState *aniState = &ah->curchan->ani; 382 struct ar5416AniState *aniState = &ah->curchan->ani;
630 u32 ofdm_base = 0;
631 u32 cck_base = 0;
632 u32 ofdmPhyErrCnt, cckPhyErrCnt;
633 u32 phyCnt1, phyCnt2; 383 u32 phyCnt1, phyCnt2;
634 int32_t listenTime; 384 int32_t listenTime;
635 385
@@ -642,11 +392,6 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
642 return false; 392 return false;
643 } 393 }
644 394
645 if (!use_new_ani(ah)) {
646 ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
647 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
648 }
649
650 aniState->listenTime += listenTime; 395 aniState->listenTime += listenTime;
651 396
652 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 397 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
@@ -654,35 +399,12 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
654 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); 399 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
655 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); 400 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
656 401
657 if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) { 402 ah->stats.ast_ani_ofdmerrs += phyCnt1 - aniState->ofdmPhyErrCount;
658 if (phyCnt1 < ofdm_base) { 403 aniState->ofdmPhyErrCount = phyCnt1;
659 ath_dbg(common, ANI,
660 "phyCnt1 0x%x, resetting counter value to 0x%x\n",
661 phyCnt1, ofdm_base);
662 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
663 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
664 AR_PHY_ERR_OFDM_TIMING);
665 }
666 if (phyCnt2 < cck_base) {
667 ath_dbg(common, ANI,
668 "phyCnt2 0x%x, resetting counter value to 0x%x\n",
669 phyCnt2, cck_base);
670 REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
671 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
672 AR_PHY_ERR_CCK_TIMING);
673 }
674 return false;
675 }
676 404
677 ofdmPhyErrCnt = phyCnt1 - ofdm_base; 405 ah->stats.ast_ani_cckerrs += phyCnt2 - aniState->cckPhyErrCount;
678 ah->stats.ast_ani_ofdmerrs += 406 aniState->cckPhyErrCount = phyCnt2;
679 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
680 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
681 407
682 cckPhyErrCnt = phyCnt2 - cck_base;
683 ah->stats.ast_ani_cckerrs +=
684 cckPhyErrCnt - aniState->cckPhyErrCount;
685 aniState->cckPhyErrCount = cckPhyErrCnt;
686 return true; 408 return true;
687} 409}
688 410
@@ -716,21 +438,10 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan)
716 438
717 if (aniState->listenTime > ah->aniperiod) { 439 if (aniState->listenTime > ah->aniperiod) {
718 if (cckPhyErrRate < ah->config.cck_trig_low && 440 if (cckPhyErrRate < ah->config.cck_trig_low &&
719 ((ofdmPhyErrRate < ah->config.ofdm_trig_low && 441 ofdmPhyErrRate < ah->config.ofdm_trig_low) {
720 aniState->ofdmNoiseImmunityLevel <
721 ATH9K_ANI_OFDM_DEF_LEVEL) ||
722 (ofdmPhyErrRate < ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI &&
723 aniState->ofdmNoiseImmunityLevel >=
724 ATH9K_ANI_OFDM_DEF_LEVEL))) {
725 ath9k_hw_ani_lower_immunity(ah); 442 ath9k_hw_ani_lower_immunity(ah);
726 aniState->ofdmsTurn = !aniState->ofdmsTurn; 443 aniState->ofdmsTurn = !aniState->ofdmsTurn;
727 } else if ((ofdmPhyErrRate > ah->config.ofdm_trig_high && 444 } else if (ofdmPhyErrRate > ah->config.ofdm_trig_high) {
728 aniState->ofdmNoiseImmunityLevel >=
729 ATH9K_ANI_OFDM_DEF_LEVEL) ||
730 (ofdmPhyErrRate >
731 ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI &&
732 aniState->ofdmNoiseImmunityLevel <
733 ATH9K_ANI_OFDM_DEF_LEVEL)) {
734 ath9k_hw_ani_ofdm_err_trigger(ah); 445 ath9k_hw_ani_ofdm_err_trigger(ah);
735 aniState->ofdmsTurn = false; 446 aniState->ofdmsTurn = false;
736 } else if (cckPhyErrRate > ah->config.cck_trig_high) { 447 } else if (cckPhyErrRate > ah->config.cck_trig_high) {
@@ -778,49 +489,6 @@ void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
778} 489}
779EXPORT_SYMBOL(ath9k_hw_disable_mib_counters); 490EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
780 491
781/*
782 * Process a MIB interrupt. We may potentially be invoked because
783 * any of the MIB counters overflow/trigger so don't assume we're
784 * here because a PHY error counter triggered.
785 */
786void ath9k_hw_proc_mib_event(struct ath_hw *ah)
787{
788 u32 phyCnt1, phyCnt2;
789
790 /* Reset these counters regardless */
791 REG_WRITE(ah, AR_FILT_OFDM, 0);
792 REG_WRITE(ah, AR_FILT_CCK, 0);
793 if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
794 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
795
796 /* Clear the mib counters and save them in the stats */
797 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
798
799 if (!DO_ANI(ah)) {
800 /*
801 * We must always clear the interrupt cause by
802 * resetting the phy error regs.
803 */
804 REG_WRITE(ah, AR_PHY_ERR_1, 0);
805 REG_WRITE(ah, AR_PHY_ERR_2, 0);
806 return;
807 }
808
809 /* NB: these are not reset-on-read */
810 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
811 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
812 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
813 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
814
815 if (!use_new_ani(ah))
816 ath9k_hw_ani_read_counters(ah);
817
818 /* NB: always restart to insure the h/w counters are reset */
819 ath9k_ani_restart(ah);
820 }
821}
822EXPORT_SYMBOL(ath9k_hw_proc_mib_event);
823
824void ath9k_hw_ani_setup(struct ath_hw *ah) 492void ath9k_hw_ani_setup(struct ath_hw *ah)
825{ 493{
826 int i; 494 int i;
@@ -845,66 +513,37 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
845 513
846 ath_dbg(common, ANI, "Initialize ANI\n"); 514 ath_dbg(common, ANI, "Initialize ANI\n");
847 515
848 if (use_new_ani(ah)) { 516 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH;
849 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW; 517 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW;
850 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_NEW;
851 518
852 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_NEW; 519 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH;
853 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_NEW; 520 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW;
854 } else {
855 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
856 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_OLD;
857
858 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_OLD;
859 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_OLD;
860 }
861 521
862 for (i = 0; i < ARRAY_SIZE(ah->channels); i++) { 522 for (i = 0; i < ARRAY_SIZE(ah->channels); i++) {
863 struct ath9k_channel *chan = &ah->channels[i]; 523 struct ath9k_channel *chan = &ah->channels[i];
864 struct ar5416AniState *ani = &chan->ani; 524 struct ar5416AniState *ani = &chan->ani;
865 525
866 if (use_new_ani(ah)) { 526 ani->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
867 ani->spurImmunityLevel =
868 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
869 527
870 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW; 528 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
871 529
872 if (AR_SREV_9300_20_OR_LATER(ah)) 530 ani->mrcCCK = AR_SREV_9300_20_OR_LATER(ah) ? true : false;
873 ani->mrcCCKOff = 531
874 !ATH9K_ANI_ENABLE_MRC_CCK; 532 ani->ofdmsTurn = true;
875 else
876 ani->mrcCCKOff = true;
877
878 ani->ofdmsTurn = true;
879 } else {
880 ani->spurImmunityLevel =
881 ATH9K_ANI_SPUR_IMMUNE_LVL_OLD;
882 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_OLD;
883
884 ani->cckWeakSigThreshold =
885 ATH9K_ANI_CCK_WEAK_SIG_THR;
886 }
887 533
888 ani->rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; 534 ani->rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
889 ani->rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; 535 ani->rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
890 ani->ofdmWeakSigDetectOff = 536 ani->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
891 !ATH9K_ANI_USE_OFDM_WEAK_SIG;
892 ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL; 537 ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
893 ani->ofdmNoiseImmunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL; 538 ani->ofdmNoiseImmunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL;
894 ani->update_ani = false;
895 } 539 }
896 540
897 /* 541 /*
898 * since we expect some ongoing maintenance on the tables, let's sanity 542 * since we expect some ongoing maintenance on the tables, let's sanity
899 * check here default level should not modify INI setting. 543 * check here default level should not modify INI setting.
900 */ 544 */
901 if (use_new_ani(ah)) { 545 ah->aniperiod = ATH9K_ANI_PERIOD;
902 ah->aniperiod = ATH9K_ANI_PERIOD_NEW; 546 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL;
903 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_NEW;
904 } else {
905 ah->aniperiod = ATH9K_ANI_PERIOD_OLD;
906 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_OLD;
907 }
908 547
909 if (ah->config.enable_ani) 548 if (ah->config.enable_ani)
910 ah->proc_phyerr |= HAL_PROCESS_ANI; 549 ah->proc_phyerr |= HAL_PROCESS_ANI;
diff --git a/drivers/net/wireless/ath/ath9k/ani.h b/drivers/net/wireless/ath/ath9k/ani.h
index 72e2b874e179..1485bf5e3518 100644
--- a/drivers/net/wireless/ath/ath9k/ani.h
+++ b/drivers/net/wireless/ath/ath9k/ani.h
@@ -24,42 +24,34 @@
24#define BEACON_RSSI(ahp) (ahp->stats.avgbrssi) 24#define BEACON_RSSI(ahp) (ahp->stats.avgbrssi)
25 25
26/* units are errors per second */ 26/* units are errors per second */
27#define ATH9K_ANI_OFDM_TRIG_HIGH_OLD 500 27#define ATH9K_ANI_OFDM_TRIG_HIGH 3500
28#define ATH9K_ANI_OFDM_TRIG_HIGH_NEW 3500
29#define ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI 1000 28#define ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI 1000
30 29
31/* units are errors per second */ 30/* units are errors per second */
32#define ATH9K_ANI_OFDM_TRIG_LOW_OLD 200 31#define ATH9K_ANI_OFDM_TRIG_LOW 400
33#define ATH9K_ANI_OFDM_TRIG_LOW_NEW 400
34#define ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI 900 32#define ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI 900
35 33
36/* units are errors per second */ 34/* units are errors per second */
37#define ATH9K_ANI_CCK_TRIG_HIGH_OLD 200 35#define ATH9K_ANI_CCK_TRIG_HIGH 600
38#define ATH9K_ANI_CCK_TRIG_HIGH_NEW 600
39 36
40/* units are errors per second */ 37/* units are errors per second */
41#define ATH9K_ANI_CCK_TRIG_LOW_OLD 100 38#define ATH9K_ANI_CCK_TRIG_LOW 300
42#define ATH9K_ANI_CCK_TRIG_LOW_NEW 300
43 39
44#define ATH9K_ANI_NOISE_IMMUNE_LVL 4 40#define ATH9K_ANI_NOISE_IMMUNE_LVL 4
45#define ATH9K_ANI_USE_OFDM_WEAK_SIG true 41#define ATH9K_ANI_USE_OFDM_WEAK_SIG true
46#define ATH9K_ANI_CCK_WEAK_SIG_THR false 42#define ATH9K_ANI_CCK_WEAK_SIG_THR false
47 43
48#define ATH9K_ANI_SPUR_IMMUNE_LVL_OLD 7 44#define ATH9K_ANI_SPUR_IMMUNE_LVL 3
49#define ATH9K_ANI_SPUR_IMMUNE_LVL_NEW 3
50 45
51#define ATH9K_ANI_FIRSTEP_LVL_OLD 0 46#define ATH9K_ANI_FIRSTEP_LVL 2
52#define ATH9K_ANI_FIRSTEP_LVL_NEW 2
53 47
54#define ATH9K_ANI_RSSI_THR_HIGH 40 48#define ATH9K_ANI_RSSI_THR_HIGH 40
55#define ATH9K_ANI_RSSI_THR_LOW 7 49#define ATH9K_ANI_RSSI_THR_LOW 7
56 50
57#define ATH9K_ANI_PERIOD_OLD 100 51#define ATH9K_ANI_PERIOD 300
58#define ATH9K_ANI_PERIOD_NEW 300
59 52
60/* in ms */ 53/* in ms */
61#define ATH9K_ANI_POLLINTERVAL_OLD 100 54#define ATH9K_ANI_POLLINTERVAL 1000
62#define ATH9K_ANI_POLLINTERVAL_NEW 1000
63 55
64#define HAL_NOISE_IMMUNE_MAX 4 56#define HAL_NOISE_IMMUNE_MAX 4
65#define HAL_SPUR_IMMUNE_MAX 7 57#define HAL_SPUR_IMMUNE_MAX 7
@@ -70,8 +62,6 @@
70#define ATH9K_SIG_SPUR_IMM_SETTING_MIN 0 62#define ATH9K_SIG_SPUR_IMM_SETTING_MIN 0
71#define ATH9K_SIG_SPUR_IMM_SETTING_MAX 22 63#define ATH9K_SIG_SPUR_IMM_SETTING_MAX 22
72 64
73#define ATH9K_ANI_ENABLE_MRC_CCK true
74
75/* values here are relative to the INI */ 65/* values here are relative to the INI */
76 66
77enum ath9k_ani_cmd { 67enum ath9k_ani_cmd {
@@ -119,16 +109,14 @@ struct ar5416AniState {
119 u8 ofdmNoiseImmunityLevel; 109 u8 ofdmNoiseImmunityLevel;
120 u8 cckNoiseImmunityLevel; 110 u8 cckNoiseImmunityLevel;
121 bool ofdmsTurn; 111 bool ofdmsTurn;
122 u8 mrcCCKOff; 112 u8 mrcCCK;
123 u8 spurImmunityLevel; 113 u8 spurImmunityLevel;
124 u8 firstepLevel; 114 u8 firstepLevel;
125 u8 ofdmWeakSigDetectOff; 115 u8 ofdmWeakSigDetect;
126 u8 cckWeakSigThreshold; 116 u8 cckWeakSigThreshold;
127 bool update_ani;
128 u32 listenTime; 117 u32 listenTime;
129 int32_t rssiThrLow; 118 int32_t rssiThrLow;
130 int32_t rssiThrHigh; 119 int32_t rssiThrHigh;
131 u32 noiseFloor;
132 u32 ofdmPhyErrCount; 120 u32 ofdmPhyErrCount;
133 u32 cckPhyErrCount; 121 u32 cckPhyErrCount;
134 int16_t pktRssi[2]; 122 int16_t pktRssi[2];
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
index c7492c6a2519..874186bfda41 100644
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -995,141 +995,6 @@ static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
995 return pll; 995 return pll;
996} 996}
997 997
998static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
999 enum ath9k_ani_cmd cmd,
1000 int param)
1001{
1002 struct ar5416AniState *aniState = &ah->curchan->ani;
1003 struct ath_common *common = ath9k_hw_common(ah);
1004
1005 switch (cmd & ah->ani_function) {
1006 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
1007 u32 level = param;
1008
1009 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
1010 ath_dbg(common, ANI, "level out of range (%u > %zu)\n",
1011 level, ARRAY_SIZE(ah->totalSizeDesired));
1012 return false;
1013 }
1014
1015 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1016 AR_PHY_DESIRED_SZ_TOT_DES,
1017 ah->totalSizeDesired[level]);
1018 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1019 AR_PHY_AGC_CTL1_COARSE_LOW,
1020 ah->coarse_low[level]);
1021 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1022 AR_PHY_AGC_CTL1_COARSE_HIGH,
1023 ah->coarse_high[level]);
1024 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1025 AR_PHY_FIND_SIG_FIRPWR,
1026 ah->firpwr[level]);
1027
1028 if (level > aniState->noiseImmunityLevel)
1029 ah->stats.ast_ani_niup++;
1030 else if (level < aniState->noiseImmunityLevel)
1031 ah->stats.ast_ani_nidown++;
1032 aniState->noiseImmunityLevel = level;
1033 break;
1034 }
1035 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1036 u32 on = param ? 1 : 0;
1037
1038 if (on)
1039 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1040 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1041 else
1042 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1043 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1044
1045 if (!on != aniState->ofdmWeakSigDetectOff) {
1046 if (on)
1047 ah->stats.ast_ani_ofdmon++;
1048 else
1049 ah->stats.ast_ani_ofdmoff++;
1050 aniState->ofdmWeakSigDetectOff = !on;
1051 }
1052 break;
1053 }
1054 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
1055 static const int weakSigThrCck[] = { 8, 6 };
1056 u32 high = param ? 1 : 0;
1057
1058 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
1059 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
1060 weakSigThrCck[high]);
1061 if (high != aniState->cckWeakSigThreshold) {
1062 if (high)
1063 ah->stats.ast_ani_cckhigh++;
1064 else
1065 ah->stats.ast_ani_ccklow++;
1066 aniState->cckWeakSigThreshold = high;
1067 }
1068 break;
1069 }
1070 case ATH9K_ANI_FIRSTEP_LEVEL:{
1071 static const int firstep[] = { 0, 4, 8 };
1072 u32 level = param;
1073
1074 if (level >= ARRAY_SIZE(firstep)) {
1075 ath_dbg(common, ANI, "level out of range (%u > %zu)\n",
1076 level, ARRAY_SIZE(firstep));
1077 return false;
1078 }
1079 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1080 AR_PHY_FIND_SIG_FIRSTEP,
1081 firstep[level]);
1082 if (level > aniState->firstepLevel)
1083 ah->stats.ast_ani_stepup++;
1084 else if (level < aniState->firstepLevel)
1085 ah->stats.ast_ani_stepdown++;
1086 aniState->firstepLevel = level;
1087 break;
1088 }
1089 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1090 static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
1091 u32 level = param;
1092
1093 if (level >= ARRAY_SIZE(cycpwrThr1)) {
1094 ath_dbg(common, ANI, "level out of range (%u > %zu)\n",
1095 level, ARRAY_SIZE(cycpwrThr1));
1096 return false;
1097 }
1098 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1099 AR_PHY_TIMING5_CYCPWR_THR1,
1100 cycpwrThr1[level]);
1101 if (level > aniState->spurImmunityLevel)
1102 ah->stats.ast_ani_spurup++;
1103 else if (level < aniState->spurImmunityLevel)
1104 ah->stats.ast_ani_spurdown++;
1105 aniState->spurImmunityLevel = level;
1106 break;
1107 }
1108 case ATH9K_ANI_PRESENT:
1109 break;
1110 default:
1111 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1112 return false;
1113 }
1114
1115 ath_dbg(common, ANI, "ANI parameters:\n");
1116 ath_dbg(common, ANI,
1117 "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n",
1118 aniState->noiseImmunityLevel,
1119 aniState->spurImmunityLevel,
1120 !aniState->ofdmWeakSigDetectOff);
1121 ath_dbg(common, ANI,
1122 "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
1123 aniState->cckWeakSigThreshold,
1124 aniState->firstepLevel,
1125 aniState->listenTime);
1126 ath_dbg(common, ANI, "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
1127 aniState->ofdmPhyErrCount,
1128 aniState->cckPhyErrCount);
1129
1130 return true;
1131}
1132
1133static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 998static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1134 enum ath9k_ani_cmd cmd, 999 enum ath9k_ani_cmd cmd,
1135 int param) 1000 int param)
@@ -1206,18 +1071,18 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1206 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 1071 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1207 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1072 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1208 1073
1209 if (!on != aniState->ofdmWeakSigDetectOff) { 1074 if (on != aniState->ofdmWeakSigDetect) {
1210 ath_dbg(common, ANI, 1075 ath_dbg(common, ANI,
1211 "** ch %d: ofdm weak signal: %s=>%s\n", 1076 "** ch %d: ofdm weak signal: %s=>%s\n",
1212 chan->channel, 1077 chan->channel,
1213 !aniState->ofdmWeakSigDetectOff ? 1078 aniState->ofdmWeakSigDetect ?
1214 "on" : "off", 1079 "on" : "off",
1215 on ? "on" : "off"); 1080 on ? "on" : "off");
1216 if (on) 1081 if (on)
1217 ah->stats.ast_ani_ofdmon++; 1082 ah->stats.ast_ani_ofdmon++;
1218 else 1083 else
1219 ah->stats.ast_ani_ofdmoff++; 1084 ah->stats.ast_ani_ofdmoff++;
1220 aniState->ofdmWeakSigDetectOff = !on; 1085 aniState->ofdmWeakSigDetect = on;
1221 } 1086 }
1222 break; 1087 break;
1223 } 1088 }
@@ -1236,7 +1101,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1236 * from INI file & cap value 1101 * from INI file & cap value
1237 */ 1102 */
1238 value = firstep_table[level] - 1103 value = firstep_table[level] -
1239 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 1104 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1240 aniState->iniDef.firstep; 1105 aniState->iniDef.firstep;
1241 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) 1106 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1242 value = ATH9K_SIG_FIRSTEP_SETTING_MIN; 1107 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
@@ -1251,7 +1116,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1251 * from INI file & cap value 1116 * from INI file & cap value
1252 */ 1117 */
1253 value2 = firstep_table[level] - 1118 value2 = firstep_table[level] -
1254 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 1119 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1255 aniState->iniDef.firstepLow; 1120 aniState->iniDef.firstepLow;
1256 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) 1121 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1257 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; 1122 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
@@ -1267,7 +1132,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1267 chan->channel, 1132 chan->channel,
1268 aniState->firstepLevel, 1133 aniState->firstepLevel,
1269 level, 1134 level,
1270 ATH9K_ANI_FIRSTEP_LVL_NEW, 1135 ATH9K_ANI_FIRSTEP_LVL,
1271 value, 1136 value,
1272 aniState->iniDef.firstep); 1137 aniState->iniDef.firstep);
1273 ath_dbg(common, ANI, 1138 ath_dbg(common, ANI,
@@ -1275,7 +1140,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1275 chan->channel, 1140 chan->channel,
1276 aniState->firstepLevel, 1141 aniState->firstepLevel,
1277 level, 1142 level,
1278 ATH9K_ANI_FIRSTEP_LVL_NEW, 1143 ATH9K_ANI_FIRSTEP_LVL,
1279 value2, 1144 value2,
1280 aniState->iniDef.firstepLow); 1145 aniState->iniDef.firstepLow);
1281 if (level > aniState->firstepLevel) 1146 if (level > aniState->firstepLevel)
@@ -1300,7 +1165,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1300 * from INI file & cap value 1165 * from INI file & cap value
1301 */ 1166 */
1302 value = cycpwrThr1_table[level] - 1167 value = cycpwrThr1_table[level] -
1303 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 1168 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1304 aniState->iniDef.cycpwrThr1; 1169 aniState->iniDef.cycpwrThr1;
1305 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1170 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1306 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1171 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
@@ -1316,7 +1181,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1316 * from INI file & cap value 1181 * from INI file & cap value
1317 */ 1182 */
1318 value2 = cycpwrThr1_table[level] - 1183 value2 = cycpwrThr1_table[level] -
1319 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 1184 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1320 aniState->iniDef.cycpwrThr1Ext; 1185 aniState->iniDef.cycpwrThr1Ext;
1321 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1186 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1322 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1187 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
@@ -1331,7 +1196,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1331 chan->channel, 1196 chan->channel,
1332 aniState->spurImmunityLevel, 1197 aniState->spurImmunityLevel,
1333 level, 1198 level,
1334 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1199 ATH9K_ANI_SPUR_IMMUNE_LVL,
1335 value, 1200 value,
1336 aniState->iniDef.cycpwrThr1); 1201 aniState->iniDef.cycpwrThr1);
1337 ath_dbg(common, ANI, 1202 ath_dbg(common, ANI,
@@ -1339,7 +1204,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1339 chan->channel, 1204 chan->channel,
1340 aniState->spurImmunityLevel, 1205 aniState->spurImmunityLevel,
1341 level, 1206 level,
1342 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1207 ATH9K_ANI_SPUR_IMMUNE_LVL,
1343 value2, 1208 value2,
1344 aniState->iniDef.cycpwrThr1Ext); 1209 aniState->iniDef.cycpwrThr1Ext);
1345 if (level > aniState->spurImmunityLevel) 1210 if (level > aniState->spurImmunityLevel)
@@ -1367,9 +1232,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1367 ath_dbg(common, ANI, 1232 ath_dbg(common, ANI,
1368 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1233 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1369 aniState->spurImmunityLevel, 1234 aniState->spurImmunityLevel,
1370 !aniState->ofdmWeakSigDetectOff ? "on" : "off", 1235 aniState->ofdmWeakSigDetect ? "on" : "off",
1371 aniState->firstepLevel, 1236 aniState->firstepLevel,
1372 !aniState->mrcCCKOff ? "on" : "off", 1237 aniState->mrcCCK ? "on" : "off",
1373 aniState->listenTime, 1238 aniState->listenTime,
1374 aniState->ofdmPhyErrCount, 1239 aniState->ofdmPhyErrCount,
1375 aniState->cckPhyErrCount); 1240 aniState->cckPhyErrCount);
@@ -1454,10 +1319,10 @@ static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1454 AR_PHY_EXT_TIMING5_CYCPWR_THR1); 1319 AR_PHY_EXT_TIMING5_CYCPWR_THR1);
1455 1320
1456 /* these levels just got reset to defaults by the INI */ 1321 /* these levels just got reset to defaults by the INI */
1457 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW; 1322 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1458 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW; 1323 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1459 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG; 1324 aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
1460 aniState->mrcCCKOff = true; /* not available on pre AR9003 */ 1325 aniState->mrcCCK = false; /* not available on pre AR9003 */
1461} 1326}
1462 1327
1463static void ar5008_hw_set_nf_limits(struct ath_hw *ah) 1328static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
@@ -1545,11 +1410,8 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1545 priv_ops->do_getnf = ar5008_hw_do_getnf; 1410 priv_ops->do_getnf = ar5008_hw_do_getnf;
1546 priv_ops->set_radar_params = ar5008_hw_set_radar_params; 1411 priv_ops->set_radar_params = ar5008_hw_set_radar_params;
1547 1412
1548 if (modparam_force_new_ani) { 1413 priv_ops->ani_control = ar5008_hw_ani_control_new;
1549 priv_ops->ani_control = ar5008_hw_ani_control_new; 1414 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
1550 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
1551 } else
1552 priv_ops->ani_control = ar5008_hw_ani_control_old;
1553 1415
1554 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 1416 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
1555 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control; 1417 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index d9a69fc470cd..edf21ea4fe93 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -21,10 +21,6 @@
21#include "ar9002_initvals.h" 21#include "ar9002_initvals.h"
22#include "ar9002_phy.h" 22#include "ar9002_phy.h"
23 23
24int modparam_force_new_ani;
25module_param_named(force_new_ani, modparam_force_new_ani, int, 0444);
26MODULE_PARM_DESC(force_new_ani, "Force new ANI for AR5008, AR9001, AR9002");
27
28/* General hardware code for the A5008/AR9001/AR9002 hadware families */ 24/* General hardware code for the A5008/AR9001/AR9002 hadware families */
29 25
30static void ar9002_hw_init_mode_regs(struct ath_hw *ah) 26static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
index 952cb2b4656b..89bf94d4d8a1 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2010-2011 Atheros Communications Inc. 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
3 * 4 *
4 * Permission to use, copy, modify, and/or distribute this software for any 5 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 6 * purpose with or without fee is hereby granted, provided that the above
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mci.c b/drivers/net/wireless/ath/ath9k/ar9003_mci.c
index cc2853ade8f8..61558375bfbf 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mci.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mci.c
@@ -767,10 +767,6 @@ static void ar9003_mci_mute_bt(struct ath_hw *ah)
767{ 767{
768 /* disable all MCI messages */ 768 /* disable all MCI messages */
769 REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xffff0000); 769 REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xffff0000);
770 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, 0xffffffff);
771 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, 0xffffffff);
772 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, 0xffffffff);
773 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, 0xffffffff);
774 REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); 770 REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
775 771
776 /* wait pending HW messages to flush out */ 772 /* wait pending HW messages to flush out */
@@ -1019,9 +1015,14 @@ void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool force)
1019 return; 1015 return;
1020 1016
1021 if (mci->is_2g) { 1017 if (mci->is_2g) {
1022 ar9003_mci_send_2g5g_status(ah, true); 1018 if (!force) {
1019 ar9003_mci_send_2g5g_status(ah, true);
1023 1020
1024 REG_SET_BIT(ah, AR_MCI_TX_CTRL, 1021 ar9003_mci_send_lna_transfer(ah, true);
1022 udelay(5);
1023 }
1024
1025 REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
1025 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); 1026 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
1026 REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL, 1027 REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL,
1027 AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); 1028 AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
@@ -1029,6 +1030,11 @@ void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool force)
1029 if (!(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA)) 1030 if (!(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA))
1030 ar9003_mci_osla_setup(ah, true); 1031 ar9003_mci_osla_setup(ah, true);
1031 } else { 1032 } else {
1033 if (!force) {
1034 ar9003_mci_send_lna_take(ah, true);
1035 udelay(5);
1036 }
1037
1032 REG_SET_BIT(ah, AR_MCI_TX_CTRL, 1038 REG_SET_BIT(ah, AR_MCI_TX_CTRL,
1033 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); 1039 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
1034 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, 1040 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
@@ -1255,6 +1261,9 @@ void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah)
1255 1261
1256 ath_dbg(common, MCI, "Give LNA and SPDT control to BT\n"); 1262 ath_dbg(common, MCI, "Give LNA and SPDT control to BT\n");
1257 1263
1264 ar9003_mci_send_lna_take(ah, true);
1265 udelay(50);
1266
1258 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); 1267 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
1259 mci->is_2g = false; 1268 mci->is_2g = false;
1260 mci->update_2g5g = true; 1269 mci->update_2g5g = true;
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index d6baf69cdc14..6b91ebb158fe 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -173,7 +173,7 @@ static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
173 int cur_bb_spur, negative = 0, cck_spur_freq; 173 int cur_bb_spur, negative = 0, cck_spur_freq;
174 int i; 174 int i;
175 int range, max_spur_cnts, synth_freq; 175 int range, max_spur_cnts, synth_freq;
176 u8 *spur_fbin_ptr = NULL; 176 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
177 177
178 /* 178 /*
179 * Need to verify range +/- 10 MHz in control channel, otherwise spur 179 * Need to verify range +/- 10 MHz in control channel, otherwise spur
@@ -181,8 +181,6 @@ static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
181 */ 181 */
182 182
183 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) { 183 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) {
184 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
185 IS_CHAN_2GHZ(chan));
186 if (spur_fbin_ptr[0] == 0) /* No spur */ 184 if (spur_fbin_ptr[0] == 0) /* No spur */
187 return; 185 return;
188 max_spur_cnts = 5; 186 max_spur_cnts = 5;
@@ -825,18 +823,18 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
825 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 823 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
826 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 824 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
827 825
828 if (!on != aniState->ofdmWeakSigDetectOff) { 826 if (on != aniState->ofdmWeakSigDetect) {
829 ath_dbg(common, ANI, 827 ath_dbg(common, ANI,
830 "** ch %d: ofdm weak signal: %s=>%s\n", 828 "** ch %d: ofdm weak signal: %s=>%s\n",
831 chan->channel, 829 chan->channel,
832 !aniState->ofdmWeakSigDetectOff ? 830 aniState->ofdmWeakSigDetect ?
833 "on" : "off", 831 "on" : "off",
834 on ? "on" : "off"); 832 on ? "on" : "off");
835 if (on) 833 if (on)
836 ah->stats.ast_ani_ofdmon++; 834 ah->stats.ast_ani_ofdmon++;
837 else 835 else
838 ah->stats.ast_ani_ofdmoff++; 836 ah->stats.ast_ani_ofdmoff++;
839 aniState->ofdmWeakSigDetectOff = !on; 837 aniState->ofdmWeakSigDetect = on;
840 } 838 }
841 break; 839 break;
842 } 840 }
@@ -855,7 +853,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
855 * from INI file & cap value 853 * from INI file & cap value
856 */ 854 */
857 value = firstep_table[level] - 855 value = firstep_table[level] -
858 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 856 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
859 aniState->iniDef.firstep; 857 aniState->iniDef.firstep;
860 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) 858 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
861 value = ATH9K_SIG_FIRSTEP_SETTING_MIN; 859 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
@@ -870,7 +868,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
870 * from INI file & cap value 868 * from INI file & cap value
871 */ 869 */
872 value2 = firstep_table[level] - 870 value2 = firstep_table[level] -
873 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 871 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
874 aniState->iniDef.firstepLow; 872 aniState->iniDef.firstepLow;
875 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) 873 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
876 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; 874 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
@@ -886,7 +884,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
886 chan->channel, 884 chan->channel,
887 aniState->firstepLevel, 885 aniState->firstepLevel,
888 level, 886 level,
889 ATH9K_ANI_FIRSTEP_LVL_NEW, 887 ATH9K_ANI_FIRSTEP_LVL,
890 value, 888 value,
891 aniState->iniDef.firstep); 889 aniState->iniDef.firstep);
892 ath_dbg(common, ANI, 890 ath_dbg(common, ANI,
@@ -894,7 +892,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
894 chan->channel, 892 chan->channel,
895 aniState->firstepLevel, 893 aniState->firstepLevel,
896 level, 894 level,
897 ATH9K_ANI_FIRSTEP_LVL_NEW, 895 ATH9K_ANI_FIRSTEP_LVL,
898 value2, 896 value2,
899 aniState->iniDef.firstepLow); 897 aniState->iniDef.firstepLow);
900 if (level > aniState->firstepLevel) 898 if (level > aniState->firstepLevel)
@@ -919,7 +917,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
919 * from INI file & cap value 917 * from INI file & cap value
920 */ 918 */
921 value = cycpwrThr1_table[level] - 919 value = cycpwrThr1_table[level] -
922 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 920 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
923 aniState->iniDef.cycpwrThr1; 921 aniState->iniDef.cycpwrThr1;
924 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 922 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
925 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 923 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
@@ -935,7 +933,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
935 * from INI file & cap value 933 * from INI file & cap value
936 */ 934 */
937 value2 = cycpwrThr1_table[level] - 935 value2 = cycpwrThr1_table[level] -
938 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 936 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
939 aniState->iniDef.cycpwrThr1Ext; 937 aniState->iniDef.cycpwrThr1Ext;
940 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 938 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
941 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 939 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
@@ -950,7 +948,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
950 chan->channel, 948 chan->channel,
951 aniState->spurImmunityLevel, 949 aniState->spurImmunityLevel,
952 level, 950 level,
953 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 951 ATH9K_ANI_SPUR_IMMUNE_LVL,
954 value, 952 value,
955 aniState->iniDef.cycpwrThr1); 953 aniState->iniDef.cycpwrThr1);
956 ath_dbg(common, ANI, 954 ath_dbg(common, ANI,
@@ -958,7 +956,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
958 chan->channel, 956 chan->channel,
959 aniState->spurImmunityLevel, 957 aniState->spurImmunityLevel,
960 level, 958 level,
961 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 959 ATH9K_ANI_SPUR_IMMUNE_LVL,
962 value2, 960 value2,
963 aniState->iniDef.cycpwrThr1Ext); 961 aniState->iniDef.cycpwrThr1Ext);
964 if (level > aniState->spurImmunityLevel) 962 if (level > aniState->spurImmunityLevel)
@@ -979,16 +977,16 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
979 AR_PHY_MRC_CCK_ENABLE, is_on); 977 AR_PHY_MRC_CCK_ENABLE, is_on);
980 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, 978 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
981 AR_PHY_MRC_CCK_MUX_REG, is_on); 979 AR_PHY_MRC_CCK_MUX_REG, is_on);
982 if (!is_on != aniState->mrcCCKOff) { 980 if (is_on != aniState->mrcCCK) {
983 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n", 981 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
984 chan->channel, 982 chan->channel,
985 !aniState->mrcCCKOff ? "on" : "off", 983 aniState->mrcCCK ? "on" : "off",
986 is_on ? "on" : "off"); 984 is_on ? "on" : "off");
987 if (is_on) 985 if (is_on)
988 ah->stats.ast_ani_ccklow++; 986 ah->stats.ast_ani_ccklow++;
989 else 987 else
990 ah->stats.ast_ani_cckhigh++; 988 ah->stats.ast_ani_cckhigh++;
991 aniState->mrcCCKOff = !is_on; 989 aniState->mrcCCK = is_on;
992 } 990 }
993 break; 991 break;
994 } 992 }
@@ -1002,9 +1000,9 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
1002 ath_dbg(common, ANI, 1000 ath_dbg(common, ANI,
1003 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1001 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1004 aniState->spurImmunityLevel, 1002 aniState->spurImmunityLevel,
1005 !aniState->ofdmWeakSigDetectOff ? "on" : "off", 1003 aniState->ofdmWeakSigDetect ? "on" : "off",
1006 aniState->firstepLevel, 1004 aniState->firstepLevel,
1007 !aniState->mrcCCKOff ? "on" : "off", 1005 aniState->mrcCCK ? "on" : "off",
1008 aniState->listenTime, 1006 aniState->listenTime,
1009 aniState->ofdmPhyErrCount, 1007 aniState->ofdmPhyErrCount,
1010 aniState->cckPhyErrCount); 1008 aniState->cckPhyErrCount);
@@ -1111,10 +1109,10 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1111 AR_PHY_EXT_CYCPWR_THR1); 1109 AR_PHY_EXT_CYCPWR_THR1);
1112 1110
1113 /* these levels just got reset to defaults by the INI */ 1111 /* these levels just got reset to defaults by the INI */
1114 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW; 1112 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1115 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW; 1113 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1116 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG; 1114 aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
1117 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK; 1115 aniState->mrcCCK = true;
1118} 1116}
1119 1117
1120static void ar9003_hw_set_radar_params(struct ath_hw *ah, 1118static void ar9003_hw_set_radar_params(struct ath_hw *ah,
diff --git a/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h b/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
index 1bd3a3d22101..6e1756bc3833 100644
--- a/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
@@ -337,12 +337,7 @@ static const u32 ar9331_modes_low_ob_db_tx_gain_1p1[][5] = {
337 {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000}, 337 {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
338}; 338};
339 339
340static const u32 ar9331_1p1_baseband_core_txfir_coeff_japan_2484[][2] = { 340#define ar9331_1p1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
341 /* Addr allmodes */
342 {0x0000a398, 0x00000000},
343 {0x0000a39c, 0x6f7f0301},
344 {0x0000a3a0, 0xca9228ee},
345};
346 341
347static const u32 ar9331_1p1_xtal_25M[][2] = { 342static const u32 ar9331_1p1_xtal_25M[][2] = {
348 /* Addr allmodes */ 343 /* Addr allmodes */
@@ -783,17 +778,7 @@ static const u32 ar9331_modes_high_power_tx_gain_1p1[][5] = {
783 {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000}, 778 {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
784}; 779};
785 780
786static const u32 ar9331_1p1_mac_postamble[][5] = { 781#define ar9331_1p1_mac_postamble ar9300_2p2_mac_postamble
787 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
788 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
789 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
790 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
791 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
792 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
793 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
794 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
795 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
796};
797 782
798static const u32 ar9331_1p1_soc_preamble[][2] = { 783static const u32 ar9331_1p1_soc_preamble[][2] = {
799 /* Addr allmodes */ 784 /* Addr allmodes */
@@ -1112,38 +1097,4 @@ static const u32 ar9331_common_tx_gain_offset1_1[][1] = {
1112 {0x00000000}, 1097 {0x00000000},
1113}; 1098};
1114 1099
1115static const u32 ar9331_1p1_chansel_xtal_25M[] = {
1116 0x0101479e,
1117 0x0101d027,
1118 0x010258af,
1119 0x0102e138,
1120 0x010369c0,
1121 0x0103f249,
1122 0x01047ad1,
1123 0x0105035a,
1124 0x01058be2,
1125 0x0106146b,
1126 0x01069cf3,
1127 0x0107257c,
1128 0x0107ae04,
1129 0x0108f5b2,
1130};
1131
1132static const u32 ar9331_1p1_chansel_xtal_40M[] = {
1133 0x00a0ccbe,
1134 0x00a12213,
1135 0x00a17769,
1136 0x00a1ccbe,
1137 0x00a22213,
1138 0x00a27769,
1139 0x00a2ccbe,
1140 0x00a32213,
1141 0x00a37769,
1142 0x00a3ccbe,
1143 0x00a42213,
1144 0x00a47769,
1145 0x00a4ccbe,
1146 0x00a5998b,
1147};
1148
1149#endif /* INITVALS_9330_1P1_H */ 1100#endif /* INITVALS_9330_1P1_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
index 0e6ca0834b34..57ed8a112173 100644
--- a/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2011 Atheros Communications Inc. 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
3 * 4 *
4 * Permission to use, copy, modify, and/or distribute this software for any 5 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 6 * purpose with or without fee is hereby granted, provided that the above
@@ -17,8 +18,8 @@
17#ifndef INITVALS_9330_1P2_H 18#ifndef INITVALS_9330_1P2_H
18#define INITVALS_9330_1P2_H 19#define INITVALS_9330_1P2_H
19 20
20static const u32 ar9331_modes_lowest_ob_db_tx_gain_1p2[][5] = { 21static const u32 ar9331_modes_high_ob_db_tx_gain_1p2[][5] = {
21 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 22 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
22 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7}, 23 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
23 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000}, 24 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
24 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002}, 25 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
@@ -102,8 +103,14 @@ static const u32 ar9331_modes_lowest_ob_db_tx_gain_1p2[][5] = {
102 {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004}, 103 {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
103}; 104};
104 105
106#define ar9331_modes_high_power_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
107
108#define ar9331_modes_low_ob_db_tx_gain_1p2 ar9331_modes_high_power_tx_gain_1p2
109
110#define ar9331_modes_lowest_ob_db_tx_gain_1p2 ar9331_modes_low_ob_db_tx_gain_1p2
111
105static const u32 ar9331_1p2_baseband_postamble[][5] = { 112static const u32 ar9331_1p2_baseband_postamble[][5] = {
106 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 113 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
107 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005}, 114 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
108 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e}, 115 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
109 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, 116 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
@@ -147,191 +154,6 @@ static const u32 ar9331_1p2_baseband_postamble[][5] = {
147 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 154 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
148}; 155};
149 156
150static const u32 ar9331_modes_high_ob_db_tx_gain_1p2[][5] = {
151 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
152 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
153 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
154 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
155 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
156 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
157 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
158 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
159 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
160 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
161 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
162 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
163 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
164 {0x0000a52c, 0x41023e85, 0x41023e85, 0x3f001620, 0x3f001620},
165 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x41001621, 0x41001621},
166 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x44001640, 0x44001640},
167 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x46001641, 0x46001641},
168 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x48001642, 0x48001642},
169 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x4b001644, 0x4b001644},
170 {0x0000a544, 0x6502feca, 0x6502feca, 0x4e001a81, 0x4e001a81},
171 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x51001a83, 0x51001a83},
172 {0x0000a54c, 0x7203feca, 0x7203feca, 0x54001c84, 0x54001c84},
173 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x57001ce3, 0x57001ce3},
174 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x5b001ce5, 0x5b001ce5},
175 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5f001ce9, 0x5f001ce9},
176 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x66001eec, 0x66001eec},
177 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x66001eec, 0x66001eec},
178 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x66001eec, 0x66001eec},
179 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
180 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
181 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
182 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
183 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
184 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
185 {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
186 {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
187 {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
188 {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
189 {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
190 {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
191 {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
192 {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
193 {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
194 {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
195 {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
196 {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
197 {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
198 {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
199 {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
200 {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
201 {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
202 {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
203 {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
204 {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
205 {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
206 {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
207 {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
208 {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
209 {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
210 {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
211 {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
212 {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
213 {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
214 {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
215 {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
216 {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
217 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
218 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
219 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
220 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
221 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
222 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
223 {0x0000a618, 0x02008501, 0x02008501, 0x02008501, 0x02008501},
224 {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
225 {0x0000a620, 0x0300c802, 0x0300c802, 0x0300c802, 0x0300c802},
226 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x0300cc03, 0x0300cc03},
227 {0x0000a628, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
228 {0x0000a62c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
229 {0x0000a630, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
230 {0x0000a634, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
231 {0x0000a638, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
232 {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
233};
234
235static const u32 ar9331_modes_low_ob_db_tx_gain_1p2[][5] = {
236 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
237 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
238 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
239 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
240 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
241 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
242 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
243 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
244 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
245 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
246 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
247 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
248 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
249 {0x0000a52c, 0x41023e85, 0x41023e85, 0x3f001620, 0x3f001620},
250 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x41001621, 0x41001621},
251 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x44001640, 0x44001640},
252 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x46001641, 0x46001641},
253 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x48001642, 0x48001642},
254 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x4b001644, 0x4b001644},
255 {0x0000a544, 0x6502feca, 0x6502feca, 0x4e001a81, 0x4e001a81},
256 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x51001a83, 0x51001a83},
257 {0x0000a54c, 0x7203feca, 0x7203feca, 0x54001c84, 0x54001c84},
258 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x57001ce3, 0x57001ce3},
259 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x5b001ce5, 0x5b001ce5},
260 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5f001ce9, 0x5f001ce9},
261 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x66001eec, 0x66001eec},
262 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x66001eec, 0x66001eec},
263 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x66001eec, 0x66001eec},
264 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
265 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
266 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
267 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
268 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
269 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
270 {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
271 {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
272 {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
273 {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
274 {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
275 {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
276 {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
277 {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
278 {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
279 {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
280 {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
281 {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
282 {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
283 {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
284 {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
285 {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
286 {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
287 {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
288 {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
289 {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
290 {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
291 {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
292 {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
293 {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
294 {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
295 {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
296 {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
297 {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
298 {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
299 {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
300 {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
301 {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
302 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
303 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
304 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
305 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
306 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
307 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
308 {0x0000a618, 0x02008501, 0x02008501, 0x02008501, 0x02008501},
309 {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
310 {0x0000a620, 0x0300c802, 0x0300c802, 0x0300c802, 0x0300c802},
311 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x0300cc03, 0x0300cc03},
312 {0x0000a628, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
313 {0x0000a62c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
314 {0x0000a630, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
315 {0x0000a634, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
316 {0x0000a638, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
317 {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
318};
319
320static const u32 ar9331_1p2_baseband_core_txfir_coeff_japan_2484[][2] = {
321 /* Addr allmodes */
322 {0x0000a398, 0x00000000},
323 {0x0000a39c, 0x6f7f0301},
324 {0x0000a3a0, 0xca9228ee},
325};
326
327static const u32 ar9331_1p2_xtal_25M[][2] = {
328 /* Addr allmodes */
329 {0x00007038, 0x000002f8},
330 {0x00008244, 0x0010f3d7},
331 {0x0000824c, 0x0001e7ae},
332 {0x0001609c, 0x0f508f29},
333};
334
335static const u32 ar9331_1p2_radio_core[][2] = { 157static const u32 ar9331_1p2_radio_core[][2] = {
336 /* Addr allmodes */ 158 /* Addr allmodes */
337 {0x00016000, 0x36db6db6}, 159 {0x00016000, 0x36db6db6},
@@ -397,684 +219,24 @@ static const u32 ar9331_1p2_radio_core[][2] = {
397 {0x000163d4, 0x00000000}, 219 {0x000163d4, 0x00000000},
398}; 220};
399 221
400static const u32 ar9331_1p2_soc_postamble[][5] = { 222#define ar9331_1p2_baseband_core_txfir_coeff_japan_2484 ar9331_1p1_baseband_core_txfir_coeff_japan_2484
401 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
402 {0x00007010, 0x00000022, 0x00000022, 0x00000022, 0x00000022},
403};
404 223
405static const u32 ar9331_common_wo_xlna_rx_gain_1p2[][2] = { 224#define ar9331_1p2_xtal_25M ar9331_1p1_xtal_25M
406 /* Addr allmodes */
407 {0x0000a000, 0x00060005},
408 {0x0000a004, 0x00810080},
409 {0x0000a008, 0x00830082},
410 {0x0000a00c, 0x00850084},
411 {0x0000a010, 0x01820181},
412 {0x0000a014, 0x01840183},
413 {0x0000a018, 0x01880185},
414 {0x0000a01c, 0x018a0189},
415 {0x0000a020, 0x02850284},
416 {0x0000a024, 0x02890288},
417 {0x0000a028, 0x028b028a},
418 {0x0000a02c, 0x03850384},
419 {0x0000a030, 0x03890388},
420 {0x0000a034, 0x038b038a},
421 {0x0000a038, 0x038d038c},
422 {0x0000a03c, 0x03910390},
423 {0x0000a040, 0x03930392},
424 {0x0000a044, 0x03950394},
425 {0x0000a048, 0x00000396},
426 {0x0000a04c, 0x00000000},
427 {0x0000a050, 0x00000000},
428 {0x0000a054, 0x00000000},
429 {0x0000a058, 0x00000000},
430 {0x0000a05c, 0x00000000},
431 {0x0000a060, 0x00000000},
432 {0x0000a064, 0x00000000},
433 {0x0000a068, 0x00000000},
434 {0x0000a06c, 0x00000000},
435 {0x0000a070, 0x00000000},
436 {0x0000a074, 0x00000000},
437 {0x0000a078, 0x00000000},
438 {0x0000a07c, 0x00000000},
439 {0x0000a080, 0x28282828},
440 {0x0000a084, 0x28282828},
441 {0x0000a088, 0x28282828},
442 {0x0000a08c, 0x28282828},
443 {0x0000a090, 0x28282828},
444 {0x0000a094, 0x24242428},
445 {0x0000a098, 0x171e1e1e},
446 {0x0000a09c, 0x02020b0b},
447 {0x0000a0a0, 0x02020202},
448 {0x0000a0a4, 0x00000000},
449 {0x0000a0a8, 0x00000000},
450 {0x0000a0ac, 0x00000000},
451 {0x0000a0b0, 0x00000000},
452 {0x0000a0b4, 0x00000000},
453 {0x0000a0b8, 0x00000000},
454 {0x0000a0bc, 0x00000000},
455 {0x0000a0c0, 0x22072208},
456 {0x0000a0c4, 0x22052206},
457 {0x0000a0c8, 0x22032204},
458 {0x0000a0cc, 0x22012202},
459 {0x0000a0d0, 0x221f2200},
460 {0x0000a0d4, 0x221d221e},
461 {0x0000a0d8, 0x33023303},
462 {0x0000a0dc, 0x33003301},
463 {0x0000a0e0, 0x331e331f},
464 {0x0000a0e4, 0x4402331d},
465 {0x0000a0e8, 0x44004401},
466 {0x0000a0ec, 0x441e441f},
467 {0x0000a0f0, 0x55025503},
468 {0x0000a0f4, 0x55005501},
469 {0x0000a0f8, 0x551e551f},
470 {0x0000a0fc, 0x6602551d},
471 {0x0000a100, 0x66006601},
472 {0x0000a104, 0x661e661f},
473 {0x0000a108, 0x7703661d},
474 {0x0000a10c, 0x77017702},
475 {0x0000a110, 0x00007700},
476 {0x0000a114, 0x00000000},
477 {0x0000a118, 0x00000000},
478 {0x0000a11c, 0x00000000},
479 {0x0000a120, 0x00000000},
480 {0x0000a124, 0x00000000},
481 {0x0000a128, 0x00000000},
482 {0x0000a12c, 0x00000000},
483 {0x0000a130, 0x00000000},
484 {0x0000a134, 0x00000000},
485 {0x0000a138, 0x00000000},
486 {0x0000a13c, 0x00000000},
487 {0x0000a140, 0x001f0000},
488 {0x0000a144, 0x111f1100},
489 {0x0000a148, 0x111d111e},
490 {0x0000a14c, 0x111b111c},
491 {0x0000a150, 0x22032204},
492 {0x0000a154, 0x22012202},
493 {0x0000a158, 0x221f2200},
494 {0x0000a15c, 0x221d221e},
495 {0x0000a160, 0x33013302},
496 {0x0000a164, 0x331f3300},
497 {0x0000a168, 0x4402331e},
498 {0x0000a16c, 0x44004401},
499 {0x0000a170, 0x441e441f},
500 {0x0000a174, 0x55015502},
501 {0x0000a178, 0x551f5500},
502 {0x0000a17c, 0x6602551e},
503 {0x0000a180, 0x66006601},
504 {0x0000a184, 0x661e661f},
505 {0x0000a188, 0x7703661d},
506 {0x0000a18c, 0x77017702},
507 {0x0000a190, 0x00007700},
508 {0x0000a194, 0x00000000},
509 {0x0000a198, 0x00000000},
510 {0x0000a19c, 0x00000000},
511 {0x0000a1a0, 0x00000000},
512 {0x0000a1a4, 0x00000000},
513 {0x0000a1a8, 0x00000000},
514 {0x0000a1ac, 0x00000000},
515 {0x0000a1b0, 0x00000000},
516 {0x0000a1b4, 0x00000000},
517 {0x0000a1b8, 0x00000000},
518 {0x0000a1bc, 0x00000000},
519 {0x0000a1c0, 0x00000000},
520 {0x0000a1c4, 0x00000000},
521 {0x0000a1c8, 0x00000000},
522 {0x0000a1cc, 0x00000000},
523 {0x0000a1d0, 0x00000000},
524 {0x0000a1d4, 0x00000000},
525 {0x0000a1d8, 0x00000000},
526 {0x0000a1dc, 0x00000000},
527 {0x0000a1e0, 0x00000000},
528 {0x0000a1e4, 0x00000000},
529 {0x0000a1e8, 0x00000000},
530 {0x0000a1ec, 0x00000000},
531 {0x0000a1f0, 0x00000396},
532 {0x0000a1f4, 0x00000396},
533 {0x0000a1f8, 0x00000396},
534 {0x0000a1fc, 0x00000296},
535};
536 225
537static const u32 ar9331_1p2_baseband_core[][2] = { 226#define ar9331_1p2_xtal_40M ar9331_1p1_xtal_40M
538 /* Addr allmodes */
539 {0x00009800, 0xafe68e30},
540 {0x00009804, 0xfd14e000},
541 {0x00009808, 0x9c0a8f6b},
542 {0x0000980c, 0x04800000},
543 {0x00009814, 0x9280c00a},
544 {0x00009818, 0x00000000},
545 {0x0000981c, 0x00020028},
546 {0x00009834, 0x5f3ca3de},
547 {0x00009838, 0x0108ecff},
548 {0x0000983c, 0x14750600},
549 {0x00009880, 0x201fff00},
550 {0x00009884, 0x00001042},
551 {0x000098a4, 0x00200400},
552 {0x000098b0, 0x32840bbe},
553 {0x000098d0, 0x004b6a8e},
554 {0x000098d4, 0x00000820},
555 {0x000098dc, 0x00000000},
556 {0x000098f0, 0x00000000},
557 {0x000098f4, 0x00000000},
558 {0x00009c04, 0x00000000},
559 {0x00009c08, 0x03200000},
560 {0x00009c0c, 0x00000000},
561 {0x00009c10, 0x00000000},
562 {0x00009c14, 0x00046384},
563 {0x00009c18, 0x05b6b440},
564 {0x00009c1c, 0x00b6b440},
565 {0x00009d00, 0xc080a333},
566 {0x00009d04, 0x40206c10},
567 {0x00009d08, 0x009c4060},
568 {0x00009d0c, 0x1883800a},
569 {0x00009d10, 0x01834061},
570 {0x00009d14, 0x00c00400},
571 {0x00009d18, 0x00000000},
572 {0x00009e08, 0x0038233c},
573 {0x00009e24, 0x9927b515},
574 {0x00009e28, 0x12ef0200},
575 {0x00009e30, 0x06336f77},
576 {0x00009e34, 0x6af6532f},
577 {0x00009e38, 0x0cc80c00},
578 {0x00009e40, 0x0d261820},
579 {0x00009e4c, 0x00001004},
580 {0x00009e50, 0x00ff03f1},
581 {0x00009fc0, 0x803e4788},
582 {0x00009fc4, 0x0001efb5},
583 {0x00009fcc, 0x40000014},
584 {0x0000a20c, 0x00000000},
585 {0x0000a220, 0x00000000},
586 {0x0000a224, 0x00000000},
587 {0x0000a228, 0x10002310},
588 {0x0000a23c, 0x00000000},
589 {0x0000a244, 0x0c000000},
590 {0x0000a2a0, 0x00000001},
591 {0x0000a2c0, 0x00000001},
592 {0x0000a2c8, 0x00000000},
593 {0x0000a2cc, 0x18c43433},
594 {0x0000a2d4, 0x00000000},
595 {0x0000a2dc, 0x00000000},
596 {0x0000a2e0, 0x00000000},
597 {0x0000a2e4, 0x00000000},
598 {0x0000a2e8, 0x00000000},
599 {0x0000a2ec, 0x00000000},
600 {0x0000a2f0, 0x00000000},
601 {0x0000a2f4, 0x00000000},
602 {0x0000a2f8, 0x00000000},
603 {0x0000a344, 0x00000000},
604 {0x0000a34c, 0x00000000},
605 {0x0000a350, 0x0000a000},
606 {0x0000a364, 0x00000000},
607 {0x0000a370, 0x00000000},
608 {0x0000a390, 0x00000001},
609 {0x0000a394, 0x00000444},
610 {0x0000a398, 0x001f0e0f},
611 {0x0000a39c, 0x0075393f},
612 {0x0000a3a0, 0xb79f6427},
613 {0x0000a3a4, 0x00000000},
614 {0x0000a3a8, 0xaaaaaaaa},
615 {0x0000a3ac, 0x3c466478},
616 {0x0000a3c0, 0x20202020},
617 {0x0000a3c4, 0x22222220},
618 {0x0000a3c8, 0x20200020},
619 {0x0000a3cc, 0x20202020},
620 {0x0000a3d0, 0x20202020},
621 {0x0000a3d4, 0x20202020},
622 {0x0000a3d8, 0x20202020},
623 {0x0000a3dc, 0x20202020},
624 {0x0000a3e0, 0x20202020},
625 {0x0000a3e4, 0x20202020},
626 {0x0000a3e8, 0x20202020},
627 {0x0000a3ec, 0x20202020},
628 {0x0000a3f0, 0x00000000},
629 {0x0000a3f4, 0x00000006},
630 {0x0000a3f8, 0x0cdbd380},
631 {0x0000a3fc, 0x000f0f01},
632 {0x0000a400, 0x8fa91f01},
633 {0x0000a404, 0x00000000},
634 {0x0000a408, 0x0e79e5c6},
635 {0x0000a40c, 0x00820820},
636 {0x0000a414, 0x1ce739ce},
637 {0x0000a418, 0x2d001dce},
638 {0x0000a41c, 0x1ce739ce},
639 {0x0000a420, 0x000001ce},
640 {0x0000a424, 0x1ce739ce},
641 {0x0000a428, 0x000001ce},
642 {0x0000a42c, 0x1ce739ce},
643 {0x0000a430, 0x1ce739ce},
644 {0x0000a434, 0x00000000},
645 {0x0000a438, 0x00001801},
646 {0x0000a43c, 0x00000000},
647 {0x0000a440, 0x00000000},
648 {0x0000a444, 0x00000000},
649 {0x0000a448, 0x04000000},
650 {0x0000a44c, 0x00000001},
651 {0x0000a450, 0x00010000},
652 {0x0000a458, 0x00000000},
653 {0x0000a640, 0x00000000},
654 {0x0000a644, 0x3fad9d74},
655 {0x0000a648, 0x0048060a},
656 {0x0000a64c, 0x00003c37},
657 {0x0000a670, 0x03020100},
658 {0x0000a674, 0x09080504},
659 {0x0000a678, 0x0d0c0b0a},
660 {0x0000a67c, 0x13121110},
661 {0x0000a680, 0x31301514},
662 {0x0000a684, 0x35343332},
663 {0x0000a688, 0x00000036},
664 {0x0000a690, 0x00000838},
665 {0x0000a7c0, 0x00000000},
666 {0x0000a7c4, 0xfffffffc},
667 {0x0000a7c8, 0x00000000},
668 {0x0000a7cc, 0x00000000},
669 {0x0000a7d0, 0x00000000},
670 {0x0000a7d4, 0x00000004},
671 {0x0000a7dc, 0x00000001},
672};
673 227
674static const u32 ar9331_modes_high_power_tx_gain_1p2[][5] = { 228#define ar9331_1p2_baseband_core ar9331_1p1_baseband_core
675 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
676 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
677 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
678 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
679 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
680 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
681 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
682 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
683 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
684 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
685 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
686 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
687 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
688 {0x0000a52c, 0x41023e85, 0x41023e85, 0x3f001620, 0x3f001620},
689 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x41001621, 0x41001621},
690 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x44001640, 0x44001640},
691 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x46001641, 0x46001641},
692 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x48001642, 0x48001642},
693 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x4b001644, 0x4b001644},
694 {0x0000a544, 0x6502feca, 0x6502feca, 0x4e001a81, 0x4e001a81},
695 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x51001a83, 0x51001a83},
696 {0x0000a54c, 0x7203feca, 0x7203feca, 0x54001c84, 0x54001c84},
697 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x57001ce3, 0x57001ce3},
698 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x5b001ce5, 0x5b001ce5},
699 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5f001ce9, 0x5f001ce9},
700 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x66001eec, 0x66001eec},
701 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x66001eec, 0x66001eec},
702 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x66001eec, 0x66001eec},
703 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
704 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
705 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
706 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
707 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
708 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
709 {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
710 {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
711 {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
712 {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
713 {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
714 {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
715 {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
716 {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
717 {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
718 {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
719 {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
720 {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
721 {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
722 {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
723 {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
724 {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
725 {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
726 {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
727 {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
728 {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
729 {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
730 {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
731 {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
732 {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
733 {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
734 {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
735 {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
736 {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
737 {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
738 {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
739 {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
740 {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
741 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
742 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
743 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
744 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
745 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
746 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
747 {0x0000a618, 0x02008501, 0x02008501, 0x02008501, 0x02008501},
748 {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
749 {0x0000a620, 0x0300c802, 0x0300c802, 0x0300c802, 0x0300c802},
750 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x0300cc03, 0x0300cc03},
751 {0x0000a628, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
752 {0x0000a62c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
753 {0x0000a630, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
754 {0x0000a634, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
755 {0x0000a638, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
756 {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
757};
758 229
759static const u32 ar9331_1p2_mac_postamble[][5] = { 230#define ar9331_1p2_soc_postamble ar9331_1p1_soc_postamble
760 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
761 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
762 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
763 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
764 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
765 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
766 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
767 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
768 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
769};
770 231
771static const u32 ar9331_1p2_soc_preamble[][2] = { 232#define ar9331_1p2_mac_postamble ar9331_1p1_mac_postamble
772 /* Addr allmodes */
773 {0x00007020, 0x00000000},
774 {0x00007034, 0x00000002},
775 {0x00007038, 0x000002f8},
776};
777 233
778static const u32 ar9331_1p2_xtal_40M[][2] = { 234#define ar9331_1p2_soc_preamble ar9331_1p1_soc_preamble
779 /* Addr allmodes */
780 {0x00007038, 0x000004c2},
781 {0x00008244, 0x0010f400},
782 {0x0000824c, 0x0001e800},
783 {0x0001609c, 0x0b283f31},
784};
785 235
786static const u32 ar9331_1p2_mac_core[][2] = { 236#define ar9331_1p2_mac_core ar9331_1p1_mac_core
787 /* Addr allmodes */
788 {0x00000008, 0x00000000},
789 {0x00000030, 0x00020085},
790 {0x00000034, 0x00000005},
791 {0x00000040, 0x00000000},
792 {0x00000044, 0x00000000},
793 {0x00000048, 0x00000008},
794 {0x0000004c, 0x00000010},
795 {0x00000050, 0x00000000},
796 {0x00001040, 0x002ffc0f},
797 {0x00001044, 0x002ffc0f},
798 {0x00001048, 0x002ffc0f},
799 {0x0000104c, 0x002ffc0f},
800 {0x00001050, 0x002ffc0f},
801 {0x00001054, 0x002ffc0f},
802 {0x00001058, 0x002ffc0f},
803 {0x0000105c, 0x002ffc0f},
804 {0x00001060, 0x002ffc0f},
805 {0x00001064, 0x002ffc0f},
806 {0x000010f0, 0x00000100},
807 {0x00001270, 0x00000000},
808 {0x000012b0, 0x00000000},
809 {0x000012f0, 0x00000000},
810 {0x0000143c, 0x00000000},
811 {0x0000147c, 0x00000000},
812 {0x00008000, 0x00000000},
813 {0x00008004, 0x00000000},
814 {0x00008008, 0x00000000},
815 {0x0000800c, 0x00000000},
816 {0x00008018, 0x00000000},
817 {0x00008020, 0x00000000},
818 {0x00008038, 0x00000000},
819 {0x0000803c, 0x00000000},
820 {0x00008040, 0x00000000},
821 {0x00008044, 0x00000000},
822 {0x00008048, 0x00000000},
823 {0x0000804c, 0xffffffff},
824 {0x00008054, 0x00000000},
825 {0x00008058, 0x00000000},
826 {0x0000805c, 0x000fc78f},
827 {0x00008060, 0x0000000f},
828 {0x00008064, 0x00000000},
829 {0x00008070, 0x00000310},
830 {0x00008074, 0x00000020},
831 {0x00008078, 0x00000000},
832 {0x0000809c, 0x0000000f},
833 {0x000080a0, 0x00000000},
834 {0x000080a4, 0x02ff0000},
835 {0x000080a8, 0x0e070605},
836 {0x000080ac, 0x0000000d},
837 {0x000080b0, 0x00000000},
838 {0x000080b4, 0x00000000},
839 {0x000080b8, 0x00000000},
840 {0x000080bc, 0x00000000},
841 {0x000080c0, 0x2a800000},
842 {0x000080c4, 0x06900168},
843 {0x000080c8, 0x13881c20},
844 {0x000080cc, 0x01f40000},
845 {0x000080d0, 0x00252500},
846 {0x000080d4, 0x00a00000},
847 {0x000080d8, 0x00400000},
848 {0x000080dc, 0x00000000},
849 {0x000080e0, 0xffffffff},
850 {0x000080e4, 0x0000ffff},
851 {0x000080e8, 0x3f3f3f3f},
852 {0x000080ec, 0x00000000},
853 {0x000080f0, 0x00000000},
854 {0x000080f4, 0x00000000},
855 {0x000080fc, 0x00020000},
856 {0x00008100, 0x00000000},
857 {0x00008108, 0x00000052},
858 {0x0000810c, 0x00000000},
859 {0x00008110, 0x00000000},
860 {0x00008114, 0x000007ff},
861 {0x00008118, 0x000000aa},
862 {0x0000811c, 0x00003210},
863 {0x00008124, 0x00000000},
864 {0x00008128, 0x00000000},
865 {0x0000812c, 0x00000000},
866 {0x00008130, 0x00000000},
867 {0x00008134, 0x00000000},
868 {0x00008138, 0x00000000},
869 {0x0000813c, 0x0000ffff},
870 {0x00008144, 0xffffffff},
871 {0x00008168, 0x00000000},
872 {0x0000816c, 0x00000000},
873 {0x00008170, 0x18486200},
874 {0x00008174, 0x33332210},
875 {0x00008178, 0x00000000},
876 {0x0000817c, 0x00020000},
877 {0x000081c0, 0x00000000},
878 {0x000081c4, 0x33332210},
879 {0x000081c8, 0x00000000},
880 {0x000081cc, 0x00000000},
881 {0x000081d4, 0x00000000},
882 {0x000081ec, 0x00000000},
883 {0x000081f0, 0x00000000},
884 {0x000081f4, 0x00000000},
885 {0x000081f8, 0x00000000},
886 {0x000081fc, 0x00000000},
887 {0x00008240, 0x00100000},
888 {0x00008248, 0x00000800},
889 {0x00008250, 0x00000000},
890 {0x00008254, 0x00000000},
891 {0x00008258, 0x00000000},
892 {0x0000825c, 0x40000000},
893 {0x00008260, 0x00080922},
894 {0x00008264, 0x9d400010},
895 {0x00008268, 0xffffffff},
896 {0x0000826c, 0x0000ffff},
897 {0x00008270, 0x00000000},
898 {0x00008274, 0x40000000},
899 {0x00008278, 0x003e4180},
900 {0x0000827c, 0x00000004},
901 {0x00008284, 0x0000002c},
902 {0x00008288, 0x0000002c},
903 {0x0000828c, 0x000000ff},
904 {0x00008294, 0x00000000},
905 {0x00008298, 0x00000000},
906 {0x0000829c, 0x00000000},
907 {0x00008300, 0x00000140},
908 {0x00008314, 0x00000000},
909 {0x0000831c, 0x0000010d},
910 {0x00008328, 0x00000000},
911 {0x0000832c, 0x00000007},
912 {0x00008330, 0x00000302},
913 {0x00008334, 0x00000700},
914 {0x00008338, 0x00ff0000},
915 {0x0000833c, 0x02400000},
916 {0x00008340, 0x000107ff},
917 {0x00008344, 0xaa48105b},
918 {0x00008348, 0x008f0000},
919 {0x0000835c, 0x00000000},
920 {0x00008360, 0xffffffff},
921 {0x00008364, 0xffffffff},
922 {0x00008368, 0x00000000},
923 {0x00008370, 0x00000000},
924 {0x00008374, 0x000000ff},
925 {0x00008378, 0x00000000},
926 {0x0000837c, 0x00000000},
927 {0x00008380, 0xffffffff},
928 {0x00008384, 0xffffffff},
929 {0x00008390, 0xffffffff},
930 {0x00008394, 0xffffffff},
931 {0x00008398, 0x00000000},
932 {0x0000839c, 0x00000000},
933 {0x000083a0, 0x00000000},
934 {0x000083a4, 0x0000fa14},
935 {0x000083a8, 0x000f0c00},
936 {0x000083ac, 0x33332210},
937 {0x000083b0, 0x33332210},
938 {0x000083b4, 0x33332210},
939 {0x000083b8, 0x33332210},
940 {0x000083bc, 0x00000000},
941 {0x000083c0, 0x00000000},
942 {0x000083c4, 0x00000000},
943 {0x000083c8, 0x00000000},
944 {0x000083cc, 0x00000200},
945 {0x000083d0, 0x000301ff},
946};
947 237
948static const u32 ar9331_common_rx_gain_1p2[][2] = { 238#define ar9331_common_wo_xlna_rx_gain_1p2 ar9331_common_wo_xlna_rx_gain_1p1
949 /* Addr allmodes */ 239
950 {0x0000a000, 0x00010000}, 240#define ar9331_common_rx_gain_1p2 ar9485_common_rx_gain_1_1
951 {0x0000a004, 0x00030002},
952 {0x0000a008, 0x00050004},
953 {0x0000a00c, 0x00810080},
954 {0x0000a010, 0x01800082},
955 {0x0000a014, 0x01820181},
956 {0x0000a018, 0x01840183},
957 {0x0000a01c, 0x01880185},
958 {0x0000a020, 0x018a0189},
959 {0x0000a024, 0x02850284},
960 {0x0000a028, 0x02890288},
961 {0x0000a02c, 0x03850384},
962 {0x0000a030, 0x03890388},
963 {0x0000a034, 0x038b038a},
964 {0x0000a038, 0x038d038c},
965 {0x0000a03c, 0x03910390},
966 {0x0000a040, 0x03930392},
967 {0x0000a044, 0x03950394},
968 {0x0000a048, 0x00000396},
969 {0x0000a04c, 0x00000000},
970 {0x0000a050, 0x00000000},
971 {0x0000a054, 0x00000000},
972 {0x0000a058, 0x00000000},
973 {0x0000a05c, 0x00000000},
974 {0x0000a060, 0x00000000},
975 {0x0000a064, 0x00000000},
976 {0x0000a068, 0x00000000},
977 {0x0000a06c, 0x00000000},
978 {0x0000a070, 0x00000000},
979 {0x0000a074, 0x00000000},
980 {0x0000a078, 0x00000000},
981 {0x0000a07c, 0x00000000},
982 {0x0000a080, 0x28282828},
983 {0x0000a084, 0x28282828},
984 {0x0000a088, 0x28282828},
985 {0x0000a08c, 0x28282828},
986 {0x0000a090, 0x28282828},
987 {0x0000a094, 0x21212128},
988 {0x0000a098, 0x171c1c1c},
989 {0x0000a09c, 0x02020212},
990 {0x0000a0a0, 0x00000202},
991 {0x0000a0a4, 0x00000000},
992 {0x0000a0a8, 0x00000000},
993 {0x0000a0ac, 0x00000000},
994 {0x0000a0b0, 0x00000000},
995 {0x0000a0b4, 0x00000000},
996 {0x0000a0b8, 0x00000000},
997 {0x0000a0bc, 0x00000000},
998 {0x0000a0c0, 0x001f0000},
999 {0x0000a0c4, 0x111f1100},
1000 {0x0000a0c8, 0x111d111e},
1001 {0x0000a0cc, 0x111b111c},
1002 {0x0000a0d0, 0x22032204},
1003 {0x0000a0d4, 0x22012202},
1004 {0x0000a0d8, 0x221f2200},
1005 {0x0000a0dc, 0x221d221e},
1006 {0x0000a0e0, 0x33013302},
1007 {0x0000a0e4, 0x331f3300},
1008 {0x0000a0e8, 0x4402331e},
1009 {0x0000a0ec, 0x44004401},
1010 {0x0000a0f0, 0x441e441f},
1011 {0x0000a0f4, 0x55015502},
1012 {0x0000a0f8, 0x551f5500},
1013 {0x0000a0fc, 0x6602551e},
1014 {0x0000a100, 0x66006601},
1015 {0x0000a104, 0x661e661f},
1016 {0x0000a108, 0x7703661d},
1017 {0x0000a10c, 0x77017702},
1018 {0x0000a110, 0x00007700},
1019 {0x0000a114, 0x00000000},
1020 {0x0000a118, 0x00000000},
1021 {0x0000a11c, 0x00000000},
1022 {0x0000a120, 0x00000000},
1023 {0x0000a124, 0x00000000},
1024 {0x0000a128, 0x00000000},
1025 {0x0000a12c, 0x00000000},
1026 {0x0000a130, 0x00000000},
1027 {0x0000a134, 0x00000000},
1028 {0x0000a138, 0x00000000},
1029 {0x0000a13c, 0x00000000},
1030 {0x0000a140, 0x001f0000},
1031 {0x0000a144, 0x111f1100},
1032 {0x0000a148, 0x111d111e},
1033 {0x0000a14c, 0x111b111c},
1034 {0x0000a150, 0x22032204},
1035 {0x0000a154, 0x22012202},
1036 {0x0000a158, 0x221f2200},
1037 {0x0000a15c, 0x221d221e},
1038 {0x0000a160, 0x33013302},
1039 {0x0000a164, 0x331f3300},
1040 {0x0000a168, 0x4402331e},
1041 {0x0000a16c, 0x44004401},
1042 {0x0000a170, 0x441e441f},
1043 {0x0000a174, 0x55015502},
1044 {0x0000a178, 0x551f5500},
1045 {0x0000a17c, 0x6602551e},
1046 {0x0000a180, 0x66006601},
1047 {0x0000a184, 0x661e661f},
1048 {0x0000a188, 0x7703661d},
1049 {0x0000a18c, 0x77017702},
1050 {0x0000a190, 0x00007700},
1051 {0x0000a194, 0x00000000},
1052 {0x0000a198, 0x00000000},
1053 {0x0000a19c, 0x00000000},
1054 {0x0000a1a0, 0x00000000},
1055 {0x0000a1a4, 0x00000000},
1056 {0x0000a1a8, 0x00000000},
1057 {0x0000a1ac, 0x00000000},
1058 {0x0000a1b0, 0x00000000},
1059 {0x0000a1b4, 0x00000000},
1060 {0x0000a1b8, 0x00000000},
1061 {0x0000a1bc, 0x00000000},
1062 {0x0000a1c0, 0x00000000},
1063 {0x0000a1c4, 0x00000000},
1064 {0x0000a1c8, 0x00000000},
1065 {0x0000a1cc, 0x00000000},
1066 {0x0000a1d0, 0x00000000},
1067 {0x0000a1d4, 0x00000000},
1068 {0x0000a1d8, 0x00000000},
1069 {0x0000a1dc, 0x00000000},
1070 {0x0000a1e0, 0x00000000},
1071 {0x0000a1e4, 0x00000000},
1072 {0x0000a1e8, 0x00000000},
1073 {0x0000a1ec, 0x00000000},
1074 {0x0000a1f0, 0x00000396},
1075 {0x0000a1f4, 0x00000396},
1076 {0x0000a1f8, 0x00000396},
1077 {0x0000a1fc, 0x00000296},
1078};
1079 241
1080#endif /* INITVALS_9330_1P2_H */ 242#endif /* INITVALS_9330_1P2_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
index 815a8af1beef..1d8235e19f0f 100644
--- a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2011 Atheros Communications Inc. 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
3 * 4 *
4 * Permission to use, copy, modify, and/or distribute this software for any 5 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 6 * purpose with or without fee is hereby granted, provided that the above
@@ -18,16 +19,16 @@
18#define INITVALS_9340_H 19#define INITVALS_9340_H
19 20
20static const u32 ar9340_1p0_radio_postamble[][5] = { 21static const u32 ar9340_1p0_radio_postamble[][5] = {
21 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 22 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
22 {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800}, 23 {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
23 {0x0001610c, 0x08000000, 0x08000000, 0x00000000, 0x00000000}, 24 {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
24 {0x00016140, 0x10804000, 0x10804000, 0x50804000, 0x50804000}, 25 {0x00016140, 0x10804000, 0x10804000, 0x50804000, 0x50804000},
25 {0x0001650c, 0x08000000, 0x08000000, 0x00000000, 0x00000000}, 26 {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
26 {0x00016540, 0x10804000, 0x10804000, 0x50804000, 0x50804000}, 27 {0x00016540, 0x10804000, 0x10804000, 0x50804000, 0x50804000},
27}; 28};
28 29
29static const u32 ar9340Modes_lowest_ob_db_tx_gain_table_1p0[][5] = { 30static const u32 ar9340Modes_lowest_ob_db_tx_gain_table_1p0[][5] = {
30 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 31 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
31 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, 32 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
32 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 33 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
33 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002}, 34 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
@@ -99,21 +100,10 @@ static const u32 ar9340Modes_lowest_ob_db_tx_gain_table_1p0[][5] = {
99 {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266}, 100 {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
100}; 101};
101 102
102static const u32 ar9340Modes_fast_clock_1p0[][3] = { 103#define ar9340Modes_fast_clock_1p0 ar9300Modes_fast_clock_2p2
103 /* Addr 5G_HT20 5G_HT40 */
104 {0x00001030, 0x00000268, 0x000004d0},
105 {0x00001070, 0x0000018c, 0x00000318},
106 {0x000010b0, 0x00000fd0, 0x00001fa0},
107 {0x00008014, 0x044c044c, 0x08980898},
108 {0x0000801c, 0x148ec02b, 0x148ec057},
109 {0x00008318, 0x000044c0, 0x00008980},
110 {0x00009e00, 0x03721821, 0x03721821},
111 {0x0000a230, 0x0000000b, 0x00000016},
112 {0x0000a254, 0x00000898, 0x00001130},
113};
114 104
115static const u32 ar9340_1p0_radio_core[][2] = { 105static const u32 ar9340_1p0_radio_core[][2] = {
116 /* Addr allmodes */ 106 /* Addr allmodes */
117 {0x00016000, 0x36db6db6}, 107 {0x00016000, 0x36db6db6},
118 {0x00016004, 0x6db6db40}, 108 {0x00016004, 0x6db6db40},
119 {0x00016008, 0x73f00000}, 109 {0x00016008, 0x73f00000},
@@ -146,15 +136,13 @@ static const u32 ar9340_1p0_radio_core[][2] = {
146 {0x00016100, 0x04cb0001}, 136 {0x00016100, 0x04cb0001},
147 {0x00016104, 0xfff80000}, 137 {0x00016104, 0xfff80000},
148 {0x00016108, 0x00080010}, 138 {0x00016108, 0x00080010},
149 {0x0001610c, 0x00000000},
150 {0x00016140, 0x50804008}, 139 {0x00016140, 0x50804008},
151 {0x00016144, 0x01884080}, 140 {0x00016144, 0x01884080},
152 {0x00016148, 0x000080c0}, 141 {0x00016148, 0x000080c0},
153 {0x00016280, 0x01000015}, 142 {0x00016280, 0x01000015},
154 {0x00016284, 0x05530000}, 143 {0x00016284, 0x15530000},
155 {0x00016288, 0x00318000}, 144 {0x00016288, 0x00318000},
156 {0x0001628c, 0x50000000}, 145 {0x0001628c, 0x50000000},
157 {0x00016290, 0x4080294f},
158 {0x00016380, 0x00000000}, 146 {0x00016380, 0x00000000},
159 {0x00016384, 0x00000000}, 147 {0x00016384, 0x00000000},
160 {0x00016388, 0x00800700}, 148 {0x00016388, 0x00800700},
@@ -219,52 +207,43 @@ static const u32 ar9340_1p0_radio_core[][2] = {
219}; 207};
220 208
221static const u32 ar9340_1p0_radio_core_40M[][2] = { 209static const u32 ar9340_1p0_radio_core_40M[][2] = {
210 /* Addr allmodes */
222 {0x0001609c, 0x02566f3a}, 211 {0x0001609c, 0x02566f3a},
223 {0x000160ac, 0xa4647c00}, 212 {0x000160ac, 0xa4647c00},
224 {0x000160b0, 0x01885f5a}, 213 {0x000160b0, 0x01885f5a},
225}; 214};
226 215
227static const u32 ar9340_1p0_mac_postamble[][5] = { 216#define ar9340_1p0_mac_postamble ar9300_2p2_mac_postamble
228 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
229 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
230 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
231 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
232 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
233 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
234 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
235 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
236 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
237};
238 217
239static const u32 ar9340_1p0_soc_postamble[][5] = { 218#define ar9340_1p0_soc_postamble ar9300_2p2_soc_postamble
240 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
241 {0x00007010, 0x00000023, 0x00000023, 0x00000023, 0x00000023},
242};
243 219
244static const u32 ar9340_1p0_baseband_postamble[][5] = { 220static const u32 ar9340_1p0_baseband_postamble[][5] = {
245 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 221 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
246 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011}, 222 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
247 {0x00009820, 0x206a022e, 0x206a022e, 0x206a022e, 0x206a022e}, 223 {0x00009820, 0x206a022e, 0x206a022e, 0x206a022e, 0x206a022e},
248 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, 224 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
249 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881}, 225 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
250 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, 226 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
251 {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c}, 227 {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
252 {0x00009c00, 0x00000044, 0x000000c4, 0x000000c4, 0x00000044}, 228 {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
253 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0}, 229 {0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a0},
254 {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020}, 230 {0x00009e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020},
255 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2}, 231 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
256 {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec88d2e, 0x7ec88d2e}, 232 {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec88d2e, 0x7ec88d2e},
257 {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e}, 233 {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3379605e, 0x33795d5e},
258 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 234 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
259 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c}, 235 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
260 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce}, 236 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
261 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021}, 237 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
238 {0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222},
262 {0x00009e44, 0x02321e27, 0x02321e27, 0x02291e27, 0x02291e27}, 239 {0x00009e44, 0x02321e27, 0x02321e27, 0x02291e27, 0x02291e27},
263 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012}, 240 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
264 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000}, 241 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
265 {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0}, 242 {0x0000a204, 0x00003ec0, 0x00003ec4, 0x00003ec4, 0x00003ec0},
266 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004}, 243 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
244 {0x0000a22c, 0x07e26a2f, 0x07e26a2f, 0x01026a2f, 0x01026a2f},
267 {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b}, 245 {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
246 {0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff},
268 {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018}, 247 {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
269 {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, 248 {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
270 {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, 249 {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
@@ -277,11 +256,11 @@ static const u32 ar9340_1p0_baseband_postamble[][5] = {
277 {0x0000a288, 0x00000220, 0x00000220, 0x00000110, 0x00000110}, 256 {0x0000a288, 0x00000220, 0x00000220, 0x00000110, 0x00000110},
278 {0x0000a28c, 0x00011111, 0x00011111, 0x00022222, 0x00022222}, 257 {0x0000a28c, 0x00011111, 0x00011111, 0x00022222, 0x00022222},
279 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18}, 258 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
280 {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982}, 259 {0x0000a2d0, 0x00041983, 0x00041983, 0x00041982, 0x00041982},
281 {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a}, 260 {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
282 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 261 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
283 {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, 262 {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
284 {0x0000ae04, 0x00180000, 0x00180000, 0x00180000, 0x00180000}, 263 {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000},
285 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 264 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
286 {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, 265 {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
287 {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce}, 266 {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
@@ -289,21 +268,21 @@ static const u32 ar9340_1p0_baseband_postamble[][5] = {
289}; 268};
290 269
291static const u32 ar9340_1p0_baseband_core[][2] = { 270static const u32 ar9340_1p0_baseband_core[][2] = {
292 /* Addr allmodes */ 271 /* Addr allmodes */
293 {0x00009800, 0xafe68e30}, 272 {0x00009800, 0xafe68e30},
294 {0x00009804, 0xfd14e000}, 273 {0x00009804, 0xfd14e000},
295 {0x00009808, 0x9c0a9f6b}, 274 {0x00009808, 0x9c0a9f6b},
296 {0x0000980c, 0x04900000}, 275 {0x0000980c, 0x04900000},
297 {0x00009814, 0xb280c00a}, 276 {0x00009814, 0x3280c00a},
298 {0x00009818, 0x00000000}, 277 {0x00009818, 0x00000000},
299 {0x0000981c, 0x00020028}, 278 {0x0000981c, 0x00020028},
300 {0x00009834, 0x5f3ca3de}, 279 {0x00009834, 0x6400a190},
301 {0x00009838, 0x0108ecff}, 280 {0x00009838, 0x0108ecff},
302 {0x0000983c, 0x14750600}, 281 {0x0000983c, 0x14000600},
303 {0x00009880, 0x201fff00}, 282 {0x00009880, 0x201fff00},
304 {0x00009884, 0x00001042}, 283 {0x00009884, 0x00001042},
305 {0x000098a4, 0x00200400}, 284 {0x000098a4, 0x00200400},
306 {0x000098b0, 0x52440bbe}, 285 {0x000098b0, 0x32840bbe},
307 {0x000098d0, 0x004b6a8e}, 286 {0x000098d0, 0x004b6a8e},
308 {0x000098d4, 0x00000820}, 287 {0x000098d4, 0x00000820},
309 {0x000098dc, 0x00000000}, 288 {0x000098dc, 0x00000000},
@@ -329,7 +308,6 @@ static const u32 ar9340_1p0_baseband_core[][2] = {
329 {0x00009e30, 0x06336f77}, 308 {0x00009e30, 0x06336f77},
330 {0x00009e34, 0x6af6532f}, 309 {0x00009e34, 0x6af6532f},
331 {0x00009e38, 0x0cc80c00}, 310 {0x00009e38, 0x0cc80c00},
332 {0x00009e3c, 0xcf946222},
333 {0x00009e40, 0x0d261820}, 311 {0x00009e40, 0x0d261820},
334 {0x00009e4c, 0x00001004}, 312 {0x00009e4c, 0x00001004},
335 {0x00009e50, 0x00ff03f1}, 313 {0x00009e50, 0x00ff03f1},
@@ -342,8 +320,6 @@ static const u32 ar9340_1p0_baseband_core[][2] = {
342 {0x0000a220, 0x00000000}, 320 {0x0000a220, 0x00000000},
343 {0x0000a224, 0x00000000}, 321 {0x0000a224, 0x00000000},
344 {0x0000a228, 0x10002310}, 322 {0x0000a228, 0x10002310},
345 {0x0000a22c, 0x01036a1e},
346 {0x0000a234, 0x10000fff},
347 {0x0000a23c, 0x00000000}, 323 {0x0000a23c, 0x00000000},
348 {0x0000a244, 0x0c000000}, 324 {0x0000a244, 0x0c000000},
349 {0x0000a2a0, 0x00000001}, 325 {0x0000a2a0, 0x00000001},
@@ -351,10 +327,6 @@ static const u32 ar9340_1p0_baseband_core[][2] = {
351 {0x0000a2c8, 0x00000000}, 327 {0x0000a2c8, 0x00000000},
352 {0x0000a2cc, 0x18c43433}, 328 {0x0000a2cc, 0x18c43433},
353 {0x0000a2d4, 0x00000000}, 329 {0x0000a2d4, 0x00000000},
354 {0x0000a2dc, 0x00000000},
355 {0x0000a2e0, 0x00000000},
356 {0x0000a2e4, 0x00000000},
357 {0x0000a2e8, 0x00000000},
358 {0x0000a2ec, 0x00000000}, 330 {0x0000a2ec, 0x00000000},
359 {0x0000a2f0, 0x00000000}, 331 {0x0000a2f0, 0x00000000},
360 {0x0000a2f4, 0x00000000}, 332 {0x0000a2f4, 0x00000000},
@@ -385,7 +357,7 @@ static const u32 ar9340_1p0_baseband_core[][2] = {
385 {0x0000a3e8, 0x20202020}, 357 {0x0000a3e8, 0x20202020},
386 {0x0000a3ec, 0x20202020}, 358 {0x0000a3ec, 0x20202020},
387 {0x0000a3f0, 0x00000000}, 359 {0x0000a3f0, 0x00000000},
388 {0x0000a3f4, 0x00000246}, 360 {0x0000a3f4, 0x00000000},
389 {0x0000a3f8, 0x0cdbd380}, 361 {0x0000a3f8, 0x0cdbd380},
390 {0x0000a3fc, 0x000f0f01}, 362 {0x0000a3fc, 0x000f0f01},
391 {0x0000a400, 0x8fa91f01}, 363 {0x0000a400, 0x8fa91f01},
@@ -402,33 +374,17 @@ static const u32 ar9340_1p0_baseband_core[][2] = {
402 {0x0000a430, 0x1ce739ce}, 374 {0x0000a430, 0x1ce739ce},
403 {0x0000a434, 0x00000000}, 375 {0x0000a434, 0x00000000},
404 {0x0000a438, 0x00001801}, 376 {0x0000a438, 0x00001801},
405 {0x0000a43c, 0x00000000}, 377 {0x0000a43c, 0x00100000},
406 {0x0000a440, 0x00000000}, 378 {0x0000a440, 0x00000000},
407 {0x0000a444, 0x00000000}, 379 {0x0000a444, 0x00000000},
408 {0x0000a448, 0x04000080}, 380 {0x0000a448, 0x05000080},
409 {0x0000a44c, 0x00000001}, 381 {0x0000a44c, 0x00000001},
410 {0x0000a450, 0x00010000}, 382 {0x0000a450, 0x00010000},
411 {0x0000a458, 0x00000000}, 383 {0x0000a458, 0x00000000},
412 {0x0000a600, 0x00000000},
413 {0x0000a604, 0x00000000},
414 {0x0000a608, 0x00000000},
415 {0x0000a60c, 0x00000000},
416 {0x0000a610, 0x00000000},
417 {0x0000a614, 0x00000000},
418 {0x0000a618, 0x00000000},
419 {0x0000a61c, 0x00000000},
420 {0x0000a620, 0x00000000},
421 {0x0000a624, 0x00000000},
422 {0x0000a628, 0x00000000},
423 {0x0000a62c, 0x00000000},
424 {0x0000a630, 0x00000000},
425 {0x0000a634, 0x00000000},
426 {0x0000a638, 0x00000000},
427 {0x0000a63c, 0x00000000},
428 {0x0000a640, 0x00000000}, 384 {0x0000a640, 0x00000000},
429 {0x0000a644, 0x3fad9d74}, 385 {0x0000a644, 0x3fad9d74},
430 {0x0000a648, 0x0048060a}, 386 {0x0000a648, 0x0048060a},
431 {0x0000a64c, 0x00000637}, 387 {0x0000a64c, 0x00003c37},
432 {0x0000a670, 0x03020100}, 388 {0x0000a670, 0x03020100},
433 {0x0000a674, 0x09080504}, 389 {0x0000a674, 0x09080504},
434 {0x0000a678, 0x0d0c0b0a}, 390 {0x0000a678, 0x0d0c0b0a},
@@ -451,10 +407,6 @@ static const u32 ar9340_1p0_baseband_core[][2] = {
451 {0x0000a8f4, 0x00000000}, 407 {0x0000a8f4, 0x00000000},
452 {0x0000b2d0, 0x00000080}, 408 {0x0000b2d0, 0x00000080},
453 {0x0000b2d4, 0x00000000}, 409 {0x0000b2d4, 0x00000000},
454 {0x0000b2dc, 0x00000000},
455 {0x0000b2e0, 0x00000000},
456 {0x0000b2e4, 0x00000000},
457 {0x0000b2e8, 0x00000000},
458 {0x0000b2ec, 0x00000000}, 410 {0x0000b2ec, 0x00000000},
459 {0x0000b2f0, 0x00000000}, 411 {0x0000b2f0, 0x00000000},
460 {0x0000b2f4, 0x00000000}, 412 {0x0000b2f4, 0x00000000},
@@ -465,80 +417,108 @@ static const u32 ar9340_1p0_baseband_core[][2] = {
465}; 417};
466 418
467static const u32 ar9340Modes_high_power_tx_gain_table_1p0[][5] = { 419static const u32 ar9340Modes_high_power_tx_gain_table_1p0[][5] = {
468 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 420 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
421 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
422 {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
423 {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
424 {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
425 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
426 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
427 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
428 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
429 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
430 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
431 {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
432 {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
433 {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
434 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
435 {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
436 {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
437 {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
438 {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
439 {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
440 {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
441 {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
442 {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
443 {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
444 {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
469 {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9}, 445 {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
470 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, 446 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
471 {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002}, 447 {0x0000a504, 0x04002222, 0x04002222, 0x02000001, 0x02000001},
472 {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004}, 448 {0x0000a508, 0x09002421, 0x09002421, 0x05000003, 0x05000003},
473 {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200}, 449 {0x0000a50c, 0x0d002621, 0x0d002621, 0x0a000005, 0x0a000005},
474 {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202}, 450 {0x0000a510, 0x13004620, 0x13004620, 0x0e000201, 0x0e000201},
475 {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400}, 451 {0x0000a514, 0x19004a20, 0x19004a20, 0x11000203, 0x11000203},
476 {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402}, 452 {0x0000a518, 0x1d004e20, 0x1d004e20, 0x14000401, 0x14000401},
477 {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404}, 453 {0x0000a51c, 0x21005420, 0x21005420, 0x18000403, 0x18000403},
478 {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603}, 454 {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000602, 0x1b000602},
479 {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02}, 455 {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000802, 0x1f000802},
480 {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04}, 456 {0x0000a528, 0x2f005e42, 0x2f005e42, 0x21000620, 0x21000620},
481 {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20}, 457 {0x0000a52c, 0x33005e44, 0x33005e44, 0x25000820, 0x25000820},
482 {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20}, 458 {0x0000a530, 0x38005e65, 0x38005e65, 0x29000822, 0x29000822},
483 {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22}, 459 {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2d000824, 0x2d000824},
484 {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24}, 460 {0x0000a538, 0x40005e6b, 0x40005e6b, 0x30000828, 0x30000828},
485 {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640}, 461 {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x3400082a, 0x3400082a},
486 {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660}, 462 {0x0000a540, 0x49005e72, 0x49005e72, 0x38000849, 0x38000849},
487 {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861}, 463 {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b000a2c, 0x3b000a2c},
488 {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81}, 464 {0x0000a548, 0x53005f12, 0x53005f12, 0x3e000e2b, 0x3e000e2b},
489 {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42001a83, 0x42001a83}, 465 {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42000e2d, 0x42000e2d},
490 {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84}, 466 {0x0000a550, 0x5e025f12, 0x5e025f12, 0x4500124a, 0x4500124a},
491 {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3}, 467 {0x0000a554, 0x61027f12, 0x61027f12, 0x4900124c, 0x4900124c},
492 {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5}, 468 {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c00126c, 0x4c00126c},
493 {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9}, 469 {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x4f00128c, 0x4f00128c},
494 {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb}, 470 {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x52001290, 0x52001290},
495 {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, 471 {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001292, 0x56001292},
496 {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, 472 {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001292, 0x56001292},
497 {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, 473 {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001292, 0x56001292},
498 {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, 474 {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001292, 0x56001292},
499 {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, 475 {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001292, 0x56001292},
500 {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, 476 {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001292, 0x56001292},
501 {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, 477 {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001292, 0x56001292},
502 {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000}, 478 {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
503 {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002}, 479 {0x0000a584, 0x04802222, 0x04802222, 0x02800001, 0x02800001},
504 {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004}, 480 {0x0000a588, 0x09802421, 0x09802421, 0x05800003, 0x05800003},
505 {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200}, 481 {0x0000a58c, 0x0d802621, 0x0d802621, 0x0a800005, 0x0a800005},
506 {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202}, 482 {0x0000a590, 0x13804620, 0x13804620, 0x0e800201, 0x0e800201},
507 {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400}, 483 {0x0000a594, 0x19804a20, 0x19804a20, 0x11800203, 0x11800203},
508 {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402}, 484 {0x0000a598, 0x1d804e20, 0x1d804e20, 0x14800401, 0x14800401},
509 {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404}, 485 {0x0000a59c, 0x21805420, 0x21805420, 0x18800403, 0x18800403},
510 {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603}, 486 {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800602, 0x1b800602},
511 {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02}, 487 {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800802, 0x1f800802},
512 {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04}, 488 {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x21800620, 0x21800620},
513 {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20}, 489 {0x0000a5ac, 0x33805e44, 0x33805e44, 0x25800820, 0x25800820},
514 {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20}, 490 {0x0000a5b0, 0x38805e65, 0x38805e65, 0x29800822, 0x29800822},
515 {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22}, 491 {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2d800824, 0x2d800824},
516 {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24}, 492 {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x30800828, 0x30800828},
517 {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640}, 493 {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x3480082a, 0x3480082a},
518 {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660}, 494 {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38800849, 0x38800849},
519 {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861}, 495 {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b800a2c, 0x3b800a2c},
520 {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81}, 496 {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e800e2b, 0x3e800e2b},
521 {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83}, 497 {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42800e2d, 0x42800e2d},
522 {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84}, 498 {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x4580124a, 0x4580124a},
523 {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3}, 499 {0x0000a5d4, 0x61827f12, 0x61827f12, 0x4980124c, 0x4980124c},
524 {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5}, 500 {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c80126c, 0x4c80126c},
525 {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9}, 501 {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x4f80128c, 0x4f80128c},
526 {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb}, 502 {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x52801290, 0x52801290},
527 {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 503 {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801292, 0x56801292},
528 {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 504 {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801292, 0x56801292},
529 {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 505 {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801292, 0x56801292},
530 {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 506 {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801292, 0x56801292},
531 {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 507 {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801292, 0x56801292},
532 {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 508 {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801292, 0x56801292},
533 {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 509 {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801292, 0x56801292},
534 {0x00016044, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db}, 510 {0x00016044, 0x056db2db, 0x056db2db, 0x022492db, 0x022492db},
535 {0x00016048, 0x24925266, 0x24925266, 0x24925266, 0x24925266}, 511 {0x00016048, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
536 {0x00016444, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db}, 512 {0x00016444, 0x056db2db, 0x056db2db, 0x022492db, 0x022492db},
537 {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266}, 513 {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
538}; 514};
539 515
540static const u32 ar9340Modes_high_ob_db_tx_gain_table_1p0[][5] = { 516static const u32 ar9340Modes_high_ob_db_tx_gain_table_1p0[][5] = {
541 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 517 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
518 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
519 {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
520 {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
521 {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
542 {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9}, 522 {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
543 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, 523 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
544 {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002}, 524 {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
@@ -559,7 +539,7 @@ static const u32 ar9340Modes_high_ob_db_tx_gain_table_1p0[][5] = {
559 {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660}, 539 {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
560 {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861}, 540 {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
561 {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81}, 541 {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
562 {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42001a83, 0x42001a83}, 542 {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
563 {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84}, 543 {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
564 {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3}, 544 {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
565 {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5}, 545 {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
@@ -604,13 +584,43 @@ static const u32 ar9340Modes_high_ob_db_tx_gain_table_1p0[][5] = {
604 {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 584 {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
605 {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 585 {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
606 {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 586 {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
587 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
588 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
589 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
590 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
591 {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
592 {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
593 {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
594 {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
595 {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
596 {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
597 {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
598 {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
599 {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
600 {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
601 {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
602 {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
603 {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
604 {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
605 {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
606 {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
607 {0x00016044, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4}, 607 {0x00016044, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4},
608 {0x00016048, 0x8e481266, 0x8e481266, 0x8e481266, 0x8e481266}, 608 {0x00016048, 0x8e481666, 0x8e481666, 0x8e481266, 0x8e481266},
609 {0x00016280, 0x01000015, 0x01000015, 0x01001015, 0x01001015},
609 {0x00016444, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4}, 610 {0x00016444, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4},
610 {0x00016448, 0x8e481266, 0x8e481266, 0x8e481266, 0x8e481266}, 611 {0x00016448, 0x8e481666, 0x8e481666, 0x8e481266, 0x8e481266},
611}; 612};
613
612static const u32 ar9340Modes_ub124_tx_gain_table_1p0[][5] = { 614static const u32 ar9340Modes_ub124_tx_gain_table_1p0[][5] = {
613 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 615 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
616 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
617 {0x00009820, 0x206a022e, 0x206a022e, 0x206a00ae, 0x206a00ae},
618 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
619 {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec82d2e, 0x7ec82d2e},
620 {0x0000a2dc, 0xfef5d402, 0xfef5d402, 0xfdab5b52, 0xfdab5b52},
621 {0x0000a2e0, 0xfe896600, 0xfe896600, 0xfd339c84, 0xfd339c84},
622 {0x0000a2e4, 0xff01f800, 0xff01f800, 0xfec3e000, 0xfec3e000},
623 {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffc0000, 0xfffc0000},
614 {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9}, 624 {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
615 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, 625 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
616 {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002}, 626 {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
@@ -676,15 +686,34 @@ static const u32 ar9340Modes_ub124_tx_gain_table_1p0[][5] = {
676 {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 686 {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
677 {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 687 {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
678 {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 688 {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
679 {0x00016044, 0x036db2db, 0x036db2db, 0x036db2db, 0x036db2db}, 689 {0x00016044, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4},
680 {0x00016048, 0x69b65266, 0x69b65266, 0x69b65266, 0x69b65266}, 690 {0x00016048, 0x8e480086, 0x8e480086, 0x8e480086, 0x8e480086},
681 {0x00016444, 0x036db2db, 0x036db2db, 0x036db2db, 0x036db2db}, 691 {0x00016444, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4},
682 {0x00016448, 0x69b65266, 0x69b65266, 0x69b65266, 0x69b65266}, 692 {0x00016448, 0x8e480086, 0x8e480086, 0x8e480086, 0x8e480086},
693 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
694 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
695 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
696 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
697 {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
698 {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
699 {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
700 {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
701 {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
702 {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
703 {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
704 {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
705 {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
706 {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
707 {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
708 {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
709 {0x0000b2dc, 0xfef5d402, 0xfef5d402, 0xfdab5b52, 0xfdab5b52},
710 {0x0000b2e0, 0xfe896600, 0xfe896600, 0xfd339c84, 0xfd339c84},
711 {0x0000b2e4, 0xff01f800, 0xff01f800, 0xfec3e000, 0xfec3e000},
712 {0x0000b2e8, 0xfffe0000, 0xfffe0000, 0xfffc0000, 0xfffc0000},
683}; 713};
684 714
685
686static const u32 ar9340Common_rx_gain_table_1p0[][2] = { 715static const u32 ar9340Common_rx_gain_table_1p0[][2] = {
687 /* Addr allmodes */ 716 /* Addr allmodes */
688 {0x0000a000, 0x00010000}, 717 {0x0000a000, 0x00010000},
689 {0x0000a004, 0x00030002}, 718 {0x0000a004, 0x00030002},
690 {0x0000a008, 0x00050004}, 719 {0x0000a008, 0x00050004},
@@ -845,14 +874,14 @@ static const u32 ar9340Common_rx_gain_table_1p0[][2] = {
845 {0x0000b074, 0x00000000}, 874 {0x0000b074, 0x00000000},
846 {0x0000b078, 0x00000000}, 875 {0x0000b078, 0x00000000},
847 {0x0000b07c, 0x00000000}, 876 {0x0000b07c, 0x00000000},
848 {0x0000b080, 0x32323232}, 877 {0x0000b080, 0x23232323},
849 {0x0000b084, 0x2f2f3232}, 878 {0x0000b084, 0x21232323},
850 {0x0000b088, 0x23282a2d}, 879 {0x0000b088, 0x19191c1e},
851 {0x0000b08c, 0x1c1e2123}, 880 {0x0000b08c, 0x12141417},
852 {0x0000b090, 0x14171919}, 881 {0x0000b090, 0x07070e0e},
853 {0x0000b094, 0x0e0e1214}, 882 {0x0000b094, 0x03030305},
854 {0x0000b098, 0x03050707}, 883 {0x0000b098, 0x00000003},
855 {0x0000b09c, 0x00030303}, 884 {0x0000b09c, 0x00000000},
856 {0x0000b0a0, 0x00000000}, 885 {0x0000b0a0, 0x00000000},
857 {0x0000b0a4, 0x00000000}, 886 {0x0000b0a4, 0x00000000},
858 {0x0000b0a8, 0x00000000}, 887 {0x0000b0a8, 0x00000000},
@@ -944,7 +973,11 @@ static const u32 ar9340Common_rx_gain_table_1p0[][2] = {
944}; 973};
945 974
946static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = { 975static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
947 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 976 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
977 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
978 {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
979 {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
980 {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
948 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, 981 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
949 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 982 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
950 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002}, 983 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
@@ -952,8 +985,8 @@ static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
952 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200}, 985 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
953 {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202}, 986 {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
954 {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400}, 987 {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
955 {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402}, 988 {0x0000a518, 0x21002220, 0x21002220, 0x16000402, 0x16000402},
956 {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404}, 989 {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404},
957 {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603}, 990 {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
958 {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02}, 991 {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
959 {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04}, 992 {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
@@ -965,19 +998,19 @@ static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
965 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660}, 998 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
966 {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861}, 999 {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
967 {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81}, 1000 {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
968 {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83}, 1001 {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x47001a83, 0x47001a83},
969 {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84}, 1002 {0x0000a550, 0x61024a6c, 0x61024a6c, 0x4a001c84, 0x4a001c84},
970 {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3}, 1003 {0x0000a554, 0x66026a6c, 0x66026a6c, 0x4e001ce3, 0x4e001ce3},
971 {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5}, 1004 {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x52001ce5, 0x52001ce5},
972 {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9}, 1005 {0x0000a55c, 0x7002708c, 0x7002708c, 0x56001ce9, 0x56001ce9},
973 {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb}, 1006 {0x0000a560, 0x7302b08a, 0x7302b08a, 0x5a001ceb, 0x5a001ceb},
974 {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, 1007 {0x0000a564, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
975 {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, 1008 {0x0000a568, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
976 {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, 1009 {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
977 {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, 1010 {0x0000a570, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
978 {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, 1011 {0x0000a574, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
979 {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, 1012 {0x0000a578, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
980 {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, 1013 {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
981 {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000}, 1014 {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
982 {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002}, 1015 {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
983 {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004}, 1016 {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
@@ -1010,14 +1043,40 @@ static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
1010 {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec}, 1043 {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
1011 {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec}, 1044 {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
1012 {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec}, 1045 {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
1046 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1047 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1048 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1049 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1050 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1051 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
1052 {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
1053 {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
1054 {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
1055 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
1056 {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
1057 {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
1058 {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
1059 {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
1060 {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
1061 {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
1062 {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
1063 {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
1064 {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
1065 {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
1013 {0x00016044, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db}, 1066 {0x00016044, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db},
1014 {0x00016048, 0x24925266, 0x24925266, 0x24925266, 0x24925266}, 1067 {0x00016048, 0x24925666, 0x24925666, 0x24925266, 0x24925266},
1068 {0x00016280, 0x01000015, 0x01000015, 0x01001015, 0x01001015},
1069 {0x00016288, 0xf0318000, 0xf0318000, 0xf0318000, 0xf0318000},
1015 {0x00016444, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db}, 1070 {0x00016444, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db},
1016 {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266}, 1071 {0x00016448, 0x24925666, 0x24925666, 0x24925266, 0x24925266},
1017}; 1072};
1018 1073
1019static const u32 ar9340Modes_mixed_ob_db_tx_gain_table_1p0[][5] = { 1074static const u32 ar9340Modes_mixed_ob_db_tx_gain_table_1p0[][5] = {
1020 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1075 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1076 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
1077 {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
1078 {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
1079 {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
1021 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, 1080 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
1022 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 1081 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1023 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002}, 1082 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
@@ -1025,8 +1084,8 @@ static const u32 ar9340Modes_mixed_ob_db_tx_gain_table_1p0[][5] = {
1025 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200}, 1084 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
1026 {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202}, 1085 {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
1027 {0x0000a514, 0x1c000223, 0x1c000223, 0x11000400, 0x11000400}, 1086 {0x0000a514, 0x1c000223, 0x1c000223, 0x11000400, 0x11000400},
1028 {0x0000a518, 0x21020220, 0x21020220, 0x15000402, 0x15000402}, 1087 {0x0000a518, 0x21002220, 0x21002220, 0x15000402, 0x15000402},
1029 {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404}, 1088 {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404},
1030 {0x0000a520, 0x2b022220, 0x2b022220, 0x1b000603, 0x1b000603}, 1089 {0x0000a520, 0x2b022220, 0x2b022220, 0x1b000603, 0x1b000603},
1031 {0x0000a524, 0x2f022222, 0x2f022222, 0x1f000a02, 0x1f000a02}, 1090 {0x0000a524, 0x2f022222, 0x2f022222, 0x1f000a02, 0x1f000a02},
1032 {0x0000a528, 0x34022225, 0x34022225, 0x23000a04, 0x23000a04}, 1091 {0x0000a528, 0x34022225, 0x34022225, 0x23000a04, 0x23000a04},
@@ -1038,19 +1097,19 @@ static const u32 ar9340Modes_mixed_ob_db_tx_gain_table_1p0[][5] = {
1038 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38001660, 0x38001660}, 1097 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38001660, 0x38001660},
1039 {0x0000a544, 0x5302266c, 0x5302266c, 0x3b001861, 0x3b001861}, 1098 {0x0000a544, 0x5302266c, 0x5302266c, 0x3b001861, 0x3b001861},
1040 {0x0000a548, 0x5702286c, 0x5702286c, 0x3e001a81, 0x3e001a81}, 1099 {0x0000a548, 0x5702286c, 0x5702286c, 0x3e001a81, 0x3e001a81},
1041 {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x42001a83, 0x42001a83}, 1100 {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x42001a83, 0x42001a83},
1042 {0x0000a550, 0x61042a6c, 0x61042a6c, 0x44001c84, 0x44001c84}, 1101 {0x0000a550, 0x61024a6c, 0x61024a6c, 0x44001c84, 0x44001c84},
1043 {0x0000a554, 0x66062a6c, 0x66062a6c, 0x48001ce3, 0x48001ce3}, 1102 {0x0000a554, 0x66026a6c, 0x66026a6c, 0x48001ce3, 0x48001ce3},
1044 {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x4c001ce5, 0x4c001ce5}, 1103 {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x4c001ce5, 0x4c001ce5},
1045 {0x0000a55c, 0x7006308c, 0x7006308c, 0x50001ce9, 0x50001ce9}, 1104 {0x0000a55c, 0x7002708c, 0x7002708c, 0x50001ce9, 0x50001ce9},
1046 {0x0000a560, 0x730a308a, 0x730a308a, 0x54001ceb, 0x54001ceb}, 1105 {0x0000a560, 0x7302b08a, 0x7302b08a, 0x54001ceb, 0x54001ceb},
1047 {0x0000a564, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec}, 1106 {0x0000a564, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
1048 {0x0000a568, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec}, 1107 {0x0000a568, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
1049 {0x0000a56c, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec}, 1108 {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
1050 {0x0000a570, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec}, 1109 {0x0000a570, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
1051 {0x0000a574, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec}, 1110 {0x0000a574, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
1052 {0x0000a578, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec}, 1111 {0x0000a578, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
1053 {0x0000a57c, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec}, 1112 {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
1054 {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000}, 1113 {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
1055 {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002}, 1114 {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
1056 {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004}, 1115 {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
@@ -1083,14 +1142,36 @@ static const u32 ar9340Modes_mixed_ob_db_tx_gain_table_1p0[][5] = {
1083 {0x0000a5f4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, 1142 {0x0000a5f4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
1084 {0x0000a5f8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, 1143 {0x0000a5f8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
1085 {0x0000a5fc, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, 1144 {0x0000a5fc, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
1145 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1146 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1147 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1148 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1149 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1150 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
1151 {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
1152 {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
1153 {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
1154 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
1155 {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
1156 {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
1157 {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
1158 {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
1159 {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
1160 {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
1161 {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
1162 {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
1163 {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
1164 {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
1086 {0x00016044, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4}, 1165 {0x00016044, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
1087 {0x00016048, 0x24927266, 0x24927266, 0x8e483266, 0x8e483266}, 1166 {0x00016048, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
1167 {0x00016280, 0x01000015, 0x01000015, 0x01001015, 0x01001015},
1168 {0x00016288, 0x30318000, 0x30318000, 0x00318000, 0x00318000},
1088 {0x00016444, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4}, 1169 {0x00016444, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
1089 {0x00016448, 0x24927266, 0x24927266, 0x8e482266, 0x8e482266}, 1170 {0x00016448, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
1090}; 1171};
1091 1172
1092static const u32 ar9340_1p0_mac_core[][2] = { 1173static const u32 ar9340_1p0_mac_core[][2] = {
1093 /* Addr allmodes */ 1174 /* Addr allmodes */
1094 {0x00000008, 0x00000000}, 1175 {0x00000008, 0x00000000},
1095 {0x00000030, 0x00020085}, 1176 {0x00000030, 0x00020085},
1096 {0x00000034, 0x00000005}, 1177 {0x00000034, 0x00000005},
@@ -1119,6 +1200,7 @@ static const u32 ar9340_1p0_mac_core[][2] = {
1119 {0x00008004, 0x00000000}, 1200 {0x00008004, 0x00000000},
1120 {0x00008008, 0x00000000}, 1201 {0x00008008, 0x00000000},
1121 {0x0000800c, 0x00000000}, 1202 {0x0000800c, 0x00000000},
1203 {0x00008010, 0x00080800},
1122 {0x00008018, 0x00000000}, 1204 {0x00008018, 0x00000000},
1123 {0x00008020, 0x00000000}, 1205 {0x00008020, 0x00000000},
1124 {0x00008038, 0x00000000}, 1206 {0x00008038, 0x00000000},
@@ -1146,7 +1228,7 @@ static const u32 ar9340_1p0_mac_core[][2] = {
1146 {0x000080bc, 0x00000000}, 1228 {0x000080bc, 0x00000000},
1147 {0x000080c0, 0x2a800000}, 1229 {0x000080c0, 0x2a800000},
1148 {0x000080c4, 0x06900168}, 1230 {0x000080c4, 0x06900168},
1149 {0x000080c8, 0x13881c20}, 1231 {0x000080c8, 0x13881c22},
1150 {0x000080cc, 0x01f40000}, 1232 {0x000080cc, 0x01f40000},
1151 {0x000080d0, 0x00252500}, 1233 {0x000080d0, 0x00252500},
1152 {0x000080d4, 0x00a00000}, 1234 {0x000080d4, 0x00a00000},
@@ -1250,276 +1332,17 @@ static const u32 ar9340_1p0_mac_core[][2] = {
1250 {0x000083c4, 0x00000000}, 1332 {0x000083c4, 0x00000000},
1251 {0x000083c8, 0x00000000}, 1333 {0x000083c8, 0x00000000},
1252 {0x000083cc, 0x00000200}, 1334 {0x000083cc, 0x00000200},
1253 {0x000083d0, 0x000301ff}, 1335 {0x000083d0, 0x000101ff},
1254}; 1336};
1255 1337
1256static const u32 ar9340Common_wo_xlna_rx_gain_table_1p0[][2] = { 1338#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2
1257 /* Addr allmodes */
1258 {0x0000a000, 0x00010000},
1259 {0x0000a004, 0x00030002},
1260 {0x0000a008, 0x00050004},
1261 {0x0000a00c, 0x00810080},
1262 {0x0000a010, 0x00830082},
1263 {0x0000a014, 0x01810180},
1264 {0x0000a018, 0x01830182},
1265 {0x0000a01c, 0x01850184},
1266 {0x0000a020, 0x01890188},
1267 {0x0000a024, 0x018b018a},
1268 {0x0000a028, 0x018d018c},
1269 {0x0000a02c, 0x03820190},
1270 {0x0000a030, 0x03840383},
1271 {0x0000a034, 0x03880385},
1272 {0x0000a038, 0x038a0389},
1273 {0x0000a03c, 0x038c038b},
1274 {0x0000a040, 0x0390038d},
1275 {0x0000a044, 0x03920391},
1276 {0x0000a048, 0x03940393},
1277 {0x0000a04c, 0x03960395},
1278 {0x0000a050, 0x00000000},
1279 {0x0000a054, 0x00000000},
1280 {0x0000a058, 0x00000000},
1281 {0x0000a05c, 0x00000000},
1282 {0x0000a060, 0x00000000},
1283 {0x0000a064, 0x00000000},
1284 {0x0000a068, 0x00000000},
1285 {0x0000a06c, 0x00000000},
1286 {0x0000a070, 0x00000000},
1287 {0x0000a074, 0x00000000},
1288 {0x0000a078, 0x00000000},
1289 {0x0000a07c, 0x00000000},
1290 {0x0000a080, 0x29292929},
1291 {0x0000a084, 0x29292929},
1292 {0x0000a088, 0x29292929},
1293 {0x0000a08c, 0x29292929},
1294 {0x0000a090, 0x22292929},
1295 {0x0000a094, 0x1d1d2222},
1296 {0x0000a098, 0x0c111117},
1297 {0x0000a09c, 0x00030303},
1298 {0x0000a0a0, 0x00000000},
1299 {0x0000a0a4, 0x00000000},
1300 {0x0000a0a8, 0x00000000},
1301 {0x0000a0ac, 0x00000000},
1302 {0x0000a0b0, 0x00000000},
1303 {0x0000a0b4, 0x00000000},
1304 {0x0000a0b8, 0x00000000},
1305 {0x0000a0bc, 0x00000000},
1306 {0x0000a0c0, 0x001f0000},
1307 {0x0000a0c4, 0x01000101},
1308 {0x0000a0c8, 0x011e011f},
1309 {0x0000a0cc, 0x011c011d},
1310 {0x0000a0d0, 0x02030204},
1311 {0x0000a0d4, 0x02010202},
1312 {0x0000a0d8, 0x021f0200},
1313 {0x0000a0dc, 0x0302021e},
1314 {0x0000a0e0, 0x03000301},
1315 {0x0000a0e4, 0x031e031f},
1316 {0x0000a0e8, 0x0402031d},
1317 {0x0000a0ec, 0x04000401},
1318 {0x0000a0f0, 0x041e041f},
1319 {0x0000a0f4, 0x0502041d},
1320 {0x0000a0f8, 0x05000501},
1321 {0x0000a0fc, 0x051e051f},
1322 {0x0000a100, 0x06010602},
1323 {0x0000a104, 0x061f0600},
1324 {0x0000a108, 0x061d061e},
1325 {0x0000a10c, 0x07020703},
1326 {0x0000a110, 0x07000701},
1327 {0x0000a114, 0x00000000},
1328 {0x0000a118, 0x00000000},
1329 {0x0000a11c, 0x00000000},
1330 {0x0000a120, 0x00000000},
1331 {0x0000a124, 0x00000000},
1332 {0x0000a128, 0x00000000},
1333 {0x0000a12c, 0x00000000},
1334 {0x0000a130, 0x00000000},
1335 {0x0000a134, 0x00000000},
1336 {0x0000a138, 0x00000000},
1337 {0x0000a13c, 0x00000000},
1338 {0x0000a140, 0x001f0000},
1339 {0x0000a144, 0x01000101},
1340 {0x0000a148, 0x011e011f},
1341 {0x0000a14c, 0x011c011d},
1342 {0x0000a150, 0x02030204},
1343 {0x0000a154, 0x02010202},
1344 {0x0000a158, 0x021f0200},
1345 {0x0000a15c, 0x0302021e},
1346 {0x0000a160, 0x03000301},
1347 {0x0000a164, 0x031e031f},
1348 {0x0000a168, 0x0402031d},
1349 {0x0000a16c, 0x04000401},
1350 {0x0000a170, 0x041e041f},
1351 {0x0000a174, 0x0502041d},
1352 {0x0000a178, 0x05000501},
1353 {0x0000a17c, 0x051e051f},
1354 {0x0000a180, 0x06010602},
1355 {0x0000a184, 0x061f0600},
1356 {0x0000a188, 0x061d061e},
1357 {0x0000a18c, 0x07020703},
1358 {0x0000a190, 0x07000701},
1359 {0x0000a194, 0x00000000},
1360 {0x0000a198, 0x00000000},
1361 {0x0000a19c, 0x00000000},
1362 {0x0000a1a0, 0x00000000},
1363 {0x0000a1a4, 0x00000000},
1364 {0x0000a1a8, 0x00000000},
1365 {0x0000a1ac, 0x00000000},
1366 {0x0000a1b0, 0x00000000},
1367 {0x0000a1b4, 0x00000000},
1368 {0x0000a1b8, 0x00000000},
1369 {0x0000a1bc, 0x00000000},
1370 {0x0000a1c0, 0x00000000},
1371 {0x0000a1c4, 0x00000000},
1372 {0x0000a1c8, 0x00000000},
1373 {0x0000a1cc, 0x00000000},
1374 {0x0000a1d0, 0x00000000},
1375 {0x0000a1d4, 0x00000000},
1376 {0x0000a1d8, 0x00000000},
1377 {0x0000a1dc, 0x00000000},
1378 {0x0000a1e0, 0x00000000},
1379 {0x0000a1e4, 0x00000000},
1380 {0x0000a1e8, 0x00000000},
1381 {0x0000a1ec, 0x00000000},
1382 {0x0000a1f0, 0x00000396},
1383 {0x0000a1f4, 0x00000396},
1384 {0x0000a1f8, 0x00000396},
1385 {0x0000a1fc, 0x00000196},
1386 {0x0000b000, 0x00010000},
1387 {0x0000b004, 0x00030002},
1388 {0x0000b008, 0x00050004},
1389 {0x0000b00c, 0x00810080},
1390 {0x0000b010, 0x00830082},
1391 {0x0000b014, 0x01810180},
1392 {0x0000b018, 0x01830182},
1393 {0x0000b01c, 0x01850184},
1394 {0x0000b020, 0x02810280},
1395 {0x0000b024, 0x02830282},
1396 {0x0000b028, 0x02850284},
1397 {0x0000b02c, 0x02890288},
1398 {0x0000b030, 0x028b028a},
1399 {0x0000b034, 0x0388028c},
1400 {0x0000b038, 0x038a0389},
1401 {0x0000b03c, 0x038c038b},
1402 {0x0000b040, 0x0390038d},
1403 {0x0000b044, 0x03920391},
1404 {0x0000b048, 0x03940393},
1405 {0x0000b04c, 0x03960395},
1406 {0x0000b050, 0x00000000},
1407 {0x0000b054, 0x00000000},
1408 {0x0000b058, 0x00000000},
1409 {0x0000b05c, 0x00000000},
1410 {0x0000b060, 0x00000000},
1411 {0x0000b064, 0x00000000},
1412 {0x0000b068, 0x00000000},
1413 {0x0000b06c, 0x00000000},
1414 {0x0000b070, 0x00000000},
1415 {0x0000b074, 0x00000000},
1416 {0x0000b078, 0x00000000},
1417 {0x0000b07c, 0x00000000},
1418 {0x0000b080, 0x32323232},
1419 {0x0000b084, 0x2f2f3232},
1420 {0x0000b088, 0x23282a2d},
1421 {0x0000b08c, 0x1c1e2123},
1422 {0x0000b090, 0x14171919},
1423 {0x0000b094, 0x0e0e1214},
1424 {0x0000b098, 0x03050707},
1425 {0x0000b09c, 0x00030303},
1426 {0x0000b0a0, 0x00000000},
1427 {0x0000b0a4, 0x00000000},
1428 {0x0000b0a8, 0x00000000},
1429 {0x0000b0ac, 0x00000000},
1430 {0x0000b0b0, 0x00000000},
1431 {0x0000b0b4, 0x00000000},
1432 {0x0000b0b8, 0x00000000},
1433 {0x0000b0bc, 0x00000000},
1434 {0x0000b0c0, 0x003f0020},
1435 {0x0000b0c4, 0x00400041},
1436 {0x0000b0c8, 0x0140005f},
1437 {0x0000b0cc, 0x0160015f},
1438 {0x0000b0d0, 0x017e017f},
1439 {0x0000b0d4, 0x02410242},
1440 {0x0000b0d8, 0x025f0240},
1441 {0x0000b0dc, 0x027f0260},
1442 {0x0000b0e0, 0x0341027e},
1443 {0x0000b0e4, 0x035f0340},
1444 {0x0000b0e8, 0x037f0360},
1445 {0x0000b0ec, 0x04400441},
1446 {0x0000b0f0, 0x0460045f},
1447 {0x0000b0f4, 0x0541047f},
1448 {0x0000b0f8, 0x055f0540},
1449 {0x0000b0fc, 0x057f0560},
1450 {0x0000b100, 0x06400641},
1451 {0x0000b104, 0x0660065f},
1452 {0x0000b108, 0x067e067f},
1453 {0x0000b10c, 0x07410742},
1454 {0x0000b110, 0x075f0740},
1455 {0x0000b114, 0x077f0760},
1456 {0x0000b118, 0x07800781},
1457 {0x0000b11c, 0x07a0079f},
1458 {0x0000b120, 0x07c107bf},
1459 {0x0000b124, 0x000007c0},
1460 {0x0000b128, 0x00000000},
1461 {0x0000b12c, 0x00000000},
1462 {0x0000b130, 0x00000000},
1463 {0x0000b134, 0x00000000},
1464 {0x0000b138, 0x00000000},
1465 {0x0000b13c, 0x00000000},
1466 {0x0000b140, 0x003f0020},
1467 {0x0000b144, 0x00400041},
1468 {0x0000b148, 0x0140005f},
1469 {0x0000b14c, 0x0160015f},
1470 {0x0000b150, 0x017e017f},
1471 {0x0000b154, 0x02410242},
1472 {0x0000b158, 0x025f0240},
1473 {0x0000b15c, 0x027f0260},
1474 {0x0000b160, 0x0341027e},
1475 {0x0000b164, 0x035f0340},
1476 {0x0000b168, 0x037f0360},
1477 {0x0000b16c, 0x04400441},
1478 {0x0000b170, 0x0460045f},
1479 {0x0000b174, 0x0541047f},
1480 {0x0000b178, 0x055f0540},
1481 {0x0000b17c, 0x057f0560},
1482 {0x0000b180, 0x06400641},
1483 {0x0000b184, 0x0660065f},
1484 {0x0000b188, 0x067e067f},
1485 {0x0000b18c, 0x07410742},
1486 {0x0000b190, 0x075f0740},
1487 {0x0000b194, 0x077f0760},
1488 {0x0000b198, 0x07800781},
1489 {0x0000b19c, 0x07a0079f},
1490 {0x0000b1a0, 0x07c107bf},
1491 {0x0000b1a4, 0x000007c0},
1492 {0x0000b1a8, 0x00000000},
1493 {0x0000b1ac, 0x00000000},
1494 {0x0000b1b0, 0x00000000},
1495 {0x0000b1b4, 0x00000000},
1496 {0x0000b1b8, 0x00000000},
1497 {0x0000b1bc, 0x00000000},
1498 {0x0000b1c0, 0x00000000},
1499 {0x0000b1c4, 0x00000000},
1500 {0x0000b1c8, 0x00000000},
1501 {0x0000b1cc, 0x00000000},
1502 {0x0000b1d0, 0x00000000},
1503 {0x0000b1d4, 0x00000000},
1504 {0x0000b1d8, 0x00000000},
1505 {0x0000b1dc, 0x00000000},
1506 {0x0000b1e0, 0x00000000},
1507 {0x0000b1e4, 0x00000000},
1508 {0x0000b1e8, 0x00000000},
1509 {0x0000b1ec, 0x00000000},
1510 {0x0000b1f0, 0x00000396},
1511 {0x0000b1f4, 0x00000396},
1512 {0x0000b1f8, 0x00000396},
1513 {0x0000b1fc, 0x00000196},
1514};
1515 1339
1516static const u32 ar9340_1p0_soc_preamble[][2] = { 1340static const u32 ar9340_1p0_soc_preamble[][2] = {
1517 /* Addr allmodes */ 1341 /* Addr allmodes */
1518 {0x000040a4, 0x00a0c1c9},
1519 {0x00007008, 0x00000000}, 1342 {0x00007008, 0x00000000},
1520 {0x00007020, 0x00000000}, 1343 {0x00007020, 0x00000000},
1521 {0x00007034, 0x00000002}, 1344 {0x00007034, 0x00000002},
1522 {0x00007038, 0x000004c2}, 1345 {0x00007038, 0x000004c2},
1523}; 1346};
1524 1347
1525#endif 1348#endif /* INITVALS_9340_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
index 8f406ff2c95e..4ef7dcccaa2f 100644
--- a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2010 Atheros Communications Inc. 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
3 * 4 *
4 * Permission to use, copy, modify, and/or distribute this software for any 5 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 6 * purpose with or without fee is hereby granted, provided that the above
@@ -61,7 +62,7 @@ static const u32 ar9462_2p0_baseband_postamble[][5] = {
61 {0x00009e44, 0x62321e27, 0x62321e27, 0xfe291e27, 0xfe291e27}, 62 {0x00009e44, 0x62321e27, 0x62321e27, 0xfe291e27, 0xfe291e27},
62 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012}, 63 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
63 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000}, 64 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
64 {0x0000a204, 0x013187c0, 0x013187c4, 0x013187c4, 0x013187c0}, 65 {0x0000a204, 0x01318fc0, 0x01318fc4, 0x01318fc4, 0x01318fc0},
65 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004}, 66 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
66 {0x0000a22c, 0x01026a2f, 0x01026a27, 0x01026a2f, 0x01026a2f}, 67 {0x0000a22c, 0x01026a2f, 0x01026a27, 0x01026a2f, 0x01026a2f},
67 {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b}, 68 {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b},
@@ -1007,7 +1008,7 @@ static const u32 ar9462_2p0_radio_core[][2] = {
1007 1008
1008static const u32 ar9462_2p0_soc_preamble[][2] = { 1009static const u32 ar9462_2p0_soc_preamble[][2] = {
1009 /* Addr allmodes */ 1010 /* Addr allmodes */
1010 {0x000040a4 ,0x00a0c1c9}, 1011 {0x000040a4, 0x00a0c1c9},
1011 {0x00007020, 0x00000000}, 1012 {0x00007020, 0x00000000},
1012 {0x00007034, 0x00000002}, 1013 {0x00007034, 0x00000002},
1013 {0x00007038, 0x000004c2}, 1014 {0x00007038, 0x000004c2},
diff --git a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
index d16d029f81a9..fb4497fc7a3d 100644
--- a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2010-2011 Atheros Communications Inc. 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
3 * 4 *
4 * Permission to use, copy, modify, and/or distribute this software for any 5 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 6 * purpose with or without fee is hereby granted, provided that the above
@@ -17,360 +18,151 @@
17#ifndef INITVALS_9485_H 18#ifndef INITVALS_9485_H
18#define INITVALS_9485_H 19#define INITVALS_9485_H
19 20
20static const u32 ar9485_1_1_mac_core[][2] = { 21/* AR9485 1.0 */
21 /* Addr allmodes */
22 {0x00000008, 0x00000000},
23 {0x00000030, 0x00020085},
24 {0x00000034, 0x00000005},
25 {0x00000040, 0x00000000},
26 {0x00000044, 0x00000000},
27 {0x00000048, 0x00000008},
28 {0x0000004c, 0x00000010},
29 {0x00000050, 0x00000000},
30 {0x00001040, 0x002ffc0f},
31 {0x00001044, 0x002ffc0f},
32 {0x00001048, 0x002ffc0f},
33 {0x0000104c, 0x002ffc0f},
34 {0x00001050, 0x002ffc0f},
35 {0x00001054, 0x002ffc0f},
36 {0x00001058, 0x002ffc0f},
37 {0x0000105c, 0x002ffc0f},
38 {0x00001060, 0x002ffc0f},
39 {0x00001064, 0x002ffc0f},
40 {0x000010f0, 0x00000100},
41 {0x00001270, 0x00000000},
42 {0x000012b0, 0x00000000},
43 {0x000012f0, 0x00000000},
44 {0x0000143c, 0x00000000},
45 {0x0000147c, 0x00000000},
46 {0x00008000, 0x00000000},
47 {0x00008004, 0x00000000},
48 {0x00008008, 0x00000000},
49 {0x0000800c, 0x00000000},
50 {0x00008018, 0x00000000},
51 {0x00008020, 0x00000000},
52 {0x00008038, 0x00000000},
53 {0x0000803c, 0x00000000},
54 {0x00008040, 0x00000000},
55 {0x00008044, 0x00000000},
56 {0x00008048, 0x00000000},
57 {0x0000804c, 0xffffffff},
58 {0x00008054, 0x00000000},
59 {0x00008058, 0x00000000},
60 {0x0000805c, 0x000fc78f},
61 {0x00008060, 0x0000000f},
62 {0x00008064, 0x00000000},
63 {0x00008070, 0x00000310},
64 {0x00008074, 0x00000020},
65 {0x00008078, 0x00000000},
66 {0x0000809c, 0x0000000f},
67 {0x000080a0, 0x00000000},
68 {0x000080a4, 0x02ff0000},
69 {0x000080a8, 0x0e070605},
70 {0x000080ac, 0x0000000d},
71 {0x000080b0, 0x00000000},
72 {0x000080b4, 0x00000000},
73 {0x000080b8, 0x00000000},
74 {0x000080bc, 0x00000000},
75 {0x000080c0, 0x2a800000},
76 {0x000080c4, 0x06900168},
77 {0x000080c8, 0x13881c22},
78 {0x000080cc, 0x01f40000},
79 {0x000080d0, 0x00252500},
80 {0x000080d4, 0x00a00000},
81 {0x000080d8, 0x00400000},
82 {0x000080dc, 0x00000000},
83 {0x000080e0, 0xffffffff},
84 {0x000080e4, 0x0000ffff},
85 {0x000080e8, 0x3f3f3f3f},
86 {0x000080ec, 0x00000000},
87 {0x000080f0, 0x00000000},
88 {0x000080f4, 0x00000000},
89 {0x000080fc, 0x00020000},
90 {0x00008100, 0x00000000},
91 {0x00008108, 0x00000052},
92 {0x0000810c, 0x00000000},
93 {0x00008110, 0x00000000},
94 {0x00008114, 0x000007ff},
95 {0x00008118, 0x000000aa},
96 {0x0000811c, 0x00003210},
97 {0x00008124, 0x00000000},
98 {0x00008128, 0x00000000},
99 {0x0000812c, 0x00000000},
100 {0x00008130, 0x00000000},
101 {0x00008134, 0x00000000},
102 {0x00008138, 0x00000000},
103 {0x0000813c, 0x0000ffff},
104 {0x00008144, 0xffffffff},
105 {0x00008168, 0x00000000},
106 {0x0000816c, 0x00000000},
107 {0x00008170, 0x18486200},
108 {0x00008174, 0x33332210},
109 {0x00008178, 0x00000000},
110 {0x0000817c, 0x00020000},
111 {0x000081c0, 0x00000000},
112 {0x000081c4, 0x33332210},
113 {0x000081d4, 0x00000000},
114 {0x000081ec, 0x00000000},
115 {0x000081f0, 0x00000000},
116 {0x000081f4, 0x00000000},
117 {0x000081f8, 0x00000000},
118 {0x000081fc, 0x00000000},
119 {0x00008240, 0x00100000},
120 {0x00008244, 0x0010f400},
121 {0x00008248, 0x00000800},
122 {0x0000824c, 0x0001e800},
123 {0x00008250, 0x00000000},
124 {0x00008254, 0x00000000},
125 {0x00008258, 0x00000000},
126 {0x0000825c, 0x40000000},
127 {0x00008260, 0x00080922},
128 {0x00008264, 0x9ca00010},
129 {0x00008268, 0xffffffff},
130 {0x0000826c, 0x0000ffff},
131 {0x00008270, 0x00000000},
132 {0x00008274, 0x40000000},
133 {0x00008278, 0x003e4180},
134 {0x0000827c, 0x00000004},
135 {0x00008284, 0x0000002c},
136 {0x00008288, 0x0000002c},
137 {0x0000828c, 0x000000ff},
138 {0x00008294, 0x00000000},
139 {0x00008298, 0x00000000},
140 {0x0000829c, 0x00000000},
141 {0x00008300, 0x00000140},
142 {0x00008314, 0x00000000},
143 {0x0000831c, 0x0000010d},
144 {0x00008328, 0x00000000},
145 {0x0000832c, 0x00000007},
146 {0x00008330, 0x00000302},
147 {0x00008334, 0x00000700},
148 {0x00008338, 0x00ff0000},
149 {0x0000833c, 0x02400000},
150 {0x00008340, 0x000107ff},
151 {0x00008344, 0xa248105b},
152 {0x00008348, 0x008f0000},
153 {0x0000835c, 0x00000000},
154 {0x00008360, 0xffffffff},
155 {0x00008364, 0xffffffff},
156 {0x00008368, 0x00000000},
157 {0x00008370, 0x00000000},
158 {0x00008374, 0x000000ff},
159 {0x00008378, 0x00000000},
160 {0x0000837c, 0x00000000},
161 {0x00008380, 0xffffffff},
162 {0x00008384, 0xffffffff},
163 {0x00008390, 0xffffffff},
164 {0x00008394, 0xffffffff},
165 {0x00008398, 0x00000000},
166 {0x0000839c, 0x00000000},
167 {0x000083a0, 0x00000000},
168 {0x000083a4, 0x0000fa14},
169 {0x000083a8, 0x000f0c00},
170 {0x000083ac, 0x33332210},
171 {0x000083b0, 0x33332210},
172 {0x000083b4, 0x33332210},
173 {0x000083b8, 0x33332210},
174 {0x000083bc, 0x00000000},
175 {0x000083c0, 0x00000000},
176 {0x000083c4, 0x00000000},
177 {0x000083c8, 0x00000000},
178 {0x000083cc, 0x00000200},
179 {0x000083d0, 0x000301ff},
180};
181 22
182static const u32 ar9485_1_1_baseband_core[][2] = { 23#define ar9485_1_1_mac_postamble ar9300_2p2_mac_postamble
183 /* Addr allmodes */
184 {0x00009800, 0xafe68e30},
185 {0x00009804, 0xfd14e000},
186 {0x00009808, 0x9c0a8f6b},
187 {0x0000980c, 0x04800000},
188 {0x00009814, 0x9280c00a},
189 {0x00009818, 0x00000000},
190 {0x0000981c, 0x00020028},
191 {0x00009834, 0x5f3ca3de},
192 {0x00009838, 0x0108ecff},
193 {0x0000983c, 0x14750600},
194 {0x00009880, 0x201fff00},
195 {0x00009884, 0x00001042},
196 {0x000098a4, 0x00200400},
197 {0x000098b0, 0x52440bbe},
198 {0x000098d0, 0x004b6a8e},
199 {0x000098d4, 0x00000820},
200 {0x000098dc, 0x00000000},
201 {0x000098f0, 0x00000000},
202 {0x000098f4, 0x00000000},
203 {0x00009c04, 0x00000000},
204 {0x00009c08, 0x03200000},
205 {0x00009c0c, 0x00000000},
206 {0x00009c10, 0x00000000},
207 {0x00009c14, 0x00046384},
208 {0x00009c18, 0x05b6b440},
209 {0x00009c1c, 0x00b6b440},
210 {0x00009d00, 0xc080a333},
211 {0x00009d04, 0x40206c10},
212 {0x00009d08, 0x009c4060},
213 {0x00009d0c, 0x1883800a},
214 {0x00009d10, 0x01834061},
215 {0x00009d14, 0x00c00400},
216 {0x00009d18, 0x00000000},
217 {0x00009d1c, 0x00000000},
218 {0x00009e08, 0x0038233c},
219 {0x00009e24, 0x9927b515},
220 {0x00009e28, 0x12ef0200},
221 {0x00009e30, 0x06336f77},
222 {0x00009e34, 0x6af6532f},
223 {0x00009e38, 0x0cc80c00},
224 {0x00009e40, 0x0d261820},
225 {0x00009e4c, 0x00001004},
226 {0x00009e50, 0x00ff03f1},
227 {0x00009fc0, 0x80be4788},
228 {0x00009fc4, 0x0001efb5},
229 {0x00009fcc, 0x40000014},
230 {0x0000a20c, 0x00000000},
231 {0x0000a210, 0x00000000},
232 {0x0000a220, 0x00000000},
233 {0x0000a224, 0x00000000},
234 {0x0000a228, 0x10002310},
235 {0x0000a23c, 0x00000000},
236 {0x0000a244, 0x0c000000},
237 {0x0000a2a0, 0x00000001},
238 {0x0000a2c0, 0x00000001},
239 {0x0000a2c8, 0x00000000},
240 {0x0000a2cc, 0x18c43433},
241 {0x0000a2d4, 0x00000000},
242 {0x0000a2dc, 0x00000000},
243 {0x0000a2e0, 0x00000000},
244 {0x0000a2e4, 0x00000000},
245 {0x0000a2e8, 0x00000000},
246 {0x0000a2ec, 0x00000000},
247 {0x0000a2f0, 0x00000000},
248 {0x0000a2f4, 0x00000000},
249 {0x0000a2f8, 0x00000000},
250 {0x0000a344, 0x00000000},
251 {0x0000a34c, 0x00000000},
252 {0x0000a350, 0x0000a000},
253 {0x0000a364, 0x00000000},
254 {0x0000a370, 0x00000000},
255 {0x0000a390, 0x00000001},
256 {0x0000a394, 0x00000444},
257 {0x0000a398, 0x001f0e0f},
258 {0x0000a39c, 0x0075393f},
259 {0x0000a3a0, 0xb79f6427},
260 {0x0000a3a4, 0x000000ff},
261 {0x0000a3a8, 0x3b3b3b3b},
262 {0x0000a3ac, 0x2f2f2f2f},
263 {0x0000a3c0, 0x20202020},
264 {0x0000a3c4, 0x22222220},
265 {0x0000a3c8, 0x20200020},
266 {0x0000a3cc, 0x20202020},
267 {0x0000a3d0, 0x20202020},
268 {0x0000a3d4, 0x20202020},
269 {0x0000a3d8, 0x20202020},
270 {0x0000a3dc, 0x20202020},
271 {0x0000a3e0, 0x20202020},
272 {0x0000a3e4, 0x20202020},
273 {0x0000a3e8, 0x20202020},
274 {0x0000a3ec, 0x20202020},
275 {0x0000a3f0, 0x00000000},
276 {0x0000a3f4, 0x00000006},
277 {0x0000a3f8, 0x0cdbd380},
278 {0x0000a3fc, 0x000f0f01},
279 {0x0000a400, 0x8fa91f01},
280 {0x0000a404, 0x00000000},
281 {0x0000a408, 0x0e79e5c6},
282 {0x0000a40c, 0x00820820},
283 {0x0000a414, 0x1ce739cf},
284 {0x0000a418, 0x2d0019ce},
285 {0x0000a41c, 0x1ce739ce},
286 {0x0000a420, 0x000001ce},
287 {0x0000a424, 0x1ce739ce},
288 {0x0000a428, 0x000001ce},
289 {0x0000a42c, 0x1ce739ce},
290 {0x0000a430, 0x1ce739ce},
291 {0x0000a434, 0x00000000},
292 {0x0000a438, 0x00001801},
293 {0x0000a43c, 0x00000000},
294 {0x0000a440, 0x00000000},
295 {0x0000a444, 0x00000000},
296 {0x0000a448, 0x04000000},
297 {0x0000a44c, 0x00000001},
298 {0x0000a450, 0x00010000},
299 {0x0000a5c4, 0xbfad9d74},
300 {0x0000a5c8, 0x0048060a},
301 {0x0000a5cc, 0x00000637},
302 {0x0000a760, 0x03020100},
303 {0x0000a764, 0x09080504},
304 {0x0000a768, 0x0d0c0b0a},
305 {0x0000a76c, 0x13121110},
306 {0x0000a770, 0x31301514},
307 {0x0000a774, 0x35343332},
308 {0x0000a778, 0x00000036},
309 {0x0000a780, 0x00000838},
310 {0x0000a7c0, 0x00000000},
311 {0x0000a7c4, 0xfffffffc},
312 {0x0000a7c8, 0x00000000},
313 {0x0000a7cc, 0x00000000},
314 {0x0000a7d0, 0x00000000},
315 {0x0000a7d4, 0x00000004},
316 {0x0000a7dc, 0x00000000},
317};
318 24
319static const u32 ar9485Common_1_1[][2] = { 25static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
320 /* Addr allmodes */ 26 /* Addr allmodes */
321 {0x00007010, 0x00000022}, 27 {0x00018c00, 0x18012e5e},
322 {0x00007020, 0x00000000}, 28 {0x00018c04, 0x000801d8},
323 {0x00007034, 0x00000002}, 29 {0x00018c08, 0x0000080c},
324 {0x00007038, 0x000004c2},
325}; 30};
326 31
327static const u32 ar9485_1_1_baseband_postamble[][5] = { 32static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {
328 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 33 /* Addr allmodes */
329 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005}, 34 {0x0000a000, 0x00060005},
330 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e}, 35 {0x0000a004, 0x00810080},
331 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, 36 {0x0000a008, 0x00830082},
332 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881}, 37 {0x0000a00c, 0x00850084},
333 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, 38 {0x0000a010, 0x01820181},
334 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c}, 39 {0x0000a014, 0x01840183},
335 {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044}, 40 {0x0000a018, 0x01880185},
336 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0}, 41 {0x0000a01c, 0x018a0189},
337 {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020}, 42 {0x0000a020, 0x02850284},
338 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2}, 43 {0x0000a024, 0x02890288},
339 {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec80d2e, 0x7ec80d2e}, 44 {0x0000a028, 0x028b028a},
340 {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e}, 45 {0x0000a02c, 0x03850384},
341 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 46 {0x0000a030, 0x03890388},
342 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c}, 47 {0x0000a034, 0x038b038a},
343 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce}, 48 {0x0000a038, 0x038d038c},
344 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021}, 49 {0x0000a03c, 0x03910390},
345 {0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222}, 50 {0x0000a040, 0x03930392},
346 {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324}, 51 {0x0000a044, 0x03950394},
347 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010}, 52 {0x0000a048, 0x00000396},
348 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000}, 53 {0x0000a04c, 0x00000000},
349 {0x0000a204, 0x01303fc0, 0x01303fc4, 0x01303fc4, 0x01303fc0}, 54 {0x0000a050, 0x00000000},
350 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004}, 55 {0x0000a054, 0x00000000},
351 {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b}, 56 {0x0000a058, 0x00000000},
352 {0x0000a234, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff}, 57 {0x0000a05c, 0x00000000},
353 {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018}, 58 {0x0000a060, 0x00000000},
354 {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, 59 {0x0000a064, 0x00000000},
355 {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, 60 {0x0000a068, 0x00000000},
356 {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002}, 61 {0x0000a06c, 0x00000000},
357 {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e}, 62 {0x0000a070, 0x00000000},
358 {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501}, 63 {0x0000a074, 0x00000000},
359 {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, 64 {0x0000a078, 0x00000000},
360 {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b}, 65 {0x0000a07c, 0x00000000},
361 {0x0000a284, 0x00000000, 0x00000000, 0x000002a0, 0x000002a0}, 66 {0x0000a080, 0x28282828},
362 {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 67 {0x0000a084, 0x28282828},
363 {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 68 {0x0000a088, 0x28282828},
364 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18}, 69 {0x0000a08c, 0x28282828},
365 {0x0000a2d0, 0x00071981, 0x00071981, 0x00071982, 0x00071982}, 70 {0x0000a090, 0x28282828},
366 {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a}, 71 {0x0000a094, 0x24242428},
367 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 72 {0x0000a098, 0x171e1e1e},
368 {0x0000be04, 0x00802020, 0x00802020, 0x00802020, 0x00802020}, 73 {0x0000a09c, 0x02020b0b},
369 {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 74 {0x0000a0a0, 0x02020202},
75 {0x0000a0a4, 0x00000000},
76 {0x0000a0a8, 0x00000000},
77 {0x0000a0ac, 0x00000000},
78 {0x0000a0b0, 0x00000000},
79 {0x0000a0b4, 0x00000000},
80 {0x0000a0b8, 0x00000000},
81 {0x0000a0bc, 0x00000000},
82 {0x0000a0c0, 0x22072208},
83 {0x0000a0c4, 0x22052206},
84 {0x0000a0c8, 0x22032204},
85 {0x0000a0cc, 0x22012202},
86 {0x0000a0d0, 0x221f2200},
87 {0x0000a0d4, 0x221d221e},
88 {0x0000a0d8, 0x33023303},
89 {0x0000a0dc, 0x33003301},
90 {0x0000a0e0, 0x331e331f},
91 {0x0000a0e4, 0x4402331d},
92 {0x0000a0e8, 0x44004401},
93 {0x0000a0ec, 0x441e441f},
94 {0x0000a0f0, 0x55025503},
95 {0x0000a0f4, 0x55005501},
96 {0x0000a0f8, 0x551e551f},
97 {0x0000a0fc, 0x6602551d},
98 {0x0000a100, 0x66006601},
99 {0x0000a104, 0x661e661f},
100 {0x0000a108, 0x7703661d},
101 {0x0000a10c, 0x77017702},
102 {0x0000a110, 0x00007700},
103 {0x0000a114, 0x00000000},
104 {0x0000a118, 0x00000000},
105 {0x0000a11c, 0x00000000},
106 {0x0000a120, 0x00000000},
107 {0x0000a124, 0x00000000},
108 {0x0000a128, 0x00000000},
109 {0x0000a12c, 0x00000000},
110 {0x0000a130, 0x00000000},
111 {0x0000a134, 0x00000000},
112 {0x0000a138, 0x00000000},
113 {0x0000a13c, 0x00000000},
114 {0x0000a140, 0x001f0000},
115 {0x0000a144, 0x111f1100},
116 {0x0000a148, 0x111d111e},
117 {0x0000a14c, 0x111b111c},
118 {0x0000a150, 0x22032204},
119 {0x0000a154, 0x22012202},
120 {0x0000a158, 0x221f2200},
121 {0x0000a15c, 0x221d221e},
122 {0x0000a160, 0x33013302},
123 {0x0000a164, 0x331f3300},
124 {0x0000a168, 0x4402331e},
125 {0x0000a16c, 0x44004401},
126 {0x0000a170, 0x441e441f},
127 {0x0000a174, 0x55015502},
128 {0x0000a178, 0x551f5500},
129 {0x0000a17c, 0x6602551e},
130 {0x0000a180, 0x66006601},
131 {0x0000a184, 0x661e661f},
132 {0x0000a188, 0x7703661d},
133 {0x0000a18c, 0x77017702},
134 {0x0000a190, 0x00007700},
135 {0x0000a194, 0x00000000},
136 {0x0000a198, 0x00000000},
137 {0x0000a19c, 0x00000000},
138 {0x0000a1a0, 0x00000000},
139 {0x0000a1a4, 0x00000000},
140 {0x0000a1a8, 0x00000000},
141 {0x0000a1ac, 0x00000000},
142 {0x0000a1b0, 0x00000000},
143 {0x0000a1b4, 0x00000000},
144 {0x0000a1b8, 0x00000000},
145 {0x0000a1bc, 0x00000000},
146 {0x0000a1c0, 0x00000000},
147 {0x0000a1c4, 0x00000000},
148 {0x0000a1c8, 0x00000000},
149 {0x0000a1cc, 0x00000000},
150 {0x0000a1d0, 0x00000000},
151 {0x0000a1d4, 0x00000000},
152 {0x0000a1d8, 0x00000000},
153 {0x0000a1dc, 0x00000000},
154 {0x0000a1e0, 0x00000000},
155 {0x0000a1e4, 0x00000000},
156 {0x0000a1e8, 0x00000000},
157 {0x0000a1ec, 0x00000000},
158 {0x0000a1f0, 0x00000396},
159 {0x0000a1f4, 0x00000396},
160 {0x0000a1f8, 0x00000396},
161 {0x0000a1fc, 0x00000296},
370}; 162};
371 163
372static const u32 ar9485Modes_high_ob_db_tx_gain_1_1[][5] = { 164static const u32 ar9485Modes_high_power_tx_gain_1_1[][5] = {
373 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 165 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
374 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, 166 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
375 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8}, 167 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
376 {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 168 {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
@@ -442,102 +234,34 @@ static const u32 ar9485Modes_high_ob_db_tx_gain_1_1[][5] = {
442 {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260}, 234 {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
443}; 235};
444 236
445static const u32 ar9485_modes_lowest_ob_db_tx_gain_1_1[][5] = { 237#define ar9485Modes_high_ob_db_tx_gain_1_1 ar9485Modes_high_power_tx_gain_1_1
446 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
447 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
448 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
449 {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
450 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
451 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
452 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
453 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
454 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
455 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
456 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
457 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
458 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
459 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
460 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
461 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
462 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
463 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
464 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
465 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
466 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
467 {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
468 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
469 {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
470 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
471 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
472 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
473 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
474 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
475 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
476 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
477 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
478 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
479 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
480 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
481 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
482 {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
483 {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
484 {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
485 {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
486 {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
487 {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
488 {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
489 {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
490 {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
491 {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
492 {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
493 {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
494 {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
495 {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
496 {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
497 {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
498 {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
499 {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
500 {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
501 {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
502 {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
503 {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
504 {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
505 {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
506 {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
507 {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
508 {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
509 {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
510 {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
511 {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
512 {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
513 {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
514 {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
515 {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
516};
517 238
518static const u32 ar9485_1_1_radio_postamble[][2] = { 239#define ar9485Modes_low_ob_db_tx_gain_1_1 ar9485Modes_high_ob_db_tx_gain_1_1
519 /* Addr allmodes */
520 {0x0001609c, 0x0b283f31},
521 {0x000160ac, 0x24611800},
522 {0x000160b0, 0x03284f3e},
523 {0x0001610c, 0x00170000},
524 {0x00016140, 0x50804008},
525};
526 240
527static const u32 ar9485_1_1_mac_postamble[][5] = { 241#define ar9485_modes_lowest_ob_db_tx_gain_1_1 ar9485Modes_low_ob_db_tx_gain_1_1
528 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 242
529 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, 243static const u32 ar9485_1_1[][2] = {
530 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, 244 /* Addr allmodes */
531 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38}, 245 {0x0000a580, 0x00000000},
532 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00}, 246 {0x0000a584, 0x00000000},
533 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b}, 247 {0x0000a588, 0x00000000},
534 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810}, 248 {0x0000a58c, 0x00000000},
535 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a}, 249 {0x0000a590, 0x00000000},
536 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, 250 {0x0000a594, 0x00000000},
251 {0x0000a598, 0x00000000},
252 {0x0000a59c, 0x00000000},
253 {0x0000a5a0, 0x00000000},
254 {0x0000a5a4, 0x00000000},
255 {0x0000a5a8, 0x00000000},
256 {0x0000a5ac, 0x00000000},
257 {0x0000a5b0, 0x00000000},
258 {0x0000a5b4, 0x00000000},
259 {0x0000a5b8, 0x00000000},
260 {0x0000a5bc, 0x00000000},
537}; 261};
538 262
539static const u32 ar9485_1_1_radio_core[][2] = { 263static const u32 ar9485_1_1_radio_core[][2] = {
540 /* Addr allmodes */ 264 /* Addr allmodes */
541 {0x00016000, 0x36db6db6}, 265 {0x00016000, 0x36db6db6},
542 {0x00016004, 0x6db6db40}, 266 {0x00016004, 0x6db6db40},
543 {0x00016008, 0x73800000}, 267 {0x00016008, 0x73800000},
@@ -601,294 +325,145 @@ static const u32 ar9485_1_1_radio_core[][2] = {
601 {0x00016c44, 0x12000000}, 325 {0x00016c44, 0x12000000},
602}; 326};
603 327
604static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = { 328static const u32 ar9485_1_1_baseband_core[][2] = {
605 /* Addr allmodes */ 329 /* Addr allmodes */
606 {0x00018c00, 0x18052e5e}, 330 {0x00009800, 0xafe68e30},
607 {0x00018c04, 0x000801d8}, 331 {0x00009804, 0xfd14e000},
608 {0x00018c08, 0x0000080c}, 332 {0x00009808, 0x9c0a8f6b},
609}; 333 {0x0000980c, 0x04800000},
610 334 {0x00009814, 0x9280c00a},
611static const u32 ar9485Modes_high_power_tx_gain_1_1[][5] = { 335 {0x00009818, 0x00000000},
612 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 336 {0x0000981c, 0x00020028},
613 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, 337 {0x00009834, 0x5f3ca3de},
614 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8}, 338 {0x00009838, 0x0108ecff},
615 {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 339 {0x0000983c, 0x14750600},
616 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000}, 340 {0x00009880, 0x201fff00},
617 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002}, 341 {0x00009884, 0x00001042},
618 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004}, 342 {0x000098a4, 0x00200400},
619 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200}, 343 {0x000098b0, 0x52440bbe},
620 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202}, 344 {0x000098d0, 0x004b6a8e},
621 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400}, 345 {0x000098d4, 0x00000820},
622 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402}, 346 {0x000098dc, 0x00000000},
623 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404}, 347 {0x000098f0, 0x00000000},
624 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603}, 348 {0x000098f4, 0x00000000},
625 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605}, 349 {0x00009c04, 0x00000000},
626 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03}, 350 {0x00009c08, 0x03200000},
627 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04}, 351 {0x00009c0c, 0x00000000},
628 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20}, 352 {0x00009c10, 0x00000000},
629 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21}, 353 {0x00009c14, 0x00046384},
630 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62}, 354 {0x00009c18, 0x05b6b440},
631 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63}, 355 {0x00009c1c, 0x00b6b440},
632 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65}, 356 {0x00009d00, 0xc080a333},
633 {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66}, 357 {0x00009d04, 0x40206c10},
634 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645}, 358 {0x00009d08, 0x009c4060},
635 {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865}, 359 {0x00009d0c, 0x1883800a},
636 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86}, 360 {0x00009d10, 0x01834061},
637 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9}, 361 {0x00009d14, 0x00c00400},
638 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb}, 362 {0x00009d18, 0x00000000},
639 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb}, 363 {0x00009d1c, 0x00000000},
640 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb}, 364 {0x00009e08, 0x0038233c},
641 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb}, 365 {0x00009e24, 0x9927b515},
642 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 366 {0x00009e28, 0x12ef0200},
643 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 367 {0x00009e30, 0x06336f77},
644 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 368 {0x00009e34, 0x6af6532f},
645 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 369 {0x00009e38, 0x0cc80c00},
646 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 370 {0x00009e40, 0x0d261820},
647 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 371 {0x00009e4c, 0x00001004},
648 {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 372 {0x00009e50, 0x00ff03f1},
649 {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 373 {0x00009fc0, 0x80be4788},
650 {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 374 {0x00009fc4, 0x0001efb5},
651 {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 375 {0x00009fcc, 0x40000014},
652 {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 376 {0x0000a20c, 0x00000000},
653 {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 377 {0x0000a210, 0x00000000},
654 {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 378 {0x0000a220, 0x00000000},
655 {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 379 {0x0000a224, 0x00000000},
656 {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 380 {0x0000a228, 0x10002310},
657 {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 381 {0x0000a23c, 0x00000000},
658 {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 382 {0x0000a244, 0x0c000000},
659 {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 383 {0x0000a2a0, 0x00000001},
660 {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 384 {0x0000a2c0, 0x00000001},
661 {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 385 {0x0000a2c8, 0x00000000},
662 {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 386 {0x0000a2cc, 0x18c43433},
663 {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 387 {0x0000a2d4, 0x00000000},
664 {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 388 {0x0000a2dc, 0x00000000},
665 {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 389 {0x0000a2e0, 0x00000000},
666 {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 390 {0x0000a2e4, 0x00000000},
667 {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 391 {0x0000a2e8, 0x00000000},
668 {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 392 {0x0000a2ec, 0x00000000},
669 {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 393 {0x0000a2f0, 0x00000000},
670 {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 394 {0x0000a2f4, 0x00000000},
671 {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 395 {0x0000a2f8, 0x00000000},
672 {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 396 {0x0000a344, 0x00000000},
673 {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 397 {0x0000a34c, 0x00000000},
674 {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 398 {0x0000a350, 0x0000a000},
675 {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 399 {0x0000a364, 0x00000000},
676 {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 400 {0x0000a370, 0x00000000},
677 {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 401 {0x0000a390, 0x00000001},
678 {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 402 {0x0000a394, 0x00000444},
679 {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 403 {0x0000a398, 0x001f0e0f},
680 {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db}, 404 {0x0000a39c, 0x0075393f},
681 {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260}, 405 {0x0000a3a0, 0xb79f6427},
682}; 406 {0x0000a3a4, 0x000000ff},
683 407 {0x0000a3a8, 0x3b3b3b3b},
684static const u32 ar9485_1_1[][2] = { 408 {0x0000a3ac, 0x2f2f2f2f},
685 /* Addr allmodes */ 409 {0x0000a3c0, 0x20202020},
686 {0x0000a580, 0x00000000}, 410 {0x0000a3c4, 0x22222220},
687 {0x0000a584, 0x00000000}, 411 {0x0000a3c8, 0x20200020},
688 {0x0000a588, 0x00000000}, 412 {0x0000a3cc, 0x20202020},
689 {0x0000a58c, 0x00000000}, 413 {0x0000a3d0, 0x20202020},
690 {0x0000a590, 0x00000000}, 414 {0x0000a3d4, 0x20202020},
691 {0x0000a594, 0x00000000}, 415 {0x0000a3d8, 0x20202020},
692 {0x0000a598, 0x00000000}, 416 {0x0000a3dc, 0x20202020},
693 {0x0000a59c, 0x00000000}, 417 {0x0000a3e0, 0x20202020},
694 {0x0000a5a0, 0x00000000}, 418 {0x0000a3e4, 0x20202020},
695 {0x0000a5a4, 0x00000000}, 419 {0x0000a3e8, 0x20202020},
696 {0x0000a5a8, 0x00000000}, 420 {0x0000a3ec, 0x20202020},
697 {0x0000a5ac, 0x00000000}, 421 {0x0000a3f0, 0x00000000},
698 {0x0000a5b0, 0x00000000}, 422 {0x0000a3f4, 0x00000006},
699 {0x0000a5b4, 0x00000000}, 423 {0x0000a3f8, 0x0cdbd380},
700 {0x0000a5b8, 0x00000000}, 424 {0x0000a3fc, 0x000f0f01},
701 {0x0000a5bc, 0x00000000}, 425 {0x0000a400, 0x8fa91f01},
702}; 426 {0x0000a404, 0x00000000},
703 427 {0x0000a408, 0x0e79e5c6},
704static const u32 ar9485_modes_green_ob_db_tx_gain_1_1[][5] = { 428 {0x0000a40c, 0x00820820},
705 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 429 {0x0000a414, 0x1ce739cf},
706 {0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003}, 430 {0x0000a418, 0x2d0019ce},
707 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8}, 431 {0x0000a41c, 0x1ce739ce},
708 {0x0000a458, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, 432 {0x0000a420, 0x000001ce},
709 {0x0000a500, 0x00022200, 0x00022200, 0x00000006, 0x00000006}, 433 {0x0000a424, 0x1ce739ce},
710 {0x0000a504, 0x05062002, 0x05062002, 0x03000201, 0x03000201}, 434 {0x0000a428, 0x000001ce},
711 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x06000203, 0x06000203}, 435 {0x0000a42c, 0x1ce739ce},
712 {0x0000a50c, 0x11062202, 0x11062202, 0x0a000401, 0x0a000401}, 436 {0x0000a430, 0x1ce739ce},
713 {0x0000a510, 0x17022e00, 0x17022e00, 0x0e000403, 0x0e000403}, 437 {0x0000a434, 0x00000000},
714 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x12000405, 0x12000405}, 438 {0x0000a438, 0x00001801},
715 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x15000604, 0x15000604}, 439 {0x0000a43c, 0x00000000},
716 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x18000605, 0x18000605}, 440 {0x0000a440, 0x00000000},
717 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x1c000a04, 0x1c000a04}, 441 {0x0000a444, 0x00000000},
718 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x21000a06, 0x21000a06}, 442 {0x0000a448, 0x04000000},
719 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x29000a24, 0x29000a24}, 443 {0x0000a44c, 0x00000001},
720 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2f000e21, 0x2f000e21}, 444 {0x0000a450, 0x00010000},
721 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000e20, 0x31000e20}, 445 {0x0000a5c4, 0xbfad9d74},
722 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x33000e20, 0x33000e20}, 446 {0x0000a5c8, 0x0048060a},
723 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62}, 447 {0x0000a5cc, 0x00000637},
724 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63}, 448 {0x0000a760, 0x03020100},
725 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65}, 449 {0x0000a764, 0x09080504},
726 {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66}, 450 {0x0000a768, 0x0d0c0b0a},
727 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645}, 451 {0x0000a76c, 0x13121110},
728 {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865}, 452 {0x0000a770, 0x31301514},
729 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86}, 453 {0x0000a774, 0x35343332},
730 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9}, 454 {0x0000a778, 0x00000036},
731 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb}, 455 {0x0000a780, 0x00000838},
732 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb}, 456 {0x0000a7c0, 0x00000000},
733 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb}, 457 {0x0000a7c4, 0xfffffffc},
734 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb}, 458 {0x0000a7c8, 0x00000000},
735 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 459 {0x0000a7cc, 0x00000000},
736 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 460 {0x0000a7d0, 0x00000000},
737 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 461 {0x0000a7d4, 0x00000004},
738 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 462 {0x0000a7dc, 0x00000000},
739 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
740 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
741 {0x0000b500, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
742 {0x0000b504, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
743 {0x0000b508, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
744 {0x0000b50c, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
745 {0x0000b510, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
746 {0x0000b514, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
747 {0x0000b518, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
748 {0x0000b51c, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
749 {0x0000b520, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
750 {0x0000b524, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
751 {0x0000b528, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
752 {0x0000b52c, 0x0000002a, 0x0000002a, 0x0000002a, 0x0000002a},
753 {0x0000b530, 0x0000003a, 0x0000003a, 0x0000003a, 0x0000003a},
754 {0x0000b534, 0x0000004a, 0x0000004a, 0x0000004a, 0x0000004a},
755 {0x0000b538, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
756 {0x0000b53c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
757 {0x0000b540, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
758 {0x0000b544, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
759 {0x0000b548, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
760 {0x0000b54c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
761 {0x0000b550, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
762 {0x0000b554, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
763 {0x0000b558, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
764 {0x0000b55c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
765 {0x0000b560, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
766 {0x0000b564, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
767 {0x0000b568, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
768 {0x0000b56c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
769 {0x0000b570, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
770 {0x0000b574, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
771 {0x0000b578, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
772 {0x0000b57c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
773 {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
774 {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
775};
776
777static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
778 /* Addr allmodes */
779 {0x00018c00, 0x18013e5e},
780 {0x00018c04, 0x000801d8},
781 {0x00018c08, 0x0000080c},
782};
783
784static const u32 ar9485_1_1_soc_preamble[][2] = {
785 /* Addr allmodes */
786 {0x00004014, 0xba280400},
787 {0x00004090, 0x00aa10aa},
788 {0x000040a4, 0x00a0c9c9},
789 {0x00007010, 0x00000022},
790 {0x00007020, 0x00000000},
791 {0x00007034, 0x00000002},
792 {0x00007038, 0x000004c2},
793 {0x00007048, 0x00000002},
794};
795
796static const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = {
797 /* Addr allmodes */
798 {0x0000a398, 0x00000000},
799 {0x0000a39c, 0x6f7f0301},
800 {0x0000a3a0, 0xca9228ee},
801};
802
803static const u32 ar9485Modes_low_ob_db_tx_gain_1_1[][5] = {
804 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
805 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
806 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
807 {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
808 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
809 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
810 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
811 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
812 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
813 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
814 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
815 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
816 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
817 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
818 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
819 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
820 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
821 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
822 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
823 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
824 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
825 {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
826 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
827 {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
828 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
829 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
830 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
831 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
832 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
833 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
834 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
835 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
836 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
837 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
838 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
839 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
840 {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
841 {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
842 {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
843 {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
844 {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
845 {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
846 {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
847 {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
848 {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
849 {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
850 {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
851 {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
852 {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
853 {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
854 {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
855 {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
856 {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
857 {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
858 {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
859 {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
860 {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
861 {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
862 {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
863 {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
864 {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
865 {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
866 {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
867 {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
868 {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
869 {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
870 {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
871 {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
872 {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
873 {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
874};
875
876static const u32 ar9485_fast_clock_1_1_baseband_postamble[][3] = {
877 /* Addr 5G_HT2 5G_HT40 */
878 {0x00009e00, 0x03721821, 0x03721821},
879 {0x0000a230, 0x0000400b, 0x00004016},
880 {0x0000a254, 0x00000898, 0x00001130},
881};
882
883static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
884 /* Addr allmodes */
885 {0x00018c00, 0x18012e5e},
886 {0x00018c04, 0x000801d8},
887 {0x00018c08, 0x0000080c},
888}; 463};
889 464
890static const u32 ar9485_common_rx_gain_1_1[][2] = { 465static const u32 ar9485_common_rx_gain_1_1[][2] = {
891 /* Addr allmodes */ 466 /* Addr allmodes */
892 {0x0000a000, 0x00010000}, 467 {0x0000a000, 0x00010000},
893 {0x0000a004, 0x00030002}, 468 {0x0000a004, 0x00030002},
894 {0x0000a008, 0x00050004}, 469 {0x0000a008, 0x00050004},
@@ -1019,143 +594,260 @@ static const u32 ar9485_common_rx_gain_1_1[][2] = {
1019 {0x0000a1fc, 0x00000296}, 594 {0x0000a1fc, 0x00000296},
1020}; 595};
1021 596
597static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
598 /* Addr allmodes */
599 {0x00018c00, 0x18052e5e},
600 {0x00018c04, 0x000801d8},
601 {0x00018c08, 0x0000080c},
602};
603
1022static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = { 604static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
1023 /* Addr allmodes */ 605 /* Addr allmodes */
1024 {0x00018c00, 0x18053e5e}, 606 {0x00018c00, 0x18053e5e},
1025 {0x00018c04, 0x000801d8}, 607 {0x00018c04, 0x000801d8},
1026 {0x00018c08, 0x0000080c}, 608 {0x00018c08, 0x0000080c},
1027}; 609};
1028 610
1029static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = { 611static const u32 ar9485_1_1_soc_preamble[][2] = {
1030 /* Addr allmodes */ 612 /* Addr allmodes */
1031 {0x0000a000, 0x00060005}, 613 {0x00004014, 0xba280400},
1032 {0x0000a004, 0x00810080}, 614 {0x00004090, 0x00aa10aa},
1033 {0x0000a008, 0x00830082}, 615 {0x000040a4, 0x00a0c9c9},
1034 {0x0000a00c, 0x00850084}, 616 {0x00007010, 0x00000022},
1035 {0x0000a010, 0x01820181}, 617 {0x00007020, 0x00000000},
1036 {0x0000a014, 0x01840183}, 618 {0x00007034, 0x00000002},
1037 {0x0000a018, 0x01880185}, 619 {0x00007038, 0x000004c2},
1038 {0x0000a01c, 0x018a0189}, 620 {0x00007048, 0x00000002},
1039 {0x0000a020, 0x02850284}, 621};
1040 {0x0000a024, 0x02890288}, 622
1041 {0x0000a028, 0x028b028a}, 623static const u32 ar9485_fast_clock_1_1_baseband_postamble[][3] = {
1042 {0x0000a02c, 0x03850384}, 624 /* Addr 5G_HT20 5G_HT40 */
1043 {0x0000a030, 0x03890388}, 625 {0x00009e00, 0x03721821, 0x03721821},
1044 {0x0000a034, 0x038b038a}, 626 {0x0000a230, 0x0000400b, 0x00004016},
1045 {0x0000a038, 0x038d038c}, 627 {0x0000a254, 0x00000898, 0x00001130},
1046 {0x0000a03c, 0x03910390}, 628};
1047 {0x0000a040, 0x03930392}, 629
1048 {0x0000a044, 0x03950394}, 630static const u32 ar9485_1_1_baseband_postamble[][5] = {
1049 {0x0000a048, 0x00000396}, 631 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1050 {0x0000a04c, 0x00000000}, 632 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
1051 {0x0000a050, 0x00000000}, 633 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
1052 {0x0000a054, 0x00000000}, 634 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
1053 {0x0000a058, 0x00000000}, 635 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
1054 {0x0000a05c, 0x00000000}, 636 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
1055 {0x0000a060, 0x00000000}, 637 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
1056 {0x0000a064, 0x00000000}, 638 {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
1057 {0x0000a068, 0x00000000}, 639 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
1058 {0x0000a06c, 0x00000000}, 640 {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
1059 {0x0000a070, 0x00000000}, 641 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
1060 {0x0000a074, 0x00000000}, 642 {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec80d2e, 0x7ec80d2e},
1061 {0x0000a078, 0x00000000}, 643 {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
1062 {0x0000a07c, 0x00000000}, 644 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1063 {0x0000a080, 0x28282828}, 645 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
1064 {0x0000a084, 0x28282828}, 646 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
1065 {0x0000a088, 0x28282828}, 647 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
1066 {0x0000a08c, 0x28282828}, 648 {0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222},
1067 {0x0000a090, 0x28282828}, 649 {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
1068 {0x0000a094, 0x24242428}, 650 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
1069 {0x0000a098, 0x171e1e1e}, 651 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
1070 {0x0000a09c, 0x02020b0b}, 652 {0x0000a204, 0x01303fc0, 0x01303fc4, 0x01303fc4, 0x01303fc0},
1071 {0x0000a0a0, 0x02020202}, 653 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
1072 {0x0000a0a4, 0x00000000}, 654 {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b},
1073 {0x0000a0a8, 0x00000000}, 655 {0x0000a234, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff},
1074 {0x0000a0ac, 0x00000000}, 656 {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
1075 {0x0000a0b0, 0x00000000}, 657 {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
1076 {0x0000a0b4, 0x00000000}, 658 {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
1077 {0x0000a0b8, 0x00000000}, 659 {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
1078 {0x0000a0bc, 0x00000000}, 660 {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
1079 {0x0000a0c0, 0x22072208}, 661 {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
1080 {0x0000a0c4, 0x22052206}, 662 {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
1081 {0x0000a0c8, 0x22032204}, 663 {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
1082 {0x0000a0cc, 0x22012202}, 664 {0x0000a284, 0x00000000, 0x00000000, 0x000002a0, 0x000002a0},
1083 {0x0000a0d0, 0x221f2200}, 665 {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1084 {0x0000a0d4, 0x221d221e}, 666 {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1085 {0x0000a0d8, 0x33023303}, 667 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
1086 {0x0000a0dc, 0x33003301}, 668 {0x0000a2d0, 0x00071981, 0x00071981, 0x00071982, 0x00071982},
1087 {0x0000a0e0, 0x331e331f}, 669 {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
1088 {0x0000a0e4, 0x4402331d}, 670 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1089 {0x0000a0e8, 0x44004401}, 671 {0x0000be04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
1090 {0x0000a0ec, 0x441e441f}, 672 {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1091 {0x0000a0f0, 0x55025503}, 673};
1092 {0x0000a0f4, 0x55005501}, 674
1093 {0x0000a0f8, 0x551e551f}, 675static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
1094 {0x0000a0fc, 0x6602551d}, 676 /* Addr allmodes */
1095 {0x0000a100, 0x66006601}, 677 {0x00018c00, 0x18013e5e},
1096 {0x0000a104, 0x661e661f}, 678 {0x00018c04, 0x000801d8},
1097 {0x0000a108, 0x7703661d}, 679 {0x00018c08, 0x0000080c},
1098 {0x0000a10c, 0x77017702}, 680};
1099 {0x0000a110, 0x00007700}, 681
1100 {0x0000a114, 0x00000000}, 682static const u32 ar9485_1_1_radio_postamble[][2] = {
1101 {0x0000a118, 0x00000000}, 683 /* Addr allmodes */
1102 {0x0000a11c, 0x00000000}, 684 {0x0001609c, 0x0b283f31},
1103 {0x0000a120, 0x00000000}, 685 {0x000160ac, 0x24611800},
1104 {0x0000a124, 0x00000000}, 686 {0x000160b0, 0x03284f3e},
1105 {0x0000a128, 0x00000000}, 687 {0x0001610c, 0x00170000},
1106 {0x0000a12c, 0x00000000}, 688 {0x00016140, 0x50804008},
1107 {0x0000a130, 0x00000000}, 689};
1108 {0x0000a134, 0x00000000}, 690
1109 {0x0000a138, 0x00000000}, 691static const u32 ar9485_1_1_mac_core[][2] = {
1110 {0x0000a13c, 0x00000000}, 692 /* Addr allmodes */
1111 {0x0000a140, 0x001f0000}, 693 {0x00000008, 0x00000000},
1112 {0x0000a144, 0x111f1100}, 694 {0x00000030, 0x00020085},
1113 {0x0000a148, 0x111d111e}, 695 {0x00000034, 0x00000005},
1114 {0x0000a14c, 0x111b111c}, 696 {0x00000040, 0x00000000},
1115 {0x0000a150, 0x22032204}, 697 {0x00000044, 0x00000000},
1116 {0x0000a154, 0x22012202}, 698 {0x00000048, 0x00000008},
1117 {0x0000a158, 0x221f2200}, 699 {0x0000004c, 0x00000010},
1118 {0x0000a15c, 0x221d221e}, 700 {0x00000050, 0x00000000},
1119 {0x0000a160, 0x33013302}, 701 {0x00001040, 0x002ffc0f},
1120 {0x0000a164, 0x331f3300}, 702 {0x00001044, 0x002ffc0f},
1121 {0x0000a168, 0x4402331e}, 703 {0x00001048, 0x002ffc0f},
1122 {0x0000a16c, 0x44004401}, 704 {0x0000104c, 0x002ffc0f},
1123 {0x0000a170, 0x441e441f}, 705 {0x00001050, 0x002ffc0f},
1124 {0x0000a174, 0x55015502}, 706 {0x00001054, 0x002ffc0f},
1125 {0x0000a178, 0x551f5500}, 707 {0x00001058, 0x002ffc0f},
1126 {0x0000a17c, 0x6602551e}, 708 {0x0000105c, 0x002ffc0f},
1127 {0x0000a180, 0x66006601}, 709 {0x00001060, 0x002ffc0f},
1128 {0x0000a184, 0x661e661f}, 710 {0x00001064, 0x002ffc0f},
1129 {0x0000a188, 0x7703661d}, 711 {0x000010f0, 0x00000100},
1130 {0x0000a18c, 0x77017702}, 712 {0x00001270, 0x00000000},
1131 {0x0000a190, 0x00007700}, 713 {0x000012b0, 0x00000000},
1132 {0x0000a194, 0x00000000}, 714 {0x000012f0, 0x00000000},
1133 {0x0000a198, 0x00000000}, 715 {0x0000143c, 0x00000000},
1134 {0x0000a19c, 0x00000000}, 716 {0x0000147c, 0x00000000},
1135 {0x0000a1a0, 0x00000000}, 717 {0x00008000, 0x00000000},
1136 {0x0000a1a4, 0x00000000}, 718 {0x00008004, 0x00000000},
1137 {0x0000a1a8, 0x00000000}, 719 {0x00008008, 0x00000000},
1138 {0x0000a1ac, 0x00000000}, 720 {0x0000800c, 0x00000000},
1139 {0x0000a1b0, 0x00000000}, 721 {0x00008018, 0x00000000},
1140 {0x0000a1b4, 0x00000000}, 722 {0x00008020, 0x00000000},
1141 {0x0000a1b8, 0x00000000}, 723 {0x00008038, 0x00000000},
1142 {0x0000a1bc, 0x00000000}, 724 {0x0000803c, 0x00000000},
1143 {0x0000a1c0, 0x00000000}, 725 {0x00008040, 0x00000000},
1144 {0x0000a1c4, 0x00000000}, 726 {0x00008044, 0x00000000},
1145 {0x0000a1c8, 0x00000000}, 727 {0x00008048, 0x00000000},
1146 {0x0000a1cc, 0x00000000}, 728 {0x0000804c, 0xffffffff},
1147 {0x0000a1d0, 0x00000000}, 729 {0x00008054, 0x00000000},
1148 {0x0000a1d4, 0x00000000}, 730 {0x00008058, 0x00000000},
1149 {0x0000a1d8, 0x00000000}, 731 {0x0000805c, 0x000fc78f},
1150 {0x0000a1dc, 0x00000000}, 732 {0x00008060, 0x0000000f},
1151 {0x0000a1e0, 0x00000000}, 733 {0x00008064, 0x00000000},
1152 {0x0000a1e4, 0x00000000}, 734 {0x00008070, 0x00000310},
1153 {0x0000a1e8, 0x00000000}, 735 {0x00008074, 0x00000020},
1154 {0x0000a1ec, 0x00000000}, 736 {0x00008078, 0x00000000},
1155 {0x0000a1f0, 0x00000396}, 737 {0x0000809c, 0x0000000f},
1156 {0x0000a1f4, 0x00000396}, 738 {0x000080a0, 0x00000000},
1157 {0x0000a1f8, 0x00000396}, 739 {0x000080a4, 0x02ff0000},
1158 {0x0000a1fc, 0x00000296}, 740 {0x000080a8, 0x0e070605},
741 {0x000080ac, 0x0000000d},
742 {0x000080b0, 0x00000000},
743 {0x000080b4, 0x00000000},
744 {0x000080b8, 0x00000000},
745 {0x000080bc, 0x00000000},
746 {0x000080c0, 0x2a800000},
747 {0x000080c4, 0x06900168},
748 {0x000080c8, 0x13881c22},
749 {0x000080cc, 0x01f40000},
750 {0x000080d0, 0x00252500},
751 {0x000080d4, 0x00a00000},
752 {0x000080d8, 0x00400000},
753 {0x000080dc, 0x00000000},
754 {0x000080e0, 0xffffffff},
755 {0x000080e4, 0x0000ffff},
756 {0x000080e8, 0x3f3f3f3f},
757 {0x000080ec, 0x00000000},
758 {0x000080f0, 0x00000000},
759 {0x000080f4, 0x00000000},
760 {0x000080fc, 0x00020000},
761 {0x00008100, 0x00000000},
762 {0x00008108, 0x00000052},
763 {0x0000810c, 0x00000000},
764 {0x00008110, 0x00000000},
765 {0x00008114, 0x000007ff},
766 {0x00008118, 0x000000aa},
767 {0x0000811c, 0x00003210},
768 {0x00008124, 0x00000000},
769 {0x00008128, 0x00000000},
770 {0x0000812c, 0x00000000},
771 {0x00008130, 0x00000000},
772 {0x00008134, 0x00000000},
773 {0x00008138, 0x00000000},
774 {0x0000813c, 0x0000ffff},
775 {0x00008144, 0xffffffff},
776 {0x00008168, 0x00000000},
777 {0x0000816c, 0x00000000},
778 {0x00008170, 0x18486200},
779 {0x00008174, 0x33332210},
780 {0x00008178, 0x00000000},
781 {0x0000817c, 0x00020000},
782 {0x000081c0, 0x00000000},
783 {0x000081c4, 0x33332210},
784 {0x000081d4, 0x00000000},
785 {0x000081ec, 0x00000000},
786 {0x000081f0, 0x00000000},
787 {0x000081f4, 0x00000000},
788 {0x000081f8, 0x00000000},
789 {0x000081fc, 0x00000000},
790 {0x00008240, 0x00100000},
791 {0x00008244, 0x0010f400},
792 {0x00008248, 0x00000800},
793 {0x0000824c, 0x0001e800},
794 {0x00008250, 0x00000000},
795 {0x00008254, 0x00000000},
796 {0x00008258, 0x00000000},
797 {0x0000825c, 0x40000000},
798 {0x00008260, 0x00080922},
799 {0x00008264, 0x9ca00010},
800 {0x00008268, 0xffffffff},
801 {0x0000826c, 0x0000ffff},
802 {0x00008270, 0x00000000},
803 {0x00008274, 0x40000000},
804 {0x00008278, 0x003e4180},
805 {0x0000827c, 0x00000004},
806 {0x00008284, 0x0000002c},
807 {0x00008288, 0x0000002c},
808 {0x0000828c, 0x000000ff},
809 {0x00008294, 0x00000000},
810 {0x00008298, 0x00000000},
811 {0x0000829c, 0x00000000},
812 {0x00008300, 0x00000140},
813 {0x00008314, 0x00000000},
814 {0x0000831c, 0x0000010d},
815 {0x00008328, 0x00000000},
816 {0x0000832c, 0x00000007},
817 {0x00008330, 0x00000302},
818 {0x00008334, 0x00000700},
819 {0x00008338, 0x00ff0000},
820 {0x0000833c, 0x02400000},
821 {0x00008340, 0x000107ff},
822 {0x00008344, 0xa248105b},
823 {0x00008348, 0x008f0000},
824 {0x0000835c, 0x00000000},
825 {0x00008360, 0xffffffff},
826 {0x00008364, 0xffffffff},
827 {0x00008368, 0x00000000},
828 {0x00008370, 0x00000000},
829 {0x00008374, 0x000000ff},
830 {0x00008378, 0x00000000},
831 {0x0000837c, 0x00000000},
832 {0x00008380, 0xffffffff},
833 {0x00008384, 0xffffffff},
834 {0x00008390, 0xffffffff},
835 {0x00008394, 0xffffffff},
836 {0x00008398, 0x00000000},
837 {0x0000839c, 0x00000000},
838 {0x000083a0, 0x00000000},
839 {0x000083a4, 0x0000fa14},
840 {0x000083a8, 0x000f0c00},
841 {0x000083ac, 0x33332210},
842 {0x000083b0, 0x33332210},
843 {0x000083b4, 0x33332210},
844 {0x000083b8, 0x33332210},
845 {0x000083bc, 0x00000000},
846 {0x000083c0, 0x00000000},
847 {0x000083c4, 0x00000000},
848 {0x000083c8, 0x00000000},
849 {0x000083cc, 0x00000200},
850 {0x000083d0, 0x000301ff},
1159}; 851};
1160 852
1161#endif 853#endif /* INITVALS_9485_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
index 06b3f0df9fad..6e1915aee712 100644
--- a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2010 Atheros Communications Inc. 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
3 * 4 *
4 * Permission to use, copy, modify, and/or distribute this software for any 5 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 6 * purpose with or without fee is hereby granted, provided that the above
@@ -19,18 +20,7 @@
19 20
20/* AR9580 1.0 */ 21/* AR9580 1.0 */
21 22
22static const u32 ar9580_1p0_modes_fast_clock[][3] = { 23#define ar9580_1p0_modes_fast_clock ar9300Modes_fast_clock_2p2
23 /* Addr 5G_HT20 5G_HT40 */
24 {0x00001030, 0x00000268, 0x000004d0},
25 {0x00001070, 0x0000018c, 0x00000318},
26 {0x000010b0, 0x00000fd0, 0x00001fa0},
27 {0x00008014, 0x044c044c, 0x08980898},
28 {0x0000801c, 0x148ec02b, 0x148ec057},
29 {0x00008318, 0x000044c0, 0x00008980},
30 {0x00009e00, 0x0372131c, 0x0372131c},
31 {0x0000a230, 0x0000000b, 0x00000016},
32 {0x0000a254, 0x00000898, 0x00001130},
33};
34 24
35static const u32 ar9580_1p0_radio_postamble[][5] = { 25static const u32 ar9580_1p0_radio_postamble[][5] = {
36 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 26 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
@@ -208,17 +198,7 @@ static const u32 ar9580_1p0_baseband_core[][2] = {
208 {0x0000c420, 0x00000000}, 198 {0x0000c420, 0x00000000},
209}; 199};
210 200
211static const u32 ar9580_1p0_mac_postamble[][5] = { 201#define ar9580_1p0_mac_postamble ar9300_2p2_mac_postamble
212 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
213 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
214 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
215 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
216 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
217 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
218 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
219 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
220 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
221};
222 202
223static const u32 ar9580_1p0_low_ob_db_tx_gain_table[][5] = { 203static const u32 ar9580_1p0_low_ob_db_tx_gain_table[][5] = {
224 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 204 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
@@ -326,111 +306,7 @@ static const u32 ar9580_1p0_low_ob_db_tx_gain_table[][5] = {
326 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, 306 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
327}; 307};
328 308
329static const u32 ar9580_1p0_high_power_tx_gain_table[][5] = { 309#define ar9580_1p0_high_power_tx_gain_table ar9580_1p0_low_ob_db_tx_gain_table
330 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
331 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
332 {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
333 {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
334 {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
335 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
336 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
337 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
338 {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
339 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
340 {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
341 {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
342 {0x0000a518, 0x21002220, 0x21002220, 0x16000402, 0x16000402},
343 {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404},
344 {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
345 {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
346 {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
347 {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
348 {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
349 {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
350 {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
351 {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
352 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
353 {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
354 {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
355 {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x47001a83, 0x47001a83},
356 {0x0000a550, 0x61024a6c, 0x61024a6c, 0x4a001c84, 0x4a001c84},
357 {0x0000a554, 0x66026a6c, 0x66026a6c, 0x4e001ce3, 0x4e001ce3},
358 {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x52001ce5, 0x52001ce5},
359 {0x0000a55c, 0x7002708c, 0x7002708c, 0x56001ce9, 0x56001ce9},
360 {0x0000a560, 0x7302b08a, 0x7302b08a, 0x5a001ceb, 0x5a001ceb},
361 {0x0000a564, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
362 {0x0000a568, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
363 {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
364 {0x0000a570, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
365 {0x0000a574, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
366 {0x0000a578, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
367 {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
368 {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
369 {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
370 {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
371 {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
372 {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
373 {0x0000a594, 0x1c800223, 0x1c800223, 0x12800400, 0x12800400},
374 {0x0000a598, 0x21802220, 0x21802220, 0x16800402, 0x16800402},
375 {0x0000a59c, 0x27802223, 0x27802223, 0x19800404, 0x19800404},
376 {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1c800603, 0x1c800603},
377 {0x0000a5a4, 0x2f822222, 0x2f822222, 0x21800a02, 0x21800a02},
378 {0x0000a5a8, 0x34822225, 0x34822225, 0x25800a04, 0x25800a04},
379 {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x28800a20, 0x28800a20},
380 {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2c800e20, 0x2c800e20},
381 {0x0000a5b4, 0x4282242a, 0x4282242a, 0x30800e22, 0x30800e22},
382 {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
383 {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
384 {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
385 {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
386 {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
387 {0x0000a5cc, 0x5c82486b, 0x5c82486b, 0x47801a83, 0x47801a83},
388 {0x0000a5d0, 0x61824a6c, 0x61824a6c, 0x4a801c84, 0x4a801c84},
389 {0x0000a5d4, 0x66826a6c, 0x66826a6c, 0x4e801ce3, 0x4e801ce3},
390 {0x0000a5d8, 0x6b826e6c, 0x6b826e6c, 0x52801ce5, 0x52801ce5},
391 {0x0000a5dc, 0x7082708c, 0x7082708c, 0x56801ce9, 0x56801ce9},
392 {0x0000a5e0, 0x7382b08a, 0x7382b08a, 0x5a801ceb, 0x5a801ceb},
393 {0x0000a5e4, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
394 {0x0000a5e8, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
395 {0x0000a5ec, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
396 {0x0000a5f0, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
397 {0x0000a5f4, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
398 {0x0000a5f8, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
399 {0x0000a5fc, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
400 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
401 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
402 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
403 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
404 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
405 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
406 {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
407 {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
408 {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
409 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
410 {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
411 {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
412 {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
413 {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
414 {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
415 {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
416 {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
417 {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
418 {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
419 {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
420 {0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
421 {0x0000c2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
422 {0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
423 {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
424 {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
425 {0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
426 {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
427 {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
428 {0x00016448, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
429 {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
430 {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
431 {0x00016848, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
432 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
433};
434 310
435static const u32 ar9580_1p0_lowest_ob_db_tx_gain_table[][5] = { 311static const u32 ar9580_1p0_lowest_ob_db_tx_gain_table[][5] = {
436 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 312 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
@@ -538,12 +414,7 @@ static const u32 ar9580_1p0_lowest_ob_db_tx_gain_table[][5] = {
538 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, 414 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
539}; 415};
540 416
541static const u32 ar9580_1p0_baseband_core_txfir_coeff_japan_2484[][2] = { 417#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
542 /* Addr allmodes */
543 {0x0000a398, 0x00000000},
544 {0x0000a39c, 0x6f7f0301},
545 {0x0000a3a0, 0xca9228ee},
546};
547 418
548static const u32 ar9580_1p0_mac_core[][2] = { 419static const u32 ar9580_1p0_mac_core[][2] = {
549 /* Addr allmodes */ 420 /* Addr allmodes */
@@ -808,376 +679,11 @@ static const u32 ar9580_1p0_mixed_ob_db_tx_gain_table[][5] = {
808 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, 679 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
809}; 680};
810 681
811static const u32 ar9580_1p0_wo_xlna_rx_gain_table[][2] = { 682#define ar9580_1p0_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
812 /* Addr allmodes */
813 {0x0000a000, 0x00010000},
814 {0x0000a004, 0x00030002},
815 {0x0000a008, 0x00050004},
816 {0x0000a00c, 0x00810080},
817 {0x0000a010, 0x00830082},
818 {0x0000a014, 0x01810180},
819 {0x0000a018, 0x01830182},
820 {0x0000a01c, 0x01850184},
821 {0x0000a020, 0x01890188},
822 {0x0000a024, 0x018b018a},
823 {0x0000a028, 0x018d018c},
824 {0x0000a02c, 0x03820190},
825 {0x0000a030, 0x03840383},
826 {0x0000a034, 0x03880385},
827 {0x0000a038, 0x038a0389},
828 {0x0000a03c, 0x038c038b},
829 {0x0000a040, 0x0390038d},
830 {0x0000a044, 0x03920391},
831 {0x0000a048, 0x03940393},
832 {0x0000a04c, 0x03960395},
833 {0x0000a050, 0x00000000},
834 {0x0000a054, 0x00000000},
835 {0x0000a058, 0x00000000},
836 {0x0000a05c, 0x00000000},
837 {0x0000a060, 0x00000000},
838 {0x0000a064, 0x00000000},
839 {0x0000a068, 0x00000000},
840 {0x0000a06c, 0x00000000},
841 {0x0000a070, 0x00000000},
842 {0x0000a074, 0x00000000},
843 {0x0000a078, 0x00000000},
844 {0x0000a07c, 0x00000000},
845 {0x0000a080, 0x29292929},
846 {0x0000a084, 0x29292929},
847 {0x0000a088, 0x29292929},
848 {0x0000a08c, 0x29292929},
849 {0x0000a090, 0x22292929},
850 {0x0000a094, 0x1d1d2222},
851 {0x0000a098, 0x0c111117},
852 {0x0000a09c, 0x00030303},
853 {0x0000a0a0, 0x00000000},
854 {0x0000a0a4, 0x00000000},
855 {0x0000a0a8, 0x00000000},
856 {0x0000a0ac, 0x00000000},
857 {0x0000a0b0, 0x00000000},
858 {0x0000a0b4, 0x00000000},
859 {0x0000a0b8, 0x00000000},
860 {0x0000a0bc, 0x00000000},
861 {0x0000a0c0, 0x001f0000},
862 {0x0000a0c4, 0x01000101},
863 {0x0000a0c8, 0x011e011f},
864 {0x0000a0cc, 0x011c011d},
865 {0x0000a0d0, 0x02030204},
866 {0x0000a0d4, 0x02010202},
867 {0x0000a0d8, 0x021f0200},
868 {0x0000a0dc, 0x0302021e},
869 {0x0000a0e0, 0x03000301},
870 {0x0000a0e4, 0x031e031f},
871 {0x0000a0e8, 0x0402031d},
872 {0x0000a0ec, 0x04000401},
873 {0x0000a0f0, 0x041e041f},
874 {0x0000a0f4, 0x0502041d},
875 {0x0000a0f8, 0x05000501},
876 {0x0000a0fc, 0x051e051f},
877 {0x0000a100, 0x06010602},
878 {0x0000a104, 0x061f0600},
879 {0x0000a108, 0x061d061e},
880 {0x0000a10c, 0x07020703},
881 {0x0000a110, 0x07000701},
882 {0x0000a114, 0x00000000},
883 {0x0000a118, 0x00000000},
884 {0x0000a11c, 0x00000000},
885 {0x0000a120, 0x00000000},
886 {0x0000a124, 0x00000000},
887 {0x0000a128, 0x00000000},
888 {0x0000a12c, 0x00000000},
889 {0x0000a130, 0x00000000},
890 {0x0000a134, 0x00000000},
891 {0x0000a138, 0x00000000},
892 {0x0000a13c, 0x00000000},
893 {0x0000a140, 0x001f0000},
894 {0x0000a144, 0x01000101},
895 {0x0000a148, 0x011e011f},
896 {0x0000a14c, 0x011c011d},
897 {0x0000a150, 0x02030204},
898 {0x0000a154, 0x02010202},
899 {0x0000a158, 0x021f0200},
900 {0x0000a15c, 0x0302021e},
901 {0x0000a160, 0x03000301},
902 {0x0000a164, 0x031e031f},
903 {0x0000a168, 0x0402031d},
904 {0x0000a16c, 0x04000401},
905 {0x0000a170, 0x041e041f},
906 {0x0000a174, 0x0502041d},
907 {0x0000a178, 0x05000501},
908 {0x0000a17c, 0x051e051f},
909 {0x0000a180, 0x06010602},
910 {0x0000a184, 0x061f0600},
911 {0x0000a188, 0x061d061e},
912 {0x0000a18c, 0x07020703},
913 {0x0000a190, 0x07000701},
914 {0x0000a194, 0x00000000},
915 {0x0000a198, 0x00000000},
916 {0x0000a19c, 0x00000000},
917 {0x0000a1a0, 0x00000000},
918 {0x0000a1a4, 0x00000000},
919 {0x0000a1a8, 0x00000000},
920 {0x0000a1ac, 0x00000000},
921 {0x0000a1b0, 0x00000000},
922 {0x0000a1b4, 0x00000000},
923 {0x0000a1b8, 0x00000000},
924 {0x0000a1bc, 0x00000000},
925 {0x0000a1c0, 0x00000000},
926 {0x0000a1c4, 0x00000000},
927 {0x0000a1c8, 0x00000000},
928 {0x0000a1cc, 0x00000000},
929 {0x0000a1d0, 0x00000000},
930 {0x0000a1d4, 0x00000000},
931 {0x0000a1d8, 0x00000000},
932 {0x0000a1dc, 0x00000000},
933 {0x0000a1e0, 0x00000000},
934 {0x0000a1e4, 0x00000000},
935 {0x0000a1e8, 0x00000000},
936 {0x0000a1ec, 0x00000000},
937 {0x0000a1f0, 0x00000396},
938 {0x0000a1f4, 0x00000396},
939 {0x0000a1f8, 0x00000396},
940 {0x0000a1fc, 0x00000196},
941 {0x0000b000, 0x00010000},
942 {0x0000b004, 0x00030002},
943 {0x0000b008, 0x00050004},
944 {0x0000b00c, 0x00810080},
945 {0x0000b010, 0x00830082},
946 {0x0000b014, 0x01810180},
947 {0x0000b018, 0x01830182},
948 {0x0000b01c, 0x01850184},
949 {0x0000b020, 0x02810280},
950 {0x0000b024, 0x02830282},
951 {0x0000b028, 0x02850284},
952 {0x0000b02c, 0x02890288},
953 {0x0000b030, 0x028b028a},
954 {0x0000b034, 0x0388028c},
955 {0x0000b038, 0x038a0389},
956 {0x0000b03c, 0x038c038b},
957 {0x0000b040, 0x0390038d},
958 {0x0000b044, 0x03920391},
959 {0x0000b048, 0x03940393},
960 {0x0000b04c, 0x03960395},
961 {0x0000b050, 0x00000000},
962 {0x0000b054, 0x00000000},
963 {0x0000b058, 0x00000000},
964 {0x0000b05c, 0x00000000},
965 {0x0000b060, 0x00000000},
966 {0x0000b064, 0x00000000},
967 {0x0000b068, 0x00000000},
968 {0x0000b06c, 0x00000000},
969 {0x0000b070, 0x00000000},
970 {0x0000b074, 0x00000000},
971 {0x0000b078, 0x00000000},
972 {0x0000b07c, 0x00000000},
973 {0x0000b080, 0x32323232},
974 {0x0000b084, 0x2f2f3232},
975 {0x0000b088, 0x23282a2d},
976 {0x0000b08c, 0x1c1e2123},
977 {0x0000b090, 0x14171919},
978 {0x0000b094, 0x0e0e1214},
979 {0x0000b098, 0x03050707},
980 {0x0000b09c, 0x00030303},
981 {0x0000b0a0, 0x00000000},
982 {0x0000b0a4, 0x00000000},
983 {0x0000b0a8, 0x00000000},
984 {0x0000b0ac, 0x00000000},
985 {0x0000b0b0, 0x00000000},
986 {0x0000b0b4, 0x00000000},
987 {0x0000b0b8, 0x00000000},
988 {0x0000b0bc, 0x00000000},
989 {0x0000b0c0, 0x003f0020},
990 {0x0000b0c4, 0x00400041},
991 {0x0000b0c8, 0x0140005f},
992 {0x0000b0cc, 0x0160015f},
993 {0x0000b0d0, 0x017e017f},
994 {0x0000b0d4, 0x02410242},
995 {0x0000b0d8, 0x025f0240},
996 {0x0000b0dc, 0x027f0260},
997 {0x0000b0e0, 0x0341027e},
998 {0x0000b0e4, 0x035f0340},
999 {0x0000b0e8, 0x037f0360},
1000 {0x0000b0ec, 0x04400441},
1001 {0x0000b0f0, 0x0460045f},
1002 {0x0000b0f4, 0x0541047f},
1003 {0x0000b0f8, 0x055f0540},
1004 {0x0000b0fc, 0x057f0560},
1005 {0x0000b100, 0x06400641},
1006 {0x0000b104, 0x0660065f},
1007 {0x0000b108, 0x067e067f},
1008 {0x0000b10c, 0x07410742},
1009 {0x0000b110, 0x075f0740},
1010 {0x0000b114, 0x077f0760},
1011 {0x0000b118, 0x07800781},
1012 {0x0000b11c, 0x07a0079f},
1013 {0x0000b120, 0x07c107bf},
1014 {0x0000b124, 0x000007c0},
1015 {0x0000b128, 0x00000000},
1016 {0x0000b12c, 0x00000000},
1017 {0x0000b130, 0x00000000},
1018 {0x0000b134, 0x00000000},
1019 {0x0000b138, 0x00000000},
1020 {0x0000b13c, 0x00000000},
1021 {0x0000b140, 0x003f0020},
1022 {0x0000b144, 0x00400041},
1023 {0x0000b148, 0x0140005f},
1024 {0x0000b14c, 0x0160015f},
1025 {0x0000b150, 0x017e017f},
1026 {0x0000b154, 0x02410242},
1027 {0x0000b158, 0x025f0240},
1028 {0x0000b15c, 0x027f0260},
1029 {0x0000b160, 0x0341027e},
1030 {0x0000b164, 0x035f0340},
1031 {0x0000b168, 0x037f0360},
1032 {0x0000b16c, 0x04400441},
1033 {0x0000b170, 0x0460045f},
1034 {0x0000b174, 0x0541047f},
1035 {0x0000b178, 0x055f0540},
1036 {0x0000b17c, 0x057f0560},
1037 {0x0000b180, 0x06400641},
1038 {0x0000b184, 0x0660065f},
1039 {0x0000b188, 0x067e067f},
1040 {0x0000b18c, 0x07410742},
1041 {0x0000b190, 0x075f0740},
1042 {0x0000b194, 0x077f0760},
1043 {0x0000b198, 0x07800781},
1044 {0x0000b19c, 0x07a0079f},
1045 {0x0000b1a0, 0x07c107bf},
1046 {0x0000b1a4, 0x000007c0},
1047 {0x0000b1a8, 0x00000000},
1048 {0x0000b1ac, 0x00000000},
1049 {0x0000b1b0, 0x00000000},
1050 {0x0000b1b4, 0x00000000},
1051 {0x0000b1b8, 0x00000000},
1052 {0x0000b1bc, 0x00000000},
1053 {0x0000b1c0, 0x00000000},
1054 {0x0000b1c4, 0x00000000},
1055 {0x0000b1c8, 0x00000000},
1056 {0x0000b1cc, 0x00000000},
1057 {0x0000b1d0, 0x00000000},
1058 {0x0000b1d4, 0x00000000},
1059 {0x0000b1d8, 0x00000000},
1060 {0x0000b1dc, 0x00000000},
1061 {0x0000b1e0, 0x00000000},
1062 {0x0000b1e4, 0x00000000},
1063 {0x0000b1e8, 0x00000000},
1064 {0x0000b1ec, 0x00000000},
1065 {0x0000b1f0, 0x00000396},
1066 {0x0000b1f4, 0x00000396},
1067 {0x0000b1f8, 0x00000396},
1068 {0x0000b1fc, 0x00000196},
1069};
1070 683
1071static const u32 ar9580_1p0_soc_postamble[][5] = { 684#define ar9580_1p0_soc_postamble ar9300_2p2_soc_postamble
1072 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1073 {0x00007010, 0x00000023, 0x00000023, 0x00000023, 0x00000023},
1074};
1075 685
1076static const u32 ar9580_1p0_high_ob_db_tx_gain_table[][5] = { 686#define ar9580_1p0_high_ob_db_tx_gain_table ar9300Modes_high_ob_db_tx_gain_table_2p2
1077 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1078 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
1079 {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
1080 {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
1081 {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
1082 {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
1083 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
1084 {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
1085 {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
1086 {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
1087 {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
1088 {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
1089 {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
1090 {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
1091 {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
1092 {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
1093 {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
1094 {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
1095 {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
1096 {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
1097 {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
1098 {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
1099 {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
1100 {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
1101 {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
1102 {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
1103 {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
1104 {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
1105 {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
1106 {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
1107 {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
1108 {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
1109 {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
1110 {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
1111 {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
1112 {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
1113 {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
1114 {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
1115 {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
1116 {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
1117 {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
1118 {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
1119 {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
1120 {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
1121 {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
1122 {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
1123 {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
1124 {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
1125 {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
1126 {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
1127 {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
1128 {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
1129 {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
1130 {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
1131 {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
1132 {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
1133 {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
1134 {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
1135 {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
1136 {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
1137 {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
1138 {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
1139 {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
1140 {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
1141 {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
1142 {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
1143 {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
1144 {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
1145 {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
1146 {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
1147 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1148 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1149 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1150 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1151 {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
1152 {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
1153 {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
1154 {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
1155 {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
1156 {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
1157 {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
1158 {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
1159 {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
1160 {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
1161 {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
1162 {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
1163 {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
1164 {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
1165 {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
1166 {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
1167 {0x0000c2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
1168 {0x0000c2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
1169 {0x0000c2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
1170 {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
1171 {0x00016044, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
1172 {0x00016048, 0x8e480001, 0x8e480001, 0x8e480001, 0x8e480001},
1173 {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
1174 {0x00016444, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
1175 {0x00016448, 0x8e480001, 0x8e480001, 0x8e480001, 0x8e480001},
1176 {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
1177 {0x00016844, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
1178 {0x00016848, 0x8e480001, 0x8e480001, 0x8e480001, 0x8e480001},
1179 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
1180};
1181 687
1182static const u32 ar9580_1p0_soc_preamble[][2] = { 688static const u32 ar9580_1p0_soc_preamble[][2] = {
1183 /* Addr allmodes */ 689 /* Addr allmodes */
@@ -1189,265 +695,7 @@ static const u32 ar9580_1p0_soc_preamble[][2] = {
1189 {0x00007048, 0x00000008}, 695 {0x00007048, 0x00000008},
1190}; 696};
1191 697
1192static const u32 ar9580_1p0_rx_gain_table[][2] = { 698#define ar9580_1p0_rx_gain_table ar9462_common_rx_gain_table_2p0
1193 /* Addr allmodes */
1194 {0x0000a000, 0x00010000},
1195 {0x0000a004, 0x00030002},
1196 {0x0000a008, 0x00050004},
1197 {0x0000a00c, 0x00810080},
1198 {0x0000a010, 0x00830082},
1199 {0x0000a014, 0x01810180},
1200 {0x0000a018, 0x01830182},
1201 {0x0000a01c, 0x01850184},
1202 {0x0000a020, 0x01890188},
1203 {0x0000a024, 0x018b018a},
1204 {0x0000a028, 0x018d018c},
1205 {0x0000a02c, 0x01910190},
1206 {0x0000a030, 0x01930192},
1207 {0x0000a034, 0x01950194},
1208 {0x0000a038, 0x038a0196},
1209 {0x0000a03c, 0x038c038b},
1210 {0x0000a040, 0x0390038d},
1211 {0x0000a044, 0x03920391},
1212 {0x0000a048, 0x03940393},
1213 {0x0000a04c, 0x03960395},
1214 {0x0000a050, 0x00000000},
1215 {0x0000a054, 0x00000000},
1216 {0x0000a058, 0x00000000},
1217 {0x0000a05c, 0x00000000},
1218 {0x0000a060, 0x00000000},
1219 {0x0000a064, 0x00000000},
1220 {0x0000a068, 0x00000000},
1221 {0x0000a06c, 0x00000000},
1222 {0x0000a070, 0x00000000},
1223 {0x0000a074, 0x00000000},
1224 {0x0000a078, 0x00000000},
1225 {0x0000a07c, 0x00000000},
1226 {0x0000a080, 0x22222229},
1227 {0x0000a084, 0x1d1d1d1d},
1228 {0x0000a088, 0x1d1d1d1d},
1229 {0x0000a08c, 0x1d1d1d1d},
1230 {0x0000a090, 0x171d1d1d},
1231 {0x0000a094, 0x11111717},
1232 {0x0000a098, 0x00030311},
1233 {0x0000a09c, 0x00000000},
1234 {0x0000a0a0, 0x00000000},
1235 {0x0000a0a4, 0x00000000},
1236 {0x0000a0a8, 0x00000000},
1237 {0x0000a0ac, 0x00000000},
1238 {0x0000a0b0, 0x00000000},
1239 {0x0000a0b4, 0x00000000},
1240 {0x0000a0b8, 0x00000000},
1241 {0x0000a0bc, 0x00000000},
1242 {0x0000a0c0, 0x001f0000},
1243 {0x0000a0c4, 0x01000101},
1244 {0x0000a0c8, 0x011e011f},
1245 {0x0000a0cc, 0x011c011d},
1246 {0x0000a0d0, 0x02030204},
1247 {0x0000a0d4, 0x02010202},
1248 {0x0000a0d8, 0x021f0200},
1249 {0x0000a0dc, 0x0302021e},
1250 {0x0000a0e0, 0x03000301},
1251 {0x0000a0e4, 0x031e031f},
1252 {0x0000a0e8, 0x0402031d},
1253 {0x0000a0ec, 0x04000401},
1254 {0x0000a0f0, 0x041e041f},
1255 {0x0000a0f4, 0x0502041d},
1256 {0x0000a0f8, 0x05000501},
1257 {0x0000a0fc, 0x051e051f},
1258 {0x0000a100, 0x06010602},
1259 {0x0000a104, 0x061f0600},
1260 {0x0000a108, 0x061d061e},
1261 {0x0000a10c, 0x07020703},
1262 {0x0000a110, 0x07000701},
1263 {0x0000a114, 0x00000000},
1264 {0x0000a118, 0x00000000},
1265 {0x0000a11c, 0x00000000},
1266 {0x0000a120, 0x00000000},
1267 {0x0000a124, 0x00000000},
1268 {0x0000a128, 0x00000000},
1269 {0x0000a12c, 0x00000000},
1270 {0x0000a130, 0x00000000},
1271 {0x0000a134, 0x00000000},
1272 {0x0000a138, 0x00000000},
1273 {0x0000a13c, 0x00000000},
1274 {0x0000a140, 0x001f0000},
1275 {0x0000a144, 0x01000101},
1276 {0x0000a148, 0x011e011f},
1277 {0x0000a14c, 0x011c011d},
1278 {0x0000a150, 0x02030204},
1279 {0x0000a154, 0x02010202},
1280 {0x0000a158, 0x021f0200},
1281 {0x0000a15c, 0x0302021e},
1282 {0x0000a160, 0x03000301},
1283 {0x0000a164, 0x031e031f},
1284 {0x0000a168, 0x0402031d},
1285 {0x0000a16c, 0x04000401},
1286 {0x0000a170, 0x041e041f},
1287 {0x0000a174, 0x0502041d},
1288 {0x0000a178, 0x05000501},
1289 {0x0000a17c, 0x051e051f},
1290 {0x0000a180, 0x06010602},
1291 {0x0000a184, 0x061f0600},
1292 {0x0000a188, 0x061d061e},
1293 {0x0000a18c, 0x07020703},
1294 {0x0000a190, 0x07000701},
1295 {0x0000a194, 0x00000000},
1296 {0x0000a198, 0x00000000},
1297 {0x0000a19c, 0x00000000},
1298 {0x0000a1a0, 0x00000000},
1299 {0x0000a1a4, 0x00000000},
1300 {0x0000a1a8, 0x00000000},
1301 {0x0000a1ac, 0x00000000},
1302 {0x0000a1b0, 0x00000000},
1303 {0x0000a1b4, 0x00000000},
1304 {0x0000a1b8, 0x00000000},
1305 {0x0000a1bc, 0x00000000},
1306 {0x0000a1c0, 0x00000000},
1307 {0x0000a1c4, 0x00000000},
1308 {0x0000a1c8, 0x00000000},
1309 {0x0000a1cc, 0x00000000},
1310 {0x0000a1d0, 0x00000000},
1311 {0x0000a1d4, 0x00000000},
1312 {0x0000a1d8, 0x00000000},
1313 {0x0000a1dc, 0x00000000},
1314 {0x0000a1e0, 0x00000000},
1315 {0x0000a1e4, 0x00000000},
1316 {0x0000a1e8, 0x00000000},
1317 {0x0000a1ec, 0x00000000},
1318 {0x0000a1f0, 0x00000396},
1319 {0x0000a1f4, 0x00000396},
1320 {0x0000a1f8, 0x00000396},
1321 {0x0000a1fc, 0x00000196},
1322 {0x0000b000, 0x00010000},
1323 {0x0000b004, 0x00030002},
1324 {0x0000b008, 0x00050004},
1325 {0x0000b00c, 0x00810080},
1326 {0x0000b010, 0x00830082},
1327 {0x0000b014, 0x01810180},
1328 {0x0000b018, 0x01830182},
1329 {0x0000b01c, 0x01850184},
1330 {0x0000b020, 0x02810280},
1331 {0x0000b024, 0x02830282},
1332 {0x0000b028, 0x02850284},
1333 {0x0000b02c, 0x02890288},
1334 {0x0000b030, 0x028b028a},
1335 {0x0000b034, 0x0388028c},
1336 {0x0000b038, 0x038a0389},
1337 {0x0000b03c, 0x038c038b},
1338 {0x0000b040, 0x0390038d},
1339 {0x0000b044, 0x03920391},
1340 {0x0000b048, 0x03940393},
1341 {0x0000b04c, 0x03960395},
1342 {0x0000b050, 0x00000000},
1343 {0x0000b054, 0x00000000},
1344 {0x0000b058, 0x00000000},
1345 {0x0000b05c, 0x00000000},
1346 {0x0000b060, 0x00000000},
1347 {0x0000b064, 0x00000000},
1348 {0x0000b068, 0x00000000},
1349 {0x0000b06c, 0x00000000},
1350 {0x0000b070, 0x00000000},
1351 {0x0000b074, 0x00000000},
1352 {0x0000b078, 0x00000000},
1353 {0x0000b07c, 0x00000000},
1354 {0x0000b080, 0x2a2d2f32},
1355 {0x0000b084, 0x21232328},
1356 {0x0000b088, 0x19191c1e},
1357 {0x0000b08c, 0x12141417},
1358 {0x0000b090, 0x07070e0e},
1359 {0x0000b094, 0x03030305},
1360 {0x0000b098, 0x00000003},
1361 {0x0000b09c, 0x00000000},
1362 {0x0000b0a0, 0x00000000},
1363 {0x0000b0a4, 0x00000000},
1364 {0x0000b0a8, 0x00000000},
1365 {0x0000b0ac, 0x00000000},
1366 {0x0000b0b0, 0x00000000},
1367 {0x0000b0b4, 0x00000000},
1368 {0x0000b0b8, 0x00000000},
1369 {0x0000b0bc, 0x00000000},
1370 {0x0000b0c0, 0x003f0020},
1371 {0x0000b0c4, 0x00400041},
1372 {0x0000b0c8, 0x0140005f},
1373 {0x0000b0cc, 0x0160015f},
1374 {0x0000b0d0, 0x017e017f},
1375 {0x0000b0d4, 0x02410242},
1376 {0x0000b0d8, 0x025f0240},
1377 {0x0000b0dc, 0x027f0260},
1378 {0x0000b0e0, 0x0341027e},
1379 {0x0000b0e4, 0x035f0340},
1380 {0x0000b0e8, 0x037f0360},
1381 {0x0000b0ec, 0x04400441},
1382 {0x0000b0f0, 0x0460045f},
1383 {0x0000b0f4, 0x0541047f},
1384 {0x0000b0f8, 0x055f0540},
1385 {0x0000b0fc, 0x057f0560},
1386 {0x0000b100, 0x06400641},
1387 {0x0000b104, 0x0660065f},
1388 {0x0000b108, 0x067e067f},
1389 {0x0000b10c, 0x07410742},
1390 {0x0000b110, 0x075f0740},
1391 {0x0000b114, 0x077f0760},
1392 {0x0000b118, 0x07800781},
1393 {0x0000b11c, 0x07a0079f},
1394 {0x0000b120, 0x07c107bf},
1395 {0x0000b124, 0x000007c0},
1396 {0x0000b128, 0x00000000},
1397 {0x0000b12c, 0x00000000},
1398 {0x0000b130, 0x00000000},
1399 {0x0000b134, 0x00000000},
1400 {0x0000b138, 0x00000000},
1401 {0x0000b13c, 0x00000000},
1402 {0x0000b140, 0x003f0020},
1403 {0x0000b144, 0x00400041},
1404 {0x0000b148, 0x0140005f},
1405 {0x0000b14c, 0x0160015f},
1406 {0x0000b150, 0x017e017f},
1407 {0x0000b154, 0x02410242},
1408 {0x0000b158, 0x025f0240},
1409 {0x0000b15c, 0x027f0260},
1410 {0x0000b160, 0x0341027e},
1411 {0x0000b164, 0x035f0340},
1412 {0x0000b168, 0x037f0360},
1413 {0x0000b16c, 0x04400441},
1414 {0x0000b170, 0x0460045f},
1415 {0x0000b174, 0x0541047f},
1416 {0x0000b178, 0x055f0540},
1417 {0x0000b17c, 0x057f0560},
1418 {0x0000b180, 0x06400641},
1419 {0x0000b184, 0x0660065f},
1420 {0x0000b188, 0x067e067f},
1421 {0x0000b18c, 0x07410742},
1422 {0x0000b190, 0x075f0740},
1423 {0x0000b194, 0x077f0760},
1424 {0x0000b198, 0x07800781},
1425 {0x0000b19c, 0x07a0079f},
1426 {0x0000b1a0, 0x07c107bf},
1427 {0x0000b1a4, 0x000007c0},
1428 {0x0000b1a8, 0x00000000},
1429 {0x0000b1ac, 0x00000000},
1430 {0x0000b1b0, 0x00000000},
1431 {0x0000b1b4, 0x00000000},
1432 {0x0000b1b8, 0x00000000},
1433 {0x0000b1bc, 0x00000000},
1434 {0x0000b1c0, 0x00000000},
1435 {0x0000b1c4, 0x00000000},
1436 {0x0000b1c8, 0x00000000},
1437 {0x0000b1cc, 0x00000000},
1438 {0x0000b1d0, 0x00000000},
1439 {0x0000b1d4, 0x00000000},
1440 {0x0000b1d8, 0x00000000},
1441 {0x0000b1dc, 0x00000000},
1442 {0x0000b1e0, 0x00000000},
1443 {0x0000b1e4, 0x00000000},
1444 {0x0000b1e8, 0x00000000},
1445 {0x0000b1ec, 0x00000000},
1446 {0x0000b1f0, 0x00000396},
1447 {0x0000b1f4, 0x00000396},
1448 {0x0000b1f8, 0x00000396},
1449 {0x0000b1fc, 0x00000196},
1450};
1451 699
1452static const u32 ar9580_1p0_radio_core[][2] = { 700static const u32 ar9580_1p0_radio_core[][2] = {
1453 /* Addr allmodes */ 701 /* Addr allmodes */
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index f72c4a36d01b..fe39eb4c42a1 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -722,6 +722,7 @@ extern int ath9k_modparam_nohwcrypt;
722extern int led_blink; 722extern int led_blink;
723extern bool is_ath9k_unloaded; 723extern bool is_ath9k_unloaded;
724 724
725u8 ath9k_parse_mpdudensity(u8 mpdudensity);
725irqreturn_t ath_isr(int irq, void *dev); 726irqreturn_t ath_isr(int irq, void *dev);
726int ath9k_init_device(u16 devid, struct ath_softc *sc, 727int ath9k_init_device(u16 devid, struct ath_softc *sc,
727 const struct ath_bus_ops *bus_ops); 728 const struct ath_bus_ops *bus_ops);
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
index 2831258d9507..5c3192ffc196 100644
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -348,8 +348,6 @@ void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status)
348 sc->debug.stats.istats.txok++; 348 sc->debug.stats.istats.txok++;
349 if (status & ATH9K_INT_TXURN) 349 if (status & ATH9K_INT_TXURN)
350 sc->debug.stats.istats.txurn++; 350 sc->debug.stats.istats.txurn++;
351 if (status & ATH9K_INT_MIB)
352 sc->debug.stats.istats.mib++;
353 if (status & ATH9K_INT_RXPHY) 351 if (status & ATH9K_INT_RXPHY)
354 sc->debug.stats.istats.rxphyerr++; 352 sc->debug.stats.istats.rxphyerr++;
355 if (status & ATH9K_INT_RXKCM) 353 if (status & ATH9K_INT_RXKCM)
diff --git a/drivers/net/wireless/ath/ath9k/gpio.c b/drivers/net/wireless/ath/ath9k/gpio.c
index 26032cb59b8a..9ae6a4d97691 100644
--- a/drivers/net/wireless/ath/ath9k/gpio.c
+++ b/drivers/net/wireless/ath/ath9k/gpio.c
@@ -416,7 +416,7 @@ int ath9k_init_btcoex(struct ath_softc *sc)
416 txq = sc->tx.txq_map[WME_AC_BE]; 416 txq = sc->tx.txq_map[WME_AC_BE];
417 ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum); 417 ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum);
418 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW; 418 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
419 if (AR_SREV_9462(ah)) { 419 if (ath9k_hw_mci_is_enabled(ah)) {
420 sc->btcoex.duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE; 420 sc->btcoex.duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE;
421 INIT_LIST_HEAD(&sc->btcoex.mci.info); 421 INIT_LIST_HEAD(&sc->btcoex.mci.info);
422 422
diff --git a/drivers/net/wireless/ath/ath9k/htc.h b/drivers/net/wireless/ath/ath9k/htc.h
index 135795257d95..936e920fb88e 100644
--- a/drivers/net/wireless/ath/ath9k/htc.h
+++ b/drivers/net/wireless/ath/ath9k/htc.h
@@ -453,7 +453,6 @@ struct ath9k_htc_priv {
453 u8 num_sta_assoc_vif; 453 u8 num_sta_assoc_vif;
454 u8 num_ap_vif; 454 u8 num_ap_vif;
455 455
456 u16 op_flags;
457 u16 curtxpow; 456 u16 curtxpow;
458 u16 txpowlimit; 457 u16 txpowlimit;
459 u16 nvifs; 458 u16 nvifs;
@@ -461,6 +460,7 @@ struct ath9k_htc_priv {
461 bool rearm_ani; 460 bool rearm_ani;
462 bool reconfig_beacon; 461 bool reconfig_beacon;
463 unsigned int rxfilter; 462 unsigned int rxfilter;
463 unsigned long op_flags;
464 464
465 struct ath9k_hw_cal_data caldata; 465 struct ath9k_hw_cal_data caldata;
466 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 466 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
@@ -572,8 +572,6 @@ bool ath9k_htc_setpower(struct ath9k_htc_priv *priv,
572 572
573void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv); 573void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv);
574void ath9k_htc_rfkill_poll_state(struct ieee80211_hw *hw); 574void ath9k_htc_rfkill_poll_state(struct ieee80211_hw *hw);
575void ath9k_htc_radio_enable(struct ieee80211_hw *hw);
576void ath9k_htc_radio_disable(struct ieee80211_hw *hw);
577 575
578#ifdef CONFIG_MAC80211_LEDS 576#ifdef CONFIG_MAC80211_LEDS
579void ath9k_init_leds(struct ath9k_htc_priv *priv); 577void ath9k_init_leds(struct ath9k_htc_priv *priv);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
index 2eadffb7971c..77d541feb910 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
@@ -207,9 +207,9 @@ static void ath9k_htc_beacon_config_ap(struct ath9k_htc_priv *priv,
207 else 207 else
208 priv->ah->config.sw_beacon_response_time = MIN_SWBA_RESPONSE; 208 priv->ah->config.sw_beacon_response_time = MIN_SWBA_RESPONSE;
209 209
210 if (priv->op_flags & OP_TSF_RESET) { 210 if (test_bit(OP_TSF_RESET, &priv->op_flags)) {
211 ath9k_hw_reset_tsf(priv->ah); 211 ath9k_hw_reset_tsf(priv->ah);
212 priv->op_flags &= ~OP_TSF_RESET; 212 clear_bit(OP_TSF_RESET, &priv->op_flags);
213 } else { 213 } else {
214 /* 214 /*
215 * Pull nexttbtt forward to reflect the current TSF. 215 * Pull nexttbtt forward to reflect the current TSF.
@@ -221,7 +221,7 @@ static void ath9k_htc_beacon_config_ap(struct ath9k_htc_priv *priv,
221 } while (nexttbtt < tsftu); 221 } while (nexttbtt < tsftu);
222 } 222 }
223 223
224 if (priv->op_flags & OP_ENABLE_BEACON) 224 if (test_bit(OP_ENABLE_BEACON, &priv->op_flags))
225 imask |= ATH9K_INT_SWBA; 225 imask |= ATH9K_INT_SWBA;
226 226
227 ath_dbg(common, CONFIG, 227 ath_dbg(common, CONFIG,
@@ -269,7 +269,7 @@ static void ath9k_htc_beacon_config_adhoc(struct ath9k_htc_priv *priv,
269 else 269 else
270 priv->ah->config.sw_beacon_response_time = MIN_SWBA_RESPONSE; 270 priv->ah->config.sw_beacon_response_time = MIN_SWBA_RESPONSE;
271 271
272 if (priv->op_flags & OP_ENABLE_BEACON) 272 if (test_bit(OP_ENABLE_BEACON, &priv->op_flags))
273 imask |= ATH9K_INT_SWBA; 273 imask |= ATH9K_INT_SWBA;
274 274
275 ath_dbg(common, CONFIG, 275 ath_dbg(common, CONFIG,
@@ -365,7 +365,7 @@ static void ath9k_htc_send_beacon(struct ath9k_htc_priv *priv,
365 vif = priv->cur_beacon_conf.bslot[slot]; 365 vif = priv->cur_beacon_conf.bslot[slot];
366 avp = (struct ath9k_htc_vif *)vif->drv_priv; 366 avp = (struct ath9k_htc_vif *)vif->drv_priv;
367 367
368 if (unlikely(priv->op_flags & OP_SCANNING)) { 368 if (unlikely(test_bit(OP_SCANNING, &priv->op_flags))) {
369 spin_unlock_bh(&priv->beacon_lock); 369 spin_unlock_bh(&priv->beacon_lock);
370 return; 370 return;
371 } 371 }
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
index 1c10e2e5c237..07df279c8d46 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
@@ -37,17 +37,18 @@ static void ath_detect_bt_priority(struct ath9k_htc_priv *priv)
37 37
38 if (time_after(jiffies, btcoex->bt_priority_time + 38 if (time_after(jiffies, btcoex->bt_priority_time +
39 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) { 39 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
40 priv->op_flags &= ~(OP_BT_PRIORITY_DETECTED | OP_BT_SCAN); 40 clear_bit(OP_BT_PRIORITY_DETECTED, &priv->op_flags);
41 clear_bit(OP_BT_SCAN, &priv->op_flags);
41 /* Detect if colocated bt started scanning */ 42 /* Detect if colocated bt started scanning */
42 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) { 43 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) {
43 ath_dbg(ath9k_hw_common(ah), BTCOEX, 44 ath_dbg(ath9k_hw_common(ah), BTCOEX,
44 "BT scan detected\n"); 45 "BT scan detected\n");
45 priv->op_flags |= (OP_BT_SCAN | 46 set_bit(OP_BT_PRIORITY_DETECTED, &priv->op_flags);
46 OP_BT_PRIORITY_DETECTED); 47 set_bit(OP_BT_SCAN, &priv->op_flags);
47 } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { 48 } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
48 ath_dbg(ath9k_hw_common(ah), BTCOEX, 49 ath_dbg(ath9k_hw_common(ah), BTCOEX,
49 "BT priority traffic detected\n"); 50 "BT priority traffic detected\n");
50 priv->op_flags |= OP_BT_PRIORITY_DETECTED; 51 set_bit(OP_BT_PRIORITY_DETECTED, &priv->op_flags);
51 } 52 }
52 53
53 btcoex->bt_priority_cnt = 0; 54 btcoex->bt_priority_cnt = 0;
@@ -67,26 +68,23 @@ static void ath_btcoex_period_work(struct work_struct *work)
67 struct ath_btcoex *btcoex = &priv->btcoex; 68 struct ath_btcoex *btcoex = &priv->btcoex;
68 struct ath_common *common = ath9k_hw_common(priv->ah); 69 struct ath_common *common = ath9k_hw_common(priv->ah);
69 u32 timer_period; 70 u32 timer_period;
70 bool is_btscan;
71 int ret; 71 int ret;
72 72
73 ath_detect_bt_priority(priv); 73 ath_detect_bt_priority(priv);
74 74
75 is_btscan = !!(priv->op_flags & OP_BT_SCAN);
76
77 ret = ath9k_htc_update_cap_target(priv, 75 ret = ath9k_htc_update_cap_target(priv,
78 !!(priv->op_flags & OP_BT_PRIORITY_DETECTED)); 76 test_bit(OP_BT_PRIORITY_DETECTED, &priv->op_flags));
79 if (ret) { 77 if (ret) {
80 ath_err(common, "Unable to set BTCOEX parameters\n"); 78 ath_err(common, "Unable to set BTCOEX parameters\n");
81 return; 79 return;
82 } 80 }
83 81
84 ath9k_hw_btcoex_bt_stomp(priv->ah, is_btscan ? ATH_BTCOEX_STOMP_ALL : 82 ath9k_hw_btcoex_bt_stomp(priv->ah, test_bit(OP_BT_SCAN, &priv->op_flags) ?
85 btcoex->bt_stomp_type); 83 ATH_BTCOEX_STOMP_ALL : btcoex->bt_stomp_type);
86 84
87 ath9k_hw_btcoex_enable(priv->ah); 85 ath9k_hw_btcoex_enable(priv->ah);
88 timer_period = is_btscan ? btcoex->btscan_no_stomp : 86 timer_period = test_bit(OP_BT_SCAN, &priv->op_flags) ?
89 btcoex->btcoex_no_stomp; 87 btcoex->btscan_no_stomp : btcoex->btcoex_no_stomp;
90 ieee80211_queue_delayed_work(priv->hw, &priv->duty_cycle_work, 88 ieee80211_queue_delayed_work(priv->hw, &priv->duty_cycle_work,
91 msecs_to_jiffies(timer_period)); 89 msecs_to_jiffies(timer_period));
92 ieee80211_queue_delayed_work(priv->hw, &priv->coex_period_work, 90 ieee80211_queue_delayed_work(priv->hw, &priv->coex_period_work,
@@ -104,14 +102,15 @@ static void ath_btcoex_duty_cycle_work(struct work_struct *work)
104 struct ath_hw *ah = priv->ah; 102 struct ath_hw *ah = priv->ah;
105 struct ath_btcoex *btcoex = &priv->btcoex; 103 struct ath_btcoex *btcoex = &priv->btcoex;
106 struct ath_common *common = ath9k_hw_common(ah); 104 struct ath_common *common = ath9k_hw_common(ah);
107 bool is_btscan = priv->op_flags & OP_BT_SCAN;
108 105
109 ath_dbg(common, BTCOEX, "time slice work for bt and wlan\n"); 106 ath_dbg(common, BTCOEX, "time slice work for bt and wlan\n");
110 107
111 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW || is_btscan) 108 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW ||
109 test_bit(OP_BT_SCAN, &priv->op_flags))
112 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE); 110 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE);
113 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL) 111 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
114 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_LOW); 112 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_LOW);
113
115 ath9k_hw_btcoex_enable(priv->ah); 114 ath9k_hw_btcoex_enable(priv->ah);
116} 115}
117 116
@@ -141,7 +140,8 @@ static void ath_htc_resume_btcoex_work(struct ath9k_htc_priv *priv)
141 140
142 btcoex->bt_priority_cnt = 0; 141 btcoex->bt_priority_cnt = 0;
143 btcoex->bt_priority_time = jiffies; 142 btcoex->bt_priority_time = jiffies;
144 priv->op_flags &= ~(OP_BT_PRIORITY_DETECTED | OP_BT_SCAN); 143 clear_bit(OP_BT_PRIORITY_DETECTED, &priv->op_flags);
144 clear_bit(OP_BT_SCAN, &priv->op_flags);
145 ieee80211_queue_delayed_work(priv->hw, &priv->coex_period_work, 0); 145 ieee80211_queue_delayed_work(priv->hw, &priv->coex_period_work, 0);
146} 146}
147 147
@@ -310,95 +310,3 @@ void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv)
310 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 310 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
311 wiphy_rfkill_start_polling(priv->hw->wiphy); 311 wiphy_rfkill_start_polling(priv->hw->wiphy);
312} 312}
313
314void ath9k_htc_radio_enable(struct ieee80211_hw *hw)
315{
316 struct ath9k_htc_priv *priv = hw->priv;
317 struct ath_hw *ah = priv->ah;
318 struct ath_common *common = ath9k_hw_common(ah);
319 int ret;
320 u8 cmd_rsp;
321
322 if (!ah->curchan)
323 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
324
325 /* Reset the HW */
326 ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
327 if (ret) {
328 ath_err(common,
329 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
330 ret, ah->curchan->channel);
331 }
332
333 ath9k_cmn_update_txpow(ah, priv->curtxpow, priv->txpowlimit,
334 &priv->curtxpow);
335
336 /* Start RX */
337 WMI_CMD(WMI_START_RECV_CMDID);
338 ath9k_host_rx_init(priv);
339
340 /* Start TX */
341 htc_start(priv->htc);
342 spin_lock_bh(&priv->tx.tx_lock);
343 priv->tx.flags &= ~ATH9K_HTC_OP_TX_QUEUES_STOP;
344 spin_unlock_bh(&priv->tx.tx_lock);
345 ieee80211_wake_queues(hw);
346
347 WMI_CMD(WMI_ENABLE_INTR_CMDID);
348
349 /* Enable LED */
350 ath9k_hw_cfg_output(ah, ah->led_pin,
351 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
352 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
353}
354
355void ath9k_htc_radio_disable(struct ieee80211_hw *hw)
356{
357 struct ath9k_htc_priv *priv = hw->priv;
358 struct ath_hw *ah = priv->ah;
359 struct ath_common *common = ath9k_hw_common(ah);
360 int ret;
361 u8 cmd_rsp;
362
363 ath9k_htc_ps_wakeup(priv);
364
365 /* Disable LED */
366 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
367 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
368
369 WMI_CMD(WMI_DISABLE_INTR_CMDID);
370
371 /* Stop TX */
372 ieee80211_stop_queues(hw);
373 ath9k_htc_tx_drain(priv);
374 WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
375
376 /* Stop RX */
377 WMI_CMD(WMI_STOP_RECV_CMDID);
378
379 /* Clear the WMI event queue */
380 ath9k_wmi_event_drain(priv);
381
382 /*
383 * The MIB counters have to be disabled here,
384 * since the target doesn't do it.
385 */
386 ath9k_hw_disable_mib_counters(ah);
387
388 if (!ah->curchan)
389 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
390
391 /* Reset the HW */
392 ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
393 if (ret) {
394 ath_err(common,
395 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
396 ret, ah->curchan->channel);
397 }
398
399 /* Disable the PHY */
400 ath9k_hw_phy_disable(ah);
401
402 ath9k_htc_ps_restore(priv);
403 ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP);
404}
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
index 25213d521bc2..a035a380d669 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
@@ -611,7 +611,7 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv,
611 struct ath_common *common; 611 struct ath_common *common;
612 int i, ret = 0, csz = 0; 612 int i, ret = 0, csz = 0;
613 613
614 priv->op_flags |= OP_INVALID; 614 set_bit(OP_INVALID, &priv->op_flags);
615 615
616 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); 616 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
617 if (!ah) 617 if (!ah)
@@ -718,7 +718,7 @@ static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
718 718
719 hw->queues = 4; 719 hw->queues = 4;
720 hw->channel_change_time = 5000; 720 hw->channel_change_time = 5000;
721 hw->max_listen_interval = 10; 721 hw->max_listen_interval = 1;
722 722
723 hw->vif_data_size = sizeof(struct ath9k_htc_vif); 723 hw->vif_data_size = sizeof(struct ath9k_htc_vif);
724 hw->sta_data_size = sizeof(struct ath9k_htc_sta); 724 hw->sta_data_size = sizeof(struct ath9k_htc_sta);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
index abbd6effd60d..374c32ed905a 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
@@ -75,14 +75,19 @@ unlock:
75 75
76void ath9k_htc_ps_restore(struct ath9k_htc_priv *priv) 76void ath9k_htc_ps_restore(struct ath9k_htc_priv *priv)
77{ 77{
78 bool reset;
79
78 mutex_lock(&priv->htc_pm_lock); 80 mutex_lock(&priv->htc_pm_lock);
79 if (--priv->ps_usecount != 0) 81 if (--priv->ps_usecount != 0)
80 goto unlock; 82 goto unlock;
81 83
82 if (priv->ps_idle) 84 if (priv->ps_idle) {
85 ath9k_hw_setrxabort(priv->ah, true);
86 ath9k_hw_stopdmarecv(priv->ah, &reset);
83 ath9k_hw_setpower(priv->ah, ATH9K_PM_FULL_SLEEP); 87 ath9k_hw_setpower(priv->ah, ATH9K_PM_FULL_SLEEP);
84 else if (priv->ps_enabled) 88 } else if (priv->ps_enabled) {
85 ath9k_hw_setpower(priv->ah, ATH9K_PM_NETWORK_SLEEP); 89 ath9k_hw_setpower(priv->ah, ATH9K_PM_NETWORK_SLEEP);
90 }
86 91
87unlock: 92unlock:
88 mutex_unlock(&priv->htc_pm_lock); 93 mutex_unlock(&priv->htc_pm_lock);
@@ -250,7 +255,7 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
250 u8 cmd_rsp; 255 u8 cmd_rsp;
251 int ret; 256 int ret;
252 257
253 if (priv->op_flags & OP_INVALID) 258 if (test_bit(OP_INVALID, &priv->op_flags))
254 return -EIO; 259 return -EIO;
255 260
256 fastcc = !!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL); 261 fastcc = !!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL);
@@ -304,7 +309,7 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
304 309
305 htc_start(priv->htc); 310 htc_start(priv->htc);
306 311
307 if (!(priv->op_flags & OP_SCANNING) && 312 if (!test_bit(OP_SCANNING, &priv->op_flags) &&
308 !(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 313 !(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
309 ath9k_htc_vif_reconfig(priv); 314 ath9k_htc_vif_reconfig(priv);
310 315
@@ -750,7 +755,7 @@ void ath9k_htc_start_ani(struct ath9k_htc_priv *priv)
750 common->ani.shortcal_timer = timestamp; 755 common->ani.shortcal_timer = timestamp;
751 common->ani.checkani_timer = timestamp; 756 common->ani.checkani_timer = timestamp;
752 757
753 priv->op_flags |= OP_ANI_RUNNING; 758 set_bit(OP_ANI_RUNNING, &priv->op_flags);
754 759
755 ieee80211_queue_delayed_work(common->hw, &priv->ani_work, 760 ieee80211_queue_delayed_work(common->hw, &priv->ani_work,
756 msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); 761 msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
@@ -759,7 +764,7 @@ void ath9k_htc_start_ani(struct ath9k_htc_priv *priv)
759void ath9k_htc_stop_ani(struct ath9k_htc_priv *priv) 764void ath9k_htc_stop_ani(struct ath9k_htc_priv *priv)
760{ 765{
761 cancel_delayed_work_sync(&priv->ani_work); 766 cancel_delayed_work_sync(&priv->ani_work);
762 priv->op_flags &= ~OP_ANI_RUNNING; 767 clear_bit(OP_ANI_RUNNING, &priv->op_flags);
763} 768}
764 769
765void ath9k_htc_ani_work(struct work_struct *work) 770void ath9k_htc_ani_work(struct work_struct *work)
@@ -944,7 +949,7 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
944 ath_dbg(common, CONFIG, 949 ath_dbg(common, CONFIG,
945 "Failed to update capability in target\n"); 950 "Failed to update capability in target\n");
946 951
947 priv->op_flags &= ~OP_INVALID; 952 clear_bit(OP_INVALID, &priv->op_flags);
948 htc_start(priv->htc); 953 htc_start(priv->htc);
949 954
950 spin_lock_bh(&priv->tx.tx_lock); 955 spin_lock_bh(&priv->tx.tx_lock);
@@ -973,7 +978,7 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw)
973 978
974 mutex_lock(&priv->mutex); 979 mutex_lock(&priv->mutex);
975 980
976 if (priv->op_flags & OP_INVALID) { 981 if (test_bit(OP_INVALID, &priv->op_flags)) {
977 ath_dbg(common, ANY, "Device not present\n"); 982 ath_dbg(common, ANY, "Device not present\n");
978 mutex_unlock(&priv->mutex); 983 mutex_unlock(&priv->mutex);
979 return; 984 return;
@@ -1015,7 +1020,7 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw)
1015 ath9k_htc_ps_restore(priv); 1020 ath9k_htc_ps_restore(priv);
1016 ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP); 1021 ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP);
1017 1022
1018 priv->op_flags |= OP_INVALID; 1023 set_bit(OP_INVALID, &priv->op_flags);
1019 1024
1020 ath_dbg(common, CONFIG, "Driver halt\n"); 1025 ath_dbg(common, CONFIG, "Driver halt\n");
1021 mutex_unlock(&priv->mutex); 1026 mutex_unlock(&priv->mutex);
@@ -1105,7 +1110,7 @@ static int ath9k_htc_add_interface(struct ieee80211_hw *hw,
1105 ath9k_htc_set_opmode(priv); 1110 ath9k_htc_set_opmode(priv);
1106 1111
1107 if ((priv->ah->opmode == NL80211_IFTYPE_AP) && 1112 if ((priv->ah->opmode == NL80211_IFTYPE_AP) &&
1108 !(priv->op_flags & OP_ANI_RUNNING)) { 1113 !test_bit(OP_ANI_RUNNING, &priv->op_flags)) {
1109 ath9k_hw_set_tsfadjust(priv->ah, 1); 1114 ath9k_hw_set_tsfadjust(priv->ah, 1);
1110 ath9k_htc_start_ani(priv); 1115 ath9k_htc_start_ani(priv);
1111 } 1116 }
@@ -1178,24 +1183,20 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
1178 struct ath9k_htc_priv *priv = hw->priv; 1183 struct ath9k_htc_priv *priv = hw->priv;
1179 struct ath_common *common = ath9k_hw_common(priv->ah); 1184 struct ath_common *common = ath9k_hw_common(priv->ah);
1180 struct ieee80211_conf *conf = &hw->conf; 1185 struct ieee80211_conf *conf = &hw->conf;
1186 bool chip_reset = false;
1187 int ret = 0;
1181 1188
1182 mutex_lock(&priv->mutex); 1189 mutex_lock(&priv->mutex);
1190 ath9k_htc_ps_wakeup(priv);
1183 1191
1184 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1192 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1185 bool enable_radio = false;
1186 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1187
1188 mutex_lock(&priv->htc_pm_lock); 1193 mutex_lock(&priv->htc_pm_lock);
1189 if (!idle && priv->ps_idle)
1190 enable_radio = true;
1191 priv->ps_idle = idle;
1192 mutex_unlock(&priv->htc_pm_lock);
1193 1194
1194 if (enable_radio) { 1195 priv->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1195 ath_dbg(common, CONFIG, "not-idle: enabling radio\n"); 1196 if (priv->ps_idle)
1196 ath9k_htc_setpower(priv, ATH9K_PM_AWAKE); 1197 chip_reset = true;
1197 ath9k_htc_radio_enable(hw); 1198
1198 } 1199 mutex_unlock(&priv->htc_pm_lock);
1199 } 1200 }
1200 1201
1201 /* 1202 /*
@@ -1210,7 +1211,7 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
1210 ath9k_htc_remove_monitor_interface(priv); 1211 ath9k_htc_remove_monitor_interface(priv);
1211 } 1212 }
1212 1213
1213 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 1214 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || chip_reset) {
1214 struct ieee80211_channel *curchan = hw->conf.channel; 1215 struct ieee80211_channel *curchan = hw->conf.channel;
1215 int pos = curchan->hw_value; 1216 int pos = curchan->hw_value;
1216 1217
@@ -1223,8 +1224,8 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
1223 1224
1224 if (ath9k_htc_set_channel(priv, hw, &priv->ah->channels[pos]) < 0) { 1225 if (ath9k_htc_set_channel(priv, hw, &priv->ah->channels[pos]) < 0) {
1225 ath_err(common, "Unable to set channel\n"); 1226 ath_err(common, "Unable to set channel\n");
1226 mutex_unlock(&priv->mutex); 1227 ret = -EINVAL;
1227 return -EINVAL; 1228 goto out;
1228 } 1229 }
1229 1230
1230 } 1231 }
@@ -1246,21 +1247,10 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
1246 priv->txpowlimit, &priv->curtxpow); 1247 priv->txpowlimit, &priv->curtxpow);
1247 } 1248 }
1248 1249
1249 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1250 mutex_lock(&priv->htc_pm_lock);
1251 if (!priv->ps_idle) {
1252 mutex_unlock(&priv->htc_pm_lock);
1253 goto out;
1254 }
1255 mutex_unlock(&priv->htc_pm_lock);
1256
1257 ath_dbg(common, CONFIG, "idle: disabling radio\n");
1258 ath9k_htc_radio_disable(hw);
1259 }
1260
1261out: 1250out:
1251 ath9k_htc_ps_restore(priv);
1262 mutex_unlock(&priv->mutex); 1252 mutex_unlock(&priv->mutex);
1263 return 0; 1253 return ret;
1264} 1254}
1265 1255
1266#define SUPPORTED_FILTERS \ 1256#define SUPPORTED_FILTERS \
@@ -1285,7 +1275,7 @@ static void ath9k_htc_configure_filter(struct ieee80211_hw *hw,
1285 changed_flags &= SUPPORTED_FILTERS; 1275 changed_flags &= SUPPORTED_FILTERS;
1286 *total_flags &= SUPPORTED_FILTERS; 1276 *total_flags &= SUPPORTED_FILTERS;
1287 1277
1288 if (priv->op_flags & OP_INVALID) { 1278 if (test_bit(OP_INVALID, &priv->op_flags)) {
1289 ath_dbg(ath9k_hw_common(priv->ah), ANY, 1279 ath_dbg(ath9k_hw_common(priv->ah), ANY,
1290 "Unable to configure filter on invalid state\n"); 1280 "Unable to configure filter on invalid state\n");
1291 mutex_unlock(&priv->mutex); 1281 mutex_unlock(&priv->mutex);
@@ -1516,7 +1506,7 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
1516 ath_dbg(common, CONFIG, "Beacon enabled for BSS: %pM\n", 1506 ath_dbg(common, CONFIG, "Beacon enabled for BSS: %pM\n",
1517 bss_conf->bssid); 1507 bss_conf->bssid);
1518 ath9k_htc_set_tsfadjust(priv, vif); 1508 ath9k_htc_set_tsfadjust(priv, vif);
1519 priv->op_flags |= OP_ENABLE_BEACON; 1509 set_bit(OP_ENABLE_BEACON, &priv->op_flags);
1520 ath9k_htc_beacon_config(priv, vif); 1510 ath9k_htc_beacon_config(priv, vif);
1521 } 1511 }
1522 1512
@@ -1529,7 +1519,7 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
1529 ath_dbg(common, CONFIG, 1519 ath_dbg(common, CONFIG,
1530 "Beacon disabled for BSS: %pM\n", 1520 "Beacon disabled for BSS: %pM\n",
1531 bss_conf->bssid); 1521 bss_conf->bssid);
1532 priv->op_flags &= ~OP_ENABLE_BEACON; 1522 clear_bit(OP_ENABLE_BEACON, &priv->op_flags);
1533 ath9k_htc_beacon_config(priv, vif); 1523 ath9k_htc_beacon_config(priv, vif);
1534 } 1524 }
1535 } 1525 }
@@ -1542,7 +1532,7 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
1542 (priv->nvifs == 1) && 1532 (priv->nvifs == 1) &&
1543 (priv->num_ap_vif == 1) && 1533 (priv->num_ap_vif == 1) &&
1544 (vif->type == NL80211_IFTYPE_AP)) { 1534 (vif->type == NL80211_IFTYPE_AP)) {
1545 priv->op_flags |= OP_TSF_RESET; 1535 set_bit(OP_TSF_RESET, &priv->op_flags);
1546 } 1536 }
1547 ath_dbg(common, CONFIG, 1537 ath_dbg(common, CONFIG,
1548 "Beacon interval changed for BSS: %pM\n", 1538 "Beacon interval changed for BSS: %pM\n",
@@ -1654,7 +1644,7 @@ static void ath9k_htc_sw_scan_start(struct ieee80211_hw *hw)
1654 1644
1655 mutex_lock(&priv->mutex); 1645 mutex_lock(&priv->mutex);
1656 spin_lock_bh(&priv->beacon_lock); 1646 spin_lock_bh(&priv->beacon_lock);
1657 priv->op_flags |= OP_SCANNING; 1647 set_bit(OP_SCANNING, &priv->op_flags);
1658 spin_unlock_bh(&priv->beacon_lock); 1648 spin_unlock_bh(&priv->beacon_lock);
1659 cancel_work_sync(&priv->ps_work); 1649 cancel_work_sync(&priv->ps_work);
1660 ath9k_htc_stop_ani(priv); 1650 ath9k_htc_stop_ani(priv);
@@ -1667,7 +1657,7 @@ static void ath9k_htc_sw_scan_complete(struct ieee80211_hw *hw)
1667 1657
1668 mutex_lock(&priv->mutex); 1658 mutex_lock(&priv->mutex);
1669 spin_lock_bh(&priv->beacon_lock); 1659 spin_lock_bh(&priv->beacon_lock);
1670 priv->op_flags &= ~OP_SCANNING; 1660 clear_bit(OP_SCANNING, &priv->op_flags);
1671 spin_unlock_bh(&priv->beacon_lock); 1661 spin_unlock_bh(&priv->beacon_lock);
1672 ath9k_htc_ps_wakeup(priv); 1662 ath9k_htc_ps_wakeup(priv);
1673 ath9k_htc_vif_reconfig(priv); 1663 ath9k_htc_vif_reconfig(priv);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
index 3e40a6461512..47e61d0da33b 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
@@ -916,7 +916,7 @@ void ath9k_host_rx_init(struct ath9k_htc_priv *priv)
916{ 916{
917 ath9k_hw_rxena(priv->ah); 917 ath9k_hw_rxena(priv->ah);
918 ath9k_htc_opmode_init(priv); 918 ath9k_htc_opmode_init(priv);
919 ath9k_hw_startpcureceive(priv->ah, (priv->op_flags & OP_SCANNING)); 919 ath9k_hw_startpcureceive(priv->ah, test_bit(OP_SCANNING, &priv->op_flags));
920 priv->rx.last_rssi = ATH_RSSI_DUMMY_MARKER; 920 priv->rx.last_rssi = ATH_RSSI_DUMMY_MARKER;
921} 921}
922 922
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 03d590924c64..94096607cbdd 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -1019,16 +1019,8 @@ void ar9002_hw_attach_ops(struct ath_hw *ah);
1019void ar9003_hw_attach_ops(struct ath_hw *ah); 1019void ar9003_hw_attach_ops(struct ath_hw *ah);
1020 1020
1021void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); 1021void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1022/* 1022
1023 * ANI work can be shared between all families but a next
1024 * generation implementation of ANI will be used only for AR9003 only
1025 * for now as the other families still need to be tested with the same
1026 * next generation ANI. Feel free to start testing it though for the
1027 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
1028 */
1029extern int modparam_force_new_ani;
1030void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); 1023void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1031void ath9k_hw_proc_mib_event(struct ath_hw *ah);
1032void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); 1024void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1033 1025
1034#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 1026#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
@@ -1038,7 +1030,8 @@ static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1038} 1030}
1039static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) 1031static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1040{ 1032{
1041 return ah->btcoex_hw.enabled && (ah->caps.hw_caps & ATH9K_HW_CAP_MCI); 1033 return ah->common.btcoex_enabled &&
1034 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1042 1035
1043} 1036}
1044void ath9k_hw_btcoex_enable(struct ath_hw *ah); 1037void ath9k_hw_btcoex_enable(struct ath_hw *ah);
diff --git a/drivers/net/wireless/ath/ath9k/link.c b/drivers/net/wireless/ath/ath9k/link.c
index a105c9426251..91650fe50461 100644
--- a/drivers/net/wireless/ath/ath9k/link.c
+++ b/drivers/net/wireless/ath/ath9k/link.c
@@ -407,6 +407,7 @@ void ath_ani_calibrate(unsigned long data)
407 longcal ? "long" : "", shortcal ? "short" : "", 407 longcal ? "long" : "", shortcal ? "short" : "",
408 aniflag ? "ani" : "", common->ani.caldone ? "true" : "false"); 408 aniflag ? "ani" : "", common->ani.caldone ? "true" : "false");
409 409
410 ath9k_debug_samp_bb_mac(sc);
410 ath9k_ps_restore(sc); 411 ath9k_ps_restore(sc);
411 412
412set_timer: 413set_timer:
@@ -415,7 +416,6 @@ set_timer:
415 * The interval must be the shortest necessary to satisfy ANI, 416 * The interval must be the shortest necessary to satisfy ANI,
416 * short calibration and long calibration. 417 * short calibration and long calibration.
417 */ 418 */
418 ath9k_debug_samp_bb_mac(sc);
419 cal_interval = ATH_LONG_CALINTERVAL; 419 cal_interval = ATH_LONG_CALINTERVAL;
420 if (sc->sc_ah->config.enable_ani) 420 if (sc->sc_ah->config.enable_ani)
421 cal_interval = min(cal_interval, 421 cal_interval = min(cal_interval,
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 52561b341d68..e4e73f061a22 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -19,7 +19,7 @@
19#include "ath9k.h" 19#include "ath9k.h"
20#include "btcoex.h" 20#include "btcoex.h"
21 21
22static u8 parse_mpdudensity(u8 mpdudensity) 22u8 ath9k_parse_mpdudensity(u8 mpdudensity)
23{ 23{
24 /* 24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
@@ -150,8 +150,10 @@ static void __ath_cancel_work(struct ath_softc *sc)
150 cancel_work_sync(&sc->hw_check_work); 150 cancel_work_sync(&sc->hw_check_work);
151 cancel_delayed_work_sync(&sc->tx_complete_work); 151 cancel_delayed_work_sync(&sc->tx_complete_work);
152 cancel_delayed_work_sync(&sc->hw_pll_work); 152 cancel_delayed_work_sync(&sc->hw_pll_work);
153
153#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 154#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
154 cancel_work_sync(&sc->mci_work); 155 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
156 cancel_work_sync(&sc->mci_work);
155#endif 157#endif
156} 158}
157 159
@@ -320,6 +322,7 @@ static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
320 struct ieee80211_vif *vif) 322 struct ieee80211_vif *vif)
321{ 323{
322 struct ath_node *an; 324 struct ath_node *an;
325 u8 density;
323 an = (struct ath_node *)sta->drv_priv; 326 an = (struct ath_node *)sta->drv_priv;
324 327
325#ifdef CONFIG_ATH9K_DEBUGFS 328#ifdef CONFIG_ATH9K_DEBUGFS
@@ -334,7 +337,8 @@ static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
334 ath_tx_node_init(sc, an); 337 ath_tx_node_init(sc, an);
335 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 338 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
336 sta->ht_cap.ampdu_factor); 339 sta->ht_cap.ampdu_factor);
337 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); 340 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
341 an->mpdudensity = density;
338 } 342 }
339} 343}
340 344
@@ -516,24 +520,6 @@ irqreturn_t ath_isr(int irq, void *dev)
516 ath9k_hw_set_interrupts(ah); 520 ath9k_hw_set_interrupts(ah);
517 } 521 }
518 522
519 if (status & ATH9K_INT_MIB) {
520 /*
521 * Disable interrupts until we service the MIB
522 * interrupt; otherwise it will continue to
523 * fire.
524 */
525 ath9k_hw_disable_interrupts(ah);
526 /*
527 * Let the hal handle the event. We assume
528 * it will clear whatever condition caused
529 * the interrupt.
530 */
531 spin_lock(&common->cc_lock);
532 ath9k_hw_proc_mib_event(ah);
533 spin_unlock(&common->cc_lock);
534 ath9k_hw_enable_interrupts(ah);
535 }
536
537 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 523 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
538 if (status & ATH9K_INT_TIM_TIMER) { 524 if (status & ATH9K_INT_TIM_TIMER) {
539 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 525 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
@@ -959,14 +945,10 @@ static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
959 /* 945 /*
960 * Enable MIB interrupts when there are hardware phy counters. 946 * Enable MIB interrupts when there are hardware phy counters.
961 */ 947 */
962 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) { 948 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
963 if (ah->config.enable_ani)
964 ah->imask |= ATH9K_INT_MIB;
965 ah->imask |= ATH9K_INT_TSFOOR; 949 ah->imask |= ATH9K_INT_TSFOOR;
966 } else { 950 else
967 ah->imask &= ~ATH9K_INT_MIB;
968 ah->imask &= ~ATH9K_INT_TSFOOR; 951 ah->imask &= ~ATH9K_INT_TSFOOR;
969 }
970 952
971 ath9k_hw_set_interrupts(ah); 953 ath9k_hw_set_interrupts(ah);
972 954
diff --git a/drivers/net/wireless/ath/ath9k/mci.c b/drivers/net/wireless/ath/ath9k/mci.c
index 7d34a504d617..64cc782587d8 100644
--- a/drivers/net/wireless/ath/ath9k/mci.c
+++ b/drivers/net/wireless/ath/ath9k/mci.c
@@ -233,8 +233,21 @@ static void ath_mci_process_profile(struct ath_softc *sc,
233 struct ath_mci_profile_info *entry = NULL; 233 struct ath_mci_profile_info *entry = NULL;
234 234
235 entry = ath_mci_find_profile(mci, info); 235 entry = ath_mci_find_profile(mci, info);
236 if (entry) 236 if (entry) {
237 /*
238 * Two MCI interrupts are generated while connecting to
239 * headset and A2DP profile, but only one MCI interrupt
240 * is generated with last added profile type while disconnecting
241 * both profiles.
242 * So while adding second profile type decrement
243 * the first one.
244 */
245 if (entry->type != info->type) {
246 DEC_PROF(mci, entry);
247 INC_PROF(mci, info);
248 }
237 memcpy(entry, info, 10); 249 memcpy(entry, info, 10);
250 }
238 251
239 if (info->start) { 252 if (info->start) {
240 if (!entry && !ath_mci_add_profile(common, mci, info)) 253 if (!entry && !ath_mci_add_profile(common, mci, info))
@@ -335,7 +348,7 @@ static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
335 348
336 seq_num = *((u32 *)(rx_payload + 12)); 349 seq_num = *((u32 *)(rx_payload + 12));
337 ath_dbg(common, MCI, 350 ath_dbg(common, MCI,
338 "BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%d\n", 351 "BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%u\n",
339 profile_status.is_link, profile_status.conn_handle, 352 profile_status.is_link, profile_status.conn_handle,
340 profile_status.is_critical, seq_num); 353 profile_status.is_critical, seq_num);
341 354
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 75acefbd4937..5046b282a93c 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -2162,10 +2162,6 @@ enum {
2162#define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000 2162#define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000
2163#define AR_BTCOEX_CTRL_SPDT_POLARITY_S 31 2163#define AR_BTCOEX_CTRL_SPDT_POLARITY_S 31
2164 2164
2165#define AR_BTCOEX_WL_WEIGHTS0 0x18b0
2166#define AR_BTCOEX_WL_WEIGHTS1 0x18b4
2167#define AR_BTCOEX_WL_WEIGHTS2 0x18b8
2168#define AR_BTCOEX_WL_WEIGHTS3 0x18bc
2169#define AR_BTCOEX_MAX_TXPWR(_x) (0x18c0 + ((_x) << 2)) 2165#define AR_BTCOEX_MAX_TXPWR(_x) (0x18c0 + ((_x) << 2))
2170#define AR_BTCOEX_WL_LNA 0x1940 2166#define AR_BTCOEX_WL_LNA 0x1940
2171#define AR_BTCOEX_RFGAIN_CTRL 0x1944 2167#define AR_BTCOEX_RFGAIN_CTRL 0x1944
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 8d8306039edb..cafb4a09729a 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -1165,6 +1165,7 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1165{ 1165{
1166 struct ath_atx_tid *txtid; 1166 struct ath_atx_tid *txtid;
1167 struct ath_node *an; 1167 struct ath_node *an;
1168 u8 density;
1168 1169
1169 an = (struct ath_node *)sta->drv_priv; 1170 an = (struct ath_node *)sta->drv_priv;
1170 txtid = ATH_AN_2_TID(an, tid); 1171 txtid = ATH_AN_2_TID(an, tid);
@@ -1172,6 +1173,17 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1172 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE)) 1173 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
1173 return -EAGAIN; 1174 return -EAGAIN;
1174 1175
1176 /* update ampdu factor/density, they may have changed. This may happen
1177 * in HT IBSS when a beacon with HT-info is received after the station
1178 * has already been added.
1179 */
1180 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1181 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1182 sta->ht_cap.ampdu_factor);
1183 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1184 an->mpdudensity = density;
1185 }
1186
1175 txtid->state |= AGGR_ADDBA_PROGRESS; 1187 txtid->state |= AGGR_ADDBA_PROGRESS;
1176 txtid->paused = true; 1188 txtid->paused = true;
1177 *ssn = txtid->seq_start = txtid->seq_next; 1189 *ssn = txtid->seq_start = txtid->seq_next;
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c b/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c
index 82f51dbd0d66..49765d34b4e0 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c
@@ -44,6 +44,7 @@
44 44
45#define SDIO_DEVICE_ID_BROADCOM_4329 0x4329 45#define SDIO_DEVICE_ID_BROADCOM_4329 0x4329
46#define SDIO_DEVICE_ID_BROADCOM_4330 0x4330 46#define SDIO_DEVICE_ID_BROADCOM_4330 0x4330
47#define SDIO_DEVICE_ID_BROADCOM_4334 0x4334
47 48
48#define SDIO_FUNC1_BLOCKSIZE 64 49#define SDIO_FUNC1_BLOCKSIZE 64
49#define SDIO_FUNC2_BLOCKSIZE 512 50#define SDIO_FUNC2_BLOCKSIZE 512
@@ -52,6 +53,7 @@
52static const struct sdio_device_id brcmf_sdmmc_ids[] = { 53static const struct sdio_device_id brcmf_sdmmc_ids[] = {
53 {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4329)}, 54 {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4329)},
54 {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4330)}, 55 {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4330)},
56 {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4334)},
55 { /* end: all zeroes */ }, 57 { /* end: all zeroes */ },
56}; 58};
57MODULE_DEVICE_TABLE(sdio, brcmf_sdmmc_ids); 59MODULE_DEVICE_TABLE(sdio, brcmf_sdmmc_ids);
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h b/drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h
index 366916494be4..537f499cc5d2 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h
@@ -36,6 +36,13 @@ struct dngl_stats {
36 unsigned long multicast; /* multicast packets received */ 36 unsigned long multicast; /* multicast packets received */
37}; 37};
38 38
39struct brcmf_bus_dcmd {
40 char *name;
41 char *param;
42 int param_len;
43 struct list_head list;
44};
45
39/* interface structure between common and bus layer */ 46/* interface structure between common and bus layer */
40struct brcmf_bus { 47struct brcmf_bus {
41 u8 type; /* bus type */ 48 u8 type; /* bus type */
@@ -50,6 +57,7 @@ struct brcmf_bus {
50 unsigned long tx_realloc; /* Tx packets realloced for headroom */ 57 unsigned long tx_realloc; /* Tx packets realloced for headroom */
51 struct dngl_stats dstats; /* Stats for dongle-based data */ 58 struct dngl_stats dstats; /* Stats for dongle-based data */
52 u8 align; /* bus alignment requirement */ 59 u8 align; /* bus alignment requirement */
60 struct list_head dcmd_list;
53 61
54 /* interface functions pointers */ 62 /* interface functions pointers */
55 /* Stop bus module: clear pending frames, disable data flow */ 63 /* Stop bus module: clear pending frames, disable data flow */
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
index 236cb9fa460c..2621dd3d7dcd 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
@@ -800,13 +800,13 @@ int brcmf_c_preinit_dcmds(struct brcmf_pub *drvr)
800 char iovbuf[BRCMF_EVENTING_MASK_LEN + 12]; /* Room for 800 char iovbuf[BRCMF_EVENTING_MASK_LEN + 12]; /* Room for
801 "event_msgs" + '\0' + bitvec */ 801 "event_msgs" + '\0' + bitvec */
802 char buf[128], *ptr; 802 char buf[128], *ptr;
803 u32 dongle_align = drvr->bus_if->align;
804 u32 glom = 0;
805 u32 roaming = 1; 803 u32 roaming = 1;
806 uint bcn_timeout = 3; 804 uint bcn_timeout = 3;
807 int scan_assoc_time = 40; 805 int scan_assoc_time = 40;
808 int scan_unassoc_time = 40; 806 int scan_unassoc_time = 40;
809 int i; 807 int i;
808 struct brcmf_bus_dcmd *cmdlst;
809 struct list_head *cur, *q;
810 810
811 mutex_lock(&drvr->proto_block); 811 mutex_lock(&drvr->proto_block);
812 812
@@ -827,17 +827,6 @@ int brcmf_c_preinit_dcmds(struct brcmf_pub *drvr)
827 /* Print fw version info */ 827 /* Print fw version info */
828 brcmf_dbg(ERROR, "Firmware version = %s\n", buf); 828 brcmf_dbg(ERROR, "Firmware version = %s\n", buf);
829 829
830 /* Match Host and Dongle rx alignment */
831 brcmf_c_mkiovar("bus:txglomalign", (char *)&dongle_align, 4, iovbuf,
832 sizeof(iovbuf));
833 brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_SET_VAR, iovbuf,
834 sizeof(iovbuf));
835
836 /* disable glom option per default */
837 brcmf_c_mkiovar("bus:txglom", (char *)&glom, 4, iovbuf, sizeof(iovbuf));
838 brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_SET_VAR, iovbuf,
839 sizeof(iovbuf));
840
841 /* Setup timeout if Beacons are lost and roam is off to report 830 /* Setup timeout if Beacons are lost and roam is off to report
842 link down */ 831 link down */
843 brcmf_c_mkiovar("bcn_timeout", (char *)&bcn_timeout, 4, iovbuf, 832 brcmf_c_mkiovar("bcn_timeout", (char *)&bcn_timeout, 4, iovbuf,
@@ -874,6 +863,20 @@ int brcmf_c_preinit_dcmds(struct brcmf_pub *drvr)
874 0, true); 863 0, true);
875 } 864 }
876 865
866 /* set bus specific command if there is any */
867 list_for_each_safe(cur, q, &drvr->bus_if->dcmd_list) {
868 cmdlst = list_entry(cur, struct brcmf_bus_dcmd, list);
869 if (cmdlst->name && cmdlst->param && cmdlst->param_len) {
870 brcmf_c_mkiovar(cmdlst->name, cmdlst->param,
871 cmdlst->param_len, iovbuf,
872 sizeof(iovbuf));
873 brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_SET_VAR,
874 iovbuf, sizeof(iovbuf));
875 }
876 list_del(cur);
877 kfree(cmdlst);
878 }
879
877 mutex_unlock(&drvr->proto_block); 880 mutex_unlock(&drvr->proto_block);
878 881
879 return 0; 882 return 0;
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
index 01cf6c03390b..57bf1d7ee80f 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
@@ -1020,6 +1020,8 @@ int brcmf_attach(uint bus_hdrlen, struct device *dev)
1020 INIT_WORK(&drvr->setmacaddr_work, _brcmf_set_mac_address); 1020 INIT_WORK(&drvr->setmacaddr_work, _brcmf_set_mac_address);
1021 INIT_WORK(&drvr->multicast_work, _brcmf_set_multicast_list); 1021 INIT_WORK(&drvr->multicast_work, _brcmf_set_multicast_list);
1022 1022
1023 INIT_LIST_HEAD(&drvr->bus_if->dcmd_list);
1024
1023 return ret; 1025 return ret;
1024 1026
1025fail: 1027fail:
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
index b023766954a6..472f2ef5c652 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
@@ -31,6 +31,8 @@
31#include <linux/firmware.h> 31#include <linux/firmware.h>
32#include <linux/module.h> 32#include <linux/module.h>
33#include <linux/bcma/bcma.h> 33#include <linux/bcma/bcma.h>
34#include <linux/debugfs.h>
35#include <linux/vmalloc.h>
34#include <asm/unaligned.h> 36#include <asm/unaligned.h>
35#include <defs.h> 37#include <defs.h>
36#include <brcmu_wifi.h> 38#include <brcmu_wifi.h>
@@ -48,6 +50,9 @@
48 50
49#define CBUF_LEN (128) 51#define CBUF_LEN (128)
50 52
53/* Device console log buffer state */
54#define CONSOLE_BUFFER_MAX 2024
55
51struct rte_log_le { 56struct rte_log_le {
52 __le32 buf; /* Can't be pointer on (64-bit) hosts */ 57 __le32 buf; /* Can't be pointer on (64-bit) hosts */
53 __le32 buf_size; 58 __le32 buf_size;
@@ -281,7 +286,7 @@ struct rte_console {
281 * Shared structure between dongle and the host. 286 * Shared structure between dongle and the host.
282 * The structure contains pointers to trap or assert information. 287 * The structure contains pointers to trap or assert information.
283 */ 288 */
284#define SDPCM_SHARED_VERSION 0x0002 289#define SDPCM_SHARED_VERSION 0x0003
285#define SDPCM_SHARED_VERSION_MASK 0x00FF 290#define SDPCM_SHARED_VERSION_MASK 0x00FF
286#define SDPCM_SHARED_ASSERT_BUILT 0x0100 291#define SDPCM_SHARED_ASSERT_BUILT 0x0100
287#define SDPCM_SHARED_ASSERT 0x0200 292#define SDPCM_SHARED_ASSERT 0x0200
@@ -428,6 +433,29 @@ struct brcmf_console {
428 u8 *buf; /* Log buffer (host copy) */ 433 u8 *buf; /* Log buffer (host copy) */
429 uint last; /* Last buffer read index */ 434 uint last; /* Last buffer read index */
430}; 435};
436
437struct brcmf_trap_info {
438 __le32 type;
439 __le32 epc;
440 __le32 cpsr;
441 __le32 spsr;
442 __le32 r0; /* a1 */
443 __le32 r1; /* a2 */
444 __le32 r2; /* a3 */
445 __le32 r3; /* a4 */
446 __le32 r4; /* v1 */
447 __le32 r5; /* v2 */
448 __le32 r6; /* v3 */
449 __le32 r7; /* v4 */
450 __le32 r8; /* v5 */
451 __le32 r9; /* sb/v6 */
452 __le32 r10; /* sl/v7 */
453 __le32 r11; /* fp/v8 */
454 __le32 r12; /* ip */
455 __le32 r13; /* sp */
456 __le32 r14; /* lr */
457 __le32 pc; /* r15 */
458};
431#endif /* DEBUG */ 459#endif /* DEBUG */
432 460
433struct sdpcm_shared { 461struct sdpcm_shared {
@@ -439,6 +467,7 @@ struct sdpcm_shared {
439 u32 console_addr; /* Address of struct rte_console */ 467 u32 console_addr; /* Address of struct rte_console */
440 u32 msgtrace_addr; 468 u32 msgtrace_addr;
441 u8 tag[32]; 469 u8 tag[32];
470 u32 brpt_addr;
442}; 471};
443 472
444struct sdpcm_shared_le { 473struct sdpcm_shared_le {
@@ -450,6 +479,7 @@ struct sdpcm_shared_le {
450 __le32 console_addr; /* Address of struct rte_console */ 479 __le32 console_addr; /* Address of struct rte_console */
451 __le32 msgtrace_addr; 480 __le32 msgtrace_addr;
452 u8 tag[32]; 481 u8 tag[32];
482 __le32 brpt_addr;
453}; 483};
454 484
455 485
@@ -2953,13 +2983,311 @@ brcmf_sdbrcm_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2953} 2983}
2954 2984
2955#ifdef DEBUG 2985#ifdef DEBUG
2986static inline bool brcmf_sdio_valid_shared_address(u32 addr)
2987{
2988 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
2989}
2990
2991static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
2992 struct sdpcm_shared *sh)
2993{
2994 u32 addr;
2995 int rv;
2996 u32 shaddr = 0;
2997 struct sdpcm_shared_le sh_le;
2998 __le32 addr_le;
2999
3000 shaddr = bus->ramsize - 4;
3001
3002 /*
3003 * Read last word in socram to determine
3004 * address of sdpcm_shared structure
3005 */
3006 rv = brcmf_sdbrcm_membytes(bus, false, shaddr,
3007 (u8 *)&addr_le, 4);
3008 if (rv < 0)
3009 return rv;
3010
3011 addr = le32_to_cpu(addr_le);
3012
3013 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
3014
3015 /*
3016 * Check if addr is valid.
3017 * NVRAM length at the end of memory should have been overwritten.
3018 */
3019 if (!brcmf_sdio_valid_shared_address(addr)) {
3020 brcmf_dbg(ERROR, "invalid sdpcm_shared address 0x%08X\n",
3021 addr);
3022 return -EINVAL;
3023 }
3024
3025 /* Read hndrte_shared structure */
3026 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&sh_le,
3027 sizeof(struct sdpcm_shared_le));
3028 if (rv < 0)
3029 return rv;
3030
3031 /* Endianness */
3032 sh->flags = le32_to_cpu(sh_le.flags);
3033 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
3034 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
3035 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
3036 sh->assert_line = le32_to_cpu(sh_le.assert_line);
3037 sh->console_addr = le32_to_cpu(sh_le.console_addr);
3038 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
3039
3040 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
3041 brcmf_dbg(ERROR,
3042 "sdpcm_shared version mismatch: dhd %d dongle %d\n",
3043 SDPCM_SHARED_VERSION,
3044 sh->flags & SDPCM_SHARED_VERSION_MASK);
3045 return -EPROTO;
3046 }
3047
3048 return 0;
3049}
3050
3051static int brcmf_sdio_dump_console(struct brcmf_sdio *bus,
3052 struct sdpcm_shared *sh, char __user *data,
3053 size_t count)
3054{
3055 u32 addr, console_ptr, console_size, console_index;
3056 char *conbuf = NULL;
3057 __le32 sh_val;
3058 int rv;
3059 loff_t pos = 0;
3060 int nbytes = 0;
3061
3062 /* obtain console information from device memory */
3063 addr = sh->console_addr + offsetof(struct rte_console, log_le);
3064 rv = brcmf_sdbrcm_membytes(bus, false, addr,
3065 (u8 *)&sh_val, sizeof(u32));
3066 if (rv < 0)
3067 return rv;
3068 console_ptr = le32_to_cpu(sh_val);
3069
3070 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
3071 rv = brcmf_sdbrcm_membytes(bus, false, addr,
3072 (u8 *)&sh_val, sizeof(u32));
3073 if (rv < 0)
3074 return rv;
3075 console_size = le32_to_cpu(sh_val);
3076
3077 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
3078 rv = brcmf_sdbrcm_membytes(bus, false, addr,
3079 (u8 *)&sh_val, sizeof(u32));
3080 if (rv < 0)
3081 return rv;
3082 console_index = le32_to_cpu(sh_val);
3083
3084 /* allocate buffer for console data */
3085 if (console_size <= CONSOLE_BUFFER_MAX)
3086 conbuf = vzalloc(console_size+1);
3087
3088 if (!conbuf)
3089 return -ENOMEM;
3090
3091 /* obtain the console data from device */
3092 conbuf[console_size] = '\0';
3093 rv = brcmf_sdbrcm_membytes(bus, false, console_ptr, (u8 *)conbuf,
3094 console_size);
3095 if (rv < 0)
3096 goto done;
3097
3098 rv = simple_read_from_buffer(data, count, &pos,
3099 conbuf + console_index,
3100 console_size - console_index);
3101 if (rv < 0)
3102 goto done;
3103
3104 nbytes = rv;
3105 if (console_index > 0) {
3106 pos = 0;
3107 rv = simple_read_from_buffer(data+nbytes, count, &pos,
3108 conbuf, console_index - 1);
3109 if (rv < 0)
3110 goto done;
3111 rv += nbytes;
3112 }
3113done:
3114 vfree(conbuf);
3115 return rv;
3116}
3117
3118static int brcmf_sdio_trap_info(struct brcmf_sdio *bus, struct sdpcm_shared *sh,
3119 char __user *data, size_t count)
3120{
3121 int error, res;
3122 char buf[350];
3123 struct brcmf_trap_info tr;
3124 int nbytes;
3125 loff_t pos = 0;
3126
3127 if ((sh->flags & SDPCM_SHARED_TRAP) == 0)
3128 return 0;
3129
3130 error = brcmf_sdbrcm_membytes(bus, false, sh->trap_addr, (u8 *)&tr,
3131 sizeof(struct brcmf_trap_info));
3132 if (error < 0)
3133 return error;
3134
3135 nbytes = brcmf_sdio_dump_console(bus, sh, data, count);
3136 if (nbytes < 0)
3137 return nbytes;
3138
3139 res = scnprintf(buf, sizeof(buf),
3140 "dongle trap info: type 0x%x @ epc 0x%08x\n"
3141 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
3142 " lr 0x%08x pc 0x%08x offset 0x%x\n"
3143 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
3144 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
3145 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
3146 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
3147 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
3148 le32_to_cpu(tr.pc), sh->trap_addr,
3149 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
3150 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
3151 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
3152 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
3153
3154 error = simple_read_from_buffer(data+nbytes, count, &pos, buf, res);
3155 if (error < 0)
3156 return error;
3157
3158 nbytes += error;
3159 return nbytes;
3160}
3161
3162static int brcmf_sdio_assert_info(struct brcmf_sdio *bus,
3163 struct sdpcm_shared *sh, char __user *data,
3164 size_t count)
3165{
3166 int error = 0;
3167 char buf[200];
3168 char file[80] = "?";
3169 char expr[80] = "<???>";
3170 int res;
3171 loff_t pos = 0;
3172
3173 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
3174 brcmf_dbg(INFO, "firmware not built with -assert\n");
3175 return 0;
3176 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
3177 brcmf_dbg(INFO, "no assert in dongle\n");
3178 return 0;
3179 }
3180
3181 if (sh->assert_file_addr != 0) {
3182 error = brcmf_sdbrcm_membytes(bus, false, sh->assert_file_addr,
3183 (u8 *)file, 80);
3184 if (error < 0)
3185 return error;
3186 }
3187 if (sh->assert_exp_addr != 0) {
3188 error = brcmf_sdbrcm_membytes(bus, false, sh->assert_exp_addr,
3189 (u8 *)expr, 80);
3190 if (error < 0)
3191 return error;
3192 }
3193
3194 res = scnprintf(buf, sizeof(buf),
3195 "dongle assert: %s:%d: assert(%s)\n",
3196 file, sh->assert_line, expr);
3197 return simple_read_from_buffer(data, count, &pos, buf, res);
3198}
3199
3200static int brcmf_sdbrcm_checkdied(struct brcmf_sdio *bus)
3201{
3202 int error;
3203 struct sdpcm_shared sh;
3204
3205 down(&bus->sdsem);
3206 error = brcmf_sdio_readshared(bus, &sh);
3207 up(&bus->sdsem);
3208
3209 if (error < 0)
3210 return error;
3211
3212 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3213 brcmf_dbg(INFO, "firmware not built with -assert\n");
3214 else if (sh.flags & SDPCM_SHARED_ASSERT)
3215 brcmf_dbg(ERROR, "assertion in dongle\n");
3216
3217 if (sh.flags & SDPCM_SHARED_TRAP)
3218 brcmf_dbg(ERROR, "firmware trap in dongle\n");
3219
3220 return 0;
3221}
3222
3223static int brcmf_sdbrcm_died_dump(struct brcmf_sdio *bus, char __user *data,
3224 size_t count, loff_t *ppos)
3225{
3226 int error = 0;
3227 struct sdpcm_shared sh;
3228 int nbytes = 0;
3229 loff_t pos = *ppos;
3230
3231 if (pos != 0)
3232 return 0;
3233
3234 down(&bus->sdsem);
3235 error = brcmf_sdio_readshared(bus, &sh);
3236 if (error < 0)
3237 goto done;
3238
3239 error = brcmf_sdio_assert_info(bus, &sh, data, count);
3240 if (error < 0)
3241 goto done;
3242
3243 nbytes = error;
3244 error = brcmf_sdio_trap_info(bus, &sh, data, count);
3245 if (error < 0)
3246 goto done;
3247
3248 error += nbytes;
3249 *ppos += error;
3250done:
3251 up(&bus->sdsem);
3252 return error;
3253}
3254
3255static ssize_t brcmf_sdio_forensic_read(struct file *f, char __user *data,
3256 size_t count, loff_t *ppos)
3257{
3258 struct brcmf_sdio *bus = f->private_data;
3259 int res;
3260
3261 res = brcmf_sdbrcm_died_dump(bus, data, count, ppos);
3262 if (res > 0)
3263 *ppos += res;
3264 return (ssize_t)res;
3265}
3266
3267static const struct file_operations brcmf_sdio_forensic_ops = {
3268 .owner = THIS_MODULE,
3269 .open = simple_open,
3270 .read = brcmf_sdio_forensic_read
3271};
3272
2956static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) 3273static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
2957{ 3274{
2958 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr; 3275 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
3276 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
2959 3277
3278 if (IS_ERR_OR_NULL(dentry))
3279 return;
3280
3281 debugfs_create_file("forensics", S_IRUGO, dentry, bus,
3282 &brcmf_sdio_forensic_ops);
2960 brcmf_debugfs_create_sdio_count(drvr, &bus->sdcnt); 3283 brcmf_debugfs_create_sdio_count(drvr, &bus->sdcnt);
2961} 3284}
2962#else 3285#else
3286static int brcmf_sdbrcm_checkdied(struct brcmf_sdio *bus)
3287{
3288 return 0;
3289}
3290
2963static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) 3291static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
2964{ 3292{
2965} 3293}
@@ -2991,11 +3319,13 @@ brcmf_sdbrcm_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
2991 rxlen, msglen); 3319 rxlen, msglen);
2992 } else if (timeleft == 0) { 3320 } else if (timeleft == 0) {
2993 brcmf_dbg(ERROR, "resumed on timeout\n"); 3321 brcmf_dbg(ERROR, "resumed on timeout\n");
3322 brcmf_sdbrcm_checkdied(bus);
2994 } else if (pending) { 3323 } else if (pending) {
2995 brcmf_dbg(CTL, "cancelled\n"); 3324 brcmf_dbg(CTL, "cancelled\n");
2996 return -ERESTARTSYS; 3325 return -ERESTARTSYS;
2997 } else { 3326 } else {
2998 brcmf_dbg(CTL, "resumed for unknown reason?\n"); 3327 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3328 brcmf_sdbrcm_checkdied(bus);
2999 } 3329 }
3000 3330
3001 if (rxlen) 3331 if (rxlen)
@@ -3006,45 +3336,10 @@ brcmf_sdbrcm_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3006 return rxlen ? (int)rxlen : -ETIMEDOUT; 3336 return rxlen ? (int)rxlen : -ETIMEDOUT;
3007} 3337}
3008 3338
3009static int brcmf_sdbrcm_downloadvars(struct brcmf_sdio *bus, void *arg, int len)
3010{
3011 int bcmerror = 0;
3012
3013 brcmf_dbg(TRACE, "Enter\n");
3014
3015 /* Basic sanity checks */
3016 if (bus->sdiodev->bus_if->drvr_up) {
3017 bcmerror = -EISCONN;
3018 goto err;
3019 }
3020 if (!len) {
3021 bcmerror = -EOVERFLOW;
3022 goto err;
3023 }
3024
3025 /* Free the old ones and replace with passed variables */
3026 kfree(bus->vars);
3027
3028 bus->vars = kmalloc(len, GFP_ATOMIC);
3029 bus->varsz = bus->vars ? len : 0;
3030 if (bus->vars == NULL) {
3031 bcmerror = -ENOMEM;
3032 goto err;
3033 }
3034
3035 /* Copy the passed variables, which should include the
3036 terminating double-null */
3037 memcpy(bus->vars, arg, bus->varsz);
3038err:
3039 return bcmerror;
3040}
3041
3042static int brcmf_sdbrcm_write_vars(struct brcmf_sdio *bus) 3339static int brcmf_sdbrcm_write_vars(struct brcmf_sdio *bus)
3043{ 3340{
3044 int bcmerror = 0; 3341 int bcmerror = 0;
3045 u32 varsize;
3046 u32 varaddr; 3342 u32 varaddr;
3047 u8 *vbuffer;
3048 u32 varsizew; 3343 u32 varsizew;
3049 __le32 varsizew_le; 3344 __le32 varsizew_le;
3050#ifdef DEBUG 3345#ifdef DEBUG
@@ -3053,56 +3348,44 @@ static int brcmf_sdbrcm_write_vars(struct brcmf_sdio *bus)
3053 3348
3054 /* Even if there are no vars are to be written, we still 3349 /* Even if there are no vars are to be written, we still
3055 need to set the ramsize. */ 3350 need to set the ramsize. */
3056 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0; 3351 varaddr = (bus->ramsize - 4) - bus->varsz;
3057 varaddr = (bus->ramsize - 4) - varsize;
3058 3352
3059 if (bus->vars) { 3353 if (bus->vars) {
3060 vbuffer = kzalloc(varsize, GFP_ATOMIC);
3061 if (!vbuffer)
3062 return -ENOMEM;
3063
3064 memcpy(vbuffer, bus->vars, bus->varsz);
3065
3066 /* Write the vars list */ 3354 /* Write the vars list */
3067 bcmerror = 3355 bcmerror = brcmf_sdbrcm_membytes(bus, true, varaddr,
3068 brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize); 3356 bus->vars, bus->varsz);
3069#ifdef DEBUG 3357#ifdef DEBUG
3070 /* Verify NVRAM bytes */ 3358 /* Verify NVRAM bytes */
3071 brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize); 3359 brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n",
3072 nvram_ularray = kmalloc(varsize, GFP_ATOMIC); 3360 bus->varsz);
3073 if (!nvram_ularray) { 3361 nvram_ularray = kmalloc(bus->varsz, GFP_ATOMIC);
3074 kfree(vbuffer); 3362 if (!nvram_ularray)
3075 return -ENOMEM; 3363 return -ENOMEM;
3076 }
3077 3364
3078 /* Upload image to verify downloaded contents. */ 3365 /* Upload image to verify downloaded contents. */
3079 memset(nvram_ularray, 0xaa, varsize); 3366 memset(nvram_ularray, 0xaa, bus->varsz);
3080 3367
3081 /* Read the vars list to temp buffer for comparison */ 3368 /* Read the vars list to temp buffer for comparison */
3082 bcmerror = 3369 bcmerror = brcmf_sdbrcm_membytes(bus, false, varaddr,
3083 brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray, 3370 nvram_ularray, bus->varsz);
3084 varsize);
3085 if (bcmerror) { 3371 if (bcmerror) {
3086 brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n", 3372 brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
3087 bcmerror, varsize, varaddr); 3373 bcmerror, bus->varsz, varaddr);
3088 } 3374 }
3089 /* Compare the org NVRAM with the one read from RAM */ 3375 /* Compare the org NVRAM with the one read from RAM */
3090 if (memcmp(vbuffer, nvram_ularray, varsize)) 3376 if (memcmp(bus->vars, nvram_ularray, bus->varsz))
3091 brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n"); 3377 brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
3092 else 3378 else
3093 brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n"); 3379 brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
3094 3380
3095 kfree(nvram_ularray); 3381 kfree(nvram_ularray);
3096#endif /* DEBUG */ 3382#endif /* DEBUG */
3097
3098 kfree(vbuffer);
3099 } 3383 }
3100 3384
3101 /* adjust to the user specified RAM */ 3385 /* adjust to the user specified RAM */
3102 brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize); 3386 brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
3103 brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n", 3387 brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
3104 varaddr, varsize); 3388 varaddr, bus->varsz);
3105 varsize = ((bus->ramsize - 4) - varaddr);
3106 3389
3107 /* 3390 /*
3108 * Determine the length token: 3391 * Determine the length token:
@@ -3113,13 +3396,13 @@ static int brcmf_sdbrcm_write_vars(struct brcmf_sdio *bus)
3113 varsizew = 0; 3396 varsizew = 0;
3114 varsizew_le = cpu_to_le32(0); 3397 varsizew_le = cpu_to_le32(0);
3115 } else { 3398 } else {
3116 varsizew = varsize / 4; 3399 varsizew = bus->varsz / 4;
3117 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF); 3400 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
3118 varsizew_le = cpu_to_le32(varsizew); 3401 varsizew_le = cpu_to_le32(varsizew);
3119 } 3402 }
3120 3403
3121 brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n", 3404 brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
3122 varsize, varsizew); 3405 bus->varsz, varsizew);
3123 3406
3124 /* Write the length token to the last word */ 3407 /* Write the length token to the last word */
3125 bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4), 3408 bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4),
@@ -3243,13 +3526,21 @@ err:
3243 * by two NULs. 3526 * by two NULs.
3244*/ 3527*/
3245 3528
3246static uint brcmf_process_nvram_vars(char *varbuf, uint len) 3529static int brcmf_process_nvram_vars(struct brcmf_sdio *bus)
3247{ 3530{
3531 char *varbuf;
3248 char *dp; 3532 char *dp;
3249 bool findNewline; 3533 bool findNewline;
3250 int column; 3534 int column;
3251 uint buf_len, n; 3535 int ret = 0;
3536 uint buf_len, n, len;
3537
3538 len = bus->firmware->size;
3539 varbuf = vmalloc(len);
3540 if (!varbuf)
3541 return -ENOMEM;
3252 3542
3543 memcpy(varbuf, bus->firmware->data, len);
3253 dp = varbuf; 3544 dp = varbuf;
3254 3545
3255 findNewline = false; 3546 findNewline = false;
@@ -3278,56 +3569,44 @@ static uint brcmf_process_nvram_vars(char *varbuf, uint len)
3278 column++; 3569 column++;
3279 } 3570 }
3280 buf_len = dp - varbuf; 3571 buf_len = dp - varbuf;
3281
3282 while (dp < varbuf + n) 3572 while (dp < varbuf + n)
3283 *dp++ = 0; 3573 *dp++ = 0;
3284 3574
3285 return buf_len; 3575 kfree(bus->vars);
3576 /* roundup needed for download to device */
3577 bus->varsz = roundup(buf_len + 1, 4);
3578 bus->vars = kmalloc(bus->varsz, GFP_KERNEL);
3579 if (bus->vars == NULL) {
3580 bus->varsz = 0;
3581 ret = -ENOMEM;
3582 goto err;
3583 }
3584
3585 /* copy the processed variables and add null termination */
3586 memcpy(bus->vars, varbuf, buf_len);
3587 bus->vars[buf_len] = 0;
3588err:
3589 vfree(varbuf);
3590 return ret;
3286} 3591}
3287 3592
3288static int brcmf_sdbrcm_download_nvram(struct brcmf_sdio *bus) 3593static int brcmf_sdbrcm_download_nvram(struct brcmf_sdio *bus)
3289{ 3594{
3290 uint len;
3291 char *memblock = NULL;
3292 char *bufp;
3293 int ret; 3595 int ret;
3294 3596
3597 if (bus->sdiodev->bus_if->drvr_up)
3598 return -EISCONN;
3599
3295 ret = request_firmware(&bus->firmware, BRCMF_SDIO_NV_NAME, 3600 ret = request_firmware(&bus->firmware, BRCMF_SDIO_NV_NAME,
3296 &bus->sdiodev->func[2]->dev); 3601 &bus->sdiodev->func[2]->dev);
3297 if (ret) { 3602 if (ret) {
3298 brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret); 3603 brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
3299 return ret; 3604 return ret;
3300 } 3605 }
3301 bus->fw_ptr = 0;
3302 3606
3303 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC); 3607 ret = brcmf_process_nvram_vars(bus);
3304 if (memblock == NULL) {
3305 ret = -ENOMEM;
3306 goto err;
3307 }
3308
3309 len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
3310
3311 if (len > 0 && len < MEMBLOCK) {
3312 bufp = memblock;
3313 bufp[len] = 0;
3314 len = brcmf_process_nvram_vars(bufp, len);
3315 bufp += len;
3316 *bufp++ = 0;
3317 if (len)
3318 ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
3319 if (ret)
3320 brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
3321 } else {
3322 brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
3323 ret = -EIO;
3324 }
3325
3326err:
3327 kfree(memblock);
3328 3608
3329 release_firmware(bus->firmware); 3609 release_firmware(bus->firmware);
3330 bus->fw_ptr = 0;
3331 3610
3332 return ret; 3611 return ret;
3333} 3612}
@@ -3606,6 +3885,8 @@ static bool brcmf_sdbrcm_chipmatch(u16 chipid)
3606 return true; 3885 return true;
3607 if (chipid == BCM4330_CHIP_ID) 3886 if (chipid == BCM4330_CHIP_ID)
3608 return true; 3887 return true;
3888 if (chipid == BCM4334_CHIP_ID)
3889 return true;
3609 return false; 3890 return false;
3610} 3891}
3611 3892
@@ -3817,6 +4098,7 @@ static void brcmf_sdbrcm_release_dongle(struct brcmf_sdio *bus)
3817static void brcmf_sdbrcm_release(struct brcmf_sdio *bus) 4098static void brcmf_sdbrcm_release(struct brcmf_sdio *bus)
3818{ 4099{
3819 brcmf_dbg(TRACE, "Enter\n"); 4100 brcmf_dbg(TRACE, "Enter\n");
4101
3820 if (bus) { 4102 if (bus) {
3821 /* De-register interrupt handler */ 4103 /* De-register interrupt handler */
3822 brcmf_sdio_intr_unregister(bus->sdiodev); 4104 brcmf_sdio_intr_unregister(bus->sdiodev);
@@ -3838,6 +4120,10 @@ void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev)
3838{ 4120{
3839 int ret; 4121 int ret;
3840 struct brcmf_sdio *bus; 4122 struct brcmf_sdio *bus;
4123 struct brcmf_bus_dcmd *dlst;
4124 u32 dngl_txglom;
4125 u32 dngl_txglomalign;
4126 u8 idx;
3841 4127
3842 brcmf_dbg(TRACE, "Enter\n"); 4128 brcmf_dbg(TRACE, "Enter\n");
3843 4129
@@ -3923,6 +4209,26 @@ void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev)
3923 brcmf_sdio_debugfs_create(bus); 4209 brcmf_sdio_debugfs_create(bus);
3924 brcmf_dbg(INFO, "completed!!\n"); 4210 brcmf_dbg(INFO, "completed!!\n");
3925 4211
4212 /* sdio bus core specific dcmd */
4213 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
4214 dlst = kzalloc(sizeof(struct brcmf_bus_dcmd), GFP_KERNEL);
4215 if (dlst) {
4216 if (bus->ci->c_inf[idx].rev < 12) {
4217 /* for sdio core rev < 12, disable txgloming */
4218 dngl_txglom = 0;
4219 dlst->name = "bus:txglom";
4220 dlst->param = (char *)&dngl_txglom;
4221 dlst->param_len = sizeof(u32);
4222 } else {
4223 /* otherwise, set txglomalign */
4224 dngl_txglomalign = bus->sdiodev->bus_if->align;
4225 dlst->name = "bus:txglomalign";
4226 dlst->param = (char *)&dngl_txglomalign;
4227 dlst->param_len = sizeof(u32);
4228 }
4229 list_add(&dlst->list, &bus->sdiodev->bus_if->dcmd_list);
4230 }
4231
3926 /* if firmware path present try to download and bring up bus */ 4232 /* if firmware path present try to download and bring up bus */
3927 ret = brcmf_bus_start(bus->sdiodev->dev); 4233 ret = brcmf_bus_start(bus->sdiodev->dev);
3928 if (ret != 0) { 4234 if (ret != 0) {
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c b/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c
index f8e1f1c84d08..58155e23d220 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c
@@ -403,6 +403,23 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
403 ci->c_inf[3].cib = 0x03004211; 403 ci->c_inf[3].cib = 0x03004211;
404 ci->ramsize = 0x48000; 404 ci->ramsize = 0x48000;
405 break; 405 break;
406 case BCM4334_CHIP_ID:
407 ci->c_inf[0].wrapbase = 0x18100000;
408 ci->c_inf[0].cib = 0x29004211;
409 ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
410 ci->c_inf[1].base = 0x18002000;
411 ci->c_inf[1].wrapbase = 0x18102000;
412 ci->c_inf[1].cib = 0x0d004211;
413 ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
414 ci->c_inf[2].base = 0x18004000;
415 ci->c_inf[2].wrapbase = 0x18104000;
416 ci->c_inf[2].cib = 0x13080401;
417 ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
418 ci->c_inf[3].base = 0x18003000;
419 ci->c_inf[3].wrapbase = 0x18103000;
420 ci->c_inf[3].cib = 0x07004211;
421 ci->ramsize = 0x80000;
422 break;
406 default: 423 default:
407 brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip); 424 brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip);
408 return -ENODEV; 425 return -ENODEV;
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/channel.c b/drivers/net/wireless/brcm80211/brcmsmac/channel.c
index eb77ac3cfb6b..2d365d3486df 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/channel.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/channel.c
@@ -15,7 +15,9 @@
15 */ 15 */
16 16
17#include <linux/types.h> 17#include <linux/types.h>
18#include <net/cfg80211.h>
18#include <net/mac80211.h> 19#include <net/mac80211.h>
20#include <net/regulatory.h>
19 21
20#include <defs.h> 22#include <defs.h>
21#include "pub.h" 23#include "pub.h"
@@ -23,73 +25,17 @@
23#include "main.h" 25#include "main.h"
24#include "stf.h" 26#include "stf.h"
25#include "channel.h" 27#include "channel.h"
28#include "mac80211_if.h"
26 29
27/* QDB() macro takes a dB value and converts to a quarter dB value */ 30/* QDB() macro takes a dB value and converts to a quarter dB value */
28#define QDB(n) ((n) * BRCMS_TXPWR_DB_FACTOR) 31#define QDB(n) ((n) * BRCMS_TXPWR_DB_FACTOR)
29 32
30#define LOCALE_CHAN_01_11 (1<<0)
31#define LOCALE_CHAN_12_13 (1<<1)
32#define LOCALE_CHAN_14 (1<<2)
33#define LOCALE_SET_5G_LOW_JP1 (1<<3) /* 34-48, step 2 */
34#define LOCALE_SET_5G_LOW_JP2 (1<<4) /* 34-46, step 4 */
35#define LOCALE_SET_5G_LOW1 (1<<5) /* 36-48, step 4 */
36#define LOCALE_SET_5G_LOW2 (1<<6) /* 52 */
37#define LOCALE_SET_5G_LOW3 (1<<7) /* 56-64, step 4 */
38#define LOCALE_SET_5G_MID1 (1<<8) /* 100-116, step 4 */
39#define LOCALE_SET_5G_MID2 (1<<9) /* 120-124, step 4 */
40#define LOCALE_SET_5G_MID3 (1<<10) /* 128 */
41#define LOCALE_SET_5G_HIGH1 (1<<11) /* 132-140, step 4 */
42#define LOCALE_SET_5G_HIGH2 (1<<12) /* 149-161, step 4 */
43#define LOCALE_SET_5G_HIGH3 (1<<13) /* 165 */
44#define LOCALE_CHAN_52_140_ALL (1<<14)
45#define LOCALE_SET_5G_HIGH4 (1<<15) /* 184-216 */
46
47#define LOCALE_CHAN_36_64 (LOCALE_SET_5G_LOW1 | \
48 LOCALE_SET_5G_LOW2 | \
49 LOCALE_SET_5G_LOW3)
50#define LOCALE_CHAN_52_64 (LOCALE_SET_5G_LOW2 | LOCALE_SET_5G_LOW3)
51#define LOCALE_CHAN_100_124 (LOCALE_SET_5G_MID1 | LOCALE_SET_5G_MID2)
52#define LOCALE_CHAN_100_140 (LOCALE_SET_5G_MID1 | LOCALE_SET_5G_MID2 | \
53 LOCALE_SET_5G_MID3 | LOCALE_SET_5G_HIGH1)
54#define LOCALE_CHAN_149_165 (LOCALE_SET_5G_HIGH2 | LOCALE_SET_5G_HIGH3)
55#define LOCALE_CHAN_184_216 LOCALE_SET_5G_HIGH4
56
57#define LOCALE_CHAN_01_14 (LOCALE_CHAN_01_11 | \
58 LOCALE_CHAN_12_13 | \
59 LOCALE_CHAN_14)
60
61#define LOCALE_RADAR_SET_NONE 0
62#define LOCALE_RADAR_SET_1 1
63
64#define LOCALE_RESTRICTED_NONE 0
65#define LOCALE_RESTRICTED_SET_2G_SHORT 1
66#define LOCALE_RESTRICTED_CHAN_165 2
67#define LOCALE_CHAN_ALL_5G 3
68#define LOCALE_RESTRICTED_JAPAN_LEGACY 4
69#define LOCALE_RESTRICTED_11D_2G 5
70#define LOCALE_RESTRICTED_11D_5G 6
71#define LOCALE_RESTRICTED_LOW_HI 7
72#define LOCALE_RESTRICTED_12_13_14 8
73
74#define LOCALE_2G_IDX_i 0
75#define LOCALE_5G_IDX_11 0
76#define LOCALE_MIMO_IDX_bn 0 33#define LOCALE_MIMO_IDX_bn 0
77#define LOCALE_MIMO_IDX_11n 0 34#define LOCALE_MIMO_IDX_11n 0
78 35
79/* max of BAND_5G_PWR_LVLS and 6 for 2.4 GHz */
80#define BRCMS_MAXPWR_TBL_SIZE 6
81/* max of BAND_5G_PWR_LVLS and 14 for 2.4 GHz */ 36/* max of BAND_5G_PWR_LVLS and 14 for 2.4 GHz */
82#define BRCMS_MAXPWR_MIMO_TBL_SIZE 14 37#define BRCMS_MAXPWR_MIMO_TBL_SIZE 14
83 38
84/* power level in group of 2.4GHz band channels:
85 * maxpwr[0] - CCK channels [1]
86 * maxpwr[1] - CCK channels [2-10]
87 * maxpwr[2] - CCK channels [11-14]
88 * maxpwr[3] - OFDM channels [1]
89 * maxpwr[4] - OFDM channels [2-10]
90 * maxpwr[5] - OFDM channels [11-14]
91 */
92
93/* maxpwr mapping to 5GHz band channels: 39/* maxpwr mapping to 5GHz band channels:
94 * maxpwr[0] - channels [34-48] 40 * maxpwr[0] - channels [34-48]
95 * maxpwr[1] - channels [52-60] 41 * maxpwr[1] - channels [52-60]
@@ -101,16 +47,8 @@
101 47
102#define LC(id) LOCALE_MIMO_IDX_ ## id 48#define LC(id) LOCALE_MIMO_IDX_ ## id
103 49
104#define LC_2G(id) LOCALE_2G_IDX_ ## id 50#define LOCALES(mimo2, mimo5) \
105 51 {LC(mimo2), LC(mimo5)}
106#define LC_5G(id) LOCALE_5G_IDX_ ## id
107
108#define LOCALES(band2, band5, mimo2, mimo5) \
109 {LC_2G(band2), LC_5G(band5), LC(mimo2), LC(mimo5)}
110
111/* macro to get 2.4 GHz channel group index for tx power */
112#define CHANNEL_POWER_IDX_2G_CCK(c) (((c) < 2) ? 0 : (((c) < 11) ? 1 : 2))
113#define CHANNEL_POWER_IDX_2G_OFDM(c) (((c) < 2) ? 3 : (((c) < 11) ? 4 : 5))
114 52
115/* macro to get 5 GHz channel group index for tx power */ 53/* macro to get 5 GHz channel group index for tx power */
116#define CHANNEL_POWER_IDX_5G(c) (((c) < 52) ? 0 : \ 54#define CHANNEL_POWER_IDX_5G(c) (((c) < 52) ? 0 : \
@@ -118,18 +56,37 @@
118 (((c) < 100) ? 2 : \ 56 (((c) < 100) ? 2 : \
119 (((c) < 149) ? 3 : 4)))) 57 (((c) < 149) ? 3 : 4))))
120 58
121#define ISDFS_EU(fl) (((fl) & BRCMS_DFS_EU) == BRCMS_DFS_EU) 59#define BRCM_2GHZ_2412_2462 REG_RULE(2412-10, 2462+10, 40, 0, 19, 0)
122 60#define BRCM_2GHZ_2467_2472 REG_RULE(2467-10, 2472+10, 20, 0, 19, \
123struct brcms_cm_band { 61 NL80211_RRF_PASSIVE_SCAN | \
124 /* struct locale_info flags */ 62 NL80211_RRF_NO_IBSS)
125 u8 locale_flags; 63
126 /* List of valid channels in the country */ 64#define BRCM_5GHZ_5180_5240 REG_RULE(5180-10, 5240+10, 40, 0, 21, \
127 struct brcms_chanvec valid_channels; 65 NL80211_RRF_PASSIVE_SCAN | \
128 /* List of restricted use channels */ 66 NL80211_RRF_NO_IBSS)
129 const struct brcms_chanvec *restricted_channels; 67#define BRCM_5GHZ_5260_5320 REG_RULE(5260-10, 5320+10, 40, 0, 21, \
130 /* List of radar sensitive channels */ 68 NL80211_RRF_PASSIVE_SCAN | \
131 const struct brcms_chanvec *radar_channels; 69 NL80211_RRF_DFS | \
132 u8 PAD[8]; 70 NL80211_RRF_NO_IBSS)
71#define BRCM_5GHZ_5500_5700 REG_RULE(5500-10, 5700+10, 40, 0, 21, \
72 NL80211_RRF_PASSIVE_SCAN | \
73 NL80211_RRF_DFS | \
74 NL80211_RRF_NO_IBSS)
75#define BRCM_5GHZ_5745_5825 REG_RULE(5745-10, 5825+10, 40, 0, 21, \
76 NL80211_RRF_PASSIVE_SCAN | \
77 NL80211_RRF_NO_IBSS)
78
79static const struct ieee80211_regdomain brcms_regdom_x2 = {
80 .n_reg_rules = 7,
81 .alpha2 = "X2",
82 .reg_rules = {
83 BRCM_2GHZ_2412_2462,
84 BRCM_2GHZ_2467_2472,
85 BRCM_5GHZ_5180_5240,
86 BRCM_5GHZ_5260_5320,
87 BRCM_5GHZ_5500_5700,
88 BRCM_5GHZ_5745_5825,
89 }
133}; 90};
134 91
135 /* locale per-channel tx power limits for MIMO frames 92 /* locale per-channel tx power limits for MIMO frames
@@ -141,337 +98,23 @@ struct locale_mimo_info {
141 s8 maxpwr20[BRCMS_MAXPWR_MIMO_TBL_SIZE]; 98 s8 maxpwr20[BRCMS_MAXPWR_MIMO_TBL_SIZE];
142 /* tx 40 MHz power limits, qdBm units */ 99 /* tx 40 MHz power limits, qdBm units */
143 s8 maxpwr40[BRCMS_MAXPWR_MIMO_TBL_SIZE]; 100 s8 maxpwr40[BRCMS_MAXPWR_MIMO_TBL_SIZE];
144 u8 flags;
145}; 101};
146 102
147/* Country names and abbreviations with locale defined from ISO 3166 */ 103/* Country names and abbreviations with locale defined from ISO 3166 */
148struct country_info { 104struct country_info {
149 const u8 locale_2G; /* 2.4G band locale */
150 const u8 locale_5G; /* 5G band locale */
151 const u8 locale_mimo_2G; /* 2.4G mimo info */ 105 const u8 locale_mimo_2G; /* 2.4G mimo info */
152 const u8 locale_mimo_5G; /* 5G mimo info */ 106 const u8 locale_mimo_5G; /* 5G mimo info */
153}; 107};
154 108
109struct brcms_regd {
110 struct country_info country;
111 const struct ieee80211_regdomain *regdomain;
112};
113
155struct brcms_cm_info { 114struct brcms_cm_info {
156 struct brcms_pub *pub; 115 struct brcms_pub *pub;
157 struct brcms_c_info *wlc; 116 struct brcms_c_info *wlc;
158 char srom_ccode[BRCM_CNTRY_BUF_SZ]; /* Country Code in SROM */ 117 const struct brcms_regd *world_regd;
159 uint srom_regrev; /* Regulatory Rev for the SROM ccode */
160 const struct country_info *country; /* current country def */
161 char ccode[BRCM_CNTRY_BUF_SZ]; /* current internal Country Code */
162 uint regrev; /* current Regulatory Revision */
163 char country_abbrev[BRCM_CNTRY_BUF_SZ]; /* current advertised ccode */
164 /* per-band state (one per phy/radio) */
165 struct brcms_cm_band bandstate[MAXBANDS];
166 /* quiet channels currently for radar sensitivity or 11h support */
167 /* channels on which we cannot transmit */
168 struct brcms_chanvec quiet_channels;
169};
170
171/* locale channel and power info. */
172struct locale_info {
173 u32 valid_channels;
174 /* List of radar sensitive channels */
175 u8 radar_channels;
176 /* List of channels used only if APs are detected */
177 u8 restricted_channels;
178 /* Max tx pwr in qdBm for each sub-band */
179 s8 maxpwr[BRCMS_MAXPWR_TBL_SIZE];
180 /* Country IE advertised max tx pwr in dBm per sub-band */
181 s8 pub_maxpwr[BAND_5G_PWR_LVLS];
182 u8 flags;
183};
184
185/* Regulatory Matrix Spreadsheet (CLM) MIMO v3.7.9 */
186
187/*
188 * Some common channel sets
189 */
190
191/* No channels */
192static const struct brcms_chanvec chanvec_none = {
193 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
194 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
195 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
196 0x00, 0x00, 0x00, 0x00}
197};
198
199/* All 2.4 GHz HW channels */
200static const struct brcms_chanvec chanvec_all_2G = {
201 {0xfe, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
202 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
203 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
204 0x00, 0x00, 0x00, 0x00}
205};
206
207/* All 5 GHz HW channels */
208static const struct brcms_chanvec chanvec_all_5G = {
209 {0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x11, 0x11,
210 0x01, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x11,
211 0x11, 0x11, 0x20, 0x22, 0x22, 0x00, 0x00, 0x11,
212 0x11, 0x11, 0x11, 0x01}
213};
214
215/*
216 * Radar channel sets
217 */
218
219/* Channels 52 - 64, 100 - 140 */
220static const struct brcms_chanvec radar_set1 = {
221 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, /* 52 - 60 */
222 0x01, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x11, /* 64, 100 - 124 */
223 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 128 - 140 */
224 0x00, 0x00, 0x00, 0x00}
225};
226
227/*
228 * Restricted channel sets
229 */
230
231/* Channels 34, 38, 42, 46 */
232static const struct brcms_chanvec restricted_set_japan_legacy = {
233 {0x00, 0x00, 0x00, 0x00, 0x44, 0x44, 0x00, 0x00,
234 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
235 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
236 0x00, 0x00, 0x00, 0x00}
237};
238
239/* Channels 12, 13 */
240static const struct brcms_chanvec restricted_set_2g_short = {
241 {0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
242 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
243 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
244 0x00, 0x00, 0x00, 0x00}
245};
246
247/* Channel 165 */
248static const struct brcms_chanvec restricted_chan_165 = {
249 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
250 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
251 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
252 0x00, 0x00, 0x00, 0x00}
253};
254
255/* Channels 36 - 48 & 149 - 165 */
256static const struct brcms_chanvec restricted_low_hi = {
257 {0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x01, 0x00,
258 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0x00, 0x00, 0x20, 0x22, 0x22, 0x00, 0x00, 0x00,
260 0x00, 0x00, 0x00, 0x00}
261};
262
263/* Channels 12 - 14 */
264static const struct brcms_chanvec restricted_set_12_13_14 = {
265 {0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
266 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
267 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
268 0x00, 0x00, 0x00, 0x00}
269};
270
271/* global memory to provide working buffer for expanded locale */
272
273static const struct brcms_chanvec *g_table_radar_set[] = {
274 &chanvec_none,
275 &radar_set1
276};
277
278static const struct brcms_chanvec *g_table_restricted_chan[] = {
279 &chanvec_none, /* restricted_set_none */
280 &restricted_set_2g_short,
281 &restricted_chan_165,
282 &chanvec_all_5G,
283 &restricted_set_japan_legacy,
284 &chanvec_all_2G, /* restricted_set_11d_2G */
285 &chanvec_all_5G, /* restricted_set_11d_5G */
286 &restricted_low_hi,
287 &restricted_set_12_13_14
288};
289
290static const struct brcms_chanvec locale_2g_01_11 = {
291 {0xfe, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
292 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
293 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
294 0x00, 0x00, 0x00, 0x00}
295};
296
297static const struct brcms_chanvec locale_2g_12_13 = {
298 {0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
299 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
300 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
301 0x00, 0x00, 0x00, 0x00}
302};
303
304static const struct brcms_chanvec locale_2g_14 = {
305 {0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
306 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
307 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
308 0x00, 0x00, 0x00, 0x00}
309};
310
311static const struct brcms_chanvec locale_5g_LOW_JP1 = {
312 {0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x01, 0x00,
313 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
314 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
315 0x00, 0x00, 0x00, 0x00}
316};
317
318static const struct brcms_chanvec locale_5g_LOW_JP2 = {
319 {0x00, 0x00, 0x00, 0x00, 0x44, 0x44, 0x00, 0x00,
320 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
321 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
322 0x00, 0x00, 0x00, 0x00}
323};
324
325static const struct brcms_chanvec locale_5g_LOW1 = {
326 {0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x01, 0x00,
327 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
328 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
329 0x00, 0x00, 0x00, 0x00}
330};
331
332static const struct brcms_chanvec locale_5g_LOW2 = {
333 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
334 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
335 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
336 0x00, 0x00, 0x00, 0x00}
337};
338
339static const struct brcms_chanvec locale_5g_LOW3 = {
340 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
341 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
342 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
343 0x00, 0x00, 0x00, 0x00}
344};
345
346static const struct brcms_chanvec locale_5g_MID1 = {
347 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
348 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x00,
349 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
350 0x00, 0x00, 0x00, 0x00}
351};
352
353static const struct brcms_chanvec locale_5g_MID2 = {
354 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
355 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
356 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
357 0x00, 0x00, 0x00, 0x00}
358};
359
360static const struct brcms_chanvec locale_5g_MID3 = {
361 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
362 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
363 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
364 0x00, 0x00, 0x00, 0x00}
365};
366
367static const struct brcms_chanvec locale_5g_HIGH1 = {
368 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
369 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
370 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
371 0x00, 0x00, 0x00, 0x00}
372};
373
374static const struct brcms_chanvec locale_5g_HIGH2 = {
375 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
376 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
377 0x00, 0x00, 0x20, 0x22, 0x02, 0x00, 0x00, 0x00,
378 0x00, 0x00, 0x00, 0x00}
379};
380
381static const struct brcms_chanvec locale_5g_HIGH3 = {
382 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
383 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
384 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
385 0x00, 0x00, 0x00, 0x00}
386};
387
388static const struct brcms_chanvec locale_5g_52_140_ALL = {
389 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11,
390 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
391 0x11, 0x11, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
392 0x00, 0x00, 0x00, 0x00}
393};
394
395static const struct brcms_chanvec locale_5g_HIGH4 = {
396 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
397 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
398 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
399 0x11, 0x11, 0x11, 0x11}
400};
401
402static const struct brcms_chanvec *g_table_locale_base[] = {
403 &locale_2g_01_11,
404 &locale_2g_12_13,
405 &locale_2g_14,
406 &locale_5g_LOW_JP1,
407 &locale_5g_LOW_JP2,
408 &locale_5g_LOW1,
409 &locale_5g_LOW2,
410 &locale_5g_LOW3,
411 &locale_5g_MID1,
412 &locale_5g_MID2,
413 &locale_5g_MID3,
414 &locale_5g_HIGH1,
415 &locale_5g_HIGH2,
416 &locale_5g_HIGH3,
417 &locale_5g_52_140_ALL,
418 &locale_5g_HIGH4
419};
420
421static void brcms_c_locale_add_channels(struct brcms_chanvec *target,
422 const struct brcms_chanvec *channels)
423{
424 u8 i;
425 for (i = 0; i < sizeof(struct brcms_chanvec); i++)
426 target->vec[i] |= channels->vec[i];
427}
428
429static void brcms_c_locale_get_channels(const struct locale_info *locale,
430 struct brcms_chanvec *channels)
431{
432 u8 i;
433
434 memset(channels, 0, sizeof(struct brcms_chanvec));
435
436 for (i = 0; i < ARRAY_SIZE(g_table_locale_base); i++) {
437 if (locale->valid_channels & (1 << i))
438 brcms_c_locale_add_channels(channels,
439 g_table_locale_base[i]);
440 }
441}
442
443/*
444 * Locale Definitions - 2.4 GHz
445 */
446static const struct locale_info locale_i = { /* locale i. channel 1 - 13 */
447 LOCALE_CHAN_01_11 | LOCALE_CHAN_12_13,
448 LOCALE_RADAR_SET_NONE,
449 LOCALE_RESTRICTED_SET_2G_SHORT,
450 {QDB(19), QDB(19), QDB(19),
451 QDB(19), QDB(19), QDB(19)},
452 {20, 20, 20, 0},
453 BRCMS_EIRP
454};
455
456/*
457 * Locale Definitions - 5 GHz
458 */
459static const struct locale_info locale_11 = {
460 /* locale 11. channel 36 - 48, 52 - 64, 100 - 140, 149 - 165 */
461 LOCALE_CHAN_36_64 | LOCALE_CHAN_100_140 | LOCALE_CHAN_149_165,
462 LOCALE_RADAR_SET_1,
463 LOCALE_RESTRICTED_NONE,
464 {QDB(21), QDB(21), QDB(21), QDB(21), QDB(21)},
465 {23, 23, 23, 30, 30},
466 BRCMS_EIRP | BRCMS_DFS_EU
467};
468
469static const struct locale_info *g_locale_2g_table[] = {
470 &locale_i
471};
472
473static const struct locale_info *g_locale_5g_table[] = {
474 &locale_11
475}; 118};
476 119
477/* 120/*
@@ -484,7 +127,6 @@ static const struct locale_mimo_info locale_bn = {
484 {0, 0, QDB(13), QDB(13), QDB(13), 127 {0, 0, QDB(13), QDB(13), QDB(13),
485 QDB(13), QDB(13), QDB(13), QDB(13), QDB(13), 128 QDB(13), QDB(13), QDB(13), QDB(13), QDB(13),
486 QDB(13), 0, 0}, 129 QDB(13), 0, 0},
487 0
488}; 130};
489 131
490static const struct locale_mimo_info *g_mimo_2g_table[] = { 132static const struct locale_mimo_info *g_mimo_2g_table[] = {
@@ -497,114 +139,20 @@ static const struct locale_mimo_info *g_mimo_2g_table[] = {
497static const struct locale_mimo_info locale_11n = { 139static const struct locale_mimo_info locale_11n = {
498 { /* 12.5 dBm */ 50, 50, 50, QDB(15), QDB(15)}, 140 { /* 12.5 dBm */ 50, 50, 50, QDB(15), QDB(15)},
499 {QDB(14), QDB(15), QDB(15), QDB(15), QDB(15)}, 141 {QDB(14), QDB(15), QDB(15), QDB(15), QDB(15)},
500 0
501}; 142};
502 143
503static const struct locale_mimo_info *g_mimo_5g_table[] = { 144static const struct locale_mimo_info *g_mimo_5g_table[] = {
504 &locale_11n 145 &locale_11n
505}; 146};
506 147
507static const struct { 148static const struct brcms_regd cntry_locales[] = {
508 char abbrev[BRCM_CNTRY_BUF_SZ]; /* country abbreviation */ 149 /* Worldwide RoW 2, must always be at index 0 */
509 struct country_info country;
510} cntry_locales[] = {
511 { 150 {
512 "X2", LOCALES(i, 11, bn, 11n)}, /* Worldwide RoW 2 */ 151 .country = LOCALES(bn, 11n),
513}; 152 .regdomain = &brcms_regdom_x2,
514 153 },
515#ifdef SUPPORT_40MHZ
516/* 20MHz channel info for 40MHz pairing support */
517struct chan20_info {
518 u8 sb;
519 u8 adj_sbs;
520}; 154};
521 155
522/* indicates adjacent channels that are allowed for a 40 Mhz channel and
523 * those that permitted by the HT
524 */
525struct chan20_info chan20_info[] = {
526 /* 11b/11g */
527/* 0 */ {1, (CH_UPPER_SB | CH_EWA_VALID)},
528/* 1 */ {2, (CH_UPPER_SB | CH_EWA_VALID)},
529/* 2 */ {3, (CH_UPPER_SB | CH_EWA_VALID)},
530/* 3 */ {4, (CH_UPPER_SB | CH_EWA_VALID)},
531/* 4 */ {5, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
532/* 5 */ {6, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
533/* 6 */ {7, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
534/* 7 */ {8, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
535/* 8 */ {9, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
536/* 9 */ {10, (CH_LOWER_SB | CH_EWA_VALID)},
537/* 10 */ {11, (CH_LOWER_SB | CH_EWA_VALID)},
538/* 11 */ {12, (CH_LOWER_SB)},
539/* 12 */ {13, (CH_LOWER_SB)},
540/* 13 */ {14, (CH_LOWER_SB)},
541
542/* 11a japan high */
543/* 14 */ {34, (CH_UPPER_SB)},
544/* 15 */ {38, (CH_LOWER_SB)},
545/* 16 */ {42, (CH_LOWER_SB)},
546/* 17 */ {46, (CH_LOWER_SB)},
547
548/* 11a usa low */
549/* 18 */ {36, (CH_UPPER_SB | CH_EWA_VALID)},
550/* 19 */ {40, (CH_LOWER_SB | CH_EWA_VALID)},
551/* 20 */ {44, (CH_UPPER_SB | CH_EWA_VALID)},
552/* 21 */ {48, (CH_LOWER_SB | CH_EWA_VALID)},
553/* 22 */ {52, (CH_UPPER_SB | CH_EWA_VALID)},
554/* 23 */ {56, (CH_LOWER_SB | CH_EWA_VALID)},
555/* 24 */ {60, (CH_UPPER_SB | CH_EWA_VALID)},
556/* 25 */ {64, (CH_LOWER_SB | CH_EWA_VALID)},
557
558/* 11a Europe */
559/* 26 */ {100, (CH_UPPER_SB | CH_EWA_VALID)},
560/* 27 */ {104, (CH_LOWER_SB | CH_EWA_VALID)},
561/* 28 */ {108, (CH_UPPER_SB | CH_EWA_VALID)},
562/* 29 */ {112, (CH_LOWER_SB | CH_EWA_VALID)},
563/* 30 */ {116, (CH_UPPER_SB | CH_EWA_VALID)},
564/* 31 */ {120, (CH_LOWER_SB | CH_EWA_VALID)},
565/* 32 */ {124, (CH_UPPER_SB | CH_EWA_VALID)},
566/* 33 */ {128, (CH_LOWER_SB | CH_EWA_VALID)},
567/* 34 */ {132, (CH_UPPER_SB | CH_EWA_VALID)},
568/* 35 */ {136, (CH_LOWER_SB | CH_EWA_VALID)},
569/* 36 */ {140, (CH_LOWER_SB)},
570
571/* 11a usa high, ref5 only */
572/* The 0x80 bit in pdiv means these are REF5, other entries are REF20 */
573/* 37 */ {149, (CH_UPPER_SB | CH_EWA_VALID)},
574/* 38 */ {153, (CH_LOWER_SB | CH_EWA_VALID)},
575/* 39 */ {157, (CH_UPPER_SB | CH_EWA_VALID)},
576/* 40 */ {161, (CH_LOWER_SB | CH_EWA_VALID)},
577/* 41 */ {165, (CH_LOWER_SB)},
578
579/* 11a japan */
580/* 42 */ {184, (CH_UPPER_SB)},
581/* 43 */ {188, (CH_LOWER_SB)},
582/* 44 */ {192, (CH_UPPER_SB)},
583/* 45 */ {196, (CH_LOWER_SB)},
584/* 46 */ {200, (CH_UPPER_SB)},
585/* 47 */ {204, (CH_LOWER_SB)},
586/* 48 */ {208, (CH_UPPER_SB)},
587/* 49 */ {212, (CH_LOWER_SB)},
588/* 50 */ {216, (CH_LOWER_SB)}
589};
590#endif /* SUPPORT_40MHZ */
591
592static const struct locale_info *brcms_c_get_locale_2g(u8 locale_idx)
593{
594 if (locale_idx >= ARRAY_SIZE(g_locale_2g_table))
595 return NULL; /* error condition */
596
597 return g_locale_2g_table[locale_idx];
598}
599
600static const struct locale_info *brcms_c_get_locale_5g(u8 locale_idx)
601{
602 if (locale_idx >= ARRAY_SIZE(g_locale_5g_table))
603 return NULL; /* error condition */
604
605 return g_locale_5g_table[locale_idx];
606}
607
608static const struct locale_mimo_info *brcms_c_get_mimo_2g(u8 locale_idx) 156static const struct locale_mimo_info *brcms_c_get_mimo_2g(u8 locale_idx)
609{ 157{
610 if (locale_idx >= ARRAY_SIZE(g_mimo_2g_table)) 158 if (locale_idx >= ARRAY_SIZE(g_mimo_2g_table))
@@ -621,13 +169,6 @@ static const struct locale_mimo_info *brcms_c_get_mimo_5g(u8 locale_idx)
621 return g_mimo_5g_table[locale_idx]; 169 return g_mimo_5g_table[locale_idx];
622} 170}
623 171
624static int
625brcms_c_country_aggregate_map(struct brcms_cm_info *wlc_cm, const char *ccode,
626 char *mapped_ccode, uint *mapped_regrev)
627{
628 return false;
629}
630
631/* 172/*
632 * Indicates whether the country provided is valid to pass 173 * Indicates whether the country provided is valid to pass
633 * to cfg80211 or not. 174 * to cfg80211 or not.
@@ -662,155 +203,24 @@ static bool brcms_c_country_valid(const char *ccode)
662 return true; 203 return true;
663} 204}
664 205
665/* Lookup a country info structure from a null terminated country 206static const struct brcms_regd *brcms_world_regd(const char *regdom, int len)
666 * abbreviation and regrev directly with no translation.
667 */
668static const struct country_info *
669brcms_c_country_lookup_direct(const char *ccode, uint regrev)
670{ 207{
671 uint size, i; 208 const struct brcms_regd *regd = NULL;
672 209 int i;
673 /* Should just return 0 for single locale driver. */
674 /* Keep it this way in case we add more locales. (for now anyway) */
675
676 /*
677 * all other country def arrays are for regrev == 0, so if
678 * regrev is non-zero, fail
679 */
680 if (regrev > 0)
681 return NULL;
682
683 /* find matched table entry from country code */
684 size = ARRAY_SIZE(cntry_locales);
685 for (i = 0; i < size; i++) {
686 if (strcmp(ccode, cntry_locales[i].abbrev) == 0)
687 return &cntry_locales[i].country;
688 }
689 return NULL;
690}
691
692static const struct country_info *
693brcms_c_countrycode_map(struct brcms_cm_info *wlc_cm, const char *ccode,
694 char *mapped_ccode, uint *mapped_regrev)
695{
696 struct brcms_c_info *wlc = wlc_cm->wlc;
697 const struct country_info *country;
698 uint srom_regrev = wlc_cm->srom_regrev;
699 const char *srom_ccode = wlc_cm->srom_ccode;
700 int mapped;
701
702 /* check for currently supported ccode size */
703 if (strlen(ccode) > (BRCM_CNTRY_BUF_SZ - 1)) {
704 wiphy_err(wlc->wiphy, "wl%d: %s: ccode \"%s\" too long for "
705 "match\n", wlc->pub->unit, __func__, ccode);
706 return NULL;
707 }
708
709 /* default mapping is the given ccode and regrev 0 */
710 strncpy(mapped_ccode, ccode, BRCM_CNTRY_BUF_SZ);
711 *mapped_regrev = 0;
712
713 /* If the desired country code matches the srom country code,
714 * then the mapped country is the srom regulatory rev.
715 * Otherwise look for an aggregate mapping.
716 */
717 if (!strcmp(srom_ccode, ccode)) {
718 *mapped_regrev = srom_regrev;
719 mapped = 0;
720 wiphy_err(wlc->wiphy, "srom_code == ccode %s\n", __func__);
721 } else {
722 mapped =
723 brcms_c_country_aggregate_map(wlc_cm, ccode, mapped_ccode,
724 mapped_regrev);
725 }
726
727 /* find the matching built-in country definition */
728 country = brcms_c_country_lookup_direct(mapped_ccode, *mapped_regrev);
729
730 /* if there is not an exact rev match, default to rev zero */
731 if (country == NULL && *mapped_regrev != 0) {
732 *mapped_regrev = 0;
733 country =
734 brcms_c_country_lookup_direct(mapped_ccode, *mapped_regrev);
735 }
736
737 return country;
738}
739
740/* Lookup a country info structure from a null terminated country code
741 * The lookup is case sensitive.
742 */
743static const struct country_info *
744brcms_c_country_lookup(struct brcms_c_info *wlc, const char *ccode)
745{
746 const struct country_info *country;
747 char mapped_ccode[BRCM_CNTRY_BUF_SZ];
748 uint mapped_regrev;
749
750 /*
751 * map the country code to a built-in country code, regrev, and
752 * country_info struct
753 */
754 country = brcms_c_countrycode_map(wlc->cmi, ccode, mapped_ccode,
755 &mapped_regrev);
756
757 return country;
758}
759
760/*
761 * reset the quiet channels vector to the union
762 * of the restricted and radar channel sets
763 */
764static void brcms_c_quiet_channels_reset(struct brcms_cm_info *wlc_cm)
765{
766 struct brcms_c_info *wlc = wlc_cm->wlc;
767 uint i, j;
768 struct brcms_band *band;
769 const struct brcms_chanvec *chanvec;
770
771 memset(&wlc_cm->quiet_channels, 0, sizeof(struct brcms_chanvec));
772
773 band = wlc->band;
774 for (i = 0; i < wlc->pub->_nbands;
775 i++, band = wlc->bandstate[OTHERBANDUNIT(wlc)]) {
776
777 /* initialize quiet channels for restricted channels */
778 chanvec = wlc_cm->bandstate[band->bandunit].restricted_channels;
779 for (j = 0; j < sizeof(struct brcms_chanvec); j++)
780 wlc_cm->quiet_channels.vec[j] |= chanvec->vec[j];
781 210
211 for (i = 0; i < ARRAY_SIZE(cntry_locales); i++) {
212 if (!strncmp(regdom, cntry_locales[i].regdomain->alpha2, len)) {
213 regd = &cntry_locales[i];
214 break;
215 }
782 } 216 }
783}
784
785/* Is the channel valid for the current locale and current band? */
786static bool brcms_c_valid_channel20(struct brcms_cm_info *wlc_cm, uint val)
787{
788 struct brcms_c_info *wlc = wlc_cm->wlc;
789 217
790 return ((val < MAXCHANNEL) && 218 return regd;
791 isset(wlc_cm->bandstate[wlc->band->bandunit].valid_channels.vec,
792 val));
793} 219}
794 220
795/* Is the channel valid for the current locale and specified band? */ 221static const struct brcms_regd *brcms_default_world_regd(void)
796static bool brcms_c_valid_channel20_in_band(struct brcms_cm_info *wlc_cm,
797 uint bandunit, uint val)
798{
799 return ((val < MAXCHANNEL)
800 && isset(wlc_cm->bandstate[bandunit].valid_channels.vec, val));
801}
802
803/* Is the channel valid for the current locale? (but don't consider channels not
804 * available due to bandlocking)
805 */
806static bool brcms_c_valid_channel20_db(struct brcms_cm_info *wlc_cm, uint val)
807{ 222{
808 struct brcms_c_info *wlc = wlc_cm->wlc; 223 return &cntry_locales[0];
809
810 return brcms_c_valid_channel20(wlc->cmi, val) ||
811 (!wlc->bandlocked
812 && brcms_c_valid_channel20_in_band(wlc->cmi,
813 OTHERBANDUNIT(wlc), val));
814} 224}
815 225
816/* JP, J1 - J10 are Japan ccodes */ 226/* JP, J1 - J10 are Japan ccodes */
@@ -820,12 +230,6 @@ static bool brcms_c_japan_ccode(const char *ccode)
820 (ccode[1] == 'P' || (ccode[1] >= '1' && ccode[1] <= '9'))); 230 (ccode[1] == 'P' || (ccode[1] >= '1' && ccode[1] <= '9')));
821} 231}
822 232
823/* Returns true if currently set country is Japan or variant */
824static bool brcms_c_japan(struct brcms_c_info *wlc)
825{
826 return brcms_c_japan_ccode(wlc->cmi->country_abbrev);
827}
828
829static void 233static void
830brcms_c_channel_min_txpower_limits_with_local_constraint( 234brcms_c_channel_min_txpower_limits_with_local_constraint(
831 struct brcms_cm_info *wlc_cm, struct txpwr_limits *txpwr, 235 struct brcms_cm_info *wlc_cm, struct txpwr_limits *txpwr,
@@ -901,140 +305,16 @@ brcms_c_channel_min_txpower_limits_with_local_constraint(
901 305
902} 306}
903 307
904/* Update the radio state (enable/disable) and tx power targets
905 * based on a new set of channel/regulatory information
906 */
907static void brcms_c_channels_commit(struct brcms_cm_info *wlc_cm)
908{
909 struct brcms_c_info *wlc = wlc_cm->wlc;
910 uint chan;
911 struct txpwr_limits txpwr;
912
913 /* search for the existence of any valid channel */
914 for (chan = 0; chan < MAXCHANNEL; chan++) {
915 if (brcms_c_valid_channel20_db(wlc->cmi, chan))
916 break;
917 }
918 if (chan == MAXCHANNEL)
919 chan = INVCHANNEL;
920
921 /*
922 * based on the channel search above, set or
923 * clear WL_RADIO_COUNTRY_DISABLE.
924 */
925 if (chan == INVCHANNEL) {
926 /*
927 * country/locale with no valid channels, set
928 * the radio disable bit
929 */
930 mboolset(wlc->pub->radio_disabled, WL_RADIO_COUNTRY_DISABLE);
931 wiphy_err(wlc->wiphy, "wl%d: %s: no valid channel for \"%s\" "
932 "nbands %d bandlocked %d\n", wlc->pub->unit,
933 __func__, wlc_cm->country_abbrev, wlc->pub->_nbands,
934 wlc->bandlocked);
935 } else if (mboolisset(wlc->pub->radio_disabled,
936 WL_RADIO_COUNTRY_DISABLE)) {
937 /*
938 * country/locale with valid channel, clear
939 * the radio disable bit
940 */
941 mboolclr(wlc->pub->radio_disabled, WL_RADIO_COUNTRY_DISABLE);
942 }
943
944 /*
945 * Now that the country abbreviation is set, if the radio supports 2G,
946 * then set channel 14 restrictions based on the new locale.
947 */
948 if (wlc->pub->_nbands > 1 || wlc->band->bandtype == BRCM_BAND_2G)
949 wlc_phy_chanspec_ch14_widefilter_set(wlc->band->pi,
950 brcms_c_japan(wlc) ? true :
951 false);
952
953 if (wlc->pub->up && chan != INVCHANNEL) {
954 brcms_c_channel_reg_limits(wlc_cm, wlc->chanspec, &txpwr);
955 brcms_c_channel_min_txpower_limits_with_local_constraint(wlc_cm,
956 &txpwr, BRCMS_TXPWR_MAX);
957 wlc_phy_txpower_limit_set(wlc->band->pi, &txpwr, wlc->chanspec);
958 }
959}
960
961static int
962brcms_c_channels_init(struct brcms_cm_info *wlc_cm,
963 const struct country_info *country)
964{
965 struct brcms_c_info *wlc = wlc_cm->wlc;
966 uint i, j;
967 struct brcms_band *band;
968 const struct locale_info *li;
969 struct brcms_chanvec sup_chan;
970 const struct locale_mimo_info *li_mimo;
971
972 band = wlc->band;
973 for (i = 0; i < wlc->pub->_nbands;
974 i++, band = wlc->bandstate[OTHERBANDUNIT(wlc)]) {
975
976 li = (band->bandtype == BRCM_BAND_5G) ?
977 brcms_c_get_locale_5g(country->locale_5G) :
978 brcms_c_get_locale_2g(country->locale_2G);
979 wlc_cm->bandstate[band->bandunit].locale_flags = li->flags;
980 li_mimo = (band->bandtype == BRCM_BAND_5G) ?
981 brcms_c_get_mimo_5g(country->locale_mimo_5G) :
982 brcms_c_get_mimo_2g(country->locale_mimo_2G);
983
984 /* merge the mimo non-mimo locale flags */
985 wlc_cm->bandstate[band->bandunit].locale_flags |=
986 li_mimo->flags;
987
988 wlc_cm->bandstate[band->bandunit].restricted_channels =
989 g_table_restricted_chan[li->restricted_channels];
990 wlc_cm->bandstate[band->bandunit].radar_channels =
991 g_table_radar_set[li->radar_channels];
992
993 /*
994 * set the channel availability, masking out the channels
995 * that may not be supported on this phy.
996 */
997 wlc_phy_chanspec_band_validch(band->pi, band->bandtype,
998 &sup_chan);
999 brcms_c_locale_get_channels(li,
1000 &wlc_cm->bandstate[band->bandunit].
1001 valid_channels);
1002 for (j = 0; j < sizeof(struct brcms_chanvec); j++)
1003 wlc_cm->bandstate[band->bandunit].valid_channels.
1004 vec[j] &= sup_chan.vec[j];
1005 }
1006
1007 brcms_c_quiet_channels_reset(wlc_cm);
1008 brcms_c_channels_commit(wlc_cm);
1009
1010 return 0;
1011}
1012
1013/* 308/*
1014 * set the driver's current country and regulatory information 309 * set the driver's current country and regulatory information
1015 * using a country code as the source. Look up built in country 310 * using a country code as the source. Look up built in country
1016 * information found with the country code. 311 * information found with the country code.
1017 */ 312 */
1018static void 313static void
1019brcms_c_set_country_common(struct brcms_cm_info *wlc_cm, 314brcms_c_set_country(struct brcms_cm_info *wlc_cm,
1020 const char *country_abbrev, 315 const struct brcms_regd *regd)
1021 const char *ccode, uint regrev,
1022 const struct country_info *country)
1023{ 316{
1024 const struct locale_info *locale;
1025 struct brcms_c_info *wlc = wlc_cm->wlc; 317 struct brcms_c_info *wlc = wlc_cm->wlc;
1026 char prev_country_abbrev[BRCM_CNTRY_BUF_SZ];
1027
1028 /* save current country state */
1029 wlc_cm->country = country;
1030
1031 memset(&prev_country_abbrev, 0, BRCM_CNTRY_BUF_SZ);
1032 strncpy(prev_country_abbrev, wlc_cm->country_abbrev,
1033 BRCM_CNTRY_BUF_SZ - 1);
1034
1035 strncpy(wlc_cm->country_abbrev, country_abbrev, BRCM_CNTRY_BUF_SZ - 1);
1036 strncpy(wlc_cm->ccode, ccode, BRCM_CNTRY_BUF_SZ - 1);
1037 wlc_cm->regrev = regrev;
1038 318
1039 if ((wlc->pub->_n_enab & SUPPORT_11N) != 319 if ((wlc->pub->_n_enab & SUPPORT_11N) !=
1040 wlc->protection->nmode_user) 320 wlc->protection->nmode_user)
@@ -1042,75 +322,19 @@ brcms_c_set_country_common(struct brcms_cm_info *wlc_cm,
1042 322
1043 brcms_c_stf_ss_update(wlc, wlc->bandstate[BAND_2G_INDEX]); 323 brcms_c_stf_ss_update(wlc, wlc->bandstate[BAND_2G_INDEX]);
1044 brcms_c_stf_ss_update(wlc, wlc->bandstate[BAND_5G_INDEX]); 324 brcms_c_stf_ss_update(wlc, wlc->bandstate[BAND_5G_INDEX]);
1045 /* set or restore gmode as required by regulatory */
1046 locale = brcms_c_get_locale_2g(country->locale_2G);
1047 if (locale && (locale->flags & BRCMS_NO_OFDM))
1048 brcms_c_set_gmode(wlc, GMODE_LEGACY_B, false);
1049 else
1050 brcms_c_set_gmode(wlc, wlc->protection->gmode_user, false);
1051 325
1052 brcms_c_channels_init(wlc_cm, country); 326 brcms_c_set_gmode(wlc, wlc->protection->gmode_user, false);
1053 327
1054 return; 328 return;
1055} 329}
1056 330
1057static int
1058brcms_c_set_countrycode_rev(struct brcms_cm_info *wlc_cm,
1059 const char *country_abbrev,
1060 const char *ccode, int regrev)
1061{
1062 const struct country_info *country;
1063 char mapped_ccode[BRCM_CNTRY_BUF_SZ];
1064 uint mapped_regrev;
1065
1066 /* if regrev is -1, lookup the mapped country code,
1067 * otherwise use the ccode and regrev directly
1068 */
1069 if (regrev == -1) {
1070 /*
1071 * map the country code to a built-in country
1072 * code, regrev, and country_info
1073 */
1074 country =
1075 brcms_c_countrycode_map(wlc_cm, ccode, mapped_ccode,
1076 &mapped_regrev);
1077 } else {
1078 /* find the matching built-in country definition */
1079 country = brcms_c_country_lookup_direct(ccode, regrev);
1080 strncpy(mapped_ccode, ccode, BRCM_CNTRY_BUF_SZ);
1081 mapped_regrev = regrev;
1082 }
1083
1084 if (country == NULL)
1085 return -EINVAL;
1086
1087 /* set the driver state for the country */
1088 brcms_c_set_country_common(wlc_cm, country_abbrev, mapped_ccode,
1089 mapped_regrev, country);
1090
1091 return 0;
1092}
1093
1094/*
1095 * set the driver's current country and regulatory information using
1096 * a country code as the source. Lookup built in country information
1097 * found with the country code.
1098 */
1099static int
1100brcms_c_set_countrycode(struct brcms_cm_info *wlc_cm, const char *ccode)
1101{
1102 char country_abbrev[BRCM_CNTRY_BUF_SZ];
1103 strncpy(country_abbrev, ccode, BRCM_CNTRY_BUF_SZ);
1104 return brcms_c_set_countrycode_rev(wlc_cm, country_abbrev, ccode, -1);
1105}
1106
1107struct brcms_cm_info *brcms_c_channel_mgr_attach(struct brcms_c_info *wlc) 331struct brcms_cm_info *brcms_c_channel_mgr_attach(struct brcms_c_info *wlc)
1108{ 332{
1109 struct brcms_cm_info *wlc_cm; 333 struct brcms_cm_info *wlc_cm;
1110 char country_abbrev[BRCM_CNTRY_BUF_SZ];
1111 const struct country_info *country;
1112 struct brcms_pub *pub = wlc->pub; 334 struct brcms_pub *pub = wlc->pub;
1113 struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom; 335 struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
336 const char *ccode = sprom->alpha2;
337 int ccode_len = sizeof(sprom->alpha2);
1114 338
1115 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 339 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
1116 340
@@ -1122,24 +346,27 @@ struct brcms_cm_info *brcms_c_channel_mgr_attach(struct brcms_c_info *wlc)
1122 wlc->cmi = wlc_cm; 346 wlc->cmi = wlc_cm;
1123 347
1124 /* store the country code for passing up as a regulatory hint */ 348 /* store the country code for passing up as a regulatory hint */
1125 if (sprom->alpha2 && brcms_c_country_valid(sprom->alpha2)) 349 wlc_cm->world_regd = brcms_world_regd(ccode, ccode_len);
1126 strncpy(wlc->pub->srom_ccode, sprom->alpha2, sizeof(sprom->alpha2)); 350 if (brcms_c_country_valid(ccode))
351 strncpy(wlc->pub->srom_ccode, ccode, ccode_len);
1127 352
1128 /* 353 /*
1129 * internal country information which must match 354 * If no custom world domain is found in the SROM, use the
1130 * regulatory constraints in firmware 355 * default "X2" domain.
1131 */ 356 */
1132 memset(country_abbrev, 0, BRCM_CNTRY_BUF_SZ); 357 if (!wlc_cm->world_regd) {
1133 strncpy(country_abbrev, "X2", sizeof(country_abbrev) - 1); 358 wlc_cm->world_regd = brcms_default_world_regd();
1134 country = brcms_c_country_lookup(wlc, country_abbrev); 359 ccode = wlc_cm->world_regd->regdomain->alpha2;
360 ccode_len = BRCM_CNTRY_BUF_SZ - 1;
361 }
1135 362
1136 /* save default country for exiting 11d regulatory mode */ 363 /* save default country for exiting 11d regulatory mode */
1137 strncpy(wlc->country_default, country_abbrev, BRCM_CNTRY_BUF_SZ - 1); 364 strncpy(wlc->country_default, ccode, ccode_len);
1138 365
1139 /* initialize autocountry_default to driver default */ 366 /* initialize autocountry_default to driver default */
1140 strncpy(wlc->autocountry_default, "X2", BRCM_CNTRY_BUF_SZ - 1); 367 strncpy(wlc->autocountry_default, ccode, ccode_len);
1141 368
1142 brcms_c_set_countrycode(wlc_cm, country_abbrev); 369 brcms_c_set_country(wlc_cm, wlc_cm->world_regd);
1143 370
1144 return wlc_cm; 371 return wlc_cm;
1145} 372}
@@ -1149,31 +376,15 @@ void brcms_c_channel_mgr_detach(struct brcms_cm_info *wlc_cm)
1149 kfree(wlc_cm); 376 kfree(wlc_cm);
1150} 377}
1151 378
1152u8
1153brcms_c_channel_locale_flags_in_band(struct brcms_cm_info *wlc_cm,
1154 uint bandunit)
1155{
1156 return wlc_cm->bandstate[bandunit].locale_flags;
1157}
1158
1159static bool
1160brcms_c_quiet_chanspec(struct brcms_cm_info *wlc_cm, u16 chspec)
1161{
1162 return (wlc_cm->wlc->pub->_n_enab & SUPPORT_11N) &&
1163 CHSPEC_IS40(chspec) ?
1164 (isset(wlc_cm->quiet_channels.vec,
1165 lower_20_sb(CHSPEC_CHANNEL(chspec))) ||
1166 isset(wlc_cm->quiet_channels.vec,
1167 upper_20_sb(CHSPEC_CHANNEL(chspec)))) :
1168 isset(wlc_cm->quiet_channels.vec, CHSPEC_CHANNEL(chspec));
1169}
1170
1171void 379void
1172brcms_c_channel_set_chanspec(struct brcms_cm_info *wlc_cm, u16 chanspec, 380brcms_c_channel_set_chanspec(struct brcms_cm_info *wlc_cm, u16 chanspec,
1173 u8 local_constraint_qdbm) 381 u8 local_constraint_qdbm)
1174{ 382{
1175 struct brcms_c_info *wlc = wlc_cm->wlc; 383 struct brcms_c_info *wlc = wlc_cm->wlc;
384 struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.channel;
385 const struct ieee80211_reg_rule *reg_rule;
1176 struct txpwr_limits txpwr; 386 struct txpwr_limits txpwr;
387 int ret;
1177 388
1178 brcms_c_channel_reg_limits(wlc_cm, chanspec, &txpwr); 389 brcms_c_channel_reg_limits(wlc_cm, chanspec, &txpwr);
1179 390
@@ -1181,8 +392,15 @@ brcms_c_channel_set_chanspec(struct brcms_cm_info *wlc_cm, u16 chanspec,
1181 wlc_cm, &txpwr, local_constraint_qdbm 392 wlc_cm, &txpwr, local_constraint_qdbm
1182 ); 393 );
1183 394
395 /* set or restore gmode as required by regulatory */
396 ret = freq_reg_info(wlc->wiphy, ch->center_freq, 0, &reg_rule);
397 if (!ret && (reg_rule->flags & NL80211_RRF_NO_OFDM))
398 brcms_c_set_gmode(wlc, GMODE_LEGACY_B, false);
399 else
400 brcms_c_set_gmode(wlc, wlc->protection->gmode_user, false);
401
1184 brcms_b_set_chanspec(wlc->hw, chanspec, 402 brcms_b_set_chanspec(wlc->hw, chanspec,
1185 (brcms_c_quiet_chanspec(wlc_cm, chanspec) != 0), 403 !!(ch->flags & IEEE80211_CHAN_PASSIVE_SCAN),
1186 &txpwr); 404 &txpwr);
1187} 405}
1188 406
@@ -1191,15 +409,14 @@ brcms_c_channel_reg_limits(struct brcms_cm_info *wlc_cm, u16 chanspec,
1191 struct txpwr_limits *txpwr) 409 struct txpwr_limits *txpwr)
1192{ 410{
1193 struct brcms_c_info *wlc = wlc_cm->wlc; 411 struct brcms_c_info *wlc = wlc_cm->wlc;
412 struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.channel;
1194 uint i; 413 uint i;
1195 uint chan; 414 uint chan;
1196 int maxpwr; 415 int maxpwr;
1197 int delta; 416 int delta;
1198 const struct country_info *country; 417 const struct country_info *country;
1199 struct brcms_band *band; 418 struct brcms_band *band;
1200 const struct locale_info *li;
1201 int conducted_max = BRCMS_TXPWR_MAX; 419 int conducted_max = BRCMS_TXPWR_MAX;
1202 int conducted_ofdm_max = BRCMS_TXPWR_MAX;
1203 const struct locale_mimo_info *li_mimo; 420 const struct locale_mimo_info *li_mimo;
1204 int maxpwr20, maxpwr40; 421 int maxpwr20, maxpwr40;
1205 int maxpwr_idx; 422 int maxpwr_idx;
@@ -1207,67 +424,35 @@ brcms_c_channel_reg_limits(struct brcms_cm_info *wlc_cm, u16 chanspec,
1207 424
1208 memset(txpwr, 0, sizeof(struct txpwr_limits)); 425 memset(txpwr, 0, sizeof(struct txpwr_limits));
1209 426
1210 if (!brcms_c_valid_chanspec_db(wlc_cm, chanspec)) { 427 if (WARN_ON(!ch))
1211 country = brcms_c_country_lookup(wlc, wlc->autocountry_default); 428 return;
1212 if (country == NULL) 429
1213 return; 430 country = &wlc_cm->world_regd->country;
1214 } else {
1215 country = wlc_cm->country;
1216 }
1217 431
1218 chan = CHSPEC_CHANNEL(chanspec); 432 chan = CHSPEC_CHANNEL(chanspec);
1219 band = wlc->bandstate[chspec_bandunit(chanspec)]; 433 band = wlc->bandstate[chspec_bandunit(chanspec)];
1220 li = (band->bandtype == BRCM_BAND_5G) ?
1221 brcms_c_get_locale_5g(country->locale_5G) :
1222 brcms_c_get_locale_2g(country->locale_2G);
1223
1224 li_mimo = (band->bandtype == BRCM_BAND_5G) ? 434 li_mimo = (band->bandtype == BRCM_BAND_5G) ?
1225 brcms_c_get_mimo_5g(country->locale_mimo_5G) : 435 brcms_c_get_mimo_5g(country->locale_mimo_5G) :
1226 brcms_c_get_mimo_2g(country->locale_mimo_2G); 436 brcms_c_get_mimo_2g(country->locale_mimo_2G);
1227 437
1228 if (li->flags & BRCMS_EIRP) { 438 delta = band->antgain;
1229 delta = band->antgain;
1230 } else {
1231 delta = 0;
1232 if (band->antgain > QDB(6))
1233 delta = band->antgain - QDB(6); /* Excess over 6 dB */
1234 }
1235 439
1236 if (li == &locale_i) { 440 if (band->bandtype == BRCM_BAND_2G)
1237 conducted_max = QDB(22); 441 conducted_max = QDB(22);
1238 conducted_ofdm_max = QDB(22); 442
1239 } 443 maxpwr = QDB(ch->max_power) - delta;
444 maxpwr = max(maxpwr, 0);
445 maxpwr = min(maxpwr, conducted_max);
1240 446
1241 /* CCK txpwr limits for 2.4G band */ 447 /* CCK txpwr limits for 2.4G band */
1242 if (band->bandtype == BRCM_BAND_2G) { 448 if (band->bandtype == BRCM_BAND_2G) {
1243 maxpwr = li->maxpwr[CHANNEL_POWER_IDX_2G_CCK(chan)];
1244
1245 maxpwr = maxpwr - delta;
1246 maxpwr = max(maxpwr, 0);
1247 maxpwr = min(maxpwr, conducted_max);
1248
1249 for (i = 0; i < BRCMS_NUM_RATES_CCK; i++) 449 for (i = 0; i < BRCMS_NUM_RATES_CCK; i++)
1250 txpwr->cck[i] = (u8) maxpwr; 450 txpwr->cck[i] = (u8) maxpwr;
1251 } 451 }
1252 452
1253 /* OFDM txpwr limits for 2.4G or 5G bands */ 453 for (i = 0; i < BRCMS_NUM_RATES_OFDM; i++) {
1254 if (band->bandtype == BRCM_BAND_2G)
1255 maxpwr = li->maxpwr[CHANNEL_POWER_IDX_2G_OFDM(chan)];
1256 else
1257 maxpwr = li->maxpwr[CHANNEL_POWER_IDX_5G(chan)];
1258
1259 maxpwr = maxpwr - delta;
1260 maxpwr = max(maxpwr, 0);
1261 maxpwr = min(maxpwr, conducted_ofdm_max);
1262
1263 /* Keep OFDM lmit below CCK limit */
1264 if (band->bandtype == BRCM_BAND_2G)
1265 maxpwr = min_t(int, maxpwr, txpwr->cck[0]);
1266
1267 for (i = 0; i < BRCMS_NUM_RATES_OFDM; i++)
1268 txpwr->ofdm[i] = (u8) maxpwr; 454 txpwr->ofdm[i] = (u8) maxpwr;
1269 455
1270 for (i = 0; i < BRCMS_NUM_RATES_OFDM; i++) {
1271 /* 456 /*
1272 * OFDM 40 MHz SISO has the same power as the corresponding 457 * OFDM 40 MHz SISO has the same power as the corresponding
1273 * MCS0-7 rate unless overriden by the locale specific code. 458 * MCS0-7 rate unless overriden by the locale specific code.
@@ -1282,14 +467,9 @@ brcms_c_channel_reg_limits(struct brcms_cm_info *wlc_cm, u16 chanspec,
1282 txpwr->ofdm_40_cdd[i] = 0; 467 txpwr->ofdm_40_cdd[i] = 0;
1283 } 468 }
1284 469
1285 /* MIMO/HT specific limits */ 470 delta = 0;
1286 if (li_mimo->flags & BRCMS_EIRP) { 471 if (band->antgain > QDB(6))
1287 delta = band->antgain; 472 delta = band->antgain - QDB(6); /* Excess over 6 dB */
1288 } else {
1289 delta = 0;
1290 if (band->antgain > QDB(6))
1291 delta = band->antgain - QDB(6); /* Excess over 6 dB */
1292 }
1293 473
1294 if (band->bandtype == BRCM_BAND_2G) 474 if (band->bandtype == BRCM_BAND_2G)
1295 maxpwr_idx = (chan - 1); 475 maxpwr_idx = (chan - 1);
@@ -1431,8 +611,7 @@ static bool brcms_c_chspec_malformed(u16 chanspec)
1431 * and they are also a legal HT combination 611 * and they are also a legal HT combination
1432 */ 612 */
1433static bool 613static bool
1434brcms_c_valid_chanspec_ext(struct brcms_cm_info *wlc_cm, u16 chspec, 614brcms_c_valid_chanspec_ext(struct brcms_cm_info *wlc_cm, u16 chspec)
1435 bool dualband)
1436{ 615{
1437 struct brcms_c_info *wlc = wlc_cm->wlc; 616 struct brcms_c_info *wlc = wlc_cm->wlc;
1438 u8 channel = CHSPEC_CHANNEL(chspec); 617 u8 channel = CHSPEC_CHANNEL(chspec);
@@ -1448,59 +627,166 @@ brcms_c_valid_chanspec_ext(struct brcms_cm_info *wlc_cm, u16 chspec,
1448 chspec_bandunit(chspec)) 627 chspec_bandunit(chspec))
1449 return false; 628 return false;
1450 629
1451 /* Check a 20Mhz channel */ 630 return true;
1452 if (CHSPEC_IS20(chspec)) { 631}
1453 if (dualband) 632
1454 return brcms_c_valid_channel20_db(wlc_cm->wlc->cmi, 633bool brcms_c_valid_chanspec_db(struct brcms_cm_info *wlc_cm, u16 chspec)
1455 channel); 634{
1456 else 635 return brcms_c_valid_chanspec_ext(wlc_cm, chspec);
1457 return brcms_c_valid_channel20(wlc_cm->wlc->cmi, 636}
1458 channel); 637
638static bool brcms_is_radar_freq(u16 center_freq)
639{
640 return center_freq >= 5260 && center_freq <= 5700;
641}
642
643static void brcms_reg_apply_radar_flags(struct wiphy *wiphy)
644{
645 struct ieee80211_supported_band *sband;
646 struct ieee80211_channel *ch;
647 int i;
648
649 sband = wiphy->bands[IEEE80211_BAND_5GHZ];
650 if (!sband)
651 return;
652
653 for (i = 0; i < sband->n_channels; i++) {
654 ch = &sband->channels[i];
655
656 if (!brcms_is_radar_freq(ch->center_freq))
657 continue;
658
659 /*
660 * All channels in this range should be passive and have
661 * DFS enabled.
662 */
663 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
664 ch->flags |= IEEE80211_CHAN_RADAR |
665 IEEE80211_CHAN_NO_IBSS |
666 IEEE80211_CHAN_PASSIVE_SCAN;
1459 } 667 }
1460#ifdef SUPPORT_40MHZ 668}
1461 /* 669
1462 * We know we are now checking a 40MHZ channel, so we should 670static void
1463 * only be here for NPHYS 671brcms_reg_apply_beaconing_flags(struct wiphy *wiphy,
1464 */ 672 enum nl80211_reg_initiator initiator)
1465 if (BRCMS_ISNPHY(wlc->band) || BRCMS_ISSSLPNPHY(wlc->band)) { 673{
1466 u8 upper_sideband = 0, idx; 674 struct ieee80211_supported_band *sband;
1467 u8 num_ch20_entries = 675 struct ieee80211_channel *ch;
1468 sizeof(chan20_info) / sizeof(struct chan20_info); 676 const struct ieee80211_reg_rule *rule;
1469 677 int band, i, ret;
1470 if (!VALID_40CHANSPEC_IN_BAND(wlc, chspec_bandunit(chspec))) 678
1471 return false; 679 for (band = 0; band < IEEE80211_NUM_BANDS; band++) {
1472 680 sband = wiphy->bands[band];
1473 if (dualband) { 681 if (!sband)
1474 if (!brcms_c_valid_channel20_db(wlc->cmi, 682 continue;
1475 lower_20_sb(channel)) || 683
1476 !brcms_c_valid_channel20_db(wlc->cmi, 684 for (i = 0; i < sband->n_channels; i++) {
1477 upper_20_sb(channel))) 685 ch = &sband->channels[i];
1478 return false; 686
1479 } else { 687 if (ch->flags &
1480 if (!brcms_c_valid_channel20(wlc->cmi, 688 (IEEE80211_CHAN_DISABLED | IEEE80211_CHAN_RADAR))
1481 lower_20_sb(channel)) || 689 continue;
1482 !brcms_c_valid_channel20(wlc->cmi, 690
1483 upper_20_sb(channel))) 691 if (initiator == NL80211_REGDOM_SET_BY_COUNTRY_IE) {
1484 return false; 692 ret = freq_reg_info(wiphy, ch->center_freq,
693 0, &rule);
694 if (ret)
695 continue;
696
697 if (!(rule->flags & NL80211_RRF_NO_IBSS))
698 ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
699 if (!(rule->flags & NL80211_RRF_PASSIVE_SCAN))
700 ch->flags &=
701 ~IEEE80211_CHAN_PASSIVE_SCAN;
702 } else if (ch->beacon_found) {
703 ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
704 IEEE80211_CHAN_PASSIVE_SCAN);
705 }
1485 } 706 }
707 }
708}
1486 709
1487 /* find the lower sideband info in the sideband array */ 710static int brcms_reg_notifier(struct wiphy *wiphy,
1488 for (idx = 0; idx < num_ch20_entries; idx++) { 711 struct regulatory_request *request)
1489 if (chan20_info[idx].sb == lower_20_sb(channel)) 712{
1490 upper_sideband = chan20_info[idx].adj_sbs; 713 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
714 struct brcms_info *wl = hw->priv;
715 struct brcms_c_info *wlc = wl->wlc;
716 struct ieee80211_supported_band *sband;
717 struct ieee80211_channel *ch;
718 int band, i;
719 bool ch_found = false;
720
721 brcms_reg_apply_radar_flags(wiphy);
722
723 if (request->initiator == NL80211_REGDOM_SET_BY_COUNTRY_IE)
724 brcms_reg_apply_beaconing_flags(wiphy, request->initiator);
725
726 /* Disable radio if all channels disallowed by regulatory */
727 for (band = 0; !ch_found && band < IEEE80211_NUM_BANDS; band++) {
728 sband = wiphy->bands[band];
729 if (!sband)
730 continue;
731
732 for (i = 0; !ch_found && i < sband->n_channels; i++) {
733 ch = &sband->channels[i];
734
735 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
736 ch_found = true;
1491 } 737 }
1492 /* check that the lower sideband allows an upper sideband */
1493 if ((upper_sideband & (CH_UPPER_SB | CH_EWA_VALID)) ==
1494 (CH_UPPER_SB | CH_EWA_VALID))
1495 return true;
1496 return false;
1497 } 738 }
1498#endif /* 40 MHZ */
1499 739
1500 return false; 740 if (ch_found) {
741 mboolclr(wlc->pub->radio_disabled, WL_RADIO_COUNTRY_DISABLE);
742 } else {
743 mboolset(wlc->pub->radio_disabled, WL_RADIO_COUNTRY_DISABLE);
744 wiphy_err(wlc->wiphy, "wl%d: %s: no valid channel for \"%s\"\n",
745 wlc->pub->unit, __func__, request->alpha2);
746 }
747
748 if (wlc->pub->_nbands > 1 || wlc->band->bandtype == BRCM_BAND_2G)
749 wlc_phy_chanspec_ch14_widefilter_set(wlc->band->pi,
750 brcms_c_japan_ccode(request->alpha2));
751
752 return 0;
1501} 753}
1502 754
1503bool brcms_c_valid_chanspec_db(struct brcms_cm_info *wlc_cm, u16 chspec) 755void brcms_c_regd_init(struct brcms_c_info *wlc)
1504{ 756{
1505 return brcms_c_valid_chanspec_ext(wlc_cm, chspec, true); 757 struct wiphy *wiphy = wlc->wiphy;
758 const struct brcms_regd *regd = wlc->cmi->world_regd;
759 struct ieee80211_supported_band *sband;
760 struct ieee80211_channel *ch;
761 struct brcms_chanvec sup_chan;
762 struct brcms_band *band;
763 int band_idx, i;
764
765 /* Disable any channels not supported by the phy */
766 for (band_idx = 0; band_idx < IEEE80211_NUM_BANDS; band_idx++) {
767 if (band_idx == IEEE80211_BAND_2GHZ)
768 band = wlc->bandstate[BAND_2G_INDEX];
769 else
770 band = wlc->bandstate[BAND_5G_INDEX];
771
772 /* skip if band not initialized */
773 if (band->pi == NULL)
774 continue;
775
776 wlc_phy_chanspec_band_validch(band->pi, band->bandtype,
777 &sup_chan);
778
779 sband = wiphy->bands[band_idx];
780 for (i = 0; i < sband->n_channels; i++) {
781 ch = &sband->channels[i];
782 if (!isset(sup_chan.vec, ch->hw_value))
783 ch->flags |= IEEE80211_CHAN_DISABLED;
784 }
785 }
786
787 wlc->wiphy->reg_notifier = brcms_reg_notifier;
788 wlc->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
789 WIPHY_FLAG_STRICT_REGULATORY;
790 wiphy_apply_custom_regulatory(wlc->wiphy, regd->regdomain);
791 brcms_reg_apply_beaconing_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER);
1506} 792}
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/channel.h b/drivers/net/wireless/brcm80211/brcmsmac/channel.h
index 808cb4fbfbe7..006483a0abe6 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/channel.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/channel.h
@@ -37,9 +37,6 @@ brcms_c_channel_mgr_attach(struct brcms_c_info *wlc);
37 37
38extern void brcms_c_channel_mgr_detach(struct brcms_cm_info *wlc_cm); 38extern void brcms_c_channel_mgr_detach(struct brcms_cm_info *wlc_cm);
39 39
40extern u8 brcms_c_channel_locale_flags_in_band(struct brcms_cm_info *wlc_cm,
41 uint bandunit);
42
43extern bool brcms_c_valid_chanspec_db(struct brcms_cm_info *wlc_cm, 40extern bool brcms_c_valid_chanspec_db(struct brcms_cm_info *wlc_cm,
44 u16 chspec); 41 u16 chspec);
45 42
@@ -49,5 +46,6 @@ extern void brcms_c_channel_reg_limits(struct brcms_cm_info *wlc_cm,
49extern void brcms_c_channel_set_chanspec(struct brcms_cm_info *wlc_cm, 46extern void brcms_c_channel_set_chanspec(struct brcms_cm_info *wlc_cm,
50 u16 chanspec, 47 u16 chanspec,
51 u8 local_constraint_qdbm); 48 u8 local_constraint_qdbm);
49extern void brcms_c_regd_init(struct brcms_c_info *wlc);
52 50
53#endif /* _WLC_CHANNEL_H */ 51#endif /* _WLC_CHANNEL_H */
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
index 341e06a0d6ec..2d5a40412690 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
@@ -1050,6 +1050,8 @@ static struct brcms_info *brcms_attach(struct bcma_device *pdev)
1050 goto fail; 1050 goto fail;
1051 } 1051 }
1052 1052
1053 brcms_c_regd_init(wl->wlc);
1054
1053 memcpy(perm, &wl->pub->cur_etheraddr, ETH_ALEN); 1055 memcpy(perm, &wl->pub->cur_etheraddr, ETH_ALEN);
1054 if (WARN_ON(!is_valid_ether_addr(perm))) 1056 if (WARN_ON(!is_valid_ether_addr(perm)))
1055 goto fail; 1057 goto fail;
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/main.c b/drivers/net/wireless/brcm80211/brcmsmac/main.c
index e67556780a31..bb00b6528d8f 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
@@ -18,6 +18,7 @@
18 18
19#include <linux/pci_ids.h> 19#include <linux/pci_ids.h>
20#include <linux/if_ether.h> 20#include <linux/if_ether.h>
21#include <net/cfg80211.h>
21#include <net/mac80211.h> 22#include <net/mac80211.h>
22#include <brcm_hw_ids.h> 23#include <brcm_hw_ids.h>
23#include <aiutils.h> 24#include <aiutils.h>
@@ -3139,20 +3140,6 @@ void brcms_c_reset(struct brcms_c_info *wlc)
3139 brcms_b_reset(wlc->hw); 3140 brcms_b_reset(wlc->hw);
3140} 3141}
3141 3142
3142/* Return the channel the driver should initialize during brcms_c_init.
3143 * the channel may have to be changed from the currently configured channel
3144 * if other configurations are in conflict (bandlocked, 11n mode disabled,
3145 * invalid channel for current country, etc.)
3146 */
3147static u16 brcms_c_init_chanspec(struct brcms_c_info *wlc)
3148{
3149 u16 chanspec =
3150 1 | WL_CHANSPEC_BW_20 | WL_CHANSPEC_CTL_SB_NONE |
3151 WL_CHANSPEC_BAND_2G;
3152
3153 return chanspec;
3154}
3155
3156void brcms_c_init_scb(struct scb *scb) 3143void brcms_c_init_scb(struct scb *scb)
3157{ 3144{
3158 int i; 3145 int i;
@@ -5129,6 +5116,8 @@ static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
5129/* make interface operational */ 5116/* make interface operational */
5130int brcms_c_up(struct brcms_c_info *wlc) 5117int brcms_c_up(struct brcms_c_info *wlc)
5131{ 5118{
5119 struct ieee80211_channel *ch;
5120
5132 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 5121 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
5133 5122
5134 /* HW is turned off so don't try to access it */ 5123 /* HW is turned off so don't try to access it */
@@ -5195,8 +5184,9 @@ int brcms_c_up(struct brcms_c_info *wlc)
5195 wlc->pub->up = true; 5184 wlc->pub->up = true;
5196 5185
5197 if (wlc->bandinit_pending) { 5186 if (wlc->bandinit_pending) {
5187 ch = wlc->pub->ieee_hw->conf.channel;
5198 brcms_c_suspend_mac_and_wait(wlc); 5188 brcms_c_suspend_mac_and_wait(wlc);
5199 brcms_c_set_chanspec(wlc, wlc->default_bss->chanspec); 5189 brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value));
5200 wlc->bandinit_pending = false; 5190 wlc->bandinit_pending = false;
5201 brcms_c_enable_mac(wlc); 5191 brcms_c_enable_mac(wlc);
5202 } 5192 }
@@ -5397,11 +5387,6 @@ int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
5397 else 5387 else
5398 return -EINVAL; 5388 return -EINVAL;
5399 5389
5400 /* Legacy or bust when no OFDM is supported by regulatory */
5401 if ((brcms_c_channel_locale_flags_in_band(wlc->cmi, band->bandunit) &
5402 BRCMS_NO_OFDM) && (gmode != GMODE_LEGACY_B))
5403 return -EINVAL;
5404
5405 /* update configuration value */ 5390 /* update configuration value */
5406 if (config) 5391 if (config)
5407 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode); 5392 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
@@ -8201,19 +8186,12 @@ bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
8201void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx) 8186void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
8202{ 8187{
8203 struct bcma_device *core = wlc->hw->d11core; 8188 struct bcma_device *core = wlc->hw->d11core;
8189 struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.channel;
8204 u16 chanspec; 8190 u16 chanspec;
8205 8191
8206 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 8192 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
8207 8193
8208 /* 8194 chanspec = ch20mhz_chspec(ch->hw_value);
8209 * This will happen if a big-hammer was executed. In
8210 * that case, we want to go back to the channel that
8211 * we were on and not new channel
8212 */
8213 if (wlc->pub->associated)
8214 chanspec = wlc->home_chanspec;
8215 else
8216 chanspec = brcms_c_init_chanspec(wlc);
8217 8195
8218 brcms_b_init(wlc->hw, chanspec); 8196 brcms_b_init(wlc->hw, chanspec);
8219 8197
diff --git a/drivers/net/wireless/brcm80211/include/brcm_hw_ids.h b/drivers/net/wireless/brcm80211/include/brcm_hw_ids.h
index 333193f20e1c..bcc79b4e3267 100644
--- a/drivers/net/wireless/brcm80211/include/brcm_hw_ids.h
+++ b/drivers/net/wireless/brcm80211/include/brcm_hw_ids.h
@@ -37,5 +37,6 @@
37#define BCM4329_CHIP_ID 0x4329 37#define BCM4329_CHIP_ID 0x4329
38#define BCM4330_CHIP_ID 0x4330 38#define BCM4330_CHIP_ID 0x4330
39#define BCM4331_CHIP_ID 0x4331 39#define BCM4331_CHIP_ID 0x4331
40#define BCM4334_CHIP_ID 0x4334
40 41
41#endif /* _BRCM_HW_IDS_H_ */ 42#endif /* _BRCM_HW_IDS_H_ */
diff --git a/drivers/net/wireless/iwlegacy/common.c b/drivers/net/wireless/iwlegacy/common.c
index cbf2dc18341f..763c7529921b 100644
--- a/drivers/net/wireless/iwlegacy/common.c
+++ b/drivers/net/wireless/iwlegacy/common.c
@@ -4717,10 +4717,11 @@ il_check_stuck_queue(struct il_priv *il, int cnt)
4717 struct il_tx_queue *txq = &il->txq[cnt]; 4717 struct il_tx_queue *txq = &il->txq[cnt];
4718 struct il_queue *q = &txq->q; 4718 struct il_queue *q = &txq->q;
4719 unsigned long timeout; 4719 unsigned long timeout;
4720 unsigned long now = jiffies;
4720 int ret; 4721 int ret;
4721 4722
4722 if (q->read_ptr == q->write_ptr) { 4723 if (q->read_ptr == q->write_ptr) {
4723 txq->time_stamp = jiffies; 4724 txq->time_stamp = now;
4724 return 0; 4725 return 0;
4725 } 4726 }
4726 4727
@@ -4728,9 +4729,9 @@ il_check_stuck_queue(struct il_priv *il, int cnt)
4728 txq->time_stamp + 4729 txq->time_stamp +
4729 msecs_to_jiffies(il->cfg->wd_timeout); 4730 msecs_to_jiffies(il->cfg->wd_timeout);
4730 4731
4731 if (time_after(jiffies, timeout)) { 4732 if (time_after(now, timeout)) {
4732 IL_ERR("Queue %d stuck for %u ms.\n", q->id, 4733 IL_ERR("Queue %d stuck for %u ms.\n", q->id,
4733 il->cfg->wd_timeout); 4734 jiffies_to_msecs(now - txq->time_stamp));
4734 ret = il_force_reset(il, false); 4735 ret = il_force_reset(il, false);
4735 return (ret == -EAGAIN) ? 0 : 1; 4736 return (ret == -EAGAIN) ? 0 : 1;
4736 } 4737 }
diff --git a/drivers/net/wireless/iwlwifi/dvm/agn.h b/drivers/net/wireless/iwlwifi/dvm/agn.h
index 6d102413dd94..9bb16bdf6d26 100644
--- a/drivers/net/wireless/iwlwifi/dvm/agn.h
+++ b/drivers/net/wireless/iwlwifi/dvm/agn.h
@@ -269,7 +269,7 @@ void iwl_scan_offchannel_skb_status(struct iwl_priv *priv);
269#define IWL_ACTIVE_QUIET_TIME cpu_to_le16(10) /* msec */ 269#define IWL_ACTIVE_QUIET_TIME cpu_to_le16(10) /* msec */
270#define IWL_PLCP_QUIET_THRESH cpu_to_le16(1) /* packets */ 270#define IWL_PLCP_QUIET_THRESH cpu_to_le16(1) /* packets */
271 271
272#define IWL_SCAN_CHECK_WATCHDOG (HZ * 7) 272#define IWL_SCAN_CHECK_WATCHDOG (HZ * 15)
273 273
274 274
275/* bt coex */ 275/* bt coex */
diff --git a/drivers/net/wireless/iwlwifi/dvm/dev.h b/drivers/net/wireless/iwlwifi/dvm/dev.h
index 4620b657948a..54cf085ddc89 100644
--- a/drivers/net/wireless/iwlwifi/dvm/dev.h
+++ b/drivers/net/wireless/iwlwifi/dvm/dev.h
@@ -568,7 +568,6 @@ enum iwl_scan_type {
568 * 568 *
569 * @tx_chains_num: Number of TX chains 569 * @tx_chains_num: Number of TX chains
570 * @rx_chains_num: Number of RX chains 570 * @rx_chains_num: Number of RX chains
571 * @sku: sku read from EEPROM
572 * @ct_kill_threshold: temperature threshold - in hw dependent unit 571 * @ct_kill_threshold: temperature threshold - in hw dependent unit
573 * @ct_kill_exit_threshold: when to reeable the device - in hw dependent unit 572 * @ct_kill_exit_threshold: when to reeable the device - in hw dependent unit
574 * relevant for 1000, 6000 and up 573 * relevant for 1000, 6000 and up
@@ -579,7 +578,6 @@ struct iwl_hw_params {
579 u8 tx_chains_num; 578 u8 tx_chains_num;
580 u8 rx_chains_num; 579 u8 rx_chains_num;
581 bool use_rts_for_aggregation; 580 bool use_rts_for_aggregation;
582 u16 sku;
583 u32 ct_kill_threshold; 581 u32 ct_kill_threshold;
584 u32 ct_kill_exit_threshold; 582 u32 ct_kill_exit_threshold;
585 583
diff --git a/drivers/net/wireless/iwlwifi/dvm/devices.c b/drivers/net/wireless/iwlwifi/dvm/devices.c
index 0521a6be09d2..349c205d5f62 100644
--- a/drivers/net/wireless/iwlwifi/dvm/devices.c
+++ b/drivers/net/wireless/iwlwifi/dvm/devices.c
@@ -250,17 +250,6 @@ struct iwl_lib_ops iwl2030_lib = {
250 */ 250 */
251 251
252/* NIC configuration for 5000 series */ 252/* NIC configuration for 5000 series */
253static void iwl5000_nic_config(struct iwl_priv *priv)
254{
255 /* W/A : NIC is stuck in a reset state after Early PCIe power off
256 * (PCIe power is lost before PERST# is asserted),
257 * causing ME FW to lose ownership and not being able to obtain it back.
258 */
259 iwl_set_bits_mask_prph(priv->trans, APMG_PS_CTRL_REG,
260 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
261 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
262}
263
264static const struct iwl_sensitivity_ranges iwl5000_sensitivity = { 253static const struct iwl_sensitivity_ranges iwl5000_sensitivity = {
265 .min_nrg_cck = 100, 254 .min_nrg_cck = 100,
266 .auto_corr_min_ofdm = 90, 255 .auto_corr_min_ofdm = 90,
@@ -433,14 +422,12 @@ static int iwl5000_hw_channel_switch(struct iwl_priv *priv,
433struct iwl_lib_ops iwl5000_lib = { 422struct iwl_lib_ops iwl5000_lib = {
434 .set_hw_params = iwl5000_hw_set_hw_params, 423 .set_hw_params = iwl5000_hw_set_hw_params,
435 .set_channel_switch = iwl5000_hw_channel_switch, 424 .set_channel_switch = iwl5000_hw_channel_switch,
436 .nic_config = iwl5000_nic_config,
437 .temperature = iwlagn_temperature, 425 .temperature = iwlagn_temperature,
438}; 426};
439 427
440struct iwl_lib_ops iwl5150_lib = { 428struct iwl_lib_ops iwl5150_lib = {
441 .set_hw_params = iwl5150_hw_set_hw_params, 429 .set_hw_params = iwl5150_hw_set_hw_params,
442 .set_channel_switch = iwl5000_hw_channel_switch, 430 .set_channel_switch = iwl5000_hw_channel_switch,
443 .nic_config = iwl5000_nic_config,
444 .temperature = iwl5150_temperature, 431 .temperature = iwl5150_temperature,
445}; 432};
446 433
diff --git a/drivers/net/wireless/iwlwifi/dvm/lib.c b/drivers/net/wireless/iwlwifi/dvm/lib.c
index 76f259283c3a..207ae91a83aa 100644
--- a/drivers/net/wireless/iwlwifi/dvm/lib.c
+++ b/drivers/net/wireless/iwlwifi/dvm/lib.c
@@ -160,7 +160,7 @@ int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
160 IWL_PAN_SCD_BK_MSK | IWL_PAN_SCD_MGMT_MSK | 160 IWL_PAN_SCD_BK_MSK | IWL_PAN_SCD_MGMT_MSK |
161 IWL_PAN_SCD_MULTICAST_MSK; 161 IWL_PAN_SCD_MULTICAST_MSK;
162 162
163 if (priv->hw_params.sku & EEPROM_SKU_CAP_11N_ENABLE) 163 if (priv->eeprom_data->sku & EEPROM_SKU_CAP_11N_ENABLE)
164 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK; 164 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
165 165
166 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n", 166 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
diff --git a/drivers/net/wireless/iwlwifi/dvm/mac80211.c b/drivers/net/wireless/iwlwifi/dvm/mac80211.c
index 2f10346c6ba1..a5f7bce96325 100644
--- a/drivers/net/wireless/iwlwifi/dvm/mac80211.c
+++ b/drivers/net/wireless/iwlwifi/dvm/mac80211.c
@@ -164,7 +164,7 @@ int iwlagn_mac_setup_register(struct iwl_priv *priv,
164 hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF; 164 hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
165 */ 165 */
166 166
167 if (priv->hw_params.sku & EEPROM_SKU_CAP_11N_ENABLE) 167 if (priv->eeprom_data->sku & EEPROM_SKU_CAP_11N_ENABLE)
168 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS | 168 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
169 IEEE80211_HW_SUPPORTS_STATIC_SMPS; 169 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
170 170
@@ -649,7 +649,7 @@ static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
649 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n", 649 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
650 sta->addr, tid); 650 sta->addr, tid);
651 651
652 if (!(priv->hw_params.sku & EEPROM_SKU_CAP_11N_ENABLE)) 652 if (!(priv->eeprom_data->sku & EEPROM_SKU_CAP_11N_ENABLE))
653 return -EACCES; 653 return -EACCES;
654 654
655 IWL_DEBUG_MAC80211(priv, "enter\n"); 655 IWL_DEBUG_MAC80211(priv, "enter\n");
@@ -1048,8 +1048,18 @@ static int iwlagn_mac_remain_on_channel(struct ieee80211_hw *hw,
1048 mutex_lock(&priv->mutex); 1048 mutex_lock(&priv->mutex);
1049 1049
1050 if (test_bit(STATUS_SCAN_HW, &priv->status)) { 1050 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
1051 err = -EBUSY; 1051 /* mac80211 should not scan while ROC or ROC while scanning */
1052 goto out; 1052 if (WARN_ON_ONCE(priv->scan_type != IWL_SCAN_RADIO_RESET)) {
1053 err = -EBUSY;
1054 goto out;
1055 }
1056
1057 iwl_scan_cancel_timeout(priv, 100);
1058
1059 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
1060 err = -EBUSY;
1061 goto out;
1062 }
1053 } 1063 }
1054 1064
1055 priv->hw_roc_channel = channel; 1065 priv->hw_roc_channel = channel;
@@ -1413,13 +1423,11 @@ static void iwlagn_mac_remove_interface(struct ieee80211_hw *hw,
1413} 1423}
1414 1424
1415static int iwlagn_mac_change_interface(struct ieee80211_hw *hw, 1425static int iwlagn_mac_change_interface(struct ieee80211_hw *hw,
1416 struct ieee80211_vif *vif, 1426 struct ieee80211_vif *vif,
1417 enum nl80211_iftype newtype, bool newp2p) 1427 enum nl80211_iftype newtype, bool newp2p)
1418{ 1428{
1419 struct iwl_priv *priv = IWL_MAC80211_GET_DVM(hw); 1429 struct iwl_priv *priv = IWL_MAC80211_GET_DVM(hw);
1420 struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif); 1430 struct iwl_rxon_context *ctx, *tmp;
1421 struct iwl_rxon_context *bss_ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1422 struct iwl_rxon_context *tmp;
1423 enum nl80211_iftype newviftype = newtype; 1431 enum nl80211_iftype newviftype = newtype;
1424 u32 interface_modes; 1432 u32 interface_modes;
1425 int err; 1433 int err;
@@ -1430,6 +1438,18 @@ static int iwlagn_mac_change_interface(struct ieee80211_hw *hw,
1430 1438
1431 mutex_lock(&priv->mutex); 1439 mutex_lock(&priv->mutex);
1432 1440
1441 ctx = iwl_rxon_ctx_from_vif(vif);
1442
1443 /*
1444 * To simplify this code, only support changes on the
1445 * BSS context. The PAN context is usually reassigned
1446 * by creating/removing P2P interfaces anyway.
1447 */
1448 if (ctx->ctxid != IWL_RXON_CTX_BSS) {
1449 err = -EBUSY;
1450 goto out;
1451 }
1452
1433 if (!ctx->vif || !iwl_is_ready_rf(priv)) { 1453 if (!ctx->vif || !iwl_is_ready_rf(priv)) {
1434 /* 1454 /*
1435 * Huh? But wait ... this can maybe happen when 1455 * Huh? But wait ... this can maybe happen when
@@ -1439,32 +1459,19 @@ static int iwlagn_mac_change_interface(struct ieee80211_hw *hw,
1439 goto out; 1459 goto out;
1440 } 1460 }
1441 1461
1462 /* Check if the switch is supported in the same context */
1442 interface_modes = ctx->interface_modes | ctx->exclusive_interface_modes; 1463 interface_modes = ctx->interface_modes | ctx->exclusive_interface_modes;
1443
1444 if (!(interface_modes & BIT(newtype))) { 1464 if (!(interface_modes & BIT(newtype))) {
1445 err = -EBUSY; 1465 err = -EBUSY;
1446 goto out; 1466 goto out;
1447 } 1467 }
1448 1468
1449 /*
1450 * Refuse a change that should be done by moving from the PAN
1451 * context to the BSS context instead, if the BSS context is
1452 * available and can support the new interface type.
1453 */
1454 if (ctx->ctxid == IWL_RXON_CTX_PAN && !bss_ctx->vif &&
1455 (bss_ctx->interface_modes & BIT(newtype) ||
1456 bss_ctx->exclusive_interface_modes & BIT(newtype))) {
1457 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
1458 err = -EBUSY;
1459 goto out;
1460 }
1461
1462 if (ctx->exclusive_interface_modes & BIT(newtype)) { 1469 if (ctx->exclusive_interface_modes & BIT(newtype)) {
1463 for_each_context(priv, tmp) { 1470 for_each_context(priv, tmp) {
1464 if (ctx == tmp) 1471 if (ctx == tmp)
1465 continue; 1472 continue;
1466 1473
1467 if (!tmp->vif) 1474 if (!tmp->is_active)
1468 continue; 1475 continue;
1469 1476
1470 /* 1477 /*
diff --git a/drivers/net/wireless/iwlwifi/dvm/main.c b/drivers/net/wireless/iwlwifi/dvm/main.c
index e620af3d592d..abfd7916bde6 100644
--- a/drivers/net/wireless/iwlwifi/dvm/main.c
+++ b/drivers/net/wireless/iwlwifi/dvm/main.c
@@ -51,11 +51,13 @@
51#include "iwl-op-mode.h" 51#include "iwl-op-mode.h"
52#include "iwl-drv.h" 52#include "iwl-drv.h"
53#include "iwl-modparams.h" 53#include "iwl-modparams.h"
54#include "iwl-prph.h"
54 55
55#include "dev.h" 56#include "dev.h"
56#include "calib.h" 57#include "calib.h"
57#include "agn.h" 58#include "agn.h"
58 59
60
59/****************************************************************************** 61/******************************************************************************
60 * 62 *
61 * module boiler plate 63 * module boiler plate
@@ -1185,9 +1187,6 @@ static void iwl_set_hw_params(struct iwl_priv *priv)
1185 priv->hw_params.use_rts_for_aggregation = 1187 priv->hw_params.use_rts_for_aggregation =
1186 priv->cfg->ht_params->use_rts_for_aggregation; 1188 priv->cfg->ht_params->use_rts_for_aggregation;
1187 1189
1188 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
1189 priv->hw_params.sku &= ~EEPROM_SKU_CAP_11N_ENABLE;
1190
1191 /* Device-specific setup */ 1190 /* Device-specific setup */
1192 priv->lib->set_hw_params(priv); 1191 priv->lib->set_hw_params(priv);
1193} 1192}
@@ -1232,20 +1231,20 @@ static int iwl_eeprom_init_hw_params(struct iwl_priv *priv)
1232{ 1231{
1233 u16 radio_cfg; 1232 u16 radio_cfg;
1234 1233
1235 priv->hw_params.sku = priv->eeprom_data->sku; 1234 priv->eeprom_data->sku = priv->eeprom_data->sku;
1236 1235
1237 if (priv->hw_params.sku & EEPROM_SKU_CAP_11N_ENABLE && 1236 if (priv->eeprom_data->sku & EEPROM_SKU_CAP_11N_ENABLE &&
1238 !priv->cfg->ht_params) { 1237 !priv->cfg->ht_params) {
1239 IWL_ERR(priv, "Invalid 11n configuration\n"); 1238 IWL_ERR(priv, "Invalid 11n configuration\n");
1240 return -EINVAL; 1239 return -EINVAL;
1241 } 1240 }
1242 1241
1243 if (!priv->hw_params.sku) { 1242 if (!priv->eeprom_data->sku) {
1244 IWL_ERR(priv, "Invalid device sku\n"); 1243 IWL_ERR(priv, "Invalid device sku\n");
1245 return -EINVAL; 1244 return -EINVAL;
1246 } 1245 }
1247 1246
1248 IWL_INFO(priv, "Device SKU: 0x%X\n", priv->hw_params.sku); 1247 IWL_INFO(priv, "Device SKU: 0x%X\n", priv->eeprom_data->sku);
1249 1248
1250 radio_cfg = priv->eeprom_data->radio_cfg; 1249 radio_cfg = priv->eeprom_data->radio_cfg;
1251 1250
@@ -1352,6 +1351,9 @@ static struct iwl_op_mode *iwl_op_mode_dvm_start(struct iwl_trans *trans,
1352 trans_cfg.queue_watchdog_timeout = IWL_WATCHDOG_DISABLED; 1351 trans_cfg.queue_watchdog_timeout = IWL_WATCHDOG_DISABLED;
1353 trans_cfg.command_names = iwl_dvm_cmd_strings; 1352 trans_cfg.command_names = iwl_dvm_cmd_strings;
1354 1353
1354 WARN_ON(sizeof(priv->transport_queue_stop) * BITS_PER_BYTE <
1355 priv->cfg->base_params->num_of_queues);
1356
1355 ucode_flags = fw->ucode_capa.flags; 1357 ucode_flags = fw->ucode_capa.flags;
1356 1358
1357#ifndef CONFIG_IWLWIFI_P2P 1359#ifndef CONFIG_IWLWIFI_P2P
@@ -1448,7 +1450,7 @@ static struct iwl_op_mode *iwl_op_mode_dvm_start(struct iwl_trans *trans,
1448 ************************/ 1450 ************************/
1449 iwl_set_hw_params(priv); 1451 iwl_set_hw_params(priv);
1450 1452
1451 if (!(priv->hw_params.sku & EEPROM_SKU_CAP_IPAN_ENABLE)) { 1453 if (!(priv->eeprom_data->sku & EEPROM_SKU_CAP_IPAN_ENABLE)) {
1452 IWL_DEBUG_INFO(priv, "Your EEPROM disabled PAN"); 1454 IWL_DEBUG_INFO(priv, "Your EEPROM disabled PAN");
1453 ucode_flags &= ~IWL_UCODE_TLV_FLAGS_PAN; 1455 ucode_flags &= ~IWL_UCODE_TLV_FLAGS_PAN;
1454 /* 1456 /*
@@ -2073,7 +2075,16 @@ static void iwl_nic_config(struct iwl_op_mode *op_mode)
2073 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 2075 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
2074 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 2076 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
2075 2077
2076 priv->lib->nic_config(priv); 2078 /* W/A : NIC is stuck in a reset state after Early PCIe power off
2079 * (PCIe power is lost before PERST# is asserted),
2080 * causing ME FW to lose ownership and not being able to obtain it back.
2081 */
2082 iwl_set_bits_mask_prph(priv->trans, APMG_PS_CTRL_REG,
2083 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
2084 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
2085
2086 if (priv->lib->nic_config)
2087 priv->lib->nic_config(priv);
2077} 2088}
2078 2089
2079static void iwl_wimax_active(struct iwl_op_mode *op_mode) 2090static void iwl_wimax_active(struct iwl_op_mode *op_mode)
diff --git a/drivers/net/wireless/iwlwifi/dvm/scan.c b/drivers/net/wireless/iwlwifi/dvm/scan.c
index 2f271c96ed39..6633074258c7 100644
--- a/drivers/net/wireless/iwlwifi/dvm/scan.c
+++ b/drivers/net/wireless/iwlwifi/dvm/scan.c
@@ -51,6 +51,9 @@
51#define IWL_CHANNEL_TUNE_TIME 5 51#define IWL_CHANNEL_TUNE_TIME 5
52#define MAX_SCAN_CHANNEL 50 52#define MAX_SCAN_CHANNEL 50
53 53
54/* For reset radio, need minimal dwell time only */
55#define IWL_RADIO_RESET_DWELL_TIME 5
56
54static int iwl_send_scan_abort(struct iwl_priv *priv) 57static int iwl_send_scan_abort(struct iwl_priv *priv)
55{ 58{
56 int ret; 59 int ret;
@@ -469,45 +472,39 @@ static u8 iwl_get_single_channel_number(struct iwl_priv *priv,
469 return 0; 472 return 0;
470} 473}
471 474
472static int iwl_get_single_channel_for_scan(struct iwl_priv *priv, 475static int iwl_get_channel_for_reset_scan(struct iwl_priv *priv,
473 struct ieee80211_vif *vif, 476 struct ieee80211_vif *vif,
474 enum ieee80211_band band, 477 enum ieee80211_band band,
475 struct iwl_scan_channel *scan_ch) 478 struct iwl_scan_channel *scan_ch)
476{ 479{
477 const struct ieee80211_supported_band *sband; 480 const struct ieee80211_supported_band *sband;
478 u16 passive_dwell = 0; 481 u16 channel;
479 u16 active_dwell = 0;
480 int added = 0;
481 u16 channel = 0;
482 482
483 sband = iwl_get_hw_mode(priv, band); 483 sband = iwl_get_hw_mode(priv, band);
484 if (!sband) { 484 if (!sband) {
485 IWL_ERR(priv, "invalid band\n"); 485 IWL_ERR(priv, "invalid band\n");
486 return added; 486 return 0;
487 } 487 }
488 488
489 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
490 passive_dwell = iwl_get_passive_dwell_time(priv, band);
491
492 if (passive_dwell <= active_dwell)
493 passive_dwell = active_dwell + 1;
494
495 channel = iwl_get_single_channel_number(priv, band); 489 channel = iwl_get_single_channel_number(priv, band);
496 if (channel) { 490 if (channel) {
497 scan_ch->channel = cpu_to_le16(channel); 491 scan_ch->channel = cpu_to_le16(channel);
498 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE; 492 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
499 scan_ch->active_dwell = cpu_to_le16(active_dwell); 493 scan_ch->active_dwell =
500 scan_ch->passive_dwell = cpu_to_le16(passive_dwell); 494 cpu_to_le16(IWL_RADIO_RESET_DWELL_TIME);
495 scan_ch->passive_dwell =
496 cpu_to_le16(IWL_RADIO_RESET_DWELL_TIME);
501 /* Set txpower levels to defaults */ 497 /* Set txpower levels to defaults */
502 scan_ch->dsp_atten = 110; 498 scan_ch->dsp_atten = 110;
503 if (band == IEEE80211_BAND_5GHZ) 499 if (band == IEEE80211_BAND_5GHZ)
504 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3; 500 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
505 else 501 else
506 scan_ch->tx_gain = ((1 << 5) | (5 << 3)); 502 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
507 added++; 503 return 1;
508 } else 504 }
509 IWL_ERR(priv, "no valid channel found\n"); 505
510 return added; 506 IWL_ERR(priv, "no valid channel found\n");
507 return 0;
511} 508}
512 509
513static int iwl_get_channels_for_scan(struct iwl_priv *priv, 510static int iwl_get_channels_for_scan(struct iwl_priv *priv,
@@ -723,6 +720,12 @@ static int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
723 switch (priv->scan_type) { 720 switch (priv->scan_type) {
724 case IWL_SCAN_RADIO_RESET: 721 case IWL_SCAN_RADIO_RESET:
725 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n"); 722 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
723 /*
724 * Override quiet time as firmware checks that active
725 * dwell is >= quiet; since we use passive scan it'll
726 * not actually be used.
727 */
728 scan->quiet_time = cpu_to_le16(IWL_RADIO_RESET_DWELL_TIME);
726 break; 729 break;
727 case IWL_SCAN_NORMAL: 730 case IWL_SCAN_NORMAL:
728 if (priv->scan_request->n_ssids) { 731 if (priv->scan_request->n_ssids) {
@@ -896,7 +899,7 @@ static int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
896 switch (priv->scan_type) { 899 switch (priv->scan_type) {
897 case IWL_SCAN_RADIO_RESET: 900 case IWL_SCAN_RADIO_RESET:
898 scan->channel_count = 901 scan->channel_count =
899 iwl_get_single_channel_for_scan(priv, vif, band, 902 iwl_get_channel_for_reset_scan(priv, vif, band,
900 (void *)&scan->data[cmd_len]); 903 (void *)&scan->data[cmd_len]);
901 break; 904 break;
902 case IWL_SCAN_NORMAL: 905 case IWL_SCAN_NORMAL:
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom-parse.c b/drivers/net/wireless/iwlwifi/iwl-eeprom-parse.c
index c87a05cbec12..f10170fe8799 100644
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom-parse.c
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom-parse.c
@@ -853,6 +853,9 @@ iwl_parse_eeprom_data(struct device *dev, const struct iwl_cfg *cfg,
853 EEPROM_RADIO_CONFIG); 853 EEPROM_RADIO_CONFIG);
854 data->sku = iwl_eeprom_query16(eeprom, eeprom_size, 854 data->sku = iwl_eeprom_query16(eeprom, eeprom_size,
855 EEPROM_SKU_CAP); 855 EEPROM_SKU_CAP);
856 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
857 data->sku &= ~EEPROM_SKU_CAP_11N_ENABLE;
858
856 data->eeprom_version = iwl_eeprom_query16(eeprom, eeprom_size, 859 data->eeprom_version = iwl_eeprom_query16(eeprom, eeprom_size,
857 EEPROM_VERSION); 860 EEPROM_VERSION);
858 861
diff --git a/drivers/net/wireless/iwlwifi/iwl-notif-wait.c b/drivers/net/wireless/iwlwifi/iwl-notif-wait.c
index 5cfed29b1b18..c61f2070f15a 100644
--- a/drivers/net/wireless/iwlwifi/iwl-notif-wait.c
+++ b/drivers/net/wireless/iwlwifi/iwl-notif-wait.c
@@ -121,13 +121,12 @@ EXPORT_SYMBOL_GPL(iwl_notification_wait_notify);
121 121
122void iwl_abort_notification_waits(struct iwl_notif_wait_data *notif_wait) 122void iwl_abort_notification_waits(struct iwl_notif_wait_data *notif_wait)
123{ 123{
124 unsigned long flags;
125 struct iwl_notification_wait *wait_entry; 124 struct iwl_notification_wait *wait_entry;
126 125
127 spin_lock_irqsave(&notif_wait->notif_wait_lock, flags); 126 spin_lock(&notif_wait->notif_wait_lock);
128 list_for_each_entry(wait_entry, &notif_wait->notif_waits, list) 127 list_for_each_entry(wait_entry, &notif_wait->notif_waits, list)
129 wait_entry->aborted = true; 128 wait_entry->aborted = true;
130 spin_unlock_irqrestore(&notif_wait->notif_wait_lock, flags); 129 spin_unlock(&notif_wait->notif_wait_lock);
131 130
132 wake_up_all(&notif_wait->notif_waitq); 131 wake_up_all(&notif_wait->notif_waitq);
133} 132}
diff --git a/drivers/net/wireless/iwlwifi/iwl-op-mode.h b/drivers/net/wireless/iwlwifi/iwl-op-mode.h
index cd9ef114d3a3..64886f95664f 100644
--- a/drivers/net/wireless/iwlwifi/iwl-op-mode.h
+++ b/drivers/net/wireless/iwlwifi/iwl-op-mode.h
@@ -111,22 +111,25 @@ struct iwl_cfg;
111 * May sleep 111 * May sleep
112 * @rx: Rx notification to the op_mode. rxb is the Rx buffer itself. Cmd is the 112 * @rx: Rx notification to the op_mode. rxb is the Rx buffer itself. Cmd is the
113 * HCMD the this Rx responds to. 113 * HCMD the this Rx responds to.
114 * Must be atomic. 114 * Must be atomic and called with BH disabled.
115 * @queue_full: notifies that a HW queue is full. 115 * @queue_full: notifies that a HW queue is full.
116 * Must be atomic 116 * Must be atomic and called with BH disabled.
117 * @queue_not_full: notifies that a HW queue is not full any more. 117 * @queue_not_full: notifies that a HW queue is not full any more.
118 * Must be atomic 118 * Must be atomic and called with BH disabled.
119 * @hw_rf_kill:notifies of a change in the HW rf kill switch. True means that 119 * @hw_rf_kill:notifies of a change in the HW rf kill switch. True means that
120 * the radio is killed. Must be atomic. 120 * the radio is killed. Must be atomic.
121 * @free_skb: allows the transport layer to free skbs that haven't been 121 * @free_skb: allows the transport layer to free skbs that haven't been
122 * reclaimed by the op_mode. This can happen when the driver is freed and 122 * reclaimed by the op_mode. This can happen when the driver is freed and
123 * there are Tx packets pending in the transport layer. 123 * there are Tx packets pending in the transport layer.
124 * Must be atomic 124 * Must be atomic
125 * @nic_error: error notification. Must be atomic 125 * @nic_error: error notification. Must be atomic and must be called with BH
126 * @cmd_queue_full: Called when the command queue gets full. Must be atomic. 126 * disabled.
127 * @cmd_queue_full: Called when the command queue gets full. Must be atomic and
128 * called with BH disabled.
127 * @nic_config: configure NIC, called before firmware is started. 129 * @nic_config: configure NIC, called before firmware is started.
128 * May sleep 130 * May sleep
129 * @wimax_active: invoked when WiMax becomes active. Must be atomic. 131 * @wimax_active: invoked when WiMax becomes active. Must be atomic and called
132 * with BH disabled.
130 */ 133 */
131struct iwl_op_mode_ops { 134struct iwl_op_mode_ops {
132 struct iwl_op_mode *(*start)(struct iwl_trans *trans, 135 struct iwl_op_mode *(*start)(struct iwl_trans *trans,
@@ -165,7 +168,6 @@ struct iwl_op_mode {
165static inline void iwl_op_mode_stop(struct iwl_op_mode *op_mode) 168static inline void iwl_op_mode_stop(struct iwl_op_mode *op_mode)
166{ 169{
167 might_sleep(); 170 might_sleep();
168
169 op_mode->ops->stop(op_mode); 171 op_mode->ops->stop(op_mode);
170} 172}
171 173
diff --git a/drivers/net/wireless/iwlwifi/pcie/rx.c b/drivers/net/wireless/iwlwifi/pcie/rx.c
index d6860c070c16..be143eb4aa4f 100644
--- a/drivers/net/wireless/iwlwifi/pcie/rx.c
+++ b/drivers/net/wireless/iwlwifi/pcie/rx.c
@@ -867,24 +867,23 @@ void iwl_disable_ict(struct iwl_trans *trans)
867 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); 867 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
868} 868}
869 869
870/* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */
870static irqreturn_t iwl_isr(int irq, void *data) 871static irqreturn_t iwl_isr(int irq, void *data)
871{ 872{
872 struct iwl_trans *trans = data; 873 struct iwl_trans *trans = data;
873 struct iwl_trans_pcie *trans_pcie; 874 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
874 u32 inta, inta_mask; 875 u32 inta, inta_mask;
875 unsigned long flags;
876#ifdef CONFIG_IWLWIFI_DEBUG 876#ifdef CONFIG_IWLWIFI_DEBUG
877 u32 inta_fh; 877 u32 inta_fh;
878#endif 878#endif
879
880 lockdep_assert_held(&trans_pcie->irq_lock);
881
879 if (!trans) 882 if (!trans)
880 return IRQ_NONE; 883 return IRQ_NONE;
881 884
882 trace_iwlwifi_dev_irq(trans->dev); 885 trace_iwlwifi_dev_irq(trans->dev);
883 886
884 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
885
886 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
887
888 /* Disable (but don't clear!) interrupts here to avoid 887 /* Disable (but don't clear!) interrupts here to avoid
889 * back-to-back ISRs and sporadic interrupts from our NIC. 888 * back-to-back ISRs and sporadic interrupts from our NIC.
890 * If we have something to service, the tasklet will re-enable ints. 889 * If we have something to service, the tasklet will re-enable ints.
@@ -907,7 +906,7 @@ static irqreturn_t iwl_isr(int irq, void *data)
907 /* Hardware disappeared. It might have already raised 906 /* Hardware disappeared. It might have already raised
908 * an interrupt */ 907 * an interrupt */
909 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 908 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
910 goto unplugged; 909 return IRQ_HANDLED;
911 } 910 }
912 911
913#ifdef CONFIG_IWLWIFI_DEBUG 912#ifdef CONFIG_IWLWIFI_DEBUG
@@ -926,18 +925,13 @@ static irqreturn_t iwl_isr(int irq, void *data)
926 !trans_pcie->inta) 925 !trans_pcie->inta)
927 iwl_enable_interrupts(trans); 926 iwl_enable_interrupts(trans);
928 927
929 unplugged: 928none:
930 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
931 return IRQ_HANDLED;
932
933 none:
934 /* re-enable interrupts here since we don't have anything to service. */ 929 /* re-enable interrupts here since we don't have anything to service. */
935 /* only Re-enable if disabled by irq and no schedules tasklet. */ 930 /* only Re-enable if disabled by irq and no schedules tasklet. */
936 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) && 931 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
937 !trans_pcie->inta) 932 !trans_pcie->inta)
938 iwl_enable_interrupts(trans); 933 iwl_enable_interrupts(trans);
939 934
940 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
941 return IRQ_NONE; 935 return IRQ_NONE;
942} 936}
943 937
@@ -963,15 +957,19 @@ irqreturn_t iwl_isr_ict(int irq, void *data)
963 957
964 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 958 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
965 959
960 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
961
966 /* dram interrupt table not set yet, 962 /* dram interrupt table not set yet,
967 * use legacy interrupt. 963 * use legacy interrupt.
968 */ 964 */
969 if (!trans_pcie->use_ict) 965 if (unlikely(!trans_pcie->use_ict)) {
970 return iwl_isr(irq, data); 966 irqreturn_t ret = iwl_isr(irq, data);
967 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
968 return ret;
969 }
971 970
972 trace_iwlwifi_dev_irq(trans->dev); 971 trace_iwlwifi_dev_irq(trans->dev);
973 972
974 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
975 973
976 /* Disable (but don't clear!) interrupts here to avoid 974 /* Disable (but don't clear!) interrupts here to avoid
977 * back-to-back ISRs and sporadic interrupts from our NIC. 975 * back-to-back ISRs and sporadic interrupts from our NIC.
diff --git a/drivers/net/wireless/iwlwifi/pcie/trans.c b/drivers/net/wireless/iwlwifi/pcie/trans.c
index 32ab8ea56135..d1950838f17f 100644
--- a/drivers/net/wireless/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/iwlwifi/pcie/trans.c
@@ -296,6 +296,7 @@ static void iwlagn_free_dma_ptr(struct iwl_trans *trans,
296static void iwl_trans_pcie_queue_stuck_timer(unsigned long data) 296static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
297{ 297{
298 struct iwl_tx_queue *txq = (void *)data; 298 struct iwl_tx_queue *txq = (void *)data;
299 struct iwl_queue *q = &txq->q;
299 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 300 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
300 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); 301 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
301 u32 scd_sram_addr = trans_pcie->scd_base_addr + 302 u32 scd_sram_addr = trans_pcie->scd_base_addr +
@@ -346,6 +347,14 @@ static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
346 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i))); 347 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
347 } 348 }
348 349
350 for (i = q->read_ptr; i != q->write_ptr;
351 i = iwl_queue_inc_wrap(i, q->n_bd)) {
352 struct iwl_tx_cmd *tx_cmd =
353 (struct iwl_tx_cmd *)txq->entries[i].cmd->payload;
354 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
355 get_unaligned_le32(&tx_cmd->scratch));
356 }
357
349 iwl_op_mode_nic_error(trans->op_mode); 358 iwl_op_mode_nic_error(trans->op_mode);
350} 359}
351 360
@@ -1037,15 +1046,12 @@ static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1037 1046
1038/* 1047/*
1039 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask 1048 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1040 * must be called under the irq lock and with MAC access
1041 */ 1049 */
1042static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask) 1050static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1043{ 1051{
1044 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1052 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1045 IWL_TRANS_GET_PCIE_TRANS(trans); 1053 IWL_TRANS_GET_PCIE_TRANS(trans);
1046 1054
1047 lockdep_assert_held(&trans_pcie->irq_lock);
1048
1049 iwl_write_prph(trans, SCD_TXFACT, mask); 1055 iwl_write_prph(trans, SCD_TXFACT, mask);
1050} 1056}
1051 1057
@@ -1053,12 +1059,9 @@ static void iwl_tx_start(struct iwl_trans *trans)
1053{ 1059{
1054 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1060 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1055 u32 a; 1061 u32 a;
1056 unsigned long flags;
1057 int i, chan; 1062 int i, chan;
1058 u32 reg_val; 1063 u32 reg_val;
1059 1064
1060 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1061
1062 /* make sure all queue are not stopped/used */ 1065 /* make sure all queue are not stopped/used */
1063 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 1066 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
1064 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 1067 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
@@ -1109,8 +1112,6 @@ static void iwl_tx_start(struct iwl_trans *trans)
1109 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, 1112 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1110 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 1113 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1111 1114
1112 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1113
1114 /* Enable L1-Active */ 1115 /* Enable L1-Active */
1115 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 1116 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1116 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 1117 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
@@ -2017,7 +2018,9 @@ static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
2017 if (!trans->op_mode) 2018 if (!trans->op_mode)
2018 return -EAGAIN; 2019 return -EAGAIN;
2019 2020
2021 local_bh_disable();
2020 iwl_op_mode_nic_error(trans->op_mode); 2022 iwl_op_mode_nic_error(trans->op_mode);
2023 local_bh_enable();
2021 2024
2022 return count; 2025 return count;
2023} 2026}
diff --git a/drivers/net/wireless/mac80211_hwsim.c b/drivers/net/wireless/mac80211_hwsim.c
index a9ba3f7ea62b..f578d0b2172d 100644
--- a/drivers/net/wireless/mac80211_hwsim.c
+++ b/drivers/net/wireless/mac80211_hwsim.c
@@ -678,8 +678,7 @@ static bool mac80211_hwsim_tx_frame_no_nl(struct ieee80211_hw *hw,
678 continue; 678 continue;
679 679
680 if (data2->idle || !data2->started || 680 if (data2->idle || !data2->started ||
681 !hwsim_ps_rx_ok(data2, skb) || 681 !hwsim_ps_rx_ok(data2, skb) || !data2->channel ||
682 !data->channel || !data2->channel ||
683 data->channel->center_freq != data2->channel->center_freq || 682 data->channel->center_freq != data2->channel->center_freq ||
684 !(data->group & data2->group)) 683 !(data->group & data2->group))
685 continue; 684 continue;
@@ -1486,7 +1485,7 @@ static int hwsim_tx_info_frame_received_nl(struct sk_buff *skb_2,
1486 struct mac80211_hwsim_data *data2; 1485 struct mac80211_hwsim_data *data2;
1487 struct ieee80211_tx_info *txi; 1486 struct ieee80211_tx_info *txi;
1488 struct hwsim_tx_rate *tx_attempts; 1487 struct hwsim_tx_rate *tx_attempts;
1489 struct sk_buff __user *ret_skb; 1488 unsigned long ret_skb_ptr;
1490 struct sk_buff *skb, *tmp; 1489 struct sk_buff *skb, *tmp;
1491 struct mac_address *src; 1490 struct mac_address *src;
1492 unsigned int hwsim_flags; 1491 unsigned int hwsim_flags;
@@ -1504,8 +1503,7 @@ static int hwsim_tx_info_frame_received_nl(struct sk_buff *skb_2,
1504 info->attrs[HWSIM_ATTR_ADDR_TRANSMITTER]); 1503 info->attrs[HWSIM_ATTR_ADDR_TRANSMITTER]);
1505 hwsim_flags = nla_get_u32(info->attrs[HWSIM_ATTR_FLAGS]); 1504 hwsim_flags = nla_get_u32(info->attrs[HWSIM_ATTR_FLAGS]);
1506 1505
1507 ret_skb = (struct sk_buff __user *) 1506 ret_skb_ptr = nla_get_u64(info->attrs[HWSIM_ATTR_COOKIE]);
1508 (unsigned long) nla_get_u64(info->attrs[HWSIM_ATTR_COOKIE]);
1509 1507
1510 data2 = get_hwsim_data_ref_from_addr(src); 1508 data2 = get_hwsim_data_ref_from_addr(src);
1511 1509
@@ -1514,7 +1512,7 @@ static int hwsim_tx_info_frame_received_nl(struct sk_buff *skb_2,
1514 1512
1515 /* look for the skb matching the cookie passed back from user */ 1513 /* look for the skb matching the cookie passed back from user */
1516 skb_queue_walk_safe(&data2->pending, skb, tmp) { 1514 skb_queue_walk_safe(&data2->pending, skb, tmp) {
1517 if (skb == ret_skb) { 1515 if ((unsigned long)skb == ret_skb_ptr) {
1518 skb_unlink(skb, &data2->pending); 1516 skb_unlink(skb, &data2->pending);
1519 found = true; 1517 found = true;
1520 break; 1518 break;
diff --git a/drivers/net/wireless/mwifiex/cfg80211.c b/drivers/net/wireless/mwifiex/cfg80211.c
index 80e9b2a39058..4b2733af1a0e 100644
--- a/drivers/net/wireless/mwifiex/cfg80211.c
+++ b/drivers/net/wireless/mwifiex/cfg80211.c
@@ -170,7 +170,9 @@ mwifiex_cfg80211_set_default_key(struct wiphy *wiphy, struct net_device *netdev,
170 if (!priv->sec_info.wep_enabled) 170 if (!priv->sec_info.wep_enabled)
171 return 0; 171 return 0;
172 172
173 if (mwifiex_set_encode(priv, NULL, 0, key_index, NULL, 0)) { 173 if (priv->bss_type == MWIFIEX_BSS_TYPE_UAP) {
174 priv->wep_key_curr_index = key_index;
175 } else if (mwifiex_set_encode(priv, NULL, 0, key_index, NULL, 0)) {
174 wiphy_err(wiphy, "set default Tx key index\n"); 176 wiphy_err(wiphy, "set default Tx key index\n");
175 return -EFAULT; 177 return -EFAULT;
176 } 178 }
@@ -187,9 +189,25 @@ mwifiex_cfg80211_add_key(struct wiphy *wiphy, struct net_device *netdev,
187 struct key_params *params) 189 struct key_params *params)
188{ 190{
189 struct mwifiex_private *priv = mwifiex_netdev_get_priv(netdev); 191 struct mwifiex_private *priv = mwifiex_netdev_get_priv(netdev);
192 struct mwifiex_wep_key *wep_key;
190 const u8 bc_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 193 const u8 bc_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
191 const u8 *peer_mac = pairwise ? mac_addr : bc_mac; 194 const u8 *peer_mac = pairwise ? mac_addr : bc_mac;
192 195
196 if (GET_BSS_ROLE(priv) == MWIFIEX_BSS_ROLE_UAP &&
197 (params->cipher == WLAN_CIPHER_SUITE_WEP40 ||
198 params->cipher == WLAN_CIPHER_SUITE_WEP104)) {
199 if (params->key && params->key_len) {
200 wep_key = &priv->wep_key[key_index];
201 memset(wep_key, 0, sizeof(struct mwifiex_wep_key));
202 memcpy(wep_key->key_material, params->key,
203 params->key_len);
204 wep_key->key_index = key_index;
205 wep_key->key_length = params->key_len;
206 priv->sec_info.wep_enabled = 1;
207 }
208 return 0;
209 }
210
193 if (mwifiex_set_encode(priv, params->key, params->key_len, 211 if (mwifiex_set_encode(priv, params->key, params->key_len,
194 key_index, peer_mac, 0)) { 212 key_index, peer_mac, 0)) {
195 wiphy_err(wiphy, "crypto keys added\n"); 213 wiphy_err(wiphy, "crypto keys added\n");
@@ -242,13 +260,13 @@ static int mwifiex_send_domain_info_cmd_fw(struct wiphy *wiphy)
242 flag = 1; 260 flag = 1;
243 first_chan = (u32) ch->hw_value; 261 first_chan = (u32) ch->hw_value;
244 next_chan = first_chan; 262 next_chan = first_chan;
245 max_pwr = ch->max_power; 263 max_pwr = ch->max_reg_power;
246 no_of_parsed_chan = 1; 264 no_of_parsed_chan = 1;
247 continue; 265 continue;
248 } 266 }
249 267
250 if (ch->hw_value == next_chan + 1 && 268 if (ch->hw_value == next_chan + 1 &&
251 ch->max_power == max_pwr) { 269 ch->max_reg_power == max_pwr) {
252 next_chan++; 270 next_chan++;
253 no_of_parsed_chan++; 271 no_of_parsed_chan++;
254 } else { 272 } else {
@@ -259,7 +277,7 @@ static int mwifiex_send_domain_info_cmd_fw(struct wiphy *wiphy)
259 no_of_triplet++; 277 no_of_triplet++;
260 first_chan = (u32) ch->hw_value; 278 first_chan = (u32) ch->hw_value;
261 next_chan = first_chan; 279 next_chan = first_chan;
262 max_pwr = ch->max_power; 280 max_pwr = ch->max_reg_power;
263 no_of_parsed_chan = 1; 281 no_of_parsed_chan = 1;
264 } 282 }
265 } 283 }
@@ -384,13 +402,13 @@ mwifiex_set_rf_channel(struct mwifiex_private *priv,
384 cfp.freq = chan->center_freq; 402 cfp.freq = chan->center_freq;
385 cfp.channel = ieee80211_frequency_to_channel(chan->center_freq); 403 cfp.channel = ieee80211_frequency_to_channel(chan->center_freq);
386 404
387 if (mwifiex_bss_set_channel(priv, &cfp)) 405 if (priv->bss_type == MWIFIEX_BSS_TYPE_STA) {
388 return -EFAULT; 406 if (mwifiex_bss_set_channel(priv, &cfp))
389 407 return -EFAULT;
390 if (priv->bss_type == MWIFIEX_BSS_TYPE_STA)
391 return mwifiex_drv_change_adhoc_chan(priv, cfp.channel); 408 return mwifiex_drv_change_adhoc_chan(priv, cfp.channel);
392 else 409 }
393 return mwifiex_uap_set_channel(priv, cfp.channel); 410
411 return 0;
394} 412}
395 413
396/* 414/*
@@ -961,12 +979,25 @@ static int mwifiex_cfg80211_start_ap(struct wiphy *wiphy,
961 return -EINVAL; 979 return -EINVAL;
962 } 980 }
963 981
982 bss_cfg->channel =
983 (u8)ieee80211_frequency_to_channel(params->channel->center_freq);
984 bss_cfg->band_cfg = BAND_CONFIG_MANUAL;
985
986 if (mwifiex_set_rf_channel(priv, params->channel,
987 params->channel_type)) {
988 kfree(bss_cfg);
989 wiphy_err(wiphy, "Failed to set band config information!\n");
990 return -1;
991 }
992
964 if (mwifiex_set_secure_params(priv, bss_cfg, params)) { 993 if (mwifiex_set_secure_params(priv, bss_cfg, params)) {
965 kfree(bss_cfg); 994 kfree(bss_cfg);
966 wiphy_err(wiphy, "Failed to parse secuirty parameters!\n"); 995 wiphy_err(wiphy, "Failed to parse secuirty parameters!\n");
967 return -1; 996 return -1;
968 } 997 }
969 998
999 mwifiex_set_ht_params(priv, bss_cfg, params);
1000
970 if (mwifiex_send_cmd_sync(priv, HostCmd_CMD_UAP_BSS_STOP, 1001 if (mwifiex_send_cmd_sync(priv, HostCmd_CMD_UAP_BSS_STOP,
971 HostCmd_ACT_GEN_SET, 0, NULL)) { 1002 HostCmd_ACT_GEN_SET, 0, NULL)) {
972 wiphy_err(wiphy, "Failed to stop the BSS\n"); 1003 wiphy_err(wiphy, "Failed to stop the BSS\n");
@@ -990,6 +1021,16 @@ static int mwifiex_cfg80211_start_ap(struct wiphy *wiphy,
990 return -1; 1021 return -1;
991 } 1022 }
992 1023
1024 if (priv->sec_info.wep_enabled)
1025 priv->curr_pkt_filter |= HostCmd_ACT_MAC_WEP_ENABLE;
1026 else
1027 priv->curr_pkt_filter &= ~HostCmd_ACT_MAC_WEP_ENABLE;
1028
1029 if (mwifiex_send_cmd_sync(priv, HostCmd_CMD_MAC_CONTROL,
1030 HostCmd_ACT_GEN_SET, 0,
1031 &priv->curr_pkt_filter))
1032 return -1;
1033
993 return 0; 1034 return 0;
994} 1035}
995 1036
@@ -1381,7 +1422,7 @@ mwifiex_cfg80211_scan(struct wiphy *wiphy, struct net_device *dev,
1381 1422
1382 priv->user_scan_cfg->chan_list[i].scan_time = 0; 1423 priv->user_scan_cfg->chan_list[i].scan_time = 0;
1383 } 1424 }
1384 if (mwifiex_set_user_scan_ioctl(priv, priv->user_scan_cfg)) 1425 if (mwifiex_scan_networks(priv, priv->user_scan_cfg))
1385 return -EFAULT; 1426 return -EFAULT;
1386 1427
1387 if (request->ie && request->ie_len) { 1428 if (request->ie && request->ie_len) {
@@ -1702,7 +1743,7 @@ int mwifiex_register_cfg80211(struct mwifiex_adapter *adapter)
1702 1743
1703 memcpy(wiphy->perm_addr, priv->curr_addr, ETH_ALEN); 1744 memcpy(wiphy->perm_addr, priv->curr_addr, ETH_ALEN);
1704 wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM; 1745 wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
1705 wiphy->flags |= WIPHY_FLAG_HAVE_AP_SME | WIPHY_FLAG_CUSTOM_REGULATORY; 1746 wiphy->flags |= WIPHY_FLAG_HAVE_AP_SME;
1706 1747
1707 /* Reserve space for mwifiex specific private data for BSS */ 1748 /* Reserve space for mwifiex specific private data for BSS */
1708 wiphy->bss_priv_size = sizeof(struct mwifiex_bss_priv); 1749 wiphy->bss_priv_size = sizeof(struct mwifiex_bss_priv);
diff --git a/drivers/net/wireless/mwifiex/cmdevt.c b/drivers/net/wireless/mwifiex/cmdevt.c
index 51e023ec1de4..c68adec3cc8b 100644
--- a/drivers/net/wireless/mwifiex/cmdevt.c
+++ b/drivers/net/wireless/mwifiex/cmdevt.c
@@ -578,6 +578,7 @@ int mwifiex_send_cmd_async(struct mwifiex_private *priv, uint16_t cmd_no,
578 } else { 578 } else {
579 adapter->cmd_queued = cmd_node; 579 adapter->cmd_queued = cmd_node;
580 mwifiex_insert_cmd_to_pending_q(adapter, cmd_node, true); 580 mwifiex_insert_cmd_to_pending_q(adapter, cmd_node, true);
581 queue_work(adapter->workqueue, &adapter->main_work);
581 } 582 }
582 583
583 return ret; 584 return ret;
@@ -1102,7 +1103,8 @@ int mwifiex_ret_802_11_hs_cfg(struct mwifiex_private *priv,
1102 &resp->params.opt_hs_cfg; 1103 &resp->params.opt_hs_cfg;
1103 uint32_t conditions = le32_to_cpu(phs_cfg->params.hs_config.conditions); 1104 uint32_t conditions = le32_to_cpu(phs_cfg->params.hs_config.conditions);
1104 1105
1105 if (phs_cfg->action == cpu_to_le16(HS_ACTIVATE)) { 1106 if (phs_cfg->action == cpu_to_le16(HS_ACTIVATE) &&
1107 adapter->iface_type == MWIFIEX_SDIO) {
1106 mwifiex_hs_activated_event(priv, true); 1108 mwifiex_hs_activated_event(priv, true);
1107 return 0; 1109 return 0;
1108 } else { 1110 } else {
@@ -1114,6 +1116,9 @@ int mwifiex_ret_802_11_hs_cfg(struct mwifiex_private *priv,
1114 } 1116 }
1115 if (conditions != HOST_SLEEP_CFG_CANCEL) { 1117 if (conditions != HOST_SLEEP_CFG_CANCEL) {
1116 adapter->is_hs_configured = true; 1118 adapter->is_hs_configured = true;
1119 if (adapter->iface_type == MWIFIEX_USB ||
1120 adapter->iface_type == MWIFIEX_PCIE)
1121 mwifiex_hs_activated_event(priv, true);
1117 } else { 1122 } else {
1118 adapter->is_hs_configured = false; 1123 adapter->is_hs_configured = false;
1119 if (adapter->hs_activated) 1124 if (adapter->hs_activated)
diff --git a/drivers/net/wireless/mwifiex/fw.h b/drivers/net/wireless/mwifiex/fw.h
index 561452a5c818..ffb6cdfdb797 100644
--- a/drivers/net/wireless/mwifiex/fw.h
+++ b/drivers/net/wireless/mwifiex/fw.h
@@ -124,6 +124,7 @@ enum MWIFIEX_802_11_PRIVACY_FILTER {
124#define TLV_TYPE_UAP_DTIM_PERIOD (PROPRIETARY_TLV_BASE_ID + 45) 124#define TLV_TYPE_UAP_DTIM_PERIOD (PROPRIETARY_TLV_BASE_ID + 45)
125#define TLV_TYPE_UAP_BCAST_SSID (PROPRIETARY_TLV_BASE_ID + 48) 125#define TLV_TYPE_UAP_BCAST_SSID (PROPRIETARY_TLV_BASE_ID + 48)
126#define TLV_TYPE_UAP_RTS_THRESHOLD (PROPRIETARY_TLV_BASE_ID + 51) 126#define TLV_TYPE_UAP_RTS_THRESHOLD (PROPRIETARY_TLV_BASE_ID + 51)
127#define TLV_TYPE_UAP_WEP_KEY (PROPRIETARY_TLV_BASE_ID + 59)
127#define TLV_TYPE_UAP_WPA_PASSPHRASE (PROPRIETARY_TLV_BASE_ID + 60) 128#define TLV_TYPE_UAP_WPA_PASSPHRASE (PROPRIETARY_TLV_BASE_ID + 60)
128#define TLV_TYPE_UAP_ENCRY_PROTOCOL (PROPRIETARY_TLV_BASE_ID + 64) 129#define TLV_TYPE_UAP_ENCRY_PROTOCOL (PROPRIETARY_TLV_BASE_ID + 64)
129#define TLV_TYPE_UAP_AKMP (PROPRIETARY_TLV_BASE_ID + 65) 130#define TLV_TYPE_UAP_AKMP (PROPRIETARY_TLV_BASE_ID + 65)
@@ -162,6 +163,12 @@ enum MWIFIEX_802_11_PRIVACY_FILTER {
162 163
163#define ISSUPP_11NENABLED(FwCapInfo) (FwCapInfo & BIT(11)) 164#define ISSUPP_11NENABLED(FwCapInfo) (FwCapInfo & BIT(11))
164 165
166#define MWIFIEX_DEF_HT_CAP (IEEE80211_HT_CAP_DSSSCCK40 | \
167 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT) | \
168 IEEE80211_HT_CAP_SM_PS)
169
170#define MWIFIEX_DEF_AMPDU IEEE80211_HT_AMPDU_PARM_FACTOR
171
165/* dev_cap bitmap 172/* dev_cap bitmap
166 * BIT 173 * BIT
167 * 0-16 reserved 174 * 0-16 reserved
@@ -219,6 +226,7 @@ enum MWIFIEX_802_11_PRIVACY_FILTER {
219#define HostCmd_CMD_RF_REG_ACCESS 0x001b 226#define HostCmd_CMD_RF_REG_ACCESS 0x001b
220#define HostCmd_CMD_PMIC_REG_ACCESS 0x00ad 227#define HostCmd_CMD_PMIC_REG_ACCESS 0x00ad
221#define HostCmd_CMD_802_11_RF_CHANNEL 0x001d 228#define HostCmd_CMD_802_11_RF_CHANNEL 0x001d
229#define HostCmd_CMD_RF_TX_PWR 0x001e
222#define HostCmd_CMD_802_11_DEAUTHENTICATE 0x0024 230#define HostCmd_CMD_802_11_DEAUTHENTICATE 0x0024
223#define HostCmd_CMD_MAC_CONTROL 0x0028 231#define HostCmd_CMD_MAC_CONTROL 0x0028
224#define HostCmd_CMD_802_11_AD_HOC_START 0x002b 232#define HostCmd_CMD_802_11_AD_HOC_START 0x002b
@@ -869,6 +877,13 @@ struct host_cmd_ds_txpwr_cfg {
869 __le32 mode; 877 __le32 mode;
870} __packed; 878} __packed;
871 879
880struct host_cmd_ds_rf_tx_pwr {
881 __le16 action;
882 __le16 cur_level;
883 u8 max_power;
884 u8 min_power;
885} __packed;
886
872struct mwifiex_bcn_param { 887struct mwifiex_bcn_param {
873 u8 bssid[ETH_ALEN]; 888 u8 bssid[ETH_ALEN];
874 u8 rssi; 889 u8 rssi;
@@ -1195,6 +1210,13 @@ struct host_cmd_tlv_passphrase {
1195 u8 passphrase[0]; 1210 u8 passphrase[0];
1196} __packed; 1211} __packed;
1197 1212
1213struct host_cmd_tlv_wep_key {
1214 struct host_cmd_tlv tlv;
1215 u8 key_index;
1216 u8 is_default;
1217 u8 key[1];
1218};
1219
1198struct host_cmd_tlv_auth_type { 1220struct host_cmd_tlv_auth_type {
1199 struct host_cmd_tlv tlv; 1221 struct host_cmd_tlv tlv;
1200 u8 auth_type; 1222 u8 auth_type;
@@ -1347,6 +1369,7 @@ struct host_cmd_ds_command {
1347 struct host_cmd_ds_tx_rate_query tx_rate; 1369 struct host_cmd_ds_tx_rate_query tx_rate;
1348 struct host_cmd_ds_tx_rate_cfg tx_rate_cfg; 1370 struct host_cmd_ds_tx_rate_cfg tx_rate_cfg;
1349 struct host_cmd_ds_txpwr_cfg txp_cfg; 1371 struct host_cmd_ds_txpwr_cfg txp_cfg;
1372 struct host_cmd_ds_rf_tx_pwr txp;
1350 struct host_cmd_ds_802_11_ps_mode_enh psmode_enh; 1373 struct host_cmd_ds_802_11_ps_mode_enh psmode_enh;
1351 struct host_cmd_ds_802_11_hs_cfg_enh opt_hs_cfg; 1374 struct host_cmd_ds_802_11_hs_cfg_enh opt_hs_cfg;
1352 struct host_cmd_ds_802_11_scan scan; 1375 struct host_cmd_ds_802_11_scan scan;
diff --git a/drivers/net/wireless/mwifiex/ie.c b/drivers/net/wireless/mwifiex/ie.c
index 383820a52beb..8374e33f195a 100644
--- a/drivers/net/wireless/mwifiex/ie.c
+++ b/drivers/net/wireless/mwifiex/ie.c
@@ -225,29 +225,46 @@ int mwifiex_set_mgmt_ies(struct mwifiex_private *priv,
225 struct cfg80211_ap_settings *params) 225 struct cfg80211_ap_settings *params)
226{ 226{
227 struct mwifiex_ie *beacon_ie = NULL, *pr_ie = NULL; 227 struct mwifiex_ie *beacon_ie = NULL, *pr_ie = NULL;
228 struct mwifiex_ie *ar_ie = NULL, *rsn_ie = NULL; 228 struct mwifiex_ie *ar_ie = NULL, *gen_ie = NULL;
229 struct ieee_types_header *ie = NULL; 229 struct ieee_types_header *rsn_ie = NULL, *wpa_ie = NULL;
230 u16 beacon_idx = MWIFIEX_AUTO_IDX_MASK, pr_idx = MWIFIEX_AUTO_IDX_MASK; 230 u16 beacon_idx = MWIFIEX_AUTO_IDX_MASK, pr_idx = MWIFIEX_AUTO_IDX_MASK;
231 u16 ar_idx = MWIFIEX_AUTO_IDX_MASK, rsn_idx = MWIFIEX_AUTO_IDX_MASK; 231 u16 ar_idx = MWIFIEX_AUTO_IDX_MASK, rsn_idx = MWIFIEX_AUTO_IDX_MASK;
232 u16 mask; 232 u16 mask, ie_len = 0;
233 const u8 *vendor_ie;
233 int ret = 0; 234 int ret = 0;
234 235
235 if (params->beacon.tail && params->beacon.tail_len) { 236 if (params->beacon.tail && params->beacon.tail_len) {
236 ie = (void *)cfg80211_find_ie(WLAN_EID_RSN, params->beacon.tail, 237 gen_ie = kzalloc(sizeof(struct mwifiex_ie), GFP_KERNEL);
237 params->beacon.tail_len); 238 if (!gen_ie)
238 if (ie) { 239 return -ENOMEM;
239 rsn_ie = kmalloc(sizeof(struct mwifiex_ie), GFP_KERNEL); 240 gen_ie->ie_index = cpu_to_le16(rsn_idx);
240 if (!rsn_ie) 241 mask = MGMT_MASK_BEACON | MGMT_MASK_PROBE_RESP |
241 return -ENOMEM; 242 MGMT_MASK_ASSOC_RESP;
242 243 gen_ie->mgmt_subtype_mask = cpu_to_le16(mask);
243 rsn_ie->ie_index = cpu_to_le16(rsn_idx); 244
244 mask = MGMT_MASK_BEACON | MGMT_MASK_PROBE_RESP | 245 rsn_ie = (void *)cfg80211_find_ie(WLAN_EID_RSN,
245 MGMT_MASK_ASSOC_RESP; 246 params->beacon.tail,
246 rsn_ie->mgmt_subtype_mask = cpu_to_le16(mask); 247 params->beacon.tail_len);
247 rsn_ie->ie_length = cpu_to_le16(ie->len + 2); 248 if (rsn_ie) {
248 memcpy(rsn_ie->ie_buffer, ie, ie->len + 2); 249 memcpy(gen_ie->ie_buffer, rsn_ie, rsn_ie->len + 2);
249 250 ie_len = rsn_ie->len + 2;
250 if (mwifiex_update_uap_custom_ie(priv, rsn_ie, &rsn_idx, 251 gen_ie->ie_length = cpu_to_le16(ie_len);
252 }
253
254 vendor_ie = cfg80211_find_vendor_ie(WLAN_OUI_MICROSOFT,
255 WLAN_OUI_TYPE_MICROSOFT_WPA,
256 params->beacon.tail,
257 params->beacon.tail_len);
258 if (vendor_ie) {
259 wpa_ie = (struct ieee_types_header *)vendor_ie;
260 memcpy(gen_ie->ie_buffer + ie_len,
261 wpa_ie, wpa_ie->len + 2);
262 ie_len += wpa_ie->len + 2;
263 gen_ie->ie_length = cpu_to_le16(ie_len);
264 }
265
266 if (rsn_ie || wpa_ie) {
267 if (mwifiex_update_uap_custom_ie(priv, gen_ie, &rsn_idx,
251 NULL, NULL, 268 NULL, NULL,
252 NULL, NULL)) { 269 NULL, NULL)) {
253 ret = -1; 270 ret = -1;
@@ -320,7 +337,7 @@ done:
320 kfree(beacon_ie); 337 kfree(beacon_ie);
321 kfree(pr_ie); 338 kfree(pr_ie);
322 kfree(ar_ie); 339 kfree(ar_ie);
323 kfree(rsn_ie); 340 kfree(gen_ie);
324 341
325 return ret; 342 return ret;
326} 343}
diff --git a/drivers/net/wireless/mwifiex/init.c b/drivers/net/wireless/mwifiex/init.c
index 0f18ef6a30c8..b543a4d82ff3 100644
--- a/drivers/net/wireless/mwifiex/init.c
+++ b/drivers/net/wireless/mwifiex/init.c
@@ -103,6 +103,7 @@ static void scan_delay_timer_fn(unsigned long data)
103 msecs_to_jiffies(MWIFIEX_SCAN_DELAY_MSEC)); 103 msecs_to_jiffies(MWIFIEX_SCAN_DELAY_MSEC));
104 adapter->scan_delay_cnt++; 104 adapter->scan_delay_cnt++;
105 } 105 }
106 queue_work(priv->adapter->workqueue, &priv->adapter->main_work);
106 } else { 107 } else {
107 /* 108 /*
108 * Tx data queue is empty. Get scan command from scan_pending_q 109 * Tx data queue is empty. Get scan command from scan_pending_q
diff --git a/drivers/net/wireless/mwifiex/ioctl.h b/drivers/net/wireless/mwifiex/ioctl.h
index e6be6ee75951..9f088fb88cb7 100644
--- a/drivers/net/wireless/mwifiex/ioctl.h
+++ b/drivers/net/wireless/mwifiex/ioctl.h
@@ -21,6 +21,7 @@
21#define _MWIFIEX_IOCTL_H_ 21#define _MWIFIEX_IOCTL_H_
22 22
23#include <net/mac80211.h> 23#include <net/mac80211.h>
24#include <net/lib80211.h>
24 25
25enum { 26enum {
26 MWIFIEX_SCAN_TYPE_UNCHANGED = 0, 27 MWIFIEX_SCAN_TYPE_UNCHANGED = 0,
@@ -71,6 +72,13 @@ struct wpa_param {
71 u8 passphrase[MWIFIEX_WPA_PASSHPHRASE_LEN]; 72 u8 passphrase[MWIFIEX_WPA_PASSHPHRASE_LEN];
72}; 73};
73 74
75struct wep_key {
76 u8 key_index;
77 u8 is_default;
78 u16 length;
79 u8 key[WLAN_KEY_LEN_WEP104];
80};
81
74#define KEY_MGMT_ON_HOST 0x03 82#define KEY_MGMT_ON_HOST 0x03
75#define MWIFIEX_AUTH_MODE_AUTO 0xFF 83#define MWIFIEX_AUTH_MODE_AUTO 0xFF
76#define BAND_CONFIG_MANUAL 0x00 84#define BAND_CONFIG_MANUAL 0x00
@@ -90,6 +98,8 @@ struct mwifiex_uap_bss_param {
90 u16 key_mgmt; 98 u16 key_mgmt;
91 u16 key_mgmt_operation; 99 u16 key_mgmt_operation;
92 struct wpa_param wpa_cfg; 100 struct wpa_param wpa_cfg;
101 struct wep_key wep_cfg[NUM_WEP_KEYS];
102 struct ieee80211_ht_cap ht_cap;
93}; 103};
94 104
95enum { 105enum {
diff --git a/drivers/net/wireless/mwifiex/main.c b/drivers/net/wireless/mwifiex/main.c
index 0f06f07a70e6..f0219efc8953 100644
--- a/drivers/net/wireless/mwifiex/main.c
+++ b/drivers/net/wireless/mwifiex/main.c
@@ -190,7 +190,8 @@ process_start:
190 adapter->tx_lock_flag) 190 adapter->tx_lock_flag)
191 break; 191 break;
192 192
193 if (adapter->scan_processing || adapter->data_sent || 193 if ((adapter->scan_processing &&
194 !adapter->scan_delay_cnt) || adapter->data_sent ||
194 mwifiex_wmm_lists_empty(adapter)) { 195 mwifiex_wmm_lists_empty(adapter)) {
195 if (adapter->cmd_sent || adapter->curr_cmd || 196 if (adapter->cmd_sent || adapter->curr_cmd ||
196 (!is_command_pending(adapter))) 197 (!is_command_pending(adapter)))
diff --git a/drivers/net/wireless/mwifiex/main.h b/drivers/net/wireless/mwifiex/main.h
index 5b32221077c4..7cd95cc99a85 100644
--- a/drivers/net/wireless/mwifiex/main.h
+++ b/drivers/net/wireless/mwifiex/main.h
@@ -840,6 +840,9 @@ void mwifiex_init_priv_params(struct mwifiex_private *priv,
840int mwifiex_set_secure_params(struct mwifiex_private *priv, 840int mwifiex_set_secure_params(struct mwifiex_private *priv,
841 struct mwifiex_uap_bss_param *bss_config, 841 struct mwifiex_uap_bss_param *bss_config,
842 struct cfg80211_ap_settings *params); 842 struct cfg80211_ap_settings *params);
843void mwifiex_set_ht_params(struct mwifiex_private *priv,
844 struct mwifiex_uap_bss_param *bss_cfg,
845 struct cfg80211_ap_settings *params);
843 846
844/* 847/*
845 * This function checks if the queuing is RA based or not. 848 * This function checks if the queuing is RA based or not.
@@ -946,8 +949,8 @@ int mwifiex_drv_get_data_rate(struct mwifiex_private *priv,
946 struct mwifiex_rate_cfg *rate); 949 struct mwifiex_rate_cfg *rate);
947int mwifiex_request_scan(struct mwifiex_private *priv, 950int mwifiex_request_scan(struct mwifiex_private *priv,
948 struct cfg80211_ssid *req_ssid); 951 struct cfg80211_ssid *req_ssid);
949int mwifiex_set_user_scan_ioctl(struct mwifiex_private *priv, 952int mwifiex_scan_networks(struct mwifiex_private *priv,
950 struct mwifiex_user_scan_cfg *scan_req); 953 const struct mwifiex_user_scan_cfg *user_scan_in);
951int mwifiex_set_radio(struct mwifiex_private *priv, u8 option); 954int mwifiex_set_radio(struct mwifiex_private *priv, u8 option);
952 955
953int mwifiex_drv_change_adhoc_chan(struct mwifiex_private *priv, u16 channel); 956int mwifiex_drv_change_adhoc_chan(struct mwifiex_private *priv, u16 channel);
@@ -990,7 +993,6 @@ int mwifiex_set_tx_power(struct mwifiex_private *priv,
990 993
991int mwifiex_main_process(struct mwifiex_adapter *); 994int mwifiex_main_process(struct mwifiex_adapter *);
992 995
993int mwifiex_uap_set_channel(struct mwifiex_private *priv, int channel);
994int mwifiex_bss_set_channel(struct mwifiex_private *, 996int mwifiex_bss_set_channel(struct mwifiex_private *,
995 struct mwifiex_chan_freq_power *cfp); 997 struct mwifiex_chan_freq_power *cfp);
996int mwifiex_get_bss_info(struct mwifiex_private *, 998int mwifiex_get_bss_info(struct mwifiex_private *,
diff --git a/drivers/net/wireless/mwifiex/scan.c b/drivers/net/wireless/mwifiex/scan.c
index 98c6aabd5a48..04dc7ca4ac22 100644
--- a/drivers/net/wireless/mwifiex/scan.c
+++ b/drivers/net/wireless/mwifiex/scan.c
@@ -1294,8 +1294,8 @@ mwifiex_radio_type_to_band(u8 radio_type)
1294 * order to send the appropriate scan commands to firmware to populate or 1294 * order to send the appropriate scan commands to firmware to populate or
1295 * update the internal driver scan table. 1295 * update the internal driver scan table.
1296 */ 1296 */
1297static int mwifiex_scan_networks(struct mwifiex_private *priv, 1297int mwifiex_scan_networks(struct mwifiex_private *priv,
1298 const struct mwifiex_user_scan_cfg *user_scan_in) 1298 const struct mwifiex_user_scan_cfg *user_scan_in)
1299{ 1299{
1300 int ret = 0; 1300 int ret = 0;
1301 struct mwifiex_adapter *adapter = priv->adapter; 1301 struct mwifiex_adapter *adapter = priv->adapter;
@@ -1360,6 +1360,7 @@ static int mwifiex_scan_networks(struct mwifiex_private *priv,
1360 adapter->cmd_queued = cmd_node; 1360 adapter->cmd_queued = cmd_node;
1361 mwifiex_insert_cmd_to_pending_q(adapter, cmd_node, 1361 mwifiex_insert_cmd_to_pending_q(adapter, cmd_node,
1362 true); 1362 true);
1363 queue_work(adapter->workqueue, &adapter->main_work);
1363 } else { 1364 } else {
1364 spin_unlock_irqrestore(&adapter->scan_pending_q_lock, 1365 spin_unlock_irqrestore(&adapter->scan_pending_q_lock,
1365 flags); 1366 flags);
@@ -1376,26 +1377,6 @@ static int mwifiex_scan_networks(struct mwifiex_private *priv,
1376} 1377}
1377 1378
1378/* 1379/*
1379 * Sends IOCTL request to start a scan with user configurations.
1380 *
1381 * This function allocates the IOCTL request buffer, fills it
1382 * with requisite parameters and calls the IOCTL handler.
1383 *
1384 * Upon completion, it also generates a wireless event to notify
1385 * applications.
1386 */
1387int mwifiex_set_user_scan_ioctl(struct mwifiex_private *priv,
1388 struct mwifiex_user_scan_cfg *scan_req)
1389{
1390 int status;
1391
1392 status = mwifiex_scan_networks(priv, scan_req);
1393 queue_work(priv->adapter->workqueue, &priv->adapter->main_work);
1394
1395 return status;
1396}
1397
1398/*
1399 * This function prepares a scan command to be sent to the firmware. 1380 * This function prepares a scan command to be sent to the firmware.
1400 * 1381 *
1401 * This uses the scan command configuration sent to the command processing 1382 * This uses the scan command configuration sent to the command processing
diff --git a/drivers/net/wireless/mwifiex/sta_cmd.c b/drivers/net/wireless/mwifiex/sta_cmd.c
index 1ff1362d8cdf..b9cd9ed48c45 100644
--- a/drivers/net/wireless/mwifiex/sta_cmd.c
+++ b/drivers/net/wireless/mwifiex/sta_cmd.c
@@ -260,6 +260,23 @@ static int mwifiex_cmd_tx_power_cfg(struct host_cmd_ds_command *cmd,
260} 260}
261 261
262/* 262/*
263 * This function prepares command to get RF Tx power.
264 */
265static int mwifiex_cmd_rf_tx_power(struct mwifiex_private *priv,
266 struct host_cmd_ds_command *cmd,
267 u16 cmd_action, void *data_buf)
268{
269 struct host_cmd_ds_rf_tx_pwr *txp = &cmd->params.txp;
270
271 cmd->size = cpu_to_le16(sizeof(struct host_cmd_ds_rf_tx_pwr)
272 + S_DS_GEN);
273 cmd->command = cpu_to_le16(HostCmd_CMD_RF_TX_PWR);
274 txp->action = cpu_to_le16(cmd_action);
275
276 return 0;
277}
278
279/*
263 * This function prepares command to set Host Sleep configuration. 280 * This function prepares command to set Host Sleep configuration.
264 * 281 *
265 * Preparation includes - 282 * Preparation includes -
@@ -1049,6 +1066,10 @@ int mwifiex_sta_prepare_cmd(struct mwifiex_private *priv, uint16_t cmd_no,
1049 ret = mwifiex_cmd_tx_power_cfg(cmd_ptr, cmd_action, 1066 ret = mwifiex_cmd_tx_power_cfg(cmd_ptr, cmd_action,
1050 data_buf); 1067 data_buf);
1051 break; 1068 break;
1069 case HostCmd_CMD_RF_TX_PWR:
1070 ret = mwifiex_cmd_rf_tx_power(priv, cmd_ptr, cmd_action,
1071 data_buf);
1072 break;
1052 case HostCmd_CMD_802_11_PS_MODE_ENH: 1073 case HostCmd_CMD_802_11_PS_MODE_ENH:
1053 ret = mwifiex_cmd_enh_power_mode(priv, cmd_ptr, cmd_action, 1074 ret = mwifiex_cmd_enh_power_mode(priv, cmd_ptr, cmd_action,
1054 (uint16_t)cmd_oid, data_buf); 1075 (uint16_t)cmd_oid, data_buf);
@@ -1277,7 +1298,7 @@ int mwifiex_sta_init_cmd(struct mwifiex_private *priv, u8 first_sta)
1277 priv->data_rate = 0; 1298 priv->data_rate = 0;
1278 1299
1279 /* get tx power */ 1300 /* get tx power */
1280 ret = mwifiex_send_cmd_async(priv, HostCmd_CMD_TXPWR_CFG, 1301 ret = mwifiex_send_cmd_async(priv, HostCmd_CMD_RF_TX_PWR,
1281 HostCmd_ACT_GEN_GET, 0, NULL); 1302 HostCmd_ACT_GEN_GET, 0, NULL);
1282 if (ret) 1303 if (ret)
1283 return -1; 1304 return -1;
diff --git a/drivers/net/wireless/mwifiex/sta_cmdresp.c b/drivers/net/wireless/mwifiex/sta_cmdresp.c
index bd40541ebd5a..78fc352c85c4 100644
--- a/drivers/net/wireless/mwifiex/sta_cmdresp.c
+++ b/drivers/net/wireless/mwifiex/sta_cmdresp.c
@@ -451,6 +451,30 @@ static int mwifiex_ret_tx_power_cfg(struct mwifiex_private *priv,
451} 451}
452 452
453/* 453/*
454 * This function handles the command response of get RF Tx power.
455 */
456static int mwifiex_ret_rf_tx_power(struct mwifiex_private *priv,
457 struct host_cmd_ds_command *resp)
458{
459 struct host_cmd_ds_rf_tx_pwr *txp = &resp->params.txp;
460 u16 action = le16_to_cpu(txp->action);
461
462 priv->tx_power_level = le16_to_cpu(txp->cur_level);
463
464 if (action == HostCmd_ACT_GEN_GET) {
465 priv->max_tx_power_level = txp->max_power;
466 priv->min_tx_power_level = txp->min_power;
467 }
468
469 dev_dbg(priv->adapter->dev,
470 "Current TxPower Level=%d, Max Power=%d, Min Power=%d\n",
471 priv->tx_power_level, priv->max_tx_power_level,
472 priv->min_tx_power_level);
473
474 return 0;
475}
476
477/*
454 * This function handles the command response of set/get MAC address. 478 * This function handles the command response of set/get MAC address.
455 * 479 *
456 * Handling includes saving the MAC address in driver. 480 * Handling includes saving the MAC address in driver.
@@ -841,6 +865,9 @@ int mwifiex_process_sta_cmdresp(struct mwifiex_private *priv, u16 cmdresp_no,
841 case HostCmd_CMD_TXPWR_CFG: 865 case HostCmd_CMD_TXPWR_CFG:
842 ret = mwifiex_ret_tx_power_cfg(priv, resp); 866 ret = mwifiex_ret_tx_power_cfg(priv, resp);
843 break; 867 break;
868 case HostCmd_CMD_RF_TX_PWR:
869 ret = mwifiex_ret_rf_tx_power(priv, resp);
870 break;
844 case HostCmd_CMD_802_11_PS_MODE_ENH: 871 case HostCmd_CMD_802_11_PS_MODE_ENH:
845 ret = mwifiex_ret_enh_power_mode(priv, resp, data_buf); 872 ret = mwifiex_ret_enh_power_mode(priv, resp, data_buf);
846 break; 873 break;
diff --git a/drivers/net/wireless/mwifiex/sta_ioctl.c b/drivers/net/wireless/mwifiex/sta_ioctl.c
index 106c449477b2..f2fd2423214f 100644
--- a/drivers/net/wireless/mwifiex/sta_ioctl.c
+++ b/drivers/net/wireless/mwifiex/sta_ioctl.c
@@ -66,9 +66,6 @@ int mwifiex_wait_queue_complete(struct mwifiex_adapter *adapter)
66 dev_dbg(adapter->dev, "cmd pending\n"); 66 dev_dbg(adapter->dev, "cmd pending\n");
67 atomic_inc(&adapter->cmd_pending); 67 atomic_inc(&adapter->cmd_pending);
68 68
69 /* Status pending, wake up main process */
70 queue_work(adapter->workqueue, &adapter->main_work);
71
72 /* Wait for completion */ 69 /* Wait for completion */
73 wait_event_interruptible(adapter->cmd_wait_q.wait, 70 wait_event_interruptible(adapter->cmd_wait_q.wait,
74 *(cmd_queued->condition)); 71 *(cmd_queued->condition));
diff --git a/drivers/net/wireless/mwifiex/uap_cmd.c b/drivers/net/wireless/mwifiex/uap_cmd.c
index 89f9a2a45de3..f40e93fe894a 100644
--- a/drivers/net/wireless/mwifiex/uap_cmd.c
+++ b/drivers/net/wireless/mwifiex/uap_cmd.c
@@ -26,6 +26,7 @@ int mwifiex_set_secure_params(struct mwifiex_private *priv,
26 struct mwifiex_uap_bss_param *bss_config, 26 struct mwifiex_uap_bss_param *bss_config,
27 struct cfg80211_ap_settings *params) { 27 struct cfg80211_ap_settings *params) {
28 int i; 28 int i;
29 struct mwifiex_wep_key wep_key;
29 30
30 if (!params->privacy) { 31 if (!params->privacy) {
31 bss_config->protocol = PROTOCOL_NO_SECURITY; 32 bss_config->protocol = PROTOCOL_NO_SECURITY;
@@ -65,7 +66,7 @@ int mwifiex_set_secure_params(struct mwifiex_private *priv,
65 } 66 }
66 if (params->crypto.wpa_versions & 67 if (params->crypto.wpa_versions &
67 NL80211_WPA_VERSION_2) { 68 NL80211_WPA_VERSION_2) {
68 bss_config->protocol = PROTOCOL_WPA2; 69 bss_config->protocol |= PROTOCOL_WPA2;
69 bss_config->key_mgmt = KEY_MGMT_EAP; 70 bss_config->key_mgmt = KEY_MGMT_EAP;
70 } 71 }
71 break; 72 break;
@@ -77,7 +78,7 @@ int mwifiex_set_secure_params(struct mwifiex_private *priv,
77 } 78 }
78 if (params->crypto.wpa_versions & 79 if (params->crypto.wpa_versions &
79 NL80211_WPA_VERSION_2) { 80 NL80211_WPA_VERSION_2) {
80 bss_config->protocol = PROTOCOL_WPA2; 81 bss_config->protocol |= PROTOCOL_WPA2;
81 bss_config->key_mgmt = KEY_MGMT_PSK; 82 bss_config->key_mgmt = KEY_MGMT_PSK;
82 } 83 }
83 break; 84 break;
@@ -91,10 +92,19 @@ int mwifiex_set_secure_params(struct mwifiex_private *priv,
91 case WLAN_CIPHER_SUITE_WEP104: 92 case WLAN_CIPHER_SUITE_WEP104:
92 break; 93 break;
93 case WLAN_CIPHER_SUITE_TKIP: 94 case WLAN_CIPHER_SUITE_TKIP:
94 bss_config->wpa_cfg.pairwise_cipher_wpa = CIPHER_TKIP; 95 if (params->crypto.wpa_versions & NL80211_WPA_VERSION_1)
96 bss_config->wpa_cfg.pairwise_cipher_wpa |=
97 CIPHER_TKIP;
98 if (params->crypto.wpa_versions & NL80211_WPA_VERSION_2)
99 bss_config->wpa_cfg.pairwise_cipher_wpa2 |=
100 CIPHER_TKIP;
95 break; 101 break;
96 case WLAN_CIPHER_SUITE_CCMP: 102 case WLAN_CIPHER_SUITE_CCMP:
97 bss_config->wpa_cfg.pairwise_cipher_wpa2 = 103 if (params->crypto.wpa_versions & NL80211_WPA_VERSION_1)
104 bss_config->wpa_cfg.pairwise_cipher_wpa |=
105 CIPHER_AES_CCMP;
106 if (params->crypto.wpa_versions & NL80211_WPA_VERSION_2)
107 bss_config->wpa_cfg.pairwise_cipher_wpa2 |=
98 CIPHER_AES_CCMP; 108 CIPHER_AES_CCMP;
99 default: 109 default:
100 break; 110 break;
@@ -104,6 +114,27 @@ int mwifiex_set_secure_params(struct mwifiex_private *priv,
104 switch (params->crypto.cipher_group) { 114 switch (params->crypto.cipher_group) {
105 case WLAN_CIPHER_SUITE_WEP40: 115 case WLAN_CIPHER_SUITE_WEP40:
106 case WLAN_CIPHER_SUITE_WEP104: 116 case WLAN_CIPHER_SUITE_WEP104:
117 if (priv->sec_info.wep_enabled) {
118 bss_config->protocol = PROTOCOL_STATIC_WEP;
119 bss_config->key_mgmt = KEY_MGMT_NONE;
120 bss_config->wpa_cfg.length = 0;
121
122 for (i = 0; i < NUM_WEP_KEYS; i++) {
123 wep_key = priv->wep_key[i];
124 bss_config->wep_cfg[i].key_index = i;
125
126 if (priv->wep_key_curr_index == i)
127 bss_config->wep_cfg[i].is_default = 1;
128 else
129 bss_config->wep_cfg[i].is_default = 0;
130
131 bss_config->wep_cfg[i].length =
132 wep_key.key_length;
133 memcpy(&bss_config->wep_cfg[i].key,
134 &wep_key.key_material,
135 wep_key.key_length);
136 }
137 }
107 break; 138 break;
108 case WLAN_CIPHER_SUITE_TKIP: 139 case WLAN_CIPHER_SUITE_TKIP:
109 bss_config->wpa_cfg.group_cipher = CIPHER_TKIP; 140 bss_config->wpa_cfg.group_cipher = CIPHER_TKIP;
@@ -118,6 +149,33 @@ int mwifiex_set_secure_params(struct mwifiex_private *priv,
118 return 0; 149 return 0;
119} 150}
120 151
152/* This function updates 11n related parameters from IE and sets them into
153 * bss_config structure.
154 */
155void
156mwifiex_set_ht_params(struct mwifiex_private *priv,
157 struct mwifiex_uap_bss_param *bss_cfg,
158 struct cfg80211_ap_settings *params)
159{
160 const u8 *ht_ie;
161
162 if (!ISSUPP_11NENABLED(priv->adapter->fw_cap_info))
163 return;
164
165 ht_ie = cfg80211_find_ie(WLAN_EID_HT_CAPABILITY, params->beacon.tail,
166 params->beacon.tail_len);
167 if (ht_ie) {
168 memcpy(&bss_cfg->ht_cap, ht_ie + 2,
169 sizeof(struct ieee80211_ht_cap));
170 } else {
171 memset(&bss_cfg->ht_cap , 0, sizeof(struct ieee80211_ht_cap));
172 bss_cfg->ht_cap.cap_info = cpu_to_le16(MWIFIEX_DEF_HT_CAP);
173 bss_cfg->ht_cap.ampdu_params_info = MWIFIEX_DEF_AMPDU;
174 }
175
176 return;
177}
178
121/* This function initializes some of mwifiex_uap_bss_param variables. 179/* This function initializes some of mwifiex_uap_bss_param variables.
122 * This helps FW in ignoring invalid values. These values may or may not 180 * This helps FW in ignoring invalid values. These values may or may not
123 * be get updated to valid ones at later stage. 181 * be get updated to valid ones at later stage.
@@ -135,6 +193,120 @@ void mwifiex_set_sys_config_invalid_data(struct mwifiex_uap_bss_param *config)
135} 193}
136 194
137/* This function parses BSS related parameters from structure 195/* This function parses BSS related parameters from structure
196 * and prepares TLVs specific to WPA/WPA2 security.
197 * These TLVs are appended to command buffer.
198 */
199static void
200mwifiex_uap_bss_wpa(u8 **tlv_buf, void *cmd_buf, u16 *param_size)
201{
202 struct host_cmd_tlv_pwk_cipher *pwk_cipher;
203 struct host_cmd_tlv_gwk_cipher *gwk_cipher;
204 struct host_cmd_tlv_passphrase *passphrase;
205 struct host_cmd_tlv_akmp *tlv_akmp;
206 struct mwifiex_uap_bss_param *bss_cfg = cmd_buf;
207 u16 cmd_size = *param_size;
208 u8 *tlv = *tlv_buf;
209
210 tlv_akmp = (struct host_cmd_tlv_akmp *)tlv;
211 tlv_akmp->tlv.type = cpu_to_le16(TLV_TYPE_UAP_AKMP);
212 tlv_akmp->tlv.len = cpu_to_le16(sizeof(struct host_cmd_tlv_akmp) -
213 sizeof(struct host_cmd_tlv));
214 tlv_akmp->key_mgmt_operation = cpu_to_le16(bss_cfg->key_mgmt_operation);
215 tlv_akmp->key_mgmt = cpu_to_le16(bss_cfg->key_mgmt);
216 cmd_size += sizeof(struct host_cmd_tlv_akmp);
217 tlv += sizeof(struct host_cmd_tlv_akmp);
218
219 if (bss_cfg->wpa_cfg.pairwise_cipher_wpa & VALID_CIPHER_BITMAP) {
220 pwk_cipher = (struct host_cmd_tlv_pwk_cipher *)tlv;
221 pwk_cipher->tlv.type = cpu_to_le16(TLV_TYPE_PWK_CIPHER);
222 pwk_cipher->tlv.len =
223 cpu_to_le16(sizeof(struct host_cmd_tlv_pwk_cipher) -
224 sizeof(struct host_cmd_tlv));
225 pwk_cipher->proto = cpu_to_le16(PROTOCOL_WPA);
226 pwk_cipher->cipher = bss_cfg->wpa_cfg.pairwise_cipher_wpa;
227 cmd_size += sizeof(struct host_cmd_tlv_pwk_cipher);
228 tlv += sizeof(struct host_cmd_tlv_pwk_cipher);
229 }
230
231 if (bss_cfg->wpa_cfg.pairwise_cipher_wpa2 & VALID_CIPHER_BITMAP) {
232 pwk_cipher = (struct host_cmd_tlv_pwk_cipher *)tlv;
233 pwk_cipher->tlv.type = cpu_to_le16(TLV_TYPE_PWK_CIPHER);
234 pwk_cipher->tlv.len =
235 cpu_to_le16(sizeof(struct host_cmd_tlv_pwk_cipher) -
236 sizeof(struct host_cmd_tlv));
237 pwk_cipher->proto = cpu_to_le16(PROTOCOL_WPA2);
238 pwk_cipher->cipher = bss_cfg->wpa_cfg.pairwise_cipher_wpa2;
239 cmd_size += sizeof(struct host_cmd_tlv_pwk_cipher);
240 tlv += sizeof(struct host_cmd_tlv_pwk_cipher);
241 }
242
243 if (bss_cfg->wpa_cfg.group_cipher & VALID_CIPHER_BITMAP) {
244 gwk_cipher = (struct host_cmd_tlv_gwk_cipher *)tlv;
245 gwk_cipher->tlv.type = cpu_to_le16(TLV_TYPE_GWK_CIPHER);
246 gwk_cipher->tlv.len =
247 cpu_to_le16(sizeof(struct host_cmd_tlv_gwk_cipher) -
248 sizeof(struct host_cmd_tlv));
249 gwk_cipher->cipher = bss_cfg->wpa_cfg.group_cipher;
250 cmd_size += sizeof(struct host_cmd_tlv_gwk_cipher);
251 tlv += sizeof(struct host_cmd_tlv_gwk_cipher);
252 }
253
254 if (bss_cfg->wpa_cfg.length) {
255 passphrase = (struct host_cmd_tlv_passphrase *)tlv;
256 passphrase->tlv.type = cpu_to_le16(TLV_TYPE_UAP_WPA_PASSPHRASE);
257 passphrase->tlv.len = cpu_to_le16(bss_cfg->wpa_cfg.length);
258 memcpy(passphrase->passphrase, bss_cfg->wpa_cfg.passphrase,
259 bss_cfg->wpa_cfg.length);
260 cmd_size += sizeof(struct host_cmd_tlv) +
261 bss_cfg->wpa_cfg.length;
262 tlv += sizeof(struct host_cmd_tlv) + bss_cfg->wpa_cfg.length;
263 }
264
265 *param_size = cmd_size;
266 *tlv_buf = tlv;
267
268 return;
269}
270
271/* This function parses BSS related parameters from structure
272 * and prepares TLVs specific to WEP encryption.
273 * These TLVs are appended to command buffer.
274 */
275static void
276mwifiex_uap_bss_wep(u8 **tlv_buf, void *cmd_buf, u16 *param_size)
277{
278 struct host_cmd_tlv_wep_key *wep_key;
279 u16 cmd_size = *param_size;
280 int i;
281 u8 *tlv = *tlv_buf;
282 struct mwifiex_uap_bss_param *bss_cfg = cmd_buf;
283
284 for (i = 0; i < NUM_WEP_KEYS; i++) {
285 if (bss_cfg->wep_cfg[i].length &&
286 (bss_cfg->wep_cfg[i].length == WLAN_KEY_LEN_WEP40 ||
287 bss_cfg->wep_cfg[i].length == WLAN_KEY_LEN_WEP104)) {
288 wep_key = (struct host_cmd_tlv_wep_key *)tlv;
289 wep_key->tlv.type = cpu_to_le16(TLV_TYPE_UAP_WEP_KEY);
290 wep_key->tlv.len =
291 cpu_to_le16(bss_cfg->wep_cfg[i].length + 2);
292 wep_key->key_index = bss_cfg->wep_cfg[i].key_index;
293 wep_key->is_default = bss_cfg->wep_cfg[i].is_default;
294 memcpy(wep_key->key, bss_cfg->wep_cfg[i].key,
295 bss_cfg->wep_cfg[i].length);
296 cmd_size += sizeof(struct host_cmd_tlv) + 2 +
297 bss_cfg->wep_cfg[i].length;
298 tlv += sizeof(struct host_cmd_tlv) + 2 +
299 bss_cfg->wep_cfg[i].length;
300 }
301 }
302
303 *param_size = cmd_size;
304 *tlv_buf = tlv;
305
306 return;
307}
308
309/* This function parses BSS related parameters from structure
138 * and prepares TLVs. These TLVs are appended to command buffer. 310 * and prepares TLVs. These TLVs are appended to command buffer.
139*/ 311*/
140static int 312static int
@@ -148,12 +320,9 @@ mwifiex_uap_bss_param_prepare(u8 *tlv, void *cmd_buf, u16 *param_size)
148 struct host_cmd_tlv_frag_threshold *frag_threshold; 320 struct host_cmd_tlv_frag_threshold *frag_threshold;
149 struct host_cmd_tlv_rts_threshold *rts_threshold; 321 struct host_cmd_tlv_rts_threshold *rts_threshold;
150 struct host_cmd_tlv_retry_limit *retry_limit; 322 struct host_cmd_tlv_retry_limit *retry_limit;
151 struct host_cmd_tlv_pwk_cipher *pwk_cipher;
152 struct host_cmd_tlv_gwk_cipher *gwk_cipher;
153 struct host_cmd_tlv_encrypt_protocol *encrypt_protocol; 323 struct host_cmd_tlv_encrypt_protocol *encrypt_protocol;
154 struct host_cmd_tlv_auth_type *auth_type; 324 struct host_cmd_tlv_auth_type *auth_type;
155 struct host_cmd_tlv_passphrase *passphrase; 325 struct mwifiex_ie_types_htcap *htcap;
156 struct host_cmd_tlv_akmp *tlv_akmp;
157 struct mwifiex_uap_bss_param *bss_cfg = cmd_buf; 326 struct mwifiex_uap_bss_param *bss_cfg = cmd_buf;
158 u16 cmd_size = *param_size; 327 u16 cmd_size = *param_size;
159 328
@@ -243,70 +412,11 @@ mwifiex_uap_bss_param_prepare(u8 *tlv, void *cmd_buf, u16 *param_size)
243 } 412 }
244 if ((bss_cfg->protocol & PROTOCOL_WPA) || 413 if ((bss_cfg->protocol & PROTOCOL_WPA) ||
245 (bss_cfg->protocol & PROTOCOL_WPA2) || 414 (bss_cfg->protocol & PROTOCOL_WPA2) ||
246 (bss_cfg->protocol & PROTOCOL_EAP)) { 415 (bss_cfg->protocol & PROTOCOL_EAP))
247 tlv_akmp = (struct host_cmd_tlv_akmp *)tlv; 416 mwifiex_uap_bss_wpa(&tlv, cmd_buf, &cmd_size);
248 tlv_akmp->tlv.type = cpu_to_le16(TLV_TYPE_UAP_AKMP); 417 else
249 tlv_akmp->tlv.len = 418 mwifiex_uap_bss_wep(&tlv, cmd_buf, &cmd_size);
250 cpu_to_le16(sizeof(struct host_cmd_tlv_akmp) - 419
251 sizeof(struct host_cmd_tlv));
252 tlv_akmp->key_mgmt_operation =
253 cpu_to_le16(bss_cfg->key_mgmt_operation);
254 tlv_akmp->key_mgmt = cpu_to_le16(bss_cfg->key_mgmt);
255 cmd_size += sizeof(struct host_cmd_tlv_akmp);
256 tlv += sizeof(struct host_cmd_tlv_akmp);
257
258 if (bss_cfg->wpa_cfg.pairwise_cipher_wpa &
259 VALID_CIPHER_BITMAP) {
260 pwk_cipher = (struct host_cmd_tlv_pwk_cipher *)tlv;
261 pwk_cipher->tlv.type =
262 cpu_to_le16(TLV_TYPE_PWK_CIPHER);
263 pwk_cipher->tlv.len = cpu_to_le16(
264 sizeof(struct host_cmd_tlv_pwk_cipher) -
265 sizeof(struct host_cmd_tlv));
266 pwk_cipher->proto = cpu_to_le16(PROTOCOL_WPA);
267 pwk_cipher->cipher =
268 bss_cfg->wpa_cfg.pairwise_cipher_wpa;
269 cmd_size += sizeof(struct host_cmd_tlv_pwk_cipher);
270 tlv += sizeof(struct host_cmd_tlv_pwk_cipher);
271 }
272 if (bss_cfg->wpa_cfg.pairwise_cipher_wpa2 &
273 VALID_CIPHER_BITMAP) {
274 pwk_cipher = (struct host_cmd_tlv_pwk_cipher *)tlv;
275 pwk_cipher->tlv.type = cpu_to_le16(TLV_TYPE_PWK_CIPHER);
276 pwk_cipher->tlv.len = cpu_to_le16(
277 sizeof(struct host_cmd_tlv_pwk_cipher) -
278 sizeof(struct host_cmd_tlv));
279 pwk_cipher->proto = cpu_to_le16(PROTOCOL_WPA2);
280 pwk_cipher->cipher =
281 bss_cfg->wpa_cfg.pairwise_cipher_wpa2;
282 cmd_size += sizeof(struct host_cmd_tlv_pwk_cipher);
283 tlv += sizeof(struct host_cmd_tlv_pwk_cipher);
284 }
285 if (bss_cfg->wpa_cfg.group_cipher & VALID_CIPHER_BITMAP) {
286 gwk_cipher = (struct host_cmd_tlv_gwk_cipher *)tlv;
287 gwk_cipher->tlv.type = cpu_to_le16(TLV_TYPE_GWK_CIPHER);
288 gwk_cipher->tlv.len = cpu_to_le16(
289 sizeof(struct host_cmd_tlv_gwk_cipher) -
290 sizeof(struct host_cmd_tlv));
291 gwk_cipher->cipher = bss_cfg->wpa_cfg.group_cipher;
292 cmd_size += sizeof(struct host_cmd_tlv_gwk_cipher);
293 tlv += sizeof(struct host_cmd_tlv_gwk_cipher);
294 }
295 if (bss_cfg->wpa_cfg.length) {
296 passphrase = (struct host_cmd_tlv_passphrase *)tlv;
297 passphrase->tlv.type =
298 cpu_to_le16(TLV_TYPE_UAP_WPA_PASSPHRASE);
299 passphrase->tlv.len =
300 cpu_to_le16(bss_cfg->wpa_cfg.length);
301 memcpy(passphrase->passphrase,
302 bss_cfg->wpa_cfg.passphrase,
303 bss_cfg->wpa_cfg.length);
304 cmd_size += sizeof(struct host_cmd_tlv) +
305 bss_cfg->wpa_cfg.length;
306 tlv += sizeof(struct host_cmd_tlv) +
307 bss_cfg->wpa_cfg.length;
308 }
309 }
310 if ((bss_cfg->auth_mode <= WLAN_AUTH_SHARED_KEY) || 420 if ((bss_cfg->auth_mode <= WLAN_AUTH_SHARED_KEY) ||
311 (bss_cfg->auth_mode == MWIFIEX_AUTH_MODE_AUTO)) { 421 (bss_cfg->auth_mode == MWIFIEX_AUTH_MODE_AUTO)) {
312 auth_type = (struct host_cmd_tlv_auth_type *)tlv; 422 auth_type = (struct host_cmd_tlv_auth_type *)tlv;
@@ -330,6 +440,25 @@ mwifiex_uap_bss_param_prepare(u8 *tlv, void *cmd_buf, u16 *param_size)
330 tlv += sizeof(struct host_cmd_tlv_encrypt_protocol); 440 tlv += sizeof(struct host_cmd_tlv_encrypt_protocol);
331 } 441 }
332 442
443 if (bss_cfg->ht_cap.cap_info) {
444 htcap = (struct mwifiex_ie_types_htcap *)tlv;
445 htcap->header.type = cpu_to_le16(WLAN_EID_HT_CAPABILITY);
446 htcap->header.len =
447 cpu_to_le16(sizeof(struct ieee80211_ht_cap));
448 htcap->ht_cap.cap_info = bss_cfg->ht_cap.cap_info;
449 htcap->ht_cap.ampdu_params_info =
450 bss_cfg->ht_cap.ampdu_params_info;
451 memcpy(&htcap->ht_cap.mcs, &bss_cfg->ht_cap.mcs,
452 sizeof(struct ieee80211_mcs_info));
453 htcap->ht_cap.extended_ht_cap_info =
454 bss_cfg->ht_cap.extended_ht_cap_info;
455 htcap->ht_cap.tx_BF_cap_info = bss_cfg->ht_cap.tx_BF_cap_info;
456 htcap->ht_cap.antenna_selection_info =
457 bss_cfg->ht_cap.antenna_selection_info;
458 cmd_size += sizeof(struct mwifiex_ie_types_htcap);
459 tlv += sizeof(struct mwifiex_ie_types_htcap);
460 }
461
333 *param_size = cmd_size; 462 *param_size = cmd_size;
334 463
335 return 0; 464 return 0;
@@ -421,33 +550,3 @@ int mwifiex_uap_prepare_cmd(struct mwifiex_private *priv, u16 cmd_no,
421 550
422 return 0; 551 return 0;
423} 552}
424
425/* This function sets the RF channel for AP.
426 *
427 * This function populates channel information in AP config structure
428 * and sends command to configure channel information in AP.
429 */
430int mwifiex_uap_set_channel(struct mwifiex_private *priv, int channel)
431{
432 struct mwifiex_uap_bss_param *bss_cfg;
433 struct wiphy *wiphy = priv->wdev->wiphy;
434
435 bss_cfg = kzalloc(sizeof(struct mwifiex_uap_bss_param), GFP_KERNEL);
436 if (!bss_cfg)
437 return -ENOMEM;
438
439 mwifiex_set_sys_config_invalid_data(bss_cfg);
440 bss_cfg->band_cfg = BAND_CONFIG_MANUAL;
441 bss_cfg->channel = channel;
442
443 if (mwifiex_send_cmd_async(priv, HostCmd_CMD_UAP_SYS_CONFIG,
444 HostCmd_ACT_GEN_SET,
445 UAP_BSS_PARAMS_I, bss_cfg)) {
446 wiphy_err(wiphy, "Failed to set the uAP channel\n");
447 kfree(bss_cfg);
448 return -1;
449 }
450
451 kfree(bss_cfg);
452 return 0;
453}
diff --git a/drivers/net/wireless/rt2x00/Kconfig b/drivers/net/wireless/rt2x00/Kconfig
index 299c3879582d..c7548da6573d 100644
--- a/drivers/net/wireless/rt2x00/Kconfig
+++ b/drivers/net/wireless/rt2x00/Kconfig
@@ -99,6 +99,14 @@ config RT2800PCI_RT53XX
99 rt2800pci driver. 99 rt2800pci driver.
100 Supported chips: RT5390 100 Supported chips: RT5390
101 101
102config RT2800PCI_RT3290
103 bool "rt2800pci - Include support for rt3290 devices (EXPERIMENTAL)"
104 depends on EXPERIMENTAL
105 default y
106 ---help---
107 This adds support for rt3290 wireless chipset family to the
108 rt2800pci driver.
109 Supported chips: RT3290
102endif 110endif
103 111
104config RT2500USB 112config RT2500USB
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
index 1ca88cdc6ece..e252e9bafd0e 100644
--- a/drivers/net/wireless/rt2x00/rt2800.h
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -68,6 +68,7 @@
68#define RF3320 0x000b 68#define RF3320 0x000b
69#define RF3322 0x000c 69#define RF3322 0x000c
70#define RF3053 0x000d 70#define RF3053 0x000d
71#define RF3290 0x3290
71#define RF5360 0x5360 72#define RF5360 0x5360
72#define RF5370 0x5370 73#define RF5370 0x5370
73#define RF5372 0x5372 74#define RF5372 0x5372
@@ -117,6 +118,12 @@
117 * Registers. 118 * Registers.
118 */ 119 */
119 120
121
122/*
123 * MAC_CSR0_3290: MAC_CSR0 for RT3290 to identity MAC version number.
124 */
125#define MAC_CSR0_3290 0x0000
126
120/* 127/*
121 * E2PROM_CSR: PCI EEPROM control register. 128 * E2PROM_CSR: PCI EEPROM control register.
122 * RELOAD: Write 1 to reload eeprom content. 129 * RELOAD: Write 1 to reload eeprom content.
@@ -133,6 +140,150 @@
133#define E2PROM_CSR_RELOAD FIELD32(0x00000080) 140#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
134 141
135/* 142/*
143 * CMB_CTRL_CFG
144 */
145#define CMB_CTRL 0x0020
146#define AUX_OPT_BIT0 FIELD32(0x00000001)
147#define AUX_OPT_BIT1 FIELD32(0x00000002)
148#define AUX_OPT_BIT2 FIELD32(0x00000004)
149#define AUX_OPT_BIT3 FIELD32(0x00000008)
150#define AUX_OPT_BIT4 FIELD32(0x00000010)
151#define AUX_OPT_BIT5 FIELD32(0x00000020)
152#define AUX_OPT_BIT6 FIELD32(0x00000040)
153#define AUX_OPT_BIT7 FIELD32(0x00000080)
154#define AUX_OPT_BIT8 FIELD32(0x00000100)
155#define AUX_OPT_BIT9 FIELD32(0x00000200)
156#define AUX_OPT_BIT10 FIELD32(0x00000400)
157#define AUX_OPT_BIT11 FIELD32(0x00000800)
158#define AUX_OPT_BIT12 FIELD32(0x00001000)
159#define AUX_OPT_BIT13 FIELD32(0x00002000)
160#define AUX_OPT_BIT14 FIELD32(0x00004000)
161#define AUX_OPT_BIT15 FIELD32(0x00008000)
162#define LDO25_LEVEL FIELD32(0x00030000)
163#define LDO25_LARGEA FIELD32(0x00040000)
164#define LDO25_FRC_ON FIELD32(0x00080000)
165#define CMB_RSV FIELD32(0x00300000)
166#define XTAL_RDY FIELD32(0x00400000)
167#define PLL_LD FIELD32(0x00800000)
168#define LDO_CORE_LEVEL FIELD32(0x0F000000)
169#define LDO_BGSEL FIELD32(0x30000000)
170#define LDO3_EN FIELD32(0x40000000)
171#define LDO0_EN FIELD32(0x80000000)
172
173/*
174 * EFUSE_CSR_3290: RT3290 EEPROM
175 */
176#define EFUSE_CTRL_3290 0x0024
177
178/*
179 * EFUSE_DATA3 of 3290
180 */
181#define EFUSE_DATA3_3290 0x0028
182
183/*
184 * EFUSE_DATA2 of 3290
185 */
186#define EFUSE_DATA2_3290 0x002c
187
188/*
189 * EFUSE_DATA1 of 3290
190 */
191#define EFUSE_DATA1_3290 0x0030
192
193/*
194 * EFUSE_DATA0 of 3290
195 */
196#define EFUSE_DATA0_3290 0x0034
197
198/*
199 * OSC_CTRL_CFG
200 * Ring oscillator configuration
201 */
202#define OSC_CTRL 0x0038
203#define OSC_REF_CYCLE FIELD32(0x00001fff)
204#define OSC_RSV FIELD32(0x0000e000)
205#define OSC_CAL_CNT FIELD32(0x0fff0000)
206#define OSC_CAL_ACK FIELD32(0x10000000)
207#define OSC_CLK_32K_VLD FIELD32(0x20000000)
208#define OSC_CAL_REQ FIELD32(0x40000000)
209#define OSC_ROSC_EN FIELD32(0x80000000)
210
211/*
212 * COEX_CFG_0
213 */
214#define COEX_CFG0 0x0040
215#define COEX_CFG_ANT FIELD32(0xff000000)
216/*
217 * COEX_CFG_1
218 */
219#define COEX_CFG1 0x0044
220
221/*
222 * COEX_CFG_2
223 */
224#define COEX_CFG2 0x0048
225#define BT_COEX_CFG1 FIELD32(0xff000000)
226#define BT_COEX_CFG0 FIELD32(0x00ff0000)
227#define WL_COEX_CFG1 FIELD32(0x0000ff00)
228#define WL_COEX_CFG0 FIELD32(0x000000ff)
229/*
230 * PLL_CTRL_CFG
231 * PLL configuration register
232 */
233#define PLL_CTRL 0x0050
234#define PLL_RESERVED_INPUT1 FIELD32(0x000000ff)
235#define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00)
236#define PLL_CONTROL FIELD32(0x00070000)
237#define PLL_LPF_R1 FIELD32(0x00080000)
238#define PLL_LPF_C1_CTRL FIELD32(0x00300000)
239#define PLL_LPF_C2_CTRL FIELD32(0x00c00000)
240#define PLL_CP_CURRENT_CTRL FIELD32(0x03000000)
241#define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000)
242#define PLL_LOCK_CTRL FIELD32(0x70000000)
243#define PLL_VBGBK_EN FIELD32(0x80000000)
244
245
246/*
247 * WLAN_CTRL_CFG
248 * RT3290 wlan configuration
249 */
250#define WLAN_FUN_CTRL 0x0080
251#define WLAN_EN FIELD32(0x00000001)
252#define WLAN_CLK_EN FIELD32(0x00000002)
253#define WLAN_RSV1 FIELD32(0x00000004)
254#define WLAN_RESET FIELD32(0x00000008)
255#define PCIE_APP0_CLK_REQ FIELD32(0x00000010)
256#define FRC_WL_ANT_SET FIELD32(0x00000020)
257#define INV_TR_SW0 FIELD32(0x00000040)
258#define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100)
259#define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200)
260#define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400)
261#define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800)
262#define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000)
263#define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000)
264#define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000)
265#define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000)
266#define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00)
267#define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000)
268#define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000)
269#define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000)
270#define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000)
271#define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000)
272#define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000)
273#define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000)
274#define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000)
275#define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000)
276#define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000)
277#define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000)
278#define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000)
279#define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000)
280#define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000)
281#define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000)
282#define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000)
283#define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000)
284#define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000)
285
286/*
136 * AUX_CTRL: Aux/PCI-E related configuration 287 * AUX_CTRL: Aux/PCI-E related configuration
137 */ 288 */
138#define AUX_CTRL 0x10c 289#define AUX_CTRL 0x10c
@@ -1763,9 +1914,11 @@ struct mac_iveiv_entry {
1763/* 1914/*
1764 * BBP 3: RX Antenna 1915 * BBP 3: RX Antenna
1765 */ 1916 */
1766#define BBP3_RX_ADC FIELD8(0x03) 1917#define BBP3_RX_ADC FIELD8(0x03)
1767#define BBP3_RX_ANTENNA FIELD8(0x18) 1918#define BBP3_RX_ANTENNA FIELD8(0x18)
1768#define BBP3_HT40_MINUS FIELD8(0x20) 1919#define BBP3_HT40_MINUS FIELD8(0x20)
1920#define BBP3_ADC_MODE_SWITCH FIELD8(0x40)
1921#define BBP3_ADC_INIT_MODE FIELD8(0x80)
1769 1922
1770/* 1923/*
1771 * BBP 4: Bandwidth 1924 * BBP 4: Bandwidth
@@ -1775,6 +1928,14 @@ struct mac_iveiv_entry {
1775#define BBP4_MAC_IF_CTRL FIELD8(0x40) 1928#define BBP4_MAC_IF_CTRL FIELD8(0x40)
1776 1929
1777/* 1930/*
1931 * BBP 47: Bandwidth
1932 */
1933#define BBP47_TSSI_REPORT_SEL FIELD8(0x03)
1934#define BBP47_TSSI_UPDATE_REQ FIELD8(0x04)
1935#define BBP47_TSSI_TSSI_MODE FIELD8(0x18)
1936#define BBP47_TSSI_ADC6 FIELD8(0x80)
1937
1938/*
1778 * BBP 109 1939 * BBP 109
1779 */ 1940 */
1780#define BBP109_TX0_POWER FIELD8(0x0f) 1941#define BBP109_TX0_POWER FIELD8(0x0f)
@@ -1917,6 +2078,16 @@ struct mac_iveiv_entry {
1917#define RFCSR27_R4 FIELD8(0x40) 2078#define RFCSR27_R4 FIELD8(0x40)
1918 2079
1919/* 2080/*
2081 * RFCSR 29:
2082 */
2083#define RFCSR29_ADC6_TEST FIELD8(0x01)
2084#define RFCSR29_ADC6_INT_TEST FIELD8(0x02)
2085#define RFCSR29_RSSI_RESET FIELD8(0x04)
2086#define RFCSR29_RSSI_ON FIELD8(0x08)
2087#define RFCSR29_RSSI_RIP_CTRL FIELD8(0x30)
2088#define RFCSR29_RSSI_GAIN FIELD8(0xc0)
2089
2090/*
1920 * RFCSR 30: 2091 * RFCSR 30:
1921 */ 2092 */
1922#define RFCSR30_TX_H20M FIELD8(0x02) 2093#define RFCSR30_TX_H20M FIELD8(0x02)
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index 4d3747c3010b..068276ee8aff 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -354,16 +354,15 @@ int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
354 * of 4kb. Certain USB chipsets however require different firmware, 354 * of 4kb. Certain USB chipsets however require different firmware,
355 * which Ralink only provides attached to the original firmware 355 * which Ralink only provides attached to the original firmware
356 * file. Thus for USB devices, firmware files have a length 356 * file. Thus for USB devices, firmware files have a length
357 * which is a multiple of 4kb. 357 * which is a multiple of 4kb. The firmware for rt3290 chip also
358 * have a length which is a multiple of 4kb.
358 */ 359 */
359 if (rt2x00_is_usb(rt2x00dev)) { 360 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
360 fw_len = 4096; 361 fw_len = 4096;
361 multiple = true; 362 else
362 } else {
363 fw_len = 8192; 363 fw_len = 8192;
364 multiple = true;
365 }
366 364
365 multiple = true;
367 /* 366 /*
368 * Validate the firmware length 367 * Validate the firmware length
369 */ 368 */
@@ -415,7 +414,8 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
415 return -EBUSY; 414 return -EBUSY;
416 415
417 if (rt2x00_is_pci(rt2x00dev)) { 416 if (rt2x00_is_pci(rt2x00dev)) {
418 if (rt2x00_rt(rt2x00dev, RT3572) || 417 if (rt2x00_rt(rt2x00dev, RT3290) ||
418 rt2x00_rt(rt2x00dev, RT3572) ||
419 rt2x00_rt(rt2x00dev, RT5390) || 419 rt2x00_rt(rt2x00dev, RT5390) ||
420 rt2x00_rt(rt2x00dev, RT5392)) { 420 rt2x00_rt(rt2x00dev, RT5392)) {
421 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg); 421 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
@@ -851,8 +851,13 @@ int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
851{ 851{
852 u32 reg; 852 u32 reg;
853 853
854 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg); 854 if (rt2x00_rt(rt2x00dev, RT3290)) {
855 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2); 855 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
856 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
857 } else {
858 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
859 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
860 }
856} 861}
857EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 862EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
858 863
@@ -1935,9 +1940,54 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1935 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 1940 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1936} 1941}
1937 1942
1943#define RT3290_POWER_BOUND 0x27
1944#define RT3290_FREQ_OFFSET_BOUND 0x5f
1938#define RT5390_POWER_BOUND 0x27 1945#define RT5390_POWER_BOUND 0x27
1939#define RT5390_FREQ_OFFSET_BOUND 0x5f 1946#define RT5390_FREQ_OFFSET_BOUND 0x5f
1940 1947
1948static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
1949 struct ieee80211_conf *conf,
1950 struct rf_channel *rf,
1951 struct channel_info *info)
1952{
1953 u8 rfcsr;
1954
1955 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1956 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1957 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1958 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1959 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1960
1961 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1962 if (info->default_power1 > RT3290_POWER_BOUND)
1963 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT3290_POWER_BOUND);
1964 else
1965 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1966 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1967
1968 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1969 if (rt2x00dev->freq_offset > RT3290_FREQ_OFFSET_BOUND)
1970 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1971 RT3290_FREQ_OFFSET_BOUND);
1972 else
1973 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1974 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1975
1976 if (rf->channel <= 14) {
1977 if (rf->channel == 6)
1978 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
1979 else
1980 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
1981
1982 if (rf->channel >= 1 && rf->channel <= 6)
1983 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
1984 else if (rf->channel >= 7 && rf->channel <= 11)
1985 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
1986 else if (rf->channel >= 12 && rf->channel <= 14)
1987 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
1988 }
1989}
1990
1941static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 1991static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1942 struct ieee80211_conf *conf, 1992 struct ieee80211_conf *conf,
1943 struct rf_channel *rf, 1993 struct rf_channel *rf,
@@ -2036,15 +2086,6 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2036 } 2086 }
2037 } 2087 }
2038 } 2088 }
2039
2040 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2041 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2042 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2043 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2044
2045 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2046 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2047 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2048} 2089}
2049 2090
2050static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 2091static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
@@ -2054,7 +2095,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2054{ 2095{
2055 u32 reg; 2096 u32 reg;
2056 unsigned int tx_pin; 2097 unsigned int tx_pin;
2057 u8 bbp; 2098 u8 bbp, rfcsr;
2058 2099
2059 if (rf->channel <= 14) { 2100 if (rf->channel <= 14) {
2060 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1); 2101 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
@@ -2075,6 +2116,9 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2075 case RF3052: 2116 case RF3052:
2076 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); 2117 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2077 break; 2118 break;
2119 case RF3290:
2120 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2121 break;
2078 case RF5360: 2122 case RF5360:
2079 case RF5370: 2123 case RF5370:
2080 case RF5372: 2124 case RF5372:
@@ -2086,6 +2130,22 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2086 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 2130 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2087 } 2131 }
2088 2132
2133 if (rt2x00_rf(rt2x00dev, RF3290) ||
2134 rt2x00_rf(rt2x00dev, RF5360) ||
2135 rt2x00_rf(rt2x00dev, RF5370) ||
2136 rt2x00_rf(rt2x00dev, RF5372) ||
2137 rt2x00_rf(rt2x00dev, RF5390) ||
2138 rt2x00_rf(rt2x00dev, RF5392)) {
2139 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2140 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2141 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2142 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2143
2144 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2145 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2146 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2147 }
2148
2089 /* 2149 /*
2090 * Change BBP settings 2150 * Change BBP settings
2091 */ 2151 */
@@ -2566,6 +2626,7 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
2566 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2626 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2567 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2627 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2568 break; 2628 break;
2629 case RF3290:
2569 case RF5360: 2630 case RF5360:
2570 case RF5370: 2631 case RF5370:
2571 case RF5372: 2632 case RF5372:
@@ -2701,6 +2762,7 @@ static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2701 if (rt2x00_rt(rt2x00dev, RT3070) || 2762 if (rt2x00_rt(rt2x00dev, RT3070) ||
2702 rt2x00_rt(rt2x00dev, RT3071) || 2763 rt2x00_rt(rt2x00dev, RT3071) ||
2703 rt2x00_rt(rt2x00dev, RT3090) || 2764 rt2x00_rt(rt2x00dev, RT3090) ||
2765 rt2x00_rt(rt2x00dev, RT3290) ||
2704 rt2x00_rt(rt2x00dev, RT3390) || 2766 rt2x00_rt(rt2x00dev, RT3390) ||
2705 rt2x00_rt(rt2x00dev, RT5390) || 2767 rt2x00_rt(rt2x00dev, RT5390) ||
2706 rt2x00_rt(rt2x00dev, RT5392)) 2768 rt2x00_rt(rt2x00dev, RT5392))
@@ -2797,10 +2859,54 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2797 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 2859 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2798 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 2860 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2799 2861
2862 if (rt2x00_rt(rt2x00dev, RT3290)) {
2863 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
2864 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
2865 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
2866 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
2867 }
2868
2869 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
2870 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
2871 rt2x00_set_field32(&reg, LDO0_EN, 1);
2872 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
2873 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
2874 }
2875
2876 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
2877 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
2878 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
2879 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
2880 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
2881
2882 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
2883 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
2884 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
2885
2886 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
2887 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
2888 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
2889 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
2890 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
2891 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
2892
2893 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
2894 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
2895 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
2896 }
2897
2800 if (rt2x00_rt(rt2x00dev, RT3071) || 2898 if (rt2x00_rt(rt2x00dev, RT3071) ||
2801 rt2x00_rt(rt2x00dev, RT3090) || 2899 rt2x00_rt(rt2x00dev, RT3090) ||
2900 rt2x00_rt(rt2x00dev, RT3290) ||
2802 rt2x00_rt(rt2x00dev, RT3390)) { 2901 rt2x00_rt(rt2x00dev, RT3390)) {
2803 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 2902
2903 if (rt2x00_rt(rt2x00dev, RT3290))
2904 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
2905 0x00000404);
2906 else
2907 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
2908 0x00000400);
2909
2804 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 2910 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2805 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 2911 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2806 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 2912 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
@@ -3209,14 +3315,16 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3209 rt2800_wait_bbp_ready(rt2x00dev))) 3315 rt2800_wait_bbp_ready(rt2x00dev)))
3210 return -EACCES; 3316 return -EACCES;
3211 3317
3212 if (rt2x00_rt(rt2x00dev, RT5390) || 3318 if (rt2x00_rt(rt2x00dev, RT3290) ||
3213 rt2x00_rt(rt2x00dev, RT5392)) { 3319 rt2x00_rt(rt2x00dev, RT5390) ||
3320 rt2x00_rt(rt2x00dev, RT5392)) {
3214 rt2800_bbp_read(rt2x00dev, 4, &value); 3321 rt2800_bbp_read(rt2x00dev, 4, &value);
3215 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 3322 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3216 rt2800_bbp_write(rt2x00dev, 4, value); 3323 rt2800_bbp_write(rt2x00dev, 4, value);
3217 } 3324 }
3218 3325
3219 if (rt2800_is_305x_soc(rt2x00dev) || 3326 if (rt2800_is_305x_soc(rt2x00dev) ||
3327 rt2x00_rt(rt2x00dev, RT3290) ||
3220 rt2x00_rt(rt2x00dev, RT3572) || 3328 rt2x00_rt(rt2x00dev, RT3572) ||
3221 rt2x00_rt(rt2x00dev, RT5390) || 3329 rt2x00_rt(rt2x00dev, RT5390) ||
3222 rt2x00_rt(rt2x00dev, RT5392)) 3330 rt2x00_rt(rt2x00dev, RT5392))
@@ -3225,20 +3333,26 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3225 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 3333 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3226 rt2800_bbp_write(rt2x00dev, 66, 0x38); 3334 rt2800_bbp_write(rt2x00dev, 66, 0x38);
3227 3335
3228 if (rt2x00_rt(rt2x00dev, RT5390) || 3336 if (rt2x00_rt(rt2x00dev, RT3290) ||
3229 rt2x00_rt(rt2x00dev, RT5392)) 3337 rt2x00_rt(rt2x00dev, RT5390) ||
3338 rt2x00_rt(rt2x00dev, RT5392))
3230 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 3339 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3231 3340
3232 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 3341 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3233 rt2800_bbp_write(rt2x00dev, 69, 0x16); 3342 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3234 rt2800_bbp_write(rt2x00dev, 73, 0x12); 3343 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3235 } else if (rt2x00_rt(rt2x00dev, RT5390) || 3344 } else if (rt2x00_rt(rt2x00dev, RT3290) ||
3236 rt2x00_rt(rt2x00dev, RT5392)) { 3345 rt2x00_rt(rt2x00dev, RT5390) ||
3346 rt2x00_rt(rt2x00dev, RT5392)) {
3237 rt2800_bbp_write(rt2x00dev, 69, 0x12); 3347 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3238 rt2800_bbp_write(rt2x00dev, 73, 0x13); 3348 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3239 rt2800_bbp_write(rt2x00dev, 75, 0x46); 3349 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3240 rt2800_bbp_write(rt2x00dev, 76, 0x28); 3350 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3241 rt2800_bbp_write(rt2x00dev, 77, 0x59); 3351
3352 if (rt2x00_rt(rt2x00dev, RT3290))
3353 rt2800_bbp_write(rt2x00dev, 77, 0x58);
3354 else
3355 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3242 } else { 3356 } else {
3243 rt2800_bbp_write(rt2x00dev, 69, 0x12); 3357 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3244 rt2800_bbp_write(rt2x00dev, 73, 0x10); 3358 rt2800_bbp_write(rt2x00dev, 73, 0x10);
@@ -3263,23 +3377,33 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3263 rt2800_bbp_write(rt2x00dev, 81, 0x37); 3377 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3264 } 3378 }
3265 3379
3380 if (rt2x00_rt(rt2x00dev, RT3290)) {
3381 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
3382 rt2800_bbp_write(rt2x00dev, 79, 0x18);
3383 rt2800_bbp_write(rt2x00dev, 80, 0x09);
3384 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3385 }
3386
3266 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3387 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3267 if (rt2x00_rt(rt2x00dev, RT5390) || 3388 if (rt2x00_rt(rt2x00dev, RT3290) ||
3268 rt2x00_rt(rt2x00dev, RT5392)) 3389 rt2x00_rt(rt2x00dev, RT5390) ||
3390 rt2x00_rt(rt2x00dev, RT5392))
3269 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 3391 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3270 else 3392 else
3271 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 3393 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3272 3394
3273 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 3395 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
3274 rt2800_bbp_write(rt2x00dev, 84, 0x19); 3396 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3275 else if (rt2x00_rt(rt2x00dev, RT5390) || 3397 else if (rt2x00_rt(rt2x00dev, RT3290) ||
3276 rt2x00_rt(rt2x00dev, RT5392)) 3398 rt2x00_rt(rt2x00dev, RT5390) ||
3399 rt2x00_rt(rt2x00dev, RT5392))
3277 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 3400 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
3278 else 3401 else
3279 rt2800_bbp_write(rt2x00dev, 84, 0x99); 3402 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3280 3403
3281 if (rt2x00_rt(rt2x00dev, RT5390) || 3404 if (rt2x00_rt(rt2x00dev, RT3290) ||
3282 rt2x00_rt(rt2x00dev, RT5392)) 3405 rt2x00_rt(rt2x00dev, RT5390) ||
3406 rt2x00_rt(rt2x00dev, RT5392))
3283 rt2800_bbp_write(rt2x00dev, 86, 0x38); 3407 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3284 else 3408 else
3285 rt2800_bbp_write(rt2x00dev, 86, 0x00); 3409 rt2800_bbp_write(rt2x00dev, 86, 0x00);
@@ -3289,8 +3413,9 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3289 3413
3290 rt2800_bbp_write(rt2x00dev, 91, 0x04); 3414 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3291 3415
3292 if (rt2x00_rt(rt2x00dev, RT5390) || 3416 if (rt2x00_rt(rt2x00dev, RT3290) ||
3293 rt2x00_rt(rt2x00dev, RT5392)) 3417 rt2x00_rt(rt2x00dev, RT5390) ||
3418 rt2x00_rt(rt2x00dev, RT5392))
3294 rt2800_bbp_write(rt2x00dev, 92, 0x02); 3419 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3295 else 3420 else
3296 rt2800_bbp_write(rt2x00dev, 92, 0x00); 3421 rt2800_bbp_write(rt2x00dev, 92, 0x00);
@@ -3304,6 +3429,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3304 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 3429 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3305 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) || 3430 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3306 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) || 3431 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3432 rt2x00_rt(rt2x00dev, RT3290) ||
3307 rt2x00_rt(rt2x00dev, RT3572) || 3433 rt2x00_rt(rt2x00dev, RT3572) ||
3308 rt2x00_rt(rt2x00dev, RT5390) || 3434 rt2x00_rt(rt2x00dev, RT5390) ||
3309 rt2x00_rt(rt2x00dev, RT5392) || 3435 rt2x00_rt(rt2x00dev, RT5392) ||
@@ -3312,27 +3438,32 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3312 else 3438 else
3313 rt2800_bbp_write(rt2x00dev, 103, 0x00); 3439 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3314 3440
3315 if (rt2x00_rt(rt2x00dev, RT5390) || 3441 if (rt2x00_rt(rt2x00dev, RT3290) ||
3316 rt2x00_rt(rt2x00dev, RT5392)) 3442 rt2x00_rt(rt2x00dev, RT5390) ||
3443 rt2x00_rt(rt2x00dev, RT5392))
3317 rt2800_bbp_write(rt2x00dev, 104, 0x92); 3444 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3318 3445
3319 if (rt2800_is_305x_soc(rt2x00dev)) 3446 if (rt2800_is_305x_soc(rt2x00dev))
3320 rt2800_bbp_write(rt2x00dev, 105, 0x01); 3447 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3448 else if (rt2x00_rt(rt2x00dev, RT3290))
3449 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
3321 else if (rt2x00_rt(rt2x00dev, RT5390) || 3450 else if (rt2x00_rt(rt2x00dev, RT5390) ||
3322 rt2x00_rt(rt2x00dev, RT5392)) 3451 rt2x00_rt(rt2x00dev, RT5392))
3323 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 3452 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
3324 else 3453 else
3325 rt2800_bbp_write(rt2x00dev, 105, 0x05); 3454 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3326 3455
3327 if (rt2x00_rt(rt2x00dev, RT5390)) 3456 if (rt2x00_rt(rt2x00dev, RT3290) ||
3457 rt2x00_rt(rt2x00dev, RT5390))
3328 rt2800_bbp_write(rt2x00dev, 106, 0x03); 3458 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3329 else if (rt2x00_rt(rt2x00dev, RT5392)) 3459 else if (rt2x00_rt(rt2x00dev, RT5392))
3330 rt2800_bbp_write(rt2x00dev, 106, 0x12); 3460 rt2800_bbp_write(rt2x00dev, 106, 0x12);
3331 else 3461 else
3332 rt2800_bbp_write(rt2x00dev, 106, 0x35); 3462 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3333 3463
3334 if (rt2x00_rt(rt2x00dev, RT5390) || 3464 if (rt2x00_rt(rt2x00dev, RT3290) ||
3335 rt2x00_rt(rt2x00dev, RT5392)) 3465 rt2x00_rt(rt2x00dev, RT5390) ||
3466 rt2x00_rt(rt2x00dev, RT5392))
3336 rt2800_bbp_write(rt2x00dev, 128, 0x12); 3467 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3337 3468
3338 if (rt2x00_rt(rt2x00dev, RT5392)) { 3469 if (rt2x00_rt(rt2x00dev, RT5392)) {
@@ -3357,6 +3488,29 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3357 rt2800_bbp_write(rt2x00dev, 138, value); 3488 rt2800_bbp_write(rt2x00dev, 138, value);
3358 } 3489 }
3359 3490
3491 if (rt2x00_rt(rt2x00dev, RT3290)) {
3492 rt2800_bbp_write(rt2x00dev, 67, 0x24);
3493 rt2800_bbp_write(rt2x00dev, 143, 0x04);
3494 rt2800_bbp_write(rt2x00dev, 142, 0x99);
3495 rt2800_bbp_write(rt2x00dev, 150, 0x30);
3496 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
3497 rt2800_bbp_write(rt2x00dev, 152, 0x20);
3498 rt2800_bbp_write(rt2x00dev, 153, 0x34);
3499 rt2800_bbp_write(rt2x00dev, 154, 0x40);
3500 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
3501 rt2800_bbp_write(rt2x00dev, 253, 0x04);
3502
3503 rt2800_bbp_read(rt2x00dev, 47, &value);
3504 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
3505 rt2800_bbp_write(rt2x00dev, 47, value);
3506
3507 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
3508 rt2800_bbp_read(rt2x00dev, 3, &value);
3509 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
3510 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
3511 rt2800_bbp_write(rt2x00dev, 3, value);
3512 }
3513
3360 if (rt2x00_rt(rt2x00dev, RT5390) || 3514 if (rt2x00_rt(rt2x00dev, RT5390) ||
3361 rt2x00_rt(rt2x00dev, RT5392)) { 3515 rt2x00_rt(rt2x00dev, RT5392)) {
3362 int ant, div_mode; 3516 int ant, div_mode;
@@ -3489,6 +3643,7 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3489 if (!rt2x00_rt(rt2x00dev, RT3070) && 3643 if (!rt2x00_rt(rt2x00dev, RT3070) &&
3490 !rt2x00_rt(rt2x00dev, RT3071) && 3644 !rt2x00_rt(rt2x00dev, RT3071) &&
3491 !rt2x00_rt(rt2x00dev, RT3090) && 3645 !rt2x00_rt(rt2x00dev, RT3090) &&
3646 !rt2x00_rt(rt2x00dev, RT3290) &&
3492 !rt2x00_rt(rt2x00dev, RT3390) && 3647 !rt2x00_rt(rt2x00dev, RT3390) &&
3493 !rt2x00_rt(rt2x00dev, RT3572) && 3648 !rt2x00_rt(rt2x00dev, RT3572) &&
3494 !rt2x00_rt(rt2x00dev, RT5390) && 3649 !rt2x00_rt(rt2x00dev, RT5390) &&
@@ -3499,8 +3654,9 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3499 /* 3654 /*
3500 * Init RF calibration. 3655 * Init RF calibration.
3501 */ 3656 */
3502 if (rt2x00_rt(rt2x00dev, RT5390) || 3657 if (rt2x00_rt(rt2x00dev, RT3290) ||
3503 rt2x00_rt(rt2x00dev, RT5392)) { 3658 rt2x00_rt(rt2x00dev, RT5390) ||
3659 rt2x00_rt(rt2x00dev, RT5392)) {
3504 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr); 3660 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3505 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 3661 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3506 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 3662 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
@@ -3538,6 +3694,53 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3538 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 3694 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3539 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 3695 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3540 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 3696 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3697 } else if (rt2x00_rt(rt2x00dev, RT3290)) {
3698 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3699 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3700 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
3701 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
3702 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3703 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
3704 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
3705 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3706 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3707 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
3708 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3709 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
3710 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3711 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
3712 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
3713 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3714 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3715 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3716 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3717 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3718 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3719 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
3720 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3721 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3722 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3723 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3724 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3725 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3726 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
3727 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
3728 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3729 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3730 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3731 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3732 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3733 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
3734 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3735 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3736 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3737 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3738 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
3739 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3740 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3741 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
3742 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3743 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
3541 } else if (rt2x00_rt(rt2x00dev, RT3390)) { 3744 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3542 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 3745 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3543 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 3746 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
@@ -3946,6 +4149,12 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3946 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 4149 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3947 } 4150 }
3948 4151
4152 if (rt2x00_rt(rt2x00dev, RT3290)) {
4153 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4154 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4155 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
4156 }
4157
3949 if (rt2x00_rt(rt2x00dev, RT5390) || 4158 if (rt2x00_rt(rt2x00dev, RT5390) ||
3950 rt2x00_rt(rt2x00dev, RT5392)) { 4159 rt2x00_rt(rt2x00dev, RT5392)) {
3951 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr); 4160 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
@@ -4052,9 +4261,14 @@ EXPORT_SYMBOL_GPL(rt2800_disable_radio);
4052int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 4261int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
4053{ 4262{
4054 u32 reg; 4263 u32 reg;
4264 u16 efuse_ctrl_reg;
4055 4265
4056 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg); 4266 if (rt2x00_rt(rt2x00dev, RT3290))
4267 efuse_ctrl_reg = EFUSE_CTRL_3290;
4268 else
4269 efuse_ctrl_reg = EFUSE_CTRL;
4057 4270
4271 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
4058 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 4272 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
4059} 4273}
4060EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 4274EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
@@ -4062,27 +4276,44 @@ EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
4062static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 4276static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
4063{ 4277{
4064 u32 reg; 4278 u32 reg;
4065 4279 u16 efuse_ctrl_reg;
4280 u16 efuse_data0_reg;
4281 u16 efuse_data1_reg;
4282 u16 efuse_data2_reg;
4283 u16 efuse_data3_reg;
4284
4285 if (rt2x00_rt(rt2x00dev, RT3290)) {
4286 efuse_ctrl_reg = EFUSE_CTRL_3290;
4287 efuse_data0_reg = EFUSE_DATA0_3290;
4288 efuse_data1_reg = EFUSE_DATA1_3290;
4289 efuse_data2_reg = EFUSE_DATA2_3290;
4290 efuse_data3_reg = EFUSE_DATA3_3290;
4291 } else {
4292 efuse_ctrl_reg = EFUSE_CTRL;
4293 efuse_data0_reg = EFUSE_DATA0;
4294 efuse_data1_reg = EFUSE_DATA1;
4295 efuse_data2_reg = EFUSE_DATA2;
4296 efuse_data3_reg = EFUSE_DATA3;
4297 }
4066 mutex_lock(&rt2x00dev->csr_mutex); 4298 mutex_lock(&rt2x00dev->csr_mutex);
4067 4299
4068 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg); 4300 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
4069 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i); 4301 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
4070 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0); 4302 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
4071 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1); 4303 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
4072 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg); 4304 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
4073 4305
4074 /* Wait until the EEPROM has been loaded */ 4306 /* Wait until the EEPROM has been loaded */
4075 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg); 4307 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
4076
4077 /* Apparently the data is read from end to start */ 4308 /* Apparently the data is read from end to start */
4078 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, &reg); 4309 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
4079 /* The returned value is in CPU order, but eeprom is le */ 4310 /* The returned value is in CPU order, but eeprom is le */
4080 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); 4311 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
4081 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, &reg); 4312 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
4082 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); 4313 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
4083 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, &reg); 4314 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
4084 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); 4315 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
4085 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, &reg); 4316 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
4086 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); 4317 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
4087 4318
4088 mutex_unlock(&rt2x00dev->csr_mutex); 4319 mutex_unlock(&rt2x00dev->csr_mutex);
@@ -4244,9 +4475,14 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4244 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 4475 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4245 * RT53xx: defined in "EEPROM_CHIP_ID" field 4476 * RT53xx: defined in "EEPROM_CHIP_ID" field
4246 */ 4477 */
4247 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg); 4478 if (rt2x00_rt(rt2x00dev, RT3290))
4248 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 || 4479 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
4249 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392) 4480 else
4481 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
4482
4483 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
4484 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
4485 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
4250 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value); 4486 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4251 else 4487 else
4252 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 4488 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
@@ -4261,6 +4497,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4261 case RT3070: 4497 case RT3070:
4262 case RT3071: 4498 case RT3071:
4263 case RT3090: 4499 case RT3090:
4500 case RT3290:
4264 case RT3390: 4501 case RT3390:
4265 case RT3572: 4502 case RT3572:
4266 case RT5390: 4503 case RT5390:
@@ -4281,6 +4518,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4281 case RF3021: 4518 case RF3021:
4282 case RF3022: 4519 case RF3022:
4283 case RF3052: 4520 case RF3052:
4521 case RF3290:
4284 case RF3320: 4522 case RF3320:
4285 case RF5360: 4523 case RF5360:
4286 case RF5370: 4524 case RF5370:
@@ -4597,6 +4835,7 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4597 rt2x00_rf(rt2x00dev, RF2020) || 4835 rt2x00_rf(rt2x00dev, RF2020) ||
4598 rt2x00_rf(rt2x00dev, RF3021) || 4836 rt2x00_rf(rt2x00dev, RF3021) ||
4599 rt2x00_rf(rt2x00dev, RF3022) || 4837 rt2x00_rf(rt2x00dev, RF3022) ||
4838 rt2x00_rf(rt2x00dev, RF3290) ||
4600 rt2x00_rf(rt2x00dev, RF3320) || 4839 rt2x00_rf(rt2x00dev, RF3320) ||
4601 rt2x00_rf(rt2x00dev, RF5360) || 4840 rt2x00_rf(rt2x00dev, RF5360) ||
4602 rt2x00_rf(rt2x00dev, RF5370) || 4841 rt2x00_rf(rt2x00dev, RF5370) ||
@@ -4685,6 +4924,7 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4685 case RF3022: 4924 case RF3022:
4686 case RF3320: 4925 case RF3320:
4687 case RF3052: 4926 case RF3052:
4927 case RF3290:
4688 case RF5360: 4928 case RF5360:
4689 case RF5370: 4929 case RF5370:
4690 case RF5372: 4930 case RF5372:
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index 206158b67426..dd436125fe3d 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -280,7 +280,13 @@ static void rt2800pci_stop_queue(struct data_queue *queue)
280 */ 280 */
281static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) 281static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
282{ 282{
283 return FIRMWARE_RT2860; 283 /*
284 * Chip rt3290 use specific 4KB firmware named rt3290.bin.
285 */
286 if (rt2x00_rt(rt2x00dev, RT3290))
287 return FIRMWARE_RT3290;
288 else
289 return FIRMWARE_RT2860;
284} 290}
285 291
286static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev, 292static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
@@ -974,6 +980,66 @@ static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
974 return rt2800_validate_eeprom(rt2x00dev); 980 return rt2800_validate_eeprom(rt2x00dev);
975} 981}
976 982
983static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
984{
985 u32 reg;
986 int i, count;
987
988 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
989 if ((rt2x00_get_field32(reg, WLAN_EN) == 1))
990 return 0;
991
992 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
993 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
994 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
995 rt2x00_set_field32(&reg, WLAN_EN, 1);
996 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
997
998 udelay(REGISTER_BUSY_DELAY);
999
1000 count = 0;
1001 do {
1002 /*
1003 * Check PLL_LD & XTAL_RDY.
1004 */
1005 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1006 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
1007 if ((rt2x00_get_field32(reg, PLL_LD) == 1) &&
1008 (rt2x00_get_field32(reg, XTAL_RDY) == 1))
1009 break;
1010 udelay(REGISTER_BUSY_DELAY);
1011 }
1012
1013 if (i >= REGISTER_BUSY_COUNT) {
1014
1015 if (count >= 10)
1016 return -EIO;
1017
1018 rt2800_register_write(rt2x00dev, 0x58, 0x018);
1019 udelay(REGISTER_BUSY_DELAY);
1020 rt2800_register_write(rt2x00dev, 0x58, 0x418);
1021 udelay(REGISTER_BUSY_DELAY);
1022 rt2800_register_write(rt2x00dev, 0x58, 0x618);
1023 udelay(REGISTER_BUSY_DELAY);
1024 count++;
1025 } else {
1026 count = 0;
1027 }
1028
1029 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1030 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
1031 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
1032 rt2x00_set_field32(&reg, WLAN_RESET, 1);
1033 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
1034 udelay(10);
1035 rt2x00_set_field32(&reg, WLAN_RESET, 0);
1036 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
1037 udelay(10);
1038 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
1039 } while (count != 0);
1040
1041 return 0;
1042}
977static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev) 1043static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
978{ 1044{
979 int retval; 1045 int retval;
@@ -997,6 +1063,17 @@ static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
997 return retval; 1063 return retval;
998 1064
999 /* 1065 /*
1066 * In probe phase call rt2800_enable_wlan_rt3290 to enable wlan
1067 * clk for rt3290. That avoid the MCU fail in start phase.
1068 */
1069 if (rt2x00_rt(rt2x00dev, RT3290)) {
1070 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
1071
1072 if (retval)
1073 return retval;
1074 }
1075
1076 /*
1000 * This device has multiple filters for control frames 1077 * This device has multiple filters for control frames
1001 * and has a separate filter for PS Poll frames. 1078 * and has a separate filter for PS Poll frames.
1002 */ 1079 */
@@ -1175,6 +1252,9 @@ static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1175 { PCI_DEVICE(0x1432, 0x7768) }, 1252 { PCI_DEVICE(0x1432, 0x7768) },
1176 { PCI_DEVICE(0x1462, 0x891a) }, 1253 { PCI_DEVICE(0x1462, 0x891a) },
1177 { PCI_DEVICE(0x1a3b, 0x1059) }, 1254 { PCI_DEVICE(0x1a3b, 0x1059) },
1255#ifdef CONFIG_RT2800PCI_RT3290
1256 { PCI_DEVICE(0x1814, 0x3290) },
1257#endif
1178#ifdef CONFIG_RT2800PCI_RT33XX 1258#ifdef CONFIG_RT2800PCI_RT33XX
1179 { PCI_DEVICE(0x1814, 0x3390) }, 1259 { PCI_DEVICE(0x1814, 0x3390) },
1180#endif 1260#endif
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.h b/drivers/net/wireless/rt2x00/rt2800pci.h
index 70e050d904c8..ab22a087c50d 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.h
+++ b/drivers/net/wireless/rt2x00/rt2800pci.h
@@ -47,6 +47,7 @@
47 * 8051 firmware image. 47 * 8051 firmware image.
48 */ 48 */
49#define FIRMWARE_RT2860 "rt2860.bin" 49#define FIRMWARE_RT2860 "rt2860.bin"
50#define FIRMWARE_RT3290 "rt3290.bin"
50#define FIRMWARE_IMAGE_BASE 0x2000 51#define FIRMWARE_IMAGE_BASE 0x2000
51 52
52/* 53/*
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
index 20a504072895..6cf336595e25 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.c
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -971,6 +971,7 @@ static struct usb_device_id rt2800usb_device_table[] = {
971 { USB_DEVICE(0x0411, 0x015d) }, 971 { USB_DEVICE(0x0411, 0x015d) },
972 { USB_DEVICE(0x0411, 0x016f) }, 972 { USB_DEVICE(0x0411, 0x016f) },
973 { USB_DEVICE(0x0411, 0x01a2) }, 973 { USB_DEVICE(0x0411, 0x01a2) },
974 { USB_DEVICE(0x0411, 0x01ee) },
974 /* Corega */ 975 /* Corega */
975 { USB_DEVICE(0x07aa, 0x002f) }, 976 { USB_DEVICE(0x07aa, 0x002f) },
976 { USB_DEVICE(0x07aa, 0x003c) }, 977 { USB_DEVICE(0x07aa, 0x003c) },
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index 8f754025b06e..8afb546c2b2d 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -187,6 +187,7 @@ struct rt2x00_chip {
187#define RT3070 0x3070 187#define RT3070 0x3070
188#define RT3071 0x3071 188#define RT3071 0x3071
189#define RT3090 0x3090 /* 2.4GHz PCIe */ 189#define RT3090 0x3090 /* 2.4GHz PCIe */
190#define RT3290 0x3290
190#define RT3390 0x3390 191#define RT3390 0x3390
191#define RT3572 0x3572 192#define RT3572 0x3572
192#define RT3593 0x3593 193#define RT3593 0x3593
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.c b/drivers/net/wireless/rt2x00/rt2x00pci.c
index 0a4653a92cab..a0c8caef3b0a 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.c
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.c
@@ -256,6 +256,7 @@ int rt2x00pci_probe(struct pci_dev *pci_dev, const struct rt2x00_ops *ops)
256 struct ieee80211_hw *hw; 256 struct ieee80211_hw *hw;
257 struct rt2x00_dev *rt2x00dev; 257 struct rt2x00_dev *rt2x00dev;
258 int retval; 258 int retval;
259 u16 chip;
259 260
260 retval = pci_enable_device(pci_dev); 261 retval = pci_enable_device(pci_dev);
261 if (retval) { 262 if (retval) {
@@ -305,6 +306,14 @@ int rt2x00pci_probe(struct pci_dev *pci_dev, const struct rt2x00_ops *ops)
305 if (retval) 306 if (retval)
306 goto exit_free_device; 307 goto exit_free_device;
307 308
309 /*
310 * Because rt3290 chip use different efuse offset to read efuse data.
311 * So before read efuse it need to indicate it is the
312 * rt3290 or not.
313 */
314 pci_read_config_word(pci_dev, PCI_DEVICE_ID, &chip);
315 rt2x00dev->chip.rt = chip;
316
308 retval = rt2x00lib_probe_dev(rt2x00dev); 317 retval = rt2x00lib_probe_dev(rt2x00dev);
309 if (retval) 318 if (retval)
310 goto exit_free_reg; 319 goto exit_free_reg;
diff --git a/drivers/net/wireless/rtl818x/rtl8180/dev.c b/drivers/net/wireless/rtl818x/rtl8180/dev.c
index 2bebcb71a1e9..3b505395d869 100644
--- a/drivers/net/wireless/rtl818x/rtl8180/dev.c
+++ b/drivers/net/wireless/rtl818x/rtl8180/dev.c
@@ -47,6 +47,8 @@ static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
47 { PCI_DEVICE(0x1799, 0x6001) }, 47 { PCI_DEVICE(0x1799, 0x6001) },
48 { PCI_DEVICE(0x1799, 0x6020) }, 48 { PCI_DEVICE(0x1799, 0x6020) },
49 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) }, 49 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
50 { PCI_DEVICE(0x1186, 0x3301) },
51 { PCI_DEVICE(0x1432, 0x7106) },
50 { } 52 { }
51}; 53};
52 54
diff --git a/drivers/net/wireless/rtlwifi/cam.c b/drivers/net/wireless/rtlwifi/cam.c
index 2d1a8220d5c0..5b4b4d4eaf9e 100644
--- a/drivers/net/wireless/rtlwifi/cam.c
+++ b/drivers/net/wireless/rtlwifi/cam.c
@@ -128,7 +128,7 @@ u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
128 u32 us_config; 128 u32 us_config;
129 struct rtl_priv *rtlpriv = rtl_priv(hw); 129 struct rtl_priv *rtlpriv = rtl_priv(hw);
130 130
131 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 131 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
132 "EntryNo:%x, ulKeyId=%x, ulEncAlg=%x, ulUseDK=%x MacAddr %pM\n", 132 "EntryNo:%x, ulKeyId=%x, ulEncAlg=%x, ulUseDK=%x MacAddr %pM\n",
133 ul_entry_idx, ul_key_id, ul_enc_alg, 133 ul_entry_idx, ul_key_id, ul_enc_alg,
134 ul_default_key, mac_addr); 134 ul_default_key, mac_addr);
@@ -342,7 +342,8 @@ void rtl_cam_del_entry(struct ieee80211_hw *hw, u8 *sta_addr)
342 /* Remove from HW Security CAM */ 342 /* Remove from HW Security CAM */
343 memset(rtlpriv->sec.hwsec_cam_sta_addr[i], 0, ETH_ALEN); 343 memset(rtlpriv->sec.hwsec_cam_sta_addr[i], 0, ETH_ALEN);
344 rtlpriv->sec.hwsec_cam_bitmap &= ~(BIT(0) << i); 344 rtlpriv->sec.hwsec_cam_bitmap &= ~(BIT(0) << i);
345 pr_info("&&&&&&&&&del entry %d\n", i); 345 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
346 "del CAM entry %d\n", i);
346 } 347 }
347 } 348 }
348 return; 349 return;
diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c
index 82d3afcfecd1..31138fdad1f7 100644
--- a/drivers/net/wireless/rtlwifi/pci.c
+++ b/drivers/net/wireless/rtlwifi/pci.c
@@ -1273,17 +1273,18 @@ int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1273 *after reset, release previous pending packet, 1273 *after reset, release previous pending packet,
1274 *and force the tx idx to the first one 1274 *and force the tx idx to the first one
1275 */ 1275 */
1276 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1277 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1276 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1278 if (rtlpci->tx_ring[i].desc) { 1277 if (rtlpci->tx_ring[i].desc) {
1279 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i]; 1278 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1280 1279
1281 while (skb_queue_len(&ring->queue)) { 1280 while (skb_queue_len(&ring->queue)) {
1282 struct rtl_tx_desc *entry = 1281 struct rtl_tx_desc *entry;
1283 &ring->desc[ring->idx]; 1282 struct sk_buff *skb;
1284 struct sk_buff *skb =
1285 __skb_dequeue(&ring->queue);
1286 1283
1284 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock,
1285 flags);
1286 entry = &ring->desc[ring->idx];
1287 skb = __skb_dequeue(&ring->queue);
1287 pci_unmap_single(rtlpci->pdev, 1288 pci_unmap_single(rtlpci->pdev,
1288 rtlpriv->cfg->ops-> 1289 rtlpriv->cfg->ops->
1289 get_desc((u8 *) 1290 get_desc((u8 *)
@@ -1291,15 +1292,15 @@ int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1291 true, 1292 true,
1292 HW_DESC_TXBUFF_ADDR), 1293 HW_DESC_TXBUFF_ADDR),
1293 skb->len, PCI_DMA_TODEVICE); 1294 skb->len, PCI_DMA_TODEVICE);
1294 kfree_skb(skb);
1295 ring->idx = (ring->idx + 1) % ring->entries; 1295 ring->idx = (ring->idx + 1) % ring->entries;
1296 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1297 flags);
1298 kfree_skb(skb);
1296 } 1299 }
1297 ring->idx = 0; 1300 ring->idx = 0;
1298 } 1301 }
1299 } 1302 }
1300 1303
1301 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1302
1303 return 0; 1304 return 0;
1304} 1305}
1305 1306
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/phy.c b/drivers/net/wireless/rtlwifi/rtl8192se/phy.c
index 8d7099bc472c..b917a2a3caf7 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/phy.c
@@ -1247,6 +1247,9 @@ static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1247 /* Read HT 40 OFDM TX power */ 1247 /* Read HT 40 OFDM TX power */
1248 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index]; 1248 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
1249 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index]; 1249 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
1250 } else {
1251 ofdmpowerLevel[0] = 0;
1252 ofdmpowerLevel[1] = 0;
1250 } 1253 }
1251} 1254}
1252 1255
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/sw.c b/drivers/net/wireless/rtlwifi/rtl8192se/sw.c
index 730bcc919529..ad4b4803482d 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/sw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/sw.c
@@ -29,7 +29,6 @@
29 29
30#include "../wifi.h" 30#include "../wifi.h"
31#include "../core.h" 31#include "../core.h"
32#include "../pci.h"
33#include "../base.h" 32#include "../base.h"
34#include "../pci.h" 33#include "../pci.h"
35#include "reg.h" 34#include "reg.h"
diff --git a/drivers/net/wireless/ti/wl1251/cmd.c b/drivers/net/wireless/ti/wl1251/cmd.c
index d14d69d733a0..6822b845efc1 100644
--- a/drivers/net/wireless/ti/wl1251/cmd.c
+++ b/drivers/net/wireless/ti/wl1251/cmd.c
@@ -277,15 +277,6 @@ int wl1251_cmd_join(struct wl1251 *wl, u8 bss_type, u8 channel,
277 join->rx_config_options = wl->rx_config; 277 join->rx_config_options = wl->rx_config;
278 join->rx_filter_options = wl->rx_filter; 278 join->rx_filter_options = wl->rx_filter;
279 279
280 /*
281 * FIXME: disable temporarily all filters because after commit
282 * 9cef8737 "mac80211: fix managed mode BSSID handling" broke
283 * association. The filter logic needs to be implemented properly
284 * and once that is done, this hack can be removed.
285 */
286 join->rx_config_options = 0;
287 join->rx_filter_options = WL1251_DEFAULT_RX_FILTER;
288
289 join->basic_rate_set = RATE_MASK_1MBPS | RATE_MASK_2MBPS | 280 join->basic_rate_set = RATE_MASK_1MBPS | RATE_MASK_2MBPS |
290 RATE_MASK_5_5MBPS | RATE_MASK_11MBPS; 281 RATE_MASK_5_5MBPS | RATE_MASK_11MBPS;
291 282
diff --git a/drivers/net/wireless/ti/wl1251/main.c b/drivers/net/wireless/ti/wl1251/main.c
index d1afb8e3b2ef..3118c425bcf1 100644
--- a/drivers/net/wireless/ti/wl1251/main.c
+++ b/drivers/net/wireless/ti/wl1251/main.c
@@ -334,6 +334,12 @@ static int wl1251_join(struct wl1251 *wl, u8 bss_type, u8 channel,
334 if (ret < 0) 334 if (ret < 0)
335 goto out; 335 goto out;
336 336
337 /*
338 * Join command applies filters, and if we are not associated,
339 * BSSID filter must be disabled for association to work.
340 */
341 if (is_zero_ether_addr(wl->bssid))
342 wl->rx_config &= ~CFG_BSSID_FILTER_EN;
337 343
338 ret = wl1251_cmd_join(wl, bss_type, channel, beacon_interval, 344 ret = wl1251_cmd_join(wl, bss_type, channel, beacon_interval,
339 dtim_period); 345 dtim_period);
@@ -348,33 +354,6 @@ out:
348 return ret; 354 return ret;
349} 355}
350 356
351static void wl1251_filter_work(struct work_struct *work)
352{
353 struct wl1251 *wl =
354 container_of(work, struct wl1251, filter_work);
355 int ret;
356
357 mutex_lock(&wl->mutex);
358
359 if (wl->state == WL1251_STATE_OFF)
360 goto out;
361
362 ret = wl1251_ps_elp_wakeup(wl);
363 if (ret < 0)
364 goto out;
365
366 ret = wl1251_join(wl, wl->bss_type, wl->channel, wl->beacon_int,
367 wl->dtim_period);
368 if (ret < 0)
369 goto out_sleep;
370
371out_sleep:
372 wl1251_ps_elp_sleep(wl);
373
374out:
375 mutex_unlock(&wl->mutex);
376}
377
378static void wl1251_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 357static void wl1251_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
379{ 358{
380 struct wl1251 *wl = hw->priv; 359 struct wl1251 *wl = hw->priv;
@@ -478,7 +457,6 @@ static void wl1251_op_stop(struct ieee80211_hw *hw)
478 457
479 cancel_work_sync(&wl->irq_work); 458 cancel_work_sync(&wl->irq_work);
480 cancel_work_sync(&wl->tx_work); 459 cancel_work_sync(&wl->tx_work);
481 cancel_work_sync(&wl->filter_work);
482 cancel_delayed_work_sync(&wl->elp_work); 460 cancel_delayed_work_sync(&wl->elp_work);
483 461
484 mutex_lock(&wl->mutex); 462 mutex_lock(&wl->mutex);
@@ -681,13 +659,15 @@ out:
681 FIF_FCSFAIL | \ 659 FIF_FCSFAIL | \
682 FIF_BCN_PRBRESP_PROMISC | \ 660 FIF_BCN_PRBRESP_PROMISC | \
683 FIF_CONTROL | \ 661 FIF_CONTROL | \
684 FIF_OTHER_BSS) 662 FIF_OTHER_BSS | \
663 FIF_PROBE_REQ)
685 664
686static void wl1251_op_configure_filter(struct ieee80211_hw *hw, 665static void wl1251_op_configure_filter(struct ieee80211_hw *hw,
687 unsigned int changed, 666 unsigned int changed,
688 unsigned int *total,u64 multicast) 667 unsigned int *total,u64 multicast)
689{ 668{
690 struct wl1251 *wl = hw->priv; 669 struct wl1251 *wl = hw->priv;
670 int ret;
691 671
692 wl1251_debug(DEBUG_MAC80211, "mac80211 configure filter"); 672 wl1251_debug(DEBUG_MAC80211, "mac80211 configure filter");
693 673
@@ -698,7 +678,7 @@ static void wl1251_op_configure_filter(struct ieee80211_hw *hw,
698 /* no filters which we support changed */ 678 /* no filters which we support changed */
699 return; 679 return;
700 680
701 /* FIXME: wl->rx_config and wl->rx_filter are not protected */ 681 mutex_lock(&wl->mutex);
702 682
703 wl->rx_config = WL1251_DEFAULT_RX_CONFIG; 683 wl->rx_config = WL1251_DEFAULT_RX_CONFIG;
704 wl->rx_filter = WL1251_DEFAULT_RX_FILTER; 684 wl->rx_filter = WL1251_DEFAULT_RX_FILTER;
@@ -721,15 +701,25 @@ static void wl1251_op_configure_filter(struct ieee80211_hw *hw,
721 } 701 }
722 if (*total & FIF_CONTROL) 702 if (*total & FIF_CONTROL)
723 wl->rx_filter |= CFG_RX_CTL_EN; 703 wl->rx_filter |= CFG_RX_CTL_EN;
724 if (*total & FIF_OTHER_BSS) 704 if (*total & FIF_OTHER_BSS || is_zero_ether_addr(wl->bssid))
725 wl->rx_filter &= ~CFG_BSSID_FILTER_EN; 705 wl->rx_config &= ~CFG_BSSID_FILTER_EN;
706 if (*total & FIF_PROBE_REQ)
707 wl->rx_filter |= CFG_RX_PREQ_EN;
726 708
727 /* 709 if (wl->state == WL1251_STATE_OFF)
728 * FIXME: workqueues need to be properly cancelled on stop(), for 710 goto out;
729 * now let's just disable changing the filter settings. They will 711
730 * be updated any on config(). 712 ret = wl1251_ps_elp_wakeup(wl);
731 */ 713 if (ret < 0)
732 /* schedule_work(&wl->filter_work); */ 714 goto out;
715
716 /* send filters to firmware */
717 wl1251_acx_rx_config(wl, wl->rx_config, wl->rx_filter);
718
719 wl1251_ps_elp_sleep(wl);
720
721out:
722 mutex_unlock(&wl->mutex);
733} 723}
734 724
735/* HW encryption */ 725/* HW encryption */
@@ -1390,7 +1380,6 @@ struct ieee80211_hw *wl1251_alloc_hw(void)
1390 1380
1391 skb_queue_head_init(&wl->tx_queue); 1381 skb_queue_head_init(&wl->tx_queue);
1392 1382
1393 INIT_WORK(&wl->filter_work, wl1251_filter_work);
1394 INIT_DELAYED_WORK(&wl->elp_work, wl1251_elp_work); 1383 INIT_DELAYED_WORK(&wl->elp_work, wl1251_elp_work);
1395 wl->channel = WL1251_DEFAULT_CHANNEL; 1384 wl->channel = WL1251_DEFAULT_CHANNEL;
1396 wl->scanning = false; 1385 wl->scanning = false;
diff --git a/drivers/net/wireless/ti/wl1251/wl1251.h b/drivers/net/wireless/ti/wl1251/wl1251.h
index 9d8f5816c6f9..fd02060038de 100644
--- a/drivers/net/wireless/ti/wl1251/wl1251.h
+++ b/drivers/net/wireless/ti/wl1251/wl1251.h
@@ -315,7 +315,6 @@ struct wl1251 {
315 bool tx_queue_stopped; 315 bool tx_queue_stopped;
316 316
317 struct work_struct tx_work; 317 struct work_struct tx_work;
318 struct work_struct filter_work;
319 318
320 /* Pending TX frames */ 319 /* Pending TX frames */
321 struct sk_buff *tx_frames[16]; 320 struct sk_buff *tx_frames[16];
diff --git a/drivers/net/wireless/ti/wl12xx/cmd.c b/drivers/net/wireless/ti/wl12xx/cmd.c
index 50ba7480b790..30be784a40d8 100644
--- a/drivers/net/wireless/ti/wl12xx/cmd.c
+++ b/drivers/net/wireless/ti/wl12xx/cmd.c
@@ -174,7 +174,7 @@ int wl1271_cmd_radio_parms(struct wl1271 *wl)
174 struct wl1271_nvs_file *nvs = (struct wl1271_nvs_file *)wl->nvs; 174 struct wl1271_nvs_file *nvs = (struct wl1271_nvs_file *)wl->nvs;
175 struct wl1271_radio_parms_cmd *radio_parms; 175 struct wl1271_radio_parms_cmd *radio_parms;
176 struct wl1271_ini_general_params *gp = &nvs->general_params; 176 struct wl1271_ini_general_params *gp = &nvs->general_params;
177 int ret; 177 int ret, fem_idx;
178 178
179 if (!wl->nvs) 179 if (!wl->nvs)
180 return -ENODEV; 180 return -ENODEV;
@@ -185,11 +185,13 @@ int wl1271_cmd_radio_parms(struct wl1271 *wl)
185 185
186 radio_parms->test.id = TEST_CMD_INI_FILE_RADIO_PARAM; 186 radio_parms->test.id = TEST_CMD_INI_FILE_RADIO_PARAM;
187 187
188 fem_idx = WL12XX_FEM_TO_NVS_ENTRY(gp->tx_bip_fem_manufacturer);
189
188 /* 2.4GHz parameters */ 190 /* 2.4GHz parameters */
189 memcpy(&radio_parms->static_params_2, &nvs->stat_radio_params_2, 191 memcpy(&radio_parms->static_params_2, &nvs->stat_radio_params_2,
190 sizeof(struct wl1271_ini_band_params_2)); 192 sizeof(struct wl1271_ini_band_params_2));
191 memcpy(&radio_parms->dyn_params_2, 193 memcpy(&radio_parms->dyn_params_2,
192 &nvs->dyn_radio_params_2[gp->tx_bip_fem_manufacturer].params, 194 &nvs->dyn_radio_params_2[fem_idx].params,
193 sizeof(struct wl1271_ini_fem_params_2)); 195 sizeof(struct wl1271_ini_fem_params_2));
194 196
195 /* 5GHz parameters */ 197 /* 5GHz parameters */
@@ -197,7 +199,7 @@ int wl1271_cmd_radio_parms(struct wl1271 *wl)
197 &nvs->stat_radio_params_5, 199 &nvs->stat_radio_params_5,
198 sizeof(struct wl1271_ini_band_params_5)); 200 sizeof(struct wl1271_ini_band_params_5));
199 memcpy(&radio_parms->dyn_params_5, 201 memcpy(&radio_parms->dyn_params_5,
200 &nvs->dyn_radio_params_5[gp->tx_bip_fem_manufacturer].params, 202 &nvs->dyn_radio_params_5[fem_idx].params,
201 sizeof(struct wl1271_ini_fem_params_5)); 203 sizeof(struct wl1271_ini_fem_params_5));
202 204
203 wl1271_dump(DEBUG_CMD, "TEST_CMD_INI_FILE_RADIO_PARAM: ", 205 wl1271_dump(DEBUG_CMD, "TEST_CMD_INI_FILE_RADIO_PARAM: ",
@@ -216,7 +218,7 @@ int wl128x_cmd_radio_parms(struct wl1271 *wl)
216 struct wl128x_nvs_file *nvs = (struct wl128x_nvs_file *)wl->nvs; 218 struct wl128x_nvs_file *nvs = (struct wl128x_nvs_file *)wl->nvs;
217 struct wl128x_radio_parms_cmd *radio_parms; 219 struct wl128x_radio_parms_cmd *radio_parms;
218 struct wl128x_ini_general_params *gp = &nvs->general_params; 220 struct wl128x_ini_general_params *gp = &nvs->general_params;
219 int ret; 221 int ret, fem_idx;
220 222
221 if (!wl->nvs) 223 if (!wl->nvs)
222 return -ENODEV; 224 return -ENODEV;
@@ -227,11 +229,13 @@ int wl128x_cmd_radio_parms(struct wl1271 *wl)
227 229
228 radio_parms->test.id = TEST_CMD_INI_FILE_RADIO_PARAM; 230 radio_parms->test.id = TEST_CMD_INI_FILE_RADIO_PARAM;
229 231
232 fem_idx = WL12XX_FEM_TO_NVS_ENTRY(gp->tx_bip_fem_manufacturer);
233
230 /* 2.4GHz parameters */ 234 /* 2.4GHz parameters */
231 memcpy(&radio_parms->static_params_2, &nvs->stat_radio_params_2, 235 memcpy(&radio_parms->static_params_2, &nvs->stat_radio_params_2,
232 sizeof(struct wl128x_ini_band_params_2)); 236 sizeof(struct wl128x_ini_band_params_2));
233 memcpy(&radio_parms->dyn_params_2, 237 memcpy(&radio_parms->dyn_params_2,
234 &nvs->dyn_radio_params_2[gp->tx_bip_fem_manufacturer].params, 238 &nvs->dyn_radio_params_2[fem_idx].params,
235 sizeof(struct wl128x_ini_fem_params_2)); 239 sizeof(struct wl128x_ini_fem_params_2));
236 240
237 /* 5GHz parameters */ 241 /* 5GHz parameters */
@@ -239,7 +243,7 @@ int wl128x_cmd_radio_parms(struct wl1271 *wl)
239 &nvs->stat_radio_params_5, 243 &nvs->stat_radio_params_5,
240 sizeof(struct wl128x_ini_band_params_5)); 244 sizeof(struct wl128x_ini_band_params_5));
241 memcpy(&radio_parms->dyn_params_5, 245 memcpy(&radio_parms->dyn_params_5,
242 &nvs->dyn_radio_params_5[gp->tx_bip_fem_manufacturer].params, 246 &nvs->dyn_radio_params_5[fem_idx].params,
243 sizeof(struct wl128x_ini_fem_params_5)); 247 sizeof(struct wl128x_ini_fem_params_5));
244 248
245 radio_parms->fem_vendor_and_options = nvs->fem_vendor_and_options; 249 radio_parms->fem_vendor_and_options = nvs->fem_vendor_and_options;
diff --git a/drivers/net/wireless/ti/wl12xx/main.c b/drivers/net/wireless/ti/wl12xx/main.c
index 85d1600ee340..47ba2e0017f4 100644
--- a/drivers/net/wireless/ti/wl12xx/main.c
+++ b/drivers/net/wireless/ti/wl12xx/main.c
@@ -246,6 +246,7 @@ static struct wlcore_conf wl12xx_conf = {
246 .forced_ps = false, 246 .forced_ps = false,
247 .keep_alive_interval = 55000, 247 .keep_alive_interval = 55000,
248 .max_listen_interval = 20, 248 .max_listen_interval = 20,
249 .sta_sleep_auth = WL1271_PSM_ILLEGAL,
249 }, 250 },
250 .itrim = { 251 .itrim = {
251 .enable = false, 252 .enable = false,
@@ -597,8 +598,10 @@ static const int wl12xx_rtable[REG_TABLE_LEN] = {
597#define WL128X_FW_NAME_SINGLE "ti-connectivity/wl128x-fw-4-sr.bin" 598#define WL128X_FW_NAME_SINGLE "ti-connectivity/wl128x-fw-4-sr.bin"
598#define WL128X_PLT_FW_NAME "ti-connectivity/wl128x-fw-4-plt.bin" 599#define WL128X_PLT_FW_NAME "ti-connectivity/wl128x-fw-4-plt.bin"
599 600
600static void wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len) 601static int wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
601{ 602{
603 int ret;
604
602 if (wl->chip.id != CHIP_ID_1283_PG20) { 605 if (wl->chip.id != CHIP_ID_1283_PG20) {
603 struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map; 606 struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
604 struct wl127x_rx_mem_pool_addr rx_mem_addr; 607 struct wl127x_rx_mem_pool_addr rx_mem_addr;
@@ -615,9 +618,13 @@ static void wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
615 618
616 rx_mem_addr.addr_extra = rx_mem_addr.addr + 4; 619 rx_mem_addr.addr_extra = rx_mem_addr.addr + 4;
617 620
618 wl1271_write(wl, WL1271_SLV_REG_DATA, 621 ret = wlcore_write(wl, WL1271_SLV_REG_DATA, &rx_mem_addr,
619 &rx_mem_addr, sizeof(rx_mem_addr), false); 622 sizeof(rx_mem_addr), false);
623 if (ret < 0)
624 return ret;
620 } 625 }
626
627 return 0;
621} 628}
622 629
623static int wl12xx_identify_chip(struct wl1271 *wl) 630static int wl12xx_identify_chip(struct wl1271 *wl)
@@ -681,64 +688,95 @@ out:
681 return ret; 688 return ret;
682} 689}
683 690
684static void wl12xx_top_reg_write(struct wl1271 *wl, int addr, u16 val) 691static int __must_check wl12xx_top_reg_write(struct wl1271 *wl, int addr,
692 u16 val)
685{ 693{
694 int ret;
695
686 /* write address >> 1 + 0x30000 to OCP_POR_CTR */ 696 /* write address >> 1 + 0x30000 to OCP_POR_CTR */
687 addr = (addr >> 1) + 0x30000; 697 addr = (addr >> 1) + 0x30000;
688 wl1271_write32(wl, WL12XX_OCP_POR_CTR, addr); 698 ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
699 if (ret < 0)
700 goto out;
689 701
690 /* write value to OCP_POR_WDATA */ 702 /* write value to OCP_POR_WDATA */
691 wl1271_write32(wl, WL12XX_OCP_DATA_WRITE, val); 703 ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val);
704 if (ret < 0)
705 goto out;
692 706
693 /* write 1 to OCP_CMD */ 707 /* write 1 to OCP_CMD */
694 wl1271_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE); 708 ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
709 if (ret < 0)
710 goto out;
711
712out:
713 return ret;
695} 714}
696 715
697static u16 wl12xx_top_reg_read(struct wl1271 *wl, int addr) 716static int __must_check wl12xx_top_reg_read(struct wl1271 *wl, int addr,
717 u16 *out)
698{ 718{
699 u32 val; 719 u32 val;
700 int timeout = OCP_CMD_LOOP; 720 int timeout = OCP_CMD_LOOP;
721 int ret;
701 722
702 /* write address >> 1 + 0x30000 to OCP_POR_CTR */ 723 /* write address >> 1 + 0x30000 to OCP_POR_CTR */
703 addr = (addr >> 1) + 0x30000; 724 addr = (addr >> 1) + 0x30000;
704 wl1271_write32(wl, WL12XX_OCP_POR_CTR, addr); 725 ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
726 if (ret < 0)
727 return ret;
705 728
706 /* write 2 to OCP_CMD */ 729 /* write 2 to OCP_CMD */
707 wl1271_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ); 730 ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
731 if (ret < 0)
732 return ret;
708 733
709 /* poll for data ready */ 734 /* poll for data ready */
710 do { 735 do {
711 val = wl1271_read32(wl, WL12XX_OCP_DATA_READ); 736 ret = wlcore_read32(wl, WL12XX_OCP_DATA_READ, &val);
737 if (ret < 0)
738 return ret;
712 } while (!(val & OCP_READY_MASK) && --timeout); 739 } while (!(val & OCP_READY_MASK) && --timeout);
713 740
714 if (!timeout) { 741 if (!timeout) {
715 wl1271_warning("Top register access timed out."); 742 wl1271_warning("Top register access timed out.");
716 return 0xffff; 743 return -ETIMEDOUT;
717 } 744 }
718 745
719 /* check data status and return if OK */ 746 /* check data status and return if OK */
720 if ((val & OCP_STATUS_MASK) == OCP_STATUS_OK) 747 if ((val & OCP_STATUS_MASK) != OCP_STATUS_OK) {
721 return val & 0xffff;
722 else {
723 wl1271_warning("Top register access returned error."); 748 wl1271_warning("Top register access returned error.");
724 return 0xffff; 749 return -EIO;
725 } 750 }
751
752 if (out)
753 *out = val & 0xffff;
754
755 return 0;
726} 756}
727 757
728static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl) 758static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
729{ 759{
730 u16 spare_reg; 760 u16 spare_reg;
761 int ret;
731 762
732 /* Mask bits [2] & [8:4] in the sys_clk_cfg register */ 763 /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
733 spare_reg = wl12xx_top_reg_read(wl, WL_SPARE_REG); 764 ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
765 if (ret < 0)
766 return ret;
767
734 if (spare_reg == 0xFFFF) 768 if (spare_reg == 0xFFFF)
735 return -EFAULT; 769 return -EFAULT;
736 spare_reg |= (BIT(3) | BIT(5) | BIT(6)); 770 spare_reg |= (BIT(3) | BIT(5) | BIT(6));
737 wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg); 771 ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
772 if (ret < 0)
773 return ret;
738 774
739 /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */ 775 /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
740 wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG, 776 ret = wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG,
741 WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF); 777 WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
778 if (ret < 0)
779 return ret;
742 780
743 /* Delay execution for 15msec, to let the HW settle */ 781 /* Delay execution for 15msec, to let the HW settle */
744 mdelay(15); 782 mdelay(15);
@@ -749,8 +787,12 @@ static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
749static bool wl128x_is_tcxo_valid(struct wl1271 *wl) 787static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
750{ 788{
751 u16 tcxo_detection; 789 u16 tcxo_detection;
790 int ret;
791
792 ret = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG, &tcxo_detection);
793 if (ret < 0)
794 return false;
752 795
753 tcxo_detection = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG);
754 if (tcxo_detection & TCXO_DET_FAILED) 796 if (tcxo_detection & TCXO_DET_FAILED)
755 return false; 797 return false;
756 798
@@ -760,8 +802,12 @@ static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
760static bool wl128x_is_fref_valid(struct wl1271 *wl) 802static bool wl128x_is_fref_valid(struct wl1271 *wl)
761{ 803{
762 u16 fref_detection; 804 u16 fref_detection;
805 int ret;
806
807 ret = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG, &fref_detection);
808 if (ret < 0)
809 return false;
763 810
764 fref_detection = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG);
765 if (fref_detection & FREF_CLK_DETECT_FAIL) 811 if (fref_detection & FREF_CLK_DETECT_FAIL)
766 return false; 812 return false;
767 813
@@ -770,11 +816,21 @@ static bool wl128x_is_fref_valid(struct wl1271 *wl)
770 816
771static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl) 817static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
772{ 818{
773 wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL); 819 int ret;
774 wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
775 wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, MCS_PLL_CONFIG_REG_VAL);
776 820
777 return 0; 821 ret = wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
822 if (ret < 0)
823 goto out;
824
825 ret = wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
826 if (ret < 0)
827 goto out;
828
829 ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG,
830 MCS_PLL_CONFIG_REG_VAL);
831
832out:
833 return ret;
778} 834}
779 835
780static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk) 836static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
@@ -783,13 +839,19 @@ static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
783 u16 pll_config; 839 u16 pll_config;
784 u8 input_freq; 840 u8 input_freq;
785 struct wl12xx_priv *priv = wl->priv; 841 struct wl12xx_priv *priv = wl->priv;
842 int ret;
786 843
787 /* Mask bits [3:1] in the sys_clk_cfg register */ 844 /* Mask bits [3:1] in the sys_clk_cfg register */
788 spare_reg = wl12xx_top_reg_read(wl, WL_SPARE_REG); 845 ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
846 if (ret < 0)
847 return ret;
848
789 if (spare_reg == 0xFFFF) 849 if (spare_reg == 0xFFFF)
790 return -EFAULT; 850 return -EFAULT;
791 spare_reg |= BIT(2); 851 spare_reg |= BIT(2);
792 wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg); 852 ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
853 if (ret < 0)
854 return ret;
793 855
794 /* Handle special cases of the TCXO clock */ 856 /* Handle special cases of the TCXO clock */
795 if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_8 || 857 if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
@@ -799,14 +861,17 @@ static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
799 /* Set the input frequency according to the selected clock source */ 861 /* Set the input frequency according to the selected clock source */
800 input_freq = (clk & 1) + 1; 862 input_freq = (clk & 1) + 1;
801 863
802 pll_config = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG); 864 ret = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG, &pll_config);
865 if (ret < 0)
866 return ret;
867
803 if (pll_config == 0xFFFF) 868 if (pll_config == 0xFFFF)
804 return -EFAULT; 869 return -EFAULT;
805 pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT); 870 pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
806 pll_config |= MCS_PLL_ENABLE_HP; 871 pll_config |= MCS_PLL_ENABLE_HP;
807 wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config); 872 ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
808 873
809 return 0; 874 return ret;
810} 875}
811 876
812/* 877/*
@@ -820,6 +885,7 @@ static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
820{ 885{
821 struct wl12xx_priv *priv = wl->priv; 886 struct wl12xx_priv *priv = wl->priv;
822 u16 sys_clk_cfg; 887 u16 sys_clk_cfg;
888 int ret;
823 889
824 /* For XTAL-only modes, FREF will be used after switching from TCXO */ 890 /* For XTAL-only modes, FREF will be used after switching from TCXO */
825 if (priv->ref_clock == WL12XX_REFCLOCK_26_XTAL || 891 if (priv->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
@@ -830,7 +896,10 @@ static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
830 } 896 }
831 897
832 /* Query the HW, to determine which clock source we should use */ 898 /* Query the HW, to determine which clock source we should use */
833 sys_clk_cfg = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG); 899 ret = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG, &sys_clk_cfg);
900 if (ret < 0)
901 return ret;
902
834 if (sys_clk_cfg == 0xFFFF) 903 if (sys_clk_cfg == 0xFFFF)
835 return -EINVAL; 904 return -EINVAL;
836 if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF) 905 if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
@@ -865,6 +934,7 @@ static int wl127x_boot_clk(struct wl1271 *wl)
865 struct wl12xx_priv *priv = wl->priv; 934 struct wl12xx_priv *priv = wl->priv;
866 u32 pause; 935 u32 pause;
867 u32 clk; 936 u32 clk;
937 int ret;
868 938
869 if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3) 939 if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
870 wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION; 940 wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION;
@@ -885,48 +955,74 @@ static int wl127x_boot_clk(struct wl1271 *wl)
885 if (priv->ref_clock != CONF_REF_CLK_19_2_E) { 955 if (priv->ref_clock != CONF_REF_CLK_19_2_E) {
886 u16 val; 956 u16 val;
887 /* Set clock type (open drain) */ 957 /* Set clock type (open drain) */
888 val = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE); 958 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE, &val);
959 if (ret < 0)
960 goto out;
961
889 val &= FREF_CLK_TYPE_BITS; 962 val &= FREF_CLK_TYPE_BITS;
890 wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val); 963 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
964 if (ret < 0)
965 goto out;
891 966
892 /* Set clock pull mode (no pull) */ 967 /* Set clock pull mode (no pull) */
893 val = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL); 968 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL, &val);
969 if (ret < 0)
970 goto out;
971
894 val |= NO_PULL; 972 val |= NO_PULL;
895 wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val); 973 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val);
974 if (ret < 0)
975 goto out;
896 } else { 976 } else {
897 u16 val; 977 u16 val;
898 /* Set clock polarity */ 978 /* Set clock polarity */
899 val = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY); 979 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY, &val);
980 if (ret < 0)
981 goto out;
982
900 val &= FREF_CLK_POLARITY_BITS; 983 val &= FREF_CLK_POLARITY_BITS;
901 val |= CLK_REQ_OUTN_SEL; 984 val |= CLK_REQ_OUTN_SEL;
902 wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val); 985 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
986 if (ret < 0)
987 goto out;
903 } 988 }
904 989
905 wl1271_write32(wl, WL12XX_PLL_PARAMETERS, clk); 990 ret = wlcore_write32(wl, WL12XX_PLL_PARAMETERS, clk);
991 if (ret < 0)
992 goto out;
906 993
907 pause = wl1271_read32(wl, WL12XX_PLL_PARAMETERS); 994 ret = wlcore_read32(wl, WL12XX_PLL_PARAMETERS, &pause);
995 if (ret < 0)
996 goto out;
908 997
909 wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause); 998 wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
910 999
911 pause &= ~(WU_COUNTER_PAUSE_VAL); 1000 pause &= ~(WU_COUNTER_PAUSE_VAL);
912 pause |= WU_COUNTER_PAUSE_VAL; 1001 pause |= WU_COUNTER_PAUSE_VAL;
913 wl1271_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause); 1002 ret = wlcore_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
914 1003
915 return 0; 1004out:
1005 return ret;
916} 1006}
917 1007
918static int wl1271_boot_soft_reset(struct wl1271 *wl) 1008static int wl1271_boot_soft_reset(struct wl1271 *wl)
919{ 1009{
920 unsigned long timeout; 1010 unsigned long timeout;
921 u32 boot_data; 1011 u32 boot_data;
1012 int ret = 0;
922 1013
923 /* perform soft reset */ 1014 /* perform soft reset */
924 wl1271_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT); 1015 ret = wlcore_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
1016 if (ret < 0)
1017 goto out;
925 1018
926 /* SOFT_RESET is self clearing */ 1019 /* SOFT_RESET is self clearing */
927 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME); 1020 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
928 while (1) { 1021 while (1) {
929 boot_data = wl1271_read32(wl, WL12XX_SLV_SOFT_RESET); 1022 ret = wlcore_read32(wl, WL12XX_SLV_SOFT_RESET, &boot_data);
1023 if (ret < 0)
1024 goto out;
1025
930 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data); 1026 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
931 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0) 1027 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
932 break; 1028 break;
@@ -942,12 +1038,15 @@ static int wl1271_boot_soft_reset(struct wl1271 *wl)
942 } 1038 }
943 1039
944 /* disable Rx/Tx */ 1040 /* disable Rx/Tx */
945 wl1271_write32(wl, WL12XX_ENABLE, 0x0); 1041 ret = wlcore_write32(wl, WL12XX_ENABLE, 0x0);
1042 if (ret < 0)
1043 goto out;
946 1044
947 /* disable auto calibration on start*/ 1045 /* disable auto calibration on start*/
948 wl1271_write32(wl, WL12XX_SPARE_A2, 0xffff); 1046 ret = wlcore_write32(wl, WL12XX_SPARE_A2, 0xffff);
949 1047
950 return 0; 1048out:
1049 return ret;
951} 1050}
952 1051
953static int wl12xx_pre_boot(struct wl1271 *wl) 1052static int wl12xx_pre_boot(struct wl1271 *wl)
@@ -968,16 +1067,23 @@ static int wl12xx_pre_boot(struct wl1271 *wl)
968 } 1067 }
969 1068
970 /* Continue the ELP wake up sequence */ 1069 /* Continue the ELP wake up sequence */
971 wl1271_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL); 1070 ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1071 if (ret < 0)
1072 goto out;
1073
972 udelay(500); 1074 udelay(500);
973 1075
974 wlcore_set_partition(wl, &wl->ptable[PART_DRPW]); 1076 ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1077 if (ret < 0)
1078 goto out;
975 1079
976 /* Read-modify-write DRPW_SCRATCH_START register (see next state) 1080 /* Read-modify-write DRPW_SCRATCH_START register (see next state)
977 to be used by DRPw FW. The RTRIM value will be added by the FW 1081 to be used by DRPw FW. The RTRIM value will be added by the FW
978 before taking DRPw out of reset */ 1082 before taking DRPw out of reset */
979 1083
980 clk = wl1271_read32(wl, WL12XX_DRPW_SCRATCH_START); 1084 ret = wlcore_read32(wl, WL12XX_DRPW_SCRATCH_START, &clk);
1085 if (ret < 0)
1086 goto out;
981 1087
982 wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk); 1088 wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
983 1089
@@ -986,12 +1092,18 @@ static int wl12xx_pre_boot(struct wl1271 *wl)
986 else 1092 else
987 clk |= (priv->ref_clock << 1) << 4; 1093 clk |= (priv->ref_clock << 1) << 4;
988 1094
989 wl1271_write32(wl, WL12XX_DRPW_SCRATCH_START, clk); 1095 ret = wlcore_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
1096 if (ret < 0)
1097 goto out;
990 1098
991 wlcore_set_partition(wl, &wl->ptable[PART_WORK]); 1099 ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
1100 if (ret < 0)
1101 goto out;
992 1102
993 /* Disable interrupts */ 1103 /* Disable interrupts */
994 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); 1104 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
1105 if (ret < 0)
1106 goto out;
995 1107
996 ret = wl1271_boot_soft_reset(wl); 1108 ret = wl1271_boot_soft_reset(wl);
997 if (ret < 0) 1109 if (ret < 0)
@@ -1001,47 +1113,72 @@ out:
1001 return ret; 1113 return ret;
1002} 1114}
1003 1115
1004static void wl12xx_pre_upload(struct wl1271 *wl) 1116static int wl12xx_pre_upload(struct wl1271 *wl)
1005{ 1117{
1006 u32 tmp, polarity; 1118 u32 tmp;
1119 u16 polarity;
1120 int ret;
1007 1121
1008 /* write firmware's last address (ie. it's length) to 1122 /* write firmware's last address (ie. it's length) to
1009 * ACX_EEPROMLESS_IND_REG */ 1123 * ACX_EEPROMLESS_IND_REG */
1010 wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG"); 1124 wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
1011 1125
1012 wl1271_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND); 1126 ret = wlcore_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
1127 if (ret < 0)
1128 goto out;
1013 1129
1014 tmp = wlcore_read_reg(wl, REG_CHIP_ID_B); 1130 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
1131 if (ret < 0)
1132 goto out;
1015 1133
1016 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp); 1134 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
1017 1135
1018 /* 6. read the EEPROM parameters */ 1136 /* 6. read the EEPROM parameters */
1019 tmp = wl1271_read32(wl, WL12XX_SCR_PAD2); 1137 ret = wlcore_read32(wl, WL12XX_SCR_PAD2, &tmp);
1138 if (ret < 0)
1139 goto out;
1020 1140
1021 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly 1141 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
1022 * to upload_fw) */ 1142 * to upload_fw) */
1023 1143
1024 if (wl->chip.id == CHIP_ID_1283_PG20) 1144 if (wl->chip.id == CHIP_ID_1283_PG20) {
1025 wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA); 1145 ret = wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
1146 if (ret < 0)
1147 goto out;
1148 }
1026 1149
1027 /* polarity must be set before the firmware is loaded */ 1150 /* polarity must be set before the firmware is loaded */
1028 polarity = wl12xx_top_reg_read(wl, OCP_REG_POLARITY); 1151 ret = wl12xx_top_reg_read(wl, OCP_REG_POLARITY, &polarity);
1152 if (ret < 0)
1153 goto out;
1029 1154
1030 /* We use HIGH polarity, so unset the LOW bit */ 1155 /* We use HIGH polarity, so unset the LOW bit */
1031 polarity &= ~POLARITY_LOW; 1156 polarity &= ~POLARITY_LOW;
1032 wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity); 1157 ret = wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity);
1033 1158
1159out:
1160 return ret;
1034} 1161}
1035 1162
1036static void wl12xx_enable_interrupts(struct wl1271 *wl) 1163static int wl12xx_enable_interrupts(struct wl1271 *wl)
1037{ 1164{
1038 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL12XX_ACX_ALL_EVENTS_VECTOR); 1165 int ret;
1166
1167 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1168 WL12XX_ACX_ALL_EVENTS_VECTOR);
1169 if (ret < 0)
1170 goto out;
1039 1171
1040 wlcore_enable_interrupts(wl); 1172 wlcore_enable_interrupts(wl);
1041 wlcore_write_reg(wl, REG_INTERRUPT_MASK, 1173 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1042 WL1271_ACX_INTR_ALL & ~(WL12XX_INTR_MASK)); 1174 WL1271_ACX_INTR_ALL & ~(WL12XX_INTR_MASK));
1175 if (ret < 0)
1176 goto out;
1043 1177
1044 wl1271_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL); 1178 ret = wlcore_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
1179
1180out:
1181 return ret;
1045} 1182}
1046 1183
1047static int wl12xx_boot(struct wl1271 *wl) 1184static int wl12xx_boot(struct wl1271 *wl)
@@ -1056,7 +1193,9 @@ static int wl12xx_boot(struct wl1271 *wl)
1056 if (ret < 0) 1193 if (ret < 0)
1057 goto out; 1194 goto out;
1058 1195
1059 wl12xx_pre_upload(wl); 1196 ret = wl12xx_pre_upload(wl);
1197 if (ret < 0)
1198 goto out;
1060 1199
1061 ret = wlcore_boot_upload_firmware(wl); 1200 ret = wlcore_boot_upload_firmware(wl);
1062 if (ret < 0) 1201 if (ret < 0)
@@ -1066,22 +1205,30 @@ static int wl12xx_boot(struct wl1271 *wl)
1066 if (ret < 0) 1205 if (ret < 0)
1067 goto out; 1206 goto out;
1068 1207
1069 wl12xx_enable_interrupts(wl); 1208 ret = wl12xx_enable_interrupts(wl);
1070 1209
1071out: 1210out:
1072 return ret; 1211 return ret;
1073} 1212}
1074 1213
1075static void wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr, 1214static int wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1076 void *buf, size_t len) 1215 void *buf, size_t len)
1077{ 1216{
1078 wl1271_write(wl, cmd_box_addr, buf, len, false); 1217 int ret;
1079 wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD); 1218
1219 ret = wlcore_write(wl, cmd_box_addr, buf, len, false);
1220 if (ret < 0)
1221 return ret;
1222
1223 ret = wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
1224
1225 return ret;
1080} 1226}
1081 1227
1082static void wl12xx_ack_event(struct wl1271 *wl) 1228static int wl12xx_ack_event(struct wl1271 *wl)
1083{ 1229{
1084 wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_EVENT_ACK); 1230 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1231 WL12XX_INTR_TRIG_EVENT_ACK);
1085} 1232}
1086 1233
1087static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks) 1234static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
@@ -1161,13 +1308,13 @@ static u32 wl12xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1161 return data_len - sizeof(*desc) - desc->pad_len; 1308 return data_len - sizeof(*desc) - desc->pad_len;
1162} 1309}
1163 1310
1164static void wl12xx_tx_delayed_compl(struct wl1271 *wl) 1311static int wl12xx_tx_delayed_compl(struct wl1271 *wl)
1165{ 1312{
1166 if (wl->fw_status_1->tx_results_counter == 1313 if (wl->fw_status_1->tx_results_counter ==
1167 (wl->tx_results_count & 0xff)) 1314 (wl->tx_results_count & 0xff))
1168 return; 1315 return 0;
1169 1316
1170 wl1271_tx_complete(wl); 1317 return wlcore_tx_complete(wl);
1171} 1318}
1172 1319
1173static int wl12xx_hw_init(struct wl1271 *wl) 1320static int wl12xx_hw_init(struct wl1271 *wl)
@@ -1268,39 +1415,58 @@ static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
1268 return supported; 1415 return supported;
1269} 1416}
1270 1417
1271static void wl12xx_get_fuse_mac(struct wl1271 *wl) 1418static int wl12xx_get_fuse_mac(struct wl1271 *wl)
1272{ 1419{
1273 u32 mac1, mac2; 1420 u32 mac1, mac2;
1421 int ret;
1274 1422
1275 wlcore_set_partition(wl, &wl->ptable[PART_DRPW]); 1423 ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1424 if (ret < 0)
1425 goto out;
1276 1426
1277 mac1 = wl1271_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1); 1427 ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1, &mac1);
1278 mac2 = wl1271_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2); 1428 if (ret < 0)
1429 goto out;
1430
1431 ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2, &mac2);
1432 if (ret < 0)
1433 goto out;
1279 1434
1280 /* these are the two parts of the BD_ADDR */ 1435 /* these are the two parts of the BD_ADDR */
1281 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) + 1436 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1282 ((mac1 & 0xff000000) >> 24); 1437 ((mac1 & 0xff000000) >> 24);
1283 wl->fuse_nic_addr = mac1 & 0xffffff; 1438 wl->fuse_nic_addr = mac1 & 0xffffff;
1284 1439
1285 wlcore_set_partition(wl, &wl->ptable[PART_DOWN]); 1440 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1441
1442out:
1443 return ret;
1286} 1444}
1287 1445
1288static s8 wl12xx_get_pg_ver(struct wl1271 *wl) 1446static int wl12xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1289{ 1447{
1290 u32 die_info; 1448 u16 die_info;
1449 int ret;
1291 1450
1292 if (wl->chip.id == CHIP_ID_1283_PG20) 1451 if (wl->chip.id == CHIP_ID_1283_PG20)
1293 die_info = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1); 1452 ret = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1,
1453 &die_info);
1294 else 1454 else
1295 die_info = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1); 1455 ret = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1,
1456 &die_info);
1296 1457
1297 return (s8) (die_info & PG_VER_MASK) >> PG_VER_OFFSET; 1458 if (ret >= 0 && ver)
1459 *ver = (s8)((die_info & PG_VER_MASK) >> PG_VER_OFFSET);
1460
1461 return ret;
1298} 1462}
1299 1463
1300static void wl12xx_get_mac(struct wl1271 *wl) 1464static int wl12xx_get_mac(struct wl1271 *wl)
1301{ 1465{
1302 if (wl12xx_mac_in_fuse(wl)) 1466 if (wl12xx_mac_in_fuse(wl))
1303 wl12xx_get_fuse_mac(wl); 1467 return wl12xx_get_fuse_mac(wl);
1468
1469 return 0;
1304} 1470}
1305 1471
1306static void wl12xx_set_tx_desc_csum(struct wl1271 *wl, 1472static void wl12xx_set_tx_desc_csum(struct wl1271 *wl,
@@ -1448,10 +1614,8 @@ static int __devinit wl12xx_probe(struct platform_device *pdev)
1448 wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0; 1614 wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0;
1449 wl->fw_status_priv_len = 0; 1615 wl->fw_status_priv_len = 0;
1450 wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics); 1616 wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics);
1451 memcpy(&wl->ht_cap[IEEE80211_BAND_2GHZ], &wl12xx_ht_cap, 1617 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, &wl12xx_ht_cap);
1452 sizeof(wl12xx_ht_cap)); 1618 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ, &wl12xx_ht_cap);
1453 memcpy(&wl->ht_cap[IEEE80211_BAND_5GHZ], &wl12xx_ht_cap,
1454 sizeof(wl12xx_ht_cap));
1455 wl12xx_conf_init(wl); 1619 wl12xx_conf_init(wl);
1456 1620
1457 if (!fref_param) { 1621 if (!fref_param) {
diff --git a/drivers/net/wireless/ti/wl18xx/acx.h b/drivers/net/wireless/ti/wl18xx/acx.h
index ebbaf611e97b..e2609a6b7341 100644
--- a/drivers/net/wireless/ti/wl18xx/acx.h
+++ b/drivers/net/wireless/ti/wl18xx/acx.h
@@ -32,25 +32,21 @@ enum {
32/* numbers of bits the length field takes (add 1 for the actual number) */ 32/* numbers of bits the length field takes (add 1 for the actual number) */
33#define WL18XX_HOST_IF_LEN_SIZE_FIELD 15 33#define WL18XX_HOST_IF_LEN_SIZE_FIELD 15
34 34
35#define WL18XX_ACX_EVENTS_VECTOR_PG1 (WL1271_ACX_INTR_WATCHDOG | \ 35#define WL18XX_ACX_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \
36 WL1271_ACX_INTR_INIT_COMPLETE | \ 36 WL1271_ACX_INTR_INIT_COMPLETE | \
37 WL1271_ACX_INTR_EVENT_A | \ 37 WL1271_ACX_INTR_EVENT_A | \
38 WL1271_ACX_INTR_EVENT_B | \ 38 WL1271_ACX_INTR_EVENT_B | \
39 WL1271_ACX_INTR_CMD_COMPLETE | \ 39 WL1271_ACX_INTR_CMD_COMPLETE | \
40 WL1271_ACX_INTR_HW_AVAILABLE | \ 40 WL1271_ACX_INTR_HW_AVAILABLE | \
41 WL1271_ACX_INTR_DATA) 41 WL1271_ACX_INTR_DATA | \
42 42 WL1271_ACX_SW_INTR_WATCHDOG)
43#define WL18XX_ACX_EVENTS_VECTOR_PG2 (WL18XX_ACX_EVENTS_VECTOR_PG1 | \ 43
44 WL1271_ACX_SW_INTR_WATCHDOG) 44#define WL18XX_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \
45 45 WL1271_ACX_INTR_EVENT_A | \
46#define WL18XX_INTR_MASK_PG1 (WL1271_ACX_INTR_WATCHDOG | \ 46 WL1271_ACX_INTR_EVENT_B | \
47 WL1271_ACX_INTR_EVENT_A | \ 47 WL1271_ACX_INTR_HW_AVAILABLE | \
48 WL1271_ACX_INTR_EVENT_B | \ 48 WL1271_ACX_INTR_DATA | \
49 WL1271_ACX_INTR_HW_AVAILABLE | \ 49 WL1271_ACX_SW_INTR_WATCHDOG)
50 WL1271_ACX_INTR_DATA)
51
52#define WL18XX_INTR_MASK_PG2 (WL18XX_INTR_MASK_PG1 | \
53 WL1271_ACX_SW_INTR_WATCHDOG)
54 50
55struct wl18xx_acx_host_config_bitmap { 51struct wl18xx_acx_host_config_bitmap {
56 struct acx_header header; 52 struct acx_header header;
diff --git a/drivers/net/wireless/ti/wl18xx/io.c b/drivers/net/wireless/ti/wl18xx/io.c
index 598c057e722b..0c06ccfd1b8c 100644
--- a/drivers/net/wireless/ti/wl18xx/io.c
+++ b/drivers/net/wireless/ti/wl18xx/io.c
@@ -24,37 +24,52 @@
24 24
25#include "io.h" 25#include "io.h"
26 26
27void wl18xx_top_reg_write(struct wl1271 *wl, int addr, u16 val) 27int wl18xx_top_reg_write(struct wl1271 *wl, int addr, u16 val)
28{ 28{
29 u32 tmp; 29 u32 tmp;
30 int ret;
30 31
31 if (WARN_ON(addr % 2)) 32 if (WARN_ON(addr % 2))
32 return; 33 return -EINVAL;
33 34
34 if ((addr % 4) == 0) { 35 if ((addr % 4) == 0) {
35 tmp = wl1271_read32(wl, addr); 36 ret = wlcore_read32(wl, addr, &tmp);
37 if (ret < 0)
38 goto out;
39
36 tmp = (tmp & 0xffff0000) | val; 40 tmp = (tmp & 0xffff0000) | val;
37 wl1271_write32(wl, addr, tmp); 41 ret = wlcore_write32(wl, addr, tmp);
38 } else { 42 } else {
39 tmp = wl1271_read32(wl, addr - 2); 43 ret = wlcore_read32(wl, addr - 2, &tmp);
44 if (ret < 0)
45 goto out;
46
40 tmp = (tmp & 0xffff) | (val << 16); 47 tmp = (tmp & 0xffff) | (val << 16);
41 wl1271_write32(wl, addr - 2, tmp); 48 ret = wlcore_write32(wl, addr - 2, tmp);
42 } 49 }
50
51out:
52 return ret;
43} 53}
44 54
45u16 wl18xx_top_reg_read(struct wl1271 *wl, int addr) 55int wl18xx_top_reg_read(struct wl1271 *wl, int addr, u16 *out)
46{ 56{
47 u32 val; 57 u32 val;
58 int ret;
48 59
49 if (WARN_ON(addr % 2)) 60 if (WARN_ON(addr % 2))
50 return 0; 61 return -EINVAL;
51 62
52 if ((addr % 4) == 0) { 63 if ((addr % 4) == 0) {
53 /* address is 4-bytes aligned */ 64 /* address is 4-bytes aligned */
54 val = wl1271_read32(wl, addr); 65 ret = wlcore_read32(wl, addr, &val);
55 return val & 0xffff; 66 if (ret >= 0 && out)
67 *out = val & 0xffff;
56 } else { 68 } else {
57 val = wl1271_read32(wl, addr - 2); 69 ret = wlcore_read32(wl, addr - 2, &val);
58 return (val & 0xffff0000) >> 16; 70 if (ret >= 0 && out)
71 *out = (val & 0xffff0000) >> 16;
59 } 72 }
73
74 return ret;
60} 75}
diff --git a/drivers/net/wireless/ti/wl18xx/io.h b/drivers/net/wireless/ti/wl18xx/io.h
index be4e126ff617..c32ae30277df 100644
--- a/drivers/net/wireless/ti/wl18xx/io.h
+++ b/drivers/net/wireless/ti/wl18xx/io.h
@@ -22,7 +22,7 @@
22#ifndef __WL18XX_IO_H__ 22#ifndef __WL18XX_IO_H__
23#define __WL18XX_IO_H__ 23#define __WL18XX_IO_H__
24 24
25void wl18xx_top_reg_write(struct wl1271 *wl, int addr, u16 val); 25int __must_check wl18xx_top_reg_write(struct wl1271 *wl, int addr, u16 val);
26u16 wl18xx_top_reg_read(struct wl1271 *wl, int addr); 26int __must_check wl18xx_top_reg_read(struct wl1271 *wl, int addr, u16 *out);
27 27
28#endif /* __WL18XX_IO_H__ */ 28#endif /* __WL18XX_IO_H__ */
diff --git a/drivers/net/wireless/ti/wl18xx/main.c b/drivers/net/wireless/ti/wl18xx/main.c
index ed9c3650e08a..5e583be8f674 100644
--- a/drivers/net/wireless/ti/wl18xx/main.c
+++ b/drivers/net/wireless/ti/wl18xx/main.c
@@ -43,10 +43,11 @@
43 43
44#define WL18XX_RX_CHECKSUM_MASK 0x40 44#define WL18XX_RX_CHECKSUM_MASK 0x40
45 45
46static char *ht_mode_param = "wide"; 46static char *ht_mode_param = "default";
47static char *board_type_param = "hdk"; 47static char *board_type_param = "hdk";
48static bool checksum_param = false; 48static bool checksum_param = false;
49static bool enable_11a_param = true; 49static bool enable_11a_param = true;
50static int num_rx_desc_param = -1;
50 51
51/* phy paramters */ 52/* phy paramters */
52static int dc2dc_param = -1; 53static int dc2dc_param = -1;
@@ -372,6 +373,7 @@ static struct wlcore_conf wl18xx_conf = {
372 .forced_ps = false, 373 .forced_ps = false,
373 .keep_alive_interval = 55000, 374 .keep_alive_interval = 55000,
374 .max_listen_interval = 20, 375 .max_listen_interval = 20,
376 .sta_sleep_auth = WL1271_PSM_ILLEGAL,
375 }, 377 },
376 .itrim = { 378 .itrim = {
377 .enable = false, 379 .enable = false,
@@ -606,24 +608,15 @@ static int wl18xx_identify_chip(struct wl1271 *wl)
606 wl->plt_fw_name = WL18XX_FW_NAME; 608 wl->plt_fw_name = WL18XX_FW_NAME;
607 wl->quirks |= WLCORE_QUIRK_NO_ELP | 609 wl->quirks |= WLCORE_QUIRK_NO_ELP |
608 WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN | 610 WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
611 WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
609 WLCORE_QUIRK_TX_PAD_LAST_FRAME; 612 WLCORE_QUIRK_TX_PAD_LAST_FRAME;
610
611 break; 613 break;
612 case CHIP_ID_185x_PG10: 614 case CHIP_ID_185x_PG10:
613 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG10)", 615 wl1271_warning("chip id 0x%x (185x PG10) is deprecated",
614 wl->chip.id); 616 wl->chip.id);
615 wl->sr_fw_name = WL18XX_FW_NAME; 617 ret = -ENODEV;
616 /* wl18xx uses the same firmware for PLT */ 618 goto out;
617 wl->plt_fw_name = WL18XX_FW_NAME;
618 wl->quirks |= WLCORE_QUIRK_NO_ELP |
619 WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED |
620 WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
621 WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
622
623 /* PG 1.0 has some problems with MCS_13, so disable it */
624 wl->ht_cap[IEEE80211_BAND_2GHZ].mcs.rx_mask[1] &= ~BIT(5);
625 619
626 break;
627 default: 620 default:
628 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id); 621 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
629 ret = -ENODEV; 622 ret = -ENODEV;
@@ -634,123 +627,178 @@ out:
634 return ret; 627 return ret;
635} 628}
636 629
637static void wl18xx_set_clk(struct wl1271 *wl) 630static int wl18xx_set_clk(struct wl1271 *wl)
638{ 631{
639 u32 clk_freq; 632 u16 clk_freq;
633 int ret;
640 634
641 wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); 635 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
636 if (ret < 0)
637 goto out;
642 638
643 /* TODO: PG2: apparently we need to read the clk type */ 639 /* TODO: PG2: apparently we need to read the clk type */
644 640
645 clk_freq = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT); 641 ret = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT, &clk_freq);
642 if (ret < 0)
643 goto out;
644
646 wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq, 645 wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
647 wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m, 646 wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
648 wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q, 647 wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
649 wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit"); 648 wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
650 649
651 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N, wl18xx_clk_table[clk_freq].n); 650 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N,
652 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M, wl18xx_clk_table[clk_freq].m); 651 wl18xx_clk_table[clk_freq].n);
652 if (ret < 0)
653 goto out;
654
655 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M,
656 wl18xx_clk_table[clk_freq].m);
657 if (ret < 0)
658 goto out;
653 659
654 if (wl18xx_clk_table[clk_freq].swallow) { 660 if (wl18xx_clk_table[clk_freq].swallow) {
655 /* first the 16 lower bits */ 661 /* first the 16 lower bits */
656 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1, 662 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
657 wl18xx_clk_table[clk_freq].q & 663 wl18xx_clk_table[clk_freq].q &
658 PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK); 664 PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
665 if (ret < 0)
666 goto out;
667
659 /* then the 16 higher bits, masked out */ 668 /* then the 16 higher bits, masked out */
660 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2, 669 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
661 (wl18xx_clk_table[clk_freq].q >> 16) & 670 (wl18xx_clk_table[clk_freq].q >> 16) &
662 PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK); 671 PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
672 if (ret < 0)
673 goto out;
663 674
664 /* first the 16 lower bits */ 675 /* first the 16 lower bits */
665 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1, 676 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
666 wl18xx_clk_table[clk_freq].p & 677 wl18xx_clk_table[clk_freq].p &
667 PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK); 678 PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
679 if (ret < 0)
680 goto out;
681
668 /* then the 16 higher bits, masked out */ 682 /* then the 16 higher bits, masked out */
669 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2, 683 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
670 (wl18xx_clk_table[clk_freq].p >> 16) & 684 (wl18xx_clk_table[clk_freq].p >> 16) &
671 PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK); 685 PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
672 } else { 686 } else {
673 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN, 687 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
674 PLLSH_WCS_PLL_SWALLOW_EN_VAL2); 688 PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
675 } 689 }
690
691out:
692 return ret;
676} 693}
677 694
678static void wl18xx_boot_soft_reset(struct wl1271 *wl) 695static int wl18xx_boot_soft_reset(struct wl1271 *wl)
679{ 696{
697 int ret;
698
680 /* disable Rx/Tx */ 699 /* disable Rx/Tx */
681 wl1271_write32(wl, WL18XX_ENABLE, 0x0); 700 ret = wlcore_write32(wl, WL18XX_ENABLE, 0x0);
701 if (ret < 0)
702 goto out;
682 703
683 /* disable auto calibration on start*/ 704 /* disable auto calibration on start*/
684 wl1271_write32(wl, WL18XX_SPARE_A2, 0xffff); 705 ret = wlcore_write32(wl, WL18XX_SPARE_A2, 0xffff);
706
707out:
708 return ret;
685} 709}
686 710
687static int wl18xx_pre_boot(struct wl1271 *wl) 711static int wl18xx_pre_boot(struct wl1271 *wl)
688{ 712{
689 wl18xx_set_clk(wl); 713 int ret;
714
715 ret = wl18xx_set_clk(wl);
716 if (ret < 0)
717 goto out;
690 718
691 /* Continue the ELP wake up sequence */ 719 /* Continue the ELP wake up sequence */
692 wl1271_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL); 720 ret = wlcore_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
721 if (ret < 0)
722 goto out;
723
693 udelay(500); 724 udelay(500);
694 725
695 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); 726 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
727 if (ret < 0)
728 goto out;
696 729
697 /* Disable interrupts */ 730 /* Disable interrupts */
698 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); 731 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
732 if (ret < 0)
733 goto out;
699 734
700 wl18xx_boot_soft_reset(wl); 735 ret = wl18xx_boot_soft_reset(wl);
701 736
702 return 0; 737out:
738 return ret;
703} 739}
704 740
705static void wl18xx_pre_upload(struct wl1271 *wl) 741static int wl18xx_pre_upload(struct wl1271 *wl)
706{ 742{
707 u32 tmp; 743 u32 tmp;
744 int ret;
708 745
709 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); 746 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
747 if (ret < 0)
748 goto out;
710 749
711 /* TODO: check if this is all needed */ 750 /* TODO: check if this is all needed */
712 wl1271_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND); 751 ret = wlcore_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
752 if (ret < 0)
753 goto out;
713 754
714 tmp = wlcore_read_reg(wl, REG_CHIP_ID_B); 755 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
756 if (ret < 0)
757 goto out;
715 758
716 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp); 759 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
717 760
718 tmp = wl1271_read32(wl, WL18XX_SCR_PAD2); 761 ret = wlcore_read32(wl, WL18XX_SCR_PAD2, &tmp);
762
763out:
764 return ret;
719} 765}
720 766
721static void wl18xx_set_mac_and_phy(struct wl1271 *wl) 767static int wl18xx_set_mac_and_phy(struct wl1271 *wl)
722{ 768{
723 struct wl18xx_priv *priv = wl->priv; 769 struct wl18xx_priv *priv = wl->priv;
724 size_t len; 770 int ret;
725 771
726 /* the parameters struct is smaller for PG1 */ 772 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
727 if (wl->chip.id == CHIP_ID_185x_PG10) 773 if (ret < 0)
728 len = offsetof(struct wl18xx_mac_and_phy_params, psat) + 1; 774 goto out;
729 else 775
730 len = sizeof(struct wl18xx_mac_and_phy_params); 776 ret = wlcore_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)&priv->conf.phy,
777 sizeof(struct wl18xx_mac_and_phy_params), false);
731 778
732 wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]); 779out:
733 wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)&priv->conf.phy, len, 780 return ret;
734 false);
735} 781}
736 782
737static void wl18xx_enable_interrupts(struct wl1271 *wl) 783static int wl18xx_enable_interrupts(struct wl1271 *wl)
738{ 784{
739 u32 event_mask, intr_mask; 785 u32 event_mask, intr_mask;
786 int ret;
740 787
741 if (wl->chip.id == CHIP_ID_185x_PG10) { 788 event_mask = WL18XX_ACX_EVENTS_VECTOR;
742 event_mask = WL18XX_ACX_EVENTS_VECTOR_PG1; 789 intr_mask = WL18XX_INTR_MASK;
743 intr_mask = WL18XX_INTR_MASK_PG1;
744 } else {
745 event_mask = WL18XX_ACX_EVENTS_VECTOR_PG2;
746 intr_mask = WL18XX_INTR_MASK_PG2;
747 }
748 790
749 wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask); 791 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask);
792 if (ret < 0)
793 goto out;
750 794
751 wlcore_enable_interrupts(wl); 795 wlcore_enable_interrupts(wl);
752 wlcore_write_reg(wl, REG_INTERRUPT_MASK, 796
753 WL1271_ACX_INTR_ALL & ~intr_mask); 797 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
798 WL1271_ACX_INTR_ALL & ~intr_mask);
799
800out:
801 return ret;
754} 802}
755 803
756static int wl18xx_boot(struct wl1271 *wl) 804static int wl18xx_boot(struct wl1271 *wl)
@@ -761,25 +809,29 @@ static int wl18xx_boot(struct wl1271 *wl)
761 if (ret < 0) 809 if (ret < 0)
762 goto out; 810 goto out;
763 811
764 wl18xx_pre_upload(wl); 812 ret = wl18xx_pre_upload(wl);
813 if (ret < 0)
814 goto out;
765 815
766 ret = wlcore_boot_upload_firmware(wl); 816 ret = wlcore_boot_upload_firmware(wl);
767 if (ret < 0) 817 if (ret < 0)
768 goto out; 818 goto out;
769 819
770 wl18xx_set_mac_and_phy(wl); 820 ret = wl18xx_set_mac_and_phy(wl);
821 if (ret < 0)
822 goto out;
771 823
772 ret = wlcore_boot_run_firmware(wl); 824 ret = wlcore_boot_run_firmware(wl);
773 if (ret < 0) 825 if (ret < 0)
774 goto out; 826 goto out;
775 827
776 wl18xx_enable_interrupts(wl); 828 ret = wl18xx_enable_interrupts(wl);
777 829
778out: 830out:
779 return ret; 831 return ret;
780} 832}
781 833
782static void wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr, 834static int wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
783 void *buf, size_t len) 835 void *buf, size_t len)
784{ 836{
785 struct wl18xx_priv *priv = wl->priv; 837 struct wl18xx_priv *priv = wl->priv;
@@ -787,13 +839,14 @@ static void wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
787 memcpy(priv->cmd_buf, buf, len); 839 memcpy(priv->cmd_buf, buf, len);
788 memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len); 840 memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
789 841
790 wl1271_write(wl, cmd_box_addr, priv->cmd_buf, WL18XX_CMD_MAX_SIZE, 842 return wlcore_write(wl, cmd_box_addr, priv->cmd_buf,
791 false); 843 WL18XX_CMD_MAX_SIZE, false);
792} 844}
793 845
794static void wl18xx_ack_event(struct wl1271 *wl) 846static int wl18xx_ack_event(struct wl1271 *wl)
795{ 847{
796 wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL18XX_INTR_TRIG_EVENT_ACK); 848 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
849 WL18XX_INTR_TRIG_EVENT_ACK);
797} 850}
798 851
799static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks) 852static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
@@ -975,34 +1028,32 @@ static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
975 } else if (!strcmp(ht_mode_param, "mimo")) { 1028 } else if (!strcmp(ht_mode_param, "mimo")) {
976 wl1271_debug(DEBUG_ACX, "using MIMO rate mask"); 1029 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
977 1030
978 /*
979 * PG 1.0 has some problems with MCS_13, so disable it
980 *
981 * TODO: instead of hacking this in here, we should
982 * make it more general and change a bit in the
983 * wlvif->rate_set instead.
984 */
985 if (wl->chip.id == CHIP_ID_185x_PG10)
986 return CONF_TX_MIMO_RATES & ~CONF_HW_BIT_RATE_MCS_13;
987
988 return CONF_TX_MIMO_RATES; 1031 return CONF_TX_MIMO_RATES;
989 } else { 1032 } else {
990 return 0; 1033 return 0;
991 } 1034 }
992} 1035}
993 1036
994static s8 wl18xx_get_pg_ver(struct wl1271 *wl) 1037static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
995{ 1038{
996 u32 fuse; 1039 u32 fuse;
1040 int ret;
997 1041
998 wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); 1042 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1043 if (ret < 0)
1044 goto out;
1045
1046 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse);
1047 if (ret < 0)
1048 goto out;
999 1049
1000 fuse = wl1271_read32(wl, WL18XX_REG_FUSE_DATA_1_3); 1050 if (ver)
1001 fuse = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET; 1051 *ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
1002 1052
1003 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); 1053 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
1004 1054
1005 return (s8)fuse; 1055out:
1056 return ret;
1006} 1057}
1007 1058
1008#define WL18XX_CONF_FILE_NAME "ti-connectivity/wl18xx-conf.bin" 1059#define WL18XX_CONF_FILE_NAME "ti-connectivity/wl18xx-conf.bin"
@@ -1021,8 +1072,7 @@ static int wl18xx_conf_init(struct wl1271 *wl, struct device *dev)
1021 } 1072 }
1022 1073
1023 if (fw->size != WL18XX_CONF_SIZE) { 1074 if (fw->size != WL18XX_CONF_SIZE) {
1024 wl1271_error("configuration binary file size is wrong, " 1075 wl1271_error("configuration binary file size is wrong, expected %zu got %zu",
1025 "expected %ld got %zd",
1026 WL18XX_CONF_SIZE, fw->size); 1076 WL18XX_CONF_SIZE, fw->size);
1027 ret = -EINVAL; 1077 ret = -EINVAL;
1028 goto out; 1078 goto out;
@@ -1069,26 +1119,41 @@ out:
1069 1119
1070static int wl18xx_plt_init(struct wl1271 *wl) 1120static int wl18xx_plt_init(struct wl1271 *wl)
1071{ 1121{
1072 wl1271_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT); 1122 int ret;
1123
1124 ret = wlcore_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
1125 if (ret < 0)
1126 return ret;
1073 1127
1074 return wl->ops->boot(wl); 1128 return wl->ops->boot(wl);
1075} 1129}
1076 1130
1077static void wl18xx_get_mac(struct wl1271 *wl) 1131static int wl18xx_get_mac(struct wl1271 *wl)
1078{ 1132{
1079 u32 mac1, mac2; 1133 u32 mac1, mac2;
1134 int ret;
1135
1136 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1137 if (ret < 0)
1138 goto out;
1080 1139
1081 wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); 1140 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1, &mac1);
1141 if (ret < 0)
1142 goto out;
1082 1143
1083 mac1 = wl1271_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1); 1144 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2, &mac2);
1084 mac2 = wl1271_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2); 1145 if (ret < 0)
1146 goto out;
1085 1147
1086 /* these are the two parts of the BD_ADDR */ 1148 /* these are the two parts of the BD_ADDR */
1087 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) + 1149 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1088 ((mac1 & 0xff000000) >> 24); 1150 ((mac1 & 0xff000000) >> 24);
1089 wl->fuse_nic_addr = (mac1 & 0xffffff); 1151 wl->fuse_nic_addr = (mac1 & 0xffffff);
1090 1152
1091 wlcore_set_partition(wl, &wl->ptable[PART_DOWN]); 1153 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1154
1155out:
1156 return ret;
1092} 1157}
1093 1158
1094static int wl18xx_handle_static_data(struct wl1271 *wl, 1159static int wl18xx_handle_static_data(struct wl1271 *wl,
@@ -1214,8 +1279,8 @@ static struct wlcore_ops wl18xx_ops = {
1214 .pre_pkt_send = wl18xx_pre_pkt_send, 1279 .pre_pkt_send = wl18xx_pre_pkt_send,
1215}; 1280};
1216 1281
1217/* HT cap appropriate for wide channels */ 1282/* HT cap appropriate for wide channels in 2Ghz */
1218static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap = { 1283static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_2ghz = {
1219 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 | 1284 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1220 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40, 1285 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40,
1221 .ht_supported = true, 1286 .ht_supported = true,
@@ -1228,40 +1293,42 @@ static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap = {
1228 }, 1293 },
1229}; 1294};
1230 1295
1231/* HT cap appropriate for SISO 20 */ 1296/* HT cap appropriate for wide channels in 5Ghz */
1232static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = { 1297static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_5ghz = {
1233 .cap = IEEE80211_HT_CAP_SGI_20, 1298 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1299 IEEE80211_HT_CAP_SUP_WIDTH_20_40,
1234 .ht_supported = true, 1300 .ht_supported = true,
1235 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K, 1301 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1236 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 1302 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1237 .mcs = { 1303 .mcs = {
1238 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 1304 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1239 .rx_highest = cpu_to_le16(72), 1305 .rx_highest = cpu_to_le16(150),
1240 .tx_params = IEEE80211_HT_MCS_TX_DEFINED, 1306 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1241 }, 1307 },
1242}; 1308};
1243 1309
1244/* HT cap appropriate for MIMO rates in 20mhz channel */ 1310/* HT cap appropriate for SISO 20 */
1245static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_2ghz = { 1311static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = {
1246 .cap = IEEE80211_HT_CAP_SGI_20, 1312 .cap = IEEE80211_HT_CAP_SGI_20,
1247 .ht_supported = true, 1313 .ht_supported = true,
1248 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K, 1314 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1249 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 1315 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1250 .mcs = { 1316 .mcs = {
1251 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, }, 1317 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1252 .rx_highest = cpu_to_le16(144), 1318 .rx_highest = cpu_to_le16(72),
1253 .tx_params = IEEE80211_HT_MCS_TX_DEFINED, 1319 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1254 }, 1320 },
1255}; 1321};
1256 1322
1257static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_5ghz = { 1323/* HT cap appropriate for MIMO rates in 20mhz channel */
1324static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_2ghz = {
1258 .cap = IEEE80211_HT_CAP_SGI_20, 1325 .cap = IEEE80211_HT_CAP_SGI_20,
1259 .ht_supported = true, 1326 .ht_supported = true,
1260 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K, 1327 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1261 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 1328 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1262 .mcs = { 1329 .mcs = {
1263 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 1330 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
1264 .rx_highest = cpu_to_le16(72), 1331 .rx_highest = cpu_to_le16(144),
1265 .tx_params = IEEE80211_HT_MCS_TX_DEFINED, 1332 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1266 }, 1333 },
1267}; 1334};
@@ -1286,7 +1353,7 @@ static int __devinit wl18xx_probe(struct platform_device *pdev)
1286 wl->ptable = wl18xx_ptable; 1353 wl->ptable = wl18xx_ptable;
1287 wl->rtable = wl18xx_rtable; 1354 wl->rtable = wl18xx_rtable;
1288 wl->num_tx_desc = 32; 1355 wl->num_tx_desc = 32;
1289 wl->num_rx_desc = 16; 1356 wl->num_rx_desc = 32;
1290 wl->band_rate_to_idx = wl18xx_band_rate_to_idx; 1357 wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1291 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX; 1358 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1292 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0; 1359 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
@@ -1294,32 +1361,8 @@ static int __devinit wl18xx_probe(struct platform_device *pdev)
1294 wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics); 1361 wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics);
1295 wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv); 1362 wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv);
1296 1363
1297 if (!strcmp(ht_mode_param, "wide")) { 1364 if (num_rx_desc_param != -1)
1298 memcpy(&wl->ht_cap[IEEE80211_BAND_2GHZ], 1365 wl->num_rx_desc = num_rx_desc_param;
1299 &wl18xx_siso40_ht_cap,
1300 sizeof(wl18xx_siso40_ht_cap));
1301 memcpy(&wl->ht_cap[IEEE80211_BAND_5GHZ],
1302 &wl18xx_siso40_ht_cap,
1303 sizeof(wl18xx_siso40_ht_cap));
1304 } else if (!strcmp(ht_mode_param, "mimo")) {
1305 memcpy(&wl->ht_cap[IEEE80211_BAND_2GHZ],
1306 &wl18xx_mimo_ht_cap_2ghz,
1307 sizeof(wl18xx_mimo_ht_cap_2ghz));
1308 memcpy(&wl->ht_cap[IEEE80211_BAND_5GHZ],
1309 &wl18xx_mimo_ht_cap_5ghz,
1310 sizeof(wl18xx_mimo_ht_cap_5ghz));
1311 } else if (!strcmp(ht_mode_param, "siso20")) {
1312 memcpy(&wl->ht_cap[IEEE80211_BAND_2GHZ],
1313 &wl18xx_siso20_ht_cap,
1314 sizeof(wl18xx_siso20_ht_cap));
1315 memcpy(&wl->ht_cap[IEEE80211_BAND_5GHZ],
1316 &wl18xx_siso20_ht_cap,
1317 sizeof(wl18xx_siso20_ht_cap));
1318 } else {
1319 wl1271_error("invalid ht_mode '%s'", ht_mode_param);
1320 ret = -EINVAL;
1321 goto out_free;
1322 }
1323 1366
1324 ret = wl18xx_conf_init(wl, &pdev->dev); 1367 ret = wl18xx_conf_init(wl, &pdev->dev);
1325 if (ret < 0) 1368 if (ret < 0)
@@ -1366,6 +1409,37 @@ static int __devinit wl18xx_probe(struct platform_device *pdev)
1366 if (dc2dc_param != -1) 1409 if (dc2dc_param != -1)
1367 priv->conf.phy.external_pa_dc2dc = dc2dc_param; 1410 priv->conf.phy.external_pa_dc2dc = dc2dc_param;
1368 1411
1412 if (!strcmp(ht_mode_param, "default")) {
1413 /*
1414 * Only support mimo with multiple antennas. Fall back to
1415 * siso20.
1416 */
1417 if (priv->conf.phy.number_of_assembled_ant2_4 >= 2)
1418 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1419 &wl18xx_mimo_ht_cap_2ghz);
1420 else
1421 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1422 &wl18xx_siso20_ht_cap);
1423
1424 /* 5Ghz is always wide */
1425 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1426 &wl18xx_siso40_ht_cap_5ghz);
1427 } else if (!strcmp(ht_mode_param, "wide")) {
1428 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1429 &wl18xx_siso40_ht_cap_2ghz);
1430 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1431 &wl18xx_siso40_ht_cap_5ghz);
1432 } else if (!strcmp(ht_mode_param, "siso20")) {
1433 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1434 &wl18xx_siso20_ht_cap);
1435 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1436 &wl18xx_siso20_ht_cap);
1437 } else {
1438 wl1271_error("invalid ht_mode '%s'", ht_mode_param);
1439 ret = -EINVAL;
1440 goto out_free;
1441 }
1442
1369 if (!checksum_param) { 1443 if (!checksum_param) {
1370 wl18xx_ops.set_rx_csum = NULL; 1444 wl18xx_ops.set_rx_csum = NULL;
1371 wl18xx_ops.init_vif = NULL; 1445 wl18xx_ops.init_vif = NULL;
@@ -1410,7 +1484,7 @@ static void __exit wl18xx_exit(void)
1410module_exit(wl18xx_exit); 1484module_exit(wl18xx_exit);
1411 1485
1412module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR); 1486module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
1413MODULE_PARM_DESC(ht_mode, "Force HT mode: wide (default), mimo or siso20"); 1487MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or siso20");
1414 1488
1415module_param_named(board_type, board_type_param, charp, S_IRUSR); 1489module_param_named(board_type, board_type_param, charp, S_IRUSR);
1416MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or " 1490MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or "
@@ -1458,6 +1532,11 @@ module_param_named(pwr_limit_reference_11_abg,
1458MODULE_PARM_DESC(pwr_limit_reference_11_abg, "Power limit reference: u8 " 1532MODULE_PARM_DESC(pwr_limit_reference_11_abg, "Power limit reference: u8 "
1459 "(default is 0xc8)"); 1533 "(default is 0xc8)");
1460 1534
1535module_param_named(num_rx_desc,
1536 num_rx_desc_param, int, S_IRUSR);
1537MODULE_PARM_DESC(num_rx_desc_param,
1538 "Number of Rx descriptors: u8 (default is 32)");
1539
1461MODULE_LICENSE("GPL v2"); 1540MODULE_LICENSE("GPL v2");
1462MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>"); 1541MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1463MODULE_FIRMWARE(WL18XX_FW_NAME); 1542MODULE_FIRMWARE(WL18XX_FW_NAME);
diff --git a/drivers/net/wireless/ti/wlcore/acx.c b/drivers/net/wireless/ti/wlcore/acx.c
index b9ec42c83757..ce108a736bd0 100644
--- a/drivers/net/wireless/ti/wlcore/acx.c
+++ b/drivers/net/wireless/ti/wlcore/acx.c
@@ -70,7 +70,7 @@ int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth)
70 struct acx_sleep_auth *auth; 70 struct acx_sleep_auth *auth;
71 int ret; 71 int ret;
72 72
73 wl1271_debug(DEBUG_ACX, "acx sleep auth"); 73 wl1271_debug(DEBUG_ACX, "acx sleep auth %d", sleep_auth);
74 74
75 auth = kzalloc(sizeof(*auth), GFP_KERNEL); 75 auth = kzalloc(sizeof(*auth), GFP_KERNEL);
76 if (!auth) { 76 if (!auth) {
@@ -81,7 +81,13 @@ int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth)
81 auth->sleep_auth = sleep_auth; 81 auth->sleep_auth = sleep_auth;
82 82
83 ret = wl1271_cmd_configure(wl, ACX_SLEEP_AUTH, auth, sizeof(*auth)); 83 ret = wl1271_cmd_configure(wl, ACX_SLEEP_AUTH, auth, sizeof(*auth));
84 if (ret < 0) {
85 wl1271_error("could not configure sleep_auth to %d: %d",
86 sleep_auth, ret);
87 goto out;
88 }
84 89
90 wl->sleep_auth = sleep_auth;
85out: 91out:
86 kfree(auth); 92 kfree(auth);
87 return ret; 93 return ret;
diff --git a/drivers/net/wireless/ti/wlcore/acx.h b/drivers/net/wireless/ti/wlcore/acx.h
index c0181258b722..d03215d6b3bd 100644
--- a/drivers/net/wireless/ti/wlcore/acx.h
+++ b/drivers/net/wireless/ti/wlcore/acx.h
@@ -118,6 +118,11 @@ enum wl1271_psm_mode {
118 118
119 /* Extreme low power */ 119 /* Extreme low power */
120 WL1271_PSM_ELP = 2, 120 WL1271_PSM_ELP = 2,
121
122 WL1271_PSM_MAX = WL1271_PSM_ELP,
123
124 /* illegal out of band value of PSM mode */
125 WL1271_PSM_ILLEGAL = 0xff
121}; 126};
122 127
123struct acx_sleep_auth { 128struct acx_sleep_auth {
diff --git a/drivers/net/wireless/ti/wlcore/boot.c b/drivers/net/wireless/ti/wlcore/boot.c
index 0fda500c01c9..8965960b841a 100644
--- a/drivers/net/wireless/ti/wlcore/boot.c
+++ b/drivers/net/wireless/ti/wlcore/boot.c
@@ -33,16 +33,22 @@
33#include "rx.h" 33#include "rx.h"
34#include "hw_ops.h" 34#include "hw_ops.h"
35 35
36static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag) 36static int wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
37{ 37{
38 u32 cpu_ctrl; 38 u32 cpu_ctrl;
39 int ret;
39 40
40 /* 10.5.0 run the firmware (I) */ 41 /* 10.5.0 run the firmware (I) */
41 cpu_ctrl = wlcore_read_reg(wl, REG_ECPU_CONTROL); 42 ret = wlcore_read_reg(wl, REG_ECPU_CONTROL, &cpu_ctrl);
43 if (ret < 0)
44 goto out;
42 45
43 /* 10.5.1 run the firmware (II) */ 46 /* 10.5.1 run the firmware (II) */
44 cpu_ctrl |= flag; 47 cpu_ctrl |= flag;
45 wlcore_write_reg(wl, REG_ECPU_CONTROL, cpu_ctrl); 48 ret = wlcore_write_reg(wl, REG_ECPU_CONTROL, cpu_ctrl);
49
50out:
51 return ret;
46} 52}
47 53
48static int wlcore_boot_parse_fw_ver(struct wl1271 *wl, 54static int wlcore_boot_parse_fw_ver(struct wl1271 *wl,
@@ -87,7 +93,9 @@ static int wlcore_boot_static_data(struct wl1271 *wl)
87 goto out; 93 goto out;
88 } 94 }
89 95
90 wl1271_read(wl, wl->cmd_box_addr, static_data, len, false); 96 ret = wlcore_read(wl, wl->cmd_box_addr, static_data, len, false);
97 if (ret < 0)
98 goto out_free;
91 99
92 ret = wlcore_boot_parse_fw_ver(wl, static_data); 100 ret = wlcore_boot_parse_fw_ver(wl, static_data);
93 if (ret < 0) 101 if (ret < 0)
@@ -109,6 +117,7 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
109 struct wlcore_partition_set partition; 117 struct wlcore_partition_set partition;
110 int addr, chunk_num, partition_limit; 118 int addr, chunk_num, partition_limit;
111 u8 *p, *chunk; 119 u8 *p, *chunk;
120 int ret;
112 121
113 /* whal_FwCtrl_LoadFwImageSm() */ 122 /* whal_FwCtrl_LoadFwImageSm() */
114 123
@@ -130,7 +139,9 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
130 139
131 memcpy(&partition, &wl->ptable[PART_DOWN], sizeof(partition)); 140 memcpy(&partition, &wl->ptable[PART_DOWN], sizeof(partition));
132 partition.mem.start = dest; 141 partition.mem.start = dest;
133 wlcore_set_partition(wl, &partition); 142 ret = wlcore_set_partition(wl, &partition);
143 if (ret < 0)
144 return ret;
134 145
135 /* 10.1 set partition limit and chunk num */ 146 /* 10.1 set partition limit and chunk num */
136 chunk_num = 0; 147 chunk_num = 0;
@@ -144,7 +155,9 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
144 partition_limit = chunk_num * CHUNK_SIZE + 155 partition_limit = chunk_num * CHUNK_SIZE +
145 wl->ptable[PART_DOWN].mem.size; 156 wl->ptable[PART_DOWN].mem.size;
146 partition.mem.start = addr; 157 partition.mem.start = addr;
147 wlcore_set_partition(wl, &partition); 158 ret = wlcore_set_partition(wl, &partition);
159 if (ret < 0)
160 return ret;
148 } 161 }
149 162
150 /* 10.3 upload the chunk */ 163 /* 10.3 upload the chunk */
@@ -153,7 +166,9 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
153 memcpy(chunk, p, CHUNK_SIZE); 166 memcpy(chunk, p, CHUNK_SIZE);
154 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x", 167 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
155 p, addr); 168 p, addr);
156 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false); 169 ret = wlcore_write(wl, addr, chunk, CHUNK_SIZE, false);
170 if (ret < 0)
171 goto out;
157 172
158 chunk_num++; 173 chunk_num++;
159 } 174 }
@@ -164,10 +179,11 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
164 memcpy(chunk, p, fw_data_len % CHUNK_SIZE); 179 memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
165 wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x", 180 wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
166 fw_data_len % CHUNK_SIZE, p, addr); 181 fw_data_len % CHUNK_SIZE, p, addr);
167 wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false); 182 ret = wlcore_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
168 183
184out:
169 kfree(chunk); 185 kfree(chunk);
170 return 0; 186 return ret;
171} 187}
172 188
173int wlcore_boot_upload_firmware(struct wl1271 *wl) 189int wlcore_boot_upload_firmware(struct wl1271 *wl)
@@ -210,6 +226,7 @@ int wlcore_boot_upload_nvs(struct wl1271 *wl)
210 int i; 226 int i;
211 u32 dest_addr, val; 227 u32 dest_addr, val;
212 u8 *nvs_ptr, *nvs_aligned; 228 u8 *nvs_ptr, *nvs_aligned;
229 int ret;
213 230
214 if (wl->nvs == NULL) { 231 if (wl->nvs == NULL) {
215 wl1271_error("NVS file is needed during boot"); 232 wl1271_error("NVS file is needed during boot");
@@ -307,7 +324,9 @@ int wlcore_boot_upload_nvs(struct wl1271 *wl)
307 wl1271_debug(DEBUG_BOOT, 324 wl1271_debug(DEBUG_BOOT,
308 "nvs burst write 0x%x: 0x%x", 325 "nvs burst write 0x%x: 0x%x",
309 dest_addr, val); 326 dest_addr, val);
310 wl1271_write32(wl, dest_addr, val); 327 ret = wlcore_write32(wl, dest_addr, val);
328 if (ret < 0)
329 return ret;
311 330
312 nvs_ptr += 4; 331 nvs_ptr += 4;
313 dest_addr += 4; 332 dest_addr += 4;
@@ -333,7 +352,9 @@ int wlcore_boot_upload_nvs(struct wl1271 *wl)
333 nvs_len -= nvs_ptr - (u8 *)wl->nvs; 352 nvs_len -= nvs_ptr - (u8 *)wl->nvs;
334 353
335 /* Now we must set the partition correctly */ 354 /* Now we must set the partition correctly */
336 wlcore_set_partition(wl, &wl->ptable[PART_WORK]); 355 ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
356 if (ret < 0)
357 return ret;
337 358
338 /* Copy the NVS tables to a new block to ensure alignment */ 359 /* Copy the NVS tables to a new block to ensure alignment */
339 nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL); 360 nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
@@ -341,11 +362,11 @@ int wlcore_boot_upload_nvs(struct wl1271 *wl)
341 return -ENOMEM; 362 return -ENOMEM;
342 363
343 /* And finally we upload the NVS tables */ 364 /* And finally we upload the NVS tables */
344 wlcore_write_data(wl, REG_CMD_MBOX_ADDRESS, 365 ret = wlcore_write_data(wl, REG_CMD_MBOX_ADDRESS, nvs_aligned, nvs_len,
345 nvs_aligned, nvs_len, false); 366 false);
346 367
347 kfree(nvs_aligned); 368 kfree(nvs_aligned);
348 return 0; 369 return ret;
349 370
350out_badnvs: 371out_badnvs:
351 wl1271_error("nvs data is malformed"); 372 wl1271_error("nvs data is malformed");
@@ -359,11 +380,17 @@ int wlcore_boot_run_firmware(struct wl1271 *wl)
359 u32 chip_id, intr; 380 u32 chip_id, intr;
360 381
361 /* Make sure we have the boot partition */ 382 /* Make sure we have the boot partition */
362 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); 383 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
384 if (ret < 0)
385 return ret;
363 386
364 wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT); 387 ret = wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
388 if (ret < 0)
389 return ret;
365 390
366 chip_id = wlcore_read_reg(wl, REG_CHIP_ID_B); 391 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &chip_id);
392 if (ret < 0)
393 return ret;
367 394
368 wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id); 395 wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
369 396
@@ -376,7 +403,9 @@ int wlcore_boot_run_firmware(struct wl1271 *wl)
376 loop = 0; 403 loop = 0;
377 while (loop++ < INIT_LOOP) { 404 while (loop++ < INIT_LOOP) {
378 udelay(INIT_LOOP_DELAY); 405 udelay(INIT_LOOP_DELAY);
379 intr = wlcore_read_reg(wl, REG_INTERRUPT_NO_CLEAR); 406 ret = wlcore_read_reg(wl, REG_INTERRUPT_NO_CLEAR, &intr);
407 if (ret < 0)
408 return ret;
380 409
381 if (intr == 0xffffffff) { 410 if (intr == 0xffffffff) {
382 wl1271_error("error reading hardware complete " 411 wl1271_error("error reading hardware complete "
@@ -385,8 +414,10 @@ int wlcore_boot_run_firmware(struct wl1271 *wl)
385 } 414 }
386 /* check that ACX_INTR_INIT_COMPLETE is enabled */ 415 /* check that ACX_INTR_INIT_COMPLETE is enabled */
387 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) { 416 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
388 wlcore_write_reg(wl, REG_INTERRUPT_ACK, 417 ret = wlcore_write_reg(wl, REG_INTERRUPT_ACK,
389 WL1271_ACX_INTR_INIT_COMPLETE); 418 WL1271_ACX_INTR_INIT_COMPLETE);
419 if (ret < 0)
420 return ret;
390 break; 421 break;
391 } 422 }
392 } 423 }
@@ -398,12 +429,17 @@ int wlcore_boot_run_firmware(struct wl1271 *wl)
398 } 429 }
399 430
400 /* get hardware config command mail box */ 431 /* get hardware config command mail box */
401 wl->cmd_box_addr = wlcore_read_reg(wl, REG_COMMAND_MAILBOX_PTR); 432 ret = wlcore_read_reg(wl, REG_COMMAND_MAILBOX_PTR, &wl->cmd_box_addr);
433 if (ret < 0)
434 return ret;
402 435
403 wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x", wl->cmd_box_addr); 436 wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x", wl->cmd_box_addr);
404 437
405 /* get hardware config event mail box */ 438 /* get hardware config event mail box */
406 wl->mbox_ptr[0] = wlcore_read_reg(wl, REG_EVENT_MAILBOX_PTR); 439 ret = wlcore_read_reg(wl, REG_EVENT_MAILBOX_PTR, &wl->mbox_ptr[0]);
440 if (ret < 0)
441 return ret;
442
407 wl->mbox_ptr[1] = wl->mbox_ptr[0] + sizeof(struct event_mailbox); 443 wl->mbox_ptr[1] = wl->mbox_ptr[0] + sizeof(struct event_mailbox);
408 444
409 wl1271_debug(DEBUG_MAILBOX, "MBOX ptrs: 0x%x 0x%x", 445 wl1271_debug(DEBUG_MAILBOX, "MBOX ptrs: 0x%x 0x%x",
@@ -445,9 +481,9 @@ int wlcore_boot_run_firmware(struct wl1271 *wl)
445 } 481 }
446 482
447 /* set the working partition to its "running" mode offset */ 483 /* set the working partition to its "running" mode offset */
448 wlcore_set_partition(wl, &wl->ptable[PART_WORK]); 484 ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
449 485
450 /* firmware startup completed */ 486 /* firmware startup completed */
451 return 0; 487 return ret;
452} 488}
453EXPORT_SYMBOL_GPL(wlcore_boot_run_firmware); 489EXPORT_SYMBOL_GPL(wlcore_boot_run_firmware);
diff --git a/drivers/net/wireless/ti/wlcore/cmd.c b/drivers/net/wireless/ti/wlcore/cmd.c
index 885364ca4344..56c7a2342fdf 100644
--- a/drivers/net/wireless/ti/wlcore/cmd.c
+++ b/drivers/net/wireless/ti/wlcore/cmd.c
@@ -65,17 +65,24 @@ int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len,
65 WARN_ON(len % 4 != 0); 65 WARN_ON(len % 4 != 0);
66 WARN_ON(test_bit(WL1271_FLAG_IN_ELP, &wl->flags)); 66 WARN_ON(test_bit(WL1271_FLAG_IN_ELP, &wl->flags));
67 67
68 wl1271_write(wl, wl->cmd_box_addr, buf, len, false); 68 ret = wlcore_write(wl, wl->cmd_box_addr, buf, len, false);
69 if (ret < 0)
70 goto fail;
69 71
70 /* 72 /*
71 * TODO: we just need this because one bit is in a different 73 * TODO: we just need this because one bit is in a different
72 * place. Is there any better way? 74 * place. Is there any better way?
73 */ 75 */
74 wl->ops->trigger_cmd(wl, wl->cmd_box_addr, buf, len); 76 ret = wl->ops->trigger_cmd(wl, wl->cmd_box_addr, buf, len);
77 if (ret < 0)
78 goto fail;
75 79
76 timeout = jiffies + msecs_to_jiffies(WL1271_COMMAND_TIMEOUT); 80 timeout = jiffies + msecs_to_jiffies(WL1271_COMMAND_TIMEOUT);
77 81
78 intr = wlcore_read_reg(wl, REG_INTERRUPT_NO_CLEAR); 82 ret = wlcore_read_reg(wl, REG_INTERRUPT_NO_CLEAR, &intr);
83 if (ret < 0)
84 goto fail;
85
79 while (!(intr & WL1271_ACX_INTR_CMD_COMPLETE)) { 86 while (!(intr & WL1271_ACX_INTR_CMD_COMPLETE)) {
80 if (time_after(jiffies, timeout)) { 87 if (time_after(jiffies, timeout)) {
81 wl1271_error("command complete timeout"); 88 wl1271_error("command complete timeout");
@@ -89,13 +96,18 @@ int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len,
89 else 96 else
90 msleep(1); 97 msleep(1);
91 98
92 intr = wlcore_read_reg(wl, REG_INTERRUPT_NO_CLEAR); 99 ret = wlcore_read_reg(wl, REG_INTERRUPT_NO_CLEAR, &intr);
100 if (ret < 0)
101 goto fail;
93 } 102 }
94 103
95 /* read back the status code of the command */ 104 /* read back the status code of the command */
96 if (res_len == 0) 105 if (res_len == 0)
97 res_len = sizeof(struct wl1271_cmd_header); 106 res_len = sizeof(struct wl1271_cmd_header);
98 wl1271_read(wl, wl->cmd_box_addr, cmd, res_len, false); 107
108 ret = wlcore_read(wl, wl->cmd_box_addr, cmd, res_len, false);
109 if (ret < 0)
110 goto fail;
99 111
100 status = le16_to_cpu(cmd->status); 112 status = le16_to_cpu(cmd->status);
101 if (status != CMD_STATUS_SUCCESS) { 113 if (status != CMD_STATUS_SUCCESS) {
@@ -104,11 +116,14 @@ int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len,
104 goto fail; 116 goto fail;
105 } 117 }
106 118
107 wlcore_write_reg(wl, REG_INTERRUPT_ACK, WL1271_ACX_INTR_CMD_COMPLETE); 119 ret = wlcore_write_reg(wl, REG_INTERRUPT_ACK,
120 WL1271_ACX_INTR_CMD_COMPLETE);
121 if (ret < 0)
122 goto fail;
123
108 return 0; 124 return 0;
109 125
110fail: 126fail:
111 WARN_ON(1);
112 wl12xx_queue_recovery_work(wl); 127 wl12xx_queue_recovery_work(wl);
113 return ret; 128 return ret;
114} 129}
@@ -117,35 +132,45 @@ fail:
117 * Poll the mailbox event field until any of the bits in the mask is set or a 132 * Poll the mailbox event field until any of the bits in the mask is set or a
118 * timeout occurs (WL1271_EVENT_TIMEOUT in msecs) 133 * timeout occurs (WL1271_EVENT_TIMEOUT in msecs)
119 */ 134 */
120static int wl1271_cmd_wait_for_event_or_timeout(struct wl1271 *wl, u32 mask) 135static int wl1271_cmd_wait_for_event_or_timeout(struct wl1271 *wl,
136 u32 mask, bool *timeout)
121{ 137{
122 u32 *events_vector; 138 u32 *events_vector;
123 u32 event; 139 u32 event;
124 unsigned long timeout; 140 unsigned long timeout_time;
125 int ret = 0; 141 int ret = 0;
126 142
143 *timeout = false;
144
127 events_vector = kmalloc(sizeof(*events_vector), GFP_KERNEL | GFP_DMA); 145 events_vector = kmalloc(sizeof(*events_vector), GFP_KERNEL | GFP_DMA);
128 if (!events_vector) 146 if (!events_vector)
129 return -ENOMEM; 147 return -ENOMEM;
130 148
131 timeout = jiffies + msecs_to_jiffies(WL1271_EVENT_TIMEOUT); 149 timeout_time = jiffies + msecs_to_jiffies(WL1271_EVENT_TIMEOUT);
132 150
133 do { 151 do {
134 if (time_after(jiffies, timeout)) { 152 if (time_after(jiffies, timeout_time)) {
135 wl1271_debug(DEBUG_CMD, "timeout waiting for event %d", 153 wl1271_debug(DEBUG_CMD, "timeout waiting for event %d",
136 (int)mask); 154 (int)mask);
137 ret = -ETIMEDOUT; 155 *timeout = true;
138 goto out; 156 goto out;
139 } 157 }
140 158
141 msleep(1); 159 msleep(1);
142 160
143 /* read from both event fields */ 161 /* read from both event fields */
144 wl1271_read(wl, wl->mbox_ptr[0], events_vector, 162 ret = wlcore_read(wl, wl->mbox_ptr[0], events_vector,
145 sizeof(*events_vector), false); 163 sizeof(*events_vector), false);
164 if (ret < 0)
165 goto out;
166
146 event = *events_vector & mask; 167 event = *events_vector & mask;
147 wl1271_read(wl, wl->mbox_ptr[1], events_vector, 168
148 sizeof(*events_vector), false); 169 ret = wlcore_read(wl, wl->mbox_ptr[1], events_vector,
170 sizeof(*events_vector), false);
171 if (ret < 0)
172 goto out;
173
149 event |= *events_vector & mask; 174 event |= *events_vector & mask;
150 } while (!event); 175 } while (!event);
151 176
@@ -157,9 +182,10 @@ out:
157static int wl1271_cmd_wait_for_event(struct wl1271 *wl, u32 mask) 182static int wl1271_cmd_wait_for_event(struct wl1271 *wl, u32 mask)
158{ 183{
159 int ret; 184 int ret;
185 bool timeout = false;
160 186
161 ret = wl1271_cmd_wait_for_event_or_timeout(wl, mask); 187 ret = wl1271_cmd_wait_for_event_or_timeout(wl, mask, &timeout);
162 if (ret != 0) { 188 if (ret != 0 || timeout) {
163 wl12xx_queue_recovery_work(wl); 189 wl12xx_queue_recovery_work(wl);
164 return ret; 190 return ret;
165 } 191 }
@@ -1412,6 +1438,7 @@ int wl12xx_cmd_remove_peer(struct wl1271 *wl, u8 hlid)
1412{ 1438{
1413 struct wl12xx_cmd_remove_peer *cmd; 1439 struct wl12xx_cmd_remove_peer *cmd;
1414 int ret; 1440 int ret;
1441 bool timeout = false;
1415 1442
1416 wl1271_debug(DEBUG_CMD, "cmd remove peer %d", (int)hlid); 1443 wl1271_debug(DEBUG_CMD, "cmd remove peer %d", (int)hlid);
1417 1444
@@ -1432,12 +1459,16 @@ int wl12xx_cmd_remove_peer(struct wl1271 *wl, u8 hlid)
1432 goto out_free; 1459 goto out_free;
1433 } 1460 }
1434 1461
1462 ret = wl1271_cmd_wait_for_event_or_timeout(wl,
1463 PEER_REMOVE_COMPLETE_EVENT_ID,
1464 &timeout);
1435 /* 1465 /*
1436 * We are ok with a timeout here. The event is sometimes not sent 1466 * We are ok with a timeout here. The event is sometimes not sent
1437 * due to a firmware bug. 1467 * due to a firmware bug. In case of another error (like SDIO timeout)
1468 * queue a recovery.
1438 */ 1469 */
1439 wl1271_cmd_wait_for_event_or_timeout(wl, 1470 if (ret)
1440 PEER_REMOVE_COMPLETE_EVENT_ID); 1471 wl12xx_queue_recovery_work(wl);
1441 1472
1442out_free: 1473out_free:
1443 kfree(cmd); 1474 kfree(cmd);
@@ -1754,7 +1785,9 @@ int wl12xx_stop_dev(struct wl1271 *wl, struct wl12xx_vif *wlvif)
1754 return -EINVAL; 1785 return -EINVAL;
1755 1786
1756 /* flush all pending packets */ 1787 /* flush all pending packets */
1757 wl1271_tx_work_locked(wl); 1788 ret = wlcore_tx_work_locked(wl);
1789 if (ret < 0)
1790 goto out;
1758 1791
1759 if (test_bit(wlvif->dev_role_id, wl->roc_map)) { 1792 if (test_bit(wlvif->dev_role_id, wl->roc_map)) {
1760 ret = wl12xx_croc(wl, wlvif->dev_role_id); 1793 ret = wl12xx_croc(wl, wlvif->dev_role_id);
diff --git a/drivers/net/wireless/ti/wlcore/cmd.h b/drivers/net/wireless/ti/wlcore/cmd.h
index 85171f2bf68e..c8a6510c72cb 100644
--- a/drivers/net/wireless/ti/wlcore/cmd.h
+++ b/drivers/net/wireless/ti/wlcore/cmd.h
@@ -652,4 +652,25 @@ struct wl12xx_cmd_stop_channel_switch {
652 struct wl1271_cmd_header header; 652 struct wl1271_cmd_header header;
653} __packed; 653} __packed;
654 654
655/* Used to check radio status after calibration */
656#define MAX_TLV_LENGTH 500
657#define TEST_CMD_P2G_CAL 2 /* TX BiP */
658
659struct wl1271_cmd_cal_p2g {
660 struct wl1271_cmd_header header;
661
662 struct wl1271_cmd_test_header test;
663
664 __le32 ver;
665 __le16 len;
666 u8 buf[MAX_TLV_LENGTH];
667 u8 type;
668 u8 padding;
669
670 __le16 radio_status;
671
672 u8 sub_band_mask;
673 u8 padding2;
674} __packed;
675
655#endif /* __WL1271_CMD_H__ */ 676#endif /* __WL1271_CMD_H__ */
diff --git a/drivers/net/wireless/ti/wlcore/conf.h b/drivers/net/wireless/ti/wlcore/conf.h
index 03c635872335..d77224f2ac6b 100644
--- a/drivers/net/wireless/ti/wlcore/conf.h
+++ b/drivers/net/wireless/ti/wlcore/conf.h
@@ -951,6 +951,12 @@ struct conf_conn_settings {
951 * Range: u16 951 * Range: u16
952 */ 952 */
953 u8 max_listen_interval; 953 u8 max_listen_interval;
954
955 /*
956 * Default sleep authorization for a new STA interface. This determines
957 * whether we can go to ELP.
958 */
959 u8 sta_sleep_auth;
954} __packed; 960} __packed;
955 961
956enum { 962enum {
@@ -1276,7 +1282,7 @@ struct conf_hangover_settings {
1276 * version, the two LSB are the lower driver's private conf 1282 * version, the two LSB are the lower driver's private conf
1277 * version. 1283 * version.
1278 */ 1284 */
1279#define WLCORE_CONF_VERSION (0x0001 << 16) 1285#define WLCORE_CONF_VERSION (0x0002 << 16)
1280#define WLCORE_CONF_MASK 0xffff0000 1286#define WLCORE_CONF_MASK 0xffff0000
1281#define WLCORE_CONF_SIZE (sizeof(struct wlcore_conf_header) + \ 1287#define WLCORE_CONF_SIZE (sizeof(struct wlcore_conf_header) + \
1282 sizeof(struct wlcore_conf)) 1288 sizeof(struct wlcore_conf))
diff --git a/drivers/net/wireless/ti/wlcore/debugfs.c b/drivers/net/wireless/ti/wlcore/debugfs.c
index 689a847005c9..80dbc5304fac 100644
--- a/drivers/net/wireless/ti/wlcore/debugfs.c
+++ b/drivers/net/wireless/ti/wlcore/debugfs.c
@@ -38,6 +38,8 @@
38/* ms */ 38/* ms */
39#define WL1271_DEBUGFS_STATS_LIFETIME 1000 39#define WL1271_DEBUGFS_STATS_LIFETIME 1000
40 40
41#define WLCORE_MAX_BLOCK_SIZE ((size_t)(4*PAGE_SIZE))
42
41/* debugfs macros idea from mac80211 */ 43/* debugfs macros idea from mac80211 */
42int wl1271_format_buffer(char __user *userbuf, size_t count, 44int wl1271_format_buffer(char __user *userbuf, size_t count,
43 loff_t *ppos, char *fmt, ...) 45 loff_t *ppos, char *fmt, ...)
@@ -963,6 +965,257 @@ static const struct file_operations fw_stats_raw_ops = {
963 .llseek = default_llseek, 965 .llseek = default_llseek,
964}; 966};
965 967
968static ssize_t sleep_auth_read(struct file *file, char __user *user_buf,
969 size_t count, loff_t *ppos)
970{
971 struct wl1271 *wl = file->private_data;
972
973 return wl1271_format_buffer(user_buf, count,
974 ppos, "%d\n",
975 wl->sleep_auth);
976}
977
978static ssize_t sleep_auth_write(struct file *file,
979 const char __user *user_buf,
980 size_t count, loff_t *ppos)
981{
982 struct wl1271 *wl = file->private_data;
983 unsigned long value;
984 int ret;
985
986 ret = kstrtoul_from_user(user_buf, count, 0, &value);
987 if (ret < 0) {
988 wl1271_warning("illegal value in sleep_auth");
989 return -EINVAL;
990 }
991
992 if (value < 0 || value > WL1271_PSM_MAX) {
993 wl1271_warning("sleep_auth must be between 0 and %d",
994 WL1271_PSM_MAX);
995 return -ERANGE;
996 }
997
998 mutex_lock(&wl->mutex);
999
1000 wl->conf.conn.sta_sleep_auth = value;
1001
1002 if (wl->state == WL1271_STATE_OFF) {
1003 /* this will show up on "read" in case we are off */
1004 wl->sleep_auth = value;
1005 goto out;
1006 }
1007
1008 ret = wl1271_ps_elp_wakeup(wl);
1009 if (ret < 0)
1010 goto out;
1011
1012 ret = wl1271_acx_sleep_auth(wl, value);
1013 if (ret < 0)
1014 goto out_sleep;
1015
1016out_sleep:
1017 wl1271_ps_elp_sleep(wl);
1018out:
1019 mutex_unlock(&wl->mutex);
1020 return count;
1021}
1022
1023static const struct file_operations sleep_auth_ops = {
1024 .read = sleep_auth_read,
1025 .write = sleep_auth_write,
1026 .open = simple_open,
1027 .llseek = default_llseek,
1028};
1029
1030static ssize_t dev_mem_read(struct file *file,
1031 char __user *user_buf, size_t count,
1032 loff_t *ppos)
1033{
1034 struct wl1271 *wl = file->private_data;
1035 struct wlcore_partition_set part, old_part;
1036 size_t bytes = count;
1037 int ret;
1038 char *buf;
1039
1040 /* only requests of dword-aligned size and offset are supported */
1041 if (bytes % 4)
1042 return -EINVAL;
1043
1044 if (*ppos % 4)
1045 return -EINVAL;
1046
1047 /* function should return in reasonable time */
1048 bytes = min(bytes, WLCORE_MAX_BLOCK_SIZE);
1049
1050 if (bytes == 0)
1051 return -EINVAL;
1052
1053 memset(&part, 0, sizeof(part));
1054 part.mem.start = file->f_pos;
1055 part.mem.size = bytes;
1056
1057 buf = kmalloc(bytes, GFP_KERNEL);
1058 if (!buf)
1059 return -ENOMEM;
1060
1061 mutex_lock(&wl->mutex);
1062
1063 if (wl->state == WL1271_STATE_OFF) {
1064 ret = -EFAULT;
1065 goto skip_read;
1066 }
1067
1068 ret = wl1271_ps_elp_wakeup(wl);
1069 if (ret < 0)
1070 goto skip_read;
1071
1072 /* store current partition and switch partition */
1073 memcpy(&old_part, &wl->curr_part, sizeof(old_part));
1074 ret = wlcore_set_partition(wl, &part);
1075 if (ret < 0)
1076 goto part_err;
1077
1078 ret = wlcore_raw_read(wl, 0, buf, bytes, false);
1079 if (ret < 0)
1080 goto read_err;
1081
1082read_err:
1083 /* recover partition */
1084 ret = wlcore_set_partition(wl, &old_part);
1085 if (ret < 0)
1086 goto part_err;
1087
1088part_err:
1089 wl1271_ps_elp_sleep(wl);
1090
1091skip_read:
1092 mutex_unlock(&wl->mutex);
1093
1094 if (ret == 0) {
1095 ret = copy_to_user(user_buf, buf, bytes);
1096 if (ret < bytes) {
1097 bytes -= ret;
1098 *ppos += bytes;
1099 ret = 0;
1100 } else {
1101 ret = -EFAULT;
1102 }
1103 }
1104
1105 kfree(buf);
1106
1107 return ((ret == 0) ? bytes : ret);
1108}
1109
1110static ssize_t dev_mem_write(struct file *file, const char __user *user_buf,
1111 size_t count, loff_t *ppos)
1112{
1113 struct wl1271 *wl = file->private_data;
1114 struct wlcore_partition_set part, old_part;
1115 size_t bytes = count;
1116 int ret;
1117 char *buf;
1118
1119 /* only requests of dword-aligned size and offset are supported */
1120 if (bytes % 4)
1121 return -EINVAL;
1122
1123 if (*ppos % 4)
1124 return -EINVAL;
1125
1126 /* function should return in reasonable time */
1127 bytes = min(bytes, WLCORE_MAX_BLOCK_SIZE);
1128
1129 if (bytes == 0)
1130 return -EINVAL;
1131
1132 memset(&part, 0, sizeof(part));
1133 part.mem.start = file->f_pos;
1134 part.mem.size = bytes;
1135
1136 buf = kmalloc(bytes, GFP_KERNEL);
1137 if (!buf)
1138 return -ENOMEM;
1139
1140 ret = copy_from_user(buf, user_buf, bytes);
1141 if (ret) {
1142 ret = -EFAULT;
1143 goto err_out;
1144 }
1145
1146 mutex_lock(&wl->mutex);
1147
1148 if (wl->state == WL1271_STATE_OFF) {
1149 ret = -EFAULT;
1150 goto skip_write;
1151 }
1152
1153 ret = wl1271_ps_elp_wakeup(wl);
1154 if (ret < 0)
1155 goto skip_write;
1156
1157 /* store current partition and switch partition */
1158 memcpy(&old_part, &wl->curr_part, sizeof(old_part));
1159 ret = wlcore_set_partition(wl, &part);
1160 if (ret < 0)
1161 goto part_err;
1162
1163 ret = wlcore_raw_write(wl, 0, buf, bytes, false);
1164 if (ret < 0)
1165 goto write_err;
1166
1167write_err:
1168 /* recover partition */
1169 ret = wlcore_set_partition(wl, &old_part);
1170 if (ret < 0)
1171 goto part_err;
1172
1173part_err:
1174 wl1271_ps_elp_sleep(wl);
1175
1176skip_write:
1177 mutex_unlock(&wl->mutex);
1178
1179 if (ret == 0)
1180 *ppos += bytes;
1181
1182err_out:
1183 kfree(buf);
1184
1185 return ((ret == 0) ? bytes : ret);
1186}
1187
1188static loff_t dev_mem_seek(struct file *file, loff_t offset, int orig)
1189{
1190 loff_t ret;
1191
1192 /* only requests of dword-aligned size and offset are supported */
1193 if (offset % 4)
1194 return -EINVAL;
1195
1196 switch (orig) {
1197 case SEEK_SET:
1198 file->f_pos = offset;
1199 ret = file->f_pos;
1200 break;
1201 case SEEK_CUR:
1202 file->f_pos += offset;
1203 ret = file->f_pos;
1204 break;
1205 default:
1206 ret = -EINVAL;
1207 }
1208
1209 return ret;
1210}
1211
1212static const struct file_operations dev_mem_ops = {
1213 .open = simple_open,
1214 .read = dev_mem_read,
1215 .write = dev_mem_write,
1216 .llseek = dev_mem_seek,
1217};
1218
966static int wl1271_debugfs_add_files(struct wl1271 *wl, 1219static int wl1271_debugfs_add_files(struct wl1271 *wl,
967 struct dentry *rootdir) 1220 struct dentry *rootdir)
968{ 1221{
@@ -988,6 +1241,7 @@ static int wl1271_debugfs_add_files(struct wl1271 *wl,
988 DEBUGFS_ADD(irq_blk_threshold, rootdir); 1241 DEBUGFS_ADD(irq_blk_threshold, rootdir);
989 DEBUGFS_ADD(irq_timeout, rootdir); 1242 DEBUGFS_ADD(irq_timeout, rootdir);
990 DEBUGFS_ADD(fw_stats_raw, rootdir); 1243 DEBUGFS_ADD(fw_stats_raw, rootdir);
1244 DEBUGFS_ADD(sleep_auth, rootdir);
991 1245
992 streaming = debugfs_create_dir("rx_streaming", rootdir); 1246 streaming = debugfs_create_dir("rx_streaming", rootdir);
993 if (!streaming || IS_ERR(streaming)) 1247 if (!streaming || IS_ERR(streaming))
@@ -996,6 +1250,7 @@ static int wl1271_debugfs_add_files(struct wl1271 *wl,
996 DEBUGFS_ADD_PREFIX(rx_streaming, interval, streaming); 1250 DEBUGFS_ADD_PREFIX(rx_streaming, interval, streaming);
997 DEBUGFS_ADD_PREFIX(rx_streaming, always, streaming); 1251 DEBUGFS_ADD_PREFIX(rx_streaming, always, streaming);
998 1252
1253 DEBUGFS_ADD_PREFIX(dev, mem, rootdir);
999 1254
1000 return 0; 1255 return 0;
1001 1256
diff --git a/drivers/net/wireless/ti/wlcore/event.c b/drivers/net/wireless/ti/wlcore/event.c
index c976f0409865..48907054d493 100644
--- a/drivers/net/wireless/ti/wlcore/event.c
+++ b/drivers/net/wireless/ti/wlcore/event.c
@@ -105,6 +105,7 @@ static int wl1271_event_process(struct wl1271 *wl)
105 u32 vector; 105 u32 vector;
106 bool disconnect_sta = false; 106 bool disconnect_sta = false;
107 unsigned long sta_bitmap = 0; 107 unsigned long sta_bitmap = 0;
108 int ret;
108 109
109 wl1271_event_mbox_dump(mbox); 110 wl1271_event_mbox_dump(mbox);
110 111
@@ -228,7 +229,9 @@ static int wl1271_event_process(struct wl1271 *wl)
228 229
229 if ((vector & DUMMY_PACKET_EVENT_ID)) { 230 if ((vector & DUMMY_PACKET_EVENT_ID)) {
230 wl1271_debug(DEBUG_EVENT, "DUMMY_PACKET_ID_EVENT_ID"); 231 wl1271_debug(DEBUG_EVENT, "DUMMY_PACKET_ID_EVENT_ID");
231 wl1271_tx_dummy_packet(wl); 232 ret = wl1271_tx_dummy_packet(wl);
233 if (ret < 0)
234 return ret;
232 } 235 }
233 236
234 /* 237 /*
@@ -301,8 +304,10 @@ int wl1271_event_handle(struct wl1271 *wl, u8 mbox_num)
301 return -EINVAL; 304 return -EINVAL;
302 305
303 /* first we read the mbox descriptor */ 306 /* first we read the mbox descriptor */
304 wl1271_read(wl, wl->mbox_ptr[mbox_num], wl->mbox, 307 ret = wlcore_read(wl, wl->mbox_ptr[mbox_num], wl->mbox,
305 sizeof(*wl->mbox), false); 308 sizeof(*wl->mbox), false);
309 if (ret < 0)
310 return ret;
306 311
307 /* process the descriptor */ 312 /* process the descriptor */
308 ret = wl1271_event_process(wl); 313 ret = wl1271_event_process(wl);
@@ -313,7 +318,7 @@ int wl1271_event_handle(struct wl1271 *wl, u8 mbox_num)
313 * TODO: we just need this because one bit is in a different 318 * TODO: we just need this because one bit is in a different
314 * place. Is there any better way? 319 * place. Is there any better way?
315 */ 320 */
316 wl->ops->ack_event(wl); 321 ret = wl->ops->ack_event(wl);
317 322
318 return 0; 323 return ret;
319} 324}
diff --git a/drivers/net/wireless/ti/wlcore/hw_ops.h b/drivers/net/wireless/ti/wlcore/hw_ops.h
index 9e7787ba9610..2673d783ec1e 100644
--- a/drivers/net/wireless/ti/wlcore/hw_ops.h
+++ b/drivers/net/wireless/ti/wlcore/hw_ops.h
@@ -65,11 +65,13 @@ wlcore_hw_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
65 return wl->ops->get_rx_buf_align(wl, rx_desc); 65 return wl->ops->get_rx_buf_align(wl, rx_desc);
66} 66}
67 67
68static inline void 68static inline int
69wlcore_hw_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len) 69wlcore_hw_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
70{ 70{
71 if (wl->ops->prepare_read) 71 if (wl->ops->prepare_read)
72 wl->ops->prepare_read(wl, rx_desc, len); 72 return wl->ops->prepare_read(wl, rx_desc, len);
73
74 return 0;
73} 75}
74 76
75static inline u32 77static inline u32
@@ -81,10 +83,12 @@ wlcore_hw_get_rx_packet_len(struct wl1271 *wl, void *rx_data, u32 data_len)
81 return wl->ops->get_rx_packet_len(wl, rx_data, data_len); 83 return wl->ops->get_rx_packet_len(wl, rx_data, data_len);
82} 84}
83 85
84static inline void wlcore_hw_tx_delayed_compl(struct wl1271 *wl) 86static inline int wlcore_hw_tx_delayed_compl(struct wl1271 *wl)
85{ 87{
86 if (wl->ops->tx_delayed_compl) 88 if (wl->ops->tx_delayed_compl)
87 wl->ops->tx_delayed_compl(wl); 89 return wl->ops->tx_delayed_compl(wl);
90
91 return 0;
88} 92}
89 93
90static inline void wlcore_hw_tx_immediate_compl(struct wl1271 *wl) 94static inline void wlcore_hw_tx_immediate_compl(struct wl1271 *wl)
diff --git a/drivers/net/wireless/ti/wlcore/ini.h b/drivers/net/wireless/ti/wlcore/ini.h
index 4cf9ecc56212..d24fe3bbc672 100644
--- a/drivers/net/wireless/ti/wlcore/ini.h
+++ b/drivers/net/wireless/ti/wlcore/ini.h
@@ -172,7 +172,19 @@ struct wl128x_ini_fem_params_5 {
172 172
173/* NVS data structure */ 173/* NVS data structure */
174#define WL1271_INI_NVS_SECTION_SIZE 468 174#define WL1271_INI_NVS_SECTION_SIZE 468
175#define WL1271_INI_FEM_MODULE_COUNT 2 175
176/* We have four FEM module types: 0-RFMD, 1-TQS, 2-SKW, 3-TQS_HP */
177#define WL1271_INI_FEM_MODULE_COUNT 4
178
179/*
180 * In NVS we only store two FEM module entries -
181 * FEM modules 0,2,3 are stored in entry 0
182 * FEM module 1 is stored in entry 1
183 */
184#define WL12XX_NVS_FEM_MODULE_COUNT 2
185
186#define WL12XX_FEM_TO_NVS_ENTRY(ini_fem_module) \
187 ((ini_fem_module) == 1 ? 1 : 0)
176 188
177#define WL1271_INI_LEGACY_NVS_FILE_SIZE 800 189#define WL1271_INI_LEGACY_NVS_FILE_SIZE 800
178 190
@@ -188,13 +200,13 @@ struct wl1271_nvs_file {
188 struct { 200 struct {
189 struct wl1271_ini_fem_params_2 params; 201 struct wl1271_ini_fem_params_2 params;
190 u8 padding; 202 u8 padding;
191 } dyn_radio_params_2[WL1271_INI_FEM_MODULE_COUNT]; 203 } dyn_radio_params_2[WL12XX_NVS_FEM_MODULE_COUNT];
192 struct wl1271_ini_band_params_5 stat_radio_params_5; 204 struct wl1271_ini_band_params_5 stat_radio_params_5;
193 u8 padding3; 205 u8 padding3;
194 struct { 206 struct {
195 struct wl1271_ini_fem_params_5 params; 207 struct wl1271_ini_fem_params_5 params;
196 u8 padding; 208 u8 padding;
197 } dyn_radio_params_5[WL1271_INI_FEM_MODULE_COUNT]; 209 } dyn_radio_params_5[WL12XX_NVS_FEM_MODULE_COUNT];
198} __packed; 210} __packed;
199 211
200struct wl128x_nvs_file { 212struct wl128x_nvs_file {
@@ -209,12 +221,12 @@ struct wl128x_nvs_file {
209 struct { 221 struct {
210 struct wl128x_ini_fem_params_2 params; 222 struct wl128x_ini_fem_params_2 params;
211 u8 padding; 223 u8 padding;
212 } dyn_radio_params_2[WL1271_INI_FEM_MODULE_COUNT]; 224 } dyn_radio_params_2[WL12XX_NVS_FEM_MODULE_COUNT];
213 struct wl128x_ini_band_params_5 stat_radio_params_5; 225 struct wl128x_ini_band_params_5 stat_radio_params_5;
214 u8 padding3; 226 u8 padding3;
215 struct { 227 struct {
216 struct wl128x_ini_fem_params_5 params; 228 struct wl128x_ini_fem_params_5 params;
217 u8 padding; 229 u8 padding;
218 } dyn_radio_params_5[WL1271_INI_FEM_MODULE_COUNT]; 230 } dyn_radio_params_5[WL12XX_NVS_FEM_MODULE_COUNT];
219} __packed; 231} __packed;
220#endif 232#endif
diff --git a/drivers/net/wireless/ti/wlcore/init.c b/drivers/net/wireless/ti/wlcore/init.c
index 645abd4b660d..8a8a8971befa 100644
--- a/drivers/net/wireless/ti/wlcore/init.c
+++ b/drivers/net/wireless/ti/wlcore/init.c
@@ -554,29 +554,28 @@ int wl1271_init_vif_specific(struct wl1271 *wl, struct ieee80211_vif *vif)
554 bool is_ap = (wlvif->bss_type == BSS_TYPE_AP_BSS); 554 bool is_ap = (wlvif->bss_type == BSS_TYPE_AP_BSS);
555 int ret, i; 555 int ret, i;
556 556
557 /* 557 /* consider all existing roles before configuring psm. */
558 * consider all existing roles before configuring psm. 558
559 * TODO: reconfigure on interface removal. 559 if (wl->ap_count == 0 && is_ap) { /* first AP */
560 */ 560 /* Configure for power always on */
561 if (!wl->ap_count) { 561 ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
562 if (is_ap) { 562 if (ret < 0)
563 /* Configure for power always on */ 563 return ret;
564 /* first STA, no APs */
565 } else if (wl->sta_count == 0 && wl->ap_count == 0 && !is_ap) {
566 u8 sta_auth = wl->conf.conn.sta_sleep_auth;
567 /* Configure for power according to debugfs */
568 if (sta_auth != WL1271_PSM_ILLEGAL)
569 ret = wl1271_acx_sleep_auth(wl, sta_auth);
570 /* Configure for power always on */
571 else if (wl->quirks & WLCORE_QUIRK_NO_ELP)
564 ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM); 572 ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
565 if (ret < 0) 573 /* Configure for ELP power saving */
566 return ret; 574 else
567 } else if (!wl->sta_count) { 575 ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_ELP);
568 if (wl->quirks & WLCORE_QUIRK_NO_ELP) { 576
569 /* Configure for power always on */ 577 if (ret < 0)
570 ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM); 578 return ret;
571 if (ret < 0)
572 return ret;
573 } else {
574 /* Configure for ELP power saving */
575 ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_ELP);
576 if (ret < 0)
577 return ret;
578 }
579 }
580 } 579 }
581 580
582 /* Mode specific init */ 581 /* Mode specific init */
diff --git a/drivers/net/wireless/ti/wlcore/io.c b/drivers/net/wireless/ti/wlcore/io.c
index 7cd0081aede5..9976219c4e49 100644
--- a/drivers/net/wireless/ti/wlcore/io.c
+++ b/drivers/net/wireless/ti/wlcore/io.c
@@ -48,6 +48,12 @@ void wlcore_disable_interrupts(struct wl1271 *wl)
48} 48}
49EXPORT_SYMBOL_GPL(wlcore_disable_interrupts); 49EXPORT_SYMBOL_GPL(wlcore_disable_interrupts);
50 50
51void wlcore_disable_interrupts_nosync(struct wl1271 *wl)
52{
53 disable_irq_nosync(wl->irq);
54}
55EXPORT_SYMBOL_GPL(wlcore_disable_interrupts_nosync);
56
51void wlcore_enable_interrupts(struct wl1271 *wl) 57void wlcore_enable_interrupts(struct wl1271 *wl)
52{ 58{
53 enable_irq(wl->irq); 59 enable_irq(wl->irq);
@@ -122,9 +128,11 @@ EXPORT_SYMBOL_GPL(wlcore_translate_addr);
122 * | | 128 * | |
123 * 129 *
124 */ 130 */
125void wlcore_set_partition(struct wl1271 *wl, 131int wlcore_set_partition(struct wl1271 *wl,
126 const struct wlcore_partition_set *p) 132 const struct wlcore_partition_set *p)
127{ 133{
134 int ret;
135
128 /* copy partition info */ 136 /* copy partition info */
129 memcpy(&wl->curr_part, p, sizeof(*p)); 137 memcpy(&wl->curr_part, p, sizeof(*p));
130 138
@@ -137,28 +145,41 @@ void wlcore_set_partition(struct wl1271 *wl,
137 wl1271_debug(DEBUG_IO, "mem3_start %08X mem3_size %08X", 145 wl1271_debug(DEBUG_IO, "mem3_start %08X mem3_size %08X",
138 p->mem3.start, p->mem3.size); 146 p->mem3.start, p->mem3.size);
139 147
140 wl1271_raw_write32(wl, HW_PART0_START_ADDR, p->mem.start); 148 ret = wlcore_raw_write32(wl, HW_PART0_START_ADDR, p->mem.start);
141 wl1271_raw_write32(wl, HW_PART0_SIZE_ADDR, p->mem.size); 149 if (ret < 0)
142 wl1271_raw_write32(wl, HW_PART1_START_ADDR, p->reg.start); 150 goto out;
143 wl1271_raw_write32(wl, HW_PART1_SIZE_ADDR, p->reg.size); 151
144 wl1271_raw_write32(wl, HW_PART2_START_ADDR, p->mem2.start); 152 ret = wlcore_raw_write32(wl, HW_PART0_SIZE_ADDR, p->mem.size);
145 wl1271_raw_write32(wl, HW_PART2_SIZE_ADDR, p->mem2.size); 153 if (ret < 0)
154 goto out;
155
156 ret = wlcore_raw_write32(wl, HW_PART1_START_ADDR, p->reg.start);
157 if (ret < 0)
158 goto out;
159
160 ret = wlcore_raw_write32(wl, HW_PART1_SIZE_ADDR, p->reg.size);
161 if (ret < 0)
162 goto out;
163
164 ret = wlcore_raw_write32(wl, HW_PART2_START_ADDR, p->mem2.start);
165 if (ret < 0)
166 goto out;
167
168 ret = wlcore_raw_write32(wl, HW_PART2_SIZE_ADDR, p->mem2.size);
169 if (ret < 0)
170 goto out;
171
146 /* 172 /*
147 * We don't need the size of the last partition, as it is 173 * We don't need the size of the last partition, as it is
148 * automatically calculated based on the total memory size and 174 * automatically calculated based on the total memory size and
149 * the sizes of the previous partitions. 175 * the sizes of the previous partitions.
150 */ 176 */
151 wl1271_raw_write32(wl, HW_PART3_START_ADDR, p->mem3.start); 177 ret = wlcore_raw_write32(wl, HW_PART3_START_ADDR, p->mem3.start);
152}
153EXPORT_SYMBOL_GPL(wlcore_set_partition);
154 178
155void wlcore_select_partition(struct wl1271 *wl, u8 part) 179out:
156{ 180 return ret;
157 wl1271_debug(DEBUG_IO, "setting partition %d", part);
158
159 wlcore_set_partition(wl, &wl->ptable[part]);
160} 181}
161EXPORT_SYMBOL_GPL(wlcore_select_partition); 182EXPORT_SYMBOL_GPL(wlcore_set_partition);
162 183
163void wl1271_io_reset(struct wl1271 *wl) 184void wl1271_io_reset(struct wl1271 *wl)
164{ 185{
diff --git a/drivers/net/wireless/ti/wlcore/io.h b/drivers/net/wireless/ti/wlcore/io.h
index 8942954b56a0..fef80adc8bf5 100644
--- a/drivers/net/wireless/ti/wlcore/io.h
+++ b/drivers/net/wireless/ti/wlcore/io.h
@@ -45,6 +45,7 @@
45struct wl1271; 45struct wl1271;
46 46
47void wlcore_disable_interrupts(struct wl1271 *wl); 47void wlcore_disable_interrupts(struct wl1271 *wl);
48void wlcore_disable_interrupts_nosync(struct wl1271 *wl);
48void wlcore_enable_interrupts(struct wl1271 *wl); 49void wlcore_enable_interrupts(struct wl1271 *wl);
49 50
50void wl1271_io_reset(struct wl1271 *wl); 51void wl1271_io_reset(struct wl1271 *wl);
@@ -52,79 +53,113 @@ void wl1271_io_init(struct wl1271 *wl);
52int wlcore_translate_addr(struct wl1271 *wl, int addr); 53int wlcore_translate_addr(struct wl1271 *wl, int addr);
53 54
54/* Raw target IO, address is not translated */ 55/* Raw target IO, address is not translated */
55static inline void wl1271_raw_write(struct wl1271 *wl, int addr, void *buf, 56static inline int __must_check wlcore_raw_write(struct wl1271 *wl, int addr,
56 size_t len, bool fixed) 57 void *buf, size_t len,
58 bool fixed)
57{ 59{
58 wl->if_ops->write(wl->dev, addr, buf, len, fixed); 60 int ret;
61
62 if (test_bit(WL1271_FLAG_SDIO_FAILED, &wl->flags))
63 return -EIO;
64
65 ret = wl->if_ops->write(wl->dev, addr, buf, len, fixed);
66 if (ret)
67 set_bit(WL1271_FLAG_SDIO_FAILED, &wl->flags);
68
69 return ret;
59} 70}
60 71
61static inline void wl1271_raw_read(struct wl1271 *wl, int addr, void *buf, 72static inline int __must_check wlcore_raw_read(struct wl1271 *wl, int addr,
62 size_t len, bool fixed) 73 void *buf, size_t len,
74 bool fixed)
63{ 75{
64 wl->if_ops->read(wl->dev, addr, buf, len, fixed); 76 int ret;
77
78 if (test_bit(WL1271_FLAG_SDIO_FAILED, &wl->flags))
79 return -EIO;
80
81 ret = wl->if_ops->read(wl->dev, addr, buf, len, fixed);
82 if (ret)
83 set_bit(WL1271_FLAG_SDIO_FAILED, &wl->flags);
84
85 return ret;
65} 86}
66 87
67static inline void wlcore_raw_read_data(struct wl1271 *wl, int reg, void *buf, 88static inline int __must_check wlcore_raw_read_data(struct wl1271 *wl, int reg,
68 size_t len, bool fixed) 89 void *buf, size_t len,
90 bool fixed)
69{ 91{
70 wl1271_raw_read(wl, wl->rtable[reg], buf, len, fixed); 92 return wlcore_raw_read(wl, wl->rtable[reg], buf, len, fixed);
71} 93}
72 94
73static inline void wlcore_raw_write_data(struct wl1271 *wl, int reg, void *buf, 95static inline int __must_check wlcore_raw_write_data(struct wl1271 *wl, int reg,
74 size_t len, bool fixed) 96 void *buf, size_t len,
97 bool fixed)
75{ 98{
76 wl1271_raw_write(wl, wl->rtable[reg], buf, len, fixed); 99 return wlcore_raw_write(wl, wl->rtable[reg], buf, len, fixed);
77} 100}
78 101
79static inline u32 wl1271_raw_read32(struct wl1271 *wl, int addr) 102static inline int __must_check wlcore_raw_read32(struct wl1271 *wl, int addr,
103 u32 *val)
80{ 104{
81 wl1271_raw_read(wl, addr, &wl->buffer_32, 105 int ret;
82 sizeof(wl->buffer_32), false); 106
107 ret = wlcore_raw_read(wl, addr, &wl->buffer_32,
108 sizeof(wl->buffer_32), false);
109 if (ret < 0)
110 return ret;
111
112 if (val)
113 *val = le32_to_cpu(wl->buffer_32);
83 114
84 return le32_to_cpu(wl->buffer_32); 115 return 0;
85} 116}
86 117
87static inline void wl1271_raw_write32(struct wl1271 *wl, int addr, u32 val) 118static inline int __must_check wlcore_raw_write32(struct wl1271 *wl, int addr,
119 u32 val)
88{ 120{
89 wl->buffer_32 = cpu_to_le32(val); 121 wl->buffer_32 = cpu_to_le32(val);
90 wl1271_raw_write(wl, addr, &wl->buffer_32, 122 return wlcore_raw_write(wl, addr, &wl->buffer_32,
91 sizeof(wl->buffer_32), false); 123 sizeof(wl->buffer_32), false);
92} 124}
93 125
94static inline void wl1271_read(struct wl1271 *wl, int addr, void *buf, 126static inline int __must_check wlcore_read(struct wl1271 *wl, int addr,
95 size_t len, bool fixed) 127 void *buf, size_t len, bool fixed)
96{ 128{
97 int physical; 129 int physical;
98 130
99 physical = wlcore_translate_addr(wl, addr); 131 physical = wlcore_translate_addr(wl, addr);
100 132
101 wl1271_raw_read(wl, physical, buf, len, fixed); 133 return wlcore_raw_read(wl, physical, buf, len, fixed);
102} 134}
103 135
104static inline void wl1271_write(struct wl1271 *wl, int addr, void *buf, 136static inline int __must_check wlcore_write(struct wl1271 *wl, int addr,
105 size_t len, bool fixed) 137 void *buf, size_t len, bool fixed)
106{ 138{
107 int physical; 139 int physical;
108 140
109 physical = wlcore_translate_addr(wl, addr); 141 physical = wlcore_translate_addr(wl, addr);
110 142
111 wl1271_raw_write(wl, physical, buf, len, fixed); 143 return wlcore_raw_write(wl, physical, buf, len, fixed);
112} 144}
113 145
114static inline void wlcore_write_data(struct wl1271 *wl, int reg, void *buf, 146static inline int __must_check wlcore_write_data(struct wl1271 *wl, int reg,
115 size_t len, bool fixed) 147 void *buf, size_t len,
148 bool fixed)
116{ 149{
117 wl1271_write(wl, wl->rtable[reg], buf, len, fixed); 150 return wlcore_write(wl, wl->rtable[reg], buf, len, fixed);
118} 151}
119 152
120static inline void wlcore_read_data(struct wl1271 *wl, int reg, void *buf, 153static inline int __must_check wlcore_read_data(struct wl1271 *wl, int reg,
121 size_t len, bool fixed) 154 void *buf, size_t len,
155 bool fixed)
122{ 156{
123 wl1271_read(wl, wl->rtable[reg], buf, len, fixed); 157 return wlcore_read(wl, wl->rtable[reg], buf, len, fixed);
124} 158}
125 159
126static inline void wl1271_read_hwaddr(struct wl1271 *wl, int hwaddr, 160static inline int __must_check wlcore_read_hwaddr(struct wl1271 *wl, int hwaddr,
127 void *buf, size_t len, bool fixed) 161 void *buf, size_t len,
162 bool fixed)
128{ 163{
129 int physical; 164 int physical;
130 int addr; 165 int addr;
@@ -134,34 +169,47 @@ static inline void wl1271_read_hwaddr(struct wl1271 *wl, int hwaddr,
134 169
135 physical = wlcore_translate_addr(wl, addr); 170 physical = wlcore_translate_addr(wl, addr);
136 171
137 wl1271_raw_read(wl, physical, buf, len, fixed); 172 return wlcore_raw_read(wl, physical, buf, len, fixed);
138} 173}
139 174
140static inline u32 wl1271_read32(struct wl1271 *wl, int addr) 175static inline int __must_check wlcore_read32(struct wl1271 *wl, int addr,
176 u32 *val)
141{ 177{
142 return wl1271_raw_read32(wl, wlcore_translate_addr(wl, addr)); 178 return wlcore_raw_read32(wl, wlcore_translate_addr(wl, addr), val);
143} 179}
144 180
145static inline void wl1271_write32(struct wl1271 *wl, int addr, u32 val) 181static inline int __must_check wlcore_write32(struct wl1271 *wl, int addr,
182 u32 val)
146{ 183{
147 wl1271_raw_write32(wl, wlcore_translate_addr(wl, addr), val); 184 return wlcore_raw_write32(wl, wlcore_translate_addr(wl, addr), val);
148} 185}
149 186
150static inline u32 wlcore_read_reg(struct wl1271 *wl, int reg) 187static inline int __must_check wlcore_read_reg(struct wl1271 *wl, int reg,
188 u32 *val)
151{ 189{
152 return wl1271_raw_read32(wl, 190 return wlcore_raw_read32(wl,
153 wlcore_translate_addr(wl, wl->rtable[reg])); 191 wlcore_translate_addr(wl, wl->rtable[reg]),
192 val);
154} 193}
155 194
156static inline void wlcore_write_reg(struct wl1271 *wl, int reg, u32 val) 195static inline int __must_check wlcore_write_reg(struct wl1271 *wl, int reg,
196 u32 val)
157{ 197{
158 wl1271_raw_write32(wl, wlcore_translate_addr(wl, wl->rtable[reg]), val); 198 return wlcore_raw_write32(wl,
199 wlcore_translate_addr(wl, wl->rtable[reg]),
200 val);
159} 201}
160 202
161static inline void wl1271_power_off(struct wl1271 *wl) 203static inline void wl1271_power_off(struct wl1271 *wl)
162{ 204{
163 wl->if_ops->power(wl->dev, false); 205 int ret;
164 clear_bit(WL1271_FLAG_GPIO_POWER, &wl->flags); 206
207 if (!test_bit(WL1271_FLAG_GPIO_POWER, &wl->flags))
208 return;
209
210 ret = wl->if_ops->power(wl->dev, false);
211 if (!ret)
212 clear_bit(WL1271_FLAG_GPIO_POWER, &wl->flags);
165} 213}
166 214
167static inline int wl1271_power_on(struct wl1271 *wl) 215static inline int wl1271_power_on(struct wl1271 *wl)
@@ -173,8 +221,8 @@ static inline int wl1271_power_on(struct wl1271 *wl)
173 return ret; 221 return ret;
174} 222}
175 223
176void wlcore_set_partition(struct wl1271 *wl, 224int wlcore_set_partition(struct wl1271 *wl,
177 const struct wlcore_partition_set *p); 225 const struct wlcore_partition_set *p);
178 226
179bool wl1271_set_block_size(struct wl1271 *wl); 227bool wl1271_set_block_size(struct wl1271 *wl);
180 228
@@ -182,6 +230,4 @@ bool wl1271_set_block_size(struct wl1271 *wl);
182 230
183int wl1271_tx_dummy_packet(struct wl1271 *wl); 231int wl1271_tx_dummy_packet(struct wl1271 *wl);
184 232
185void wlcore_select_partition(struct wl1271 *wl, u8 part);
186
187#endif 233#endif
diff --git a/drivers/net/wireless/ti/wlcore/main.c b/drivers/net/wireless/ti/wlcore/main.c
index 1156e3f578c1..2240cca597ac 100644
--- a/drivers/net/wireless/ti/wlcore/main.c
+++ b/drivers/net/wireless/ti/wlcore/main.c
@@ -378,9 +378,9 @@ static void wl12xx_irq_update_links_status(struct wl1271 *wl,
378 } 378 }
379} 379}
380 380
381static void wl12xx_fw_status(struct wl1271 *wl, 381static int wlcore_fw_status(struct wl1271 *wl,
382 struct wl_fw_status_1 *status_1, 382 struct wl_fw_status_1 *status_1,
383 struct wl_fw_status_2 *status_2) 383 struct wl_fw_status_2 *status_2)
384{ 384{
385 struct wl12xx_vif *wlvif; 385 struct wl12xx_vif *wlvif;
386 struct timespec ts; 386 struct timespec ts;
@@ -388,12 +388,15 @@ static void wl12xx_fw_status(struct wl1271 *wl,
388 int avail, freed_blocks; 388 int avail, freed_blocks;
389 int i; 389 int i;
390 size_t status_len; 390 size_t status_len;
391 int ret;
391 392
392 status_len = WLCORE_FW_STATUS_1_LEN(wl->num_rx_desc) + 393 status_len = WLCORE_FW_STATUS_1_LEN(wl->num_rx_desc) +
393 sizeof(*status_2) + wl->fw_status_priv_len; 394 sizeof(*status_2) + wl->fw_status_priv_len;
394 395
395 wlcore_raw_read_data(wl, REG_RAW_FW_STATUS_ADDR, status_1, 396 ret = wlcore_raw_read_data(wl, REG_RAW_FW_STATUS_ADDR, status_1,
396 status_len, false); 397 status_len, false);
398 if (ret < 0)
399 return ret;
397 400
398 wl1271_debug(DEBUG_IRQ, "intr: 0x%x (fw_rx_counter = %d, " 401 wl1271_debug(DEBUG_IRQ, "intr: 0x%x (fw_rx_counter = %d, "
399 "drv_rx_counter = %d, tx_results_counter = %d)", 402 "drv_rx_counter = %d, tx_results_counter = %d)",
@@ -462,6 +465,8 @@ static void wl12xx_fw_status(struct wl1271 *wl,
462 getnstimeofday(&ts); 465 getnstimeofday(&ts);
463 wl->time_offset = (timespec_to_ns(&ts) >> 10) - 466 wl->time_offset = (timespec_to_ns(&ts) >> 10) -
464 (s64)le32_to_cpu(status_2->fw_localtime); 467 (s64)le32_to_cpu(status_2->fw_localtime);
468
469 return 0;
465} 470}
466 471
467static void wl1271_flush_deferred_work(struct wl1271 *wl) 472static void wl1271_flush_deferred_work(struct wl1271 *wl)
@@ -489,20 +494,15 @@ static void wl1271_netstack_work(struct work_struct *work)
489 494
490#define WL1271_IRQ_MAX_LOOPS 256 495#define WL1271_IRQ_MAX_LOOPS 256
491 496
492static irqreturn_t wl1271_irq(int irq, void *cookie) 497static int wlcore_irq_locked(struct wl1271 *wl)
493{ 498{
494 int ret; 499 int ret = 0;
495 u32 intr; 500 u32 intr;
496 int loopcount = WL1271_IRQ_MAX_LOOPS; 501 int loopcount = WL1271_IRQ_MAX_LOOPS;
497 struct wl1271 *wl = (struct wl1271 *)cookie;
498 bool done = false; 502 bool done = false;
499 unsigned int defer_count; 503 unsigned int defer_count;
500 unsigned long flags; 504 unsigned long flags;
501 505
502 /* TX might be handled here, avoid redundant work */
503 set_bit(WL1271_FLAG_TX_PENDING, &wl->flags);
504 cancel_work_sync(&wl->tx_work);
505
506 /* 506 /*
507 * In case edge triggered interrupt must be used, we cannot iterate 507 * In case edge triggered interrupt must be used, we cannot iterate
508 * more than once without introducing race conditions with the hardirq. 508 * more than once without introducing race conditions with the hardirq.
@@ -510,8 +510,6 @@ static irqreturn_t wl1271_irq(int irq, void *cookie)
510 if (wl->platform_quirks & WL12XX_PLATFORM_QUIRK_EDGE_IRQ) 510 if (wl->platform_quirks & WL12XX_PLATFORM_QUIRK_EDGE_IRQ)
511 loopcount = 1; 511 loopcount = 1;
512 512
513 mutex_lock(&wl->mutex);
514
515 wl1271_debug(DEBUG_IRQ, "IRQ work"); 513 wl1271_debug(DEBUG_IRQ, "IRQ work");
516 514
517 if (unlikely(wl->state == WL1271_STATE_OFF)) 515 if (unlikely(wl->state == WL1271_STATE_OFF))
@@ -530,7 +528,9 @@ static irqreturn_t wl1271_irq(int irq, void *cookie)
530 clear_bit(WL1271_FLAG_IRQ_RUNNING, &wl->flags); 528 clear_bit(WL1271_FLAG_IRQ_RUNNING, &wl->flags);
531 smp_mb__after_clear_bit(); 529 smp_mb__after_clear_bit();
532 530
533 wl12xx_fw_status(wl, wl->fw_status_1, wl->fw_status_2); 531 ret = wlcore_fw_status(wl, wl->fw_status_1, wl->fw_status_2);
532 if (ret < 0)
533 goto out;
534 534
535 wlcore_hw_tx_immediate_compl(wl); 535 wlcore_hw_tx_immediate_compl(wl);
536 536
@@ -544,7 +544,7 @@ static irqreturn_t wl1271_irq(int irq, void *cookie)
544 if (unlikely(intr & WL1271_ACX_INTR_WATCHDOG)) { 544 if (unlikely(intr & WL1271_ACX_INTR_WATCHDOG)) {
545 wl1271_error("HW watchdog interrupt received! starting recovery."); 545 wl1271_error("HW watchdog interrupt received! starting recovery.");
546 wl->watchdog_recovery = true; 546 wl->watchdog_recovery = true;
547 wl12xx_queue_recovery_work(wl); 547 ret = -EIO;
548 548
549 /* restarting the chip. ignore any other interrupt. */ 549 /* restarting the chip. ignore any other interrupt. */
550 goto out; 550 goto out;
@@ -554,7 +554,7 @@ static irqreturn_t wl1271_irq(int irq, void *cookie)
554 wl1271_error("SW watchdog interrupt received! " 554 wl1271_error("SW watchdog interrupt received! "
555 "starting recovery."); 555 "starting recovery.");
556 wl->watchdog_recovery = true; 556 wl->watchdog_recovery = true;
557 wl12xx_queue_recovery_work(wl); 557 ret = -EIO;
558 558
559 /* restarting the chip. ignore any other interrupt. */ 559 /* restarting the chip. ignore any other interrupt. */
560 goto out; 560 goto out;
@@ -563,7 +563,9 @@ static irqreturn_t wl1271_irq(int irq, void *cookie)
563 if (likely(intr & WL1271_ACX_INTR_DATA)) { 563 if (likely(intr & WL1271_ACX_INTR_DATA)) {
564 wl1271_debug(DEBUG_IRQ, "WL1271_ACX_INTR_DATA"); 564 wl1271_debug(DEBUG_IRQ, "WL1271_ACX_INTR_DATA");
565 565
566 wl12xx_rx(wl, wl->fw_status_1); 566 ret = wlcore_rx(wl, wl->fw_status_1);
567 if (ret < 0)
568 goto out;
567 569
568 /* Check if any tx blocks were freed */ 570 /* Check if any tx blocks were freed */
569 spin_lock_irqsave(&wl->wl_lock, flags); 571 spin_lock_irqsave(&wl->wl_lock, flags);
@@ -574,13 +576,17 @@ static irqreturn_t wl1271_irq(int irq, void *cookie)
574 * In order to avoid starvation of the TX path, 576 * In order to avoid starvation of the TX path,
575 * call the work function directly. 577 * call the work function directly.
576 */ 578 */
577 wl1271_tx_work_locked(wl); 579 ret = wlcore_tx_work_locked(wl);
580 if (ret < 0)
581 goto out;
578 } else { 582 } else {
579 spin_unlock_irqrestore(&wl->wl_lock, flags); 583 spin_unlock_irqrestore(&wl->wl_lock, flags);
580 } 584 }
581 585
582 /* check for tx results */ 586 /* check for tx results */
583 wlcore_hw_tx_delayed_compl(wl); 587 ret = wlcore_hw_tx_delayed_compl(wl);
588 if (ret < 0)
589 goto out;
584 590
585 /* Make sure the deferred queues don't get too long */ 591 /* Make sure the deferred queues don't get too long */
586 defer_count = skb_queue_len(&wl->deferred_tx_queue) + 592 defer_count = skb_queue_len(&wl->deferred_tx_queue) +
@@ -591,12 +597,16 @@ static irqreturn_t wl1271_irq(int irq, void *cookie)
591 597
592 if (intr & WL1271_ACX_INTR_EVENT_A) { 598 if (intr & WL1271_ACX_INTR_EVENT_A) {
593 wl1271_debug(DEBUG_IRQ, "WL1271_ACX_INTR_EVENT_A"); 599 wl1271_debug(DEBUG_IRQ, "WL1271_ACX_INTR_EVENT_A");
594 wl1271_event_handle(wl, 0); 600 ret = wl1271_event_handle(wl, 0);
601 if (ret < 0)
602 goto out;
595 } 603 }
596 604
597 if (intr & WL1271_ACX_INTR_EVENT_B) { 605 if (intr & WL1271_ACX_INTR_EVENT_B) {
598 wl1271_debug(DEBUG_IRQ, "WL1271_ACX_INTR_EVENT_B"); 606 wl1271_debug(DEBUG_IRQ, "WL1271_ACX_INTR_EVENT_B");
599 wl1271_event_handle(wl, 1); 607 ret = wl1271_event_handle(wl, 1);
608 if (ret < 0)
609 goto out;
600 } 610 }
601 611
602 if (intr & WL1271_ACX_INTR_INIT_COMPLETE) 612 if (intr & WL1271_ACX_INTR_INIT_COMPLETE)
@@ -610,6 +620,25 @@ static irqreturn_t wl1271_irq(int irq, void *cookie)
610 wl1271_ps_elp_sleep(wl); 620 wl1271_ps_elp_sleep(wl);
611 621
612out: 622out:
623 return ret;
624}
625
626static irqreturn_t wlcore_irq(int irq, void *cookie)
627{
628 int ret;
629 unsigned long flags;
630 struct wl1271 *wl = cookie;
631
632 /* TX might be handled here, avoid redundant work */
633 set_bit(WL1271_FLAG_TX_PENDING, &wl->flags);
634 cancel_work_sync(&wl->tx_work);
635
636 mutex_lock(&wl->mutex);
637
638 ret = wlcore_irq_locked(wl);
639 if (ret)
640 wl12xx_queue_recovery_work(wl);
641
613 spin_lock_irqsave(&wl->wl_lock, flags); 642 spin_lock_irqsave(&wl->wl_lock, flags);
614 /* In case TX was not handled here, queue TX work */ 643 /* In case TX was not handled here, queue TX work */
615 clear_bit(WL1271_FLAG_TX_PENDING, &wl->flags); 644 clear_bit(WL1271_FLAG_TX_PENDING, &wl->flags);
@@ -743,8 +772,13 @@ out:
743 772
744void wl12xx_queue_recovery_work(struct wl1271 *wl) 773void wl12xx_queue_recovery_work(struct wl1271 *wl)
745{ 774{
746 if (!test_bit(WL1271_FLAG_RECOVERY_IN_PROGRESS, &wl->flags)) 775 WARN_ON(!test_bit(WL1271_FLAG_INTENDED_FW_RECOVERY, &wl->flags));
776
777 /* Avoid a recursive recovery */
778 if (!test_and_set_bit(WL1271_FLAG_RECOVERY_IN_PROGRESS, &wl->flags)) {
779 wlcore_disable_interrupts_nosync(wl);
747 ieee80211_queue_work(wl->hw, &wl->recovery_work); 780 ieee80211_queue_work(wl->hw, &wl->recovery_work);
781 }
748} 782}
749 783
750size_t wl12xx_copy_fwlog(struct wl1271 *wl, u8 *memblock, size_t maxlen) 784size_t wl12xx_copy_fwlog(struct wl1271 *wl, u8 *memblock, size_t maxlen)
@@ -770,14 +804,17 @@ size_t wl12xx_copy_fwlog(struct wl1271 *wl, u8 *memblock, size_t maxlen)
770 return len; 804 return len;
771} 805}
772 806
807#define WLCORE_FW_LOG_END 0x2000000
808
773static void wl12xx_read_fwlog_panic(struct wl1271 *wl) 809static void wl12xx_read_fwlog_panic(struct wl1271 *wl)
774{ 810{
775 u32 addr; 811 u32 addr;
776 u32 first_addr; 812 u32 offset;
813 u32 end_of_log;
777 u8 *block; 814 u8 *block;
815 int ret;
778 816
779 if ((wl->quirks & WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED) || 817 if ((wl->quirks & WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED) ||
780 (wl->conf.fwlog.mode != WL12XX_FWLOG_ON_DEMAND) ||
781 (wl->conf.fwlog.mem_blocks == 0)) 818 (wl->conf.fwlog.mem_blocks == 0))
782 return; 819 return;
783 820
@@ -791,34 +828,47 @@ static void wl12xx_read_fwlog_panic(struct wl1271 *wl)
791 * Make sure the chip is awake and the logger isn't active. 828 * Make sure the chip is awake and the logger isn't active.
792 * Do not send a stop fwlog command if the fw is hanged. 829 * Do not send a stop fwlog command if the fw is hanged.
793 */ 830 */
794 if (!wl1271_ps_elp_wakeup(wl) && !wl->watchdog_recovery) 831 if (wl1271_ps_elp_wakeup(wl))
795 wl12xx_cmd_stop_fwlog(wl);
796 else
797 goto out; 832 goto out;
833 if (!wl->watchdog_recovery)
834 wl12xx_cmd_stop_fwlog(wl);
798 835
799 /* Read the first memory block address */ 836 /* Read the first memory block address */
800 wl12xx_fw_status(wl, wl->fw_status_1, wl->fw_status_2); 837 ret = wlcore_fw_status(wl, wl->fw_status_1, wl->fw_status_2);
801 first_addr = le32_to_cpu(wl->fw_status_2->log_start_addr); 838 if (ret < 0)
802 if (!first_addr) 839 goto out;
840
841 addr = le32_to_cpu(wl->fw_status_2->log_start_addr);
842 if (!addr)
803 goto out; 843 goto out;
804 844
845 if (wl->conf.fwlog.mode == WL12XX_FWLOG_CONTINUOUS) {
846 offset = sizeof(addr) + sizeof(struct wl1271_rx_descriptor);
847 end_of_log = WLCORE_FW_LOG_END;
848 } else {
849 offset = sizeof(addr);
850 end_of_log = addr;
851 }
852
805 /* Traverse the memory blocks linked list */ 853 /* Traverse the memory blocks linked list */
806 addr = first_addr;
807 do { 854 do {
808 memset(block, 0, WL12XX_HW_BLOCK_SIZE); 855 memset(block, 0, WL12XX_HW_BLOCK_SIZE);
809 wl1271_read_hwaddr(wl, addr, block, WL12XX_HW_BLOCK_SIZE, 856 ret = wlcore_read_hwaddr(wl, addr, block, WL12XX_HW_BLOCK_SIZE,
810 false); 857 false);
858 if (ret < 0)
859 goto out;
811 860
812 /* 861 /*
813 * Memory blocks are linked to one another. The first 4 bytes 862 * Memory blocks are linked to one another. The first 4 bytes
814 * of each memory block hold the hardware address of the next 863 * of each memory block hold the hardware address of the next
815 * one. The last memory block points to the first one. 864 * one. The last memory block points to the first one in
865 * on demand mode and is equal to 0x2000000 in continuous mode.
816 */ 866 */
817 addr = le32_to_cpup((__le32 *)block); 867 addr = le32_to_cpup((__le32 *)block);
818 if (!wl12xx_copy_fwlog(wl, block + sizeof(addr), 868 if (!wl12xx_copy_fwlog(wl, block + offset,
819 WL12XX_HW_BLOCK_SIZE - sizeof(addr))) 869 WL12XX_HW_BLOCK_SIZE - offset))
820 break; 870 break;
821 } while (addr && (addr != first_addr)); 871 } while (addr && (addr != end_of_log));
822 872
823 wake_up_interruptible(&wl->fwlog_waitq); 873 wake_up_interruptible(&wl->fwlog_waitq);
824 874
@@ -826,6 +876,34 @@ out:
826 kfree(block); 876 kfree(block);
827} 877}
828 878
879static void wlcore_print_recovery(struct wl1271 *wl)
880{
881 u32 pc = 0;
882 u32 hint_sts = 0;
883 int ret;
884
885 wl1271_info("Hardware recovery in progress. FW ver: %s",
886 wl->chip.fw_ver_str);
887
888 /* change partitions momentarily so we can read the FW pc */
889 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
890 if (ret < 0)
891 return;
892
893 ret = wlcore_read_reg(wl, REG_PC_ON_RECOVERY, &pc);
894 if (ret < 0)
895 return;
896
897 ret = wlcore_read_reg(wl, REG_INTERRUPT_NO_CLEAR, &hint_sts);
898 if (ret < 0)
899 return;
900
901 wl1271_info("pc: 0x%x, hint_sts: 0x%08x", pc, hint_sts);
902
903 wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
904}
905
906
829static void wl1271_recovery_work(struct work_struct *work) 907static void wl1271_recovery_work(struct work_struct *work)
830{ 908{
831 struct wl1271 *wl = 909 struct wl1271 *wl =
@@ -838,19 +916,9 @@ static void wl1271_recovery_work(struct work_struct *work)
838 if (wl->state != WL1271_STATE_ON || wl->plt) 916 if (wl->state != WL1271_STATE_ON || wl->plt)
839 goto out_unlock; 917 goto out_unlock;
840 918
841 /* Avoid a recursive recovery */
842 set_bit(WL1271_FLAG_RECOVERY_IN_PROGRESS, &wl->flags);
843
844 wl12xx_read_fwlog_panic(wl); 919 wl12xx_read_fwlog_panic(wl);
845 920
846 /* change partitions momentarily so we can read the FW pc */ 921 wlcore_print_recovery(wl);
847 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
848 wl1271_info("Hardware recovery in progress. FW ver: %s pc: 0x%x "
849 "hint_sts: 0x%08x",
850 wl->chip.fw_ver_str,
851 wlcore_read_reg(wl, REG_PC_ON_RECOVERY),
852 wlcore_read_reg(wl, REG_INTERRUPT_NO_CLEAR));
853 wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
854 922
855 BUG_ON(bug_on_recovery && 923 BUG_ON(bug_on_recovery &&
856 !test_bit(WL1271_FLAG_INTENDED_FW_RECOVERY, &wl->flags)); 924 !test_bit(WL1271_FLAG_INTENDED_FW_RECOVERY, &wl->flags));
@@ -892,8 +960,6 @@ static void wl1271_recovery_work(struct work_struct *work)
892 mutex_unlock(&wl->mutex); 960 mutex_unlock(&wl->mutex);
893 wl1271_op_stop(wl->hw); 961 wl1271_op_stop(wl->hw);
894 962
895 clear_bit(WL1271_FLAG_RECOVERY_IN_PROGRESS, &wl->flags);
896
897 ieee80211_restart_hw(wl->hw); 963 ieee80211_restart_hw(wl->hw);
898 964
899 /* 965 /*
@@ -907,9 +973,9 @@ out_unlock:
907 mutex_unlock(&wl->mutex); 973 mutex_unlock(&wl->mutex);
908} 974}
909 975
910static void wl1271_fw_wakeup(struct wl1271 *wl) 976static int wlcore_fw_wakeup(struct wl1271 *wl)
911{ 977{
912 wl1271_raw_write32(wl, HW_ACCESS_ELP_CTRL_REG, ELPCTRL_WAKE_UP); 978 return wlcore_raw_write32(wl, HW_ACCESS_ELP_CTRL_REG, ELPCTRL_WAKE_UP);
913} 979}
914 980
915static int wl1271_setup(struct wl1271 *wl) 981static int wl1271_setup(struct wl1271 *wl)
@@ -945,13 +1011,21 @@ static int wl12xx_set_power_on(struct wl1271 *wl)
945 wl1271_io_reset(wl); 1011 wl1271_io_reset(wl);
946 wl1271_io_init(wl); 1012 wl1271_io_init(wl);
947 1013
948 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); 1014 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
1015 if (ret < 0)
1016 goto fail;
949 1017
950 /* ELP module wake up */ 1018 /* ELP module wake up */
951 wl1271_fw_wakeup(wl); 1019 ret = wlcore_fw_wakeup(wl);
1020 if (ret < 0)
1021 goto fail;
952 1022
953out: 1023out:
954 return ret; 1024 return ret;
1025
1026fail:
1027 wl1271_power_off(wl);
1028 return ret;
955} 1029}
956 1030
957static int wl12xx_chip_wakeup(struct wl1271 *wl, bool plt) 1031static int wl12xx_chip_wakeup(struct wl1271 *wl, bool plt)
@@ -1082,6 +1156,7 @@ int wl1271_plt_stop(struct wl1271 *wl)
1082 mutex_lock(&wl->mutex); 1156 mutex_lock(&wl->mutex);
1083 wl1271_power_off(wl); 1157 wl1271_power_off(wl);
1084 wl->flags = 0; 1158 wl->flags = 0;
1159 wl->sleep_auth = WL1271_PSM_ILLEGAL;
1085 wl->state = WL1271_STATE_OFF; 1160 wl->state = WL1271_STATE_OFF;
1086 wl->plt = false; 1161 wl->plt = false;
1087 wl->rx_counter = 0; 1162 wl->rx_counter = 0;
@@ -1173,7 +1248,7 @@ int wl1271_tx_dummy_packet(struct wl1271 *wl)
1173 1248
1174 /* The FW is low on RX memory blocks, so send the dummy packet asap */ 1249 /* The FW is low on RX memory blocks, so send the dummy packet asap */
1175 if (!test_bit(WL1271_FLAG_FW_TX_BUSY, &wl->flags)) 1250 if (!test_bit(WL1271_FLAG_FW_TX_BUSY, &wl->flags))
1176 wl1271_tx_work_locked(wl); 1251 return wlcore_tx_work_locked(wl);
1177 1252
1178 /* 1253 /*
1179 * If the FW TX is busy, TX work will be scheduled by the threaded 1254 * If the FW TX is busy, TX work will be scheduled by the threaded
@@ -1440,8 +1515,15 @@ static int wl1271_configure_wowlan(struct wl1271 *wl,
1440 int i, ret; 1515 int i, ret;
1441 1516
1442 if (!wow || wow->any || !wow->n_patterns) { 1517 if (!wow || wow->any || !wow->n_patterns) {
1443 wl1271_acx_default_rx_filter_enable(wl, 0, FILTER_SIGNAL); 1518 ret = wl1271_acx_default_rx_filter_enable(wl, 0,
1444 wl1271_rx_filter_clear_all(wl); 1519 FILTER_SIGNAL);
1520 if (ret)
1521 goto out;
1522
1523 ret = wl1271_rx_filter_clear_all(wl);
1524 if (ret)
1525 goto out;
1526
1445 return 0; 1527 return 0;
1446 } 1528 }
1447 1529
@@ -1457,8 +1539,13 @@ static int wl1271_configure_wowlan(struct wl1271 *wl,
1457 } 1539 }
1458 } 1540 }
1459 1541
1460 wl1271_acx_default_rx_filter_enable(wl, 0, FILTER_SIGNAL); 1542 ret = wl1271_acx_default_rx_filter_enable(wl, 0, FILTER_SIGNAL);
1461 wl1271_rx_filter_clear_all(wl); 1543 if (ret)
1544 goto out;
1545
1546 ret = wl1271_rx_filter_clear_all(wl);
1547 if (ret)
1548 goto out;
1462 1549
1463 /* Translate WoWLAN patterns into filters */ 1550 /* Translate WoWLAN patterns into filters */
1464 for (i = 0; i < wow->n_patterns; i++) { 1551 for (i = 0; i < wow->n_patterns; i++) {
@@ -1500,7 +1587,10 @@ static int wl1271_configure_suspend_sta(struct wl1271 *wl,
1500 if (ret < 0) 1587 if (ret < 0)
1501 goto out; 1588 goto out;
1502 1589
1503 wl1271_configure_wowlan(wl, wow); 1590 ret = wl1271_configure_wowlan(wl, wow);
1591 if (ret < 0)
1592 goto out_sleep;
1593
1504 ret = wl1271_acx_wake_up_conditions(wl, wlvif, 1594 ret = wl1271_acx_wake_up_conditions(wl, wlvif,
1505 wl->conf.conn.suspend_wake_up_event, 1595 wl->conf.conn.suspend_wake_up_event,
1506 wl->conf.conn.suspend_listen_interval); 1596 wl->conf.conn.suspend_listen_interval);
@@ -1508,8 +1598,8 @@ static int wl1271_configure_suspend_sta(struct wl1271 *wl,
1508 if (ret < 0) 1598 if (ret < 0)
1509 wl1271_error("suspend: set wake up conditions failed: %d", ret); 1599 wl1271_error("suspend: set wake up conditions failed: %d", ret);
1510 1600
1601out_sleep:
1511 wl1271_ps_elp_sleep(wl); 1602 wl1271_ps_elp_sleep(wl);
1512
1513out: 1603out:
1514 return ret; 1604 return ret;
1515 1605
@@ -1588,6 +1678,12 @@ static int wl1271_op_suspend(struct ieee80211_hw *hw,
1588 wl1271_debug(DEBUG_MAC80211, "mac80211 suspend wow=%d", !!wow); 1678 wl1271_debug(DEBUG_MAC80211, "mac80211 suspend wow=%d", !!wow);
1589 WARN_ON(!wow); 1679 WARN_ON(!wow);
1590 1680
1681 /* we want to perform the recovery before suspending */
1682 if (test_bit(WL1271_FLAG_RECOVERY_IN_PROGRESS, &wl->flags)) {
1683 wl1271_warning("postponing suspend to perform recovery");
1684 return -EBUSY;
1685 }
1686
1591 wl1271_tx_flush(wl); 1687 wl1271_tx_flush(wl);
1592 1688
1593 mutex_lock(&wl->mutex); 1689 mutex_lock(&wl->mutex);
@@ -1628,7 +1724,8 @@ static int wl1271_op_resume(struct ieee80211_hw *hw)
1628 struct wl1271 *wl = hw->priv; 1724 struct wl1271 *wl = hw->priv;
1629 struct wl12xx_vif *wlvif; 1725 struct wl12xx_vif *wlvif;
1630 unsigned long flags; 1726 unsigned long flags;
1631 bool run_irq_work = false; 1727 bool run_irq_work = false, pending_recovery;
1728 int ret;
1632 1729
1633 wl1271_debug(DEBUG_MAC80211, "mac80211 resume wow=%d", 1730 wl1271_debug(DEBUG_MAC80211, "mac80211 resume wow=%d",
1634 wl->wow_enabled); 1731 wl->wow_enabled);
@@ -1644,17 +1741,37 @@ static int wl1271_op_resume(struct ieee80211_hw *hw)
1644 run_irq_work = true; 1741 run_irq_work = true;
1645 spin_unlock_irqrestore(&wl->wl_lock, flags); 1742 spin_unlock_irqrestore(&wl->wl_lock, flags);
1646 1743
1744 mutex_lock(&wl->mutex);
1745
1746 /* test the recovery flag before calling any SDIO functions */
1747 pending_recovery = test_bit(WL1271_FLAG_RECOVERY_IN_PROGRESS,
1748 &wl->flags);
1749
1647 if (run_irq_work) { 1750 if (run_irq_work) {
1648 wl1271_debug(DEBUG_MAC80211, 1751 wl1271_debug(DEBUG_MAC80211,
1649 "run postponed irq_work directly"); 1752 "run postponed irq_work directly");
1650 wl1271_irq(0, wl); 1753
1754 /* don't talk to the HW if recovery is pending */
1755 if (!pending_recovery) {
1756 ret = wlcore_irq_locked(wl);
1757 if (ret)
1758 wl12xx_queue_recovery_work(wl);
1759 }
1760
1651 wlcore_enable_interrupts(wl); 1761 wlcore_enable_interrupts(wl);
1652 } 1762 }
1653 1763
1654 mutex_lock(&wl->mutex); 1764 if (pending_recovery) {
1765 wl1271_warning("queuing forgotten recovery on resume");
1766 ieee80211_queue_work(wl->hw, &wl->recovery_work);
1767 goto out;
1768 }
1769
1655 wl12xx_for_each_wlvif(wl, wlvif) { 1770 wl12xx_for_each_wlvif(wl, wlvif) {
1656 wl1271_configure_resume(wl, wlvif); 1771 wl1271_configure_resume(wl, wlvif);
1657 } 1772 }
1773
1774out:
1658 wl->wow_enabled = false; 1775 wl->wow_enabled = false;
1659 mutex_unlock(&wl->mutex); 1776 mutex_unlock(&wl->mutex);
1660 1777
@@ -1695,6 +1812,10 @@ static void wl1271_op_stop(struct ieee80211_hw *hw)
1695 wlcore_disable_interrupts(wl); 1812 wlcore_disable_interrupts(wl);
1696 mutex_lock(&wl->mutex); 1813 mutex_lock(&wl->mutex);
1697 if (wl->state == WL1271_STATE_OFF) { 1814 if (wl->state == WL1271_STATE_OFF) {
1815 if (test_and_clear_bit(WL1271_FLAG_RECOVERY_IN_PROGRESS,
1816 &wl->flags))
1817 wlcore_enable_interrupts(wl);
1818
1698 mutex_unlock(&wl->mutex); 1819 mutex_unlock(&wl->mutex);
1699 1820
1700 /* 1821 /*
@@ -1726,6 +1847,13 @@ static void wl1271_op_stop(struct ieee80211_hw *hw)
1726 mutex_lock(&wl->mutex); 1847 mutex_lock(&wl->mutex);
1727 1848
1728 wl1271_power_off(wl); 1849 wl1271_power_off(wl);
1850 /*
1851 * In case a recovery was scheduled, interrupts were disabled to avoid
1852 * an interrupt storm. Now that the power is down, it is safe to
1853 * re-enable interrupts to balance the disable depth
1854 */
1855 if (test_and_clear_bit(WL1271_FLAG_RECOVERY_IN_PROGRESS, &wl->flags))
1856 wlcore_enable_interrupts(wl);
1729 1857
1730 wl->band = IEEE80211_BAND_2GHZ; 1858 wl->band = IEEE80211_BAND_2GHZ;
1731 1859
@@ -1740,6 +1868,7 @@ static void wl1271_op_stop(struct ieee80211_hw *hw)
1740 wl->ap_fw_ps_map = 0; 1868 wl->ap_fw_ps_map = 0;
1741 wl->ap_ps_map = 0; 1869 wl->ap_ps_map = 0;
1742 wl->sched_scanning = false; 1870 wl->sched_scanning = false;
1871 wl->sleep_auth = WL1271_PSM_ILLEGAL;
1743 memset(wl->roles_map, 0, sizeof(wl->roles_map)); 1872 memset(wl->roles_map, 0, sizeof(wl->roles_map));
1744 memset(wl->links_map, 0, sizeof(wl->links_map)); 1873 memset(wl->links_map, 0, sizeof(wl->links_map));
1745 memset(wl->roc_map, 0, sizeof(wl->roc_map)); 1874 memset(wl->roc_map, 0, sizeof(wl->roc_map));
@@ -2146,6 +2275,7 @@ static void __wl1271_op_remove_interface(struct wl1271 *wl,
2146{ 2275{
2147 struct wl12xx_vif *wlvif = wl12xx_vif_to_data(vif); 2276 struct wl12xx_vif *wlvif = wl12xx_vif_to_data(vif);
2148 int i, ret; 2277 int i, ret;
2278 bool is_ap = (wlvif->bss_type == BSS_TYPE_AP_BSS);
2149 2279
2150 wl1271_debug(DEBUG_MAC80211, "mac80211 remove interface"); 2280 wl1271_debug(DEBUG_MAC80211, "mac80211 remove interface");
2151 2281
@@ -2226,11 +2356,25 @@ deinit:
2226 wlvif->role_id = WL12XX_INVALID_ROLE_ID; 2356 wlvif->role_id = WL12XX_INVALID_ROLE_ID;
2227 wlvif->dev_role_id = WL12XX_INVALID_ROLE_ID; 2357 wlvif->dev_role_id = WL12XX_INVALID_ROLE_ID;
2228 2358
2229 if (wlvif->bss_type == BSS_TYPE_AP_BSS) 2359 if (is_ap)
2230 wl->ap_count--; 2360 wl->ap_count--;
2231 else 2361 else
2232 wl->sta_count--; 2362 wl->sta_count--;
2233 2363
2364 /* Last AP, have more stations. Configure according to STA. */
2365 if (wl->ap_count == 0 && is_ap && wl->sta_count) {
2366 u8 sta_auth = wl->conf.conn.sta_sleep_auth;
2367 /* Configure for power according to debugfs */
2368 if (sta_auth != WL1271_PSM_ILLEGAL)
2369 wl1271_acx_sleep_auth(wl, sta_auth);
2370 /* Configure for power always on */
2371 else if (wl->quirks & WLCORE_QUIRK_NO_ELP)
2372 wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
2373 /* Configure for ELP power saving */
2374 else
2375 wl1271_acx_sleep_auth(wl, WL1271_PSM_ELP);
2376 }
2377
2234 mutex_unlock(&wl->mutex); 2378 mutex_unlock(&wl->mutex);
2235 2379
2236 del_timer_sync(&wlvif->rx_streaming_timer); 2380 del_timer_sync(&wlvif->rx_streaming_timer);
@@ -2448,12 +2592,16 @@ static int wl12xx_config_vif(struct wl1271 *wl, struct wl12xx_vif *wlvif,
2448 (wlvif->channel != channel) || 2592 (wlvif->channel != channel) ||
2449 (wlvif->channel_type != conf->channel_type))) { 2593 (wlvif->channel_type != conf->channel_type))) {
2450 /* send all pending packets */ 2594 /* send all pending packets */
2451 wl1271_tx_work_locked(wl); 2595 ret = wlcore_tx_work_locked(wl);
2596 if (ret < 0)
2597 return ret;
2598
2452 wlvif->band = conf->channel->band; 2599 wlvif->band = conf->channel->band;
2453 wlvif->channel = channel; 2600 wlvif->channel = channel;
2454 wlvif->channel_type = conf->channel_type; 2601 wlvif->channel_type = conf->channel_type;
2455 2602
2456 if (is_ap) { 2603 if (is_ap) {
2604 wl1271_set_band_rate(wl, wlvif);
2457 ret = wl1271_init_ap_rates(wl, wlvif); 2605 ret = wl1271_init_ap_rates(wl, wlvif);
2458 if (ret < 0) 2606 if (ret < 0)
2459 wl1271_error("AP rate policy change failed %d", 2607 wl1271_error("AP rate policy change failed %d",
@@ -4090,16 +4238,13 @@ out:
4090static int wl1271_op_get_survey(struct ieee80211_hw *hw, int idx, 4238static int wl1271_op_get_survey(struct ieee80211_hw *hw, int idx,
4091 struct survey_info *survey) 4239 struct survey_info *survey)
4092{ 4240{
4093 struct wl1271 *wl = hw->priv;
4094 struct ieee80211_conf *conf = &hw->conf; 4241 struct ieee80211_conf *conf = &hw->conf;
4095 4242
4096 if (idx != 0) 4243 if (idx != 0)
4097 return -ENOENT; 4244 return -ENOENT;
4098 4245
4099 survey->channel = conf->channel; 4246 survey->channel = conf->channel;
4100 survey->filled = SURVEY_INFO_NOISE_DBM; 4247 survey->filled = 0;
4101 survey->noise = wl->noise;
4102
4103 return 0; 4248 return 0;
4104} 4249}
4105 4250
@@ -4365,9 +4510,14 @@ static int wl1271_op_ampdu_action(struct ieee80211_hw *hw,
4365 4510
4366 case IEEE80211_AMPDU_RX_STOP: 4511 case IEEE80211_AMPDU_RX_STOP:
4367 if (!(*ba_bitmap & BIT(tid))) { 4512 if (!(*ba_bitmap & BIT(tid))) {
4368 ret = -EINVAL; 4513 /*
4369 wl1271_error("no active RX BA session on tid: %d", 4514 * this happens on reconfig - so only output a debug
4515 * message for now, and don't fail the function.
4516 */
4517 wl1271_debug(DEBUG_MAC80211,
4518 "no active RX BA session on tid: %d",
4370 tid); 4519 tid);
4520 ret = 0;
4371 break; 4521 break;
4372 } 4522 }
4373 4523
@@ -4904,18 +5054,22 @@ static int wl12xx_get_hw_info(struct wl1271 *wl)
4904 if (ret < 0) 5054 if (ret < 0)
4905 goto out; 5055 goto out;
4906 5056
4907 wl->chip.id = wlcore_read_reg(wl, REG_CHIP_ID_B); 5057 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &wl->chip.id);
5058 if (ret < 0)
5059 goto out;
4908 5060
4909 wl->fuse_oui_addr = 0; 5061 wl->fuse_oui_addr = 0;
4910 wl->fuse_nic_addr = 0; 5062 wl->fuse_nic_addr = 0;
4911 5063
4912 wl->hw_pg_ver = wl->ops->get_pg_ver(wl); 5064 ret = wl->ops->get_pg_ver(wl, &wl->hw_pg_ver);
5065 if (ret < 0)
5066 goto out;
4913 5067
4914 if (wl->ops->get_mac) 5068 if (wl->ops->get_mac)
4915 wl->ops->get_mac(wl); 5069 ret = wl->ops->get_mac(wl);
4916 5070
4917 wl1271_power_off(wl);
4918out: 5071out:
5072 wl1271_power_off(wl);
4919 return ret; 5073 return ret;
4920} 5074}
4921 5075
@@ -4976,6 +5130,29 @@ static void wl1271_unregister_hw(struct wl1271 *wl)
4976 5130
4977} 5131}
4978 5132
5133static const struct ieee80211_iface_limit wlcore_iface_limits[] = {
5134 {
5135 .max = 2,
5136 .types = BIT(NL80211_IFTYPE_STATION),
5137 },
5138 {
5139 .max = 1,
5140 .types = BIT(NL80211_IFTYPE_AP) |
5141 BIT(NL80211_IFTYPE_P2P_GO) |
5142 BIT(NL80211_IFTYPE_P2P_CLIENT),
5143 },
5144};
5145
5146static const struct ieee80211_iface_combination
5147wlcore_iface_combinations[] = {
5148 {
5149 .num_different_channels = 1,
5150 .max_interfaces = 2,
5151 .limits = wlcore_iface_limits,
5152 .n_limits = ARRAY_SIZE(wlcore_iface_limits),
5153 },
5154};
5155
4979static int wl1271_init_ieee80211(struct wl1271 *wl) 5156static int wl1271_init_ieee80211(struct wl1271 *wl)
4980{ 5157{
4981 static const u32 cipher_suites[] = { 5158 static const u32 cipher_suites[] = {
@@ -5069,6 +5246,11 @@ static int wl1271_init_ieee80211(struct wl1271 *wl)
5069 NL80211_PROBE_RESP_OFFLOAD_SUPPORT_WPS2 | 5246 NL80211_PROBE_RESP_OFFLOAD_SUPPORT_WPS2 |
5070 NL80211_PROBE_RESP_OFFLOAD_SUPPORT_P2P; 5247 NL80211_PROBE_RESP_OFFLOAD_SUPPORT_P2P;
5071 5248
5249 /* allowed interface combinations */
5250 wl->hw->wiphy->iface_combinations = wlcore_iface_combinations;
5251 wl->hw->wiphy->n_iface_combinations =
5252 ARRAY_SIZE(wlcore_iface_combinations);
5253
5072 SET_IEEE80211_DEV(wl->hw, wl->dev); 5254 SET_IEEE80211_DEV(wl->hw, wl->dev);
5073 5255
5074 wl->hw->sta_data_size = sizeof(struct wl1271_station); 5256 wl->hw->sta_data_size = sizeof(struct wl1271_station);
@@ -5140,6 +5322,7 @@ struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size)
5140 wl->channel_type = NL80211_CHAN_NO_HT; 5322 wl->channel_type = NL80211_CHAN_NO_HT;
5141 wl->flags = 0; 5323 wl->flags = 0;
5142 wl->sg_enabled = true; 5324 wl->sg_enabled = true;
5325 wl->sleep_auth = WL1271_PSM_ILLEGAL;
5143 wl->hw_pg_ver = -1; 5326 wl->hw_pg_ver = -1;
5144 wl->ap_ps_map = 0; 5327 wl->ap_ps_map = 0;
5145 wl->ap_fw_ps_map = 0; 5328 wl->ap_fw_ps_map = 0;
@@ -5313,7 +5496,7 @@ int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev)
5313 else 5496 else
5314 irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT; 5497 irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT;
5315 5498
5316 ret = request_threaded_irq(wl->irq, wl12xx_hardirq, wl1271_irq, 5499 ret = request_threaded_irq(wl->irq, wl12xx_hardirq, wlcore_irq,
5317 irqflags, 5500 irqflags,
5318 pdev->name, wl); 5501 pdev->name, wl);
5319 if (ret < 0) { 5502 if (ret < 0) {
@@ -5339,12 +5522,12 @@ int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev)
5339 ret = wl12xx_get_hw_info(wl); 5522 ret = wl12xx_get_hw_info(wl);
5340 if (ret < 0) { 5523 if (ret < 0) {
5341 wl1271_error("couldn't get hw info"); 5524 wl1271_error("couldn't get hw info");
5342 goto out; 5525 goto out_irq;
5343 } 5526 }
5344 5527
5345 ret = wl->ops->identify_chip(wl); 5528 ret = wl->ops->identify_chip(wl);
5346 if (ret < 0) 5529 if (ret < 0)
5347 goto out; 5530 goto out_irq;
5348 5531
5349 ret = wl1271_init_ieee80211(wl); 5532 ret = wl1271_init_ieee80211(wl);
5350 if (ret) 5533 if (ret)
@@ -5358,7 +5541,7 @@ int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev)
5358 ret = device_create_file(wl->dev, &dev_attr_bt_coex_state); 5541 ret = device_create_file(wl->dev, &dev_attr_bt_coex_state);
5359 if (ret < 0) { 5542 if (ret < 0) {
5360 wl1271_error("failed to create sysfs file bt_coex_state"); 5543 wl1271_error("failed to create sysfs file bt_coex_state");
5361 goto out_irq; 5544 goto out_unreg;
5362 } 5545 }
5363 5546
5364 /* Create sysfs file to get HW PG version */ 5547 /* Create sysfs file to get HW PG version */
@@ -5383,6 +5566,9 @@ out_hw_pg_ver:
5383out_bt_coex_state: 5566out_bt_coex_state:
5384 device_remove_file(wl->dev, &dev_attr_bt_coex_state); 5567 device_remove_file(wl->dev, &dev_attr_bt_coex_state);
5385 5568
5569out_unreg:
5570 wl1271_unregister_hw(wl);
5571
5386out_irq: 5572out_irq:
5387 free_irq(wl->irq, wl); 5573 free_irq(wl->irq, wl);
5388 5574
diff --git a/drivers/net/wireless/ti/wlcore/ps.c b/drivers/net/wireless/ti/wlcore/ps.c
index 47e81b32f7da..46d36fd30eba 100644
--- a/drivers/net/wireless/ti/wlcore/ps.c
+++ b/drivers/net/wireless/ti/wlcore/ps.c
@@ -35,6 +35,7 @@ void wl1271_elp_work(struct work_struct *work)
35 struct delayed_work *dwork; 35 struct delayed_work *dwork;
36 struct wl1271 *wl; 36 struct wl1271 *wl;
37 struct wl12xx_vif *wlvif; 37 struct wl12xx_vif *wlvif;
38 int ret;
38 39
39 dwork = container_of(work, struct delayed_work, work); 40 dwork = container_of(work, struct delayed_work, work);
40 wl = container_of(dwork, struct wl1271, elp_work); 41 wl = container_of(dwork, struct wl1271, elp_work);
@@ -63,7 +64,12 @@ void wl1271_elp_work(struct work_struct *work)
63 } 64 }
64 65
65 wl1271_debug(DEBUG_PSM, "chip to elp"); 66 wl1271_debug(DEBUG_PSM, "chip to elp");
66 wl1271_raw_write32(wl, HW_ACCESS_ELP_CTRL_REG, ELPCTRL_SLEEP); 67 ret = wlcore_raw_write32(wl, HW_ACCESS_ELP_CTRL_REG, ELPCTRL_SLEEP);
68 if (ret < 0) {
69 wl12xx_queue_recovery_work(wl);
70 goto out;
71 }
72
67 set_bit(WL1271_FLAG_IN_ELP, &wl->flags); 73 set_bit(WL1271_FLAG_IN_ELP, &wl->flags);
68 74
69out: 75out:
@@ -76,7 +82,7 @@ void wl1271_ps_elp_sleep(struct wl1271 *wl)
76 struct wl12xx_vif *wlvif; 82 struct wl12xx_vif *wlvif;
77 u32 timeout; 83 u32 timeout;
78 84
79 if (wl->quirks & WLCORE_QUIRK_NO_ELP) 85 if (wl->sleep_auth != WL1271_PSM_ELP)
80 return; 86 return;
81 87
82 /* we shouldn't get consecutive sleep requests */ 88 /* we shouldn't get consecutive sleep requests */
@@ -135,7 +141,11 @@ int wl1271_ps_elp_wakeup(struct wl1271 *wl)
135 wl->elp_compl = &compl; 141 wl->elp_compl = &compl;
136 spin_unlock_irqrestore(&wl->wl_lock, flags); 142 spin_unlock_irqrestore(&wl->wl_lock, flags);
137 143
138 wl1271_raw_write32(wl, HW_ACCESS_ELP_CTRL_REG, ELPCTRL_WAKE_UP); 144 ret = wlcore_raw_write32(wl, HW_ACCESS_ELP_CTRL_REG, ELPCTRL_WAKE_UP);
145 if (ret < 0) {
146 wl12xx_queue_recovery_work(wl);
147 goto err;
148 }
139 149
140 if (!pending) { 150 if (!pending) {
141 ret = wait_for_completion_timeout( 151 ret = wait_for_completion_timeout(
diff --git a/drivers/net/wireless/ti/wlcore/rx.c b/drivers/net/wireless/ti/wlcore/rx.c
index 78200dcacfca..f55e2f9e7ac5 100644
--- a/drivers/net/wireless/ti/wlcore/rx.c
+++ b/drivers/net/wireless/ti/wlcore/rx.c
@@ -127,7 +127,7 @@ static int wl1271_rx_handle_data(struct wl1271 *wl, u8 *data, u32 length,
127 } 127 }
128 128
129 if (rx_align == WLCORE_RX_BUF_UNALIGNED) 129 if (rx_align == WLCORE_RX_BUF_UNALIGNED)
130 reserved = NET_IP_ALIGN; 130 reserved = RX_BUF_ALIGN;
131 131
132 /* the data read starts with the descriptor */ 132 /* the data read starts with the descriptor */
133 desc = (struct wl1271_rx_descriptor *) data; 133 desc = (struct wl1271_rx_descriptor *) data;
@@ -175,7 +175,7 @@ static int wl1271_rx_handle_data(struct wl1271 *wl, u8 *data, u32 length,
175 */ 175 */
176 memcpy(buf, data + sizeof(*desc), pkt_data_len); 176 memcpy(buf, data + sizeof(*desc), pkt_data_len);
177 if (rx_align == WLCORE_RX_BUF_PADDED) 177 if (rx_align == WLCORE_RX_BUF_PADDED)
178 skb_pull(skb, NET_IP_ALIGN); 178 skb_pull(skb, RX_BUF_ALIGN);
179 179
180 *hlid = desc->hlid; 180 *hlid = desc->hlid;
181 181
@@ -200,7 +200,7 @@ static int wl1271_rx_handle_data(struct wl1271 *wl, u8 *data, u32 length,
200 return is_data; 200 return is_data;
201} 201}
202 202
203void wl12xx_rx(struct wl1271 *wl, struct wl_fw_status_1 *status) 203int wlcore_rx(struct wl1271 *wl, struct wl_fw_status_1 *status)
204{ 204{
205 unsigned long active_hlids[BITS_TO_LONGS(WL12XX_MAX_LINKS)] = {0}; 205 unsigned long active_hlids[BITS_TO_LONGS(WL12XX_MAX_LINKS)] = {0};
206 u32 buf_size; 206 u32 buf_size;
@@ -211,6 +211,7 @@ void wl12xx_rx(struct wl1271 *wl, struct wl_fw_status_1 *status)
211 u32 pkt_offset, des; 211 u32 pkt_offset, des;
212 u8 hlid; 212 u8 hlid;
213 enum wl_rx_buf_align rx_align; 213 enum wl_rx_buf_align rx_align;
214 int ret = 0;
214 215
215 while (drv_rx_counter != fw_rx_counter) { 216 while (drv_rx_counter != fw_rx_counter) {
216 buf_size = 0; 217 buf_size = 0;
@@ -234,9 +235,14 @@ void wl12xx_rx(struct wl1271 *wl, struct wl_fw_status_1 *status)
234 235
235 /* Read all available packets at once */ 236 /* Read all available packets at once */
236 des = le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]); 237 des = le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]);
237 wlcore_hw_prepare_read(wl, des, buf_size); 238 ret = wlcore_hw_prepare_read(wl, des, buf_size);
238 wlcore_read_data(wl, REG_SLV_MEM_DATA, wl->aggr_buf, 239 if (ret < 0)
239 buf_size, true); 240 goto out;
241
242 ret = wlcore_read_data(wl, REG_SLV_MEM_DATA, wl->aggr_buf,
243 buf_size, true);
244 if (ret < 0)
245 goto out;
240 246
241 /* Split data into separate packets */ 247 /* Split data into separate packets */
242 pkt_offset = 0; 248 pkt_offset = 0;
@@ -273,11 +279,17 @@ void wl12xx_rx(struct wl1271 *wl, struct wl_fw_status_1 *status)
273 * Write the driver's packet counter to the FW. This is only required 279 * Write the driver's packet counter to the FW. This is only required
274 * for older hardware revisions 280 * for older hardware revisions
275 */ 281 */
276 if (wl->quirks & WLCORE_QUIRK_END_OF_TRANSACTION) 282 if (wl->quirks & WLCORE_QUIRK_END_OF_TRANSACTION) {
277 wl1271_write32(wl, WL12XX_REG_RX_DRIVER_COUNTER, 283 ret = wlcore_write32(wl, WL12XX_REG_RX_DRIVER_COUNTER,
278 wl->rx_counter); 284 wl->rx_counter);
285 if (ret < 0)
286 goto out;
287 }
279 288
280 wl12xx_rearm_rx_streaming(wl, active_hlids); 289 wl12xx_rearm_rx_streaming(wl, active_hlids);
290
291out:
292 return ret;
281} 293}
282 294
283#ifdef CONFIG_PM 295#ifdef CONFIG_PM
@@ -306,14 +318,19 @@ int wl1271_rx_filter_enable(struct wl1271 *wl,
306 return 0; 318 return 0;
307} 319}
308 320
309void wl1271_rx_filter_clear_all(struct wl1271 *wl) 321int wl1271_rx_filter_clear_all(struct wl1271 *wl)
310{ 322{
311 int i; 323 int i, ret = 0;
312 324
313 for (i = 0; i < WL1271_MAX_RX_FILTERS; i++) { 325 for (i = 0; i < WL1271_MAX_RX_FILTERS; i++) {
314 if (!wl->rx_filter_enabled[i]) 326 if (!wl->rx_filter_enabled[i])
315 continue; 327 continue;
316 wl1271_rx_filter_enable(wl, i, 0, NULL); 328 ret = wl1271_rx_filter_enable(wl, i, 0, NULL);
329 if (ret)
330 goto out;
317 } 331 }
332
333out:
334 return ret;
318} 335}
319#endif /* CONFIG_PM */ 336#endif /* CONFIG_PM */
diff --git a/drivers/net/wireless/ti/wlcore/rx.h b/drivers/net/wireless/ti/wlcore/rx.h
index 9be780179456..71eba1899915 100644
--- a/drivers/net/wireless/ti/wlcore/rx.h
+++ b/drivers/net/wireless/ti/wlcore/rx.h
@@ -103,6 +103,12 @@
103/* If set, the buffer was padded by the FW to be 4 bytes aligned */ 103/* If set, the buffer was padded by the FW to be 4 bytes aligned */
104#define RX_BUF_PADDED_PAYLOAD BIT(30) 104#define RX_BUF_PADDED_PAYLOAD BIT(30)
105 105
106/*
107 * Account for the padding inserted by the FW in case of RX_ALIGNMENT
108 * or for fixing alignment in case the packet wasn't aligned.
109 */
110#define RX_BUF_ALIGN 2
111
106/* Describes the alignment state of a Rx buffer */ 112/* Describes the alignment state of a Rx buffer */
107enum wl_rx_buf_align { 113enum wl_rx_buf_align {
108 WLCORE_RX_BUF_ALIGNED, 114 WLCORE_RX_BUF_ALIGNED,
@@ -137,11 +143,11 @@ struct wl1271_rx_descriptor {
137 u8 reserved; 143 u8 reserved;
138} __packed; 144} __packed;
139 145
140void wl12xx_rx(struct wl1271 *wl, struct wl_fw_status_1 *status); 146int wlcore_rx(struct wl1271 *wl, struct wl_fw_status_1 *status);
141u8 wl1271_rate_to_idx(int rate, enum ieee80211_band band); 147u8 wl1271_rate_to_idx(int rate, enum ieee80211_band band);
142int wl1271_rx_filter_enable(struct wl1271 *wl, 148int wl1271_rx_filter_enable(struct wl1271 *wl,
143 int index, bool enable, 149 int index, bool enable,
144 struct wl12xx_rx_filter *filter); 150 struct wl12xx_rx_filter *filter);
145void wl1271_rx_filter_clear_all(struct wl1271 *wl); 151int wl1271_rx_filter_clear_all(struct wl1271 *wl);
146 152
147#endif 153#endif
diff --git a/drivers/net/wireless/ti/wlcore/sdio.c b/drivers/net/wireless/ti/wlcore/sdio.c
index c67ec482e445..204e69fa9327 100644
--- a/drivers/net/wireless/ti/wlcore/sdio.c
+++ b/drivers/net/wireless/ti/wlcore/sdio.c
@@ -71,8 +71,8 @@ static void wl1271_sdio_set_block_size(struct device *child,
71 sdio_release_host(func); 71 sdio_release_host(func);
72} 72}
73 73
74static void wl12xx_sdio_raw_read(struct device *child, int addr, void *buf, 74static int __must_check wl12xx_sdio_raw_read(struct device *child, int addr,
75 size_t len, bool fixed) 75 void *buf, size_t len, bool fixed)
76{ 76{
77 int ret; 77 int ret;
78 struct wl12xx_sdio_glue *glue = dev_get_drvdata(child->parent); 78 struct wl12xx_sdio_glue *glue = dev_get_drvdata(child->parent);
@@ -103,12 +103,14 @@ static void wl12xx_sdio_raw_read(struct device *child, int addr, void *buf,
103 103
104 sdio_release_host(func); 104 sdio_release_host(func);
105 105
106 if (ret) 106 if (WARN_ON(ret))
107 dev_err(child->parent, "sdio read failed (%d)\n", ret); 107 dev_err(child->parent, "sdio read failed (%d)\n", ret);
108
109 return ret;
108} 110}
109 111
110static void wl12xx_sdio_raw_write(struct device *child, int addr, void *buf, 112static int __must_check wl12xx_sdio_raw_write(struct device *child, int addr,
111 size_t len, bool fixed) 113 void *buf, size_t len, bool fixed)
112{ 114{
113 int ret; 115 int ret;
114 struct wl12xx_sdio_glue *glue = dev_get_drvdata(child->parent); 116 struct wl12xx_sdio_glue *glue = dev_get_drvdata(child->parent);
@@ -139,25 +141,30 @@ static void wl12xx_sdio_raw_write(struct device *child, int addr, void *buf,
139 141
140 sdio_release_host(func); 142 sdio_release_host(func);
141 143
142 if (ret) 144 if (WARN_ON(ret))
143 dev_err(child->parent, "sdio write failed (%d)\n", ret); 145 dev_err(child->parent, "sdio write failed (%d)\n", ret);
146
147 return ret;
144} 148}
145 149
146static int wl12xx_sdio_power_on(struct wl12xx_sdio_glue *glue) 150static int wl12xx_sdio_power_on(struct wl12xx_sdio_glue *glue)
147{ 151{
148 int ret; 152 int ret;
149 struct sdio_func *func = dev_to_sdio_func(glue->dev); 153 struct sdio_func *func = dev_to_sdio_func(glue->dev);
154 struct mmc_card *card = func->card;
150 155
151 /* If enabled, tell runtime PM not to power off the card */ 156 ret = pm_runtime_get_sync(&card->dev);
152 if (pm_runtime_enabled(&func->dev)) { 157 if (ret) {
153 ret = pm_runtime_get_sync(&func->dev); 158 /*
154 if (ret < 0) 159 * Runtime PM might be temporarily disabled, or the device
155 goto out; 160 * might have a positive reference counter. Make sure it is
156 } else { 161 * really powered on.
157 /* Runtime PM is disabled: power up the card manually */ 162 */
158 ret = mmc_power_restore_host(func->card->host); 163 ret = mmc_power_restore_host(card->host);
159 if (ret < 0) 164 if (ret < 0) {
165 pm_runtime_put_sync(&card->dev);
160 goto out; 166 goto out;
167 }
161 } 168 }
162 169
163 sdio_claim_host(func); 170 sdio_claim_host(func);
@@ -172,20 +179,21 @@ static int wl12xx_sdio_power_off(struct wl12xx_sdio_glue *glue)
172{ 179{
173 int ret; 180 int ret;
174 struct sdio_func *func = dev_to_sdio_func(glue->dev); 181 struct sdio_func *func = dev_to_sdio_func(glue->dev);
182 struct mmc_card *card = func->card;
175 183
176 sdio_claim_host(func); 184 sdio_claim_host(func);
177 sdio_disable_func(func); 185 sdio_disable_func(func);
178 sdio_release_host(func); 186 sdio_release_host(func);
179 187
180 /* Power off the card manually, even if runtime PM is enabled. */ 188 /* Power off the card manually in case it wasn't powered off above */
181 ret = mmc_power_save_host(func->card->host); 189 ret = mmc_power_save_host(card->host);
182 if (ret < 0) 190 if (ret < 0)
183 return ret; 191 goto out;
184 192
185 /* If enabled, let runtime PM know the card is powered off */ 193 /* Let runtime PM know the card is powered off */
186 if (pm_runtime_enabled(&func->dev)) 194 pm_runtime_put_sync(&card->dev);
187 ret = pm_runtime_put_sync(&func->dev);
188 195
196out:
189 return ret; 197 return ret;
190} 198}
191 199
diff --git a/drivers/net/wireless/ti/wlcore/spi.c b/drivers/net/wireless/ti/wlcore/spi.c
index 553cd3cbb98c..6420abae40ee 100644
--- a/drivers/net/wireless/ti/wlcore/spi.c
+++ b/drivers/net/wireless/ti/wlcore/spi.c
@@ -193,8 +193,8 @@ static int wl12xx_spi_read_busy(struct device *child)
193 return -ETIMEDOUT; 193 return -ETIMEDOUT;
194} 194}
195 195
196static void wl12xx_spi_raw_read(struct device *child, int addr, void *buf, 196static int __must_check wl12xx_spi_raw_read(struct device *child, int addr,
197 size_t len, bool fixed) 197 void *buf, size_t len, bool fixed)
198{ 198{
199 struct wl12xx_spi_glue *glue = dev_get_drvdata(child->parent); 199 struct wl12xx_spi_glue *glue = dev_get_drvdata(child->parent);
200 struct wl1271 *wl = dev_get_drvdata(child); 200 struct wl1271 *wl = dev_get_drvdata(child);
@@ -238,7 +238,7 @@ static void wl12xx_spi_raw_read(struct device *child, int addr, void *buf,
238 if (!(busy_buf[WL1271_BUSY_WORD_CNT - 1] & 0x1) && 238 if (!(busy_buf[WL1271_BUSY_WORD_CNT - 1] & 0x1) &&
239 wl12xx_spi_read_busy(child)) { 239 wl12xx_spi_read_busy(child)) {
240 memset(buf, 0, chunk_len); 240 memset(buf, 0, chunk_len);
241 return; 241 return 0;
242 } 242 }
243 243
244 spi_message_init(&m); 244 spi_message_init(&m);
@@ -256,10 +256,12 @@ static void wl12xx_spi_raw_read(struct device *child, int addr, void *buf,
256 buf += chunk_len; 256 buf += chunk_len;
257 len -= chunk_len; 257 len -= chunk_len;
258 } 258 }
259
260 return 0;
259} 261}
260 262
261static void wl12xx_spi_raw_write(struct device *child, int addr, void *buf, 263static int __must_check wl12xx_spi_raw_write(struct device *child, int addr,
262 size_t len, bool fixed) 264 void *buf, size_t len, bool fixed)
263{ 265{
264 struct wl12xx_spi_glue *glue = dev_get_drvdata(child->parent); 266 struct wl12xx_spi_glue *glue = dev_get_drvdata(child->parent);
265 struct spi_transfer t[2 * WSPI_MAX_NUM_OF_CHUNKS]; 267 struct spi_transfer t[2 * WSPI_MAX_NUM_OF_CHUNKS];
@@ -304,6 +306,8 @@ static void wl12xx_spi_raw_write(struct device *child, int addr, void *buf,
304 } 306 }
305 307
306 spi_sync(to_spi_device(glue->dev), &m); 308 spi_sync(to_spi_device(glue->dev), &m);
309
310 return 0;
307} 311}
308 312
309static struct wl1271_if_operations spi_ops = { 313static struct wl1271_if_operations spi_ops = {
diff --git a/drivers/net/wireless/ti/wlcore/testmode.c b/drivers/net/wireless/ti/wlcore/testmode.c
index 0e59ea2cdd39..eeb339d61d1e 100644
--- a/drivers/net/wireless/ti/wlcore/testmode.c
+++ b/drivers/net/wireless/ti/wlcore/testmode.c
@@ -108,6 +108,20 @@ static int wl1271_tm_cmd_test(struct wl1271 *wl, struct nlattr *tb[])
108 } 108 }
109 109
110 if (answer) { 110 if (answer) {
111 /* If we got bip calibration answer print radio status */
112 struct wl1271_cmd_cal_p2g *params =
113 (struct wl1271_cmd_cal_p2g *) buf;
114
115 s16 radio_status = (s16) le16_to_cpu(params->radio_status);
116
117 if (params->test.id == TEST_CMD_P2G_CAL &&
118 radio_status < 0)
119 wl1271_warning("testmode cmd: radio status=%d",
120 radio_status);
121 else
122 wl1271_info("testmode cmd: radio status=%d",
123 radio_status);
124
111 len = nla_total_size(buf_len); 125 len = nla_total_size(buf_len);
112 skb = cfg80211_testmode_alloc_reply_skb(wl->hw->wiphy, len); 126 skb = cfg80211_testmode_alloc_reply_skb(wl->hw->wiphy, len);
113 if (!skb) { 127 if (!skb) {
diff --git a/drivers/net/wireless/ti/wlcore/tx.c b/drivers/net/wireless/ti/wlcore/tx.c
index 9273fdb3aaec..8038a5026933 100644
--- a/drivers/net/wireless/ti/wlcore/tx.c
+++ b/drivers/net/wireless/ti/wlcore/tx.c
@@ -305,11 +305,15 @@ static void wl1271_tx_fill_hdr(struct wl1271 *wl, struct wl12xx_vif *wlvif,
305 if (is_dummy || !wlvif) 305 if (is_dummy || !wlvif)
306 rate_idx = 0; 306 rate_idx = 0;
307 else if (wlvif->bss_type != BSS_TYPE_AP_BSS) { 307 else if (wlvif->bss_type != BSS_TYPE_AP_BSS) {
308 /* if the packets are destined for AP (have a STA entry) 308 /*
309 send them with AP rate policies, otherwise use default 309 * if the packets are destined for AP (have a STA entry)
310 basic rates */ 310 * send them with AP rate policies (EAPOLs are an exception),
311 * otherwise use default basic rates
312 */
311 if (control->flags & IEEE80211_TX_CTL_NO_CCK_RATE) 313 if (control->flags & IEEE80211_TX_CTL_NO_CCK_RATE)
312 rate_idx = wlvif->sta.p2p_rate_idx; 314 rate_idx = wlvif->sta.p2p_rate_idx;
315 else if (skb->protocol == cpu_to_be16(ETH_P_PAE))
316 rate_idx = wlvif->sta.basic_rate_idx;
313 else if (control->control.sta) 317 else if (control->control.sta)
314 rate_idx = wlvif->sta.ap_rate_idx; 318 rate_idx = wlvif->sta.ap_rate_idx;
315 else 319 else
@@ -348,8 +352,10 @@ static int wl1271_prepare_tx_frame(struct wl1271 *wl, struct wl12xx_vif *wlvif,
348 bool is_dummy; 352 bool is_dummy;
349 bool is_gem = false; 353 bool is_gem = false;
350 354
351 if (!skb) 355 if (!skb) {
356 wl1271_error("discarding null skb");
352 return -EINVAL; 357 return -EINVAL;
358 }
353 359
354 info = IEEE80211_SKB_CB(skb); 360 info = IEEE80211_SKB_CB(skb);
355 361
@@ -658,7 +664,17 @@ void wl12xx_rearm_rx_streaming(struct wl1271 *wl, unsigned long *active_hlids)
658 } 664 }
659} 665}
660 666
661void wl1271_tx_work_locked(struct wl1271 *wl) 667/*
668 * Returns failure values only in case of failed bus ops within this function.
669 * wl1271_prepare_tx_frame retvals won't be returned in order to avoid
670 * triggering recovery by higher layers when not necessary.
671 * In case a FW command fails within wl1271_prepare_tx_frame fails a recovery
672 * will be queued in wl1271_cmd_send. -EAGAIN/-EBUSY from prepare_tx_frame
673 * can occur and are legitimate so don't propagate. -EINVAL will emit a WARNING
674 * within prepare_tx_frame code but there's nothing we should do about those
675 * as well.
676 */
677int wlcore_tx_work_locked(struct wl1271 *wl)
662{ 678{
663 struct wl12xx_vif *wlvif; 679 struct wl12xx_vif *wlvif;
664 struct sk_buff *skb; 680 struct sk_buff *skb;
@@ -666,10 +682,11 @@ void wl1271_tx_work_locked(struct wl1271 *wl)
666 u32 buf_offset = 0, last_len = 0; 682 u32 buf_offset = 0, last_len = 0;
667 bool sent_packets = false; 683 bool sent_packets = false;
668 unsigned long active_hlids[BITS_TO_LONGS(WL12XX_MAX_LINKS)] = {0}; 684 unsigned long active_hlids[BITS_TO_LONGS(WL12XX_MAX_LINKS)] = {0};
669 int ret; 685 int ret = 0;
686 int bus_ret = 0;
670 687
671 if (unlikely(wl->state == WL1271_STATE_OFF)) 688 if (unlikely(wl->state == WL1271_STATE_OFF))
672 return; 689 return 0;
673 690
674 while ((skb = wl1271_skb_dequeue(wl))) { 691 while ((skb = wl1271_skb_dequeue(wl))) {
675 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 692 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
@@ -690,8 +707,11 @@ void wl1271_tx_work_locked(struct wl1271 *wl)
690 707
691 buf_offset = wlcore_hw_pre_pkt_send(wl, buf_offset, 708 buf_offset = wlcore_hw_pre_pkt_send(wl, buf_offset,
692 last_len); 709 last_len);
693 wlcore_write_data(wl, REG_SLV_MEM_DATA, wl->aggr_buf, 710 bus_ret = wlcore_write_data(wl, REG_SLV_MEM_DATA,
694 buf_offset, true); 711 wl->aggr_buf, buf_offset, true);
712 if (bus_ret < 0)
713 goto out;
714
695 sent_packets = true; 715 sent_packets = true;
696 buf_offset = 0; 716 buf_offset = 0;
697 continue; 717 continue;
@@ -727,8 +747,11 @@ void wl1271_tx_work_locked(struct wl1271 *wl)
727out_ack: 747out_ack:
728 if (buf_offset) { 748 if (buf_offset) {
729 buf_offset = wlcore_hw_pre_pkt_send(wl, buf_offset, last_len); 749 buf_offset = wlcore_hw_pre_pkt_send(wl, buf_offset, last_len);
730 wlcore_write_data(wl, REG_SLV_MEM_DATA, wl->aggr_buf, 750 bus_ret = wlcore_write_data(wl, REG_SLV_MEM_DATA, wl->aggr_buf,
731 buf_offset, true); 751 buf_offset, true);
752 if (bus_ret < 0)
753 goto out;
754
732 sent_packets = true; 755 sent_packets = true;
733 } 756 }
734 if (sent_packets) { 757 if (sent_packets) {
@@ -736,13 +759,19 @@ out_ack:
736 * Interrupt the firmware with the new packets. This is only 759 * Interrupt the firmware with the new packets. This is only
737 * required for older hardware revisions 760 * required for older hardware revisions
738 */ 761 */
739 if (wl->quirks & WLCORE_QUIRK_END_OF_TRANSACTION) 762 if (wl->quirks & WLCORE_QUIRK_END_OF_TRANSACTION) {
740 wl1271_write32(wl, WL12XX_HOST_WR_ACCESS, 763 bus_ret = wlcore_write32(wl, WL12XX_HOST_WR_ACCESS,
741 wl->tx_packets_count); 764 wl->tx_packets_count);
765 if (bus_ret < 0)
766 goto out;
767 }
742 768
743 wl1271_handle_tx_low_watermark(wl); 769 wl1271_handle_tx_low_watermark(wl);
744 } 770 }
745 wl12xx_rearm_rx_streaming(wl, active_hlids); 771 wl12xx_rearm_rx_streaming(wl, active_hlids);
772
773out:
774 return bus_ret;
746} 775}
747 776
748void wl1271_tx_work(struct work_struct *work) 777void wl1271_tx_work(struct work_struct *work)
@@ -755,7 +784,11 @@ void wl1271_tx_work(struct work_struct *work)
755 if (ret < 0) 784 if (ret < 0)
756 goto out; 785 goto out;
757 786
758 wl1271_tx_work_locked(wl); 787 ret = wlcore_tx_work_locked(wl);
788 if (ret < 0) {
789 wl12xx_queue_recovery_work(wl);
790 goto out;
791 }
759 792
760 wl1271_ps_elp_sleep(wl); 793 wl1271_ps_elp_sleep(wl);
761out: 794out:
@@ -877,21 +910,27 @@ static void wl1271_tx_complete_packet(struct wl1271 *wl,
877} 910}
878 911
879/* Called upon reception of a TX complete interrupt */ 912/* Called upon reception of a TX complete interrupt */
880void wl1271_tx_complete(struct wl1271 *wl) 913int wlcore_tx_complete(struct wl1271 *wl)
881{ 914{
882 struct wl1271_acx_mem_map *memmap = wl->target_mem_map; 915 struct wl1271_acx_mem_map *memmap = wl->target_mem_map;
883 u32 count, fw_counter; 916 u32 count, fw_counter;
884 u32 i; 917 u32 i;
918 int ret;
885 919
886 /* read the tx results from the chipset */ 920 /* read the tx results from the chipset */
887 wl1271_read(wl, le32_to_cpu(memmap->tx_result), 921 ret = wlcore_read(wl, le32_to_cpu(memmap->tx_result),
888 wl->tx_res_if, sizeof(*wl->tx_res_if), false); 922 wl->tx_res_if, sizeof(*wl->tx_res_if), false);
923 if (ret < 0)
924 goto out;
925
889 fw_counter = le32_to_cpu(wl->tx_res_if->tx_result_fw_counter); 926 fw_counter = le32_to_cpu(wl->tx_res_if->tx_result_fw_counter);
890 927
891 /* write host counter to chipset (to ack) */ 928 /* write host counter to chipset (to ack) */
892 wl1271_write32(wl, le32_to_cpu(memmap->tx_result) + 929 ret = wlcore_write32(wl, le32_to_cpu(memmap->tx_result) +
893 offsetof(struct wl1271_tx_hw_res_if, 930 offsetof(struct wl1271_tx_hw_res_if,
894 tx_result_host_counter), fw_counter); 931 tx_result_host_counter), fw_counter);
932 if (ret < 0)
933 goto out;
895 934
896 count = fw_counter - wl->tx_results_count; 935 count = fw_counter - wl->tx_results_count;
897 wl1271_debug(DEBUG_TX, "tx_complete received, packets: %d", count); 936 wl1271_debug(DEBUG_TX, "tx_complete received, packets: %d", count);
@@ -911,8 +950,11 @@ void wl1271_tx_complete(struct wl1271 *wl)
911 950
912 wl->tx_results_count++; 951 wl->tx_results_count++;
913 } 952 }
953
954out:
955 return ret;
914} 956}
915EXPORT_SYMBOL(wl1271_tx_complete); 957EXPORT_SYMBOL(wlcore_tx_complete);
916 958
917void wl1271_tx_reset_link_queues(struct wl1271 *wl, u8 hlid) 959void wl1271_tx_reset_link_queues(struct wl1271 *wl, u8 hlid)
918{ 960{
diff --git a/drivers/net/wireless/ti/wlcore/tx.h b/drivers/net/wireless/ti/wlcore/tx.h
index fa4be1b91135..1e939b016155 100644
--- a/drivers/net/wireless/ti/wlcore/tx.h
+++ b/drivers/net/wireless/ti/wlcore/tx.h
@@ -234,8 +234,8 @@ static inline int wl1271_tx_total_queue_count(struct wl1271 *wl)
234} 234}
235 235
236void wl1271_tx_work(struct work_struct *work); 236void wl1271_tx_work(struct work_struct *work);
237void wl1271_tx_work_locked(struct wl1271 *wl); 237int wlcore_tx_work_locked(struct wl1271 *wl);
238void wl1271_tx_complete(struct wl1271 *wl); 238int wlcore_tx_complete(struct wl1271 *wl);
239void wl12xx_tx_reset_wlvif(struct wl1271 *wl, struct wl12xx_vif *wlvif); 239void wl12xx_tx_reset_wlvif(struct wl1271 *wl, struct wl12xx_vif *wlvif);
240void wl12xx_tx_reset(struct wl1271 *wl); 240void wl12xx_tx_reset(struct wl1271 *wl);
241void wl1271_tx_flush(struct wl1271 *wl); 241void wl1271_tx_flush(struct wl1271 *wl);
diff --git a/drivers/net/wireless/ti/wlcore/wlcore.h b/drivers/net/wireless/ti/wlcore/wlcore.h
index 761a72f4b8d1..e796974df59b 100644
--- a/drivers/net/wireless/ti/wlcore/wlcore.h
+++ b/drivers/net/wireless/ti/wlcore/wlcore.h
@@ -41,9 +41,9 @@ struct wlcore_ops {
41 int (*identify_fw)(struct wl1271 *wl); 41 int (*identify_fw)(struct wl1271 *wl);
42 int (*boot)(struct wl1271 *wl); 42 int (*boot)(struct wl1271 *wl);
43 int (*plt_init)(struct wl1271 *wl); 43 int (*plt_init)(struct wl1271 *wl);
44 void (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr, 44 int (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
45 void *buf, size_t len); 45 void *buf, size_t len);
46 void (*ack_event)(struct wl1271 *wl); 46 int (*ack_event)(struct wl1271 *wl);
47 u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks); 47 u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
48 void (*set_tx_desc_blocks)(struct wl1271 *wl, 48 void (*set_tx_desc_blocks)(struct wl1271 *wl,
49 struct wl1271_tx_hw_descr *desc, 49 struct wl1271_tx_hw_descr *desc,
@@ -53,17 +53,17 @@ struct wlcore_ops {
53 struct sk_buff *skb); 53 struct sk_buff *skb);
54 enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl, 54 enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
55 u32 rx_desc); 55 u32 rx_desc);
56 void (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len); 56 int (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
57 u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data, 57 u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
58 u32 data_len); 58 u32 data_len);
59 void (*tx_delayed_compl)(struct wl1271 *wl); 59 int (*tx_delayed_compl)(struct wl1271 *wl);
60 void (*tx_immediate_compl)(struct wl1271 *wl); 60 void (*tx_immediate_compl)(struct wl1271 *wl);
61 int (*hw_init)(struct wl1271 *wl); 61 int (*hw_init)(struct wl1271 *wl);
62 int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif); 62 int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
63 u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl, 63 u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
64 struct wl12xx_vif *wlvif); 64 struct wl12xx_vif *wlvif);
65 s8 (*get_pg_ver)(struct wl1271 *wl); 65 int (*get_pg_ver)(struct wl1271 *wl, s8 *ver);
66 void (*get_mac)(struct wl1271 *wl); 66 int (*get_mac)(struct wl1271 *wl);
67 void (*set_tx_desc_csum)(struct wl1271 *wl, 67 void (*set_tx_desc_csum)(struct wl1271 *wl,
68 struct wl1271_tx_hw_descr *desc, 68 struct wl1271_tx_hw_descr *desc,
69 struct sk_buff *skb); 69 struct sk_buff *skb);
@@ -387,6 +387,9 @@ struct wl1271 {
387 387
388 /* mutex for protecting the tx_flush function */ 388 /* mutex for protecting the tx_flush function */
389 struct mutex flush_mutex; 389 struct mutex flush_mutex;
390
391 /* sleep auth value currently configured to FW */
392 int sleep_auth;
390}; 393};
391 394
392int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev); 395int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
@@ -398,6 +401,13 @@ int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
398 struct ieee80211_sta *sta, 401 struct ieee80211_sta *sta,
399 struct ieee80211_key_conf *key_conf); 402 struct ieee80211_key_conf *key_conf);
400 403
404static inline void
405wlcore_set_ht_cap(struct wl1271 *wl, enum ieee80211_band band,
406 struct ieee80211_sta_ht_cap *ht_cap)
407{
408 memcpy(&wl->ht_cap[band], ht_cap, sizeof(*ht_cap));
409}
410
401/* Firmware image load chunk size */ 411/* Firmware image load chunk size */
402#define CHUNK_SIZE 16384 412#define CHUNK_SIZE 16384
403 413
diff --git a/drivers/net/wireless/ti/wlcore/wlcore_i.h b/drivers/net/wireless/ti/wlcore/wlcore_i.h
index 8260b1e9288a..4273a21cdde1 100644
--- a/drivers/net/wireless/ti/wlcore/wlcore_i.h
+++ b/drivers/net/wireless/ti/wlcore/wlcore_i.h
@@ -209,10 +209,10 @@ struct wl1271_scan {
209}; 209};
210 210
211struct wl1271_if_operations { 211struct wl1271_if_operations {
212 void (*read)(struct device *child, int addr, void *buf, size_t len, 212 int __must_check (*read)(struct device *child, int addr, void *buf,
213 bool fixed); 213 size_t len, bool fixed);
214 void (*write)(struct device *child, int addr, void *buf, size_t len, 214 int __must_check (*write)(struct device *child, int addr, void *buf,
215 bool fixed); 215 size_t len, bool fixed);
216 void (*reset)(struct device *child); 216 void (*reset)(struct device *child);
217 void (*init)(struct device *child); 217 void (*init)(struct device *child);
218 int (*power)(struct device *child, bool enable); 218 int (*power)(struct device *child, bool enable);
@@ -247,6 +247,7 @@ enum wl12xx_flags {
247 WL1271_FLAG_RECOVERY_IN_PROGRESS, 247 WL1271_FLAG_RECOVERY_IN_PROGRESS,
248 WL1271_FLAG_VIF_CHANGE_IN_PROGRESS, 248 WL1271_FLAG_VIF_CHANGE_IN_PROGRESS,
249 WL1271_FLAG_INTENDED_FW_RECOVERY, 249 WL1271_FLAG_INTENDED_FW_RECOVERY,
250 WL1271_FLAG_SDIO_FAILED,
250}; 251};
251 252
252enum wl12xx_vif_flags { 253enum wl12xx_vif_flags {