diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/edac/edac_mce_amd.c | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/drivers/edac/edac_mce_amd.c b/drivers/edac/edac_mce_amd.c index 9014df6f605d..564fe7c75345 100644 --- a/drivers/edac/edac_mce_amd.c +++ b/drivers/edac/edac_mce_amd.c | |||
@@ -133,7 +133,7 @@ static void amd_decode_dc_mce(u64 mc0_status) | |||
133 | u32 ec = mc0_status & 0xffff; | 133 | u32 ec = mc0_status & 0xffff; |
134 | u32 xec = (mc0_status >> 16) & 0xf; | 134 | u32 xec = (mc0_status >> 16) & 0xf; |
135 | 135 | ||
136 | pr_emerg("Data Cache Error"); | 136 | pr_emerg(HW_ERR "Data Cache Error: "); |
137 | 137 | ||
138 | if (xec == 1 && TLB_ERROR(ec)) | 138 | if (xec == 1 && TLB_ERROR(ec)) |
139 | pr_cont(": %s TLB multimatch.\n", LL_MSG(ec)); | 139 | pr_cont(": %s TLB multimatch.\n", LL_MSG(ec)); |
@@ -168,7 +168,7 @@ static void amd_decode_dc_mce(u64 mc0_status) | |||
168 | return; | 168 | return; |
169 | 169 | ||
170 | wrong_dc_mce: | 170 | wrong_dc_mce: |
171 | pr_warning("Corrupted DC MCE info?\n"); | 171 | pr_emerg(HW_ERR "Corrupted DC MCE info?\n"); |
172 | } | 172 | } |
173 | 173 | ||
174 | static void amd_decode_ic_mce(u64 mc1_status) | 174 | static void amd_decode_ic_mce(u64 mc1_status) |
@@ -176,7 +176,7 @@ static void amd_decode_ic_mce(u64 mc1_status) | |||
176 | u32 ec = mc1_status & 0xffff; | 176 | u32 ec = mc1_status & 0xffff; |
177 | u32 xec = (mc1_status >> 16) & 0xf; | 177 | u32 xec = (mc1_status >> 16) & 0xf; |
178 | 178 | ||
179 | pr_emerg("Instruction Cache Error"); | 179 | pr_emerg(HW_ERR "Instruction Cache Error"); |
180 | 180 | ||
181 | if (xec == 1 && TLB_ERROR(ec)) | 181 | if (xec == 1 && TLB_ERROR(ec)) |
182 | pr_cont(": %s TLB multimatch.\n", LL_MSG(ec)); | 182 | pr_cont(": %s TLB multimatch.\n", LL_MSG(ec)); |
@@ -225,7 +225,7 @@ static void amd_decode_ic_mce(u64 mc1_status) | |||
225 | return; | 225 | return; |
226 | 226 | ||
227 | wrong_ic_mce: | 227 | wrong_ic_mce: |
228 | pr_warning("Corrupted IC MCE info?\n"); | 228 | pr_emerg(HW_ERR "Corrupted IC MCE info?\n"); |
229 | } | 229 | } |
230 | 230 | ||
231 | static void amd_decode_bu_mce(u64 mc2_status) | 231 | static void amd_decode_bu_mce(u64 mc2_status) |
@@ -233,7 +233,7 @@ static void amd_decode_bu_mce(u64 mc2_status) | |||
233 | u32 ec = mc2_status & 0xffff; | 233 | u32 ec = mc2_status & 0xffff; |
234 | u32 xec = (mc2_status >> 16) & 0xf; | 234 | u32 xec = (mc2_status >> 16) & 0xf; |
235 | 235 | ||
236 | pr_emerg("Bus Unit Error"); | 236 | pr_emerg(HW_ERR "Bus Unit Error"); |
237 | 237 | ||
238 | if (xec == 0x1) | 238 | if (xec == 0x1) |
239 | pr_cont(" in the write data buffers.\n"); | 239 | pr_cont(" in the write data buffers.\n"); |
@@ -267,7 +267,7 @@ static void amd_decode_bu_mce(u64 mc2_status) | |||
267 | return; | 267 | return; |
268 | 268 | ||
269 | wrong_bu_mce: | 269 | wrong_bu_mce: |
270 | pr_warning("Corrupted BU MCE info?\n"); | 270 | pr_emerg(HW_ERR "Corrupted BU MCE info?\n"); |
271 | } | 271 | } |
272 | 272 | ||
273 | static void amd_decode_ls_mce(u64 mc3_status) | 273 | static void amd_decode_ls_mce(u64 mc3_status) |
@@ -275,7 +275,7 @@ static void amd_decode_ls_mce(u64 mc3_status) | |||
275 | u32 ec = mc3_status & 0xffff; | 275 | u32 ec = mc3_status & 0xffff; |
276 | u32 xec = (mc3_status >> 16) & 0xf; | 276 | u32 xec = (mc3_status >> 16) & 0xf; |
277 | 277 | ||
278 | pr_emerg("Load Store Error"); | 278 | pr_emerg(HW_ERR "Load Store Error"); |
279 | 279 | ||
280 | if (xec == 0x0) { | 280 | if (xec == 0x0) { |
281 | u8 rrrr = (ec >> 4) & 0xf; | 281 | u8 rrrr = (ec >> 4) & 0xf; |
@@ -288,7 +288,7 @@ static void amd_decode_ls_mce(u64 mc3_status) | |||
288 | return; | 288 | return; |
289 | 289 | ||
290 | wrong_ls_mce: | 290 | wrong_ls_mce: |
291 | pr_warning("Corrupted LS MCE info?\n"); | 291 | pr_emerg(HW_ERR "Corrupted LS MCE info?\n"); |
292 | } | 292 | } |
293 | 293 | ||
294 | void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors) | 294 | void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors) |
@@ -304,7 +304,7 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors) | |||
304 | if (TLB_ERROR(ec) && !report_gart_errors) | 304 | if (TLB_ERROR(ec) && !report_gart_errors) |
305 | return; | 305 | return; |
306 | 306 | ||
307 | pr_emerg("Northbridge Error, node %d", node_id); | 307 | pr_emerg(HW_ERR "Northbridge Error, node %d", node_id); |
308 | 308 | ||
309 | /* | 309 | /* |
310 | * F10h, revD can disable ErrCpu[3:0] so check that first and also the | 310 | * F10h, revD can disable ErrCpu[3:0] so check that first and also the |
@@ -323,7 +323,7 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors) | |||
323 | pr_cont("\n"); | 323 | pr_cont("\n"); |
324 | } | 324 | } |
325 | 325 | ||
326 | pr_emerg("%s.\n", EXT_ERR_MSG(regs->nbsl)); | 326 | pr_emerg(HW_ERR "%s.\n", EXT_ERR_MSG(regs->nbsl)); |
327 | 327 | ||
328 | if (BUS_ERROR(ec) && nb_bus_decoder) | 328 | if (BUS_ERROR(ec) && nb_bus_decoder) |
329 | nb_bus_decoder(node_id, regs); | 329 | nb_bus_decoder(node_id, regs); |
@@ -334,26 +334,26 @@ static void amd_decode_fr_mce(u64 mc5_status) | |||
334 | { | 334 | { |
335 | /* we have only one error signature so match all fields at once. */ | 335 | /* we have only one error signature so match all fields at once. */ |
336 | if ((mc5_status & 0xffff) == 0x0f0f) | 336 | if ((mc5_status & 0xffff) == 0x0f0f) |
337 | pr_emerg(" FR Error: CPU Watchdog timer expire.\n"); | 337 | pr_emerg(HW_ERR " FR Error: CPU Watchdog timer expire.\n"); |
338 | else | 338 | else |
339 | pr_warning("Corrupted FR MCE info?\n"); | 339 | pr_emerg(HW_ERR "Corrupted FR MCE info?\n"); |
340 | } | 340 | } |
341 | 341 | ||
342 | static inline void amd_decode_err_code(unsigned int ec) | 342 | static inline void amd_decode_err_code(unsigned int ec) |
343 | { | 343 | { |
344 | if (TLB_ERROR(ec)) { | 344 | if (TLB_ERROR(ec)) { |
345 | pr_emerg("Transaction: %s, Cache Level %s\n", | 345 | pr_emerg(HW_ERR "Transaction: %s, Cache Level: %s\n", |
346 | TT_MSG(ec), LL_MSG(ec)); | 346 | TT_MSG(ec), LL_MSG(ec)); |
347 | } else if (MEM_ERROR(ec)) { | 347 | } else if (MEM_ERROR(ec)) { |
348 | pr_emerg("Transaction: %s, Type: %s, Cache Level: %s", | 348 | pr_emerg(HW_ERR "Transaction: %s, Type: %s, Cache Level: %s", |
349 | RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec)); | 349 | RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec)); |
350 | } else if (BUS_ERROR(ec)) { | 350 | } else if (BUS_ERROR(ec)) { |
351 | pr_emerg("Transaction type: %s(%s), %s, Cache Level: %s, " | 351 | pr_emerg(HW_ERR "Transaction type: %s(%s), %s, Cache Level: %s, " |
352 | "Participating Processor: %s\n", | 352 | "Participating Processor: %s\n", |
353 | RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec), | 353 | RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec), |
354 | PP_MSG(ec)); | 354 | PP_MSG(ec)); |
355 | } else | 355 | } else |
356 | pr_warning("Huh? Unknown MCE error 0x%x\n", ec); | 356 | pr_emerg(HW_ERR "Huh? Unknown MCE error 0x%x\n", ec); |
357 | } | 357 | } |
358 | 358 | ||
359 | static int amd_decode_mce(struct notifier_block *nb, unsigned long val, | 359 | static int amd_decode_mce(struct notifier_block *nb, unsigned long val, |
@@ -363,7 +363,7 @@ static int amd_decode_mce(struct notifier_block *nb, unsigned long val, | |||
363 | struct err_regs regs; | 363 | struct err_regs regs; |
364 | int node, ecc; | 364 | int node, ecc; |
365 | 365 | ||
366 | pr_emerg("MC%d_STATUS: ", m->bank); | 366 | pr_emerg(HW_ERR "MC%d_STATUS: ", m->bank); |
367 | 367 | ||
368 | pr_cont("%sorrected error, other errors lost: %s, " | 368 | pr_cont("%sorrected error, other errors lost: %s, " |
369 | "CPU context corrupt: %s", | 369 | "CPU context corrupt: %s", |