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-rw-r--r--drivers/ata/Kconfig10
-rw-r--r--drivers/ata/Makefile1
-rw-r--r--drivers/ata/pata_icside.c686
-rw-r--r--drivers/i2c/busses/i2c-pxa.c18
-rw-r--r--drivers/mmc/host/pxamci.c4
-rw-r--r--drivers/net/irda/pxaficp_ir.c12
-rw-r--r--drivers/serial/amba-pl010.c295
-rw-r--r--drivers/serial/atmel_serial.c9
-rw-r--r--drivers/serial/atmel_serial.h3
-rw-r--r--drivers/serial/imx.c268
-rw-r--r--drivers/serial/pxa.c8
-rw-r--r--drivers/usb/gadget/pxa2xx_udc.c4
-rw-r--r--drivers/usb/host/ohci-pxa27x.c4
-rw-r--r--drivers/video/pxafb.c4
14 files changed, 1109 insertions, 217 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 365c306c7cf8..45dbdc14915f 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -550,13 +550,21 @@ config PATA_WINBOND_VLB
550 550
551config PATA_PLATFORM 551config PATA_PLATFORM
552 tristate "Generic platform device PATA support" 552 tristate "Generic platform device PATA support"
553 depends on EMBEDDED 553 depends on EMBEDDED || ARCH_RPC
554 help 554 help
555 This option enables support for generic directly connected ATA 555 This option enables support for generic directly connected ATA
556 devices commonly found on embedded systems. 556 devices commonly found on embedded systems.
557 557
558 If unsure, say N. 558 If unsure, say N.
559 559
560config PATA_ICSIDE
561 tristate "Acorn ICS PATA support"
562 depends on ARM && ARCH_ACORN
563 help
564 On Acorn systems, say Y here if you wish to use the ICS PATA
565 interface card. This is not required for ICS partition support.
566 If you are unsure, say N to this.
567
560config PATA_IXP4XX_CF 568config PATA_IXP4XX_CF
561 tristate "IXP4XX Compact Flash support" 569 tristate "IXP4XX Compact Flash support"
562 depends on ARCH_IXP4XX 570 depends on ARCH_IXP4XX
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index b7055e302650..6f42a0e2812d 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -62,6 +62,7 @@ obj-$(CONFIG_PATA_TRIFLEX) += pata_triflex.o
62obj-$(CONFIG_PATA_IXP4XX_CF) += pata_ixp4xx_cf.o 62obj-$(CONFIG_PATA_IXP4XX_CF) += pata_ixp4xx_cf.o
63obj-$(CONFIG_PATA_SCC) += pata_scc.o 63obj-$(CONFIG_PATA_SCC) += pata_scc.o
64obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o 64obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o
65obj-$(CONFIG_PATA_ICSIDE) += pata_icside.o
65# Should be last but one libata driver 66# Should be last but one libata driver
66obj-$(CONFIG_ATA_GENERIC) += ata_generic.o 67obj-$(CONFIG_ATA_GENERIC) += ata_generic.o
67# Should be last libata driver 68# Should be last libata driver
diff --git a/drivers/ata/pata_icside.c b/drivers/ata/pata_icside.c
new file mode 100644
index 000000000000..dbc8ee2adcf0
--- /dev/null
+++ b/drivers/ata/pata_icside.c
@@ -0,0 +1,686 @@
1#include <linux/kernel.h>
2#include <linux/module.h>
3#include <linux/init.h>
4#include <linux/blkdev.h>
5#include <scsi/scsi_host.h>
6#include <linux/ata.h>
7#include <linux/libata.h>
8
9#include <asm/dma.h>
10#include <asm/ecard.h>
11
12#define DRV_NAME "pata_icside"
13
14#define ICS_IDENT_OFFSET 0x2280
15
16#define ICS_ARCIN_V5_INTRSTAT 0x0000
17#define ICS_ARCIN_V5_INTROFFSET 0x0004
18
19#define ICS_ARCIN_V6_INTROFFSET_1 0x2200
20#define ICS_ARCIN_V6_INTRSTAT_1 0x2290
21#define ICS_ARCIN_V6_INTROFFSET_2 0x3200
22#define ICS_ARCIN_V6_INTRSTAT_2 0x3290
23
24struct portinfo {
25 unsigned int dataoffset;
26 unsigned int ctrloffset;
27 unsigned int stepping;
28};
29
30static const struct portinfo pata_icside_portinfo_v5 = {
31 .dataoffset = 0x2800,
32 .ctrloffset = 0x2b80,
33 .stepping = 6,
34};
35
36static const struct portinfo pata_icside_portinfo_v6_1 = {
37 .dataoffset = 0x2000,
38 .ctrloffset = 0x2380,
39 .stepping = 6,
40};
41
42static const struct portinfo pata_icside_portinfo_v6_2 = {
43 .dataoffset = 0x3000,
44 .ctrloffset = 0x3380,
45 .stepping = 6,
46};
47
48#define PATA_ICSIDE_MAX_SG 128
49
50struct pata_icside_state {
51 void __iomem *irq_port;
52 void __iomem *ioc_base;
53 unsigned int type;
54 unsigned int dma;
55 struct {
56 u8 port_sel;
57 u8 disabled;
58 unsigned int speed[ATA_MAX_DEVICES];
59 } port[2];
60 struct scatterlist sg[PATA_ICSIDE_MAX_SG];
61};
62
63#define ICS_TYPE_A3IN 0
64#define ICS_TYPE_A3USER 1
65#define ICS_TYPE_V6 3
66#define ICS_TYPE_V5 15
67#define ICS_TYPE_NOTYPE ((unsigned int)-1)
68
69/* ---------------- Version 5 PCB Support Functions --------------------- */
70/* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
71 * Purpose : enable interrupts from card
72 */
73static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
74{
75 struct pata_icside_state *state = ec->irq_data;
76
77 writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
78}
79
80/* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
81 * Purpose : disable interrupts from card
82 */
83static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
84{
85 struct pata_icside_state *state = ec->irq_data;
86
87 readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
88}
89
90static const expansioncard_ops_t pata_icside_ops_arcin_v5 = {
91 .irqenable = pata_icside_irqenable_arcin_v5,
92 .irqdisable = pata_icside_irqdisable_arcin_v5,
93};
94
95
96/* ---------------- Version 6 PCB Support Functions --------------------- */
97/* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
98 * Purpose : enable interrupts from card
99 */
100static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
101{
102 struct pata_icside_state *state = ec->irq_data;
103 void __iomem *base = state->irq_port;
104
105 if (!state->port[0].disabled)
106 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
107 if (!state->port[1].disabled)
108 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
109}
110
111/* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
112 * Purpose : disable interrupts from card
113 */
114static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
115{
116 struct pata_icside_state *state = ec->irq_data;
117
118 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
119 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
120}
121
122/* Prototype: pata_icside_irqprobe(struct expansion_card *ec)
123 * Purpose : detect an active interrupt from card
124 */
125static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec)
126{
127 struct pata_icside_state *state = ec->irq_data;
128
129 return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
130 readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
131}
132
133static const expansioncard_ops_t pata_icside_ops_arcin_v6 = {
134 .irqenable = pata_icside_irqenable_arcin_v6,
135 .irqdisable = pata_icside_irqdisable_arcin_v6,
136 .irqpending = pata_icside_irqpending_arcin_v6,
137};
138
139
140/*
141 * SG-DMA support.
142 *
143 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
144 * There is only one DMA controller per card, which means that only
145 * one drive can be accessed at one time. NOTE! We do not enforce that
146 * here, but we rely on the main IDE driver spotting that both
147 * interfaces use the same IRQ, which should guarantee this.
148 */
149
150/*
151 * Configure the IOMD to give the appropriate timings for the transfer
152 * mode being requested. We take the advice of the ATA standards, and
153 * calculate the cycle time based on the transfer mode, and the EIDE
154 * MW DMA specs that the drive provides in the IDENTIFY command.
155 *
156 * We have the following IOMD DMA modes to choose from:
157 *
158 * Type Active Recovery Cycle
159 * A 250 (250) 312 (550) 562 (800)
160 * B 187 (200) 250 (550) 437 (750)
161 * C 125 (125) 125 (375) 250 (500)
162 * D 62 (50) 125 (375) 187 (425)
163 *
164 * (figures in brackets are actual measured timings on DIOR/DIOW)
165 *
166 * However, we also need to take care of the read/write active and
167 * recovery timings:
168 *
169 * Read Write
170 * Mode Active -- Recovery -- Cycle IOMD type
171 * MW0 215 50 215 480 A
172 * MW1 80 50 50 150 C
173 * MW2 70 25 25 120 C
174 */
175static void pata_icside_set_dmamode(struct ata_port *ap, struct ata_device *adev)
176{
177 struct pata_icside_state *state = ap->host->private_data;
178 struct ata_timing t;
179 unsigned int cycle;
180 char iomd_type;
181
182 /*
183 * DMA is based on a 16MHz clock
184 */
185 if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1))
186 return;
187
188 /*
189 * Choose the IOMD cycle timing which ensure that the interface
190 * satisfies the measured active, recovery and cycle times.
191 */
192 if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425)
193 iomd_type = 'D', cycle = 187;
194 else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500)
195 iomd_type = 'C', cycle = 250;
196 else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750)
197 iomd_type = 'B', cycle = 437;
198 else
199 iomd_type = 'A', cycle = 562;
200
201 ata_dev_printk(adev, KERN_INFO, "timings: act %dns rec %dns cyc %dns (%c)\n",
202 t.active, t.recover, t.cycle, iomd_type);
203
204 state->port[ap->port_no].speed[adev->devno] = cycle;
205}
206
207static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc)
208{
209 struct ata_port *ap = qc->ap;
210 struct pata_icside_state *state = ap->host->private_data;
211 struct scatterlist *sg, *rsg = state->sg;
212 unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE;
213
214 /*
215 * We are simplex; BUG if we try to fiddle with DMA
216 * while it's active.
217 */
218 BUG_ON(dma_channel_active(state->dma));
219
220 /*
221 * Copy ATAs scattered sg list into a contiguous array of sg
222 */
223 ata_for_each_sg(sg, qc) {
224 memcpy(rsg, sg, sizeof(*sg));
225 rsg++;
226 }
227
228 /*
229 * Route the DMA signals to the correct interface
230 */
231 writeb(state->port[ap->port_no].port_sel, state->ioc_base);
232
233 set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]);
234 set_dma_sg(state->dma, state->sg, rsg - state->sg);
235 set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ);
236
237 /* issue r/w command */
238 ap->ops->exec_command(ap, &qc->tf);
239}
240
241static void pata_icside_bmdma_start(struct ata_queued_cmd *qc)
242{
243 struct ata_port *ap = qc->ap;
244 struct pata_icside_state *state = ap->host->private_data;
245
246 BUG_ON(dma_channel_active(state->dma));
247 enable_dma(state->dma);
248}
249
250static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc)
251{
252 struct ata_port *ap = qc->ap;
253 struct pata_icside_state *state = ap->host->private_data;
254
255 disable_dma(state->dma);
256
257 /* see ata_bmdma_stop */
258 ata_altstatus(ap);
259}
260
261static u8 pata_icside_bmdma_status(struct ata_port *ap)
262{
263 struct pata_icside_state *state = ap->host->private_data;
264 void __iomem *irq_port;
265
266 irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 :
267 ICS_ARCIN_V6_INTRSTAT_1);
268
269 return readb(irq_port) & 1 ? ATA_DMA_INTR : 0;
270}
271
272static int icside_dma_init(struct ata_probe_ent *ae, struct expansion_card *ec)
273{
274 struct pata_icside_state *state = ae->private_data;
275 int i;
276
277 for (i = 0; i < ATA_MAX_DEVICES; i++) {
278 state->port[0].speed[i] = 480;
279 state->port[1].speed[i] = 480;
280 }
281
282 if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
283 state->dma = ec->dma;
284 ae->mwdma_mask = 0x07; /* MW0..2 */
285 }
286
287 return 0;
288}
289
290
291static int pata_icside_port_start(struct ata_port *ap)
292{
293 /* No PRD to alloc */
294 return ata_pad_alloc(ap, ap->dev);
295}
296
297static struct scsi_host_template pata_icside_sht = {
298 .module = THIS_MODULE,
299 .name = DRV_NAME,
300 .ioctl = ata_scsi_ioctl,
301 .queuecommand = ata_scsi_queuecmd,
302 .can_queue = ATA_DEF_QUEUE,
303 .this_id = ATA_SHT_THIS_ID,
304 .sg_tablesize = PATA_ICSIDE_MAX_SG,
305 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
306 .emulated = ATA_SHT_EMULATED,
307 .use_clustering = ATA_SHT_USE_CLUSTERING,
308 .proc_name = DRV_NAME,
309 .dma_boundary = ~0, /* no dma boundaries */
310 .slave_configure = ata_scsi_slave_config,
311 .slave_destroy = ata_scsi_slave_destroy,
312 .bios_param = ata_std_bios_param,
313};
314
315/* wish this was exported from libata-core */
316static void ata_dummy_noret(struct ata_port *port)
317{
318}
319
320/*
321 * We need to shut down unused ports to prevent spurious interrupts.
322 * FIXME: the libata core doesn't call this function for PATA interfaces.
323 */
324static void pata_icside_port_disable(struct ata_port *ap)
325{
326 struct pata_icside_state *state = ap->host->private_data;
327
328 ata_port_printk(ap, KERN_ERR, "disabling icside port\n");
329
330 ata_port_disable(ap);
331
332 state->port[ap->port_no].disabled = 1;
333
334 if (state->type == ICS_TYPE_V6) {
335 /*
336 * Disable interrupts from this port, otherwise we
337 * receive spurious interrupts from the floating
338 * interrupt line.
339 */
340 void __iomem *irq_port = state->irq_port +
341 (ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1);
342 readb(irq_port);
343 }
344}
345
346static u8 pata_icside_irq_ack(struct ata_port *ap, unsigned int chk_drq)
347{
348 unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY;
349 u8 status;
350
351 status = ata_busy_wait(ap, bits, 1000);
352 if (status & bits)
353 if (ata_msg_err(ap))
354 printk(KERN_ERR "abnormal status 0x%X\n", status);
355
356 if (ata_msg_intr(ap))
357 printk(KERN_INFO "%s: irq ack: drv_stat 0x%X\n",
358 __FUNCTION__, status);
359
360 return status;
361}
362
363static struct ata_port_operations pata_icside_port_ops = {
364 .port_disable = pata_icside_port_disable,
365
366 .set_dmamode = pata_icside_set_dmamode,
367
368 .tf_load = ata_tf_load,
369 .tf_read = ata_tf_read,
370 .exec_command = ata_exec_command,
371 .check_status = ata_check_status,
372 .dev_select = ata_std_dev_select,
373
374 .bmdma_setup = pata_icside_bmdma_setup,
375 .bmdma_start = pata_icside_bmdma_start,
376
377 .data_xfer = ata_data_xfer_noirq,
378
379 /* no need to build any PRD tables for DMA */
380 .qc_prep = ata_noop_qc_prep,
381 .qc_issue = ata_qc_issue_prot,
382
383 .freeze = ata_bmdma_freeze,
384 .thaw = ata_bmdma_thaw,
385 .error_handler = ata_bmdma_error_handler,
386 .post_internal_cmd = pata_icside_bmdma_stop,
387
388 .irq_handler = ata_interrupt,
389 .irq_clear = ata_dummy_noret,
390 .irq_on = ata_irq_on,
391 .irq_ack = pata_icside_irq_ack,
392
393 .port_start = pata_icside_port_start,
394
395 .bmdma_stop = pata_icside_bmdma_stop,
396 .bmdma_status = pata_icside_bmdma_status,
397};
398
399static void
400pata_icside_add_port(struct ata_probe_ent *ae, void __iomem *base,
401 const struct portinfo *info)
402{
403 struct ata_ioports *ioaddr = &ae->port[ae->n_ports++];
404 void __iomem *cmd = base + info->dataoffset;
405
406 ioaddr->cmd_addr = cmd;
407 ioaddr->data_addr = cmd + (ATA_REG_DATA << info->stepping);
408 ioaddr->error_addr = cmd + (ATA_REG_ERR << info->stepping);
409 ioaddr->feature_addr = cmd + (ATA_REG_FEATURE << info->stepping);
410 ioaddr->nsect_addr = cmd + (ATA_REG_NSECT << info->stepping);
411 ioaddr->lbal_addr = cmd + (ATA_REG_LBAL << info->stepping);
412 ioaddr->lbam_addr = cmd + (ATA_REG_LBAM << info->stepping);
413 ioaddr->lbah_addr = cmd + (ATA_REG_LBAH << info->stepping);
414 ioaddr->device_addr = cmd + (ATA_REG_DEVICE << info->stepping);
415 ioaddr->status_addr = cmd + (ATA_REG_STATUS << info->stepping);
416 ioaddr->command_addr = cmd + (ATA_REG_CMD << info->stepping);
417
418 ioaddr->ctl_addr = base + info->ctrloffset;
419 ioaddr->altstatus_addr = ioaddr->ctl_addr;
420}
421
422static int __init
423pata_icside_register_v5(struct ata_probe_ent *ae, struct expansion_card *ec)
424{
425 struct pata_icside_state *state = ae->private_data;
426 void __iomem *base;
427
428 base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC),
429 ecard_resource_len(ec, ECARD_RES_MEMC));
430 if (!base)
431 return -ENOMEM;
432
433 state->irq_port = base;
434
435 ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
436 ec->irqmask = 1;
437 ec->irq_data = state;
438 ec->ops = &pata_icside_ops_arcin_v5;
439
440 /*
441 * Be on the safe side - disable interrupts
442 */
443 ec->ops->irqdisable(ec, ec->irq);
444
445 pata_icside_add_port(ae, base, &pata_icside_portinfo_v5);
446
447 return 0;
448}
449
450static int __init
451pata_icside_register_v6(struct ata_probe_ent *ae, struct expansion_card *ec)
452{
453 struct pata_icside_state *state = ae->private_data;
454 void __iomem *ioc_base, *easi_base;
455 unsigned int sel = 0;
456 int ret;
457
458 ioc_base = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST),
459 ecard_resource_len(ec, ECARD_RES_IOCFAST));
460 if (!ioc_base) {
461 ret = -ENOMEM;
462 goto out;
463 }
464
465 easi_base = ioc_base;
466
467 if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
468 easi_base = ioremap(ecard_resource_start(ec, ECARD_RES_EASI),
469 ecard_resource_len(ec, ECARD_RES_EASI));
470 if (!easi_base) {
471 ret = -ENOMEM;
472 goto unmap_slot;
473 }
474
475 /*
476 * Enable access to the EASI region.
477 */
478 sel = 1 << 5;
479 }
480
481 writeb(sel, ioc_base);
482
483 ec->irq_data = state;
484 ec->ops = &pata_icside_ops_arcin_v6;
485
486 state->irq_port = easi_base;
487 state->ioc_base = ioc_base;
488 state->port[0].port_sel = sel;
489 state->port[1].port_sel = sel | 1;
490
491 /*
492 * Be on the safe side - disable interrupts
493 */
494 ec->ops->irqdisable(ec, ec->irq);
495
496 /*
497 * Find and register the interfaces.
498 */
499 pata_icside_add_port(ae, easi_base, &pata_icside_portinfo_v6_1);
500 pata_icside_add_port(ae, easi_base, &pata_icside_portinfo_v6_2);
501
502 /*
503 * FIXME: work around libata's aversion to calling port_disable.
504 * This permanently disables interrupts on port 0 - bad luck if
505 * you have a drive on that port.
506 */
507 state->port[0].disabled = 1;
508
509 return icside_dma_init(ae, ec);
510
511 unmap_slot:
512 iounmap(ioc_base);
513 out:
514 return ret;
515}
516
517static int __devinit
518pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id)
519{
520 struct pata_icside_state *state;
521 struct ata_probe_ent ae;
522 void __iomem *idmem;
523 int ret;
524
525 ret = ecard_request_resources(ec);
526 if (ret)
527 goto out;
528
529 state = kzalloc(sizeof(struct pata_icside_state), GFP_KERNEL);
530 if (!state) {
531 ret = -ENOMEM;
532 goto release;
533 }
534
535 state->type = ICS_TYPE_NOTYPE;
536 state->dma = NO_DMA;
537
538 idmem = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST),
539 ecard_resource_len(ec, ECARD_RES_IOCFAST));
540 if (idmem) {
541 unsigned int type;
542
543 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
544 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
545 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
546 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
547 iounmap(idmem);
548
549 state->type = type;
550 }
551
552 memset(&ae, 0, sizeof(ae));
553 INIT_LIST_HEAD(&ae.node);
554 ae.dev = &ec->dev;
555 ae.port_ops = &pata_icside_port_ops;
556 ae.sht = &pata_icside_sht;
557 ae.pio_mask = 0x1f;
558 ae.irq = ec->irq;
559 ae.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST;
560 ae._host_flags = ATA_HOST_SIMPLEX;
561 ae.private_data = state;
562
563 switch (state->type) {
564 case ICS_TYPE_A3IN:
565 dev_warn(&ec->dev, "A3IN unsupported\n");
566 ret = -ENODEV;
567 break;
568
569 case ICS_TYPE_A3USER:
570 dev_warn(&ec->dev, "A3USER unsupported\n");
571 ret = -ENODEV;
572 break;
573
574 case ICS_TYPE_V5:
575 ret = pata_icside_register_v5(&ae, ec);
576 break;
577
578 case ICS_TYPE_V6:
579 ret = pata_icside_register_v6(&ae, ec);
580 break;
581
582 default:
583 dev_warn(&ec->dev, "unknown interface type\n");
584 ret = -ENODEV;
585 break;
586 }
587
588 if (ret == 0)
589 ret = ata_device_add(&ae) == 0 ? -ENODEV : 0;
590
591 if (ret == 0)
592 goto out;
593
594 kfree(state);
595 release:
596 ecard_release_resources(ec);
597 out:
598 return ret;
599}
600
601static void pata_icside_shutdown(struct expansion_card *ec)
602{
603 struct ata_host *host = ecard_get_drvdata(ec);
604 unsigned long flags;
605
606 /*
607 * Disable interrupts from this card. We need to do
608 * this before disabling EASI since we may be accessing
609 * this register via that region.
610 */
611 local_irq_save(flags);
612 if (ec->ops)
613 ec->ops->irqdisable(ec, ec->irq);
614 local_irq_restore(flags);
615
616 /*
617 * Reset the ROM pointer so that we can read the ROM
618 * after a soft reboot. This also disables access to
619 * the IDE taskfile via the EASI region.
620 */
621 if (host) {
622 struct pata_icside_state *state = host->private_data;
623 if (state->ioc_base)
624 writeb(0, state->ioc_base);
625 }
626}
627
628static void __devexit pata_icside_remove(struct expansion_card *ec)
629{
630 struct ata_host *host = ecard_get_drvdata(ec);
631 struct pata_icside_state *state = host->private_data;
632
633 ata_host_detach(host);
634
635 pata_icside_shutdown(ec);
636
637 /*
638 * don't NULL out the drvdata - devres/libata wants it
639 * to free the ata_host structure.
640 */
641 ec->ops = NULL;
642 ec->irq_data = NULL;
643
644 if (state->dma != NO_DMA)
645 free_dma(state->dma);
646 if (state->ioc_base)
647 iounmap(state->ioc_base);
648 if (state->ioc_base != state->irq_port)
649 iounmap(state->irq_port);
650
651 kfree(state);
652 ecard_release_resources(ec);
653}
654
655static const struct ecard_id pata_icside_ids[] = {
656 { MANU_ICS, PROD_ICS_IDE },
657 { MANU_ICS2, PROD_ICS2_IDE },
658 { 0xffff, 0xffff }
659};
660
661static struct ecard_driver pata_icside_driver = {
662 .probe = pata_icside_probe,
663 .remove = __devexit_p(pata_icside_remove),
664 .shutdown = pata_icside_shutdown,
665 .id_table = pata_icside_ids,
666 .drv = {
667 .name = DRV_NAME,
668 },
669};
670
671static int __init pata_icside_init(void)
672{
673 return ecard_register_driver(&pata_icside_driver);
674}
675
676static void __exit pata_icside_exit(void)
677{
678 ecard_remove_driver(&pata_icside_driver);
679}
680
681MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
682MODULE_LICENSE("GPL");
683MODULE_DESCRIPTION("ICS PATA driver");
684
685module_init(pata_icside_init);
686module_exit(pata_icside_exit);
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index c059b27fa881..873544ab598e 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -852,9 +852,7 @@ static int i2c_pxa_probe(struct platform_device *dev)
852{ 852{
853 struct pxa_i2c *i2c = &i2c_pxa; 853 struct pxa_i2c *i2c = &i2c_pxa;
854 struct resource *res; 854 struct resource *res;
855#ifdef CONFIG_I2C_PXA_SLAVE
856 struct i2c_pxa_platform_data *plat = dev->dev.platform_data; 855 struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
857#endif
858 int ret; 856 int ret;
859 int irq; 857 int irq;
860 858
@@ -902,14 +900,14 @@ static int i2c_pxa_probe(struct platform_device *dev)
902 pxa_gpio_mode(GPIO117_I2CSCL_MD); 900 pxa_gpio_mode(GPIO117_I2CSCL_MD);
903 pxa_gpio_mode(GPIO118_I2CSDA_MD); 901 pxa_gpio_mode(GPIO118_I2CSDA_MD);
904#endif 902#endif
905 pxa_set_cken(CKEN14_I2C, 1); 903 pxa_set_cken(CKEN_I2C, 1);
906 break; 904 break;
907#ifdef CONFIG_PXA27x 905#ifdef CONFIG_PXA27x
908 case 1: 906 case 1:
909 local_irq_disable(); 907 local_irq_disable();
910 PCFR |= PCFR_PI2CEN; 908 PCFR |= PCFR_PI2CEN;
911 local_irq_enable(); 909 local_irq_enable();
912 pxa_set_cken(CKEN15_PWRI2C, 1); 910 pxa_set_cken(CKEN_PWRI2C, 1);
913#endif 911#endif
914 } 912 }
915 913
@@ -924,6 +922,10 @@ static int i2c_pxa_probe(struct platform_device *dev)
924 i2c->adap.algo_data = i2c; 922 i2c->adap.algo_data = i2c;
925 i2c->adap.dev.parent = &dev->dev; 923 i2c->adap.dev.parent = &dev->dev;
926 924
925 if (plat) {
926 i2c->adap.class = plat->class;
927 }
928
927 ret = i2c_add_adapter(&i2c->adap); 929 ret = i2c_add_adapter(&i2c->adap);
928 if (ret < 0) { 930 if (ret < 0) {
929 printk(KERN_INFO "I2C: Failed to add bus\n"); 931 printk(KERN_INFO "I2C: Failed to add bus\n");
@@ -946,11 +948,11 @@ eadapt:
946ereqirq: 948ereqirq:
947 switch (dev->id) { 949 switch (dev->id) {
948 case 0: 950 case 0:
949 pxa_set_cken(CKEN14_I2C, 0); 951 pxa_set_cken(CKEN_I2C, 0);
950 break; 952 break;
951#ifdef CONFIG_PXA27x 953#ifdef CONFIG_PXA27x
952 case 1: 954 case 1:
953 pxa_set_cken(CKEN15_PWRI2C, 0); 955 pxa_set_cken(CKEN_PWRI2C, 0);
954 local_irq_disable(); 956 local_irq_disable();
955 PCFR &= ~PCFR_PI2CEN; 957 PCFR &= ~PCFR_PI2CEN;
956 local_irq_enable(); 958 local_irq_enable();
@@ -973,11 +975,11 @@ static int i2c_pxa_remove(struct platform_device *dev)
973 free_irq(i2c->irq, i2c); 975 free_irq(i2c->irq, i2c);
974 switch (dev->id) { 976 switch (dev->id) {
975 case 0: 977 case 0:
976 pxa_set_cken(CKEN14_I2C, 0); 978 pxa_set_cken(CKEN_I2C, 0);
977 break; 979 break;
978#ifdef CONFIG_PXA27x 980#ifdef CONFIG_PXA27x
979 case 1: 981 case 1:
980 pxa_set_cken(CKEN15_PWRI2C, 0); 982 pxa_set_cken(CKEN_PWRI2C, 0);
981 local_irq_disable(); 983 local_irq_disable();
982 PCFR &= ~PCFR_PI2CEN; 984 PCFR &= ~PCFR_PI2CEN;
983 local_irq_enable(); 985 local_irq_enable();
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index a98ff98fa567..d97d3864b57f 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -368,14 +368,14 @@ static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
368 if (CLOCKRATE / clk > ios->clock) 368 if (CLOCKRATE / clk > ios->clock)
369 clk <<= 1; 369 clk <<= 1;
370 host->clkrt = fls(clk) - 1; 370 host->clkrt = fls(clk) - 1;
371 pxa_set_cken(CKEN12_MMC, 1); 371 pxa_set_cken(CKEN_MMC, 1);
372 372
373 /* 373 /*
374 * we write clkrt on the next command 374 * we write clkrt on the next command
375 */ 375 */
376 } else { 376 } else {
377 pxamci_stop_clock(host); 377 pxamci_stop_clock(host);
378 pxa_set_cken(CKEN12_MMC, 0); 378 pxa_set_cken(CKEN_MMC, 0);
379 } 379 }
380 380
381 if (host->power_mode != ios->power_mode) { 381 if (host->power_mode != ios->power_mode) {
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index fb196fd91855..55ff0fbe525a 100644
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -134,7 +134,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
134 DCSR(si->rxdma) &= ~DCSR_RUN; 134 DCSR(si->rxdma) &= ~DCSR_RUN;
135 /* disable FICP */ 135 /* disable FICP */
136 ICCR0 = 0; 136 ICCR0 = 0;
137 pxa_set_cken(CKEN13_FICP, 0); 137 pxa_set_cken(CKEN_FICP, 0);
138 138
139 /* set board transceiver to SIR mode */ 139 /* set board transceiver to SIR mode */
140 si->pdata->transceiver_mode(si->dev, IR_SIRMODE); 140 si->pdata->transceiver_mode(si->dev, IR_SIRMODE);
@@ -144,7 +144,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
144 pxa_gpio_mode(GPIO47_STTXD_MD); 144 pxa_gpio_mode(GPIO47_STTXD_MD);
145 145
146 /* enable the STUART clock */ 146 /* enable the STUART clock */
147 pxa_set_cken(CKEN5_STUART, 1); 147 pxa_set_cken(CKEN_STUART, 1);
148 } 148 }
149 149
150 /* disable STUART first */ 150 /* disable STUART first */
@@ -169,7 +169,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
169 /* disable STUART */ 169 /* disable STUART */
170 STIER = 0; 170 STIER = 0;
171 STISR = 0; 171 STISR = 0;
172 pxa_set_cken(CKEN5_STUART, 0); 172 pxa_set_cken(CKEN_STUART, 0);
173 173
174 /* disable FICP first */ 174 /* disable FICP first */
175 ICCR0 = 0; 175 ICCR0 = 0;
@@ -182,7 +182,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
182 pxa_gpio_mode(GPIO47_ICPTXD_MD); 182 pxa_gpio_mode(GPIO47_ICPTXD_MD);
183 183
184 /* enable the FICP clock */ 184 /* enable the FICP clock */
185 pxa_set_cken(CKEN13_FICP, 1); 185 pxa_set_cken(CKEN_FICP, 1);
186 186
187 si->speed = speed; 187 si->speed = speed;
188 pxa_irda_fir_dma_rx_start(si); 188 pxa_irda_fir_dma_rx_start(si);
@@ -593,7 +593,7 @@ static void pxa_irda_shutdown(struct pxa_irda *si)
593 /* disable STUART SIR mode */ 593 /* disable STUART SIR mode */
594 STISR = 0; 594 STISR = 0;
595 /* disable the STUART clock */ 595 /* disable the STUART clock */
596 pxa_set_cken(CKEN5_STUART, 0); 596 pxa_set_cken(CKEN_STUART, 0);
597 597
598 /* disable DMA */ 598 /* disable DMA */
599 DCSR(si->txdma) &= ~DCSR_RUN; 599 DCSR(si->txdma) &= ~DCSR_RUN;
@@ -601,7 +601,7 @@ static void pxa_irda_shutdown(struct pxa_irda *si)
601 /* disable FICP */ 601 /* disable FICP */
602 ICCR0 = 0; 602 ICCR0 = 0;
603 /* disable the FICP clock */ 603 /* disable the FICP clock */
604 pxa_set_cken(CKEN13_FICP, 0); 604 pxa_set_cken(CKEN_FICP, 0);
605 605
606 DRCMR17 = 0; 606 DRCMR17 = 0;
607 DRCMR18 = 0; 607 DRCMR18 = 0;
diff --git a/drivers/serial/amba-pl010.c b/drivers/serial/amba-pl010.c
index f69bd097166e..1a9a24b82636 100644
--- a/drivers/serial/amba-pl010.c
+++ b/drivers/serial/amba-pl010.c
@@ -48,6 +48,7 @@
48#include <linux/serial.h> 48#include <linux/serial.h>
49#include <linux/amba/bus.h> 49#include <linux/amba/bus.h>
50#include <linux/amba/serial.h> 50#include <linux/amba/serial.h>
51#include <linux/clk.h>
51 52
52#include <asm/io.h> 53#include <asm/io.h>
53 54
@@ -70,6 +71,7 @@
70 */ 71 */
71struct uart_amba_port { 72struct uart_amba_port {
72 struct uart_port port; 73 struct uart_port port;
74 struct clk *clk;
73 struct amba_device *dev; 75 struct amba_device *dev;
74 struct amba_pl010_data *data; 76 struct amba_pl010_data *data;
75 unsigned int old_status; 77 unsigned int old_status;
@@ -77,73 +79,77 @@ struct uart_amba_port {
77 79
78static void pl010_stop_tx(struct uart_port *port) 80static void pl010_stop_tx(struct uart_port *port)
79{ 81{
82 struct uart_amba_port *uap = (struct uart_amba_port *)port;
80 unsigned int cr; 83 unsigned int cr;
81 84
82 cr = readb(port->membase + UART010_CR); 85 cr = readb(uap->port.membase + UART010_CR);
83 cr &= ~UART010_CR_TIE; 86 cr &= ~UART010_CR_TIE;
84 writel(cr, port->membase + UART010_CR); 87 writel(cr, uap->port.membase + UART010_CR);
85} 88}
86 89
87static void pl010_start_tx(struct uart_port *port) 90static void pl010_start_tx(struct uart_port *port)
88{ 91{
92 struct uart_amba_port *uap = (struct uart_amba_port *)port;
89 unsigned int cr; 93 unsigned int cr;
90 94
91 cr = readb(port->membase + UART010_CR); 95 cr = readb(uap->port.membase + UART010_CR);
92 cr |= UART010_CR_TIE; 96 cr |= UART010_CR_TIE;
93 writel(cr, port->membase + UART010_CR); 97 writel(cr, uap->port.membase + UART010_CR);
94} 98}
95 99
96static void pl010_stop_rx(struct uart_port *port) 100static void pl010_stop_rx(struct uart_port *port)
97{ 101{
102 struct uart_amba_port *uap = (struct uart_amba_port *)port;
98 unsigned int cr; 103 unsigned int cr;
99 104
100 cr = readb(port->membase + UART010_CR); 105 cr = readb(uap->port.membase + UART010_CR);
101 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE); 106 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
102 writel(cr, port->membase + UART010_CR); 107 writel(cr, uap->port.membase + UART010_CR);
103} 108}
104 109
105static void pl010_enable_ms(struct uart_port *port) 110static void pl010_enable_ms(struct uart_port *port)
106{ 111{
112 struct uart_amba_port *uap = (struct uart_amba_port *)port;
107 unsigned int cr; 113 unsigned int cr;
108 114
109 cr = readb(port->membase + UART010_CR); 115 cr = readb(uap->port.membase + UART010_CR);
110 cr |= UART010_CR_MSIE; 116 cr |= UART010_CR_MSIE;
111 writel(cr, port->membase + UART010_CR); 117 writel(cr, uap->port.membase + UART010_CR);
112} 118}
113 119
114static void pl010_rx_chars(struct uart_port *port) 120static void pl010_rx_chars(struct uart_amba_port *uap)
115{ 121{
116 struct tty_struct *tty = port->info->tty; 122 struct tty_struct *tty = uap->port.info->tty;
117 unsigned int status, ch, flag, rsr, max_count = 256; 123 unsigned int status, ch, flag, rsr, max_count = 256;
118 124
119 status = readb(port->membase + UART01x_FR); 125 status = readb(uap->port.membase + UART01x_FR);
120 while (UART_RX_DATA(status) && max_count--) { 126 while (UART_RX_DATA(status) && max_count--) {
121 ch = readb(port->membase + UART01x_DR); 127 ch = readb(uap->port.membase + UART01x_DR);
122 flag = TTY_NORMAL; 128 flag = TTY_NORMAL;
123 129
124 port->icount.rx++; 130 uap->port.icount.rx++;
125 131
126 /* 132 /*
127 * Note that the error handling code is 133 * Note that the error handling code is
128 * out of the main execution path 134 * out of the main execution path
129 */ 135 */
130 rsr = readb(port->membase + UART01x_RSR) | UART_DUMMY_RSR_RX; 136 rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
131 if (unlikely(rsr & UART01x_RSR_ANY)) { 137 if (unlikely(rsr & UART01x_RSR_ANY)) {
132 writel(0, port->membase + UART01x_ECR); 138 writel(0, uap->port.membase + UART01x_ECR);
133 139
134 if (rsr & UART01x_RSR_BE) { 140 if (rsr & UART01x_RSR_BE) {
135 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); 141 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
136 port->icount.brk++; 142 uap->port.icount.brk++;
137 if (uart_handle_break(port)) 143 if (uart_handle_break(&uap->port))
138 goto ignore_char; 144 goto ignore_char;
139 } else if (rsr & UART01x_RSR_PE) 145 } else if (rsr & UART01x_RSR_PE)
140 port->icount.parity++; 146 uap->port.icount.parity++;
141 else if (rsr & UART01x_RSR_FE) 147 else if (rsr & UART01x_RSR_FE)
142 port->icount.frame++; 148 uap->port.icount.frame++;
143 if (rsr & UART01x_RSR_OE) 149 if (rsr & UART01x_RSR_OE)
144 port->icount.overrun++; 150 uap->port.icount.overrun++;
145 151
146 rsr &= port->read_status_mask; 152 rsr &= uap->port.read_status_mask;
147 153
148 if (rsr & UART01x_RSR_BE) 154 if (rsr & UART01x_RSR_BE)
149 flag = TTY_BREAK; 155 flag = TTY_BREAK;
@@ -153,53 +159,52 @@ static void pl010_rx_chars(struct uart_port *port)
153 flag = TTY_FRAME; 159 flag = TTY_FRAME;
154 } 160 }
155 161
156 if (uart_handle_sysrq_char(port, ch)) 162 if (uart_handle_sysrq_char(&uap->port, ch))
157 goto ignore_char; 163 goto ignore_char;
158 164
159 uart_insert_char(port, rsr, UART01x_RSR_OE, ch, flag); 165 uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
160 166
161 ignore_char: 167 ignore_char:
162 status = readb(port->membase + UART01x_FR); 168 status = readb(uap->port.membase + UART01x_FR);
163 } 169 }
164 tty_flip_buffer_push(tty); 170 tty_flip_buffer_push(tty);
165 return; 171 return;
166} 172}
167 173
168static void pl010_tx_chars(struct uart_port *port) 174static void pl010_tx_chars(struct uart_amba_port *uap)
169{ 175{
170 struct circ_buf *xmit = &port->info->xmit; 176 struct circ_buf *xmit = &uap->port.info->xmit;
171 int count; 177 int count;
172 178
173 if (port->x_char) { 179 if (uap->port.x_char) {
174 writel(port->x_char, port->membase + UART01x_DR); 180 writel(uap->port.x_char, uap->port.membase + UART01x_DR);
175 port->icount.tx++; 181 uap->port.icount.tx++;
176 port->x_char = 0; 182 uap->port.x_char = 0;
177 return; 183 return;
178 } 184 }
179 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 185 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
180 pl010_stop_tx(port); 186 pl010_stop_tx(&uap->port);
181 return; 187 return;
182 } 188 }
183 189
184 count = port->fifosize >> 1; 190 count = uap->port.fifosize >> 1;
185 do { 191 do {
186 writel(xmit->buf[xmit->tail], port->membase + UART01x_DR); 192 writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
187 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 193 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
188 port->icount.tx++; 194 uap->port.icount.tx++;
189 if (uart_circ_empty(xmit)) 195 if (uart_circ_empty(xmit))
190 break; 196 break;
191 } while (--count > 0); 197 } while (--count > 0);
192 198
193 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 199 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
194 uart_write_wakeup(port); 200 uart_write_wakeup(&uap->port);
195 201
196 if (uart_circ_empty(xmit)) 202 if (uart_circ_empty(xmit))
197 pl010_stop_tx(port); 203 pl010_stop_tx(&uap->port);
198} 204}
199 205
200static void pl010_modem_status(struct uart_port *port) 206static void pl010_modem_status(struct uart_amba_port *uap)
201{ 207{
202 struct uart_amba_port *uap = (struct uart_amba_port *)port;
203 unsigned int status, delta; 208 unsigned int status, delta;
204 209
205 writel(0, uap->port.membase + UART010_ICR); 210 writel(0, uap->port.membase + UART010_ICR);
@@ -226,47 +231,50 @@ static void pl010_modem_status(struct uart_port *port)
226 231
227static irqreturn_t pl010_int(int irq, void *dev_id) 232static irqreturn_t pl010_int(int irq, void *dev_id)
228{ 233{
229 struct uart_port *port = dev_id; 234 struct uart_amba_port *uap = dev_id;
230 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 235 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
231 int handled = 0; 236 int handled = 0;
232 237
233 spin_lock(&port->lock); 238 spin_lock(&uap->port.lock);
234 239
235 status = readb(port->membase + UART010_IIR); 240 status = readb(uap->port.membase + UART010_IIR);
236 if (status) { 241 if (status) {
237 do { 242 do {
238 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS)) 243 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
239 pl010_rx_chars(port); 244 pl010_rx_chars(uap);
240 if (status & UART010_IIR_MIS) 245 if (status & UART010_IIR_MIS)
241 pl010_modem_status(port); 246 pl010_modem_status(uap);
242 if (status & UART010_IIR_TIS) 247 if (status & UART010_IIR_TIS)
243 pl010_tx_chars(port); 248 pl010_tx_chars(uap);
244 249
245 if (pass_counter-- == 0) 250 if (pass_counter-- == 0)
246 break; 251 break;
247 252
248 status = readb(port->membase + UART010_IIR); 253 status = readb(uap->port.membase + UART010_IIR);
249 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS | 254 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
250 UART010_IIR_TIS)); 255 UART010_IIR_TIS));
251 handled = 1; 256 handled = 1;
252 } 257 }
253 258
254 spin_unlock(&port->lock); 259 spin_unlock(&uap->port.lock);
255 260
256 return IRQ_RETVAL(handled); 261 return IRQ_RETVAL(handled);
257} 262}
258 263
259static unsigned int pl010_tx_empty(struct uart_port *port) 264static unsigned int pl010_tx_empty(struct uart_port *port)
260{ 265{
261 return readb(port->membase + UART01x_FR) & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT; 266 struct uart_amba_port *uap = (struct uart_amba_port *)port;
267 unsigned int status = readb(uap->port.membase + UART01x_FR);
268 return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
262} 269}
263 270
264static unsigned int pl010_get_mctrl(struct uart_port *port) 271static unsigned int pl010_get_mctrl(struct uart_port *port)
265{ 272{
273 struct uart_amba_port *uap = (struct uart_amba_port *)port;
266 unsigned int result = 0; 274 unsigned int result = 0;
267 unsigned int status; 275 unsigned int status;
268 276
269 status = readb(port->membase + UART01x_FR); 277 status = readb(uap->port.membase + UART01x_FR);
270 if (status & UART01x_FR_DCD) 278 if (status & UART01x_FR_DCD)
271 result |= TIOCM_CAR; 279 result |= TIOCM_CAR;
272 if (status & UART01x_FR_DSR) 280 if (status & UART01x_FR_DSR)
@@ -287,17 +295,18 @@ static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
287 295
288static void pl010_break_ctl(struct uart_port *port, int break_state) 296static void pl010_break_ctl(struct uart_port *port, int break_state)
289{ 297{
298 struct uart_amba_port *uap = (struct uart_amba_port *)port;
290 unsigned long flags; 299 unsigned long flags;
291 unsigned int lcr_h; 300 unsigned int lcr_h;
292 301
293 spin_lock_irqsave(&port->lock, flags); 302 spin_lock_irqsave(&uap->port.lock, flags);
294 lcr_h = readb(port->membase + UART010_LCRH); 303 lcr_h = readb(uap->port.membase + UART010_LCRH);
295 if (break_state == -1) 304 if (break_state == -1)
296 lcr_h |= UART01x_LCRH_BRK; 305 lcr_h |= UART01x_LCRH_BRK;
297 else 306 else
298 lcr_h &= ~UART01x_LCRH_BRK; 307 lcr_h &= ~UART01x_LCRH_BRK;
299 writel(lcr_h, port->membase + UART010_LCRH); 308 writel(lcr_h, uap->port.membase + UART010_LCRH);
300 spin_unlock_irqrestore(&port->lock, flags); 309 spin_unlock_irqrestore(&uap->port.lock, flags);
301} 310}
302 311
303static int pl010_startup(struct uart_port *port) 312static int pl010_startup(struct uart_port *port)
@@ -306,48 +315,70 @@ static int pl010_startup(struct uart_port *port)
306 int retval; 315 int retval;
307 316
308 /* 317 /*
318 * Try to enable the clock producer.
319 */
320 retval = clk_enable(uap->clk);
321 if (retval)
322 goto out;
323
324 uap->port.uartclk = clk_get_rate(uap->clk);
325
326 /*
309 * Allocate the IRQ 327 * Allocate the IRQ
310 */ 328 */
311 retval = request_irq(port->irq, pl010_int, 0, "uart-pl010", port); 329 retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap);
312 if (retval) 330 if (retval)
313 return retval; 331 goto clk_dis;
314 332
315 /* 333 /*
316 * initialise the old status of the modem signals 334 * initialise the old status of the modem signals
317 */ 335 */
318 uap->old_status = readb(port->membase + UART01x_FR) & UART01x_FR_MODEM_ANY; 336 uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
319 337
320 /* 338 /*
321 * Finally, enable interrupts 339 * Finally, enable interrupts
322 */ 340 */
323 writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE, 341 writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
324 port->membase + UART010_CR); 342 uap->port.membase + UART010_CR);
325 343
326 return 0; 344 return 0;
345
346 clk_dis:
347 clk_disable(uap->clk);
348 out:
349 return retval;
327} 350}
328 351
329static void pl010_shutdown(struct uart_port *port) 352static void pl010_shutdown(struct uart_port *port)
330{ 353{
354 struct uart_amba_port *uap = (struct uart_amba_port *)port;
355
331 /* 356 /*
332 * Free the interrupt 357 * Free the interrupt
333 */ 358 */
334 free_irq(port->irq, port); 359 free_irq(uap->port.irq, uap);
335 360
336 /* 361 /*
337 * disable all interrupts, disable the port 362 * disable all interrupts, disable the port
338 */ 363 */
339 writel(0, port->membase + UART010_CR); 364 writel(0, uap->port.membase + UART010_CR);
340 365
341 /* disable break condition and fifos */ 366 /* disable break condition and fifos */
342 writel(readb(port->membase + UART010_LCRH) & 367 writel(readb(uap->port.membase + UART010_LCRH) &
343 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN), 368 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
344 port->membase + UART010_LCRH); 369 uap->port.membase + UART010_LCRH);
370
371 /*
372 * Shut down the clock producer
373 */
374 clk_disable(uap->clk);
345} 375}
346 376
347static void 377static void
348pl010_set_termios(struct uart_port *port, struct ktermios *termios, 378pl010_set_termios(struct uart_port *port, struct ktermios *termios,
349 struct ktermios *old) 379 struct ktermios *old)
350{ 380{
381 struct uart_amba_port *uap = (struct uart_amba_port *)port;
351 unsigned int lcr_h, old_cr; 382 unsigned int lcr_h, old_cr;
352 unsigned long flags; 383 unsigned long flags;
353 unsigned int baud, quot; 384 unsigned int baud, quot;
@@ -355,7 +386,7 @@ pl010_set_termios(struct uart_port *port, struct ktermios *termios,
355 /* 386 /*
356 * Ask the core to calculate the divisor for us. 387 * Ask the core to calculate the divisor for us.
357 */ 388 */
358 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 389 baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
359 quot = uart_get_divisor(port, baud); 390 quot = uart_get_divisor(port, baud);
360 391
361 switch (termios->c_cflag & CSIZE) { 392 switch (termios->c_cflag & CSIZE) {
@@ -379,66 +410,66 @@ pl010_set_termios(struct uart_port *port, struct ktermios *termios,
379 if (!(termios->c_cflag & PARODD)) 410 if (!(termios->c_cflag & PARODD))
380 lcr_h |= UART01x_LCRH_EPS; 411 lcr_h |= UART01x_LCRH_EPS;
381 } 412 }
382 if (port->fifosize > 1) 413 if (uap->port.fifosize > 1)
383 lcr_h |= UART01x_LCRH_FEN; 414 lcr_h |= UART01x_LCRH_FEN;
384 415
385 spin_lock_irqsave(&port->lock, flags); 416 spin_lock_irqsave(&uap->port.lock, flags);
386 417
387 /* 418 /*
388 * Update the per-port timeout. 419 * Update the per-port timeout.
389 */ 420 */
390 uart_update_timeout(port, termios->c_cflag, baud); 421 uart_update_timeout(port, termios->c_cflag, baud);
391 422
392 port->read_status_mask = UART01x_RSR_OE; 423 uap->port.read_status_mask = UART01x_RSR_OE;
393 if (termios->c_iflag & INPCK) 424 if (termios->c_iflag & INPCK)
394 port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; 425 uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
395 if (termios->c_iflag & (BRKINT | PARMRK)) 426 if (termios->c_iflag & (BRKINT | PARMRK))
396 port->read_status_mask |= UART01x_RSR_BE; 427 uap->port.read_status_mask |= UART01x_RSR_BE;
397 428
398 /* 429 /*
399 * Characters to ignore 430 * Characters to ignore
400 */ 431 */
401 port->ignore_status_mask = 0; 432 uap->port.ignore_status_mask = 0;
402 if (termios->c_iflag & IGNPAR) 433 if (termios->c_iflag & IGNPAR)
403 port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; 434 uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
404 if (termios->c_iflag & IGNBRK) { 435 if (termios->c_iflag & IGNBRK) {
405 port->ignore_status_mask |= UART01x_RSR_BE; 436 uap->port.ignore_status_mask |= UART01x_RSR_BE;
406 /* 437 /*
407 * If we're ignoring parity and break indicators, 438 * If we're ignoring parity and break indicators,
408 * ignore overruns too (for real raw support). 439 * ignore overruns too (for real raw support).
409 */ 440 */
410 if (termios->c_iflag & IGNPAR) 441 if (termios->c_iflag & IGNPAR)
411 port->ignore_status_mask |= UART01x_RSR_OE; 442 uap->port.ignore_status_mask |= UART01x_RSR_OE;
412 } 443 }
413 444
414 /* 445 /*
415 * Ignore all characters if CREAD is not set. 446 * Ignore all characters if CREAD is not set.
416 */ 447 */
417 if ((termios->c_cflag & CREAD) == 0) 448 if ((termios->c_cflag & CREAD) == 0)
418 port->ignore_status_mask |= UART_DUMMY_RSR_RX; 449 uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
419 450
420 /* first, disable everything */ 451 /* first, disable everything */
421 old_cr = readb(port->membase + UART010_CR) & ~UART010_CR_MSIE; 452 old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
422 453
423 if (UART_ENABLE_MS(port, termios->c_cflag)) 454 if (UART_ENABLE_MS(port, termios->c_cflag))
424 old_cr |= UART010_CR_MSIE; 455 old_cr |= UART010_CR_MSIE;
425 456
426 writel(0, port->membase + UART010_CR); 457 writel(0, uap->port.membase + UART010_CR);
427 458
428 /* Set baud rate */ 459 /* Set baud rate */
429 quot -= 1; 460 quot -= 1;
430 writel((quot & 0xf00) >> 8, port->membase + UART010_LCRM); 461 writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
431 writel(quot & 0xff, port->membase + UART010_LCRL); 462 writel(quot & 0xff, uap->port.membase + UART010_LCRL);
432 463
433 /* 464 /*
434 * ----------v----------v----------v----------v----- 465 * ----------v----------v----------v----------v-----
435 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L 466 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
436 * ----------^----------^----------^----------^----- 467 * ----------^----------^----------^----------^-----
437 */ 468 */
438 writel(lcr_h, port->membase + UART010_LCRH); 469 writel(lcr_h, uap->port.membase + UART010_LCRH);
439 writel(old_cr, port->membase + UART010_CR); 470 writel(old_cr, uap->port.membase + UART010_CR);
440 471
441 spin_unlock_irqrestore(&port->lock, flags); 472 spin_unlock_irqrestore(&uap->port.lock, flags);
442} 473}
443 474
444static const char *pl010_type(struct uart_port *port) 475static const char *pl010_type(struct uart_port *port)
@@ -514,47 +545,52 @@ static struct uart_amba_port *amba_ports[UART_NR];
514 545
515static void pl010_console_putchar(struct uart_port *port, int ch) 546static void pl010_console_putchar(struct uart_port *port, int ch)
516{ 547{
548 struct uart_amba_port *uap = (struct uart_amba_port *)port;
517 unsigned int status; 549 unsigned int status;
518 550
519 do { 551 do {
520 status = readb(port->membase + UART01x_FR); 552 status = readb(uap->port.membase + UART01x_FR);
521 barrier(); 553 barrier();
522 } while (!UART_TX_READY(status)); 554 } while (!UART_TX_READY(status));
523 writel(ch, port->membase + UART01x_DR); 555 writel(ch, uap->port.membase + UART01x_DR);
524} 556}
525 557
526static void 558static void
527pl010_console_write(struct console *co, const char *s, unsigned int count) 559pl010_console_write(struct console *co, const char *s, unsigned int count)
528{ 560{
529 struct uart_port *port = &amba_ports[co->index]->port; 561 struct uart_amba_port *uap = amba_ports[co->index];
530 unsigned int status, old_cr; 562 unsigned int status, old_cr;
531 563
564 clk_enable(uap->clk);
565
532 /* 566 /*
533 * First save the CR then disable the interrupts 567 * First save the CR then disable the interrupts
534 */ 568 */
535 old_cr = readb(port->membase + UART010_CR); 569 old_cr = readb(uap->port.membase + UART010_CR);
536 writel(UART01x_CR_UARTEN, port->membase + UART010_CR); 570 writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
537 571
538 uart_console_write(port, s, count, pl010_console_putchar); 572 uart_console_write(&uap->port, s, count, pl010_console_putchar);
539 573
540 /* 574 /*
541 * Finally, wait for transmitter to become empty 575 * Finally, wait for transmitter to become empty
542 * and restore the TCR 576 * and restore the TCR
543 */ 577 */
544 do { 578 do {
545 status = readb(port->membase + UART01x_FR); 579 status = readb(uap->port.membase + UART01x_FR);
546 barrier(); 580 barrier();
547 } while (status & UART01x_FR_BUSY); 581 } while (status & UART01x_FR_BUSY);
548 writel(old_cr, port->membase + UART010_CR); 582 writel(old_cr, uap->port.membase + UART010_CR);
583
584 clk_disable(uap->clk);
549} 585}
550 586
551static void __init 587static void __init
552pl010_console_get_options(struct uart_port *port, int *baud, 588pl010_console_get_options(struct uart_amba_port *uap, int *baud,
553 int *parity, int *bits) 589 int *parity, int *bits)
554{ 590{
555 if (readb(port->membase + UART010_CR) & UART01x_CR_UARTEN) { 591 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
556 unsigned int lcr_h, quot; 592 unsigned int lcr_h, quot;
557 lcr_h = readb(port->membase + UART010_LCRH); 593 lcr_h = readb(uap->port.membase + UART010_LCRH);
558 594
559 *parity = 'n'; 595 *parity = 'n';
560 if (lcr_h & UART01x_LCRH_PEN) { 596 if (lcr_h & UART01x_LCRH_PEN) {
@@ -569,14 +605,15 @@ pl010_console_get_options(struct uart_port *port, int *baud,
569 else 605 else
570 *bits = 8; 606 *bits = 8;
571 607
572 quot = readb(port->membase + UART010_LCRL) | readb(port->membase + UART010_LCRM) << 8; 608 quot = readb(uap->port.membase + UART010_LCRL) |
573 *baud = port->uartclk / (16 * (quot + 1)); 609 readb(uap->port.membase + UART010_LCRM) << 8;
610 *baud = uap->port.uartclk / (16 * (quot + 1));
574 } 611 }
575} 612}
576 613
577static int __init pl010_console_setup(struct console *co, char *options) 614static int __init pl010_console_setup(struct console *co, char *options)
578{ 615{
579 struct uart_port *port; 616 struct uart_amba_port *uap;
580 int baud = 38400; 617 int baud = 38400;
581 int bits = 8; 618 int bits = 8;
582 int parity = 'n'; 619 int parity = 'n';
@@ -589,16 +626,18 @@ static int __init pl010_console_setup(struct console *co, char *options)
589 */ 626 */
590 if (co->index >= UART_NR) 627 if (co->index >= UART_NR)
591 co->index = 0; 628 co->index = 0;
592 if (!amba_ports[co->index]) 629 uap = amba_ports[co->index];
630 if (!uap)
593 return -ENODEV; 631 return -ENODEV;
594 port = &amba_ports[co->index]->port; 632
633 uap->port.uartclk = clk_get_rate(uap->clk);
595 634
596 if (options) 635 if (options)
597 uart_parse_options(options, &baud, &parity, &bits, &flow); 636 uart_parse_options(options, &baud, &parity, &bits, &flow);
598 else 637 else
599 pl010_console_get_options(port, &baud, &parity, &bits); 638 pl010_console_get_options(uap, &baud, &parity, &bits);
600 639
601 return uart_set_options(port, co, baud, parity, bits, flow); 640 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
602} 641}
603 642
604static struct uart_driver amba_reg; 643static struct uart_driver amba_reg;
@@ -629,7 +668,7 @@ static struct uart_driver amba_reg = {
629 668
630static int pl010_probe(struct amba_device *dev, void *id) 669static int pl010_probe(struct amba_device *dev, void *id)
631{ 670{
632 struct uart_amba_port *port; 671 struct uart_amba_port *uap;
633 void __iomem *base; 672 void __iomem *base;
634 int i, ret; 673 int i, ret;
635 674
@@ -642,8 +681,8 @@ static int pl010_probe(struct amba_device *dev, void *id)
642 goto out; 681 goto out;
643 } 682 }
644 683
645 port = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL); 684 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
646 if (!port) { 685 if (!uap) {
647 ret = -ENOMEM; 686 ret = -ENOMEM;
648 goto out; 687 goto out;
649 } 688 }
@@ -654,51 +693,57 @@ static int pl010_probe(struct amba_device *dev, void *id)
654 goto free; 693 goto free;
655 } 694 }
656 695
657 port->port.dev = &dev->dev; 696 uap->clk = clk_get(&dev->dev, "UARTCLK");
658 port->port.mapbase = dev->res.start; 697 if (IS_ERR(uap->clk)) {
659 port->port.membase = base; 698 ret = PTR_ERR(uap->clk);
660 port->port.iotype = UPIO_MEM; 699 goto unmap;
661 port->port.irq = dev->irq[0]; 700 }
662 port->port.uartclk = 14745600; 701
663 port->port.fifosize = 16; 702 uap->port.dev = &dev->dev;
664 port->port.ops = &amba_pl010_pops; 703 uap->port.mapbase = dev->res.start;
665 port->port.flags = UPF_BOOT_AUTOCONF; 704 uap->port.membase = base;
666 port->port.line = i; 705 uap->port.iotype = UPIO_MEM;
667 port->dev = dev; 706 uap->port.irq = dev->irq[0];
668 port->data = dev->dev.platform_data; 707 uap->port.fifosize = 16;
669 708 uap->port.ops = &amba_pl010_pops;
670 amba_ports[i] = port; 709 uap->port.flags = UPF_BOOT_AUTOCONF;
671 710 uap->port.line = i;
672 amba_set_drvdata(dev, port); 711 uap->dev = dev;
673 ret = uart_add_one_port(&amba_reg, &port->port); 712 uap->data = dev->dev.platform_data;
713
714 amba_ports[i] = uap;
715
716 amba_set_drvdata(dev, uap);
717 ret = uart_add_one_port(&amba_reg, &uap->port);
674 if (ret) { 718 if (ret) {
675 amba_set_drvdata(dev, NULL); 719 amba_set_drvdata(dev, NULL);
676 amba_ports[i] = NULL; 720 amba_ports[i] = NULL;
721 clk_put(uap->clk);
722 unmap:
677 iounmap(base); 723 iounmap(base);
678 free: 724 free:
679 kfree(port); 725 kfree(uap);
680 } 726 }
681
682 out: 727 out:
683 return ret; 728 return ret;
684} 729}
685 730
686static int pl010_remove(struct amba_device *dev) 731static int pl010_remove(struct amba_device *dev)
687{ 732{
688 struct uart_amba_port *port = amba_get_drvdata(dev); 733 struct uart_amba_port *uap = amba_get_drvdata(dev);
689 int i; 734 int i;
690 735
691 amba_set_drvdata(dev, NULL); 736 amba_set_drvdata(dev, NULL);
692 737
693 uart_remove_one_port(&amba_reg, &port->port); 738 uart_remove_one_port(&amba_reg, &uap->port);
694 739
695 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 740 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
696 if (amba_ports[i] == port) 741 if (amba_ports[i] == uap)
697 amba_ports[i] = NULL; 742 amba_ports[i] = NULL;
698 743
699 iounmap(port->port.membase); 744 iounmap(uap->port.membase);
700 kfree(port); 745 clk_put(uap->clk);
701 746 kfree(uap);
702 return 0; 747 return 0;
703} 748}
704 749
diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c
index 935f48fa501d..3320bcd92c0a 100644
--- a/drivers/serial/atmel_serial.c
+++ b/drivers/serial/atmel_serial.c
@@ -484,11 +484,16 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios * termios,
484 unsigned long flags; 484 unsigned long flags;
485 unsigned int mode, imr, quot, baud; 485 unsigned int mode, imr, quot, baud;
486 486
487 /* Get current mode register */
488 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR);
489
487 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 490 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
488 quot = uart_get_divisor(port, baud); 491 quot = uart_get_divisor(port, baud);
489 492
490 /* Get current mode register */ 493 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
491 mode = UART_GET_MR(port) & ~(ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR); 494 quot /= 8;
495 mode |= ATMEL_US_USCLKS_MCK_DIV8;
496 }
492 497
493 /* byte size */ 498 /* byte size */
494 switch (termios->c_cflag & CSIZE) { 499 switch (termios->c_cflag & CSIZE) {
diff --git a/drivers/serial/atmel_serial.h b/drivers/serial/atmel_serial.h
index 11b44360e108..e0141776517c 100644
--- a/drivers/serial/atmel_serial.h
+++ b/drivers/serial/atmel_serial.h
@@ -46,6 +46,9 @@
46#define ATMEL_US_USMODE_ISO7816_T1 6 46#define ATMEL_US_USMODE_ISO7816_T1 6
47#define ATMEL_US_USMODE_IRDA 8 47#define ATMEL_US_USMODE_IRDA 8
48#define ATMEL_US_USCLKS (3 << 4) /* Clock Selection */ 48#define ATMEL_US_USCLKS (3 << 4) /* Clock Selection */
49#define ATMEL_US_USCLKS_MCK (0 << 4)
50#define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4)
51#define ATMEL_US_USCLKS_SCK (3 << 4)
49#define ATMEL_US_CHRL (3 << 6) /* Character Length */ 52#define ATMEL_US_CHRL (3 << 6) /* Character Length */
50#define ATMEL_US_CHRL_5 (0 << 6) 53#define ATMEL_US_CHRL_5 (0 << 6)
51#define ATMEL_US_CHRL_6 (1 << 6) 54#define ATMEL_US_CHRL_6 (1 << 6)
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c
index 04cc88cc528c..e42faa4e4282 100644
--- a/drivers/serial/imx.c
+++ b/drivers/serial/imx.c
@@ -46,6 +46,122 @@
46#include <asm/hardware.h> 46#include <asm/hardware.h>
47#include <asm/arch/imx-uart.h> 47#include <asm/arch/imx-uart.h>
48 48
49/* Register definitions */
50#define URXD0 0x0 /* Receiver Register */
51#define URTX0 0x40 /* Transmitter Register */
52#define UCR1 0x80 /* Control Register 1 */
53#define UCR2 0x84 /* Control Register 2 */
54#define UCR3 0x88 /* Control Register 3 */
55#define UCR4 0x8c /* Control Register 4 */
56#define UFCR 0x90 /* FIFO Control Register */
57#define USR1 0x94 /* Status Register 1 */
58#define USR2 0x98 /* Status Register 2 */
59#define UESC 0x9c /* Escape Character Register */
60#define UTIM 0xa0 /* Escape Timer Register */
61#define UBIR 0xa4 /* BRM Incremental Register */
62#define UBMR 0xa8 /* BRM Modulator Register */
63#define UBRC 0xac /* Baud Rate Count Register */
64#define BIPR1 0xb0 /* Incremental Preset Register 1 */
65#define BIPR2 0xb4 /* Incremental Preset Register 2 */
66#define BIPR3 0xb8 /* Incremental Preset Register 3 */
67#define BIPR4 0xbc /* Incremental Preset Register 4 */
68#define BMPR1 0xc0 /* BRM Modulator Register 1 */
69#define BMPR2 0xc4 /* BRM Modulator Register 2 */
70#define BMPR3 0xc8 /* BRM Modulator Register 3 */
71#define BMPR4 0xcc /* BRM Modulator Register 4 */
72#define UTS 0xd0 /* UART Test Register */
73
74/* UART Control Register Bit Fields.*/
75#define URXD_CHARRDY (1<<15)
76#define URXD_ERR (1<<14)
77#define URXD_OVRRUN (1<<13)
78#define URXD_FRMERR (1<<12)
79#define URXD_BRK (1<<11)
80#define URXD_PRERR (1<<10)
81#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
82#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87#define UCR1_IREN (1<<7) /* Infrared interface enable */
88#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90#define UCR1_SNDBRK (1<<4) /* Send break */
91#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
93#define UCR1_DOZE (1<<1) /* Doze */
94#define UCR1_UARTEN (1<<0) /* UART enabled */
95#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97#define UCR2_CTSC (1<<13) /* CTS pin control */
98#define UCR2_CTS (1<<12) /* Clear to send */
99#define UCR2_ESCEN (1<<11) /* Escape enable */
100#define UCR2_PREN (1<<8) /* Parity enable */
101#define UCR2_PROE (1<<7) /* Parity odd/even */
102#define UCR2_STPB (1<<6) /* Stop */
103#define UCR2_WS (1<<5) /* Word size */
104#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105#define UCR2_TXEN (1<<2) /* Transmitter enabled */
106#define UCR2_RXEN (1<<1) /* Receiver enabled */
107#define UCR2_SRST (1<<0) /* SW reset */
108#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
109#define UCR3_PARERREN (1<<12) /* Parity enable */
110#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111#define UCR3_DSR (1<<10) /* Data set ready */
112#define UCR3_DCD (1<<9) /* Data carrier detect */
113#define UCR3_RI (1<<8) /* Ring indicator */
114#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
118#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
119#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
120#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
121#define UCR3_BPEN (1<<0) /* Preset registers enable */
122#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
123#define UCR4_INVR (1<<9) /* Inverted infrared reception */
124#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127#define UCR4_IRSC (1<<5) /* IR special case */
128#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
134#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
136#define USR1_RTSS (1<<14) /* RTS pin status */
137#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138#define USR1_RTSD (1<<12) /* RTS delta */
139#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
140#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
142#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
143#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
144#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
145#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
146#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
147#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
148#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
149#define USR2_IDLE (1<<12) /* Idle condition */
150#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
151#define USR2_WAKE (1<<7) /* Wake */
152#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
153#define USR2_TXDC (1<<3) /* Transmitter complete */
154#define USR2_BRCD (1<<2) /* Break condition */
155#define USR2_ORE (1<<1) /* Overrun error */
156#define USR2_RDR (1<<0) /* Recv data ready */
157#define UTS_FRCPERR (1<<13) /* Force parity error */
158#define UTS_LOOP (1<<12) /* Loop tx and rx */
159#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
160#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
161#define UTS_TXFULL (1<<4) /* TxFIFO full */
162#define UTS_RXFULL (1<<3) /* RxFIFO full */
163#define UTS_SOFTRST (1<<0) /* Software reset */
164
49/* We've been assigned a range on the "Low-density serial ports" major */ 165/* We've been assigned a range on the "Low-density serial ports" major */
50#define SERIAL_IMX_MAJOR 204 166#define SERIAL_IMX_MAJOR 204
51#define MINOR_START 41 167#define MINOR_START 41
@@ -128,7 +244,10 @@ static void imx_timeout(unsigned long data)
128static void imx_stop_tx(struct uart_port *port) 244static void imx_stop_tx(struct uart_port *port)
129{ 245{
130 struct imx_port *sport = (struct imx_port *)port; 246 struct imx_port *sport = (struct imx_port *)port;
131 UCR1((u32)sport->port.membase) &= ~UCR1_TXMPTYEN; 247 unsigned long temp;
248
249 temp = readl(sport->port.membase + UCR1);
250 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
132} 251}
133 252
134/* 253/*
@@ -137,7 +256,10 @@ static void imx_stop_tx(struct uart_port *port)
137static void imx_stop_rx(struct uart_port *port) 256static void imx_stop_rx(struct uart_port *port)
138{ 257{
139 struct imx_port *sport = (struct imx_port *)port; 258 struct imx_port *sport = (struct imx_port *)port;
140 UCR2((u32)sport->port.membase) &= ~UCR2_RXEN; 259 unsigned long temp;
260
261 temp = readl(sport->port.membase + UCR2);
262 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
141} 263}
142 264
143/* 265/*
@@ -154,10 +276,10 @@ static inline void imx_transmit_buffer(struct imx_port *sport)
154{ 276{
155 struct circ_buf *xmit = &sport->port.info->xmit; 277 struct circ_buf *xmit = &sport->port.info->xmit;
156 278
157 while (!(UTS((u32)sport->port.membase) & UTS_TXFULL)) { 279 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
158 /* send xmit->buf[xmit->tail] 280 /* send xmit->buf[xmit->tail]
159 * out the port here */ 281 * out the port here */
160 URTX0((u32)sport->port.membase) = xmit->buf[xmit->tail]; 282 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
161 xmit->tail = (xmit->tail + 1) & 283 xmit->tail = (xmit->tail + 1) &
162 (UART_XMIT_SIZE - 1); 284 (UART_XMIT_SIZE - 1);
163 sport->port.icount.tx++; 285 sport->port.icount.tx++;
@@ -175,21 +297,24 @@ static inline void imx_transmit_buffer(struct imx_port *sport)
175static void imx_start_tx(struct uart_port *port) 297static void imx_start_tx(struct uart_port *port)
176{ 298{
177 struct imx_port *sport = (struct imx_port *)port; 299 struct imx_port *sport = (struct imx_port *)port;
300 unsigned long temp;
178 301
179 UCR1((u32)sport->port.membase) |= UCR1_TXMPTYEN; 302 temp = readl(sport->port.membase + UCR1);
303 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
180 304
181 imx_transmit_buffer(sport); 305 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
306 imx_transmit_buffer(sport);
182} 307}
183 308
184static irqreturn_t imx_rtsint(int irq, void *dev_id) 309static irqreturn_t imx_rtsint(int irq, void *dev_id)
185{ 310{
186 struct imx_port *sport = (struct imx_port *)dev_id; 311 struct imx_port *sport = (struct imx_port *)dev_id;
187 unsigned int val = USR1((u32)sport->port.membase)&USR1_RTSS; 312 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
188 unsigned long flags; 313 unsigned long flags;
189 314
190 spin_lock_irqsave(&sport->port.lock, flags); 315 spin_lock_irqsave(&sport->port.lock, flags);
191 316
192 USR1((u32)sport->port.membase) = USR1_RTSD; 317 writel(USR1_RTSD, sport->port.membase + USR1);
193 uart_handle_cts_change(&sport->port, !!val); 318 uart_handle_cts_change(&sport->port, !!val);
194 wake_up_interruptible(&sport->port.info->delta_msr_wait); 319 wake_up_interruptible(&sport->port.info->delta_msr_wait);
195 320
@@ -207,7 +332,7 @@ static irqreturn_t imx_txint(int irq, void *dev_id)
207 if (sport->port.x_char) 332 if (sport->port.x_char)
208 { 333 {
209 /* Send next char */ 334 /* Send next char */
210 URTX0((u32)sport->port.membase) = sport->port.x_char; 335 writel(sport->port.x_char, sport->port.membase + URTX0);
211 goto out; 336 goto out;
212 } 337 }
213 338
@@ -231,17 +356,18 @@ static irqreturn_t imx_rxint(int irq, void *dev_id)
231 struct imx_port *sport = dev_id; 356 struct imx_port *sport = dev_id;
232 unsigned int rx,flg,ignored = 0; 357 unsigned int rx,flg,ignored = 0;
233 struct tty_struct *tty = sport->port.info->tty; 358 struct tty_struct *tty = sport->port.info->tty;
234 unsigned long flags; 359 unsigned long flags, temp;
235 360
236 rx = URXD0((u32)sport->port.membase); 361 rx = readl(sport->port.membase + URXD0);
237 spin_lock_irqsave(&sport->port.lock,flags); 362 spin_lock_irqsave(&sport->port.lock,flags);
238 363
239 do { 364 do {
240 flg = TTY_NORMAL; 365 flg = TTY_NORMAL;
241 sport->port.icount.rx++; 366 sport->port.icount.rx++;
242 367
243 if( USR2((u32)sport->port.membase) & USR2_BRCD ) { 368 temp = readl(sport->port.membase + USR2);
244 USR2((u32)sport->port.membase) |= USR2_BRCD; 369 if( temp & USR2_BRCD ) {
370 writel(temp | USR2_BRCD, sport->port.membase + USR2);
245 if(uart_handle_break(&sport->port)) 371 if(uart_handle_break(&sport->port))
246 goto ignore_char; 372 goto ignore_char;
247 } 373 }
@@ -257,7 +383,7 @@ static irqreturn_t imx_rxint(int irq, void *dev_id)
257 tty_insert_flip_char(tty, rx, flg); 383 tty_insert_flip_char(tty, rx, flg);
258 384
259 ignore_char: 385 ignore_char:
260 rx = URXD0((u32)sport->port.membase); 386 rx = readl(sport->port.membase + URXD0);
261 } while(rx & URXD_CHARRDY); 387 } while(rx & URXD_CHARRDY);
262 388
263out: 389out:
@@ -301,7 +427,7 @@ static unsigned int imx_tx_empty(struct uart_port *port)
301{ 427{
302 struct imx_port *sport = (struct imx_port *)port; 428 struct imx_port *sport = (struct imx_port *)port;
303 429
304 return USR2((u32)sport->port.membase) & USR2_TXDC ? TIOCSER_TEMT : 0; 430 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
305} 431}
306 432
307/* 433/*
@@ -312,10 +438,10 @@ static unsigned int imx_get_mctrl(struct uart_port *port)
312 struct imx_port *sport = (struct imx_port *)port; 438 struct imx_port *sport = (struct imx_port *)port;
313 unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 439 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
314 440
315 if (USR1((u32)sport->port.membase) & USR1_RTSS) 441 if (readl(sport->port.membase + USR1) & USR1_RTSS)
316 tmp |= TIOCM_CTS; 442 tmp |= TIOCM_CTS;
317 443
318 if (UCR2((u32)sport->port.membase) & UCR2_CTS) 444 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
319 tmp |= TIOCM_RTS; 445 tmp |= TIOCM_RTS;
320 446
321 return tmp; 447 return tmp;
@@ -324,11 +450,14 @@ static unsigned int imx_get_mctrl(struct uart_port *port)
324static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 450static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
325{ 451{
326 struct imx_port *sport = (struct imx_port *)port; 452 struct imx_port *sport = (struct imx_port *)port;
453 unsigned long temp;
454
455 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
327 456
328 if (mctrl & TIOCM_RTS) 457 if (mctrl & TIOCM_RTS)
329 UCR2((u32)sport->port.membase) |= UCR2_CTS; 458 temp |= UCR2_CTS;
330 else 459
331 UCR2((u32)sport->port.membase) &= ~UCR2_CTS; 460 writel(temp, sport->port.membase + UCR2);
332} 461}
333 462
334/* 463/*
@@ -337,14 +466,16 @@ static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
337static void imx_break_ctl(struct uart_port *port, int break_state) 466static void imx_break_ctl(struct uart_port *port, int break_state)
338{ 467{
339 struct imx_port *sport = (struct imx_port *)port; 468 struct imx_port *sport = (struct imx_port *)port;
340 unsigned long flags; 469 unsigned long flags, temp;
341 470
342 spin_lock_irqsave(&sport->port.lock, flags); 471 spin_lock_irqsave(&sport->port.lock, flags);
343 472
473 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
474
344 if ( break_state != 0 ) 475 if ( break_state != 0 )
345 UCR1((u32)sport->port.membase) |= UCR1_SNDBRK; 476 temp |= UCR1_SNDBRK;
346 else 477
347 UCR1((u32)sport->port.membase) &= ~UCR1_SNDBRK; 478 writel(temp, sport->port.membase + UCR1);
348 479
349 spin_unlock_irqrestore(&sport->port.lock, flags); 480 spin_unlock_irqrestore(&sport->port.lock, flags);
350} 481}
@@ -360,7 +491,7 @@ static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
360 /* set receiver / transmitter trigger level. 491 /* set receiver / transmitter trigger level.
361 * RFDIV is set such way to satisfy requested uartclk value 492 * RFDIV is set such way to satisfy requested uartclk value
362 */ 493 */
363 val = TXTL<<10 | RXTL; 494 val = TXTL << 10 | RXTL;
364 ufcr_rfdiv = (imx_get_perclk1() + sport->port.uartclk / 2) / sport->port.uartclk; 495 ufcr_rfdiv = (imx_get_perclk1() + sport->port.uartclk / 2) / sport->port.uartclk;
365 496
366 if(!ufcr_rfdiv) 497 if(!ufcr_rfdiv)
@@ -373,7 +504,7 @@ static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
373 504
374 val |= UFCR_RFDIV & (ufcr_rfdiv << 7); 505 val |= UFCR_RFDIV & (ufcr_rfdiv << 7);
375 506
376 UFCR((u32)sport->port.membase) = val; 507 writel(val, sport->port.membase + UFCR);
377 508
378 return 0; 509 return 0;
379} 510}
@@ -382,14 +513,15 @@ static int imx_startup(struct uart_port *port)
382{ 513{
383 struct imx_port *sport = (struct imx_port *)port; 514 struct imx_port *sport = (struct imx_port *)port;
384 int retval; 515 int retval;
385 unsigned long flags; 516 unsigned long flags, temp;
386 517
387 imx_setup_ufcr(sport, 0); 518 imx_setup_ufcr(sport, 0);
388 519
389 /* disable the DREN bit (Data Ready interrupt enable) before 520 /* disable the DREN bit (Data Ready interrupt enable) before
390 * requesting IRQs 521 * requesting IRQs
391 */ 522 */
392 UCR4((u32)sport->port.membase) &= ~UCR4_DREN; 523 temp = readl(sport->port.membase + UCR4);
524 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
393 525
394 /* 526 /*
395 * Allocate the IRQ 527 * Allocate the IRQ
@@ -411,12 +543,16 @@ static int imx_startup(struct uart_port *port)
411 /* 543 /*
412 * Finally, clear and enable interrupts 544 * Finally, clear and enable interrupts
413 */ 545 */
546 writel(USR1_RTSD, sport->port.membase + USR1);
547
548 temp = readl(sport->port.membase + UCR1);
549 temp |= (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
550 writel(temp, sport->port.membase + UCR1);
414 551
415 USR1((u32)sport->port.membase) = USR1_RTSD; 552 temp = readl(sport->port.membase + UCR2);
416 UCR1((u32)sport->port.membase) |= 553 temp |= (UCR2_RXEN | UCR2_TXEN);
417 (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 554 writel(temp, sport->port.membase + UCR2);
418 555
419 UCR2((u32)sport->port.membase) |= (UCR2_RXEN | UCR2_TXEN);
420 /* 556 /*
421 * Enable modem status interrupts 557 * Enable modem status interrupts
422 */ 558 */
@@ -437,6 +573,7 @@ error_out1:
437static void imx_shutdown(struct uart_port *port) 573static void imx_shutdown(struct uart_port *port)
438{ 574{
439 struct imx_port *sport = (struct imx_port *)port; 575 struct imx_port *sport = (struct imx_port *)port;
576 unsigned long temp;
440 577
441 /* 578 /*
442 * Stop our timer. 579 * Stop our timer.
@@ -454,8 +591,9 @@ static void imx_shutdown(struct uart_port *port)
454 * Disable all interrupts, port and break condition. 591 * Disable all interrupts, port and break condition.
455 */ 592 */
456 593
457 UCR1((u32)sport->port.membase) &= 594 temp = readl(sport->port.membase + UCR1);
458 ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 595 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
596 writel(temp, sport->port.membase + UCR1);
459} 597}
460 598
461static void 599static void
@@ -548,18 +686,18 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
548 /* 686 /*
549 * disable interrupts and drain transmitter 687 * disable interrupts and drain transmitter
550 */ 688 */
551 old_ucr1 = UCR1((u32)sport->port.membase); 689 old_ucr1 = readl(sport->port.membase + UCR1);
552 UCR1((u32)sport->port.membase) &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 690 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
691 sport->port.membase + UCR1);
553 692
554 while ( !(USR2((u32)sport->port.membase) & USR2_TXDC)) 693 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
555 barrier(); 694 barrier();
556 695
557 /* then, disable everything */ 696 /* then, disable everything */
558 old_txrxen = UCR2((u32)sport->port.membase) & ( UCR2_TXEN | UCR2_RXEN ); 697 old_txrxen = readl(sport->port.membase + UCR2);
559 UCR2((u32)sport->port.membase) &= ~( UCR2_TXEN | UCR2_RXEN); 698 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
560 699 sport->port.membase + UCR2);
561 /* set the parity, stop bits and data size */ 700 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
562 UCR2((u32)sport->port.membase) = ucr2;
563 701
564 /* set the baud rate. We assume uartclk = 16 MHz 702 /* set the baud rate. We assume uartclk = 16 MHz
565 * 703 *
@@ -567,11 +705,13 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
567 * --------- = -------- 705 * --------- = --------
568 * uartclk UBMR - 1 706 * uartclk UBMR - 1
569 */ 707 */
570 UBIR((u32)sport->port.membase) = (baud / 100) - 1; 708 writel((baud / 100) - 1, sport->port.membase + UBIR);
571 UBMR((u32)sport->port.membase) = 10000 - 1; 709 writel(10000 - 1, sport->port.membase + UBMR);
710
711 writel(old_ucr1, sport->port.membase + UCR1);
572 712
573 UCR1((u32)sport->port.membase) = old_ucr1; 713 /* set the parity, stop bits and data size */
574 UCR2((u32)sport->port.membase) |= old_txrxen; 714 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
575 715
576 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 716 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
577 imx_enable_ms(&sport->port); 717 imx_enable_ms(&sport->port);
@@ -730,9 +870,11 @@ static void __init imx_init_ports(void)
730static void imx_console_putchar(struct uart_port *port, int ch) 870static void imx_console_putchar(struct uart_port *port, int ch)
731{ 871{
732 struct imx_port *sport = (struct imx_port *)port; 872 struct imx_port *sport = (struct imx_port *)port;
733 while ((UTS((u32)sport->port.membase) & UTS_TXFULL)) 873
874 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
734 barrier(); 875 barrier();
735 URTX0((u32)sport->port.membase) = ch; 876
877 writel(ch, sport->port.membase + URTX0);
736} 878}
737 879
738/* 880/*
@@ -747,13 +889,14 @@ imx_console_write(struct console *co, const char *s, unsigned int count)
747 /* 889 /*
748 * First, save UCR1/2 and then disable interrupts 890 * First, save UCR1/2 and then disable interrupts
749 */ 891 */
750 old_ucr1 = UCR1((u32)sport->port.membase); 892 old_ucr1 = readl(sport->port.membase + UCR1);
751 old_ucr2 = UCR2((u32)sport->port.membase); 893 old_ucr2 = readl(sport->port.membase + UCR2);
752 894
753 UCR1((u32)sport->port.membase) = 895 writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
754 (old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) 896 ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
755 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 897 sport->port.membase + UCR1);
756 UCR2((u32)sport->port.membase) = old_ucr2 | UCR2_TXEN; 898
899 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
757 900
758 uart_console_write(&sport->port, s, count, imx_console_putchar); 901 uart_console_write(&sport->port, s, count, imx_console_putchar);
759 902
@@ -761,10 +904,10 @@ imx_console_write(struct console *co, const char *s, unsigned int count)
761 * Finally, wait for transmitter to become empty 904 * Finally, wait for transmitter to become empty
762 * and restore UCR1/2 905 * and restore UCR1/2
763 */ 906 */
764 while (!(USR2((u32)sport->port.membase) & USR2_TXDC)); 907 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
765 908
766 UCR1((u32)sport->port.membase) = old_ucr1; 909 writel(old_ucr1, sport->port.membase + UCR1);
767 UCR2((u32)sport->port.membase) = old_ucr2; 910 writel(old_ucr2, sport->port.membase + UCR2);
768} 911}
769 912
770/* 913/*
@@ -776,13 +919,13 @@ imx_console_get_options(struct imx_port *sport, int *baud,
776 int *parity, int *bits) 919 int *parity, int *bits)
777{ 920{
778 921
779 if ( UCR1((u32)sport->port.membase) | UCR1_UARTEN ) { 922 if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
780 /* ok, the port was enabled */ 923 /* ok, the port was enabled */
781 unsigned int ucr2, ubir,ubmr, uartclk; 924 unsigned int ucr2, ubir,ubmr, uartclk;
782 unsigned int baud_raw; 925 unsigned int baud_raw;
783 unsigned int ucfr_rfdiv; 926 unsigned int ucfr_rfdiv;
784 927
785 ucr2 = UCR2((u32)sport->port.membase); 928 ucr2 = readl(sport->port.membase + UCR2);
786 929
787 *parity = 'n'; 930 *parity = 'n';
788 if (ucr2 & UCR2_PREN) { 931 if (ucr2 & UCR2_PREN) {
@@ -797,11 +940,10 @@ imx_console_get_options(struct imx_port *sport, int *baud,
797 else 940 else
798 *bits = 7; 941 *bits = 7;
799 942
800 ubir = UBIR((u32)sport->port.membase) & 0xffff; 943 ubir = readl(sport->port.membase + UBIR) & 0xffff;
801 ubmr = UBMR((u32)sport->port.membase) & 0xffff; 944 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
802
803 945
804 ucfr_rfdiv = (UFCR((u32)sport->port.membase) & UFCR_RFDIV) >> 7; 946 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
805 if (ucfr_rfdiv == 6) 947 if (ucfr_rfdiv == 6)
806 ucfr_rfdiv = 7; 948 ucfr_rfdiv = 7;
807 else 949 else
diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c
index d403aaa55092..e9c6cb391a23 100644
--- a/drivers/serial/pxa.c
+++ b/drivers/serial/pxa.c
@@ -717,7 +717,7 @@ struct uart_ops serial_pxa_pops = {
717static struct uart_pxa_port serial_pxa_ports[] = { 717static struct uart_pxa_port serial_pxa_ports[] = {
718 { /* FFUART */ 718 { /* FFUART */
719 .name = "FFUART", 719 .name = "FFUART",
720 .cken = CKEN6_FFUART, 720 .cken = CKEN_FFUART,
721 .port = { 721 .port = {
722 .type = PORT_PXA, 722 .type = PORT_PXA,
723 .iotype = UPIO_MEM, 723 .iotype = UPIO_MEM,
@@ -731,7 +731,7 @@ static struct uart_pxa_port serial_pxa_ports[] = {
731 }, 731 },
732 }, { /* BTUART */ 732 }, { /* BTUART */
733 .name = "BTUART", 733 .name = "BTUART",
734 .cken = CKEN7_BTUART, 734 .cken = CKEN_BTUART,
735 .port = { 735 .port = {
736 .type = PORT_PXA, 736 .type = PORT_PXA,
737 .iotype = UPIO_MEM, 737 .iotype = UPIO_MEM,
@@ -745,7 +745,7 @@ static struct uart_pxa_port serial_pxa_ports[] = {
745 }, 745 },
746 }, { /* STUART */ 746 }, { /* STUART */
747 .name = "STUART", 747 .name = "STUART",
748 .cken = CKEN5_STUART, 748 .cken = CKEN_STUART,
749 .port = { 749 .port = {
750 .type = PORT_PXA, 750 .type = PORT_PXA,
751 .iotype = UPIO_MEM, 751 .iotype = UPIO_MEM,
@@ -759,7 +759,7 @@ static struct uart_pxa_port serial_pxa_ports[] = {
759 }, 759 },
760 }, { /* HWUART */ 760 }, { /* HWUART */
761 .name = "HWUART", 761 .name = "HWUART",
762 .cken = CKEN4_HWUART, 762 .cken = CKEN_HWUART,
763 .port = { 763 .port = {
764 .type = PORT_PXA, 764 .type = PORT_PXA,
765 .iotype = UPIO_MEM, 765 .iotype = UPIO_MEM,
diff --git a/drivers/usb/gadget/pxa2xx_udc.c b/drivers/usb/gadget/pxa2xx_udc.c
index 2c043a1ea156..84392e835d5f 100644
--- a/drivers/usb/gadget/pxa2xx_udc.c
+++ b/drivers/usb/gadget/pxa2xx_udc.c
@@ -1483,7 +1483,7 @@ static void udc_disable(struct pxa2xx_udc *dev)
1483 1483
1484#ifdef CONFIG_ARCH_PXA 1484#ifdef CONFIG_ARCH_PXA
1485 /* Disable clock for USB device */ 1485 /* Disable clock for USB device */
1486 pxa_set_cken(CKEN11_USB, 0); 1486 pxa_set_cken(CKEN_USB, 0);
1487#endif 1487#endif
1488 1488
1489 ep0_idle (dev); 1489 ep0_idle (dev);
@@ -1529,7 +1529,7 @@ static void udc_enable (struct pxa2xx_udc *dev)
1529 1529
1530#ifdef CONFIG_ARCH_PXA 1530#ifdef CONFIG_ARCH_PXA
1531 /* Enable clock for USB device */ 1531 /* Enable clock for USB device */
1532 pxa_set_cken(CKEN11_USB, 1); 1532 pxa_set_cken(CKEN_USB, 1);
1533 udelay(5); 1533 udelay(5);
1534#endif 1534#endif
1535 1535
diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c
index f1563dc319d3..23d2fe5a62f4 100644
--- a/drivers/usb/host/ohci-pxa27x.c
+++ b/drivers/usb/host/ohci-pxa27x.c
@@ -80,7 +80,7 @@ static int pxa27x_start_hc(struct device *dev)
80 80
81 inf = dev->platform_data; 81 inf = dev->platform_data;
82 82
83 pxa_set_cken(CKEN10_USBHOST, 1); 83 pxa_set_cken(CKEN_USBHOST, 1);
84 84
85 UHCHR |= UHCHR_FHR; 85 UHCHR |= UHCHR_FHR;
86 udelay(11); 86 udelay(11);
@@ -123,7 +123,7 @@ static void pxa27x_stop_hc(struct device *dev)
123 UHCCOMS |= 1; 123 UHCCOMS |= 1;
124 udelay(10); 124 udelay(10);
125 125
126 pxa_set_cken(CKEN10_USBHOST, 0); 126 pxa_set_cken(CKEN_USBHOST, 0);
127} 127}
128 128
129 129
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index b4947c810706..0b195f33f84f 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -803,7 +803,7 @@ static void pxafb_enable_controller(struct pxafb_info *fbi)
803 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3); 803 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
804 804
805 /* enable LCD controller clock */ 805 /* enable LCD controller clock */
806 pxa_set_cken(CKEN16_LCD, 1); 806 pxa_set_cken(CKEN_LCD, 1);
807 807
808 /* Sequence from 11.7.10 */ 808 /* Sequence from 11.7.10 */
809 LCCR3 = fbi->reg_lccr3; 809 LCCR3 = fbi->reg_lccr3;
@@ -840,7 +840,7 @@ static void pxafb_disable_controller(struct pxafb_info *fbi)
840 remove_wait_queue(&fbi->ctrlr_wait, &wait); 840 remove_wait_queue(&fbi->ctrlr_wait, &wait);
841 841
842 /* disable LCD controller clock */ 842 /* disable LCD controller clock */
843 pxa_set_cken(CKEN16_LCD, 0); 843 pxa_set_cken(CKEN_LCD, 0);
844} 844}
845 845
846/* 846/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 02:24:58 -0400