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-rw-r--r--drivers/gpu/drm/i915/i915_drv.c4
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h2
-rw-r--r--drivers/gpu/drm/i915/intel_display.c33
3 files changed, 33 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 28836fe72211..47a42eb6cc43 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -63,10 +63,10 @@ module_param_named(semaphores, i915_semaphores, int, 0600);
63MODULE_PARM_DESC(semaphores, 63MODULE_PARM_DESC(semaphores,
64 "Use semaphores for inter-ring sync (default: false)"); 64 "Use semaphores for inter-ring sync (default: false)");
65 65
66unsigned int i915_enable_rc6 __read_mostly = 0; 66int i915_enable_rc6 __read_mostly = -1;
67module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); 67module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
68MODULE_PARM_DESC(i915_enable_rc6, 68MODULE_PARM_DESC(i915_enable_rc6,
69 "Enable power-saving render C-state 6 (default: true)"); 69 "Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
70 70
71int i915_enable_fbc __read_mostly = -1; 71int i915_enable_fbc __read_mostly = -1;
72module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); 72module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 39a72f642b33..6bcafb5bf7fe 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1006,7 +1006,7 @@ extern unsigned int i915_semaphores __read_mostly;
1006extern unsigned int i915_lvds_downclock __read_mostly; 1006extern unsigned int i915_lvds_downclock __read_mostly;
1007extern int i915_panel_use_ssc __read_mostly; 1007extern int i915_panel_use_ssc __read_mostly;
1008extern int i915_vbt_sdvo_panel_type __read_mostly; 1008extern int i915_vbt_sdvo_panel_type __read_mostly;
1009extern unsigned int i915_enable_rc6 __read_mostly; 1009extern int i915_enable_rc6 __read_mostly;
1010extern int i915_enable_fbc __read_mostly; 1010extern int i915_enable_fbc __read_mostly;
1011extern bool i915_enable_hangcheck __read_mostly; 1011extern bool i915_enable_hangcheck __read_mostly;
1012 1012
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 633c69365388..d544de9e6634 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -38,8 +38,8 @@
38#include "i915_drv.h" 38#include "i915_drv.h"
39#include "i915_trace.h" 39#include "i915_trace.h"
40#include "drm_dp_helper.h" 40#include "drm_dp_helper.h"
41
42#include "drm_crtc_helper.h" 41#include "drm_crtc_helper.h"
42#include <linux/dma_remapping.h>
43 43
44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45 45
@@ -7887,6 +7887,33 @@ void intel_init_emon(struct drm_device *dev)
7887 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); 7887 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7888} 7888}
7889 7889
7890static bool intel_enable_rc6(struct drm_device *dev)
7891{
7892 /*
7893 * Respect the kernel parameter if it is set
7894 */
7895 if (i915_enable_rc6 >= 0)
7896 return i915_enable_rc6;
7897
7898 /*
7899 * Disable RC6 on Ironlake
7900 */
7901 if (INTEL_INFO(dev)->gen == 5)
7902 return 0;
7903
7904 /*
7905 * Enable rc6 on Sandybridge if DMA remapping is disabled
7906 */
7907 if (INTEL_INFO(dev)->gen == 6) {
7908 DRM_DEBUG_DRIVER("Sandybridge: intel_iommu_enabled %s -- RC6 %sabled\n",
7909 intel_iommu_enabled ? "true" : "false",
7910 !intel_iommu_enabled ? "en" : "dis");
7911 return !intel_iommu_enabled;
7912 }
7913 DRM_DEBUG_DRIVER("RC6 enabled\n");
7914 return 1;
7915}
7916
7890void gen6_enable_rps(struct drm_i915_private *dev_priv) 7917void gen6_enable_rps(struct drm_i915_private *dev_priv)
7891{ 7918{
7892 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 7919 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
@@ -7923,7 +7950,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
7923 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); 7950 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7924 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 7951 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7925 7952
7926 if (i915_enable_rc6) 7953 if (intel_enable_rc6(dev_priv->dev))
7927 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE | 7954 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7928 GEN6_RC_CTL_RC6_ENABLE; 7955 GEN6_RC_CTL_RC6_ENABLE;
7929 7956
@@ -8372,7 +8399,7 @@ void ironlake_enable_rc6(struct drm_device *dev)
8372 /* rc6 disabled by default due to repeated reports of hanging during 8399 /* rc6 disabled by default due to repeated reports of hanging during
8373 * boot and resume. 8400 * boot and resume.
8374 */ 8401 */
8375 if (!i915_enable_rc6) 8402 if (!intel_enable_rc6(dev))
8376 return; 8403 return;
8377 8404
8378 mutex_lock(&dev->struct_mutex); 8405 mutex_lock(&dev->struct_mutex);