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-rw-r--r--drivers/ide/pci/serverworks.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/ide/pci/serverworks.c b/drivers/ide/pci/serverworks.c
index c6f5fa4b4ca6..ff2e217a8c84 100644
--- a/drivers/ide/pci/serverworks.c
+++ b/drivers/ide/pci/serverworks.c
@@ -21,6 +21,9 @@
21 * 21 *
22 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel) 22 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
23 * 23 *
24 * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
25 * controller same as the CSB6. Single channel ATA100 only.
26 *
24 * Documentation: 27 * Documentation:
25 * Available under NDA only. Errata info very hard to get. 28 * Available under NDA only. Errata info very hard to get.
26 * 29 *
@@ -71,6 +74,8 @@ static u8 svwks_ratemask (ide_drive_t *drive)
71 if (!svwks_revision) 74 if (!svwks_revision)
72 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision); 75 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
73 76
77 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
78 return 2;
74 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { 79 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
75 u32 reg = 0; 80 u32 reg = 0;
76 if (isa_dev) 81 if (isa_dev)
@@ -109,6 +114,7 @@ static u8 svwks_csb_check (struct pci_dev *dev)
109 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: 114 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
110 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: 115 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
111 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: 116 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
117 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
112 return 1; 118 return 1;
113 default: 119 default:
114 break; 120 break;
@@ -438,6 +444,13 @@ static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const cha
438 btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2; 444 btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
439 pci_write_config_byte(dev, 0x5A, btr); 445 pci_write_config_byte(dev, 0x5A, btr);
440 } 446 }
447 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
448 else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
449 pci_read_config_byte(dev, 0x5A, &btr);
450 btr &= ~0x40;
451 btr |= 0x3;
452 pci_write_config_byte(dev, 0x5A, btr);
453 }
441 454
442 return (dev->irq) ? dev->irq : 0; 455 return (dev->irq) ? dev->irq : 0;
443} 456}
@@ -629,6 +642,15 @@ static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
629 .channels = 1, /* 2 */ 642 .channels = 1, /* 2 */
630 .autodma = AUTODMA, 643 .autodma = AUTODMA,
631 .bootable = ON_BOARD, 644 .bootable = ON_BOARD,
645 },{ /* 4 */
646 .name = "SvrWks HT1000",
647 .init_setup = init_setup_svwks,
648 .init_chipset = init_chipset_svwks,
649 .init_hwif = init_hwif_svwks,
650 .init_dma = init_dma_svwks,
651 .channels = 1, /* 2 */
652 .autodma = AUTODMA,
653 .bootable = ON_BOARD,
632 } 654 }
633}; 655};
634 656
@@ -653,6 +675,7 @@ static struct pci_device_id svwks_pci_tbl[] = {
653 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, 675 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
654 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, 676 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
655 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, 677 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
678 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
656 { 0, }, 679 { 0, },
657}; 680};
658MODULE_DEVICE_TABLE(pci, svwks_pci_tbl); 681MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);