diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/cxgb4/t4_hw.c | 3131 | ||||
-rw-r--r-- | drivers/net/cxgb4/t4_hw.h | 100 |
2 files changed, 3231 insertions, 0 deletions
diff --git a/drivers/net/cxgb4/t4_hw.c b/drivers/net/cxgb4/t4_hw.c new file mode 100644 index 000000000000..a814a3afe123 --- /dev/null +++ b/drivers/net/cxgb4/t4_hw.c | |||
@@ -0,0 +1,3131 @@ | |||
1 | /* | ||
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | ||
3 | * | ||
4 | * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved. | ||
5 | * | ||
6 | * This software is available to you under a choice of one of two | ||
7 | * licenses. You may choose to be licensed under the terms of the GNU | ||
8 | * General Public License (GPL) Version 2, available from the file | ||
9 | * COPYING in the main directory of this source tree, or the | ||
10 | * OpenIB.org BSD license below: | ||
11 | * | ||
12 | * Redistribution and use in source and binary forms, with or | ||
13 | * without modification, are permitted provided that the following | ||
14 | * conditions are met: | ||
15 | * | ||
16 | * - Redistributions of source code must retain the above | ||
17 | * copyright notice, this list of conditions and the following | ||
18 | * disclaimer. | ||
19 | * | ||
20 | * - Redistributions in binary form must reproduce the above | ||
21 | * copyright notice, this list of conditions and the following | ||
22 | * disclaimer in the documentation and/or other materials | ||
23 | * provided with the distribution. | ||
24 | * | ||
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | ||
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | ||
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | ||
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | ||
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | ||
32 | * SOFTWARE. | ||
33 | */ | ||
34 | |||
35 | #include <linux/init.h> | ||
36 | #include <linux/delay.h> | ||
37 | #include "cxgb4.h" | ||
38 | #include "t4_regs.h" | ||
39 | #include "t4fw_api.h" | ||
40 | |||
41 | /** | ||
42 | * t4_wait_op_done_val - wait until an operation is completed | ||
43 | * @adapter: the adapter performing the operation | ||
44 | * @reg: the register to check for completion | ||
45 | * @mask: a single-bit field within @reg that indicates completion | ||
46 | * @polarity: the value of the field when the operation is completed | ||
47 | * @attempts: number of check iterations | ||
48 | * @delay: delay in usecs between iterations | ||
49 | * @valp: where to store the value of the register at completion time | ||
50 | * | ||
51 | * Wait until an operation is completed by checking a bit in a register | ||
52 | * up to @attempts times. If @valp is not NULL the value of the register | ||
53 | * at the time it indicated completion is stored there. Returns 0 if the | ||
54 | * operation completes and -EAGAIN otherwise. | ||
55 | */ | ||
56 | int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, | ||
57 | int polarity, int attempts, int delay, u32 *valp) | ||
58 | { | ||
59 | while (1) { | ||
60 | u32 val = t4_read_reg(adapter, reg); | ||
61 | |||
62 | if (!!(val & mask) == polarity) { | ||
63 | if (valp) | ||
64 | *valp = val; | ||
65 | return 0; | ||
66 | } | ||
67 | if (--attempts == 0) | ||
68 | return -EAGAIN; | ||
69 | if (delay) | ||
70 | udelay(delay); | ||
71 | } | ||
72 | } | ||
73 | |||
74 | static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, | ||
75 | int polarity, int attempts, int delay) | ||
76 | { | ||
77 | return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, | ||
78 | delay, NULL); | ||
79 | } | ||
80 | |||
81 | /** | ||
82 | * t4_set_reg_field - set a register field to a value | ||
83 | * @adapter: the adapter to program | ||
84 | * @addr: the register address | ||
85 | * @mask: specifies the portion of the register to modify | ||
86 | * @val: the new value for the register field | ||
87 | * | ||
88 | * Sets a register field specified by the supplied mask to the | ||
89 | * given value. | ||
90 | */ | ||
91 | void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, | ||
92 | u32 val) | ||
93 | { | ||
94 | u32 v = t4_read_reg(adapter, addr) & ~mask; | ||
95 | |||
96 | t4_write_reg(adapter, addr, v | val); | ||
97 | (void) t4_read_reg(adapter, addr); /* flush */ | ||
98 | } | ||
99 | |||
100 | /** | ||
101 | * t4_read_indirect - read indirectly addressed registers | ||
102 | * @adap: the adapter | ||
103 | * @addr_reg: register holding the indirect address | ||
104 | * @data_reg: register holding the value of the indirect register | ||
105 | * @vals: where the read register values are stored | ||
106 | * @nregs: how many indirect registers to read | ||
107 | * @start_idx: index of first indirect register to read | ||
108 | * | ||
109 | * Reads registers that are accessed indirectly through an address/data | ||
110 | * register pair. | ||
111 | */ | ||
112 | void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, | ||
113 | unsigned int data_reg, u32 *vals, unsigned int nregs, | ||
114 | unsigned int start_idx) | ||
115 | { | ||
116 | while (nregs--) { | ||
117 | t4_write_reg(adap, addr_reg, start_idx); | ||
118 | *vals++ = t4_read_reg(adap, data_reg); | ||
119 | start_idx++; | ||
120 | } | ||
121 | } | ||
122 | |||
123 | /** | ||
124 | * t4_write_indirect - write indirectly addressed registers | ||
125 | * @adap: the adapter | ||
126 | * @addr_reg: register holding the indirect addresses | ||
127 | * @data_reg: register holding the value for the indirect registers | ||
128 | * @vals: values to write | ||
129 | * @nregs: how many indirect registers to write | ||
130 | * @start_idx: address of first indirect register to write | ||
131 | * | ||
132 | * Writes a sequential block of registers that are accessed indirectly | ||
133 | * through an address/data register pair. | ||
134 | */ | ||
135 | void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, | ||
136 | unsigned int data_reg, const u32 *vals, | ||
137 | unsigned int nregs, unsigned int start_idx) | ||
138 | { | ||
139 | while (nregs--) { | ||
140 | t4_write_reg(adap, addr_reg, start_idx++); | ||
141 | t4_write_reg(adap, data_reg, *vals++); | ||
142 | } | ||
143 | } | ||
144 | |||
145 | /* | ||
146 | * Get the reply to a mailbox command and store it in @rpl in big-endian order. | ||
147 | */ | ||
148 | static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, | ||
149 | u32 mbox_addr) | ||
150 | { | ||
151 | for ( ; nflit; nflit--, mbox_addr += 8) | ||
152 | *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); | ||
153 | } | ||
154 | |||
155 | /* | ||
156 | * Handle a FW assertion reported in a mailbox. | ||
157 | */ | ||
158 | static void fw_asrt(struct adapter *adap, u32 mbox_addr) | ||
159 | { | ||
160 | struct fw_debug_cmd asrt; | ||
161 | |||
162 | get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr); | ||
163 | dev_alert(adap->pdev_dev, | ||
164 | "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", | ||
165 | asrt.u.assert.filename_0_7, ntohl(asrt.u.assert.line), | ||
166 | ntohl(asrt.u.assert.x), ntohl(asrt.u.assert.y)); | ||
167 | } | ||
168 | |||
169 | static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg) | ||
170 | { | ||
171 | dev_err(adap->pdev_dev, | ||
172 | "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox, | ||
173 | (unsigned long long)t4_read_reg64(adap, data_reg), | ||
174 | (unsigned long long)t4_read_reg64(adap, data_reg + 8), | ||
175 | (unsigned long long)t4_read_reg64(adap, data_reg + 16), | ||
176 | (unsigned long long)t4_read_reg64(adap, data_reg + 24), | ||
177 | (unsigned long long)t4_read_reg64(adap, data_reg + 32), | ||
178 | (unsigned long long)t4_read_reg64(adap, data_reg + 40), | ||
179 | (unsigned long long)t4_read_reg64(adap, data_reg + 48), | ||
180 | (unsigned long long)t4_read_reg64(adap, data_reg + 56)); | ||
181 | } | ||
182 | |||
183 | /** | ||
184 | * t4_wr_mbox_meat - send a command to FW through the given mailbox | ||
185 | * @adap: the adapter | ||
186 | * @mbox: index of the mailbox to use | ||
187 | * @cmd: the command to write | ||
188 | * @size: command length in bytes | ||
189 | * @rpl: where to optionally store the reply | ||
190 | * @sleep_ok: if true we may sleep while awaiting command completion | ||
191 | * | ||
192 | * Sends the given command to FW through the selected mailbox and waits | ||
193 | * for the FW to execute the command. If @rpl is not %NULL it is used to | ||
194 | * store the FW's reply to the command. The command and its optional | ||
195 | * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms | ||
196 | * to respond. @sleep_ok determines whether we may sleep while awaiting | ||
197 | * the response. If sleeping is allowed we use progressive backoff | ||
198 | * otherwise we spin. | ||
199 | * | ||
200 | * The return value is 0 on success or a negative errno on failure. A | ||
201 | * failure can happen either because we are not able to execute the | ||
202 | * command or FW executes it but signals an error. In the latter case | ||
203 | * the return value is the error code indicated by FW (negated). | ||
204 | */ | ||
205 | int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, | ||
206 | void *rpl, bool sleep_ok) | ||
207 | { | ||
208 | static int delay[] = { | ||
209 | 1, 1, 3, 5, 10, 10, 20, 50, 100, 200 | ||
210 | }; | ||
211 | |||
212 | u32 v; | ||
213 | u64 res; | ||
214 | int i, ms, delay_idx; | ||
215 | const __be64 *p = cmd; | ||
216 | u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA); | ||
217 | u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL); | ||
218 | |||
219 | if ((size & 15) || size > MBOX_LEN) | ||
220 | return -EINVAL; | ||
221 | |||
222 | v = MBOWNER_GET(t4_read_reg(adap, ctl_reg)); | ||
223 | for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++) | ||
224 | v = MBOWNER_GET(t4_read_reg(adap, ctl_reg)); | ||
225 | |||
226 | if (v != MBOX_OWNER_DRV) | ||
227 | return v ? -EBUSY : -ETIMEDOUT; | ||
228 | |||
229 | for (i = 0; i < size; i += 8) | ||
230 | t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++)); | ||
231 | |||
232 | t4_write_reg(adap, ctl_reg, MBMSGVALID | MBOWNER(MBOX_OWNER_FW)); | ||
233 | t4_read_reg(adap, ctl_reg); /* flush write */ | ||
234 | |||
235 | delay_idx = 0; | ||
236 | ms = delay[0]; | ||
237 | |||
238 | for (i = 0; i < FW_CMD_MAX_TIMEOUT; i += ms) { | ||
239 | if (sleep_ok) { | ||
240 | ms = delay[delay_idx]; /* last element may repeat */ | ||
241 | if (delay_idx < ARRAY_SIZE(delay) - 1) | ||
242 | delay_idx++; | ||
243 | msleep(ms); | ||
244 | } else | ||
245 | mdelay(ms); | ||
246 | |||
247 | v = t4_read_reg(adap, ctl_reg); | ||
248 | if (MBOWNER_GET(v) == MBOX_OWNER_DRV) { | ||
249 | if (!(v & MBMSGVALID)) { | ||
250 | t4_write_reg(adap, ctl_reg, 0); | ||
251 | continue; | ||
252 | } | ||
253 | |||
254 | res = t4_read_reg64(adap, data_reg); | ||
255 | if (FW_CMD_OP_GET(res >> 32) == FW_DEBUG_CMD) { | ||
256 | fw_asrt(adap, data_reg); | ||
257 | res = FW_CMD_RETVAL(EIO); | ||
258 | } else if (rpl) | ||
259 | get_mbox_rpl(adap, rpl, size / 8, data_reg); | ||
260 | |||
261 | if (FW_CMD_RETVAL_GET((int)res)) | ||
262 | dump_mbox(adap, mbox, data_reg); | ||
263 | t4_write_reg(adap, ctl_reg, 0); | ||
264 | return -FW_CMD_RETVAL_GET((int)res); | ||
265 | } | ||
266 | } | ||
267 | |||
268 | dump_mbox(adap, mbox, data_reg); | ||
269 | dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n", | ||
270 | *(const u8 *)cmd, mbox); | ||
271 | return -ETIMEDOUT; | ||
272 | } | ||
273 | |||
274 | /** | ||
275 | * t4_mc_read - read from MC through backdoor accesses | ||
276 | * @adap: the adapter | ||
277 | * @addr: address of first byte requested | ||
278 | * @data: 64 bytes of data containing the requested address | ||
279 | * @ecc: where to store the corresponding 64-bit ECC word | ||
280 | * | ||
281 | * Read 64 bytes of data from MC starting at a 64-byte-aligned address | ||
282 | * that covers the requested address @addr. If @parity is not %NULL it | ||
283 | * is assigned the 64-bit ECC word for the read data. | ||
284 | */ | ||
285 | int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *ecc) | ||
286 | { | ||
287 | int i; | ||
288 | |||
289 | if (t4_read_reg(adap, MC_BIST_CMD) & START_BIST) | ||
290 | return -EBUSY; | ||
291 | t4_write_reg(adap, MC_BIST_CMD_ADDR, addr & ~0x3fU); | ||
292 | t4_write_reg(adap, MC_BIST_CMD_LEN, 64); | ||
293 | t4_write_reg(adap, MC_BIST_DATA_PATTERN, 0xc); | ||
294 | t4_write_reg(adap, MC_BIST_CMD, BIST_OPCODE(1) | START_BIST | | ||
295 | BIST_CMD_GAP(1)); | ||
296 | i = t4_wait_op_done(adap, MC_BIST_CMD, START_BIST, 0, 10, 1); | ||
297 | if (i) | ||
298 | return i; | ||
299 | |||
300 | #define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA, i) | ||
301 | |||
302 | for (i = 15; i >= 0; i--) | ||
303 | *data++ = htonl(t4_read_reg(adap, MC_DATA(i))); | ||
304 | if (ecc) | ||
305 | *ecc = t4_read_reg64(adap, MC_DATA(16)); | ||
306 | #undef MC_DATA | ||
307 | return 0; | ||
308 | } | ||
309 | |||
310 | /** | ||
311 | * t4_edc_read - read from EDC through backdoor accesses | ||
312 | * @adap: the adapter | ||
313 | * @idx: which EDC to access | ||
314 | * @addr: address of first byte requested | ||
315 | * @data: 64 bytes of data containing the requested address | ||
316 | * @ecc: where to store the corresponding 64-bit ECC word | ||
317 | * | ||
318 | * Read 64 bytes of data from EDC starting at a 64-byte-aligned address | ||
319 | * that covers the requested address @addr. If @parity is not %NULL it | ||
320 | * is assigned the 64-bit ECC word for the read data. | ||
321 | */ | ||
322 | int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) | ||
323 | { | ||
324 | int i; | ||
325 | |||
326 | idx *= EDC_STRIDE; | ||
327 | if (t4_read_reg(adap, EDC_BIST_CMD + idx) & START_BIST) | ||
328 | return -EBUSY; | ||
329 | t4_write_reg(adap, EDC_BIST_CMD_ADDR + idx, addr & ~0x3fU); | ||
330 | t4_write_reg(adap, EDC_BIST_CMD_LEN + idx, 64); | ||
331 | t4_write_reg(adap, EDC_BIST_DATA_PATTERN + idx, 0xc); | ||
332 | t4_write_reg(adap, EDC_BIST_CMD + idx, | ||
333 | BIST_OPCODE(1) | BIST_CMD_GAP(1) | START_BIST); | ||
334 | i = t4_wait_op_done(adap, EDC_BIST_CMD + idx, START_BIST, 0, 10, 1); | ||
335 | if (i) | ||
336 | return i; | ||
337 | |||
338 | #define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA, i) + idx) | ||
339 | |||
340 | for (i = 15; i >= 0; i--) | ||
341 | *data++ = htonl(t4_read_reg(adap, EDC_DATA(i))); | ||
342 | if (ecc) | ||
343 | *ecc = t4_read_reg64(adap, EDC_DATA(16)); | ||
344 | #undef EDC_DATA | ||
345 | return 0; | ||
346 | } | ||
347 | |||
348 | #define VPD_ENTRY(name, len) \ | ||
349 | u8 name##_kword[2]; u8 name##_len; u8 name##_data[len] | ||
350 | |||
351 | /* | ||
352 | * Partial EEPROM Vital Product Data structure. Includes only the ID and | ||
353 | * VPD-R sections. | ||
354 | */ | ||
355 | struct t4_vpd { | ||
356 | u8 id_tag; | ||
357 | u8 id_len[2]; | ||
358 | u8 id_data[ID_LEN]; | ||
359 | u8 vpdr_tag; | ||
360 | u8 vpdr_len[2]; | ||
361 | VPD_ENTRY(pn, 16); /* part number */ | ||
362 | VPD_ENTRY(ec, EC_LEN); /* EC level */ | ||
363 | VPD_ENTRY(sn, SERNUM_LEN); /* serial number */ | ||
364 | VPD_ENTRY(na, 12); /* MAC address base */ | ||
365 | VPD_ENTRY(port_type, 8); /* port types */ | ||
366 | VPD_ENTRY(gpio, 14); /* GPIO usage */ | ||
367 | VPD_ENTRY(cclk, 6); /* core clock */ | ||
368 | VPD_ENTRY(port_addr, 8); /* port MDIO addresses */ | ||
369 | VPD_ENTRY(rv, 1); /* csum */ | ||
370 | u32 pad; /* for multiple-of-4 sizing and alignment */ | ||
371 | }; | ||
372 | |||
373 | #define EEPROM_STAT_ADDR 0x7bfc | ||
374 | #define VPD_BASE 0 | ||
375 | |||
376 | /** | ||
377 | * t4_seeprom_wp - enable/disable EEPROM write protection | ||
378 | * @adapter: the adapter | ||
379 | * @enable: whether to enable or disable write protection | ||
380 | * | ||
381 | * Enables or disables write protection on the serial EEPROM. | ||
382 | */ | ||
383 | int t4_seeprom_wp(struct adapter *adapter, bool enable) | ||
384 | { | ||
385 | unsigned int v = enable ? 0xc : 0; | ||
386 | int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v); | ||
387 | return ret < 0 ? ret : 0; | ||
388 | } | ||
389 | |||
390 | /** | ||
391 | * get_vpd_params - read VPD parameters from VPD EEPROM | ||
392 | * @adapter: adapter to read | ||
393 | * @p: where to store the parameters | ||
394 | * | ||
395 | * Reads card parameters stored in VPD EEPROM. | ||
396 | */ | ||
397 | static int get_vpd_params(struct adapter *adapter, struct vpd_params *p) | ||
398 | { | ||
399 | int ret; | ||
400 | struct t4_vpd vpd; | ||
401 | u8 *q = (u8 *)&vpd, csum; | ||
402 | |||
403 | ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(vpd), &vpd); | ||
404 | if (ret < 0) | ||
405 | return ret; | ||
406 | |||
407 | for (csum = 0; q <= vpd.rv_data; q++) | ||
408 | csum += *q; | ||
409 | |||
410 | if (csum) { | ||
411 | dev_err(adapter->pdev_dev, | ||
412 | "corrupted VPD EEPROM, actual csum %u\n", csum); | ||
413 | return -EINVAL; | ||
414 | } | ||
415 | |||
416 | p->cclk = simple_strtoul(vpd.cclk_data, NULL, 10); | ||
417 | memcpy(p->id, vpd.id_data, sizeof(vpd.id_data)); | ||
418 | strim(p->id); | ||
419 | memcpy(p->ec, vpd.ec_data, sizeof(vpd.ec_data)); | ||
420 | strim(p->ec); | ||
421 | memcpy(p->sn, vpd.sn_data, sizeof(vpd.sn_data)); | ||
422 | strim(p->sn); | ||
423 | return 0; | ||
424 | } | ||
425 | |||
426 | /* serial flash and firmware constants */ | ||
427 | enum { | ||
428 | SF_ATTEMPTS = 10, /* max retries for SF operations */ | ||
429 | |||
430 | /* flash command opcodes */ | ||
431 | SF_PROG_PAGE = 2, /* program page */ | ||
432 | SF_WR_DISABLE = 4, /* disable writes */ | ||
433 | SF_RD_STATUS = 5, /* read status register */ | ||
434 | SF_WR_ENABLE = 6, /* enable writes */ | ||
435 | SF_RD_DATA_FAST = 0xb, /* read flash */ | ||
436 | SF_ERASE_SECTOR = 0xd8, /* erase sector */ | ||
437 | |||
438 | FW_START_SEC = 8, /* first flash sector for FW */ | ||
439 | FW_END_SEC = 15, /* last flash sector for FW */ | ||
440 | FW_IMG_START = FW_START_SEC * SF_SEC_SIZE, | ||
441 | FW_MAX_SIZE = (FW_END_SEC - FW_START_SEC + 1) * SF_SEC_SIZE, | ||
442 | }; | ||
443 | |||
444 | /** | ||
445 | * sf1_read - read data from the serial flash | ||
446 | * @adapter: the adapter | ||
447 | * @byte_cnt: number of bytes to read | ||
448 | * @cont: whether another operation will be chained | ||
449 | * @lock: whether to lock SF for PL access only | ||
450 | * @valp: where to store the read data | ||
451 | * | ||
452 | * Reads up to 4 bytes of data from the serial flash. The location of | ||
453 | * the read needs to be specified prior to calling this by issuing the | ||
454 | * appropriate commands to the serial flash. | ||
455 | */ | ||
456 | static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, | ||
457 | int lock, u32 *valp) | ||
458 | { | ||
459 | int ret; | ||
460 | |||
461 | if (!byte_cnt || byte_cnt > 4) | ||
462 | return -EINVAL; | ||
463 | if (t4_read_reg(adapter, SF_OP) & BUSY) | ||
464 | return -EBUSY; | ||
465 | cont = cont ? SF_CONT : 0; | ||
466 | lock = lock ? SF_LOCK : 0; | ||
467 | t4_write_reg(adapter, SF_OP, lock | cont | BYTECNT(byte_cnt - 1)); | ||
468 | ret = t4_wait_op_done(adapter, SF_OP, BUSY, 0, SF_ATTEMPTS, 5); | ||
469 | if (!ret) | ||
470 | *valp = t4_read_reg(adapter, SF_DATA); | ||
471 | return ret; | ||
472 | } | ||
473 | |||
474 | /** | ||
475 | * sf1_write - write data to the serial flash | ||
476 | * @adapter: the adapter | ||
477 | * @byte_cnt: number of bytes to write | ||
478 | * @cont: whether another operation will be chained | ||
479 | * @lock: whether to lock SF for PL access only | ||
480 | * @val: value to write | ||
481 | * | ||
482 | * Writes up to 4 bytes of data to the serial flash. The location of | ||
483 | * the write needs to be specified prior to calling this by issuing the | ||
484 | * appropriate commands to the serial flash. | ||
485 | */ | ||
486 | static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, | ||
487 | int lock, u32 val) | ||
488 | { | ||
489 | if (!byte_cnt || byte_cnt > 4) | ||
490 | return -EINVAL; | ||
491 | if (t4_read_reg(adapter, SF_OP) & BUSY) | ||
492 | return -EBUSY; | ||
493 | cont = cont ? SF_CONT : 0; | ||
494 | lock = lock ? SF_LOCK : 0; | ||
495 | t4_write_reg(adapter, SF_DATA, val); | ||
496 | t4_write_reg(adapter, SF_OP, lock | | ||
497 | cont | BYTECNT(byte_cnt - 1) | OP_WR); | ||
498 | return t4_wait_op_done(adapter, SF_OP, BUSY, 0, SF_ATTEMPTS, 5); | ||
499 | } | ||
500 | |||
501 | /** | ||
502 | * flash_wait_op - wait for a flash operation to complete | ||
503 | * @adapter: the adapter | ||
504 | * @attempts: max number of polls of the status register | ||
505 | * @delay: delay between polls in ms | ||
506 | * | ||
507 | * Wait for a flash operation to complete by polling the status register. | ||
508 | */ | ||
509 | static int flash_wait_op(struct adapter *adapter, int attempts, int delay) | ||
510 | { | ||
511 | int ret; | ||
512 | u32 status; | ||
513 | |||
514 | while (1) { | ||
515 | if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || | ||
516 | (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) | ||
517 | return ret; | ||
518 | if (!(status & 1)) | ||
519 | return 0; | ||
520 | if (--attempts == 0) | ||
521 | return -EAGAIN; | ||
522 | if (delay) | ||
523 | msleep(delay); | ||
524 | } | ||
525 | } | ||
526 | |||
527 | /** | ||
528 | * t4_read_flash - read words from serial flash | ||
529 | * @adapter: the adapter | ||
530 | * @addr: the start address for the read | ||
531 | * @nwords: how many 32-bit words to read | ||
532 | * @data: where to store the read data | ||
533 | * @byte_oriented: whether to store data as bytes or as words | ||
534 | * | ||
535 | * Read the specified number of 32-bit words from the serial flash. | ||
536 | * If @byte_oriented is set the read data is stored as a byte array | ||
537 | * (i.e., big-endian), otherwise as 32-bit words in the platform's | ||
538 | * natural endianess. | ||
539 | */ | ||
540 | int t4_read_flash(struct adapter *adapter, unsigned int addr, | ||
541 | unsigned int nwords, u32 *data, int byte_oriented) | ||
542 | { | ||
543 | int ret; | ||
544 | |||
545 | if (addr + nwords * sizeof(u32) > SF_SIZE || (addr & 3)) | ||
546 | return -EINVAL; | ||
547 | |||
548 | addr = swab32(addr) | SF_RD_DATA_FAST; | ||
549 | |||
550 | if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || | ||
551 | (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) | ||
552 | return ret; | ||
553 | |||
554 | for ( ; nwords; nwords--, data++) { | ||
555 | ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); | ||
556 | if (nwords == 1) | ||
557 | t4_write_reg(adapter, SF_OP, 0); /* unlock SF */ | ||
558 | if (ret) | ||
559 | return ret; | ||
560 | if (byte_oriented) | ||
561 | *data = htonl(*data); | ||
562 | } | ||
563 | return 0; | ||
564 | } | ||
565 | |||
566 | /** | ||
567 | * t4_write_flash - write up to a page of data to the serial flash | ||
568 | * @adapter: the adapter | ||
569 | * @addr: the start address to write | ||
570 | * @n: length of data to write in bytes | ||
571 | * @data: the data to write | ||
572 | * | ||
573 | * Writes up to a page of data (256 bytes) to the serial flash starting | ||
574 | * at the given address. All the data must be written to the same page. | ||
575 | */ | ||
576 | static int t4_write_flash(struct adapter *adapter, unsigned int addr, | ||
577 | unsigned int n, const u8 *data) | ||
578 | { | ||
579 | int ret; | ||
580 | u32 buf[64]; | ||
581 | unsigned int i, c, left, val, offset = addr & 0xff; | ||
582 | |||
583 | if (addr >= SF_SIZE || offset + n > SF_PAGE_SIZE) | ||
584 | return -EINVAL; | ||
585 | |||
586 | val = swab32(addr) | SF_PROG_PAGE; | ||
587 | |||
588 | if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || | ||
589 | (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) | ||
590 | goto unlock; | ||
591 | |||
592 | for (left = n; left; left -= c) { | ||
593 | c = min(left, 4U); | ||
594 | for (val = 0, i = 0; i < c; ++i) | ||
595 | val = (val << 8) + *data++; | ||
596 | |||
597 | ret = sf1_write(adapter, c, c != left, 1, val); | ||
598 | if (ret) | ||
599 | goto unlock; | ||
600 | } | ||
601 | ret = flash_wait_op(adapter, 5, 1); | ||
602 | if (ret) | ||
603 | goto unlock; | ||
604 | |||
605 | t4_write_reg(adapter, SF_OP, 0); /* unlock SF */ | ||
606 | |||
607 | /* Read the page to verify the write succeeded */ | ||
608 | ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); | ||
609 | if (ret) | ||
610 | return ret; | ||
611 | |||
612 | if (memcmp(data - n, (u8 *)buf + offset, n)) { | ||
613 | dev_err(adapter->pdev_dev, | ||
614 | "failed to correctly write the flash page at %#x\n", | ||
615 | addr); | ||
616 | return -EIO; | ||
617 | } | ||
618 | return 0; | ||
619 | |||
620 | unlock: | ||
621 | t4_write_reg(adapter, SF_OP, 0); /* unlock SF */ | ||
622 | return ret; | ||
623 | } | ||
624 | |||
625 | /** | ||
626 | * get_fw_version - read the firmware version | ||
627 | * @adapter: the adapter | ||
628 | * @vers: where to place the version | ||
629 | * | ||
630 | * Reads the FW version from flash. | ||
631 | */ | ||
632 | static int get_fw_version(struct adapter *adapter, u32 *vers) | ||
633 | { | ||
634 | return t4_read_flash(adapter, | ||
635 | FW_IMG_START + offsetof(struct fw_hdr, fw_ver), 1, | ||
636 | vers, 0); | ||
637 | } | ||
638 | |||
639 | /** | ||
640 | * get_tp_version - read the TP microcode version | ||
641 | * @adapter: the adapter | ||
642 | * @vers: where to place the version | ||
643 | * | ||
644 | * Reads the TP microcode version from flash. | ||
645 | */ | ||
646 | static int get_tp_version(struct adapter *adapter, u32 *vers) | ||
647 | { | ||
648 | return t4_read_flash(adapter, FW_IMG_START + offsetof(struct fw_hdr, | ||
649 | tp_microcode_ver), | ||
650 | 1, vers, 0); | ||
651 | } | ||
652 | |||
653 | /** | ||
654 | * t4_check_fw_version - check if the FW is compatible with this driver | ||
655 | * @adapter: the adapter | ||
656 | * | ||
657 | * Checks if an adapter's FW is compatible with the driver. Returns 0 | ||
658 | * if there's exact match, a negative error if the version could not be | ||
659 | * read or there's a major version mismatch, and a positive value if the | ||
660 | * expected major version is found but there's a minor version mismatch. | ||
661 | */ | ||
662 | int t4_check_fw_version(struct adapter *adapter) | ||
663 | { | ||
664 | u32 api_vers[2]; | ||
665 | int ret, major, minor, micro; | ||
666 | |||
667 | ret = get_fw_version(adapter, &adapter->params.fw_vers); | ||
668 | if (!ret) | ||
669 | ret = get_tp_version(adapter, &adapter->params.tp_vers); | ||
670 | if (!ret) | ||
671 | ret = t4_read_flash(adapter, | ||
672 | FW_IMG_START + offsetof(struct fw_hdr, intfver_nic), | ||
673 | 2, api_vers, 1); | ||
674 | if (ret) | ||
675 | return ret; | ||
676 | |||
677 | major = FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers); | ||
678 | minor = FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers); | ||
679 | micro = FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers); | ||
680 | memcpy(adapter->params.api_vers, api_vers, | ||
681 | sizeof(adapter->params.api_vers)); | ||
682 | |||
683 | if (major != FW_VERSION_MAJOR) { /* major mismatch - fail */ | ||
684 | dev_err(adapter->pdev_dev, | ||
685 | "card FW has major version %u, driver wants %u\n", | ||
686 | major, FW_VERSION_MAJOR); | ||
687 | return -EINVAL; | ||
688 | } | ||
689 | |||
690 | if (minor == FW_VERSION_MINOR && micro == FW_VERSION_MICRO) | ||
691 | return 0; /* perfect match */ | ||
692 | |||
693 | /* Minor/micro version mismatch. Report it but often it's OK. */ | ||
694 | return 1; | ||
695 | } | ||
696 | |||
697 | /** | ||
698 | * t4_flash_erase_sectors - erase a range of flash sectors | ||
699 | * @adapter: the adapter | ||
700 | * @start: the first sector to erase | ||
701 | * @end: the last sector to erase | ||
702 | * | ||
703 | * Erases the sectors in the given inclusive range. | ||
704 | */ | ||
705 | static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) | ||
706 | { | ||
707 | int ret = 0; | ||
708 | |||
709 | while (start <= end) { | ||
710 | if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || | ||
711 | (ret = sf1_write(adapter, 4, 0, 1, | ||
712 | SF_ERASE_SECTOR | (start << 8))) != 0 || | ||
713 | (ret = flash_wait_op(adapter, 5, 500)) != 0) { | ||
714 | dev_err(adapter->pdev_dev, | ||
715 | "erase of flash sector %d failed, error %d\n", | ||
716 | start, ret); | ||
717 | break; | ||
718 | } | ||
719 | start++; | ||
720 | } | ||
721 | t4_write_reg(adapter, SF_OP, 0); /* unlock SF */ | ||
722 | return ret; | ||
723 | } | ||
724 | |||
725 | /** | ||
726 | * t4_load_fw - download firmware | ||
727 | * @adap: the adapter | ||
728 | * @fw_data: the firmware image to write | ||
729 | * @size: image size | ||
730 | * | ||
731 | * Write the supplied firmware image to the card's serial flash. | ||
732 | */ | ||
733 | int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) | ||
734 | { | ||
735 | u32 csum; | ||
736 | int ret, addr; | ||
737 | unsigned int i; | ||
738 | u8 first_page[SF_PAGE_SIZE]; | ||
739 | const u32 *p = (const u32 *)fw_data; | ||
740 | const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; | ||
741 | |||
742 | if (!size) { | ||
743 | dev_err(adap->pdev_dev, "FW image has no data\n"); | ||
744 | return -EINVAL; | ||
745 | } | ||
746 | if (size & 511) { | ||
747 | dev_err(adap->pdev_dev, | ||
748 | "FW image size not multiple of 512 bytes\n"); | ||
749 | return -EINVAL; | ||
750 | } | ||
751 | if (ntohs(hdr->len512) * 512 != size) { | ||
752 | dev_err(adap->pdev_dev, | ||
753 | "FW image size differs from size in FW header\n"); | ||
754 | return -EINVAL; | ||
755 | } | ||
756 | if (size > FW_MAX_SIZE) { | ||
757 | dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n", | ||
758 | FW_MAX_SIZE); | ||
759 | return -EFBIG; | ||
760 | } | ||
761 | |||
762 | for (csum = 0, i = 0; i < size / sizeof(csum); i++) | ||
763 | csum += ntohl(p[i]); | ||
764 | |||
765 | if (csum != 0xffffffff) { | ||
766 | dev_err(adap->pdev_dev, | ||
767 | "corrupted firmware image, checksum %#x\n", csum); | ||
768 | return -EINVAL; | ||
769 | } | ||
770 | |||
771 | i = DIV_ROUND_UP(size, SF_SEC_SIZE); /* # of sectors spanned */ | ||
772 | ret = t4_flash_erase_sectors(adap, FW_START_SEC, FW_START_SEC + i - 1); | ||
773 | if (ret) | ||
774 | goto out; | ||
775 | |||
776 | /* | ||
777 | * We write the correct version at the end so the driver can see a bad | ||
778 | * version if the FW write fails. Start by writing a copy of the | ||
779 | * first page with a bad version. | ||
780 | */ | ||
781 | memcpy(first_page, fw_data, SF_PAGE_SIZE); | ||
782 | ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff); | ||
783 | ret = t4_write_flash(adap, FW_IMG_START, SF_PAGE_SIZE, first_page); | ||
784 | if (ret) | ||
785 | goto out; | ||
786 | |||
787 | addr = FW_IMG_START; | ||
788 | for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { | ||
789 | addr += SF_PAGE_SIZE; | ||
790 | fw_data += SF_PAGE_SIZE; | ||
791 | ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data); | ||
792 | if (ret) | ||
793 | goto out; | ||
794 | } | ||
795 | |||
796 | ret = t4_write_flash(adap, | ||
797 | FW_IMG_START + offsetof(struct fw_hdr, fw_ver), | ||
798 | sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver); | ||
799 | out: | ||
800 | if (ret) | ||
801 | dev_err(adap->pdev_dev, "firmware download failed, error %d\n", | ||
802 | ret); | ||
803 | return ret; | ||
804 | } | ||
805 | |||
806 | #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\ | ||
807 | FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_ANEG) | ||
808 | |||
809 | /** | ||
810 | * t4_link_start - apply link configuration to MAC/PHY | ||
811 | * @phy: the PHY to setup | ||
812 | * @mac: the MAC to setup | ||
813 | * @lc: the requested link configuration | ||
814 | * | ||
815 | * Set up a port's MAC and PHY according to a desired link configuration. | ||
816 | * - If the PHY can auto-negotiate first decide what to advertise, then | ||
817 | * enable/disable auto-negotiation as desired, and reset. | ||
818 | * - If the PHY does not auto-negotiate just reset it. | ||
819 | * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, | ||
820 | * otherwise do it later based on the outcome of auto-negotiation. | ||
821 | */ | ||
822 | int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, | ||
823 | struct link_config *lc) | ||
824 | { | ||
825 | struct fw_port_cmd c; | ||
826 | unsigned int fc = 0, mdi = FW_PORT_MDI(FW_PORT_MDI_AUTO); | ||
827 | |||
828 | lc->link_ok = 0; | ||
829 | if (lc->requested_fc & PAUSE_RX) | ||
830 | fc |= FW_PORT_CAP_FC_RX; | ||
831 | if (lc->requested_fc & PAUSE_TX) | ||
832 | fc |= FW_PORT_CAP_FC_TX; | ||
833 | |||
834 | memset(&c, 0, sizeof(c)); | ||
835 | c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST | | ||
836 | FW_CMD_EXEC | FW_PORT_CMD_PORTID(port)); | ||
837 | c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | | ||
838 | FW_LEN16(c)); | ||
839 | |||
840 | if (!(lc->supported & FW_PORT_CAP_ANEG)) { | ||
841 | c.u.l1cfg.rcap = htonl((lc->supported & ADVERT_MASK) | fc); | ||
842 | lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); | ||
843 | } else if (lc->autoneg == AUTONEG_DISABLE) { | ||
844 | c.u.l1cfg.rcap = htonl(lc->requested_speed | fc | mdi); | ||
845 | lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); | ||
846 | } else | ||
847 | c.u.l1cfg.rcap = htonl(lc->advertising | fc | mdi); | ||
848 | |||
849 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | ||
850 | } | ||
851 | |||
852 | /** | ||
853 | * t4_restart_aneg - restart autonegotiation | ||
854 | * @adap: the adapter | ||
855 | * @mbox: mbox to use for the FW command | ||
856 | * @port: the port id | ||
857 | * | ||
858 | * Restarts autonegotiation for the selected port. | ||
859 | */ | ||
860 | int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) | ||
861 | { | ||
862 | struct fw_port_cmd c; | ||
863 | |||
864 | memset(&c, 0, sizeof(c)); | ||
865 | c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST | | ||
866 | FW_CMD_EXEC | FW_PORT_CMD_PORTID(port)); | ||
867 | c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | | ||
868 | FW_LEN16(c)); | ||
869 | c.u.l1cfg.rcap = htonl(FW_PORT_CAP_ANEG); | ||
870 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | ||
871 | } | ||
872 | |||
873 | /** | ||
874 | * t4_set_vlan_accel - configure HW VLAN extraction | ||
875 | * @adap: the adapter | ||
876 | * @ports: bitmap of adapter ports to operate on | ||
877 | * @on: enable (1) or disable (0) HW VLAN extraction | ||
878 | * | ||
879 | * Enables or disables HW extraction of VLAN tags for the ports specified | ||
880 | * by @ports. @ports is a bitmap with the ith bit designating the port | ||
881 | * associated with the ith adapter channel. | ||
882 | */ | ||
883 | void t4_set_vlan_accel(struct adapter *adap, unsigned int ports, int on) | ||
884 | { | ||
885 | ports <<= VLANEXTENABLE_SHIFT; | ||
886 | t4_set_reg_field(adap, TP_OUT_CONFIG, ports, on ? ports : 0); | ||
887 | } | ||
888 | |||
889 | struct intr_info { | ||
890 | unsigned int mask; /* bits to check in interrupt status */ | ||
891 | const char *msg; /* message to print or NULL */ | ||
892 | short stat_idx; /* stat counter to increment or -1 */ | ||
893 | unsigned short fatal; /* whether the condition reported is fatal */ | ||
894 | }; | ||
895 | |||
896 | /** | ||
897 | * t4_handle_intr_status - table driven interrupt handler | ||
898 | * @adapter: the adapter that generated the interrupt | ||
899 | * @reg: the interrupt status register to process | ||
900 | * @acts: table of interrupt actions | ||
901 | * | ||
902 | * A table driven interrupt handler that applies a set of masks to an | ||
903 | * interrupt status word and performs the corresponding actions if the | ||
904 | * interrupts described by the mask have occured. The actions include | ||
905 | * optionally emitting a warning or alert message. The table is terminated | ||
906 | * by an entry specifying mask 0. Returns the number of fatal interrupt | ||
907 | * conditions. | ||
908 | */ | ||
909 | static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg, | ||
910 | const struct intr_info *acts) | ||
911 | { | ||
912 | int fatal = 0; | ||
913 | unsigned int mask = 0; | ||
914 | unsigned int status = t4_read_reg(adapter, reg); | ||
915 | |||
916 | for ( ; acts->mask; ++acts) { | ||
917 | if (!(status & acts->mask)) | ||
918 | continue; | ||
919 | if (acts->fatal) { | ||
920 | fatal++; | ||
921 | dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg, | ||
922 | status & acts->mask); | ||
923 | } else if (acts->msg && printk_ratelimit()) | ||
924 | dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg, | ||
925 | status & acts->mask); | ||
926 | mask |= acts->mask; | ||
927 | } | ||
928 | status &= mask; | ||
929 | if (status) /* clear processed interrupts */ | ||
930 | t4_write_reg(adapter, reg, status); | ||
931 | return fatal; | ||
932 | } | ||
933 | |||
934 | /* | ||
935 | * Interrupt handler for the PCIE module. | ||
936 | */ | ||
937 | static void pcie_intr_handler(struct adapter *adapter) | ||
938 | { | ||
939 | static struct intr_info sysbus_intr_info[] = { | ||
940 | { RNPP, "RXNP array parity error", -1, 1 }, | ||
941 | { RPCP, "RXPC array parity error", -1, 1 }, | ||
942 | { RCIP, "RXCIF array parity error", -1, 1 }, | ||
943 | { RCCP, "Rx completions control array parity error", -1, 1 }, | ||
944 | { RFTP, "RXFT array parity error", -1, 1 }, | ||
945 | { 0 } | ||
946 | }; | ||
947 | static struct intr_info pcie_port_intr_info[] = { | ||
948 | { TPCP, "TXPC array parity error", -1, 1 }, | ||
949 | { TNPP, "TXNP array parity error", -1, 1 }, | ||
950 | { TFTP, "TXFT array parity error", -1, 1 }, | ||
951 | { TCAP, "TXCA array parity error", -1, 1 }, | ||
952 | { TCIP, "TXCIF array parity error", -1, 1 }, | ||
953 | { RCAP, "RXCA array parity error", -1, 1 }, | ||
954 | { OTDD, "outbound request TLP discarded", -1, 1 }, | ||
955 | { RDPE, "Rx data parity error", -1, 1 }, | ||
956 | { TDUE, "Tx uncorrectable data error", -1, 1 }, | ||
957 | { 0 } | ||
958 | }; | ||
959 | static struct intr_info pcie_intr_info[] = { | ||
960 | { MSIADDRLPERR, "MSI AddrL parity error", -1, 1 }, | ||
961 | { MSIADDRHPERR, "MSI AddrH parity error", -1, 1 }, | ||
962 | { MSIDATAPERR, "MSI data parity error", -1, 1 }, | ||
963 | { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, | ||
964 | { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, | ||
965 | { MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, | ||
966 | { MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, | ||
967 | { PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 }, | ||
968 | { PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 }, | ||
969 | { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, | ||
970 | { CCNTPERR, "PCI CMD channel count parity error", -1, 1 }, | ||
971 | { CREQPERR, "PCI CMD channel request parity error", -1, 1 }, | ||
972 | { CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, | ||
973 | { DCNTPERR, "PCI DMA channel count parity error", -1, 1 }, | ||
974 | { DREQPERR, "PCI DMA channel request parity error", -1, 1 }, | ||
975 | { DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, | ||
976 | { HCNTPERR, "PCI HMA channel count parity error", -1, 1 }, | ||
977 | { HREQPERR, "PCI HMA channel request parity error", -1, 1 }, | ||
978 | { HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, | ||
979 | { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, | ||
980 | { FIDPERR, "PCI FID parity error", -1, 1 }, | ||
981 | { INTXCLRPERR, "PCI INTx clear parity error", -1, 1 }, | ||
982 | { MATAGPERR, "PCI MA tag parity error", -1, 1 }, | ||
983 | { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, | ||
984 | { RXCPLPERR, "PCI Rx completion parity error", -1, 1 }, | ||
985 | { RXWRPERR, "PCI Rx write parity error", -1, 1 }, | ||
986 | { RPLPERR, "PCI replay buffer parity error", -1, 1 }, | ||
987 | { PCIESINT, "PCI core secondary fault", -1, 1 }, | ||
988 | { PCIEPINT, "PCI core primary fault", -1, 1 }, | ||
989 | { UNXSPLCPLERR, "PCI unexpected split completion error", -1, 0 }, | ||
990 | { 0 } | ||
991 | }; | ||
992 | |||
993 | int fat; | ||
994 | |||
995 | fat = t4_handle_intr_status(adapter, | ||
996 | PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, | ||
997 | sysbus_intr_info) + | ||
998 | t4_handle_intr_status(adapter, | ||
999 | PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, | ||
1000 | pcie_port_intr_info) + | ||
1001 | t4_handle_intr_status(adapter, PCIE_INT_CAUSE, pcie_intr_info); | ||
1002 | if (fat) | ||
1003 | t4_fatal_err(adapter); | ||
1004 | } | ||
1005 | |||
1006 | /* | ||
1007 | * TP interrupt handler. | ||
1008 | */ | ||
1009 | static void tp_intr_handler(struct adapter *adapter) | ||
1010 | { | ||
1011 | static struct intr_info tp_intr_info[] = { | ||
1012 | { 0x3fffffff, "TP parity error", -1, 1 }, | ||
1013 | { FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, | ||
1014 | { 0 } | ||
1015 | }; | ||
1016 | |||
1017 | if (t4_handle_intr_status(adapter, TP_INT_CAUSE, tp_intr_info)) | ||
1018 | t4_fatal_err(adapter); | ||
1019 | } | ||
1020 | |||
1021 | /* | ||
1022 | * SGE interrupt handler. | ||
1023 | */ | ||
1024 | static void sge_intr_handler(struct adapter *adapter) | ||
1025 | { | ||
1026 | u64 v; | ||
1027 | |||
1028 | static struct intr_info sge_intr_info[] = { | ||
1029 | { ERR_CPL_EXCEED_IQE_SIZE, | ||
1030 | "SGE received CPL exceeding IQE size", -1, 1 }, | ||
1031 | { ERR_INVALID_CIDX_INC, | ||
1032 | "SGE GTS CIDX increment too large", -1, 0 }, | ||
1033 | { ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 }, | ||
1034 | { ERR_DROPPED_DB, "SGE doorbell dropped", -1, 0 }, | ||
1035 | { ERR_DATA_CPL_ON_HIGH_QID1 | ERR_DATA_CPL_ON_HIGH_QID0, | ||
1036 | "SGE IQID > 1023 received CPL for FL", -1, 0 }, | ||
1037 | { ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1, | ||
1038 | 0 }, | ||
1039 | { ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1, | ||
1040 | 0 }, | ||
1041 | { ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1, | ||
1042 | 0 }, | ||
1043 | { ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1, | ||
1044 | 0 }, | ||
1045 | { ERR_ING_CTXT_PRIO, | ||
1046 | "SGE too many priority ingress contexts", -1, 0 }, | ||
1047 | { ERR_EGR_CTXT_PRIO, | ||
1048 | "SGE too many priority egress contexts", -1, 0 }, | ||
1049 | { INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 }, | ||
1050 | { EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 }, | ||
1051 | { 0 } | ||
1052 | }; | ||
1053 | |||
1054 | v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1) | | ||
1055 | ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2) << 32); | ||
1056 | if (v) { | ||
1057 | dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n", | ||
1058 | (unsigned long long)v); | ||
1059 | t4_write_reg(adapter, SGE_INT_CAUSE1, v); | ||
1060 | t4_write_reg(adapter, SGE_INT_CAUSE2, v >> 32); | ||
1061 | } | ||
1062 | |||
1063 | if (t4_handle_intr_status(adapter, SGE_INT_CAUSE3, sge_intr_info) || | ||
1064 | v != 0) | ||
1065 | t4_fatal_err(adapter); | ||
1066 | } | ||
1067 | |||
1068 | /* | ||
1069 | * CIM interrupt handler. | ||
1070 | */ | ||
1071 | static void cim_intr_handler(struct adapter *adapter) | ||
1072 | { | ||
1073 | static struct intr_info cim_intr_info[] = { | ||
1074 | { PREFDROPINT, "CIM control register prefetch drop", -1, 1 }, | ||
1075 | { OBQPARERR, "CIM OBQ parity error", -1, 1 }, | ||
1076 | { IBQPARERR, "CIM IBQ parity error", -1, 1 }, | ||
1077 | { MBUPPARERR, "CIM mailbox uP parity error", -1, 1 }, | ||
1078 | { MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 }, | ||
1079 | { TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 }, | ||
1080 | { TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 }, | ||
1081 | { 0 } | ||
1082 | }; | ||
1083 | static struct intr_info cim_upintr_info[] = { | ||
1084 | { RSVDSPACEINT, "CIM reserved space access", -1, 1 }, | ||
1085 | { ILLTRANSINT, "CIM illegal transaction", -1, 1 }, | ||
1086 | { ILLWRINT, "CIM illegal write", -1, 1 }, | ||
1087 | { ILLRDINT, "CIM illegal read", -1, 1 }, | ||
1088 | { ILLRDBEINT, "CIM illegal read BE", -1, 1 }, | ||
1089 | { ILLWRBEINT, "CIM illegal write BE", -1, 1 }, | ||
1090 | { SGLRDBOOTINT, "CIM single read from boot space", -1, 1 }, | ||
1091 | { SGLWRBOOTINT, "CIM single write to boot space", -1, 1 }, | ||
1092 | { BLKWRBOOTINT, "CIM block write to boot space", -1, 1 }, | ||
1093 | { SGLRDFLASHINT, "CIM single read from flash space", -1, 1 }, | ||
1094 | { SGLWRFLASHINT, "CIM single write to flash space", -1, 1 }, | ||
1095 | { BLKWRFLASHINT, "CIM block write to flash space", -1, 1 }, | ||
1096 | { SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 }, | ||
1097 | { SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 }, | ||
1098 | { BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 }, | ||
1099 | { BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 }, | ||
1100 | { SGLRDCTLINT , "CIM single read from CTL space", -1, 1 }, | ||
1101 | { SGLWRCTLINT , "CIM single write to CTL space", -1, 1 }, | ||
1102 | { BLKRDCTLINT , "CIM block read from CTL space", -1, 1 }, | ||
1103 | { BLKWRCTLINT , "CIM block write to CTL space", -1, 1 }, | ||
1104 | { SGLRDPLINT , "CIM single read from PL space", -1, 1 }, | ||
1105 | { SGLWRPLINT , "CIM single write to PL space", -1, 1 }, | ||
1106 | { BLKRDPLINT , "CIM block read from PL space", -1, 1 }, | ||
1107 | { BLKWRPLINT , "CIM block write to PL space", -1, 1 }, | ||
1108 | { REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 }, | ||
1109 | { RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 }, | ||
1110 | { TIMEOUTINT , "CIM PIF timeout", -1, 1 }, | ||
1111 | { TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 }, | ||
1112 | { 0 } | ||
1113 | }; | ||
1114 | |||
1115 | int fat; | ||
1116 | |||
1117 | fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE, | ||
1118 | cim_intr_info) + | ||
1119 | t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE, | ||
1120 | cim_upintr_info); | ||
1121 | if (fat) | ||
1122 | t4_fatal_err(adapter); | ||
1123 | } | ||
1124 | |||
1125 | /* | ||
1126 | * ULP RX interrupt handler. | ||
1127 | */ | ||
1128 | static void ulprx_intr_handler(struct adapter *adapter) | ||
1129 | { | ||
1130 | static struct intr_info ulprx_intr_info[] = { | ||
1131 | { 0x7fffff, "ULPRX parity error", -1, 1 }, | ||
1132 | { 0 } | ||
1133 | }; | ||
1134 | |||
1135 | if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE, ulprx_intr_info)) | ||
1136 | t4_fatal_err(adapter); | ||
1137 | } | ||
1138 | |||
1139 | /* | ||
1140 | * ULP TX interrupt handler. | ||
1141 | */ | ||
1142 | static void ulptx_intr_handler(struct adapter *adapter) | ||
1143 | { | ||
1144 | static struct intr_info ulptx_intr_info[] = { | ||
1145 | { PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1, | ||
1146 | 0 }, | ||
1147 | { PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1, | ||
1148 | 0 }, | ||
1149 | { PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1, | ||
1150 | 0 }, | ||
1151 | { PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1, | ||
1152 | 0 }, | ||
1153 | { 0xfffffff, "ULPTX parity error", -1, 1 }, | ||
1154 | { 0 } | ||
1155 | }; | ||
1156 | |||
1157 | if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE, ulptx_intr_info)) | ||
1158 | t4_fatal_err(adapter); | ||
1159 | } | ||
1160 | |||
1161 | /* | ||
1162 | * PM TX interrupt handler. | ||
1163 | */ | ||
1164 | static void pmtx_intr_handler(struct adapter *adapter) | ||
1165 | { | ||
1166 | static struct intr_info pmtx_intr_info[] = { | ||
1167 | { PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 }, | ||
1168 | { PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 }, | ||
1169 | { PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 }, | ||
1170 | { ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 }, | ||
1171 | { PMTX_FRAMING_ERROR, "PMTX framing error", -1, 1 }, | ||
1172 | { OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 }, | ||
1173 | { DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 1 }, | ||
1174 | { ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 }, | ||
1175 | { C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1}, | ||
1176 | { 0 } | ||
1177 | }; | ||
1178 | |||
1179 | if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE, pmtx_intr_info)) | ||
1180 | t4_fatal_err(adapter); | ||
1181 | } | ||
1182 | |||
1183 | /* | ||
1184 | * PM RX interrupt handler. | ||
1185 | */ | ||
1186 | static void pmrx_intr_handler(struct adapter *adapter) | ||
1187 | { | ||
1188 | static struct intr_info pmrx_intr_info[] = { | ||
1189 | { ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 }, | ||
1190 | { PMRX_FRAMING_ERROR, "PMRX framing error", -1, 1 }, | ||
1191 | { OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 }, | ||
1192 | { DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 1 }, | ||
1193 | { IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 }, | ||
1194 | { E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1}, | ||
1195 | { 0 } | ||
1196 | }; | ||
1197 | |||
1198 | if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE, pmrx_intr_info)) | ||
1199 | t4_fatal_err(adapter); | ||
1200 | } | ||
1201 | |||
1202 | /* | ||
1203 | * CPL switch interrupt handler. | ||
1204 | */ | ||
1205 | static void cplsw_intr_handler(struct adapter *adapter) | ||
1206 | { | ||
1207 | static struct intr_info cplsw_intr_info[] = { | ||
1208 | { CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 }, | ||
1209 | { CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 }, | ||
1210 | { TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 }, | ||
1211 | { SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 }, | ||
1212 | { CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 }, | ||
1213 | { ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 }, | ||
1214 | { 0 } | ||
1215 | }; | ||
1216 | |||
1217 | if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE, cplsw_intr_info)) | ||
1218 | t4_fatal_err(adapter); | ||
1219 | } | ||
1220 | |||
1221 | /* | ||
1222 | * LE interrupt handler. | ||
1223 | */ | ||
1224 | static void le_intr_handler(struct adapter *adap) | ||
1225 | { | ||
1226 | static struct intr_info le_intr_info[] = { | ||
1227 | { LIPMISS, "LE LIP miss", -1, 0 }, | ||
1228 | { LIP0, "LE 0 LIP error", -1, 0 }, | ||
1229 | { PARITYERR, "LE parity error", -1, 1 }, | ||
1230 | { UNKNOWNCMD, "LE unknown command", -1, 1 }, | ||
1231 | { REQQPARERR, "LE request queue parity error", -1, 1 }, | ||
1232 | { 0 } | ||
1233 | }; | ||
1234 | |||
1235 | if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE, le_intr_info)) | ||
1236 | t4_fatal_err(adap); | ||
1237 | } | ||
1238 | |||
1239 | /* | ||
1240 | * MPS interrupt handler. | ||
1241 | */ | ||
1242 | static void mps_intr_handler(struct adapter *adapter) | ||
1243 | { | ||
1244 | static struct intr_info mps_rx_intr_info[] = { | ||
1245 | { 0xffffff, "MPS Rx parity error", -1, 1 }, | ||
1246 | { 0 } | ||
1247 | }; | ||
1248 | static struct intr_info mps_tx_intr_info[] = { | ||
1249 | { TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 }, | ||
1250 | { NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 }, | ||
1251 | { TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 }, | ||
1252 | { TXDESCFIFO, "MPS Tx desc FIFO parity error", -1, 1 }, | ||
1253 | { BUBBLE, "MPS Tx underflow", -1, 1 }, | ||
1254 | { SECNTERR, "MPS Tx SOP/EOP error", -1, 1 }, | ||
1255 | { FRMERR, "MPS Tx framing error", -1, 1 }, | ||
1256 | { 0 } | ||
1257 | }; | ||
1258 | static struct intr_info mps_trc_intr_info[] = { | ||
1259 | { FILTMEM, "MPS TRC filter parity error", -1, 1 }, | ||
1260 | { PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 }, | ||
1261 | { MISCPERR, "MPS TRC misc parity error", -1, 1 }, | ||
1262 | { 0 } | ||
1263 | }; | ||
1264 | static struct intr_info mps_stat_sram_intr_info[] = { | ||
1265 | { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, | ||
1266 | { 0 } | ||
1267 | }; | ||
1268 | static struct intr_info mps_stat_tx_intr_info[] = { | ||
1269 | { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, | ||
1270 | { 0 } | ||
1271 | }; | ||
1272 | static struct intr_info mps_stat_rx_intr_info[] = { | ||
1273 | { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, | ||
1274 | { 0 } | ||
1275 | }; | ||
1276 | static struct intr_info mps_cls_intr_info[] = { | ||
1277 | { MATCHSRAM, "MPS match SRAM parity error", -1, 1 }, | ||
1278 | { MATCHTCAM, "MPS match TCAM parity error", -1, 1 }, | ||
1279 | { HASHSRAM, "MPS hash SRAM parity error", -1, 1 }, | ||
1280 | { 0 } | ||
1281 | }; | ||
1282 | |||
1283 | int fat; | ||
1284 | |||
1285 | fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE, | ||
1286 | mps_rx_intr_info) + | ||
1287 | t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE, | ||
1288 | mps_tx_intr_info) + | ||
1289 | t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE, | ||
1290 | mps_trc_intr_info) + | ||
1291 | t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM, | ||
1292 | mps_stat_sram_intr_info) + | ||
1293 | t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO, | ||
1294 | mps_stat_tx_intr_info) + | ||
1295 | t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO, | ||
1296 | mps_stat_rx_intr_info) + | ||
1297 | t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE, | ||
1298 | mps_cls_intr_info); | ||
1299 | |||
1300 | t4_write_reg(adapter, MPS_INT_CAUSE, CLSINT | TRCINT | | ||
1301 | RXINT | TXINT | STATINT); | ||
1302 | t4_read_reg(adapter, MPS_INT_CAUSE); /* flush */ | ||
1303 | if (fat) | ||
1304 | t4_fatal_err(adapter); | ||
1305 | } | ||
1306 | |||
1307 | #define MEM_INT_MASK (PERR_INT_CAUSE | ECC_CE_INT_CAUSE | ECC_UE_INT_CAUSE) | ||
1308 | |||
1309 | /* | ||
1310 | * EDC/MC interrupt handler. | ||
1311 | */ | ||
1312 | static void mem_intr_handler(struct adapter *adapter, int idx) | ||
1313 | { | ||
1314 | static const char name[3][5] = { "EDC0", "EDC1", "MC" }; | ||
1315 | |||
1316 | unsigned int addr, cnt_addr, v; | ||
1317 | |||
1318 | if (idx <= MEM_EDC1) { | ||
1319 | addr = EDC_REG(EDC_INT_CAUSE, idx); | ||
1320 | cnt_addr = EDC_REG(EDC_ECC_STATUS, idx); | ||
1321 | } else { | ||
1322 | addr = MC_INT_CAUSE; | ||
1323 | cnt_addr = MC_ECC_STATUS; | ||
1324 | } | ||
1325 | |||
1326 | v = t4_read_reg(adapter, addr) & MEM_INT_MASK; | ||
1327 | if (v & PERR_INT_CAUSE) | ||
1328 | dev_alert(adapter->pdev_dev, "%s FIFO parity error\n", | ||
1329 | name[idx]); | ||
1330 | if (v & ECC_CE_INT_CAUSE) { | ||
1331 | u32 cnt = ECC_CECNT_GET(t4_read_reg(adapter, cnt_addr)); | ||
1332 | |||
1333 | t4_write_reg(adapter, cnt_addr, ECC_CECNT_MASK); | ||
1334 | if (printk_ratelimit()) | ||
1335 | dev_warn(adapter->pdev_dev, | ||
1336 | "%u %s correctable ECC data error%s\n", | ||
1337 | cnt, name[idx], cnt > 1 ? "s" : ""); | ||
1338 | } | ||
1339 | if (v & ECC_UE_INT_CAUSE) | ||
1340 | dev_alert(adapter->pdev_dev, | ||
1341 | "%s uncorrectable ECC data error\n", name[idx]); | ||
1342 | |||
1343 | t4_write_reg(adapter, addr, v); | ||
1344 | if (v & (PERR_INT_CAUSE | ECC_UE_INT_CAUSE)) | ||
1345 | t4_fatal_err(adapter); | ||
1346 | } | ||
1347 | |||
1348 | /* | ||
1349 | * MA interrupt handler. | ||
1350 | */ | ||
1351 | static void ma_intr_handler(struct adapter *adap) | ||
1352 | { | ||
1353 | u32 v, status = t4_read_reg(adap, MA_INT_CAUSE); | ||
1354 | |||
1355 | if (status & MEM_PERR_INT_CAUSE) | ||
1356 | dev_alert(adap->pdev_dev, | ||
1357 | "MA parity error, parity status %#x\n", | ||
1358 | t4_read_reg(adap, MA_PARITY_ERROR_STATUS)); | ||
1359 | if (status & MEM_WRAP_INT_CAUSE) { | ||
1360 | v = t4_read_reg(adap, MA_INT_WRAP_STATUS); | ||
1361 | dev_alert(adap->pdev_dev, "MA address wrap-around error by " | ||
1362 | "client %u to address %#x\n", | ||
1363 | MEM_WRAP_CLIENT_NUM_GET(v), | ||
1364 | MEM_WRAP_ADDRESS_GET(v) << 4); | ||
1365 | } | ||
1366 | t4_write_reg(adap, MA_INT_CAUSE, status); | ||
1367 | t4_fatal_err(adap); | ||
1368 | } | ||
1369 | |||
1370 | /* | ||
1371 | * SMB interrupt handler. | ||
1372 | */ | ||
1373 | static void smb_intr_handler(struct adapter *adap) | ||
1374 | { | ||
1375 | static struct intr_info smb_intr_info[] = { | ||
1376 | { MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 }, | ||
1377 | { MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 }, | ||
1378 | { SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 }, | ||
1379 | { 0 } | ||
1380 | }; | ||
1381 | |||
1382 | if (t4_handle_intr_status(adap, SMB_INT_CAUSE, smb_intr_info)) | ||
1383 | t4_fatal_err(adap); | ||
1384 | } | ||
1385 | |||
1386 | /* | ||
1387 | * NC-SI interrupt handler. | ||
1388 | */ | ||
1389 | static void ncsi_intr_handler(struct adapter *adap) | ||
1390 | { | ||
1391 | static struct intr_info ncsi_intr_info[] = { | ||
1392 | { CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 }, | ||
1393 | { MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 }, | ||
1394 | { TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 }, | ||
1395 | { RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 }, | ||
1396 | { 0 } | ||
1397 | }; | ||
1398 | |||
1399 | if (t4_handle_intr_status(adap, NCSI_INT_CAUSE, ncsi_intr_info)) | ||
1400 | t4_fatal_err(adap); | ||
1401 | } | ||
1402 | |||
1403 | /* | ||
1404 | * XGMAC interrupt handler. | ||
1405 | */ | ||
1406 | static void xgmac_intr_handler(struct adapter *adap, int port) | ||
1407 | { | ||
1408 | u32 v = t4_read_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE)); | ||
1409 | |||
1410 | v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR; | ||
1411 | if (!v) | ||
1412 | return; | ||
1413 | |||
1414 | if (v & TXFIFO_PRTY_ERR) | ||
1415 | dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n", | ||
1416 | port); | ||
1417 | if (v & RXFIFO_PRTY_ERR) | ||
1418 | dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n", | ||
1419 | port); | ||
1420 | t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE), v); | ||
1421 | t4_fatal_err(adap); | ||
1422 | } | ||
1423 | |||
1424 | /* | ||
1425 | * PL interrupt handler. | ||
1426 | */ | ||
1427 | static void pl_intr_handler(struct adapter *adap) | ||
1428 | { | ||
1429 | static struct intr_info pl_intr_info[] = { | ||
1430 | { FATALPERR, "T4 fatal parity error", -1, 1 }, | ||
1431 | { PERRVFID, "PL VFID_MAP parity error", -1, 1 }, | ||
1432 | { 0 } | ||
1433 | }; | ||
1434 | |||
1435 | if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE, pl_intr_info)) | ||
1436 | t4_fatal_err(adap); | ||
1437 | } | ||
1438 | |||
1439 | #define PF_INTR_MASK (PFSW | PFCIM) | ||
1440 | #define GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \ | ||
1441 | EDC1 | LE | TP | MA | PM_TX | PM_RX | ULP_RX | \ | ||
1442 | CPL_SWITCH | SGE | ULP_TX) | ||
1443 | |||
1444 | /** | ||
1445 | * t4_slow_intr_handler - control path interrupt handler | ||
1446 | * @adapter: the adapter | ||
1447 | * | ||
1448 | * T4 interrupt handler for non-data global interrupt events, e.g., errors. | ||
1449 | * The designation 'slow' is because it involves register reads, while | ||
1450 | * data interrupts typically don't involve any MMIOs. | ||
1451 | */ | ||
1452 | int t4_slow_intr_handler(struct adapter *adapter) | ||
1453 | { | ||
1454 | u32 cause = t4_read_reg(adapter, PL_INT_CAUSE); | ||
1455 | |||
1456 | if (!(cause & GLBL_INTR_MASK)) | ||
1457 | return 0; | ||
1458 | if (cause & CIM) | ||
1459 | cim_intr_handler(adapter); | ||
1460 | if (cause & MPS) | ||
1461 | mps_intr_handler(adapter); | ||
1462 | if (cause & NCSI) | ||
1463 | ncsi_intr_handler(adapter); | ||
1464 | if (cause & PL) | ||
1465 | pl_intr_handler(adapter); | ||
1466 | if (cause & SMB) | ||
1467 | smb_intr_handler(adapter); | ||
1468 | if (cause & XGMAC0) | ||
1469 | xgmac_intr_handler(adapter, 0); | ||
1470 | if (cause & XGMAC1) | ||
1471 | xgmac_intr_handler(adapter, 1); | ||
1472 | if (cause & XGMAC_KR0) | ||
1473 | xgmac_intr_handler(adapter, 2); | ||
1474 | if (cause & XGMAC_KR1) | ||
1475 | xgmac_intr_handler(adapter, 3); | ||
1476 | if (cause & PCIE) | ||
1477 | pcie_intr_handler(adapter); | ||
1478 | if (cause & MC) | ||
1479 | mem_intr_handler(adapter, MEM_MC); | ||
1480 | if (cause & EDC0) | ||
1481 | mem_intr_handler(adapter, MEM_EDC0); | ||
1482 | if (cause & EDC1) | ||
1483 | mem_intr_handler(adapter, MEM_EDC1); | ||
1484 | if (cause & LE) | ||
1485 | le_intr_handler(adapter); | ||
1486 | if (cause & TP) | ||
1487 | tp_intr_handler(adapter); | ||
1488 | if (cause & MA) | ||
1489 | ma_intr_handler(adapter); | ||
1490 | if (cause & PM_TX) | ||
1491 | pmtx_intr_handler(adapter); | ||
1492 | if (cause & PM_RX) | ||
1493 | pmrx_intr_handler(adapter); | ||
1494 | if (cause & ULP_RX) | ||
1495 | ulprx_intr_handler(adapter); | ||
1496 | if (cause & CPL_SWITCH) | ||
1497 | cplsw_intr_handler(adapter); | ||
1498 | if (cause & SGE) | ||
1499 | sge_intr_handler(adapter); | ||
1500 | if (cause & ULP_TX) | ||
1501 | ulptx_intr_handler(adapter); | ||
1502 | |||
1503 | /* Clear the interrupts just processed for which we are the master. */ | ||
1504 | t4_write_reg(adapter, PL_INT_CAUSE, cause & GLBL_INTR_MASK); | ||
1505 | (void) t4_read_reg(adapter, PL_INT_CAUSE); /* flush */ | ||
1506 | return 1; | ||
1507 | } | ||
1508 | |||
1509 | /** | ||
1510 | * t4_intr_enable - enable interrupts | ||
1511 | * @adapter: the adapter whose interrupts should be enabled | ||
1512 | * | ||
1513 | * Enable PF-specific interrupts for the calling function and the top-level | ||
1514 | * interrupt concentrator for global interrupts. Interrupts are already | ||
1515 | * enabled at each module, here we just enable the roots of the interrupt | ||
1516 | * hierarchies. | ||
1517 | * | ||
1518 | * Note: this function should be called only when the driver manages | ||
1519 | * non PF-specific interrupts from the various HW modules. Only one PCI | ||
1520 | * function at a time should be doing this. | ||
1521 | */ | ||
1522 | void t4_intr_enable(struct adapter *adapter) | ||
1523 | { | ||
1524 | u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI)); | ||
1525 | |||
1526 | t4_write_reg(adapter, SGE_INT_ENABLE3, ERR_CPL_EXCEED_IQE_SIZE | | ||
1527 | ERR_INVALID_CIDX_INC | ERR_CPL_OPCODE_0 | | ||
1528 | ERR_DROPPED_DB | ERR_DATA_CPL_ON_HIGH_QID1 | | ||
1529 | ERR_DATA_CPL_ON_HIGH_QID0 | ERR_BAD_DB_PIDX3 | | ||
1530 | ERR_BAD_DB_PIDX2 | ERR_BAD_DB_PIDX1 | | ||
1531 | ERR_BAD_DB_PIDX0 | ERR_ING_CTXT_PRIO | | ||
1532 | ERR_EGR_CTXT_PRIO | INGRESS_SIZE_ERR | | ||
1533 | EGRESS_SIZE_ERR); | ||
1534 | t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), PF_INTR_MASK); | ||
1535 | t4_set_reg_field(adapter, PL_INT_MAP0, 0, 1 << pf); | ||
1536 | } | ||
1537 | |||
1538 | /** | ||
1539 | * t4_intr_disable - disable interrupts | ||
1540 | * @adapter: the adapter whose interrupts should be disabled | ||
1541 | * | ||
1542 | * Disable interrupts. We only disable the top-level interrupt | ||
1543 | * concentrators. The caller must be a PCI function managing global | ||
1544 | * interrupts. | ||
1545 | */ | ||
1546 | void t4_intr_disable(struct adapter *adapter) | ||
1547 | { | ||
1548 | u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI)); | ||
1549 | |||
1550 | t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), 0); | ||
1551 | t4_set_reg_field(adapter, PL_INT_MAP0, 1 << pf, 0); | ||
1552 | } | ||
1553 | |||
1554 | /** | ||
1555 | * t4_intr_clear - clear all interrupts | ||
1556 | * @adapter: the adapter whose interrupts should be cleared | ||
1557 | * | ||
1558 | * Clears all interrupts. The caller must be a PCI function managing | ||
1559 | * global interrupts. | ||
1560 | */ | ||
1561 | void t4_intr_clear(struct adapter *adapter) | ||
1562 | { | ||
1563 | static const unsigned int cause_reg[] = { | ||
1564 | SGE_INT_CAUSE1, SGE_INT_CAUSE2, SGE_INT_CAUSE3, | ||
1565 | PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, | ||
1566 | PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, | ||
1567 | PCIE_NONFAT_ERR, PCIE_INT_CAUSE, | ||
1568 | MC_INT_CAUSE, | ||
1569 | MA_INT_WRAP_STATUS, MA_PARITY_ERROR_STATUS, MA_INT_CAUSE, | ||
1570 | EDC_INT_CAUSE, EDC_REG(EDC_INT_CAUSE, 1), | ||
1571 | CIM_HOST_INT_CAUSE, CIM_HOST_UPACC_INT_CAUSE, | ||
1572 | MYPF_REG(CIM_PF_HOST_INT_CAUSE), | ||
1573 | TP_INT_CAUSE, | ||
1574 | ULP_RX_INT_CAUSE, ULP_TX_INT_CAUSE, | ||
1575 | PM_RX_INT_CAUSE, PM_TX_INT_CAUSE, | ||
1576 | MPS_RX_PERR_INT_CAUSE, | ||
1577 | CPL_INTR_CAUSE, | ||
1578 | MYPF_REG(PL_PF_INT_CAUSE), | ||
1579 | PL_PL_INT_CAUSE, | ||
1580 | LE_DB_INT_CAUSE, | ||
1581 | }; | ||
1582 | |||
1583 | unsigned int i; | ||
1584 | |||
1585 | for (i = 0; i < ARRAY_SIZE(cause_reg); ++i) | ||
1586 | t4_write_reg(adapter, cause_reg[i], 0xffffffff); | ||
1587 | |||
1588 | t4_write_reg(adapter, PL_INT_CAUSE, GLBL_INTR_MASK); | ||
1589 | (void) t4_read_reg(adapter, PL_INT_CAUSE); /* flush */ | ||
1590 | } | ||
1591 | |||
1592 | /** | ||
1593 | * hash_mac_addr - return the hash value of a MAC address | ||
1594 | * @addr: the 48-bit Ethernet MAC address | ||
1595 | * | ||
1596 | * Hashes a MAC address according to the hash function used by HW inexact | ||
1597 | * (hash) address matching. | ||
1598 | */ | ||
1599 | static int hash_mac_addr(const u8 *addr) | ||
1600 | { | ||
1601 | u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; | ||
1602 | u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; | ||
1603 | a ^= b; | ||
1604 | a ^= (a >> 12); | ||
1605 | a ^= (a >> 6); | ||
1606 | return a & 0x3f; | ||
1607 | } | ||
1608 | |||
1609 | /** | ||
1610 | * t4_config_rss_range - configure a portion of the RSS mapping table | ||
1611 | * @adapter: the adapter | ||
1612 | * @mbox: mbox to use for the FW command | ||
1613 | * @viid: virtual interface whose RSS subtable is to be written | ||
1614 | * @start: start entry in the table to write | ||
1615 | * @n: how many table entries to write | ||
1616 | * @rspq: values for the response queue lookup table | ||
1617 | * @nrspq: number of values in @rspq | ||
1618 | * | ||
1619 | * Programs the selected part of the VI's RSS mapping table with the | ||
1620 | * provided values. If @nrspq < @n the supplied values are used repeatedly | ||
1621 | * until the full table range is populated. | ||
1622 | * | ||
1623 | * The caller must ensure the values in @rspq are in the range allowed for | ||
1624 | * @viid. | ||
1625 | */ | ||
1626 | int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, | ||
1627 | int start, int n, const u16 *rspq, unsigned int nrspq) | ||
1628 | { | ||
1629 | int ret; | ||
1630 | const u16 *rsp = rspq; | ||
1631 | const u16 *rsp_end = rspq + nrspq; | ||
1632 | struct fw_rss_ind_tbl_cmd cmd; | ||
1633 | |||
1634 | memset(&cmd, 0, sizeof(cmd)); | ||
1635 | cmd.op_to_viid = htonl(FW_CMD_OP(FW_RSS_IND_TBL_CMD) | | ||
1636 | FW_CMD_REQUEST | FW_CMD_WRITE | | ||
1637 | FW_RSS_IND_TBL_CMD_VIID(viid)); | ||
1638 | cmd.retval_len16 = htonl(FW_LEN16(cmd)); | ||
1639 | |||
1640 | /* each fw_rss_ind_tbl_cmd takes up to 32 entries */ | ||
1641 | while (n > 0) { | ||
1642 | int nq = min(n, 32); | ||
1643 | __be32 *qp = &cmd.iq0_to_iq2; | ||
1644 | |||
1645 | cmd.niqid = htons(nq); | ||
1646 | cmd.startidx = htons(start); | ||
1647 | |||
1648 | start += nq; | ||
1649 | n -= nq; | ||
1650 | |||
1651 | while (nq > 0) { | ||
1652 | unsigned int v; | ||
1653 | |||
1654 | v = FW_RSS_IND_TBL_CMD_IQ0(*rsp); | ||
1655 | if (++rsp >= rsp_end) | ||
1656 | rsp = rspq; | ||
1657 | v |= FW_RSS_IND_TBL_CMD_IQ1(*rsp); | ||
1658 | if (++rsp >= rsp_end) | ||
1659 | rsp = rspq; | ||
1660 | v |= FW_RSS_IND_TBL_CMD_IQ2(*rsp); | ||
1661 | if (++rsp >= rsp_end) | ||
1662 | rsp = rspq; | ||
1663 | |||
1664 | *qp++ = htonl(v); | ||
1665 | nq -= 3; | ||
1666 | } | ||
1667 | |||
1668 | ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); | ||
1669 | if (ret) | ||
1670 | return ret; | ||
1671 | } | ||
1672 | return 0; | ||
1673 | } | ||
1674 | |||
1675 | /** | ||
1676 | * t4_config_glbl_rss - configure the global RSS mode | ||
1677 | * @adapter: the adapter | ||
1678 | * @mbox: mbox to use for the FW command | ||
1679 | * @mode: global RSS mode | ||
1680 | * @flags: mode-specific flags | ||
1681 | * | ||
1682 | * Sets the global RSS mode. | ||
1683 | */ | ||
1684 | int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, | ||
1685 | unsigned int flags) | ||
1686 | { | ||
1687 | struct fw_rss_glb_config_cmd c; | ||
1688 | |||
1689 | memset(&c, 0, sizeof(c)); | ||
1690 | c.op_to_write = htonl(FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | | ||
1691 | FW_CMD_REQUEST | FW_CMD_WRITE); | ||
1692 | c.retval_len16 = htonl(FW_LEN16(c)); | ||
1693 | if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { | ||
1694 | c.u.manual.mode_pkd = htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode)); | ||
1695 | } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { | ||
1696 | c.u.basicvirtual.mode_pkd = | ||
1697 | htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode)); | ||
1698 | c.u.basicvirtual.synmapen_to_hashtoeplitz = htonl(flags); | ||
1699 | } else | ||
1700 | return -EINVAL; | ||
1701 | return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); | ||
1702 | } | ||
1703 | |||
1704 | /* Read an RSS table row */ | ||
1705 | static int rd_rss_row(struct adapter *adap, int row, u32 *val) | ||
1706 | { | ||
1707 | t4_write_reg(adap, TP_RSS_LKP_TABLE, 0xfff00000 | row); | ||
1708 | return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE, LKPTBLROWVLD, 1, | ||
1709 | 5, 0, val); | ||
1710 | } | ||
1711 | |||
1712 | /** | ||
1713 | * t4_read_rss - read the contents of the RSS mapping table | ||
1714 | * @adapter: the adapter | ||
1715 | * @map: holds the contents of the RSS mapping table | ||
1716 | * | ||
1717 | * Reads the contents of the RSS hash->queue mapping table. | ||
1718 | */ | ||
1719 | int t4_read_rss(struct adapter *adapter, u16 *map) | ||
1720 | { | ||
1721 | u32 val; | ||
1722 | int i, ret; | ||
1723 | |||
1724 | for (i = 0; i < RSS_NENTRIES / 2; ++i) { | ||
1725 | ret = rd_rss_row(adapter, i, &val); | ||
1726 | if (ret) | ||
1727 | return ret; | ||
1728 | *map++ = LKPTBLQUEUE0_GET(val); | ||
1729 | *map++ = LKPTBLQUEUE1_GET(val); | ||
1730 | } | ||
1731 | return 0; | ||
1732 | } | ||
1733 | |||
1734 | /** | ||
1735 | * t4_tp_get_tcp_stats - read TP's TCP MIB counters | ||
1736 | * @adap: the adapter | ||
1737 | * @v4: holds the TCP/IP counter values | ||
1738 | * @v6: holds the TCP/IPv6 counter values | ||
1739 | * | ||
1740 | * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. | ||
1741 | * Either @v4 or @v6 may be %NULL to skip the corresponding stats. | ||
1742 | */ | ||
1743 | void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, | ||
1744 | struct tp_tcp_stats *v6) | ||
1745 | { | ||
1746 | u32 val[TP_MIB_TCP_RXT_SEG_LO - TP_MIB_TCP_OUT_RST + 1]; | ||
1747 | |||
1748 | #define STAT_IDX(x) ((TP_MIB_TCP_##x) - TP_MIB_TCP_OUT_RST) | ||
1749 | #define STAT(x) val[STAT_IDX(x)] | ||
1750 | #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) | ||
1751 | |||
1752 | if (v4) { | ||
1753 | t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val, | ||
1754 | ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST); | ||
1755 | v4->tcpOutRsts = STAT(OUT_RST); | ||
1756 | v4->tcpInSegs = STAT64(IN_SEG); | ||
1757 | v4->tcpOutSegs = STAT64(OUT_SEG); | ||
1758 | v4->tcpRetransSegs = STAT64(RXT_SEG); | ||
1759 | } | ||
1760 | if (v6) { | ||
1761 | t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val, | ||
1762 | ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST); | ||
1763 | v6->tcpOutRsts = STAT(OUT_RST); | ||
1764 | v6->tcpInSegs = STAT64(IN_SEG); | ||
1765 | v6->tcpOutSegs = STAT64(OUT_SEG); | ||
1766 | v6->tcpRetransSegs = STAT64(RXT_SEG); | ||
1767 | } | ||
1768 | #undef STAT64 | ||
1769 | #undef STAT | ||
1770 | #undef STAT_IDX | ||
1771 | } | ||
1772 | |||
1773 | /** | ||
1774 | * t4_tp_get_err_stats - read TP's error MIB counters | ||
1775 | * @adap: the adapter | ||
1776 | * @st: holds the counter values | ||
1777 | * | ||
1778 | * Returns the values of TP's error counters. | ||
1779 | */ | ||
1780 | void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st) | ||
1781 | { | ||
1782 | t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, st->macInErrs, | ||
1783 | 12, TP_MIB_MAC_IN_ERR_0); | ||
1784 | t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, st->tnlCongDrops, | ||
1785 | 8, TP_MIB_TNL_CNG_DROP_0); | ||
1786 | t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, st->tnlTxDrops, | ||
1787 | 4, TP_MIB_TNL_DROP_0); | ||
1788 | t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, st->ofldVlanDrops, | ||
1789 | 4, TP_MIB_OFD_VLN_DROP_0); | ||
1790 | t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, st->tcp6InErrs, | ||
1791 | 4, TP_MIB_TCP_V6IN_ERR_0); | ||
1792 | t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, &st->ofldNoNeigh, | ||
1793 | 2, TP_MIB_OFD_ARP_DROP); | ||
1794 | } | ||
1795 | |||
1796 | /** | ||
1797 | * t4_read_mtu_tbl - returns the values in the HW path MTU table | ||
1798 | * @adap: the adapter | ||
1799 | * @mtus: where to store the MTU values | ||
1800 | * @mtu_log: where to store the MTU base-2 log (may be %NULL) | ||
1801 | * | ||
1802 | * Reads the HW path MTU table. | ||
1803 | */ | ||
1804 | void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) | ||
1805 | { | ||
1806 | u32 v; | ||
1807 | int i; | ||
1808 | |||
1809 | for (i = 0; i < NMTUS; ++i) { | ||
1810 | t4_write_reg(adap, TP_MTU_TABLE, | ||
1811 | MTUINDEX(0xff) | MTUVALUE(i)); | ||
1812 | v = t4_read_reg(adap, TP_MTU_TABLE); | ||
1813 | mtus[i] = MTUVALUE_GET(v); | ||
1814 | if (mtu_log) | ||
1815 | mtu_log[i] = MTUWIDTH_GET(v); | ||
1816 | } | ||
1817 | } | ||
1818 | |||
1819 | /** | ||
1820 | * init_cong_ctrl - initialize congestion control parameters | ||
1821 | * @a: the alpha values for congestion control | ||
1822 | * @b: the beta values for congestion control | ||
1823 | * | ||
1824 | * Initialize the congestion control parameters. | ||
1825 | */ | ||
1826 | static void __devinit init_cong_ctrl(unsigned short *a, unsigned short *b) | ||
1827 | { | ||
1828 | a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; | ||
1829 | a[9] = 2; | ||
1830 | a[10] = 3; | ||
1831 | a[11] = 4; | ||
1832 | a[12] = 5; | ||
1833 | a[13] = 6; | ||
1834 | a[14] = 7; | ||
1835 | a[15] = 8; | ||
1836 | a[16] = 9; | ||
1837 | a[17] = 10; | ||
1838 | a[18] = 14; | ||
1839 | a[19] = 17; | ||
1840 | a[20] = 21; | ||
1841 | a[21] = 25; | ||
1842 | a[22] = 30; | ||
1843 | a[23] = 35; | ||
1844 | a[24] = 45; | ||
1845 | a[25] = 60; | ||
1846 | a[26] = 80; | ||
1847 | a[27] = 100; | ||
1848 | a[28] = 200; | ||
1849 | a[29] = 300; | ||
1850 | a[30] = 400; | ||
1851 | a[31] = 500; | ||
1852 | |||
1853 | b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; | ||
1854 | b[9] = b[10] = 1; | ||
1855 | b[11] = b[12] = 2; | ||
1856 | b[13] = b[14] = b[15] = b[16] = 3; | ||
1857 | b[17] = b[18] = b[19] = b[20] = b[21] = 4; | ||
1858 | b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; | ||
1859 | b[28] = b[29] = 6; | ||
1860 | b[30] = b[31] = 7; | ||
1861 | } | ||
1862 | |||
1863 | /* The minimum additive increment value for the congestion control table */ | ||
1864 | #define CC_MIN_INCR 2U | ||
1865 | |||
1866 | /** | ||
1867 | * t4_load_mtus - write the MTU and congestion control HW tables | ||
1868 | * @adap: the adapter | ||
1869 | * @mtus: the values for the MTU table | ||
1870 | * @alpha: the values for the congestion control alpha parameter | ||
1871 | * @beta: the values for the congestion control beta parameter | ||
1872 | * | ||
1873 | * Write the HW MTU table with the supplied MTUs and the high-speed | ||
1874 | * congestion control table with the supplied alpha, beta, and MTUs. | ||
1875 | * We write the two tables together because the additive increments | ||
1876 | * depend on the MTUs. | ||
1877 | */ | ||
1878 | void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, | ||
1879 | const unsigned short *alpha, const unsigned short *beta) | ||
1880 | { | ||
1881 | static const unsigned int avg_pkts[NCCTRL_WIN] = { | ||
1882 | 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, | ||
1883 | 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, | ||
1884 | 28672, 40960, 57344, 81920, 114688, 163840, 229376 | ||
1885 | }; | ||
1886 | |||
1887 | unsigned int i, w; | ||
1888 | |||
1889 | for (i = 0; i < NMTUS; ++i) { | ||
1890 | unsigned int mtu = mtus[i]; | ||
1891 | unsigned int log2 = fls(mtu); | ||
1892 | |||
1893 | if (!(mtu & ((1 << log2) >> 2))) /* round */ | ||
1894 | log2--; | ||
1895 | t4_write_reg(adap, TP_MTU_TABLE, MTUINDEX(i) | | ||
1896 | MTUWIDTH(log2) | MTUVALUE(mtu)); | ||
1897 | |||
1898 | for (w = 0; w < NCCTRL_WIN; ++w) { | ||
1899 | unsigned int inc; | ||
1900 | |||
1901 | inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], | ||
1902 | CC_MIN_INCR); | ||
1903 | |||
1904 | t4_write_reg(adap, TP_CCTRL_TABLE, (i << 21) | | ||
1905 | (w << 16) | (beta[w] << 13) | inc); | ||
1906 | } | ||
1907 | } | ||
1908 | } | ||
1909 | |||
1910 | /** | ||
1911 | * t4_set_trace_filter - configure one of the tracing filters | ||
1912 | * @adap: the adapter | ||
1913 | * @tp: the desired trace filter parameters | ||
1914 | * @idx: which filter to configure | ||
1915 | * @enable: whether to enable or disable the filter | ||
1916 | * | ||
1917 | * Configures one of the tracing filters available in HW. If @enable is | ||
1918 | * %0 @tp is not examined and may be %NULL. | ||
1919 | */ | ||
1920 | int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, | ||
1921 | int idx, int enable) | ||
1922 | { | ||
1923 | int i, ofst = idx * 4; | ||
1924 | u32 data_reg, mask_reg, cfg; | ||
1925 | u32 multitrc = TRCMULTIFILTER; | ||
1926 | |||
1927 | if (!enable) { | ||
1928 | t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A + ofst, 0); | ||
1929 | goto out; | ||
1930 | } | ||
1931 | |||
1932 | if (tp->port > 11 || tp->invert > 1 || tp->skip_len > 0x1f || | ||
1933 | tp->skip_ofst > 0x1f || tp->min_len > 0x1ff || | ||
1934 | tp->snap_len > 9600 || (idx && tp->snap_len > 256)) | ||
1935 | return -EINVAL; | ||
1936 | |||
1937 | if (tp->snap_len > 256) { /* must be tracer 0 */ | ||
1938 | if ((t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A + 4) | | ||
1939 | t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A + 8) | | ||
1940 | t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A + 12)) & TFEN) | ||
1941 | return -EINVAL; /* other tracers are enabled */ | ||
1942 | multitrc = 0; | ||
1943 | } else if (idx) { | ||
1944 | i = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B); | ||
1945 | if (TFCAPTUREMAX_GET(i) > 256 && | ||
1946 | (t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A) & TFEN)) | ||
1947 | return -EINVAL; | ||
1948 | } | ||
1949 | |||
1950 | /* stop the tracer we'll be changing */ | ||
1951 | t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A + ofst, 0); | ||
1952 | |||
1953 | /* disable tracing globally if running in the wrong single/multi mode */ | ||
1954 | cfg = t4_read_reg(adap, MPS_TRC_CFG); | ||
1955 | if ((cfg & TRCEN) && multitrc != (cfg & TRCMULTIFILTER)) { | ||
1956 | t4_write_reg(adap, MPS_TRC_CFG, cfg ^ TRCEN); | ||
1957 | t4_read_reg(adap, MPS_TRC_CFG); /* flush */ | ||
1958 | msleep(1); | ||
1959 | if (!(t4_read_reg(adap, MPS_TRC_CFG) & TRCFIFOEMPTY)) | ||
1960 | return -ETIMEDOUT; | ||
1961 | } | ||
1962 | /* | ||
1963 | * At this point either the tracing is enabled and in the right mode or | ||
1964 | * disabled. | ||
1965 | */ | ||
1966 | |||
1967 | idx *= (MPS_TRC_FILTER1_MATCH - MPS_TRC_FILTER0_MATCH); | ||
1968 | data_reg = MPS_TRC_FILTER0_MATCH + idx; | ||
1969 | mask_reg = MPS_TRC_FILTER0_DONT_CARE + idx; | ||
1970 | |||
1971 | for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { | ||
1972 | t4_write_reg(adap, data_reg, tp->data[i]); | ||
1973 | t4_write_reg(adap, mask_reg, ~tp->mask[i]); | ||
1974 | } | ||
1975 | t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B + ofst, | ||
1976 | TFCAPTUREMAX(tp->snap_len) | | ||
1977 | TFMINPKTSIZE(tp->min_len)); | ||
1978 | t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A + ofst, | ||
1979 | TFOFFSET(tp->skip_ofst) | TFLENGTH(tp->skip_len) | | ||
1980 | TFPORT(tp->port) | TFEN | | ||
1981 | (tp->invert ? TFINVERTMATCH : 0)); | ||
1982 | |||
1983 | cfg &= ~TRCMULTIFILTER; | ||
1984 | t4_write_reg(adap, MPS_TRC_CFG, cfg | TRCEN | multitrc); | ||
1985 | out: t4_read_reg(adap, MPS_TRC_CFG); /* flush */ | ||
1986 | return 0; | ||
1987 | } | ||
1988 | |||
1989 | /** | ||
1990 | * t4_get_trace_filter - query one of the tracing filters | ||
1991 | * @adap: the adapter | ||
1992 | * @tp: the current trace filter parameters | ||
1993 | * @idx: which trace filter to query | ||
1994 | * @enabled: non-zero if the filter is enabled | ||
1995 | * | ||
1996 | * Returns the current settings of one of the HW tracing filters. | ||
1997 | */ | ||
1998 | void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, | ||
1999 | int *enabled) | ||
2000 | { | ||
2001 | u32 ctla, ctlb; | ||
2002 | int i, ofst = idx * 4; | ||
2003 | u32 data_reg, mask_reg; | ||
2004 | |||
2005 | ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A + ofst); | ||
2006 | ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B + ofst); | ||
2007 | |||
2008 | *enabled = !!(ctla & TFEN); | ||
2009 | tp->snap_len = TFCAPTUREMAX_GET(ctlb); | ||
2010 | tp->min_len = TFMINPKTSIZE_GET(ctlb); | ||
2011 | tp->skip_ofst = TFOFFSET_GET(ctla); | ||
2012 | tp->skip_len = TFLENGTH_GET(ctla); | ||
2013 | tp->invert = !!(ctla & TFINVERTMATCH); | ||
2014 | tp->port = TFPORT_GET(ctla); | ||
2015 | |||
2016 | ofst = (MPS_TRC_FILTER1_MATCH - MPS_TRC_FILTER0_MATCH) * idx; | ||
2017 | data_reg = MPS_TRC_FILTER0_MATCH + ofst; | ||
2018 | mask_reg = MPS_TRC_FILTER0_DONT_CARE + ofst; | ||
2019 | |||
2020 | for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { | ||
2021 | tp->mask[i] = ~t4_read_reg(adap, mask_reg); | ||
2022 | tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; | ||
2023 | } | ||
2024 | } | ||
2025 | |||
2026 | /** | ||
2027 | * get_mps_bg_map - return the buffer groups associated with a port | ||
2028 | * @adap: the adapter | ||
2029 | * @idx: the port index | ||
2030 | * | ||
2031 | * Returns a bitmap indicating which MPS buffer groups are associated | ||
2032 | * with the given port. Bit i is set if buffer group i is used by the | ||
2033 | * port. | ||
2034 | */ | ||
2035 | static unsigned int get_mps_bg_map(struct adapter *adap, int idx) | ||
2036 | { | ||
2037 | u32 n = NUMPORTS_GET(t4_read_reg(adap, MPS_CMN_CTL)); | ||
2038 | |||
2039 | if (n == 0) | ||
2040 | return idx == 0 ? 0xf : 0; | ||
2041 | if (n == 1) | ||
2042 | return idx < 2 ? (3 << (2 * idx)) : 0; | ||
2043 | return 1 << idx; | ||
2044 | } | ||
2045 | |||
2046 | /** | ||
2047 | * t4_get_port_stats - collect port statistics | ||
2048 | * @adap: the adapter | ||
2049 | * @idx: the port index | ||
2050 | * @p: the stats structure to fill | ||
2051 | * | ||
2052 | * Collect statistics related to the given port from HW. | ||
2053 | */ | ||
2054 | void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) | ||
2055 | { | ||
2056 | u32 bgmap = get_mps_bg_map(adap, idx); | ||
2057 | |||
2058 | #define GET_STAT(name) \ | ||
2059 | t4_read_reg64(adap, PORT_REG(idx, MPS_PORT_STAT_##name##_L)) | ||
2060 | #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) | ||
2061 | |||
2062 | p->tx_octets = GET_STAT(TX_PORT_BYTES); | ||
2063 | p->tx_frames = GET_STAT(TX_PORT_FRAMES); | ||
2064 | p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); | ||
2065 | p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); | ||
2066 | p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); | ||
2067 | p->tx_error_frames = GET_STAT(TX_PORT_ERROR); | ||
2068 | p->tx_frames_64 = GET_STAT(TX_PORT_64B); | ||
2069 | p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); | ||
2070 | p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); | ||
2071 | p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); | ||
2072 | p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); | ||
2073 | p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); | ||
2074 | p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); | ||
2075 | p->tx_drop = GET_STAT(TX_PORT_DROP); | ||
2076 | p->tx_pause = GET_STAT(TX_PORT_PAUSE); | ||
2077 | p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); | ||
2078 | p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); | ||
2079 | p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); | ||
2080 | p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); | ||
2081 | p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); | ||
2082 | p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); | ||
2083 | p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); | ||
2084 | p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); | ||
2085 | |||
2086 | p->rx_octets = GET_STAT(RX_PORT_BYTES); | ||
2087 | p->rx_frames = GET_STAT(RX_PORT_FRAMES); | ||
2088 | p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); | ||
2089 | p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); | ||
2090 | p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); | ||
2091 | p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); | ||
2092 | p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); | ||
2093 | p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR); | ||
2094 | p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); | ||
2095 | p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); | ||
2096 | p->rx_runt = GET_STAT(RX_PORT_LESS_64B); | ||
2097 | p->rx_frames_64 = GET_STAT(RX_PORT_64B); | ||
2098 | p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); | ||
2099 | p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); | ||
2100 | p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); | ||
2101 | p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); | ||
2102 | p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); | ||
2103 | p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); | ||
2104 | p->rx_pause = GET_STAT(RX_PORT_PAUSE); | ||
2105 | p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); | ||
2106 | p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); | ||
2107 | p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); | ||
2108 | p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); | ||
2109 | p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); | ||
2110 | p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); | ||
2111 | p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); | ||
2112 | p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); | ||
2113 | |||
2114 | p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; | ||
2115 | p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; | ||
2116 | p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; | ||
2117 | p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; | ||
2118 | p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; | ||
2119 | p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; | ||
2120 | p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; | ||
2121 | p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; | ||
2122 | |||
2123 | #undef GET_STAT | ||
2124 | #undef GET_STAT_COM | ||
2125 | } | ||
2126 | |||
2127 | /** | ||
2128 | * t4_get_lb_stats - collect loopback port statistics | ||
2129 | * @adap: the adapter | ||
2130 | * @idx: the loopback port index | ||
2131 | * @p: the stats structure to fill | ||
2132 | * | ||
2133 | * Return HW statistics for the given loopback port. | ||
2134 | */ | ||
2135 | void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) | ||
2136 | { | ||
2137 | u32 bgmap = get_mps_bg_map(adap, idx); | ||
2138 | |||
2139 | #define GET_STAT(name) \ | ||
2140 | t4_read_reg64(adap, PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)) | ||
2141 | #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) | ||
2142 | |||
2143 | p->octets = GET_STAT(BYTES); | ||
2144 | p->frames = GET_STAT(FRAMES); | ||
2145 | p->bcast_frames = GET_STAT(BCAST); | ||
2146 | p->mcast_frames = GET_STAT(MCAST); | ||
2147 | p->ucast_frames = GET_STAT(UCAST); | ||
2148 | p->error_frames = GET_STAT(ERROR); | ||
2149 | |||
2150 | p->frames_64 = GET_STAT(64B); | ||
2151 | p->frames_65_127 = GET_STAT(65B_127B); | ||
2152 | p->frames_128_255 = GET_STAT(128B_255B); | ||
2153 | p->frames_256_511 = GET_STAT(256B_511B); | ||
2154 | p->frames_512_1023 = GET_STAT(512B_1023B); | ||
2155 | p->frames_1024_1518 = GET_STAT(1024B_1518B); | ||
2156 | p->frames_1519_max = GET_STAT(1519B_MAX); | ||
2157 | p->drop = t4_read_reg(adap, PORT_REG(idx, | ||
2158 | MPS_PORT_STAT_LB_PORT_DROP_FRAMES)); | ||
2159 | |||
2160 | p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; | ||
2161 | p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; | ||
2162 | p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; | ||
2163 | p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; | ||
2164 | p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; | ||
2165 | p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; | ||
2166 | p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; | ||
2167 | p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; | ||
2168 | |||
2169 | #undef GET_STAT | ||
2170 | #undef GET_STAT_COM | ||
2171 | } | ||
2172 | |||
2173 | /** | ||
2174 | * t4_wol_magic_enable - enable/disable magic packet WoL | ||
2175 | * @adap: the adapter | ||
2176 | * @port: the physical port index | ||
2177 | * @addr: MAC address expected in magic packets, %NULL to disable | ||
2178 | * | ||
2179 | * Enables/disables magic packet wake-on-LAN for the selected port. | ||
2180 | */ | ||
2181 | void t4_wol_magic_enable(struct adapter *adap, unsigned int port, | ||
2182 | const u8 *addr) | ||
2183 | { | ||
2184 | if (addr) { | ||
2185 | t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO), | ||
2186 | (addr[2] << 24) | (addr[3] << 16) | | ||
2187 | (addr[4] << 8) | addr[5]); | ||
2188 | t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI), | ||
2189 | (addr[0] << 8) | addr[1]); | ||
2190 | } | ||
2191 | t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), MAGICEN, | ||
2192 | addr ? MAGICEN : 0); | ||
2193 | } | ||
2194 | |||
2195 | /** | ||
2196 | * t4_wol_pat_enable - enable/disable pattern-based WoL | ||
2197 | * @adap: the adapter | ||
2198 | * @port: the physical port index | ||
2199 | * @map: bitmap of which HW pattern filters to set | ||
2200 | * @mask0: byte mask for bytes 0-63 of a packet | ||
2201 | * @mask1: byte mask for bytes 64-127 of a packet | ||
2202 | * @crc: Ethernet CRC for selected bytes | ||
2203 | * @enable: enable/disable switch | ||
2204 | * | ||
2205 | * Sets the pattern filters indicated in @map to mask out the bytes | ||
2206 | * specified in @mask0/@mask1 in received packets and compare the CRC of | ||
2207 | * the resulting packet against @crc. If @enable is %true pattern-based | ||
2208 | * WoL is enabled, otherwise disabled. | ||
2209 | */ | ||
2210 | int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, | ||
2211 | u64 mask0, u64 mask1, unsigned int crc, bool enable) | ||
2212 | { | ||
2213 | int i; | ||
2214 | |||
2215 | if (!enable) { | ||
2216 | t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), | ||
2217 | PATEN, 0); | ||
2218 | return 0; | ||
2219 | } | ||
2220 | if (map > 0xff) | ||
2221 | return -EINVAL; | ||
2222 | |||
2223 | #define EPIO_REG(name) PORT_REG(port, XGMAC_PORT_EPIO_##name) | ||
2224 | |||
2225 | t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); | ||
2226 | t4_write_reg(adap, EPIO_REG(DATA2), mask1); | ||
2227 | t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); | ||
2228 | |||
2229 | for (i = 0; i < NWOL_PAT; i++, map >>= 1) { | ||
2230 | if (!(map & 1)) | ||
2231 | continue; | ||
2232 | |||
2233 | /* write byte masks */ | ||
2234 | t4_write_reg(adap, EPIO_REG(DATA0), mask0); | ||
2235 | t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i) | EPIOWR); | ||
2236 | t4_read_reg(adap, EPIO_REG(OP)); /* flush */ | ||
2237 | if (t4_read_reg(adap, EPIO_REG(OP)) & BUSY) | ||
2238 | return -ETIMEDOUT; | ||
2239 | |||
2240 | /* write CRC */ | ||
2241 | t4_write_reg(adap, EPIO_REG(DATA0), crc); | ||
2242 | t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i + 32) | EPIOWR); | ||
2243 | t4_read_reg(adap, EPIO_REG(OP)); /* flush */ | ||
2244 | if (t4_read_reg(adap, EPIO_REG(OP)) & BUSY) | ||
2245 | return -ETIMEDOUT; | ||
2246 | } | ||
2247 | #undef EPIO_REG | ||
2248 | |||
2249 | t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), 0, PATEN); | ||
2250 | return 0; | ||
2251 | } | ||
2252 | |||
2253 | #define INIT_CMD(var, cmd, rd_wr) do { \ | ||
2254 | (var).op_to_write = htonl(FW_CMD_OP(FW_##cmd##_CMD) | \ | ||
2255 | FW_CMD_REQUEST | FW_CMD_##rd_wr); \ | ||
2256 | (var).retval_len16 = htonl(FW_LEN16(var)); \ | ||
2257 | } while (0) | ||
2258 | |||
2259 | /** | ||
2260 | * t4_mdio_rd - read a PHY register through MDIO | ||
2261 | * @adap: the adapter | ||
2262 | * @mbox: mailbox to use for the FW command | ||
2263 | * @phy_addr: the PHY address | ||
2264 | * @mmd: the PHY MMD to access (0 for clause 22 PHYs) | ||
2265 | * @reg: the register to read | ||
2266 | * @valp: where to store the value | ||
2267 | * | ||
2268 | * Issues a FW command through the given mailbox to read a PHY register. | ||
2269 | */ | ||
2270 | int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, | ||
2271 | unsigned int mmd, unsigned int reg, u16 *valp) | ||
2272 | { | ||
2273 | int ret; | ||
2274 | struct fw_ldst_cmd c; | ||
2275 | |||
2276 | memset(&c, 0, sizeof(c)); | ||
2277 | c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST | | ||
2278 | FW_CMD_READ | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO)); | ||
2279 | c.cycles_to_len16 = htonl(FW_LEN16(c)); | ||
2280 | c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) | | ||
2281 | FW_LDST_CMD_MMD(mmd)); | ||
2282 | c.u.mdio.raddr = htons(reg); | ||
2283 | |||
2284 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | ||
2285 | if (ret == 0) | ||
2286 | *valp = ntohs(c.u.mdio.rval); | ||
2287 | return ret; | ||
2288 | } | ||
2289 | |||
2290 | /** | ||
2291 | * t4_mdio_wr - write a PHY register through MDIO | ||
2292 | * @adap: the adapter | ||
2293 | * @mbox: mailbox to use for the FW command | ||
2294 | * @phy_addr: the PHY address | ||
2295 | * @mmd: the PHY MMD to access (0 for clause 22 PHYs) | ||
2296 | * @reg: the register to write | ||
2297 | * @valp: value to write | ||
2298 | * | ||
2299 | * Issues a FW command through the given mailbox to write a PHY register. | ||
2300 | */ | ||
2301 | int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, | ||
2302 | unsigned int mmd, unsigned int reg, u16 val) | ||
2303 | { | ||
2304 | struct fw_ldst_cmd c; | ||
2305 | |||
2306 | memset(&c, 0, sizeof(c)); | ||
2307 | c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST | | ||
2308 | FW_CMD_WRITE | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO)); | ||
2309 | c.cycles_to_len16 = htonl(FW_LEN16(c)); | ||
2310 | c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) | | ||
2311 | FW_LDST_CMD_MMD(mmd)); | ||
2312 | c.u.mdio.raddr = htons(reg); | ||
2313 | c.u.mdio.rval = htons(val); | ||
2314 | |||
2315 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | ||
2316 | } | ||
2317 | |||
2318 | /** | ||
2319 | * t4_fw_hello - establish communication with FW | ||
2320 | * @adap: the adapter | ||
2321 | * @mbox: mailbox to use for the FW command | ||
2322 | * @evt_mbox: mailbox to receive async FW events | ||
2323 | * @master: specifies the caller's willingness to be the device master | ||
2324 | * @state: returns the current device state | ||
2325 | * | ||
2326 | * Issues a command to establish communication with FW. | ||
2327 | */ | ||
2328 | int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, | ||
2329 | enum dev_master master, enum dev_state *state) | ||
2330 | { | ||
2331 | int ret; | ||
2332 | struct fw_hello_cmd c; | ||
2333 | |||
2334 | INIT_CMD(c, HELLO, WRITE); | ||
2335 | c.err_to_mbasyncnot = htonl( | ||
2336 | FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | | ||
2337 | FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | | ||
2338 | FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox : 0xff) | | ||
2339 | FW_HELLO_CMD_MBASYNCNOT(evt_mbox)); | ||
2340 | |||
2341 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | ||
2342 | if (ret == 0 && state) { | ||
2343 | u32 v = ntohl(c.err_to_mbasyncnot); | ||
2344 | if (v & FW_HELLO_CMD_INIT) | ||
2345 | *state = DEV_STATE_INIT; | ||
2346 | else if (v & FW_HELLO_CMD_ERR) | ||
2347 | *state = DEV_STATE_ERR; | ||
2348 | else | ||
2349 | *state = DEV_STATE_UNINIT; | ||
2350 | } | ||
2351 | return ret; | ||
2352 | } | ||
2353 | |||
2354 | /** | ||
2355 | * t4_fw_bye - end communication with FW | ||
2356 | * @adap: the adapter | ||
2357 | * @mbox: mailbox to use for the FW command | ||
2358 | * | ||
2359 | * Issues a command to terminate communication with FW. | ||
2360 | */ | ||
2361 | int t4_fw_bye(struct adapter *adap, unsigned int mbox) | ||
2362 | { | ||
2363 | struct fw_bye_cmd c; | ||
2364 | |||
2365 | INIT_CMD(c, BYE, WRITE); | ||
2366 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | ||
2367 | } | ||
2368 | |||
2369 | /** | ||
2370 | * t4_init_cmd - ask FW to initialize the device | ||
2371 | * @adap: the adapter | ||
2372 | * @mbox: mailbox to use for the FW command | ||
2373 | * | ||
2374 | * Issues a command to FW to partially initialize the device. This | ||
2375 | * performs initialization that generally doesn't depend on user input. | ||
2376 | */ | ||
2377 | int t4_early_init(struct adapter *adap, unsigned int mbox) | ||
2378 | { | ||
2379 | struct fw_initialize_cmd c; | ||
2380 | |||
2381 | INIT_CMD(c, INITIALIZE, WRITE); | ||
2382 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | ||
2383 | } | ||
2384 | |||
2385 | /** | ||
2386 | * t4_fw_reset - issue a reset to FW | ||
2387 | * @adap: the adapter | ||
2388 | * @mbox: mailbox to use for the FW command | ||
2389 | * @reset: specifies the type of reset to perform | ||
2390 | * | ||
2391 | * Issues a reset command of the specified type to FW. | ||
2392 | */ | ||
2393 | int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) | ||
2394 | { | ||
2395 | struct fw_reset_cmd c; | ||
2396 | |||
2397 | INIT_CMD(c, RESET, WRITE); | ||
2398 | c.val = htonl(reset); | ||
2399 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | ||
2400 | } | ||
2401 | |||
2402 | /** | ||
2403 | * t4_query_params - query FW or device parameters | ||
2404 | * @adap: the adapter | ||
2405 | * @mbox: mailbox to use for the FW command | ||
2406 | * @pf: the PF | ||
2407 | * @vf: the VF | ||
2408 | * @nparams: the number of parameters | ||
2409 | * @params: the parameter names | ||
2410 | * @val: the parameter values | ||
2411 | * | ||
2412 | * Reads the value of FW or device parameters. Up to 7 parameters can be | ||
2413 | * queried at once. | ||
2414 | */ | ||
2415 | int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, | ||
2416 | unsigned int vf, unsigned int nparams, const u32 *params, | ||
2417 | u32 *val) | ||
2418 | { | ||
2419 | int i, ret; | ||
2420 | struct fw_params_cmd c; | ||
2421 | __be32 *p = &c.param[0].mnem; | ||
2422 | |||
2423 | if (nparams > 7) | ||
2424 | return -EINVAL; | ||
2425 | |||
2426 | memset(&c, 0, sizeof(c)); | ||
2427 | c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST | | ||
2428 | FW_CMD_READ | FW_PARAMS_CMD_PFN(pf) | | ||
2429 | FW_PARAMS_CMD_VFN(vf)); | ||
2430 | c.retval_len16 = htonl(FW_LEN16(c)); | ||
2431 | for (i = 0; i < nparams; i++, p += 2) | ||
2432 | *p = htonl(*params++); | ||
2433 | |||
2434 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | ||
2435 | if (ret == 0) | ||
2436 | for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) | ||
2437 | *val++ = ntohl(*p); | ||
2438 | return ret; | ||
2439 | } | ||
2440 | |||
2441 | /** | ||
2442 | * t4_set_params - sets FW or device parameters | ||
2443 | * @adap: the adapter | ||
2444 | * @mbox: mailbox to use for the FW command | ||
2445 | * @pf: the PF | ||
2446 | * @vf: the VF | ||
2447 | * @nparams: the number of parameters | ||
2448 | * @params: the parameter names | ||
2449 | * @val: the parameter values | ||
2450 | * | ||
2451 | * Sets the value of FW or device parameters. Up to 7 parameters can be | ||
2452 | * specified at once. | ||
2453 | */ | ||
2454 | int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, | ||
2455 | unsigned int vf, unsigned int nparams, const u32 *params, | ||
2456 | const u32 *val) | ||
2457 | { | ||
2458 | struct fw_params_cmd c; | ||
2459 | __be32 *p = &c.param[0].mnem; | ||
2460 | |||
2461 | if (nparams > 7) | ||
2462 | return -EINVAL; | ||
2463 | |||
2464 | memset(&c, 0, sizeof(c)); | ||
2465 | c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST | | ||
2466 | FW_CMD_WRITE | FW_PARAMS_CMD_PFN(pf) | | ||
2467 | FW_PARAMS_CMD_VFN(vf)); | ||
2468 | c.retval_len16 = htonl(FW_LEN16(c)); | ||
2469 | while (nparams--) { | ||
2470 | *p++ = htonl(*params++); | ||
2471 | *p++ = htonl(*val++); | ||
2472 | } | ||
2473 | |||
2474 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | ||
2475 | } | ||
2476 | |||
2477 | /** | ||
2478 | * t4_cfg_pfvf - configure PF/VF resource limits | ||
2479 | * @adap: the adapter | ||
2480 | * @mbox: mailbox to use for the FW command | ||
2481 | * @pf: the PF being configured | ||
2482 | * @vf: the VF being configured | ||
2483 | * @txq: the max number of egress queues | ||
2484 | * @txq_eth_ctrl: the max number of egress Ethernet or control queues | ||
2485 | * @rxqi: the max number of interrupt-capable ingress queues | ||
2486 | * @rxq: the max number of interruptless ingress queues | ||
2487 | * @tc: the PCI traffic class | ||
2488 | * @vi: the max number of virtual interfaces | ||
2489 | * @cmask: the channel access rights mask for the PF/VF | ||
2490 | * @pmask: the port access rights mask for the PF/VF | ||
2491 | * @nexact: the maximum number of exact MPS filters | ||
2492 | * @rcaps: read capabilities | ||
2493 | * @wxcaps: write/execute capabilities | ||
2494 | * | ||
2495 | * Configures resource limits and capabilities for a physical or virtual | ||
2496 | * function. | ||
2497 | */ | ||
2498 | int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, | ||
2499 | unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, | ||
2500 | unsigned int rxqi, unsigned int rxq, unsigned int tc, | ||
2501 | unsigned int vi, unsigned int cmask, unsigned int pmask, | ||
2502 | unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) | ||
2503 | { | ||
2504 | struct fw_pfvf_cmd c; | ||
2505 | |||
2506 | memset(&c, 0, sizeof(c)); | ||
2507 | c.op_to_vfn = htonl(FW_CMD_OP(FW_PFVF_CMD) | FW_CMD_REQUEST | | ||
2508 | FW_CMD_WRITE | FW_PFVF_CMD_PFN(pf) | | ||
2509 | FW_PFVF_CMD_VFN(vf)); | ||
2510 | c.retval_len16 = htonl(FW_LEN16(c)); | ||
2511 | c.niqflint_niq = htonl(FW_PFVF_CMD_NIQFLINT(rxqi) | | ||
2512 | FW_PFVF_CMD_NIQ(rxq)); | ||
2513 | c.cmask_to_neq = htonl(FW_PFVF_CMD_CMASK(cmask) | | ||
2514 | FW_PFVF_CMD_PMASK(pmask) | | ||
2515 | FW_PFVF_CMD_NEQ(txq)); | ||
2516 | c.tc_to_nexactf = htonl(FW_PFVF_CMD_TC(tc) | FW_PFVF_CMD_NVI(vi) | | ||
2517 | FW_PFVF_CMD_NEXACTF(nexact)); | ||
2518 | c.r_caps_to_nethctrl = htonl(FW_PFVF_CMD_R_CAPS(rcaps) | | ||
2519 | FW_PFVF_CMD_WX_CAPS(wxcaps) | | ||
2520 | FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); | ||
2521 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | ||
2522 | } | ||
2523 | |||
2524 | /** | ||
2525 | * t4_alloc_vi - allocate a virtual interface | ||
2526 | * @adap: the adapter | ||
2527 | * @mbox: mailbox to use for the FW command | ||
2528 | * @port: physical port associated with the VI | ||
2529 | * @pf: the PF owning the VI | ||
2530 | * @vf: the VF owning the VI | ||
2531 | * @nmac: number of MAC addresses needed (1 to 5) | ||
2532 | * @mac: the MAC addresses of the VI | ||
2533 | * @rss_size: size of RSS table slice associated with this VI | ||
2534 | * | ||
2535 | * Allocates a virtual interface for the given physical port. If @mac is | ||
2536 | * not %NULL it contains the MAC addresses of the VI as assigned by FW. | ||
2537 | * @mac should be large enough to hold @nmac Ethernet addresses, they are | ||
2538 | * stored consecutively so the space needed is @nmac * 6 bytes. | ||
2539 | * Returns a negative error number or the non-negative VI id. | ||
2540 | */ | ||
2541 | int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, | ||
2542 | unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, | ||
2543 | unsigned int *rss_size) | ||
2544 | { | ||
2545 | int ret; | ||
2546 | struct fw_vi_cmd c; | ||
2547 | |||
2548 | memset(&c, 0, sizeof(c)); | ||
2549 | c.op_to_vfn = htonl(FW_CMD_OP(FW_VI_CMD) | FW_CMD_REQUEST | | ||
2550 | FW_CMD_WRITE | FW_CMD_EXEC | | ||
2551 | FW_VI_CMD_PFN(pf) | FW_VI_CMD_VFN(vf)); | ||
2552 | c.alloc_to_len16 = htonl(FW_VI_CMD_ALLOC | FW_LEN16(c)); | ||
2553 | c.portid_pkd = FW_VI_CMD_PORTID(port); | ||
2554 | c.nmac = nmac - 1; | ||
2555 | |||
2556 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | ||
2557 | if (ret) | ||
2558 | return ret; | ||
2559 | |||
2560 | if (mac) { | ||
2561 | memcpy(mac, c.mac, sizeof(c.mac)); | ||
2562 | switch (nmac) { | ||
2563 | case 5: | ||
2564 | memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); | ||
2565 | case 4: | ||
2566 | memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); | ||
2567 | case 3: | ||
2568 | memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); | ||
2569 | case 2: | ||
2570 | memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); | ||
2571 | } | ||
2572 | } | ||
2573 | if (rss_size) | ||
2574 | *rss_size = FW_VI_CMD_RSSSIZE_GET(ntohs(c.rsssize_pkd)); | ||
2575 | return ntohs(c.viid_pkd); | ||
2576 | } | ||
2577 | |||
2578 | /** | ||
2579 | * t4_free_vi - free a virtual interface | ||
2580 | * @adap: the adapter | ||
2581 | * @mbox: mailbox to use for the FW command | ||
2582 | * @pf: the PF owning the VI | ||
2583 | * @vf: the VF owning the VI | ||
2584 | * @viid: virtual interface identifiler | ||
2585 | * | ||
2586 | * Free a previously allocated virtual interface. | ||
2587 | */ | ||
2588 | int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, | ||
2589 | unsigned int vf, unsigned int viid) | ||
2590 | { | ||
2591 | struct fw_vi_cmd c; | ||
2592 | |||
2593 | memset(&c, 0, sizeof(c)); | ||
2594 | c.op_to_vfn = htonl(FW_CMD_OP(FW_VI_CMD) | FW_CMD_REQUEST | | ||
2595 | FW_CMD_EXEC | FW_VI_CMD_PFN(pf) | | ||
2596 | FW_VI_CMD_VFN(vf)); | ||
2597 | c.alloc_to_len16 = htonl(FW_VI_CMD_FREE | FW_LEN16(c)); | ||
2598 | c.viid_pkd = htons(FW_VI_CMD_VIID(viid)); | ||
2599 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | ||
2600 | } | ||
2601 | |||
2602 | /** | ||
2603 | * t4_set_rxmode - set Rx properties of a virtual interface | ||
2604 | * @adap: the adapter | ||
2605 | * @mbox: mailbox to use for the FW command | ||
2606 | * @viid: the VI id | ||
2607 | * @mtu: the new MTU or -1 | ||
2608 | * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change | ||
2609 | * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change | ||
2610 | * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change | ||
2611 | * @sleep_ok: if true we may sleep while awaiting command completion | ||
2612 | * | ||
2613 | * Sets Rx properties of a virtual interface. | ||
2614 | */ | ||
2615 | int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, | ||
2616 | int mtu, int promisc, int all_multi, int bcast, bool sleep_ok) | ||
2617 | { | ||
2618 | struct fw_vi_rxmode_cmd c; | ||
2619 | |||
2620 | /* convert to FW values */ | ||
2621 | if (mtu < 0) | ||
2622 | mtu = FW_RXMODE_MTU_NO_CHG; | ||
2623 | if (promisc < 0) | ||
2624 | promisc = FW_VI_RXMODE_CMD_PROMISCEN_MASK; | ||
2625 | if (all_multi < 0) | ||
2626 | all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_MASK; | ||
2627 | if (bcast < 0) | ||
2628 | bcast = FW_VI_RXMODE_CMD_BROADCASTEN_MASK; | ||
2629 | |||
2630 | memset(&c, 0, sizeof(c)); | ||
2631 | c.op_to_viid = htonl(FW_CMD_OP(FW_VI_RXMODE_CMD) | FW_CMD_REQUEST | | ||
2632 | FW_CMD_WRITE | FW_VI_RXMODE_CMD_VIID(viid)); | ||
2633 | c.retval_len16 = htonl(FW_LEN16(c)); | ||
2634 | c.mtu_to_broadcasten = htonl(FW_VI_RXMODE_CMD_MTU(mtu) | | ||
2635 | FW_VI_RXMODE_CMD_PROMISCEN(promisc) | | ||
2636 | FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | | ||
2637 | FW_VI_RXMODE_CMD_BROADCASTEN(bcast)); | ||
2638 | return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); | ||
2639 | } | ||
2640 | |||
2641 | /** | ||
2642 | * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses | ||
2643 | * @adap: the adapter | ||
2644 | * @mbox: mailbox to use for the FW command | ||
2645 | * @viid: the VI id | ||
2646 | * @free: if true any existing filters for this VI id are first removed | ||
2647 | * @naddr: the number of MAC addresses to allocate filters for (up to 7) | ||
2648 | * @addr: the MAC address(es) | ||
2649 | * @idx: where to store the index of each allocated filter | ||
2650 | * @hash: pointer to hash address filter bitmap | ||
2651 | * @sleep_ok: call is allowed to sleep | ||
2652 | * | ||
2653 | * Allocates an exact-match filter for each of the supplied addresses and | ||
2654 | * sets it to the corresponding address. If @idx is not %NULL it should | ||
2655 | * have at least @naddr entries, each of which will be set to the index of | ||
2656 | * the filter allocated for the corresponding MAC address. If a filter | ||
2657 | * could not be allocated for an address its index is set to 0xffff. | ||
2658 | * If @hash is not %NULL addresses that fail to allocate an exact filter | ||
2659 | * are hashed and update the hash filter bitmap pointed at by @hash. | ||
2660 | * | ||
2661 | * Returns a negative error number or the number of filters allocated. | ||
2662 | */ | ||
2663 | int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, | ||
2664 | unsigned int viid, bool free, unsigned int naddr, | ||
2665 | const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) | ||
2666 | { | ||
2667 | int i, ret; | ||
2668 | struct fw_vi_mac_cmd c; | ||
2669 | struct fw_vi_mac_exact *p; | ||
2670 | |||
2671 | if (naddr > 7) | ||
2672 | return -EINVAL; | ||
2673 | |||
2674 | memset(&c, 0, sizeof(c)); | ||
2675 | c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST | | ||
2676 | FW_CMD_WRITE | (free ? FW_CMD_EXEC : 0) | | ||
2677 | FW_VI_MAC_CMD_VIID(viid)); | ||
2678 | c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_FREEMACS(free) | | ||
2679 | FW_CMD_LEN16((naddr + 2) / 2)); | ||
2680 | |||
2681 | for (i = 0, p = c.u.exact; i < naddr; i++, p++) { | ||
2682 | p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID | | ||
2683 | FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); | ||
2684 | memcpy(p->macaddr, addr[i], sizeof(p->macaddr)); | ||
2685 | } | ||
2686 | |||
2687 | ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); | ||
2688 | if (ret) | ||
2689 | return ret; | ||
2690 | |||
2691 | for (i = 0, p = c.u.exact; i < naddr; i++, p++) { | ||
2692 | u16 index = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx)); | ||
2693 | |||
2694 | if (idx) | ||
2695 | idx[i] = index >= NEXACT_MAC ? 0xffff : index; | ||
2696 | if (index < NEXACT_MAC) | ||
2697 | ret++; | ||
2698 | else if (hash) | ||
2699 | *hash |= (1 << hash_mac_addr(addr[i])); | ||
2700 | } | ||
2701 | return ret; | ||
2702 | } | ||
2703 | |||
2704 | /** | ||
2705 | * t4_change_mac - modifies the exact-match filter for a MAC address | ||
2706 | * @adap: the adapter | ||
2707 | * @mbox: mailbox to use for the FW command | ||
2708 | * @viid: the VI id | ||
2709 | * @idx: index of existing filter for old value of MAC address, or -1 | ||
2710 | * @addr: the new MAC address value | ||
2711 | * @persist: whether a new MAC allocation should be persistent | ||
2712 | * @add_smt: if true also add the address to the HW SMT | ||
2713 | * | ||
2714 | * Modifies an exact-match filter and sets it to the new MAC address. | ||
2715 | * Note that in general it is not possible to modify the value of a given | ||
2716 | * filter so the generic way to modify an address filter is to free the one | ||
2717 | * being used by the old address value and allocate a new filter for the | ||
2718 | * new address value. @idx can be -1 if the address is a new addition. | ||
2719 | * | ||
2720 | * Returns a negative error number or the index of the filter with the new | ||
2721 | * MAC value. | ||
2722 | */ | ||
2723 | int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, | ||
2724 | int idx, const u8 *addr, bool persist, bool add_smt) | ||
2725 | { | ||
2726 | int ret, mode; | ||
2727 | struct fw_vi_mac_cmd c; | ||
2728 | struct fw_vi_mac_exact *p = c.u.exact; | ||
2729 | |||
2730 | if (idx < 0) /* new allocation */ | ||
2731 | idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; | ||
2732 | mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; | ||
2733 | |||
2734 | memset(&c, 0, sizeof(c)); | ||
2735 | c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST | | ||
2736 | FW_CMD_WRITE | FW_VI_MAC_CMD_VIID(viid)); | ||
2737 | c.freemacs_to_len16 = htonl(FW_CMD_LEN16(1)); | ||
2738 | p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID | | ||
2739 | FW_VI_MAC_CMD_SMAC_RESULT(mode) | | ||
2740 | FW_VI_MAC_CMD_IDX(idx)); | ||
2741 | memcpy(p->macaddr, addr, sizeof(p->macaddr)); | ||
2742 | |||
2743 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | ||
2744 | if (ret == 0) { | ||
2745 | ret = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx)); | ||
2746 | if (ret >= NEXACT_MAC) | ||
2747 | ret = -ENOMEM; | ||
2748 | } | ||
2749 | return ret; | ||
2750 | } | ||
2751 | |||
2752 | /** | ||
2753 | * t4_set_addr_hash - program the MAC inexact-match hash filter | ||
2754 | * @adap: the adapter | ||
2755 | * @mbox: mailbox to use for the FW command | ||
2756 | * @viid: the VI id | ||
2757 | * @ucast: whether the hash filter should also match unicast addresses | ||
2758 | * @vec: the value to be written to the hash filter | ||
2759 | * @sleep_ok: call is allowed to sleep | ||
2760 | * | ||
2761 | * Sets the 64-bit inexact-match hash filter for a virtual interface. | ||
2762 | */ | ||
2763 | int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, | ||
2764 | bool ucast, u64 vec, bool sleep_ok) | ||
2765 | { | ||
2766 | struct fw_vi_mac_cmd c; | ||
2767 | |||
2768 | memset(&c, 0, sizeof(c)); | ||
2769 | c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST | | ||
2770 | FW_CMD_WRITE | FW_VI_ENABLE_CMD_VIID(viid)); | ||
2771 | c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_HASHVECEN | | ||
2772 | FW_VI_MAC_CMD_HASHUNIEN(ucast) | | ||
2773 | FW_CMD_LEN16(1)); | ||
2774 | c.u.hash.hashvec = cpu_to_be64(vec); | ||
2775 | return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); | ||
2776 | } | ||
2777 | |||
2778 | /** | ||
2779 | * t4_enable_vi - enable/disable a virtual interface | ||
2780 | * @adap: the adapter | ||
2781 | * @mbox: mailbox to use for the FW command | ||
2782 | * @viid: the VI id | ||
2783 | * @rx_en: 1=enable Rx, 0=disable Rx | ||
2784 | * @tx_en: 1=enable Tx, 0=disable Tx | ||
2785 | * | ||
2786 | * Enables/disables a virtual interface. | ||
2787 | */ | ||
2788 | int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, | ||
2789 | bool rx_en, bool tx_en) | ||
2790 | { | ||
2791 | struct fw_vi_enable_cmd c; | ||
2792 | |||
2793 | memset(&c, 0, sizeof(c)); | ||
2794 | c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST | | ||
2795 | FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid)); | ||
2796 | c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_IEN(rx_en) | | ||
2797 | FW_VI_ENABLE_CMD_EEN(tx_en) | FW_LEN16(c)); | ||
2798 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | ||
2799 | } | ||
2800 | |||
2801 | /** | ||
2802 | * t4_identify_port - identify a VI's port by blinking its LED | ||
2803 | * @adap: the adapter | ||
2804 | * @mbox: mailbox to use for the FW command | ||
2805 | * @viid: the VI id | ||
2806 | * @nblinks: how many times to blink LED at 2.5 Hz | ||
2807 | * | ||
2808 | * Identifies a VI's port by blinking its LED. | ||
2809 | */ | ||
2810 | int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, | ||
2811 | unsigned int nblinks) | ||
2812 | { | ||
2813 | struct fw_vi_enable_cmd c; | ||
2814 | |||
2815 | c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST | | ||
2816 | FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid)); | ||
2817 | c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); | ||
2818 | c.blinkdur = htons(nblinks); | ||
2819 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | ||
2820 | } | ||
2821 | |||
2822 | /** | ||
2823 | * t4_iq_start_stop - enable/disable an ingress queue and its FLs | ||
2824 | * @adap: the adapter | ||
2825 | * @mbox: mailbox to use for the FW command | ||
2826 | * @start: %true to enable the queues, %false to disable them | ||
2827 | * @pf: the PF owning the queues | ||
2828 | * @vf: the VF owning the queues | ||
2829 | * @iqid: ingress queue id | ||
2830 | * @fl0id: FL0 queue id or 0xffff if no attached FL0 | ||
2831 | * @fl1id: FL1 queue id or 0xffff if no attached FL1 | ||
2832 | * | ||
2833 | * Starts or stops an ingress queue and its associated FLs, if any. | ||
2834 | */ | ||
2835 | int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start, | ||
2836 | unsigned int pf, unsigned int vf, unsigned int iqid, | ||
2837 | unsigned int fl0id, unsigned int fl1id) | ||
2838 | { | ||
2839 | struct fw_iq_cmd c; | ||
2840 | |||
2841 | memset(&c, 0, sizeof(c)); | ||
2842 | c.op_to_vfn = htonl(FW_CMD_OP(FW_IQ_CMD) | FW_CMD_REQUEST | | ||
2843 | FW_CMD_EXEC | FW_IQ_CMD_PFN(pf) | | ||
2844 | FW_IQ_CMD_VFN(vf)); | ||
2845 | c.alloc_to_len16 = htonl(FW_IQ_CMD_IQSTART(start) | | ||
2846 | FW_IQ_CMD_IQSTOP(!start) | FW_LEN16(c)); | ||
2847 | c.iqid = htons(iqid); | ||
2848 | c.fl0id = htons(fl0id); | ||
2849 | c.fl1id = htons(fl1id); | ||
2850 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | ||
2851 | } | ||
2852 | |||
2853 | /** | ||
2854 | * t4_iq_free - free an ingress queue and its FLs | ||
2855 | * @adap: the adapter | ||
2856 | * @mbox: mailbox to use for the FW command | ||
2857 | * @pf: the PF owning the queues | ||
2858 | * @vf: the VF owning the queues | ||
2859 | * @iqtype: the ingress queue type | ||
2860 | * @iqid: ingress queue id | ||
2861 | * @fl0id: FL0 queue id or 0xffff if no attached FL0 | ||
2862 | * @fl1id: FL1 queue id or 0xffff if no attached FL1 | ||
2863 | * | ||
2864 | * Frees an ingress queue and its associated FLs, if any. | ||
2865 | */ | ||
2866 | int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | ||
2867 | unsigned int vf, unsigned int iqtype, unsigned int iqid, | ||
2868 | unsigned int fl0id, unsigned int fl1id) | ||
2869 | { | ||
2870 | struct fw_iq_cmd c; | ||
2871 | |||
2872 | memset(&c, 0, sizeof(c)); | ||
2873 | c.op_to_vfn = htonl(FW_CMD_OP(FW_IQ_CMD) | FW_CMD_REQUEST | | ||
2874 | FW_CMD_EXEC | FW_IQ_CMD_PFN(pf) | | ||
2875 | FW_IQ_CMD_VFN(vf)); | ||
2876 | c.alloc_to_len16 = htonl(FW_IQ_CMD_FREE | FW_LEN16(c)); | ||
2877 | c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE(iqtype)); | ||
2878 | c.iqid = htons(iqid); | ||
2879 | c.fl0id = htons(fl0id); | ||
2880 | c.fl1id = htons(fl1id); | ||
2881 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | ||
2882 | } | ||
2883 | |||
2884 | /** | ||
2885 | * t4_eth_eq_free - free an Ethernet egress queue | ||
2886 | * @adap: the adapter | ||
2887 | * @mbox: mailbox to use for the FW command | ||
2888 | * @pf: the PF owning the queue | ||
2889 | * @vf: the VF owning the queue | ||
2890 | * @eqid: egress queue id | ||
2891 | * | ||
2892 | * Frees an Ethernet egress queue. | ||
2893 | */ | ||
2894 | int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | ||
2895 | unsigned int vf, unsigned int eqid) | ||
2896 | { | ||
2897 | struct fw_eq_eth_cmd c; | ||
2898 | |||
2899 | memset(&c, 0, sizeof(c)); | ||
2900 | c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_ETH_CMD) | FW_CMD_REQUEST | | ||
2901 | FW_CMD_EXEC | FW_EQ_ETH_CMD_PFN(pf) | | ||
2902 | FW_EQ_ETH_CMD_VFN(vf)); | ||
2903 | c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); | ||
2904 | c.eqid_pkd = htonl(FW_EQ_ETH_CMD_EQID(eqid)); | ||
2905 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | ||
2906 | } | ||
2907 | |||
2908 | /** | ||
2909 | * t4_ctrl_eq_free - free a control egress queue | ||
2910 | * @adap: the adapter | ||
2911 | * @mbox: mailbox to use for the FW command | ||
2912 | * @pf: the PF owning the queue | ||
2913 | * @vf: the VF owning the queue | ||
2914 | * @eqid: egress queue id | ||
2915 | * | ||
2916 | * Frees a control egress queue. | ||
2917 | */ | ||
2918 | int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | ||
2919 | unsigned int vf, unsigned int eqid) | ||
2920 | { | ||
2921 | struct fw_eq_ctrl_cmd c; | ||
2922 | |||
2923 | memset(&c, 0, sizeof(c)); | ||
2924 | c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST | | ||
2925 | FW_CMD_EXEC | FW_EQ_CTRL_CMD_PFN(pf) | | ||
2926 | FW_EQ_CTRL_CMD_VFN(vf)); | ||
2927 | c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); | ||
2928 | c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_EQID(eqid)); | ||
2929 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | ||
2930 | } | ||
2931 | |||
2932 | /** | ||
2933 | * t4_ofld_eq_free - free an offload egress queue | ||
2934 | * @adap: the adapter | ||
2935 | * @mbox: mailbox to use for the FW command | ||
2936 | * @pf: the PF owning the queue | ||
2937 | * @vf: the VF owning the queue | ||
2938 | * @eqid: egress queue id | ||
2939 | * | ||
2940 | * Frees a control egress queue. | ||
2941 | */ | ||
2942 | int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | ||
2943 | unsigned int vf, unsigned int eqid) | ||
2944 | { | ||
2945 | struct fw_eq_ofld_cmd c; | ||
2946 | |||
2947 | memset(&c, 0, sizeof(c)); | ||
2948 | c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST | | ||
2949 | FW_CMD_EXEC | FW_EQ_OFLD_CMD_PFN(pf) | | ||
2950 | FW_EQ_OFLD_CMD_VFN(vf)); | ||
2951 | c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); | ||
2952 | c.eqid_pkd = htonl(FW_EQ_OFLD_CMD_EQID(eqid)); | ||
2953 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | ||
2954 | } | ||
2955 | |||
2956 | /** | ||
2957 | * t4_handle_fw_rpl - process a FW reply message | ||
2958 | * @adap: the adapter | ||
2959 | * @rpl: start of the FW message | ||
2960 | * | ||
2961 | * Processes a FW message, such as link state change messages. | ||
2962 | */ | ||
2963 | int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) | ||
2964 | { | ||
2965 | u8 opcode = *(const u8 *)rpl; | ||
2966 | |||
2967 | if (opcode == FW_PORT_CMD) { /* link/module state change message */ | ||
2968 | int speed = 0, fc = 0; | ||
2969 | const struct fw_port_cmd *p = (void *)rpl; | ||
2970 | int chan = FW_PORT_CMD_PORTID_GET(ntohl(p->op_to_portid)); | ||
2971 | int port = adap->chan_map[chan]; | ||
2972 | struct port_info *pi = adap2pinfo(adap, port); | ||
2973 | struct link_config *lc = &pi->link_cfg; | ||
2974 | u32 stat = ntohl(p->u.info.lstatus_to_modtype); | ||
2975 | int link_ok = (stat & FW_PORT_CMD_LSTATUS) != 0; | ||
2976 | u32 mod = FW_PORT_CMD_MODTYPE_GET(stat); | ||
2977 | |||
2978 | if (stat & FW_PORT_CMD_RXPAUSE) | ||
2979 | fc |= PAUSE_RX; | ||
2980 | if (stat & FW_PORT_CMD_TXPAUSE) | ||
2981 | fc |= PAUSE_TX; | ||
2982 | if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) | ||
2983 | speed = SPEED_100; | ||
2984 | else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) | ||
2985 | speed = SPEED_1000; | ||
2986 | else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) | ||
2987 | speed = SPEED_10000; | ||
2988 | |||
2989 | if (link_ok != lc->link_ok || speed != lc->speed || | ||
2990 | fc != lc->fc) { /* something changed */ | ||
2991 | lc->link_ok = link_ok; | ||
2992 | lc->speed = speed; | ||
2993 | lc->fc = fc; | ||
2994 | t4_os_link_changed(adap, port, link_ok); | ||
2995 | } | ||
2996 | if (mod != pi->mod_type) { | ||
2997 | pi->mod_type = mod; | ||
2998 | t4_os_portmod_changed(adap, port); | ||
2999 | } | ||
3000 | } | ||
3001 | return 0; | ||
3002 | } | ||
3003 | |||
3004 | static void __devinit get_pci_mode(struct adapter *adapter, | ||
3005 | struct pci_params *p) | ||
3006 | { | ||
3007 | u16 val; | ||
3008 | u32 pcie_cap = pci_pcie_cap(adapter->pdev); | ||
3009 | |||
3010 | if (pcie_cap) { | ||
3011 | pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA, | ||
3012 | &val); | ||
3013 | p->speed = val & PCI_EXP_LNKSTA_CLS; | ||
3014 | p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; | ||
3015 | } | ||
3016 | } | ||
3017 | |||
3018 | /** | ||
3019 | * init_link_config - initialize a link's SW state | ||
3020 | * @lc: structure holding the link state | ||
3021 | * @caps: link capabilities | ||
3022 | * | ||
3023 | * Initializes the SW state maintained for each link, including the link's | ||
3024 | * capabilities and default speed/flow-control/autonegotiation settings. | ||
3025 | */ | ||
3026 | static void __devinit init_link_config(struct link_config *lc, | ||
3027 | unsigned int caps) | ||
3028 | { | ||
3029 | lc->supported = caps; | ||
3030 | lc->requested_speed = 0; | ||
3031 | lc->speed = 0; | ||
3032 | lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX; | ||
3033 | if (lc->supported & FW_PORT_CAP_ANEG) { | ||
3034 | lc->advertising = lc->supported & ADVERT_MASK; | ||
3035 | lc->autoneg = AUTONEG_ENABLE; | ||
3036 | lc->requested_fc |= PAUSE_AUTONEG; | ||
3037 | } else { | ||
3038 | lc->advertising = 0; | ||
3039 | lc->autoneg = AUTONEG_DISABLE; | ||
3040 | } | ||
3041 | } | ||
3042 | |||
3043 | static int __devinit wait_dev_ready(struct adapter *adap) | ||
3044 | { | ||
3045 | if (t4_read_reg(adap, PL_WHOAMI) != 0xffffffff) | ||
3046 | return 0; | ||
3047 | msleep(500); | ||
3048 | return t4_read_reg(adap, PL_WHOAMI) != 0xffffffff ? 0 : -EIO; | ||
3049 | } | ||
3050 | |||
3051 | /** | ||
3052 | * t4_prep_adapter - prepare SW and HW for operation | ||
3053 | * @adapter: the adapter | ||
3054 | * @reset: if true perform a HW reset | ||
3055 | * | ||
3056 | * Initialize adapter SW state for the various HW modules, set initial | ||
3057 | * values for some adapter tunables, take PHYs out of reset, and | ||
3058 | * initialize the MDIO interface. | ||
3059 | */ | ||
3060 | int __devinit t4_prep_adapter(struct adapter *adapter) | ||
3061 | { | ||
3062 | int ret; | ||
3063 | |||
3064 | ret = wait_dev_ready(adapter); | ||
3065 | if (ret < 0) | ||
3066 | return ret; | ||
3067 | |||
3068 | get_pci_mode(adapter, &adapter->params.pci); | ||
3069 | adapter->params.rev = t4_read_reg(adapter, PL_REV); | ||
3070 | |||
3071 | ret = get_vpd_params(adapter, &adapter->params.vpd); | ||
3072 | if (ret < 0) | ||
3073 | return ret; | ||
3074 | |||
3075 | init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); | ||
3076 | |||
3077 | /* | ||
3078 | * Default port for debugging in case we can't reach FW. | ||
3079 | */ | ||
3080 | adapter->params.nports = 1; | ||
3081 | adapter->params.portvec = 1; | ||
3082 | return 0; | ||
3083 | } | ||
3084 | |||
3085 | int __devinit t4_port_init(struct adapter *adap, int mbox, int pf, int vf) | ||
3086 | { | ||
3087 | u8 addr[6]; | ||
3088 | int ret, i, j = 0; | ||
3089 | struct fw_port_cmd c; | ||
3090 | |||
3091 | memset(&c, 0, sizeof(c)); | ||
3092 | |||
3093 | for_each_port(adap, i) { | ||
3094 | unsigned int rss_size; | ||
3095 | struct port_info *p = adap2pinfo(adap, i); | ||
3096 | |||
3097 | while ((adap->params.portvec & (1 << j)) == 0) | ||
3098 | j++; | ||
3099 | |||
3100 | c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | | ||
3101 | FW_CMD_REQUEST | FW_CMD_READ | | ||
3102 | FW_PORT_CMD_PORTID(j)); | ||
3103 | c.action_to_len16 = htonl( | ||
3104 | FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) | | ||
3105 | FW_LEN16(c)); | ||
3106 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | ||
3107 | if (ret) | ||
3108 | return ret; | ||
3109 | |||
3110 | ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size); | ||
3111 | if (ret < 0) | ||
3112 | return ret; | ||
3113 | |||
3114 | p->viid = ret; | ||
3115 | p->tx_chan = j; | ||
3116 | p->lport = j; | ||
3117 | p->rss_size = rss_size; | ||
3118 | memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN); | ||
3119 | memcpy(adap->port[i]->perm_addr, addr, ETH_ALEN); | ||
3120 | |||
3121 | ret = ntohl(c.u.info.lstatus_to_modtype); | ||
3122 | p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP) ? | ||
3123 | FW_PORT_CMD_MDIOADDR_GET(ret) : -1; | ||
3124 | p->port_type = FW_PORT_CMD_PTYPE_GET(ret); | ||
3125 | p->mod_type = FW_PORT_CMD_MODTYPE_GET(ret); | ||
3126 | |||
3127 | init_link_config(&p->link_cfg, ntohs(c.u.info.pcap)); | ||
3128 | j++; | ||
3129 | } | ||
3130 | return 0; | ||
3131 | } | ||
diff --git a/drivers/net/cxgb4/t4_hw.h b/drivers/net/cxgb4/t4_hw.h new file mode 100644 index 000000000000..025623285c93 --- /dev/null +++ b/drivers/net/cxgb4/t4_hw.h | |||
@@ -0,0 +1,100 @@ | |||
1 | /* | ||
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | ||
3 | * | ||
4 | * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved. | ||
5 | * | ||
6 | * This software is available to you under a choice of one of two | ||
7 | * licenses. You may choose to be licensed under the terms of the GNU | ||
8 | * General Public License (GPL) Version 2, available from the file | ||
9 | * COPYING in the main directory of this source tree, or the | ||
10 | * OpenIB.org BSD license below: | ||
11 | * | ||
12 | * Redistribution and use in source and binary forms, with or | ||
13 | * without modification, are permitted provided that the following | ||
14 | * conditions are met: | ||
15 | * | ||
16 | * - Redistributions of source code must retain the above | ||
17 | * copyright notice, this list of conditions and the following | ||
18 | * disclaimer. | ||
19 | * | ||
20 | * - Redistributions in binary form must reproduce the above | ||
21 | * copyright notice, this list of conditions and the following | ||
22 | * disclaimer in the documentation and/or other materials | ||
23 | * provided with the distribution. | ||
24 | * | ||
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | ||
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | ||
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | ||
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | ||
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | ||
32 | * SOFTWARE. | ||
33 | */ | ||
34 | |||
35 | #ifndef __T4_HW_H | ||
36 | #define __T4_HW_H | ||
37 | |||
38 | #include <linux/types.h> | ||
39 | |||
40 | enum { | ||
41 | NCHAN = 4, /* # of HW channels */ | ||
42 | MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */ | ||
43 | EEPROMSIZE = 17408, /* Serial EEPROM physical size */ | ||
44 | EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */ | ||
45 | RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */ | ||
46 | TCB_SIZE = 128, /* TCB size */ | ||
47 | NMTUS = 16, /* size of MTU table */ | ||
48 | NCCTRL_WIN = 32, /* # of congestion control windows */ | ||
49 | NEXACT_MAC = 336, /* # of exact MAC address filters */ | ||
50 | L2T_SIZE = 4096, /* # of L2T entries */ | ||
51 | MBOX_LEN = 64, /* mailbox size in bytes */ | ||
52 | TRACE_LEN = 112, /* length of trace data and mask */ | ||
53 | FILTER_OPT_LEN = 36, /* filter tuple width for optional components */ | ||
54 | NWOL_PAT = 8, /* # of WoL patterns */ | ||
55 | WOL_PAT_LEN = 128, /* length of WoL patterns */ | ||
56 | }; | ||
57 | |||
58 | enum { | ||
59 | SF_PAGE_SIZE = 256, /* serial flash page size */ | ||
60 | SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ | ||
61 | SF_SIZE = SF_SEC_SIZE * 16, /* serial flash size */ | ||
62 | }; | ||
63 | |||
64 | enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */ | ||
65 | |||
66 | enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */ | ||
67 | |||
68 | enum { | ||
69 | SGE_MAX_WR_LEN = 512, /* max WR size in bytes */ | ||
70 | SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */ | ||
71 | SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */ | ||
72 | }; | ||
73 | |||
74 | struct sge_qstat { /* data written to SGE queue status entries */ | ||
75 | __be32 qid; | ||
76 | __be16 cidx; | ||
77 | __be16 pidx; | ||
78 | }; | ||
79 | |||
80 | /* | ||
81 | * Structure for last 128 bits of response descriptors | ||
82 | */ | ||
83 | struct rsp_ctrl { | ||
84 | __be32 hdrbuflen_pidx; | ||
85 | __be32 pldbuflen_qid; | ||
86 | union { | ||
87 | u8 type_gen; | ||
88 | __be64 last_flit; | ||
89 | }; | ||
90 | }; | ||
91 | |||
92 | #define RSPD_NEWBUF 0x80000000U | ||
93 | #define RSPD_LEN 0x7fffffffU | ||
94 | |||
95 | #define RSPD_GEN(x) ((x) >> 7) | ||
96 | #define RSPD_TYPE(x) (((x) >> 4) & 3) | ||
97 | |||
98 | #define QINTR_CNT_EN 0x1 | ||
99 | #define QINTR_TIMER_IDX(x) ((x) << 1) | ||
100 | #endif /* __T4_HW_H */ | ||