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-rw-r--r--drivers/watchdog/ath79_wdt.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/watchdog/ath79_wdt.c b/drivers/watchdog/ath79_wdt.c
index 399c3fddecf6..0e67d96b3ebd 100644
--- a/drivers/watchdog/ath79_wdt.c
+++ b/drivers/watchdog/ath79_wdt.c
@@ -20,6 +20,7 @@
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 21
22#include <linux/bitops.h> 22#include <linux/bitops.h>
23#include <linux/delay.h>
23#include <linux/errno.h> 24#include <linux/errno.h>
24#include <linux/fs.h> 25#include <linux/fs.h>
25#include <linux/io.h> 26#include <linux/io.h>
@@ -90,6 +91,15 @@ static inline void ath79_wdt_keepalive(void)
90static inline void ath79_wdt_enable(void) 91static inline void ath79_wdt_enable(void)
91{ 92{
92 ath79_wdt_keepalive(); 93 ath79_wdt_keepalive();
94
95 /*
96 * Updating the TIMER register requires a few microseconds
97 * on the AR934x SoCs at least. Use a small delay to ensure
98 * that the TIMER register is updated within the hardware
99 * before enabling the watchdog.
100 */
101 udelay(2);
102
93 ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_FCR); 103 ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_FCR);
94 /* flush write */ 104 /* flush write */
95 ath79_wdt_rr(WDOG_REG_CTRL); 105 ath79_wdt_rr(WDOG_REG_CTRL);