diff options
Diffstat (limited to 'drivers/watchdog/davinci_wdt.c')
-rw-r--r-- | drivers/watchdog/davinci_wdt.c | 45 |
1 files changed, 25 insertions, 20 deletions
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c index 2e1360286732..c51d0b0ea0c4 100644 --- a/drivers/watchdog/davinci_wdt.c +++ b/drivers/watchdog/davinci_wdt.c | |||
@@ -24,7 +24,7 @@ | |||
24 | #include <linux/spinlock.h> | 24 | #include <linux/spinlock.h> |
25 | #include <linux/uaccess.h> | 25 | #include <linux/uaccess.h> |
26 | #include <linux/io.h> | 26 | #include <linux/io.h> |
27 | #include <mach/hardware.h> | 27 | #include <linux/device.h> |
28 | 28 | ||
29 | #define MODULE_NAME "DAVINCI-WDT: " | 29 | #define MODULE_NAME "DAVINCI-WDT: " |
30 | 30 | ||
@@ -75,9 +75,9 @@ static void wdt_service(void) | |||
75 | spin_lock(&io_lock); | 75 | spin_lock(&io_lock); |
76 | 76 | ||
77 | /* put watchdog in service state */ | 77 | /* put watchdog in service state */ |
78 | davinci_writel(WDKEY_SEQ0, wdt_base + WDTCR); | 78 | iowrite32(WDKEY_SEQ0, wdt_base + WDTCR); |
79 | /* put watchdog in active state */ | 79 | /* put watchdog in active state */ |
80 | davinci_writel(WDKEY_SEQ1, wdt_base + WDTCR); | 80 | iowrite32(WDKEY_SEQ1, wdt_base + WDTCR); |
81 | 81 | ||
82 | spin_unlock(&io_lock); | 82 | spin_unlock(&io_lock); |
83 | } | 83 | } |
@@ -90,29 +90,29 @@ static void wdt_enable(void) | |||
90 | spin_lock(&io_lock); | 90 | spin_lock(&io_lock); |
91 | 91 | ||
92 | /* disable, internal clock source */ | 92 | /* disable, internal clock source */ |
93 | davinci_writel(0, wdt_base + TCR); | 93 | iowrite32(0, wdt_base + TCR); |
94 | /* reset timer, set mode to 64-bit watchdog, and unreset */ | 94 | /* reset timer, set mode to 64-bit watchdog, and unreset */ |
95 | davinci_writel(0, wdt_base + TGCR); | 95 | iowrite32(0, wdt_base + TGCR); |
96 | tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET; | 96 | tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET; |
97 | davinci_writel(tgcr, wdt_base + TGCR); | 97 | iowrite32(tgcr, wdt_base + TGCR); |
98 | /* clear counter regs */ | 98 | /* clear counter regs */ |
99 | davinci_writel(0, wdt_base + TIM12); | 99 | iowrite32(0, wdt_base + TIM12); |
100 | davinci_writel(0, wdt_base + TIM34); | 100 | iowrite32(0, wdt_base + TIM34); |
101 | /* set timeout period */ | 101 | /* set timeout period */ |
102 | timer_margin = (((u64)heartbeat * CLOCK_TICK_RATE) & 0xffffffff); | 102 | timer_margin = (((u64)heartbeat * CLOCK_TICK_RATE) & 0xffffffff); |
103 | davinci_writel(timer_margin, wdt_base + PRD12); | 103 | iowrite32(timer_margin, wdt_base + PRD12); |
104 | timer_margin = (((u64)heartbeat * CLOCK_TICK_RATE) >> 32); | 104 | timer_margin = (((u64)heartbeat * CLOCK_TICK_RATE) >> 32); |
105 | davinci_writel(timer_margin, wdt_base + PRD34); | 105 | iowrite32(timer_margin, wdt_base + PRD34); |
106 | /* enable run continuously */ | 106 | /* enable run continuously */ |
107 | davinci_writel(ENAMODE12_PERIODIC, wdt_base + TCR); | 107 | iowrite32(ENAMODE12_PERIODIC, wdt_base + TCR); |
108 | /* Once the WDT is in pre-active state write to | 108 | /* Once the WDT is in pre-active state write to |
109 | * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are | 109 | * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are |
110 | * write protected (except for the WDKEY field) | 110 | * write protected (except for the WDKEY field) |
111 | */ | 111 | */ |
112 | /* put watchdog in pre-active state */ | 112 | /* put watchdog in pre-active state */ |
113 | davinci_writel(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR); | 113 | iowrite32(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR); |
114 | /* put watchdog in active state */ | 114 | /* put watchdog in active state */ |
115 | davinci_writel(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR); | 115 | iowrite32(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR); |
116 | 116 | ||
117 | spin_unlock(&io_lock); | 117 | spin_unlock(&io_lock); |
118 | } | 118 | } |
@@ -197,17 +197,16 @@ static int davinci_wdt_probe(struct platform_device *pdev) | |||
197 | { | 197 | { |
198 | int ret = 0, size; | 198 | int ret = 0, size; |
199 | struct resource *res; | 199 | struct resource *res; |
200 | struct device *dev = &pdev->dev; | ||
200 | 201 | ||
201 | if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT) | 202 | if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT) |
202 | heartbeat = DEFAULT_HEARTBEAT; | 203 | heartbeat = DEFAULT_HEARTBEAT; |
203 | 204 | ||
204 | printk(KERN_INFO MODULE_NAME | 205 | dev_info(dev, "heartbeat %d sec\n", heartbeat); |
205 | "DaVinci Watchdog Timer: heartbeat %d sec\n", heartbeat); | ||
206 | 206 | ||
207 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 207 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
208 | if (res == NULL) { | 208 | if (res == NULL) { |
209 | printk(KERN_INFO MODULE_NAME | 209 | dev_err(dev, "failed to get memory region resource\n"); |
210 | "failed to get memory region resource\n"); | ||
211 | return -ENOENT; | 210 | return -ENOENT; |
212 | } | 211 | } |
213 | 212 | ||
@@ -215,20 +214,26 @@ static int davinci_wdt_probe(struct platform_device *pdev) | |||
215 | wdt_mem = request_mem_region(res->start, size, pdev->name); | 214 | wdt_mem = request_mem_region(res->start, size, pdev->name); |
216 | 215 | ||
217 | if (wdt_mem == NULL) { | 216 | if (wdt_mem == NULL) { |
218 | printk(KERN_INFO MODULE_NAME "failed to get memory region\n"); | 217 | dev_err(dev, "failed to get memory region\n"); |
219 | return -ENOENT; | 218 | return -ENOENT; |
220 | } | 219 | } |
221 | wdt_base = (void __iomem *)(res->start); | 220 | |
221 | wdt_base = ioremap(res->start, size); | ||
222 | if (!wdt_base) { | ||
223 | dev_err(dev, "failed to map memory region\n"); | ||
224 | return -ENOMEM; | ||
225 | } | ||
222 | 226 | ||
223 | ret = misc_register(&davinci_wdt_miscdev); | 227 | ret = misc_register(&davinci_wdt_miscdev); |
224 | if (ret < 0) { | 228 | if (ret < 0) { |
225 | printk(KERN_ERR MODULE_NAME "cannot register misc device\n"); | 229 | dev_err(dev, "cannot register misc device\n"); |
226 | release_resource(wdt_mem); | 230 | release_resource(wdt_mem); |
227 | kfree(wdt_mem); | 231 | kfree(wdt_mem); |
228 | } else { | 232 | } else { |
229 | set_bit(WDT_DEVICE_INITED, &wdt_status); | 233 | set_bit(WDT_DEVICE_INITED, &wdt_status); |
230 | } | 234 | } |
231 | 235 | ||
236 | iounmap(wdt_base); | ||
232 | return ret; | 237 | return ret; |
233 | } | 238 | } |
234 | 239 | ||