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-rw-r--r--drivers/video/fsl-diu-fb.c104
1 files changed, 55 insertions, 49 deletions
diff --git a/drivers/video/fsl-diu-fb.c b/drivers/video/fsl-diu-fb.c
index 0f1933b54596..dbb4cb7124dc 100644
--- a/drivers/video/fsl-diu-fb.c
+++ b/drivers/video/fsl-diu-fb.c
@@ -223,53 +223,53 @@ struct mfb_info {
223 223
224static struct mfb_info mfb_template[] = { 224static struct mfb_info mfb_template[] = {
225 { /* AOI 0 for plane 0 */ 225 { /* AOI 0 for plane 0 */
226 .index = 0, 226 .index = 0,
227 .type = MFB_TYPE_OUTPUT, 227 .type = MFB_TYPE_OUTPUT,
228 .id = "Panel0", 228 .id = "Panel0",
229 .registered = 0, 229 .registered = 0,
230 .count = 0, 230 .count = 0,
231 .x_aoi_d = 0, 231 .x_aoi_d = 0,
232 .y_aoi_d = 0, 232 .y_aoi_d = 0,
233 }, 233 },
234 { /* AOI 0 for plane 1 */ 234 { /* AOI 0 for plane 1 */
235 .index = 1, 235 .index = 1,
236 .type = MFB_TYPE_OUTPUT, 236 .type = MFB_TYPE_OUTPUT,
237 .id = "Panel1 AOI0", 237 .id = "Panel1 AOI0",
238 .registered = 0, 238 .registered = 0,
239 .g_alpha = 0xff, 239 .g_alpha = 0xff,
240 .count = 0, 240 .count = 0,
241 .x_aoi_d = 0, 241 .x_aoi_d = 0,
242 .y_aoi_d = 0, 242 .y_aoi_d = 0,
243 }, 243 },
244 { /* AOI 1 for plane 1 */ 244 { /* AOI 1 for plane 1 */
245 .index = 2, 245 .index = 2,
246 .type = MFB_TYPE_OUTPUT, 246 .type = MFB_TYPE_OUTPUT,
247 .id = "Panel1 AOI1", 247 .id = "Panel1 AOI1",
248 .registered = 0, 248 .registered = 0,
249 .g_alpha = 0xff, 249 .g_alpha = 0xff,
250 .count = 0, 250 .count = 0,
251 .x_aoi_d = 0, 251 .x_aoi_d = 0,
252 .y_aoi_d = 480, 252 .y_aoi_d = 480,
253 }, 253 },
254 { /* AOI 0 for plane 2 */ 254 { /* AOI 0 for plane 2 */
255 .index = 3, 255 .index = 3,
256 .type = MFB_TYPE_OUTPUT, 256 .type = MFB_TYPE_OUTPUT,
257 .id = "Panel2 AOI0", 257 .id = "Panel2 AOI0",
258 .registered = 0, 258 .registered = 0,
259 .g_alpha = 0xff, 259 .g_alpha = 0xff,
260 .count = 0, 260 .count = 0,
261 .x_aoi_d = 640, 261 .x_aoi_d = 640,
262 .y_aoi_d = 0, 262 .y_aoi_d = 0,
263 }, 263 },
264 { /* AOI 1 for plane 2 */ 264 { /* AOI 1 for plane 2 */
265 .index = 4, 265 .index = 4,
266 .type = MFB_TYPE_OUTPUT, 266 .type = MFB_TYPE_OUTPUT,
267 .id = "Panel2 AOI1", 267 .id = "Panel2 AOI1",
268 .registered = 0, 268 .registered = 0,
269 .g_alpha = 0xff, 269 .g_alpha = 0xff,
270 .count = 0, 270 .count = 0,
271 .x_aoi_d = 640, 271 .x_aoi_d = 640,
272 .y_aoi_d = 480, 272 .y_aoi_d = 480,
273 }, 273 },
274}; 274};
275 275
@@ -715,8 +715,8 @@ static void update_lcdc(struct fb_info *info)
715 /* Prep for DIU init - gamma table, cursor table */ 715 /* Prep for DIU init - gamma table, cursor table */
716 716
717 for (i = 0; i <= 2; i++) 717 for (i = 0; i <= 2; i++)
718 for (j = 0; j <= 255; j++) 718 for (j = 0; j <= 255; j++)
719 *gamma_table_base++ = j; 719 *gamma_table_base++ = j;
720 720
721 diu_ops.set_gamma_table(machine_data->monitor_port, pool.gamma.vaddr); 721 diu_ops.set_gamma_table(machine_data->monitor_port, pool.gamma.vaddr);
722 722
@@ -887,7 +887,7 @@ static int fsl_diu_set_par(struct fb_info *info)
887 887
888static inline __u32 CNVT_TOHW(__u32 val, __u32 width) 888static inline __u32 CNVT_TOHW(__u32 val, __u32 width)
889{ 889{
890 return ((val<<width) + 0x7FFF - val)>>16; 890 return ((val << width) + 0x7FFF - val) >> 16;
891} 891}
892 892
893/* 893/*
@@ -899,8 +899,9 @@ static inline __u32 CNVT_TOHW(__u32 val, __u32 width)
899 * pseudo_palette in struct fb_info. For pseudocolor mode we have a limited 899 * pseudo_palette in struct fb_info. For pseudocolor mode we have a limited
900 * color palette. 900 * color palette.
901 */ 901 */
902static int fsl_diu_setcolreg(unsigned regno, unsigned red, unsigned green, 902static int fsl_diu_setcolreg(unsigned int regno, unsigned int red,
903 unsigned blue, unsigned transp, struct fb_info *info) 903 unsigned int green, unsigned int blue,
904 unsigned int transp, struct fb_info *info)
904{ 905{
905 int ret = 1; 906 int ret = 1;
906 907
@@ -1350,6 +1351,7 @@ static irqreturn_t fsl_diu_isr(int irq, void *dev_id)
1350#if defined(CONFIG_NOT_COHERENT_CACHE) 1351#if defined(CONFIG_NOT_COHERENT_CACHE)
1351 else if (status & INT_VSYNC) { 1352 else if (status & INT_VSYNC) {
1352 unsigned int i; 1353 unsigned int i;
1354
1353 for (i = 0; i < coherence_data_size; 1355 for (i = 0; i < coherence_data_size;
1354 i += d_cache_line_size) 1356 i += d_cache_line_size)
1355 __asm__ __volatile__ ( 1357 __asm__ __volatile__ (
@@ -1381,6 +1383,7 @@ static int request_irq_local(int irq)
1381#if !defined(CONFIG_NOT_COHERENT_CACHE) 1383#if !defined(CONFIG_NOT_COHERENT_CACHE)
1382 ints |= INT_VSYNC; 1384 ints |= INT_VSYNC;
1383#endif 1385#endif
1386
1384 if (dr.mode == MFB_MODE2 || dr.mode == MFB_MODE3) 1387 if (dr.mode == MFB_MODE2 || dr.mode == MFB_MODE3)
1385 ints |= INT_VSYNC_WB; 1388 ints |= INT_VSYNC_WB;
1386 1389
@@ -1388,6 +1391,7 @@ static int request_irq_local(int irq)
1388 status = in_be32(&hw->int_status); 1391 status = in_be32(&hw->int_status);
1389 out_be32(&hw->int_mask, ints); 1392 out_be32(&hw->int_mask, ints);
1390 } 1393 }
1394
1391 return ret; 1395 return ret;
1392} 1396}
1393 1397
@@ -1454,15 +1458,15 @@ static int allocate_buf(struct device *dev, struct diu_addr *buf, u32 size,
1454 buf->paddr = (u32)buf->paddr + offset; 1458 buf->paddr = (u32)buf->paddr + offset;
1455 } else 1459 } else
1456 buf->offset = 0; 1460 buf->offset = 0;
1461
1457 return 0; 1462 return 0;
1458} 1463}
1459 1464
1460static void free_buf(struct device *dev, struct diu_addr *buf, u32 size, 1465static void free_buf(struct device *dev, struct diu_addr *buf, u32 size,
1461 u32 bytes_align) 1466 u32 bytes_align)
1462{ 1467{
1463 dma_free_coherent(dev, size + bytes_align, 1468 dma_free_coherent(dev, size + bytes_align, buf->vaddr,
1464 buf->vaddr, (buf->paddr - buf->offset)); 1469 buf->paddr - buf->offset);
1465 return;
1466} 1470}
1467 1471
1468static ssize_t store_monitor(struct device *device, 1472static ssize_t store_monitor(struct device *device,
@@ -1798,8 +1802,9 @@ static int __init fsl_diu_init(void)
1798 return -ENODEV; 1802 return -ENODEV;
1799 } 1803 }
1800 1804
1801 /* Freescale PLRU requires 13/8 times the cache size to do a proper 1805 /*
1802 displacement flush 1806 * Freescale PLRU requires 13/8 times the cache size to do a proper
1807 * displacement flush
1803 */ 1808 */
1804 coherence_data_size = *prop * 13; 1809 coherence_data_size = *prop * 13;
1805 coherence_data_size /= 8; 1810 coherence_data_size /= 8;
@@ -1816,6 +1821,7 @@ static int __init fsl_diu_init(void)
1816 if (!coherence_data) 1821 if (!coherence_data)
1817 return -ENOMEM; 1822 return -ENOMEM;
1818#endif 1823#endif
1824
1819 ret = platform_driver_register(&fsl_diu_driver); 1825 ret = platform_driver_register(&fsl_diu_driver);
1820 if (ret) { 1826 if (ret) {
1821 printk(KERN_ERR 1827 printk(KERN_ERR