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-rw-r--r--drivers/video/omap2/dss/hdmi.c501
-rw-r--r--drivers/video/omap2/dss/hdmi.h292
2 files changed, 435 insertions, 358 deletions
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index b8e02e418c6d..bfd113ce3b47 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -43,11 +43,17 @@
43#include "hdmi.h" 43#include "hdmi.h"
44#include "dss_features.h" 44#include "dss_features.h"
45 45
46#define HDMI_WP 0x0
47#define HDMI_CORE_SYS 0x400
48#define HDMI_CORE_AV 0x900
49#define HDMI_PLLCTRL 0x200
50#define HDMI_PHY 0x300
51
46static struct { 52static struct {
47 struct mutex lock; 53 struct mutex lock;
48 struct omap_display_platform_data *pdata; 54 struct omap_display_platform_data *pdata;
49 struct platform_device *pdev; 55 struct platform_device *pdev;
50 void __iomem *base_wp; /* HDMI wrapper */ 56 struct hdmi_ip_data ip_data;
51 int code; 57 int code;
52 int mode; 58 int mode;
53 u8 edid[HDMI_EDID_MAX_LENGTH]; 59 u8 edid[HDMI_EDID_MAX_LENGTH];
@@ -145,21 +151,49 @@ static const int code_vesa[85] = {
145 151
146static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0}; 152static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0};
147 153
148static inline void hdmi_write_reg(const struct hdmi_reg idx, u32 val) 154static inline void hdmi_write_reg(void __iomem *base_addr,
155 const struct hdmi_reg idx, u32 val)
156{
157 __raw_writel(val, base_addr + idx.idx);
158}
159
160static inline u32 hdmi_read_reg(void __iomem *base_addr,
161 const struct hdmi_reg idx)
162{
163 return __raw_readl(base_addr + idx.idx);
164}
165
166static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
167{
168 return ip_data->base_wp;
169}
170
171static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data)
149{ 172{
150 __raw_writel(val, hdmi.base_wp + idx.idx); 173 return ip_data->base_wp + ip_data->phy_offset;
151} 174}
152 175
153static inline u32 hdmi_read_reg(const struct hdmi_reg idx) 176static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data)
154{ 177{
155 return __raw_readl(hdmi.base_wp + idx.idx); 178 return ip_data->base_wp + ip_data->pll_offset;
156} 179}
157 180
158static inline int hdmi_wait_for_bit_change(const struct hdmi_reg idx, 181static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data)
182{
183 return ip_data->base_wp + ip_data->core_av_offset;
184}
185
186static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
187{
188 return ip_data->base_wp + ip_data->core_sys_offset;
189}
190
191static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
192 const struct hdmi_reg idx,
159 int b2, int b1, u32 val) 193 int b2, int b1, u32 val)
160{ 194{
161 u32 t = 0; 195 u32 t = 0;
162 while (val != REG_GET(idx, b2, b1)) { 196 while (val != REG_GET(base_addr, idx, b2, b1)) {
163 udelay(1); 197 udelay(1);
164 if (t++ > 10000) 198 if (t++ > 10000)
165 return !val; 199 return !val;
@@ -195,21 +229,23 @@ int hdmi_init_display(struct omap_dss_device *dssdev)
195 return 0; 229 return 0;
196} 230}
197 231
198static int hdmi_pll_init(enum hdmi_clk_refsel refsel, int dcofreq, 232static int hdmi_pll_init(struct hdmi_ip_data *ip_data,
233 enum hdmi_clk_refsel refsel, int dcofreq,
199 struct hdmi_pll_info *fmt, u16 sd) 234 struct hdmi_pll_info *fmt, u16 sd)
200{ 235{
201 u32 r; 236 u32 r;
237 void __iomem *pll_base = hdmi_pll_base(ip_data);
202 238
203 /* PLL start always use manual mode */ 239 /* PLL start always use manual mode */
204 REG_FLD_MOD(PLLCTRL_PLL_CONTROL, 0x0, 0, 0); 240 REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
205 241
206 r = hdmi_read_reg(PLLCTRL_CFG1); 242 r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
207 r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */ 243 r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
208 r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */ 244 r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */
209 245
210 hdmi_write_reg(PLLCTRL_CFG1, r); 246 hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
211 247
212 r = hdmi_read_reg(PLLCTRL_CFG2); 248 r = hdmi_read_reg(pll_base, PLLCTRL_CFG2);
213 249
214 r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ 250 r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
215 r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ 251 r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
@@ -217,38 +253,40 @@ static int hdmi_pll_init(enum hdmi_clk_refsel refsel, int dcofreq,
217 253
218 if (dcofreq) { 254 if (dcofreq) {
219 /* divider programming for frequency beyond 1000Mhz */ 255 /* divider programming for frequency beyond 1000Mhz */
220 REG_FLD_MOD(PLLCTRL_CFG3, sd, 17, 10); 256 REG_FLD_MOD(pll_base, PLLCTRL_CFG3, sd, 17, 10);
221 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ 257 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
222 } else { 258 } else {
223 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ 259 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
224 } 260 }
225 261
226 hdmi_write_reg(PLLCTRL_CFG2, r); 262 hdmi_write_reg(pll_base, PLLCTRL_CFG2, r);
227 263
228 r = hdmi_read_reg(PLLCTRL_CFG4); 264 r = hdmi_read_reg(pll_base, PLLCTRL_CFG4);
229 r = FLD_MOD(r, fmt->regm2, 24, 18); 265 r = FLD_MOD(r, fmt->regm2, 24, 18);
230 r = FLD_MOD(r, fmt->regmf, 17, 0); 266 r = FLD_MOD(r, fmt->regmf, 17, 0);
231 267
232 hdmi_write_reg(PLLCTRL_CFG4, r); 268 hdmi_write_reg(pll_base, PLLCTRL_CFG4, r);
233 269
234 /* go now */ 270 /* go now */
235 REG_FLD_MOD(PLLCTRL_PLL_GO, 0x1, 0, 0); 271 REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0);
236 272
237 /* wait for bit change */ 273 /* wait for bit change */
238 if (hdmi_wait_for_bit_change(PLLCTRL_PLL_GO, 0, 0, 1) != 1) { 274 if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO,
275 0, 0, 1) != 1) {
239 DSSERR("PLL GO bit not set\n"); 276 DSSERR("PLL GO bit not set\n");
240 return -ETIMEDOUT; 277 return -ETIMEDOUT;
241 } 278 }
242 279
243 /* Wait till the lock bit is set in PLL status */ 280 /* Wait till the lock bit is set in PLL status */
244 if (hdmi_wait_for_bit_change(PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) { 281 if (hdmi_wait_for_bit_change(pll_base,
282 PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
245 DSSWARN("cannot lock PLL\n"); 283 DSSWARN("cannot lock PLL\n");
246 DSSWARN("CFG1 0x%x\n", 284 DSSWARN("CFG1 0x%x\n",
247 hdmi_read_reg(PLLCTRL_CFG1)); 285 hdmi_read_reg(pll_base, PLLCTRL_CFG1));
248 DSSWARN("CFG2 0x%x\n", 286 DSSWARN("CFG2 0x%x\n",
249 hdmi_read_reg(PLLCTRL_CFG2)); 287 hdmi_read_reg(pll_base, PLLCTRL_CFG2));
250 DSSWARN("CFG4 0x%x\n", 288 DSSWARN("CFG4 0x%x\n",
251 hdmi_read_reg(PLLCTRL_CFG4)); 289 hdmi_read_reg(pll_base, PLLCTRL_CFG4));
252 return -ETIMEDOUT; 290 return -ETIMEDOUT;
253 } 291 }
254 292
@@ -258,13 +296,14 @@ static int hdmi_pll_init(enum hdmi_clk_refsel refsel, int dcofreq,
258} 296}
259 297
260/* PHY_PWR_CMD */ 298/* PHY_PWR_CMD */
261static int hdmi_set_phy_pwr(enum hdmi_phy_pwr val) 299static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val)
262{ 300{
263 /* Command for power control of HDMI PHY */ 301 /* Command for power control of HDMI PHY */
264 REG_FLD_MOD(HDMI_WP_PWR_CTRL, val, 7, 6); 302 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6);
265 303
266 /* Status of the power control of HDMI PHY */ 304 /* Status of the power control of HDMI PHY */
267 if (hdmi_wait_for_bit_change(HDMI_WP_PWR_CTRL, 5, 4, val) != val) { 305 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data),
306 HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
268 DSSERR("Failed to set PHY power mode to %d\n", val); 307 DSSERR("Failed to set PHY power mode to %d\n", val);
269 return -ETIMEDOUT; 308 return -ETIMEDOUT;
270 } 309 }
@@ -273,13 +312,14 @@ static int hdmi_set_phy_pwr(enum hdmi_phy_pwr val)
273} 312}
274 313
275/* PLL_PWR_CMD */ 314/* PLL_PWR_CMD */
276static int hdmi_set_pll_pwr(enum hdmi_pll_pwr val) 315int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val)
277{ 316{
278 /* Command for power control of HDMI PLL */ 317 /* Command for power control of HDMI PLL */
279 REG_FLD_MOD(HDMI_WP_PWR_CTRL, val, 3, 2); 318 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2);
280 319
281 /* wait till PHY_PWR_STATUS is set */ 320 /* wait till PHY_PWR_STATUS is set */
282 if (hdmi_wait_for_bit_change(HDMI_WP_PWR_CTRL, 1, 0, val) != val) { 321 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL,
322 1, 0, val) != val) {
283 DSSERR("Failed to set PHY_PWR_STATUS\n"); 323 DSSERR("Failed to set PHY_PWR_STATUS\n");
284 return -ETIMEDOUT; 324 return -ETIMEDOUT;
285 } 325 }
@@ -287,13 +327,14 @@ static int hdmi_set_pll_pwr(enum hdmi_pll_pwr val)
287 return 0; 327 return 0;
288} 328}
289 329
290static int hdmi_pll_reset(void) 330static int hdmi_pll_reset(struct hdmi_ip_data *ip_data)
291{ 331{
292 /* SYSRESET controlled by power FSM */ 332 /* SYSRESET controlled by power FSM */
293 REG_FLD_MOD(PLLCTRL_PLL_CONTROL, 0x0, 3, 3); 333 REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
294 334
295 /* READ 0x0 reset is in progress */ 335 /* READ 0x0 reset is in progress */
296 if (hdmi_wait_for_bit_change(PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) { 336 if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data),
337 PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
297 DSSERR("Failed to sysreset PLL\n"); 338 DSSERR("Failed to sysreset PLL\n");
298 return -ETIMEDOUT; 339 return -ETIMEDOUT;
299 } 340 }
@@ -301,15 +342,16 @@ static int hdmi_pll_reset(void)
301 return 0; 342 return 0;
302} 343}
303 344
304static int hdmi_phy_init(void) 345static int hdmi_phy_init(struct hdmi_ip_data *ip_data)
305{ 346{
306 u16 r = 0; 347 u16 r = 0;
348 void __iomem *phy_base = hdmi_phy_base(ip_data);
307 349
308 r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_LDOON); 350 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
309 if (r) 351 if (r)
310 return r; 352 return r;
311 353
312 r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_TXON); 354 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON);
313 if (r) 355 if (r)
314 return r; 356 return r;
315 357
@@ -317,65 +359,68 @@ static int hdmi_phy_init(void)
317 * Read address 0 in order to get the SCP reset done completed 359 * Read address 0 in order to get the SCP reset done completed
318 * Dummy access performed to make sure reset is done 360 * Dummy access performed to make sure reset is done
319 */ 361 */
320 hdmi_read_reg(HDMI_TXPHY_TX_CTRL); 362 hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL);
321 363
322 /* 364 /*
323 * Write to phy address 0 to configure the clock 365 * Write to phy address 0 to configure the clock
324 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field 366 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
325 */ 367 */
326 REG_FLD_MOD(HDMI_TXPHY_TX_CTRL, 0x1, 31, 30); 368 REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
327 369
328 /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */ 370 /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
329 hdmi_write_reg(HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); 371 hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
330 372
331 /* Setup max LDO voltage */ 373 /* Setup max LDO voltage */
332 REG_FLD_MOD(HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); 374 REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
333 375
334 /* Write to phy address 3 to change the polarity control */ 376 /* Write to phy address 3 to change the polarity control */
335 REG_FLD_MOD(HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27); 377 REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
336 378
337 return 0; 379 return 0;
338} 380}
339 381
340static int hdmi_pll_program(struct hdmi_pll_info *fmt) 382static int hdmi_pll_program(struct hdmi_ip_data *ip_data,
383 struct hdmi_pll_info *fmt)
341{ 384{
342 u16 r = 0; 385 u16 r = 0;
343 enum hdmi_clk_refsel refsel; 386 enum hdmi_clk_refsel refsel;
344 387
345 r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF); 388 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
346 if (r) 389 if (r)
347 return r; 390 return r;
348 391
349 r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_BOTHON_ALLCLKS); 392 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
350 if (r) 393 if (r)
351 return r; 394 return r;
352 395
353 r = hdmi_pll_reset(); 396 r = hdmi_pll_reset(ip_data);
354 if (r) 397 if (r)
355 return r; 398 return r;
356 399
357 refsel = HDMI_REFSEL_SYSCLK; 400 refsel = HDMI_REFSEL_SYSCLK;
358 401
359 r = hdmi_pll_init(refsel, fmt->dcofreq, fmt, fmt->regsd); 402 r = hdmi_pll_init(ip_data, refsel, fmt->dcofreq, fmt, fmt->regsd);
360 if (r) 403 if (r)
361 return r; 404 return r;
362 405
363 return 0; 406 return 0;
364} 407}
365 408
366static void hdmi_phy_off(void) 409static void hdmi_phy_off(struct hdmi_ip_data *ip_data)
367{ 410{
368 hdmi_set_phy_pwr(HDMI_PHYPWRCMD_OFF); 411 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
369} 412}
370 413
371static int hdmi_core_ddc_edid(u8 *pedid, int ext) 414static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data,
415 u8 *pedid, int ext)
372{ 416{
373 u32 i, j; 417 u32 i, j;
374 char checksum = 0; 418 char checksum = 0;
375 u32 offset = 0; 419 u32 offset = 0;
420 void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
376 421
377 /* Turn on CLK for DDC */ 422 /* Turn on CLK for DDC */
378 REG_FLD_MOD(HDMI_CORE_AV_DPD, 0x7, 2, 0); 423 REG_FLD_MOD(hdmi_av_base(ip_data), HDMI_CORE_AV_DPD, 0x7, 2, 0);
379 424
380 /* 425 /*
381 * SW HACK : Without the Delay DDC(i2c bus) reads 0 values / 426 * SW HACK : Without the Delay DDC(i2c bus) reads 0 values /
@@ -386,21 +431,21 @@ static int hdmi_core_ddc_edid(u8 *pedid, int ext)
386 431
387 if (!ext) { 432 if (!ext) {
388 /* Clk SCL Devices */ 433 /* Clk SCL Devices */
389 REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0xA, 3, 0); 434 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
390 435
391 /* HDMI_CORE_DDC_STATUS_IN_PROG */ 436 /* HDMI_CORE_DDC_STATUS_IN_PROG */
392 if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS, 437 if (hdmi_wait_for_bit_change(core_sys_base,
393 4, 4, 0) != 0) { 438 HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) {
394 DSSERR("Failed to program DDC\n"); 439 DSSERR("Failed to program DDC\n");
395 return -ETIMEDOUT; 440 return -ETIMEDOUT;
396 } 441 }
397 442
398 /* Clear FIFO */ 443 /* Clear FIFO */
399 REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x9, 3, 0); 444 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
400 445
401 /* HDMI_CORE_DDC_STATUS_IN_PROG */ 446 /* HDMI_CORE_DDC_STATUS_IN_PROG */
402 if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS, 447 if (hdmi_wait_for_bit_change(core_sys_base,
403 4, 4, 0) != 0) { 448 HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) {
404 DSSERR("Failed to program DDC\n"); 449 DSSERR("Failed to program DDC\n");
405 return -ETIMEDOUT; 450 return -ETIMEDOUT;
406 } 451 }
@@ -411,44 +456,45 @@ static int hdmi_core_ddc_edid(u8 *pedid, int ext)
411 } 456 }
412 457
413 /* Load Segment Address Register */ 458 /* Load Segment Address Register */
414 REG_FLD_MOD(HDMI_CORE_DDC_SEGM, ext/2, 7, 0); 459 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_SEGM, ext/2, 7, 0);
415 460
416 /* Load Slave Address Register */ 461 /* Load Slave Address Register */
417 REG_FLD_MOD(HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); 462 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
418 463
419 /* Load Offset Address Register */ 464 /* Load Offset Address Register */
420 REG_FLD_MOD(HDMI_CORE_DDC_OFFSET, offset, 7, 0); 465 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
421 466
422 /* Load Byte Count */ 467 /* Load Byte Count */
423 REG_FLD_MOD(HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); 468 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
424 REG_FLD_MOD(HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); 469 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
425 470
426 /* Set DDC_CMD */ 471 /* Set DDC_CMD */
427 if (ext) 472 if (ext)
428 REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x4, 3, 0); 473 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
429 else 474 else
430 REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x2, 3, 0); 475 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
431 476
432 /* HDMI_CORE_DDC_STATUS_BUS_LOW */ 477 /* HDMI_CORE_DDC_STATUS_BUS_LOW */
433 if (REG_GET(HDMI_CORE_DDC_STATUS, 6, 6) == 1) { 478 if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
434 DSSWARN("I2C Bus Low?\n"); 479 DSSWARN("I2C Bus Low?\n");
435 return -EIO; 480 return -EIO;
436 } 481 }
437 /* HDMI_CORE_DDC_STATUS_NO_ACK */ 482 /* HDMI_CORE_DDC_STATUS_NO_ACK */
438 if (REG_GET(HDMI_CORE_DDC_STATUS, 5, 5) == 1) { 483 if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
439 DSSWARN("I2C No Ack\n"); 484 DSSWARN("I2C No Ack\n");
440 return -EIO; 485 return -EIO;
441 } 486 }
442 487
443 i = ext * 128; 488 i = ext * 128;
444 j = 0; 489 j = 0;
445 while (((REG_GET(HDMI_CORE_DDC_STATUS, 4, 4) == 1) || 490 while (((REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) ||
446 (REG_GET(HDMI_CORE_DDC_STATUS, 2, 2) == 0)) && 491 (REG_GET(core_sys_base,
447 j < 128) { 492 HDMI_CORE_DDC_STATUS, 2, 2) == 0)) && j < 128) {
448 493
449 if (REG_GET(HDMI_CORE_DDC_STATUS, 2, 2) == 0) { 494 if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 2, 2) == 0) {
450 /* FIFO not empty */ 495 /* FIFO not empty */
451 pedid[i++] = REG_GET(HDMI_CORE_DDC_DATA, 7, 0); 496 pedid[i++] = REG_GET(core_sys_base,
497 HDMI_CORE_DDC_DATA, 7, 0);
452 j++; 498 j++;
453 } 499 }
454 } 500 }
@@ -464,12 +510,12 @@ static int hdmi_core_ddc_edid(u8 *pedid, int ext)
464 return 0; 510 return 0;
465} 511}
466 512
467static int read_edid(u8 *pedid, u16 max_length) 513static int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length)
468{ 514{
469 int r = 0, n = 0, i = 0; 515 int r = 0, n = 0, i = 0;
470 int max_ext_blocks = (max_length / 128) - 1; 516 int max_ext_blocks = (max_length / 128) - 1;
471 517
472 r = hdmi_core_ddc_edid(pedid, 0); 518 r = hdmi_core_ddc_edid(ip_data, pedid, 0);
473 if (r) { 519 if (r) {
474 return r; 520 return r;
475 } else { 521 } else {
@@ -485,7 +531,7 @@ static int read_edid(u8 *pedid, u16 max_length)
485 n = max_ext_blocks; 531 n = max_ext_blocks;
486 532
487 for (i = 1; i <= n; i++) { 533 for (i = 1; i <= n; i++) {
488 r = hdmi_core_ddc_edid(pedid, i); 534 r = hdmi_core_ddc_edid(ip_data, pedid, i);
489 if (r) 535 if (r)
490 return r; 536 return r;
491 } 537 }
@@ -655,8 +701,8 @@ static void hdmi_read_edid(struct omap_video_timings *dp)
655 memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH); 701 memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH);
656 702
657 if (!hdmi.edid_set) 703 if (!hdmi.edid_set)
658 ret = read_edid(hdmi.edid, HDMI_EDID_MAX_LENGTH); 704 ret = read_edid(&hdmi.ip_data, hdmi.edid,
659 705 HDMI_EDID_MAX_LENGTH);
660 if (!ret) { 706 if (!ret) {
661 if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) { 707 if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) {
662 /* search for timings of default resolution */ 708 /* search for timings of default resolution */
@@ -722,41 +768,44 @@ static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
722 repeat_cfg->generic_pkt_repeat = 0; 768 repeat_cfg->generic_pkt_repeat = 0;
723} 769}
724 770
725static void hdmi_core_powerdown_disable(void) 771static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data)
726{ 772{
727 DSSDBG("Enter hdmi_core_powerdown_disable\n"); 773 DSSDBG("Enter hdmi_core_powerdown_disable\n");
728 REG_FLD_MOD(HDMI_CORE_CTRL1, 0x0, 0, 0); 774 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0);
729} 775}
730 776
731static void hdmi_core_swreset_release(void) 777static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data)
732{ 778{
733 DSSDBG("Enter hdmi_core_swreset_release\n"); 779 DSSDBG("Enter hdmi_core_swreset_release\n");
734 REG_FLD_MOD(HDMI_CORE_SYS_SRST, 0x0, 0, 0); 780 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0);
735} 781}
736 782
737static void hdmi_core_swreset_assert(void) 783static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data)
738{ 784{
739 DSSDBG("Enter hdmi_core_swreset_assert\n"); 785 DSSDBG("Enter hdmi_core_swreset_assert\n");
740 REG_FLD_MOD(HDMI_CORE_SYS_SRST, 0x1, 0, 0); 786 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0);
741} 787}
742 788
743/* DSS_HDMI_CORE_VIDEO_CONFIG */ 789/* HDMI_CORE_VIDEO_CONFIG */
744static void hdmi_core_video_config(struct hdmi_core_video_config *cfg) 790static void hdmi_core_video_config(struct hdmi_ip_data *ip_data,
791 struct hdmi_core_video_config *cfg)
745{ 792{
746 u32 r = 0; 793 u32 r = 0;
794 void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
747 795
748 /* sys_ctrl1 default configuration not tunable */ 796 /* sys_ctrl1 default configuration not tunable */
749 r = hdmi_read_reg(HDMI_CORE_CTRL1); 797 r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1);
750 r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5); 798 r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
751 r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4); 799 r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
752 r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2); 800 r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
753 r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1); 801 r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
754 hdmi_write_reg(HDMI_CORE_CTRL1, r); 802 hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r);
755 803
756 REG_FLD_MOD(HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); 804 REG_FLD_MOD(core_sys_base,
805 HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
757 806
758 /* Vid_Mode */ 807 /* Vid_Mode */
759 r = hdmi_read_reg(HDMI_CORE_SYS_VID_MODE); 808 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
760 809
761 /* dither truncation configuration */ 810 /* dither truncation configuration */
762 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) { 811 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
@@ -766,106 +815,108 @@ static void hdmi_core_video_config(struct hdmi_core_video_config *cfg)
766 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); 815 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
767 r = FLD_MOD(r, 0, 5, 5); 816 r = FLD_MOD(r, 0, 5, 5);
768 } 817 }
769 hdmi_write_reg(HDMI_CORE_SYS_VID_MODE, r); 818 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
770 819
771 /* HDMI_Ctrl */ 820 /* HDMI_Ctrl */
772 r = hdmi_read_reg(HDMI_CORE_AV_HDMI_CTRL); 821 r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL);
773 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); 822 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
774 r = FLD_MOD(r, cfg->pkt_mode, 5, 3); 823 r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
775 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); 824 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
776 hdmi_write_reg(HDMI_CORE_AV_HDMI_CTRL, r); 825 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r);
777 826
778 /* TMDS_CTRL */ 827 /* TMDS_CTRL */
779 REG_FLD_MOD(HDMI_CORE_SYS_TMDS_CTRL, 828 REG_FLD_MOD(core_sys_base,
780 cfg->tclk_sel_clkmult, 6, 5); 829 HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
781} 830}
782 831
783static void hdmi_core_aux_infoframe_avi_config( 832static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data,
784 struct hdmi_core_infoframe_avi info_avi) 833 struct hdmi_core_infoframe_avi info_avi)
785{ 834{
786 u32 val; 835 u32 val;
787 char sum = 0, checksum = 0; 836 char sum = 0, checksum = 0;
837 void __iomem *av_base = hdmi_av_base(ip_data);
788 838
789 sum += 0x82 + 0x002 + 0x00D; 839 sum += 0x82 + 0x002 + 0x00D;
790 hdmi_write_reg(HDMI_CORE_AV_AVI_TYPE, 0x082); 840 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
791 hdmi_write_reg(HDMI_CORE_AV_AVI_VERS, 0x002); 841 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002);
792 hdmi_write_reg(HDMI_CORE_AV_AVI_LEN, 0x00D); 842 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D);
793 843
794 val = (info_avi.db1_format << 5) | 844 val = (info_avi.db1_format << 5) |
795 (info_avi.db1_active_info << 4) | 845 (info_avi.db1_active_info << 4) |
796 (info_avi.db1_bar_info_dv << 2) | 846 (info_avi.db1_bar_info_dv << 2) |
797 (info_avi.db1_scan_info); 847 (info_avi.db1_scan_info);
798 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(0), val); 848 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val);
799 sum += val; 849 sum += val;
800 850
801 val = (info_avi.db2_colorimetry << 6) | 851 val = (info_avi.db2_colorimetry << 6) |
802 (info_avi.db2_aspect_ratio << 4) | 852 (info_avi.db2_aspect_ratio << 4) |
803 (info_avi.db2_active_fmt_ar); 853 (info_avi.db2_active_fmt_ar);
804 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(1), val); 854 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val);
805 sum += val; 855 sum += val;
806 856
807 val = (info_avi.db3_itc << 7) | 857 val = (info_avi.db3_itc << 7) |
808 (info_avi.db3_ec << 4) | 858 (info_avi.db3_ec << 4) |
809 (info_avi.db3_q_range << 2) | 859 (info_avi.db3_q_range << 2) |
810 (info_avi.db3_nup_scaling); 860 (info_avi.db3_nup_scaling);
811 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(2), val); 861 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val);
812 sum += val; 862 sum += val;
813 863
814 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(3), info_avi.db4_videocode); 864 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3),
865 info_avi.db4_videocode);
815 sum += info_avi.db4_videocode; 866 sum += info_avi.db4_videocode;
816 867
817 val = info_avi.db5_pixel_repeat; 868 val = info_avi.db5_pixel_repeat;
818 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(4), val); 869 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val);
819 sum += val; 870 sum += val;
820 871
821 val = info_avi.db6_7_line_eoftop & 0x00FF; 872 val = info_avi.db6_7_line_eoftop & 0x00FF;
822 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(5), val); 873 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val);
823 sum += val; 874 sum += val;
824 875
825 val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF); 876 val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
826 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(6), val); 877 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val);
827 sum += val; 878 sum += val;
828 879
829 val = info_avi.db8_9_line_sofbottom & 0x00FF; 880 val = info_avi.db8_9_line_sofbottom & 0x00FF;
830 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(7), val); 881 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val);
831 sum += val; 882 sum += val;
832 883
833 val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF); 884 val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
834 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(8), val); 885 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val);
835 sum += val; 886 sum += val;
836 887
837 val = info_avi.db10_11_pixel_eofleft & 0x00FF; 888 val = info_avi.db10_11_pixel_eofleft & 0x00FF;
838 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(9), val); 889 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val);
839 sum += val; 890 sum += val;
840 891
841 val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF); 892 val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
842 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(10), val); 893 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val);
843 sum += val; 894 sum += val;
844 895
845 val = info_avi.db12_13_pixel_sofright & 0x00FF; 896 val = info_avi.db12_13_pixel_sofright & 0x00FF;
846 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(11), val); 897 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val);
847 sum += val; 898 sum += val;
848 899
849 val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF); 900 val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
850 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(12), val); 901 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val);
851 sum += val; 902 sum += val;
852 903
853 checksum = 0x100 - sum; 904 checksum = 0x100 - sum;
854 hdmi_write_reg(HDMI_CORE_AV_AVI_CHSUM, checksum); 905 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum);
855} 906}
856 907
857static void hdmi_core_av_packet_config( 908static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data,
858 struct hdmi_core_packet_enable_repeat repeat_cfg) 909 struct hdmi_core_packet_enable_repeat repeat_cfg)
859{ 910{
860 /* enable/repeat the infoframe */ 911 /* enable/repeat the infoframe */
861 hdmi_write_reg(HDMI_CORE_AV_PB_CTRL1, 912 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1,
862 (repeat_cfg.audio_pkt << 5) | 913 (repeat_cfg.audio_pkt << 5) |
863 (repeat_cfg.audio_pkt_repeat << 4) | 914 (repeat_cfg.audio_pkt_repeat << 4) |
864 (repeat_cfg.avi_infoframe << 1) | 915 (repeat_cfg.avi_infoframe << 1) |
865 (repeat_cfg.avi_infoframe_repeat)); 916 (repeat_cfg.avi_infoframe_repeat));
866 917
867 /* enable/repeat the packet */ 918 /* enable/repeat the packet */
868 hdmi_write_reg(HDMI_CORE_AV_PB_CTRL2, 919 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2,
869 (repeat_cfg.gen_cntrl_pkt << 3) | 920 (repeat_cfg.gen_cntrl_pkt << 3) |
870 (repeat_cfg.gen_cntrl_pkt_repeat << 2) | 921 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
871 (repeat_cfg.generic_pkt << 1) | 922 (repeat_cfg.generic_pkt << 1) |
@@ -897,9 +948,9 @@ static void hdmi_wp_init(struct omap_video_timings *timings,
897 948
898} 949}
899 950
900static void hdmi_wp_video_start(bool start) 951static void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start)
901{ 952{
902 REG_FLD_MOD(HDMI_WP_VIDEO_CFG, start, 31, 31); 953 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, start, 31, 31);
903} 954}
904 955
905static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt, 956static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
@@ -918,33 +969,34 @@ static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
918 timings->vsw = param->timings.timings.vsw; 969 timings->vsw = param->timings.timings.vsw;
919} 970}
920 971
921static void hdmi_wp_video_config_format( 972static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
922 struct hdmi_video_format *video_fmt) 973 struct hdmi_video_format *video_fmt)
923{ 974{
924 u32 l = 0; 975 u32 l = 0;
925 976
926 REG_FLD_MOD(HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, 10, 8); 977 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG,
978 video_fmt->packing_mode, 10, 8);
927 979
928 l |= FLD_VAL(video_fmt->y_res, 31, 16); 980 l |= FLD_VAL(video_fmt->y_res, 31, 16);
929 l |= FLD_VAL(video_fmt->x_res, 15, 0); 981 l |= FLD_VAL(video_fmt->x_res, 15, 0);
930 hdmi_write_reg(HDMI_WP_VIDEO_SIZE, l); 982 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l);
931} 983}
932 984
933static void hdmi_wp_video_config_interface( 985static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data,
934 struct hdmi_video_interface *video_int) 986 struct hdmi_video_interface *video_int)
935{ 987{
936 u32 r; 988 u32 r;
937 DSSDBG("Enter hdmi_wp_video_config_interface\n"); 989 DSSDBG("Enter hdmi_wp_video_config_interface\n");
938 990
939 r = hdmi_read_reg(HDMI_WP_VIDEO_CFG); 991 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
940 r = FLD_MOD(r, video_int->vsp, 7, 7); 992 r = FLD_MOD(r, video_int->vsp, 7, 7);
941 r = FLD_MOD(r, video_int->hsp, 6, 6); 993 r = FLD_MOD(r, video_int->hsp, 6, 6);
942 r = FLD_MOD(r, video_int->interlacing, 3, 3); 994 r = FLD_MOD(r, video_int->interlacing, 3, 3);
943 r = FLD_MOD(r, video_int->tm, 1, 0); 995 r = FLD_MOD(r, video_int->tm, 1, 0);
944 hdmi_write_reg(HDMI_WP_VIDEO_CFG, r); 996 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
945} 997}
946 998
947static void hdmi_wp_video_config_timing( 999static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data,
948 struct omap_video_timings *timings) 1000 struct omap_video_timings *timings)
949{ 1001{
950 u32 timing_h = 0; 1002 u32 timing_h = 0;
@@ -955,15 +1007,16 @@ static void hdmi_wp_video_config_timing(
955 timing_h |= FLD_VAL(timings->hbp, 31, 20); 1007 timing_h |= FLD_VAL(timings->hbp, 31, 20);
956 timing_h |= FLD_VAL(timings->hfp, 19, 8); 1008 timing_h |= FLD_VAL(timings->hfp, 19, 8);
957 timing_h |= FLD_VAL(timings->hsw, 7, 0); 1009 timing_h |= FLD_VAL(timings->hsw, 7, 0);
958 hdmi_write_reg(HDMI_WP_VIDEO_TIMING_H, timing_h); 1010 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h);
959 1011
960 timing_v |= FLD_VAL(timings->vbp, 31, 20); 1012 timing_v |= FLD_VAL(timings->vbp, 31, 20);
961 timing_v |= FLD_VAL(timings->vfp, 19, 8); 1013 timing_v |= FLD_VAL(timings->vfp, 19, 8);
962 timing_v |= FLD_VAL(timings->vsw, 7, 0); 1014 timing_v |= FLD_VAL(timings->vsw, 7, 0);
963 hdmi_write_reg(HDMI_WP_VIDEO_TIMING_V, timing_v); 1015 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
964} 1016}
965 1017
966static void hdmi_basic_configure(struct hdmi_config *cfg) 1018static void hdmi_basic_configure(struct hdmi_ip_data *ip_data,
1019 struct hdmi_config *cfg)
967{ 1020{
968 /* HDMI */ 1021 /* HDMI */
969 struct omap_video_timings video_timing; 1022 struct omap_video_timings video_timing;
@@ -984,36 +1037,36 @@ static void hdmi_basic_configure(struct hdmi_config *cfg)
984 hdmi_wp_video_init_format(&video_format, 1037 hdmi_wp_video_init_format(&video_format,
985 &video_timing, cfg); 1038 &video_timing, cfg);
986 1039
987 hdmi_wp_video_config_timing(&video_timing); 1040 hdmi_wp_video_config_timing(ip_data, &video_timing);
988 1041
989 /* video config */ 1042 /* video config */
990 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; 1043 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
991 1044
992 hdmi_wp_video_config_format(&video_format); 1045 hdmi_wp_video_config_format(ip_data, &video_format);
993 1046
994 video_interface.vsp = cfg->timings.vsync_pol; 1047 video_interface.vsp = cfg->timings.vsync_pol;
995 video_interface.hsp = cfg->timings.hsync_pol; 1048 video_interface.hsp = cfg->timings.hsync_pol;
996 video_interface.interlacing = cfg->interlace; 1049 video_interface.interlacing = cfg->interlace;
997 video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */ 1050 video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */
998 1051
999 hdmi_wp_video_config_interface(&video_interface); 1052 hdmi_wp_video_config_interface(ip_data, &video_interface);
1000 1053
1001 /* 1054 /*
1002 * configure core video part 1055 * configure core video part
1003 * set software reset in the core 1056 * set software reset in the core
1004 */ 1057 */
1005 hdmi_core_swreset_assert(); 1058 hdmi_core_swreset_assert(ip_data);
1006 1059
1007 /* power down off */ 1060 /* power down off */
1008 hdmi_core_powerdown_disable(); 1061 hdmi_core_powerdown_disable(ip_data);
1009 1062
1010 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; 1063 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
1011 v_core_cfg.hdmi_dvi = cfg->cm.mode; 1064 v_core_cfg.hdmi_dvi = cfg->cm.mode;
1012 1065
1013 hdmi_core_video_config(&v_core_cfg); 1066 hdmi_core_video_config(ip_data, &v_core_cfg);
1014 1067
1015 /* release software reset in the core */ 1068 /* release software reset in the core */
1016 hdmi_core_swreset_release(); 1069 hdmi_core_swreset_release(ip_data);
1017 1070
1018 /* 1071 /*
1019 * configure packet 1072 * configure packet
@@ -1038,7 +1091,7 @@ static void hdmi_basic_configure(struct hdmi_config *cfg)
1038 avi_cfg.db10_11_pixel_eofleft = 0; 1091 avi_cfg.db10_11_pixel_eofleft = 0;
1039 avi_cfg.db12_13_pixel_sofright = 0; 1092 avi_cfg.db12_13_pixel_sofright = 0;
1040 1093
1041 hdmi_core_aux_infoframe_avi_config(avi_cfg); 1094 hdmi_core_aux_infoframe_avi_config(ip_data, avi_cfg);
1042 1095
1043 /* enable/repeat the infoframe */ 1096 /* enable/repeat the infoframe */
1044 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; 1097 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
@@ -1046,7 +1099,7 @@ static void hdmi_basic_configure(struct hdmi_config *cfg)
1046 /* wakeup */ 1099 /* wakeup */
1047 repeat_cfg.audio_pkt = HDMI_PACKETENABLE; 1100 repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
1048 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; 1101 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
1049 hdmi_core_av_packet_config(repeat_cfg); 1102 hdmi_core_av_packet_config(ip_data, repeat_cfg);
1050} 1103}
1051 1104
1052static void update_hdmi_timings(struct hdmi_config *cfg, 1105static void update_hdmi_timings(struct hdmi_config *cfg,
@@ -1136,16 +1189,16 @@ static int hdmi_power_on(struct omap_dss_device *dssdev)
1136 1189
1137 hdmi_compute_pll(dssdev, phy, &pll_data); 1190 hdmi_compute_pll(dssdev, phy, &pll_data);
1138 1191
1139 hdmi_wp_video_start(0); 1192 hdmi_wp_video_start(&hdmi.ip_data, 0);
1140 1193
1141 /* config the PLL and PHY first */ 1194 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
1142 r = hdmi_pll_program(&pll_data); 1195 r = hdmi_pll_program(&hdmi.ip_data, &pll_data);
1143 if (r) { 1196 if (r) {
1144 DSSDBG("Failed to lock PLL\n"); 1197 DSSDBG("Failed to lock PLL\n");
1145 goto err; 1198 goto err;
1146 } 1199 }
1147 1200
1148 r = hdmi_phy_init(); 1201 r = hdmi_phy_init(&hdmi.ip_data);
1149 if (r) { 1202 if (r) {
1150 DSSDBG("Failed to start PHY\n"); 1203 DSSDBG("Failed to start PHY\n");
1151 goto err; 1204 goto err;
@@ -1153,7 +1206,7 @@ static int hdmi_power_on(struct omap_dss_device *dssdev)
1153 1206
1154 hdmi.cfg.cm.mode = hdmi.mode; 1207 hdmi.cfg.cm.mode = hdmi.mode;
1155 hdmi.cfg.cm.code = hdmi.code; 1208 hdmi.cfg.cm.code = hdmi.code;
1156 hdmi_basic_configure(&hdmi.cfg); 1209 hdmi_basic_configure(&hdmi.ip_data, &hdmi.cfg);
1157 1210
1158 /* Make selection of HDMI in DSS */ 1211 /* Make selection of HDMI in DSS */
1159 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); 1212 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
@@ -1175,7 +1228,7 @@ static int hdmi_power_on(struct omap_dss_device *dssdev)
1175 1228
1176 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 1); 1229 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 1);
1177 1230
1178 hdmi_wp_video_start(1); 1231 hdmi_wp_video_start(&hdmi.ip_data, 1);
1179 1232
1180 return 0; 1233 return 0;
1181err: 1234err:
@@ -1187,9 +1240,9 @@ static void hdmi_power_off(struct omap_dss_device *dssdev)
1187{ 1240{
1188 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0); 1241 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0);
1189 1242
1190 hdmi_wp_video_start(0); 1243 hdmi_wp_video_start(&hdmi.ip_data, 0);
1191 hdmi_phy_off(); 1244 hdmi_phy_off(&hdmi.ip_data);
1192 hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF); 1245 hdmi_set_pll_pwr(&hdmi.ip_data, HDMI_PLLPWRCMD_ALLOFF);
1193 hdmi_runtime_put(); 1246 hdmi_runtime_put();
1194 1247
1195 hdmi.edid_set = 0; 1248 hdmi.edid_set = 0;
@@ -1287,14 +1340,14 @@ void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
1287 1340
1288#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ 1341#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
1289 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) 1342 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
1290static void hdmi_wp_audio_config_format( 1343static void hdmi_wp_audio_config_format(struct hdmi_ip_data *ip_data,
1291 struct hdmi_audio_format *aud_fmt) 1344 struct hdmi_audio_format *aud_fmt)
1292{ 1345{
1293 u32 r; 1346 u32 r;
1294 1347
1295 DSSDBG("Enter hdmi_wp_audio_config_format\n"); 1348 DSSDBG("Enter hdmi_wp_audio_config_format\n");
1296 1349
1297 r = hdmi_read_reg(HDMI_WP_AUDIO_CFG); 1350 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG);
1298 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24); 1351 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
1299 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16); 1352 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
1300 r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5); 1353 r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
@@ -1303,68 +1356,76 @@ static void hdmi_wp_audio_config_format(
1303 r = FLD_MOD(r, aud_fmt->sample_order, 2, 2); 1356 r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
1304 r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1); 1357 r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
1305 r = FLD_MOD(r, aud_fmt->sample_size, 0, 0); 1358 r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
1306 hdmi_write_reg(HDMI_WP_AUDIO_CFG, r); 1359 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG, r);
1307} 1360}
1308 1361
1309static void hdmi_wp_audio_config_dma(struct hdmi_audio_dma *aud_dma) 1362static void hdmi_wp_audio_config_dma(struct hdmi_ip_data *ip_data,
1363 struct hdmi_audio_dma *aud_dma)
1310{ 1364{
1311 u32 r; 1365 u32 r;
1312 1366
1313 DSSDBG("Enter hdmi_wp_audio_config_dma\n"); 1367 DSSDBG("Enter hdmi_wp_audio_config_dma\n");
1314 1368
1315 r = hdmi_read_reg(HDMI_WP_AUDIO_CFG2); 1369 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2);
1316 r = FLD_MOD(r, aud_dma->transfer_size, 15, 8); 1370 r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
1317 r = FLD_MOD(r, aud_dma->block_size, 7, 0); 1371 r = FLD_MOD(r, aud_dma->block_size, 7, 0);
1318 hdmi_write_reg(HDMI_WP_AUDIO_CFG2, r); 1372 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2, r);
1319 1373
1320 r = hdmi_read_reg(HDMI_WP_AUDIO_CTRL); 1374 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL);
1321 r = FLD_MOD(r, aud_dma->mode, 9, 9); 1375 r = FLD_MOD(r, aud_dma->mode, 9, 9);
1322 r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0); 1376 r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
1323 hdmi_write_reg(HDMI_WP_AUDIO_CTRL, r); 1377 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL, r);
1324} 1378}
1325 1379
1326static void hdmi_core_audio_config(struct hdmi_core_audio_config *cfg) 1380static void hdmi_core_audio_config(struct hdmi_ip_data *ip_data,
1381 struct hdmi_core_audio_config *cfg)
1327{ 1382{
1328 u32 r; 1383 u32 r;
1384 void __iomem *av_base = hdmi_av_base(ip_data);
1329 1385
1330 /* audio clock recovery parameters */ 1386 /* audio clock recovery parameters */
1331 r = hdmi_read_reg(HDMI_CORE_AV_ACR_CTRL); 1387 r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
1332 r = FLD_MOD(r, cfg->use_mclk, 2, 2); 1388 r = FLD_MOD(r, cfg->use_mclk, 2, 2);
1333 r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1); 1389 r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
1334 r = FLD_MOD(r, cfg->cts_mode, 0, 0); 1390 r = FLD_MOD(r, cfg->cts_mode, 0, 0);
1335 hdmi_write_reg(HDMI_CORE_AV_ACR_CTRL, r); 1391 hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
1336 1392
1337 REG_FLD_MOD(HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0); 1393 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
1338 REG_FLD_MOD(HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0); 1394 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
1339 REG_FLD_MOD(HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0); 1395 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
1340 1396
1341 if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) { 1397 if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
1342 REG_FLD_MOD(HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0); 1398 REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
1343 REG_FLD_MOD(HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0); 1399 REG_FLD_MOD(av_base,
1344 REG_FLD_MOD(HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0); 1400 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
1401 REG_FLD_MOD(av_base,
1402 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
1345 } else { 1403 } else {
1346 /* 1404 /*
1347 * HDMI IP uses this configuration to divide the MCLK to 1405 * HDMI IP uses this configuration to divide the MCLK to
1348 * update CTS value. 1406 * update CTS value.
1349 */ 1407 */
1350 REG_FLD_MOD(HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0); 1408 REG_FLD_MOD(av_base,
1409 HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
1351 1410
1352 /* Configure clock for audio packets */ 1411 /* Configure clock for audio packets */
1353 REG_FLD_MOD(HDMI_CORE_AV_AUD_PAR_BUSCLK_1, 1412 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
1354 cfg->aud_par_busclk, 7, 0); 1413 cfg->aud_par_busclk, 7, 0);
1355 REG_FLD_MOD(HDMI_CORE_AV_AUD_PAR_BUSCLK_2, 1414 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
1356 (cfg->aud_par_busclk >> 8), 7, 0); 1415 (cfg->aud_par_busclk >> 8), 7, 0);
1357 REG_FLD_MOD(HDMI_CORE_AV_AUD_PAR_BUSCLK_3, 1416 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
1358 (cfg->aud_par_busclk >> 16), 7, 0); 1417 (cfg->aud_par_busclk >> 16), 7, 0);
1359 } 1418 }
1360 1419
1361 /* Override of SPDIF sample frequency with value in I2S_CHST4 */ 1420 /* Override of SPDIF sample frequency with value in I2S_CHST4 */
1362 REG_FLD_MOD(HDMI_CORE_AV_SPDIF_CTRL, cfg->fs_override, 1, 1); 1421 REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
1422 cfg->fs_override, 1, 1);
1363 1423
1364 /* I2S parameters */ 1424 /* I2S parameters */
1365 REG_FLD_MOD(HDMI_CORE_AV_I2S_CHST4, cfg->freq_sample, 3, 0); 1425 REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_CHST4,
1426 cfg->freq_sample, 3, 0);
1366 1427
1367 r = hdmi_read_reg(HDMI_CORE_AV_I2S_IN_CTRL); 1428 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
1368 r = FLD_MOD(r, cfg->i2s_cfg.en_high_bitrate_aud, 7, 7); 1429 r = FLD_MOD(r, cfg->i2s_cfg.en_high_bitrate_aud, 7, 7);
1369 r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6); 1430 r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
1370 r = FLD_MOD(r, cfg->i2s_cfg.cbit_order, 5, 5); 1431 r = FLD_MOD(r, cfg->i2s_cfg.cbit_order, 5, 5);
@@ -1373,69 +1434,72 @@ static void hdmi_core_audio_config(struct hdmi_core_audio_config *cfg)
1373 r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2); 1434 r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
1374 r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1); 1435 r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
1375 r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0); 1436 r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
1376 hdmi_write_reg(HDMI_CORE_AV_I2S_IN_CTRL, r); 1437 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r);
1377 1438
1378 r = hdmi_read_reg(HDMI_CORE_AV_I2S_CHST5); 1439 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_CHST5);
1379 r = FLD_MOD(r, cfg->freq_sample, 7, 4); 1440 r = FLD_MOD(r, cfg->freq_sample, 7, 4);
1380 r = FLD_MOD(r, cfg->i2s_cfg.word_length, 3, 1); 1441 r = FLD_MOD(r, cfg->i2s_cfg.word_length, 3, 1);
1381 r = FLD_MOD(r, cfg->i2s_cfg.word_max_length, 0, 0); 1442 r = FLD_MOD(r, cfg->i2s_cfg.word_max_length, 0, 0);
1382 hdmi_write_reg(HDMI_CORE_AV_I2S_CHST5, r); 1443 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5, r);
1383 1444
1384 REG_FLD_MOD(HDMI_CORE_AV_I2S_IN_LEN, cfg->i2s_cfg.in_length_bits, 3, 0); 1445 REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN,
1446 cfg->i2s_cfg.in_length_bits, 3, 0);
1385 1447
1386 /* Audio channels and mode parameters */ 1448 /* Audio channels and mode parameters */
1387 REG_FLD_MOD(HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1); 1449 REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
1388 r = hdmi_read_reg(HDMI_CORE_AV_AUD_MODE); 1450 r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
1389 r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4); 1451 r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
1390 r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3); 1452 r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
1391 r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2); 1453 r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
1392 r = FLD_MOD(r, cfg->en_spdif, 1, 1); 1454 r = FLD_MOD(r, cfg->en_spdif, 1, 1);
1393 hdmi_write_reg(HDMI_CORE_AV_AUD_MODE, r); 1455 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r);
1394} 1456}
1395 1457
1396static void hdmi_core_audio_infoframe_config( 1458static void hdmi_core_audio_infoframe_config(struct hdmi_ip_data *ip_data,
1397 struct hdmi_core_infoframe_audio *info_aud) 1459 struct hdmi_core_infoframe_audio *info_aud)
1398{ 1460{
1399 u8 val; 1461 u8 val;
1400 u8 sum = 0, checksum = 0; 1462 u8 sum = 0, checksum = 0;
1463 void __iomem *av_base = hdmi_av_base(ip_data);
1401 1464
1402 /* 1465 /*
1403 * Set audio info frame type, version and length as 1466 * Set audio info frame type, version and length as
1404 * described in HDMI 1.4a Section 8.2.2 specification. 1467 * described in HDMI 1.4a Section 8.2.2 specification.
1405 * Checksum calculation is defined in Section 5.3.5. 1468 * Checksum calculation is defined in Section 5.3.5.
1406 */ 1469 */
1407 hdmi_write_reg(HDMI_CORE_AV_AUDIO_TYPE, 0x84); 1470 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84);
1408 hdmi_write_reg(HDMI_CORE_AV_AUDIO_VERS, 0x01); 1471 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01);
1409 hdmi_write_reg(HDMI_CORE_AV_AUDIO_LEN, 0x0a); 1472 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a);
1410 sum += 0x84 + 0x001 + 0x00a; 1473 sum += 0x84 + 0x001 + 0x00a;
1411 1474
1412 val = (info_aud->db1_coding_type << 4) 1475 val = (info_aud->db1_coding_type << 4)
1413 | (info_aud->db1_channel_count - 1); 1476 | (info_aud->db1_channel_count - 1);
1414 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(0), val); 1477 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0), val);
1415 sum += val; 1478 sum += val;
1416 1479
1417 val = (info_aud->db2_sample_freq << 2) | info_aud->db2_sample_size; 1480 val = (info_aud->db2_sample_freq << 2) | info_aud->db2_sample_size;
1418 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(1), val); 1481 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1), val);
1419 sum += val; 1482 sum += val;
1420 1483
1421 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(2), 0x00); 1484 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), 0x00);
1422 1485
1423 val = info_aud->db4_channel_alloc; 1486 val = info_aud->db4_channel_alloc;
1424 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(3), val); 1487 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), val);
1425 sum += val; 1488 sum += val;
1426 1489
1427 val = (info_aud->db5_downmix_inh << 7) | (info_aud->db5_lsv << 3); 1490 val = (info_aud->db5_downmix_inh << 7) | (info_aud->db5_lsv << 3);
1428 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(4), val); 1491 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4), val);
1429 sum += val; 1492 sum += val;
1430 1493
1431 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(5), 0x00); 1494 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
1432 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(6), 0x00); 1495 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
1433 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(7), 0x00); 1496 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
1434 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(8), 0x00); 1497 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
1435 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(9), 0x00); 1498 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
1436 1499
1437 checksum = 0x100 - sum; 1500 checksum = 0x100 - sum;
1438 hdmi_write_reg(HDMI_CORE_AV_AUDIO_CHSUM, checksum); 1501 hdmi_write_reg(av_base,
1502 HDMI_CORE_AV_AUDIO_CHSUM, checksum);
1439 1503
1440 /* 1504 /*
1441 * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing 1505 * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
@@ -1443,7 +1507,8 @@ static void hdmi_core_audio_infoframe_config(
1443 */ 1507 */
1444} 1508}
1445 1509
1446static int hdmi_config_audio_acr(u32 sample_freq, u32 *n, u32 *cts) 1510static int hdmi_config_audio_acr(struct hdmi_ip_data *ip_data,
1511 u32 sample_freq, u32 *n, u32 *cts)
1447{ 1512{
1448 u32 r; 1513 u32 r;
1449 u32 deep_color = 0; 1514 u32 deep_color = 0;
@@ -1455,7 +1520,7 @@ static int hdmi_config_audio_acr(u32 sample_freq, u32 *n, u32 *cts)
1455 * Obtain current deep color configuration. This needed 1520 * Obtain current deep color configuration. This needed
1456 * to calculate the TMDS clock based on the pixel clock. 1521 * to calculate the TMDS clock based on the pixel clock.
1457 */ 1522 */
1458 r = REG_GET(HDMI_WP_VIDEO_CFG, 1, 0); 1523 r = REG_GET(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, 1, 0);
1459 switch (r) { 1524 switch (r) {
1460 case 1: /* No deep color selected */ 1525 case 1: /* No deep color selected */
1461 deep_color = 100; 1526 deep_color = 100;
@@ -1499,7 +1564,8 @@ static int hdmi_config_audio_acr(u32 sample_freq, u32 *n, u32 *cts)
1499 return 0; 1564 return 0;
1500} 1565}
1501 1566
1502static int hdmi_audio_hw_params(struct snd_pcm_substream *substream, 1567static int hdmi_audio_hw_params(struct hdmi_ip_data *ip_data,
1568 struct snd_pcm_substream *substream,
1503 struct snd_pcm_hw_params *params, 1569 struct snd_pcm_hw_params *params,
1504 struct snd_soc_dai *dai) 1570 struct snd_soc_dai *dai)
1505{ 1571{
@@ -1553,7 +1619,7 @@ static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
1553 return -EINVAL; 1619 return -EINVAL;
1554 } 1620 }
1555 1621
1556 err = hdmi_config_audio_acr(params_rate(params), &n, &cts); 1622 err = hdmi_config_audio_acr(ip_data, params_rate(params), &n, &cts);
1557 if (err < 0) 1623 if (err < 0)
1558 return err; 1624 return err;
1559 1625
@@ -1569,8 +1635,8 @@ static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
1569 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA; 1635 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
1570 audio_dma.fifo_threshold = 0x20; /* in number of samples */ 1636 audio_dma.fifo_threshold = 0x20; /* in number of samples */
1571 1637
1572 hdmi_wp_audio_config_dma(&audio_dma); 1638 hdmi_wp_audio_config_dma(ip_data, &audio_dma);
1573 hdmi_wp_audio_config_format(&audio_format); 1639 hdmi_wp_audio_config_format(ip_data, &audio_format);
1574 1640
1575 /* 1641 /*
1576 * I2S config 1642 * I2S config
@@ -1614,7 +1680,7 @@ static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
1614 /* Use parallel audio interface */ 1680 /* Use parallel audio interface */
1615 core_cfg.en_parallel_aud_input = true; 1681 core_cfg.en_parallel_aud_input = true;
1616 1682
1617 hdmi_core_audio_config(&core_cfg); 1683 hdmi_core_audio_config(ip_data, &core_cfg);
1618 1684
1619 /* 1685 /*
1620 * Configure packet 1686 * Configure packet
@@ -1628,29 +1694,36 @@ static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
1628 aud_if_cfg.db5_downmix_inh = false; 1694 aud_if_cfg.db5_downmix_inh = false;
1629 aud_if_cfg.db5_lsv = 0; 1695 aud_if_cfg.db5_lsv = 0;
1630 1696
1631 hdmi_core_audio_infoframe_config(&aud_if_cfg); 1697 hdmi_core_audio_infoframe_config(ip_data, &aud_if_cfg);
1632 return 0; 1698 return 0;
1633} 1699}
1634 1700
1635static int hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, 1701static int hdmi_audio_trigger(struct hdmi_ip_data *ip_data,
1636 struct snd_soc_dai *dai) 1702 struct snd_pcm_substream *substream, int cmd,
1703 struct snd_soc_dai *dai)
1637{ 1704{
1638 int err = 0; 1705 int err = 0;
1639 switch (cmd) { 1706 switch (cmd) {
1640 case SNDRV_PCM_TRIGGER_START: 1707 case SNDRV_PCM_TRIGGER_START:
1641 case SNDRV_PCM_TRIGGER_RESUME: 1708 case SNDRV_PCM_TRIGGER_RESUME:
1642 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1709 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1643 REG_FLD_MOD(HDMI_CORE_AV_AUD_MODE, 1, 0, 0); 1710 REG_FLD_MOD(hdmi_av_base(ip_data),
1644 REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 1, 31, 31); 1711 HDMI_CORE_AV_AUD_MODE, 1, 0, 0);
1645 REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 1, 30, 30); 1712 REG_FLD_MOD(hdmi_wp_base(ip_data),
1713 HDMI_WP_AUDIO_CTRL, 1, 31, 31);
1714 REG_FLD_MOD(hdmi_wp_base(ip_data),
1715 HDMI_WP_AUDIO_CTRL, 1, 30, 30);
1646 break; 1716 break;
1647 1717
1648 case SNDRV_PCM_TRIGGER_STOP: 1718 case SNDRV_PCM_TRIGGER_STOP:
1649 case SNDRV_PCM_TRIGGER_SUSPEND: 1719 case SNDRV_PCM_TRIGGER_SUSPEND:
1650 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1720 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1651 REG_FLD_MOD(HDMI_CORE_AV_AUD_MODE, 0, 0, 0); 1721 REG_FLD_MOD(hdmi_av_base(ip_data),
1652 REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 0, 30, 30); 1722 HDMI_CORE_AV_AUD_MODE, 0, 0, 0);
1653 REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 0, 31, 31); 1723 REG_FLD_MOD(hdmi_wp_base(ip_data),
1724 HDMI_WP_AUDIO_CTRL, 0, 30, 30);
1725 REG_FLD_MOD(hdmi_wp_base(ip_data),
1726 HDMI_WP_AUDIO_CTRL, 0, 31, 31);
1654 break; 1727 break;
1655 default: 1728 default:
1656 err = -EINVAL; 1729 err = -EINVAL;
@@ -1730,20 +1803,26 @@ static int omapdss_hdmihw_probe(struct platform_device *pdev)
1730 } 1803 }
1731 1804
1732 /* Base address taken from platform */ 1805 /* Base address taken from platform */
1733 hdmi.base_wp = ioremap(hdmi_mem->start, resource_size(hdmi_mem)); 1806 hdmi.ip_data.base_wp = ioremap(hdmi_mem->start,
1734 if (!hdmi.base_wp) { 1807 resource_size(hdmi_mem));
1808 if (!hdmi.ip_data.base_wp) {
1735 DSSERR("can't ioremap WP\n"); 1809 DSSERR("can't ioremap WP\n");
1736 return -ENOMEM; 1810 return -ENOMEM;
1737 } 1811 }
1738 1812
1739 r = hdmi_get_clocks(pdev); 1813 r = hdmi_get_clocks(pdev);
1740 if (r) { 1814 if (r) {
1741 iounmap(hdmi.base_wp); 1815 iounmap(hdmi.ip_data.base_wp);
1742 return r; 1816 return r;
1743 } 1817 }
1744 1818
1745 pm_runtime_enable(&pdev->dev); 1819 pm_runtime_enable(&pdev->dev);
1746 1820
1821 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
1822 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
1823 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
1824 hdmi.ip_data.phy_offset = HDMI_PHY;
1825
1747 hdmi_panel_init(); 1826 hdmi_panel_init();
1748 1827
1749#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ 1828#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
@@ -1773,7 +1852,7 @@ static int omapdss_hdmihw_remove(struct platform_device *pdev)
1773 1852
1774 hdmi_put_clocks(); 1853 hdmi_put_clocks();
1775 1854
1776 iounmap(hdmi.base_wp); 1855 iounmap(hdmi.ip_data.base_wp);
1777 1856
1778 return 0; 1857 return 0;
1779} 1858}
diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h
index c885f9cb0659..ee37bd932116 100644
--- a/drivers/video/omap2/dss/hdmi.h
+++ b/drivers/video/omap2/dss/hdmi.h
@@ -24,174 +24,163 @@
24#include <linux/string.h> 24#include <linux/string.h>
25#include <video/omapdss.h> 25#include <video/omapdss.h>
26 26
27#define HDMI_WP 0x0
28#define HDMI_CORE_SYS 0x400
29#define HDMI_CORE_AV 0x900
30#define HDMI_PLLCTRL 0x200
31#define HDMI_PHY 0x300
32
33struct hdmi_reg { u16 idx; }; 27struct hdmi_reg { u16 idx; };
34 28
35#define HDMI_REG(idx) ((const struct hdmi_reg) { idx }) 29#define HDMI_REG(idx) ((const struct hdmi_reg) { idx })
36 30
37/* HDMI Wrapper */ 31/* HDMI Wrapper */
38#define HDMI_WP_REG(idx) HDMI_REG(HDMI_WP + idx) 32
39 33#define HDMI_WP_REVISION HDMI_REG(0x0)
40#define HDMI_WP_REVISION HDMI_WP_REG(0x0) 34#define HDMI_WP_SYSCONFIG HDMI_REG(0x10)
41#define HDMI_WP_SYSCONFIG HDMI_WP_REG(0x10) 35#define HDMI_WP_IRQSTATUS_RAW HDMI_REG(0x24)
42#define HDMI_WP_IRQSTATUS_RAW HDMI_WP_REG(0x24) 36#define HDMI_WP_IRQSTATUS HDMI_REG(0x28)
43#define HDMI_WP_IRQSTATUS HDMI_WP_REG(0x28) 37#define HDMI_WP_PWR_CTRL HDMI_REG(0x40)
44#define HDMI_WP_PWR_CTRL HDMI_WP_REG(0x40) 38#define HDMI_WP_IRQENABLE_SET HDMI_REG(0x2C)
45#define HDMI_WP_IRQENABLE_SET HDMI_WP_REG(0x2C) 39#define HDMI_WP_VIDEO_CFG HDMI_REG(0x50)
46#define HDMI_WP_VIDEO_CFG HDMI_WP_REG(0x50) 40#define HDMI_WP_VIDEO_SIZE HDMI_REG(0x60)
47#define HDMI_WP_VIDEO_SIZE HDMI_WP_REG(0x60) 41#define HDMI_WP_VIDEO_TIMING_H HDMI_REG(0x68)
48#define HDMI_WP_VIDEO_TIMING_H HDMI_WP_REG(0x68) 42#define HDMI_WP_VIDEO_TIMING_V HDMI_REG(0x6C)
49#define HDMI_WP_VIDEO_TIMING_V HDMI_WP_REG(0x6C) 43#define HDMI_WP_WP_CLK HDMI_REG(0x70)
50#define HDMI_WP_WP_CLK HDMI_WP_REG(0x70) 44#define HDMI_WP_AUDIO_CFG HDMI_REG(0x80)
51#define HDMI_WP_AUDIO_CFG HDMI_WP_REG(0x80) 45#define HDMI_WP_AUDIO_CFG2 HDMI_REG(0x84)
52#define HDMI_WP_AUDIO_CFG2 HDMI_WP_REG(0x84) 46#define HDMI_WP_AUDIO_CTRL HDMI_REG(0x88)
53#define HDMI_WP_AUDIO_CTRL HDMI_WP_REG(0x88) 47#define HDMI_WP_AUDIO_DATA HDMI_REG(0x8C)
54#define HDMI_WP_AUDIO_DATA HDMI_WP_REG(0x8C)
55 48
56/* HDMI IP Core System */ 49/* HDMI IP Core System */
57#define HDMI_CORE_SYS_REG(idx) HDMI_REG(HDMI_CORE_SYS + idx) 50
58 51#define HDMI_CORE_SYS_VND_IDL HDMI_REG(0x0)
59#define HDMI_CORE_SYS_VND_IDL HDMI_CORE_SYS_REG(0x0) 52#define HDMI_CORE_SYS_DEV_IDL HDMI_REG(0x8)
60#define HDMI_CORE_SYS_DEV_IDL HDMI_CORE_SYS_REG(0x8) 53#define HDMI_CORE_SYS_DEV_IDH HDMI_REG(0xC)
61#define HDMI_CORE_SYS_DEV_IDH HDMI_CORE_SYS_REG(0xC) 54#define HDMI_CORE_SYS_DEV_REV HDMI_REG(0x10)
62#define HDMI_CORE_SYS_DEV_REV HDMI_CORE_SYS_REG(0x10) 55#define HDMI_CORE_SYS_SRST HDMI_REG(0x14)
63#define HDMI_CORE_SYS_SRST HDMI_CORE_SYS_REG(0x14) 56#define HDMI_CORE_CTRL1 HDMI_REG(0x20)
64#define HDMI_CORE_CTRL1 HDMI_CORE_SYS_REG(0x20) 57#define HDMI_CORE_SYS_SYS_STAT HDMI_REG(0x24)
65#define HDMI_CORE_SYS_SYS_STAT HDMI_CORE_SYS_REG(0x24) 58#define HDMI_CORE_SYS_VID_ACEN HDMI_REG(0x124)
66#define HDMI_CORE_SYS_VID_ACEN HDMI_CORE_SYS_REG(0x124) 59#define HDMI_CORE_SYS_VID_MODE HDMI_REG(0x128)
67#define HDMI_CORE_SYS_VID_MODE HDMI_CORE_SYS_REG(0x128) 60#define HDMI_CORE_SYS_INTR_STATE HDMI_REG(0x1C0)
68#define HDMI_CORE_SYS_INTR_STATE HDMI_CORE_SYS_REG(0x1C0) 61#define HDMI_CORE_SYS_INTR1 HDMI_REG(0x1C4)
69#define HDMI_CORE_SYS_INTR1 HDMI_CORE_SYS_REG(0x1C4) 62#define HDMI_CORE_SYS_INTR2 HDMI_REG(0x1C8)
70#define HDMI_CORE_SYS_INTR2 HDMI_CORE_SYS_REG(0x1C8) 63#define HDMI_CORE_SYS_INTR3 HDMI_REG(0x1CC)
71#define HDMI_CORE_SYS_INTR3 HDMI_CORE_SYS_REG(0x1CC) 64#define HDMI_CORE_SYS_INTR4 HDMI_REG(0x1D0)
72#define HDMI_CORE_SYS_INTR4 HDMI_CORE_SYS_REG(0x1D0) 65#define HDMI_CORE_SYS_UMASK1 HDMI_REG(0x1D4)
73#define HDMI_CORE_SYS_UMASK1 HDMI_CORE_SYS_REG(0x1D4) 66#define HDMI_CORE_SYS_TMDS_CTRL HDMI_REG(0x208)
74#define HDMI_CORE_SYS_TMDS_CTRL HDMI_CORE_SYS_REG(0x208) 67#define HDMI_CORE_SYS_DE_DLY HDMI_REG(0xC8)
75#define HDMI_CORE_SYS_DE_DLY HDMI_CORE_SYS_REG(0xC8) 68#define HDMI_CORE_SYS_DE_CTRL HDMI_REG(0xCC)
76#define HDMI_CORE_SYS_DE_CTRL HDMI_CORE_SYS_REG(0xCC) 69#define HDMI_CORE_SYS_DE_TOP HDMI_REG(0xD0)
77#define HDMI_CORE_SYS_DE_TOP HDMI_CORE_SYS_REG(0xD0) 70#define HDMI_CORE_SYS_DE_CNTL HDMI_REG(0xD8)
78#define HDMI_CORE_SYS_DE_CNTL HDMI_CORE_SYS_REG(0xD8) 71#define HDMI_CORE_SYS_DE_CNTH HDMI_REG(0xDC)
79#define HDMI_CORE_SYS_DE_CNTH HDMI_CORE_SYS_REG(0xDC) 72#define HDMI_CORE_SYS_DE_LINL HDMI_REG(0xE0)
80#define HDMI_CORE_SYS_DE_LINL HDMI_CORE_SYS_REG(0xE0) 73#define HDMI_CORE_SYS_DE_LINH_1 HDMI_REG(0xE4)
81#define HDMI_CORE_SYS_DE_LINH_1 HDMI_CORE_SYS_REG(0xE4)
82#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1 74#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
83#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1 75#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
84#define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1 76#define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1
85#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1 77#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
86 78
87/* HDMI DDC E-DID */ 79/* HDMI DDC E-DID */
88#define HDMI_CORE_DDC_CMD HDMI_CORE_SYS_REG(0x3CC) 80#define HDMI_CORE_DDC_CMD HDMI_REG(0x3CC)
89#define HDMI_CORE_DDC_STATUS HDMI_CORE_SYS_REG(0x3C8) 81#define HDMI_CORE_DDC_STATUS HDMI_REG(0x3C8)
90#define HDMI_CORE_DDC_ADDR HDMI_CORE_SYS_REG(0x3B4) 82#define HDMI_CORE_DDC_ADDR HDMI_REG(0x3B4)
91#define HDMI_CORE_DDC_OFFSET HDMI_CORE_SYS_REG(0x3BC) 83#define HDMI_CORE_DDC_OFFSET HDMI_REG(0x3BC)
92#define HDMI_CORE_DDC_COUNT1 HDMI_CORE_SYS_REG(0x3C0) 84#define HDMI_CORE_DDC_COUNT1 HDMI_REG(0x3C0)
93#define HDMI_CORE_DDC_COUNT2 HDMI_CORE_SYS_REG(0x3C4) 85#define HDMI_CORE_DDC_COUNT2 HDMI_REG(0x3C4)
94#define HDMI_CORE_DDC_DATA HDMI_CORE_SYS_REG(0x3D0) 86#define HDMI_CORE_DDC_DATA HDMI_REG(0x3D0)
95#define HDMI_CORE_DDC_SEGM HDMI_CORE_SYS_REG(0x3B8) 87#define HDMI_CORE_DDC_SEGM HDMI_REG(0x3B8)
96 88
97/* HDMI IP Core Audio Video */ 89/* HDMI IP Core Audio Video */
98#define HDMI_CORE_AV_REG(idx) HDMI_REG(HDMI_CORE_AV + idx) 90
99 91#define HDMI_CORE_AV_HDMI_CTRL HDMI_REG(0xBC)
100#define HDMI_CORE_AV_HDMI_CTRL HDMI_CORE_AV_REG(0xBC) 92#define HDMI_CORE_AV_DPD HDMI_REG(0xF4)
101#define HDMI_CORE_AV_DPD HDMI_CORE_AV_REG(0xF4) 93#define HDMI_CORE_AV_PB_CTRL1 HDMI_REG(0xF8)
102#define HDMI_CORE_AV_PB_CTRL1 HDMI_CORE_AV_REG(0xF8) 94#define HDMI_CORE_AV_PB_CTRL2 HDMI_REG(0xFC)
103#define HDMI_CORE_AV_PB_CTRL2 HDMI_CORE_AV_REG(0xFC) 95#define HDMI_CORE_AV_AVI_TYPE HDMI_REG(0x100)
104#define HDMI_CORE_AV_AVI_TYPE HDMI_CORE_AV_REG(0x100) 96#define HDMI_CORE_AV_AVI_VERS HDMI_REG(0x104)
105#define HDMI_CORE_AV_AVI_VERS HDMI_CORE_AV_REG(0x104) 97#define HDMI_CORE_AV_AVI_LEN HDMI_REG(0x108)
106#define HDMI_CORE_AV_AVI_LEN HDMI_CORE_AV_REG(0x108) 98#define HDMI_CORE_AV_AVI_CHSUM HDMI_REG(0x10C)
107#define HDMI_CORE_AV_AVI_CHSUM HDMI_CORE_AV_REG(0x10C) 99#define HDMI_CORE_AV_AVI_DBYTE(n) HDMI_REG(n * 4 + 0x110)
108#define HDMI_CORE_AV_AVI_DBYTE(n) HDMI_CORE_AV_REG(n * 4 + 0x110) 100#define HDMI_CORE_AV_AVI_DBYTE_NELEMS HDMI_REG(15)
109#define HDMI_CORE_AV_AVI_DBYTE_NELEMS HDMI_CORE_AV_REG(15) 101#define HDMI_CORE_AV_SPD_DBYTE HDMI_REG(0x190)
110#define HDMI_CORE_AV_SPD_DBYTE HDMI_CORE_AV_REG(0x190) 102#define HDMI_CORE_AV_SPD_DBYTE_NELEMS HDMI_REG(27)
111#define HDMI_CORE_AV_SPD_DBYTE_NELEMS HDMI_CORE_AV_REG(27) 103#define HDMI_CORE_AV_AUD_DBYTE(n) HDMI_REG(n * 4 + 0x210)
112#define HDMI_CORE_AV_AUD_DBYTE(n) HDMI_CORE_AV_REG(n * 4 + 0x210) 104#define HDMI_CORE_AV_AUD_DBYTE_NELEMS HDMI_REG(10)
113#define HDMI_CORE_AV_AUD_DBYTE_NELEMS HDMI_CORE_AV_REG(10) 105#define HDMI_CORE_AV_MPEG_DBYTE HDMI_REG(0x290)
114#define HDMI_CORE_AV_MPEG_DBYTE HDMI_CORE_AV_REG(0x290) 106#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS HDMI_REG(27)
115#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS HDMI_CORE_AV_REG(27) 107#define HDMI_CORE_AV_GEN_DBYTE HDMI_REG(0x300)
116#define HDMI_CORE_AV_GEN_DBYTE HDMI_CORE_AV_REG(0x300) 108#define HDMI_CORE_AV_GEN_DBYTE_NELEMS HDMI_REG(31)
117#define HDMI_CORE_AV_GEN_DBYTE_NELEMS HDMI_CORE_AV_REG(31) 109#define HDMI_CORE_AV_GEN2_DBYTE HDMI_REG(0x380)
118#define HDMI_CORE_AV_GEN2_DBYTE HDMI_CORE_AV_REG(0x380) 110#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS HDMI_REG(31)
119#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS HDMI_CORE_AV_REG(31) 111#define HDMI_CORE_AV_ACR_CTRL HDMI_REG(0x4)
120#define HDMI_CORE_AV_ACR_CTRL HDMI_CORE_AV_REG(0x4) 112#define HDMI_CORE_AV_FREQ_SVAL HDMI_REG(0x8)
121#define HDMI_CORE_AV_FREQ_SVAL HDMI_CORE_AV_REG(0x8) 113#define HDMI_CORE_AV_N_SVAL1 HDMI_REG(0xC)
122#define HDMI_CORE_AV_N_SVAL1 HDMI_CORE_AV_REG(0xC) 114#define HDMI_CORE_AV_N_SVAL2 HDMI_REG(0x10)
123#define HDMI_CORE_AV_N_SVAL2 HDMI_CORE_AV_REG(0x10) 115#define HDMI_CORE_AV_N_SVAL3 HDMI_REG(0x14)
124#define HDMI_CORE_AV_N_SVAL3 HDMI_CORE_AV_REG(0x14) 116#define HDMI_CORE_AV_CTS_SVAL1 HDMI_REG(0x18)
125#define HDMI_CORE_AV_CTS_SVAL1 HDMI_CORE_AV_REG(0x18) 117#define HDMI_CORE_AV_CTS_SVAL2 HDMI_REG(0x1C)
126#define HDMI_CORE_AV_CTS_SVAL2 HDMI_CORE_AV_REG(0x1C) 118#define HDMI_CORE_AV_CTS_SVAL3 HDMI_REG(0x20)
127#define HDMI_CORE_AV_CTS_SVAL3 HDMI_CORE_AV_REG(0x20) 119#define HDMI_CORE_AV_CTS_HVAL1 HDMI_REG(0x24)
128#define HDMI_CORE_AV_CTS_HVAL1 HDMI_CORE_AV_REG(0x24) 120#define HDMI_CORE_AV_CTS_HVAL2 HDMI_REG(0x28)
129#define HDMI_CORE_AV_CTS_HVAL2 HDMI_CORE_AV_REG(0x28) 121#define HDMI_CORE_AV_CTS_HVAL3 HDMI_REG(0x2C)
130#define HDMI_CORE_AV_CTS_HVAL3 HDMI_CORE_AV_REG(0x2C) 122#define HDMI_CORE_AV_AUD_MODE HDMI_REG(0x50)
131#define HDMI_CORE_AV_AUD_MODE HDMI_CORE_AV_REG(0x50) 123#define HDMI_CORE_AV_SPDIF_CTRL HDMI_REG(0x54)
132#define HDMI_CORE_AV_SPDIF_CTRL HDMI_CORE_AV_REG(0x54) 124#define HDMI_CORE_AV_HW_SPDIF_FS HDMI_REG(0x60)
133#define HDMI_CORE_AV_HW_SPDIF_FS HDMI_CORE_AV_REG(0x60) 125#define HDMI_CORE_AV_SWAP_I2S HDMI_REG(0x64)
134#define HDMI_CORE_AV_SWAP_I2S HDMI_CORE_AV_REG(0x64) 126#define HDMI_CORE_AV_SPDIF_ERTH HDMI_REG(0x6C)
135#define HDMI_CORE_AV_SPDIF_ERTH HDMI_CORE_AV_REG(0x6C) 127#define HDMI_CORE_AV_I2S_IN_MAP HDMI_REG(0x70)
136#define HDMI_CORE_AV_I2S_IN_MAP HDMI_CORE_AV_REG(0x70) 128#define HDMI_CORE_AV_I2S_IN_CTRL HDMI_REG(0x74)
137#define HDMI_CORE_AV_I2S_IN_CTRL HDMI_CORE_AV_REG(0x74) 129#define HDMI_CORE_AV_I2S_CHST0 HDMI_REG(0x78)
138#define HDMI_CORE_AV_I2S_CHST0 HDMI_CORE_AV_REG(0x78) 130#define HDMI_CORE_AV_I2S_CHST1 HDMI_REG(0x7C)
139#define HDMI_CORE_AV_I2S_CHST1 HDMI_CORE_AV_REG(0x7C) 131#define HDMI_CORE_AV_I2S_CHST2 HDMI_REG(0x80)
140#define HDMI_CORE_AV_I2S_CHST2 HDMI_CORE_AV_REG(0x80) 132#define HDMI_CORE_AV_I2S_CHST4 HDMI_REG(0x84)
141#define HDMI_CORE_AV_I2S_CHST4 HDMI_CORE_AV_REG(0x84) 133#define HDMI_CORE_AV_I2S_CHST5 HDMI_REG(0x88)
142#define HDMI_CORE_AV_I2S_CHST5 HDMI_CORE_AV_REG(0x88) 134#define HDMI_CORE_AV_ASRC HDMI_REG(0x8C)
143#define HDMI_CORE_AV_ASRC HDMI_CORE_AV_REG(0x8C) 135#define HDMI_CORE_AV_I2S_IN_LEN HDMI_REG(0x90)
144#define HDMI_CORE_AV_I2S_IN_LEN HDMI_CORE_AV_REG(0x90) 136#define HDMI_CORE_AV_HDMI_CTRL HDMI_REG(0xBC)
145#define HDMI_CORE_AV_HDMI_CTRL HDMI_CORE_AV_REG(0xBC) 137#define HDMI_CORE_AV_AUDO_TXSTAT HDMI_REG(0xC0)
146#define HDMI_CORE_AV_AUDO_TXSTAT HDMI_CORE_AV_REG(0xC0) 138#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 HDMI_REG(0xCC)
147#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 HDMI_CORE_AV_REG(0xCC) 139#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 HDMI_REG(0xD0)
148#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 HDMI_CORE_AV_REG(0xD0) 140#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 HDMI_REG(0xD4)
149#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 HDMI_CORE_AV_REG(0xD4) 141#define HDMI_CORE_AV_TEST_TXCTRL HDMI_REG(0xF0)
150#define HDMI_CORE_AV_TEST_TXCTRL HDMI_CORE_AV_REG(0xF0) 142#define HDMI_CORE_AV_DPD HDMI_REG(0xF4)
151#define HDMI_CORE_AV_DPD HDMI_CORE_AV_REG(0xF4) 143#define HDMI_CORE_AV_PB_CTRL1 HDMI_REG(0xF8)
152#define HDMI_CORE_AV_PB_CTRL1 HDMI_CORE_AV_REG(0xF8) 144#define HDMI_CORE_AV_PB_CTRL2 HDMI_REG(0xFC)
153#define HDMI_CORE_AV_PB_CTRL2 HDMI_CORE_AV_REG(0xFC) 145#define HDMI_CORE_AV_AVI_TYPE HDMI_REG(0x100)
154#define HDMI_CORE_AV_AVI_TYPE HDMI_CORE_AV_REG(0x100) 146#define HDMI_CORE_AV_AVI_VERS HDMI_REG(0x104)
155#define HDMI_CORE_AV_AVI_VERS HDMI_CORE_AV_REG(0x104) 147#define HDMI_CORE_AV_AVI_LEN HDMI_REG(0x108)
156#define HDMI_CORE_AV_AVI_LEN HDMI_CORE_AV_REG(0x108) 148#define HDMI_CORE_AV_AVI_CHSUM HDMI_REG(0x10C)
157#define HDMI_CORE_AV_AVI_CHSUM HDMI_CORE_AV_REG(0x10C) 149#define HDMI_CORE_AV_SPD_TYPE HDMI_REG(0x180)
158#define HDMI_CORE_AV_SPD_TYPE HDMI_CORE_AV_REG(0x180) 150#define HDMI_CORE_AV_SPD_VERS HDMI_REG(0x184)
159#define HDMI_CORE_AV_SPD_VERS HDMI_CORE_AV_REG(0x184) 151#define HDMI_CORE_AV_SPD_LEN HDMI_REG(0x188)
160#define HDMI_CORE_AV_SPD_LEN HDMI_CORE_AV_REG(0x188) 152#define HDMI_CORE_AV_SPD_CHSUM HDMI_REG(0x18C)
161#define HDMI_CORE_AV_SPD_CHSUM HDMI_CORE_AV_REG(0x18C) 153#define HDMI_CORE_AV_AUDIO_TYPE HDMI_REG(0x200)
162#define HDMI_CORE_AV_AUDIO_TYPE HDMI_CORE_AV_REG(0x200) 154#define HDMI_CORE_AV_AUDIO_VERS HDMI_REG(0x204)
163#define HDMI_CORE_AV_AUDIO_VERS HDMI_CORE_AV_REG(0x204) 155#define HDMI_CORE_AV_AUDIO_LEN HDMI_REG(0x208)
164#define HDMI_CORE_AV_AUDIO_LEN HDMI_CORE_AV_REG(0x208) 156#define HDMI_CORE_AV_AUDIO_CHSUM HDMI_REG(0x20C)
165#define HDMI_CORE_AV_AUDIO_CHSUM HDMI_CORE_AV_REG(0x20C) 157#define HDMI_CORE_AV_MPEG_TYPE HDMI_REG(0x280)
166#define HDMI_CORE_AV_MPEG_TYPE HDMI_CORE_AV_REG(0x280) 158#define HDMI_CORE_AV_MPEG_VERS HDMI_REG(0x284)
167#define HDMI_CORE_AV_MPEG_VERS HDMI_CORE_AV_REG(0x284) 159#define HDMI_CORE_AV_MPEG_LEN HDMI_REG(0x288)
168#define HDMI_CORE_AV_MPEG_LEN HDMI_CORE_AV_REG(0x288) 160#define HDMI_CORE_AV_MPEG_CHSUM HDMI_REG(0x28C)
169#define HDMI_CORE_AV_MPEG_CHSUM HDMI_CORE_AV_REG(0x28C) 161#define HDMI_CORE_AV_CP_BYTE1 HDMI_REG(0x37C)
170#define HDMI_CORE_AV_CP_BYTE1 HDMI_CORE_AV_REG(0x37C) 162#define HDMI_CORE_AV_CEC_ADDR_ID HDMI_REG(0x3FC)
171#define HDMI_CORE_AV_CEC_ADDR_ID HDMI_CORE_AV_REG(0x3FC)
172#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4 163#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4
173#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4 164#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4
174#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4 165#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4
175#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE 0x4 166#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE 0x4
176 167
177/* PLL */ 168/* PLL */
178#define HDMI_PLL_REG(idx) HDMI_REG(HDMI_PLLCTRL + idx)
179 169
180#define PLLCTRL_PLL_CONTROL HDMI_PLL_REG(0x0) 170#define PLLCTRL_PLL_CONTROL HDMI_REG(0x0)
181#define PLLCTRL_PLL_STATUS HDMI_PLL_REG(0x4) 171#define PLLCTRL_PLL_STATUS HDMI_REG(0x4)
182#define PLLCTRL_PLL_GO HDMI_PLL_REG(0x8) 172#define PLLCTRL_PLL_GO HDMI_REG(0x8)
183#define PLLCTRL_CFG1 HDMI_PLL_REG(0xC) 173#define PLLCTRL_CFG1 HDMI_REG(0xC)
184#define PLLCTRL_CFG2 HDMI_PLL_REG(0x10) 174#define PLLCTRL_CFG2 HDMI_REG(0x10)
185#define PLLCTRL_CFG3 HDMI_PLL_REG(0x14) 175#define PLLCTRL_CFG3 HDMI_REG(0x14)
186#define PLLCTRL_CFG4 HDMI_PLL_REG(0x20) 176#define PLLCTRL_CFG4 HDMI_REG(0x20)
187 177
188/* HDMI PHY */ 178/* HDMI PHY */
189#define HDMI_PHY_REG(idx) HDMI_REG(HDMI_PHY + idx)
190 179
191#define HDMI_TXPHY_TX_CTRL HDMI_PHY_REG(0x0) 180#define HDMI_TXPHY_TX_CTRL HDMI_REG(0x0)
192#define HDMI_TXPHY_DIGITAL_CTRL HDMI_PHY_REG(0x4) 181#define HDMI_TXPHY_DIGITAL_CTRL HDMI_REG(0x4)
193#define HDMI_TXPHY_POWER_CTRL HDMI_PHY_REG(0x8) 182#define HDMI_TXPHY_POWER_CTRL HDMI_REG(0x8)
194#define HDMI_TXPHY_PAD_CFG_CTRL HDMI_PHY_REG(0xC) 183#define HDMI_TXPHY_PAD_CFG_CTRL HDMI_REG(0xC)
195 184
196/* HDMI EDID Length */ 185/* HDMI EDID Length */
197#define HDMI_EDID_MAX_LENGTH 256 186#define HDMI_EDID_MAX_LENGTH 256
@@ -203,10 +192,11 @@ struct hdmi_reg { u16 idx; };
203 192
204#define OMAP_HDMI_TIMINGS_NB 34 193#define OMAP_HDMI_TIMINGS_NB 34
205 194
206#define REG_FLD_MOD(idx, val, start, end) \ 195#define REG_FLD_MOD(base, idx, val, start, end) \
207 hdmi_write_reg(idx, FLD_MOD(hdmi_read_reg(idx), val, start, end)) 196 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
208#define REG_GET(idx, start, end) \ 197 val, start, end))
209 FLD_GET(hdmi_read_reg(idx), start, end) 198#define REG_GET(base, idx, start, end) \
199 FLD_GET(hdmi_read_reg(base, idx), start, end)
210 200
211/* HDMI timing structure */ 201/* HDMI timing structure */
212struct hdmi_timings { 202struct hdmi_timings {
@@ -568,6 +558,14 @@ struct hdmi_video_interface {
568 int tm; /* Timing mode */ 558 int tm; /* Timing mode */
569}; 559};
570 560
561struct hdmi_ip_data {
562 void __iomem *base_wp; /* HDMI wrapper */
563 unsigned long core_sys_offset;
564 unsigned long core_av_offset;
565 unsigned long pll_offset;
566 unsigned long phy_offset;
567};
568
571struct hdmi_cm { 569struct hdmi_cm {
572 int code; 570 int code;
573 int mode; 571 int mode;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 03:08:34 -0500