diff options
Diffstat (limited to 'drivers/video')
61 files changed, 1002 insertions, 484 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 4f2e1b35eb38..22262a3a0e2d 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig | |||
@@ -312,7 +312,8 @@ config FB_PM2_FIFO_DISCONNECT | |||
312 | 312 | ||
313 | config FB_ARMCLCD | 313 | config FB_ARMCLCD |
314 | tristate "ARM PrimeCell PL110 support" | 314 | tristate "ARM PrimeCell PL110 support" |
315 | depends on FB && ARM && ARM_AMBA | 315 | depends on ARM || ARM64 || COMPILE_TEST |
316 | depends on FB && ARM_AMBA | ||
316 | select FB_CFB_FILLRECT | 317 | select FB_CFB_FILLRECT |
317 | select FB_CFB_COPYAREA | 318 | select FB_CFB_COPYAREA |
318 | select FB_CFB_IMAGEBLIT | 319 | select FB_CFB_IMAGEBLIT |
@@ -979,6 +980,22 @@ config FB_PVR2 | |||
979 | (<file:drivers/video/pvr2fb.c>). Please see the file | 980 | (<file:drivers/video/pvr2fb.c>). Please see the file |
980 | <file:Documentation/fb/pvr2fb.txt>. | 981 | <file:Documentation/fb/pvr2fb.txt>. |
981 | 982 | ||
983 | config FB_OPENCORES | ||
984 | tristate "OpenCores VGA/LCD core 2.0 framebuffer support" | ||
985 | depends on FB | ||
986 | select FB_CFB_FILLRECT | ||
987 | select FB_CFB_COPYAREA | ||
988 | select FB_CFB_IMAGEBLIT | ||
989 | help | ||
990 | This enables support for the OpenCores VGA/LCD core. | ||
991 | |||
992 | The OpenCores VGA/LCD core is typically used together with | ||
993 | softcore CPUs (e.g. OpenRISC or Microblaze) or hard processor | ||
994 | systems (e.g. Altera socfpga or Xilinx Zynq) on FPGAs. | ||
995 | |||
996 | The source code and specification for the core is available at | ||
997 | <http://opencores.org/project,vga_lcd> | ||
998 | |||
982 | config FB_S1D13XXX | 999 | config FB_S1D13XXX |
983 | tristate "Epson S1D13XXX framebuffer support" | 1000 | tristate "Epson S1D13XXX framebuffer support" |
984 | depends on FB | 1001 | depends on FB |
diff --git a/drivers/video/Makefile b/drivers/video/Makefile index e8bae8dd4804..ae17ddf49a00 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile | |||
@@ -150,6 +150,7 @@ obj-$(CONFIG_FB_NUC900) += nuc900fb.o | |||
150 | obj-$(CONFIG_FB_JZ4740) += jz4740_fb.o | 150 | obj-$(CONFIG_FB_JZ4740) += jz4740_fb.o |
151 | obj-$(CONFIG_FB_PUV3_UNIGFX) += fb-puv3.o | 151 | obj-$(CONFIG_FB_PUV3_UNIGFX) += fb-puv3.o |
152 | obj-$(CONFIG_FB_HYPERV) += hyperv_fb.o | 152 | obj-$(CONFIG_FB_HYPERV) += hyperv_fb.o |
153 | obj-$(CONFIG_FB_OPENCORES) += ocfb.o | ||
153 | 154 | ||
154 | # Platform or fallback drivers go here | 155 | # Platform or fallback drivers go here |
155 | obj-$(CONFIG_FB_UVESA) += uvesafb.o | 156 | obj-$(CONFIG_FB_UVESA) += uvesafb.o |
diff --git a/drivers/video/amifb.c b/drivers/video/amifb.c index 0dac36ce09d6..518f790ef88a 100644 --- a/drivers/video/amifb.c +++ b/drivers/video/amifb.c | |||
@@ -3710,7 +3710,7 @@ default_chipset: | |||
3710 | if (!videomemory) { | 3710 | if (!videomemory) { |
3711 | dev_warn(&pdev->dev, | 3711 | dev_warn(&pdev->dev, |
3712 | "Unable to map videomem cached writethrough\n"); | 3712 | "Unable to map videomem cached writethrough\n"); |
3713 | info->screen_base = (char *)ZTWO_VADDR(info->fix.smem_start); | 3713 | info->screen_base = ZTWO_VADDR(info->fix.smem_start); |
3714 | } else | 3714 | } else |
3715 | info->screen_base = (char *)videomemory; | 3715 | info->screen_base = (char *)videomemory; |
3716 | 3716 | ||
diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c index a6b29bd4a12a..adc4ea2cc5a0 100644 --- a/drivers/video/arkfb.c +++ b/drivers/video/arkfb.c | |||
@@ -1014,7 +1014,7 @@ static int ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |||
1014 | 1014 | ||
1015 | vga_res.flags = IORESOURCE_IO; | 1015 | vga_res.flags = IORESOURCE_IO; |
1016 | 1016 | ||
1017 | pcibios_bus_to_resource(dev, &vga_res, &bus_reg); | 1017 | pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg); |
1018 | 1018 | ||
1019 | par->state.vgabase = (void __iomem *) vga_res.start; | 1019 | par->state.vgabase = (void __iomem *) vga_res.start; |
1020 | 1020 | ||
diff --git a/drivers/video/asiliantfb.c b/drivers/video/asiliantfb.c index d611f1a1ac53..7e8ddf00ccc2 100644 --- a/drivers/video/asiliantfb.c +++ b/drivers/video/asiliantfb.c | |||
@@ -589,7 +589,6 @@ static void asiliantfb_remove(struct pci_dev *dp) | |||
589 | fb_dealloc_cmap(&p->cmap); | 589 | fb_dealloc_cmap(&p->cmap); |
590 | iounmap(p->screen_base); | 590 | iounmap(p->screen_base); |
591 | release_mem_region(pci_resource_start(dp, 0), pci_resource_len(dp, 0)); | 591 | release_mem_region(pci_resource_start(dp, 0), pci_resource_len(dp, 0)); |
592 | pci_set_drvdata(dp, NULL); | ||
593 | framebuffer_release(p); | 592 | framebuffer_release(p); |
594 | } | 593 | } |
595 | 594 | ||
diff --git a/drivers/video/aty/aty128fb.c b/drivers/video/aty/aty128fb.c index 12ca031877d4..52108be69e77 100644 --- a/drivers/video/aty/aty128fb.c +++ b/drivers/video/aty/aty128fb.c | |||
@@ -357,11 +357,13 @@ static int default_lcd_on = 1; | |||
357 | static bool mtrr = true; | 357 | static bool mtrr = true; |
358 | #endif | 358 | #endif |
359 | 359 | ||
360 | #ifdef CONFIG_FB_ATY128_BACKLIGHT | ||
360 | #ifdef CONFIG_PMAC_BACKLIGHT | 361 | #ifdef CONFIG_PMAC_BACKLIGHT |
361 | static int backlight = 1; | 362 | static int backlight = 1; |
362 | #else | 363 | #else |
363 | static int backlight = 0; | 364 | static int backlight = 0; |
364 | #endif | 365 | #endif |
366 | #endif | ||
365 | 367 | ||
366 | /* PLL constants */ | 368 | /* PLL constants */ |
367 | struct aty128_constants { | 369 | struct aty128_constants { |
@@ -1671,7 +1673,9 @@ static int aty128fb_setup(char *options) | |||
1671 | default_crt_on = simple_strtoul(this_opt+4, NULL, 0); | 1673 | default_crt_on = simple_strtoul(this_opt+4, NULL, 0); |
1672 | continue; | 1674 | continue; |
1673 | } else if (!strncmp(this_opt, "backlight:", 10)) { | 1675 | } else if (!strncmp(this_opt, "backlight:", 10)) { |
1676 | #ifdef CONFIG_FB_ATY128_BACKLIGHT | ||
1674 | backlight = simple_strtoul(this_opt+10, NULL, 0); | 1677 | backlight = simple_strtoul(this_opt+10, NULL, 0); |
1678 | #endif | ||
1675 | continue; | 1679 | continue; |
1676 | } | 1680 | } |
1677 | #ifdef CONFIG_MTRR | 1681 | #ifdef CONFIG_MTRR |
diff --git a/drivers/video/backlight/hp680_bl.c b/drivers/video/backlight/hp680_bl.c index 00076ecfe9b8..8ea42b8d9bc8 100644 --- a/drivers/video/backlight/hp680_bl.c +++ b/drivers/video/backlight/hp680_bl.c | |||
@@ -110,8 +110,8 @@ static int hp680bl_probe(struct platform_device *pdev) | |||
110 | memset(&props, 0, sizeof(struct backlight_properties)); | 110 | memset(&props, 0, sizeof(struct backlight_properties)); |
111 | props.type = BACKLIGHT_RAW; | 111 | props.type = BACKLIGHT_RAW; |
112 | props.max_brightness = HP680_MAX_INTENSITY; | 112 | props.max_brightness = HP680_MAX_INTENSITY; |
113 | bd = backlight_device_register("hp680-bl", &pdev->dev, NULL, | 113 | bd = devm_backlight_device_register(&pdev->dev, "hp680-bl", &pdev->dev, |
114 | &hp680bl_ops, &props); | 114 | NULL, &hp680bl_ops, &props); |
115 | if (IS_ERR(bd)) | 115 | if (IS_ERR(bd)) |
116 | return PTR_ERR(bd); | 116 | return PTR_ERR(bd); |
117 | 117 | ||
@@ -131,8 +131,6 @@ static int hp680bl_remove(struct platform_device *pdev) | |||
131 | bd->props.power = 0; | 131 | bd->props.power = 0; |
132 | hp680bl_send_intensity(bd); | 132 | hp680bl_send_intensity(bd); |
133 | 133 | ||
134 | backlight_device_unregister(bd); | ||
135 | |||
136 | return 0; | 134 | return 0; |
137 | } | 135 | } |
138 | 136 | ||
diff --git a/drivers/video/backlight/jornada720_bl.c b/drivers/video/backlight/jornada720_bl.c index 3ccb89340f22..6ce96b4a8796 100644 --- a/drivers/video/backlight/jornada720_bl.c +++ b/drivers/video/backlight/jornada720_bl.c | |||
@@ -115,9 +115,10 @@ static int jornada_bl_probe(struct platform_device *pdev) | |||
115 | memset(&props, 0, sizeof(struct backlight_properties)); | 115 | memset(&props, 0, sizeof(struct backlight_properties)); |
116 | props.type = BACKLIGHT_RAW; | 116 | props.type = BACKLIGHT_RAW; |
117 | props.max_brightness = BL_MAX_BRIGHT; | 117 | props.max_brightness = BL_MAX_BRIGHT; |
118 | bd = backlight_device_register(S1D_DEVICENAME, &pdev->dev, NULL, | ||
119 | &jornada_bl_ops, &props); | ||
120 | 118 | ||
119 | bd = devm_backlight_device_register(&pdev->dev, S1D_DEVICENAME, | ||
120 | &pdev->dev, NULL, &jornada_bl_ops, | ||
121 | &props); | ||
121 | if (IS_ERR(bd)) { | 122 | if (IS_ERR(bd)) { |
122 | ret = PTR_ERR(bd); | 123 | ret = PTR_ERR(bd); |
123 | dev_err(&pdev->dev, "failed to register device, err=%x\n", ret); | 124 | dev_err(&pdev->dev, "failed to register device, err=%x\n", ret); |
@@ -139,18 +140,8 @@ static int jornada_bl_probe(struct platform_device *pdev) | |||
139 | return 0; | 140 | return 0; |
140 | } | 141 | } |
141 | 142 | ||
142 | static int jornada_bl_remove(struct platform_device *pdev) | ||
143 | { | ||
144 | struct backlight_device *bd = platform_get_drvdata(pdev); | ||
145 | |||
146 | backlight_device_unregister(bd); | ||
147 | |||
148 | return 0; | ||
149 | } | ||
150 | |||
151 | static struct platform_driver jornada_bl_driver = { | 143 | static struct platform_driver jornada_bl_driver = { |
152 | .probe = jornada_bl_probe, | 144 | .probe = jornada_bl_probe, |
153 | .remove = jornada_bl_remove, | ||
154 | .driver = { | 145 | .driver = { |
155 | .name = "jornada_bl", | 146 | .name = "jornada_bl", |
156 | }, | 147 | }, |
diff --git a/drivers/video/backlight/jornada720_lcd.c b/drivers/video/backlight/jornada720_lcd.c index b061413f1a65..da3876c9b3ae 100644 --- a/drivers/video/backlight/jornada720_lcd.c +++ b/drivers/video/backlight/jornada720_lcd.c | |||
@@ -100,7 +100,8 @@ static int jornada_lcd_probe(struct platform_device *pdev) | |||
100 | struct lcd_device *lcd_device; | 100 | struct lcd_device *lcd_device; |
101 | int ret; | 101 | int ret; |
102 | 102 | ||
103 | lcd_device = lcd_device_register(S1D_DEVICENAME, &pdev->dev, NULL, &jornada_lcd_props); | 103 | lcd_device = devm_lcd_device_register(&pdev->dev, S1D_DEVICENAME, |
104 | &pdev->dev, NULL, &jornada_lcd_props); | ||
104 | 105 | ||
105 | if (IS_ERR(lcd_device)) { | 106 | if (IS_ERR(lcd_device)) { |
106 | ret = PTR_ERR(lcd_device); | 107 | ret = PTR_ERR(lcd_device); |
@@ -119,18 +120,8 @@ static int jornada_lcd_probe(struct platform_device *pdev) | |||
119 | return 0; | 120 | return 0; |
120 | } | 121 | } |
121 | 122 | ||
122 | static int jornada_lcd_remove(struct platform_device *pdev) | ||
123 | { | ||
124 | struct lcd_device *lcd_device = platform_get_drvdata(pdev); | ||
125 | |||
126 | lcd_device_unregister(lcd_device); | ||
127 | |||
128 | return 0; | ||
129 | } | ||
130 | |||
131 | static struct platform_driver jornada_lcd_driver = { | 123 | static struct platform_driver jornada_lcd_driver = { |
132 | .probe = jornada_lcd_probe, | 124 | .probe = jornada_lcd_probe, |
133 | .remove = jornada_lcd_remove, | ||
134 | .driver = { | 125 | .driver = { |
135 | .name = "jornada_lcd", | 126 | .name = "jornada_lcd", |
136 | }, | 127 | }, |
diff --git a/drivers/video/backlight/kb3886_bl.c b/drivers/video/backlight/kb3886_bl.c index 7592cc25c963..84a110a719cb 100644 --- a/drivers/video/backlight/kb3886_bl.c +++ b/drivers/video/backlight/kb3886_bl.c | |||
@@ -78,7 +78,7 @@ static struct kb3886bl_machinfo *bl_machinfo; | |||
78 | static unsigned long kb3886bl_flags; | 78 | static unsigned long kb3886bl_flags; |
79 | #define KB3886BL_SUSPENDED 0x01 | 79 | #define KB3886BL_SUSPENDED 0x01 |
80 | 80 | ||
81 | static struct dmi_system_id __initdata kb3886bl_device_table[] = { | 81 | static struct dmi_system_id kb3886bl_device_table[] __initdata = { |
82 | { | 82 | { |
83 | .ident = "Sahara Touch-iT", | 83 | .ident = "Sahara Touch-iT", |
84 | .matches = { | 84 | .matches = { |
diff --git a/drivers/video/backlight/l4f00242t03.c b/drivers/video/backlight/l4f00242t03.c index b5fc13bc24e7..63e763828e0e 100644 --- a/drivers/video/backlight/l4f00242t03.c +++ b/drivers/video/backlight/l4f00242t03.c | |||
@@ -223,8 +223,8 @@ static int l4f00242t03_probe(struct spi_device *spi) | |||
223 | return PTR_ERR(priv->core_reg); | 223 | return PTR_ERR(priv->core_reg); |
224 | } | 224 | } |
225 | 225 | ||
226 | priv->ld = lcd_device_register("l4f00242t03", | 226 | priv->ld = devm_lcd_device_register(&spi->dev, "l4f00242t03", &spi->dev, |
227 | &spi->dev, priv, &l4f_ops); | 227 | priv, &l4f_ops); |
228 | if (IS_ERR(priv->ld)) | 228 | if (IS_ERR(priv->ld)) |
229 | return PTR_ERR(priv->ld); | 229 | return PTR_ERR(priv->ld); |
230 | 230 | ||
@@ -243,8 +243,6 @@ static int l4f00242t03_remove(struct spi_device *spi) | |||
243 | struct l4f00242t03_priv *priv = spi_get_drvdata(spi); | 243 | struct l4f00242t03_priv *priv = spi_get_drvdata(spi); |
244 | 244 | ||
245 | l4f00242t03_lcd_power_set(priv->ld, FB_BLANK_POWERDOWN); | 245 | l4f00242t03_lcd_power_set(priv->ld, FB_BLANK_POWERDOWN); |
246 | lcd_device_unregister(priv->ld); | ||
247 | |||
248 | return 0; | 246 | return 0; |
249 | } | 247 | } |
250 | 248 | ||
diff --git a/drivers/video/backlight/lcd.c b/drivers/video/backlight/lcd.c index 93cf15efc717..7de847df224f 100644 --- a/drivers/video/backlight/lcd.c +++ b/drivers/video/backlight/lcd.c | |||
@@ -228,7 +228,7 @@ struct lcd_device *lcd_device_register(const char *name, struct device *parent, | |||
228 | 228 | ||
229 | rc = device_register(&new_ld->dev); | 229 | rc = device_register(&new_ld->dev); |
230 | if (rc) { | 230 | if (rc) { |
231 | kfree(new_ld); | 231 | put_device(&new_ld->dev); |
232 | return ERR_PTR(rc); | 232 | return ERR_PTR(rc); |
233 | } | 233 | } |
234 | 234 | ||
diff --git a/drivers/video/backlight/lp855x_bl.c b/drivers/video/backlight/lp855x_bl.c index cae80d555e84..2ca3a040007b 100644 --- a/drivers/video/backlight/lp855x_bl.c +++ b/drivers/video/backlight/lp855x_bl.c | |||
@@ -125,7 +125,7 @@ static bool lp855x_is_valid_rom_area(struct lp855x *lp, u8 addr) | |||
125 | return false; | 125 | return false; |
126 | } | 126 | } |
127 | 127 | ||
128 | return (addr >= start && addr <= end); | 128 | return addr >= start && addr <= end; |
129 | } | 129 | } |
130 | 130 | ||
131 | static int lp8557_bl_off(struct lp855x *lp) | 131 | static int lp8557_bl_off(struct lp855x *lp) |
diff --git a/drivers/video/backlight/lp8788_bl.c b/drivers/video/backlight/lp8788_bl.c index e49905d495dc..daba34dc46d4 100644 --- a/drivers/video/backlight/lp8788_bl.c +++ b/drivers/video/backlight/lp8788_bl.c | |||
@@ -63,13 +63,13 @@ static struct lp8788_bl_config default_bl_config = { | |||
63 | 63 | ||
64 | static inline bool is_brightness_ctrl_by_pwm(enum lp8788_bl_ctrl_mode mode) | 64 | static inline bool is_brightness_ctrl_by_pwm(enum lp8788_bl_ctrl_mode mode) |
65 | { | 65 | { |
66 | return (mode == LP8788_BL_COMB_PWM_BASED); | 66 | return mode == LP8788_BL_COMB_PWM_BASED; |
67 | } | 67 | } |
68 | 68 | ||
69 | static inline bool is_brightness_ctrl_by_register(enum lp8788_bl_ctrl_mode mode) | 69 | static inline bool is_brightness_ctrl_by_register(enum lp8788_bl_ctrl_mode mode) |
70 | { | 70 | { |
71 | return (mode == LP8788_BL_REGISTER_ONLY || | 71 | return mode == LP8788_BL_REGISTER_ONLY || |
72 | mode == LP8788_BL_COMB_REGISTER_BASED); | 72 | mode == LP8788_BL_COMB_REGISTER_BASED; |
73 | } | 73 | } |
74 | 74 | ||
75 | static int lp8788_backlight_configure(struct lp8788_bl *bl) | 75 | static int lp8788_backlight_configure(struct lp8788_bl *bl) |
diff --git a/drivers/video/backlight/omap1_bl.c b/drivers/video/backlight/omap1_bl.c index ac11a4650c19..a0dcd88ac74f 100644 --- a/drivers/video/backlight/omap1_bl.c +++ b/drivers/video/backlight/omap1_bl.c | |||
@@ -146,8 +146,8 @@ static int omapbl_probe(struct platform_device *pdev) | |||
146 | memset(&props, 0, sizeof(struct backlight_properties)); | 146 | memset(&props, 0, sizeof(struct backlight_properties)); |
147 | props.type = BACKLIGHT_RAW; | 147 | props.type = BACKLIGHT_RAW; |
148 | props.max_brightness = OMAPBL_MAX_INTENSITY; | 148 | props.max_brightness = OMAPBL_MAX_INTENSITY; |
149 | dev = backlight_device_register("omap-bl", &pdev->dev, bl, &omapbl_ops, | 149 | dev = devm_backlight_device_register(&pdev->dev, "omap-bl", &pdev->dev, |
150 | &props); | 150 | bl, &omapbl_ops, &props); |
151 | if (IS_ERR(dev)) | 151 | if (IS_ERR(dev)) |
152 | return PTR_ERR(dev); | 152 | return PTR_ERR(dev); |
153 | 153 | ||
@@ -170,20 +170,10 @@ static int omapbl_probe(struct platform_device *pdev) | |||
170 | return 0; | 170 | return 0; |
171 | } | 171 | } |
172 | 172 | ||
173 | static int omapbl_remove(struct platform_device *pdev) | ||
174 | { | ||
175 | struct backlight_device *dev = platform_get_drvdata(pdev); | ||
176 | |||
177 | backlight_device_unregister(dev); | ||
178 | |||
179 | return 0; | ||
180 | } | ||
181 | |||
182 | static SIMPLE_DEV_PM_OPS(omapbl_pm_ops, omapbl_suspend, omapbl_resume); | 173 | static SIMPLE_DEV_PM_OPS(omapbl_pm_ops, omapbl_suspend, omapbl_resume); |
183 | 174 | ||
184 | static struct platform_driver omapbl_driver = { | 175 | static struct platform_driver omapbl_driver = { |
185 | .probe = omapbl_probe, | 176 | .probe = omapbl_probe, |
186 | .remove = omapbl_remove, | ||
187 | .driver = { | 177 | .driver = { |
188 | .name = "omap-bl", | 178 | .name = "omap-bl", |
189 | .pm = &omapbl_pm_ops, | 179 | .pm = &omapbl_pm_ops, |
diff --git a/drivers/video/backlight/ot200_bl.c b/drivers/video/backlight/ot200_bl.c index fdbb6ee5027c..f5a5202dd79d 100644 --- a/drivers/video/backlight/ot200_bl.c +++ b/drivers/video/backlight/ot200_bl.c | |||
@@ -118,8 +118,9 @@ static int ot200_backlight_probe(struct platform_device *pdev) | |||
118 | props.brightness = 100; | 118 | props.brightness = 100; |
119 | props.type = BACKLIGHT_RAW; | 119 | props.type = BACKLIGHT_RAW; |
120 | 120 | ||
121 | bl = backlight_device_register(dev_name(&pdev->dev), &pdev->dev, data, | 121 | bl = devm_backlight_device_register(&pdev->dev, dev_name(&pdev->dev), |
122 | &ot200_backlight_ops, &props); | 122 | &pdev->dev, data, &ot200_backlight_ops, |
123 | &props); | ||
123 | if (IS_ERR(bl)) { | 124 | if (IS_ERR(bl)) { |
124 | dev_err(&pdev->dev, "failed to register backlight\n"); | 125 | dev_err(&pdev->dev, "failed to register backlight\n"); |
125 | retval = PTR_ERR(bl); | 126 | retval = PTR_ERR(bl); |
@@ -137,10 +138,6 @@ error_devm_kzalloc: | |||
137 | 138 | ||
138 | static int ot200_backlight_remove(struct platform_device *pdev) | 139 | static int ot200_backlight_remove(struct platform_device *pdev) |
139 | { | 140 | { |
140 | struct backlight_device *bl = platform_get_drvdata(pdev); | ||
141 | |||
142 | backlight_device_unregister(bl); | ||
143 | |||
144 | /* on module unload set brightness to 100% */ | 141 | /* on module unload set brightness to 100% */ |
145 | cs5535_mfgpt_write(pwm_timer, MFGPT_REG_COUNTER, 0); | 142 | cs5535_mfgpt_write(pwm_timer, MFGPT_REG_COUNTER, 0); |
146 | cs5535_mfgpt_write(pwm_timer, MFGPT_REG_SETUP, MFGPT_SETUP_CNTEN); | 143 | cs5535_mfgpt_write(pwm_timer, MFGPT_REG_SETUP, MFGPT_SETUP_CNTEN); |
diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c index fb80d68f4d33..b75201ff46f6 100644 --- a/drivers/video/backlight/pwm_bl.c +++ b/drivers/video/backlight/pwm_bl.c | |||
@@ -241,7 +241,6 @@ static int pwm_backlight_probe(struct platform_device *pdev) | |||
241 | 241 | ||
242 | pb = devm_kzalloc(&pdev->dev, sizeof(*pb), GFP_KERNEL); | 242 | pb = devm_kzalloc(&pdev->dev, sizeof(*pb), GFP_KERNEL); |
243 | if (!pb) { | 243 | if (!pb) { |
244 | dev_err(&pdev->dev, "no memory for state\n"); | ||
245 | ret = -ENOMEM; | 244 | ret = -ENOMEM; |
246 | goto err_alloc; | 245 | goto err_alloc; |
247 | } | 246 | } |
diff --git a/drivers/video/backlight/tosa_bl.c b/drivers/video/backlight/tosa_bl.c index b8db9338cacd..3ad676558c80 100644 --- a/drivers/video/backlight/tosa_bl.c +++ b/drivers/video/backlight/tosa_bl.c | |||
@@ -105,8 +105,9 @@ static int tosa_bl_probe(struct i2c_client *client, | |||
105 | memset(&props, 0, sizeof(struct backlight_properties)); | 105 | memset(&props, 0, sizeof(struct backlight_properties)); |
106 | props.type = BACKLIGHT_RAW; | 106 | props.type = BACKLIGHT_RAW; |
107 | props.max_brightness = 512 - 1; | 107 | props.max_brightness = 512 - 1; |
108 | data->bl = backlight_device_register("tosa-bl", &client->dev, data, | 108 | data->bl = devm_backlight_device_register(&client->dev, "tosa-bl", |
109 | &bl_ops, &props); | 109 | &client->dev, data, &bl_ops, |
110 | &props); | ||
110 | if (IS_ERR(data->bl)) { | 111 | if (IS_ERR(data->bl)) { |
111 | ret = PTR_ERR(data->bl); | 112 | ret = PTR_ERR(data->bl); |
112 | goto err_reg; | 113 | goto err_reg; |
@@ -128,9 +129,7 @@ static int tosa_bl_remove(struct i2c_client *client) | |||
128 | { | 129 | { |
129 | struct tosa_bl_data *data = i2c_get_clientdata(client); | 130 | struct tosa_bl_data *data = i2c_get_clientdata(client); |
130 | 131 | ||
131 | backlight_device_unregister(data->bl); | ||
132 | data->bl = NULL; | 132 | data->bl = NULL; |
133 | |||
134 | return 0; | 133 | return 0; |
135 | } | 134 | } |
136 | 135 | ||
diff --git a/drivers/video/backlight/tosa_lcd.c b/drivers/video/backlight/tosa_lcd.c index be5d636764bf..f08d641ccd01 100644 --- a/drivers/video/backlight/tosa_lcd.c +++ b/drivers/video/backlight/tosa_lcd.c | |||
@@ -206,8 +206,8 @@ static int tosa_lcd_probe(struct spi_device *spi) | |||
206 | 206 | ||
207 | tosa_lcd_tg_on(data); | 207 | tosa_lcd_tg_on(data); |
208 | 208 | ||
209 | data->lcd = lcd_device_register("tosa-lcd", &spi->dev, data, | 209 | data->lcd = devm_lcd_device_register(&spi->dev, "tosa-lcd", &spi->dev, |
210 | &tosa_lcd_ops); | 210 | data, &tosa_lcd_ops); |
211 | 211 | ||
212 | if (IS_ERR(data->lcd)) { | 212 | if (IS_ERR(data->lcd)) { |
213 | ret = PTR_ERR(data->lcd); | 213 | ret = PTR_ERR(data->lcd); |
@@ -226,8 +226,6 @@ static int tosa_lcd_remove(struct spi_device *spi) | |||
226 | { | 226 | { |
227 | struct tosa_lcd_data *data = spi_get_drvdata(spi); | 227 | struct tosa_lcd_data *data = spi_get_drvdata(spi); |
228 | 228 | ||
229 | lcd_device_unregister(data->lcd); | ||
230 | |||
231 | if (data->i2c) | 229 | if (data->i2c) |
232 | i2c_unregister_device(data->i2c); | 230 | i2c_unregister_device(data->i2c); |
233 | 231 | ||
diff --git a/drivers/video/cirrusfb.c b/drivers/video/cirrusfb.c index 5aab9b9dc210..d992aa5eb3f0 100644 --- a/drivers/video/cirrusfb.c +++ b/drivers/video/cirrusfb.c | |||
@@ -2256,7 +2256,7 @@ static int cirrusfb_zorro_register(struct zorro_dev *z, | |||
2256 | 2256 | ||
2257 | info->fix.mmio_start = regbase; | 2257 | info->fix.mmio_start = regbase; |
2258 | cinfo->regbase = regbase > 16 * MB_ ? ioremap(regbase, 64 * 1024) | 2258 | cinfo->regbase = regbase > 16 * MB_ ? ioremap(regbase, 64 * 1024) |
2259 | : (caddr_t)ZTWO_VADDR(regbase); | 2259 | : ZTWO_VADDR(regbase); |
2260 | if (!cinfo->regbase) { | 2260 | if (!cinfo->regbase) { |
2261 | dev_err(info->device, "Cannot map registers\n"); | 2261 | dev_err(info->device, "Cannot map registers\n"); |
2262 | error = -EIO; | 2262 | error = -EIO; |
@@ -2266,7 +2266,7 @@ static int cirrusfb_zorro_register(struct zorro_dev *z, | |||
2266 | info->fix.smem_start = rambase; | 2266 | info->fix.smem_start = rambase; |
2267 | info->screen_size = ramsize; | 2267 | info->screen_size = ramsize; |
2268 | info->screen_base = rambase > 16 * MB_ ? ioremap(rambase, ramsize) | 2268 | info->screen_base = rambase > 16 * MB_ ? ioremap(rambase, ramsize) |
2269 | : (caddr_t)ZTWO_VADDR(rambase); | 2269 | : ZTWO_VADDR(rambase); |
2270 | if (!info->screen_base) { | 2270 | if (!info->screen_base) { |
2271 | dev_err(info->device, "Cannot map video RAM\n"); | 2271 | dev_err(info->device, "Cannot map video RAM\n"); |
2272 | error = -EIO; | 2272 | error = -EIO; |
diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig index 846caab75a46..fe1cd0148e13 100644 --- a/drivers/video/console/Kconfig +++ b/drivers/video/console/Kconfig | |||
@@ -8,7 +8,8 @@ config VGA_CONSOLE | |||
8 | bool "VGA text console" if EXPERT || !X86 | 8 | bool "VGA text console" if EXPERT || !X86 |
9 | depends on !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && \ | 9 | depends on !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && \ |
10 | !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && !CRIS && \ | 10 | !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && !CRIS && \ |
11 | (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) | 11 | (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) && \ |
12 | !ARM64 | ||
12 | default y | 13 | default y |
13 | help | 14 | help |
14 | Saying Y here will allow you to use Linux in text mode through a | 15 | Saying Y here will allow you to use Linux in text mode through a |
diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c index cd8a8027f8ae..4e39291ac8b4 100644 --- a/drivers/video/console/fbcon.c +++ b/drivers/video/console/fbcon.c | |||
@@ -3547,8 +3547,10 @@ static void fbcon_exit(void) | |||
3547 | "no")); | 3547 | "no")); |
3548 | 3548 | ||
3549 | for (j = first_fb_vc; j <= last_fb_vc; j++) { | 3549 | for (j = first_fb_vc; j <= last_fb_vc; j++) { |
3550 | if (con2fb_map[j] == i) | 3550 | if (con2fb_map[j] == i) { |
3551 | mapped = 1; | 3551 | mapped = 1; |
3552 | break; | ||
3553 | } | ||
3552 | } | 3554 | } |
3553 | 3555 | ||
3554 | if (mapped) { | 3556 | if (mapped) { |
@@ -3561,6 +3563,7 @@ static void fbcon_exit(void) | |||
3561 | 3563 | ||
3562 | fbcon_del_cursor_timer(info); | 3564 | fbcon_del_cursor_timer(info); |
3563 | kfree(ops->cursor_src); | 3565 | kfree(ops->cursor_src); |
3566 | kfree(ops->cursor_state.mask); | ||
3564 | kfree(info->fbcon_par); | 3567 | kfree(info->fbcon_par); |
3565 | info->fbcon_par = NULL; | 3568 | info->fbcon_par = NULL; |
3566 | } | 3569 | } |
diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c index 010d19105ebc..7309ac704e26 100644 --- a/drivers/video/fbmem.c +++ b/drivers/video/fbmem.c | |||
@@ -1577,10 +1577,10 @@ static bool fb_do_apertures_overlap(struct apertures_struct *gena, | |||
1577 | static int do_unregister_framebuffer(struct fb_info *fb_info); | 1577 | static int do_unregister_framebuffer(struct fb_info *fb_info); |
1578 | 1578 | ||
1579 | #define VGA_FB_PHYS 0xA0000 | 1579 | #define VGA_FB_PHYS 0xA0000 |
1580 | static void do_remove_conflicting_framebuffers(struct apertures_struct *a, | 1580 | static int do_remove_conflicting_framebuffers(struct apertures_struct *a, |
1581 | const char *name, bool primary) | 1581 | const char *name, bool primary) |
1582 | { | 1582 | { |
1583 | int i; | 1583 | int i, ret; |
1584 | 1584 | ||
1585 | /* check all firmware fbs and kick off if the base addr overlaps */ | 1585 | /* check all firmware fbs and kick off if the base addr overlaps */ |
1586 | for (i = 0 ; i < FB_MAX; i++) { | 1586 | for (i = 0 ; i < FB_MAX; i++) { |
@@ -1599,22 +1599,29 @@ static void do_remove_conflicting_framebuffers(struct apertures_struct *a, | |||
1599 | printk(KERN_INFO "fb: conflicting fb hw usage " | 1599 | printk(KERN_INFO "fb: conflicting fb hw usage " |
1600 | "%s vs %s - removing generic driver\n", | 1600 | "%s vs %s - removing generic driver\n", |
1601 | name, registered_fb[i]->fix.id); | 1601 | name, registered_fb[i]->fix.id); |
1602 | do_unregister_framebuffer(registered_fb[i]); | 1602 | ret = do_unregister_framebuffer(registered_fb[i]); |
1603 | if (ret) | ||
1604 | return ret; | ||
1603 | } | 1605 | } |
1604 | } | 1606 | } |
1607 | |||
1608 | return 0; | ||
1605 | } | 1609 | } |
1606 | 1610 | ||
1607 | static int do_register_framebuffer(struct fb_info *fb_info) | 1611 | static int do_register_framebuffer(struct fb_info *fb_info) |
1608 | { | 1612 | { |
1609 | int i; | 1613 | int i, ret; |
1610 | struct fb_event event; | 1614 | struct fb_event event; |
1611 | struct fb_videomode mode; | 1615 | struct fb_videomode mode; |
1612 | 1616 | ||
1613 | if (fb_check_foreignness(fb_info)) | 1617 | if (fb_check_foreignness(fb_info)) |
1614 | return -ENOSYS; | 1618 | return -ENOSYS; |
1615 | 1619 | ||
1616 | do_remove_conflicting_framebuffers(fb_info->apertures, fb_info->fix.id, | 1620 | ret = do_remove_conflicting_framebuffers(fb_info->apertures, |
1617 | fb_is_primary_device(fb_info)); | 1621 | fb_info->fix.id, |
1622 | fb_is_primary_device(fb_info)); | ||
1623 | if (ret) | ||
1624 | return ret; | ||
1618 | 1625 | ||
1619 | if (num_registered_fb == FB_MAX) | 1626 | if (num_registered_fb == FB_MAX) |
1620 | return -ENXIO; | 1627 | return -ENXIO; |
@@ -1739,12 +1746,16 @@ int unlink_framebuffer(struct fb_info *fb_info) | |||
1739 | } | 1746 | } |
1740 | EXPORT_SYMBOL(unlink_framebuffer); | 1747 | EXPORT_SYMBOL(unlink_framebuffer); |
1741 | 1748 | ||
1742 | void remove_conflicting_framebuffers(struct apertures_struct *a, | 1749 | int remove_conflicting_framebuffers(struct apertures_struct *a, |
1743 | const char *name, bool primary) | 1750 | const char *name, bool primary) |
1744 | { | 1751 | { |
1752 | int ret; | ||
1753 | |||
1745 | mutex_lock(®istration_lock); | 1754 | mutex_lock(®istration_lock); |
1746 | do_remove_conflicting_framebuffers(a, name, primary); | 1755 | ret = do_remove_conflicting_framebuffers(a, name, primary); |
1747 | mutex_unlock(®istration_lock); | 1756 | mutex_unlock(®istration_lock); |
1757 | |||
1758 | return ret; | ||
1748 | } | 1759 | } |
1749 | EXPORT_SYMBOL(remove_conflicting_framebuffers); | 1760 | EXPORT_SYMBOL(remove_conflicting_framebuffers); |
1750 | 1761 | ||
@@ -1930,6 +1941,9 @@ int fb_get_options(const char *name, char **option) | |||
1930 | options = opt + name_len + 1; | 1941 | options = opt + name_len + 1; |
1931 | } | 1942 | } |
1932 | } | 1943 | } |
1944 | /* No match, pass global option */ | ||
1945 | if (!options && option && fb_mode_option) | ||
1946 | options = kstrdup(fb_mode_option, GFP_KERNEL); | ||
1933 | if (options && !strncmp(options, "off", 3)) | 1947 | if (options && !strncmp(options, "off", 3)) |
1934 | retval = 1; | 1948 | retval = 1; |
1935 | 1949 | ||
diff --git a/drivers/video/i810/i810_main.c b/drivers/video/i810/i810_main.c index 038192ac7369..bb674e431741 100644 --- a/drivers/video/i810/i810_main.c +++ b/drivers/video/i810/i810_main.c | |||
@@ -2011,9 +2011,7 @@ static int i810fb_init_pci(struct pci_dev *dev, | |||
2011 | struct fb_info *info; | 2011 | struct fb_info *info; |
2012 | struct i810fb_par *par = NULL; | 2012 | struct i810fb_par *par = NULL; |
2013 | struct fb_videomode mode; | 2013 | struct fb_videomode mode; |
2014 | int i, err = -1, vfreq, hfreq, pixclock; | 2014 | int err = -1, vfreq, hfreq, pixclock; |
2015 | |||
2016 | i = 0; | ||
2017 | 2015 | ||
2018 | info = framebuffer_alloc(sizeof(struct i810fb_par), &dev->dev); | 2016 | info = framebuffer_alloc(sizeof(struct i810fb_par), &dev->dev); |
2019 | if (!info) | 2017 | if (!info) |
diff --git a/drivers/video/logo/logo.c b/drivers/video/logo/logo.c index 080c35b34bbb..b670cbda38e3 100644 --- a/drivers/video/logo/logo.c +++ b/drivers/video/logo/logo.c | |||
@@ -17,10 +17,6 @@ | |||
17 | #include <asm/setup.h> | 17 | #include <asm/setup.h> |
18 | #endif | 18 | #endif |
19 | 19 | ||
20 | #ifdef CONFIG_MIPS | ||
21 | #include <asm/bootinfo.h> | ||
22 | #endif | ||
23 | |||
24 | static bool nologo; | 20 | static bool nologo; |
25 | module_param(nologo, bool, 0); | 21 | module_param(nologo, bool, 0); |
26 | MODULE_PARM_DESC(nologo, "Disables startup logo"); | 22 | MODULE_PARM_DESC(nologo, "Disables startup logo"); |
diff --git a/drivers/video/macfb.c b/drivers/video/macfb.c index 5bd2eb8d4f39..cda7587cbc86 100644 --- a/drivers/video/macfb.c +++ b/drivers/video/macfb.c | |||
@@ -34,7 +34,6 @@ | |||
34 | #include <linux/fb.h> | 34 | #include <linux/fb.h> |
35 | 35 | ||
36 | #include <asm/setup.h> | 36 | #include <asm/setup.h> |
37 | #include <asm/bootinfo.h> | ||
38 | #include <asm/macintosh.h> | 37 | #include <asm/macintosh.h> |
39 | #include <asm/io.h> | 38 | #include <asm/io.h> |
40 | 39 | ||
diff --git a/drivers/video/mmp/core.c b/drivers/video/mmp/core.c index 84de2632857a..b563b920f159 100644 --- a/drivers/video/mmp/core.c +++ b/drivers/video/mmp/core.c | |||
@@ -30,7 +30,7 @@ static struct mmp_overlay *path_get_overlay(struct mmp_path *path, | |||
30 | { | 30 | { |
31 | if (path && overlay_id < path->overlay_num) | 31 | if (path && overlay_id < path->overlay_num) |
32 | return &path->overlays[overlay_id]; | 32 | return &path->overlays[overlay_id]; |
33 | return 0; | 33 | return NULL; |
34 | } | 34 | } |
35 | 35 | ||
36 | static int path_check_status(struct mmp_path *path) | 36 | static int path_check_status(struct mmp_path *path) |
@@ -173,7 +173,7 @@ struct mmp_path *mmp_register_path(struct mmp_path_info *info) | |||
173 | + sizeof(struct mmp_overlay) * info->overlay_num; | 173 | + sizeof(struct mmp_overlay) * info->overlay_num; |
174 | path = kzalloc(size, GFP_KERNEL); | 174 | path = kzalloc(size, GFP_KERNEL); |
175 | if (!path) | 175 | if (!path) |
176 | goto failed; | 176 | return NULL; |
177 | 177 | ||
178 | /* path set */ | 178 | /* path set */ |
179 | mutex_init(&path->access_ok); | 179 | mutex_init(&path->access_ok); |
@@ -219,11 +219,6 @@ struct mmp_path *mmp_register_path(struct mmp_path_info *info) | |||
219 | 219 | ||
220 | mutex_unlock(&disp_lock); | 220 | mutex_unlock(&disp_lock); |
221 | return path; | 221 | return path; |
222 | |||
223 | failed: | ||
224 | kfree(path); | ||
225 | mutex_unlock(&disp_lock); | ||
226 | return NULL; | ||
227 | } | 222 | } |
228 | EXPORT_SYMBOL_GPL(mmp_register_path); | 223 | EXPORT_SYMBOL_GPL(mmp_register_path); |
229 | 224 | ||
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c index 804f874d32d3..142e860fb527 100644 --- a/drivers/video/mx3fb.c +++ b/drivers/video/mx3fb.c | |||
@@ -1263,7 +1263,7 @@ static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len, | |||
1263 | 1263 | ||
1264 | fbi->screen_base = dma_alloc_writecombine(fbi->device, | 1264 | fbi->screen_base = dma_alloc_writecombine(fbi->device, |
1265 | mem_len, | 1265 | mem_len, |
1266 | &addr, GFP_DMA); | 1266 | &addr, GFP_DMA | GFP_KERNEL); |
1267 | 1267 | ||
1268 | if (!fbi->screen_base) { | 1268 | if (!fbi->screen_base) { |
1269 | dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n", | 1269 | dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n", |
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 27197a8048c0..accf48a2cce4 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c | |||
@@ -49,6 +49,7 @@ | |||
49 | #include <linux/fb.h> | 49 | #include <linux/fb.h> |
50 | #include <linux/regulator/consumer.h> | 50 | #include <linux/regulator/consumer.h> |
51 | #include <video/of_display_timing.h> | 51 | #include <video/of_display_timing.h> |
52 | #include <video/of_videomode.h> | ||
52 | #include <video/videomode.h> | 53 | #include <video/videomode.h> |
53 | 54 | ||
54 | #define REG_SET 4 | 55 | #define REG_SET 4 |
@@ -297,7 +298,7 @@ static int mxsfb_check_var(struct fb_var_screeninfo *var, | |||
297 | } | 298 | } |
298 | break; | 299 | break; |
299 | default: | 300 | default: |
300 | pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel); | 301 | pr_err("Unsupported colour depth: %u\n", var->bits_per_pixel); |
301 | return -EINVAL; | 302 | return -EINVAL; |
302 | } | 303 | } |
303 | 304 | ||
@@ -426,7 +427,7 @@ static int mxsfb_set_par(struct fb_info *fb_info) | |||
426 | ctrl |= CTRL_SET_WORD_LENGTH(3); | 427 | ctrl |= CTRL_SET_WORD_LENGTH(3); |
427 | switch (host->ld_intf_width) { | 428 | switch (host->ld_intf_width) { |
428 | case STMLCDIF_8BIT: | 429 | case STMLCDIF_8BIT: |
429 | dev_dbg(&host->pdev->dev, | 430 | dev_err(&host->pdev->dev, |
430 | "Unsupported LCD bus width mapping\n"); | 431 | "Unsupported LCD bus width mapping\n"); |
431 | return -EINVAL; | 432 | return -EINVAL; |
432 | case STMLCDIF_16BIT: | 433 | case STMLCDIF_16BIT: |
@@ -439,7 +440,7 @@ static int mxsfb_set_par(struct fb_info *fb_info) | |||
439 | writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1); | 440 | writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1); |
440 | break; | 441 | break; |
441 | default: | 442 | default: |
442 | dev_dbg(&host->pdev->dev, "Unhandled color depth of %u\n", | 443 | dev_err(&host->pdev->dev, "Unhandled color depth of %u\n", |
443 | fb_info->var.bits_per_pixel); | 444 | fb_info->var.bits_per_pixel); |
444 | return -EINVAL; | 445 | return -EINVAL; |
445 | } | 446 | } |
@@ -589,7 +590,8 @@ static struct fb_ops mxsfb_ops = { | |||
589 | .fb_imageblit = cfb_imageblit, | 590 | .fb_imageblit = cfb_imageblit, |
590 | }; | 591 | }; |
591 | 592 | ||
592 | static int mxsfb_restore_mode(struct mxsfb_info *host) | 593 | static int mxsfb_restore_mode(struct mxsfb_info *host, |
594 | struct fb_videomode *vmode) | ||
593 | { | 595 | { |
594 | struct fb_info *fb_info = &host->fb_info; | 596 | struct fb_info *fb_info = &host->fb_info; |
595 | unsigned line_count; | 597 | unsigned line_count; |
@@ -597,7 +599,6 @@ static int mxsfb_restore_mode(struct mxsfb_info *host) | |||
597 | unsigned long pa, fbsize; | 599 | unsigned long pa, fbsize; |
598 | int bits_per_pixel, ofs; | 600 | int bits_per_pixel, ofs; |
599 | u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl; | 601 | u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl; |
600 | struct fb_videomode vmode; | ||
601 | 602 | ||
602 | /* Only restore the mode when the controller is running */ | 603 | /* Only restore the mode when the controller is running */ |
603 | ctrl = readl(host->base + LCDC_CTRL); | 604 | ctrl = readl(host->base + LCDC_CTRL); |
@@ -611,8 +612,8 @@ static int mxsfb_restore_mode(struct mxsfb_info *host) | |||
611 | 612 | ||
612 | transfer_count = readl(host->base + host->devdata->transfer_count); | 613 | transfer_count = readl(host->base + host->devdata->transfer_count); |
613 | 614 | ||
614 | vmode.xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count); | 615 | vmode->xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count); |
615 | vmode.yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count); | 616 | vmode->yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count); |
616 | 617 | ||
617 | switch (CTRL_GET_WORD_LENGTH(ctrl)) { | 618 | switch (CTRL_GET_WORD_LENGTH(ctrl)) { |
618 | case 0: | 619 | case 0: |
@@ -628,40 +629,39 @@ static int mxsfb_restore_mode(struct mxsfb_info *host) | |||
628 | 629 | ||
629 | fb_info->var.bits_per_pixel = bits_per_pixel; | 630 | fb_info->var.bits_per_pixel = bits_per_pixel; |
630 | 631 | ||
631 | vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U); | 632 | vmode->pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U); |
632 | vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2); | 633 | vmode->hsync_len = get_hsync_pulse_width(host, vdctrl2); |
633 | vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len; | 634 | vmode->left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode->hsync_len; |
634 | vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len - | 635 | vmode->right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - |
635 | vmode.left_margin - vmode.xres; | 636 | vmode->hsync_len - vmode->left_margin - vmode->xres; |
636 | vmode.vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0); | 637 | vmode->vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0); |
637 | period = readl(host->base + LCDC_VDCTRL1); | 638 | period = readl(host->base + LCDC_VDCTRL1); |
638 | vmode.upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode.vsync_len; | 639 | vmode->upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode->vsync_len; |
639 | vmode.lower_margin = period - vmode.vsync_len - vmode.upper_margin - vmode.yres; | 640 | vmode->lower_margin = period - vmode->vsync_len - |
641 | vmode->upper_margin - vmode->yres; | ||
640 | 642 | ||
641 | vmode.vmode = FB_VMODE_NONINTERLACED; | 643 | vmode->vmode = FB_VMODE_NONINTERLACED; |
642 | 644 | ||
643 | vmode.sync = 0; | 645 | vmode->sync = 0; |
644 | if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH) | 646 | if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH) |
645 | vmode.sync |= FB_SYNC_HOR_HIGH_ACT; | 647 | vmode->sync |= FB_SYNC_HOR_HIGH_ACT; |
646 | if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH) | 648 | if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH) |
647 | vmode.sync |= FB_SYNC_VERT_HIGH_ACT; | 649 | vmode->sync |= FB_SYNC_VERT_HIGH_ACT; |
648 | 650 | ||
649 | pr_debug("Reconstructed video mode:\n"); | 651 | pr_debug("Reconstructed video mode:\n"); |
650 | pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n", | 652 | pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n", |
651 | vmode.xres, vmode.yres, | 653 | vmode->xres, vmode->yres, vmode->hsync_len, vmode->left_margin, |
652 | vmode.hsync_len, vmode.left_margin, vmode.right_margin, | 654 | vmode->right_margin, vmode->vsync_len, vmode->upper_margin, |
653 | vmode.vsync_len, vmode.upper_margin, vmode.lower_margin); | 655 | vmode->lower_margin); |
654 | pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode.pixclock)); | 656 | pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode->pixclock)); |
655 | |||
656 | fb_add_videomode(&vmode, &fb_info->modelist); | ||
657 | 657 | ||
658 | host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl); | 658 | host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl); |
659 | host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4); | 659 | host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4); |
660 | 660 | ||
661 | fb_info->fix.line_length = vmode.xres * (bits_per_pixel >> 3); | 661 | fb_info->fix.line_length = vmode->xres * (bits_per_pixel >> 3); |
662 | 662 | ||
663 | pa = readl(host->base + host->devdata->cur_buf); | 663 | pa = readl(host->base + host->devdata->cur_buf); |
664 | fbsize = fb_info->fix.line_length * vmode.yres; | 664 | fbsize = fb_info->fix.line_length * vmode->yres; |
665 | if (pa < fb_info->fix.smem_start) | 665 | if (pa < fb_info->fix.smem_start) |
666 | return -EINVAL; | 666 | return -EINVAL; |
667 | if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len) | 667 | if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len) |
@@ -681,18 +681,17 @@ static int mxsfb_restore_mode(struct mxsfb_info *host) | |||
681 | return 0; | 681 | return 0; |
682 | } | 682 | } |
683 | 683 | ||
684 | static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host) | 684 | static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host, |
685 | struct fb_videomode *vmode) | ||
685 | { | 686 | { |
686 | struct fb_info *fb_info = &host->fb_info; | 687 | struct fb_info *fb_info = &host->fb_info; |
687 | struct fb_var_screeninfo *var = &fb_info->var; | 688 | struct fb_var_screeninfo *var = &fb_info->var; |
688 | struct device *dev = &host->pdev->dev; | 689 | struct device *dev = &host->pdev->dev; |
689 | struct device_node *np = host->pdev->dev.of_node; | 690 | struct device_node *np = host->pdev->dev.of_node; |
690 | struct device_node *display_np; | 691 | struct device_node *display_np; |
691 | struct device_node *timings_np; | 692 | struct videomode vm; |
692 | struct display_timings *timings; | ||
693 | u32 width; | 693 | u32 width; |
694 | int i; | 694 | int ret; |
695 | int ret = 0; | ||
696 | 695 | ||
697 | display_np = of_parse_phandle(np, "display", 0); | 696 | display_np = of_parse_phandle(np, "display", 0); |
698 | if (!display_np) { | 697 | if (!display_np) { |
@@ -732,54 +731,35 @@ static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host) | |||
732 | goto put_display_node; | 731 | goto put_display_node; |
733 | } | 732 | } |
734 | 733 | ||
735 | timings = of_get_display_timings(display_np); | 734 | ret = of_get_videomode(display_np, &vm, OF_USE_NATIVE_MODE); |
736 | if (!timings) { | 735 | if (ret) { |
737 | dev_err(dev, "failed to get display timings\n"); | 736 | dev_err(dev, "failed to get videomode from DT\n"); |
738 | ret = -ENOENT; | ||
739 | goto put_display_node; | 737 | goto put_display_node; |
740 | } | 738 | } |
741 | 739 | ||
742 | timings_np = of_find_node_by_name(display_np, | 740 | ret = fb_videomode_from_videomode(&vm, vmode); |
743 | "display-timings"); | 741 | if (ret < 0) |
744 | if (!timings_np) { | ||
745 | dev_err(dev, "failed to find display-timings node\n"); | ||
746 | ret = -ENOENT; | ||
747 | goto put_display_node; | 742 | goto put_display_node; |
748 | } | ||
749 | 743 | ||
750 | for (i = 0; i < of_get_child_count(timings_np); i++) { | 744 | if (vm.flags & DISPLAY_FLAGS_DE_HIGH) |
751 | struct videomode vm; | 745 | host->sync |= MXSFB_SYNC_DATA_ENABLE_HIGH_ACT; |
752 | struct fb_videomode fb_vm; | 746 | if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) |
753 | 747 | host->sync |= MXSFB_SYNC_DOTCLK_FALLING_ACT; | |
754 | ret = videomode_from_timings(timings, &vm, i); | ||
755 | if (ret < 0) | ||
756 | goto put_timings_node; | ||
757 | ret = fb_videomode_from_videomode(&vm, &fb_vm); | ||
758 | if (ret < 0) | ||
759 | goto put_timings_node; | ||
760 | |||
761 | if (vm.flags & DISPLAY_FLAGS_DE_HIGH) | ||
762 | host->sync |= MXSFB_SYNC_DATA_ENABLE_HIGH_ACT; | ||
763 | if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) | ||
764 | host->sync |= MXSFB_SYNC_DOTCLK_FALLING_ACT; | ||
765 | fb_add_videomode(&fb_vm, &fb_info->modelist); | ||
766 | } | ||
767 | 748 | ||
768 | put_timings_node: | ||
769 | of_node_put(timings_np); | ||
770 | put_display_node: | 749 | put_display_node: |
771 | of_node_put(display_np); | 750 | of_node_put(display_np); |
772 | return ret; | 751 | return ret; |
773 | } | 752 | } |
774 | 753 | ||
775 | static int mxsfb_init_fbinfo(struct mxsfb_info *host) | 754 | static int mxsfb_init_fbinfo(struct mxsfb_info *host, |
755 | struct fb_videomode *vmode) | ||
776 | { | 756 | { |
757 | int ret; | ||
777 | struct fb_info *fb_info = &host->fb_info; | 758 | struct fb_info *fb_info = &host->fb_info; |
778 | struct fb_var_screeninfo *var = &fb_info->var; | 759 | struct fb_var_screeninfo *var = &fb_info->var; |
779 | dma_addr_t fb_phys; | 760 | dma_addr_t fb_phys; |
780 | void *fb_virt; | 761 | void *fb_virt; |
781 | unsigned fb_size; | 762 | unsigned fb_size; |
782 | int ret; | ||
783 | 763 | ||
784 | fb_info->fbops = &mxsfb_ops; | 764 | fb_info->fbops = &mxsfb_ops; |
785 | fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST; | 765 | fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST; |
@@ -789,7 +769,7 @@ static int mxsfb_init_fbinfo(struct mxsfb_info *host) | |||
789 | fb_info->fix.visual = FB_VISUAL_TRUECOLOR, | 769 | fb_info->fix.visual = FB_VISUAL_TRUECOLOR, |
790 | fb_info->fix.accel = FB_ACCEL_NONE; | 770 | fb_info->fix.accel = FB_ACCEL_NONE; |
791 | 771 | ||
792 | ret = mxsfb_init_fbinfo_dt(host); | 772 | ret = mxsfb_init_fbinfo_dt(host, vmode); |
793 | if (ret) | 773 | if (ret) |
794 | return ret; | 774 | return ret; |
795 | 775 | ||
@@ -810,7 +790,7 @@ static int mxsfb_init_fbinfo(struct mxsfb_info *host) | |||
810 | fb_info->screen_base = fb_virt; | 790 | fb_info->screen_base = fb_virt; |
811 | fb_info->screen_size = fb_info->fix.smem_len = fb_size; | 791 | fb_info->screen_size = fb_info->fix.smem_len = fb_size; |
812 | 792 | ||
813 | if (mxsfb_restore_mode(host)) | 793 | if (mxsfb_restore_mode(host, vmode)) |
814 | memset(fb_virt, 0, fb_size); | 794 | memset(fb_virt, 0, fb_size); |
815 | 795 | ||
816 | return 0; | 796 | return 0; |
@@ -850,7 +830,7 @@ static int mxsfb_probe(struct platform_device *pdev) | |||
850 | struct resource *res; | 830 | struct resource *res; |
851 | struct mxsfb_info *host; | 831 | struct mxsfb_info *host; |
852 | struct fb_info *fb_info; | 832 | struct fb_info *fb_info; |
853 | struct fb_modelist *modelist; | 833 | struct fb_videomode *mode; |
854 | int ret; | 834 | int ret; |
855 | 835 | ||
856 | if (of_id) | 836 | if (of_id) |
@@ -862,6 +842,11 @@ static int mxsfb_probe(struct platform_device *pdev) | |||
862 | return -ENOMEM; | 842 | return -ENOMEM; |
863 | } | 843 | } |
864 | 844 | ||
845 | mode = devm_kzalloc(&pdev->dev, sizeof(struct fb_videomode), | ||
846 | GFP_KERNEL); | ||
847 | if (mode == NULL) | ||
848 | return -ENOMEM; | ||
849 | |||
865 | host = to_imxfb_host(fb_info); | 850 | host = to_imxfb_host(fb_info); |
866 | 851 | ||
867 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 852 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
@@ -893,15 +878,11 @@ static int mxsfb_probe(struct platform_device *pdev) | |||
893 | goto fb_release; | 878 | goto fb_release; |
894 | } | 879 | } |
895 | 880 | ||
896 | INIT_LIST_HEAD(&fb_info->modelist); | 881 | ret = mxsfb_init_fbinfo(host, mode); |
897 | |||
898 | ret = mxsfb_init_fbinfo(host); | ||
899 | if (ret != 0) | 882 | if (ret != 0) |
900 | goto fb_release; | 883 | goto fb_release; |
901 | 884 | ||
902 | modelist = list_first_entry(&fb_info->modelist, | 885 | fb_videomode_to_var(&fb_info->var, mode); |
903 | struct fb_modelist, list); | ||
904 | fb_videomode_to_var(&fb_info->var, &modelist->mode); | ||
905 | 886 | ||
906 | /* init the color fields */ | 887 | /* init the color fields */ |
907 | mxsfb_check_var(&fb_info->var, fb_info); | 888 | mxsfb_check_var(&fb_info->var, fb_info); |
@@ -927,7 +908,6 @@ static int mxsfb_probe(struct platform_device *pdev) | |||
927 | fb_destroy: | 908 | fb_destroy: |
928 | if (host->enabled) | 909 | if (host->enabled) |
929 | clk_disable_unprepare(host->clk); | 910 | clk_disable_unprepare(host->clk); |
930 | fb_destroy_modelist(&fb_info->modelist); | ||
931 | fb_release: | 911 | fb_release: |
932 | framebuffer_release(fb_info); | 912 | framebuffer_release(fb_info); |
933 | 913 | ||
diff --git a/drivers/video/nvidia/nvidia.c b/drivers/video/nvidia/nvidia.c index ff228713425e..def041204676 100644 --- a/drivers/video/nvidia/nvidia.c +++ b/drivers/video/nvidia/nvidia.c | |||
@@ -1461,7 +1461,6 @@ static void nvidiafb_remove(struct pci_dev *pd) | |||
1461 | pci_release_regions(pd); | 1461 | pci_release_regions(pd); |
1462 | kfree(info->pixmap.addr); | 1462 | kfree(info->pixmap.addr); |
1463 | framebuffer_release(info); | 1463 | framebuffer_release(info); |
1464 | pci_set_drvdata(pd, NULL); | ||
1465 | NVTRACE_LEAVE(); | 1464 | NVTRACE_LEAVE(); |
1466 | } | 1465 | } |
1467 | 1466 | ||
diff --git a/drivers/video/ocfb.c b/drivers/video/ocfb.c new file mode 100644 index 000000000000..7f9dc9bec309 --- /dev/null +++ b/drivers/video/ocfb.c | |||
@@ -0,0 +1,440 @@ | |||
1 | /* | ||
2 | * OpenCores VGA/LCD 2.0 core frame buffer driver | ||
3 | * | ||
4 | * Copyright (C) 2013 Stefan Kristiansson, stefan.kristiansson@saunalahti.fi | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public License | ||
7 | * version 2. This program is licensed "as is" without any warranty of any | ||
8 | * kind, whether express or implied. | ||
9 | */ | ||
10 | |||
11 | #include <linux/delay.h> | ||
12 | #include <linux/dma-mapping.h> | ||
13 | #include <linux/errno.h> | ||
14 | #include <linux/fb.h> | ||
15 | #include <linux/init.h> | ||
16 | #include <linux/io.h> | ||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/mm.h> | ||
19 | #include <linux/module.h> | ||
20 | #include <linux/of.h> | ||
21 | #include <linux/platform_device.h> | ||
22 | #include <linux/string.h> | ||
23 | #include <linux/slab.h> | ||
24 | |||
25 | /* OCFB register defines */ | ||
26 | #define OCFB_CTRL 0x000 | ||
27 | #define OCFB_STAT 0x004 | ||
28 | #define OCFB_HTIM 0x008 | ||
29 | #define OCFB_VTIM 0x00c | ||
30 | #define OCFB_HVLEN 0x010 | ||
31 | #define OCFB_VBARA 0x014 | ||
32 | #define OCFB_PALETTE 0x800 | ||
33 | |||
34 | #define OCFB_CTRL_VEN 0x00000001 /* Video Enable */ | ||
35 | #define OCFB_CTRL_HIE 0x00000002 /* HSync Interrupt Enable */ | ||
36 | #define OCFB_CTRL_PC 0x00000800 /* 8-bit Pseudo Color Enable*/ | ||
37 | #define OCFB_CTRL_CD8 0x00000000 /* Color Depth 8 */ | ||
38 | #define OCFB_CTRL_CD16 0x00000200 /* Color Depth 16 */ | ||
39 | #define OCFB_CTRL_CD24 0x00000400 /* Color Depth 24 */ | ||
40 | #define OCFB_CTRL_CD32 0x00000600 /* Color Depth 32 */ | ||
41 | #define OCFB_CTRL_VBL1 0x00000000 /* Burst Length 1 */ | ||
42 | #define OCFB_CTRL_VBL2 0x00000080 /* Burst Length 2 */ | ||
43 | #define OCFB_CTRL_VBL4 0x00000100 /* Burst Length 4 */ | ||
44 | #define OCFB_CTRL_VBL8 0x00000180 /* Burst Length 8 */ | ||
45 | |||
46 | #define PALETTE_SIZE 256 | ||
47 | |||
48 | #define OCFB_NAME "OC VGA/LCD" | ||
49 | |||
50 | static char *mode_option; | ||
51 | |||
52 | static const struct fb_videomode default_mode = { | ||
53 | /* 640x480 @ 60 Hz, 31.5 kHz hsync */ | ||
54 | NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2, | ||
55 | 0, FB_VMODE_NONINTERLACED | ||
56 | }; | ||
57 | |||
58 | struct ocfb_dev { | ||
59 | struct fb_info info; | ||
60 | void __iomem *regs; | ||
61 | /* flag indicating whether the regs are little endian accessed */ | ||
62 | int little_endian; | ||
63 | /* Physical and virtual addresses of framebuffer */ | ||
64 | phys_addr_t fb_phys; | ||
65 | void __iomem *fb_virt; | ||
66 | u32 pseudo_palette[PALETTE_SIZE]; | ||
67 | }; | ||
68 | |||
69 | #ifndef MODULE | ||
70 | static int __init ocfb_setup(char *options) | ||
71 | { | ||
72 | char *curr_opt; | ||
73 | |||
74 | if (!options || !*options) | ||
75 | return 0; | ||
76 | |||
77 | while ((curr_opt = strsep(&options, ",")) != NULL) { | ||
78 | if (!*curr_opt) | ||
79 | continue; | ||
80 | mode_option = curr_opt; | ||
81 | } | ||
82 | |||
83 | return 0; | ||
84 | } | ||
85 | #endif | ||
86 | |||
87 | static inline u32 ocfb_readreg(struct ocfb_dev *fbdev, loff_t offset) | ||
88 | { | ||
89 | if (fbdev->little_endian) | ||
90 | return ioread32(fbdev->regs + offset); | ||
91 | else | ||
92 | return ioread32be(fbdev->regs + offset); | ||
93 | } | ||
94 | |||
95 | static void ocfb_writereg(struct ocfb_dev *fbdev, loff_t offset, u32 data) | ||
96 | { | ||
97 | if (fbdev->little_endian) | ||
98 | iowrite32(data, fbdev->regs + offset); | ||
99 | else | ||
100 | iowrite32be(data, fbdev->regs + offset); | ||
101 | } | ||
102 | |||
103 | static int ocfb_setupfb(struct ocfb_dev *fbdev) | ||
104 | { | ||
105 | unsigned long bpp_config; | ||
106 | struct fb_var_screeninfo *var = &fbdev->info.var; | ||
107 | struct device *dev = fbdev->info.device; | ||
108 | u32 hlen; | ||
109 | u32 vlen; | ||
110 | |||
111 | /* Disable display */ | ||
112 | ocfb_writereg(fbdev, OCFB_CTRL, 0); | ||
113 | |||
114 | /* Register framebuffer address */ | ||
115 | fbdev->little_endian = 0; | ||
116 | ocfb_writereg(fbdev, OCFB_VBARA, fbdev->fb_phys); | ||
117 | |||
118 | /* Detect endianess */ | ||
119 | if (ocfb_readreg(fbdev, OCFB_VBARA) != fbdev->fb_phys) { | ||
120 | fbdev->little_endian = 1; | ||
121 | ocfb_writereg(fbdev, OCFB_VBARA, fbdev->fb_phys); | ||
122 | } | ||
123 | |||
124 | /* Horizontal timings */ | ||
125 | ocfb_writereg(fbdev, OCFB_HTIM, (var->hsync_len - 1) << 24 | | ||
126 | (var->right_margin - 1) << 16 | (var->xres - 1)); | ||
127 | |||
128 | /* Vertical timings */ | ||
129 | ocfb_writereg(fbdev, OCFB_VTIM, (var->vsync_len - 1) << 24 | | ||
130 | (var->lower_margin - 1) << 16 | (var->yres - 1)); | ||
131 | |||
132 | /* Total length of frame */ | ||
133 | hlen = var->left_margin + var->right_margin + var->hsync_len + | ||
134 | var->xres; | ||
135 | |||
136 | vlen = var->upper_margin + var->lower_margin + var->vsync_len + | ||
137 | var->yres; | ||
138 | |||
139 | ocfb_writereg(fbdev, OCFB_HVLEN, (hlen - 1) << 16 | (vlen - 1)); | ||
140 | |||
141 | bpp_config = OCFB_CTRL_CD8; | ||
142 | switch (var->bits_per_pixel) { | ||
143 | case 8: | ||
144 | if (!var->grayscale) | ||
145 | bpp_config |= OCFB_CTRL_PC; /* enable palette */ | ||
146 | break; | ||
147 | |||
148 | case 16: | ||
149 | bpp_config |= OCFB_CTRL_CD16; | ||
150 | break; | ||
151 | |||
152 | case 24: | ||
153 | bpp_config |= OCFB_CTRL_CD24; | ||
154 | break; | ||
155 | |||
156 | case 32: | ||
157 | bpp_config |= OCFB_CTRL_CD32; | ||
158 | break; | ||
159 | |||
160 | default: | ||
161 | dev_err(dev, "no bpp specified\n"); | ||
162 | break; | ||
163 | } | ||
164 | |||
165 | /* maximum (8) VBL (video memory burst length) */ | ||
166 | bpp_config |= OCFB_CTRL_VBL8; | ||
167 | |||
168 | /* Enable output */ | ||
169 | ocfb_writereg(fbdev, OCFB_CTRL, (OCFB_CTRL_VEN | bpp_config)); | ||
170 | |||
171 | return 0; | ||
172 | } | ||
173 | |||
174 | static int ocfb_setcolreg(unsigned regno, unsigned red, unsigned green, | ||
175 | unsigned blue, unsigned transp, | ||
176 | struct fb_info *info) | ||
177 | { | ||
178 | struct ocfb_dev *fbdev = (struct ocfb_dev *)info->par; | ||
179 | u32 color; | ||
180 | |||
181 | if (regno >= info->cmap.len) { | ||
182 | dev_err(info->device, "regno >= cmap.len\n"); | ||
183 | return 1; | ||
184 | } | ||
185 | |||
186 | if (info->var.grayscale) { | ||
187 | /* grayscale = 0.30*R + 0.59*G + 0.11*B */ | ||
188 | red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; | ||
189 | } | ||
190 | |||
191 | red >>= (16 - info->var.red.length); | ||
192 | green >>= (16 - info->var.green.length); | ||
193 | blue >>= (16 - info->var.blue.length); | ||
194 | transp >>= (16 - info->var.transp.length); | ||
195 | |||
196 | if (info->var.bits_per_pixel == 8 && !info->var.grayscale) { | ||
197 | regno <<= 2; | ||
198 | color = (red << 16) | (green << 8) | blue; | ||
199 | ocfb_writereg(fbdev, OCFB_PALETTE + regno, color); | ||
200 | } else { | ||
201 | ((u32 *)(info->pseudo_palette))[regno] = | ||
202 | (red << info->var.red.offset) | | ||
203 | (green << info->var.green.offset) | | ||
204 | (blue << info->var.blue.offset) | | ||
205 | (transp << info->var.transp.offset); | ||
206 | } | ||
207 | |||
208 | return 0; | ||
209 | } | ||
210 | |||
211 | static int ocfb_init_fix(struct ocfb_dev *fbdev) | ||
212 | { | ||
213 | struct fb_var_screeninfo *var = &fbdev->info.var; | ||
214 | struct fb_fix_screeninfo *fix = &fbdev->info.fix; | ||
215 | |||
216 | strcpy(fix->id, OCFB_NAME); | ||
217 | |||
218 | fix->line_length = var->xres * var->bits_per_pixel/8; | ||
219 | fix->smem_len = fix->line_length * var->yres; | ||
220 | fix->type = FB_TYPE_PACKED_PIXELS; | ||
221 | |||
222 | if (var->bits_per_pixel == 8 && !var->grayscale) | ||
223 | fix->visual = FB_VISUAL_PSEUDOCOLOR; | ||
224 | else | ||
225 | fix->visual = FB_VISUAL_TRUECOLOR; | ||
226 | |||
227 | return 0; | ||
228 | } | ||
229 | |||
230 | static int ocfb_init_var(struct ocfb_dev *fbdev) | ||
231 | { | ||
232 | struct fb_var_screeninfo *var = &fbdev->info.var; | ||
233 | |||
234 | var->accel_flags = FB_ACCEL_NONE; | ||
235 | var->activate = FB_ACTIVATE_NOW; | ||
236 | var->xres_virtual = var->xres; | ||
237 | var->yres_virtual = var->yres; | ||
238 | |||
239 | switch (var->bits_per_pixel) { | ||
240 | case 8: | ||
241 | var->transp.offset = 0; | ||
242 | var->transp.length = 0; | ||
243 | var->red.offset = 0; | ||
244 | var->red.length = 8; | ||
245 | var->green.offset = 0; | ||
246 | var->green.length = 8; | ||
247 | var->blue.offset = 0; | ||
248 | var->blue.length = 8; | ||
249 | break; | ||
250 | |||
251 | case 16: | ||
252 | var->transp.offset = 0; | ||
253 | var->transp.length = 0; | ||
254 | var->red.offset = 11; | ||
255 | var->red.length = 5; | ||
256 | var->green.offset = 5; | ||
257 | var->green.length = 6; | ||
258 | var->blue.offset = 0; | ||
259 | var->blue.length = 5; | ||
260 | break; | ||
261 | |||
262 | case 24: | ||
263 | var->transp.offset = 0; | ||
264 | var->transp.length = 0; | ||
265 | var->red.offset = 16; | ||
266 | var->red.length = 8; | ||
267 | var->green.offset = 8; | ||
268 | var->green.length = 8; | ||
269 | var->blue.offset = 0; | ||
270 | var->blue.length = 8; | ||
271 | break; | ||
272 | |||
273 | case 32: | ||
274 | var->transp.offset = 24; | ||
275 | var->transp.length = 8; | ||
276 | var->red.offset = 16; | ||
277 | var->red.length = 8; | ||
278 | var->green.offset = 8; | ||
279 | var->green.length = 8; | ||
280 | var->blue.offset = 0; | ||
281 | var->blue.length = 8; | ||
282 | break; | ||
283 | } | ||
284 | |||
285 | return 0; | ||
286 | } | ||
287 | |||
288 | static struct fb_ops ocfb_ops = { | ||
289 | .owner = THIS_MODULE, | ||
290 | .fb_setcolreg = ocfb_setcolreg, | ||
291 | .fb_fillrect = cfb_fillrect, | ||
292 | .fb_copyarea = cfb_copyarea, | ||
293 | .fb_imageblit = cfb_imageblit, | ||
294 | }; | ||
295 | |||
296 | static int ocfb_probe(struct platform_device *pdev) | ||
297 | { | ||
298 | int ret = 0; | ||
299 | struct ocfb_dev *fbdev; | ||
300 | struct resource *res; | ||
301 | int fbsize; | ||
302 | |||
303 | fbdev = devm_kzalloc(&pdev->dev, sizeof(*fbdev), GFP_KERNEL); | ||
304 | if (!fbdev) | ||
305 | return -ENOMEM; | ||
306 | |||
307 | platform_set_drvdata(pdev, fbdev); | ||
308 | |||
309 | fbdev->info.fbops = &ocfb_ops; | ||
310 | fbdev->info.device = &pdev->dev; | ||
311 | fbdev->info.par = fbdev; | ||
312 | |||
313 | /* Video mode setup */ | ||
314 | if (!fb_find_mode(&fbdev->info.var, &fbdev->info, mode_option, | ||
315 | NULL, 0, &default_mode, 16)) { | ||
316 | dev_err(&pdev->dev, "No valid video modes found\n"); | ||
317 | return -EINVAL; | ||
318 | } | ||
319 | ocfb_init_var(fbdev); | ||
320 | ocfb_init_fix(fbdev); | ||
321 | |||
322 | /* Request I/O resource */ | ||
323 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
324 | if (!res) { | ||
325 | dev_err(&pdev->dev, "I/O resource request failed\n"); | ||
326 | return -ENXIO; | ||
327 | } | ||
328 | res->flags &= ~IORESOURCE_CACHEABLE; | ||
329 | fbdev->regs = devm_ioremap_resource(&pdev->dev, res); | ||
330 | if (IS_ERR(fbdev->regs)) | ||
331 | return PTR_ERR(fbdev->regs); | ||
332 | |||
333 | /* Allocate framebuffer memory */ | ||
334 | fbsize = fbdev->info.fix.smem_len; | ||
335 | fbdev->fb_virt = dma_alloc_coherent(&pdev->dev, PAGE_ALIGN(fbsize), | ||
336 | &fbdev->fb_phys, GFP_KERNEL); | ||
337 | if (!fbdev->fb_virt) { | ||
338 | dev_err(&pdev->dev, | ||
339 | "Frame buffer memory allocation failed\n"); | ||
340 | return -ENOMEM; | ||
341 | } | ||
342 | fbdev->info.fix.smem_start = fbdev->fb_phys; | ||
343 | fbdev->info.screen_base = fbdev->fb_virt; | ||
344 | fbdev->info.pseudo_palette = fbdev->pseudo_palette; | ||
345 | |||
346 | /* Clear framebuffer */ | ||
347 | memset_io(fbdev->fb_virt, 0, fbsize); | ||
348 | |||
349 | /* Setup and enable the framebuffer */ | ||
350 | ocfb_setupfb(fbdev); | ||
351 | |||
352 | if (fbdev->little_endian) | ||
353 | fbdev->info.flags |= FBINFO_FOREIGN_ENDIAN; | ||
354 | |||
355 | /* Allocate color map */ | ||
356 | ret = fb_alloc_cmap(&fbdev->info.cmap, PALETTE_SIZE, 0); | ||
357 | if (ret) { | ||
358 | dev_err(&pdev->dev, "Color map allocation failed\n"); | ||
359 | goto err_dma_free; | ||
360 | } | ||
361 | |||
362 | /* Register framebuffer */ | ||
363 | ret = register_framebuffer(&fbdev->info); | ||
364 | if (ret) { | ||
365 | dev_err(&pdev->dev, "Framebuffer registration failed\n"); | ||
366 | goto err_dealloc_cmap; | ||
367 | } | ||
368 | |||
369 | return 0; | ||
370 | |||
371 | err_dealloc_cmap: | ||
372 | fb_dealloc_cmap(&fbdev->info.cmap); | ||
373 | |||
374 | err_dma_free: | ||
375 | dma_free_coherent(&pdev->dev, PAGE_ALIGN(fbsize), fbdev->fb_virt, | ||
376 | fbdev->fb_phys); | ||
377 | |||
378 | return ret; | ||
379 | } | ||
380 | |||
381 | static int ocfb_remove(struct platform_device *pdev) | ||
382 | { | ||
383 | struct ocfb_dev *fbdev = platform_get_drvdata(pdev); | ||
384 | |||
385 | unregister_framebuffer(&fbdev->info); | ||
386 | fb_dealloc_cmap(&fbdev->info.cmap); | ||
387 | dma_free_coherent(&pdev->dev, PAGE_ALIGN(fbdev->info.fix.smem_len), | ||
388 | fbdev->fb_virt, fbdev->fb_phys); | ||
389 | |||
390 | /* Disable display */ | ||
391 | ocfb_writereg(fbdev, OCFB_CTRL, 0); | ||
392 | |||
393 | platform_set_drvdata(pdev, NULL); | ||
394 | |||
395 | return 0; | ||
396 | } | ||
397 | |||
398 | static struct of_device_id ocfb_match[] = { | ||
399 | { .compatible = "opencores,ocfb", }, | ||
400 | {}, | ||
401 | }; | ||
402 | MODULE_DEVICE_TABLE(of, ocfb_match); | ||
403 | |||
404 | static struct platform_driver ocfb_driver = { | ||
405 | .probe = ocfb_probe, | ||
406 | .remove = ocfb_remove, | ||
407 | .driver = { | ||
408 | .name = "ocfb_fb", | ||
409 | .of_match_table = ocfb_match, | ||
410 | } | ||
411 | }; | ||
412 | |||
413 | /* | ||
414 | * Init and exit routines | ||
415 | */ | ||
416 | static int __init ocfb_init(void) | ||
417 | { | ||
418 | #ifndef MODULE | ||
419 | char *option = NULL; | ||
420 | |||
421 | if (fb_get_options("ocfb", &option)) | ||
422 | return -ENODEV; | ||
423 | ocfb_setup(option); | ||
424 | #endif | ||
425 | return platform_driver_register(&ocfb_driver); | ||
426 | } | ||
427 | |||
428 | static void __exit ocfb_exit(void) | ||
429 | { | ||
430 | platform_driver_unregister(&ocfb_driver); | ||
431 | } | ||
432 | |||
433 | module_init(ocfb_init); | ||
434 | module_exit(ocfb_exit); | ||
435 | |||
436 | MODULE_AUTHOR("Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>"); | ||
437 | MODULE_DESCRIPTION("OpenCores VGA/LCD 2.0 frame buffer driver"); | ||
438 | MODULE_LICENSE("GPL v2"); | ||
439 | module_param(mode_option, charp, 0); | ||
440 | MODULE_PARM_DESC(mode_option, "Video mode ('<xres>x<yres>[-<bpp>][@refresh]')"); | ||
diff --git a/drivers/video/omap2/displays-new/panel-sony-acx565akm.c b/drivers/video/omap2/displays-new/panel-sony-acx565akm.c index d94f35dbd536..8e97d06921ff 100644 --- a/drivers/video/omap2/displays-new/panel-sony-acx565akm.c +++ b/drivers/video/omap2/displays-new/panel-sony-acx565akm.c | |||
@@ -346,28 +346,22 @@ static int acx565akm_get_actual_brightness(struct panel_drv_data *ddata) | |||
346 | static int acx565akm_bl_update_status(struct backlight_device *dev) | 346 | static int acx565akm_bl_update_status(struct backlight_device *dev) |
347 | { | 347 | { |
348 | struct panel_drv_data *ddata = dev_get_drvdata(&dev->dev); | 348 | struct panel_drv_data *ddata = dev_get_drvdata(&dev->dev); |
349 | int r; | ||
350 | int level; | 349 | int level; |
351 | 350 | ||
352 | dev_dbg(&ddata->spi->dev, "%s\n", __func__); | 351 | dev_dbg(&ddata->spi->dev, "%s\n", __func__); |
353 | 352 | ||
354 | mutex_lock(&ddata->mutex); | ||
355 | |||
356 | if (dev->props.fb_blank == FB_BLANK_UNBLANK && | 353 | if (dev->props.fb_blank == FB_BLANK_UNBLANK && |
357 | dev->props.power == FB_BLANK_UNBLANK) | 354 | dev->props.power == FB_BLANK_UNBLANK) |
358 | level = dev->props.brightness; | 355 | level = dev->props.brightness; |
359 | else | 356 | else |
360 | level = 0; | 357 | level = 0; |
361 | 358 | ||
362 | r = 0; | ||
363 | if (ddata->has_bc) | 359 | if (ddata->has_bc) |
364 | acx565akm_set_brightness(ddata, level); | 360 | acx565akm_set_brightness(ddata, level); |
365 | else | 361 | else |
366 | r = -ENODEV; | 362 | return -ENODEV; |
367 | |||
368 | mutex_unlock(&ddata->mutex); | ||
369 | 363 | ||
370 | return r; | 364 | return 0; |
371 | } | 365 | } |
372 | 366 | ||
373 | static int acx565akm_bl_get_intensity(struct backlight_device *dev) | 367 | static int acx565akm_bl_get_intensity(struct backlight_device *dev) |
@@ -390,9 +384,33 @@ static int acx565akm_bl_get_intensity(struct backlight_device *dev) | |||
390 | return 0; | 384 | return 0; |
391 | } | 385 | } |
392 | 386 | ||
387 | static int acx565akm_bl_update_status_locked(struct backlight_device *dev) | ||
388 | { | ||
389 | struct panel_drv_data *ddata = dev_get_drvdata(&dev->dev); | ||
390 | int r; | ||
391 | |||
392 | mutex_lock(&ddata->mutex); | ||
393 | r = acx565akm_bl_update_status(dev); | ||
394 | mutex_unlock(&ddata->mutex); | ||
395 | |||
396 | return r; | ||
397 | } | ||
398 | |||
399 | static int acx565akm_bl_get_intensity_locked(struct backlight_device *dev) | ||
400 | { | ||
401 | struct panel_drv_data *ddata = dev_get_drvdata(&dev->dev); | ||
402 | int r; | ||
403 | |||
404 | mutex_lock(&ddata->mutex); | ||
405 | r = acx565akm_bl_get_intensity(dev); | ||
406 | mutex_unlock(&ddata->mutex); | ||
407 | |||
408 | return r; | ||
409 | } | ||
410 | |||
393 | static const struct backlight_ops acx565akm_bl_ops = { | 411 | static const struct backlight_ops acx565akm_bl_ops = { |
394 | .get_brightness = acx565akm_bl_get_intensity, | 412 | .get_brightness = acx565akm_bl_get_intensity_locked, |
395 | .update_status = acx565akm_bl_update_status, | 413 | .update_status = acx565akm_bl_update_status_locked, |
396 | }; | 414 | }; |
397 | 415 | ||
398 | /*--------------------Auto Brightness control via Sysfs---------------------*/ | 416 | /*--------------------Auto Brightness control via Sysfs---------------------*/ |
@@ -526,8 +544,6 @@ static int acx565akm_panel_power_on(struct omap_dss_device *dssdev) | |||
526 | struct omap_dss_device *in = ddata->in; | 544 | struct omap_dss_device *in = ddata->in; |
527 | int r; | 545 | int r; |
528 | 546 | ||
529 | mutex_lock(&ddata->mutex); | ||
530 | |||
531 | dev_dbg(&ddata->spi->dev, "%s\n", __func__); | 547 | dev_dbg(&ddata->spi->dev, "%s\n", __func__); |
532 | 548 | ||
533 | in->ops.sdi->set_timings(in, &ddata->videomode); | 549 | in->ops.sdi->set_timings(in, &ddata->videomode); |
@@ -568,8 +584,6 @@ static int acx565akm_panel_power_on(struct omap_dss_device *dssdev) | |||
568 | set_display_state(ddata, 1); | 584 | set_display_state(ddata, 1); |
569 | set_cabc_mode(ddata, ddata->cabc_mode); | 585 | set_cabc_mode(ddata, ddata->cabc_mode); |
570 | 586 | ||
571 | mutex_unlock(&ddata->mutex); | ||
572 | |||
573 | return acx565akm_bl_update_status(ddata->bl_dev); | 587 | return acx565akm_bl_update_status(ddata->bl_dev); |
574 | } | 588 | } |
575 | 589 | ||
@@ -616,7 +630,9 @@ static int acx565akm_enable(struct omap_dss_device *dssdev) | |||
616 | if (omapdss_device_is_enabled(dssdev)) | 630 | if (omapdss_device_is_enabled(dssdev)) |
617 | return 0; | 631 | return 0; |
618 | 632 | ||
633 | mutex_lock(&ddata->mutex); | ||
619 | r = acx565akm_panel_power_on(dssdev); | 634 | r = acx565akm_panel_power_on(dssdev); |
635 | mutex_unlock(&ddata->mutex); | ||
620 | if (r) | 636 | if (r) |
621 | return r; | 637 | return r; |
622 | 638 | ||
diff --git a/drivers/video/omap2/dss/apply.c b/drivers/video/omap2/dss/apply.c index 60758dbefd79..0a0b084ce65d 100644 --- a/drivers/video/omap2/dss/apply.c +++ b/drivers/video/omap2/dss/apply.c | |||
@@ -149,6 +149,9 @@ static void apply_init_priv(void) | |||
149 | 149 | ||
150 | op = &dss_data.ovl_priv_data_array[i]; | 150 | op = &dss_data.ovl_priv_data_array[i]; |
151 | 151 | ||
152 | op->info.color_mode = OMAP_DSS_COLOR_RGB16; | ||
153 | op->info.rotation_type = OMAP_DSS_ROT_DMA; | ||
154 | |||
152 | op->info.global_alpha = 255; | 155 | op->info.global_alpha = 255; |
153 | 156 | ||
154 | switch (i) { | 157 | switch (i) { |
@@ -629,7 +632,7 @@ static void dss_ovl_write_regs(struct omap_overlay *ovl) | |||
629 | struct mgr_priv_data *mp; | 632 | struct mgr_priv_data *mp; |
630 | int r; | 633 | int r; |
631 | 634 | ||
632 | DSSDBG("writing ovl %d regs", ovl->id); | 635 | DSSDBG("writing ovl %d regs\n", ovl->id); |
633 | 636 | ||
634 | if (!op->enabled || !op->info_dirty) | 637 | if (!op->enabled || !op->info_dirty) |
635 | return; | 638 | return; |
@@ -664,7 +667,7 @@ static void dss_ovl_write_regs_extra(struct omap_overlay *ovl) | |||
664 | struct ovl_priv_data *op = get_ovl_priv(ovl); | 667 | struct ovl_priv_data *op = get_ovl_priv(ovl); |
665 | struct mgr_priv_data *mp; | 668 | struct mgr_priv_data *mp; |
666 | 669 | ||
667 | DSSDBG("writing ovl %d regs extra", ovl->id); | 670 | DSSDBG("writing ovl %d regs extra\n", ovl->id); |
668 | 671 | ||
669 | if (!op->extra_info_dirty) | 672 | if (!op->extra_info_dirty) |
670 | return; | 673 | return; |
@@ -687,7 +690,7 @@ static void dss_mgr_write_regs(struct omap_overlay_manager *mgr) | |||
687 | struct mgr_priv_data *mp = get_mgr_priv(mgr); | 690 | struct mgr_priv_data *mp = get_mgr_priv(mgr); |
688 | struct omap_overlay *ovl; | 691 | struct omap_overlay *ovl; |
689 | 692 | ||
690 | DSSDBG("writing mgr %d regs", mgr->id); | 693 | DSSDBG("writing mgr %d regs\n", mgr->id); |
691 | 694 | ||
692 | if (!mp->enabled) | 695 | if (!mp->enabled) |
693 | return; | 696 | return; |
@@ -713,7 +716,7 @@ static void dss_mgr_write_regs_extra(struct omap_overlay_manager *mgr) | |||
713 | { | 716 | { |
714 | struct mgr_priv_data *mp = get_mgr_priv(mgr); | 717 | struct mgr_priv_data *mp = get_mgr_priv(mgr); |
715 | 718 | ||
716 | DSSDBG("writing mgr %d regs extra", mgr->id); | 719 | DSSDBG("writing mgr %d regs extra\n", mgr->id); |
717 | 720 | ||
718 | if (!mp->extra_info_dirty) | 721 | if (!mp->extra_info_dirty) |
719 | return; | 722 | return; |
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 4ec59ca72e5d..bbeb8dd7f108 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c | |||
@@ -90,6 +90,8 @@ struct dispc_features { | |||
90 | 90 | ||
91 | /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */ | 91 | /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */ |
92 | bool mstandby_workaround:1; | 92 | bool mstandby_workaround:1; |
93 | |||
94 | bool set_max_preload:1; | ||
93 | }; | 95 | }; |
94 | 96 | ||
95 | #define DISPC_MAX_NR_FIFOS 5 | 97 | #define DISPC_MAX_NR_FIFOS 5 |
@@ -1200,7 +1202,17 @@ void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high) | |||
1200 | dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane), | 1202 | dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane), |
1201 | FLD_VAL(high, hi_start, hi_end) | | 1203 | FLD_VAL(high, hi_start, hi_end) | |
1202 | FLD_VAL(low, lo_start, lo_end)); | 1204 | FLD_VAL(low, lo_start, lo_end)); |
1205 | |||
1206 | /* | ||
1207 | * configure the preload to the pipeline's high threhold, if HT it's too | ||
1208 | * large for the preload field, set the threshold to the maximum value | ||
1209 | * that can be held by the preload register | ||
1210 | */ | ||
1211 | if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && | ||
1212 | plane != OMAP_DSS_WB) | ||
1213 | dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu)); | ||
1203 | } | 1214 | } |
1215 | EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold); | ||
1204 | 1216 | ||
1205 | void dispc_enable_fifomerge(bool enable) | 1217 | void dispc_enable_fifomerge(bool enable) |
1206 | { | 1218 | { |
@@ -1259,6 +1271,7 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, | |||
1259 | *fifo_high = total_fifo_size - buf_unit; | 1271 | *fifo_high = total_fifo_size - buf_unit; |
1260 | } | 1272 | } |
1261 | } | 1273 | } |
1274 | EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds); | ||
1262 | 1275 | ||
1263 | static void dispc_ovl_set_fir(enum omap_plane plane, | 1276 | static void dispc_ovl_set_fir(enum omap_plane plane, |
1264 | int hinc, int vinc, | 1277 | int hinc, int vinc, |
@@ -1988,7 +2001,8 @@ static void calc_tiler_rotation_offset(u16 screen_width, u16 width, | |||
1988 | */ | 2001 | */ |
1989 | static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, | 2002 | static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, |
1990 | const struct omap_video_timings *t, u16 pos_x, | 2003 | const struct omap_video_timings *t, u16 pos_x, |
1991 | u16 width, u16 height, u16 out_width, u16 out_height) | 2004 | u16 width, u16 height, u16 out_width, u16 out_height, |
2005 | bool five_taps) | ||
1992 | { | 2006 | { |
1993 | const int ds = DIV_ROUND_UP(height, out_height); | 2007 | const int ds = DIV_ROUND_UP(height, out_height); |
1994 | unsigned long nonactive; | 2008 | unsigned long nonactive; |
@@ -2008,6 +2022,10 @@ static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, | |||
2008 | if (blank <= limits[i]) | 2022 | if (blank <= limits[i]) |
2009 | return -EINVAL; | 2023 | return -EINVAL; |
2010 | 2024 | ||
2025 | /* FIXME add checks for 3-tap filter once the limitations are known */ | ||
2026 | if (!five_taps) | ||
2027 | return 0; | ||
2028 | |||
2011 | /* | 2029 | /* |
2012 | * Pixel data should be prepared before visible display point starts. | 2030 | * Pixel data should be prepared before visible display point starts. |
2013 | * So, atleast DS-2 lines must have already been fetched by DISPC | 2031 | * So, atleast DS-2 lines must have already been fetched by DISPC |
@@ -2183,22 +2201,30 @@ static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk, | |||
2183 | do { | 2201 | do { |
2184 | in_height = DIV_ROUND_UP(height, *decim_y); | 2202 | in_height = DIV_ROUND_UP(height, *decim_y); |
2185 | in_width = DIV_ROUND_UP(width, *decim_x); | 2203 | in_width = DIV_ROUND_UP(width, *decim_x); |
2186 | *core_clk = calc_core_clk_five_taps(pclk, mgr_timings, | 2204 | *five_taps = in_height > out_height; |
2187 | in_width, in_height, out_width, out_height, color_mode); | ||
2188 | |||
2189 | error = check_horiz_timing_omap3(pclk, lclk, mgr_timings, | ||
2190 | pos_x, in_width, in_height, out_width, | ||
2191 | out_height); | ||
2192 | 2205 | ||
2193 | if (in_width > maxsinglelinewidth) | 2206 | if (in_width > maxsinglelinewidth) |
2194 | if (in_height > out_height && | 2207 | if (in_height > out_height && |
2195 | in_height < out_height * 2) | 2208 | in_height < out_height * 2) |
2196 | *five_taps = false; | 2209 | *five_taps = false; |
2197 | if (!*five_taps) | 2210 | again: |
2211 | if (*five_taps) | ||
2212 | *core_clk = calc_core_clk_five_taps(pclk, mgr_timings, | ||
2213 | in_width, in_height, out_width, | ||
2214 | out_height, color_mode); | ||
2215 | else | ||
2198 | *core_clk = dispc.feat->calc_core_clk(pclk, in_width, | 2216 | *core_clk = dispc.feat->calc_core_clk(pclk, in_width, |
2199 | in_height, out_width, out_height, | 2217 | in_height, out_width, out_height, |
2200 | mem_to_mem); | 2218 | mem_to_mem); |
2201 | 2219 | ||
2220 | error = check_horiz_timing_omap3(pclk, lclk, mgr_timings, | ||
2221 | pos_x, in_width, in_height, out_width, | ||
2222 | out_height, *five_taps); | ||
2223 | if (error && *five_taps) { | ||
2224 | *five_taps = false; | ||
2225 | goto again; | ||
2226 | } | ||
2227 | |||
2202 | error = (error || in_width > maxsinglelinewidth * 2 || | 2228 | error = (error || in_width > maxsinglelinewidth * 2 || |
2203 | (in_width > maxsinglelinewidth && *five_taps) || | 2229 | (in_width > maxsinglelinewidth && *five_taps) || |
2204 | !*core_clk || *core_clk > dispc_core_clk_rate()); | 2230 | !*core_clk || *core_clk > dispc_core_clk_rate()); |
@@ -2215,7 +2241,7 @@ static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk, | |||
2215 | } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); | 2241 | } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); |
2216 | 2242 | ||
2217 | if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width, | 2243 | if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width, |
2218 | height, out_width, out_height)){ | 2244 | height, out_width, out_height, *five_taps)) { |
2219 | DSSERR("horizontal timing too tight\n"); | 2245 | DSSERR("horizontal timing too tight\n"); |
2220 | return -EINVAL; | 2246 | return -EINVAL; |
2221 | } | 2247 | } |
@@ -3211,6 +3237,8 @@ static void dispc_dump_regs(struct seq_file *s) | |||
3211 | DUMPREG(DISPC_CONTROL3); | 3237 | DUMPREG(DISPC_CONTROL3); |
3212 | DUMPREG(DISPC_CONFIG3); | 3238 | DUMPREG(DISPC_CONFIG3); |
3213 | } | 3239 | } |
3240 | if (dss_has_feature(FEAT_MFLAG)) | ||
3241 | DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE); | ||
3214 | 3242 | ||
3215 | #undef DUMPREG | 3243 | #undef DUMPREG |
3216 | 3244 | ||
@@ -3285,6 +3313,8 @@ static void dispc_dump_regs(struct seq_file *s) | |||
3285 | DUMPREG(i, DISPC_OVL_ATTRIBUTES2); | 3313 | DUMPREG(i, DISPC_OVL_ATTRIBUTES2); |
3286 | if (dss_has_feature(FEAT_PRELOAD)) | 3314 | if (dss_has_feature(FEAT_PRELOAD)) |
3287 | DUMPREG(i, DISPC_OVL_PRELOAD); | 3315 | DUMPREG(i, DISPC_OVL_PRELOAD); |
3316 | if (dss_has_feature(FEAT_MFLAG)) | ||
3317 | DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); | ||
3288 | } | 3318 | } |
3289 | 3319 | ||
3290 | #undef DISPC_REG | 3320 | #undef DISPC_REG |
@@ -3520,6 +3550,7 @@ static const struct dispc_features omap24xx_dispc_feats __initconst = { | |||
3520 | .calc_core_clk = calc_core_clk_24xx, | 3550 | .calc_core_clk = calc_core_clk_24xx, |
3521 | .num_fifos = 3, | 3551 | .num_fifos = 3, |
3522 | .no_framedone_tv = true, | 3552 | .no_framedone_tv = true, |
3553 | .set_max_preload = false, | ||
3523 | }; | 3554 | }; |
3524 | 3555 | ||
3525 | static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = { | 3556 | static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = { |
@@ -3539,6 +3570,7 @@ static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = { | |||
3539 | .calc_core_clk = calc_core_clk_34xx, | 3570 | .calc_core_clk = calc_core_clk_34xx, |
3540 | .num_fifos = 3, | 3571 | .num_fifos = 3, |
3541 | .no_framedone_tv = true, | 3572 | .no_framedone_tv = true, |
3573 | .set_max_preload = false, | ||
3542 | }; | 3574 | }; |
3543 | 3575 | ||
3544 | static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = { | 3576 | static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = { |
@@ -3558,6 +3590,7 @@ static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = { | |||
3558 | .calc_core_clk = calc_core_clk_34xx, | 3590 | .calc_core_clk = calc_core_clk_34xx, |
3559 | .num_fifos = 3, | 3591 | .num_fifos = 3, |
3560 | .no_framedone_tv = true, | 3592 | .no_framedone_tv = true, |
3593 | .set_max_preload = false, | ||
3561 | }; | 3594 | }; |
3562 | 3595 | ||
3563 | static const struct dispc_features omap44xx_dispc_feats __initconst = { | 3596 | static const struct dispc_features omap44xx_dispc_feats __initconst = { |
@@ -3577,6 +3610,7 @@ static const struct dispc_features omap44xx_dispc_feats __initconst = { | |||
3577 | .calc_core_clk = calc_core_clk_44xx, | 3610 | .calc_core_clk = calc_core_clk_44xx, |
3578 | .num_fifos = 5, | 3611 | .num_fifos = 5, |
3579 | .gfx_fifo_workaround = true, | 3612 | .gfx_fifo_workaround = true, |
3613 | .set_max_preload = true, | ||
3580 | }; | 3614 | }; |
3581 | 3615 | ||
3582 | static const struct dispc_features omap54xx_dispc_feats __initconst = { | 3616 | static const struct dispc_features omap54xx_dispc_feats __initconst = { |
@@ -3597,6 +3631,7 @@ static const struct dispc_features omap54xx_dispc_feats __initconst = { | |||
3597 | .num_fifos = 5, | 3631 | .num_fifos = 5, |
3598 | .gfx_fifo_workaround = true, | 3632 | .gfx_fifo_workaround = true, |
3599 | .mstandby_workaround = true, | 3633 | .mstandby_workaround = true, |
3634 | .set_max_preload = true, | ||
3600 | }; | 3635 | }; |
3601 | 3636 | ||
3602 | static int __init dispc_init_features(struct platform_device *pdev) | 3637 | static int __init dispc_init_features(struct platform_device *pdev) |
@@ -3691,7 +3726,6 @@ static int __init omap_dispchw_probe(struct platform_device *pdev) | |||
3691 | } | 3726 | } |
3692 | 3727 | ||
3693 | pm_runtime_enable(&pdev->dev); | 3728 | pm_runtime_enable(&pdev->dev); |
3694 | pm_runtime_irq_safe(&pdev->dev); | ||
3695 | 3729 | ||
3696 | r = dispc_runtime_get(); | 3730 | r = dispc_runtime_get(); |
3697 | if (r) | 3731 | if (r) |
@@ -3734,6 +3768,8 @@ static int dispc_runtime_suspend(struct device *dev) | |||
3734 | 3768 | ||
3735 | static int dispc_runtime_resume(struct device *dev) | 3769 | static int dispc_runtime_resume(struct device *dev) |
3736 | { | 3770 | { |
3771 | _omap_dispc_initial_config(); | ||
3772 | |||
3737 | dispc_restore_context(); | 3773 | dispc_restore_context(); |
3738 | 3774 | ||
3739 | return 0; | 3775 | return 0; |
diff --git a/drivers/video/omap2/dss/dispc.h b/drivers/video/omap2/dss/dispc.h index de4863d21ab7..78edb449c763 100644 --- a/drivers/video/omap2/dss/dispc.h +++ b/drivers/video/omap2/dss/dispc.h | |||
@@ -40,6 +40,7 @@ | |||
40 | #define DISPC_CONTROL3 0x0848 | 40 | #define DISPC_CONTROL3 0x0848 |
41 | #define DISPC_CONFIG3 0x084C | 41 | #define DISPC_CONFIG3 0x084C |
42 | #define DISPC_MSTANDBY_CTRL 0x0858 | 42 | #define DISPC_MSTANDBY_CTRL 0x0858 |
43 | #define DISPC_GLOBAL_MFLAG_ATTRIBUTE 0x085C | ||
43 | 44 | ||
44 | /* DISPC overlay registers */ | 45 | /* DISPC overlay registers */ |
45 | #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \ | 46 | #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \ |
@@ -100,6 +101,8 @@ | |||
100 | DISPC_FIR_COEF_V2_OFFSET(n, i)) | 101 | DISPC_FIR_COEF_V2_OFFSET(n, i)) |
101 | #define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \ | 102 | #define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \ |
102 | DISPC_PRELOAD_OFFSET(n)) | 103 | DISPC_PRELOAD_OFFSET(n)) |
104 | #define DISPC_OVL_MFLAG_THRESHOLD(n) (DISPC_OVL_BASE(n) + \ | ||
105 | DISPC_MFLAG_THRESHOLD_OFFSET(n)) | ||
103 | 106 | ||
104 | /* DISPC up/downsampling FIR filter coefficient structure */ | 107 | /* DISPC up/downsampling FIR filter coefficient structure */ |
105 | struct dispc_coef { | 108 | struct dispc_coef { |
@@ -894,4 +897,21 @@ static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane) | |||
894 | return 0; | 897 | return 0; |
895 | } | 898 | } |
896 | } | 899 | } |
900 | |||
901 | static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane plane) | ||
902 | { | ||
903 | switch (plane) { | ||
904 | case OMAP_DSS_GFX: | ||
905 | return 0x0860; | ||
906 | case OMAP_DSS_VIDEO1: | ||
907 | return 0x0864; | ||
908 | case OMAP_DSS_VIDEO2: | ||
909 | return 0x0868; | ||
910 | case OMAP_DSS_VIDEO3: | ||
911 | return 0x086c; | ||
912 | default: | ||
913 | BUG(); | ||
914 | return 0; | ||
915 | } | ||
916 | } | ||
897 | #endif | 917 | #endif |
diff --git a/drivers/video/omap2/dss/display-sysfs.c b/drivers/video/omap2/dss/display-sysfs.c index 21d7f77df702..f7b5f9561041 100644 --- a/drivers/video/omap2/dss/display-sysfs.c +++ b/drivers/video/omap2/dss/display-sysfs.c | |||
@@ -277,7 +277,7 @@ static ssize_t display_wss_store(struct device *dev, | |||
277 | return size; | 277 | return size; |
278 | } | 278 | } |
279 | 279 | ||
280 | static DEVICE_ATTR(name, S_IRUGO, display_name_show, NULL); | 280 | static DEVICE_ATTR(display_name, S_IRUGO, display_name_show, NULL); |
281 | static DEVICE_ATTR(enabled, S_IRUGO|S_IWUSR, | 281 | static DEVICE_ATTR(enabled, S_IRUGO|S_IWUSR, |
282 | display_enabled_show, display_enabled_store); | 282 | display_enabled_show, display_enabled_store); |
283 | static DEVICE_ATTR(tear_elim, S_IRUGO|S_IWUSR, | 283 | static DEVICE_ATTR(tear_elim, S_IRUGO|S_IWUSR, |
@@ -292,7 +292,7 @@ static DEVICE_ATTR(wss, S_IRUGO|S_IWUSR, | |||
292 | display_wss_show, display_wss_store); | 292 | display_wss_show, display_wss_store); |
293 | 293 | ||
294 | static const struct attribute *display_sysfs_attrs[] = { | 294 | static const struct attribute *display_sysfs_attrs[] = { |
295 | &dev_attr_name.attr, | 295 | &dev_attr_display_name.attr, |
296 | &dev_attr_enabled.attr, | 296 | &dev_attr_enabled.attr, |
297 | &dev_attr_tear_elim.attr, | 297 | &dev_attr_tear_elim.attr, |
298 | &dev_attr_timings.attr, | 298 | &dev_attr_timings.attr, |
diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c index bd48cde53561..7411f2674e16 100644 --- a/drivers/video/omap2/dss/dpi.c +++ b/drivers/video/omap2/dss/dpi.c | |||
@@ -117,7 +117,7 @@ struct dpi_clk_calc_ctx { | |||
117 | /* outputs */ | 117 | /* outputs */ |
118 | 118 | ||
119 | struct dsi_clock_info dsi_cinfo; | 119 | struct dsi_clock_info dsi_cinfo; |
120 | struct dss_clock_info dss_cinfo; | 120 | unsigned long long fck; |
121 | struct dispc_clock_info dispc_cinfo; | 121 | struct dispc_clock_info dispc_cinfo; |
122 | }; | 122 | }; |
123 | 123 | ||
@@ -184,12 +184,11 @@ static bool dpi_calc_pll_cb(int regn, int regm, unsigned long fint, | |||
184 | dpi_calc_hsdiv_cb, ctx); | 184 | dpi_calc_hsdiv_cb, ctx); |
185 | } | 185 | } |
186 | 186 | ||
187 | static bool dpi_calc_dss_cb(int fckd, unsigned long fck, void *data) | 187 | static bool dpi_calc_dss_cb(unsigned long fck, void *data) |
188 | { | 188 | { |
189 | struct dpi_clk_calc_ctx *ctx = data; | 189 | struct dpi_clk_calc_ctx *ctx = data; |
190 | 190 | ||
191 | ctx->dss_cinfo.fck = fck; | 191 | ctx->fck = fck; |
192 | ctx->dss_cinfo.fck_div = fckd; | ||
193 | 192 | ||
194 | return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max, | 193 | return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max, |
195 | dpi_calc_dispc_cb, ctx); | 194 | dpi_calc_dispc_cb, ctx); |
@@ -237,7 +236,7 @@ static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx) | |||
237 | ctx->pck_min = 0; | 236 | ctx->pck_min = 0; |
238 | ctx->pck_max = pck + 1000 * i * i * i; | 237 | ctx->pck_max = pck + 1000 * i * i * i; |
239 | 238 | ||
240 | ok = dss_div_calc(ctx->pck_min, dpi_calc_dss_cb, ctx); | 239 | ok = dss_div_calc(pck, ctx->pck_min, dpi_calc_dss_cb, ctx); |
241 | if (ok) | 240 | if (ok) |
242 | return ok; | 241 | return ok; |
243 | } | 242 | } |
@@ -286,13 +285,13 @@ static int dpi_set_dispc_clk(unsigned long pck_req, unsigned long *fck, | |||
286 | if (!ok) | 285 | if (!ok) |
287 | return -EINVAL; | 286 | return -EINVAL; |
288 | 287 | ||
289 | r = dss_set_clock_div(&ctx.dss_cinfo); | 288 | r = dss_set_fck_rate(ctx.fck); |
290 | if (r) | 289 | if (r) |
291 | return r; | 290 | return r; |
292 | 291 | ||
293 | dpi.mgr_config.clock_info = ctx.dispc_cinfo; | 292 | dpi.mgr_config.clock_info = ctx.dispc_cinfo; |
294 | 293 | ||
295 | *fck = ctx.dss_cinfo.fck; | 294 | *fck = ctx.fck; |
296 | *lck_div = ctx.dispc_cinfo.lck_div; | 295 | *lck_div = ctx.dispc_cinfo.lck_div; |
297 | *pck_div = ctx.dispc_cinfo.pck_div; | 296 | *pck_div = ctx.dispc_cinfo.pck_div; |
298 | 297 | ||
@@ -495,7 +494,7 @@ static int dpi_check_timings(struct omap_dss_device *dssdev, | |||
495 | if (!ok) | 494 | if (!ok) |
496 | return -EINVAL; | 495 | return -EINVAL; |
497 | 496 | ||
498 | fck = ctx.dss_cinfo.fck; | 497 | fck = ctx.fck; |
499 | } | 498 | } |
500 | 499 | ||
501 | lck_div = ctx.dispc_cinfo.lck_div; | 500 | lck_div = ctx.dispc_cinfo.lck_div; |
@@ -551,7 +550,8 @@ static int dpi_init_regulator(void) | |||
551 | 550 | ||
552 | vdds_dsi = devm_regulator_get(&dpi.pdev->dev, "vdds_dsi"); | 551 | vdds_dsi = devm_regulator_get(&dpi.pdev->dev, "vdds_dsi"); |
553 | if (IS_ERR(vdds_dsi)) { | 552 | if (IS_ERR(vdds_dsi)) { |
554 | DSSERR("can't get VDDS_DSI regulator\n"); | 553 | if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) |
554 | DSSERR("can't get VDDS_DSI regulator\n"); | ||
555 | return PTR_ERR(vdds_dsi); | 555 | return PTR_ERR(vdds_dsi); |
556 | } | 556 | } |
557 | 557 | ||
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index 6056b27cf73c..a820c37e323e 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c | |||
@@ -47,63 +47,73 @@ | |||
47 | 47 | ||
48 | #define DSI_CATCH_MISSING_TE | 48 | #define DSI_CATCH_MISSING_TE |
49 | 49 | ||
50 | struct dsi_reg { u16 idx; }; | 50 | struct dsi_reg { u16 module; u16 idx; }; |
51 | 51 | ||
52 | #define DSI_REG(idx) ((const struct dsi_reg) { idx }) | 52 | #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx }) |
53 | 53 | ||
54 | #define DSI_SZ_REGS SZ_1K | ||
55 | /* DSI Protocol Engine */ | 54 | /* DSI Protocol Engine */ |
56 | 55 | ||
57 | #define DSI_REVISION DSI_REG(0x0000) | 56 | #define DSI_PROTO 0 |
58 | #define DSI_SYSCONFIG DSI_REG(0x0010) | 57 | #define DSI_PROTO_SZ 0x200 |
59 | #define DSI_SYSSTATUS DSI_REG(0x0014) | 58 | |
60 | #define DSI_IRQSTATUS DSI_REG(0x0018) | 59 | #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000) |
61 | #define DSI_IRQENABLE DSI_REG(0x001C) | 60 | #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010) |
62 | #define DSI_CTRL DSI_REG(0x0040) | 61 | #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014) |
63 | #define DSI_GNQ DSI_REG(0x0044) | 62 | #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018) |
64 | #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048) | 63 | #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C) |
65 | #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C) | 64 | #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040) |
66 | #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050) | 65 | #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044) |
67 | #define DSI_CLK_CTRL DSI_REG(0x0054) | 66 | #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048) |
68 | #define DSI_TIMING1 DSI_REG(0x0058) | 67 | #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C) |
69 | #define DSI_TIMING2 DSI_REG(0x005C) | 68 | #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050) |
70 | #define DSI_VM_TIMING1 DSI_REG(0x0060) | 69 | #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054) |
71 | #define DSI_VM_TIMING2 DSI_REG(0x0064) | 70 | #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058) |
72 | #define DSI_VM_TIMING3 DSI_REG(0x0068) | 71 | #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C) |
73 | #define DSI_CLK_TIMING DSI_REG(0x006C) | 72 | #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060) |
74 | #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070) | 73 | #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064) |
75 | #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074) | 74 | #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068) |
76 | #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078) | 75 | #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C) |
77 | #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C) | 76 | #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070) |
78 | #define DSI_VM_TIMING4 DSI_REG(0x0080) | 77 | #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074) |
79 | #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084) | 78 | #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078) |
80 | #define DSI_VM_TIMING5 DSI_REG(0x0088) | 79 | #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C) |
81 | #define DSI_VM_TIMING6 DSI_REG(0x008C) | 80 | #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080) |
82 | #define DSI_VM_TIMING7 DSI_REG(0x0090) | 81 | #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084) |
83 | #define DSI_STOPCLK_TIMING DSI_REG(0x0094) | 82 | #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088) |
84 | #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20)) | 83 | #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C) |
85 | #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20)) | 84 | #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090) |
86 | #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20)) | 85 | #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094) |
87 | #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20)) | 86 | #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20)) |
88 | #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20)) | 87 | #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20)) |
89 | #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20)) | 88 | #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20)) |
90 | #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20)) | 89 | #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20)) |
90 | #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20)) | ||
91 | #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20)) | ||
92 | #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20)) | ||
91 | 93 | ||
92 | /* DSIPHY_SCP */ | 94 | /* DSIPHY_SCP */ |
93 | 95 | ||
94 | #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000) | 96 | #define DSI_PHY 1 |
95 | #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004) | 97 | #define DSI_PHY_OFFSET 0x200 |
96 | #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008) | 98 | #define DSI_PHY_SZ 0x40 |
97 | #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014) | 99 | |
98 | #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028) | 100 | #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000) |
101 | #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004) | ||
102 | #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008) | ||
103 | #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014) | ||
104 | #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028) | ||
99 | 105 | ||
100 | /* DSI_PLL_CTRL_SCP */ | 106 | /* DSI_PLL_CTRL_SCP */ |
101 | 107 | ||
102 | #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000) | 108 | #define DSI_PLL 2 |
103 | #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004) | 109 | #define DSI_PLL_OFFSET 0x300 |
104 | #define DSI_PLL_GO DSI_REG(0x300 + 0x0008) | 110 | #define DSI_PLL_SZ 0x20 |
105 | #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C) | 111 | |
106 | #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010) | 112 | #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000) |
113 | #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004) | ||
114 | #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008) | ||
115 | #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C) | ||
116 | #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010) | ||
107 | 117 | ||
108 | #define REG_GET(dsidev, idx, start, end) \ | 118 | #define REG_GET(dsidev, idx, start, end) \ |
109 | FLD_GET(dsi_read_reg(dsidev, idx), start, end) | 119 | FLD_GET(dsi_read_reg(dsidev, idx), start, end) |
@@ -277,7 +287,9 @@ struct dsi_clk_calc_ctx { | |||
277 | 287 | ||
278 | struct dsi_data { | 288 | struct dsi_data { |
279 | struct platform_device *pdev; | 289 | struct platform_device *pdev; |
280 | void __iomem *base; | 290 | void __iomem *proto_base; |
291 | void __iomem *phy_base; | ||
292 | void __iomem *pll_base; | ||
281 | 293 | ||
282 | int module_id; | 294 | int module_id; |
283 | 295 | ||
@@ -297,7 +309,8 @@ struct dsi_data { | |||
297 | struct { | 309 | struct { |
298 | enum dsi_vc_source source; | 310 | enum dsi_vc_source source; |
299 | struct omap_dss_device *dssdev; | 311 | struct omap_dss_device *dssdev; |
300 | enum fifo_size fifo_size; | 312 | enum fifo_size tx_fifo_size; |
313 | enum fifo_size rx_fifo_size; | ||
301 | int vc_id; | 314 | int vc_id; |
302 | } vc[4]; | 315 | } vc[4]; |
303 | 316 | ||
@@ -413,16 +426,32 @@ static inline void dsi_write_reg(struct platform_device *dsidev, | |||
413 | const struct dsi_reg idx, u32 val) | 426 | const struct dsi_reg idx, u32 val) |
414 | { | 427 | { |
415 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | 428 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
429 | void __iomem *base; | ||
430 | |||
431 | switch(idx.module) { | ||
432 | case DSI_PROTO: base = dsi->proto_base; break; | ||
433 | case DSI_PHY: base = dsi->phy_base; break; | ||
434 | case DSI_PLL: base = dsi->pll_base; break; | ||
435 | default: return; | ||
436 | } | ||
416 | 437 | ||
417 | __raw_writel(val, dsi->base + idx.idx); | 438 | __raw_writel(val, base + idx.idx); |
418 | } | 439 | } |
419 | 440 | ||
420 | static inline u32 dsi_read_reg(struct platform_device *dsidev, | 441 | static inline u32 dsi_read_reg(struct platform_device *dsidev, |
421 | const struct dsi_reg idx) | 442 | const struct dsi_reg idx) |
422 | { | 443 | { |
423 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | 444 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
445 | void __iomem *base; | ||
424 | 446 | ||
425 | return __raw_readl(dsi->base + idx.idx); | 447 | switch(idx.module) { |
448 | case DSI_PROTO: base = dsi->proto_base; break; | ||
449 | case DSI_PHY: base = dsi->phy_base; break; | ||
450 | case DSI_PLL: base = dsi->pll_base; break; | ||
451 | default: return 0; | ||
452 | } | ||
453 | |||
454 | return __raw_readl(base + idx.idx); | ||
426 | } | 455 | } |
427 | 456 | ||
428 | static void dsi_bus_lock(struct omap_dss_device *dssdev) | 457 | static void dsi_bus_lock(struct omap_dss_device *dssdev) |
@@ -1129,7 +1158,8 @@ static int dsi_regulator_init(struct platform_device *dsidev) | |||
1129 | vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "VCXIO"); | 1158 | vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "VCXIO"); |
1130 | 1159 | ||
1131 | if (IS_ERR(vdds_dsi)) { | 1160 | if (IS_ERR(vdds_dsi)) { |
1132 | DSSERR("can't get VDDS_DSI regulator\n"); | 1161 | if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) |
1162 | DSSERR("can't get VDDS_DSI regulator\n"); | ||
1133 | return PTR_ERR(vdds_dsi); | 1163 | return PTR_ERR(vdds_dsi); |
1134 | } | 1164 | } |
1135 | 1165 | ||
@@ -2427,14 +2457,14 @@ static void dsi_config_tx_fifo(struct platform_device *dsidev, | |||
2427 | int add = 0; | 2457 | int add = 0; |
2428 | int i; | 2458 | int i; |
2429 | 2459 | ||
2430 | dsi->vc[0].fifo_size = size1; | 2460 | dsi->vc[0].tx_fifo_size = size1; |
2431 | dsi->vc[1].fifo_size = size2; | 2461 | dsi->vc[1].tx_fifo_size = size2; |
2432 | dsi->vc[2].fifo_size = size3; | 2462 | dsi->vc[2].tx_fifo_size = size3; |
2433 | dsi->vc[3].fifo_size = size4; | 2463 | dsi->vc[3].tx_fifo_size = size4; |
2434 | 2464 | ||
2435 | for (i = 0; i < 4; i++) { | 2465 | for (i = 0; i < 4; i++) { |
2436 | u8 v; | 2466 | u8 v; |
2437 | int size = dsi->vc[i].fifo_size; | 2467 | int size = dsi->vc[i].tx_fifo_size; |
2438 | 2468 | ||
2439 | if (add + size > 4) { | 2469 | if (add + size > 4) { |
2440 | DSSERR("Illegal FIFO configuration\n"); | 2470 | DSSERR("Illegal FIFO configuration\n"); |
@@ -2460,14 +2490,14 @@ static void dsi_config_rx_fifo(struct platform_device *dsidev, | |||
2460 | int add = 0; | 2490 | int add = 0; |
2461 | int i; | 2491 | int i; |
2462 | 2492 | ||
2463 | dsi->vc[0].fifo_size = size1; | 2493 | dsi->vc[0].rx_fifo_size = size1; |
2464 | dsi->vc[1].fifo_size = size2; | 2494 | dsi->vc[1].rx_fifo_size = size2; |
2465 | dsi->vc[2].fifo_size = size3; | 2495 | dsi->vc[2].rx_fifo_size = size3; |
2466 | dsi->vc[3].fifo_size = size4; | 2496 | dsi->vc[3].rx_fifo_size = size4; |
2467 | 2497 | ||
2468 | for (i = 0; i < 4; i++) { | 2498 | for (i = 0; i < 4; i++) { |
2469 | u8 v; | 2499 | u8 v; |
2470 | int size = dsi->vc[i].fifo_size; | 2500 | int size = dsi->vc[i].rx_fifo_size; |
2471 | 2501 | ||
2472 | if (add + size > 4) { | 2502 | if (add + size > 4) { |
2473 | DSSERR("Illegal FIFO configuration\n"); | 2503 | DSSERR("Illegal FIFO configuration\n"); |
@@ -2920,7 +2950,7 @@ static int dsi_vc_send_long(struct platform_device *dsidev, int channel, | |||
2920 | DSSDBG("dsi_vc_send_long, %d bytes\n", len); | 2950 | DSSDBG("dsi_vc_send_long, %d bytes\n", len); |
2921 | 2951 | ||
2922 | /* len + header */ | 2952 | /* len + header */ |
2923 | if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) { | 2953 | if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) { |
2924 | DSSERR("unable to send long packet: packet too long.\n"); | 2954 | DSSERR("unable to send long packet: packet too long.\n"); |
2925 | return -EINVAL; | 2955 | return -EINVAL; |
2926 | } | 2956 | } |
@@ -5345,8 +5375,9 @@ static int omap_dsihw_probe(struct platform_device *dsidev) | |||
5345 | { | 5375 | { |
5346 | u32 rev; | 5376 | u32 rev; |
5347 | int r, i; | 5377 | int r, i; |
5348 | struct resource *dsi_mem; | ||
5349 | struct dsi_data *dsi; | 5378 | struct dsi_data *dsi; |
5379 | struct resource *res; | ||
5380 | struct resource temp_res; | ||
5350 | 5381 | ||
5351 | dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL); | 5382 | dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL); |
5352 | if (!dsi) | 5383 | if (!dsi) |
@@ -5376,16 +5407,64 @@ static int omap_dsihw_probe(struct platform_device *dsidev) | |||
5376 | dsi->te_timer.function = dsi_te_timeout; | 5407 | dsi->te_timer.function = dsi_te_timeout; |
5377 | dsi->te_timer.data = 0; | 5408 | dsi->te_timer.data = 0; |
5378 | #endif | 5409 | #endif |
5379 | dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0); | 5410 | |
5380 | if (!dsi_mem) { | 5411 | res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto"); |
5381 | DSSERR("can't get IORESOURCE_MEM DSI\n"); | 5412 | if (!res) { |
5382 | return -EINVAL; | 5413 | res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); |
5414 | if (!res) { | ||
5415 | DSSERR("can't get IORESOURCE_MEM DSI\n"); | ||
5416 | return -EINVAL; | ||
5417 | } | ||
5418 | |||
5419 | temp_res.start = res->start; | ||
5420 | temp_res.end = temp_res.start + DSI_PROTO_SZ - 1; | ||
5421 | res = &temp_res; | ||
5422 | } | ||
5423 | |||
5424 | dsi->proto_base = devm_ioremap(&dsidev->dev, res->start, | ||
5425 | resource_size(res)); | ||
5426 | if (!dsi->proto_base) { | ||
5427 | DSSERR("can't ioremap DSI protocol engine\n"); | ||
5428 | return -ENOMEM; | ||
5429 | } | ||
5430 | |||
5431 | res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy"); | ||
5432 | if (!res) { | ||
5433 | res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); | ||
5434 | if (!res) { | ||
5435 | DSSERR("can't get IORESOURCE_MEM DSI\n"); | ||
5436 | return -EINVAL; | ||
5437 | } | ||
5438 | |||
5439 | temp_res.start = res->start + DSI_PHY_OFFSET; | ||
5440 | temp_res.end = temp_res.start + DSI_PHY_SZ - 1; | ||
5441 | res = &temp_res; | ||
5442 | } | ||
5443 | |||
5444 | dsi->phy_base = devm_ioremap(&dsidev->dev, res->start, | ||
5445 | resource_size(res)); | ||
5446 | if (!dsi->proto_base) { | ||
5447 | DSSERR("can't ioremap DSI PHY\n"); | ||
5448 | return -ENOMEM; | ||
5449 | } | ||
5450 | |||
5451 | res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll"); | ||
5452 | if (!res) { | ||
5453 | res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); | ||
5454 | if (!res) { | ||
5455 | DSSERR("can't get IORESOURCE_MEM DSI\n"); | ||
5456 | return -EINVAL; | ||
5457 | } | ||
5458 | |||
5459 | temp_res.start = res->start + DSI_PLL_OFFSET; | ||
5460 | temp_res.end = temp_res.start + DSI_PLL_SZ - 1; | ||
5461 | res = &temp_res; | ||
5383 | } | 5462 | } |
5384 | 5463 | ||
5385 | dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start, | 5464 | dsi->pll_base = devm_ioremap(&dsidev->dev, res->start, |
5386 | resource_size(dsi_mem)); | 5465 | resource_size(res)); |
5387 | if (!dsi->base) { | 5466 | if (!dsi->proto_base) { |
5388 | DSSERR("can't ioremap DSI\n"); | 5467 | DSSERR("can't ioremap DSI PLL\n"); |
5389 | return -ENOMEM; | 5468 | return -ENOMEM; |
5390 | } | 5469 | } |
5391 | 5470 | ||
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index bd01608e67e2..9a145da35ad3 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c | |||
@@ -67,7 +67,7 @@ static void dss_runtime_put(void); | |||
67 | struct dss_features { | 67 | struct dss_features { |
68 | u8 fck_div_max; | 68 | u8 fck_div_max; |
69 | u8 dss_fck_multiplier; | 69 | u8 dss_fck_multiplier; |
70 | const char *clk_name; | 70 | const char *parent_clk_name; |
71 | int (*dpi_select_source)(enum omap_channel channel); | 71 | int (*dpi_select_source)(enum omap_channel channel); |
72 | }; | 72 | }; |
73 | 73 | ||
@@ -75,13 +75,12 @@ static struct { | |||
75 | struct platform_device *pdev; | 75 | struct platform_device *pdev; |
76 | void __iomem *base; | 76 | void __iomem *base; |
77 | 77 | ||
78 | struct clk *dpll4_m4_ck; | 78 | struct clk *parent_clk; |
79 | struct clk *dss_clk; | 79 | struct clk *dss_clk; |
80 | unsigned long dss_clk_rate; | 80 | unsigned long dss_clk_rate; |
81 | 81 | ||
82 | unsigned long cache_req_pck; | 82 | unsigned long cache_req_pck; |
83 | unsigned long cache_prate; | 83 | unsigned long cache_prate; |
84 | struct dss_clock_info cache_dss_cinfo; | ||
85 | struct dispc_clock_info cache_dispc_cinfo; | 84 | struct dispc_clock_info cache_dispc_cinfo; |
86 | 85 | ||
87 | enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI]; | 86 | enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI]; |
@@ -265,8 +264,6 @@ const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src) | |||
265 | 264 | ||
266 | void dss_dump_clocks(struct seq_file *s) | 265 | void dss_dump_clocks(struct seq_file *s) |
267 | { | 266 | { |
268 | unsigned long dpll4_ck_rate; | ||
269 | unsigned long dpll4_m4_ck_rate; | ||
270 | const char *fclk_name, *fclk_real_name; | 267 | const char *fclk_name, *fclk_real_name; |
271 | unsigned long fclk_rate; | 268 | unsigned long fclk_rate; |
272 | 269 | ||
@@ -279,21 +276,9 @@ void dss_dump_clocks(struct seq_file *s) | |||
279 | fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK); | 276 | fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK); |
280 | fclk_rate = clk_get_rate(dss.dss_clk); | 277 | fclk_rate = clk_get_rate(dss.dss_clk); |
281 | 278 | ||
282 | if (dss.dpll4_m4_ck) { | 279 | seq_printf(s, "%s (%s) = %lu\n", |
283 | dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); | 280 | fclk_name, fclk_real_name, |
284 | dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); | 281 | fclk_rate); |
285 | |||
286 | seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); | ||
287 | |||
288 | seq_printf(s, "%s (%s) = %lu / %lu * %d = %lu\n", | ||
289 | fclk_name, fclk_real_name, dpll4_ck_rate, | ||
290 | dpll4_ck_rate / dpll4_m4_ck_rate, | ||
291 | dss.feat->dss_fck_multiplier, fclk_rate); | ||
292 | } else { | ||
293 | seq_printf(s, "%s (%s) = %lu\n", | ||
294 | fclk_name, fclk_real_name, | ||
295 | fclk_rate); | ||
296 | } | ||
297 | 282 | ||
298 | dss_runtime_put(); | 283 | dss_runtime_put(); |
299 | } | 284 | } |
@@ -451,30 +436,8 @@ enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) | |||
451 | } | 436 | } |
452 | } | 437 | } |
453 | 438 | ||
454 | /* calculate clock rates using dividers in cinfo */ | 439 | bool dss_div_calc(unsigned long pck, unsigned long fck_min, |
455 | int dss_calc_clock_rates(struct dss_clock_info *cinfo) | 440 | dss_div_calc_func func, void *data) |
456 | { | ||
457 | if (dss.dpll4_m4_ck) { | ||
458 | unsigned long prate; | ||
459 | |||
460 | if (cinfo->fck_div > dss.feat->fck_div_max || | ||
461 | cinfo->fck_div == 0) | ||
462 | return -EINVAL; | ||
463 | |||
464 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); | ||
465 | |||
466 | cinfo->fck = prate / cinfo->fck_div * | ||
467 | dss.feat->dss_fck_multiplier; | ||
468 | } else { | ||
469 | if (cinfo->fck_div != 0) | ||
470 | return -EINVAL; | ||
471 | cinfo->fck = clk_get_rate(dss.dss_clk); | ||
472 | } | ||
473 | |||
474 | return 0; | ||
475 | } | ||
476 | |||
477 | bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data) | ||
478 | { | 441 | { |
479 | int fckd, fckd_start, fckd_stop; | 442 | int fckd, fckd_start, fckd_stop; |
480 | unsigned long fck; | 443 | unsigned long fck; |
@@ -483,22 +446,24 @@ bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data) | |||
483 | unsigned long prate; | 446 | unsigned long prate; |
484 | unsigned m; | 447 | unsigned m; |
485 | 448 | ||
486 | if (dss.dpll4_m4_ck == NULL) { | 449 | fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
487 | /* | 450 | |
488 | * TODO: dss1_fclk can be changed on OMAP2, but the available | 451 | if (dss.parent_clk == NULL) { |
489 | * dividers are not continuous. We just use the pre-set rate for | 452 | unsigned pckd; |
490 | * now. | 453 | |
491 | */ | 454 | pckd = fck_hw_max / pck; |
492 | fck = clk_get_rate(dss.dss_clk); | 455 | |
493 | fckd = 1; | 456 | fck = pck * pckd; |
494 | return func(fckd, fck, data); | 457 | |
458 | fck = clk_round_rate(dss.dss_clk, fck); | ||
459 | |||
460 | return func(fck, data); | ||
495 | } | 461 | } |
496 | 462 | ||
497 | fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); | ||
498 | fckd_hw_max = dss.feat->fck_div_max; | 463 | fckd_hw_max = dss.feat->fck_div_max; |
499 | 464 | ||
500 | m = dss.feat->dss_fck_multiplier; | 465 | m = dss.feat->dss_fck_multiplier; |
501 | prate = dss_get_dpll4_rate(); | 466 | prate = clk_get_rate(dss.parent_clk); |
502 | 467 | ||
503 | fck_min = fck_min ? fck_min : 1; | 468 | fck_min = fck_min ? fck_min : 1; |
504 | 469 | ||
@@ -508,50 +473,32 @@ bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data) | |||
508 | for (fckd = fckd_start; fckd >= fckd_stop; --fckd) { | 473 | for (fckd = fckd_start; fckd >= fckd_stop; --fckd) { |
509 | fck = prate / fckd * m; | 474 | fck = prate / fckd * m; |
510 | 475 | ||
511 | if (func(fckd, fck, data)) | 476 | if (func(fck, data)) |
512 | return true; | 477 | return true; |
513 | } | 478 | } |
514 | 479 | ||
515 | return false; | 480 | return false; |
516 | } | 481 | } |
517 | 482 | ||
518 | int dss_set_clock_div(struct dss_clock_info *cinfo) | 483 | int dss_set_fck_rate(unsigned long rate) |
519 | { | 484 | { |
520 | if (dss.dpll4_m4_ck) { | 485 | int r; |
521 | unsigned long prate; | ||
522 | int r; | ||
523 | 486 | ||
524 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); | 487 | DSSDBG("set fck to %lu\n", rate); |
525 | DSSDBG("dpll4_m4 = %ld\n", prate); | ||
526 | 488 | ||
527 | r = clk_set_rate(dss.dpll4_m4_ck, | 489 | r = clk_set_rate(dss.dss_clk, rate); |
528 | DIV_ROUND_UP(prate, cinfo->fck_div)); | 490 | if (r) |
529 | if (r) | 491 | return r; |
530 | return r; | ||
531 | } else { | ||
532 | if (cinfo->fck_div != 0) | ||
533 | return -EINVAL; | ||
534 | } | ||
535 | 492 | ||
536 | dss.dss_clk_rate = clk_get_rate(dss.dss_clk); | 493 | dss.dss_clk_rate = clk_get_rate(dss.dss_clk); |
537 | 494 | ||
538 | WARN_ONCE(dss.dss_clk_rate != cinfo->fck, | 495 | WARN_ONCE(dss.dss_clk_rate != rate, |
539 | "clk rate mismatch: %lu != %lu", dss.dss_clk_rate, | 496 | "clk rate mismatch: %lu != %lu", dss.dss_clk_rate, |
540 | cinfo->fck); | 497 | rate); |
541 | |||
542 | DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div); | ||
543 | 498 | ||
544 | return 0; | 499 | return 0; |
545 | } | 500 | } |
546 | 501 | ||
547 | unsigned long dss_get_dpll4_rate(void) | ||
548 | { | ||
549 | if (dss.dpll4_m4_ck) | ||
550 | return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); | ||
551 | else | ||
552 | return 0; | ||
553 | } | ||
554 | |||
555 | unsigned long dss_get_dispc_clk_rate(void) | 502 | unsigned long dss_get_dispc_clk_rate(void) |
556 | { | 503 | { |
557 | return dss.dss_clk_rate; | 504 | return dss.dss_clk_rate; |
@@ -560,27 +507,23 @@ unsigned long dss_get_dispc_clk_rate(void) | |||
560 | static int dss_setup_default_clock(void) | 507 | static int dss_setup_default_clock(void) |
561 | { | 508 | { |
562 | unsigned long max_dss_fck, prate; | 509 | unsigned long max_dss_fck, prate; |
510 | unsigned long fck; | ||
563 | unsigned fck_div; | 511 | unsigned fck_div; |
564 | struct dss_clock_info dss_cinfo = { 0 }; | ||
565 | int r; | 512 | int r; |
566 | 513 | ||
567 | if (dss.dpll4_m4_ck == NULL) | ||
568 | return 0; | ||
569 | |||
570 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); | 514 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
571 | 515 | ||
572 | prate = dss_get_dpll4_rate(); | 516 | if (dss.parent_clk == NULL) { |
573 | 517 | fck = clk_round_rate(dss.dss_clk, max_dss_fck); | |
574 | fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier, | 518 | } else { |
575 | max_dss_fck); | 519 | prate = clk_get_rate(dss.parent_clk); |
576 | |||
577 | dss_cinfo.fck_div = fck_div; | ||
578 | 520 | ||
579 | r = dss_calc_clock_rates(&dss_cinfo); | 521 | fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier, |
580 | if (r) | 522 | max_dss_fck); |
581 | return r; | 523 | fck = prate / fck_div * dss.feat->dss_fck_multiplier; |
524 | } | ||
582 | 525 | ||
583 | r = dss_set_clock_div(&dss_cinfo); | 526 | r = dss_set_fck_rate(fck); |
584 | if (r) | 527 | if (r) |
585 | return r; | 528 | return r; |
586 | 529 | ||
@@ -706,25 +649,25 @@ static int dss_get_clocks(void) | |||
706 | 649 | ||
707 | dss.dss_clk = clk; | 650 | dss.dss_clk = clk; |
708 | 651 | ||
709 | if (dss.feat->clk_name) { | 652 | if (dss.feat->parent_clk_name) { |
710 | clk = clk_get(NULL, dss.feat->clk_name); | 653 | clk = clk_get(NULL, dss.feat->parent_clk_name); |
711 | if (IS_ERR(clk)) { | 654 | if (IS_ERR(clk)) { |
712 | DSSERR("Failed to get %s\n", dss.feat->clk_name); | 655 | DSSERR("Failed to get %s\n", dss.feat->parent_clk_name); |
713 | return PTR_ERR(clk); | 656 | return PTR_ERR(clk); |
714 | } | 657 | } |
715 | } else { | 658 | } else { |
716 | clk = NULL; | 659 | clk = NULL; |
717 | } | 660 | } |
718 | 661 | ||
719 | dss.dpll4_m4_ck = clk; | 662 | dss.parent_clk = clk; |
720 | 663 | ||
721 | return 0; | 664 | return 0; |
722 | } | 665 | } |
723 | 666 | ||
724 | static void dss_put_clocks(void) | 667 | static void dss_put_clocks(void) |
725 | { | 668 | { |
726 | if (dss.dpll4_m4_ck) | 669 | if (dss.parent_clk) |
727 | clk_put(dss.dpll4_m4_ck); | 670 | clk_put(dss.parent_clk); |
728 | } | 671 | } |
729 | 672 | ||
730 | static int dss_runtime_get(void) | 673 | static int dss_runtime_get(void) |
@@ -761,37 +704,41 @@ void dss_debug_dump_clocks(struct seq_file *s) | |||
761 | #endif | 704 | #endif |
762 | 705 | ||
763 | static const struct dss_features omap24xx_dss_feats __initconst = { | 706 | static const struct dss_features omap24xx_dss_feats __initconst = { |
764 | .fck_div_max = 16, | 707 | /* |
708 | * fck div max is really 16, but the divider range has gaps. The range | ||
709 | * from 1 to 6 has no gaps, so let's use that as a max. | ||
710 | */ | ||
711 | .fck_div_max = 6, | ||
765 | .dss_fck_multiplier = 2, | 712 | .dss_fck_multiplier = 2, |
766 | .clk_name = NULL, | 713 | .parent_clk_name = "core_ck", |
767 | .dpi_select_source = &dss_dpi_select_source_omap2_omap3, | 714 | .dpi_select_source = &dss_dpi_select_source_omap2_omap3, |
768 | }; | 715 | }; |
769 | 716 | ||
770 | static const struct dss_features omap34xx_dss_feats __initconst = { | 717 | static const struct dss_features omap34xx_dss_feats __initconst = { |
771 | .fck_div_max = 16, | 718 | .fck_div_max = 16, |
772 | .dss_fck_multiplier = 2, | 719 | .dss_fck_multiplier = 2, |
773 | .clk_name = "dpll4_m4_ck", | 720 | .parent_clk_name = "dpll4_ck", |
774 | .dpi_select_source = &dss_dpi_select_source_omap2_omap3, | 721 | .dpi_select_source = &dss_dpi_select_source_omap2_omap3, |
775 | }; | 722 | }; |
776 | 723 | ||
777 | static const struct dss_features omap3630_dss_feats __initconst = { | 724 | static const struct dss_features omap3630_dss_feats __initconst = { |
778 | .fck_div_max = 32, | 725 | .fck_div_max = 32, |
779 | .dss_fck_multiplier = 1, | 726 | .dss_fck_multiplier = 1, |
780 | .clk_name = "dpll4_m4_ck", | 727 | .parent_clk_name = "dpll4_ck", |
781 | .dpi_select_source = &dss_dpi_select_source_omap2_omap3, | 728 | .dpi_select_source = &dss_dpi_select_source_omap2_omap3, |
782 | }; | 729 | }; |
783 | 730 | ||
784 | static const struct dss_features omap44xx_dss_feats __initconst = { | 731 | static const struct dss_features omap44xx_dss_feats __initconst = { |
785 | .fck_div_max = 32, | 732 | .fck_div_max = 32, |
786 | .dss_fck_multiplier = 1, | 733 | .dss_fck_multiplier = 1, |
787 | .clk_name = "dpll_per_m5x2_ck", | 734 | .parent_clk_name = "dpll_per_x2_ck", |
788 | .dpi_select_source = &dss_dpi_select_source_omap4, | 735 | .dpi_select_source = &dss_dpi_select_source_omap4, |
789 | }; | 736 | }; |
790 | 737 | ||
791 | static const struct dss_features omap54xx_dss_feats __initconst = { | 738 | static const struct dss_features omap54xx_dss_feats __initconst = { |
792 | .fck_div_max = 64, | 739 | .fck_div_max = 64, |
793 | .dss_fck_multiplier = 1, | 740 | .dss_fck_multiplier = 1, |
794 | .clk_name = "dpll_per_h12x2_ck", | 741 | .parent_clk_name = "dpll_per_x2_ck", |
795 | .dpi_select_source = &dss_dpi_select_source_omap5, | 742 | .dpi_select_source = &dss_dpi_select_source_omap5, |
796 | }; | 743 | }; |
797 | 744 | ||
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index f538e867c0f8..057f24c8a332 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h | |||
@@ -100,14 +100,6 @@ enum dss_writeback_channel { | |||
100 | DSS_WB_LCD3_MGR = 7, | 100 | DSS_WB_LCD3_MGR = 7, |
101 | }; | 101 | }; |
102 | 102 | ||
103 | struct dss_clock_info { | ||
104 | /* rates that we get with dividers below */ | ||
105 | unsigned long fck; | ||
106 | |||
107 | /* dividers */ | ||
108 | u16 fck_div; | ||
109 | }; | ||
110 | |||
111 | struct dispc_clock_info { | 103 | struct dispc_clock_info { |
112 | /* rates that we get with dividers below */ | 104 | /* rates that we get with dividers below */ |
113 | unsigned long lck; | 105 | unsigned long lck; |
@@ -250,12 +242,11 @@ enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel); | |||
250 | void dss_set_venc_output(enum omap_dss_venc_type type); | 242 | void dss_set_venc_output(enum omap_dss_venc_type type); |
251 | void dss_set_dac_pwrdn_bgz(bool enable); | 243 | void dss_set_dac_pwrdn_bgz(bool enable); |
252 | 244 | ||
253 | unsigned long dss_get_dpll4_rate(void); | 245 | int dss_set_fck_rate(unsigned long rate); |
254 | int dss_calc_clock_rates(struct dss_clock_info *cinfo); | ||
255 | int dss_set_clock_div(struct dss_clock_info *cinfo); | ||
256 | 246 | ||
257 | typedef bool (*dss_div_calc_func)(int fckd, unsigned long fck, void *data); | 247 | typedef bool (*dss_div_calc_func)(unsigned long fck, void *data); |
258 | bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data); | 248 | bool dss_div_calc(unsigned long pck, unsigned long fck_min, |
249 | dss_div_calc_func func, void *data); | ||
259 | 250 | ||
260 | /* SDI */ | 251 | /* SDI */ |
261 | int sdi_init_platform_driver(void) __init; | 252 | int sdi_init_platform_driver(void) __init; |
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index f8fd6dbacabc..7f8969191dc6 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c | |||
@@ -613,6 +613,7 @@ static const enum dss_feat_id omap5_dss_feat_list[] = { | |||
613 | FEAT_DSI_PLL_SELFREQDCO, | 613 | FEAT_DSI_PLL_SELFREQDCO, |
614 | FEAT_DSI_PLL_REFSEL, | 614 | FEAT_DSI_PLL_REFSEL, |
615 | FEAT_DSI_PHY_DCC, | 615 | FEAT_DSI_PHY_DCC, |
616 | FEAT_MFLAG, | ||
616 | }; | 617 | }; |
617 | 618 | ||
618 | /* OMAP2 DSS Features */ | 619 | /* OMAP2 DSS Features */ |
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h index 10b0556e1352..e3ef3b714896 100644 --- a/drivers/video/omap2/dss/dss_features.h +++ b/drivers/video/omap2/dss/dss_features.h | |||
@@ -64,6 +64,7 @@ enum dss_feat_id { | |||
64 | FEAT_DSI_PLL_SELFREQDCO, | 64 | FEAT_DSI_PLL_SELFREQDCO, |
65 | FEAT_DSI_PLL_REFSEL, | 65 | FEAT_DSI_PLL_REFSEL, |
66 | FEAT_DSI_PHY_DCC, | 66 | FEAT_DSI_PHY_DCC, |
67 | FEAT_MFLAG, | ||
67 | }; | 68 | }; |
68 | 69 | ||
69 | /* DSS register field id */ | 70 | /* DSS register field id */ |
diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h index b0493768a5d7..e25681ff5a70 100644 --- a/drivers/video/omap2/dss/hdmi.h +++ b/drivers/video/omap2/dss/hdmi.h | |||
@@ -41,14 +41,14 @@ | |||
41 | #define HDMI_WP_VIDEO_SIZE 0x60 | 41 | #define HDMI_WP_VIDEO_SIZE 0x60 |
42 | #define HDMI_WP_VIDEO_TIMING_H 0x68 | 42 | #define HDMI_WP_VIDEO_TIMING_H 0x68 |
43 | #define HDMI_WP_VIDEO_TIMING_V 0x6C | 43 | #define HDMI_WP_VIDEO_TIMING_V 0x6C |
44 | #define HDMI_WP_WP_CLK 0x70 | 44 | #define HDMI_WP_CLK 0x70 |
45 | #define HDMI_WP_AUDIO_CFG 0x80 | 45 | #define HDMI_WP_AUDIO_CFG 0x80 |
46 | #define HDMI_WP_AUDIO_CFG2 0x84 | 46 | #define HDMI_WP_AUDIO_CFG2 0x84 |
47 | #define HDMI_WP_AUDIO_CTRL 0x88 | 47 | #define HDMI_WP_AUDIO_CTRL 0x88 |
48 | #define HDMI_WP_AUDIO_DATA 0x8C | 48 | #define HDMI_WP_AUDIO_DATA 0x8C |
49 | 49 | ||
50 | /* HDMI WP IRQ flags */ | 50 | /* HDMI WP IRQ flags */ |
51 | 51 | #define HDMI_IRQ_CORE (1 << 0) | |
52 | #define HDMI_IRQ_OCP_TIMEOUT (1 << 4) | 52 | #define HDMI_IRQ_OCP_TIMEOUT (1 << 4) |
53 | #define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW (1 << 8) | 53 | #define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW (1 << 8) |
54 | #define HDMI_IRQ_AUDIO_FIFO_OVERFLOW (1 << 9) | 54 | #define HDMI_IRQ_AUDIO_FIFO_OVERFLOW (1 << 9) |
@@ -378,15 +378,15 @@ static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx) | |||
378 | FLD_GET(hdmi_read_reg(base, idx), start, end) | 378 | FLD_GET(hdmi_read_reg(base, idx), start, end) |
379 | 379 | ||
380 | static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, | 380 | static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, |
381 | const u16 idx, int b2, int b1, u32 val) | 381 | const u32 idx, int b2, int b1, u32 val) |
382 | { | 382 | { |
383 | u32 t = 0; | 383 | u32 t = 0, v; |
384 | while (val != REG_GET(base_addr, idx, b2, b1)) { | 384 | while (val != (v = REG_GET(base_addr, idx, b2, b1))) { |
385 | udelay(1); | ||
386 | if (t++ > 10000) | 385 | if (t++ > 10000) |
387 | return !val; | 386 | return v; |
387 | udelay(1); | ||
388 | } | 388 | } |
389 | return val; | 389 | return v; |
390 | } | 390 | } |
391 | 391 | ||
392 | /* HDMI wrapper funcs */ | 392 | /* HDMI wrapper funcs */ |
diff --git a/drivers/video/omap2/dss/hdmi4.c b/drivers/video/omap2/dss/hdmi4.c index e14009614338..4a74538f9ea5 100644 --- a/drivers/video/omap2/dss/hdmi4.c +++ b/drivers/video/omap2/dss/hdmi4.c | |||
@@ -95,7 +95,8 @@ static int hdmi_init_regulator(void) | |||
95 | reg = devm_regulator_get(&hdmi.pdev->dev, "VDAC"); | 95 | reg = devm_regulator_get(&hdmi.pdev->dev, "VDAC"); |
96 | 96 | ||
97 | if (IS_ERR(reg)) { | 97 | if (IS_ERR(reg)) { |
98 | DSSERR("can't get VDDA_HDMI_DAC regulator\n"); | 98 | if (PTR_ERR(reg) != -EPROBE_DEFER) |
99 | DSSERR("can't get VDDA_HDMI_DAC regulator\n"); | ||
99 | return PTR_ERR(reg); | 100 | return PTR_ERR(reg); |
100 | } | 101 | } |
101 | 102 | ||
@@ -148,8 +149,6 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) | |||
148 | if (r) | 149 | if (r) |
149 | return r; | 150 | return r; |
150 | 151 | ||
151 | dss_mgr_disable(mgr); | ||
152 | |||
153 | p = &hdmi.cfg.timings; | 152 | p = &hdmi.cfg.timings; |
154 | 153 | ||
155 | DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); | 154 | DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); |
@@ -158,8 +157,6 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) | |||
158 | 157 | ||
159 | hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy); | 158 | hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy); |
160 | 159 | ||
161 | hdmi_wp_video_stop(&hdmi.wp); | ||
162 | |||
163 | /* config the PLL and PHY hdmi_set_pll_pwrfirst */ | 160 | /* config the PLL and PHY hdmi_set_pll_pwrfirst */ |
164 | r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp); | 161 | r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp); |
165 | if (r) { | 162 | if (r) { |
@@ -218,14 +215,12 @@ static void hdmi_power_off_full(struct omap_dss_device *dssdev) | |||
218 | static int hdmi_display_check_timing(struct omap_dss_device *dssdev, | 215 | static int hdmi_display_check_timing(struct omap_dss_device *dssdev, |
219 | struct omap_video_timings *timings) | 216 | struct omap_video_timings *timings) |
220 | { | 217 | { |
221 | struct hdmi_cm cm; | 218 | struct omap_dss_device *out = &hdmi.output; |
222 | 219 | ||
223 | cm = hdmi_get_code(timings); | 220 | if (!dispc_mgr_timings_ok(out->dispc_channel, timings)) |
224 | if (cm.code == -1) | ||
225 | return -EINVAL; | 221 | return -EINVAL; |
226 | 222 | ||
227 | return 0; | 223 | return 0; |
228 | |||
229 | } | 224 | } |
230 | 225 | ||
231 | static void hdmi_display_set_timing(struct omap_dss_device *dssdev, | 226 | static void hdmi_display_set_timing(struct omap_dss_device *dssdev, |
@@ -244,8 +239,17 @@ static void hdmi_display_set_timing(struct omap_dss_device *dssdev, | |||
244 | hdmi.cfg = *t; | 239 | hdmi.cfg = *t; |
245 | 240 | ||
246 | dispc_set_tv_pclk(t->timings.pixel_clock * 1000); | 241 | dispc_set_tv_pclk(t->timings.pixel_clock * 1000); |
242 | } else { | ||
243 | hdmi.cfg.timings = *timings; | ||
244 | hdmi.cfg.cm.code = 0; | ||
245 | hdmi.cfg.cm.mode = HDMI_DVI; | ||
246 | |||
247 | dispc_set_tv_pclk(timings->pixel_clock * 1000); | ||
247 | } | 248 | } |
248 | 249 | ||
250 | DSSDBG("using mode: %s, code %d\n", hdmi.cfg.cm.mode == HDMI_DVI ? | ||
251 | "DVI" : "HDMI", hdmi.cfg.cm.code); | ||
252 | |||
249 | mutex_unlock(&hdmi.lock); | 253 | mutex_unlock(&hdmi.lock); |
250 | } | 254 | } |
251 | 255 | ||
diff --git a/drivers/video/omap2/dss/hdmi4_core.c b/drivers/video/omap2/dss/hdmi4_core.c index 5dd5e5489b41..2eb04dcf807c 100644 --- a/drivers/video/omap2/dss/hdmi4_core.c +++ b/drivers/video/omap2/dss/hdmi4_core.c | |||
@@ -19,6 +19,8 @@ | |||
19 | * this program. If not, see <http://www.gnu.org/licenses/>. | 19 | * this program. If not, see <http://www.gnu.org/licenses/>. |
20 | */ | 20 | */ |
21 | 21 | ||
22 | #define DSS_SUBSYS_NAME "HDMICORE" | ||
23 | |||
22 | #include <linux/kernel.h> | 24 | #include <linux/kernel.h> |
23 | #include <linux/module.h> | 25 | #include <linux/module.h> |
24 | #include <linux/err.h> | 26 | #include <linux/err.h> |
@@ -125,12 +127,12 @@ static int hdmi_core_ddc_edid(struct hdmi_core_data *core, | |||
125 | 127 | ||
126 | /* HDMI_CORE_DDC_STATUS_BUS_LOW */ | 128 | /* HDMI_CORE_DDC_STATUS_BUS_LOW */ |
127 | if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { | 129 | if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { |
128 | pr_err("I2C Bus Low?\n"); | 130 | DSSERR("I2C Bus Low?\n"); |
129 | return -EIO; | 131 | return -EIO; |
130 | } | 132 | } |
131 | /* HDMI_CORE_DDC_STATUS_NO_ACK */ | 133 | /* HDMI_CORE_DDC_STATUS_NO_ACK */ |
132 | if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { | 134 | if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { |
133 | pr_err("I2C No Ack\n"); | 135 | DSSERR("I2C No Ack\n"); |
134 | return -EIO; | 136 | return -EIO; |
135 | } | 137 | } |
136 | 138 | ||
@@ -161,7 +163,7 @@ static int hdmi_core_ddc_edid(struct hdmi_core_data *core, | |||
161 | checksum += pedid[i]; | 163 | checksum += pedid[i]; |
162 | 164 | ||
163 | if (checksum != 0) { | 165 | if (checksum != 0) { |
164 | pr_err("E-EDID checksum failed!!\n"); | 166 | DSSERR("E-EDID checksum failed!!\n"); |
165 | return -EIO; | 167 | return -EIO; |
166 | } | 168 | } |
167 | 169 | ||
@@ -199,7 +201,7 @@ static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, | |||
199 | struct hdmi_core_infoframe_avi *avi_cfg, | 201 | struct hdmi_core_infoframe_avi *avi_cfg, |
200 | struct hdmi_core_packet_enable_repeat *repeat_cfg) | 202 | struct hdmi_core_packet_enable_repeat *repeat_cfg) |
201 | { | 203 | { |
202 | pr_debug("Enter hdmi_core_init\n"); | 204 | DSSDBG("Enter hdmi_core_init\n"); |
203 | 205 | ||
204 | /* video core */ | 206 | /* video core */ |
205 | video_cfg->ip_bus_width = HDMI_INPUT_8BIT; | 207 | video_cfg->ip_bus_width = HDMI_INPUT_8BIT; |
@@ -241,19 +243,19 @@ static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, | |||
241 | 243 | ||
242 | static void hdmi_core_powerdown_disable(struct hdmi_core_data *core) | 244 | static void hdmi_core_powerdown_disable(struct hdmi_core_data *core) |
243 | { | 245 | { |
244 | pr_debug("Enter hdmi_core_powerdown_disable\n"); | 246 | DSSDBG("Enter hdmi_core_powerdown_disable\n"); |
245 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0); | 247 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0); |
246 | } | 248 | } |
247 | 249 | ||
248 | static void hdmi_core_swreset_release(struct hdmi_core_data *core) | 250 | static void hdmi_core_swreset_release(struct hdmi_core_data *core) |
249 | { | 251 | { |
250 | pr_debug("Enter hdmi_core_swreset_release\n"); | 252 | DSSDBG("Enter hdmi_core_swreset_release\n"); |
251 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0); | 253 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0); |
252 | } | 254 | } |
253 | 255 | ||
254 | static void hdmi_core_swreset_assert(struct hdmi_core_data *core) | 256 | static void hdmi_core_swreset_assert(struct hdmi_core_data *core) |
255 | { | 257 | { |
256 | pr_debug("Enter hdmi_core_swreset_assert\n"); | 258 | DSSDBG("Enter hdmi_core_swreset_assert\n"); |
257 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0); | 259 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0); |
258 | } | 260 | } |
259 | 261 | ||
@@ -1004,7 +1006,7 @@ int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core) | |||
1004 | struct resource *res; | 1006 | struct resource *res; |
1005 | struct resource temp_res; | 1007 | struct resource temp_res; |
1006 | 1008 | ||
1007 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_core"); | 1009 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); |
1008 | if (!res) { | 1010 | if (!res) { |
1009 | DSSDBG("can't get CORE mem resource by name\n"); | 1011 | DSSDBG("can't get CORE mem resource by name\n"); |
1010 | /* | 1012 | /* |
diff --git a/drivers/video/omap2/dss/hdmi_common.c b/drivers/video/omap2/dss/hdmi_common.c index 5586aaad9d63..0614922902dd 100644 --- a/drivers/video/omap2/dss/hdmi_common.c +++ b/drivers/video/omap2/dss/hdmi_common.c | |||
@@ -13,6 +13,8 @@ | |||
13 | * map it to corresponding CEA or VESA index. | 13 | * map it to corresponding CEA or VESA index. |
14 | */ | 14 | */ |
15 | 15 | ||
16 | #define DSS_SUBSYS_NAME "HDMI" | ||
17 | |||
16 | #include <linux/kernel.h> | 18 | #include <linux/kernel.h> |
17 | #include <linux/err.h> | 19 | #include <linux/err.h> |
18 | #include <video/omapdss.h> | 20 | #include <video/omapdss.h> |
diff --git a/drivers/video/omap2/dss/hdmi_phy.c b/drivers/video/omap2/dss/hdmi_phy.c index 45acb997ac00..dd376ce8da01 100644 --- a/drivers/video/omap2/dss/hdmi_phy.c +++ b/drivers/video/omap2/dss/hdmi_phy.c | |||
@@ -124,7 +124,7 @@ int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy) | |||
124 | struct resource *res; | 124 | struct resource *res; |
125 | struct resource temp_res; | 125 | struct resource temp_res; |
126 | 126 | ||
127 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_txphy"); | 127 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); |
128 | if (!res) { | 128 | if (!res) { |
129 | DSSDBG("can't get PHY mem resource by name\n"); | 129 | DSSDBG("can't get PHY mem resource by name\n"); |
130 | /* | 130 | /* |
diff --git a/drivers/video/omap2/dss/hdmi_pll.c b/drivers/video/omap2/dss/hdmi_pll.c index d3e6e78c0082..5fc71215c303 100644 --- a/drivers/video/omap2/dss/hdmi_pll.c +++ b/drivers/video/omap2/dss/hdmi_pll.c | |||
@@ -8,6 +8,8 @@ | |||
8 | * the Free Software Foundation. | 8 | * the Free Software Foundation. |
9 | */ | 9 | */ |
10 | 10 | ||
11 | #define DSS_SUBSYS_NAME "HDMIPLL" | ||
12 | |||
11 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
12 | #include <linux/module.h> | 14 | #include <linux/module.h> |
13 | #include <linux/err.h> | 15 | #include <linux/err.h> |
@@ -127,24 +129,24 @@ static int hdmi_pll_config(struct hdmi_pll_data *pll) | |||
127 | /* wait for bit change */ | 129 | /* wait for bit change */ |
128 | if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_GO, | 130 | if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_GO, |
129 | 0, 0, 1) != 1) { | 131 | 0, 0, 1) != 1) { |
130 | pr_err("PLL GO bit not set\n"); | 132 | DSSERR("PLL GO bit not set\n"); |
131 | return -ETIMEDOUT; | 133 | return -ETIMEDOUT; |
132 | } | 134 | } |
133 | 135 | ||
134 | /* Wait till the lock bit is set in PLL status */ | 136 | /* Wait till the lock bit is set in PLL status */ |
135 | if (hdmi_wait_for_bit_change(pll->base, | 137 | if (hdmi_wait_for_bit_change(pll->base, |
136 | PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) { | 138 | PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) { |
137 | pr_err("cannot lock PLL\n"); | 139 | DSSERR("cannot lock PLL\n"); |
138 | pr_err("CFG1 0x%x\n", | 140 | DSSERR("CFG1 0x%x\n", |
139 | hdmi_read_reg(pll->base, PLLCTRL_CFG1)); | 141 | hdmi_read_reg(pll->base, PLLCTRL_CFG1)); |
140 | pr_err("CFG2 0x%x\n", | 142 | DSSERR("CFG2 0x%x\n", |
141 | hdmi_read_reg(pll->base, PLLCTRL_CFG2)); | 143 | hdmi_read_reg(pll->base, PLLCTRL_CFG2)); |
142 | pr_err("CFG4 0x%x\n", | 144 | DSSERR("CFG4 0x%x\n", |
143 | hdmi_read_reg(pll->base, PLLCTRL_CFG4)); | 145 | hdmi_read_reg(pll->base, PLLCTRL_CFG4)); |
144 | return -ETIMEDOUT; | 146 | return -ETIMEDOUT; |
145 | } | 147 | } |
146 | 148 | ||
147 | pr_debug("PLL locked!\n"); | 149 | DSSDBG("PLL locked!\n"); |
148 | 150 | ||
149 | return 0; | 151 | return 0; |
150 | } | 152 | } |
@@ -157,7 +159,7 @@ static int hdmi_pll_reset(struct hdmi_pll_data *pll) | |||
157 | /* READ 0x0 reset is in progress */ | 159 | /* READ 0x0 reset is in progress */ |
158 | if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_STATUS, 0, 0, 1) | 160 | if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_STATUS, 0, 0, 1) |
159 | != 1) { | 161 | != 1) { |
160 | pr_err("Failed to sysreset PLL\n"); | 162 | DSSERR("Failed to sysreset PLL\n"); |
161 | return -ETIMEDOUT; | 163 | return -ETIMEDOUT; |
162 | } | 164 | } |
163 | 165 | ||
@@ -200,7 +202,7 @@ int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll) | |||
200 | struct resource *res; | 202 | struct resource *res; |
201 | struct resource temp_res; | 203 | struct resource temp_res; |
202 | 204 | ||
203 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_pllctrl"); | 205 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll"); |
204 | if (!res) { | 206 | if (!res) { |
205 | DSSDBG("can't get PLL mem resource by name\n"); | 207 | DSSDBG("can't get PLL mem resource by name\n"); |
206 | /* | 208 | /* |
diff --git a/drivers/video/omap2/dss/hdmi_wp.c b/drivers/video/omap2/dss/hdmi_wp.c index 8151d8969a6e..cd620c6e43a0 100644 --- a/drivers/video/omap2/dss/hdmi_wp.c +++ b/drivers/video/omap2/dss/hdmi_wp.c | |||
@@ -8,6 +8,8 @@ | |||
8 | * the Free Software Foundation. | 8 | * the Free Software Foundation. |
9 | */ | 9 | */ |
10 | 10 | ||
11 | #define DSS_SUBSYS_NAME "HDMIWP" | ||
12 | |||
11 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
12 | #include <linux/err.h> | 14 | #include <linux/err.h> |
13 | #include <linux/io.h> | 15 | #include <linux/io.h> |
@@ -34,7 +36,7 @@ void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) | |||
34 | DUMPREG(HDMI_WP_VIDEO_SIZE); | 36 | DUMPREG(HDMI_WP_VIDEO_SIZE); |
35 | DUMPREG(HDMI_WP_VIDEO_TIMING_H); | 37 | DUMPREG(HDMI_WP_VIDEO_TIMING_H); |
36 | DUMPREG(HDMI_WP_VIDEO_TIMING_V); | 38 | DUMPREG(HDMI_WP_VIDEO_TIMING_V); |
37 | DUMPREG(HDMI_WP_WP_CLK); | 39 | DUMPREG(HDMI_WP_CLK); |
38 | DUMPREG(HDMI_WP_AUDIO_CFG); | 40 | DUMPREG(HDMI_WP_AUDIO_CFG); |
39 | DUMPREG(HDMI_WP_AUDIO_CFG2); | 41 | DUMPREG(HDMI_WP_AUDIO_CFG2); |
40 | DUMPREG(HDMI_WP_AUDIO_CTRL); | 42 | DUMPREG(HDMI_WP_AUDIO_CTRL); |
@@ -76,7 +78,7 @@ int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val) | |||
76 | /* Status of the power control of HDMI PHY */ | 78 | /* Status of the power control of HDMI PHY */ |
77 | if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) | 79 | if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) |
78 | != val) { | 80 | != val) { |
79 | pr_err("Failed to set PHY power mode to %d\n", val); | 81 | DSSERR("Failed to set PHY power mode to %d\n", val); |
80 | return -ETIMEDOUT; | 82 | return -ETIMEDOUT; |
81 | } | 83 | } |
82 | 84 | ||
@@ -92,7 +94,7 @@ int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val) | |||
92 | /* wait till PHY_PWR_STATUS is set */ | 94 | /* wait till PHY_PWR_STATUS is set */ |
93 | if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val) | 95 | if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val) |
94 | != val) { | 96 | != val) { |
95 | pr_err("Failed to set PLL_PWR_STATUS\n"); | 97 | DSSERR("Failed to set PLL_PWR_STATUS\n"); |
96 | return -ETIMEDOUT; | 98 | return -ETIMEDOUT; |
97 | } | 99 | } |
98 | 100 | ||
@@ -129,7 +131,7 @@ void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, | |||
129 | { | 131 | { |
130 | u32 r; | 132 | u32 r; |
131 | bool vsync_pol, hsync_pol; | 133 | bool vsync_pol, hsync_pol; |
132 | pr_debug("Enter hdmi_wp_video_config_interface\n"); | 134 | DSSDBG("Enter hdmi_wp_video_config_interface\n"); |
133 | 135 | ||
134 | vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; | 136 | vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; |
135 | hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; | 137 | hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; |
@@ -148,7 +150,7 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, | |||
148 | u32 timing_h = 0; | 150 | u32 timing_h = 0; |
149 | u32 timing_v = 0; | 151 | u32 timing_v = 0; |
150 | 152 | ||
151 | pr_debug("Enter hdmi_wp_video_config_timing\n"); | 153 | DSSDBG("Enter hdmi_wp_video_config_timing\n"); |
152 | 154 | ||
153 | timing_h |= FLD_VAL(timings->hbp, 31, 20); | 155 | timing_h |= FLD_VAL(timings->hbp, 31, 20); |
154 | timing_h |= FLD_VAL(timings->hfp, 19, 8); | 156 | timing_h |= FLD_VAL(timings->hfp, 19, 8); |
@@ -164,7 +166,7 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, | |||
164 | void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, | 166 | void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, |
165 | struct omap_video_timings *timings, struct hdmi_config *param) | 167 | struct omap_video_timings *timings, struct hdmi_config *param) |
166 | { | 168 | { |
167 | pr_debug("Enter hdmi_wp_video_init_format\n"); | 169 | DSSDBG("Enter hdmi_wp_video_init_format\n"); |
168 | 170 | ||
169 | video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444; | 171 | video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444; |
170 | video_fmt->y_res = param->timings.y_res; | 172 | video_fmt->y_res = param->timings.y_res; |
@@ -241,7 +243,7 @@ int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp) | |||
241 | struct resource *res; | 243 | struct resource *res; |
242 | struct resource temp_res; | 244 | struct resource temp_res; |
243 | 245 | ||
244 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_wp"); | 246 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wp"); |
245 | if (!res) { | 247 | if (!res) { |
246 | DSSDBG("can't get WP mem resource by name\n"); | 248 | DSSDBG("can't get WP mem resource by name\n"); |
247 | /* | 249 | /* |
diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c index eccde322c28a..2f7cee985cdd 100644 --- a/drivers/video/omap2/dss/overlay.c +++ b/drivers/video/omap2/dss/overlay.c | |||
@@ -113,11 +113,6 @@ void dss_uninit_overlays(struct platform_device *pdev) | |||
113 | int dss_ovl_simple_check(struct omap_overlay *ovl, | 113 | int dss_ovl_simple_check(struct omap_overlay *ovl, |
114 | const struct omap_overlay_info *info) | 114 | const struct omap_overlay_info *info) |
115 | { | 115 | { |
116 | if (info->paddr == 0) { | ||
117 | DSSERR("check_overlay: paddr cannot be 0\n"); | ||
118 | return -EINVAL; | ||
119 | } | ||
120 | |||
121 | if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) { | 116 | if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) { |
122 | if (info->out_width != 0 && info->width != info->out_width) { | 117 | if (info->out_width != 0 && info->width != info->out_width) { |
123 | DSSERR("check_overlay: overlay %d doesn't support " | 118 | DSSERR("check_overlay: overlay %d doesn't support " |
diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c index ccc569ae7cca..efb9ee9e3c96 100644 --- a/drivers/video/omap2/dss/sdi.c +++ b/drivers/video/omap2/dss/sdi.c | |||
@@ -46,7 +46,7 @@ static struct { | |||
46 | struct sdi_clk_calc_ctx { | 46 | struct sdi_clk_calc_ctx { |
47 | unsigned long pck_min, pck_max; | 47 | unsigned long pck_min, pck_max; |
48 | 48 | ||
49 | struct dss_clock_info dss_cinfo; | 49 | unsigned long long fck; |
50 | struct dispc_clock_info dispc_cinfo; | 50 | struct dispc_clock_info dispc_cinfo; |
51 | }; | 51 | }; |
52 | 52 | ||
@@ -63,19 +63,18 @@ static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck, | |||
63 | return true; | 63 | return true; |
64 | } | 64 | } |
65 | 65 | ||
66 | static bool dpi_calc_dss_cb(int fckd, unsigned long fck, void *data) | 66 | static bool dpi_calc_dss_cb(unsigned long fck, void *data) |
67 | { | 67 | { |
68 | struct sdi_clk_calc_ctx *ctx = data; | 68 | struct sdi_clk_calc_ctx *ctx = data; |
69 | 69 | ||
70 | ctx->dss_cinfo.fck = fck; | 70 | ctx->fck = fck; |
71 | ctx->dss_cinfo.fck_div = fckd; | ||
72 | 71 | ||
73 | return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max, | 72 | return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max, |
74 | dpi_calc_dispc_cb, ctx); | 73 | dpi_calc_dispc_cb, ctx); |
75 | } | 74 | } |
76 | 75 | ||
77 | static int sdi_calc_clock_div(unsigned long pclk, | 76 | static int sdi_calc_clock_div(unsigned long pclk, |
78 | struct dss_clock_info *dss_cinfo, | 77 | unsigned long *fck, |
79 | struct dispc_clock_info *dispc_cinfo) | 78 | struct dispc_clock_info *dispc_cinfo) |
80 | { | 79 | { |
81 | int i; | 80 | int i; |
@@ -98,9 +97,9 @@ static int sdi_calc_clock_div(unsigned long pclk, | |||
98 | ctx.pck_min = 0; | 97 | ctx.pck_min = 0; |
99 | ctx.pck_max = pclk + 1000 * i * i * i; | 98 | ctx.pck_max = pclk + 1000 * i * i * i; |
100 | 99 | ||
101 | ok = dss_div_calc(ctx.pck_min, dpi_calc_dss_cb, &ctx); | 100 | ok = dss_div_calc(pclk, ctx.pck_min, dpi_calc_dss_cb, &ctx); |
102 | if (ok) { | 101 | if (ok) { |
103 | *dss_cinfo = ctx.dss_cinfo; | 102 | *fck = ctx.fck; |
104 | *dispc_cinfo = ctx.dispc_cinfo; | 103 | *dispc_cinfo = ctx.dispc_cinfo; |
105 | return 0; | 104 | return 0; |
106 | } | 105 | } |
@@ -128,7 +127,7 @@ static int sdi_display_enable(struct omap_dss_device *dssdev) | |||
128 | { | 127 | { |
129 | struct omap_dss_device *out = &sdi.output; | 128 | struct omap_dss_device *out = &sdi.output; |
130 | struct omap_video_timings *t = &sdi.timings; | 129 | struct omap_video_timings *t = &sdi.timings; |
131 | struct dss_clock_info dss_cinfo; | 130 | unsigned long fck; |
132 | struct dispc_clock_info dispc_cinfo; | 131 | struct dispc_clock_info dispc_cinfo; |
133 | unsigned long pck; | 132 | unsigned long pck; |
134 | int r; | 133 | int r; |
@@ -150,13 +149,13 @@ static int sdi_display_enable(struct omap_dss_device *dssdev) | |||
150 | t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; | 149 | t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; |
151 | t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; | 150 | t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; |
152 | 151 | ||
153 | r = sdi_calc_clock_div(t->pixel_clock * 1000, &dss_cinfo, &dispc_cinfo); | 152 | r = sdi_calc_clock_div(t->pixel_clock * 1000, &fck, &dispc_cinfo); |
154 | if (r) | 153 | if (r) |
155 | goto err_calc_clock_div; | 154 | goto err_calc_clock_div; |
156 | 155 | ||
157 | sdi.mgr_config.clock_info = dispc_cinfo; | 156 | sdi.mgr_config.clock_info = dispc_cinfo; |
158 | 157 | ||
159 | pck = dss_cinfo.fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div / 1000; | 158 | pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div / 1000; |
160 | 159 | ||
161 | if (pck != t->pixel_clock) { | 160 | if (pck != t->pixel_clock) { |
162 | DSSWARN("Could not find exact pixel clock. Requested %d kHz, " | 161 | DSSWARN("Could not find exact pixel clock. Requested %d kHz, " |
@@ -169,7 +168,7 @@ static int sdi_display_enable(struct omap_dss_device *dssdev) | |||
169 | 168 | ||
170 | dss_mgr_set_timings(out->manager, t); | 169 | dss_mgr_set_timings(out->manager, t); |
171 | 170 | ||
172 | r = dss_set_clock_div(&dss_cinfo); | 171 | r = dss_set_fck_rate(fck); |
173 | if (r) | 172 | if (r) |
174 | goto err_set_dss_clock_div; | 173 | goto err_set_dss_clock_div; |
175 | 174 | ||
@@ -265,7 +264,8 @@ static int sdi_init_regulator(void) | |||
265 | 264 | ||
266 | vdds_sdi = devm_regulator_get(&sdi.pdev->dev, "vdds_sdi"); | 265 | vdds_sdi = devm_regulator_get(&sdi.pdev->dev, "vdds_sdi"); |
267 | if (IS_ERR(vdds_sdi)) { | 266 | if (IS_ERR(vdds_sdi)) { |
268 | DSSERR("can't get VDDS_SDI regulator\n"); | 267 | if (PTR_ERR(vdds_sdi) != -EPROBE_DEFER) |
268 | DSSERR("can't get VDDS_SDI regulator\n"); | ||
269 | return PTR_ERR(vdds_sdi); | 269 | return PTR_ERR(vdds_sdi); |
270 | } | 270 | } |
271 | 271 | ||
diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c index 5f88ac47b7fa..2cd7f7e42105 100644 --- a/drivers/video/omap2/dss/venc.c +++ b/drivers/video/omap2/dss/venc.c | |||
@@ -639,7 +639,8 @@ static int venc_init_regulator(void) | |||
639 | vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac"); | 639 | vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac"); |
640 | 640 | ||
641 | if (IS_ERR(vdda_dac)) { | 641 | if (IS_ERR(vdda_dac)) { |
642 | DSSERR("can't get VDDA_DAC regulator\n"); | 642 | if (PTR_ERR(vdda_dac) != -EPROBE_DEFER) |
643 | DSSERR("can't get VDDA_DAC regulator\n"); | ||
643 | return PTR_ERR(vdda_dac); | 644 | return PTR_ERR(vdda_dac); |
644 | } | 645 | } |
645 | 646 | ||
diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c index 27d6905683f3..fcb9e932d00c 100644 --- a/drivers/video/omap2/omapfb/omapfb-main.c +++ b/drivers/video/omap2/omapfb/omapfb-main.c | |||
@@ -1833,6 +1833,16 @@ static void omapfb_free_resources(struct omapfb2_device *fbdev) | |||
1833 | if (fbdev == NULL) | 1833 | if (fbdev == NULL) |
1834 | return; | 1834 | return; |
1835 | 1835 | ||
1836 | for (i = 0; i < fbdev->num_fbs; i++) { | ||
1837 | struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]); | ||
1838 | int j; | ||
1839 | |||
1840 | for (j = 0; j < ofbi->num_overlays; j++) { | ||
1841 | struct omap_overlay *ovl = ofbi->overlays[j]; | ||
1842 | ovl->disable(ovl); | ||
1843 | } | ||
1844 | } | ||
1845 | |||
1836 | for (i = 0; i < fbdev->num_fbs; i++) | 1846 | for (i = 0; i < fbdev->num_fbs; i++) |
1837 | unregister_framebuffer(fbdev->fbs[i]); | 1847 | unregister_framebuffer(fbdev->fbs[i]); |
1838 | 1848 | ||
@@ -2557,6 +2567,15 @@ static int omapfb_probe(struct platform_device *pdev) | |||
2557 | goto cleanup; | 2567 | goto cleanup; |
2558 | } | 2568 | } |
2559 | 2569 | ||
2570 | if (def_display) { | ||
2571 | u16 w, h; | ||
2572 | |||
2573 | def_display->driver->get_resolution(def_display, &w, &h); | ||
2574 | |||
2575 | dev_info(fbdev->dev, "using display '%s' mode %dx%d\n", | ||
2576 | def_display->name, w, h); | ||
2577 | } | ||
2578 | |||
2560 | return 0; | 2579 | return 0; |
2561 | 2580 | ||
2562 | cleanup: | 2581 | cleanup: |
diff --git a/drivers/video/riva/fbdev.c b/drivers/video/riva/fbdev.c index a5514acd2ac6..8a8d7f060784 100644 --- a/drivers/video/riva/fbdev.c +++ b/drivers/video/riva/fbdev.c | |||
@@ -2128,7 +2128,6 @@ static void rivafb_remove(struct pci_dev *pd) | |||
2128 | pci_release_regions(pd); | 2128 | pci_release_regions(pd); |
2129 | kfree(info->pixmap.addr); | 2129 | kfree(info->pixmap.addr); |
2130 | framebuffer_release(info); | 2130 | framebuffer_release(info); |
2131 | pci_set_drvdata(pd, NULL); | ||
2132 | NVTRACE_LEAVE(); | 2131 | NVTRACE_LEAVE(); |
2133 | } | 2132 | } |
2134 | 2133 | ||
diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index 968b2997175a..9a3f8f1c6aab 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c | |||
@@ -1180,7 +1180,7 @@ static int s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |||
1180 | 1180 | ||
1181 | vga_res.flags = IORESOURCE_IO; | 1181 | vga_res.flags = IORESOURCE_IO; |
1182 | 1182 | ||
1183 | pcibios_bus_to_resource(dev, &vga_res, &bus_reg); | 1183 | pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg); |
1184 | 1184 | ||
1185 | par->state.vgabase = (void __iomem *) vga_res.start; | 1185 | par->state.vgabase = (void __iomem *) vga_res.start; |
1186 | 1186 | ||
diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c index ab85ad6c25ec..2bcc84ac18c7 100644 --- a/drivers/video/sh_mobile_lcdcfb.c +++ b/drivers/video/sh_mobile_lcdcfb.c | |||
@@ -1227,7 +1227,7 @@ static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv) | |||
1227 | /* Free the MERAM cache. */ | 1227 | /* Free the MERAM cache. */ |
1228 | if (ch->cache) { | 1228 | if (ch->cache) { |
1229 | sh_mobile_meram_cache_free(priv->meram_dev, ch->cache); | 1229 | sh_mobile_meram_cache_free(priv->meram_dev, ch->cache); |
1230 | ch->cache = 0; | 1230 | ch->cache = NULL; |
1231 | } | 1231 | } |
1232 | 1232 | ||
1233 | } | 1233 | } |
diff --git a/drivers/video/tgafb.c b/drivers/video/tgafb.c index f28674fea909..07c7df9ee77b 100644 --- a/drivers/video/tgafb.c +++ b/drivers/video/tgafb.c | |||
@@ -32,12 +32,6 @@ | |||
32 | 32 | ||
33 | #include <video/tgafb.h> | 33 | #include <video/tgafb.h> |
34 | 34 | ||
35 | #ifdef CONFIG_PCI | ||
36 | #define TGA_BUS_PCI(dev) (dev->bus == &pci_bus_type) | ||
37 | #else | ||
38 | #define TGA_BUS_PCI(dev) 0 | ||
39 | #endif | ||
40 | |||
41 | #ifdef CONFIG_TC | 35 | #ifdef CONFIG_TC |
42 | #define TGA_BUS_TC(dev) (dev->bus == &tc_bus_type) | 36 | #define TGA_BUS_TC(dev) (dev->bus == &tc_bus_type) |
43 | #else | 37 | #else |
@@ -236,7 +230,7 @@ tgafb_set_par(struct fb_info *info) | |||
236 | }; | 230 | }; |
237 | 231 | ||
238 | struct tga_par *par = (struct tga_par *) info->par; | 232 | struct tga_par *par = (struct tga_par *) info->par; |
239 | int tga_bus_pci = TGA_BUS_PCI(par->dev); | 233 | int tga_bus_pci = dev_is_pci(par->dev); |
240 | int tga_bus_tc = TGA_BUS_TC(par->dev); | 234 | int tga_bus_tc = TGA_BUS_TC(par->dev); |
241 | u32 htimings, vtimings, pll_freq; | 235 | u32 htimings, vtimings, pll_freq; |
242 | u8 tga_type; | 236 | u8 tga_type; |
@@ -519,7 +513,7 @@ tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, | |||
519 | unsigned transp, struct fb_info *info) | 513 | unsigned transp, struct fb_info *info) |
520 | { | 514 | { |
521 | struct tga_par *par = (struct tga_par *) info->par; | 515 | struct tga_par *par = (struct tga_par *) info->par; |
522 | int tga_bus_pci = TGA_BUS_PCI(par->dev); | 516 | int tga_bus_pci = dev_is_pci(par->dev); |
523 | int tga_bus_tc = TGA_BUS_TC(par->dev); | 517 | int tga_bus_tc = TGA_BUS_TC(par->dev); |
524 | 518 | ||
525 | if (regno > 255) | 519 | if (regno > 255) |
@@ -1472,7 +1466,7 @@ static void | |||
1472 | tgafb_init_fix(struct fb_info *info) | 1466 | tgafb_init_fix(struct fb_info *info) |
1473 | { | 1467 | { |
1474 | struct tga_par *par = (struct tga_par *)info->par; | 1468 | struct tga_par *par = (struct tga_par *)info->par; |
1475 | int tga_bus_pci = TGA_BUS_PCI(par->dev); | 1469 | int tga_bus_pci = dev_is_pci(par->dev); |
1476 | int tga_bus_tc = TGA_BUS_TC(par->dev); | 1470 | int tga_bus_tc = TGA_BUS_TC(par->dev); |
1477 | u8 tga_type = par->tga_type; | 1471 | u8 tga_type = par->tga_type; |
1478 | const char *tga_type_name = NULL; | 1472 | const char *tga_type_name = NULL; |
@@ -1496,10 +1490,9 @@ tgafb_init_fix(struct fb_info *info) | |||
1496 | if (tga_bus_tc) | 1490 | if (tga_bus_tc) |
1497 | tga_type_name = "Digital ZLX-E3"; | 1491 | tga_type_name = "Digital ZLX-E3"; |
1498 | break; | 1492 | break; |
1499 | default: | ||
1500 | tga_type_name = "Unknown"; | ||
1501 | break; | ||
1502 | } | 1493 | } |
1494 | if (!tga_type_name) | ||
1495 | tga_type_name = "Unknown"; | ||
1503 | 1496 | ||
1504 | strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id)); | 1497 | strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id)); |
1505 | 1498 | ||
@@ -1560,7 +1553,7 @@ static int tgafb_register(struct device *dev) | |||
1560 | const struct fb_videomode *modedb_tga = NULL; | 1553 | const struct fb_videomode *modedb_tga = NULL; |
1561 | resource_size_t bar0_start = 0, bar0_len = 0; | 1554 | resource_size_t bar0_start = 0, bar0_len = 0; |
1562 | const char *mode_option_tga = NULL; | 1555 | const char *mode_option_tga = NULL; |
1563 | int tga_bus_pci = TGA_BUS_PCI(dev); | 1556 | int tga_bus_pci = dev_is_pci(dev); |
1564 | int tga_bus_tc = TGA_BUS_TC(dev); | 1557 | int tga_bus_tc = TGA_BUS_TC(dev); |
1565 | unsigned int modedbsize_tga = 0; | 1558 | unsigned int modedbsize_tga = 0; |
1566 | void __iomem *mem_base; | 1559 | void __iomem *mem_base; |
@@ -1690,7 +1683,7 @@ static int tgafb_register(struct device *dev) | |||
1690 | static void tgafb_unregister(struct device *dev) | 1683 | static void tgafb_unregister(struct device *dev) |
1691 | { | 1684 | { |
1692 | resource_size_t bar0_start = 0, bar0_len = 0; | 1685 | resource_size_t bar0_start = 0, bar0_len = 0; |
1693 | int tga_bus_pci = TGA_BUS_PCI(dev); | 1686 | int tga_bus_pci = dev_is_pci(dev); |
1694 | int tga_bus_tc = TGA_BUS_TC(dev); | 1687 | int tga_bus_tc = TGA_BUS_TC(dev); |
1695 | struct fb_info *info = NULL; | 1688 | struct fb_info *info = NULL; |
1696 | struct tga_par *par; | 1689 | struct tga_par *par; |
diff --git a/drivers/video/udlfb.c b/drivers/video/udlfb.c index 025f14e30eed..77b890e4d296 100644 --- a/drivers/video/udlfb.c +++ b/drivers/video/udlfb.c | |||
@@ -1624,7 +1624,7 @@ static int dlfb_usb_probe(struct usb_interface *interface, | |||
1624 | } | 1624 | } |
1625 | 1625 | ||
1626 | if (pixel_limit) { | 1626 | if (pixel_limit) { |
1627 | pr_warn("DL chip limit of %d overriden" | 1627 | pr_warn("DL chip limit of %d overridden" |
1628 | " by module param to %d\n", | 1628 | " by module param to %d\n", |
1629 | dev->sku_pixel_limit, pixel_limit); | 1629 | dev->sku_pixel_limit, pixel_limit); |
1630 | dev->sku_pixel_limit = pixel_limit; | 1630 | dev->sku_pixel_limit = pixel_limit; |
diff --git a/drivers/video/valkyriefb.c b/drivers/video/valkyriefb.c index e287ebc47817..97cb9bd1d1dd 100644 --- a/drivers/video/valkyriefb.c +++ b/drivers/video/valkyriefb.c | |||
@@ -56,7 +56,6 @@ | |||
56 | #include <linux/cuda.h> | 56 | #include <linux/cuda.h> |
57 | #include <asm/io.h> | 57 | #include <asm/io.h> |
58 | #ifdef CONFIG_MAC | 58 | #ifdef CONFIG_MAC |
59 | #include <asm/bootinfo.h> | ||
60 | #include <asm/macintosh.h> | 59 | #include <asm/macintosh.h> |
61 | #else | 60 | #else |
62 | #include <asm/prom.h> | 61 | #include <asm/prom.h> |
diff --git a/drivers/video/vermilion/vermilion.c b/drivers/video/vermilion/vermilion.c index 09a136633f35..048a66640b03 100644 --- a/drivers/video/vermilion/vermilion.c +++ b/drivers/video/vermilion/vermilion.c | |||
@@ -383,7 +383,6 @@ static void vmlfb_disable_mmio(struct vml_par *par) | |||
383 | static void vmlfb_release_devices(struct vml_par *par) | 383 | static void vmlfb_release_devices(struct vml_par *par) |
384 | { | 384 | { |
385 | if (atomic_dec_and_test(&par->refcount)) { | 385 | if (atomic_dec_and_test(&par->refcount)) { |
386 | pci_set_drvdata(par->vdc, NULL); | ||
387 | pci_disable_device(par->gpu); | 386 | pci_disable_device(par->gpu); |
388 | pci_disable_device(par->vdc); | 387 | pci_disable_device(par->vdc); |
389 | } | 388 | } |
diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c index 8bc6e0958a09..5c7cbc6c6236 100644 --- a/drivers/video/vt8623fb.c +++ b/drivers/video/vt8623fb.c | |||
@@ -729,7 +729,7 @@ static int vt8623_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |||
729 | 729 | ||
730 | vga_res.flags = IORESOURCE_IO; | 730 | vga_res.flags = IORESOURCE_IO; |
731 | 731 | ||
732 | pcibios_bus_to_resource(dev, &vga_res, &bus_reg); | 732 | pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg); |
733 | 733 | ||
734 | par->state.vgabase = (void __iomem *) vga_res.start; | 734 | par->state.vgabase = (void __iomem *) vga_res.start; |
735 | 735 | ||