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-rw-r--r--drivers/video/Kconfig2
-rw-r--r--drivers/video/amba-clcd.c4
-rw-r--r--drivers/video/aty/radeon_accel.c291
-rw-r--r--drivers/video/aty/radeon_backlight.c2
-rw-r--r--drivers/video/aty/radeon_base.c22
-rw-r--r--drivers/video/aty/radeon_pm.c6
-rw-r--r--drivers/video/aty/radeonfb.h38
-rw-r--r--drivers/video/console/fbcon.c15
-rw-r--r--drivers/video/imxfb.c468
-rw-r--r--drivers/video/imxfb.h73
-rw-r--r--drivers/video/macfb.c74
-rw-r--r--drivers/video/mb862xx/mb862xxfb.c4
-rw-r--r--drivers/video/omap/Makefile1
-rw-r--r--drivers/video/omap/lcd_sx1.c327
-rw-r--r--drivers/video/omap/omapfb_main.c2
-rw-r--r--drivers/video/pxafb.c120
-rw-r--r--drivers/video/pxafb.h3
-rw-r--r--drivers/video/sa1100fb.c2
-rw-r--r--drivers/video/xen-fbfront.c6
-rw-r--r--drivers/video/xilinxfb.c5
20 files changed, 487 insertions, 978 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 3f3ce13fef43..237301849075 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -362,7 +362,7 @@ endchoice
362 362
363config FB_ACORN 363config FB_ACORN
364 bool "Acorn VIDC support" 364 bool "Acorn VIDC support"
365 depends on (FB = y) && ARM && (ARCH_ACORN || ARCH_CLPS7500) 365 depends on (FB = y) && ARM && ARCH_ACORN
366 select FB_CFB_FILLRECT 366 select FB_CFB_FILLRECT
367 select FB_CFB_COPYAREA 367 select FB_CFB_COPYAREA
368 select FB_CFB_IMAGEBLIT 368 select FB_CFB_IMAGEBLIT
diff --git a/drivers/video/amba-clcd.c b/drivers/video/amba-clcd.c
index a7a1c891bfa2..2ac52fd8cc11 100644
--- a/drivers/video/amba-clcd.c
+++ b/drivers/video/amba-clcd.c
@@ -343,14 +343,14 @@ static int clcdfb_register(struct clcd_fb *fb)
343{ 343{
344 int ret; 344 int ret;
345 345
346 fb->clk = clk_get(&fb->dev->dev, "CLCDCLK"); 346 fb->clk = clk_get(&fb->dev->dev, NULL);
347 if (IS_ERR(fb->clk)) { 347 if (IS_ERR(fb->clk)) {
348 ret = PTR_ERR(fb->clk); 348 ret = PTR_ERR(fb->clk);
349 goto out; 349 goto out;
350 } 350 }
351 351
352 fb->fb.fix.mmio_start = fb->dev->res.start; 352 fb->fb.fix.mmio_start = fb->dev->res.start;
353 fb->fb.fix.mmio_len = SZ_4K; 353 fb->fb.fix.mmio_len = 4096;
354 354
355 fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len); 355 fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
356 if (!fb->regs) { 356 if (!fb->regs) {
diff --git a/drivers/video/aty/radeon_accel.c b/drivers/video/aty/radeon_accel.c
index 8718f7349d6b..a469a3d6edcb 100644
--- a/drivers/video/aty/radeon_accel.c
+++ b/drivers/video/aty/radeon_accel.c
@@ -5,61 +5,61 @@
5 * --dte 5 * --dte
6 */ 6 */
7 7
8#define FLUSH_CACHE_WORKAROUND 1 8static void radeon_fixup_offset(struct radeonfb_info *rinfo)
9
10void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries)
11{ 9{
12 int i; 10 u32 local_base;
11
12 /* *** Ugly workaround *** */
13 /*
14 * On some platforms, the video memory is mapped at 0 in radeon chip space
15 * (like PPCs) by the firmware. X will always move it up so that it's seen
16 * by the chip to be at the same address as the PCI BAR.
17 * That means that when switching back from X, there is a mismatch between
18 * the offsets programmed into the engine. This means that potentially,
19 * accel operations done before radeonfb has a chance to re-init the engine
20 * will have incorrect offsets, and potentially trash system memory !
21 *
22 * The correct fix is for fbcon to never call any accel op before the engine
23 * has properly been re-initialized (by a call to set_var), but this is a
24 * complex fix. This workaround in the meantime, called before every accel
25 * operation, makes sure the offsets are in sync.
26 */
13 27
14 for (i=0; i<2000000; i++) { 28 radeon_fifo_wait (1);
15 rinfo->fifo_free = INREG(RBBM_STATUS) & 0x7f; 29 local_base = INREG(MC_FB_LOCATION) << 16;
16 if (rinfo->fifo_free >= entries) 30 if (local_base == rinfo->fb_local_base)
17 return; 31 return;
18 udelay(10);
19 }
20 printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
21 /* XXX Todo: attempt to reset the engine */
22}
23 32
24static inline void radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) 33 rinfo->fb_local_base = local_base;
25{
26 if (entries <= rinfo->fifo_free)
27 rinfo->fifo_free -= entries;
28 else
29 radeon_fifo_update_and_wait(rinfo, entries);
30}
31 34
32static inline void radeonfb_set_creg(struct radeonfb_info *rinfo, u32 reg, 35 radeon_fifo_wait (3);
33 u32 *cache, u32 new_val) 36 OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
34{ 37 (rinfo->fb_local_base >> 10));
35 if (new_val == *cache) 38 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
36 return; 39 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
37 *cache = new_val;
38 radeon_fifo_wait(rinfo, 1);
39 OUTREG(reg, new_val);
40} 40}
41 41
42static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo, 42static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo,
43 const struct fb_fillrect *region) 43 const struct fb_fillrect *region)
44{ 44{
45 radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache, 45 radeon_fifo_wait(4);
46 rinfo->dp_gui_mc_base | GMC_BRUSH_SOLID_COLOR | ROP3_P); 46
47 radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache, 47 OUTREG(DP_GUI_MASTER_CNTL,
48 DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 48 rinfo->dp_gui_master_cntl /* contains, like GMC_DST_32BPP */
49 radeonfb_set_creg(rinfo, DP_BRUSH_FRGD_CLR, &rinfo->dp_brush_fg_cache, 49 | GMC_BRUSH_SOLID_COLOR
50 region->color); 50 | ROP3_P);
51 51 if (radeon_get_dstbpp(rinfo->depth) != DST_8BPP)
52 /* Ensure the dst cache is flushed and the engine idle before 52 OUTREG(DP_BRUSH_FRGD_CLR, rinfo->pseudo_palette[region->color]);
53 * issuing the operation. 53 else
54 * 54 OUTREG(DP_BRUSH_FRGD_CLR, region->color);
55 * This works around engine lockups on some cards 55 OUTREG(DP_WRITE_MSK, 0xffffffff);
56 */ 56 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
57#if FLUSH_CACHE_WORKAROUND 57
58 radeon_fifo_wait(rinfo, 2); 58 radeon_fifo_wait(2);
59 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); 59 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
60 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); 60 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
61#endif 61
62 radeon_fifo_wait(rinfo, 2); 62 radeon_fifo_wait(2);
63 OUTREG(DST_Y_X, (region->dy << 16) | region->dx); 63 OUTREG(DST_Y_X, (region->dy << 16) | region->dx);
64 OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height); 64 OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height);
65} 65}
@@ -70,14 +70,15 @@ void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
70 struct fb_fillrect modded; 70 struct fb_fillrect modded;
71 int vxres, vyres; 71 int vxres, vyres;
72 72
73 WARN_ON(rinfo->gfx_mode); 73 if (info->state != FBINFO_STATE_RUNNING)
74 if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
75 return; 74 return;
76 if (info->flags & FBINFO_HWACCEL_DISABLED) { 75 if (info->flags & FBINFO_HWACCEL_DISABLED) {
77 cfb_fillrect(info, region); 76 cfb_fillrect(info, region);
78 return; 77 return;
79 } 78 }
80 79
80 radeon_fixup_offset(rinfo);
81
81 vxres = info->var.xres_virtual; 82 vxres = info->var.xres_virtual;
82 vyres = info->var.yres_virtual; 83 vyres = info->var.yres_virtual;
83 84
@@ -90,10 +91,6 @@ void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
90 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx; 91 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
91 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy; 92 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
92 93
93 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
94 info->fix.visual == FB_VISUAL_DIRECTCOLOR )
95 modded.color = ((u32 *) (info->pseudo_palette))[region->color];
96
97 radeonfb_prim_fillrect(rinfo, &modded); 94 radeonfb_prim_fillrect(rinfo, &modded);
98} 95}
99 96
@@ -112,22 +109,22 @@ static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo,
112 if ( xdir < 0 ) { sx += w-1; dx += w-1; } 109 if ( xdir < 0 ) { sx += w-1; dx += w-1; }
113 if ( ydir < 0 ) { sy += h-1; dy += h-1; } 110 if ( ydir < 0 ) { sy += h-1; dy += h-1; }
114 111
115 radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache, 112 radeon_fifo_wait(3);
116 rinfo->dp_gui_mc_base | 113 OUTREG(DP_GUI_MASTER_CNTL,
117 GMC_BRUSH_NONE | 114 rinfo->dp_gui_master_cntl /* i.e. GMC_DST_32BPP */
118 GMC_SRC_DATATYPE_COLOR | 115 | GMC_BRUSH_NONE
119 ROP3_S | 116 | GMC_SRC_DSTCOLOR
120 DP_SRC_SOURCE_MEMORY); 117 | ROP3_S
121 radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache, 118 | DP_SRC_SOURCE_MEMORY );
122 (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0) | 119 OUTREG(DP_WRITE_MSK, 0xffffffff);
123 (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0)); 120 OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0)
124 121 | (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0));
125#if FLUSH_CACHE_WORKAROUND 122
126 radeon_fifo_wait(rinfo, 2); 123 radeon_fifo_wait(2);
127 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); 124 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
128 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); 125 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
129#endif 126
130 radeon_fifo_wait(rinfo, 3); 127 radeon_fifo_wait(3);
131 OUTREG(SRC_Y_X, (sy << 16) | sx); 128 OUTREG(SRC_Y_X, (sy << 16) | sx);
132 OUTREG(DST_Y_X, (dy << 16) | dx); 129 OUTREG(DST_Y_X, (dy << 16) | dx);
133 OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w); 130 OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w);
@@ -146,14 +143,15 @@ void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
146 modded.width = area->width; 143 modded.width = area->width;
147 modded.height = area->height; 144 modded.height = area->height;
148 145
149 WARN_ON(rinfo->gfx_mode); 146 if (info->state != FBINFO_STATE_RUNNING)
150 if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
151 return; 147 return;
152 if (info->flags & FBINFO_HWACCEL_DISABLED) { 148 if (info->flags & FBINFO_HWACCEL_DISABLED) {
153 cfb_copyarea(info, area); 149 cfb_copyarea(info, area);
154 return; 150 return;
155 } 151 }
156 152
153 radeon_fixup_offset(rinfo);
154
157 vxres = info->var.xres_virtual; 155 vxres = info->var.xres_virtual;
158 vyres = info->var.yres_virtual; 156 vyres = info->var.yres_virtual;
159 157
@@ -170,112 +168,13 @@ void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
170 radeonfb_prim_copyarea(rinfo, &modded); 168 radeonfb_prim_copyarea(rinfo, &modded);
171} 169}
172 170
173static void radeonfb_prim_imageblit(struct radeonfb_info *rinfo,
174 const struct fb_image *image,
175 u32 fg, u32 bg)
176{
177 unsigned int src_bytes, dwords;
178 u32 *bits;
179
180 radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache,
181 rinfo->dp_gui_mc_base |
182 GMC_BRUSH_NONE |
183 GMC_SRC_DATATYPE_MONO_FG_BG |
184 ROP3_S |
185 GMC_BYTE_ORDER_MSB_TO_LSB |
186 DP_SRC_SOURCE_HOST_DATA);
187 radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache,
188 DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
189 radeonfb_set_creg(rinfo, DP_SRC_FRGD_CLR, &rinfo->dp_src_fg_cache, fg);
190 radeonfb_set_creg(rinfo, DP_SRC_BKGD_CLR, &rinfo->dp_src_bg_cache, bg);
191
192 radeon_fifo_wait(rinfo, 1);
193 OUTREG(DST_Y_X, (image->dy << 16) | image->dx);
194
195 /* Ensure the dst cache is flushed and the engine idle before
196 * issuing the operation.
197 *
198 * This works around engine lockups on some cards
199 */
200#if FLUSH_CACHE_WORKAROUND
201 radeon_fifo_wait(rinfo, 2);
202 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
203 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
204#endif
205
206 /* X here pads width to a multiple of 32 and uses the clipper to
207 * adjust the result. Is that really necessary ? Things seem to
208 * work ok for me without that and the doco doesn't seem to imply
209 * there is such a restriction.
210 */
211 OUTREG(DST_WIDTH_HEIGHT, (image->width << 16) | image->height);
212
213 src_bytes = (((image->width * image->depth) + 7) / 8) * image->height;
214 dwords = (src_bytes + 3) / 4;
215 bits = (u32*)(image->data);
216
217 while(dwords >= 8) {
218 radeon_fifo_wait(rinfo, 8);
219#if BITS_PER_LONG == 64
220 __raw_writeq(*((u64 *)(bits)), rinfo->mmio_base + HOST_DATA0);
221 __raw_writeq(*((u64 *)(bits+2)), rinfo->mmio_base + HOST_DATA2);
222 __raw_writeq(*((u64 *)(bits+4)), rinfo->mmio_base + HOST_DATA4);
223 __raw_writeq(*((u64 *)(bits+6)), rinfo->mmio_base + HOST_DATA6);
224 bits += 8;
225#else
226 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA0);
227 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA1);
228 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA2);
229 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA3);
230 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA4);
231 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA5);
232 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA6);
233 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA7);
234#endif
235 dwords -= 8;
236 }
237 while(dwords--) {
238 radeon_fifo_wait(rinfo, 1);
239 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA0);
240 }
241}
242
243void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image) 171void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image)
244{ 172{
245 struct radeonfb_info *rinfo = info->par; 173 struct radeonfb_info *rinfo = info->par;
246 u32 fg, bg;
247
248 WARN_ON(rinfo->gfx_mode);
249 if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
250 return;
251 174
252 if (!image->width || !image->height) 175 if (info->state != FBINFO_STATE_RUNNING)
253 return; 176 return;
254 177 radeon_engine_idle();
255 /* We only do 1 bpp color expansion for now */
256 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1)
257 goto fallback;
258
259 /* Fallback if running out of the screen. We may do clipping
260 * in the future */
261 if ((image->dx + image->width) > info->var.xres_virtual ||
262 (image->dy + image->height) > info->var.yres_virtual)
263 goto fallback;
264
265 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
266 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
267 fg = ((u32*)(info->pseudo_palette))[image->fg_color];
268 bg = ((u32*)(info->pseudo_palette))[image->bg_color];
269 } else {
270 fg = image->fg_color;
271 bg = image->bg_color;
272 }
273
274 radeonfb_prim_imageblit(rinfo, image, fg, bg);
275 return;
276
277 fallback:
278 radeon_engine_idle(rinfo);
279 178
280 cfb_imageblit(info, image); 179 cfb_imageblit(info, image);
281} 180}
@@ -286,8 +185,7 @@ int radeonfb_sync(struct fb_info *info)
286 185
287 if (info->state != FBINFO_STATE_RUNNING) 186 if (info->state != FBINFO_STATE_RUNNING)
288 return 0; 187 return 0;
289 188 radeon_engine_idle();
290 radeon_engine_idle(rinfo);
291 189
292 return 0; 190 return 0;
293} 191}
@@ -363,10 +261,9 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
363 /* disable 3D engine */ 261 /* disable 3D engine */
364 OUTREG(RB3D_CNTL, 0); 262 OUTREG(RB3D_CNTL, 0);
365 263
366 rinfo->fifo_free = 0;
367 radeonfb_engine_reset(rinfo); 264 radeonfb_engine_reset(rinfo);
368 265
369 radeon_fifo_wait(rinfo, 1); 266 radeon_fifo_wait (1);
370 if (IS_R300_VARIANT(rinfo)) { 267 if (IS_R300_VARIANT(rinfo)) {
371 OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) | 268 OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) |
372 RB2D_DC_AUTOFLUSH_ENABLE | 269 RB2D_DC_AUTOFLUSH_ENABLE |
@@ -380,7 +277,7 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
380 OUTREG(RB2D_DSTCACHE_MODE, 0); 277 OUTREG(RB2D_DSTCACHE_MODE, 0);
381 } 278 }
382 279
383 radeon_fifo_wait(rinfo, 3); 280 radeon_fifo_wait (3);
384 /* We re-read MC_FB_LOCATION from card as it can have been 281 /* We re-read MC_FB_LOCATION from card as it can have been
385 * modified by XFree drivers (ouch !) 282 * modified by XFree drivers (ouch !)
386 */ 283 */
@@ -391,57 +288,41 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
391 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); 288 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
392 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); 289 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
393 290
394 radeon_fifo_wait(rinfo, 1); 291 radeon_fifo_wait (1);
395#ifdef __BIG_ENDIAN 292#if defined(__BIG_ENDIAN)
396 OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); 293 OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
397#else 294#else
398 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); 295 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
399#endif 296#endif
400 radeon_fifo_wait(rinfo, 2); 297 radeon_fifo_wait (2);
401 OUTREG(DEFAULT_SC_TOP_LEFT, 0); 298 OUTREG(DEFAULT_SC_TOP_LEFT, 0);
402 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | 299 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
403 DEFAULT_SC_BOTTOM_MAX)); 300 DEFAULT_SC_BOTTOM_MAX));
404 301
405 /* set default DP_GUI_MASTER_CNTL */
406 temp = radeon_get_dstbpp(rinfo->depth); 302 temp = radeon_get_dstbpp(rinfo->depth);
407 rinfo->dp_gui_mc_base = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS); 303 rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
408 304
409 rinfo->dp_gui_mc_cache = rinfo->dp_gui_mc_base | 305 radeon_fifo_wait (1);
410 GMC_BRUSH_SOLID_COLOR | 306 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
411 GMC_SRC_DATATYPE_COLOR; 307 GMC_BRUSH_SOLID_COLOR |
412 radeon_fifo_wait(rinfo, 1); 308 GMC_SRC_DATATYPE_COLOR));
413 OUTREG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_mc_cache);
414 309
310 radeon_fifo_wait (7);
415 311
416 /* clear line drawing regs */ 312 /* clear line drawing regs */
417 radeon_fifo_wait(rinfo, 2);
418 OUTREG(DST_LINE_START, 0); 313 OUTREG(DST_LINE_START, 0);
419 OUTREG(DST_LINE_END, 0); 314 OUTREG(DST_LINE_END, 0);
420 315
421 /* set brush and source color regs */ 316 /* set brush color regs */
422 rinfo->dp_brush_fg_cache = 0xffffffff; 317 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
423 rinfo->dp_brush_bg_cache = 0x00000000; 318 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
424 rinfo->dp_src_fg_cache = 0xffffffff; 319
425 rinfo->dp_src_bg_cache = 0x00000000; 320 /* set source color regs */
426 radeon_fifo_wait(rinfo, 4); 321 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
427 OUTREG(DP_BRUSH_FRGD_CLR, rinfo->dp_brush_fg_cache); 322 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
428 OUTREG(DP_BRUSH_BKGD_CLR, rinfo->dp_brush_bg_cache);
429 OUTREG(DP_SRC_FRGD_CLR, rinfo->dp_src_fg_cache);
430 OUTREG(DP_SRC_BKGD_CLR, rinfo->dp_src_bg_cache);
431
432 /* Default direction */
433 rinfo->dp_cntl_cache = DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM;
434 radeon_fifo_wait(rinfo, 1);
435 OUTREG(DP_CNTL, rinfo->dp_cntl_cache);
436 323
437 /* default write mask */ 324 /* default write mask */
438 radeon_fifo_wait(rinfo, 1);
439 OUTREG(DP_WRITE_MSK, 0xffffffff); 325 OUTREG(DP_WRITE_MSK, 0xffffffff);
440 326
441 /* Default to no swapping of host data */ 327 radeon_engine_idle ();
442 radeon_fifo_wait(rinfo, 1);
443 OUTREG(RBBM_GUICNTL, RBBM_GUICNTL_HOST_DATA_SWAP_NONE);
444
445 /* Make sure it's settled */
446 radeon_engine_idle(rinfo);
447} 328}
diff --git a/drivers/video/aty/radeon_backlight.c b/drivers/video/aty/radeon_backlight.c
index f343ba83f0ae..1a056adb61c8 100644
--- a/drivers/video/aty/radeon_backlight.c
+++ b/drivers/video/aty/radeon_backlight.c
@@ -66,7 +66,7 @@ static int radeon_bl_update_status(struct backlight_device *bd)
66 level = bd->props.brightness; 66 level = bd->props.brightness;
67 67
68 del_timer_sync(&rinfo->lvds_timer); 68 del_timer_sync(&rinfo->lvds_timer);
69 radeon_engine_idle(rinfo); 69 radeon_engine_idle();
70 70
71 lvds_gen_cntl = INREG(LVDS_GEN_CNTL); 71 lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
72 if (level > 0) { 72 if (level > 0) {
diff --git a/drivers/video/aty/radeon_base.c b/drivers/video/aty/radeon_base.c
index 9a5821c65ebf..d0f1a7fc2c9d 100644
--- a/drivers/video/aty/radeon_base.c
+++ b/drivers/video/aty/radeon_base.c
@@ -852,6 +852,7 @@ static int radeonfb_pan_display (struct fb_var_screeninfo *var,
852 if (rinfo->asleep) 852 if (rinfo->asleep)
853 return 0; 853 return 0;
854 854
855 radeon_fifo_wait(2);
855 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset) 856 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
856 * var->bits_per_pixel / 8) & ~7); 857 * var->bits_per_pixel / 8) & ~7);
857 return 0; 858 return 0;
@@ -881,6 +882,7 @@ static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
881 if (rc) 882 if (rc)
882 return rc; 883 return rc;
883 884
885 radeon_fifo_wait(2);
884 if (value & 0x01) { 886 if (value & 0x01) {
885 tmp = INREG(LVDS_GEN_CNTL); 887 tmp = INREG(LVDS_GEN_CNTL);
886 888
@@ -938,7 +940,7 @@ int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
938 if (rinfo->lock_blank) 940 if (rinfo->lock_blank)
939 return 0; 941 return 0;
940 942
941 radeon_engine_idle(rinfo); 943 radeon_engine_idle();
942 944
943 val = INREG(CRTC_EXT_CNTL); 945 val = INREG(CRTC_EXT_CNTL);
944 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | 946 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
@@ -1046,7 +1048,7 @@ static int radeonfb_blank (int blank, struct fb_info *info)
1046 1048
1047 if (rinfo->asleep) 1049 if (rinfo->asleep)
1048 return 0; 1050 return 0;
1049 1051
1050 return radeon_screen_blank(rinfo, blank, 0); 1052 return radeon_screen_blank(rinfo, blank, 0);
1051} 1053}
1052 1054
@@ -1072,6 +1074,8 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1072 pindex = regno; 1074 pindex = regno;
1073 1075
1074 if (!rinfo->asleep) { 1076 if (!rinfo->asleep) {
1077 radeon_fifo_wait(9);
1078
1075 if (rinfo->bpp == 16) { 1079 if (rinfo->bpp == 16) {
1076 pindex = regno * 8; 1080 pindex = regno * 8;
1077 1081
@@ -1240,6 +1244,8 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg
1240{ 1244{
1241 int i; 1245 int i;
1242 1246
1247 radeon_fifo_wait(20);
1248
1243 /* Workaround from XFree */ 1249 /* Workaround from XFree */
1244 if (rinfo->is_mobility) { 1250 if (rinfo->is_mobility) {
1245 /* A temporal workaround for the occational blanking on certain laptop 1251 /* A temporal workaround for the occational blanking on certain laptop
@@ -1335,7 +1341,7 @@ static void radeon_lvds_timer_func(unsigned long data)
1335{ 1341{
1336 struct radeonfb_info *rinfo = (struct radeonfb_info *)data; 1342 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1337 1343
1338 radeon_engine_idle(rinfo); 1344 radeon_engine_idle();
1339 1345
1340 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); 1346 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1341} 1347}
@@ -1353,11 +1359,10 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1353 if (nomodeset) 1359 if (nomodeset)
1354 return; 1360 return;
1355 1361
1356 radeon_engine_idle(rinfo);
1357
1358 if (!regs_only) 1362 if (!regs_only)
1359 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0); 1363 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1360 1364
1365 radeon_fifo_wait(31);
1361 for (i=0; i<10; i++) 1366 for (i=0; i<10; i++)
1362 OUTREG(common_regs[i].reg, common_regs[i].val); 1367 OUTREG(common_regs[i].reg, common_regs[i].val);
1363 1368
@@ -1385,6 +1390,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1385 radeon_write_pll_regs(rinfo, mode); 1390 radeon_write_pll_regs(rinfo, mode);
1386 1391
1387 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { 1392 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1393 radeon_fifo_wait(10);
1388 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); 1394 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1389 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); 1395 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1390 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); 1396 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
@@ -1399,6 +1405,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1399 if (!regs_only) 1405 if (!regs_only)
1400 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0); 1406 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1401 1407
1408 radeon_fifo_wait(2);
1402 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); 1409 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1403 1410
1404 return; 1411 return;
@@ -1549,7 +1556,7 @@ static int radeonfb_set_par(struct fb_info *info)
1549 /* We always want engine to be idle on a mode switch, even 1556 /* We always want engine to be idle on a mode switch, even
1550 * if we won't actually change the mode 1557 * if we won't actually change the mode
1551 */ 1558 */
1552 radeon_engine_idle(rinfo); 1559 radeon_engine_idle();
1553 1560
1554 hSyncStart = mode->xres + mode->right_margin; 1561 hSyncStart = mode->xres + mode->right_margin;
1555 hSyncEnd = hSyncStart + mode->hsync_len; 1562 hSyncEnd = hSyncStart + mode->hsync_len;
@@ -1844,6 +1851,7 @@ static int radeonfb_set_par(struct fb_info *info)
1844 return 0; 1851 return 0;
1845} 1852}
1846 1853
1854
1847static struct fb_ops radeonfb_ops = { 1855static struct fb_ops radeonfb_ops = {
1848 .owner = THIS_MODULE, 1856 .owner = THIS_MODULE,
1849 .fb_check_var = radeonfb_check_var, 1857 .fb_check_var = radeonfb_check_var,
@@ -1867,7 +1875,6 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1867 info->par = rinfo; 1875 info->par = rinfo;
1868 info->pseudo_palette = rinfo->pseudo_palette; 1876 info->pseudo_palette = rinfo->pseudo_palette;
1869 info->flags = FBINFO_DEFAULT 1877 info->flags = FBINFO_DEFAULT
1870 | FBINFO_HWACCEL_IMAGEBLIT
1871 | FBINFO_HWACCEL_COPYAREA 1878 | FBINFO_HWACCEL_COPYAREA
1872 | FBINFO_HWACCEL_FILLRECT 1879 | FBINFO_HWACCEL_FILLRECT
1873 | FBINFO_HWACCEL_XPAN 1880 | FBINFO_HWACCEL_XPAN
@@ -1999,6 +2006,7 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo)
1999 u32 tom = INREG(NB_TOM); 2006 u32 tom = INREG(NB_TOM);
2000 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); 2007 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2001 2008
2009 radeon_fifo_wait(6);
2002 OUTREG(MC_FB_LOCATION, tom); 2010 OUTREG(MC_FB_LOCATION, tom);
2003 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 2011 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2004 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 2012 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
diff --git a/drivers/video/aty/radeon_pm.c b/drivers/video/aty/radeon_pm.c
index 3df5015f1d13..675abdafc2d8 100644
--- a/drivers/video/aty/radeon_pm.c
+++ b/drivers/video/aty/radeon_pm.c
@@ -2653,9 +2653,9 @@ int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
2653 2653
2654 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { 2654 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
2655 /* Make sure engine is reset */ 2655 /* Make sure engine is reset */
2656 radeon_engine_idle(rinfo); 2656 radeon_engine_idle();
2657 radeonfb_engine_reset(rinfo); 2657 radeonfb_engine_reset(rinfo);
2658 radeon_engine_idle(rinfo); 2658 radeon_engine_idle();
2659 } 2659 }
2660 2660
2661 /* Blank display and LCD */ 2661 /* Blank display and LCD */
@@ -2767,7 +2767,7 @@ int radeonfb_pci_resume(struct pci_dev *pdev)
2767 2767
2768 rinfo->asleep = 0; 2768 rinfo->asleep = 0;
2769 } else 2769 } else
2770 radeon_engine_idle(rinfo); 2770 radeon_engine_idle();
2771 2771
2772 /* Restore display & engine */ 2772 /* Restore display & engine */
2773 radeon_write_mode (rinfo, &rinfo->state, 1); 2773 radeon_write_mode (rinfo, &rinfo->state, 1);
diff --git a/drivers/video/aty/radeonfb.h b/drivers/video/aty/radeonfb.h
index ea0b5b47acaf..3ea1b00fdd22 100644
--- a/drivers/video/aty/radeonfb.h
+++ b/drivers/video/aty/radeonfb.h
@@ -336,15 +336,7 @@ struct radeonfb_info {
336 int mon2_type; 336 int mon2_type;
337 u8 *mon2_EDID; 337 u8 *mon2_EDID;
338 338
339 /* accel bits */ 339 u32 dp_gui_master_cntl;
340 u32 dp_gui_mc_base;
341 u32 dp_gui_mc_cache;
342 u32 dp_cntl_cache;
343 u32 dp_brush_fg_cache;
344 u32 dp_brush_bg_cache;
345 u32 dp_src_fg_cache;
346 u32 dp_src_bg_cache;
347 u32 fifo_free;
348 340
349 struct pll_info pll; 341 struct pll_info pll;
350 342
@@ -356,7 +348,6 @@ struct radeonfb_info {
356 int lock_blank; 348 int lock_blank;
357 int dynclk; 349 int dynclk;
358 int no_schedule; 350 int no_schedule;
359 int gfx_mode;
360 enum radeon_pm_mode pm_mode; 351 enum radeon_pm_mode pm_mode;
361 reinit_function_ptr reinit_func; 352 reinit_function_ptr reinit_func;
362 353
@@ -401,14 +392,8 @@ static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
401#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) 392#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
402#define INREG16(addr) readw((rinfo->mmio_base)+addr) 393#define INREG16(addr) readw((rinfo->mmio_base)+addr)
403#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) 394#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
404
405#ifdef CONFIG_PPC
406#define INREG(addr) ({ eieio(); ld_le32(rinfo->mmio_base+(addr)); })
407#define OUTREG(addr,val) do { eieio(); st_le32(rinfo->mmio_base+(addr),(val)); } while(0)
408#else
409#define INREG(addr) readl((rinfo->mmio_base)+addr) 395#define INREG(addr) readl((rinfo->mmio_base)+addr)
410#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) 396#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
411#endif
412 397
413static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, 398static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
414 u32 val, u32 mask) 399 u32 val, u32 mask)
@@ -550,7 +535,17 @@ static inline u32 radeon_get_dstbpp(u16 depth)
550 * 2D Engine helper routines 535 * 2D Engine helper routines
551 */ 536 */
552 537
553extern void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries); 538static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
539{
540 int i;
541
542 for (i=0; i<2000000; i++) {
543 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
544 return;
545 udelay(1);
546 }
547 printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
548}
554 549
555static inline void radeon_engine_flush (struct radeonfb_info *rinfo) 550static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
556{ 551{
@@ -563,7 +558,7 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
563 /* Ensure FIFO is empty, ie, make sure the flush commands 558 /* Ensure FIFO is empty, ie, make sure the flush commands
564 * has reached the cache 559 * has reached the cache
565 */ 560 */
566 radeon_fifo_update_and_wait(rinfo, 64); 561 _radeon_fifo_wait (rinfo, 64);
567 562
568 /* Wait for the flush to complete */ 563 /* Wait for the flush to complete */
569 for (i=0; i < 2000000; i++) { 564 for (i=0; i < 2000000; i++) {
@@ -575,12 +570,12 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
575} 570}
576 571
577 572
578static inline void radeon_engine_idle(struct radeonfb_info *rinfo) 573static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
579{ 574{
580 int i; 575 int i;
581 576
582 /* ensure FIFO is empty before waiting for idle */ 577 /* ensure FIFO is empty before waiting for idle */
583 radeon_fifo_update_and_wait (rinfo, 64); 578 _radeon_fifo_wait (rinfo, 64);
584 579
585 for (i=0; i<2000000; i++) { 580 for (i=0; i<2000000; i++) {
586 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { 581 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
@@ -593,6 +588,8 @@ static inline void radeon_engine_idle(struct radeonfb_info *rinfo)
593} 588}
594 589
595 590
591#define radeon_engine_idle() _radeon_engine_idle(rinfo)
592#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
596#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) 593#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
597 594
598 595
@@ -622,7 +619,6 @@ extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
622extern int radeonfb_sync(struct fb_info *info); 619extern int radeonfb_sync(struct fb_info *info);
623extern void radeonfb_engine_init (struct radeonfb_info *rinfo); 620extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
624extern void radeonfb_engine_reset(struct radeonfb_info *rinfo); 621extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
625extern void radeon_fixup_mem_offset(struct radeonfb_info *rinfo);
626 622
627/* Other functions */ 623/* Other functions */
628extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch); 624extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c
index b92947d62ad6..0b2adefe9e3d 100644
--- a/drivers/video/console/fbcon.c
+++ b/drivers/video/console/fbcon.c
@@ -2389,16 +2389,13 @@ static int fbcon_blank(struct vc_data *vc, int blank, int mode_switch)
2389 2389
2390 if (!fbcon_is_inactive(vc, info)) { 2390 if (!fbcon_is_inactive(vc, info)) {
2391 if (ops->blank_state != blank) { 2391 if (ops->blank_state != blank) {
2392 int ret = 1;
2393
2394 ops->blank_state = blank; 2392 ops->blank_state = blank;
2395 fbcon_cursor(vc, blank ? CM_ERASE : CM_DRAW); 2393 fbcon_cursor(vc, blank ? CM_ERASE : CM_DRAW);
2396 ops->cursor_flash = (!blank); 2394 ops->cursor_flash = (!blank);
2397 2395
2398 if (info->fbops->fb_blank) 2396 if (!(info->flags & FBINFO_MISC_USEREVENT))
2399 ret = info->fbops->fb_blank(blank, info); 2397 if (fb_blank(info, blank))
2400 if (ret) 2398 fbcon_generic_blank(vc, info, blank);
2401 fbcon_generic_blank(vc, info, blank);
2402 } 2399 }
2403 2400
2404 if (!blank) 2401 if (!blank)
@@ -3534,12 +3531,18 @@ static void fbcon_exit(void)
3534 softback_buf = 0UL; 3531 softback_buf = 0UL;
3535 3532
3536 for (i = 0; i < FB_MAX; i++) { 3533 for (i = 0; i < FB_MAX; i++) {
3534 int pending;
3535
3537 mapped = 0; 3536 mapped = 0;
3538 info = registered_fb[i]; 3537 info = registered_fb[i];
3539 3538
3540 if (info == NULL) 3539 if (info == NULL)
3541 continue; 3540 continue;
3542 3541
3542 pending = cancel_work_sync(&info->queue);
3543 DPRINTK("fbcon: %s pending work\n", (pending ? "canceled" :
3544 "no"));
3545
3543 for (j = first_fb_vc; j <= last_fb_vc; j++) { 3546 for (j = first_fb_vc; j <= last_fb_vc; j++) {
3544 if (con2fb_map[j] == i) 3547 if (con2fb_map[j] == i)
3545 mapped = 1; 3548 mapped = 1;
diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
index ccd986140c95..d58c68cd456e 100644
--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -1,6 +1,4 @@
1/* 1/*
2 * linux/drivers/video/imxfb.c
3 *
4 * Freescale i.MX Frame Buffer device driver 2 * Freescale i.MX Frame Buffer device driver
5 * 3 *
6 * Copyright (C) 2004 Sascha Hauer, Pengutronix 4 * Copyright (C) 2004 Sascha Hauer, Pengutronix
@@ -16,7 +14,6 @@
16 * linux-arm-kernel@lists.arm.linux.org.uk 14 * linux-arm-kernel@lists.arm.linux.org.uk
17 */ 15 */
18 16
19//#define DEBUG 1
20 17
21#include <linux/module.h> 18#include <linux/module.h>
22#include <linux/kernel.h> 19#include <linux/kernel.h>
@@ -32,9 +29,8 @@
32#include <linux/cpufreq.h> 29#include <linux/cpufreq.h>
33#include <linux/platform_device.h> 30#include <linux/platform_device.h>
34#include <linux/dma-mapping.h> 31#include <linux/dma-mapping.h>
32#include <linux/io.h>
35 33
36#include <mach/hardware.h>
37#include <asm/io.h>
38#include <mach/imxfb.h> 34#include <mach/imxfb.h>
39 35
40/* 36/*
@@ -42,23 +38,150 @@
42 */ 38 */
43#define DEBUG_VAR 1 39#define DEBUG_VAR 1
44 40
45#include "imxfb.h" 41#define DRIVER_NAME "imx-fb"
42
43#define LCDC_SSA 0x00
44
45#define LCDC_SIZE 0x04
46#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
47#define SIZE_YMAX(y) ((y) & 0x1ff)
48
49#define LCDC_VPW 0x08
50#define VPW_VPW(x) ((x) & 0x3ff)
51
52#define LCDC_CPOS 0x0C
53#define CPOS_CC1 (1<<31)
54#define CPOS_CC0 (1<<30)
55#define CPOS_OP (1<<28)
56#define CPOS_CXP(x) (((x) & 3ff) << 16)
57#define CPOS_CYP(y) ((y) & 0x1ff)
58
59#define LCDC_LCWHB 0x10
60#define LCWHB_BK_EN (1<<31)
61#define LCWHB_CW(w) (((w) & 0x1f) << 24)
62#define LCWHB_CH(h) (((h) & 0x1f) << 16)
63#define LCWHB_BD(x) ((x) & 0xff)
64
65#define LCDC_LCHCC 0x14
66#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
67#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
68#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
69
70#define LCDC_PCR 0x18
71
72#define LCDC_HCR 0x1C
73#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
74#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
75#define HCR_H_WAIT_2(x) ((x) & 0xff)
76
77#define LCDC_VCR 0x20
78#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
79#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
80#define VCR_V_WAIT_2(x) ((x) & 0xff)
81
82#define LCDC_POS 0x24
83#define POS_POS(x) ((x) & 1f)
84
85#define LCDC_LSCR1 0x28
86/* bit fields in imxfb.h */
87
88#define LCDC_PWMR 0x2C
89/* bit fields in imxfb.h */
90
91#define LCDC_DMACR 0x30
92/* bit fields in imxfb.h */
93
94#define LCDC_RMCR 0x34
95#define RMCR_LCDC_EN (1<<1)
96#define RMCR_SELF_REF (1<<0)
97
98#define LCDC_LCDICR 0x38
99#define LCDICR_INT_SYN (1<<2)
100#define LCDICR_INT_CON (1)
101
102#define LCDC_LCDISR 0x40
103#define LCDISR_UDR_ERR (1<<3)
104#define LCDISR_ERR_RES (1<<2)
105#define LCDISR_EOF (1<<1)
106#define LCDISR_BOF (1<<0)
107
108/*
109 * These are the bitfields for each
110 * display depth that we support.
111 */
112struct imxfb_rgb {
113 struct fb_bitfield red;
114 struct fb_bitfield green;
115 struct fb_bitfield blue;
116 struct fb_bitfield transp;
117};
118
119struct imxfb_info {
120 struct platform_device *pdev;
121 void __iomem *regs;
46 122
47static struct imxfb_rgb def_rgb_16 = { 123 u_int max_bpp;
48 .red = { .offset = 8, .length = 4, }, 124 u_int max_xres;
49 .green = { .offset = 4, .length = 4, }, 125 u_int max_yres;
50 .blue = { .offset = 0, .length = 4, }, 126
51 .transp = { .offset = 0, .length = 0, }, 127 /*
128 * These are the addresses we mapped
129 * the framebuffer memory region to.
130 */
131 dma_addr_t map_dma;
132 u_char *map_cpu;
133 u_int map_size;
134
135 u_char *screen_cpu;
136 dma_addr_t screen_dma;
137 u_int palette_size;
138
139 dma_addr_t dbar1;
140 dma_addr_t dbar2;
141
142 u_int pcr;
143 u_int pwmr;
144 u_int lscr1;
145 u_int dmacr;
146 u_int cmap_inverse:1,
147 cmap_static:1,
148 unused:30;
149
150 void (*lcd_power)(int);
151 void (*backlight_power)(int);
152};
153
154#define IMX_NAME "IMX"
155
156/*
157 * Minimum X and Y resolutions
158 */
159#define MIN_XRES 64
160#define MIN_YRES 64
161
162static struct imxfb_rgb def_rgb_16_tft = {
163 .red = {.offset = 11, .length = 5,},
164 .green = {.offset = 5, .length = 6,},
165 .blue = {.offset = 0, .length = 5,},
166 .transp = {.offset = 0, .length = 0,},
167};
168
169static struct imxfb_rgb def_rgb_16_stn = {
170 .red = {.offset = 8, .length = 4,},
171 .green = {.offset = 4, .length = 4,},
172 .blue = {.offset = 0, .length = 4,},
173 .transp = {.offset = 0, .length = 0,},
52}; 174};
53 175
54static struct imxfb_rgb def_rgb_8 = { 176static struct imxfb_rgb def_rgb_8 = {
55 .red = { .offset = 0, .length = 8, }, 177 .red = {.offset = 0, .length = 8,},
56 .green = { .offset = 0, .length = 8, }, 178 .green = {.offset = 0, .length = 8,},
57 .blue = { .offset = 0, .length = 8, }, 179 .blue = {.offset = 0, .length = 8,},
58 .transp = { .offset = 0, .length = 0, }, 180 .transp = {.offset = 0, .length = 0,},
59}; 181};
60 182
61static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info); 183static int imxfb_activate_var(struct fb_var_screeninfo *var,
184 struct fb_info *info);
62 185
63static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) 186static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
64{ 187{
@@ -67,10 +190,8 @@ static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
67 return chan << bf->offset; 190 return chan << bf->offset;
68} 191}
69 192
70#define LCDC_PALETTE(x) __REG2(IMX_LCDC_BASE+0x800, (x)<<2) 193static int imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
71static int 194 u_int trans, struct fb_info *info)
72imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
73 u_int trans, struct fb_info *info)
74{ 195{
75 struct imxfb_info *fbi = info->par; 196 struct imxfb_info *fbi = info->par;
76 u_int val, ret = 1; 197 u_int val, ret = 1;
@@ -81,14 +202,13 @@ imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
81 (CNVT_TOHW(green,4) << 4) | 202 (CNVT_TOHW(green,4) << 4) |
82 CNVT_TOHW(blue, 4); 203 CNVT_TOHW(blue, 4);
83 204
84 LCDC_PALETTE(regno) = val; 205 writel(val, fbi->regs + 0x800 + (regno << 2));
85 ret = 0; 206 ret = 0;
86 } 207 }
87 return ret; 208 return ret;
88} 209}
89 210
90static int 211static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
91imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
92 u_int trans, struct fb_info *info) 212 u_int trans, struct fb_info *info)
93{ 213{
94 struct imxfb_info *fbi = info->par; 214 struct imxfb_info *fbi = info->par;
@@ -148,11 +268,10 @@ imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
148 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, 268 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
149 * bitfields, horizontal timing, vertical timing. 269 * bitfields, horizontal timing, vertical timing.
150 */ 270 */
151static int 271static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
152imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
153{ 272{
154 struct imxfb_info *fbi = info->par; 273 struct imxfb_info *fbi = info->par;
155 int rgbidx; 274 struct imxfb_rgb *rgb;
156 275
157 if (var->xres < MIN_XRES) 276 if (var->xres < MIN_XRES)
158 var->xres = MIN_XRES; 277 var->xres = MIN_XRES;
@@ -168,23 +287,25 @@ imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
168 pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel); 287 pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel);
169 switch (var->bits_per_pixel) { 288 switch (var->bits_per_pixel) {
170 case 16: 289 case 16:
171 rgbidx = RGB_16; 290 default:
291 if (readl(fbi->regs + LCDC_PCR) & PCR_TFT)
292 rgb = &def_rgb_16_tft;
293 else
294 rgb = &def_rgb_16_stn;
172 break; 295 break;
173 case 8: 296 case 8:
174 rgbidx = RGB_8; 297 rgb = &def_rgb_8;
175 break; 298 break;
176 default:
177 rgbidx = RGB_16;
178 } 299 }
179 300
180 /* 301 /*
181 * Copy the RGB parameters for this display 302 * Copy the RGB parameters for this display
182 * from the machine specific parameters. 303 * from the machine specific parameters.
183 */ 304 */
184 var->red = fbi->rgb[rgbidx]->red; 305 var->red = rgb->red;
185 var->green = fbi->rgb[rgbidx]->green; 306 var->green = rgb->green;
186 var->blue = fbi->rgb[rgbidx]->blue; 307 var->blue = rgb->blue;
187 var->transp = fbi->rgb[rgbidx]->transp; 308 var->transp = rgb->transp;
188 309
189 pr_debug("RGBT length = %d:%d:%d:%d\n", 310 pr_debug("RGBT length = %d:%d:%d:%d\n",
190 var->red.length, var->green.length, var->blue.length, 311 var->red.length, var->green.length, var->blue.length,
@@ -221,8 +342,7 @@ static int imxfb_set_par(struct fb_info *info)
221 info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; 342 info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
222 } 343 }
223 344
224 info->fix.line_length = var->xres_virtual * 345 info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
225 var->bits_per_pixel / 8;
226 fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16; 346 fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
227 347
228 imxfb_activate_var(var, info); 348 imxfb_activate_var(var, info);
@@ -235,22 +355,27 @@ static void imxfb_enable_controller(struct imxfb_info *fbi)
235 pr_debug("Enabling LCD controller\n"); 355 pr_debug("Enabling LCD controller\n");
236 356
237 /* initialize LCDC */ 357 /* initialize LCDC */
238 LCDC_RMCR &= ~RMCR_LCDC_EN; /* just to be safe... */ 358 writel(readl(fbi->regs + LCDC_RMCR) & ~RMCR_LCDC_EN,
359 fbi->regs + LCDC_RMCR); /* just to be safe... */
360
361 writel(fbi->screen_dma, fbi->regs + LCDC_SSA);
239 362
240 LCDC_SSA = fbi->screen_dma;
241 /* physical screen start address */ 363 /* physical screen start address */
242 LCDC_VPW = VPW_VPW(fbi->max_xres * fbi->max_bpp / 8 / 4); 364 writel(VPW_VPW(fbi->max_xres * fbi->max_bpp / 8 / 4),
365 fbi->regs + LCDC_VPW);
243 366
244 LCDC_POS = 0x00000000; /* panning offset 0 (0 pixel offset) */ 367 /* panning offset 0 (0 pixel offset) */
368 writel(0x00000000, fbi->regs + LCDC_POS);
245 369
246 /* disable hardware cursor */ 370 /* disable hardware cursor */
247 LCDC_CPOS &= ~(CPOS_CC0 | CPOS_CC1); 371 writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1),
372 fbi->regs + LCDC_CPOS);
248 373
249 LCDC_RMCR = RMCR_LCDC_EN; 374 writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR);
250 375
251 if(fbi->backlight_power) 376 if (fbi->backlight_power)
252 fbi->backlight_power(1); 377 fbi->backlight_power(1);
253 if(fbi->lcd_power) 378 if (fbi->lcd_power)
254 fbi->lcd_power(1); 379 fbi->lcd_power(1);
255} 380}
256 381
@@ -258,12 +383,12 @@ static void imxfb_disable_controller(struct imxfb_info *fbi)
258{ 383{
259 pr_debug("Disabling LCD controller\n"); 384 pr_debug("Disabling LCD controller\n");
260 385
261 if(fbi->backlight_power) 386 if (fbi->backlight_power)
262 fbi->backlight_power(0); 387 fbi->backlight_power(0);
263 if(fbi->lcd_power) 388 if (fbi->lcd_power)
264 fbi->lcd_power(0); 389 fbi->lcd_power(0);
265 390
266 LCDC_RMCR = 0; 391 writel(0, fbi->regs + LCDC_RMCR);
267} 392}
268 393
269static int imxfb_blank(int blank, struct fb_info *info) 394static int imxfb_blank(int blank, struct fb_info *info)
@@ -340,74 +465,26 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf
340 info->fix.id, var->lower_margin); 465 info->fix.id, var->lower_margin);
341#endif 466#endif
342 467
343 LCDC_HCR = HCR_H_WIDTH(var->hsync_len) | 468 writel(HCR_H_WIDTH(var->hsync_len) |
344 HCR_H_WAIT_1(var->left_margin) | 469 HCR_H_WAIT_1(var->right_margin) |
345 HCR_H_WAIT_2(var->right_margin); 470 HCR_H_WAIT_2(var->left_margin),
471 fbi->regs + LCDC_HCR);
346 472
347 LCDC_VCR = VCR_V_WIDTH(var->vsync_len) | 473 writel(VCR_V_WIDTH(var->vsync_len) |
348 VCR_V_WAIT_1(var->upper_margin) | 474 VCR_V_WAIT_1(var->lower_margin) |
349 VCR_V_WAIT_2(var->lower_margin); 475 VCR_V_WAIT_2(var->upper_margin),
476 fbi->regs + LCDC_VCR);
350 477
351 LCDC_SIZE = SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres); 478 writel(SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres),
352 LCDC_PCR = fbi->pcr; 479 fbi->regs + LCDC_SIZE);
353 LCDC_PWMR = fbi->pwmr; 480 writel(fbi->pcr, fbi->regs + LCDC_PCR);
354 LCDC_LSCR1 = fbi->lscr1; 481 writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
355 LCDC_DMACR = fbi->dmacr; 482 writel(fbi->lscr1, fbi->regs + LCDC_LSCR1);
483 writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
356 484
357 return 0; 485 return 0;
358} 486}
359 487
360static void imxfb_setup_gpio(struct imxfb_info *fbi)
361{
362 int width;
363
364 LCDC_RMCR &= ~(RMCR_LCDC_EN | RMCR_SELF_REF);
365
366 if( fbi->pcr & PCR_TFT )
367 width = 16;
368 else
369 width = 1 << ((fbi->pcr >> 28) & 0x3);
370
371 switch(width) {
372 case 16:
373 imx_gpio_mode(PD30_PF_LD15);
374 imx_gpio_mode(PD29_PF_LD14);
375 imx_gpio_mode(PD28_PF_LD13);
376 imx_gpio_mode(PD27_PF_LD12);
377 imx_gpio_mode(PD26_PF_LD11);
378 imx_gpio_mode(PD25_PF_LD10);
379 imx_gpio_mode(PD24_PF_LD9);
380 imx_gpio_mode(PD23_PF_LD8);
381 case 8:
382 imx_gpio_mode(PD22_PF_LD7);
383 imx_gpio_mode(PD21_PF_LD6);
384 imx_gpio_mode(PD20_PF_LD5);
385 imx_gpio_mode(PD19_PF_LD4);
386 case 4:
387 imx_gpio_mode(PD18_PF_LD3);
388 imx_gpio_mode(PD17_PF_LD2);
389 case 2:
390 imx_gpio_mode(PD16_PF_LD1);
391 case 1:
392 imx_gpio_mode(PD15_PF_LD0);
393 }
394
395 /* initialize GPIOs */
396 imx_gpio_mode(PD6_PF_LSCLK);
397 imx_gpio_mode(PD11_PF_CONTRAST);
398 imx_gpio_mode(PD14_PF_FLM_VSYNC);
399 imx_gpio_mode(PD13_PF_LP_HSYNC);
400 imx_gpio_mode(PD12_PF_ACD_OE);
401
402 /* These are only needed for Sharp HR TFT displays */
403 if (fbi->pcr & PCR_SHARP) {
404 imx_gpio_mode(PD7_PF_REV);
405 imx_gpio_mode(PD8_PF_CLS);
406 imx_gpio_mode(PD9_PF_PS);
407 imx_gpio_mode(PD10_PF_SPL_SPR);
408 }
409}
410
411#ifdef CONFIG_PM 488#ifdef CONFIG_PM
412/* 489/*
413 * Power management hooks. Note that we won't be called from IRQ context, 490 * Power management hooks. Note that we won't be called from IRQ context,
@@ -416,7 +493,8 @@ static void imxfb_setup_gpio(struct imxfb_info *fbi)
416static int imxfb_suspend(struct platform_device *dev, pm_message_t state) 493static int imxfb_suspend(struct platform_device *dev, pm_message_t state)
417{ 494{
418 struct imxfb_info *fbi = platform_get_drvdata(dev); 495 struct imxfb_info *fbi = platform_get_drvdata(dev);
419 pr_debug("%s\n",__func__); 496
497 pr_debug("%s\n", __func__);
420 498
421 imxfb_disable_controller(fbi); 499 imxfb_disable_controller(fbi);
422 return 0; 500 return 0;
@@ -425,7 +503,8 @@ static int imxfb_suspend(struct platform_device *dev, pm_message_t state)
425static int imxfb_resume(struct platform_device *dev) 503static int imxfb_resume(struct platform_device *dev)
426{ 504{
427 struct imxfb_info *fbi = platform_get_drvdata(dev); 505 struct imxfb_info *fbi = platform_get_drvdata(dev);
428 pr_debug("%s\n",__func__); 506
507 pr_debug("%s\n", __func__);
429 508
430 imxfb_enable_controller(fbi); 509 imxfb_enable_controller(fbi);
431 return 0; 510 return 0;
@@ -435,149 +514,136 @@ static int imxfb_resume(struct platform_device *dev)
435#define imxfb_resume NULL 514#define imxfb_resume NULL
436#endif 515#endif
437 516
438static int __init imxfb_init_fbinfo(struct device *dev) 517static int __init imxfb_init_fbinfo(struct platform_device *pdev)
439{ 518{
440 struct imxfb_mach_info *inf = dev->platform_data; 519 struct imx_fb_platform_data *pdata = pdev->dev.platform_data;
441 struct fb_info *info = dev_get_drvdata(dev); 520 struct fb_info *info = dev_get_drvdata(&pdev->dev);
442 struct imxfb_info *fbi = info->par; 521 struct imxfb_info *fbi = info->par;
443 522
444 pr_debug("%s\n",__func__); 523 pr_debug("%s\n",__func__);
445 524
446 info->pseudo_palette = kmalloc( sizeof(u32) * 16, GFP_KERNEL); 525 info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
447 if (!info->pseudo_palette) 526 if (!info->pseudo_palette)
448 return -ENOMEM; 527 return -ENOMEM;
449 528
450 memset(fbi, 0, sizeof(struct imxfb_info)); 529 memset(fbi, 0, sizeof(struct imxfb_info));
451 fbi->dev = dev;
452 530
453 strlcpy(info->fix.id, IMX_NAME, sizeof(info->fix.id)); 531 strlcpy(info->fix.id, IMX_NAME, sizeof(info->fix.id));
454 532
455 info->fix.type = FB_TYPE_PACKED_PIXELS; 533 info->fix.type = FB_TYPE_PACKED_PIXELS;
456 info->fix.type_aux = 0; 534 info->fix.type_aux = 0;
457 info->fix.xpanstep = 0; 535 info->fix.xpanstep = 0;
458 info->fix.ypanstep = 0; 536 info->fix.ypanstep = 0;
459 info->fix.ywrapstep = 0; 537 info->fix.ywrapstep = 0;
460 info->fix.accel = FB_ACCEL_NONE; 538 info->fix.accel = FB_ACCEL_NONE;
461 539
462 info->var.nonstd = 0; 540 info->var.nonstd = 0;
463 info->var.activate = FB_ACTIVATE_NOW; 541 info->var.activate = FB_ACTIVATE_NOW;
464 info->var.height = -1; 542 info->var.height = -1;
465 info->var.width = -1; 543 info->var.width = -1;
466 info->var.accel_flags = 0; 544 info->var.accel_flags = 0;
467 info->var.vmode = FB_VMODE_NONINTERLACED; 545 info->var.vmode = FB_VMODE_NONINTERLACED;
468 546
469 info->fbops = &imxfb_ops; 547 info->fbops = &imxfb_ops;
470 info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST; 548 info->flags = FBINFO_FLAG_DEFAULT |
471 549 FBINFO_READS_FAST;
472 fbi->rgb[RGB_16] = &def_rgb_16; 550
473 fbi->rgb[RGB_8] = &def_rgb_8; 551 fbi->max_xres = pdata->xres;
474 552 info->var.xres = pdata->xres;
475 fbi->max_xres = inf->xres; 553 info->var.xres_virtual = pdata->xres;
476 info->var.xres = inf->xres; 554 fbi->max_yres = pdata->yres;
477 info->var.xres_virtual = inf->xres; 555 info->var.yres = pdata->yres;
478 fbi->max_yres = inf->yres; 556 info->var.yres_virtual = pdata->yres;
479 info->var.yres = inf->yres; 557 fbi->max_bpp = pdata->bpp;
480 info->var.yres_virtual = inf->yres; 558 info->var.bits_per_pixel = pdata->bpp;
481 fbi->max_bpp = inf->bpp; 559 info->var.nonstd = pdata->nonstd;
482 info->var.bits_per_pixel = inf->bpp; 560 info->var.pixclock = pdata->pixclock;
483 info->var.nonstd = inf->nonstd; 561 info->var.hsync_len = pdata->hsync_len;
484 info->var.pixclock = inf->pixclock; 562 info->var.left_margin = pdata->left_margin;
485 info->var.hsync_len = inf->hsync_len; 563 info->var.right_margin = pdata->right_margin;
486 info->var.left_margin = inf->left_margin; 564 info->var.vsync_len = pdata->vsync_len;
487 info->var.right_margin = inf->right_margin; 565 info->var.upper_margin = pdata->upper_margin;
488 info->var.vsync_len = inf->vsync_len; 566 info->var.lower_margin = pdata->lower_margin;
489 info->var.upper_margin = inf->upper_margin; 567 info->var.sync = pdata->sync;
490 info->var.lower_margin = inf->lower_margin; 568 info->var.grayscale = pdata->cmap_greyscale;
491 info->var.sync = inf->sync; 569 fbi->cmap_inverse = pdata->cmap_inverse;
492 info->var.grayscale = inf->cmap_greyscale; 570 fbi->cmap_static = pdata->cmap_static;
493 fbi->cmap_inverse = inf->cmap_inverse; 571 fbi->pcr = pdata->pcr;
494 fbi->cmap_static = inf->cmap_static; 572 fbi->lscr1 = pdata->lscr1;
495 fbi->pcr = inf->pcr; 573 fbi->dmacr = pdata->dmacr;
496 fbi->lscr1 = inf->lscr1; 574 fbi->pwmr = pdata->pwmr;
497 fbi->dmacr = inf->dmacr; 575 fbi->lcd_power = pdata->lcd_power;
498 fbi->pwmr = inf->pwmr; 576 fbi->backlight_power = pdata->backlight_power;
499 fbi->lcd_power = inf->lcd_power;
500 fbi->backlight_power = inf->backlight_power;
501 info->fix.smem_len = fbi->max_xres * fbi->max_yres * 577 info->fix.smem_len = fbi->max_xres * fbi->max_yres *
502 fbi->max_bpp / 8; 578 fbi->max_bpp / 8;
503 579
504 return 0; 580 return 0;
505} 581}
506 582
507/*
508 * Allocates the DRAM memory for the frame buffer. This buffer is
509 * remapped into a non-cached, non-buffered, memory region to
510 * allow pixel writes to occur without flushing the cache.
511 * Once this area is remapped, all virtual memory access to the
512 * video memory should occur at the new region.
513 */
514static int __init imxfb_map_video_memory(struct fb_info *info)
515{
516 struct imxfb_info *fbi = info->par;
517
518 fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
519 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
520 &fbi->map_dma,GFP_KERNEL);
521
522 if (fbi->map_cpu) {
523 info->screen_base = fbi->map_cpu;
524 fbi->screen_cpu = fbi->map_cpu;
525 fbi->screen_dma = fbi->map_dma;
526 info->fix.smem_start = fbi->screen_dma;
527 }
528
529 return fbi->map_cpu ? 0 : -ENOMEM;
530}
531
532static int __init imxfb_probe(struct platform_device *pdev) 583static int __init imxfb_probe(struct platform_device *pdev)
533{ 584{
534 struct imxfb_info *fbi; 585 struct imxfb_info *fbi;
535 struct fb_info *info; 586 struct fb_info *info;
536 struct imxfb_mach_info *inf; 587 struct imx_fb_platform_data *pdata;
537 struct resource *res; 588 struct resource *res;
538 int ret; 589 int ret;
539 590
540 printk("i.MX Framebuffer driver\n"); 591 printk("i.MX Framebuffer driver\n");
541 592
542 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 593 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
543 if(!res) 594 if (!res)
544 return -ENODEV; 595 return -ENODEV;
545 596
546 inf = pdev->dev.platform_data; 597 pdata = pdev->dev.platform_data;
547 if(!inf) { 598 if (!pdata) {
548 dev_err(&pdev->dev,"No platform_data available\n"); 599 dev_err(&pdev->dev,"No platform_data available\n");
549 return -ENOMEM; 600 return -ENOMEM;
550 } 601 }
551 602
552 info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev); 603 info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev);
553 if(!info) 604 if (!info)
554 return -ENOMEM; 605 return -ENOMEM;
555 606
556 fbi = info->par; 607 fbi = info->par;
557 608
558 platform_set_drvdata(pdev, info); 609 platform_set_drvdata(pdev, info);
559 610
560 ret = imxfb_init_fbinfo(&pdev->dev); 611 ret = imxfb_init_fbinfo(pdev);
561 if( ret < 0 ) 612 if (ret < 0)
562 goto failed_init; 613 goto failed_init;
563 614
564 res = request_mem_region(res->start, res->end - res->start + 1, "IMXFB"); 615 res = request_mem_region(res->start, resource_size(res),
616 DRIVER_NAME);
565 if (!res) { 617 if (!res) {
566 ret = -EBUSY; 618 ret = -EBUSY;
567 goto failed_regs; 619 goto failed_req;
620 }
621
622 fbi->regs = ioremap(res->start, resource_size(res));
623 if (fbi->regs == NULL) {
624 printk(KERN_ERR"Cannot map frame buffer registers\n");
625 goto failed_ioremap;
568 } 626 }
569 627
570 if (!inf->fixed_screen_cpu) { 628 if (!pdata->fixed_screen_cpu) {
571 ret = imxfb_map_video_memory(info); 629 fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
572 if (ret) { 630 fbi->map_cpu = dma_alloc_writecombine(&pdev->dev,
631 fbi->map_size, &fbi->map_dma, GFP_KERNEL);
632
633 if (!fbi->map_cpu) {
573 dev_err(&pdev->dev, "Failed to allocate video RAM: %d\n", ret); 634 dev_err(&pdev->dev, "Failed to allocate video RAM: %d\n", ret);
574 ret = -ENOMEM; 635 ret = -ENOMEM;
575 goto failed_map; 636 goto failed_map;
576 } 637 }
638
639 info->screen_base = fbi->map_cpu;
640 fbi->screen_cpu = fbi->map_cpu;
641 fbi->screen_dma = fbi->map_dma;
642 info->fix.smem_start = fbi->screen_dma;
577 } else { 643 } else {
578 /* Fixed framebuffer mapping enables location of the screen in eSRAM */ 644 /* Fixed framebuffer mapping enables location of the screen in eSRAM */
579 fbi->map_cpu = inf->fixed_screen_cpu; 645 fbi->map_cpu = pdata->fixed_screen_cpu;
580 fbi->map_dma = inf->fixed_screen_dma; 646 fbi->map_dma = pdata->fixed_screen_dma;
581 info->screen_base = fbi->map_cpu; 647 info->screen_base = fbi->map_cpu;
582 fbi->screen_cpu = fbi->map_cpu; 648 fbi->screen_cpu = fbi->map_cpu;
583 fbi->screen_dma = fbi->map_dma; 649 fbi->screen_dma = fbi->map_dma;
@@ -590,12 +656,10 @@ static int __init imxfb_probe(struct platform_device *pdev)
590 */ 656 */
591 imxfb_check_var(&info->var, info); 657 imxfb_check_var(&info->var, info);
592 658
593 ret = fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0); 659 ret = fb_alloc_cmap(&info->cmap, 1 << info->var.bits_per_pixel, 0);
594 if (ret < 0) 660 if (ret < 0)
595 goto failed_cmap; 661 goto failed_cmap;
596 662
597 imxfb_setup_gpio(fbi);
598
599 imxfb_set_par(info); 663 imxfb_set_par(info);
600 ret = register_framebuffer(info); 664 ret = register_framebuffer(info);
601 if (ret < 0) { 665 if (ret < 0) {
@@ -610,20 +674,22 @@ static int __init imxfb_probe(struct platform_device *pdev)
610failed_register: 674failed_register:
611 fb_dealloc_cmap(&info->cmap); 675 fb_dealloc_cmap(&info->cmap);
612failed_cmap: 676failed_cmap:
613 if (!inf->fixed_screen_cpu) 677 if (!pdata->fixed_screen_cpu)
614 dma_free_writecombine(&pdev->dev,fbi->map_size,fbi->map_cpu, 678 dma_free_writecombine(&pdev->dev,fbi->map_size,fbi->map_cpu,
615 fbi->map_dma); 679 fbi->map_dma);
616failed_map: 680failed_map:
617 kfree(info->pseudo_palette); 681 iounmap(fbi->regs);
618failed_regs: 682failed_ioremap:
619 release_mem_region(res->start, res->end - res->start); 683 release_mem_region(res->start, res->end - res->start);
684failed_req:
685 kfree(info->pseudo_palette);
620failed_init: 686failed_init:
621 platform_set_drvdata(pdev, NULL); 687 platform_set_drvdata(pdev, NULL);
622 framebuffer_release(info); 688 framebuffer_release(info);
623 return ret; 689 return ret;
624} 690}
625 691
626static int imxfb_remove(struct platform_device *pdev) 692static int __devexit imxfb_remove(struct platform_device *pdev)
627{ 693{
628 struct fb_info *info = platform_get_drvdata(pdev); 694 struct fb_info *info = platform_get_drvdata(pdev);
629 struct imxfb_info *fbi = info->par; 695 struct imxfb_info *fbi = info->par;
@@ -639,6 +705,7 @@ static int imxfb_remove(struct platform_device *pdev)
639 kfree(info->pseudo_palette); 705 kfree(info->pseudo_palette);
640 framebuffer_release(info); 706 framebuffer_release(info);
641 707
708 iounmap(fbi->regs);
642 release_mem_region(res->start, res->end - res->start + 1); 709 release_mem_region(res->start, res->end - res->start + 1);
643 platform_set_drvdata(pdev, NULL); 710 platform_set_drvdata(pdev, NULL);
644 711
@@ -653,19 +720,18 @@ void imxfb_shutdown(struct platform_device * dev)
653} 720}
654 721
655static struct platform_driver imxfb_driver = { 722static struct platform_driver imxfb_driver = {
656 .probe = imxfb_probe,
657 .suspend = imxfb_suspend, 723 .suspend = imxfb_suspend,
658 .resume = imxfb_resume, 724 .resume = imxfb_resume,
659 .remove = imxfb_remove, 725 .remove = __devexit_p(imxfb_remove),
660 .shutdown = imxfb_shutdown, 726 .shutdown = imxfb_shutdown,
661 .driver = { 727 .driver = {
662 .name = "imx-fb", 728 .name = DRIVER_NAME,
663 }, 729 },
664}; 730};
665 731
666int __init imxfb_init(void) 732int __init imxfb_init(void)
667{ 733{
668 return platform_driver_register(&imxfb_driver); 734 return platform_driver_probe(&imxfb_driver, imxfb_probe);
669} 735}
670 736
671static void __exit imxfb_cleanup(void) 737static void __exit imxfb_cleanup(void)
diff --git a/drivers/video/imxfb.h b/drivers/video/imxfb.h
deleted file mode 100644
index e837a8b48eb8..000000000000
--- a/drivers/video/imxfb.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * linux/drivers/video/imxfb.h
3 *
4 * Freescale i.MX Frame Buffer device driver
5 *
6 * Copyright (C) 2004 S.Hauer, Pengutronix
7 *
8 * Copyright (C) 1999 Eric A. Thomas
9 * Based on acornfb.c Copyright (C) Russell King.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive
13 * for more details.
14 */
15
16/*
17 * These are the bitfields for each
18 * display depth that we support.
19 */
20struct imxfb_rgb {
21 struct fb_bitfield red;
22 struct fb_bitfield green;
23 struct fb_bitfield blue;
24 struct fb_bitfield transp;
25};
26
27#define RGB_16 (0)
28#define RGB_8 (1)
29#define NR_RGB 2
30
31struct imxfb_info {
32 struct device *dev;
33 struct imxfb_rgb *rgb[NR_RGB];
34
35 u_int max_bpp;
36 u_int max_xres;
37 u_int max_yres;
38
39 /*
40 * These are the addresses we mapped
41 * the framebuffer memory region to.
42 */
43 dma_addr_t map_dma;
44 u_char * map_cpu;
45 u_int map_size;
46
47 u_char * screen_cpu;
48 dma_addr_t screen_dma;
49 u_int palette_size;
50
51 dma_addr_t dbar1;
52 dma_addr_t dbar2;
53
54 u_int pcr;
55 u_int pwmr;
56 u_int lscr1;
57 u_int dmacr;
58 u_int cmap_inverse:1,
59 cmap_static:1,
60 unused:30;
61
62 void (*lcd_power)(int);
63 void (*backlight_power)(int);
64};
65
66#define IMX_NAME "IMX"
67
68/*
69 * Minimum X and Y resolutions
70 */
71#define MIN_XRES 64
72#define MIN_YRES 64
73
diff --git a/drivers/video/macfb.c b/drivers/video/macfb.c
index b790ddff76f9..ee380d5f3410 100644
--- a/drivers/video/macfb.c
+++ b/drivers/video/macfb.c
@@ -164,7 +164,6 @@ static struct fb_var_screeninfo macfb_defined = {
164}; 164};
165 165
166static struct fb_fix_screeninfo macfb_fix = { 166static struct fb_fix_screeninfo macfb_fix = {
167 .id = "Macintosh ",
168 .type = FB_TYPE_PACKED_PIXELS, 167 .type = FB_TYPE_PACKED_PIXELS,
169 .accel = FB_ACCEL_NONE, 168 .accel = FB_ACCEL_NONE,
170}; 169};
@@ -760,22 +759,22 @@ static int __init macfb_init(void)
760 759
761 switch(ndev->dr_hw) { 760 switch(ndev->dr_hw) {
762 case NUBUS_DRHW_APPLE_MDC: 761 case NUBUS_DRHW_APPLE_MDC:
763 strcat( macfb_fix.id, "Display Card" ); 762 strcpy(macfb_fix.id, "Mac Disp. Card");
764 macfb_setpalette = mdc_setpalette; 763 macfb_setpalette = mdc_setpalette;
765 macfb_defined.activate = FB_ACTIVATE_NOW; 764 macfb_defined.activate = FB_ACTIVATE_NOW;
766 break; 765 break;
767 case NUBUS_DRHW_APPLE_TFB: 766 case NUBUS_DRHW_APPLE_TFB:
768 strcat( macfb_fix.id, "Toby" ); 767 strcpy(macfb_fix.id, "Toby");
769 macfb_setpalette = toby_setpalette; 768 macfb_setpalette = toby_setpalette;
770 macfb_defined.activate = FB_ACTIVATE_NOW; 769 macfb_defined.activate = FB_ACTIVATE_NOW;
771 break; 770 break;
772 case NUBUS_DRHW_APPLE_JET: 771 case NUBUS_DRHW_APPLE_JET:
773 strcat( macfb_fix.id, "Jet"); 772 strcpy(macfb_fix.id, "Jet");
774 macfb_setpalette = jet_setpalette; 773 macfb_setpalette = jet_setpalette;
775 macfb_defined.activate = FB_ACTIVATE_NOW; 774 macfb_defined.activate = FB_ACTIVATE_NOW;
776 break; 775 break;
777 default: 776 default:
778 strcat( macfb_fix.id, "Generic NuBus" ); 777 strcpy(macfb_fix.id, "Generic NuBus");
779 break; 778 break;
780 } 779 }
781 } 780 }
@@ -786,21 +785,11 @@ static int __init macfb_init(void)
786 if (!video_is_nubus) 785 if (!video_is_nubus)
787 switch( mac_bi_data.id ) 786 switch( mac_bi_data.id )
788 { 787 {
789 /* These don't have onboard video. Eventually, we may
790 be able to write separate framebuffer drivers for
791 them (tobyfb.c, hiresfb.c, etc, etc) */
792 case MAC_MODEL_II:
793 case MAC_MODEL_IIX:
794 case MAC_MODEL_IICX:
795 case MAC_MODEL_IIFX:
796 strcat( macfb_fix.id, "Generic NuBus" );
797 break;
798
799 /* Valkyrie Quadras */ 788 /* Valkyrie Quadras */
800 case MAC_MODEL_Q630: 789 case MAC_MODEL_Q630:
801 /* I'm not sure about this one */ 790 /* I'm not sure about this one */
802 case MAC_MODEL_P588: 791 case MAC_MODEL_P588:
803 strcat( macfb_fix.id, "Valkyrie built-in" ); 792 strcpy(macfb_fix.id, "Valkyrie");
804 macfb_setpalette = valkyrie_setpalette; 793 macfb_setpalette = valkyrie_setpalette;
805 macfb_defined.activate = FB_ACTIVATE_NOW; 794 macfb_defined.activate = FB_ACTIVATE_NOW;
806 valkyrie_cmap_regs = ioremap(DAC_BASE, 0x1000); 795 valkyrie_cmap_regs = ioremap(DAC_BASE, 0x1000);
@@ -823,7 +812,7 @@ static int __init macfb_init(void)
823 case MAC_MODEL_Q700: 812 case MAC_MODEL_Q700:
824 case MAC_MODEL_Q900: 813 case MAC_MODEL_Q900:
825 case MAC_MODEL_Q950: 814 case MAC_MODEL_Q950:
826 strcat( macfb_fix.id, "DAFB built-in" ); 815 strcpy(macfb_fix.id, "DAFB");
827 macfb_setpalette = dafb_setpalette; 816 macfb_setpalette = dafb_setpalette;
828 macfb_defined.activate = FB_ACTIVATE_NOW; 817 macfb_defined.activate = FB_ACTIVATE_NOW;
829 dafb_cmap_regs = ioremap(DAFB_BASE, 0x1000); 818 dafb_cmap_regs = ioremap(DAFB_BASE, 0x1000);
@@ -831,7 +820,7 @@ static int __init macfb_init(void)
831 820
832 /* LC II uses the V8 framebuffer */ 821 /* LC II uses the V8 framebuffer */
833 case MAC_MODEL_LCII: 822 case MAC_MODEL_LCII:
834 strcat( macfb_fix.id, "V8 built-in" ); 823 strcpy(macfb_fix.id, "V8");
835 macfb_setpalette = v8_brazil_setpalette; 824 macfb_setpalette = v8_brazil_setpalette;
836 macfb_defined.activate = FB_ACTIVATE_NOW; 825 macfb_defined.activate = FB_ACTIVATE_NOW;
837 v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000); 826 v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000);
@@ -843,7 +832,7 @@ static int __init macfb_init(void)
843 case MAC_MODEL_IIVI: 832 case MAC_MODEL_IIVI:
844 case MAC_MODEL_IIVX: 833 case MAC_MODEL_IIVX:
845 case MAC_MODEL_P600: 834 case MAC_MODEL_P600:
846 strcat( macfb_fix.id, "Brazil built-in" ); 835 strcpy(macfb_fix.id, "Brazil");
847 macfb_setpalette = v8_brazil_setpalette; 836 macfb_setpalette = v8_brazil_setpalette;
848 macfb_defined.activate = FB_ACTIVATE_NOW; 837 macfb_defined.activate = FB_ACTIVATE_NOW;
849 v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000); 838 v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000);
@@ -860,7 +849,7 @@ static int __init macfb_init(void)
860 case MAC_MODEL_P460: 849 case MAC_MODEL_P460:
861 macfb_setpalette = v8_brazil_setpalette; 850 macfb_setpalette = v8_brazil_setpalette;
862 macfb_defined.activate = FB_ACTIVATE_NOW; 851 macfb_defined.activate = FB_ACTIVATE_NOW;
863 strcat( macfb_fix.id, "Sonora built-in" ); 852 strcpy(macfb_fix.id, "Sonora");
864 v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000); 853 v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000);
865 break; 854 break;
866 855
@@ -871,7 +860,7 @@ static int __init macfb_init(void)
871 case MAC_MODEL_IISI: 860 case MAC_MODEL_IISI:
872 macfb_setpalette = rbv_setpalette; 861 macfb_setpalette = rbv_setpalette;
873 macfb_defined.activate = FB_ACTIVATE_NOW; 862 macfb_defined.activate = FB_ACTIVATE_NOW;
874 strcat( macfb_fix.id, "RBV built-in" ); 863 strcpy(macfb_fix.id, "RBV");
875 rbv_cmap_regs = ioremap(DAC_BASE, 0x1000); 864 rbv_cmap_regs = ioremap(DAC_BASE, 0x1000);
876 break; 865 break;
877 866
@@ -880,7 +869,7 @@ static int __init macfb_init(void)
880 case MAC_MODEL_C660: 869 case MAC_MODEL_C660:
881 macfb_setpalette = civic_setpalette; 870 macfb_setpalette = civic_setpalette;
882 macfb_defined.activate = FB_ACTIVATE_NOW; 871 macfb_defined.activate = FB_ACTIVATE_NOW;
883 strcat( macfb_fix.id, "Civic built-in" ); 872 strcpy(macfb_fix.id, "Civic");
884 civic_cmap_regs = ioremap(CIVIC_BASE, 0x1000); 873 civic_cmap_regs = ioremap(CIVIC_BASE, 0x1000);
885 break; 874 break;
886 875
@@ -901,7 +890,7 @@ static int __init macfb_init(void)
901 v8_brazil_cmap_regs = 890 v8_brazil_cmap_regs =
902 ioremap(DAC_BASE, 0x1000); 891 ioremap(DAC_BASE, 0x1000);
903 } 892 }
904 strcat( macfb_fix.id, "LC built-in" ); 893 strcpy(macfb_fix.id, "LC");
905 break; 894 break;
906 /* We think this may be like the LC II */ 895 /* We think this may be like the LC II */
907 case MAC_MODEL_CCL: 896 case MAC_MODEL_CCL:
@@ -911,18 +900,18 @@ static int __init macfb_init(void)
911 v8_brazil_cmap_regs = 900 v8_brazil_cmap_regs =
912 ioremap(DAC_BASE, 0x1000); 901 ioremap(DAC_BASE, 0x1000);
913 } 902 }
914 strcat( macfb_fix.id, "Color Classic built-in" ); 903 strcpy(macfb_fix.id, "Color Classic");
915 break; 904 break;
916 905
917 /* And we *do* mean "weirdos" */ 906 /* And we *do* mean "weirdos" */
918 case MAC_MODEL_TV: 907 case MAC_MODEL_TV:
919 strcat( macfb_fix.id, "Mac TV built-in" ); 908 strcpy(macfb_fix.id, "Mac TV");
920 break; 909 break;
921 910
922 /* These don't have colour, so no need to worry */ 911 /* These don't have colour, so no need to worry */
923 case MAC_MODEL_SE30: 912 case MAC_MODEL_SE30:
924 case MAC_MODEL_CLII: 913 case MAC_MODEL_CLII:
925 strcat( macfb_fix.id, "Monochrome built-in" ); 914 strcpy(macfb_fix.id, "Monochrome");
926 break; 915 break;
927 916
928 /* Powerbooks are particularly difficult. Many of 917 /* Powerbooks are particularly difficult. Many of
@@ -935,7 +924,7 @@ static int __init macfb_init(void)
935 case MAC_MODEL_PB140: 924 case MAC_MODEL_PB140:
936 case MAC_MODEL_PB145: 925 case MAC_MODEL_PB145:
937 case MAC_MODEL_PB170: 926 case MAC_MODEL_PB170:
938 strcat( macfb_fix.id, "DDC built-in" ); 927 strcpy(macfb_fix.id, "DDC");
939 break; 928 break;
940 929
941 /* Internal is GSC, External (if present) is ViSC */ 930 /* Internal is GSC, External (if present) is ViSC */
@@ -945,13 +934,13 @@ static int __init macfb_init(void)
945 case MAC_MODEL_PB180: 934 case MAC_MODEL_PB180:
946 case MAC_MODEL_PB210: 935 case MAC_MODEL_PB210:
947 case MAC_MODEL_PB230: 936 case MAC_MODEL_PB230:
948 strcat( macfb_fix.id, "GSC built-in" ); 937 strcpy(macfb_fix.id, "GSC");
949 break; 938 break;
950 939
951 /* Internal is TIM, External is ViSC */ 940 /* Internal is TIM, External is ViSC */
952 case MAC_MODEL_PB165C: 941 case MAC_MODEL_PB165C:
953 case MAC_MODEL_PB180C: 942 case MAC_MODEL_PB180C:
954 strcat( macfb_fix.id, "TIM built-in" ); 943 strcpy(macfb_fix.id, "TIM");
955 break; 944 break;
956 945
957 /* Internal is CSC, External is Keystone+Ariel. */ 946 /* Internal is CSC, External is Keystone+Ariel. */
@@ -963,12 +952,12 @@ static int __init macfb_init(void)
963 case MAC_MODEL_PB280C: 952 case MAC_MODEL_PB280C:
964 macfb_setpalette = csc_setpalette; 953 macfb_setpalette = csc_setpalette;
965 macfb_defined.activate = FB_ACTIVATE_NOW; 954 macfb_defined.activate = FB_ACTIVATE_NOW;
966 strcat( macfb_fix.id, "CSC built-in" ); 955 strcpy(macfb_fix.id, "CSC");
967 csc_cmap_regs = ioremap(CSC_BASE, 0x1000); 956 csc_cmap_regs = ioremap(CSC_BASE, 0x1000);
968 break; 957 break;
969 958
970 default: 959 default:
971 strcat( macfb_fix.id, "Unknown/Unsupported built-in" ); 960 strcpy(macfb_fix.id, "Unknown");
972 break; 961 break;
973 } 962 }
974 963
@@ -978,16 +967,23 @@ static int __init macfb_init(void)
978 fb_info.pseudo_palette = pseudo_palette; 967 fb_info.pseudo_palette = pseudo_palette;
979 fb_info.flags = FBINFO_DEFAULT; 968 fb_info.flags = FBINFO_DEFAULT;
980 969
981 fb_alloc_cmap(&fb_info.cmap, video_cmap_len, 0); 970 err = fb_alloc_cmap(&fb_info.cmap, video_cmap_len, 0);
971 if (err)
972 goto fail_unmap;
982 973
983 err = register_framebuffer(&fb_info); 974 err = register_framebuffer(&fb_info);
984 if (!err) 975 if (err)
985 printk("fb%d: %s frame buffer device\n", 976 goto fail_dealloc;
986 fb_info.node, fb_info.fix.id); 977
987 else { 978 printk("fb%d: %s frame buffer device\n",
988 iounmap(fb_info.screen_base); 979 fb_info.node, fb_info.fix.id);
989 iounmap_macfb(); 980 return 0;
990 } 981
982fail_dealloc:
983 fb_dealloc_cmap(&fb_info.cmap);
984fail_unmap:
985 iounmap(fb_info.screen_base);
986 iounmap_macfb();
991 return err; 987 return err;
992} 988}
993 989
diff --git a/drivers/video/mb862xx/mb862xxfb.c b/drivers/video/mb862xx/mb862xxfb.c
index 38718d95fbb9..fb64234a3825 100644
--- a/drivers/video/mb862xx/mb862xxfb.c
+++ b/drivers/video/mb862xx/mb862xxfb.c
@@ -927,9 +927,9 @@ static int __devinit mb862xx_pci_probe(struct pci_dev *pdev,
927 } 927 }
928 928
929 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n", 929 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
930 (u64)par->fb_base_phys, (ulong)par->mapped_vram); 930 (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
931 dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n", 931 dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
932 (u64)par->mmio_base_phys, (ulong)par->mmio_len); 932 (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
933 933
934 if (mb862xx_pci_gdc_init(par)) 934 if (mb862xx_pci_gdc_init(par))
935 goto io_unmap; 935 goto io_unmap;
diff --git a/drivers/video/omap/Makefile b/drivers/video/omap/Makefile
index 99da8b6d2c36..ed13889c1162 100644
--- a/drivers/video/omap/Makefile
+++ b/drivers/video/omap/Makefile
@@ -23,7 +23,6 @@ objs-y$(CONFIG_MACH_OMAP_PALMZ71) += lcd_palmz71.o
23objs-$(CONFIG_ARCH_OMAP16XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1610.o 23objs-$(CONFIG_ARCH_OMAP16XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1610.o
24objs-$(CONFIG_ARCH_OMAP15XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1510.o 24objs-$(CONFIG_ARCH_OMAP15XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1510.o
25objs-y$(CONFIG_MACH_OMAP_OSK) += lcd_osk.o 25objs-y$(CONFIG_MACH_OMAP_OSK) += lcd_osk.o
26objs-y$(CONFIG_MACH_SX1) += lcd_sx1.o
27 26
28omapfb-objs := $(objs-yy) 27omapfb-objs := $(objs-yy)
29 28
diff --git a/drivers/video/omap/lcd_sx1.c b/drivers/video/omap/lcd_sx1.c
deleted file mode 100644
index e55de201b8ff..000000000000
--- a/drivers/video/omap/lcd_sx1.c
+++ /dev/null
@@ -1,327 +0,0 @@
1/*
2 * LCD panel support for the Siemens SX1 mobile phone
3 *
4 * Current version : Vovan888@gmail.com, great help from FCA00000
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25
26#include <mach/gpio.h>
27#include <mach/omapfb.h>
28#include <mach/mcbsp.h>
29#include <mach/mux.h>
30
31/*
32 * OMAP310 GPIO registers
33 */
34#define GPIO_DATA_INPUT 0xfffce000
35#define GPIO_DATA_OUTPUT 0xfffce004
36#define GPIO_DIR_CONTROL 0xfffce008
37#define GPIO_INT_CONTROL 0xfffce00c
38#define GPIO_INT_MASK 0xfffce010
39#define GPIO_INT_STATUS 0xfffce014
40#define GPIO_PIN_CONTROL 0xfffce018
41
42
43#define A_LCD_SSC_RD 3
44#define A_LCD_SSC_SD 7
45#define _A_LCD_RESET 9
46#define _A_LCD_SSC_CS 12
47#define _A_LCD_SSC_A0 13
48
49#define DSP_REG 0xE1017024
50
51const unsigned char INIT_1[12] = {
52 0x1C, 0x02, 0x88, 0x00, 0x1E, 0xE0, 0x00, 0xDC, 0x00, 0x02, 0x00
53};
54
55const unsigned char INIT_2[127] = {
56 0x15, 0x00, 0x29, 0x00, 0x3E, 0x00, 0x51, 0x00,
57 0x65, 0x00, 0x7A, 0x00, 0x8D, 0x00, 0xA1, 0x00,
58 0xB6, 0x00, 0xC7, 0x00, 0xD8, 0x00, 0xEB, 0x00,
59 0xFB, 0x00, 0x0B, 0x01, 0x1B, 0x01, 0x27, 0x01,
60 0x34, 0x01, 0x41, 0x01, 0x4C, 0x01, 0x55, 0x01,
61 0x5F, 0x01, 0x68, 0x01, 0x70, 0x01, 0x78, 0x01,
62 0x7E, 0x01, 0x86, 0x01, 0x8C, 0x01, 0x94, 0x01,
63 0x9B, 0x01, 0xA1, 0x01, 0xA4, 0x01, 0xA9, 0x01,
64 0xAD, 0x01, 0xB2, 0x01, 0xB7, 0x01, 0xBC, 0x01,
65 0xC0, 0x01, 0xC4, 0x01, 0xC8, 0x01, 0xCB, 0x01,
66 0xCF, 0x01, 0xD2, 0x01, 0xD5, 0x01, 0xD8, 0x01,
67 0xDB, 0x01, 0xE0, 0x01, 0xE3, 0x01, 0xE6, 0x01,
68 0xE8, 0x01, 0xEB, 0x01, 0xEE, 0x01, 0xF1, 0x01,
69 0xF3, 0x01, 0xF8, 0x01, 0xF9, 0x01, 0xFC, 0x01,
70 0x00, 0x02, 0x03, 0x02, 0x07, 0x02, 0x09, 0x02,
71 0x0E, 0x02, 0x13, 0x02, 0x1C, 0x02, 0x00
72};
73
74const unsigned char INIT_3[15] = {
75 0x14, 0x26, 0x33, 0x3D, 0x45, 0x4D, 0x53, 0x59,
76 0x5E, 0x63, 0x67, 0x6D, 0x71, 0x78, 0xFF
77};
78
79static void epson_sendbyte(int flag, unsigned char byte)
80{
81 int i, shifter = 0x80;
82
83 if (!flag)
84 gpio_set_value(_A_LCD_SSC_A0, 0);
85 mdelay(2);
86 gpio_set_value(A_LCD_SSC_RD, 1);
87
88 gpio_set_value(A_LCD_SSC_SD, flag);
89
90 OMAP_MCBSP_WRITE(OMAP1510_MCBSP3_BASE, PCR0, 0x2200);
91 OMAP_MCBSP_WRITE(OMAP1510_MCBSP3_BASE, PCR0, 0x2202);
92 for (i = 0; i < 8; i++) {
93 OMAP_MCBSP_WRITE(OMAP1510_MCBSP3_BASE, PCR0, 0x2200);
94 gpio_set_value(A_LCD_SSC_SD, shifter & byte);
95 OMAP_MCBSP_WRITE(OMAP1510_MCBSP3_BASE, PCR0, 0x2202);
96 shifter >>= 1;
97 }
98 gpio_set_value(_A_LCD_SSC_A0, 1);
99}
100
101static void init_system(void)
102{
103 omap_mcbsp_request(OMAP_MCBSP3);
104 omap_mcbsp_stop(OMAP_MCBSP3);
105}
106
107static void setup_GPIO(void)
108{
109 /* new wave */
110 gpio_request(A_LCD_SSC_RD, "lcd_ssc_rd");
111 gpio_request(A_LCD_SSC_SD, "lcd_ssc_sd");
112 gpio_request(_A_LCD_RESET, "lcd_reset");
113 gpio_request(_A_LCD_SSC_CS, "lcd_ssc_cs");
114 gpio_request(_A_LCD_SSC_A0, "lcd_ssc_a0");
115
116 /* set GPIOs to output, with initial data */
117 gpio_direction_output(A_LCD_SSC_RD, 1);
118 gpio_direction_output(A_LCD_SSC_SD, 0);
119 gpio_direction_output(_A_LCD_RESET, 0);
120 gpio_direction_output(_A_LCD_SSC_CS, 1);
121 gpio_direction_output(_A_LCD_SSC_A0, 1);
122}
123
124static void display_init(void)
125{
126 int i;
127
128 omap_cfg_reg(MCBSP3_CLKX);
129
130 mdelay(2);
131 setup_GPIO();
132 mdelay(2);
133
134 /* reset LCD */
135 gpio_set_value(A_LCD_SSC_SD, 1);
136 epson_sendbyte(0, 0x25);
137
138 gpio_set_value(_A_LCD_RESET, 0);
139 mdelay(10);
140 gpio_set_value(_A_LCD_RESET, 1);
141
142 gpio_set_value(_A_LCD_SSC_CS, 1);
143 mdelay(2);
144 gpio_set_value(_A_LCD_SSC_CS, 0);
145
146 /* init LCD, phase 1 */
147 epson_sendbyte(0, 0xCA);
148 for (i = 0; i < 10; i++)
149 epson_sendbyte(1, INIT_1[i]);
150 gpio_set_value(_A_LCD_SSC_CS, 1);
151 gpio_set_value(_A_LCD_SSC_CS, 0);
152
153 /* init LCD phase 2 */
154 epson_sendbyte(0, 0xCB);
155 for (i = 0; i < 125; i++)
156 epson_sendbyte(1, INIT_2[i]);
157 gpio_set_value(_A_LCD_SSC_CS, 1);
158 gpio_set_value(_A_LCD_SSC_CS, 0);
159
160 /* init LCD phase 2a */
161 epson_sendbyte(0, 0xCC);
162 for (i = 0; i < 14; i++)
163 epson_sendbyte(1, INIT_3[i]);
164 gpio_set_value(_A_LCD_SSC_CS, 1);
165 gpio_set_value(_A_LCD_SSC_CS, 0);
166
167 /* init LCD phase 3 */
168 epson_sendbyte(0, 0xBC);
169 epson_sendbyte(1, 0x08);
170 gpio_set_value(_A_LCD_SSC_CS, 1);
171 gpio_set_value(_A_LCD_SSC_CS, 0);
172
173 /* init LCD phase 4 */
174 epson_sendbyte(0, 0x07);
175 epson_sendbyte(1, 0x05);
176 gpio_set_value(_A_LCD_SSC_CS, 1);
177 gpio_set_value(_A_LCD_SSC_CS, 0);
178
179 /* init LCD phase 5 */
180 epson_sendbyte(0, 0x94);
181 gpio_set_value(_A_LCD_SSC_CS, 1);
182 gpio_set_value(_A_LCD_SSC_CS, 0);
183
184 /* init LCD phase 6 */
185 epson_sendbyte(0, 0xC6);
186 epson_sendbyte(1, 0x80);
187 gpio_set_value(_A_LCD_SSC_CS, 1);
188 mdelay(100); /* used to be 1000 */
189 gpio_set_value(_A_LCD_SSC_CS, 0);
190
191 /* init LCD phase 7 */
192 epson_sendbyte(0, 0x16);
193 epson_sendbyte(1, 0x02);
194 epson_sendbyte(1, 0x00);
195 epson_sendbyte(1, 0xB1);
196 epson_sendbyte(1, 0x00);
197 gpio_set_value(_A_LCD_SSC_CS, 1);
198 gpio_set_value(_A_LCD_SSC_CS, 0);
199
200 /* init LCD phase 8 */
201 epson_sendbyte(0, 0x76);
202 epson_sendbyte(1, 0x00);
203 epson_sendbyte(1, 0x00);
204 epson_sendbyte(1, 0xDB);
205 epson_sendbyte(1, 0x00);
206 gpio_set_value(_A_LCD_SSC_CS, 1);
207 gpio_set_value(_A_LCD_SSC_CS, 0);
208
209 /* init LCD phase 9 */
210 epson_sendbyte(0, 0xAF);
211 gpio_set_value(_A_LCD_SSC_CS, 1);
212}
213
214static int sx1_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
215{
216 return 0;
217}
218
219static void sx1_panel_cleanup(struct lcd_panel *panel)
220{
221}
222
223static void sx1_panel_disable(struct lcd_panel *panel)
224{
225 printk(KERN_INFO "SX1: LCD panel disable\n");
226 sx1_setmmipower(0);
227 gpio_set_value(_A_LCD_SSC_CS, 1);
228
229 epson_sendbyte(0, 0x25);
230 gpio_set_value(_A_LCD_SSC_CS, 0);
231
232 epson_sendbyte(0, 0xAE);
233 gpio_set_value(_A_LCD_SSC_CS, 1);
234 mdelay(100);
235 gpio_set_value(_A_LCD_SSC_CS, 0);
236
237 epson_sendbyte(0, 0x95);
238 gpio_set_value(_A_LCD_SSC_CS, 1);
239}
240
241static int sx1_panel_enable(struct lcd_panel *panel)
242{
243 printk(KERN_INFO "lcd_sx1: LCD panel enable\n");
244 init_system();
245 display_init();
246
247 sx1_setmmipower(1);
248 sx1_setbacklight(0x18);
249 sx1_setkeylight (0x06);
250 return 0;
251}
252
253
254static unsigned long sx1_panel_get_caps(struct lcd_panel *panel)
255{
256 return 0;
257}
258
259struct lcd_panel sx1_panel = {
260 .name = "sx1",
261 .config = OMAP_LCDC_PANEL_TFT | OMAP_LCDC_INV_VSYNC |
262 OMAP_LCDC_INV_HSYNC | OMAP_LCDC_INV_PIX_CLOCK |
263 OMAP_LCDC_INV_OUTPUT_EN,
264
265 .x_res = 176,
266 .y_res = 220,
267 .data_lines = 16,
268 .bpp = 16,
269 .hsw = 5,
270 .hfp = 5,
271 .hbp = 5,
272 .vsw = 2,
273 .vfp = 1,
274 .vbp = 1,
275 .pixel_clock = 1500,
276
277 .init = sx1_panel_init,
278 .cleanup = sx1_panel_cleanup,
279 .enable = sx1_panel_enable,
280 .disable = sx1_panel_disable,
281 .get_caps = sx1_panel_get_caps,
282};
283
284static int sx1_panel_probe(struct platform_device *pdev)
285{
286 omapfb_register_panel(&sx1_panel);
287 return 0;
288}
289
290static int sx1_panel_remove(struct platform_device *pdev)
291{
292 return 0;
293}
294
295static int sx1_panel_suspend(struct platform_device *pdev, pm_message_t mesg)
296{
297 return 0;
298}
299
300static int sx1_panel_resume(struct platform_device *pdev)
301{
302 return 0;
303}
304
305struct platform_driver sx1_panel_driver = {
306 .probe = sx1_panel_probe,
307 .remove = sx1_panel_remove,
308 .suspend = sx1_panel_suspend,
309 .resume = sx1_panel_resume,
310 .driver = {
311 .name = "lcd_sx1",
312 .owner = THIS_MODULE,
313 },
314};
315
316static int sx1_panel_drv_init(void)
317{
318 return platform_driver_register(&sx1_panel_driver);
319}
320
321static void sx1_panel_drv_cleanup(void)
322{
323 platform_driver_unregister(&sx1_panel_driver);
324}
325
326module_init(sx1_panel_drv_init);
327module_exit(sx1_panel_drv_cleanup);
diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
index 5a5e407dc45f..1a49519dafa4 100644
--- a/drivers/video/omap/omapfb_main.c
+++ b/drivers/video/omap/omapfb_main.c
@@ -392,7 +392,7 @@ static void set_fb_fix(struct fb_info *fbi)
392 int bpp; 392 int bpp;
393 393
394 rg = &plane->fbdev->mem_desc.region[plane->idx]; 394 rg = &plane->fbdev->mem_desc.region[plane->idx];
395 fbi->screen_base = (char __iomem *)rg->vaddr; 395 fbi->screen_base = rg->vaddr;
396 fix->smem_start = rg->paddr; 396 fix->smem_start = rg->paddr;
397 fix->smem_len = rg->size; 397 fix->smem_len = rg->size;
398 398
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index 0bc2c5a127b9..d0fd22e06737 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -50,7 +50,6 @@
50#include <asm/irq.h> 50#include <asm/irq.h>
51#include <asm/div64.h> 51#include <asm/div64.h>
52#include <mach/pxa-regs.h> 52#include <mach/pxa-regs.h>
53#include <mach/pxa2xx-gpio.h>
54#include <mach/bitfield.h> 53#include <mach/bitfield.h>
55#include <mach/pxafb.h> 54#include <mach/pxafb.h>
56 55
@@ -69,9 +68,6 @@
69#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\ 68#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
70 LCCR3_PCD | LCCR3_BPP) 69 LCCR3_PCD | LCCR3_BPP)
71 70
72static void (*pxafb_backlight_power)(int);
73static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
74
75static int pxafb_activate_var(struct fb_var_screeninfo *var, 71static int pxafb_activate_var(struct fb_var_screeninfo *var,
76 struct pxafb_info *); 72 struct pxafb_info *);
77static void set_ctrlr_state(struct pxafb_info *fbi, u_int state); 73static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
@@ -727,12 +723,19 @@ int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
727 int i; 723 int i;
728 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 724 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
729 725
730 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */ 726 for (i = 0; i < n_cmds; i++, cmds++) {
731 for (i = 0; i < n_cmds; i++) { 727 /* if it is a software delay, flush and delay */
728 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
729 pxafb_smart_flush(info);
730 mdelay(*cmds & 0xff);
731 continue;
732 }
733
734 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
732 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8) 735 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
733 pxafb_smart_flush(info); 736 pxafb_smart_flush(info);
734 737
735 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds++; 738 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
736 } 739 }
737 740
738 return 0; 741 return 0;
@@ -764,7 +767,9 @@ static void setup_smart_timing(struct pxafb_info *fbi,
764 LCCR1_HorSnchWdth(__smart_timing(t3, lclk)); 767 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
765 768
766 fbi->reg_lccr2 = LCCR2_DisHght(var->yres); 769 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
767 fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk)); 770 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
771 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
772 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
768 773
769 /* FIXME: make this configurable */ 774 /* FIXME: make this configurable */
770 fbi->reg_cmdcr = 1; 775 fbi->reg_cmdcr = 1;
@@ -789,11 +794,15 @@ static int pxafb_smart_thread(void *arg)
789 if (try_to_freeze()) 794 if (try_to_freeze())
790 continue; 795 continue;
791 796
797 mutex_lock(&fbi->ctrlr_lock);
798
792 if (fbi->state == C_ENABLE) { 799 if (fbi->state == C_ENABLE) {
793 inf->smart_update(&fbi->fb); 800 inf->smart_update(&fbi->fb);
794 complete(&fbi->refresh_done); 801 complete(&fbi->refresh_done);
795 } 802 }
796 803
804 mutex_unlock(&fbi->ctrlr_lock);
805
797 set_current_state(TASK_INTERRUPTIBLE); 806 set_current_state(TASK_INTERRUPTIBLE);
798 schedule_timeout(30 * HZ / 1000); 807 schedule_timeout(30 * HZ / 1000);
799 } 808 }
@@ -804,16 +813,22 @@ static int pxafb_smart_thread(void *arg)
804 813
805static int pxafb_smart_init(struct pxafb_info *fbi) 814static int pxafb_smart_init(struct pxafb_info *fbi)
806{ 815{
807 if (!(fbi->lccr0 | LCCR0_LCDT)) 816 if (!(fbi->lccr0 & LCCR0_LCDT))
808 return 0; 817 return 0;
809 818
819 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
820 fbi->n_smart_cmds = 0;
821
822 init_completion(&fbi->command_done);
823 init_completion(&fbi->refresh_done);
824
810 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi, 825 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
811 "lcd_refresh"); 826 "lcd_refresh");
812 if (IS_ERR(fbi->smart_thread)) { 827 if (IS_ERR(fbi->smart_thread)) {
813 printk(KERN_ERR "%s: unable to create kernel thread\n", 828 pr_err("%s: unable to create kernel thread\n", __func__);
814 __func__);
815 return PTR_ERR(fbi->smart_thread); 829 return PTR_ERR(fbi->smart_thread);
816 } 830 }
831
817 return 0; 832 return 0;
818} 833}
819#else 834#else
@@ -826,7 +841,9 @@ int pxafb_smart_flush(struct fb_info *info)
826{ 841{
827 return 0; 842 return 0;
828} 843}
829#endif /* CONFIG_FB_SMART_PANEL */ 844
845static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
846#endif /* CONFIG_FB_PXA_SMARTPANEL */
830 847
831static void setup_parallel_timing(struct pxafb_info *fbi, 848static void setup_parallel_timing(struct pxafb_info *fbi,
832 struct fb_var_screeninfo *var) 849 struct fb_var_screeninfo *var)
@@ -976,67 +993,16 @@ static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
976{ 993{
977 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff"); 994 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
978 995
979 if (pxafb_backlight_power) 996 if (fbi->backlight_power)
980 pxafb_backlight_power(on); 997 fbi->backlight_power(on);
981} 998}
982 999
983static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on) 1000static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
984{ 1001{
985 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff"); 1002 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
986 1003
987 if (pxafb_lcd_power) 1004 if (fbi->lcd_power)
988 pxafb_lcd_power(on, &fbi->fb.var); 1005 fbi->lcd_power(on, &fbi->fb.var);
989}
990
991static void pxafb_setup_gpio(struct pxafb_info *fbi)
992{
993 int gpio, ldd_bits;
994 unsigned int lccr0 = fbi->lccr0;
995
996 /*
997 * setup is based on type of panel supported
998 */
999
1000 /* 4 bit interface */
1001 if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
1002 (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
1003 (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
1004 ldd_bits = 4;
1005
1006 /* 8 bit interface */
1007 else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
1008 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
1009 (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
1010 ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
1011 (lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1012 (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
1013 ldd_bits = 8;
1014
1015 /* 16 bit interface */
1016 else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
1017 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
1018 (lccr0 & LCCR0_PAS) == LCCR0_Act))
1019 ldd_bits = 16;
1020
1021 else {
1022 printk(KERN_ERR "pxafb_setup_gpio: unable to determine "
1023 "bits per pixel\n");
1024 return;
1025 }
1026
1027 for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
1028 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
1029 /* 18 bit interface */
1030 if (fbi->fb.var.bits_per_pixel > 16) {
1031 pxa_gpio_mode(86 | GPIO_ALT_FN_2_OUT);
1032 pxa_gpio_mode(87 | GPIO_ALT_FN_2_OUT);
1033 }
1034 pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
1035 pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
1036 pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
1037
1038 if ((lccr0 & LCCR0_PAS) == 0)
1039 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
1040} 1006}
1041 1007
1042static void pxafb_enable_controller(struct pxafb_info *fbi) 1008static void pxafb_enable_controller(struct pxafb_info *fbi)
@@ -1181,7 +1147,6 @@ static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1181 if (old_state == C_ENABLE) { 1147 if (old_state == C_ENABLE) {
1182 __pxafb_lcd_power(fbi, 0); 1148 __pxafb_lcd_power(fbi, 0);
1183 pxafb_disable_controller(fbi); 1149 pxafb_disable_controller(fbi);
1184 pxafb_setup_gpio(fbi);
1185 pxafb_enable_controller(fbi); 1150 pxafb_enable_controller(fbi);
1186 __pxafb_lcd_power(fbi, 1); 1151 __pxafb_lcd_power(fbi, 1);
1187 } 1152 }
@@ -1204,7 +1169,6 @@ static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1204 */ 1169 */
1205 if (old_state != C_ENABLE) { 1170 if (old_state != C_ENABLE) {
1206 fbi->state = C_ENABLE; 1171 fbi->state = C_ENABLE;
1207 pxafb_setup_gpio(fbi);
1208 pxafb_enable_controller(fbi); 1172 pxafb_enable_controller(fbi);
1209 __pxafb_lcd_power(fbi, 1); 1173 __pxafb_lcd_power(fbi, 1);
1210 __pxafb_backlight_power(fbi, 1); 1174 __pxafb_backlight_power(fbi, 1);
@@ -1342,11 +1306,6 @@ static int __devinit pxafb_map_video_memory(struct pxafb_info *fbi)
1342 fbi->palette_cpu = (u16 *) fbi->dma_buff->palette; 1306 fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
1343 1307
1344 pr_debug("pxafb: palette_mem_size = 0x%08x\n", fbi->palette_size*sizeof(u16)); 1308 pr_debug("pxafb: palette_mem_size = 0x%08x\n", fbi->palette_size*sizeof(u16));
1345
1346#ifdef CONFIG_FB_PXA_SMARTPANEL
1347 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1348 fbi->n_smart_cmds = 0;
1349#endif
1350 } 1309 }
1351 1310
1352 return fbi->map_cpu ? 0 : -ENOMEM; 1311 return fbi->map_cpu ? 0 : -ENOMEM;
@@ -1468,10 +1427,6 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1468 INIT_WORK(&fbi->task, pxafb_task); 1427 INIT_WORK(&fbi->task, pxafb_task);
1469 mutex_init(&fbi->ctrlr_lock); 1428 mutex_init(&fbi->ctrlr_lock);
1470 init_completion(&fbi->disable_done); 1429 init_completion(&fbi->disable_done);
1471#ifdef CONFIG_FB_PXA_SMARTPANEL
1472 init_completion(&fbi->command_done);
1473 init_completion(&fbi->refresh_done);
1474#endif
1475 1430
1476 return fbi; 1431 return fbi;
1477} 1432}
@@ -1748,8 +1703,7 @@ static int __devinit pxafb_probe(struct platform_device *dev)
1748 ret = -EINVAL; 1703 ret = -EINVAL;
1749 goto failed; 1704 goto failed;
1750 } 1705 }
1751 pxafb_backlight_power = inf->pxafb_backlight_power; 1706
1752 pxafb_lcd_power = inf->pxafb_lcd_power;
1753 fbi = pxafb_init_fbinfo(&dev->dev); 1707 fbi = pxafb_init_fbinfo(&dev->dev);
1754 if (!fbi) { 1708 if (!fbi) {
1755 /* only reason for pxafb_init_fbinfo to fail is kmalloc */ 1709 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
@@ -1758,6 +1712,9 @@ static int __devinit pxafb_probe(struct platform_device *dev)
1758 goto failed; 1712 goto failed;
1759 } 1713 }
1760 1714
1715 fbi->backlight_power = inf->pxafb_backlight_power;
1716 fbi->lcd_power = inf->pxafb_lcd_power;
1717
1761 r = platform_get_resource(dev, IORESOURCE_MEM, 0); 1718 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1762 if (r == NULL) { 1719 if (r == NULL) {
1763 dev_err(&dev->dev, "no I/O memory resource defined\n"); 1720 dev_err(&dev->dev, "no I/O memory resource defined\n");
@@ -1801,13 +1758,12 @@ static int __devinit pxafb_probe(struct platform_device *dev)
1801 goto failed_free_mem; 1758 goto failed_free_mem;
1802 } 1759 }
1803 1760
1804#ifdef CONFIG_FB_PXA_SMARTPANEL
1805 ret = pxafb_smart_init(fbi); 1761 ret = pxafb_smart_init(fbi);
1806 if (ret) { 1762 if (ret) {
1807 dev_err(&dev->dev, "failed to initialize smartpanel\n"); 1763 dev_err(&dev->dev, "failed to initialize smartpanel\n");
1808 goto failed_free_irq; 1764 goto failed_free_irq;
1809 } 1765 }
1810#endif 1766
1811 /* 1767 /*
1812 * This makes sure that our colour bitfield 1768 * This makes sure that our colour bitfield
1813 * descriptors are correctly initialised. 1769 * descriptors are correctly initialised.
diff --git a/drivers/video/pxafb.h b/drivers/video/pxafb.h
index 31541b86f13d..d8eb93fa03a3 100644
--- a/drivers/video/pxafb.h
+++ b/drivers/video/pxafb.h
@@ -124,6 +124,9 @@ struct pxafb_info {
124 struct notifier_block freq_transition; 124 struct notifier_block freq_transition;
125 struct notifier_block freq_policy; 125 struct notifier_block freq_policy;
126#endif 126#endif
127
128 void (*lcd_power)(int, struct fb_var_screeninfo *);
129 void (*backlight_power)(int);
127}; 130};
128 131
129#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member) 132#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
diff --git a/drivers/video/sa1100fb.c b/drivers/video/sa1100fb.c
index c052bd4c0b06..076f946fa0f5 100644
--- a/drivers/video/sa1100fb.c
+++ b/drivers/video/sa1100fb.c
@@ -114,7 +114,7 @@
114 * - convert dma address types to dma_addr_t 114 * - convert dma address types to dma_addr_t
115 * - remove unused 'montype' stuff 115 * - remove unused 'montype' stuff
116 * - remove redundant zero inits of init_var after the initial 116 * - remove redundant zero inits of init_var after the initial
117 * memzero. 117 * memset.
118 * - remove allow_modeset (acornfb idea does not belong here) 118 * - remove allow_modeset (acornfb idea does not belong here)
119 * 119 *
120 * 2001/05/28: <rmk@arm.linux.org.uk> 120 * 2001/05/28: <rmk@arm.linux.org.uk>
diff --git a/drivers/video/xen-fbfront.c b/drivers/video/xen-fbfront.c
index a463b3dd837b..2493f05e9f61 100644
--- a/drivers/video/xen-fbfront.c
+++ b/drivers/video/xen-fbfront.c
@@ -668,7 +668,7 @@ static struct xenbus_device_id xenfb_ids[] = {
668 { "" } 668 { "" }
669}; 669};
670 670
671static struct xenbus_driver xenfb = { 671static struct xenbus_driver xenfb_driver = {
672 .name = "vfb", 672 .name = "vfb",
673 .owner = THIS_MODULE, 673 .owner = THIS_MODULE,
674 .ids = xenfb_ids, 674 .ids = xenfb_ids,
@@ -687,12 +687,12 @@ static int __init xenfb_init(void)
687 if (xen_initial_domain()) 687 if (xen_initial_domain())
688 return -ENODEV; 688 return -ENODEV;
689 689
690 return xenbus_register_frontend(&xenfb); 690 return xenbus_register_frontend(&xenfb_driver);
691} 691}
692 692
693static void __exit xenfb_cleanup(void) 693static void __exit xenfb_cleanup(void)
694{ 694{
695 xenbus_unregister_driver(&xenfb); 695 xenbus_unregister_driver(&xenfb_driver);
696} 696}
697 697
698module_init(xenfb_init); 698module_init(xenfb_init);
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index 5da3d2423cc0..40a3a2afbfe7 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -298,8 +298,9 @@ static int xilinxfb_assign(struct device *dev, unsigned long physaddr,
298 298
299 /* Put a banner in the log (for DEBUG) */ 299 /* Put a banner in the log (for DEBUG) */
300 dev_dbg(dev, "regs: phys=%lx, virt=%p\n", physaddr, drvdata->regs); 300 dev_dbg(dev, "regs: phys=%lx, virt=%p\n", physaddr, drvdata->regs);
301 dev_dbg(dev, "fb: phys=%p, virt=%p, size=%x\n", 301 dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n",
302 (void*)drvdata->fb_phys, drvdata->fb_virt, fbsize); 302 (unsigned long long) drvdata->fb_phys, drvdata->fb_virt,
303 fbsize);
303 304
304 return 0; /* success */ 305 return 0; /* success */
305 306
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 04:42:59 -0500