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-rw-r--r--drivers/video/Kconfig2
-rw-r--r--drivers/video/amba-clcd.c31
2 files changed, 25 insertions, 8 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index feaff4f04b58..6e16244f3ed1 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1881,7 +1881,7 @@ config FB_W100
1881 1881
1882config FB_SH_MOBILE_LCDC 1882config FB_SH_MOBILE_LCDC
1883 tristate "SuperH Mobile LCDC framebuffer support" 1883 tristate "SuperH Mobile LCDC framebuffer support"
1884 depends on FB && SUPERH && HAVE_CLK 1884 depends on FB && (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
1885 select FB_SYS_FILLRECT 1885 select FB_SYS_FILLRECT
1886 select FB_SYS_COPYAREA 1886 select FB_SYS_COPYAREA
1887 select FB_SYS_IMAGEBLIT 1887 select FB_SYS_IMAGEBLIT
diff --git a/drivers/video/amba-clcd.c b/drivers/video/amba-clcd.c
index a21efcd10b78..afe21e6eb544 100644
--- a/drivers/video/amba-clcd.c
+++ b/drivers/video/amba-clcd.c
@@ -65,16 +65,16 @@ static void clcdfb_disable(struct clcd_fb *fb)
65 if (fb->board->disable) 65 if (fb->board->disable)
66 fb->board->disable(fb); 66 fb->board->disable(fb);
67 67
68 val = readl(fb->regs + CLCD_CNTL); 68 val = readl(fb->regs + fb->off_cntl);
69 if (val & CNTL_LCDPWR) { 69 if (val & CNTL_LCDPWR) {
70 val &= ~CNTL_LCDPWR; 70 val &= ~CNTL_LCDPWR;
71 writel(val, fb->regs + CLCD_CNTL); 71 writel(val, fb->regs + fb->off_cntl);
72 72
73 clcdfb_sleep(20); 73 clcdfb_sleep(20);
74 } 74 }
75 if (val & CNTL_LCDEN) { 75 if (val & CNTL_LCDEN) {
76 val &= ~CNTL_LCDEN; 76 val &= ~CNTL_LCDEN;
77 writel(val, fb->regs + CLCD_CNTL); 77 writel(val, fb->regs + fb->off_cntl);
78 } 78 }
79 79
80 /* 80 /*
@@ -94,7 +94,7 @@ static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
94 * Bring up by first enabling.. 94 * Bring up by first enabling..
95 */ 95 */
96 cntl |= CNTL_LCDEN; 96 cntl |= CNTL_LCDEN;
97 writel(cntl, fb->regs + CLCD_CNTL); 97 writel(cntl, fb->regs + fb->off_cntl);
98 98
99 clcdfb_sleep(20); 99 clcdfb_sleep(20);
100 100
@@ -102,7 +102,7 @@ static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
102 * and now apply power. 102 * and now apply power.
103 */ 103 */
104 cntl |= CNTL_LCDPWR; 104 cntl |= CNTL_LCDPWR;
105 writel(cntl, fb->regs + CLCD_CNTL); 105 writel(cntl, fb->regs + fb->off_cntl);
106 106
107 /* 107 /*
108 * finally, enable the interface. 108 * finally, enable the interface.
@@ -233,7 +233,7 @@ static int clcdfb_set_par(struct fb_info *info)
233 readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1), 233 readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1),
234 readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3), 234 readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3),
235 readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS), 235 readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS),
236 readl(fb->regs + CLCD_IENB), readl(fb->regs + CLCD_CNTL)); 236 readl(fb->regs + fb->off_ienb), readl(fb->regs + fb->off_cntl));
237#endif 237#endif
238 238
239 return 0; 239 return 0;
@@ -345,6 +345,23 @@ static int clcdfb_register(struct clcd_fb *fb)
345{ 345{
346 int ret; 346 int ret;
347 347
348 /*
349 * ARM PL111 always has IENB at 0x1c; it's only PL110
350 * which is reversed on some platforms.
351 */
352 if (amba_manf(fb->dev) == 0x41 && amba_part(fb->dev) == 0x111) {
353 fb->off_ienb = CLCD_PL111_IENB;
354 fb->off_cntl = CLCD_PL111_CNTL;
355 } else {
356#ifdef CONFIG_ARCH_VERSATILE
357 fb->off_ienb = CLCD_PL111_IENB;
358 fb->off_cntl = CLCD_PL111_CNTL;
359#else
360 fb->off_ienb = CLCD_PL110_IENB;
361 fb->off_cntl = CLCD_PL110_CNTL;
362#endif
363 }
364
348 fb->clk = clk_get(&fb->dev->dev, NULL); 365 fb->clk = clk_get(&fb->dev->dev, NULL);
349 if (IS_ERR(fb->clk)) { 366 if (IS_ERR(fb->clk)) {
350 ret = PTR_ERR(fb->clk); 367 ret = PTR_ERR(fb->clk);
@@ -416,7 +433,7 @@ static int clcdfb_register(struct clcd_fb *fb)
416 /* 433 /*
417 * Ensure interrupts are disabled. 434 * Ensure interrupts are disabled.
418 */ 435 */
419 writel(0, fb->regs + CLCD_IENB); 436 writel(0, fb->regs + fb->off_ienb);
420 437
421 fb_set_var(&fb->fb, &fb->fb.var); 438 fb_set_var(&fb->fb, &fb->fb.var);
422 439