133 files changed, 9900 insertions, 3536 deletions

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 6bafb51bb437..e6a8d8c0101d 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -322,69 +322,6 @@ config FB_ARMCLCD
           here and read <file:Documentation/kbuild/modules.txt>.  The module
           will be called amba-clcd.
 
-choice
-
-        depends on FB_ARMCLCD && (ARCH_LH7A40X || ARCH_LH7952X)
-        prompt "LCD Panel"
-        default FB_ARMCLCD_SHARP_LQ035Q7DB02
-
-config FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT
-        bool "LogicPD LCD 3.5\" QVGA w/HRTFT IC"
-        help
-          This is an implementation of the Sharp LQ035Q7DB02, a 3.5"
-          color QVGA, HRTFT panel.  The LogicPD device includes
-          an integrated HRTFT controller IC.
-          The native resolution is 240x320.
-
-config FB_ARMCLCD_SHARP_LQ057Q3DC02
-        bool "LogicPD LCD 5.7\" QVGA"
-        help
-          This is an implementation of the Sharp LQ057Q3DC02, a 5.7"
-          color QVGA, TFT panel.  The LogicPD device includes an
-          The native resolution is 320x240.
-
-config FB_ARMCLCD_SHARP_LQ64D343
-        bool "LogicPD LCD 6.4\" VGA"
-        help
-          This is an implementation of the Sharp LQ64D343, a 6.4"
-          color VGA, TFT panel.  The LogicPD device includes an
-          The native resolution is 640x480.
-
-config FB_ARMCLCD_SHARP_LQ10D368
-        bool "LogicPD LCD 10.4\" VGA"
-        help
-          This is an implementation of the Sharp LQ10D368, a 10.4"
-          color VGA, TFT panel.  The LogicPD device includes an
-          The native resolution is 640x480.
-
-
-config FB_ARMCLCD_SHARP_LQ121S1DG41
-        bool "LogicPD LCD 12.1\" SVGA"
-        help
-          This is an implementation of the Sharp LQ121S1DG41, a 12.1"
-          color SVGA, TFT panel.  The LogicPD device includes an
-          The native resolution is 800x600.
-
-          This panel requires a clock rate may be an integer fraction
-          of the base LCDCLK frequency.  The driver will select the
-          highest frequency available that is lower than the maximum
-          allowed.  The panel may flicker if the clock rate is
-          slower than the recommended minimum.
-
-config FB_ARMCLCD_AUO_A070VW01_WIDE
-        bool "AU Optronics A070VW01 LCD 7.0\" WIDE"
-        help
-          This is an implementation of the AU Optronics, a 7.0"
-          WIDE Color.  The native resolution is 234x480.
-
-config FB_ARMCLCD_HITACHI
-        bool "Hitachi Wide Screen 800x480"
-        help
-          This is an implementation of the Hitachi 800x480.
-
-endchoice
-
-
 config FB_ACORN
         bool "Acorn VIDC support"
         depends on (FB = y) && ARM && ARCH_ACORN
@@ -439,6 +376,24 @@ config FB_CYBER2000
           Say Y if you have a NetWinder or a graphics card containing this
           device, otherwise say N.
 
+config FB_CYBER2000_DDC
+        bool "DDC for CyberPro support"
+        depends on FB_CYBER2000
+        select FB_DDC
+        default y
+        help
+          Say Y here if you want DDC support for your CyberPro graphics
+          card. This is only I2C bus support, driver does not use EDID.
+
+config FB_CYBER2000_I2C
+        bool "CyberPro 2000/2010/5000 I2C support"
+        depends on FB_CYBER2000 && I2C && ARCH_NETWINDER
+        select I2C_ALGOBIT
+        help
+          Enable support for the I2C video decoder interface on the
+          Integraphics CyberPro 20x0 and 5000 VGA chips.  This is used
+          on the Netwinder machines for the SAA7111 video capture.
+
 config FB_APOLLO
         bool
         depends on (FB = y) && APOLLO
@@ -2005,6 +1960,7 @@ config FB_SH_MOBILE_LCDC
         select FB_SYS_IMAGEBLIT
         select FB_SYS_FOPS
         select FB_DEFERRED_IO
+        select FB_BACKLIGHT
         select SH_MIPI_DSI if SH_LCD_MIPI_DSI
         ---help---
           Frame buffer driver for the on-chip SH-Mobile LCD controller.
@@ -2365,6 +2321,26 @@ config FB_JZ4740
         help
           Framebuffer support for the JZ4740 SoC.
 
+config FB_MXS
+        tristate "MXS LCD framebuffer support"
+        depends on FB && ARCH_MXS
+        select FB_CFB_FILLRECT
+        select FB_CFB_COPYAREA
+        select FB_CFB_IMAGEBLIT
+        help
+          Framebuffer support for the MXS SoC.
+
+config FB_PUV3_UNIGFX
+        tristate "PKUnity v3 Unigfx framebuffer support"
+        depends on FB && UNICORE32 && ARCH_PUV3
+        select FB_SYS_FILLRECT
+        select FB_SYS_COPYAREA
+        select FB_SYS_IMAGEBLIT
+        select FB_SYS_FOPS
+        help
+          Choose this option if you want to use the Unigfx device as a
+          framebuffer device. Without the support of PCI & AGP.
+
 source "drivers/video/omap/Kconfig"
 source "drivers/video/omap2/Kconfig"
 
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 8c8fabdff9d0..2ea44b6625fe 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -139,6 +139,7 @@ obj-$(CONFIG_FB_MB862XX)	  += mb862xx/
 obj-$(CONFIG_FB_MSM)              += msm/
 obj-$(CONFIG_FB_NUC900)           += nuc900fb.o
 obj-$(CONFIG_FB_JZ4740)           += jz4740_fb.o
+obj-$(CONFIG_FB_PUV3_UNIGFX)      += fb-puv3.o
 
 # Platform or fallback drivers go here
 obj-$(CONFIG_FB_UVESA)            += uvesafb.o
@@ -153,6 +154,7 @@ obj-$(CONFIG_FB_BFIN_T350MCQB)	  += bfin-t350mcqb-fb.o
 obj-$(CONFIG_FB_BFIN_7393)        += bfin_adv7393fb.o
 obj-$(CONFIG_FB_MX3)              += mx3fb.o
 obj-$(CONFIG_FB_DA8XX)            += da8xx-fb.o
+obj-$(CONFIG_FB_MXS)              += mxsfb.o
 
 # the test framebuffer is last
 obj-$(CONFIG_FB_VIRTUAL)          += vfb.o
diff --git a/drivers/video/amba-clcd.c b/drivers/video/amba-clcd.c
index 1c2c68356ea7..5fc983c5b92c 100644
--- a/drivers/video/amba-clcd.c
+++ b/drivers/video/amba-clcd.c
@@ -120,8 +120,23 @@ static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
 static int
 clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
 {
+        u32 caps;
         int ret = 0;
 
+        if (fb->panel->caps && fb->board->caps)
+                caps = fb->panel->caps & fb->board->caps;
+        else {
+                /* Old way of specifying what can be used */
+                caps = fb->panel->cntl & CNTL_BGR ?
+                        CLCD_CAP_BGR : CLCD_CAP_RGB;
+                /* But mask out 444 modes as they weren't supported */
+                caps &= ~CLCD_CAP_444;
+        }
+
+        /* Only TFT panels can do RGB888/BGR888 */
+        if (!(fb->panel->cntl & CNTL_LCDTFT))
+                caps &= ~CLCD_CAP_888;
+
         memset(&var->transp, 0, sizeof(var->transp));
 
         var->red.msb_right = 0;
@@ -133,6 +148,13 @@ clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
         case 2:
         case 4:
         case 8:
+                /* If we can't do 5551, reject */
+                caps &= CLCD_CAP_5551;
+                if (!caps) {
+                        ret = -EINVAL;
+                        break;
+                }
+
                 var->red.length         = var->bits_per_pixel;
                 var->red.offset         = 0;
                 var->green.length       = var->bits_per_pixel;
@@ -140,23 +162,61 @@ clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
                 var->blue.length        = var->bits_per_pixel;
                 var->blue.offset        = 0;
                 break;
+
         case 16:
-                var->red.length = 5;
-                var->blue.length = 5;
+                /* If we can't do 444, 5551 or 565, reject */
+                if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) {
+                        ret = -EINVAL;
+                        break;
+                }
+
                 /*
-                 * Green length can be 5 or 6 depending whether
-                 * we're operating in RGB555 or RGB565 mode.
+                 * Green length can be 4, 5 or 6 depending whether
+                 * we're operating in 444, 5551 or 565 mode.
                  */
-                if (var->green.length != 5 && var->green.length != 6)
-                        var->green.length = 6;
+                if (var->green.length == 4 && caps & CLCD_CAP_444)
+                        caps &= CLCD_CAP_444;
+                if (var->green.length == 5 && caps & CLCD_CAP_5551)
+                        caps &= CLCD_CAP_5551;
+                else if (var->green.length == 6 && caps & CLCD_CAP_565)
+                        caps &= CLCD_CAP_565;
+                else {
+                        /*
+                         * PL110 officially only supports RGB555,
+                         * but may be wired up to allow RGB565.
+                         */
+                        if (caps & CLCD_CAP_565) {
+                                var->green.length = 6;
+                                caps &= CLCD_CAP_565;
+                        } else if (caps & CLCD_CAP_5551) {
+                                var->green.length = 5;
+                                caps &= CLCD_CAP_5551;
+                        } else {
+                                var->green.length = 4;
+                                caps &= CLCD_CAP_444;
+                        }
+                }
+
+                if (var->green.length >= 5) {
+                        var->red.length = 5;
+                        var->blue.length = 5;
+                } else {
+                        var->red.length = 4;
+                        var->blue.length = 4;
+                }
                 break;
         case 32:
-                if (fb->panel->cntl & CNTL_LCDTFT) {
-                        var->red.length         = 8;
-                        var->green.length       = 8;
-                        var->blue.length        = 8;
+                /* If we can't do 888, reject */
+                caps &= CLCD_CAP_888;
+                if (!caps) {
+                        ret = -EINVAL;
                         break;
                 }
+
+                var->red.length = 8;
+                var->green.length = 8;
+                var->blue.length = 8;
+                break;
         default:
                 ret = -EINVAL;
                 break;
@@ -168,7 +228,20 @@ clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
          * the bitfield length defined above.
          */
         if (ret == 0 && var->bits_per_pixel >= 16) {
-                if (fb->panel->cntl & CNTL_BGR) {
+                bool bgr, rgb;
+
+                bgr = caps & CLCD_CAP_BGR && var->blue.offset == 0;
+                rgb = caps & CLCD_CAP_RGB && var->red.offset == 0;
+
+                if (!bgr && !rgb)
+                        /*
+                         * The requested format was not possible, try just
+                         * our capabilities.  One of BGR or RGB must be
+                         * supported.
+                         */
+                        bgr = caps & CLCD_CAP_BGR;
+
+                if (bgr) {
                         var->blue.offset = 0;
                         var->green.offset = var->blue.offset + var->blue.length;
                         var->red.offset = var->green.offset + var->green.length;
@@ -443,8 +516,8 @@ static int clcdfb_register(struct clcd_fb *fb)
 
         fb_set_var(&fb->fb, &fb->fb.var);
 
-        printk(KERN_INFO "CLCD: %s hardware, %s display\n",
-               fb->board->name, fb->panel->mode.name);
+        dev_info(&fb->dev->dev, "%s hardware, %s display\n",
+                 fb->board->name, fb->panel->mode.name);
 
         ret = register_framebuffer(&fb->fb);
         if (ret == 0)
@@ -461,7 +534,7 @@ static int clcdfb_register(struct clcd_fb *fb)
         return ret;
 }
 
-static int clcdfb_probe(struct amba_device *dev, struct amba_id *id)
+static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id)
 {
         struct clcd_board *board = dev->dev.platform_data;
         struct clcd_fb *fb;
@@ -486,6 +559,10 @@ static int clcdfb_probe(struct amba_device *dev, struct amba_id *id)
         fb->dev = dev;
         fb->board = board;
 
+        dev_info(&fb->dev->dev, "PL%03x rev%u at 0x%08llx\n",
+                amba_part(dev), amba_rev(dev),
+                (unsigned long long)dev->res.start);
+
         ret = fb->board->setup(fb);
         if (ret)
                 goto free_fb;
diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c
index 391ac939f011..8686429cbdf0 100644
--- a/drivers/video/arkfb.c
+++ b/drivers/video/arkfb.c
@@ -158,12 +158,19 @@ static void arkfb_settile(struct fb_info *info, struct fb_tilemap *map)
         }
 }
 
+static void arkfb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
+{
+        struct arkfb_info *par = info->par;
+
+        svga_tilecursor(par->state.vgabase, info, cursor);
+}
+
 static struct fb_tile_ops arkfb_tile_ops = {
         .fb_settile     = arkfb_settile,
         .fb_tilecopy    = svga_tilecopy,
         .fb_tilefill    = svga_tilefill,
         .fb_tileblit    = svga_tileblit,
-        .fb_tilecursor  = svga_tilecursor,
+        .fb_tilecursor  = arkfb_tilecursor,
         .fb_get_tilemax = svga_get_tilemax,
 };
 
@@ -466,32 +473,40 @@ static unsigned short dac_regs[4] = {0x3c8, 0x3c9, 0x3c6, 0x3c7};
 
 static void ark_dac_read_regs(void *data, u8 *code, int count)
 {
-        u8 regval = vga_rseq(NULL, 0x1C);
+        struct fb_info *info = data;
+        struct arkfb_info *par;
+        u8 regval;
 
+        par = info->par;
+        regval = vga_rseq(par->state.vgabase, 0x1C);
         while (count != 0)
         {
-                vga_wseq(NULL, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
-                code[1] = vga_r(NULL, dac_regs[code[0] & 3]);
+                vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
+                code[1] = vga_r(par->state.vgabase, dac_regs[code[0] & 3]);
                 count--;
                 code += 2;
         }
 
-        vga_wseq(NULL, 0x1C, regval);
+        vga_wseq(par->state.vgabase, 0x1C, regval);
 }
 
 static void ark_dac_write_regs(void *data, u8 *code, int count)
 {
-        u8 regval = vga_rseq(NULL, 0x1C);
+        struct fb_info *info = data;
+        struct arkfb_info *par;
+        u8 regval;
 
+        par = info->par;
+        regval = vga_rseq(par->state.vgabase, 0x1C);
         while (count != 0)
         {
-                vga_wseq(NULL, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
-                vga_w(NULL, dac_regs[code[0] & 3], code[1]);
+                vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
+                vga_w(par->state.vgabase, dac_regs[code[0] & 3], code[1]);
                 count--;
                 code += 2;
         }
 
-        vga_wseq(NULL, 0x1C, regval);
+        vga_wseq(par->state.vgabase, 0x1C, regval);
 }
 
 
@@ -507,8 +522,8 @@ static void ark_set_pixclock(struct fb_info *info, u32 pixclock)
         }
 
         /* Set VGA misc register  */
-        regval = vga_r(NULL, VGA_MIS_R);
-        vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
+        regval = vga_r(par->state.vgabase, VGA_MIS_R);
+        vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
 }
 
 
@@ -520,7 +535,10 @@ static int arkfb_open(struct fb_info *info, int user)
 
         mutex_lock(&(par->open_lock));
         if (par->ref_count == 0) {
+                void __iomem *vgabase = par->state.vgabase;
+
                 memset(&(par->state), 0, sizeof(struct vgastate));
+                par->state.vgabase = vgabase;
                 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
                 par->state.num_crtc = 0x60;
                 par->state.num_seq = 0x30;
@@ -646,50 +664,50 @@ static int arkfb_set_par(struct fb_info *info)
         info->var.activate = FB_ACTIVATE_NOW;
 
         /* Unlock registers */
-        svga_wcrt_mask(0x11, 0x00, 0x80);
+        svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
 
         /* Blank screen and turn off sync */
-        svga_wseq_mask(0x01, 0x20, 0x20);
-        svga_wcrt_mask(0x17, 0x00, 0x80);
+        svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
+        svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
 
         /* Set default values */
-        svga_set_default_gfx_regs();
-        svga_set_default_atc_regs();
-        svga_set_default_seq_regs();
-        svga_set_default_crt_regs();
-        svga_wcrt_multi(ark_line_compare_regs, 0xFFFFFFFF);
-        svga_wcrt_multi(ark_start_address_regs, 0);
+        svga_set_default_gfx_regs(par->state.vgabase);
+        svga_set_default_atc_regs(par->state.vgabase);
+        svga_set_default_seq_regs(par->state.vgabase);
+        svga_set_default_crt_regs(par->state.vgabase);
+        svga_wcrt_multi(par->state.vgabase, ark_line_compare_regs, 0xFFFFFFFF);
+        svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0);
 
         /* ARK specific initialization */
-        svga_wseq_mask(0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */
-        svga_wseq_mask(0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */
+        svga_wseq_mask(par->state.vgabase, 0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */
+        svga_wseq_mask(par->state.vgabase, 0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */
 
-        vga_wseq(NULL, 0x13, info->fix.smem_start >> 16);
-        vga_wseq(NULL, 0x14, info->fix.smem_start >> 24);
-        vga_wseq(NULL, 0x15, 0);
-        vga_wseq(NULL, 0x16, 0);
+        vga_wseq(par->state.vgabase, 0x13, info->fix.smem_start >> 16);
+        vga_wseq(par->state.vgabase, 0x14, info->fix.smem_start >> 24);
+        vga_wseq(par->state.vgabase, 0x15, 0);
+        vga_wseq(par->state.vgabase, 0x16, 0);
 
         /* Set the FIFO threshold register */
         /* It is fascinating way to store 5-bit value in 8-bit register */
         regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1;
-        vga_wseq(NULL, 0x18, regval);
+        vga_wseq(par->state.vgabase, 0x18, regval);
 
         /* Set the offset register */
         pr_debug("fb%d: offset register       : %d\n", info->node, offset_value);
-        svga_wcrt_multi(ark_offset_regs, offset_value);
+        svga_wcrt_multi(par->state.vgabase, ark_offset_regs, offset_value);
 
         /* fix for hi-res textmode */
-        svga_wcrt_mask(0x40, 0x08, 0x08);
+        svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08);
 
         if (info->var.vmode & FB_VMODE_DOUBLE)
-                svga_wcrt_mask(0x09, 0x80, 0x80);
+                svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
         else
-                svga_wcrt_mask(0x09, 0x00, 0x80);
+                svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
 
         if (info->var.vmode & FB_VMODE_INTERLACED)
-                svga_wcrt_mask(0x44, 0x04, 0x04);
+                svga_wcrt_mask(par->state.vgabase, 0x44, 0x04, 0x04);
         else
-                svga_wcrt_mask(0x44, 0x00, 0x04);
+                svga_wcrt_mask(par->state.vgabase, 0x44, 0x00, 0x04);
 
         hmul = 1;
         hdiv = 1;
@@ -699,40 +717,40 @@ static int arkfb_set_par(struct fb_info *info)
         switch (mode) {
         case 0:
                 pr_debug("fb%d: text mode\n", info->node);
-                svga_set_textmode_vga_regs();
+                svga_set_textmode_vga_regs(par->state.vgabase);
 
-                vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */
-                svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */
+                vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
+                svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
                 dac_set_mode(par->dac, DAC_PSEUDO8_8);
 
                 break;
         case 1:
                 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
-                vga_wgfx(NULL, VGA_GFX_MODE, 0x40);
+                vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
 
-                vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */
-                svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */
+                vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
+                svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
                 dac_set_mode(par->dac, DAC_PSEUDO8_8);
                 break;
         case 2:
                 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
 
-                vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */
-                svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */
+                vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
+                svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
                 dac_set_mode(par->dac, DAC_PSEUDO8_8);
                 break;
         case 3:
                 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
 
-                vga_wseq(NULL, 0x11, 0x16); /* 8bpp accel mode */
+                vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode */
 
                 if (info->var.pixclock > 20000) {
                         pr_debug("fb%d: not using multiplex\n", info->node);
-                        svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */
+                        svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
                         dac_set_mode(par->dac, DAC_PSEUDO8_8);
                 } else {
                         pr_debug("fb%d: using multiplex\n", info->node);
-                        svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
+                        svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
                         dac_set_mode(par->dac, DAC_PSEUDO8_16);
                         hdiv = 2;
                 }
@@ -740,22 +758,22 @@ static int arkfb_set_par(struct fb_info *info)
         case 4:
                 pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
 
-                vga_wseq(NULL, 0x11, 0x1A); /* 16bpp accel mode */
-                svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
+                vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
+                svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
                 dac_set_mode(par->dac, DAC_RGB1555_16);
                 break;
         case 5:
                 pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
 
-                vga_wseq(NULL, 0x11, 0x1A); /* 16bpp accel mode */
-                svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
+                vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
+                svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
                 dac_set_mode(par->dac, DAC_RGB0565_16);
                 break;
         case 6:
                 pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
 
-                vga_wseq(NULL, 0x11, 0x16); /* 8bpp accel mode ??? */
-                svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
+                vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode ??? */
+                svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
                 dac_set_mode(par->dac, DAC_RGB0888_16);
                 hmul = 3;
                 hdiv = 2;
@@ -763,8 +781,8 @@ static int arkfb_set_par(struct fb_info *info)
         case 7:
                 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
 
-                vga_wseq(NULL, 0x11, 0x1E); /* 32bpp accel mode */
-                svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
+                vga_wseq(par->state.vgabase, 0x11, 0x1E); /* 32bpp accel mode */
+                svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
                 dac_set_mode(par->dac, DAC_RGB8888_16);
                 hmul = 2;
                 break;
@@ -774,7 +792,7 @@ static int arkfb_set_par(struct fb_info *info)
         }
 
         ark_set_pixclock(info, (hdiv * info->var.pixclock) / hmul);
-        svga_set_timings(&ark_timing_regs, &(info->var), hmul, hdiv,
+        svga_set_timings(par->state.vgabase, &ark_timing_regs, &(info->var), hmul, hdiv,
                          (info->var.vmode & FB_VMODE_DOUBLE)     ? 2 : 1,
                          (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
                           hmul, info->node);
@@ -782,12 +800,12 @@ static int arkfb_set_par(struct fb_info *info)
         /* Set interlaced mode start/end register */
         value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
         value = ((value * hmul / hdiv) / 8) - 5;
-        vga_wcrt(NULL, 0x42, (value + 1) / 2);
+        vga_wcrt(par->state.vgabase, 0x42, (value + 1) / 2);
 
         memset_io(info->screen_base, 0x00, screen_size);
         /* Device and screen back on */
-        svga_wcrt_mask(0x17, 0x80, 0x80);
-        svga_wseq_mask(0x01, 0x00, 0x20);
+        svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
+        svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
 
         return 0;
 }
@@ -857,23 +875,25 @@ static int arkfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 
 static int arkfb_blank(int blank_mode, struct fb_info *info)
 {
+        struct arkfb_info *par = info->par;
+
         switch (blank_mode) {
         case FB_BLANK_UNBLANK:
                 pr_debug("fb%d: unblank\n", info->node);
-                svga_wseq_mask(0x01, 0x00, 0x20);
-                svga_wcrt_mask(0x17, 0x80, 0x80);
+                svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
+                svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
                 break;
         case FB_BLANK_NORMAL:
                 pr_debug("fb%d: blank\n", info->node);
-                svga_wseq_mask(0x01, 0x20, 0x20);
-                svga_wcrt_mask(0x17, 0x80, 0x80);
+                svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
+                svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
                 break;
         case FB_BLANK_POWERDOWN:
         case FB_BLANK_HSYNC_SUSPEND:
         case FB_BLANK_VSYNC_SUSPEND:
                 pr_debug("fb%d: sync down\n", info->node);
-                svga_wseq_mask(0x01, 0x20, 0x20);
-                svga_wcrt_mask(0x17, 0x00, 0x80);
+                svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
+                svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
                 break;
         }
         return 0;
@@ -884,6 +904,7 @@ static int arkfb_blank(int blank_mode, struct fb_info *info)
 
 static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 {
+        struct arkfb_info *par = info->par;
         unsigned int offset;
 
         /* Calculate the offset */
@@ -897,7 +918,7 @@ static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info
         }
 
         /* Set the offset */
-        svga_wcrt_multi(ark_start_address_regs, offset);
+        svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, offset);
 
         return 0;
 }
@@ -930,6 +951,8 @@ static struct fb_ops arkfb_ops = {
 /* PCI probe */
 static int __devinit ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 {
+        struct pci_bus_region bus_reg;
+        struct resource vga_res;
         struct fb_info *info;
         struct arkfb_info *par;
         int rc;
@@ -985,8 +1008,17 @@ static int __devinit ark_pci_probe(struct pci_dev *dev, const struct pci_device_
                 goto err_iomap;
         }
 
+        bus_reg.start = 0;
+        bus_reg.end = 64 * 1024;
+
+        vga_res.flags = IORESOURCE_IO;
+
+        pcibios_bus_to_resource(dev, &vga_res, &bus_reg);
+
+        par->state.vgabase = (void __iomem *) vga_res.start;
+
         /* FIXME get memsize */
-        regval = vga_rseq(NULL, 0x10);
+        regval = vga_rseq(par->state.vgabase, 0x10);
         info->screen_size = (1 << (regval >> 6)) << 20;
         info->fix.smem_len = info->screen_size;
 
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index bac163450216..ccecf9974587 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -68,7 +68,7 @@ static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
 }
 #endif
 
-static const u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
+static u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
                 | ATMEL_LCDC_POL_POSITIVE
                 | ATMEL_LCDC_ENA_PWMENABLE;
 
@@ -127,6 +127,7 @@ static void init_backlight(struct atmel_lcdfb_info *sinfo)
                 return;
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = 0xff;
         bl = backlight_device_register("backlight", &sinfo->pdev->dev, sinfo,
                                        &atmel_lcdc_bl_ops, &props);
@@ -163,6 +164,10 @@ static void exit_backlight(struct atmel_lcdfb_info *sinfo)
 
 static void init_contrast(struct atmel_lcdfb_info *sinfo)
 {
+        /* contrast pwm can be 'inverted' */
+        if (sinfo->lcdcon_pol_negative)
+                        contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE);
+
         /* have some default contrast/backlight settings */
         lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
         lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
@@ -710,11 +715,35 @@ static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
         return 0;
 }
 
+static int atmel_lcdfb_blank(int blank_mode, struct fb_info *info)
+{
+        struct atmel_lcdfb_info *sinfo = info->par;
+
+        switch (blank_mode) {
+        case FB_BLANK_UNBLANK:
+        case FB_BLANK_NORMAL:
+                atmel_lcdfb_start(sinfo);
+                break;
+        case FB_BLANK_VSYNC_SUSPEND:
+        case FB_BLANK_HSYNC_SUSPEND:
+                break;
+        case FB_BLANK_POWERDOWN:
+                atmel_lcdfb_stop(sinfo);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* let fbcon do a soft blank for us */
+        return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
+}
+
 static struct fb_ops atmel_lcdfb_ops = {
         .owner          = THIS_MODULE,
         .fb_check_var   = atmel_lcdfb_check_var,
         .fb_set_par     = atmel_lcdfb_set_par,
         .fb_setcolreg   = atmel_lcdfb_setcolreg,
+        .fb_blank       = atmel_lcdfb_blank,
         .fb_pan_display = atmel_lcdfb_pan_display,
         .fb_fillrect    = cfb_fillrect,
         .fb_copyarea    = cfb_copyarea,
@@ -816,6 +845,7 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
                 sinfo->guard_time = pdata_sinfo->guard_time;
                 sinfo->smem_len = pdata_sinfo->smem_len;
                 sinfo->lcdcon_is_backlight = pdata_sinfo->lcdcon_is_backlight;
+                sinfo->lcdcon_pol_negative = pdata_sinfo->lcdcon_pol_negative;
                 sinfo->lcd_wiring_mode = pdata_sinfo->lcd_wiring_mode;
         } else {
                 dev_err(dev, "cannot get default configuration\n");
diff --git a/drivers/video/aty/aty128fb.c b/drivers/video/aty/aty128fb.c
index 4cb6a576c567..b0b2ac335347 100644
--- a/drivers/video/aty/aty128fb.c
+++ b/drivers/video/aty/aty128fb.c
@@ -1818,6 +1818,7 @@ static void aty128_bl_init(struct aty128fb_par *par)
         snprintf(name, sizeof(name), "aty128bl%d", info->node);
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
         bd = backlight_device_register(name, info->dev, par, &aty128_bl_data,
                                        &props);
diff --git a/drivers/video/aty/atyfb_base.c b/drivers/video/aty/atyfb_base.c
index 94e293fce1d2..d437b3daf1f5 100644
--- a/drivers/video/aty/atyfb_base.c
+++ b/drivers/video/aty/atyfb_base.c
@@ -2241,6 +2241,7 @@ static void aty_bl_init(struct atyfb_par *par)
         snprintf(name, sizeof(name), "atybl%d", info->node);
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
         bd = backlight_device_register(name, info->dev, par, &aty_bl_data,
                                        &props);
diff --git a/drivers/video/aty/radeon_backlight.c b/drivers/video/aty/radeon_backlight.c
index 9b811ddbce83..db572df7e1ef 100644
--- a/drivers/video/aty/radeon_backlight.c
+++ b/drivers/video/aty/radeon_backlight.c
@@ -158,6 +158,7 @@ void radeonfb_bl_init(struct radeonfb_info *rinfo)
         snprintf(name, sizeof(name), "radeonbl%d", rinfo->info->node);
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
         bd = backlight_device_register(name, rinfo->info->dev, pdata,
                                        &radeon_bl_data, &props);
diff --git a/drivers/video/aty/radeon_base.c b/drivers/video/aty/radeon_base.c
index 3c1e13ed1cba..32f8cf6200a7 100644
--- a/drivers/video/aty/radeon_base.c
+++ b/drivers/video/aty/radeon_base.c
@@ -1248,7 +1248,7 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg
 
         /* Workaround from XFree */
         if (rinfo->is_mobility) {
-                /* A temporal workaround for the occational blanking on certain laptop
+                /* A temporal workaround for the occasional blanking on certain laptop
                  * panels. This appears to related to the PLL divider registers
                  * (fail to lock?). It occurs even when all dividers are the same
                  * with their old settings. In this case we really don't need to
diff --git a/drivers/video/aty/radeon_i2c.c b/drivers/video/aty/radeon_i2c.c
index 78d1f4cd1fe0..ab1d0fd76316 100644
--- a/drivers/video/aty/radeon_i2c.c
+++ b/drivers/video/aty/radeon_i2c.c
@@ -100,6 +100,9 @@ void radeon_create_i2c_busses(struct radeonfb_info *rinfo)
 {
         rinfo->i2c[0].rinfo     = rinfo;
         rinfo->i2c[0].ddc_reg   = GPIO_MONID;
+#ifndef CONFIG_PPC
+        rinfo->i2c[0].adapter.class = I2C_CLASS_HWMON;
+#endif
         radeon_setup_i2c_bus(&rinfo->i2c[0], "monid");
 
         rinfo->i2c[1].rinfo     = rinfo;
diff --git a/drivers/video/backlight/88pm860x_bl.c b/drivers/video/backlight/88pm860x_bl.c
index b224396b86d5..c8b520e9a11a 100644
--- a/drivers/video/backlight/88pm860x_bl.c
+++ b/drivers/video/backlight/88pm860x_bl.c
@@ -12,11 +12,12 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
 #include <linux/fb.h>
 #include <linux/i2c.h>
 #include <linux/backlight.h>
+#include <linux/mfd/core.h>
 #include <linux/mfd/88pm860x.h>
-#include <linux/slab.h>
 
 #define MAX_BRIGHTNESS          (0xFF)
 #define MIN_BRIGHTNESS          (0)
@@ -161,32 +162,13 @@ static const struct backlight_ops pm860x_backlight_ops = {
         .get_brightness = pm860x_backlight_get_brightness,
 };
 
-static int __check_device(struct pm860x_backlight_pdata *pdata, char *name)
-{
-        struct pm860x_backlight_pdata *p = pdata;
-        int ret = -EINVAL;
-
-        while (p && p->id) {
-                if ((p->id != PM8606_ID_BACKLIGHT) || (p->flags < 0))
-                        break;
-
-                if (!strncmp(name, pm860x_backlight_name[p->flags],
-                        MFD_NAME_SIZE)) {
-                        ret = (int)p->flags;
-                        break;
-                }
-                p++;
-        }
-        return ret;
-}
-
 static int pm860x_backlight_probe(struct platform_device *pdev)
 {
         struct pm860x_chip *chip = dev_get_drvdata(pdev->dev.parent);
-        struct pm860x_platform_data *pm860x_pdata;
         struct pm860x_backlight_pdata *pdata = NULL;
         struct pm860x_backlight_data *data;
         struct backlight_device *bl;
+        struct mfd_cell *cell;
         struct resource *res;
         struct backlight_properties props;
         unsigned char value;
@@ -199,10 +181,10 @@ static int pm860x_backlight_probe(struct platform_device *pdev)
                 return -EINVAL;
         }
 
-        if (pdev->dev.parent->platform_data) {
-                pm860x_pdata = pdev->dev.parent->platform_data;
-                pdata = pm860x_pdata->backlight;
-        }
+        cell = pdev->dev.platform_data;
+        if (cell == NULL)
+                return -ENODEV;
+        pdata = cell->mfd_data;
         if (pdata == NULL) {
                 dev_err(&pdev->dev, "platform data isn't assigned to "
                         "backlight\n");
@@ -219,7 +201,7 @@ static int pm860x_backlight_probe(struct platform_device *pdev)
         data->current_brightness = MAX_BRIGHTNESS;
         data->pwm = pdata->pwm;
         data->iset = pdata->iset;
-        data->port = __check_device(pdata, name);
+        data->port = pdata->flags;
         if (data->port < 0) {
                 dev_err(&pdev->dev, "wrong platform data is assigned");
                 kfree(data);
@@ -227,6 +209,7 @@ static int pm860x_backlight_probe(struct platform_device *pdev)
         }
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = MAX_BRIGHTNESS;
         bl = backlight_device_register(name, &pdev->dev, data,
                                         &pm860x_backlight_ops, &props);
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
index e54a337227ea..0c9373bedd1f 100644
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -109,6 +109,14 @@ config LCD_S6E63M0
           If you have an S6E63M0 LCD Panel, say Y to enable its
           LCD control driver.
 
+config LCD_LD9040
+        tristate "LD9040 AMOLED LCD Driver"
+        depends on SPI && BACKLIGHT_CLASS_DEVICE
+        default n
+        help
+          If you have an LD9040 Panel, say Y to enable its
+          control driver.
+
 endif # LCD_CLASS_DEVICE
 
 #
@@ -236,12 +244,12 @@ config BACKLIGHT_MAX8925
           If you have a LCD backlight connected to the WLED output of MAX8925
           WLED output, say Y here to enable this driver.
 
-config BACKLIGHT_MBP_NVIDIA
-       tristate "MacBook Pro Nvidia Backlight Driver"
-       depends on X86
+config BACKLIGHT_APPLE
+       tristate "Apple Backlight Driver"
+       depends on X86 && ACPI
        help
-         If you have an Apple Macbook Pro with Nvidia graphics hardware say Y
-         to enable a driver for its backlight
+         If you have an Intel-based Apple say Y to enable a driver for its
+         backlight.
 
 config BACKLIGHT_TOSA
         tristate "Sharp SL-6000 Backlight Driver"
diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
index 44c0f81ad85d..b9ca8490df87 100644
--- a/drivers/video/backlight/Makefile
+++ b/drivers/video/backlight/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_LCD_VGG2432A4)	   += vgg2432a4.o
 obj-$(CONFIG_LCD_TDO24M)           += tdo24m.o
 obj-$(CONFIG_LCD_TOSA)             += tosa_lcd.o
 obj-$(CONFIG_LCD_S6E63M0)       += s6e63m0.o
+obj-$(CONFIG_LCD_LD9040)        += ld9040.o
 
 obj-$(CONFIG_BACKLIGHT_CLASS_DEVICE) += backlight.o
 obj-$(CONFIG_BACKLIGHT_ATMEL_PWM)    += atmel-pwm-bl.o
@@ -26,7 +27,7 @@ obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o
 obj-$(CONFIG_BACKLIGHT_PWM)     += pwm_bl.o
 obj-$(CONFIG_BACKLIGHT_DA903X)  += da903x_bl.o
 obj-$(CONFIG_BACKLIGHT_MAX8925) += max8925_bl.o
-obj-$(CONFIG_BACKLIGHT_MBP_NVIDIA) += mbp_nvidia_bl.o
+obj-$(CONFIG_BACKLIGHT_APPLE)   += apple_bl.o
 obj-$(CONFIG_BACKLIGHT_TOSA)    += tosa_bl.o
 obj-$(CONFIG_BACKLIGHT_SAHARA)  += kb3886_bl.o
 obj-$(CONFIG_BACKLIGHT_WM831X)  += wm831x_bl.o
diff --git a/drivers/video/backlight/adp5520_bl.c b/drivers/video/backlight/adp5520_bl.c
index 9f436e014f85..af3119707dbf 100644
--- a/drivers/video/backlight/adp5520_bl.c
+++ b/drivers/video/backlight/adp5520_bl.c
@@ -303,6 +303,7 @@ static int __devinit adp5520_bl_probe(struct platform_device *pdev)
         mutex_init(&data->lock);
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = ADP5020_MAX_BRIGHTNESS;
         bl = backlight_device_register(pdev->name, data->master, data,
                                        &adp5520_bl_ops, &props);
diff --git a/drivers/video/backlight/adp8860_bl.c b/drivers/video/backlight/adp8860_bl.c
index 734c650a47c4..d2a96a421ffd 100644
--- a/drivers/video/backlight/adp8860_bl.c
+++ b/drivers/video/backlight/adp8860_bl.c
@@ -709,6 +709,7 @@ static int __devinit adp8860_probe(struct i2c_client *client,
         i2c_set_clientdata(client, data);
 
         memset(&props, 0, sizeof(props));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = ADP8860_MAX_BRIGHTNESS;
 
         mutex_init(&data->lock);
diff --git a/drivers/video/backlight/adx_bl.c b/drivers/video/backlight/adx_bl.c
index fe9af129c5dd..c861c41af442 100644
--- a/drivers/video/backlight/adx_bl.c
+++ b/drivers/video/backlight/adx_bl.c
@@ -104,6 +104,7 @@ static int __devinit adx_backlight_probe(struct platform_device *pdev)
         }
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = 0xff;
         bldev = backlight_device_register(dev_name(&pdev->dev), &pdev->dev,
                                           bl, &adx_backlight_ops, &props);
diff --git a/drivers/video/backlight/apple_bl.c b/drivers/video/backlight/apple_bl.c
new file mode 100644
index 000000000000..be98d152b7fd
--- /dev/null
+++ b/drivers/video/backlight/apple_bl.c
@@ -0,0 +1,241 @@
+/*
+ *  Backlight Driver for Intel-based Apples
+ *
+ *  Copyright (c) Red Hat <mjg@redhat.com>
+ *  Based on code from Pommed:
+ *  Copyright (C) 2006 Nicolas Boichat <nicolas @boichat.ch>
+ *  Copyright (C) 2006 Felipe Alfaro Solana <felipe_alfaro @linuxmail.org>
+ *  Copyright (C) 2007 Julien BLACHE <jb@jblache.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This driver triggers SMIs which cause the firmware to change the
+ *  backlight brightness. This is icky in many ways, but it's impractical to
+ *  get at the firmware code in order to figure out what it's actually doing.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/backlight.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/pci.h>
+#include <linux/acpi.h>
+
+static struct backlight_device *apple_backlight_device;
+
+struct hw_data {
+        /* I/O resource to allocate. */
+        unsigned long iostart;
+        unsigned long iolen;
+        /* Backlight operations structure. */
+        const struct backlight_ops backlight_ops;
+        void (*set_brightness)(int);
+};
+
+static const struct hw_data *hw_data;
+
+#define DRIVER "apple_backlight: "
+
+/* Module parameters. */
+static int debug;
+module_param_named(debug, debug, int, 0644);
+MODULE_PARM_DESC(debug, "Set to one to enable debugging messages.");
+
+/*
+ * Implementation for machines with Intel chipset.
+ */
+static void intel_chipset_set_brightness(int intensity)
+{
+        outb(0x04 | (intensity << 4), 0xb3);
+        outb(0xbf, 0xb2);
+}
+
+static int intel_chipset_send_intensity(struct backlight_device *bd)
+{
+        int intensity = bd->props.brightness;
+
+        if (debug)
+                printk(KERN_DEBUG DRIVER "setting brightness to %d\n",
+                       intensity);
+
+        intel_chipset_set_brightness(intensity);
+        return 0;
+}
+
+static int intel_chipset_get_intensity(struct backlight_device *bd)
+{
+        int intensity;
+
+        outb(0x03, 0xb3);
+        outb(0xbf, 0xb2);
+        intensity = inb(0xb3) >> 4;
+
+        if (debug)
+                printk(KERN_DEBUG DRIVER "read brightness of %d\n",
+                       intensity);
+
+        return intensity;
+}
+
+static const struct hw_data intel_chipset_data = {
+        .iostart = 0xb2,
+        .iolen = 2,
+        .backlight_ops  = {
+                .options        = BL_CORE_SUSPENDRESUME,
+                .get_brightness = intel_chipset_get_intensity,
+                .update_status  = intel_chipset_send_intensity,
+        },
+        .set_brightness = intel_chipset_set_brightness,
+};
+
+/*
+ * Implementation for machines with Nvidia chipset.
+ */
+static void nvidia_chipset_set_brightness(int intensity)
+{
+        outb(0x04 | (intensity << 4), 0x52f);
+        outb(0xbf, 0x52e);
+}
+
+static int nvidia_chipset_send_intensity(struct backlight_device *bd)
+{
+        int intensity = bd->props.brightness;
+
+        if (debug)
+                printk(KERN_DEBUG DRIVER "setting brightness to %d\n",
+                       intensity);
+
+        nvidia_chipset_set_brightness(intensity);
+        return 0;
+}
+
+static int nvidia_chipset_get_intensity(struct backlight_device *bd)
+{
+        int intensity;
+
+        outb(0x03, 0x52f);
+        outb(0xbf, 0x52e);
+        intensity = inb(0x52f) >> 4;
+
+        if (debug)
+                printk(KERN_DEBUG DRIVER "read brightness of %d\n",
+                       intensity);
+
+        return intensity;
+}
+
+static const struct hw_data nvidia_chipset_data = {
+        .iostart = 0x52e,
+        .iolen = 2,
+        .backlight_ops          = {
+                .options        = BL_CORE_SUSPENDRESUME,
+                .get_brightness = nvidia_chipset_get_intensity,
+                .update_status  = nvidia_chipset_send_intensity
+        },
+        .set_brightness = nvidia_chipset_set_brightness,
+};
+
+static int __devinit apple_bl_add(struct acpi_device *dev)
+{
+        struct backlight_properties props;
+        struct pci_dev *host;
+        int intensity;
+
+        host = pci_get_bus_and_slot(0, 0);
+
+        if (!host) {
+                printk(KERN_ERR DRIVER "unable to find PCI host\n");
+                return -ENODEV;
+        }
+
+        if (host->vendor == PCI_VENDOR_ID_INTEL)
+                hw_data = &intel_chipset_data;
+        else if (host->vendor == PCI_VENDOR_ID_NVIDIA)
+                hw_data = &nvidia_chipset_data;
+
+        pci_dev_put(host);
+
+        if (!hw_data) {
+                printk(KERN_ERR DRIVER "unknown hardware\n");
+                return -ENODEV;
+        }
+
+        /* Check that the hardware responds - this may not work under EFI */
+
+        intensity = hw_data->backlight_ops.get_brightness(NULL);
+
+        if (!intensity) {
+                hw_data->set_brightness(1);
+                if (!hw_data->backlight_ops.get_brightness(NULL))
+                        return -ENODEV;
+
+                hw_data->set_brightness(0);
+        }
+
+        if (!request_region(hw_data->iostart, hw_data->iolen,
+                            "Apple backlight"))
+                return -ENXIO;
+
+        memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_PLATFORM;
+        props.max_brightness = 15;
+        apple_backlight_device = backlight_device_register("apple_backlight",
+                                  NULL, NULL, &hw_data->backlight_ops, &props);
+
+        if (IS_ERR(apple_backlight_device)) {
+                release_region(hw_data->iostart, hw_data->iolen);
+                return PTR_ERR(apple_backlight_device);
+        }
+
+        apple_backlight_device->props.brightness =
+                hw_data->backlight_ops.get_brightness(apple_backlight_device);
+        backlight_update_status(apple_backlight_device);
+
+        return 0;
+}
+
+static int __devexit apple_bl_remove(struct acpi_device *dev, int type)
+{
+        backlight_device_unregister(apple_backlight_device);
+
+        release_region(hw_data->iostart, hw_data->iolen);
+        hw_data = NULL;
+        return 0;
+}
+
+static const struct acpi_device_id apple_bl_ids[] = {
+        {"APP0002", 0},
+        {"", 0},
+};
+
+static struct acpi_driver apple_bl_driver = {
+        .name = "Apple backlight",
+        .ids = apple_bl_ids,
+        .ops = {
+                .add = apple_bl_add,
+                .remove = apple_bl_remove,
+        },
+};
+
+static int __init apple_bl_init(void)
+{
+        return acpi_bus_register_driver(&apple_bl_driver);
+}
+
+static void __exit apple_bl_exit(void)
+{
+        acpi_bus_unregister_driver(&apple_bl_driver);
+}
+
+module_init(apple_bl_init);
+module_exit(apple_bl_exit);
+
+MODULE_AUTHOR("Matthew Garrett <mjg@redhat.com>");
+MODULE_DESCRIPTION("Apple Backlight Driver");
+MODULE_LICENSE("GPL");
+MODULE_DEVICE_TABLE(acpi, apple_bl_ids);
+MODULE_ALIAS("mbp_nvidia_bl");
diff --git a/drivers/video/backlight/atmel-pwm-bl.c b/drivers/video/backlight/atmel-pwm-bl.c
index e6a66dab088c..0443a4f71858 100644
--- a/drivers/video/backlight/atmel-pwm-bl.c
+++ b/drivers/video/backlight/atmel-pwm-bl.c
@@ -168,6 +168,7 @@ static int atmel_pwm_bl_probe(struct platform_device *pdev)
         }
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = pdata->pwm_duty_max - pdata->pwm_duty_min;
         bldev = backlight_device_register("atmel-pwm-bl", &pdev->dev, pwmbl,
                                           &atmel_pwm_bl_ops, &props);
diff --git a/drivers/video/backlight/backlight.c b/drivers/video/backlight/backlight.c
index 08703299ef61..80d292fb92d8 100644
--- a/drivers/video/backlight/backlight.c
+++ b/drivers/video/backlight/backlight.c
@@ -19,6 +19,12 @@
 #include <asm/backlight.h>
 #endif
 
+static const char const *backlight_types[] = {
+        [BACKLIGHT_RAW] = "raw",
+        [BACKLIGHT_PLATFORM] = "platform",
+        [BACKLIGHT_FIRMWARE] = "firmware",
+};
+
 #if defined(CONFIG_FB) || (defined(CONFIG_FB_MODULE) && \
                            defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE))
 /* This callback gets called when something important happens inside a
@@ -169,6 +175,14 @@ static ssize_t backlight_store_brightness(struct device *dev,
         return rc;
 }
 
+static ssize_t backlight_show_type(struct device *dev,
+                struct device_attribute *attr, char *buf)
+{
+        struct backlight_device *bd = to_backlight_device(dev);
+
+        return sprintf(buf, "%s\n", backlight_types[bd->props.type]);
+}
+
 static ssize_t backlight_show_max_brightness(struct device *dev,
                 struct device_attribute *attr, char *buf)
 {
@@ -234,6 +248,7 @@ static struct device_attribute bl_device_attributes[] = {
         __ATTR(actual_brightness, 0444, backlight_show_actual_brightness,
                      NULL),
         __ATTR(max_brightness, 0444, backlight_show_max_brightness, NULL),
+        __ATTR(type, 0444, backlight_show_type, NULL),
         __ATTR_NULL,
 };
 
@@ -292,9 +307,16 @@ struct backlight_device *backlight_device_register(const char *name,
         dev_set_drvdata(&new_bd->dev, devdata);
 
         /* Set default properties */
-        if (props)
+        if (props) {
                 memcpy(&new_bd->props, props,
                        sizeof(struct backlight_properties));
+                if (props->type <= 0 || props->type >= BACKLIGHT_TYPE_MAX) {
+                        WARN(1, "%s: invalid backlight type", name);
+                        new_bd->props.type = BACKLIGHT_RAW;
+                }
+        } else {
+                new_bd->props.type = BACKLIGHT_RAW;
+        }
 
         rc = device_register(&new_bd->dev);
         if (rc) {
diff --git a/drivers/video/backlight/corgi_lcd.c b/drivers/video/backlight/corgi_lcd.c
index 1e71c35083bb..af6098396fe6 100644
--- a/drivers/video/backlight/corgi_lcd.c
+++ b/drivers/video/backlight/corgi_lcd.c
@@ -562,6 +562,7 @@ static int __devinit corgi_lcd_probe(struct spi_device *spi)
         lcd->mode = (pdata) ? pdata->init_mode : CORGI_LCD_MODE_VGA;
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = pdata->max_intensity;
         lcd->bl_dev = backlight_device_register("corgi_bl", &spi->dev, lcd,
                                                 &corgi_bl_ops, &props);
diff --git a/drivers/video/backlight/cr_bllcd.c b/drivers/video/backlight/cr_bllcd.c
index 397d15eb1ea8..6c8c54041fae 100644
--- a/drivers/video/backlight/cr_bllcd.c
+++ b/drivers/video/backlight/cr_bllcd.c
@@ -193,6 +193,7 @@ static int cr_backlight_probe(struct platform_device *pdev)
         }
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         bdp = backlight_device_register("cr-backlight", &pdev->dev, NULL,
                                         &cr_backlight_ops, &props);
         if (IS_ERR(bdp)) {
diff --git a/drivers/video/backlight/da903x_bl.c b/drivers/video/backlight/da903x_bl.c
index 87659ed79bd7..62043f12a5a4 100644
--- a/drivers/video/backlight/da903x_bl.c
+++ b/drivers/video/backlight/da903x_bl.c
@@ -136,6 +136,7 @@ static int da903x_backlight_probe(struct platform_device *pdev)
                 da903x_write(data->da903x_dev, DA9034_WLED_CONTROL2,
                                 DA9034_WLED_ISET(pdata->output_current));
 
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = max_brightness;
         bl = backlight_device_register(pdev->name, data->da903x_dev, data,
                                        &da903x_backlight_ops, &props);
diff --git a/drivers/video/backlight/ep93xx_bl.c b/drivers/video/backlight/ep93xx_bl.c
index b0cc49184803..9f1e389d51d2 100644
--- a/drivers/video/backlight/ep93xx_bl.c
+++ b/drivers/video/backlight/ep93xx_bl.c
@@ -87,6 +87,7 @@ static int __init ep93xxbl_probe(struct platform_device *dev)
         ep93xxbl->mmio = EP93XX_RASTER_BRIGHTNESS;
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = EP93XX_MAX_BRIGHT;
         bl = backlight_device_register(dev->name, &dev->dev, ep93xxbl,
                                        &ep93xxbl_ops, &props);
diff --git a/drivers/video/backlight/generic_bl.c b/drivers/video/backlight/generic_bl.c
index 312ca619735d..8c6befd65a33 100644
--- a/drivers/video/backlight/generic_bl.c
+++ b/drivers/video/backlight/generic_bl.c
@@ -91,6 +91,7 @@ static int genericbl_probe(struct platform_device *pdev)
                 name = machinfo->name;
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = machinfo->max_intensity;
         bd = backlight_device_register(name, &pdev->dev, NULL, &genericbl_ops,
                                        &props);
diff --git a/drivers/video/backlight/hp680_bl.c b/drivers/video/backlight/hp680_bl.c
index 267d23f8d645..38aa00272141 100644
--- a/drivers/video/backlight/hp680_bl.c
+++ b/drivers/video/backlight/hp680_bl.c
@@ -109,6 +109,7 @@ static int __devinit hp680bl_probe(struct platform_device *pdev)
         struct backlight_device *bd;
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = HP680_MAX_INTENSITY;
         bd = backlight_device_register("hp680-bl", &pdev->dev, NULL,
                                        &hp680bl_ops, &props);
diff --git a/drivers/video/backlight/jornada720_bl.c b/drivers/video/backlight/jornada720_bl.c
index 2f177b3a4885..de65d80159be 100644
--- a/drivers/video/backlight/jornada720_bl.c
+++ b/drivers/video/backlight/jornada720_bl.c
@@ -106,6 +106,7 @@ static int jornada_bl_probe(struct platform_device *pdev)
         struct backlight_device *bd;
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = BL_MAX_BRIGHT;
         bd = backlight_device_register(S1D_DEVICENAME, &pdev->dev, NULL,
                                        &jornada_bl_ops, &props);
@@ -146,12 +147,12 @@ static struct platform_driver jornada_bl_driver = {
         },
 };
 
-int __init jornada_bl_init(void)
+static int __init jornada_bl_init(void)
 {
         return platform_driver_register(&jornada_bl_driver);
 }
 
-void __exit jornada_bl_exit(void)
+static void __exit jornada_bl_exit(void)
 {
         platform_driver_unregister(&jornada_bl_driver);
 }
diff --git a/drivers/video/backlight/jornada720_lcd.c b/drivers/video/backlight/jornada720_lcd.c
index cbbb167fd268..d2ff658b4144 100644
--- a/drivers/video/backlight/jornada720_lcd.c
+++ b/drivers/video/backlight/jornada720_lcd.c
@@ -135,12 +135,12 @@ static struct platform_driver jornada_lcd_driver = {
         },
 };
 
-int __init jornada_lcd_init(void)
+static int __init jornada_lcd_init(void)
 {
         return platform_driver_register(&jornada_lcd_driver);
 }
 
-void __exit jornada_lcd_exit(void)
+static void __exit jornada_lcd_exit(void)
 {
         platform_driver_unregister(&jornada_lcd_driver);
 }
diff --git a/drivers/video/backlight/kb3886_bl.c b/drivers/video/backlight/kb3886_bl.c
index f439a8632287..72dd5556a35b 100644
--- a/drivers/video/backlight/kb3886_bl.c
+++ b/drivers/video/backlight/kb3886_bl.c
@@ -149,6 +149,7 @@ static int kb3886bl_probe(struct platform_device *pdev)
                 machinfo->limit_mask = -1;
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = machinfo->max_intensity;
         kb3886_backlight_device = backlight_device_register("kb3886-bl",
                                                             &pdev->dev, NULL,
diff --git a/drivers/video/backlight/ld9040.c b/drivers/video/backlight/ld9040.c
new file mode 100644
index 000000000000..7281b2506a67
--- /dev/null
+++ b/drivers/video/backlight/ld9040.c
@@ -0,0 +1,819 @@
+/*
+ * ld9040 AMOLED LCD panel driver.
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ * Author: Donghwa Lee  <dh09.lee@samsung.com>
+ * Derived from drivers/video/backlight/s6e63m0.c
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#include <linux/wait.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/spi/spi.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/lcd.h>
+#include <linux/backlight.h>
+
+#include "ld9040_gamma.h"
+
+#define SLEEPMSEC               0x1000
+#define ENDDEF                  0x2000
+#define DEFMASK                 0xFF00
+#define COMMAND_ONLY            0xFE
+#define DATA_ONLY               0xFF
+
+#define MIN_BRIGHTNESS          0
+#define MAX_BRIGHTNESS          24
+#define power_is_on(pwr)        ((pwr) <= FB_BLANK_NORMAL)
+
+struct ld9040 {
+        struct device                   *dev;
+        struct spi_device               *spi;
+        unsigned int                    power;
+        unsigned int                    current_brightness;
+
+        struct lcd_device               *ld;
+        struct backlight_device         *bd;
+        struct lcd_platform_data        *lcd_pd;
+};
+
+static const unsigned short seq_swreset[] = {
+        0x01, COMMAND_ONLY,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_user_setting[] = {
+        0xF0, 0x5A,
+
+        DATA_ONLY, 0x5A,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_elvss_on[] = {
+        0xB1, 0x0D,
+
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x16,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_gtcon[] = {
+        0xF7, 0x09,
+
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_panel_condition[] = {
+        0xF8, 0x05,
+
+        DATA_ONLY, 0x65,
+        DATA_ONLY, 0x96,
+        DATA_ONLY, 0x71,
+        DATA_ONLY, 0x7D,
+        DATA_ONLY, 0x19,
+        DATA_ONLY, 0x3B,
+        DATA_ONLY, 0x0D,
+        DATA_ONLY, 0x19,
+        DATA_ONLY, 0x7E,
+        DATA_ONLY, 0x0D,
+        DATA_ONLY, 0xE2,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x7E,
+        DATA_ONLY, 0x7D,
+        DATA_ONLY, 0x07,
+        DATA_ONLY, 0x07,
+        DATA_ONLY, 0x20,
+        DATA_ONLY, 0x20,
+        DATA_ONLY, 0x20,
+        DATA_ONLY, 0x02,
+        DATA_ONLY, 0x02,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_gamma_set1[] = {
+        0xF9, 0x00,
+
+        DATA_ONLY, 0xA7,
+        DATA_ONLY, 0xB4,
+        DATA_ONLY, 0xAE,
+        DATA_ONLY, 0xBF,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x91,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0xB2,
+        DATA_ONLY, 0xB4,
+        DATA_ONLY, 0xAA,
+        DATA_ONLY, 0xBB,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0xAC,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0xB3,
+        DATA_ONLY, 0xB1,
+        DATA_ONLY, 0xAA,
+        DATA_ONLY, 0xBC,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0xB3,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_gamma_ctrl[] = {
+        0xFB, 0x02,
+
+        DATA_ONLY, 0x5A,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_gamma_start[] = {
+        0xF9, COMMAND_ONLY,
+
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_apon[] = {
+        0xF3, 0x00,
+
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x0A,
+        DATA_ONLY, 0x02,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_display_ctrl[] = {
+        0xF2, 0x02,
+
+        DATA_ONLY, 0x08,
+        DATA_ONLY, 0x08,
+        DATA_ONLY, 0x10,
+        DATA_ONLY, 0x10,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_manual_pwr[] = {
+        0xB0, 0x04,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_pwr_ctrl[] = {
+        0xF4, 0x0A,
+
+        DATA_ONLY, 0x87,
+        DATA_ONLY, 0x25,
+        DATA_ONLY, 0x6A,
+        DATA_ONLY, 0x44,
+        DATA_ONLY, 0x02,
+        DATA_ONLY, 0x88,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_sleep_out[] = {
+        0x11, COMMAND_ONLY,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_sleep_in[] = {
+        0x10, COMMAND_ONLY,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_display_on[] = {
+        0x29, COMMAND_ONLY,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_display_off[] = {
+        0x28, COMMAND_ONLY,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_vci1_1st_en[] = {
+        0xF3, 0x10,
+
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x02,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_vl1_en[] = {
+        0xF3, 0x11,
+
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x02,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_vl2_en[] = {
+        0xF3, 0x13,
+
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x02,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_vci1_2nd_en[] = {
+        0xF3, 0x33,
+
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x02,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_vl3_en[] = {
+        0xF3, 0x37,
+
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x02,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_vreg1_amp_en[] = {
+        0xF3, 0x37,
+
+        DATA_ONLY, 0x01,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x02,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_vgh_amp_en[] = {
+        0xF3, 0x37,
+
+        DATA_ONLY, 0x11,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x02,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_vgl_amp_en[] = {
+        0xF3, 0x37,
+
+        DATA_ONLY, 0x31,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x02,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_vmos_amp_en[] = {
+        0xF3, 0x37,
+
+        DATA_ONLY, 0xB1,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x03,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_vint_amp_en[] = {
+        0xF3, 0x37,
+
+        DATA_ONLY, 0xF1,
+        /* DATA_ONLY, 0x71,     VMOS/VBL/VBH not used */
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x03,
+        /* DATA_ONLY, 0x02,     VMOS/VBL/VBH not used */
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_vbh_amp_en[] = {
+        0xF3, 0x37,
+
+        DATA_ONLY, 0xF9,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x03,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_vbl_amp_en[] = {
+        0xF3, 0x37,
+
+        DATA_ONLY, 0xFD,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x03,
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_gam_amp_en[] = {
+        0xF3, 0x37,
+
+        DATA_ONLY, 0xFF,
+        /* DATA_ONLY, 0x73,     VMOS/VBL/VBH not used */
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x03,
+        /* DATA_ONLY, 0x02,     VMOS/VBL/VBH not used */
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_sd_amp_en[] = {
+        0xF3, 0x37,
+
+        DATA_ONLY, 0xFF,
+        /* DATA_ONLY, 0x73,     VMOS/VBL/VBH not used */
+        DATA_ONLY, 0x80,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x03,
+        /* DATA_ONLY, 0x02,     VMOS/VBL/VBH not used */
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_gls_en[] = {
+        0xF3, 0x37,
+
+        DATA_ONLY, 0xFF,
+        /* DATA_ONLY, 0x73,     VMOS/VBL/VBH not used */
+        DATA_ONLY, 0x81,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x03,
+        /* DATA_ONLY, 0x02,     VMOS/VBL/VBH not used */
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_els_en[] = {
+        0xF3, 0x37,
+
+        DATA_ONLY, 0xFF,
+        /* DATA_ONLY, 0x73,     VMOS/VBL/VBH not used */
+        DATA_ONLY, 0x83,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x03,
+        /* DATA_ONLY, 0x02,     VMOS/VBL/VBH not used */
+        ENDDEF, 0x00
+};
+
+static const unsigned short seq_el_on[] = {
+        0xF3, 0x37,
+
+        DATA_ONLY, 0xFF,
+        /* DATA_ONLY, 0x73,     VMOS/VBL/VBH not used */
+        DATA_ONLY, 0x87,
+        DATA_ONLY, 0x00,
+        DATA_ONLY, 0x03,
+        /* DATA_ONLY, 0x02,     VMOS/VBL/VBH not used */
+        ENDDEF, 0x00
+};
+
+static int ld9040_spi_write_byte(struct ld9040 *lcd, int addr, int data)
+{
+        u16 buf[1];
+        struct spi_message msg;
+
+        struct spi_transfer xfer = {
+                .len            = 2,
+                .tx_buf         = buf,
+        };
+
+        buf[0] = (addr << 8) | data;
+
+        spi_message_init(&msg);
+        spi_message_add_tail(&xfer, &msg);
+
+        return spi_sync(lcd->spi, &msg);
+}
+
+static int ld9040_spi_write(struct ld9040 *lcd, unsigned char address,
+        unsigned char command)
+{
+        int ret = 0;
+
+        if (address != DATA_ONLY)
+                ret = ld9040_spi_write_byte(lcd, 0x0, address);
+        if (command != COMMAND_ONLY)
+                ret = ld9040_spi_write_byte(lcd, 0x1, command);
+
+        return ret;
+}
+
+static int ld9040_panel_send_sequence(struct ld9040 *lcd,
+        const unsigned short *wbuf)
+{
+        int ret = 0, i = 0;
+
+        while ((wbuf[i] & DEFMASK) != ENDDEF) {
+                if ((wbuf[i] & DEFMASK) != SLEEPMSEC) {
+                        ret = ld9040_spi_write(lcd, wbuf[i], wbuf[i+1]);
+                        if (ret)
+                                break;
+                } else
+                        udelay(wbuf[i+1]*1000);
+                i += 2;
+        }
+
+        return ret;
+}
+
+static int _ld9040_gamma_ctl(struct ld9040 *lcd, const unsigned int *gamma)
+{
+        unsigned int i = 0;
+        int ret = 0;
+
+        /* start gamma table updating. */
+        ret = ld9040_panel_send_sequence(lcd, seq_gamma_start);
+        if (ret) {
+                dev_err(lcd->dev, "failed to disable gamma table updating.\n");
+                goto gamma_err;
+        }
+
+        for (i = 0 ; i < GAMMA_TABLE_COUNT; i++) {
+                ret = ld9040_spi_write(lcd, DATA_ONLY, gamma[i]);
+                if (ret) {
+                        dev_err(lcd->dev, "failed to set gamma table.\n");
+                        goto gamma_err;
+                }
+        }
+
+        /* update gamma table. */
+        ret = ld9040_panel_send_sequence(lcd, seq_gamma_ctrl);
+        if (ret)
+                dev_err(lcd->dev, "failed to update gamma table.\n");
+
+gamma_err:
+        return ret;
+}
+
+static int ld9040_gamma_ctl(struct ld9040 *lcd, int gamma)
+{
+        int ret = 0;
+
+        ret = _ld9040_gamma_ctl(lcd, gamma_table.gamma_22_table[gamma]);
+
+        return ret;
+}
+
+
+static int ld9040_ldi_init(struct ld9040 *lcd)
+{
+        int ret, i;
+        static const unsigned short *init_seq[] = {
+                seq_user_setting,
+                seq_panel_condition,
+                seq_display_ctrl,
+                seq_manual_pwr,
+                seq_elvss_on,
+                seq_gtcon,
+                seq_gamma_set1,
+                seq_gamma_ctrl,
+                seq_sleep_out,
+        };
+
+        for (i = 0; i < ARRAY_SIZE(init_seq); i++) {
+                ret = ld9040_panel_send_sequence(lcd, init_seq[i]);
+                /* workaround: minimum delay time for transferring CMD */
+                udelay(300);
+                if (ret)
+                        break;
+        }
+
+        return ret;
+}
+
+static int ld9040_ldi_enable(struct ld9040 *lcd)
+{
+        int ret = 0;
+
+        ret = ld9040_panel_send_sequence(lcd, seq_display_on);
+
+        return ret;
+}
+
+static int ld9040_ldi_disable(struct ld9040 *lcd)
+{
+        int ret;
+
+        ret = ld9040_panel_send_sequence(lcd, seq_display_off);
+        ret = ld9040_panel_send_sequence(lcd, seq_sleep_in);
+
+        return ret;
+}
+
+static int ld9040_power_on(struct ld9040 *lcd)
+{
+        int ret = 0;
+        struct lcd_platform_data *pd = NULL;
+        pd = lcd->lcd_pd;
+        if (!pd) {
+                dev_err(lcd->dev, "platform data is NULL.\n");
+                return -EFAULT;
+        }
+
+        if (!pd->power_on) {
+                dev_err(lcd->dev, "power_on is NULL.\n");
+                return -EFAULT;
+        } else {
+                pd->power_on(lcd->ld, 1);
+                mdelay(pd->power_on_delay);
+        }
+
+        if (!pd->reset) {
+                dev_err(lcd->dev, "reset is NULL.\n");
+                return -EFAULT;
+        } else {
+                pd->reset(lcd->ld);
+                mdelay(pd->reset_delay);
+        }
+
+        ret = ld9040_ldi_init(lcd);
+        if (ret) {
+                dev_err(lcd->dev, "failed to initialize ldi.\n");
+                return ret;
+        }
+
+        ret = ld9040_ldi_enable(lcd);
+        if (ret) {
+                dev_err(lcd->dev, "failed to enable ldi.\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+static int ld9040_power_off(struct ld9040 *lcd)
+{
+        int ret = 0;
+        struct lcd_platform_data *pd = NULL;
+
+        pd = lcd->lcd_pd;
+        if (!pd) {
+                dev_err(lcd->dev, "platform data is NULL.\n");
+                return -EFAULT;
+        }
+
+        ret = ld9040_ldi_disable(lcd);
+        if (ret) {
+                dev_err(lcd->dev, "lcd setting failed.\n");
+                return -EIO;
+        }
+
+        mdelay(pd->power_off_delay);
+
+        if (!pd->power_on) {
+                dev_err(lcd->dev, "power_on is NULL.\n");
+                return -EFAULT;
+        } else
+                pd->power_on(lcd->ld, 0);
+
+        return 0;
+}
+
+static int ld9040_power(struct ld9040 *lcd, int power)
+{
+        int ret = 0;
+
+        if (power_is_on(power) && !power_is_on(lcd->power))
+                ret = ld9040_power_on(lcd);
+        else if (!power_is_on(power) && power_is_on(lcd->power))
+                ret = ld9040_power_off(lcd);
+
+        if (!ret)
+                lcd->power = power;
+
+        return ret;
+}
+
+static int ld9040_set_power(struct lcd_device *ld, int power)
+{
+        struct ld9040 *lcd = lcd_get_data(ld);
+
+        if (power != FB_BLANK_UNBLANK && power != FB_BLANK_POWERDOWN &&
+                power != FB_BLANK_NORMAL) {
+                dev_err(lcd->dev, "power value should be 0, 1 or 4.\n");
+                return -EINVAL;
+        }
+
+        return ld9040_power(lcd, power);
+}
+
+static int ld9040_get_power(struct lcd_device *ld)
+{
+        struct ld9040 *lcd = lcd_get_data(ld);
+
+        return lcd->power;
+}
+
+static int ld9040_get_brightness(struct backlight_device *bd)
+{
+        return bd->props.brightness;
+}
+
+static int ld9040_set_brightness(struct backlight_device *bd)
+{
+        int ret = 0, brightness = bd->props.brightness;
+        struct ld9040 *lcd = bl_get_data(bd);
+
+        if (brightness < MIN_BRIGHTNESS ||
+                brightness > bd->props.max_brightness) {
+                dev_err(&bd->dev, "lcd brightness should be %d to %d.\n",
+                        MIN_BRIGHTNESS, MAX_BRIGHTNESS);
+                return -EINVAL;
+        }
+
+        ret = ld9040_gamma_ctl(lcd, bd->props.brightness);
+        if (ret) {
+                dev_err(&bd->dev, "lcd brightness setting failed.\n");
+                return -EIO;
+        }
+
+        return ret;
+}
+
+static struct lcd_ops ld9040_lcd_ops = {
+        .set_power = ld9040_set_power,
+        .get_power = ld9040_get_power,
+};
+
+static const struct backlight_ops ld9040_backlight_ops  = {
+        .get_brightness = ld9040_get_brightness,
+        .update_status = ld9040_set_brightness,
+};
+
+
+static int ld9040_probe(struct spi_device *spi)
+{
+        int ret = 0;
+        struct ld9040 *lcd = NULL;
+        struct lcd_device *ld = NULL;
+        struct backlight_device *bd = NULL;
+
+        lcd = kzalloc(sizeof(struct ld9040), GFP_KERNEL);
+        if (!lcd)
+                return -ENOMEM;
+
+        /* ld9040 lcd panel uses 3-wire 9bits SPI Mode. */
+        spi->bits_per_word = 9;
+
+        ret = spi_setup(spi);
+        if (ret < 0) {
+                dev_err(&spi->dev, "spi setup failed.\n");
+                goto out_free_lcd;
+        }
+
+        lcd->spi = spi;
+        lcd->dev = &spi->dev;
+
+        lcd->lcd_pd = spi->dev.platform_data;
+        if (!lcd->lcd_pd) {
+                dev_err(&spi->dev, "platform data is NULL.\n");
+                goto out_free_lcd;
+        }
+
+        ld = lcd_device_register("ld9040", &spi->dev, lcd, &ld9040_lcd_ops);
+        if (IS_ERR(ld)) {
+                ret = PTR_ERR(ld);
+                goto out_free_lcd;
+        }
+
+        lcd->ld = ld;
+
+        bd = backlight_device_register("ld9040-bl", &spi->dev,
+                lcd, &ld9040_backlight_ops, NULL);
+        if (IS_ERR(ld)) {
+                ret = PTR_ERR(ld);
+                goto out_free_lcd;
+        }
+
+        bd->props.max_brightness = MAX_BRIGHTNESS;
+        bd->props.brightness = MAX_BRIGHTNESS;
+        lcd->bd = bd;
+
+        /*
+         * if lcd panel was on from bootloader like u-boot then
+         * do not lcd on.
+         */
+        if (!lcd->lcd_pd->lcd_enabled) {
+                /*
+                 * if lcd panel was off from bootloader then
+                 * current lcd status is powerdown and then
+                 * it enables lcd panel.
+                 */
+                lcd->power = FB_BLANK_POWERDOWN;
+
+                ld9040_power(lcd, FB_BLANK_UNBLANK);
+        } else
+                lcd->power = FB_BLANK_UNBLANK;
+
+        dev_set_drvdata(&spi->dev, lcd);
+
+        dev_info(&spi->dev, "ld9040 panel driver has been probed.\n");
+        return 0;
+
+out_free_lcd:
+        kfree(lcd);
+        return ret;
+}
+
+static int __devexit ld9040_remove(struct spi_device *spi)
+{
+        struct ld9040 *lcd = dev_get_drvdata(&spi->dev);
+
+        ld9040_power(lcd, FB_BLANK_POWERDOWN);
+        lcd_device_unregister(lcd->ld);
+        kfree(lcd);
+
+        return 0;
+}
+
+#if defined(CONFIG_PM)
+static int ld9040_suspend(struct spi_device *spi, pm_message_t mesg)
+{
+        int ret = 0;
+        struct ld9040 *lcd = dev_get_drvdata(&spi->dev);
+
+        dev_dbg(&spi->dev, "lcd->power = %d\n", lcd->power);
+
+        /*
+         * when lcd panel is suspend, lcd panel becomes off
+         * regardless of status.
+         */
+        ret = ld9040_power(lcd, FB_BLANK_POWERDOWN);
+
+        return ret;
+}
+
+static int ld9040_resume(struct spi_device *spi)
+{
+        int ret = 0;
+        struct ld9040 *lcd = dev_get_drvdata(&spi->dev);
+
+        lcd->power = FB_BLANK_POWERDOWN;
+
+        ret = ld9040_power(lcd, FB_BLANK_UNBLANK);
+
+        return ret;
+}
+#else
+#define ld9040_suspend          NULL
+#define ld9040_resume           NULL
+#endif
+
+/* Power down all displays on reboot, poweroff or halt. */
+static void ld9040_shutdown(struct spi_device *spi)
+{
+        struct ld9040 *lcd = dev_get_drvdata(&spi->dev);
+
+        ld9040_power(lcd, FB_BLANK_POWERDOWN);
+}
+
+static struct spi_driver ld9040_driver = {
+        .driver = {
+                .name   = "ld9040",
+                .bus    = &spi_bus_type,
+                .owner  = THIS_MODULE,
+        },
+        .probe          = ld9040_probe,
+        .remove         = __devexit_p(ld9040_remove),
+        .shutdown       = ld9040_shutdown,
+        .suspend        = ld9040_suspend,
+        .resume         = ld9040_resume,
+};
+
+static int __init ld9040_init(void)
+{
+        return spi_register_driver(&ld9040_driver);
+}
+
+static void __exit ld9040_exit(void)
+{
+        spi_unregister_driver(&ld9040_driver);
+}
+
+module_init(ld9040_init);
+module_exit(ld9040_exit);
+
+MODULE_AUTHOR("Donghwa Lee <dh09.lee@samsung.com>");
+MODULE_DESCRIPTION("ld9040 LCD Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/backlight/ld9040_gamma.h b/drivers/video/backlight/ld9040_gamma.h
new file mode 100644
index 000000000000..038d9c86ec03
--- /dev/null
+++ b/drivers/video/backlight/ld9040_gamma.h
@@ -0,0 +1,200 @@
+/*
+ * Gamma level definitions.
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ * InKi Dae <inki.dae@samsung.com>
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _LD9040_BRIGHTNESS_H
+#define _LD9040_BRIGHTNESS_H
+
+#define MAX_GAMMA_LEVEL         25
+#define GAMMA_TABLE_COUNT       21
+
+/* gamma value: 2.2 */
+static const unsigned int ld9040_22_300[] = {
+        0x00, 0xa7, 0xb4, 0xae, 0xbf, 0x00, 0x91,
+        0x00, 0xb2, 0xb4, 0xaa, 0xbb, 0x00, 0xac,
+        0x00, 0xb3, 0xb1, 0xaa, 0xbc, 0x00, 0xb3
+};
+
+static const unsigned int ld9040_22_290[] = {
+        0x00, 0xa9, 0xb7, 0xae, 0xbd, 0x00, 0x89,
+        0x00, 0xb7, 0xb6, 0xa8, 0xba, 0x00, 0xa4,
+        0x00, 0xb1, 0xb4, 0xaa, 0xbb, 0x00, 0xaa
+};
+
+static const unsigned int ld9040_22_280[] = {
+        0x00, 0xa9, 0xb6, 0xad, 0xbf, 0x00, 0x86,
+        0x00, 0xb8, 0xb5, 0xa8, 0xbc, 0x00, 0xa0,
+        0x00, 0xb3, 0xb3, 0xa9, 0xbc, 0x00, 0xa7
+};
+
+static const unsigned int ld9040_22_270[] = {
+        0x00, 0xa8, 0xb8, 0xae, 0xbe, 0x00, 0x84,
+        0x00, 0xb9, 0xb7, 0xa8, 0xbc, 0x00, 0x9d,
+        0x00, 0xb2, 0xb5, 0xaa, 0xbc, 0x00, 0xa4
+
+};
+static const unsigned int ld9040_22_260[] = {
+        0x00, 0xa4, 0xb8, 0xb0, 0xbf, 0x00, 0x80,
+        0x00, 0xb8, 0xb6, 0xaa, 0xbc, 0x00, 0x9a,
+        0x00, 0xb0, 0xb5, 0xab, 0xbd, 0x00, 0xa0
+};
+
+static const unsigned int ld9040_22_250[] = {
+        0x00, 0xa4, 0xb9, 0xaf, 0xc1, 0x00, 0x7d,
+        0x00, 0xb9, 0xb6, 0xaa, 0xbb, 0x00, 0x97,
+        0x00, 0xb1, 0xb5, 0xaa, 0xbf, 0x00, 0x9d
+};
+
+static const unsigned int ld9040_22_240[] = {
+        0x00, 0xa2, 0xb9, 0xaf, 0xc2, 0x00, 0x7a,
+        0x00, 0xb9, 0xb7, 0xaa, 0xbd, 0x00, 0x94,
+        0x00, 0xb0, 0xb5, 0xab, 0xbf, 0x00, 0x9a
+};
+
+static const unsigned int ld9040_22_230[] = {
+        0x00, 0xa0, 0xb9, 0xaf, 0xc3, 0x00, 0x77,
+        0x00, 0xb9, 0xb7, 0xab, 0xbe, 0x00, 0x90,
+        0x00, 0xb0, 0xb6, 0xab, 0xbf, 0x00, 0x97
+};
+
+static const unsigned int ld9040_22_220[] = {
+        0x00, 0x9e, 0xba, 0xb0, 0xc2, 0x00, 0x75,
+        0x00, 0xb9, 0xb8, 0xab, 0xbe, 0x00, 0x8e,
+        0x00, 0xb0, 0xb6, 0xac, 0xbf, 0x00, 0x94
+};
+
+static const unsigned int ld9040_22_210[] = {
+        0x00, 0x9c, 0xb9, 0xb0, 0xc4, 0x00, 0x72,
+        0x00, 0xb8, 0xb8, 0xac, 0xbf, 0x00, 0x8a,
+        0x00, 0xb0, 0xb6, 0xac, 0xc0, 0x00, 0x91
+};
+
+static const unsigned int ld9040_22_200[] = {
+        0x00, 0x9a, 0xba, 0xb1, 0xc4, 0x00, 0x6f,
+        0x00, 0xb8, 0xb8, 0xad, 0xc0, 0x00, 0x86,
+        0x00, 0xb0, 0xb7, 0xad, 0xc0, 0x00, 0x8d
+};
+
+static const unsigned int ld9040_22_190[] = {
+        0x00, 0x97, 0xba, 0xb2, 0xc5, 0x00, 0x6c,
+        0x00, 0xb8, 0xb8, 0xae, 0xc1, 0x00, 0x82,
+        0x00, 0xb0, 0xb6, 0xae, 0xc2, 0x00, 0x89
+};
+
+static const unsigned int ld9040_22_180[] = {
+        0x00, 0x93, 0xba, 0xb3, 0xc5, 0x00, 0x69,
+        0x00, 0xb8, 0xb9, 0xae, 0xc1, 0x00, 0x7f,
+        0x00, 0xb0, 0xb6, 0xae, 0xc3, 0x00, 0x85
+};
+
+static const unsigned int ld9040_22_170[] = {
+        0x00, 0x8b, 0xb9, 0xb3, 0xc7, 0x00, 0x65,
+        0x00, 0xb7, 0xb8, 0xaf, 0xc3, 0x00, 0x7a,
+        0x00, 0x80, 0xb6, 0xae, 0xc4, 0x00, 0x81
+};
+
+static const unsigned int ld9040_22_160[] = {
+        0x00, 0x89, 0xba, 0xb3, 0xc8, 0x00, 0x62,
+        0x00, 0xb6, 0xba, 0xaf, 0xc3, 0x00, 0x76,
+        0x00, 0xaf, 0xb7, 0xae, 0xc4, 0x00, 0x7e
+};
+
+static const unsigned int ld9040_22_150[] = {
+        0x00, 0x82, 0xba, 0xb4, 0xc7, 0x00, 0x5f,
+        0x00, 0xb5, 0xba, 0xb0, 0xc3, 0x00, 0x72,
+        0x00, 0xae, 0xb8, 0xb0, 0xc3, 0x00, 0x7a
+};
+
+static const unsigned int ld9040_22_140[] = {
+        0x00, 0x7b, 0xbb, 0xb4, 0xc8, 0x00, 0x5b,
+        0x00, 0xb5, 0xba, 0xb1, 0xc4, 0x00, 0x6e,
+        0x00, 0xae, 0xb9, 0xb0, 0xc5, 0x00, 0x75
+};
+
+static const unsigned int ld9040_22_130[] = {
+        0x00, 0x71, 0xbb, 0xb5, 0xc8, 0x00, 0x57,
+        0x00, 0xb5, 0xbb, 0xb0, 0xc5, 0x00, 0x6a,
+        0x00, 0xae, 0xb9, 0xb1, 0xc6, 0x00, 0x70
+};
+
+static const unsigned int ld9040_22_120[] = {
+        0x00, 0x47, 0xba, 0xb6, 0xca, 0x00, 0x53,
+        0x00, 0xb5, 0xbb, 0xb3, 0xc6, 0x00, 0x65,
+        0x00, 0xae, 0xb8, 0xb3, 0xc7, 0x00, 0x6c
+};
+
+static const unsigned int ld9040_22_110[] = {
+        0x00, 0x13, 0xbb, 0xb7, 0xca, 0x00, 0x4f,
+        0x00, 0xb4, 0xbb, 0xb3, 0xc7, 0x00, 0x60,
+        0x00, 0xad, 0xb8, 0xb4, 0xc7, 0x00, 0x67
+};
+
+static const unsigned int ld9040_22_100[] = {
+        0x00, 0x13, 0xba, 0xb8, 0xcb, 0x00, 0x4b,
+        0x00, 0xb3, 0xbc, 0xb4, 0xc7, 0x00, 0x5c,
+        0x00, 0xac, 0xb8, 0xb4, 0xc8, 0x00, 0x62
+};
+
+static const unsigned int ld9040_22_90[] = {
+        0x00, 0x13, 0xb9, 0xb8, 0xcd, 0x00, 0x46,
+        0x00, 0xb1, 0xbc, 0xb5, 0xc8, 0x00, 0x56,
+        0x00, 0xaa, 0xb8, 0xb4, 0xc9, 0x00, 0x5d
+};
+
+static const unsigned int ld9040_22_80[] = {
+        0x00, 0x13, 0xba, 0xb9, 0xcd, 0x00, 0x41,
+        0x00, 0xb0, 0xbe, 0xb5, 0xc9, 0x00, 0x51,
+        0x00, 0xa9, 0xb9, 0xb5, 0xca, 0x00, 0x57
+};
+
+static const unsigned int ld9040_22_70[] = {
+        0x00, 0x13, 0xb9, 0xb9, 0xd0, 0x00, 0x3c,
+        0x00, 0xaf, 0xbf, 0xb6, 0xcb, 0x00, 0x4b,
+        0x00, 0xa8, 0xb9, 0xb5, 0xcc, 0x00, 0x52
+};
+
+static const unsigned int ld9040_22_50[] = {
+        0x00, 0x13, 0xb2, 0xba, 0xd2, 0x00, 0x30,
+        0x00, 0xaf, 0xc0, 0xb8, 0xcd, 0x00, 0x3d,
+        0x00, 0xa8, 0xb8, 0xb7, 0xcd, 0x00, 0x44
+};
+
+struct ld9040_gamma {
+        unsigned int *gamma_22_table[MAX_GAMMA_LEVEL];
+} gamma_table = {
+        .gamma_22_table[0] = (unsigned int *)&ld9040_22_50,
+        .gamma_22_table[1] = (unsigned int *)&ld9040_22_70,
+        .gamma_22_table[2] = (unsigned int *)&ld9040_22_80,
+        .gamma_22_table[3] = (unsigned int *)&ld9040_22_90,
+        .gamma_22_table[4] = (unsigned int *)&ld9040_22_100,
+        .gamma_22_table[5] = (unsigned int *)&ld9040_22_110,
+        .gamma_22_table[6] = (unsigned int *)&ld9040_22_120,
+        .gamma_22_table[7] = (unsigned int *)&ld9040_22_130,
+        .gamma_22_table[8] = (unsigned int *)&ld9040_22_140,
+        .gamma_22_table[9] = (unsigned int *)&ld9040_22_150,
+        .gamma_22_table[10] = (unsigned int *)&ld9040_22_160,
+        .gamma_22_table[11] = (unsigned int *)&ld9040_22_170,
+        .gamma_22_table[12] = (unsigned int *)&ld9040_22_180,
+        .gamma_22_table[13] = (unsigned int *)&ld9040_22_190,
+        .gamma_22_table[14] = (unsigned int *)&ld9040_22_200,
+        .gamma_22_table[15] = (unsigned int *)&ld9040_22_210,
+        .gamma_22_table[16] = (unsigned int *)&ld9040_22_220,
+        .gamma_22_table[17] = (unsigned int *)&ld9040_22_230,
+        .gamma_22_table[18] = (unsigned int *)&ld9040_22_240,
+        .gamma_22_table[19] = (unsigned int *)&ld9040_22_250,
+        .gamma_22_table[20] = (unsigned int *)&ld9040_22_260,
+        .gamma_22_table[21] = (unsigned int *)&ld9040_22_270,
+        .gamma_22_table[22] = (unsigned int *)&ld9040_22_280,
+        .gamma_22_table[23] = (unsigned int *)&ld9040_22_290,
+        .gamma_22_table[24] = (unsigned int *)&ld9040_22_300,
+};
+
+#endif
diff --git a/drivers/video/backlight/locomolcd.c b/drivers/video/backlight/locomolcd.c
index d2f59015d517..bbca3127071e 100644
--- a/drivers/video/backlight/locomolcd.c
+++ b/drivers/video/backlight/locomolcd.c
@@ -184,6 +184,7 @@ static int locomolcd_probe(struct locomo_dev *ldev)
         local_irq_restore(flags);
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = 4;
         locomolcd_bl_device = backlight_device_register("locomo-bl",
                                                         &ldev->dev, NULL,
diff --git a/drivers/video/backlight/max8925_bl.c b/drivers/video/backlight/max8925_bl.c
index 209acc105cbc..07e8e273ced0 100644
--- a/drivers/video/backlight/max8925_bl.c
+++ b/drivers/video/backlight/max8925_bl.c
@@ -136,6 +136,7 @@ static int __devinit max8925_backlight_probe(struct platform_device *pdev)
         data->current_brightness = 0;
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = MAX_BRIGHTNESS;
         bl = backlight_device_register(name, &pdev->dev, data,
                                         &max8925_backlight_ops, &props);
diff --git a/drivers/video/backlight/mbp_nvidia_bl.c b/drivers/video/backlight/mbp_nvidia_bl.c
deleted file mode 100644
index 1485f7345f49..000000000000
--- a/drivers/video/backlight/mbp_nvidia_bl.c
+++ /dev/null
@@ -1,400 +0,0 @@
-/*
- *  Backlight Driver for Nvidia 8600 in Macbook Pro
- *
- *  Copyright (c) Red Hat <mjg@redhat.com>
- *  Based on code from Pommed:
- *  Copyright (C) 2006 Nicolas Boichat <nicolas @boichat.ch>
- *  Copyright (C) 2006 Felipe Alfaro Solana <felipe_alfaro @linuxmail.org>
- *  Copyright (C) 2007 Julien BLACHE <jb@jblache.org>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- *
- *  This driver triggers SMIs which cause the firmware to change the
- *  backlight brightness. This is icky in many ways, but it's impractical to
- *  get at the firmware code in order to figure out what it's actually doing.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/backlight.h>
-#include <linux/err.h>
-#include <linux/dmi.h>
-#include <linux/io.h>
-
-static struct backlight_device *mbp_backlight_device;
-
-/* Structure to be passed to the DMI_MATCH function. */
-struct dmi_match_data {
-        /* I/O resource to allocate. */
-        unsigned long iostart;
-        unsigned long iolen;
-        /* Backlight operations structure. */
-        const struct backlight_ops backlight_ops;
-};
-
-/* Module parameters. */
-static int debug;
-module_param_named(debug, debug, int, 0644);
-MODULE_PARM_DESC(debug, "Set to one to enable debugging messages.");
-
-/*
- * Implementation for MacBooks with Intel chipset.
- */
-static int intel_chipset_send_intensity(struct backlight_device *bd)
-{
-        int intensity = bd->props.brightness;
-
-        if (debug)
-                printk(KERN_DEBUG "mbp_nvidia_bl: setting brightness to %d\n",
-                       intensity);
-
-        outb(0x04 | (intensity << 4), 0xb3);
-        outb(0xbf, 0xb2);
-        return 0;
-}
-
-static int intel_chipset_get_intensity(struct backlight_device *bd)
-{
-        int intensity;
-
-        outb(0x03, 0xb3);
-        outb(0xbf, 0xb2);
-        intensity = inb(0xb3) >> 4;
-
-        if (debug)
-                printk(KERN_DEBUG "mbp_nvidia_bl: read brightness of %d\n",
-                       intensity);
-
-        return intensity;
-}
-
-static const struct dmi_match_data intel_chipset_data = {
-        .iostart = 0xb2,
-        .iolen = 2,
-        .backlight_ops  = {
-                .options        = BL_CORE_SUSPENDRESUME,
-                .get_brightness = intel_chipset_get_intensity,
-                .update_status  = intel_chipset_send_intensity,
-        }
-};
-
-/*
- * Implementation for MacBooks with Nvidia chipset.
- */
-static int nvidia_chipset_send_intensity(struct backlight_device *bd)
-{
-        int intensity = bd->props.brightness;
-
-        if (debug)
-                printk(KERN_DEBUG "mbp_nvidia_bl: setting brightness to %d\n",
-                       intensity);
-
-        outb(0x04 | (intensity << 4), 0x52f);
-        outb(0xbf, 0x52e);
-        return 0;
-}
-
-static int nvidia_chipset_get_intensity(struct backlight_device *bd)
-{
-        int intensity;
-
-        outb(0x03, 0x52f);
-        outb(0xbf, 0x52e);
-        intensity = inb(0x52f) >> 4;
-
-        if (debug)
-                printk(KERN_DEBUG "mbp_nvidia_bl: read brightness of %d\n",
-                       intensity);
-
-        return intensity;
-}
-
-static const struct dmi_match_data nvidia_chipset_data = {
-        .iostart = 0x52e,
-        .iolen = 2,
-        .backlight_ops          = {
-                .options        = BL_CORE_SUSPENDRESUME,
-                .get_brightness = nvidia_chipset_get_intensity,
-                .update_status  = nvidia_chipset_send_intensity
-        }
-};
-
-/*
- * DMI matching.
- */
-static /* const */ struct dmi_match_data *driver_data;
-
-static int mbp_dmi_match(const struct dmi_system_id *id)
-{
-        driver_data = id->driver_data;
-
-        printk(KERN_INFO "mbp_nvidia_bl: %s detected\n", id->ident);
-        return 1;
-}
-
-static const struct dmi_system_id __initdata mbp_device_table[] = {
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBook 1,1",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Computer, Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBook1,1"),
-                },
-                .driver_data    = (void *)&intel_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBook 2,1",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBook2,1"),
-                },
-                .driver_data    = (void *)&intel_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBook 3,1",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBook3,1"),
-                },
-                .driver_data    = (void *)&intel_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBook 4,1",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBook4,1"),
-                },
-                .driver_data    = (void *)&intel_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBook 4,2",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBook4,2"),
-                },
-                .driver_data    = (void *)&intel_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBookPro 1,1",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro1,1"),
-                },
-                .driver_data    = (void *)&intel_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBookPro 1,2",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro1,2"),
-                },
-                .driver_data    = (void *)&intel_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBookPro 2,1",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro2,1"),
-                },
-                .driver_data    = (void *)&intel_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBookPro 2,2",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro2,2"),
-                },
-                .driver_data    = (void *)&intel_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBookPro 3,1",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro3,1"),
-                },
-                .driver_data    = (void *)&intel_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBookPro 3,2",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro3,2"),
-                },
-                .driver_data    = (void *)&intel_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBookPro 4,1",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro4,1"),
-                },
-                .driver_data    = (void *)&intel_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBookAir 1,1",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookAir1,1"),
-                },
-                .driver_data    = (void *)&intel_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBook 5,1",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBook5,1"),
-                },
-                .driver_data    = (void *)&nvidia_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBook 5,2",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBook5,2"),
-                },
-                .driver_data    = (void *)&nvidia_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBook 6,1",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBook6,1"),
-                },
-                .driver_data    = (void *)&nvidia_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBookAir 2,1",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookAir2,1"),
-                },
-                .driver_data    = (void *)&nvidia_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBookPro 5,1",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro5,1"),
-                },
-                .driver_data    = (void *)&nvidia_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBookPro 5,2",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro5,2"),
-                },
-                .driver_data    = (void *)&nvidia_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBookPro 5,3",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro5,3"),
-                },
-                .driver_data    = (void *)&nvidia_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBookPro 5,4",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro5,4"),
-                },
-                .driver_data    = (void *)&nvidia_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBookPro 5,5",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro5,5"),
-                },
-                .driver_data    = (void *)&nvidia_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBookAir 3,1",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookAir3,1"),
-                },
-                .driver_data    = (void *)&nvidia_chipset_data,
-        },
-        {
-                .callback       = mbp_dmi_match,
-                .ident          = "MacBookAir 3,2",
-                .matches        = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookAir3,2"),
-                },
-                .driver_data    = (void *)&nvidia_chipset_data,
-        },
-        { }
-};
-
-static int __init mbp_init(void)
-{
-        struct backlight_properties props;
-        if (!dmi_check_system(mbp_device_table))
-                return -ENODEV;
-
-        if (!request_region(driver_data->iostart, driver_data->iolen, 
-                                                "Macbook Pro backlight"))
-                return -ENXIO;
-
-        memset(&props, 0, sizeof(struct backlight_properties));
-        props.max_brightness = 15;
-        mbp_backlight_device = backlight_device_register("mbp_backlight", NULL,
-                                                         NULL,
-                                                         &driver_data->backlight_ops,
-                                                         &props);
-        if (IS_ERR(mbp_backlight_device)) {
-                release_region(driver_data->iostart, driver_data->iolen);
-                return PTR_ERR(mbp_backlight_device);
-        }
-
-        mbp_backlight_device->props.brightness =
-                driver_data->backlight_ops.get_brightness(mbp_backlight_device);
-        backlight_update_status(mbp_backlight_device);
-
-        return 0;
-}
-
-static void __exit mbp_exit(void)
-{
-        backlight_device_unregister(mbp_backlight_device);
-
-        release_region(driver_data->iostart, driver_data->iolen);
-}
-
-module_init(mbp_init);
-module_exit(mbp_exit);
-
-MODULE_AUTHOR("Matthew Garrett <mjg@redhat.com>");
-MODULE_DESCRIPTION("Nvidia-based Macbook Pro Backlight Driver");
-MODULE_LICENSE("GPL");
-MODULE_DEVICE_TABLE(dmi, mbp_device_table);
diff --git a/drivers/video/backlight/omap1_bl.c b/drivers/video/backlight/omap1_bl.c
index d3bc56296c8d..08d26a72394c 100644
--- a/drivers/video/backlight/omap1_bl.c
+++ b/drivers/video/backlight/omap1_bl.c
@@ -146,6 +146,7 @@ static int omapbl_probe(struct platform_device *pdev)
                 return -ENOMEM;
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = OMAPBL_MAX_INTENSITY;
         dev = backlight_device_register("omap-bl", &pdev->dev, bl, &omapbl_ops,
                                         &props);
diff --git a/drivers/video/backlight/pcf50633-backlight.c b/drivers/video/backlight/pcf50633-backlight.c
index 3c424f7efdcc..ef5628d60563 100644
--- a/drivers/video/backlight/pcf50633-backlight.c
+++ b/drivers/video/backlight/pcf50633-backlight.c
@@ -112,6 +112,7 @@ static int __devinit pcf50633_bl_probe(struct platform_device *pdev)
         if (!pcf_bl)
                 return -ENOMEM;
 
+        bl_props.type = BACKLIGHT_RAW;
         bl_props.max_brightness = 0x3f;
         bl_props.power = FB_BLANK_UNBLANK;
 
diff --git a/drivers/video/backlight/progear_bl.c b/drivers/video/backlight/progear_bl.c
index 809278c90738..6af183d6465e 100644
--- a/drivers/video/backlight/progear_bl.c
+++ b/drivers/video/backlight/progear_bl.c
@@ -84,6 +84,7 @@ static int progearbl_probe(struct platform_device *pdev)
         pci_write_config_byte(sb_dev, SB_MPS1, temp | 0x20);
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = HW_LEVEL_MAX - HW_LEVEL_MIN;
         progear_backlight_device = backlight_device_register("progear-bl",
                                                              &pdev->dev, NULL,
diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
index 21866ec69656..b8f38ec6eb18 100644
--- a/drivers/video/backlight/pwm_bl.c
+++ b/drivers/video/backlight/pwm_bl.c
@@ -28,6 +28,7 @@ struct pwm_bl_data {
         unsigned int            lth_brightness;
         int                     (*notify)(struct device *,
                                           int brightness);
+        int                     (*check_fb)(struct device *, struct fb_info *);
 };
 
 static int pwm_backlight_update_status(struct backlight_device *bl)
@@ -62,9 +63,18 @@ static int pwm_backlight_get_brightness(struct backlight_device *bl)
         return bl->props.brightness;
 }
 
+static int pwm_backlight_check_fb(struct backlight_device *bl,
+                                  struct fb_info *info)
+{
+        struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
+
+        return !pb->check_fb || pb->check_fb(pb->dev, info);
+}
+
 static const struct backlight_ops pwm_backlight_ops = {
         .update_status  = pwm_backlight_update_status,
         .get_brightness = pwm_backlight_get_brightness,
+        .check_fb       = pwm_backlight_check_fb,
 };
 
 static int pwm_backlight_probe(struct platform_device *pdev)
@@ -95,6 +105,7 @@ static int pwm_backlight_probe(struct platform_device *pdev)
 
         pb->period = data->pwm_period_ns;
         pb->notify = data->notify;
+        pb->check_fb = data->check_fb;
         pb->lth_brightness = data->lth_brightness *
                 (data->pwm_period_ns / data->max_brightness);
         pb->dev = &pdev->dev;
@@ -108,6 +119,7 @@ static int pwm_backlight_probe(struct platform_device *pdev)
                 dev_dbg(&pdev->dev, "got pwm for backlight\n");
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = data->max_brightness;
         bl = backlight_device_register(dev_name(&pdev->dev), &pdev->dev, pb,
                                        &pwm_backlight_ops, &props);
diff --git a/drivers/video/backlight/s6e63m0.c b/drivers/video/backlight/s6e63m0.c
index 5927db0da999..322040f686c2 100644
--- a/drivers/video/backlight/s6e63m0.c
+++ b/drivers/video/backlight/s6e63m0.c
@@ -778,6 +778,7 @@ static int __devinit s6e63m0_probe(struct spi_device *spi)
 
         bd->props.max_brightness = MAX_BRIGHTNESS;
         bd->props.brightness = MAX_BRIGHTNESS;
+        bd->props.type = BACKLIGHT_RAW;
         lcd->bd = bd;
 
         /*
diff --git a/drivers/video/backlight/tosa_bl.c b/drivers/video/backlight/tosa_bl.c
index 2a04b382ec48..425a7365470b 100644
--- a/drivers/video/backlight/tosa_bl.c
+++ b/drivers/video/backlight/tosa_bl.c
@@ -102,6 +102,7 @@ static int __devinit tosa_bl_probe(struct i2c_client *client,
         data->i2c = client;
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = 512 - 1;
         data->bl = backlight_device_register("tosa-bl", &client->dev, data,
                                              &bl_ops, &props);
diff --git a/drivers/video/backlight/wm831x_bl.c b/drivers/video/backlight/wm831x_bl.c
index 08fd87f3aecc..d4c6eb248ff9 100644
--- a/drivers/video/backlight/wm831x_bl.c
+++ b/drivers/video/backlight/wm831x_bl.c
@@ -193,6 +193,7 @@ static int wm831x_backlight_probe(struct platform_device *pdev)
         data->current_brightness = 0;
         data->isink_reg = isink_reg;
 
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = max_isel;
         bl = backlight_device_register("wm831x", &pdev->dev, data,
                                        &wm831x_backlight_ops, &props);
diff --git a/drivers/video/bf54x-lq043fb.c b/drivers/video/bf54x-lq043fb.c
index e7d0f525041e..2464b910b590 100644
--- a/drivers/video/bf54x-lq043fb.c
+++ b/drivers/video/bf54x-lq043fb.c
@@ -649,6 +649,7 @@ static int __devinit bfin_bf54x_probe(struct platform_device *pdev)
         }
 #ifndef NO_BL_SUPPORT
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = 255;
         bl_dev = backlight_device_register("bf54x-bl", NULL, NULL,
                                            &bfin_lq043fb_bl_ops, &props);
diff --git a/drivers/video/bfin-t350mcqb-fb.c b/drivers/video/bfin-t350mcqb-fb.c
index 3cf77676947c..d8de29f0dd8d 100644
--- a/drivers/video/bfin-t350mcqb-fb.c
+++ b/drivers/video/bfin-t350mcqb-fb.c
@@ -545,6 +545,7 @@ static int __devinit bfin_t350mcqb_probe(struct platform_device *pdev)
         }
 #ifndef NO_BL_SUPPORT
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = 255;
         bl_dev = backlight_device_register("bf52x-bl", NULL, NULL,
                                            &bfin_lq043fb_bl_ops, &props);
diff --git a/drivers/video/bw2.c b/drivers/video/bw2.c
index 4dc13467281d..7ba74cd4be61 100644
--- a/drivers/video/bw2.c
+++ b/drivers/video/bw2.c
@@ -273,7 +273,7 @@ static int __devinit bw2_do_default_mode(struct bw2_par *par,
         return 0;
 }
 
-static int __devinit bw2_probe(struct platform_device *op, const struct of_device_id *match)
+static int __devinit bw2_probe(struct platform_device *op)
 {
         struct device_node *dp = op->dev.of_node;
         struct fb_info *info;
@@ -375,7 +375,7 @@ static const struct of_device_id bw2_match[] = {
 };
 MODULE_DEVICE_TABLE(of, bw2_match);
 
-static struct of_platform_driver bw2_driver = {
+static struct platform_driver bw2_driver = {
         .driver = {
                 .name = "bw2",
                 .owner = THIS_MODULE,
@@ -390,12 +390,12 @@ static int __init bw2_init(void)
         if (fb_get_options("bw2fb", NULL))
                 return -ENODEV;
 
-        return of_register_platform_driver(&bw2_driver);
+        return platform_driver_register(&bw2_driver);
 }
 
 static void __exit bw2_exit(void)
 {
-        of_unregister_platform_driver(&bw2_driver);
+        platform_driver_unregister(&bw2_driver);
 }
 
 module_init(bw2_init);
diff --git a/drivers/video/cg14.c b/drivers/video/cg14.c
index 24249535ac86..f18895006627 100644
--- a/drivers/video/cg14.c
+++ b/drivers/video/cg14.c
@@ -463,7 +463,7 @@ static void cg14_unmap_regs(struct platform_device *op, struct fb_info *info,
                            info->screen_base, info->fix.smem_len);
 }
 
-static int __devinit cg14_probe(struct platform_device *op, const struct of_device_id *match)
+static int __devinit cg14_probe(struct platform_device *op)
 {
         struct device_node *dp = op->dev.of_node;
         struct fb_info *info;
@@ -565,6 +565,7 @@ out_dealloc_cmap:
 
 out_unmap_regs:
         cg14_unmap_regs(op, info, par);
+        framebuffer_release(info);
 
 out_err:
         return err;
@@ -595,7 +596,7 @@ static const struct of_device_id cg14_match[] = {
 };
 MODULE_DEVICE_TABLE(of, cg14_match);
 
-static struct of_platform_driver cg14_driver = {
+static struct platform_driver cg14_driver = {
         .driver = {
                 .name = "cg14",
                 .owner = THIS_MODULE,
@@ -610,12 +611,12 @@ static int __init cg14_init(void)
         if (fb_get_options("cg14fb", NULL))
                 return -ENODEV;
 
-        return of_register_platform_driver(&cg14_driver);
+        return platform_driver_register(&cg14_driver);
 }
 
 static void __exit cg14_exit(void)
 {
-        of_unregister_platform_driver(&cg14_driver);
+        platform_driver_unregister(&cg14_driver);
 }
 
 module_init(cg14_init);
diff --git a/drivers/video/cg3.c b/drivers/video/cg3.c
index 09c0c3c42482..f927a7b1a8d4 100644
--- a/drivers/video/cg3.c
+++ b/drivers/video/cg3.c
@@ -346,8 +346,7 @@ static int __devinit cg3_do_default_mode(struct cg3_par *par)
         return 0;
 }
 
-static int __devinit cg3_probe(struct platform_device *op,
-                               const struct of_device_id *match)
+static int __devinit cg3_probe(struct platform_device *op)
 {
         struct device_node *dp = op->dev.of_node;
         struct fb_info *info;
@@ -462,7 +461,7 @@ static const struct of_device_id cg3_match[] = {
 };
 MODULE_DEVICE_TABLE(of, cg3_match);
 
-static struct of_platform_driver cg3_driver = {
+static struct platform_driver cg3_driver = {
         .driver = {
                 .name = "cg3",
                 .owner = THIS_MODULE,
@@ -477,12 +476,12 @@ static int __init cg3_init(void)
         if (fb_get_options("cg3fb", NULL))
                 return -ENODEV;
 
-        return of_register_platform_driver(&cg3_driver);
+        return platform_driver_register(&cg3_driver);
 }
 
 static void __exit cg3_exit(void)
 {
-        of_unregister_platform_driver(&cg3_driver);
+        platform_driver_unregister(&cg3_driver);
 }
 
 module_init(cg3_init);
diff --git a/drivers/video/cg6.c b/drivers/video/cg6.c
index 2b5a97058b08..179e96cdb323 100644
--- a/drivers/video/cg6.c
+++ b/drivers/video/cg6.c
@@ -737,8 +737,7 @@ static void cg6_unmap_regs(struct platform_device *op, struct fb_info *info,
                            info->fix.smem_len);
 }
 
-static int __devinit cg6_probe(struct platform_device *op,
-                                const struct of_device_id *match)
+static int __devinit cg6_probe(struct platform_device *op)
 {
         struct device_node *dp = op->dev.of_node;
         struct fb_info *info;
@@ -822,6 +821,7 @@ out_dealloc_cmap:
 
 out_unmap_regs:
         cg6_unmap_regs(op, info, par);
+        framebuffer_release(info);
 
 out_err:
         return err;
@@ -855,7 +855,7 @@ static const struct of_device_id cg6_match[] = {
 };
 MODULE_DEVICE_TABLE(of, cg6_match);
 
-static struct of_platform_driver cg6_driver = {
+static struct platform_driver cg6_driver = {
         .driver = {
                 .name = "cg6",
                 .owner = THIS_MODULE,
@@ -870,12 +870,12 @@ static int __init cg6_init(void)
         if (fb_get_options("cg6fb", NULL))
                 return -ENODEV;
 
-        return of_register_platform_driver(&cg6_driver);
+        return platform_driver_register(&cg6_driver);
 }
 
 static void __exit cg6_exit(void)
 {
-        of_unregister_platform_driver(&cg6_driver);
+        platform_driver_unregister(&cg6_driver);
 }
 
 module_init(cg6_init);
diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c
index 9c092b8d64e6..c58393402da2 100644
--- a/drivers/video/console/fbcon.c
+++ b/drivers/video/console/fbcon.c
@@ -823,10 +823,10 @@ static int set_con2fb_map(int unit, int newidx, int user)
         if (oldidx == newidx)
                 return 0;
 
-        if (!info || fbcon_has_exited)
+        if (!info)
                 return -EINVAL;
 
-        if (!err && !search_for_mapped_con()) {
+        if (!search_for_mapped_con() || !con_is_bound(&fb_con)) {
                 info_idx = newidx;
                 return fbcon_takeover(0);
         }
diff --git a/drivers/video/console/tileblit.c b/drivers/video/console/tileblit.c
index 0056a41e5c35..15e8e1a89c45 100644
--- a/drivers/video/console/tileblit.c
+++ b/drivers/video/console/tileblit.c
@@ -83,7 +83,7 @@ static void tile_cursor(struct vc_data *vc, struct fb_info *info, int mode,
                         int softback_lines, int fg, int bg)
 {
         struct fb_tilecursor cursor;
-        int use_sw = (vc->vc_cursor_type & 0x01);
+        int use_sw = (vc->vc_cursor_type & 0x10);
 
         cursor.sx = vc->vc_x;
         cursor.sy = vc->vc_y;
diff --git a/drivers/video/cyber2000fb.c b/drivers/video/cyber2000fb.c
index 0c1afd13ddd3..850380795b05 100644
--- a/drivers/video/cyber2000fb.c
+++ b/drivers/video/cyber2000fb.c
@@ -47,6 +47,8 @@
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
 
 #include <asm/pgtable.h>
 #include <asm/system.h>
@@ -61,10 +63,10 @@ struct cfb_info {
         struct fb_info          fb;
         struct display_switch   *dispsw;
         struct display          *display;
-        struct pci_dev          *dev;
         unsigned char           __iomem *region;
         unsigned char           __iomem *regs;
         u_int                   id;
+        u_int                   irq;
         int                     func_use_count;
         u_long                  ref_ps;
 
@@ -88,6 +90,19 @@ struct cfb_info {
         u_char                  ramdac_powerdown;
 
         u32                     pseudo_palette[16];
+
+        spinlock_t              reg_b0_lock;
+
+#ifdef CONFIG_FB_CYBER2000_DDC
+        bool                    ddc_registered;
+        struct i2c_adapter      ddc_adapter;
+        struct i2c_algo_bit_data        ddc_algo;
+#endif
+
+#ifdef CONFIG_FB_CYBER2000_I2C
+        struct i2c_adapter      i2c_adapter;
+        struct i2c_algo_bit_data i2c_algo;
+#endif
 };
 
 static char *default_font = "Acorn8x8";
@@ -494,6 +509,7 @@ static void cyber2000fb_set_timing(struct cfb_info *cfb, struct par_info *hw)
         cyber2000_attrw(0x14, 0x00, cfb);
 
         /* PLL registers */
+        spin_lock(&cfb->reg_b0_lock);
         cyber2000_grphw(EXT_DCLK_MULT, hw->clock_mult, cfb);
         cyber2000_grphw(EXT_DCLK_DIV, hw->clock_div, cfb);
         cyber2000_grphw(EXT_MCLK_MULT, cfb->mclk_mult, cfb);
@@ -501,6 +517,7 @@ static void cyber2000fb_set_timing(struct cfb_info *cfb, struct par_info *hw)
         cyber2000_grphw(0x90, 0x01, cfb);
         cyber2000_grphw(0xb9, 0x80, cfb);
         cyber2000_grphw(0xb9, 0x00, cfb);
+        spin_unlock(&cfb->reg_b0_lock);
 
         cfb->ramdac_ctrl = hw->ramdac;
         cyber2000fb_write_ramdac_ctrl(cfb);
@@ -681,9 +698,9 @@ cyber2000fb_decode_clock(struct par_info *hw, struct cfb_info *cfb,
          *    pll_ps_calc = best_div1 / (ref_ps * best_mult)
          */
         best_diff = 0x7fffffff;
-        best_mult = 32;
-        best_div1 = 255;
-        for (t_div1 = 32; t_div1 > 1; t_div1 -= 1) {
+        best_mult = 2;
+        best_div1 = 32;
+        for (t_div1 = 2; t_div1 < 32; t_div1 += 1) {
                 u_int rr, t_mult, t_pll_ps;
                 int diff;
 
@@ -1105,24 +1122,22 @@ void cyber2000fb_disable_extregs(struct cfb_info *cfb)
 }
 EXPORT_SYMBOL(cyber2000fb_disable_extregs);
 
-void cyber2000fb_get_fb_var(struct cfb_info *cfb, struct fb_var_screeninfo *var)
-{
-        memcpy(var, &cfb->fb.var, sizeof(struct fb_var_screeninfo));
-}
-EXPORT_SYMBOL(cyber2000fb_get_fb_var);
-
 /*
  * Attach a capture/tv driver to the core CyberX0X0 driver.
  */
 int cyber2000fb_attach(struct cyberpro_info *info, int idx)
 {
         if (int_cfb_info != NULL) {
-                info->dev             = int_cfb_info->dev;
+                info->dev             = int_cfb_info->fb.device;
+#ifdef CONFIG_FB_CYBER2000_I2C
+                info->i2c             = &int_cfb_info->i2c_adapter;
+#else
+                info->i2c             = NULL;
+#endif
                 info->regs            = int_cfb_info->regs;
+                info->irq             = int_cfb_info->irq;
                 info->fb              = int_cfb_info->fb.screen_base;
                 info->fb_size         = int_cfb_info->fb.fix.smem_len;
-                info->enable_extregs  = cyber2000fb_enable_extregs;
-                info->disable_extregs = cyber2000fb_disable_extregs;
                 info->info            = int_cfb_info;
 
                 strlcpy(info->dev_name, int_cfb_info->fb.fix.id,
@@ -1141,6 +1156,183 @@ void cyber2000fb_detach(int idx)
 }
 EXPORT_SYMBOL(cyber2000fb_detach);
 
+#ifdef CONFIG_FB_CYBER2000_DDC
+
+#define DDC_REG         0xb0
+#define DDC_SCL_OUT     (1 << 0)
+#define DDC_SDA_OUT     (1 << 4)
+#define DDC_SCL_IN      (1 << 2)
+#define DDC_SDA_IN      (1 << 6)
+
+static void cyber2000fb_enable_ddc(struct cfb_info *cfb)
+{
+        spin_lock(&cfb->reg_b0_lock);
+        cyber2000fb_writew(0x1bf, 0x3ce, cfb);
+}
+
+static void cyber2000fb_disable_ddc(struct cfb_info *cfb)
+{
+        cyber2000fb_writew(0x0bf, 0x3ce, cfb);
+        spin_unlock(&cfb->reg_b0_lock);
+}
+
+
+static void cyber2000fb_ddc_setscl(void *data, int val)
+{
+        struct cfb_info *cfb = data;
+        unsigned char reg;
+
+        cyber2000fb_enable_ddc(cfb);
+        reg = cyber2000_grphr(DDC_REG, cfb);
+        if (!val)       /* bit is inverted */
+                reg |= DDC_SCL_OUT;
+        else
+                reg &= ~DDC_SCL_OUT;
+        cyber2000_grphw(DDC_REG, reg, cfb);
+        cyber2000fb_disable_ddc(cfb);
+}
+
+static void cyber2000fb_ddc_setsda(void *data, int val)
+{
+        struct cfb_info *cfb = data;
+        unsigned char reg;
+
+        cyber2000fb_enable_ddc(cfb);
+        reg = cyber2000_grphr(DDC_REG, cfb);
+        if (!val)       /* bit is inverted */
+                reg |= DDC_SDA_OUT;
+        else
+                reg &= ~DDC_SDA_OUT;
+        cyber2000_grphw(DDC_REG, reg, cfb);
+        cyber2000fb_disable_ddc(cfb);
+}
+
+static int cyber2000fb_ddc_getscl(void *data)
+{
+        struct cfb_info *cfb = data;
+        int retval;
+
+        cyber2000fb_enable_ddc(cfb);
+        retval = !!(cyber2000_grphr(DDC_REG, cfb) & DDC_SCL_IN);
+        cyber2000fb_disable_ddc(cfb);
+
+        return retval;
+}
+
+static int cyber2000fb_ddc_getsda(void *data)
+{
+        struct cfb_info *cfb = data;
+        int retval;
+
+        cyber2000fb_enable_ddc(cfb);
+        retval = !!(cyber2000_grphr(DDC_REG, cfb) & DDC_SDA_IN);
+        cyber2000fb_disable_ddc(cfb);
+
+        return retval;
+}
+
+static int __devinit cyber2000fb_setup_ddc_bus(struct cfb_info *cfb)
+{
+        strlcpy(cfb->ddc_adapter.name, cfb->fb.fix.id,
+                sizeof(cfb->ddc_adapter.name));
+        cfb->ddc_adapter.owner          = THIS_MODULE;
+        cfb->ddc_adapter.class          = I2C_CLASS_DDC;
+        cfb->ddc_adapter.algo_data      = &cfb->ddc_algo;
+        cfb->ddc_adapter.dev.parent     = cfb->fb.device;
+        cfb->ddc_algo.setsda            = cyber2000fb_ddc_setsda;
+        cfb->ddc_algo.setscl            = cyber2000fb_ddc_setscl;
+        cfb->ddc_algo.getsda            = cyber2000fb_ddc_getsda;
+        cfb->ddc_algo.getscl            = cyber2000fb_ddc_getscl;
+        cfb->ddc_algo.udelay            = 10;
+        cfb->ddc_algo.timeout           = 20;
+        cfb->ddc_algo.data              = cfb;
+
+        i2c_set_adapdata(&cfb->ddc_adapter, cfb);
+
+        return i2c_bit_add_bus(&cfb->ddc_adapter);
+}
+#endif /* CONFIG_FB_CYBER2000_DDC */
+
+#ifdef CONFIG_FB_CYBER2000_I2C
+static void cyber2000fb_i2c_setsda(void *data, int state)
+{
+        struct cfb_info *cfb = data;
+        unsigned int latch2;
+
+        spin_lock(&cfb->reg_b0_lock);
+        latch2 = cyber2000_grphr(EXT_LATCH2, cfb);
+        latch2 &= EXT_LATCH2_I2C_CLKEN;
+        if (state)
+                latch2 |= EXT_LATCH2_I2C_DATEN;
+        cyber2000_grphw(EXT_LATCH2, latch2, cfb);
+        spin_unlock(&cfb->reg_b0_lock);
+}
+
+static void cyber2000fb_i2c_setscl(void *data, int state)
+{
+        struct cfb_info *cfb = data;
+        unsigned int latch2;
+
+        spin_lock(&cfb->reg_b0_lock);
+        latch2 = cyber2000_grphr(EXT_LATCH2, cfb);
+        latch2 &= EXT_LATCH2_I2C_DATEN;
+        if (state)
+                latch2 |= EXT_LATCH2_I2C_CLKEN;
+        cyber2000_grphw(EXT_LATCH2, latch2, cfb);
+        spin_unlock(&cfb->reg_b0_lock);
+}
+
+static int cyber2000fb_i2c_getsda(void *data)
+{
+        struct cfb_info *cfb = data;
+        int ret;
+
+        spin_lock(&cfb->reg_b0_lock);
+        ret = !!(cyber2000_grphr(EXT_LATCH2, cfb) & EXT_LATCH2_I2C_DAT);
+        spin_unlock(&cfb->reg_b0_lock);
+
+        return ret;
+}
+
+static int cyber2000fb_i2c_getscl(void *data)
+{
+        struct cfb_info *cfb = data;
+        int ret;
+
+        spin_lock(&cfb->reg_b0_lock);
+        ret = !!(cyber2000_grphr(EXT_LATCH2, cfb) & EXT_LATCH2_I2C_CLK);
+        spin_unlock(&cfb->reg_b0_lock);
+
+        return ret;
+}
+
+static int __devinit cyber2000fb_i2c_register(struct cfb_info *cfb)
+{
+        strlcpy(cfb->i2c_adapter.name, cfb->fb.fix.id,
+                sizeof(cfb->i2c_adapter.name));
+        cfb->i2c_adapter.owner = THIS_MODULE;
+        cfb->i2c_adapter.algo_data = &cfb->i2c_algo;
+        cfb->i2c_adapter.dev.parent = cfb->fb.device;
+        cfb->i2c_algo.setsda = cyber2000fb_i2c_setsda;
+        cfb->i2c_algo.setscl = cyber2000fb_i2c_setscl;
+        cfb->i2c_algo.getsda = cyber2000fb_i2c_getsda;
+        cfb->i2c_algo.getscl = cyber2000fb_i2c_getscl;
+        cfb->i2c_algo.udelay = 5;
+        cfb->i2c_algo.timeout = msecs_to_jiffies(100);
+        cfb->i2c_algo.data = cfb;
+
+        return i2c_bit_add_bus(&cfb->i2c_adapter);
+}
+
+static void cyber2000fb_i2c_unregister(struct cfb_info *cfb)
+{
+        i2c_del_adapter(&cfb->i2c_adapter);
+}
+#else
+#define cyber2000fb_i2c_register(cfb)   (0)
+#define cyber2000fb_i2c_unregister(cfb) do { } while (0)
+#endif
+
 /*
  * These parameters give
  * 640x480, hsync 31.5kHz, vsync 60Hz
@@ -1275,6 +1467,8 @@ static struct cfb_info __devinit *cyberpro_alloc_fb_info(unsigned int id,
         cfb->fb.flags           = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
         cfb->fb.pseudo_palette  = cfb->pseudo_palette;
 
+        spin_lock_init(&cfb->reg_b0_lock);
+
         fb_alloc_cmap(&cfb->fb.cmap, NR_PALETTE, 0);
 
         return cfb;
@@ -1369,6 +1563,11 @@ static int __devinit cyberpro_common_probe(struct cfb_info *cfb)
         cfb->fb.fix.mmio_len   = MMIO_SIZE;
         cfb->fb.screen_base    = cfb->region;
 
+#ifdef CONFIG_FB_CYBER2000_DDC
+        if (cyber2000fb_setup_ddc_bus(cfb) == 0)
+                cfb->ddc_registered = true;
+#endif
+
         err = -EINVAL;
         if (!fb_find_mode(&cfb->fb.var, &cfb->fb, NULL, NULL, 0,
                           &cyber2000fb_default_mode, 8)) {
@@ -1401,14 +1600,32 @@ static int __devinit cyberpro_common_probe(struct cfb_info *cfb)
                 cfb->fb.var.xres, cfb->fb.var.yres,
                 h_sync / 1000, h_sync % 1000, v_sync);
 
-        if (cfb->dev)
-                cfb->fb.device = &cfb->dev->dev;
+        err = cyber2000fb_i2c_register(cfb);
+        if (err)
+                goto failed;
+
         err = register_framebuffer(&cfb->fb);
+        if (err)
+                cyber2000fb_i2c_unregister(cfb);
 
 failed:
+#ifdef CONFIG_FB_CYBER2000_DDC
+        if (err && cfb->ddc_registered)
+                i2c_del_adapter(&cfb->ddc_adapter);
+#endif
         return err;
 }
 
+static void __devexit cyberpro_common_remove(struct cfb_info *cfb)
+{
+        unregister_framebuffer(&cfb->fb);
+#ifdef CONFIG_FB_CYBER2000_DDC
+        if (cfb->ddc_registered)
+                i2c_del_adapter(&cfb->ddc_adapter);
+#endif
+        cyber2000fb_i2c_unregister(cfb);
+}
+
 static void cyberpro_common_resume(struct cfb_info *cfb)
 {
         cyberpro_init_hw(cfb);
@@ -1442,12 +1659,13 @@ static int __devinit cyberpro_vl_probe(void)
         if (!cfb)
                 goto failed_release;
 
-        cfb->dev = NULL;
+        cfb->irq = -1;
         cfb->region = ioremap(FB_START, FB_SIZE);
         if (!cfb->region)
                 goto failed_ioremap;
 
         cfb->regs = cfb->region + MMIO_OFFSET;
+        cfb->fb.device = NULL;
         cfb->fb.fix.mmio_start = FB_START + MMIO_OFFSET;
         cfb->fb.fix.smem_start = FB_START;
 
@@ -1585,12 +1803,13 @@ cyberpro_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
         if (err)
                 goto failed_regions;
 
-        cfb->dev = dev;
+        cfb->irq = dev->irq;
         cfb->region = pci_ioremap_bar(dev, 0);
         if (!cfb->region)
                 goto failed_ioremap;
 
         cfb->regs = cfb->region + MMIO_OFFSET;
+        cfb->fb.device = &dev->dev;
         cfb->fb.fix.mmio_start = pci_resource_start(dev, 0) + MMIO_OFFSET;
         cfb->fb.fix.smem_start = pci_resource_start(dev, 0);
 
@@ -1648,15 +1867,7 @@ static void __devexit cyberpro_pci_remove(struct pci_dev *dev)
         struct cfb_info *cfb = pci_get_drvdata(dev);
 
         if (cfb) {
-                /*
-                 * If unregister_framebuffer fails, then
-                 * we will be leaving hooks that could cause
-                 * oopsen laying around.
-                 */
-                if (unregister_framebuffer(&cfb->fb))
-                        printk(KERN_WARNING "%s: danger Will Robinson, "
-                                "danger danger!  Oopsen imminent!\n",
-                                cfb->fb.fix.id);
+                cyberpro_common_remove(cfb);
                 iounmap(cfb->region);
                 cyberpro_free_fb_info(cfb);
 
diff --git a/drivers/video/cyber2000fb.h b/drivers/video/cyber2000fb.h
index de4fc43e51c1..bad69102e774 100644
--- a/drivers/video/cyber2000fb.h
+++ b/drivers/video/cyber2000fb.h
@@ -464,12 +464,14 @@ static void debug_printf(char *fmt, ...)
 struct cfb_info;
 
 struct cyberpro_info {
-        struct pci_dev  *dev;
+        struct device   *dev;
+        struct i2c_adapter *i2c;
         unsigned char   __iomem *regs;
         char            __iomem *fb;
         char            dev_name[32];
         unsigned int    fb_size;
         unsigned int    chip_id;
+        unsigned int    irq;
 
         /*
          * The following is a pointer to be passed into the
@@ -478,15 +480,6 @@ struct cyberpro_info {
          * is within this structure.
          */
         struct cfb_info *info;
-
-        /*
-         * Use these to enable the BM or TV registers.  In an SMP
-         * environment, these two function pointers should only be
-         * called from the module_init() or module_exit()
-         * functions.
-         */
-        void (*enable_extregs)(struct cfb_info *);
-        void (*disable_extregs)(struct cfb_info *);
 };
 
 #define ID_IGA_1682             0
@@ -494,8 +487,6 @@ struct cyberpro_info {
 #define ID_CYBERPRO_2010        2
 #define ID_CYBERPRO_5000        3
 
-struct fb_var_screeninfo;
-
 /*
  * Note! Writing to the Cyber20x0 registers from an interrupt
  * routine is definitely a bad idea atm.
@@ -504,4 +495,3 @@ int cyber2000fb_attach(struct cyberpro_info *info, int idx);
 void cyber2000fb_detach(int idx);
 void cyber2000fb_enable_extregs(struct cfb_info *cfb);
 void cyber2000fb_disable_extregs(struct cfb_info *cfb);
-void cyber2000fb_get_fb_var(struct cfb_info *cfb, struct fb_var_screeninfo *var);
diff --git a/drivers/video/edid.h b/drivers/video/edid.h
index bd89fb3be8c2..d03a232d90b2 100644
--- a/drivers/video/edid.h
+++ b/drivers/video/edid.h
@@ -101,8 +101,8 @@
 #define V_SYNC_WIDTH       COMBINE_HI_4LO( V_SYNC_WIDTH_HI, V_SYNC_WIDTH_LO )
 #define V_SYNC_OFFSET      COMBINE_HI_4LO( V_SYNC_OFFSET_HI, V_SYNC_OFFSET_LO )
 
-#define H_SYNC_WIDTH       COMBINE_HI_4LO( H_SYNC_WIDTH_HI, H_SYNC_WIDTH_LO )
-#define H_SYNC_OFFSET      COMBINE_HI_4LO( H_SYNC_OFFSET_HI, H_SYNC_OFFSET_LO )
+#define H_SYNC_WIDTH       COMBINE_HI_8LO( H_SYNC_WIDTH_HI, H_SYNC_WIDTH_LO )
+#define H_SYNC_OFFSET      COMBINE_HI_8LO( H_SYNC_OFFSET_HI, H_SYNC_OFFSET_LO )
 
 #define H_SIZE_LO          (unsigned)block[ 12 ]
 #define V_SIZE_LO          (unsigned)block[ 13 ]
diff --git a/drivers/video/fb-puv3.c b/drivers/video/fb-puv3.c
new file mode 100644
index 000000000000..dbd2dc4745d1
--- /dev/null
+++ b/drivers/video/fb-puv3.c
@@ -0,0 +1,846 @@
+/*
+ * Frame Buffer Driver for PKUnity-v3 Unigfx
+ * Code specific to PKUnity SoC and UniCore ISA
+ *
+ *      Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn>
+ *      Copyright (C) 2001-2010 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/console.h>
+
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+
+/* Platform_data reserved for unifb registers. */
+#define UNIFB_REGS_NUM          10
+/* RAM reserved for the frame buffer. */
+#define UNIFB_MEMSIZE           (SZ_4M)         /* 4 MB for 1024*768*32b */
+
+/*
+ * cause UNIGFX don not have EDID
+ * all the modes are organized as follow
+ */
+static const struct fb_videomode unifb_modes[] = {
+        /* 0 640x480-60 VESA */
+        { "640x480@60",  60,  640, 480,  25175000,  48, 16, 34, 10,  96, 1,
+          0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+        /* 1 640x480-75 VESA */
+        { "640x480@75",  75,  640, 480,  31500000, 120, 16, 18,  1,  64, 1,
+          0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+        /* 2 800x600-60 VESA */
+        { "800x600@60",  60,  800, 600,  40000000,  88, 40, 26,  1, 128, 1,
+          0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+        /* 3 800x600-75 VESA */
+        { "800x600@75",  75,  800, 600,  49500000, 160, 16, 23,  1,  80, 1,
+          0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+        /* 4 1024x768-60 VESA */
+        { "1024x768@60", 60, 1024, 768,  65000000, 160, 24, 34,  3, 136, 1,
+          0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+        /* 5 1024x768-75 VESA */
+        { "1024x768@75", 75, 1024, 768,  78750000, 176, 16, 30,  1,  96, 1,
+          0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+        /* 6 1280x960-60 VESA */
+        { "1280x960@60", 60, 1280, 960, 108000000, 312, 96, 38,  1, 112, 1,
+          0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+        /* 7 1440x900-60 VESA */
+        { "1440x900@60", 60, 1440, 900, 106500000, 232, 80, 30,  3, 152, 1,
+          0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+        /* 8 FIXME 9 1024x600-60 VESA UNTESTED */
+        { "1024x600@60", 60, 1024, 600,  50650000, 160, 24, 26,  1, 136, 1,
+          0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+        /* 9 FIXME 10 1024x600-75 VESA UNTESTED */
+        { "1024x600@75", 75, 1024, 600,  61500000, 176, 16, 23,  1,  96, 1,
+          0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+        /* 10 FIXME 11 1366x768-60 VESA UNTESTED */
+        { "1366x768@60", 60, 1366, 768,  85500000, 256, 58, 18,  1,  112, 3,
+          0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+};
+
+static struct fb_var_screeninfo unifb_default = {
+        .xres =         640,
+        .yres =         480,
+        .xres_virtual = 640,
+        .yres_virtual = 480,
+        .bits_per_pixel = 16,
+        .red =          { 11, 5, 0 },
+        .green =        { 5,  6, 0 },
+        .blue =         { 0,  5, 0 },
+        .activate =     FB_ACTIVATE_NOW,
+        .height =       -1,
+        .width =        -1,
+        .pixclock =     25175000,
+        .left_margin =  48,
+        .right_margin = 16,
+        .upper_margin = 33,
+        .lower_margin = 10,
+        .hsync_len =    96,
+        .vsync_len =    2,
+        .vmode =        FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_fix_screeninfo unifb_fix = {
+        .id =           "UNIGFX FB",
+        .type =         FB_TYPE_PACKED_PIXELS,
+        .visual =       FB_VISUAL_TRUECOLOR,
+        .xpanstep =     1,
+        .ypanstep =     1,
+        .ywrapstep =    1,
+        .accel =        FB_ACCEL_NONE,
+};
+
+static void unifb_sync(struct fb_info *info)
+{
+        /* TODO: may, this can be replaced by interrupt */
+        int cnt;
+
+        for (cnt = 0; cnt < 0x10000000; cnt++) {
+                if (readl(UGE_COMMAND) & 0x1000000)
+                        return;
+        }
+
+        if (cnt > 0x8000000)
+                dev_warn(info->device, "Warning: UniGFX GE time out ...\n");
+}
+
+static void unifb_prim_fillrect(struct fb_info *info,
+                                const struct fb_fillrect *region)
+{
+        int awidth = region->width;
+        int aheight = region->height;
+        int m_iBpp = info->var.bits_per_pixel;
+        int screen_width = info->var.xres;
+        int src_sel = 1;        /* from fg_color */
+        int pat_sel = 1;
+        int src_x0 = 0;
+        int dst_x0 = region->dx;
+        int src_y0 = 0;
+        int dst_y0 = region->dy;
+        int rop_alpha_sel = 0;
+        int rop_alpha_code = 0xCC;
+        int x_dir = 1;
+        int y_dir = 1;
+        int alpha_r = 0;
+        int alpha_sel = 0;
+        int dst_pitch = screen_width * (m_iBpp / 8);
+        int dst_offset = dst_y0 * dst_pitch + dst_x0 * (m_iBpp / 8);
+        int src_pitch = screen_width * (m_iBpp / 8);
+        int src_offset = src_y0 * src_pitch + src_x0 * (m_iBpp / 8);
+        unsigned int command = 0;
+        int clip_region = 0;
+        int clip_en = 0;
+        int tp_en = 0;
+        int fg_color = 0;
+        int bottom = info->var.yres - 1;
+        int right = info->var.xres - 1;
+        int top = 0;
+
+        bottom = (bottom << 16) | right;
+        command = (rop_alpha_sel << 26) | (pat_sel << 18) | (src_sel << 16)
+                | (x_dir << 20) | (y_dir << 21) | (command << 24)
+                | (clip_region << 23) | (clip_en << 22) | (tp_en << 27);
+        src_pitch = (dst_pitch << 16) | src_pitch;
+        awidth = awidth | (aheight << 16);
+        alpha_r = ((rop_alpha_code & 0xff) << 8) | (alpha_r & 0xff)
+                | (alpha_sel << 16);
+        src_x0 = (src_x0 & 0x1fff) | ((src_y0 & 0x1fff) << 16);
+        dst_x0 = (dst_x0 & 0x1fff) | ((dst_y0 & 0x1fff) << 16);
+        fg_color = region->color;
+
+        unifb_sync(info);
+
+        writel(((u32 *)(info->pseudo_palette))[fg_color], UGE_FCOLOR);
+        writel(0, UGE_BCOLOR);
+        writel(src_pitch, UGE_PITCH);
+        writel(src_offset, UGE_SRCSTART);
+        writel(dst_offset, UGE_DSTSTART);
+        writel(awidth, UGE_WIDHEIGHT);
+        writel(top, UGE_CLIP0);
+        writel(bottom, UGE_CLIP1);
+        writel(alpha_r, UGE_ROPALPHA);
+        writel(src_x0, UGE_SRCXY);
+        writel(dst_x0, UGE_DSTXY);
+        writel(command, UGE_COMMAND);
+}
+
+static void unifb_fillrect(struct fb_info *info,
+                const struct fb_fillrect *region)
+{
+        struct fb_fillrect modded;
+        int vxres, vyres;
+
+        if (info->flags & FBINFO_HWACCEL_DISABLED) {
+                sys_fillrect(info, region);
+                return;
+        }
+
+        vxres = info->var.xres_virtual;
+        vyres = info->var.yres_virtual;
+
+        memcpy(&modded, region, sizeof(struct fb_fillrect));
+
+        if (!modded.width || !modded.height ||
+            modded.dx >= vxres || modded.dy >= vyres)
+                return;
+
+        if (modded.dx + modded.width > vxres)
+                modded.width = vxres - modded.dx;
+        if (modded.dy + modded.height > vyres)
+                modded.height = vyres - modded.dy;
+
+        unifb_prim_fillrect(info, &modded);
+}
+
+static void unifb_prim_copyarea(struct fb_info *info,
+                                const struct fb_copyarea *area)
+{
+        int awidth = area->width;
+        int aheight = area->height;
+        int m_iBpp = info->var.bits_per_pixel;
+        int screen_width = info->var.xres;
+        int src_sel = 2;        /* from mem */
+        int pat_sel = 0;
+        int src_x0 = area->sx;
+        int dst_x0 = area->dx;
+        int src_y0 = area->sy;
+        int dst_y0 = area->dy;
+
+        int rop_alpha_sel = 0;
+        int rop_alpha_code = 0xCC;
+        int x_dir = 1;
+        int y_dir = 1;
+
+        int alpha_r = 0;
+        int alpha_sel = 0;
+        int dst_pitch = screen_width * (m_iBpp / 8);
+        int dst_offset = dst_y0 * dst_pitch + dst_x0 * (m_iBpp / 8);
+        int src_pitch = screen_width * (m_iBpp / 8);
+        int src_offset = src_y0 * src_pitch + src_x0 * (m_iBpp / 8);
+        unsigned int command = 0;
+        int clip_region = 0;
+        int clip_en = 1;
+        int tp_en = 0;
+        int top = 0;
+        int bottom = info->var.yres;
+        int right = info->var.xres;
+        int fg_color = 0;
+        int bg_color = 0;
+
+        if (src_x0 < 0)
+                src_x0 = 0;
+        if (src_y0 < 0)
+                src_y0 = 0;
+
+        if (src_y0 - dst_y0 > 0) {
+                y_dir = 1;
+        } else {
+                y_dir = 0;
+                src_offset = (src_y0 + aheight) * src_pitch +
+                                src_x0 * (m_iBpp / 8);
+                dst_offset = (dst_y0 + aheight) * dst_pitch +
+                                dst_x0 * (m_iBpp / 8);
+                src_y0 += aheight;
+                dst_y0 += aheight;
+        }
+
+        command = (rop_alpha_sel << 26) | (pat_sel << 18) | (src_sel << 16) |
+                (x_dir << 20) | (y_dir << 21) | (command << 24) |
+                (clip_region << 23) | (clip_en << 22) | (tp_en << 27);
+        src_pitch = (dst_pitch << 16) | src_pitch;
+        awidth = awidth | (aheight << 16);
+        alpha_r = ((rop_alpha_code & 0xff) << 8) | (alpha_r & 0xff) |
+                (alpha_sel << 16);
+        src_x0 = (src_x0 & 0x1fff) | ((src_y0 & 0x1fff) << 16);
+        dst_x0 = (dst_x0 & 0x1fff) | ((dst_y0 & 0x1fff) << 16);
+        bottom = (bottom << 16) | right;
+
+        unifb_sync(info);
+
+        writel(src_pitch, UGE_PITCH);
+        writel(src_offset, UGE_SRCSTART);
+        writel(dst_offset, UGE_DSTSTART);
+        writel(awidth, UGE_WIDHEIGHT);
+        writel(top, UGE_CLIP0);
+        writel(bottom, UGE_CLIP1);
+        writel(bg_color, UGE_BCOLOR);
+        writel(fg_color, UGE_FCOLOR);
+        writel(alpha_r, UGE_ROPALPHA);
+        writel(src_x0, UGE_SRCXY);
+        writel(dst_x0, UGE_DSTXY);
+        writel(command, UGE_COMMAND);
+}
+
+static void unifb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
+{
+        struct fb_copyarea modded;
+        u32 vxres, vyres;
+        modded.sx = area->sx;
+        modded.sy = area->sy;
+        modded.dx = area->dx;
+        modded.dy = area->dy;
+        modded.width = area->width;
+        modded.height = area->height;
+
+        if (info->flags & FBINFO_HWACCEL_DISABLED) {
+                sys_copyarea(info, area);
+                return;
+        }
+
+        vxres = info->var.xres_virtual;
+        vyres = info->var.yres_virtual;
+
+        if (!modded.width || !modded.height ||
+            modded.sx >= vxres || modded.sy >= vyres ||
+            modded.dx >= vxres || modded.dy >= vyres)
+                return;
+
+        if (modded.sx + modded.width > vxres)
+                modded.width = vxres - modded.sx;
+        if (modded.dx + modded.width > vxres)
+                modded.width = vxres - modded.dx;
+        if (modded.sy + modded.height > vyres)
+                modded.height = vyres - modded.sy;
+        if (modded.dy + modded.height > vyres)
+                modded.height = vyres - modded.dy;
+
+        unifb_prim_copyarea(info, &modded);
+}
+
+static void unifb_imageblit(struct fb_info *info, const struct fb_image *image)
+{
+        sys_imageblit(info, image);
+}
+
+static u_long get_line_length(int xres_virtual, int bpp)
+{
+        u_long length;
+
+        length = xres_virtual * bpp;
+        length = (length + 31) & ~31;
+        length >>= 3;
+        return length;
+}
+
+/*
+ *  Setting the video mode has been split into two parts.
+ *  First part, xxxfb_check_var, must not write anything
+ *  to hardware, it should only verify and adjust var.
+ *  This means it doesn't alter par but it does use hardware
+ *  data from it to check this var.
+ */
+static int unifb_check_var(struct fb_var_screeninfo *var,
+                         struct fb_info *info)
+{
+        u_long line_length;
+
+        /*
+         *  FB_VMODE_CONUPDATE and FB_VMODE_SMOOTH_XPAN are equal!
+         *  as FB_VMODE_SMOOTH_XPAN is only used internally
+         */
+
+        if (var->vmode & FB_VMODE_CONUPDATE) {
+                var->vmode |= FB_VMODE_YWRAP;
+                var->xoffset = info->var.xoffset;
+                var->yoffset = info->var.yoffset;
+        }
+
+        /*
+         *  Some very basic checks
+         */
+        if (!var->xres)
+                var->xres = 1;
+        if (!var->yres)
+                var->yres = 1;
+        if (var->xres > var->xres_virtual)
+                var->xres_virtual = var->xres;
+        if (var->yres > var->yres_virtual)
+                var->yres_virtual = var->yres;
+        if (var->bits_per_pixel <= 1)
+                var->bits_per_pixel = 1;
+        else if (var->bits_per_pixel <= 8)
+                var->bits_per_pixel = 8;
+        else if (var->bits_per_pixel <= 16)
+                var->bits_per_pixel = 16;
+        else if (var->bits_per_pixel <= 24)
+                var->bits_per_pixel = 24;
+        else if (var->bits_per_pixel <= 32)
+                var->bits_per_pixel = 32;
+        else
+                return -EINVAL;
+
+        if (var->xres_virtual < var->xoffset + var->xres)
+                var->xres_virtual = var->xoffset + var->xres;
+        if (var->yres_virtual < var->yoffset + var->yres)
+                var->yres_virtual = var->yoffset + var->yres;
+
+        /*
+         *  Memory limit
+         */
+        line_length =
+            get_line_length(var->xres_virtual, var->bits_per_pixel);
+        if (line_length * var->yres_virtual > UNIFB_MEMSIZE)
+                return -ENOMEM;
+
+        /*
+         * Now that we checked it we alter var. The reason being is that the
+         * video mode passed in might not work but slight changes to it might
+         * make it work. This way we let the user know what is acceptable.
+         */
+        switch (var->bits_per_pixel) {
+        case 1:
+        case 8:
+                var->red.offset = 0;
+                var->red.length = 8;
+                var->green.offset = 0;
+                var->green.length = 8;
+                var->blue.offset = 0;
+                var->blue.length = 8;
+                var->transp.offset = 0;
+                var->transp.length = 0;
+                break;
+        case 16:                /* RGBA 5551 */
+                if (var->transp.length) {
+                        var->red.offset = 0;
+                        var->red.length = 5;
+                        var->green.offset = 5;
+                        var->green.length = 5;
+                        var->blue.offset = 10;
+                        var->blue.length = 5;
+                        var->transp.offset = 15;
+                        var->transp.length = 1;
+                } else {        /* RGB 565 */
+                        var->red.offset = 11;
+                        var->red.length = 5;
+                        var->green.offset = 5;
+                        var->green.length = 6;
+                        var->blue.offset = 0;
+                        var->blue.length = 5;
+                        var->transp.offset = 0;
+                        var->transp.length = 0;
+                }
+                break;
+        case 24:                /* RGB 888 */
+                var->red.offset = 0;
+                var->red.length = 8;
+                var->green.offset = 8;
+                var->green.length = 8;
+                var->blue.offset = 16;
+                var->blue.length = 8;
+                var->transp.offset = 0;
+                var->transp.length = 0;
+                break;
+        case 32:                /* RGBA 8888 */
+                var->red.offset = 16;
+                var->red.length = 8;
+                var->green.offset = 8;
+                var->green.length = 8;
+                var->blue.offset = 0;
+                var->blue.length = 8;
+                var->transp.offset = 24;
+                var->transp.length = 8;
+                break;
+        }
+        var->red.msb_right = 0;
+        var->green.msb_right = 0;
+        var->blue.msb_right = 0;
+        var->transp.msb_right = 0;
+
+        return 0;
+}
+
+/*
+ * This routine actually sets the video mode. It's in here where we
+ * the hardware state info->par and fix which can be affected by the
+ * change in par. For this driver it doesn't do much.
+ */
+static int unifb_set_par(struct fb_info *info)
+{
+        int hTotal, vTotal, hSyncStart, hSyncEnd, vSyncStart, vSyncEnd;
+        int format;
+
+#ifdef CONFIG_PUV3_PM
+        struct clk *clk_vga;
+        u32 pixclk = 0;
+        int i;
+
+        for (i = 0; i <= 10; i++) {
+                if    (info->var.xres         == unifb_modes[i].xres
+                    && info->var.yres         == unifb_modes[i].yres
+                    && info->var.upper_margin == unifb_modes[i].upper_margin
+                    && info->var.lower_margin == unifb_modes[i].lower_margin
+                    && info->var.left_margin  == unifb_modes[i].left_margin
+                    && info->var.right_margin == unifb_modes[i].right_margin
+                    && info->var.hsync_len    == unifb_modes[i].hsync_len
+                    && info->var.vsync_len    == unifb_modes[i].vsync_len) {
+                        pixclk = unifb_modes[i].pixclock;
+                        break;
+                }
+        }
+
+        /* set clock rate */
+        clk_vga = clk_get(info->device, "VGA_CLK");
+        if (clk_vga == ERR_PTR(-ENOENT))
+                return -ENOENT;
+
+        if (pixclk != 0) {
+                if (clk_set_rate(clk_vga, pixclk)) { /* set clock failed */
+                        info->fix = unifb_fix;
+                        info->var = unifb_default;
+                        if (clk_set_rate(clk_vga, unifb_default.pixclock))
+                                return -EINVAL;
+                }
+        }
+#endif
+
+        info->fix.line_length = get_line_length(info->var.xres_virtual,
+                                                info->var.bits_per_pixel);
+
+        hSyncStart = info->var.xres + info->var.right_margin;
+        hSyncEnd = hSyncStart + info->var.hsync_len;
+        hTotal = hSyncEnd + info->var.left_margin;
+
+        vSyncStart = info->var.yres + info->var.lower_margin;
+        vSyncEnd = vSyncStart + info->var.vsync_len;
+        vTotal = vSyncEnd + info->var.upper_margin;
+
+        switch (info->var.bits_per_pixel) {
+        case 8:
+                format = UDE_CFG_DST8;
+                break;
+        case 16:
+                format = UDE_CFG_DST16;
+                break;
+        case 24:
+                format = UDE_CFG_DST24;
+                break;
+        case 32:
+                format = UDE_CFG_DST32;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        writel(PKUNITY_UNIGFX_MMAP_BASE, UDE_FSA);
+        writel(info->var.yres, UDE_LS);
+        writel(get_line_length(info->var.xres,
+                        info->var.bits_per_pixel) >> 3, UDE_PS);
+                        /* >> 3 for hardware required. */
+        writel((hTotal << 16) | (info->var.xres), UDE_HAT);
+        writel(((hTotal - 1) << 16) | (info->var.xres - 1), UDE_HBT);
+        writel(((hSyncEnd - 1) << 16) | (hSyncStart - 1), UDE_HST);
+        writel((vTotal << 16) | (info->var.yres), UDE_VAT);
+        writel(((vTotal - 1) << 16) | (info->var.yres - 1), UDE_VBT);
+        writel(((vSyncEnd - 1) << 16) | (vSyncStart - 1), UDE_VST);
+        writel(UDE_CFG_GDEN_ENABLE | UDE_CFG_TIMEUP_ENABLE
+                        | format | 0xC0000001, UDE_CFG);
+
+        return 0;
+}
+
+/*
+ *  Set a single color register. The values supplied are already
+ *  rounded down to the hardware's capabilities (according to the
+ *  entries in the var structure). Return != 0 for invalid regno.
+ */
+static int unifb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+                         u_int transp, struct fb_info *info)
+{
+        if (regno >= 256)       /* no. of hw registers */
+                return 1;
+
+        /* grayscale works only partially under directcolor */
+        if (info->var.grayscale) {
+                /* grayscale = 0.30*R + 0.59*G + 0.11*B */
+                red = green = blue =
+                    (red * 77 + green * 151 + blue * 28) >> 8;
+        }
+
+#define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16)
+        switch (info->fix.visual) {
+        case FB_VISUAL_TRUECOLOR:
+        case FB_VISUAL_PSEUDOCOLOR:
+                red = CNVT_TOHW(red, info->var.red.length);
+                green = CNVT_TOHW(green, info->var.green.length);
+                blue = CNVT_TOHW(blue, info->var.blue.length);
+                transp = CNVT_TOHW(transp, info->var.transp.length);
+                break;
+        case FB_VISUAL_DIRECTCOLOR:
+                red = CNVT_TOHW(red, 8);        /* expect 8 bit DAC */
+                green = CNVT_TOHW(green, 8);
+                blue = CNVT_TOHW(blue, 8);
+                /* hey, there is bug in transp handling... */
+                transp = CNVT_TOHW(transp, 8);
+                break;
+        }
+#undef CNVT_TOHW
+        /* Truecolor has hardware independent palette */
+        if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
+                u32 v;
+
+                if (regno >= 16)
+                        return 1;
+
+                v = (red << info->var.red.offset) |
+                    (green << info->var.green.offset) |
+                    (blue << info->var.blue.offset) |
+                    (transp << info->var.transp.offset);
+                switch (info->var.bits_per_pixel) {
+                case 8:
+                        break;
+                case 16:
+                case 24:
+                case 32:
+                        ((u32 *) (info->pseudo_palette))[regno] = v;
+                        break;
+                default:
+                        return 1;
+                }
+                return 0;
+        }
+        return 0;
+}
+
+/*
+ *  Pan or Wrap the Display
+ *
+ *  This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
+ */
+static int unifb_pan_display(struct fb_var_screeninfo *var,
+                           struct fb_info *info)
+{
+        if (var->vmode & FB_VMODE_YWRAP) {
+                if (var->yoffset < 0
+                    || var->yoffset >= info->var.yres_virtual
+                    || var->xoffset)
+                        return -EINVAL;
+        } else {
+                if (var->xoffset + var->xres > info->var.xres_virtual ||
+                    var->yoffset + var->yres > info->var.yres_virtual)
+                        return -EINVAL;
+        }
+        info->var.xoffset = var->xoffset;
+        info->var.yoffset = var->yoffset;
+        if (var->vmode & FB_VMODE_YWRAP)
+                info->var.vmode |= FB_VMODE_YWRAP;
+        else
+                info->var.vmode &= ~FB_VMODE_YWRAP;
+        return 0;
+}
+
+int unifb_mmap(struct fb_info *info,
+                    struct vm_area_struct *vma)
+{
+        unsigned long size = vma->vm_end - vma->vm_start;
+        unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
+        unsigned long pos = info->fix.smem_start + offset;
+
+        if (offset + size > info->fix.smem_len)
+                return -EINVAL;
+
+        vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+        if (io_remap_pfn_range(vma, vma->vm_start, pos >> PAGE_SHIFT, size,
+                                vma->vm_page_prot))
+                return -EAGAIN;
+
+        vma->vm_flags |= VM_RESERVED;   /* avoid to swap out this VMA */
+        return 0;
+
+}
+
+static struct fb_ops unifb_ops = {
+        .fb_read        = fb_sys_read,
+        .fb_write       = fb_sys_write,
+        .fb_check_var   = unifb_check_var,
+        .fb_set_par     = unifb_set_par,
+        .fb_setcolreg   = unifb_setcolreg,
+        .fb_pan_display = unifb_pan_display,
+        .fb_fillrect    = unifb_fillrect,
+        .fb_copyarea    = unifb_copyarea,
+        .fb_imageblit   = unifb_imageblit,
+        .fb_mmap        = unifb_mmap,
+};
+
+/*
+ *  Initialisation
+ */
+static int unifb_probe(struct platform_device *dev)
+{
+        struct fb_info *info;
+        u32 unifb_regs[UNIFB_REGS_NUM];
+        int retval = -ENOMEM;
+        struct resource *iomem, *mapmem;
+
+        info = framebuffer_alloc(sizeof(u32)*256, &dev->dev);
+        if (!info)
+                goto err;
+
+        info->screen_base = (char __iomem *)KUSER_UNIGFX_BASE;
+        info->fbops = &unifb_ops;
+
+        retval = fb_find_mode(&info->var, info, NULL,
+                              unifb_modes, 10, &unifb_modes[0], 16);
+
+        if (!retval || (retval == 4))
+                info->var = unifb_default;
+
+        iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
+        unifb_fix.mmio_start = iomem->start;
+
+        mapmem = platform_get_resource(dev, IORESOURCE_MEM, 1);
+        unifb_fix.smem_start = mapmem->start;
+        unifb_fix.smem_len = UNIFB_MEMSIZE;
+
+        info->fix = unifb_fix;
+        info->pseudo_palette = info->par;
+        info->par = NULL;
+        info->flags = FBINFO_FLAG_DEFAULT;
+#ifdef FB_ACCEL_PUV3_UNIGFX
+        info->fix.accel = FB_ACCEL_PUV3_UNIGFX;
+#endif
+
+        retval = fb_alloc_cmap(&info->cmap, 256, 0);
+        if (retval < 0)
+                goto err1;
+
+        retval = register_framebuffer(info);
+        if (retval < 0)
+                goto err2;
+        platform_set_drvdata(dev, info);
+        platform_device_add_data(dev, unifb_regs, sizeof(u32) * UNIFB_REGS_NUM);
+
+        printk(KERN_INFO
+               "fb%d: Virtual frame buffer device, using %dM of video memory\n",
+               info->node, UNIFB_MEMSIZE >> 20);
+        return 0;
+err2:
+        fb_dealloc_cmap(&info->cmap);
+err1:
+        framebuffer_release(info);
+err:
+        return retval;
+}
+
+static int unifb_remove(struct platform_device *dev)
+{
+        struct fb_info *info = platform_get_drvdata(dev);
+
+        if (info) {
+                unregister_framebuffer(info);
+                fb_dealloc_cmap(&info->cmap);
+                framebuffer_release(info);
+        }
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int unifb_resume(struct platform_device *dev)
+{
+        int rc = 0;
+        u32 *unifb_regs = dev->dev.platform_data;
+
+        if (dev->dev.power.power_state.event == PM_EVENT_ON)
+                return 0;
+
+        console_lock();
+
+        if (dev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
+                writel(unifb_regs[0], UDE_FSA);
+                writel(unifb_regs[1], UDE_LS);
+                writel(unifb_regs[2], UDE_PS);
+                writel(unifb_regs[3], UDE_HAT);
+                writel(unifb_regs[4], UDE_HBT);
+                writel(unifb_regs[5], UDE_HST);
+                writel(unifb_regs[6], UDE_VAT);
+                writel(unifb_regs[7], UDE_VBT);
+                writel(unifb_regs[8], UDE_VST);
+                writel(unifb_regs[9], UDE_CFG);
+        }
+        dev->dev.power.power_state = PMSG_ON;
+
+        console_unlock();
+
+        return rc;
+}
+
+static int unifb_suspend(struct platform_device *dev, pm_message_t mesg)
+{
+        u32 *unifb_regs = dev->dev.platform_data;
+
+        unifb_regs[0] = readl(UDE_FSA);
+        unifb_regs[1] = readl(UDE_LS);
+        unifb_regs[2] = readl(UDE_PS);
+        unifb_regs[3] = readl(UDE_HAT);
+        unifb_regs[4] = readl(UDE_HBT);
+        unifb_regs[5] = readl(UDE_HST);
+        unifb_regs[6] = readl(UDE_VAT);
+        unifb_regs[7] = readl(UDE_VBT);
+        unifb_regs[8] = readl(UDE_VST);
+        unifb_regs[9] = readl(UDE_CFG);
+
+        if (mesg.event == dev->dev.power.power_state.event)
+                return 0;
+
+        switch (mesg.event) {
+        case PM_EVENT_FREEZE:           /* about to take snapshot */
+        case PM_EVENT_PRETHAW:          /* before restoring snapshot */
+                goto done;
+        }
+
+        console_lock();
+
+        /* do nothing... */
+
+        console_unlock();
+
+done:
+        dev->dev.power.power_state = mesg;
+
+        return 0;
+}
+#else
+#define unifb_resume    NULL
+#define unifb_suspend   NULL
+#endif
+
+static struct platform_driver unifb_driver = {
+        .probe   = unifb_probe,
+        .remove  = unifb_remove,
+        .resume  = unifb_resume,
+        .suspend = unifb_suspend,
+        .driver  = {
+                .name   = "PKUnity-v3-UNIGFX",
+        },
+};
+
+static int __init unifb_init(void)
+{
+#ifndef MODULE
+        if (fb_get_options("unifb", NULL))
+                return -ENODEV;
+#endif
+
+        return platform_driver_register(&unifb_driver);
+}
+
+module_init(unifb_init);
+
+static void __exit unifb_exit(void)
+{
+        platform_driver_unregister(&unifb_driver);
+}
+
+module_exit(unifb_exit);
+
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/video/ffb.c b/drivers/video/ffb.c
index 6739b2af3bc0..14102a3f70f5 100644
--- a/drivers/video/ffb.c
+++ b/drivers/video/ffb.c
@@ -893,8 +893,7 @@ static void ffb_init_fix(struct fb_info *info)
         info->fix.accel = FB_ACCEL_SUN_CREATOR;
 }
 
-static int __devinit ffb_probe(struct platform_device *op,
-                               const struct of_device_id *match)
+static int __devinit ffb_probe(struct platform_device *op)
 {
         struct device_node *dp = op->dev.of_node;
         struct ffb_fbc __iomem *fbc;
@@ -1011,7 +1010,7 @@ out_dealloc_cmap:
         fb_dealloc_cmap(&info->cmap);
 
 out_unmap_dac:
-        of_iounmap(&op->resource[2], par->fbc, sizeof(struct ffb_fbc));
+        of_iounmap(&op->resource[1], par->dac, sizeof(struct ffb_dac));
 
 out_unmap_fbc:
         of_iounmap(&op->resource[2], par->fbc, sizeof(struct ffb_fbc));
@@ -1052,7 +1051,7 @@ static const struct of_device_id ffb_match[] = {
 };
 MODULE_DEVICE_TABLE(of, ffb_match);
 
-static struct of_platform_driver ffb_driver = {
+static struct platform_driver ffb_driver = {
         .driver = {
                 .name = "ffb",
                 .owner = THIS_MODULE,
@@ -1067,12 +1066,12 @@ static int __init ffb_init(void)
         if (fb_get_options("ffb", NULL))
                 return -ENODEV;
 
-        return of_register_platform_driver(&ffb_driver);
+        return platform_driver_register(&ffb_driver);
 }
 
 static void __exit ffb_exit(void)
 {
-        of_unregister_platform_driver(&ffb_driver);
+        platform_driver_unregister(&ffb_driver);
 }
 
 module_init(ffb_init);
diff --git a/drivers/video/fsl-diu-fb.c b/drivers/video/fsl-diu-fb.c
index 8bbbf08fa3ce..9048f87fa8c1 100644
--- a/drivers/video/fsl-diu-fb.c
+++ b/drivers/video/fsl-diu-fb.c
@@ -1487,8 +1487,7 @@ static ssize_t show_monitor(struct device *device,
         return diu_ops.show_monitor_port(machine_data->monitor_port, buf);
 }
 
-static int __devinit fsl_diu_probe(struct platform_device *ofdev,
-        const struct of_device_id *match)
+static int __devinit fsl_diu_probe(struct platform_device *ofdev)
 {
         struct device_node *np = ofdev->dev.of_node;
         struct mfb_info *mfbi;
@@ -1735,7 +1734,7 @@ static struct of_device_id fsl_diu_match[] = {
 };
 MODULE_DEVICE_TABLE(of, fsl_diu_match);
 
-static struct of_platform_driver fsl_diu_driver = {
+static struct platform_driver fsl_diu_driver = {
         .driver = {
                 .name = "fsl_diu",
                 .owner = THIS_MODULE,
@@ -1797,7 +1796,7 @@ static int __init fsl_diu_init(void)
         if (!coherence_data)
                 return -ENOMEM;
 #endif
-        ret = of_register_platform_driver(&fsl_diu_driver);
+        ret = platform_driver_register(&fsl_diu_driver);
         if (ret) {
                 printk(KERN_ERR
                         "fsl-diu: failed to register platform driver\n");
@@ -1811,7 +1810,7 @@ static int __init fsl_diu_init(void)
 
 static void __exit fsl_diu_exit(void)
 {
-        of_unregister_platform_driver(&fsl_diu_driver);
+        platform_driver_unregister(&fsl_diu_driver);
 #if defined(CONFIG_NOT_COHERENT_CACHE)
         vfree(coherence_data);
 #endif
diff --git a/drivers/video/hecubafb.c b/drivers/video/hecubafb.c
index c77bcc6ab463..1b94643ecbcf 100644
--- a/drivers/video/hecubafb.c
+++ b/drivers/video/hecubafb.c
@@ -299,7 +299,7 @@ static int __devexit hecubafb_remove(struct platform_device *dev)
 
 static struct platform_driver hecubafb_driver = {
         .probe  = hecubafb_probe,
-        .remove = hecubafb_remove,
+        .remove = __devexit_p(hecubafb_remove),
         .driver = {
                 .owner  = THIS_MODULE,
                 .name   = "hecubafb",
diff --git a/drivers/video/hpfb.c b/drivers/video/hpfb.c
index c8e280f1bb0b..ebf8495ff198 100644
--- a/drivers/video/hpfb.c
+++ b/drivers/video/hpfb.c
@@ -321,11 +321,11 @@ static int __devinit hpfb_dio_probe(struct dio_dev * d, const struct dio_device_
         unsigned long paddr, vaddr;
 
         paddr = d->resource.start;
-        if (!request_mem_region(d->resource.start, d->resource.end - d->resource.start, d->name))
+        if (!request_mem_region(d->resource.start, resource_size(&d->resource), d->name))
                 return -EBUSY;
 
         if (d->scode >= DIOII_SCBASE) {
-                vaddr = (unsigned long)ioremap(paddr, d->resource.end - d->resource.start);
+                vaddr = (unsigned long)ioremap(paddr, resource_size(&d->resource));
         } else {
                 vaddr = paddr + DIO_VIRADDRBASE;
         }
@@ -344,7 +344,7 @@ static void __devexit hpfb_remove_one(struct dio_dev *d)
         unregister_framebuffer(&fb_info);
         if (d->scode >= DIOII_SCBASE)
                 iounmap((void *)fb_regs);
-        release_mem_region(d->resource.start, d->resource.end - d->resource.start);
+        release_mem_region(d->resource.start, resource_size(&d->resource));
 }
 
 static struct dio_device_id hpfb_dio_tbl[] = {
diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
index 69bd4a581d4a..ef72cb483834 100644
--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -499,6 +499,7 @@ static void imxfb_init_backlight(struct imxfb_info *fbi)
 
         memset(&props, 0, sizeof(struct backlight_properties));
         props.max_brightness = 0xff;
+        props.type = BACKLIGHT_RAW;
         writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
 
         bl = backlight_device_register("imxfb-bl", &fbi->pdev->dev, fbi,
diff --git a/drivers/video/intelfb/Makefile b/drivers/video/intelfb/Makefile
index 6c782d3ae1be..f7d631ebee8e 100644
--- a/drivers/video/intelfb/Makefile
+++ b/drivers/video/intelfb/Makefile
@@ -4,7 +4,4 @@ intelfb-y := intelfbdrv.o intelfbhw.o
 intelfb-$(CONFIG_FB_INTEL_I2C) += intelfb_i2c.o
 intelfb-objs := $(intelfb-y)
 
-ifdef CONFIG_FB_INTEL_DEBUG
-#EXTRA_CFLAGS += -DDEBUG -DVERBOSE -DREGDUMP
-EXTRA_CFLAGS += -DDEBUG -DREGDUMP
-endif
+ccflags-$(CONFIG_FB_INTEL_DEBUG) := -DDEBUG -DREGDUMP
diff --git a/drivers/video/leo.c b/drivers/video/leo.c
index b599e5e36ced..9e946e2c1da9 100644
--- a/drivers/video/leo.c
+++ b/drivers/video/leo.c
@@ -547,8 +547,7 @@ static void leo_unmap_regs(struct platform_device *op, struct fb_info *info,
                 of_iounmap(&op->resource[0], info->screen_base, 0x800000);
 }
 
-static int __devinit leo_probe(struct platform_device *op,
-                               const struct of_device_id *match)
+static int __devinit leo_probe(struct platform_device *op)
 {
         struct device_node *dp = op->dev.of_node;
         struct fb_info *info;
@@ -662,7 +661,7 @@ static const struct of_device_id leo_match[] = {
 };
 MODULE_DEVICE_TABLE(of, leo_match);
 
-static struct of_platform_driver leo_driver = {
+static struct platform_driver leo_driver = {
         .driver = {
                 .name = "leo",
                 .owner = THIS_MODULE,
@@ -677,12 +676,12 @@ static int __init leo_init(void)
         if (fb_get_options("leofb", NULL))
                 return -ENODEV;
 
-        return of_register_platform_driver(&leo_driver);
+        return platform_driver_register(&leo_driver);
 }
 
 static void __exit leo_exit(void)
 {
-        of_unregister_platform_driver(&leo_driver);
+        platform_driver_unregister(&leo_driver);
 }
 
 module_init(leo_init);
diff --git a/drivers/video/matrox/matroxfb_base.c b/drivers/video/matrox/matroxfb_base.c
index 8c9dbac9dc1b..5ce6fa6e59f0 100644
--- a/drivers/video/matrox/matroxfb_base.c
+++ b/drivers/video/matrox/matroxfb_base.c
@@ -1458,13 +1458,6 @@ static struct board {
                 MGA_G100,
                 &vbG100,
                 "MGA-G100 (AGP)"},
-        {PCI_VENDOR_ID_MATROX,  PCI_DEVICE_ID_MATROX_G200EV_PCI,        0xFF,
-                0,                      0,
-                DEVF_G200,
-                230000,
-                MGA_G200,
-                &vbG200,
-                "MGA-G200eV (PCI)"},
         {PCI_VENDOR_ID_MATROX,  PCI_DEVICE_ID_MATROX_G200_PCI,  0xFF,
                 0,                      0,
                 DEVF_G200,
@@ -2116,8 +2109,6 @@ static struct pci_device_id matroxfb_devices[] = {
                 PCI_ANY_ID,     PCI_ANY_ID,     0, 0, 0},
         {PCI_VENDOR_ID_MATROX,  PCI_DEVICE_ID_MATROX_G100_AGP,
                 PCI_ANY_ID,     PCI_ANY_ID,     0, 0, 0},
-        {PCI_VENDOR_ID_MATROX,  PCI_DEVICE_ID_MATROX_G200EV_PCI,
-                PCI_ANY_ID,     PCI_ANY_ID,     0, 0, 0},
         {PCI_VENDOR_ID_MATROX,  PCI_DEVICE_ID_MATROX_G200_PCI,
                 PCI_ANY_ID,     PCI_ANY_ID,     0, 0, 0},
         {PCI_VENDOR_ID_MATROX,  PCI_DEVICE_ID_MATROX_G200_AGP,
diff --git a/drivers/video/mb862xx/mb862xxfb.c b/drivers/video/mb862xx/mb862xxfb.c
index b1c4374cf940..c76e663a6cd4 100644
--- a/drivers/video/mb862xx/mb862xxfb.c
+++ b/drivers/video/mb862xx/mb862xxfb.c
@@ -550,8 +550,7 @@ static int mb862xx_gdc_init(struct mb862xxfb_par *par)
         return 0;
 }
 
-static int __devinit of_platform_mb862xx_probe(struct platform_device *ofdev,
-                                               const struct of_device_id *id)
+static int __devinit of_platform_mb862xx_probe(struct platform_device *ofdev)
 {
         struct device_node *np = ofdev->dev.of_node;
         struct device *dev = &ofdev->dev;
@@ -717,7 +716,7 @@ static struct of_device_id __devinitdata of_platform_mb862xx_tbl[] = {
         { /* end */ }
 };
 
-static struct of_platform_driver of_platform_mb862xxfb_driver = {
+static struct platform_driver of_platform_mb862xxfb_driver = {
         .driver = {
                 .name = DRV_NAME,
                 .owner = THIS_MODULE,
@@ -1038,7 +1037,7 @@ static int __devinit mb862xxfb_init(void)
         int ret = -ENODEV;
 
 #if defined(CONFIG_FB_MB862XX_LIME)
-        ret = of_register_platform_driver(&of_platform_mb862xxfb_driver);
+        ret = platform_driver_register(&of_platform_mb862xxfb_driver);
 #endif
 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
         ret = pci_register_driver(&mb862xxfb_pci_driver);
@@ -1049,7 +1048,7 @@ static int __devinit mb862xxfb_init(void)
 static void __exit mb862xxfb_exit(void)
 {
 #if defined(CONFIG_FB_MB862XX_LIME)
-        of_unregister_platform_driver(&of_platform_mb862xxfb_driver);
+        platform_driver_unregister(&of_platform_mb862xxfb_driver);
 #endif
 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
         pci_unregister_driver(&mb862xxfb_pci_driver);
diff --git a/drivers/video/metronomefb.c b/drivers/video/metronomefb.c
index 63ed3b72b01c..ed64edfd2c43 100644
--- a/drivers/video/metronomefb.c
+++ b/drivers/video/metronomefb.c
@@ -765,7 +765,7 @@ static int __devexit metronomefb_remove(struct platform_device *dev)
 
 static struct platform_driver metronomefb_driver = {
         .probe  = metronomefb_probe,
-        .remove = metronomefb_remove,
+        .remove = __devexit_p(metronomefb_remove),
         .driver = {
                 .owner  = THIS_MODULE,
                 .name   = "metronomefb",
diff --git a/drivers/video/msm/mdp_hw.h b/drivers/video/msm/mdp_hw.h
index 4e3deb4e592b..d80477415caa 100644
--- a/drivers/video/msm/mdp_hw.h
+++ b/drivers/video/msm/mdp_hw.h
@@ -449,6 +449,7 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
 #define PPP_CFG_MDP_XRGB_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
 #define PPP_CFG_MDP_RGBA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
 #define PPP_CFG_MDP_BGRA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
+#define PPP_CFG_MDP_RGBX_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
 
 #define PPP_CFG_MDP_Y_CBCR_H2V2(dir)   (PPP_##dir##_C2R_8BIT | \
                                         PPP_##dir##_C0G_8BIT | \
@@ -488,12 +489,14 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
         MDP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 8)
 #define PPP_PACK_PATTERN_MDP_RGB_888 PPP_PACK_PATTERN_MDP_RGB_565
 #define PPP_PACK_PATTERN_MDP_XRGB_8888 \
-        MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_R, CLR_G, CLR_B, 8)
+        MDP_GET_PACK_PATTERN(CLR_B, CLR_G, CLR_R, CLR_ALPHA, 8)
 #define PPP_PACK_PATTERN_MDP_ARGB_8888 PPP_PACK_PATTERN_MDP_XRGB_8888
 #define PPP_PACK_PATTERN_MDP_RGBA_8888 \
         MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B, CLR_G, CLR_R, 8)
 #define PPP_PACK_PATTERN_MDP_BGRA_8888 \
         MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_R, CLR_G, CLR_B, 8)
+#define PPP_PACK_PATTERN_MDP_RGBX_8888 \
+        MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B, CLR_G, CLR_R, 8)
 #define PPP_PACK_PATTERN_MDP_Y_CBCR_H2V1 \
         MDP_GET_PACK_PATTERN(0, 0, CLR_CB, CLR_CR, 8)
 #define PPP_PACK_PATTERN_MDP_Y_CBCR_H2V2 PPP_PACK_PATTERN_MDP_Y_CBCR_H2V1
@@ -509,6 +512,7 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
 #define PPP_CHROMA_SAMP_MDP_ARGB_8888(dir) PPP_OP_##dir##_CHROMA_RGB
 #define PPP_CHROMA_SAMP_MDP_RGBA_8888(dir) PPP_OP_##dir##_CHROMA_RGB
 #define PPP_CHROMA_SAMP_MDP_BGRA_8888(dir) PPP_OP_##dir##_CHROMA_RGB
+#define PPP_CHROMA_SAMP_MDP_RGBX_8888(dir) PPP_OP_##dir##_CHROMA_RGB
 #define PPP_CHROMA_SAMP_MDP_Y_CBCR_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1
 #define PPP_CHROMA_SAMP_MDP_Y_CBCR_H2V2(dir) PPP_OP_##dir##_CHROMA_420
 #define PPP_CHROMA_SAMP_MDP_Y_CRCB_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1
@@ -523,6 +527,7 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
         [MDP_ARGB_8888] = PPP_##name##_MDP_ARGB_8888,\
         [MDP_RGBA_8888] = PPP_##name##_MDP_RGBA_8888,\
         [MDP_BGRA_8888] = PPP_##name##_MDP_BGRA_8888,\
+        [MDP_RGBX_8888] = PPP_##name##_MDP_RGBX_8888,\
         [MDP_Y_CBCR_H2V1] = PPP_##name##_MDP_Y_CBCR_H2V1,\
         [MDP_Y_CBCR_H2V2] = PPP_##name##_MDP_Y_CBCR_H2V2,\
         [MDP_Y_CRCB_H2V1] = PPP_##name##_MDP_Y_CRCB_H2V1,\
@@ -536,6 +541,7 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
         [MDP_ARGB_8888] = PPP_##name##_MDP_ARGB_8888(dir),\
         [MDP_RGBA_8888] = PPP_##name##_MDP_RGBA_8888(dir),\
         [MDP_BGRA_8888] = PPP_##name##_MDP_BGRA_8888(dir),\
+        [MDP_RGBX_8888] = PPP_##name##_MDP_RGBX_8888(dir),\
         [MDP_Y_CBCR_H2V1] = PPP_##name##_MDP_Y_CBCR_H2V1(dir),\
         [MDP_Y_CBCR_H2V2] = PPP_##name##_MDP_Y_CBCR_H2V2(dir),\
         [MDP_Y_CRCB_H2V1] = PPP_##name##_MDP_Y_CRCB_H2V1(dir),\
@@ -547,7 +553,8 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
                        (img == MDP_YCRYCB_H2V1))
 #define IS_RGB(img) ((img == MDP_RGB_565) | (img == MDP_RGB_888) | \
                      (img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \
-                     (img == MDP_XRGB_8888) | (img == MDP_BGRA_8888))
+                     (img == MDP_XRGB_8888) | (img == MDP_BGRA_8888) | \
+                     (img == MDP_RGBX_8888))
 #define HAS_ALPHA(img) ((img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \
                         (img == MDP_BGRA_8888))
 
diff --git a/drivers/video/msm/mdp_ppp.c b/drivers/video/msm/mdp_ppp.c
index 4ff001f4cbbd..2b6564e8bfea 100644
--- a/drivers/video/msm/mdp_ppp.c
+++ b/drivers/video/msm/mdp_ppp.c
@@ -69,6 +69,7 @@ static uint32_t bytes_per_pixel[] = {
         [MDP_ARGB_8888] = 4,
         [MDP_RGBA_8888] = 4,
         [MDP_BGRA_8888] = 4,
+        [MDP_RGBX_8888] = 4,
         [MDP_Y_CBCR_H2V1] = 1,
         [MDP_Y_CBCR_H2V2] = 1,
         [MDP_Y_CRCB_H2V1] = 1,
diff --git a/drivers/video/msm/msm_fb.c b/drivers/video/msm/msm_fb.c
index debe5933fd2e..ec351309e607 100644
--- a/drivers/video/msm/msm_fb.c
+++ b/drivers/video/msm/msm_fb.c
@@ -81,7 +81,6 @@ struct msmfb_info {
         spinlock_t update_lock;
         struct mutex panel_init_lock;
         wait_queue_head_t frame_wq;
-        struct workqueue_struct *resume_workqueue;
         struct work_struct resume_work;
         struct msmfb_callback dma_callback;
         struct msmfb_callback vsync_callback;
@@ -111,7 +110,7 @@ static void msmfb_handle_dma_interrupt(struct msmfb_callback *callback)
         if (msmfb->sleeping == UPDATING &&
             msmfb->frame_done == msmfb->update_frame) {
                 DLOG(SUSPEND_RESUME, "full update completed\n");
-                queue_work(msmfb->resume_workqueue, &msmfb->resume_work);
+                schedule_work(&msmfb->resume_work);
         }
         spin_unlock_irqrestore(&msmfb->update_lock, irq_flags);
         wake_up(&msmfb->frame_wq);
@@ -220,8 +219,8 @@ restart:
 
         sleeping = msmfb->sleeping;
         /* on a full update, if the last frame has not completed, wait for it */
-        if (pan_display && (msmfb->frame_requested != msmfb->frame_done ||
-                            sleeping == UPDATING)) {
+        if ((pan_display && msmfb->frame_requested != msmfb->frame_done) ||
+                            sleeping == UPDATING) {
                 int ret;
                 spin_unlock_irqrestore(&msmfb->update_lock, irq_flags);
                 ret = wait_event_interruptible_timeout(msmfb->frame_wq,
@@ -470,6 +469,18 @@ static void setup_fb_info(struct msmfb_info *msmfb)
         fb_info->var.yoffset = 0;
 
         if (msmfb->panel->caps & MSMFB_CAP_PARTIAL_UPDATES) {
+                /*
+                 * Set the param in the fixed screen, so userspace can't
+                 * change it. This will be used to check for the
+                 * capability.
+                 */
+                fb_info->fix.reserved[0] = 0x5444;
+                fb_info->fix.reserved[1] = 0x5055;
+
+                /*
+                 * This preloads the value so that if userspace doesn't
+                 * change it, it will be a full update
+                 */
                 fb_info->var.reserved[0] = 0x54445055;
                 fb_info->var.reserved[1] = 0;
                 fb_info->var.reserved[2] = (uint16_t)msmfb->xres |
@@ -559,12 +570,6 @@ static int msmfb_probe(struct platform_device *pdev)
         spin_lock_init(&msmfb->update_lock);
         mutex_init(&msmfb->panel_init_lock);
         init_waitqueue_head(&msmfb->frame_wq);
-        msmfb->resume_workqueue = create_workqueue("panel_on");
-        if (msmfb->resume_workqueue == NULL) {
-                printk(KERN_ERR "failed to create panel_on workqueue\n");
-                ret = -ENOMEM;
-                goto error_create_workqueue;
-        }
         INIT_WORK(&msmfb->resume_work, power_on_panel);
         msmfb->black = kzalloc(msmfb->fb->var.bits_per_pixel*msmfb->xres,
                                GFP_KERNEL);
@@ -589,8 +594,6 @@ static int msmfb_probe(struct platform_device *pdev)
         return 0;
 
 error_register_framebuffer:
-        destroy_workqueue(msmfb->resume_workqueue);
-error_create_workqueue:
         iounmap(fb->screen_base);
 error_setup_fbmem:
         framebuffer_release(msmfb->fb);
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
new file mode 100644
index 000000000000..7d0284882984
--- /dev/null
+++ b/drivers/video/mxsfb.c
@@ -0,0 +1,919 @@
+/*
+ * Copyright (C) 2010 Juergen Beisert, Pengutronix
+ *
+ * This code is based on:
+ * Author: Vitaly Wool <vital@embeddedalley.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DRIVER_NAME "mxsfb"
+
+/**
+ * @file
+ * @brief LCDIF driver for i.MX23 and i.MX28
+ *
+ * The LCDIF support four modes of operation
+ * - MPU interface (to drive smart displays) -> not supported yet
+ * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet
+ * - Dotclock interface (to drive LC displays with RGB data and sync signals)
+ * - DVI (to drive ITU-R BT656)  -> not supported yet
+ *
+ * This driver depends on a correct setup of the pins used for this purpose
+ * (platform specific).
+ *
+ * For the developer: Don't forget to set the data bus width to the display
+ * in the imx_fb_videomode structure. You will else end up with ugly colours.
+ * If you fight against jitter you can vary the clock delay. This is a feature
+ * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give
+ * the required value in the imx_fb_videomode structure.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <mach/mxsfb.h>
+
+#define REG_SET 4
+#define REG_CLR 8
+
+#define LCDC_CTRL                       0x00
+#define LCDC_CTRL1                      0x10
+#define LCDC_V4_CTRL2                   0x20
+#define LCDC_V3_TRANSFER_COUNT          0x20
+#define LCDC_V4_TRANSFER_COUNT          0x30
+#define LCDC_V4_CUR_BUF                 0x40
+#define LCDC_V4_NEXT_BUF                0x50
+#define LCDC_V3_CUR_BUF                 0x30
+#define LCDC_V3_NEXT_BUF                0x40
+#define LCDC_TIMING                     0x60
+#define LCDC_VDCTRL0                    0x70
+#define LCDC_VDCTRL1                    0x80
+#define LCDC_VDCTRL2                    0x90
+#define LCDC_VDCTRL3                    0xa0
+#define LCDC_VDCTRL4                    0xb0
+#define LCDC_DVICTRL0                   0xc0
+#define LCDC_DVICTRL1                   0xd0
+#define LCDC_DVICTRL2                   0xe0
+#define LCDC_DVICTRL3                   0xf0
+#define LCDC_DVICTRL4                   0x100
+#define LCDC_V4_DATA                    0x180
+#define LCDC_V3_DATA                    0x1b0
+#define LCDC_V4_DEBUG0                  0x1d0
+#define LCDC_V3_DEBUG0                  0x1f0
+
+#define CTRL_SFTRST                     (1 << 31)
+#define CTRL_CLKGATE                    (1 << 30)
+#define CTRL_BYPASS_COUNT               (1 << 19)
+#define CTRL_VSYNC_MODE                 (1 << 18)
+#define CTRL_DOTCLK_MODE                (1 << 17)
+#define CTRL_DATA_SELECT                (1 << 16)
+#define CTRL_SET_BUS_WIDTH(x)           (((x) & 0x3) << 10)
+#define CTRL_GET_BUS_WIDTH(x)           (((x) >> 10) & 0x3)
+#define CTRL_SET_WORD_LENGTH(x)         (((x) & 0x3) << 8)
+#define CTRL_GET_WORD_LENGTH(x)         (((x) >> 8) & 0x3)
+#define CTRL_MASTER                     (1 << 5)
+#define CTRL_DF16                       (1 << 3)
+#define CTRL_DF18                       (1 << 2)
+#define CTRL_DF24                       (1 << 1)
+#define CTRL_RUN                        (1 << 0)
+
+#define CTRL1_FIFO_CLEAR                (1 << 21)
+#define CTRL1_SET_BYTE_PACKAGING(x)     (((x) & 0xf) << 16)
+#define CTRL1_GET_BYTE_PACKAGING(x)     (((x) >> 16) & 0xf)
+
+#define TRANSFER_COUNT_SET_VCOUNT(x)    (((x) & 0xffff) << 16)
+#define TRANSFER_COUNT_GET_VCOUNT(x)    (((x) >> 16) & 0xffff)
+#define TRANSFER_COUNT_SET_HCOUNT(x)    ((x) & 0xffff)
+#define TRANSFER_COUNT_GET_HCOUNT(x)    ((x) & 0xffff)
+
+
+#define VDCTRL0_ENABLE_PRESENT          (1 << 28)
+#define VDCTRL0_VSYNC_ACT_HIGH          (1 << 27)
+#define VDCTRL0_HSYNC_ACT_HIGH          (1 << 26)
+#define VDCTRL0_DOTCLK_ACT_FAILING      (1 << 25)
+#define VDCTRL0_ENABLE_ACT_HIGH         (1 << 24)
+#define VDCTRL0_VSYNC_PERIOD_UNIT       (1 << 21)
+#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT  (1 << 20)
+#define VDCTRL0_HALF_LINE               (1 << 19)
+#define VDCTRL0_HALF_LINE_MODE          (1 << 18)
+#define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
+#define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
+
+#define VDCTRL2_SET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
+#define VDCTRL2_GET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
+
+#define VDCTRL3_MUX_SYNC_SIGNALS        (1 << 29)
+#define VDCTRL3_VSYNC_ONLY              (1 << 28)
+#define SET_HOR_WAIT_CNT(x)             (((x) & 0xfff) << 16)
+#define GET_HOR_WAIT_CNT(x)             (((x) >> 16) & 0xfff)
+#define SET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
+#define GET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
+
+#define VDCTRL4_SET_DOTCLK_DLY(x)       (((x) & 0x7) << 29) /* v4 only */
+#define VDCTRL4_GET_DOTCLK_DLY(x)       (((x) >> 29) & 0x7) /* v4 only */
+#define VDCTRL4_SYNC_SIGNALS_ON         (1 << 18)
+#define SET_DOTCLK_H_VALID_DATA_CNT(x)  ((x) & 0x3ffff)
+
+#define DEBUG0_HSYNC                    (1 < 26)
+#define DEBUG0_VSYNC                    (1 < 25)
+
+#define MIN_XRES                        120
+#define MIN_YRES                        120
+
+#define RED 0
+#define GREEN 1
+#define BLUE 2
+#define TRANSP 3
+
+enum mxsfb_devtype {
+        MXSFB_V3,
+        MXSFB_V4,
+};
+
+/* CPU dependent register offsets */
+struct mxsfb_devdata {
+        unsigned transfer_count;
+        unsigned cur_buf;
+        unsigned next_buf;
+        unsigned debug0;
+        unsigned hs_wdth_mask;
+        unsigned hs_wdth_shift;
+        unsigned ipversion;
+};
+
+struct mxsfb_info {
+        struct fb_info fb_info;
+        struct platform_device *pdev;
+        struct clk *clk;
+        void __iomem *base;     /* registers */
+        unsigned allocated_size;
+        int enabled;
+        unsigned ld_intf_width;
+        unsigned dotclk_delay;
+        const struct mxsfb_devdata *devdata;
+        int mapped;
+};
+
+#define mxsfb_is_v3(host) (host->devdata->ipversion == 3)
+#define mxsfb_is_v4(host) (host->devdata->ipversion == 4)
+
+static const struct mxsfb_devdata mxsfb_devdata[] = {
+        [MXSFB_V3] = {
+                .transfer_count = LCDC_V3_TRANSFER_COUNT,
+                .cur_buf = LCDC_V3_CUR_BUF,
+                .next_buf = LCDC_V3_NEXT_BUF,
+                .debug0 = LCDC_V3_DEBUG0,
+                .hs_wdth_mask = 0xff,
+                .hs_wdth_shift = 24,
+                .ipversion = 3,
+        },
+        [MXSFB_V4] = {
+                .transfer_count = LCDC_V4_TRANSFER_COUNT,
+                .cur_buf = LCDC_V4_CUR_BUF,
+                .next_buf = LCDC_V4_NEXT_BUF,
+                .debug0 = LCDC_V4_DEBUG0,
+                .hs_wdth_mask = 0x3fff,
+                .hs_wdth_shift = 18,
+                .ipversion = 4,
+        },
+};
+
+#define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info))
+
+/* mask and shift depends on architecture */
+static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
+{
+        return (val & host->devdata->hs_wdth_mask) <<
+                host->devdata->hs_wdth_shift;
+}
+
+static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
+{
+        return (val >> host->devdata->hs_wdth_shift) &
+                host->devdata->hs_wdth_mask;
+}
+
+static const struct fb_bitfield def_rgb565[] = {
+        [RED] = {
+                .offset = 11,
+                .length = 5,
+        },
+        [GREEN] = {
+                .offset = 5,
+                .length = 6,
+        },
+        [BLUE] = {
+                .offset = 0,
+                .length = 5,
+        },
+        [TRANSP] = {    /* no support for transparency */
+                .length = 0,
+        }
+};
+
+static const struct fb_bitfield def_rgb666[] = {
+        [RED] = {
+                .offset = 16,
+                .length = 6,
+        },
+        [GREEN] = {
+                .offset = 8,
+                .length = 6,
+        },
+        [BLUE] = {
+                .offset = 0,
+                .length = 6,
+        },
+        [TRANSP] = {    /* no support for transparency */
+                .length = 0,
+        }
+};
+
+static const struct fb_bitfield def_rgb888[] = {
+        [RED] = {
+                .offset = 16,
+                .length = 8,
+        },
+        [GREEN] = {
+                .offset = 8,
+                .length = 8,
+        },
+        [BLUE] = {
+                .offset = 0,
+                .length = 8,
+        },
+        [TRANSP] = {    /* no support for transparency */
+                .length = 0,
+        }
+};
+
+static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf)
+{
+        chan &= 0xffff;
+        chan >>= 16 - bf->length;
+        return chan << bf->offset;
+}
+
+static int mxsfb_check_var(struct fb_var_screeninfo *var,
+                struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        const struct fb_bitfield *rgb = NULL;
+
+        if (var->xres < MIN_XRES)
+                var->xres = MIN_XRES;
+        if (var->yres < MIN_YRES)
+                var->yres = MIN_YRES;
+
+        var->xres_virtual = var->xres;
+
+        var->yres_virtual = var->yres;
+
+        switch (var->bits_per_pixel) {
+        case 16:
+                /* always expect RGB 565 */
+                rgb = def_rgb565;
+                break;
+        case 32:
+                switch (host->ld_intf_width) {
+                case STMLCDIF_8BIT:
+                        pr_debug("Unsupported LCD bus width mapping\n");
+                        break;
+                case STMLCDIF_16BIT:
+                case STMLCDIF_18BIT:
+                        /* 24 bit to 18 bit mapping */
+                        rgb = def_rgb666;
+                        break;
+                case STMLCDIF_24BIT:
+                        /* real 24 bit */
+                        rgb = def_rgb888;
+                        break;
+                }
+                break;
+        default:
+                pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel);
+                return -EINVAL;
+        }
+
+        /*
+         * Copy the RGB parameters for this display
+         * from the machine specific parameters.
+         */
+        var->red    = rgb[RED];
+        var->green  = rgb[GREEN];
+        var->blue   = rgb[BLUE];
+        var->transp = rgb[TRANSP];
+
+        return 0;
+}
+
+static void mxsfb_enable_controller(struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        u32 reg;
+
+        dev_dbg(&host->pdev->dev, "%s\n", __func__);
+
+        clk_enable(host->clk);
+        clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
+
+        /* if it was disabled, re-enable the mode again */
+        writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
+
+        /* enable the SYNC signals first, then the DMA engine */
+        reg = readl(host->base + LCDC_VDCTRL4);
+        reg |= VDCTRL4_SYNC_SIGNALS_ON;
+        writel(reg, host->base + LCDC_VDCTRL4);
+
+        writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET);
+
+        host->enabled = 1;
+}
+
+static void mxsfb_disable_controller(struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        unsigned loop;
+        u32 reg;
+
+        dev_dbg(&host->pdev->dev, "%s\n", __func__);
+
+        /*
+         * Even if we disable the controller here, it will still continue
+         * until its FIFOs are running out of data
+         */
+        writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR);
+
+        loop = 1000;
+        while (loop) {
+                reg = readl(host->base + LCDC_CTRL);
+                if (!(reg & CTRL_RUN))
+                        break;
+                loop--;
+        }
+
+        writel(VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4 + REG_CLR);
+
+        clk_disable(host->clk);
+
+        host->enabled = 0;
+}
+
+static int mxsfb_set_par(struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        u32 ctrl, vdctrl0, vdctrl4;
+        int line_size, fb_size;
+        int reenable = 0;
+
+        line_size =  fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
+        fb_size = fb_info->var.yres_virtual * line_size;
+
+        if (fb_size > fb_info->fix.smem_len)
+                return -ENOMEM;
+
+        fb_info->fix.line_length = line_size;
+
+        /*
+         * It seems, you can't re-program the controller if it is still running.
+         * This may lead into shifted pictures (FIFO issue?).
+         * So, first stop the controller and drain its FIFOs
+         */
+        if (host->enabled) {
+                reenable = 1;
+                mxsfb_disable_controller(fb_info);
+        }
+
+        /* clear the FIFOs */
+        writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
+
+        ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER |
+                CTRL_SET_BUS_WIDTH(host->ld_intf_width);;
+
+        switch (fb_info->var.bits_per_pixel) {
+        case 16:
+                dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n");
+                ctrl |= CTRL_SET_WORD_LENGTH(0);
+                writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1);
+                break;
+        case 32:
+                dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
+                ctrl |= CTRL_SET_WORD_LENGTH(3);
+                switch (host->ld_intf_width) {
+                case STMLCDIF_8BIT:
+                        dev_dbg(&host->pdev->dev,
+                                        "Unsupported LCD bus width mapping\n");
+                        return -EINVAL;
+                case STMLCDIF_16BIT:
+                case STMLCDIF_18BIT:
+                        /* 24 bit to 18 bit mapping */
+                        ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
+                                            *  each colour component
+                                            */
+                        break;
+                case STMLCDIF_24BIT:
+                        /* real 24 bit */
+                        break;
+                }
+                /* do not use packed pixels = one pixel per word instead */
+                writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1);
+                break;
+        default:
+                dev_dbg(&host->pdev->dev, "Unhandled color depth of %u\n",
+                                fb_info->var.bits_per_pixel);
+                return -EINVAL;
+        }
+
+        writel(ctrl, host->base + LCDC_CTRL);
+
+        writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) |
+                        TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres),
+                        host->base + host->devdata->transfer_count);
+
+        vdctrl0 = VDCTRL0_ENABLE_PRESENT |      /* always in DOTCLOCK mode */
+                VDCTRL0_VSYNC_PERIOD_UNIT |
+                VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
+                VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len);
+        if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT)
+                vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
+        if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT)
+                vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
+        if (fb_info->var.sync & FB_SYNC_DATA_ENABLE_HIGH_ACT)
+                vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
+        if (fb_info->var.sync & FB_SYNC_DOTCLK_FAILING_ACT)
+                vdctrl0 |= VDCTRL0_DOTCLK_ACT_FAILING;
+
+        writel(vdctrl0, host->base + LCDC_VDCTRL0);
+
+        /* frame length in lines */
+        writel(fb_info->var.upper_margin + fb_info->var.vsync_len +
+                fb_info->var.lower_margin + fb_info->var.yres,
+                host->base + LCDC_VDCTRL1);
+
+        /* line length in units of clocks or pixels */
+        writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) |
+                VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin +
+                fb_info->var.hsync_len + fb_info->var.right_margin +
+                fb_info->var.xres),
+                host->base + LCDC_VDCTRL2);
+
+        writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin +
+                fb_info->var.hsync_len) |
+                SET_VERT_WAIT_CNT(fb_info->var.upper_margin +
+                        fb_info->var.vsync_len),
+                host->base + LCDC_VDCTRL3);
+
+        vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres);
+        if (mxsfb_is_v4(host))
+                vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay);
+        writel(vdctrl4, host->base + LCDC_VDCTRL4);
+
+        writel(fb_info->fix.smem_start +
+                        fb_info->fix.line_length * fb_info->var.yoffset,
+                        host->base + host->devdata->next_buf);
+
+        if (reenable)
+                mxsfb_enable_controller(fb_info);
+
+        return 0;
+}
+
+static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+                u_int transp, struct fb_info *fb_info)
+{
+        unsigned int val;
+        int ret = -EINVAL;
+
+        /*
+         * If greyscale is true, then we convert the RGB value
+         * to greyscale no matter what visual we are using.
+         */
+        if (fb_info->var.grayscale)
+                red = green = blue = (19595 * red + 38470 * green +
+                                        7471 * blue) >> 16;
+
+        switch (fb_info->fix.visual) {
+        case FB_VISUAL_TRUECOLOR:
+                /*
+                 * 12 or 16-bit True Colour.  We encode the RGB value
+                 * according to the RGB bitfield information.
+                 */
+                if (regno < 16) {
+                        u32 *pal = fb_info->pseudo_palette;
+
+                        val  = chan_to_field(red, &fb_info->var.red);
+                        val |= chan_to_field(green, &fb_info->var.green);
+                        val |= chan_to_field(blue, &fb_info->var.blue);
+
+                        pal[regno] = val;
+                        ret = 0;
+                }
+                break;
+
+        case FB_VISUAL_STATIC_PSEUDOCOLOR:
+        case FB_VISUAL_PSEUDOCOLOR:
+                break;
+        }
+
+        return ret;
+}
+
+static int mxsfb_blank(int blank, struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+
+        switch (blank) {
+        case FB_BLANK_POWERDOWN:
+        case FB_BLANK_VSYNC_SUSPEND:
+        case FB_BLANK_HSYNC_SUSPEND:
+        case FB_BLANK_NORMAL:
+                if (host->enabled)
+                        mxsfb_disable_controller(fb_info);
+                break;
+
+        case FB_BLANK_UNBLANK:
+                if (!host->enabled)
+                        mxsfb_enable_controller(fb_info);
+                break;
+        }
+        return 0;
+}
+
+static int mxsfb_pan_display(struct fb_var_screeninfo *var,
+                struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        unsigned offset;
+
+        if (var->xoffset != 0)
+                return -EINVAL;
+
+        offset = fb_info->fix.line_length * var->yoffset;
+
+        /* update on next VSYNC */
+        writel(fb_info->fix.smem_start + offset,
+                        host->base + host->devdata->next_buf);
+
+        return 0;
+}
+
+static struct fb_ops mxsfb_ops = {
+        .owner = THIS_MODULE,
+        .fb_check_var = mxsfb_check_var,
+        .fb_set_par = mxsfb_set_par,
+        .fb_setcolreg = mxsfb_setcolreg,
+        .fb_blank = mxsfb_blank,
+        .fb_pan_display = mxsfb_pan_display,
+        .fb_fillrect = cfb_fillrect,
+        .fb_copyarea = cfb_copyarea,
+        .fb_imageblit = cfb_imageblit,
+};
+
+static int __devinit mxsfb_restore_mode(struct mxsfb_info *host)
+{
+        struct fb_info *fb_info = &host->fb_info;
+        unsigned line_count;
+        unsigned period;
+        unsigned long pa, fbsize;
+        int bits_per_pixel, ofs;
+        u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
+        struct fb_videomode vmode;
+
+        /* Only restore the mode when the controller is running */
+        ctrl = readl(host->base + LCDC_CTRL);
+        if (!(ctrl & CTRL_RUN))
+                return -EINVAL;
+
+        vdctrl0 = readl(host->base + LCDC_VDCTRL0);
+        vdctrl2 = readl(host->base + LCDC_VDCTRL2);
+        vdctrl3 = readl(host->base + LCDC_VDCTRL3);
+        vdctrl4 = readl(host->base + LCDC_VDCTRL4);
+
+        transfer_count = readl(host->base + host->devdata->transfer_count);
+
+        vmode.xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count);
+        vmode.yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count);
+
+        switch (CTRL_GET_WORD_LENGTH(ctrl)) {
+        case 0:
+                bits_per_pixel = 16;
+                break;
+        case 3:
+                bits_per_pixel = 32;
+        case 1:
+        default:
+                return -EINVAL;
+        }
+
+        fb_info->var.bits_per_pixel = bits_per_pixel;
+
+        vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U);
+        vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2);
+        vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len;
+        vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len -
+                vmode.left_margin - vmode.xres;
+        vmode.vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0);
+        period = readl(host->base + LCDC_VDCTRL1);
+        vmode.upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode.vsync_len;
+        vmode.lower_margin = period - vmode.vsync_len - vmode.upper_margin - vmode.yres;
+
+        vmode.vmode = FB_VMODE_NONINTERLACED;
+
+        vmode.sync = 0;
+        if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH)
+                vmode.sync |= FB_SYNC_HOR_HIGH_ACT;
+        if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH)
+                vmode.sync |= FB_SYNC_VERT_HIGH_ACT;
+
+        pr_debug("Reconstructed video mode:\n");
+        pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n",
+                        vmode.xres, vmode.yres,
+                        vmode.hsync_len, vmode.left_margin, vmode.right_margin,
+                        vmode.vsync_len, vmode.upper_margin, vmode.lower_margin);
+        pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode.pixclock));
+
+        fb_add_videomode(&vmode, &fb_info->modelist);
+
+        host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl);
+        host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4);
+
+        fb_info->fix.line_length = vmode.xres * (bits_per_pixel >> 3);
+
+        pa = readl(host->base + host->devdata->cur_buf);
+        fbsize = fb_info->fix.line_length * vmode.yres;
+        if (pa < fb_info->fix.smem_start)
+                return -EINVAL;
+        if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len)
+                return -EINVAL;
+        ofs = pa - fb_info->fix.smem_start;
+        if (ofs) {
+                memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize);
+                writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf);
+        }
+
+        line_count = fb_info->fix.smem_len / fb_info->fix.line_length;
+        fb_info->fix.ypanstep = 1;
+
+        clk_enable(host->clk);
+        host->enabled = 1;
+
+        return 0;
+}
+
+static int __devinit mxsfb_init_fbinfo(struct mxsfb_info *host)
+{
+        struct fb_info *fb_info = &host->fb_info;
+        struct fb_var_screeninfo *var = &fb_info->var;
+        struct mxsfb_platform_data *pdata = host->pdev->dev.platform_data;
+        dma_addr_t fb_phys;
+        void *fb_virt;
+        unsigned fb_size = pdata->fb_size;
+
+        fb_info->fbops = &mxsfb_ops;
+        fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
+        strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id));
+        fb_info->fix.type = FB_TYPE_PACKED_PIXELS;
+        fb_info->fix.ypanstep = 1;
+        fb_info->fix.visual = FB_VISUAL_TRUECOLOR,
+        fb_info->fix.accel = FB_ACCEL_NONE;
+
+        var->bits_per_pixel = pdata->default_bpp ? pdata->default_bpp : 16;
+        var->nonstd = 0;
+        var->activate = FB_ACTIVATE_NOW;
+        var->accel_flags = 0;
+        var->vmode = FB_VMODE_NONINTERLACED;
+
+        host->dotclk_delay = pdata->dotclk_delay;
+        host->ld_intf_width = pdata->ld_intf_width;
+
+        /* Memory allocation for framebuffer */
+        if (pdata->fb_phys) {
+                if (!fb_size)
+                        return -EINVAL;
+
+                fb_phys = pdata->fb_phys;
+
+                if (!request_mem_region(fb_phys, fb_size, host->pdev->name))
+                        return -ENOMEM;
+
+                fb_virt = ioremap(fb_phys, fb_size);
+                if (!fb_virt) {
+                        release_mem_region(fb_phys, fb_size);
+                        return -ENOMEM;
+                }
+                host->mapped = 1;
+        } else {
+                if (!fb_size)
+                        fb_size = SZ_2M; /* default */
+                fb_virt = alloc_pages_exact(fb_size, GFP_DMA);
+                if (!fb_virt)
+                        return -ENOMEM;
+
+                fb_phys = virt_to_phys(fb_virt);
+        }
+
+        fb_info->fix.smem_start = fb_phys;
+        fb_info->screen_base = fb_virt;
+        fb_info->screen_size = fb_info->fix.smem_len = fb_size;
+
+        if (mxsfb_restore_mode(host))
+                memset(fb_virt, 0, fb_size);
+
+        return 0;
+}
+
+static void __devexit mxsfb_free_videomem(struct mxsfb_info *host)
+{
+        struct fb_info *fb_info = &host->fb_info;
+
+        if (host->mapped) {
+                iounmap(fb_info->screen_base);
+                release_mem_region(fb_info->fix.smem_start,
+                                fb_info->screen_size);
+        } else {
+                free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len);
+        }
+}
+
+static int __devinit mxsfb_probe(struct platform_device *pdev)
+{
+        struct mxsfb_platform_data *pdata = pdev->dev.platform_data;
+        struct resource *res;
+        struct mxsfb_info *host;
+        struct fb_info *fb_info;
+        struct fb_modelist *modelist;
+        int i, ret;
+
+        if (!pdata) {
+                dev_err(&pdev->dev, "No platformdata. Giving up\n");
+                return -ENODEV;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "Cannot get memory IO resource\n");
+                return -ENODEV;
+        }
+
+        if (!request_mem_region(res->start, resource_size(res), pdev->name))
+                return -EBUSY;
+
+        fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev);
+        if (!fb_info) {
+                dev_err(&pdev->dev, "Failed to allocate fbdev\n");
+                ret = -ENOMEM;
+                goto error_alloc_info;
+        }
+
+        host = to_imxfb_host(fb_info);
+
+        host->base = ioremap(res->start, resource_size(res));
+        if (!host->base) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto error_ioremap;
+        }
+
+        host->pdev = pdev;
+        platform_set_drvdata(pdev, host);
+
+        host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data];
+
+        host->clk = clk_get(&host->pdev->dev, NULL);
+        if (IS_ERR(host->clk)) {
+                ret = PTR_ERR(host->clk);
+                goto error_getclock;
+        }
+
+        fb_info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
+        if (!fb_info->pseudo_palette) {
+                ret = -ENOMEM;
+                goto error_pseudo_pallette;
+        }
+
+        INIT_LIST_HEAD(&fb_info->modelist);
+
+        ret = mxsfb_init_fbinfo(host);
+        if (ret != 0)
+                goto error_init_fb;
+
+        for (i = 0; i < pdata->mode_count; i++)
+                fb_add_videomode(&pdata->mode_list[i], &fb_info->modelist);
+
+        modelist = list_first_entry(&fb_info->modelist,
+                        struct fb_modelist, list);
+        fb_videomode_to_var(&fb_info->var, &modelist->mode);
+
+        /* init the color fields */
+        mxsfb_check_var(&fb_info->var, fb_info);
+
+        platform_set_drvdata(pdev, fb_info);
+
+        ret = register_framebuffer(fb_info);
+        if (ret != 0) {
+                dev_err(&pdev->dev,"Failed to register framebuffer\n");
+                goto error_register;
+        }
+
+        if (!host->enabled) {
+                writel(0, host->base + LCDC_CTRL);
+                mxsfb_set_par(fb_info);
+                mxsfb_enable_controller(fb_info);
+        }
+
+        dev_info(&pdev->dev, "initialized\n");
+
+        return 0;
+
+error_register:
+        if (host->enabled)
+                clk_disable(host->clk);
+        fb_destroy_modelist(&fb_info->modelist);
+error_init_fb:
+        kfree(fb_info->pseudo_palette);
+error_pseudo_pallette:
+        clk_put(host->clk);
+error_getclock:
+        iounmap(host->base);
+error_ioremap:
+        framebuffer_release(fb_info);
+error_alloc_info:
+        release_mem_region(res->start, resource_size(res));
+
+        return ret;
+}
+
+static int __devexit mxsfb_remove(struct platform_device *pdev)
+{
+        struct fb_info *fb_info = platform_get_drvdata(pdev);
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+        if (host->enabled)
+                mxsfb_disable_controller(fb_info);
+
+        unregister_framebuffer(fb_info);
+        kfree(fb_info->pseudo_palette);
+        mxsfb_free_videomem(host);
+        iounmap(host->base);
+        clk_put(host->clk);
+
+        framebuffer_release(fb_info);
+        release_mem_region(res->start, resource_size(res));
+
+        platform_set_drvdata(pdev, NULL);
+
+        return 0;
+}
+
+static struct platform_device_id mxsfb_devtype[] = {
+        {
+                .name = "imx23-fb",
+                .driver_data = MXSFB_V3,
+        }, {
+                .name = "imx28-fb",
+                .driver_data = MXSFB_V4,
+        }, {
+                /* sentinel */
+        }
+};
+MODULE_DEVICE_TABLE(platform, mxsfb_devtype);
+
+static struct platform_driver mxsfb_driver = {
+        .probe = mxsfb_probe,
+        .remove = __devexit_p(mxsfb_remove),
+        .id_table = mxsfb_devtype,
+        .driver = {
+                   .name = DRIVER_NAME,
+        },
+};
+
+static int __init mxsfb_init(void)
+{
+        return platform_driver_register(&mxsfb_driver);
+}
+
+static void __exit mxsfb_exit(void)
+{
+        platform_driver_unregister(&mxsfb_driver);
+}
+
+module_init(mxsfb_init);
+module_exit(mxsfb_exit);
+
+MODULE_DESCRIPTION("Freescale mxs framebuffer driver");
+MODULE_AUTHOR("Sascha Hauer, Pengutronix");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/nvidia/nv_backlight.c b/drivers/video/nvidia/nv_backlight.c
index 6aac6d1b937b..8471008aa6ff 100644
--- a/drivers/video/nvidia/nv_backlight.c
+++ b/drivers/video/nvidia/nv_backlight.c
@@ -111,6 +111,7 @@ void nvidia_bl_init(struct nvidia_par *par)
         snprintf(name, sizeof(name), "nvidiabl%d", info->node);
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
         bd = backlight_device_register(name, info->dev, par, &nvidia_bl_ops,
                                        &props);
diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig
index 083c8fe53e24..15e7f1912af9 100644
--- a/drivers/video/omap/Kconfig
+++ b/drivers/video/omap/Kconfig
@@ -5,13 +5,18 @@ config FB_OMAP
         select FB_CFB_FILLRECT
         select FB_CFB_COPYAREA
         select FB_CFB_IMAGEBLIT
+        select TWL4030_CORE if MACH_OMAP_2430SDP
         help
           Frame buffer driver for OMAP based boards.
 
 config FB_OMAP_LCD_VGA
         bool "Use LCD in VGA mode"
                 depends on MACH_OMAP_3430SDP || MACH_OMAP_LDP
-
+                help
+                  Set LCD resolution as VGA (640 X 480).
+                  Default resolution without this option is QVGA(320 X 240).
+                  Please take a look at drivers/video/omap/lcd_ldp.c file
+                  for lcd driver code.
 choice
         depends on FB_OMAP && MACH_OVERO
         prompt "Screen resolution"
diff --git a/drivers/video/omap/blizzard.c b/drivers/video/omap/blizzard.c
index 87785c215a52..c0504a8a5079 100644
--- a/drivers/video/omap/blizzard.c
+++ b/drivers/video/omap/blizzard.c
@@ -397,8 +397,7 @@ static inline void free_req(struct blizzard_request *req)
 
         spin_lock_irqsave(&blizzard.req_lock, flags);
 
-        list_del(&req->entry);
-        list_add(&req->entry, &blizzard.free_req_list);
+        list_move(&req->entry, &blizzard.free_req_list);
         if (!(req->flags & REQ_FROM_IRQ_POOL))
                 up(&blizzard.req_sema);
 
diff --git a/drivers/video/omap/hwa742.c b/drivers/video/omap/hwa742.c
index 0016f77cd13f..084aa0ac562b 100644
--- a/drivers/video/omap/hwa742.c
+++ b/drivers/video/omap/hwa742.c
@@ -269,8 +269,7 @@ static inline void free_req(struct hwa742_request *req)
 
         spin_lock_irqsave(&hwa742.req_lock, flags);
 
-        list_del(&req->entry);
-        list_add(&req->entry, &hwa742.free_req_list);
+        list_move(&req->entry, &hwa742.free_req_list);
         if (!(req->flags & REQ_FROM_IRQ_POOL))
                 up(&hwa742.req_sema);
 
diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig
index 940cab394c2e..d18ad6b2372a 100644
--- a/drivers/video/omap2/displays/Kconfig
+++ b/drivers/video/omap2/displays/Kconfig
@@ -9,6 +9,12 @@ config PANEL_GENERIC_DPI
           Supports LCD Panel used in TI SDP3430 and EVM boards,
           OMAP3517 EVM boards and CM-T35.
 
+config PANEL_LGPHILIPS_LB035Q02
+        tristate "LG.Philips LB035Q02 LCD Panel"
+        depends on OMAP2_DSS && SPI
+        help
+          LCD Panel used on the Gumstix Overo Palo35
+
 config PANEL_SHARP_LS037V7DW01
         tristate "Sharp LS037V7DW01 LCD Panel"
         depends on OMAP2_DSS
diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile
index 861f0255ec6b..0f601ab3abf4 100644
--- a/drivers/video/omap2/displays/Makefile
+++ b/drivers/video/omap2/displays/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_PANEL_GENERIC_DPI) += panel-generic-dpi.o
+obj-$(CONFIG_PANEL_LGPHILIPS_LB035Q02) += panel-lgphilips-lb035q02.o
 obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
 obj-$(CONFIG_PANEL_NEC_NL8048HL11_01B) += panel-nec-nl8048hl11-01b.o
 
diff --git a/drivers/video/omap2/displays/panel-acx565akm.c b/drivers/video/omap2/displays/panel-acx565akm.c
index e77310653207..7e04c921aa2a 100644
--- a/drivers/video/omap2/displays/panel-acx565akm.c
+++ b/drivers/video/omap2/displays/panel-acx565akm.c
@@ -534,6 +534,7 @@ static int acx_panel_probe(struct omap_dss_device *dssdev)
 
         props.fb_blank = FB_BLANK_UNBLANK;
         props.power = FB_BLANK_UNBLANK;
+        props.type = BACKLIGHT_RAW;
 
         bldev = backlight_device_register("acx565akm", &md->spi->dev,
                         md, &acx565akm_bl_ops, &props);
diff --git a/drivers/video/omap2/displays/panel-generic-dpi.c b/drivers/video/omap2/displays/panel-generic-dpi.c
index 07eb30ee59c8..4a9b9ff59467 100644
--- a/drivers/video/omap2/displays/panel-generic-dpi.c
+++ b/drivers/video/omap2/displays/panel-generic-dpi.c
@@ -156,6 +156,31 @@ static struct panel_config generic_dpi_panels[] = {
                 .power_off_delay        = 0,
                 .name                   = "toppoly_tdo35s",
         },
+
+        /* Samsung LTE430WQ-F0C */
+        {
+                {
+                        .x_res          = 480,
+                        .y_res          = 272,
+
+                        .pixel_clock    = 9200,
+
+                        .hfp            = 8,
+                        .hsw            = 41,
+                        .hbp            = 45 - 41,
+
+                        .vfp            = 4,
+                        .vsw            = 10,
+                        .vbp            = 12 - 10,
+                },
+                .acbi                   = 0x0,
+                .acb                    = 0x0,
+                .config                 = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
+                                                OMAP_DSS_LCD_IHS,
+                .power_on_delay         = 0,
+                .power_off_delay        = 0,
+                .name                   = "samsung_lte430wq_f0c",
+        },
 };
 
 struct panel_drv_data {
diff --git a/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c b/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c
new file mode 100644
index 000000000000..271324db2436
--- /dev/null
+++ b/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c
@@ -0,0 +1,279 @@
+/*
+ * LCD panel driver for LG.Philips LB035Q02
+ *
+ * Author: Steve Sakoman <steve@sakoman.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/spi/spi.h>
+#include <linux/mutex.h>
+
+#include <plat/display.h>
+
+struct lb035q02_data {
+        struct mutex lock;
+};
+
+static struct omap_video_timings lb035q02_timings = {
+        .x_res = 320,
+        .y_res = 240,
+
+        .pixel_clock    = 6500,
+
+        .hsw            = 2,
+        .hfp            = 20,
+        .hbp            = 68,
+
+        .vsw            = 2,
+        .vfp            = 4,
+        .vbp            = 18,
+};
+
+static int lb035q02_panel_power_on(struct omap_dss_device *dssdev)
+{
+        int r;
+
+        if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
+                return 0;
+
+        r = omapdss_dpi_display_enable(dssdev);
+        if (r)
+                goto err0;
+
+        if (dssdev->platform_enable) {
+                r = dssdev->platform_enable(dssdev);
+                if (r)
+                        goto err1;
+        }
+
+        return 0;
+err1:
+        omapdss_dpi_display_disable(dssdev);
+err0:
+        return r;
+}
+
+static void lb035q02_panel_power_off(struct omap_dss_device *dssdev)
+{
+        if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
+                return;
+
+        if (dssdev->platform_disable)
+                dssdev->platform_disable(dssdev);
+
+        omapdss_dpi_display_disable(dssdev);
+}
+
+static int lb035q02_panel_probe(struct omap_dss_device *dssdev)
+{
+        struct lb035q02_data *ld;
+        int r;
+
+        dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
+                OMAP_DSS_LCD_IHS;
+        dssdev->panel.timings = lb035q02_timings;
+
+        ld = kzalloc(sizeof(*ld), GFP_KERNEL);
+        if (!ld) {
+                r = -ENOMEM;
+                goto err;
+        }
+        mutex_init(&ld->lock);
+        dev_set_drvdata(&dssdev->dev, ld);
+        return 0;
+err:
+        return r;
+}
+
+static void lb035q02_panel_remove(struct omap_dss_device *dssdev)
+{
+        struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev);
+
+        kfree(ld);
+}
+
+static int lb035q02_panel_enable(struct omap_dss_device *dssdev)
+{
+        struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev);
+        int r;
+
+        mutex_lock(&ld->lock);
+
+        r = lb035q02_panel_power_on(dssdev);
+        if (r)
+                goto err;
+        dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+
+        mutex_unlock(&ld->lock);
+        return 0;
+err:
+        mutex_unlock(&ld->lock);
+        return r;
+}
+
+static void lb035q02_panel_disable(struct omap_dss_device *dssdev)
+{
+        struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev);
+
+        mutex_lock(&ld->lock);
+
+        lb035q02_panel_power_off(dssdev);
+        dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
+
+        mutex_unlock(&ld->lock);
+}
+
+static int lb035q02_panel_suspend(struct omap_dss_device *dssdev)
+{
+        struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev);
+
+        mutex_lock(&ld->lock);
+
+        lb035q02_panel_power_off(dssdev);
+        dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
+
+        mutex_unlock(&ld->lock);
+        return 0;
+}
+
+static int lb035q02_panel_resume(struct omap_dss_device *dssdev)
+{
+        struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev);
+        int r;
+
+        mutex_lock(&ld->lock);
+
+        r = lb035q02_panel_power_on(dssdev);
+        if (r)
+                goto err;
+        dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+
+        mutex_unlock(&ld->lock);
+        return 0;
+err:
+        mutex_unlock(&ld->lock);
+        return r;
+}
+
+static struct omap_dss_driver lb035q02_driver = {
+        .probe          = lb035q02_panel_probe,
+        .remove         = lb035q02_panel_remove,
+
+        .enable         = lb035q02_panel_enable,
+        .disable        = lb035q02_panel_disable,
+        .suspend        = lb035q02_panel_suspend,
+        .resume         = lb035q02_panel_resume,
+
+        .driver         = {
+                .name   = "lgphilips_lb035q02_panel",
+                .owner  = THIS_MODULE,
+        },
+};
+
+static int lb035q02_write_reg(struct spi_device *spi, u8 reg, u16 val)
+{
+        struct spi_message msg;
+        struct spi_transfer index_xfer = {
+                .len            = 3,
+                .cs_change      = 1,
+        };
+        struct spi_transfer value_xfer = {
+                .len            = 3,
+        };
+        u8      buffer[16];
+
+        spi_message_init(&msg);
+
+        /* register index */
+        buffer[0] = 0x70;
+        buffer[1] = 0x00;
+        buffer[2] = reg & 0x7f;
+        index_xfer.tx_buf = buffer;
+        spi_message_add_tail(&index_xfer, &msg);
+
+        /* register value */
+        buffer[4] = 0x72;
+        buffer[5] = val >> 8;
+        buffer[6] = val;
+        value_xfer.tx_buf = buffer + 4;
+        spi_message_add_tail(&value_xfer, &msg);
+
+        return spi_sync(spi, &msg);
+}
+
+static void init_lb035q02_panel(struct spi_device *spi)
+{
+        /* Init sequence from page 28 of the lb035q02 spec */
+        lb035q02_write_reg(spi, 0x01, 0x6300);
+        lb035q02_write_reg(spi, 0x02, 0x0200);
+        lb035q02_write_reg(spi, 0x03, 0x0177);
+        lb035q02_write_reg(spi, 0x04, 0x04c7);
+        lb035q02_write_reg(spi, 0x05, 0xffc0);
+        lb035q02_write_reg(spi, 0x06, 0xe806);
+        lb035q02_write_reg(spi, 0x0a, 0x4008);
+        lb035q02_write_reg(spi, 0x0b, 0x0000);
+        lb035q02_write_reg(spi, 0x0d, 0x0030);
+        lb035q02_write_reg(spi, 0x0e, 0x2800);
+        lb035q02_write_reg(spi, 0x0f, 0x0000);
+        lb035q02_write_reg(spi, 0x16, 0x9f80);
+        lb035q02_write_reg(spi, 0x17, 0x0a0f);
+        lb035q02_write_reg(spi, 0x1e, 0x00c1);
+        lb035q02_write_reg(spi, 0x30, 0x0300);
+        lb035q02_write_reg(spi, 0x31, 0x0007);
+        lb035q02_write_reg(spi, 0x32, 0x0000);
+        lb035q02_write_reg(spi, 0x33, 0x0000);
+        lb035q02_write_reg(spi, 0x34, 0x0707);
+        lb035q02_write_reg(spi, 0x35, 0x0004);
+        lb035q02_write_reg(spi, 0x36, 0x0302);
+        lb035q02_write_reg(spi, 0x37, 0x0202);
+        lb035q02_write_reg(spi, 0x3a, 0x0a0d);
+        lb035q02_write_reg(spi, 0x3b, 0x0806);
+}
+
+static int __devinit lb035q02_panel_spi_probe(struct spi_device *spi)
+{
+        init_lb035q02_panel(spi);
+        return omap_dss_register_driver(&lb035q02_driver);
+}
+
+static int __devexit lb035q02_panel_spi_remove(struct spi_device *spi)
+{
+        omap_dss_unregister_driver(&lb035q02_driver);
+        return 0;
+}
+
+static struct spi_driver lb035q02_spi_driver = {
+        .driver         = {
+                .name   = "lgphilips_lb035q02_panel-spi",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = lb035q02_panel_spi_probe,
+        .remove         = __devexit_p(lb035q02_panel_spi_remove),
+};
+
+static int __init lb035q02_panel_drv_init(void)
+{
+        return spi_register_driver(&lb035q02_spi_driver);
+}
+
+static void __exit lb035q02_panel_drv_exit(void)
+{
+        spi_unregister_driver(&lb035q02_spi_driver);
+}
+
+module_init(lb035q02_panel_drv_init);
+module_exit(lb035q02_panel_drv_exit);
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
index 9a138f650e05..d2b35d2df2a6 100644
--- a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
+++ b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
@@ -99,6 +99,7 @@ static int sharp_ls_panel_probe(struct omap_dss_device *dssdev)
 
         memset(&props, 0, sizeof(struct backlight_properties));
         props.max_brightness = dssdev->max_backlight_level;
+        props.type = BACKLIGHT_RAW;
 
         bl = backlight_device_register("sharp-ls", &dssdev->dev, dssdev,
                         &sharp_ls_bl_ops, &props);
diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c
index 61026f96ad20..adc9900458e1 100644
--- a/drivers/video/omap2/displays/panel-taal.c
+++ b/drivers/video/omap2/displays/panel-taal.c
@@ -218,6 +218,8 @@ struct taal_data {
                 u16 w;
                 u16 h;
         } update_region;
+        int channel;
+
         struct delayed_work te_timeout_work;
 
         bool use_dsi_bl;
@@ -257,12 +259,12 @@ static void hw_guard_wait(struct taal_data *td)
         }
 }
 
-static int taal_dcs_read_1(u8 dcs_cmd, u8 *data)
+static int taal_dcs_read_1(struct taal_data *td, u8 dcs_cmd, u8 *data)
 {
         int r;
         u8 buf[1];
 
-        r = dsi_vc_dcs_read(TCH, dcs_cmd, buf, 1);
+        r = dsi_vc_dcs_read(td->channel, dcs_cmd, buf, 1);
 
         if (r < 0)
                 return r;
@@ -272,17 +274,17 @@ static int taal_dcs_read_1(u8 dcs_cmd, u8 *data)
         return 0;
 }
 
-static int taal_dcs_write_0(u8 dcs_cmd)
+static int taal_dcs_write_0(struct taal_data *td, u8 dcs_cmd)
 {
-        return dsi_vc_dcs_write(TCH, &dcs_cmd, 1);
+        return dsi_vc_dcs_write(td->channel, &dcs_cmd, 1);
 }
 
-static int taal_dcs_write_1(u8 dcs_cmd, u8 param)
+static int taal_dcs_write_1(struct taal_data *td, u8 dcs_cmd, u8 param)
 {
         u8 buf[2];
         buf[0] = dcs_cmd;
         buf[1] = param;
-        return dsi_vc_dcs_write(TCH, buf, 2);
+        return dsi_vc_dcs_write(td->channel, buf, 2);
 }
 
 static int taal_sleep_in(struct taal_data *td)
@@ -294,7 +296,7 @@ static int taal_sleep_in(struct taal_data *td)
         hw_guard_wait(td);
 
         cmd = DCS_SLEEP_IN;
-        r = dsi_vc_dcs_write_nosync(TCH, &cmd, 1);
+        r = dsi_vc_dcs_write_nosync(td->channel, &cmd, 1);
         if (r)
                 return r;
 
@@ -312,7 +314,7 @@ static int taal_sleep_out(struct taal_data *td)
 
         hw_guard_wait(td);
 
-        r = taal_dcs_write_0(DCS_SLEEP_OUT);
+        r = taal_dcs_write_0(td, DCS_SLEEP_OUT);
         if (r)
                 return r;
 
@@ -324,30 +326,30 @@ static int taal_sleep_out(struct taal_data *td)
         return 0;
 }
 
-static int taal_get_id(u8 *id1, u8 *id2, u8 *id3)
+static int taal_get_id(struct taal_data *td, u8 *id1, u8 *id2, u8 *id3)
 {
         int r;
 
-        r = taal_dcs_read_1(DCS_GET_ID1, id1);
+        r = taal_dcs_read_1(td, DCS_GET_ID1, id1);
         if (r)
                 return r;
-        r = taal_dcs_read_1(DCS_GET_ID2, id2);
+        r = taal_dcs_read_1(td, DCS_GET_ID2, id2);
         if (r)
                 return r;
-        r = taal_dcs_read_1(DCS_GET_ID3, id3);
+        r = taal_dcs_read_1(td, DCS_GET_ID3, id3);
         if (r)
                 return r;
 
         return 0;
 }
 
-static int taal_set_addr_mode(u8 rotate, bool mirror)
+static int taal_set_addr_mode(struct taal_data *td, u8 rotate, bool mirror)
 {
         int r;
         u8 mode;
         int b5, b6, b7;
 
-        r = taal_dcs_read_1(DCS_READ_MADCTL, &mode);
+        r = taal_dcs_read_1(td, DCS_READ_MADCTL, &mode);
         if (r)
                 return r;
 
@@ -381,10 +383,11 @@ static int taal_set_addr_mode(u8 rotate, bool mirror)
         mode &= ~((1<<7) | (1<<6) | (1<<5));
         mode |= (b7 << 7) | (b6 << 6) | (b5 << 5);
 
-        return taal_dcs_write_1(DCS_MEM_ACC_CTRL, mode);
+        return taal_dcs_write_1(td, DCS_MEM_ACC_CTRL, mode);
 }
 
-static int taal_set_update_window(u16 x, u16 y, u16 w, u16 h)
+static int taal_set_update_window(struct taal_data *td,
+                u16 x, u16 y, u16 w, u16 h)
 {
         int r;
         u16 x1 = x;
@@ -399,7 +402,7 @@ static int taal_set_update_window(u16 x, u16 y, u16 w, u16 h)
         buf[3] = (x2 >> 8) & 0xff;
         buf[4] = (x2 >> 0) & 0xff;
 
-        r = dsi_vc_dcs_write_nosync(TCH, buf, sizeof(buf));
+        r = dsi_vc_dcs_write_nosync(td->channel, buf, sizeof(buf));
         if (r)
                 return r;
 
@@ -409,11 +412,11 @@ static int taal_set_update_window(u16 x, u16 y, u16 w, u16 h)
         buf[3] = (y2 >> 8) & 0xff;
         buf[4] = (y2 >> 0) & 0xff;
 
-        r = dsi_vc_dcs_write_nosync(TCH, buf, sizeof(buf));
+        r = dsi_vc_dcs_write_nosync(td->channel, buf, sizeof(buf));
         if (r)
                 return r;
 
-        dsi_vc_send_bta_sync(TCH);
+        dsi_vc_send_bta_sync(td->channel);
 
         return r;
 }
@@ -439,7 +442,7 @@ static int taal_bl_update_status(struct backlight_device *dev)
         if (td->use_dsi_bl) {
                 if (td->enabled) {
                         dsi_bus_lock();
-                        r = taal_dcs_write_1(DCS_BRIGHTNESS, level);
+                        r = taal_dcs_write_1(td, DCS_BRIGHTNESS, level);
                         dsi_bus_unlock();
                 } else {
                         r = 0;
@@ -502,7 +505,7 @@ static ssize_t taal_num_errors_show(struct device *dev,
 
         if (td->enabled) {
                 dsi_bus_lock();
-                r = taal_dcs_read_1(DCS_READ_NUM_ERRORS, &errors);
+                r = taal_dcs_read_1(td, DCS_READ_NUM_ERRORS, &errors);
                 dsi_bus_unlock();
         } else {
                 r = -ENODEV;
@@ -528,7 +531,7 @@ static ssize_t taal_hw_revision_show(struct device *dev,
 
         if (td->enabled) {
                 dsi_bus_lock();
-                r = taal_get_id(&id1, &id2, &id3);
+                r = taal_get_id(td, &id1, &id2, &id3);
                 dsi_bus_unlock();
         } else {
                 r = -ENODEV;
@@ -590,7 +593,7 @@ static ssize_t store_cabc_mode(struct device *dev,
         if (td->enabled) {
                 dsi_bus_lock();
                 if (!td->cabc_broken)
-                        taal_dcs_write_1(DCS_WRITE_CABC, i);
+                        taal_dcs_write_1(td, DCS_WRITE_CABC, i);
                 dsi_bus_unlock();
         }
 
@@ -729,6 +732,8 @@ static int taal_probe(struct omap_dss_device *dssdev)
                 props.max_brightness = 255;
         else
                 props.max_brightness = 127;
+
+        props.type = BACKLIGHT_RAW;
         bldev = backlight_device_register("taal", &dssdev->dev, dssdev,
                                           &taal_bl_ops, &props);
         if (IS_ERR(bldev)) {
@@ -774,14 +779,29 @@ static int taal_probe(struct omap_dss_device *dssdev)
                 dev_dbg(&dssdev->dev, "Using GPIO TE\n");
         }
 
+        r = omap_dsi_request_vc(dssdev, &td->channel);
+        if (r) {
+                dev_err(&dssdev->dev, "failed to get virtual channel\n");
+                goto err_req_vc;
+        }
+
+        r = omap_dsi_set_vc_id(dssdev, td->channel, TCH);
+        if (r) {
+                dev_err(&dssdev->dev, "failed to set VC_ID\n");
+                goto err_vc_id;
+        }
+
         r = sysfs_create_group(&dssdev->dev.kobj, &taal_attr_group);
         if (r) {
                 dev_err(&dssdev->dev, "failed to create sysfs files\n");
-                goto err_sysfs;
+                goto err_vc_id;
         }
 
         return 0;
-err_sysfs:
+
+err_vc_id:
+        omap_dsi_release_vc(dssdev, td->channel);
+err_req_vc:
         if (panel_data->use_ext_te)
                 free_irq(gpio_to_irq(panel_data->ext_te_gpio), dssdev);
 err_irq:
@@ -808,6 +828,7 @@ static void taal_remove(struct omap_dss_device *dssdev)
         dev_dbg(&dssdev->dev, "remove\n");
 
         sysfs_remove_group(&dssdev->dev.kobj, &taal_attr_group);
+        omap_dsi_release_vc(dssdev, td->channel);
 
         if (panel_data->use_ext_te) {
                 int gpio = panel_data->ext_te_gpio;
@@ -846,13 +867,13 @@ static int taal_power_on(struct omap_dss_device *dssdev)
 
         taal_hw_reset(dssdev);
 
-        omapdss_dsi_vc_enable_hs(TCH, false);
+        omapdss_dsi_vc_enable_hs(td->channel, false);
 
         r = taal_sleep_out(td);
         if (r)
                 goto err;
 
-        r = taal_get_id(&id1, &id2, &id3);
+        r = taal_get_id(td, &id1, &id2, &id3);
         if (r)
                 goto err;
 
@@ -861,30 +882,30 @@ static int taal_power_on(struct omap_dss_device *dssdev)
                 (id2 == 0x00 || id2 == 0xff || id2 == 0x81))
                 td->cabc_broken = true;
 
-        r = taal_dcs_write_1(DCS_BRIGHTNESS, 0xff);
+        r = taal_dcs_write_1(td, DCS_BRIGHTNESS, 0xff);
         if (r)
                 goto err;
 
-        r = taal_dcs_write_1(DCS_CTRL_DISPLAY,
+        r = taal_dcs_write_1(td, DCS_CTRL_DISPLAY,
                         (1<<2) | (1<<5));       /* BL | BCTRL */
         if (r)
                 goto err;
 
-        r = taal_dcs_write_1(DCS_PIXEL_FORMAT, 0x7); /* 24bit/pixel */
+        r = taal_dcs_write_1(td, DCS_PIXEL_FORMAT, 0x7); /* 24bit/pixel */
         if (r)
                 goto err;
 
-        r = taal_set_addr_mode(td->rotate, td->mirror);
+        r = taal_set_addr_mode(td, td->rotate, td->mirror);
         if (r)
                 goto err;
 
         if (!td->cabc_broken) {
-                r = taal_dcs_write_1(DCS_WRITE_CABC, td->cabc_mode);
+                r = taal_dcs_write_1(td, DCS_WRITE_CABC, td->cabc_mode);
                 if (r)
                         goto err;
         }
 
-        r = taal_dcs_write_0(DCS_DISPLAY_ON);
+        r = taal_dcs_write_0(td, DCS_DISPLAY_ON);
         if (r)
                 goto err;
 
@@ -903,7 +924,7 @@ static int taal_power_on(struct omap_dss_device *dssdev)
                 td->intro_printed = true;
         }
 
-        omapdss_dsi_vc_enable_hs(TCH, true);
+        omapdss_dsi_vc_enable_hs(td->channel, true);
 
         return 0;
 err:
@@ -921,7 +942,7 @@ static void taal_power_off(struct omap_dss_device *dssdev)
         struct taal_data *td = dev_get_drvdata(&dssdev->dev);
         int r;
 
-        r = taal_dcs_write_0(DCS_DISPLAY_OFF);
+        r = taal_dcs_write_0(td, DCS_DISPLAY_OFF);
         if (!r) {
                 r = taal_sleep_in(td);
                 /* HACK: wait a bit so that the message goes through */
@@ -1089,7 +1110,7 @@ static irqreturn_t taal_te_isr(int irq, void *data)
         if (old) {
                 cancel_delayed_work(&td->te_timeout_work);
 
-                r = omap_dsi_update(dssdev, TCH,
+                r = omap_dsi_update(dssdev, td->channel,
                                 td->update_region.x,
                                 td->update_region.y,
                                 td->update_region.w,
@@ -1139,7 +1160,7 @@ static int taal_update(struct omap_dss_device *dssdev,
         if (r)
                 goto err;
 
-        r = taal_set_update_window(x, y, w, h);
+        r = taal_set_update_window(td, x, y, w, h);
         if (r)
                 goto err;
 
@@ -1153,7 +1174,7 @@ static int taal_update(struct omap_dss_device *dssdev,
                                 msecs_to_jiffies(250));
                 atomic_set(&td->do_update, 1);
         } else {
-                r = omap_dsi_update(dssdev, TCH, x, y, w, h,
+                r = omap_dsi_update(dssdev, td->channel, x, y, w, h,
                                 taal_framedone_cb, dssdev);
                 if (r)
                         goto err;
@@ -1191,9 +1212,9 @@ static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable)
         int r;
 
         if (enable)
-                r = taal_dcs_write_1(DCS_TEAR_ON, 0);
+                r = taal_dcs_write_1(td, DCS_TEAR_ON, 0);
         else
-                r = taal_dcs_write_0(DCS_TEAR_OFF);
+                r = taal_dcs_write_0(td, DCS_TEAR_OFF);
 
         if (!panel_data->use_ext_te)
                 omapdss_dsi_enable_te(dssdev, enable);
@@ -1263,7 +1284,7 @@ static int taal_rotate(struct omap_dss_device *dssdev, u8 rotate)
         dsi_bus_lock();
 
         if (td->enabled) {
-                r = taal_set_addr_mode(rotate, td->mirror);
+                r = taal_set_addr_mode(td, rotate, td->mirror);
                 if (r)
                         goto err;
         }
@@ -1306,7 +1327,7 @@ static int taal_mirror(struct omap_dss_device *dssdev, bool enable)
 
         dsi_bus_lock();
         if (td->enabled) {
-                r = taal_set_addr_mode(td->rotate, enable);
+                r = taal_set_addr_mode(td, td->rotate, enable);
                 if (r)
                         goto err;
         }
@@ -1350,13 +1371,13 @@ static int taal_run_test(struct omap_dss_device *dssdev, int test_num)
 
         dsi_bus_lock();
 
-        r = taal_dcs_read_1(DCS_GET_ID1, &id1);
+        r = taal_dcs_read_1(td, DCS_GET_ID1, &id1);
         if (r)
                 goto err2;
-        r = taal_dcs_read_1(DCS_GET_ID2, &id2);
+        r = taal_dcs_read_1(td, DCS_GET_ID2, &id2);
         if (r)
                 goto err2;
-        r = taal_dcs_read_1(DCS_GET_ID3, &id3);
+        r = taal_dcs_read_1(td, DCS_GET_ID3, &id3);
         if (r)
                 goto err2;
 
@@ -1404,9 +1425,9 @@ static int taal_memory_read(struct omap_dss_device *dssdev,
         else
                 plen = 2;
 
-        taal_set_update_window(x, y, w, h);
+        taal_set_update_window(td, x, y, w, h);
 
-        r = dsi_vc_set_max_rx_packet_size(TCH, plen);
+        r = dsi_vc_set_max_rx_packet_size(td->channel, plen);
         if (r)
                 goto err2;
 
@@ -1414,7 +1435,7 @@ static int taal_memory_read(struct omap_dss_device *dssdev,
                 u8 dcs_cmd = first ? 0x2e : 0x3e;
                 first = 0;
 
-                r = dsi_vc_dcs_read(TCH, dcs_cmd,
+                r = dsi_vc_dcs_read(td->channel, dcs_cmd,
                                 buf + buf_used, size - buf_used);
 
                 if (r < 0) {
@@ -1440,7 +1461,7 @@ static int taal_memory_read(struct omap_dss_device *dssdev,
         r = buf_used;
 
 err3:
-        dsi_vc_set_max_rx_packet_size(TCH, 1);
+        dsi_vc_set_max_rx_packet_size(td->channel, 1);
 err2:
         dsi_bus_unlock();
 err1:
@@ -1466,7 +1487,7 @@ static void taal_esd_work(struct work_struct *work)
 
         dsi_bus_lock();
 
-        r = taal_dcs_read_1(DCS_RDDSDR, &state1);
+        r = taal_dcs_read_1(td, DCS_RDDSDR, &state1);
         if (r) {
                 dev_err(&dssdev->dev, "failed to read Taal status\n");
                 goto err;
@@ -1479,7 +1500,7 @@ static void taal_esd_work(struct work_struct *work)
                 goto err;
         }
 
-        r = taal_dcs_read_1(DCS_RDDSDR, &state2);
+        r = taal_dcs_read_1(td, DCS_RDDSDR, &state2);
         if (r) {
                 dev_err(&dssdev->dev, "failed to read Taal status\n");
                 goto err;
@@ -1495,7 +1516,7 @@ static void taal_esd_work(struct work_struct *work)
         /* Self-diagnostics result is also shown on TE GPIO line. We need
          * to re-enable TE after self diagnostics */
         if (td->te_enabled && panel_data->use_ext_te) {
-                r = taal_dcs_write_1(DCS_TEAR_ON, 0);
+                r = taal_dcs_write_1(td, DCS_TEAR_ON, 0);
                 if (r)
                         goto err;
         }
diff --git a/drivers/video/omap2/dss/Kconfig b/drivers/video/omap2/dss/Kconfig
index 43b64403eaa4..bfc5da0e9700 100644
--- a/drivers/video/omap2/dss/Kconfig
+++ b/drivers/video/omap2/dss/Kconfig
@@ -1,8 +1,8 @@
 menuconfig OMAP2_DSS
-        tristate "OMAP2/3 Display Subsystem support (EXPERIMENTAL)"
-        depends on ARCH_OMAP2 || ARCH_OMAP3
+        tristate "OMAP2+ Display Subsystem support (EXPERIMENTAL)"
+        depends on ARCH_OMAP2PLUS
         help
-          OMAP2/3 Display Subsystem support.
+          OMAP2+ Display Subsystem support.
 
 if OMAP2_DSS
 
@@ -60,6 +60,14 @@ config OMAP2_DSS_VENC
         help
           OMAP Video Encoder support for S-Video and composite TV-out.
 
+config OMAP4_DSS_HDMI
+        bool "HDMI support"
+        depends on ARCH_OMAP4
+        default y
+        help
+          HDMI Interface. This adds the High Definition Multimedia Interface.
+          See http://www.hdmi.org/ for HDMI specification.
+
 config OMAP2_DSS_SDI
         bool "SDI support"
         depends on ARCH_OMAP3
diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile
index 7db17b5e570c..10d9d3bb3e24 100644
--- a/drivers/video/omap2/dss/Makefile
+++ b/drivers/video/omap2/dss/Makefile
@@ -5,3 +5,5 @@ omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
 omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o
 omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o
 omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
+omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi.o \
+                                    hdmi_omap4_panel.o
diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
index 8e89f6049280..1aa2ed1e786e 100644
--- a/drivers/video/omap2/dss/core.c
+++ b/drivers/video/omap2/dss/core.c
@@ -34,332 +34,26 @@
 #include <linux/regulator/consumer.h>
 
 #include <plat/display.h>
-#include <plat/clock.h>
 
 #include "dss.h"
 #include "dss_features.h"
 
 static struct {
         struct platform_device *pdev;
-        int             ctx_id;
-
-        struct clk      *dss_ick;
-        struct clk      *dss1_fck;
-        struct clk      *dss2_fck;
-        struct clk      *dss_54m_fck;
-        struct clk      *dss_96m_fck;
-        unsigned        num_clks_enabled;
 
         struct regulator *vdds_dsi_reg;
         struct regulator *vdds_sdi_reg;
-        struct regulator *vdda_dac_reg;
 } core;
 
-static void dss_clk_enable_all_no_ctx(void);
-static void dss_clk_disable_all_no_ctx(void);
-static void dss_clk_enable_no_ctx(enum dss_clock clks);
-static void dss_clk_disable_no_ctx(enum dss_clock clks);
-
 static char *def_disp_name;
 module_param_named(def_disp, def_disp_name, charp, 0);
-MODULE_PARM_DESC(def_disp_name, "default display name");
+MODULE_PARM_DESC(def_disp, "default display name");
 
 #ifdef DEBUG
 unsigned int dss_debug;
 module_param_named(debug, dss_debug, bool, 0644);
 #endif
 
-/* CONTEXT */
-static int dss_get_ctx_id(void)
-{
-        struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
-        int r;
-
-        if (!pdata->get_last_off_on_transaction_id)
-                return 0;
-        r = pdata->get_last_off_on_transaction_id(&core.pdev->dev);
-        if (r < 0) {
-                dev_err(&core.pdev->dev, "getting transaction ID failed, "
-                                "will force context restore\n");
-                r = -1;
-        }
-        return r;
-}
-
-int dss_need_ctx_restore(void)
-{
-        int id = dss_get_ctx_id();
-
-        if (id < 0 || id != core.ctx_id) {
-                DSSDBG("ctx id %d -> id %d\n",
-                                core.ctx_id, id);
-                core.ctx_id = id;
-                return 1;
-        } else {
-                return 0;
-        }
-}
-
-static void save_all_ctx(void)
-{
-        DSSDBG("save context\n");
-
-        dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
-
-        dss_save_context();
-        dispc_save_context();
-#ifdef CONFIG_OMAP2_DSS_DSI
-        dsi_save_context();
-#endif
-
-        dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
-}
-
-static void restore_all_ctx(void)
-{
-        DSSDBG("restore context\n");
-
-        dss_clk_enable_all_no_ctx();
-
-        dss_restore_context();
-        dispc_restore_context();
-#ifdef CONFIG_OMAP2_DSS_DSI
-        dsi_restore_context();
-#endif
-
-        dss_clk_disable_all_no_ctx();
-}
-
-#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
-/* CLOCKS */
-static void core_dump_clocks(struct seq_file *s)
-{
-        int i;
-        struct clk *clocks[5] = {
-                core.dss_ick,
-                core.dss1_fck,
-                core.dss2_fck,
-                core.dss_54m_fck,
-                core.dss_96m_fck
-        };
-
-        seq_printf(s, "- CORE -\n");
-
-        seq_printf(s, "internal clk count\t\t%u\n", core.num_clks_enabled);
-
-        for (i = 0; i < 5; i++) {
-                if (!clocks[i])
-                        continue;
-                seq_printf(s, "%-15s\t%lu\t%d\n",
-                                clocks[i]->name,
-                                clk_get_rate(clocks[i]),
-                                clocks[i]->usecount);
-        }
-}
-#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
-
-static int dss_get_clock(struct clk **clock, const char *clk_name)
-{
-        struct clk *clk;
-
-        clk = clk_get(&core.pdev->dev, clk_name);
-
-        if (IS_ERR(clk)) {
-                DSSERR("can't get clock %s", clk_name);
-                return PTR_ERR(clk);
-        }
-
-        *clock = clk;
-
-        DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
-
-        return 0;
-}
-
-static int dss_get_clocks(void)
-{
-        int r;
-
-        core.dss_ick = NULL;
-        core.dss1_fck = NULL;
-        core.dss2_fck = NULL;
-        core.dss_54m_fck = NULL;
-        core.dss_96m_fck = NULL;
-
-        r = dss_get_clock(&core.dss_ick, "ick");
-        if (r)
-                goto err;
-
-        r = dss_get_clock(&core.dss1_fck, "dss1_fck");
-        if (r)
-                goto err;
-
-        r = dss_get_clock(&core.dss2_fck, "dss2_fck");
-        if (r)
-                goto err;
-
-        r = dss_get_clock(&core.dss_54m_fck, "tv_fck");
-        if (r)
-                goto err;
-
-        r = dss_get_clock(&core.dss_96m_fck, "video_fck");
-        if (r)
-                goto err;
-
-        return 0;
-
-err:
-        if (core.dss_ick)
-                clk_put(core.dss_ick);
-        if (core.dss1_fck)
-                clk_put(core.dss1_fck);
-        if (core.dss2_fck)
-                clk_put(core.dss2_fck);
-        if (core.dss_54m_fck)
-                clk_put(core.dss_54m_fck);
-        if (core.dss_96m_fck)
-                clk_put(core.dss_96m_fck);
-
-        return r;
-}
-
-static void dss_put_clocks(void)
-{
-        if (core.dss_96m_fck)
-                clk_put(core.dss_96m_fck);
-        clk_put(core.dss_54m_fck);
-        clk_put(core.dss1_fck);
-        clk_put(core.dss2_fck);
-        clk_put(core.dss_ick);
-}
-
-unsigned long dss_clk_get_rate(enum dss_clock clk)
-{
-        switch (clk) {
-        case DSS_CLK_ICK:
-                return clk_get_rate(core.dss_ick);
-        case DSS_CLK_FCK1:
-                return clk_get_rate(core.dss1_fck);
-        case DSS_CLK_FCK2:
-                return clk_get_rate(core.dss2_fck);
-        case DSS_CLK_54M:
-                return clk_get_rate(core.dss_54m_fck);
-        case DSS_CLK_96M:
-                return clk_get_rate(core.dss_96m_fck);
-        }
-
-        BUG();
-        return 0;
-}
-
-static unsigned count_clk_bits(enum dss_clock clks)
-{
-        unsigned num_clks = 0;
-
-        if (clks & DSS_CLK_ICK)
-                ++num_clks;
-        if (clks & DSS_CLK_FCK1)
-                ++num_clks;
-        if (clks & DSS_CLK_FCK2)
-                ++num_clks;
-        if (clks & DSS_CLK_54M)
-                ++num_clks;
-        if (clks & DSS_CLK_96M)
-                ++num_clks;
-
-        return num_clks;
-}
-
-static void dss_clk_enable_no_ctx(enum dss_clock clks)
-{
-        unsigned num_clks = count_clk_bits(clks);
-
-        if (clks & DSS_CLK_ICK)
-                clk_enable(core.dss_ick);
-        if (clks & DSS_CLK_FCK1)
-                clk_enable(core.dss1_fck);
-        if (clks & DSS_CLK_FCK2)
-                clk_enable(core.dss2_fck);
-        if (clks & DSS_CLK_54M)
-                clk_enable(core.dss_54m_fck);
-        if (clks & DSS_CLK_96M)
-                clk_enable(core.dss_96m_fck);
-
-        core.num_clks_enabled += num_clks;
-}
-
-void dss_clk_enable(enum dss_clock clks)
-{
-        bool check_ctx = core.num_clks_enabled == 0;
-
-        dss_clk_enable_no_ctx(clks);
-
-        if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore())
-                restore_all_ctx();
-}
-
-static void dss_clk_disable_no_ctx(enum dss_clock clks)
-{
-        unsigned num_clks = count_clk_bits(clks);
-
-        if (clks & DSS_CLK_ICK)
-                clk_disable(core.dss_ick);
-        if (clks & DSS_CLK_FCK1)
-                clk_disable(core.dss1_fck);
-        if (clks & DSS_CLK_FCK2)
-                clk_disable(core.dss2_fck);
-        if (clks & DSS_CLK_54M)
-                clk_disable(core.dss_54m_fck);
-        if (clks & DSS_CLK_96M)
-                clk_disable(core.dss_96m_fck);
-
-        core.num_clks_enabled -= num_clks;
-}
-
-void dss_clk_disable(enum dss_clock clks)
-{
-        if (cpu_is_omap34xx()) {
-                unsigned num_clks = count_clk_bits(clks);
-
-                BUG_ON(core.num_clks_enabled < num_clks);
-
-                if (core.num_clks_enabled == num_clks)
-                        save_all_ctx();
-        }
-
-        dss_clk_disable_no_ctx(clks);
-}
-
-static void dss_clk_enable_all_no_ctx(void)
-{
-        enum dss_clock clks;
-
-        clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
-        if (cpu_is_omap34xx())
-                clks |= DSS_CLK_96M;
-        dss_clk_enable_no_ctx(clks);
-}
-
-static void dss_clk_disable_all_no_ctx(void)
-{
-        enum dss_clock clks;
-
-        clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
-        if (cpu_is_omap34xx())
-                clks |= DSS_CLK_96M;
-        dss_clk_disable_no_ctx(clks);
-}
-
-static void dss_clk_disable_all(void)
-{
-        enum dss_clock clks;
-
-        clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
-        if (cpu_is_omap34xx())
-                clks |= DSS_CLK_96M;
-        dss_clk_disable(clks);
-}
-
 /* REGULATORS */
 
 struct regulator *dss_get_vdds_dsi(void)
@@ -390,32 +84,7 @@ struct regulator *dss_get_vdds_sdi(void)
         return reg;
 }
 
-struct regulator *dss_get_vdda_dac(void)
-{
-        struct regulator *reg;
-
-        if (core.vdda_dac_reg != NULL)
-                return core.vdda_dac_reg;
-
-        reg = regulator_get(&core.pdev->dev, "vdda_dac");
-        if (!IS_ERR(reg))
-                core.vdda_dac_reg = reg;
-
-        return reg;
-}
-
-/* DEBUGFS */
 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
-static void dss_debug_dump_clocks(struct seq_file *s)
-{
-        core_dump_clocks(s);
-        dss_dump_clocks(s);
-        dispc_dump_clocks(s);
-#ifdef CONFIG_OMAP2_DSS_DSI
-        dsi_dump_clocks(s);
-#endif
-}
-
 static int dss_debug_show(struct seq_file *s, void *unused)
 {
         void (*func)(struct seq_file *) = s->private;
@@ -497,7 +166,6 @@ static inline void dss_uninitialize_debugfs(void)
 static int omap_dss_probe(struct platform_device *pdev)
 {
         struct omap_dss_board_info *pdata = pdev->dev.platform_data;
-        int skip_init = 0;
         int r;
         int i;
 
@@ -508,63 +176,43 @@ static int omap_dss_probe(struct platform_device *pdev)
         dss_init_overlay_managers(pdev);
         dss_init_overlays(pdev);
 
-        r = dss_get_clocks();
-        if (r)
-                goto err_clocks;
-
-        dss_clk_enable_all_no_ctx();
-
-        core.ctx_id = dss_get_ctx_id();
-        DSSDBG("initial ctx id %u\n", core.ctx_id);
-
-#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
-        /* DISPC_CONTROL */
-        if (omap_readl(0x48050440) & 1) /* LCD enabled? */
-                skip_init = 1;
-#endif
-
-        r = dss_init(skip_init);
+        r = dss_init_platform_driver();
         if (r) {
-                DSSERR("Failed to initialize DSS\n");
+                DSSERR("Failed to initialize DSS platform driver\n");
                 goto err_dss;
         }
 
-        r = rfbi_init();
-        if (r) {
-                DSSERR("Failed to initialize rfbi\n");
-                goto err_rfbi;
-        }
+        /* keep clocks enabled to prevent context saves/restores during init */
+        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 
-        r = dpi_init(pdev);
+        r = rfbi_init_platform_driver();
         if (r) {
-                DSSERR("Failed to initialize dpi\n");
-                goto err_dpi;
+                DSSERR("Failed to initialize rfbi platform driver\n");
+                goto err_rfbi;
         }
 
-        r = dispc_init();
+        r = dispc_init_platform_driver();
         if (r) {
-                DSSERR("Failed to initialize dispc\n");
+                DSSERR("Failed to initialize dispc platform driver\n");
                 goto err_dispc;
         }
 
-        r = venc_init(pdev);
+        r = venc_init_platform_driver();
         if (r) {
-                DSSERR("Failed to initialize venc\n");
+                DSSERR("Failed to initialize venc platform driver\n");
                 goto err_venc;
         }
 
-        if (cpu_is_omap34xx()) {
-                r = sdi_init(skip_init);
-                if (r) {
-                        DSSERR("Failed to initialize SDI\n");
-                        goto err_sdi;
-                }
+        r = dsi_init_platform_driver();
+        if (r) {
+                DSSERR("Failed to initialize DSI platform driver\n");
+                goto err_dsi;
+        }
 
-                r = dsi_init(pdev);
-                if (r) {
-                        DSSERR("Failed to initialize DSI\n");
-                        goto err_dsi;
-                }
+        r = hdmi_init_platform_driver();
+        if (r) {
+                DSSERR("Failed to initialize hdmi\n");
+                goto err_hdmi;
         }
 
         r = dss_initialize_debugfs();
@@ -589,32 +237,25 @@ static int omap_dss_probe(struct platform_device *pdev)
                         pdata->default_device = dssdev;
         }
 
-        dss_clk_disable_all();
+        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 
         return 0;
 
 err_register:
         dss_uninitialize_debugfs();
 err_debugfs:
-        if (cpu_is_omap34xx())
-                dsi_exit();
+        hdmi_uninit_platform_driver();
+err_hdmi:
+        dsi_uninit_platform_driver();
 err_dsi:
-        if (cpu_is_omap34xx())
-                sdi_exit();
-err_sdi:
-        venc_exit();
+        venc_uninit_platform_driver();
 err_venc:
-        dispc_exit();
+        dispc_uninit_platform_driver();
 err_dispc:
-        dpi_exit();
-err_dpi:
-        rfbi_exit();
+        rfbi_uninit_platform_driver();
 err_rfbi:
-        dss_exit();
+        dss_uninit_platform_driver();
 err_dss:
-        dss_clk_disable_all_no_ctx();
-        dss_put_clocks();
-err_clocks:
 
         return r;
 }
@@ -623,61 +264,15 @@ static int omap_dss_remove(struct platform_device *pdev)
 {
         struct omap_dss_board_info *pdata = pdev->dev.platform_data;
         int i;
-        int c;
 
         dss_uninitialize_debugfs();
 
-        venc_exit();
-        dispc_exit();
-        dpi_exit();
-        rfbi_exit();
-        if (cpu_is_omap34xx()) {
-                dsi_exit();
-                sdi_exit();
-        }
-
-        dss_exit();
-
-        /* these should be removed at some point */
-        c = core.dss_ick->usecount;
-        if (c > 0) {
-                DSSERR("warning: dss_ick usecount %d, disabling\n", c);
-                while (c-- > 0)
-                        clk_disable(core.dss_ick);
-        }
-
-        c = core.dss1_fck->usecount;
-        if (c > 0) {
-                DSSERR("warning: dss1_fck usecount %d, disabling\n", c);
-                while (c-- > 0)
-                        clk_disable(core.dss1_fck);
-        }
-
-        c = core.dss2_fck->usecount;
-        if (c > 0) {
-                DSSERR("warning: dss2_fck usecount %d, disabling\n", c);
-                while (c-- > 0)
-                        clk_disable(core.dss2_fck);
-        }
-
-        c = core.dss_54m_fck->usecount;
-        if (c > 0) {
-                DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c);
-                while (c-- > 0)
-                        clk_disable(core.dss_54m_fck);
-        }
-
-        if (core.dss_96m_fck) {
-                c = core.dss_96m_fck->usecount;
-                if (c > 0) {
-                        DSSERR("warning: dss_96m_fck usecount %d, disabling\n",
-                                        c);
-                        while (c-- > 0)
-                                clk_disable(core.dss_96m_fck);
-                }
-        }
-
-        dss_put_clocks();
+        venc_uninit_platform_driver();
+        dispc_uninit_platform_driver();
+        rfbi_uninit_platform_driver();
+        dsi_uninit_platform_driver();
+        hdmi_uninit_platform_driver();
+        dss_uninit_platform_driver();
 
         dss_uninit_overlays(pdev);
         dss_uninit_overlay_managers(pdev);
@@ -965,11 +560,6 @@ static void __exit omap_dss_exit(void)
                 core.vdds_sdi_reg = NULL;
         }
 
-        if (core.vdda_dac_reg != NULL) {
-                regulator_put(core.vdda_dac_reg);
-                core.vdda_dac_reg = NULL;
-        }
-
         platform_driver_unregister(&omap_dss_driver);
 
         omap_dss_bus_unregister();
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 9f8c69f16e61..7804779c9da1 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -32,6 +32,7 @@
 #include <linux/delay.h>
 #include <linux/workqueue.h>
 #include <linux/hardirq.h>
+#include <linux/interrupt.h>
 
 #include <plat/sram.h>
 #include <plat/clock.h>
@@ -42,8 +43,6 @@
 #include "dss_features.h"
 
 /* DISPC */
-#define DISPC_BASE                      0x48050400
-
 #define DISPC_SZ_REGS                   SZ_4K
 
 struct dispc_reg { u16 idx; };
@@ -74,7 +73,7 @@ struct dispc_reg { u16 idx; };
 #define DISPC_TIMING_H(ch)              DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
 #define DISPC_TIMING_V(ch)              DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
 #define DISPC_POL_FREQ(ch)              DISPC_REG(ch != 2 ? 0x006C : 0x0408)
-#define DISPC_DIVISOR(ch)               DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
+#define DISPC_DIVISORo(ch)              DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
 #define DISPC_GLOBAL_ALPHA              DISPC_REG(0x0074)
 #define DISPC_SIZE_DIG                  DISPC_REG(0x0078)
 #define DISPC_SIZE_LCD(ch)              DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
@@ -129,6 +128,7 @@ struct dispc_reg { u16 idx; };
 
 #define DISPC_VID_PRELOAD(n)            DISPC_REG(0x230 + (n)*0x04)
 
+#define DISPC_DIVISOR                   DISPC_REG(0x0804)
 
 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
                                          DISPC_IRQ_OCP_ERR | \
@@ -178,7 +178,9 @@ struct dispc_irq_stats {
 };
 
 static struct {
+        struct platform_device *pdev;
         void __iomem    *base;
+        int irq;
 
         u32     fifo_size[3];
 
@@ -230,7 +232,7 @@ void dispc_save_context(void)
         SR(TIMING_H(0));
         SR(TIMING_V(0));
         SR(POL_FREQ(0));
-        SR(DIVISOR(0));
+        SR(DIVISORo(0));
         SR(GLOBAL_ALPHA);
         SR(SIZE_DIG);
         SR(SIZE_LCD(0));
@@ -242,7 +244,7 @@ void dispc_save_context(void)
                 SR(TIMING_H(2));
                 SR(TIMING_V(2));
                 SR(POL_FREQ(2));
-                SR(DIVISOR(2));
+                SR(DIVISORo(2));
                 SR(CONFIG2);
         }
 
@@ -373,6 +375,9 @@ void dispc_save_context(void)
         SR(VID_FIR_COEF_V(1, 7));
 
         SR(VID_PRELOAD(1));
+
+        if (dss_has_feature(FEAT_CORE_CLK_DIV))
+                SR(DIVISOR);
 }
 
 void dispc_restore_context(void)
@@ -389,7 +394,7 @@ void dispc_restore_context(void)
         RR(TIMING_H(0));
         RR(TIMING_V(0));
         RR(POL_FREQ(0));
-        RR(DIVISOR(0));
+        RR(DIVISORo(0));
         RR(GLOBAL_ALPHA);
         RR(SIZE_DIG);
         RR(SIZE_LCD(0));
@@ -400,7 +405,7 @@ void dispc_restore_context(void)
                 RR(TIMING_H(2));
                 RR(TIMING_V(2));
                 RR(POL_FREQ(2));
-                RR(DIVISOR(2));
+                RR(DIVISORo(2));
                 RR(CONFIG2);
         }
 
@@ -532,6 +537,9 @@ void dispc_restore_context(void)
 
         RR(VID_PRELOAD(1));
 
+        if (dss_has_feature(FEAT_CORE_CLK_DIV))
+                RR(DIVISOR);
+
         /* enable last, because LCD & DIGIT enable are here */
         RR(CONTROL);
         if (dss_has_feature(FEAT_MGR_LCD2))
@@ -552,9 +560,9 @@ void dispc_restore_context(void)
 static inline void enable_clocks(bool enable)
 {
         if (enable)
-                dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+                dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
         else
-                dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+                dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 }
 
 bool dispc_go_busy(enum omap_channel channel)
@@ -1000,6 +1008,20 @@ void dispc_set_burst_size(enum omap_plane plane,
         enable_clocks(0);
 }
 
+void dispc_enable_gamma_table(bool enable)
+{
+        /*
+         * This is partially implemented to support only disabling of
+         * the gamma table.
+         */
+        if (enable) {
+                DSSWARN("Gamma table enabling for TV not yet supported");
+                return;
+        }
+
+        REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
+}
+
 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
 {
         u32 val;
@@ -1129,10 +1151,16 @@ static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
         u32 val;
         const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
                                       DISPC_VID_ACCU0(1) };
+        u8 hor_start, hor_end, vert_start, vert_end;
 
         BUG_ON(plane == OMAP_DSS_GFX);
 
-        val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
+        dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
+        dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
+
+        val = FLD_VAL(vaccu, vert_start, vert_end) |
+                        FLD_VAL(haccu, hor_start, hor_end);
+
         dispc_write_reg(ac0_reg[plane-1], val);
 }
 
@@ -1141,10 +1169,16 @@ static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
         u32 val;
         const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
                                       DISPC_VID_ACCU1(1) };
+        u8 hor_start, hor_end, vert_start, vert_end;
 
         BUG_ON(plane == OMAP_DSS_GFX);
 
-        val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
+        dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
+        dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
+
+        val = FLD_VAL(vaccu, vert_start, vert_end) |
+                        FLD_VAL(haccu, hor_start, hor_end);
+
         dispc_write_reg(ac1_reg[plane-1], val);
 }
 
@@ -1182,16 +1216,25 @@ static void _dispc_set_scaling(enum omap_plane plane,
         _dispc_set_fir(plane, fir_hinc, fir_vinc);
 
         l = dispc_read_reg(dispc_reg_att[plane]);
-        l &= ~((0x0f << 5) | (0x3 << 21));
 
+        /* RESIZEENABLE and VERTICALTAPS */
+        l &= ~((0x3 << 5) | (0x1 << 21));
         l |= fir_hinc ? (1 << 5) : 0;
         l |= fir_vinc ? (1 << 6) : 0;
+        l |= five_taps ? (1 << 21) : 0;
 
-        l |= hscaleup ? 0 : (1 << 7);
-        l |= vscaleup ? 0 : (1 << 8);
+        /* VRESIZECONF and HRESIZECONF */
+        if (dss_has_feature(FEAT_RESIZECONF)) {
+                l &= ~(0x3 << 7);
+                l |= hscaleup ? 0 : (1 << 7);
+                l |= vscaleup ? 0 : (1 << 8);
+        }
 
-        l |= five_taps ? (1 << 21) : 0;
-        l |= five_taps ? (1 << 22) : 0;
+        /* LINEBUFFERSPLIT */
+        if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
+                l &= ~(0x1 << 22);
+                l |= five_taps ? (1 << 22) : 0;
+        }
 
         dispc_write_reg(dispc_reg_att[plane], l);
 
@@ -1215,9 +1258,11 @@ static void _dispc_set_scaling(enum omap_plane plane,
 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
                 bool mirroring, enum omap_color_mode color_mode)
 {
+        bool row_repeat = false;
+        int vidrot = 0;
+
         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
                         color_mode == OMAP_DSS_COLOR_UYVY) {
-                int vidrot = 0;
 
                 if (mirroring) {
                         switch (rotation) {
@@ -1251,16 +1296,15 @@ static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
                         }
                 }
 
-                REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
-
                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
-                        REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
+                        row_repeat = true;
                 else
-                        REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
-        } else {
-                REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
-                REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
+                        row_repeat = false;
         }
+
+        REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
+        if (dss_has_feature(FEAT_ROWREPEATENABLE))
+                REG_FLD_MOD(dispc_reg_att[plane], row_repeat ? 1 : 0, 18, 18);
 }
 
 static int color_mode_to_bpp(enum omap_color_mode color_mode)
@@ -2293,7 +2337,7 @@ static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
         BUG_ON(pck_div < 2);
 
         enable_clocks(1);
-        dispc_write_reg(DISPC_DIVISOR(channel),
+        dispc_write_reg(DISPC_DIVISORo(channel),
                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
         enable_clocks(0);
 }
@@ -2302,7 +2346,7 @@ static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
                 int *pck_div)
 {
         u32 l;
-        l = dispc_read_reg(DISPC_DIVISOR(channel));
+        l = dispc_read_reg(DISPC_DIVISORo(channel));
         *lck_div = FLD_GET(l, 23, 16);
         *pck_div = FLD_GET(l, 7, 0);
 }
@@ -2311,14 +2355,17 @@ unsigned long dispc_fclk_rate(void)
 {
         unsigned long r = 0;
 
-        if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
-                r = dss_clk_get_rate(DSS_CLK_FCK1);
-        else
-#ifdef CONFIG_OMAP2_DSS_DSI
-                r = dsi_get_dsi1_pll_rate();
-#else
-        BUG();
-#endif
+        switch (dss_get_dispc_clk_source()) {
+        case DSS_CLK_SRC_FCK:
+                r = dss_clk_get_rate(DSS_CLK_FCK);
+                break;
+        case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
+                r = dsi_get_pll_hsdiv_dispc_rate();
+                break;
+        default:
+                BUG();
+        }
+
         return r;
 }
 
@@ -2328,47 +2375,72 @@ unsigned long dispc_lclk_rate(enum omap_channel channel)
         unsigned long r;
         u32 l;
 
-        l = dispc_read_reg(DISPC_DIVISOR(channel));
+        l = dispc_read_reg(DISPC_DIVISORo(channel));
 
         lcd = FLD_GET(l, 23, 16);
 
-        r = dispc_fclk_rate();
+        switch (dss_get_lcd_clk_source(channel)) {
+        case DSS_CLK_SRC_FCK:
+                r = dss_clk_get_rate(DSS_CLK_FCK);
+                break;
+        case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
+                r = dsi_get_pll_hsdiv_dispc_rate();
+                break;
+        default:
+                BUG();
+        }
 
         return r / lcd;
 }
 
 unsigned long dispc_pclk_rate(enum omap_channel channel)
 {
-        int lcd, pcd;
+        int pcd;
         unsigned long r;
         u32 l;
 
-        l = dispc_read_reg(DISPC_DIVISOR(channel));
+        l = dispc_read_reg(DISPC_DIVISORo(channel));
 
-        lcd = FLD_GET(l, 23, 16);
         pcd = FLD_GET(l, 7, 0);
 
-        r = dispc_fclk_rate();
+        r = dispc_lclk_rate(channel);
 
-        return r / lcd / pcd;
+        return r / pcd;
 }
 
 void dispc_dump_clocks(struct seq_file *s)
 {
         int lcd, pcd;
+        u32 l;
+        enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
+        enum dss_clk_source lcd_clk_src;
 
         enable_clocks(1);
 
         seq_printf(s, "- DISPC -\n");
 
-        seq_printf(s, "dispc fclk source = %s\n",
-                        dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
-                        "dss1_alwon_fclk" : "dsi1_pll_fclk");
+        seq_printf(s, "dispc fclk source = %s (%s)\n",
+                        dss_get_generic_clk_source_name(dispc_clk_src),
+                        dss_feat_get_clk_source_name(dispc_clk_src));
 
         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
 
+        if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
+                seq_printf(s, "- DISPC-CORE-CLK -\n");
+                l = dispc_read_reg(DISPC_DIVISOR);
+                lcd = FLD_GET(l, 23, 16);
+
+                seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
+                                (dispc_fclk_rate()/lcd), lcd);
+        }
         seq_printf(s, "- LCD1 -\n");
 
+        lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
+
+        seq_printf(s, "lcd1_clk source = %s (%s)\n",
+                dss_get_generic_clk_source_name(lcd_clk_src),
+                dss_feat_get_clk_source_name(lcd_clk_src));
+
         dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
 
         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
@@ -2378,6 +2450,12 @@ void dispc_dump_clocks(struct seq_file *s)
         if (dss_has_feature(FEAT_MGR_LCD2)) {
                 seq_printf(s, "- LCD2 -\n");
 
+                lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
+
+                seq_printf(s, "lcd2_clk source = %s (%s)\n",
+                        dss_get_generic_clk_source_name(lcd_clk_src),
+                        dss_feat_get_clk_source_name(lcd_clk_src));
+
                 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
 
                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
@@ -2440,7 +2518,7 @@ void dispc_dump_regs(struct seq_file *s)
 {
 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
 
-        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 
         DUMPREG(DISPC_REVISION);
         DUMPREG(DISPC_SYSCONFIG);
@@ -2459,7 +2537,7 @@ void dispc_dump_regs(struct seq_file *s)
         DUMPREG(DISPC_TIMING_H(0));
         DUMPREG(DISPC_TIMING_V(0));
         DUMPREG(DISPC_POL_FREQ(0));
-        DUMPREG(DISPC_DIVISOR(0));
+        DUMPREG(DISPC_DIVISORo(0));
         DUMPREG(DISPC_GLOBAL_ALPHA);
         DUMPREG(DISPC_SIZE_DIG);
         DUMPREG(DISPC_SIZE_LCD(0));
@@ -2471,7 +2549,7 @@ void dispc_dump_regs(struct seq_file *s)
                 DUMPREG(DISPC_TIMING_H(2));
                 DUMPREG(DISPC_TIMING_V(2));
                 DUMPREG(DISPC_POL_FREQ(2));
-                DUMPREG(DISPC_DIVISOR(2));
+                DUMPREG(DISPC_DIVISORo(2));
                 DUMPREG(DISPC_SIZE_LCD(2));
         }
 
@@ -2597,7 +2675,7 @@ void dispc_dump_regs(struct seq_file *s)
         DUMPREG(DISPC_VID_PRELOAD(0));
         DUMPREG(DISPC_VID_PRELOAD(1));
 
-        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 #undef DUMPREG
 }
 
@@ -2713,8 +2791,8 @@ int dispc_get_clock_div(enum omap_channel channel,
 
         fck = dispc_fclk_rate();
 
-        cinfo->lck_div = REG_GET(DISPC_DIVISOR(channel), 23, 16);
-        cinfo->pck_div = REG_GET(DISPC_DIVISOR(channel), 7, 0);
+        cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
+        cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
 
         cinfo->lck = fck / cinfo->lck_div;
         cinfo->pck = cinfo->lck / cinfo->pck_div;
@@ -2791,6 +2869,9 @@ int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
                 break;
         }
 
+        if (ret)
+                goto err;
+
         _omap_dispc_set_irqs();
 
         spin_unlock_irqrestore(&dispc.irq_lock, flags);
@@ -2866,10 +2947,10 @@ static void print_irq_status(u32 status)
  * but we presume they are on because we got an IRQ. However,
  * an irq handler may turn the clocks off, so we may not have
  * clock later in the function. */
-void dispc_irq_handler(void)
+static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
 {
         int i;
-        u32 irqstatus;
+        u32 irqstatus, irqenable;
         u32 handledirqs = 0;
         u32 unhandled_errors;
         struct omap_dispc_isr_data *isr_data;
@@ -2878,6 +2959,13 @@ void dispc_irq_handler(void)
         spin_lock(&dispc.irq_lock);
 
         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
+        irqenable = dispc_read_reg(DISPC_IRQENABLE);
+
+        /* IRQ is not for us */
+        if (!(irqstatus & irqenable)) {
+                spin_unlock(&dispc.irq_lock);
+                return IRQ_NONE;
+        }
 
 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
         spin_lock(&dispc.irq_stats_lock);
@@ -2929,6 +3017,8 @@ void dispc_irq_handler(void)
         }
 
         spin_unlock(&dispc.irq_lock);
+
+        return IRQ_HANDLED;
 }
 
 static void dispc_error_worker(struct work_struct *work)
@@ -3253,6 +3343,15 @@ static void _omap_dispc_initial_config(void)
         l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
         dispc_write_reg(DISPC_SYSCONFIG, l);
 
+        /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
+        if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
+                l = dispc_read_reg(DISPC_DIVISOR);
+                /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
+                l = FLD_MOD(l, 1, 0, 0);
+                l = FLD_MOD(l, 1, 23, 16);
+                dispc_write_reg(DISPC_DIVISOR, l);
+        }
+
         /* FUNCGATED */
         if (dss_has_feature(FEAT_FUNCGATED))
                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
@@ -3269,47 +3368,6 @@ static void _omap_dispc_initial_config(void)
         dispc_read_plane_fifo_sizes();
 }
 
-int dispc_init(void)
-{
-        u32 rev;
-
-        spin_lock_init(&dispc.irq_lock);
-
-#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
-        spin_lock_init(&dispc.irq_stats_lock);
-        dispc.irq_stats.last_reset = jiffies;
-#endif
-
-        INIT_WORK(&dispc.error_work, dispc_error_worker);
-
-        dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
-        if (!dispc.base) {
-                DSSERR("can't ioremap DISPC\n");
-                return -ENOMEM;
-        }
-
-        enable_clocks(1);
-
-        _omap_dispc_initial_config();
-
-        _omap_dispc_initialize_irq();
-
-        dispc_save_context();
-
-        rev = dispc_read_reg(DISPC_REVISION);
-        printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
-               FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
-
-        enable_clocks(0);
-
-        return 0;
-}
-
-void dispc_exit(void)
-{
-        iounmap(dispc.base);
-}
-
 int dispc_enable_plane(enum omap_plane plane, bool enable)
 {
         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
@@ -3359,3 +3417,94 @@ int dispc_setup_plane(enum omap_plane plane,
 
         return r;
 }
+
+/* DISPC HW IP initialisation */
+static int omap_dispchw_probe(struct platform_device *pdev)
+{
+        u32 rev;
+        int r = 0;
+        struct resource *dispc_mem;
+
+        dispc.pdev = pdev;
+
+        spin_lock_init(&dispc.irq_lock);
+
+#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
+        spin_lock_init(&dispc.irq_stats_lock);
+        dispc.irq_stats.last_reset = jiffies;
+#endif
+
+        INIT_WORK(&dispc.error_work, dispc_error_worker);
+
+        dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
+        if (!dispc_mem) {
+                DSSERR("can't get IORESOURCE_MEM DISPC\n");
+                r = -EINVAL;
+                goto fail0;
+        }
+        dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
+        if (!dispc.base) {
+                DSSERR("can't ioremap DISPC\n");
+                r = -ENOMEM;
+                goto fail0;
+        }
+        dispc.irq = platform_get_irq(dispc.pdev, 0);
+        if (dispc.irq < 0) {
+                DSSERR("platform_get_irq failed\n");
+                r = -ENODEV;
+                goto fail1;
+        }
+
+        r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
+                "OMAP DISPC", dispc.pdev);
+        if (r < 0) {
+                DSSERR("request_irq failed\n");
+                goto fail1;
+        }
+
+        enable_clocks(1);
+
+        _omap_dispc_initial_config();
+
+        _omap_dispc_initialize_irq();
+
+        dispc_save_context();
+
+        rev = dispc_read_reg(DISPC_REVISION);
+        dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
+               FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
+
+        enable_clocks(0);
+
+        return 0;
+fail1:
+        iounmap(dispc.base);
+fail0:
+        return r;
+}
+
+static int omap_dispchw_remove(struct platform_device *pdev)
+{
+        free_irq(dispc.irq, dispc.pdev);
+        iounmap(dispc.base);
+        return 0;
+}
+
+static struct platform_driver omap_dispchw_driver = {
+        .probe          = omap_dispchw_probe,
+        .remove         = omap_dispchw_remove,
+        .driver         = {
+                .name   = "omapdss_dispc",
+                .owner  = THIS_MODULE,
+        },
+};
+
+int dispc_init_platform_driver(void)
+{
+        return platform_driver_register(&omap_dispchw_driver);
+}
+
+void dispc_uninit_platform_driver(void)
+{
+        return platform_driver_unregister(&omap_dispchw_driver);
+}
diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c
index 22dd7a474f79..a85a6f38b40c 100644
--- a/drivers/video/omap2/dss/display.c
+++ b/drivers/video/omap2/dss/display.c
@@ -25,14 +25,11 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/jiffies.h>
-#include <linux/list.h>
 #include <linux/platform_device.h>
 
 #include <plat/display.h>
 #include "dss.h"
 
-static LIST_HEAD(display_list);
-
 static ssize_t display_enabled_show(struct device *dev,
                 struct device_attribute *attr, char *buf)
 {
@@ -345,6 +342,7 @@ int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev)
                         return 16;
         case OMAP_DISPLAY_TYPE_VENC:
         case OMAP_DISPLAY_TYPE_SDI:
+        case OMAP_DISPLAY_TYPE_HDMI:
                 return 24;
         default:
                 BUG();
@@ -371,6 +369,7 @@ bool dss_use_replication(struct omap_dss_device *dssdev,
         case OMAP_DISPLAY_TYPE_DPI:
                 bpp = dssdev->phy.dpi.data_lines;
                 break;
+        case OMAP_DISPLAY_TYPE_HDMI:
         case OMAP_DISPLAY_TYPE_VENC:
         case OMAP_DISPLAY_TYPE_SDI:
                 bpp = 24;
@@ -396,29 +395,6 @@ void dss_init_device(struct platform_device *pdev,
         switch (dssdev->type) {
 #ifdef CONFIG_OMAP2_DSS_DPI
         case OMAP_DISPLAY_TYPE_DPI:
-#endif
-#ifdef CONFIG_OMAP2_DSS_RFBI
-        case OMAP_DISPLAY_TYPE_DBI:
-#endif
-#ifdef CONFIG_OMAP2_DSS_SDI
-        case OMAP_DISPLAY_TYPE_SDI:
-#endif
-#ifdef CONFIG_OMAP2_DSS_DSI
-        case OMAP_DISPLAY_TYPE_DSI:
-#endif
-#ifdef CONFIG_OMAP2_DSS_VENC
-        case OMAP_DISPLAY_TYPE_VENC:
-#endif
-                break;
-        default:
-                DSSERR("Support for display '%s' not compiled in.\n",
-                                dssdev->name);
-                return;
-        }
-
-        switch (dssdev->type) {
-#ifdef CONFIG_OMAP2_DSS_DPI
-        case OMAP_DISPLAY_TYPE_DPI:
                 r = dpi_init_display(dssdev);
                 break;
 #endif
@@ -442,8 +418,13 @@ void dss_init_device(struct platform_device *pdev,
                 r = dsi_init_display(dssdev);
                 break;
 #endif
+        case OMAP_DISPLAY_TYPE_HDMI:
+                r = hdmi_init_display(dssdev);
+                break;
         default:
-                BUG();
+                DSSERR("Support for display '%s' not compiled in.\n",
+                                dssdev->name);
+                return;
         }
 
         if (r) {
diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
index 75fb0a515430..2d3ca4ca4a05 100644
--- a/drivers/video/omap2/dss/dpi.c
+++ b/drivers/video/omap2/dss/dpi.c
@@ -57,13 +57,13 @@ static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
         if (r)
                 return r;
 
-        dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
+        dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);
 
         r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
         if (r)
                 return r;
 
-        *fck = dsi_cinfo.dsi1_pll_fclk;
+        *fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
         *lck_div = dispc_cinfo.lck_div;
         *pck_div = dispc_cinfo.pck_div;
 
@@ -107,7 +107,7 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
         bool is_tft;
         int r = 0;
 
-        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 
         dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
                         dssdev->panel.acbi, dssdev->panel.acb);
@@ -137,7 +137,7 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
         dispc_set_lcd_timings(dssdev->manager->id, t);
 
 err0:
-        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
         return r;
 }
 
@@ -173,14 +173,14 @@ int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
                         goto err1;
         }
 
-        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 
         r = dpi_basic_init(dssdev);
         if (r)
                 goto err2;
 
 #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
-        dss_clk_enable(DSS_CLK_FCK2);
+        dss_clk_enable(DSS_CLK_SYSCK);
         r = dsi_pll_init(dssdev, 0, 1);
         if (r)
                 goto err3;
@@ -199,10 +199,10 @@ err4:
 #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
         dsi_pll_uninit();
 err3:
-        dss_clk_disable(DSS_CLK_FCK2);
+        dss_clk_disable(DSS_CLK_SYSCK);
 #endif
 err2:
-        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
         if (cpu_is_omap34xx())
                 regulator_disable(dpi.vdds_dsi_reg);
 err1:
@@ -217,12 +217,12 @@ void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
         dssdev->manager->disable(dssdev->manager);
 
 #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
-        dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
+        dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
         dsi_pll_uninit();
-        dss_clk_disable(DSS_CLK_FCK2);
+        dss_clk_disable(DSS_CLK_SYSCK);
 #endif
 
-        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 
         if (cpu_is_omap34xx())
                 regulator_disable(dpi.vdds_dsi_reg);
@@ -271,7 +271,7 @@ int dpi_check_timings(struct omap_dss_device *dssdev,
                 if (r)
                         return r;
 
-                fck = dsi_cinfo.dsi1_pll_fclk;
+                fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
                 lck_div = dispc_cinfo.lck_div;
                 pck_div = dispc_cinfo.pck_div;
         }
@@ -303,22 +303,27 @@ int dpi_init_display(struct omap_dss_device *dssdev)
 {
         DSSDBG("init_display\n");
 
-        return 0;
-}
+        if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) {
+                struct regulator *vdds_dsi;
 
-int dpi_init(struct platform_device *pdev)
-{
-        if (cpu_is_omap34xx()) {
-                dpi.vdds_dsi_reg = dss_get_vdds_dsi();
-                if (IS_ERR(dpi.vdds_dsi_reg)) {
+                vdds_dsi = dss_get_vdds_dsi();
+
+                if (IS_ERR(vdds_dsi)) {
                         DSSERR("can't get VDDS_DSI regulator\n");
-                        return PTR_ERR(dpi.vdds_dsi_reg);
+                        return PTR_ERR(vdds_dsi);
                 }
+
+                dpi.vdds_dsi_reg = vdds_dsi;
         }
 
         return 0;
 }
 
+int dpi_init(void)
+{
+        return 0;
+}
+
 void dpi_exit(void)
 {
 }
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index ddf3a0560822..0a7f1a47f8e3 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -38,12 +38,11 @@
 #include <plat/clock.h>
 
 #include "dss.h"
+#include "dss_features.h"
 
 /*#define VERBOSE_IRQ*/
 #define DSI_CATCH_MISSING_TE
 
-#define DSI_BASE                0x4804FC00
-
 struct dsi_reg { u16 idx; };
 
 #define DSI_REG(idx)            ((const struct dsi_reg) { idx })
@@ -186,13 +185,15 @@ struct dsi_reg { u16 idx; };
 #define DSI_DT_RX_SHORT_READ_1          0x21
 #define DSI_DT_RX_SHORT_READ_2          0x22
 
-#define FINT_MAX 2100000
-#define FINT_MIN 750000
-#define REGN_MAX (1 << 7)
-#define REGM_MAX ((1 << 11) - 1)
-#define REGM3_MAX (1 << 4)
-#define REGM4_MAX (1 << 4)
-#define LP_DIV_MAX ((1 << 13) - 1)
+typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
+
+#define DSI_MAX_NR_ISRS                2
+
+struct dsi_isr_data {
+        omap_dsi_isr_t  isr;
+        void            *arg;
+        u32             mask;
+};
 
 enum fifo_size {
         DSI_FIFO_SIZE_0         = 0,
@@ -220,9 +221,17 @@ struct dsi_irq_stats {
         unsigned cio_irqs[32];
 };
 
+struct dsi_isr_tables {
+        struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
+        struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
+        struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
+};
+
 static struct
 {
+        struct platform_device *pdev;
         void __iomem    *base;
+        int irq;
 
         struct dsi_clock_info current_cinfo;
 
@@ -232,6 +241,7 @@ static struct
                 enum dsi_vc_mode mode;
                 struct omap_dss_device *dssdev;
                 enum fifo_size fifo_size;
+                int vc_id;
         } vc[4];
 
         struct mutex lock;
@@ -239,8 +249,10 @@ static struct
 
         unsigned pll_locked;
 
-        struct completion bta_completion;
-        void (*bta_callback)(void);
+        spinlock_t irq_lock;
+        struct dsi_isr_tables isr_tables;
+        /* space for a copy used by the interrupt handler */
+        struct dsi_isr_tables isr_tables_copy;
 
         int update_channel;
         struct dsi_update_region update_region;
@@ -275,6 +287,11 @@ static struct
         spinlock_t irq_stats_lock;
         struct dsi_irq_stats irq_stats;
 #endif
+        /* DSI PLL Parameter Ranges */
+        unsigned long regm_max, regn_max;
+        unsigned long  regm_dispc_max, regm_dsi_max;
+        unsigned long  fint_min, fint_max;
+        unsigned long lpdiv_max;
 } dsi;
 
 #ifdef DEBUG
@@ -318,6 +335,11 @@ static bool dsi_bus_is_locked(void)
         return dsi.bus_lock.count == 0;
 }
 
+static void dsi_completion_handler(void *data, u32 mask)
+{
+        complete((struct completion *)data);
+}
+
 static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
                 int value)
 {
@@ -387,6 +409,9 @@ static void dsi_perf_show(const char *name)
 
 static void print_irq_status(u32 status)
 {
+        if (status == 0)
+                return;
+
 #ifndef VERBOSE_IRQ
         if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
                 return;
@@ -422,6 +447,9 @@ static void print_irq_status(u32 status)
 
 static void print_irq_status_vc(int channel, u32 status)
 {
+        if (status == 0)
+                return;
+
 #ifndef VERBOSE_IRQ
         if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
                 return;
@@ -448,6 +476,9 @@ static void print_irq_status_vc(int channel, u32 status)
 
 static void print_irq_status_cio(u32 status)
 {
+        if (status == 0)
+                return;
+
         printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
 
 #define PIS(x) \
@@ -478,22 +509,33 @@ static void print_irq_status_cio(u32 status)
         printk("\n");
 }
 
-static int debug_irq;
-
-/* called from dss */
-void dsi_irq_handler(void)
+#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
+static void dsi_collect_irq_stats(u32 irqstatus, u32 *vcstatus, u32 ciostatus)
 {
-        u32 irqstatus, vcstatus, ciostatus;
         int i;
 
-        irqstatus = dsi_read_reg(DSI_IRQSTATUS);
-
-#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
         spin_lock(&dsi.irq_stats_lock);
+
         dsi.irq_stats.irq_count++;
         dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs);
+
+        for (i = 0; i < 4; ++i)
+                dss_collect_irq_stats(vcstatus[i], dsi.irq_stats.vc_irqs[i]);
+
+        dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
+
+        spin_unlock(&dsi.irq_stats_lock);
+}
+#else
+#define dsi_collect_irq_stats(irqstatus, vcstatus, ciostatus)
 #endif
 
+static int debug_irq;
+
+static void dsi_handle_irq_errors(u32 irqstatus, u32 *vcstatus, u32 ciostatus)
+{
+        int i;
+
         if (irqstatus & DSI_IRQ_ERROR_MASK) {
                 DSSERR("DSI error, irqstatus %x\n", irqstatus);
                 print_irq_status(irqstatus);
@@ -504,37 +546,88 @@ void dsi_irq_handler(void)
                 print_irq_status(irqstatus);
         }
 
-#ifdef DSI_CATCH_MISSING_TE
-        if (irqstatus & DSI_IRQ_TE_TRIGGER)
-                del_timer(&dsi.te_timer);
-#endif
+        for (i = 0; i < 4; ++i) {
+                if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
+                        DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
+                                       i, vcstatus[i]);
+                        print_irq_status_vc(i, vcstatus[i]);
+                } else if (debug_irq) {
+                        print_irq_status_vc(i, vcstatus[i]);
+                }
+        }
+
+        if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
+                DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
+                print_irq_status_cio(ciostatus);
+        } else if (debug_irq) {
+                print_irq_status_cio(ciostatus);
+        }
+}
+
+static void dsi_call_isrs(struct dsi_isr_data *isr_array,
+                unsigned isr_array_size, u32 irqstatus)
+{
+        struct dsi_isr_data *isr_data;
+        int i;
+
+        for (i = 0; i < isr_array_size; i++) {
+                isr_data = &isr_array[i];
+                if (isr_data->isr && isr_data->mask & irqstatus)
+                        isr_data->isr(isr_data->arg, irqstatus);
+        }
+}
+
+static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
+                u32 irqstatus, u32 *vcstatus, u32 ciostatus)
+{
+        int i;
+
+        dsi_call_isrs(isr_tables->isr_table,
+                        ARRAY_SIZE(isr_tables->isr_table),
+                        irqstatus);
 
         for (i = 0; i < 4; ++i) {
-                if ((irqstatus & (1<<i)) == 0)
+                if (vcstatus[i] == 0)
                         continue;
+                dsi_call_isrs(isr_tables->isr_table_vc[i],
+                                ARRAY_SIZE(isr_tables->isr_table_vc[i]),
+                                vcstatus[i]);
+        }
 
-                vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
+        if (ciostatus != 0)
+                dsi_call_isrs(isr_tables->isr_table_cio,
+                                ARRAY_SIZE(isr_tables->isr_table_cio),
+                                ciostatus);
+}
 
-#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
-                dss_collect_irq_stats(vcstatus, dsi.irq_stats.vc_irqs[i]);
-#endif
+static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
+{
+        u32 irqstatus, vcstatus[4], ciostatus;
+        int i;
 
-                if (vcstatus & DSI_VC_IRQ_BTA) {
-                        complete(&dsi.bta_completion);
+        spin_lock(&dsi.irq_lock);
 
-                        if (dsi.bta_callback)
-                                dsi.bta_callback();
-                }
+        irqstatus = dsi_read_reg(DSI_IRQSTATUS);
 
-                if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
-                        DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
-                                       i, vcstatus);
-                        print_irq_status_vc(i, vcstatus);
-                } else if (debug_irq) {
-                        print_irq_status_vc(i, vcstatus);
+        /* IRQ is not for us */
+        if (!irqstatus) {
+                spin_unlock(&dsi.irq_lock);
+                return IRQ_NONE;
+        }
+
+        dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
+        /* flush posted write */
+        dsi_read_reg(DSI_IRQSTATUS);
+
+        for (i = 0; i < 4; ++i) {
+                if ((irqstatus & (1 << i)) == 0) {
+                        vcstatus[i] = 0;
+                        continue;
                 }
 
-                dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
+                vcstatus[i] = dsi_read_reg(DSI_VC_IRQSTATUS(i));
+
+                dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus[i]);
                 /* flush posted write */
                 dsi_read_reg(DSI_VC_IRQSTATUS(i));
         }
@@ -542,117 +635,307 @@ void dsi_irq_handler(void)
         if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
                 ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
 
-#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
-                dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
-#endif
-
                 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
                 /* flush posted write */
                 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
+        } else {
+                ciostatus = 0;
+        }
 
-                if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
-                        DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
-                        print_irq_status_cio(ciostatus);
-                } else if (debug_irq) {
-                        print_irq_status_cio(ciostatus);
-                }
+#ifdef DSI_CATCH_MISSING_TE
+        if (irqstatus & DSI_IRQ_TE_TRIGGER)
+                del_timer(&dsi.te_timer);
+#endif
+
+        /* make a copy and unlock, so that isrs can unregister
+         * themselves */
+        memcpy(&dsi.isr_tables_copy, &dsi.isr_tables, sizeof(dsi.isr_tables));
+
+        spin_unlock(&dsi.irq_lock);
+
+        dsi_handle_isrs(&dsi.isr_tables_copy, irqstatus, vcstatus, ciostatus);
+
+        dsi_handle_irq_errors(irqstatus, vcstatus, ciostatus);
+
+        dsi_collect_irq_stats(irqstatus, vcstatus, ciostatus);
+
+        return IRQ_HANDLED;
+}
+
+/* dsi.irq_lock has to be locked by the caller */
+static void _omap_dsi_configure_irqs(struct dsi_isr_data *isr_array,
+                unsigned isr_array_size, u32 default_mask,
+                const struct dsi_reg enable_reg,
+                const struct dsi_reg status_reg)
+{
+        struct dsi_isr_data *isr_data;
+        u32 mask;
+        u32 old_mask;
+        int i;
+
+        mask = default_mask;
+
+        for (i = 0; i < isr_array_size; i++) {
+                isr_data = &isr_array[i];
+
+                if (isr_data->isr == NULL)
+                        continue;
+
+                mask |= isr_data->mask;
         }
 
-        dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
-        /* flush posted write */
-        dsi_read_reg(DSI_IRQSTATUS);
+        old_mask = dsi_read_reg(enable_reg);
+        /* clear the irqstatus for newly enabled irqs */
+        dsi_write_reg(status_reg, (mask ^ old_mask) & mask);
+        dsi_write_reg(enable_reg, mask);
 
-#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
-        spin_unlock(&dsi.irq_stats_lock);
+        /* flush posted writes */
+        dsi_read_reg(enable_reg);
+        dsi_read_reg(status_reg);
+}
+
+/* dsi.irq_lock has to be locked by the caller */
+static void _omap_dsi_set_irqs(void)
+{
+        u32 mask = DSI_IRQ_ERROR_MASK;
+#ifdef DSI_CATCH_MISSING_TE
+        mask |= DSI_IRQ_TE_TRIGGER;
 #endif
+        _omap_dsi_configure_irqs(dsi.isr_tables.isr_table,
+                        ARRAY_SIZE(dsi.isr_tables.isr_table), mask,
+                        DSI_IRQENABLE, DSI_IRQSTATUS);
+}
+
+/* dsi.irq_lock has to be locked by the caller */
+static void _omap_dsi_set_irqs_vc(int vc)
+{
+        _omap_dsi_configure_irqs(dsi.isr_tables.isr_table_vc[vc],
+                        ARRAY_SIZE(dsi.isr_tables.isr_table_vc[vc]),
+                        DSI_VC_IRQ_ERROR_MASK,
+                        DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
 }
 
+/* dsi.irq_lock has to be locked by the caller */
+static void _omap_dsi_set_irqs_cio(void)
+{
+        _omap_dsi_configure_irqs(dsi.isr_tables.isr_table_cio,
+                        ARRAY_SIZE(dsi.isr_tables.isr_table_cio),
+                        DSI_CIO_IRQ_ERROR_MASK,
+                        DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
+}
 
 static void _dsi_initialize_irq(void)
 {
-        u32 l;
+        unsigned long flags;
+        int vc;
+
+        spin_lock_irqsave(&dsi.irq_lock, flags);
+
+        memset(&dsi.isr_tables, 0, sizeof(dsi.isr_tables));
+
+        _omap_dsi_set_irqs();
+        for (vc = 0; vc < 4; ++vc)
+                _omap_dsi_set_irqs_vc(vc);
+        _omap_dsi_set_irqs_cio();
+
+        spin_unlock_irqrestore(&dsi.irq_lock, flags);
+}
+
+static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
+                struct dsi_isr_data *isr_array, unsigned isr_array_size)
+{
+        struct dsi_isr_data *isr_data;
+        int free_idx;
         int i;
 
-        /* disable all interrupts */
-        dsi_write_reg(DSI_IRQENABLE, 0);
-        for (i = 0; i < 4; ++i)
-                dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
-        dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
+        BUG_ON(isr == NULL);
 
-        /* clear interrupt status */
-        l = dsi_read_reg(DSI_IRQSTATUS);
-        dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
+        /* check for duplicate entry and find a free slot */
+        free_idx = -1;
+        for (i = 0; i < isr_array_size; i++) {
+                isr_data = &isr_array[i];
 
-        for (i = 0; i < 4; ++i) {
-                l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
-                dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
+                if (isr_data->isr == isr && isr_data->arg == arg &&
+                                isr_data->mask == mask) {
+                        return -EINVAL;
+                }
+
+                if (isr_data->isr == NULL && free_idx == -1)
+                        free_idx = i;
         }
 
-        l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
-        dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
+        if (free_idx == -1)
+                return -EBUSY;
 
-        /* enable error irqs */
-        l = DSI_IRQ_ERROR_MASK;
-#ifdef DSI_CATCH_MISSING_TE
-        l |= DSI_IRQ_TE_TRIGGER;
-#endif
-        dsi_write_reg(DSI_IRQENABLE, l);
+        isr_data = &isr_array[free_idx];
+        isr_data->isr = isr;
+        isr_data->arg = arg;
+        isr_data->mask = mask;
 
-        l = DSI_VC_IRQ_ERROR_MASK;
-        for (i = 0; i < 4; ++i)
-                dsi_write_reg(DSI_VC_IRQENABLE(i), l);
+        return 0;
+}
+
+static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
+                struct dsi_isr_data *isr_array, unsigned isr_array_size)
+{
+        struct dsi_isr_data *isr_data;
+        int i;
+
+        for (i = 0; i < isr_array_size; i++) {
+                isr_data = &isr_array[i];
+                if (isr_data->isr != isr || isr_data->arg != arg ||
+                                isr_data->mask != mask)
+                        continue;
+
+                isr_data->isr = NULL;
+                isr_data->arg = NULL;
+                isr_data->mask = 0;
+
+                return 0;
+        }
 
-        l = DSI_CIO_IRQ_ERROR_MASK;
-        dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, l);
+        return -EINVAL;
 }
 
-static u32 dsi_get_errors(void)
+static int dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask)
 {
         unsigned long flags;
-        u32 e;
-        spin_lock_irqsave(&dsi.errors_lock, flags);
-        e = dsi.errors;
-        dsi.errors = 0;
-        spin_unlock_irqrestore(&dsi.errors_lock, flags);
-        return e;
+        int r;
+
+        spin_lock_irqsave(&dsi.irq_lock, flags);
+
+        r = _dsi_register_isr(isr, arg, mask, dsi.isr_tables.isr_table,
+                        ARRAY_SIZE(dsi.isr_tables.isr_table));
+
+        if (r == 0)
+                _omap_dsi_set_irqs();
+
+        spin_unlock_irqrestore(&dsi.irq_lock, flags);
+
+        return r;
 }
 
-static void dsi_vc_enable_bta_irq(int channel)
+static int dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask)
 {
-        u32 l;
+        unsigned long flags;
+        int r;
+
+        spin_lock_irqsave(&dsi.irq_lock, flags);
+
+        r = _dsi_unregister_isr(isr, arg, mask, dsi.isr_tables.isr_table,
+                        ARRAY_SIZE(dsi.isr_tables.isr_table));
+
+        if (r == 0)
+                _omap_dsi_set_irqs();
 
-        dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
+        spin_unlock_irqrestore(&dsi.irq_lock, flags);
 
-        l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
-        l |= DSI_VC_IRQ_BTA;
-        dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
+        return r;
 }
 
-static void dsi_vc_disable_bta_irq(int channel)
+static int dsi_register_isr_vc(int channel, omap_dsi_isr_t isr, void *arg,
+                u32 mask)
 {
-        u32 l;
+        unsigned long flags;
+        int r;
+
+        spin_lock_irqsave(&dsi.irq_lock, flags);
+
+        r = _dsi_register_isr(isr, arg, mask,
+                        dsi.isr_tables.isr_table_vc[channel],
+                        ARRAY_SIZE(dsi.isr_tables.isr_table_vc[channel]));
+
+        if (r == 0)
+                _omap_dsi_set_irqs_vc(channel);
+
+        spin_unlock_irqrestore(&dsi.irq_lock, flags);
+
+        return r;
+}
+
+static int dsi_unregister_isr_vc(int channel, omap_dsi_isr_t isr, void *arg,
+                u32 mask)
+{
+        unsigned long flags;
+        int r;
+
+        spin_lock_irqsave(&dsi.irq_lock, flags);
+
+        r = _dsi_unregister_isr(isr, arg, mask,
+                        dsi.isr_tables.isr_table_vc[channel],
+                        ARRAY_SIZE(dsi.isr_tables.isr_table_vc[channel]));
+
+        if (r == 0)
+                _omap_dsi_set_irqs_vc(channel);
+
+        spin_unlock_irqrestore(&dsi.irq_lock, flags);
+
+        return r;
+}
+
+static int dsi_register_isr_cio(omap_dsi_isr_t isr, void *arg, u32 mask)
+{
+        unsigned long flags;
+        int r;
+
+        spin_lock_irqsave(&dsi.irq_lock, flags);
+
+        r = _dsi_register_isr(isr, arg, mask, dsi.isr_tables.isr_table_cio,
+                        ARRAY_SIZE(dsi.isr_tables.isr_table_cio));
+
+        if (r == 0)
+                _omap_dsi_set_irqs_cio();
+
+        spin_unlock_irqrestore(&dsi.irq_lock, flags);
+
+        return r;
+}
+
+static int dsi_unregister_isr_cio(omap_dsi_isr_t isr, void *arg, u32 mask)
+{
+        unsigned long flags;
+        int r;
+
+        spin_lock_irqsave(&dsi.irq_lock, flags);
+
+        r = _dsi_unregister_isr(isr, arg, mask, dsi.isr_tables.isr_table_cio,
+                        ARRAY_SIZE(dsi.isr_tables.isr_table_cio));
+
+        if (r == 0)
+                _omap_dsi_set_irqs_cio();
+
+        spin_unlock_irqrestore(&dsi.irq_lock, flags);
 
-        l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
-        l &= ~DSI_VC_IRQ_BTA;
-        dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
+        return r;
 }
 
-/* DSI func clock. this could also be DSI2_PLL_FCLK */
+static u32 dsi_get_errors(void)
+{
+        unsigned long flags;
+        u32 e;
+        spin_lock_irqsave(&dsi.errors_lock, flags);
+        e = dsi.errors;
+        dsi.errors = 0;
+        spin_unlock_irqrestore(&dsi.errors_lock, flags);
+        return e;
+}
+
+/* DSI func clock. this could also be dsi_pll_hsdiv_dsi_clk */
 static inline void enable_clocks(bool enable)
 {
         if (enable)
-                dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+                dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
         else
-                dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+                dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 }
 
 /* source clock for DSI PLL. this could also be PCLKFREE */
 static inline void dsi_enable_pll_clock(bool enable)
 {
         if (enable)
-                dss_clk_enable(DSS_CLK_FCK2);
+                dss_clk_enable(DSS_CLK_SYSCK);
         else
-                dss_clk_disable(DSS_CLK_FCK2);
+                dss_clk_disable(DSS_CLK_SYSCK);
 
         if (enable && dsi.pll_locked) {
                 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
@@ -707,14 +990,14 @@ static inline int dsi_if_enable(bool enable)
         return 0;
 }
 
-unsigned long dsi_get_dsi1_pll_rate(void)
+unsigned long dsi_get_pll_hsdiv_dispc_rate(void)
 {
-        return dsi.current_cinfo.dsi1_pll_fclk;
+        return dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk;
 }
 
-static unsigned long dsi_get_dsi2_pll_rate(void)
+static unsigned long dsi_get_pll_hsdiv_dsi_rate(void)
 {
-        return dsi.current_cinfo.dsi2_pll_fclk;
+        return dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk;
 }
 
 static unsigned long dsi_get_txbyteclkhs(void)
@@ -726,12 +1009,12 @@ static unsigned long dsi_fclk_rate(void)
 {
         unsigned long r;
 
-        if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) {
-                /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
-                r = dss_clk_get_rate(DSS_CLK_FCK1);
+        if (dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK) {
+                /* DSI FCLK source is DSS_CLK_FCK */
+                r = dss_clk_get_rate(DSS_CLK_FCK);
         } else {
-                /* DSI FCLK source is DSI2_PLL_FCLK */
-                r = dsi_get_dsi2_pll_rate();
+                /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
+                r = dsi_get_pll_hsdiv_dsi_rate();
         }
 
         return r;
@@ -745,7 +1028,7 @@ static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
 
         lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
 
-        if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX)
+        if (lp_clk_div == 0 || lp_clk_div > dsi.lpdiv_max)
                 return -EINVAL;
 
         dsi_fclk = dsi_fclk_rate();
@@ -795,22 +1078,22 @@ static int dsi_pll_power(enum dsi_pll_power_state state)
 static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
                 struct dsi_clock_info *cinfo)
 {
-        if (cinfo->regn == 0 || cinfo->regn > REGN_MAX)
+        if (cinfo->regn == 0 || cinfo->regn > dsi.regn_max)
                 return -EINVAL;
 
-        if (cinfo->regm == 0 || cinfo->regm > REGM_MAX)
+        if (cinfo->regm == 0 || cinfo->regm > dsi.regm_max)
                 return -EINVAL;
 
-        if (cinfo->regm3 > REGM3_MAX)
+        if (cinfo->regm_dispc > dsi.regm_dispc_max)
                 return -EINVAL;
 
-        if (cinfo->regm4 > REGM4_MAX)
+        if (cinfo->regm_dsi > dsi.regm_dsi_max)
                 return -EINVAL;
 
-        if (cinfo->use_dss2_fck) {
-                cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2);
+        if (cinfo->use_sys_clk) {
+                cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK);
                 /* XXX it is unclear if highfreq should be used
-                 * with DSS2_FCK source also */
+                 * with DSS_SYS_CLK source also */
                 cinfo->highfreq = 0;
         } else {
                 cinfo->clkin = dispc_pclk_rate(dssdev->manager->id);
@@ -823,7 +1106,7 @@ static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
 
         cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
 
-        if (cinfo->fint > FINT_MAX || cinfo->fint < FINT_MIN)
+        if (cinfo->fint > dsi.fint_max || cinfo->fint < dsi.fint_min)
                 return -EINVAL;
 
         cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
@@ -831,15 +1114,17 @@ static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
         if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
                 return -EINVAL;
 
-        if (cinfo->regm3 > 0)
-                cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3;
+        if (cinfo->regm_dispc > 0)
+                cinfo->dsi_pll_hsdiv_dispc_clk =
+                        cinfo->clkin4ddr / cinfo->regm_dispc;
         else
-                cinfo->dsi1_pll_fclk = 0;
+                cinfo->dsi_pll_hsdiv_dispc_clk = 0;
 
-        if (cinfo->regm4 > 0)
-                cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4;
+        if (cinfo->regm_dsi > 0)
+                cinfo->dsi_pll_hsdiv_dsi_clk =
+                        cinfo->clkin4ddr / cinfo->regm_dsi;
         else
-                cinfo->dsi2_pll_fclk = 0;
+                cinfo->dsi_pll_hsdiv_dsi_clk = 0;
 
         return 0;
 }
@@ -852,23 +1137,25 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
         struct dispc_clock_info best_dispc;
         int min_fck_per_pck;
         int match = 0;
-        unsigned long dss_clk_fck2;
+        unsigned long dss_sys_clk, max_dss_fck;
+
+        dss_sys_clk = dss_clk_get_rate(DSS_CLK_SYSCK);
 
-        dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);
+        max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 
         if (req_pck == dsi.cache_req_pck &&
-                        dsi.cache_cinfo.clkin == dss_clk_fck2) {
+                        dsi.cache_cinfo.clkin == dss_sys_clk) {
                 DSSDBG("DSI clock info found from cache\n");
                 *dsi_cinfo = dsi.cache_cinfo;
-                dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk,
-                                dispc_cinfo);
+                dispc_find_clk_divs(is_tft, req_pck,
+                        dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
                 return 0;
         }
 
         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
 
         if (min_fck_per_pck &&
-                req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
+                req_pck * min_fck_per_pck > max_dss_fck) {
                 DSSERR("Requested pixel clock not possible with the current "
                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
                                 "the constraint off.\n");
@@ -882,24 +1169,24 @@ retry:
         memset(&best_dispc, 0, sizeof(best_dispc));
 
         memset(&cur, 0, sizeof(cur));
-        cur.clkin = dss_clk_fck2;
-        cur.use_dss2_fck = 1;
+        cur.clkin = dss_sys_clk;
+        cur.use_sys_clk = 1;
         cur.highfreq = 0;
 
         /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
         /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
         /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
-        for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
+        for (cur.regn = 1; cur.regn < dsi.regn_max; ++cur.regn) {
                 if (cur.highfreq == 0)
                         cur.fint = cur.clkin / cur.regn;
                 else
                         cur.fint = cur.clkin / (2 * cur.regn);
 
-                if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
+                if (cur.fint > dsi.fint_max || cur.fint < dsi.fint_min)
                         continue;
 
                 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
-                for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
+                for (cur.regm = 1; cur.regm < dsi.regm_max; ++cur.regm) {
                         unsigned long a, b;
 
                         a = 2 * cur.regm * (cur.clkin/1000);
@@ -909,30 +1196,32 @@ retry:
                         if (cur.clkin4ddr > 1800 * 1000 * 1000)
                                 break;
 
-                        /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3  < 173MHz */
-                        for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
-                                        ++cur.regm3) {
+                        /* dsi_pll_hsdiv_dispc_clk(MHz) =
+                         * DSIPHY(MHz) / regm_dispc  < 173MHz/186Mhz */
+                        for (cur.regm_dispc = 1; cur.regm_dispc < dsi.regm_dispc_max;
+                                        ++cur.regm_dispc) {
                                 struct dispc_clock_info cur_dispc;
-                                cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3;
+                                cur.dsi_pll_hsdiv_dispc_clk =
+                                        cur.clkin4ddr / cur.regm_dispc;
 
                                 /* this will narrow down the search a bit,
                                  * but still give pixclocks below what was
                                  * requested */
-                                if (cur.dsi1_pll_fclk  < req_pck)
+                                if (cur.dsi_pll_hsdiv_dispc_clk  < req_pck)
                                         break;
 
-                                if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
+                                if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
                                         continue;
 
                                 if (min_fck_per_pck &&
-                                        cur.dsi1_pll_fclk <
+                                        cur.dsi_pll_hsdiv_dispc_clk <
                                                 req_pck * min_fck_per_pck)
                                         continue;
 
                                 match = 1;
 
                                 dispc_find_clk_divs(is_tft, req_pck,
-                                                cur.dsi1_pll_fclk,
+                                                cur.dsi_pll_hsdiv_dispc_clk,
                                                 &cur_dispc);
 
                                 if (abs(cur_dispc.pck - req_pck) <
@@ -961,9 +1250,9 @@ found:
                 return -EINVAL;
         }
 
-        /* DSI2_PLL_FCLK (regm4) is not used */
-        best.regm4 = 0;
-        best.dsi2_pll_fclk = 0;
+        /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
+        best.regm_dsi = 0;
+        best.dsi_pll_hsdiv_dsi_clk = 0;
 
         if (dsi_cinfo)
                 *dsi_cinfo = best;
@@ -982,23 +1271,27 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
         int r = 0;
         u32 l;
         int f;
+        u8 regn_start, regn_end, regm_start, regm_end;
+        u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
 
         DSSDBGF();
 
         dsi.current_cinfo.fint = cinfo->fint;
         dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
-        dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
-        dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
+        dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk =
+                        cinfo->dsi_pll_hsdiv_dispc_clk;
+        dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk =
+                        cinfo->dsi_pll_hsdiv_dsi_clk;
 
         dsi.current_cinfo.regn = cinfo->regn;
         dsi.current_cinfo.regm = cinfo->regm;
-        dsi.current_cinfo.regm3 = cinfo->regm3;
-        dsi.current_cinfo.regm4 = cinfo->regm4;
+        dsi.current_cinfo.regm_dispc = cinfo->regm_dispc;
+        dsi.current_cinfo.regm_dsi = cinfo->regm_dsi;
 
         DSSDBG("DSI Fint %ld\n", cinfo->fint);
 
         DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
-                        cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
+                        cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
                         cinfo->clkin,
                         cinfo->highfreq);
 
@@ -1015,24 +1308,39 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
 
         DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
 
-        DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
-                        cinfo->regm3, cinfo->dsi1_pll_fclk);
-        DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
-                        cinfo->regm4, cinfo->dsi2_pll_fclk);
+        DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
+                dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
+                dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
+                cinfo->dsi_pll_hsdiv_dispc_clk);
+        DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
+                dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
+                dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
+                cinfo->dsi_pll_hsdiv_dsi_clk);
+
+        dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
+        dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
+        dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
+                        &regm_dispc_end);
+        dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
+                        &regm_dsi_end);
 
         REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
 
         l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
         l = FLD_MOD(l, 1, 0, 0);                /* DSI_PLL_STOPMODE */
-        l = FLD_MOD(l, cinfo->regn - 1, 7, 1);  /* DSI_PLL_REGN */
-        l = FLD_MOD(l, cinfo->regm, 18, 8);     /* DSI_PLL_REGM */
-        l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0,
-                        22, 19);                /* DSI_CLOCK_DIV */
-        l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0,
-                        26, 23);                /* DSIPROTO_CLOCK_DIV */
+        /* DSI_PLL_REGN */
+        l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
+        /* DSI_PLL_REGM */
+        l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
+        /* DSI_CLOCK_DIV */
+        l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
+                        regm_dispc_start, regm_dispc_end);
+        /* DSIPROTO_CLOCK_DIV */
+        l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
+                        regm_dsi_start, regm_dsi_end);
         dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
 
-        BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000);
+        BUG_ON(cinfo->fint < dsi.fint_min || cinfo->fint > dsi.fint_max);
         if (cinfo->fint < 1000000)
                 f = 0x3;
         else if (cinfo->fint < 1250000)
@@ -1046,7 +1354,7 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
 
         l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
         l = FLD_MOD(l, f, 4, 1);                /* DSI_PLL_FREQSEL */
-        l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1,
+        l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
                         11, 11);                /* DSI_PLL_CLKSEL */
         l = FLD_MOD(l, cinfo->highfreq,
                         12, 12);                /* DSI_PLL_HIGHFREQ */
@@ -1101,6 +1409,26 @@ int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
 
         DSSDBG("PLL init\n");
 
+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
+        /*
+         * HACK: this is just a quick hack to get the USE_DSI_PLL
+         * option working. USE_DSI_PLL is itself a big hack, and
+         * should be removed.
+         */
+        if (dsi.vdds_dsi_reg == NULL) {
+                struct regulator *vdds_dsi;
+
+                vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi");
+
+                if (IS_ERR(vdds_dsi)) {
+                        DSSERR("can't get VDDS_DSI regulator\n");
+                        return PTR_ERR(vdds_dsi);
+                }
+
+                dsi.vdds_dsi_reg = vdds_dsi;
+        }
+#endif
+
         enable_clocks(1);
         dsi_enable_pll_clock(1);
 
@@ -1162,6 +1490,10 @@ void dsi_dump_clocks(struct seq_file *s)
 {
         int clksel;
         struct dsi_clock_info *cinfo = &dsi.current_cinfo;
+        enum dss_clk_source dispc_clk_src, dsi_clk_src;
+
+        dispc_clk_src = dss_get_dispc_clk_source();
+        dsi_clk_src = dss_get_dsi_clk_source();
 
         enable_clocks(1);
 
@@ -1171,30 +1503,34 @@ void dsi_dump_clocks(struct seq_file *s)
 
         seq_printf(s,   "dsi pll source = %s\n",
                         clksel == 0 ?
-                        "dss2_alwon_fclk" : "pclkfree");
+                        "dss_sys_clk" : "pclkfree");
 
         seq_printf(s,   "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
 
         seq_printf(s,   "CLKIN4DDR\t%-16luregm %u\n",
                         cinfo->clkin4ddr, cinfo->regm);
 
-        seq_printf(s,   "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
-                        cinfo->dsi1_pll_fclk,
-                        cinfo->regm3,
-                        dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
+        seq_printf(s,   "%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
+                        dss_get_generic_clk_source_name(dispc_clk_src),
+                        dss_feat_get_clk_source_name(dispc_clk_src),
+                        cinfo->dsi_pll_hsdiv_dispc_clk,
+                        cinfo->regm_dispc,
+                        dispc_clk_src == DSS_CLK_SRC_FCK ?
                         "off" : "on");
 
-        seq_printf(s,   "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
-                        cinfo->dsi2_pll_fclk,
-                        cinfo->regm4,
-                        dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
+        seq_printf(s,   "%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
+                        dss_get_generic_clk_source_name(dsi_clk_src),
+                        dss_feat_get_clk_source_name(dsi_clk_src),
+                        cinfo->dsi_pll_hsdiv_dsi_clk,
+                        cinfo->regm_dsi,
+                        dsi_clk_src == DSS_CLK_SRC_FCK ?
                         "off" : "on");
 
         seq_printf(s,   "- DSI -\n");
 
-        seq_printf(s,   "dsi fclk source = %s\n",
-                        dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
-                        "dss1_alwon_fclk" : "dsi2_pll_fclk");
+        seq_printf(s,   "dsi fclk source = %s (%s)\n",
+                        dss_get_generic_clk_source_name(dsi_clk_src),
+                        dss_feat_get_clk_source_name(dsi_clk_src));
 
         seq_printf(s,   "DSI_FCLK\t%lu\n", dsi_fclk_rate());
 
@@ -1306,7 +1642,7 @@ void dsi_dump_regs(struct seq_file *s)
 {
 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
 
-        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 
         DUMPREG(DSI_REVISION);
         DUMPREG(DSI_SYSCONFIG);
@@ -1378,7 +1714,7 @@ void dsi_dump_regs(struct seq_file *s)
         DUMPREG(DSI_PLL_CONFIGURATION1);
         DUMPREG(DSI_PLL_CONFIGURATION2);
 
-        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 #undef DUMPREG
 }
 
@@ -1622,20 +1958,6 @@ static int _dsi_reset(void)
         return _dsi_wait_reset();
 }
 
-static void dsi_reset_tx_fifo(int channel)
-{
-        u32 mask;
-        u32 l;
-
-        /* set fifosize of the channel to 0, then return the old size */
-        l = dsi_read_reg(DSI_TX_FIFO_VC_SIZE);
-
-        mask = FLD_MASK((8 * channel) + 7, (8 * channel) + 4);
-        dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l & ~mask);
-
-        dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l);
-}
-
 static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
                 enum fifo_size size3, enum fifo_size size4)
 {
@@ -1753,8 +2075,6 @@ static void dsi_vc_initial_config(int channel)
         r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
 
         dsi_write_reg(DSI_VC_CTRL(channel), r);
-
-        dsi.vc[channel].mode = DSI_VC_MODE_L4;
 }
 
 static int dsi_vc_config_l4(int channel)
@@ -1922,33 +2242,44 @@ static int dsi_vc_send_bta(int channel)
 
 int dsi_vc_send_bta_sync(int channel)
 {
+        DECLARE_COMPLETION_ONSTACK(completion);
         int r = 0;
         u32 err;
 
-        INIT_COMPLETION(dsi.bta_completion);
+        r = dsi_register_isr_vc(channel, dsi_completion_handler,
+                        &completion, DSI_VC_IRQ_BTA);
+        if (r)
+                goto err0;
 
-        dsi_vc_enable_bta_irq(channel);
+        r = dsi_register_isr(dsi_completion_handler, &completion,
+                        DSI_IRQ_ERROR_MASK);
+        if (r)
+                goto err1;
 
         r = dsi_vc_send_bta(channel);
         if (r)
-                goto err;
+                goto err2;
 
-        if (wait_for_completion_timeout(&dsi.bta_completion,
+        if (wait_for_completion_timeout(&completion,
                                 msecs_to_jiffies(500)) == 0) {
                 DSSERR("Failed to receive BTA\n");
                 r = -EIO;
-                goto err;
+                goto err2;
         }
 
         err = dsi_get_errors();
         if (err) {
                 DSSERR("Error while sending BTA: %x\n", err);
                 r = -EIO;
-                goto err;
+                goto err2;
         }
-err:
-        dsi_vc_disable_bta_irq(channel);
-
+err2:
+        dsi_unregister_isr(dsi_completion_handler, &completion,
+                        DSI_IRQ_ERROR_MASK);
+err1:
+        dsi_unregister_isr_vc(channel, dsi_completion_handler,
+                        &completion, DSI_VC_IRQ_BTA);
+err0:
         return r;
 }
 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
@@ -1961,7 +2292,7 @@ static inline void dsi_vc_write_long_header(int channel, u8 data_type,
 
         WARN_ON(!dsi_bus_is_locked());
 
-        data_id = data_type | channel << 6;
+        data_id = data_type | dsi.vc[channel].vc_id << 6;
 
         val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
                 FLD_VAL(ecc, 31, 24);
@@ -2064,7 +2395,7 @@ static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
                 return -EINVAL;
         }
 
-        data_id = data_type | channel << 6;
+        data_id = data_type | dsi.vc[channel].vc_id << 6;
 
         r = (data_id << 0) | (data << 8) | (ecc << 24);
 
@@ -2762,19 +3093,20 @@ static void dsi_te_timeout(unsigned long arg)
 }
 #endif
 
+static void dsi_framedone_bta_callback(void *data, u32 mask);
+
 static void dsi_handle_framedone(int error)
 {
         const int channel = dsi.update_channel;
 
-        cancel_delayed_work(&dsi.framedone_timeout_work);
+        dsi_unregister_isr_vc(channel, dsi_framedone_bta_callback,
+                        NULL, DSI_VC_IRQ_BTA);
 
-        dsi_vc_disable_bta_irq(channel);
+        cancel_delayed_work(&dsi.framedone_timeout_work);
 
         /* SIDLEMODE back to smart-idle */
         dispc_enable_sidle();
 
-        dsi.bta_callback = NULL;
-
         if (dsi.te_enabled) {
                 /* enable LP_RX_TO again after the TE */
                 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
@@ -2808,7 +3140,7 @@ static void dsi_framedone_timeout_work_callback(struct work_struct *work)
         dsi_handle_framedone(-ETIMEDOUT);
 }
 
-static void dsi_framedone_bta_callback(void)
+static void dsi_framedone_bta_callback(void *data, u32 mask)
 {
         dsi_handle_framedone(0);
 
@@ -2848,15 +3180,19 @@ static void dsi_framedone_irq_callback(void *data, u32 mask)
          * asynchronously.
          * */
 
-        dsi.bta_callback = dsi_framedone_bta_callback;
-
-        barrier();
-
-        dsi_vc_enable_bta_irq(channel);
+        r = dsi_register_isr_vc(channel, dsi_framedone_bta_callback,
+                        NULL, DSI_VC_IRQ_BTA);
+        if (r) {
+                DSSERR("Failed to register BTA ISR\n");
+                dsi_handle_framedone(-EIO);
+                return;
+        }
 
         r = dsi_vc_send_bta(channel);
         if (r) {
                 DSSERR("BTA after framedone failed\n");
+                dsi_unregister_isr_vc(channel, dsi_framedone_bta_callback,
+                                NULL, DSI_VC_IRQ_BTA);
                 dsi_handle_framedone(-EIO);
         }
 }
@@ -2984,12 +3320,12 @@ static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
         struct dsi_clock_info cinfo;
         int r;
 
-        /* we always use DSS2_FCK as input clock */
-        cinfo.use_dss2_fck = true;
+        /* we always use DSS_CLK_SYSCK as input clock */
+        cinfo.use_sys_clk = true;
         cinfo.regn  = dssdev->phy.dsi.div.regn;
         cinfo.regm  = dssdev->phy.dsi.div.regm;
-        cinfo.regm3 = dssdev->phy.dsi.div.regm3;
-        cinfo.regm4 = dssdev->phy.dsi.div.regm4;
+        cinfo.regm_dispc = dssdev->phy.dsi.div.regm_dispc;
+        cinfo.regm_dsi = dssdev->phy.dsi.div.regm_dsi;
         r = dsi_calc_clock_rates(dssdev, &cinfo);
         if (r) {
                 DSSERR("Failed to calc dsi clocks\n");
@@ -3011,7 +3347,7 @@ static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
         int r;
         unsigned long long fck;
 
-        fck = dsi_get_dsi1_pll_rate();
+        fck = dsi_get_pll_hsdiv_dispc_rate();
 
         dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
         dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
@@ -3045,8 +3381,8 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
         if (r)
                 goto err1;
 
-        dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
-        dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK);
+        dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);
+        dss_select_dsi_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI);
 
         DSSDBG("PLL OK\n");
 
@@ -3082,8 +3418,8 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
 err3:
         dsi_complexio_uninit();
 err2:
-        dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
-        dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
+        dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
+        dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);
 err1:
         dsi_pll_uninit();
 err0:
@@ -3099,8 +3435,8 @@ static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
         dsi_vc_enable(2, 0);
         dsi_vc_enable(3, 0);
 
-        dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
-        dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
+        dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
+        dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);
         dsi_complexio_uninit();
         dsi_pll_uninit();
 }
@@ -3220,29 +3556,107 @@ int dsi_init_display(struct omap_dss_device *dssdev)
         dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
                 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
 
-        dsi.vc[0].dssdev = dssdev;
-        dsi.vc[1].dssdev = dssdev;
+        if (dsi.vdds_dsi_reg == NULL) {
+                struct regulator *vdds_dsi;
+
+                vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi");
+
+                if (IS_ERR(vdds_dsi)) {
+                        DSSERR("can't get VDDS_DSI regulator\n");
+                        return PTR_ERR(vdds_dsi);
+                }
+
+                dsi.vdds_dsi_reg = vdds_dsi;
+        }
 
         return 0;
 }
 
-void dsi_wait_dsi1_pll_active(void)
+int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) {
+                if (!dsi.vc[i].dssdev) {
+                        dsi.vc[i].dssdev = dssdev;
+                        *channel = i;
+                        return 0;
+                }
+        }
+
+        DSSERR("cannot get VC for display %s", dssdev->name);
+        return -ENOSPC;
+}
+EXPORT_SYMBOL(omap_dsi_request_vc);
+
+int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
+{
+        if (vc_id < 0 || vc_id > 3) {
+                DSSERR("VC ID out of range\n");
+                return -EINVAL;
+        }
+
+        if (channel < 0 || channel > 3) {
+                DSSERR("Virtual Channel out of range\n");
+                return -EINVAL;
+        }
+
+        if (dsi.vc[channel].dssdev != dssdev) {
+                DSSERR("Virtual Channel not allocated to display %s\n",
+                        dssdev->name);
+                return -EINVAL;
+        }
+
+        dsi.vc[channel].vc_id = vc_id;
+
+        return 0;
+}
+EXPORT_SYMBOL(omap_dsi_set_vc_id);
+
+void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
+{
+        if ((channel >= 0 && channel <= 3) &&
+                dsi.vc[channel].dssdev == dssdev) {
+                dsi.vc[channel].dssdev = NULL;
+                dsi.vc[channel].vc_id = 0;
+        }
+}
+EXPORT_SYMBOL(omap_dsi_release_vc);
+
+void dsi_wait_pll_hsdiv_dispc_active(void)
 {
         if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)
-                DSSERR("DSI1 PLL clock not active\n");
+                DSSERR("%s (%s) not active\n",
+                        dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
+                        dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
 }
 
-void dsi_wait_dsi2_pll_active(void)
+void dsi_wait_pll_hsdiv_dsi_active(void)
 {
         if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)
-                DSSERR("DSI2 PLL clock not active\n");
+                DSSERR("%s (%s) not active\n",
+                        dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
+                        dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
+}
+
+static void dsi_calc_clock_param_ranges(void)
+{
+        dsi.regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
+        dsi.regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
+        dsi.regm_dispc_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
+        dsi.regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
+        dsi.fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
+        dsi.fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
+        dsi.lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
 }
 
-int dsi_init(struct platform_device *pdev)
+static int dsi_init(struct platform_device *pdev)
 {
         u32 rev;
-        int r;
+        int r, i;
+        struct resource *dsi_mem;
 
+        spin_lock_init(&dsi.irq_lock);
         spin_lock_init(&dsi.errors_lock);
         dsi.errors = 0;
 
@@ -3251,8 +3665,6 @@ int dsi_init(struct platform_device *pdev)
         dsi.irq_stats.last_reset = jiffies;
 #endif
 
-        init_completion(&dsi.bta_completion);
-
         mutex_init(&dsi.lock);
         sema_init(&dsi.bus_lock, 1);
 
@@ -3268,24 +3680,45 @@ int dsi_init(struct platform_device *pdev)
         dsi.te_timer.function = dsi_te_timeout;
         dsi.te_timer.data = 0;
 #endif
-        dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS);
+        dsi_mem = platform_get_resource(dsi.pdev, IORESOURCE_MEM, 0);
+        if (!dsi_mem) {
+                DSSERR("can't get IORESOURCE_MEM DSI\n");
+                r = -EINVAL;
+                goto err1;
+        }
+        dsi.base = ioremap(dsi_mem->start, resource_size(dsi_mem));
         if (!dsi.base) {
                 DSSERR("can't ioremap DSI\n");
                 r = -ENOMEM;
                 goto err1;
         }
+        dsi.irq = platform_get_irq(dsi.pdev, 0);
+        if (dsi.irq < 0) {
+                DSSERR("platform_get_irq failed\n");
+                r = -ENODEV;
+                goto err2;
+        }
 
-        dsi.vdds_dsi_reg = dss_get_vdds_dsi();
-        if (IS_ERR(dsi.vdds_dsi_reg)) {
-                DSSERR("can't get VDDS_DSI regulator\n");
-                r = PTR_ERR(dsi.vdds_dsi_reg);
+        r = request_irq(dsi.irq, omap_dsi_irq_handler, IRQF_SHARED,
+                "OMAP DSI1", dsi.pdev);
+        if (r < 0) {
+                DSSERR("request_irq failed\n");
                 goto err2;
         }
 
+        /* DSI VCs initialization */
+        for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) {
+                dsi.vc[i].mode = DSI_VC_MODE_L4;
+                dsi.vc[i].dssdev = NULL;
+                dsi.vc[i].vc_id = 0;
+        }
+
+        dsi_calc_clock_param_ranges();
+
         enable_clocks(1);
 
         rev = dsi_read_reg(DSI_REVISION);
-        printk(KERN_INFO "OMAP DSI rev %d.%d\n",
+        dev_dbg(&pdev->dev, "OMAP DSI rev %d.%d\n",
                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
 
         enable_clocks(0);
@@ -3298,8 +3731,14 @@ err1:
         return r;
 }
 
-void dsi_exit(void)
+static void dsi_exit(void)
 {
+        if (dsi.vdds_dsi_reg != NULL) {
+                regulator_put(dsi.vdds_dsi_reg);
+                dsi.vdds_dsi_reg = NULL;
+        }
+
+        free_irq(dsi.irq, dsi.pdev);
         iounmap(dsi.base);
 
         destroy_workqueue(dsi.workqueue);
@@ -3307,3 +3746,41 @@ void dsi_exit(void)
         DSSDBG("omap_dsi_exit\n");
 }
 
+/* DSI1 HW IP initialisation */
+static int omap_dsi1hw_probe(struct platform_device *pdev)
+{
+        int r;
+        dsi.pdev = pdev;
+        r = dsi_init(pdev);
+        if (r) {
+                DSSERR("Failed to initialize DSI\n");
+                goto err_dsi;
+        }
+err_dsi:
+        return r;
+}
+
+static int omap_dsi1hw_remove(struct platform_device *pdev)
+{
+        dsi_exit();
+        return 0;
+}
+
+static struct platform_driver omap_dsi1hw_driver = {
+        .probe          = omap_dsi1hw_probe,
+        .remove         = omap_dsi1hw_remove,
+        .driver         = {
+                .name   = "omapdss_dsi1",
+                .owner  = THIS_MODULE,
+        },
+};
+
+int dsi_init_platform_driver(void)
+{
+        return platform_driver_register(&omap_dsi1hw_driver);
+}
+
+void dsi_uninit_platform_driver(void)
+{
+        return platform_driver_unregister(&omap_dsi1hw_driver);
+}
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 77c3621c9171..3f1fee63c678 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -26,14 +26,13 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/delay.h>
-#include <linux/interrupt.h>
 #include <linux/seq_file.h>
 #include <linux/clk.h>
 
 #include <plat/display.h>
+#include <plat/clock.h>
 #include "dss.h"
-
-#define DSS_BASE                        0x48050000
+#include "dss_features.h"
 
 #define DSS_SZ_REGS                     SZ_512
 
@@ -59,9 +58,17 @@ struct dss_reg {
         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
 
 static struct {
+        struct platform_device *pdev;
         void __iomem    *base;
+        int             ctx_id;
 
         struct clk      *dpll4_m4_ck;
+        struct clk      *dss_ick;
+        struct clk      *dss_fck;
+        struct clk      *dss_sys_clk;
+        struct clk      *dss_tv_fck;
+        struct clk      *dss_video_fck;
+        unsigned        num_clks_enabled;
 
         unsigned long   cache_req_pck;
         unsigned long   cache_prate;
@@ -70,10 +77,22 @@ static struct {
 
         enum dss_clk_source dsi_clk_source;
         enum dss_clk_source dispc_clk_source;
+        enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
 
         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
 } dss;
 
+static const char * const dss_generic_clk_source_names[] = {
+        [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]       = "DSI_PLL_HSDIV_DISPC",
+        [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]         = "DSI_PLL_HSDIV_DSI",
+        [DSS_CLK_SRC_FCK]                       = "DSS_FCK",
+};
+
+static void dss_clk_enable_all_no_ctx(void);
+static void dss_clk_disable_all_no_ctx(void);
+static void dss_clk_enable_no_ctx(enum dss_clock clks);
+static void dss_clk_disable_no_ctx(enum dss_clock clks);
+
 static int _omap_dss_wait_reset(void);
 
 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
@@ -99,10 +118,11 @@ void dss_save_context(void)
         SR(SYSCONFIG);
         SR(CONTROL);
 
-#ifdef CONFIG_OMAP2_DSS_SDI
-        SR(SDI_CONTROL);
-        SR(PLL_CONTROL);
-#endif
+        if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
+                        OMAP_DISPLAY_TYPE_SDI) {
+                SR(SDI_CONTROL);
+                SR(PLL_CONTROL);
+        }
 }
 
 void dss_restore_context(void)
@@ -113,10 +133,11 @@ void dss_restore_context(void)
         RR(SYSCONFIG);
         RR(CONTROL);
 
-#ifdef CONFIG_OMAP2_DSS_SDI
-        RR(SDI_CONTROL);
-        RR(PLL_CONTROL);
-#endif
+        if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
+                        OMAP_DISPLAY_TYPE_SDI) {
+                RR(SDI_CONTROL);
+                RR(PLL_CONTROL);
+        }
 }
 
 #undef SR
@@ -209,66 +230,96 @@ void dss_sdi_disable(void)
         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 }
 
+const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src)
+{
+        return dss_generic_clk_source_names[clk_src];
+}
+
 void dss_dump_clocks(struct seq_file *s)
 {
         unsigned long dpll4_ck_rate;
         unsigned long dpll4_m4_ck_rate;
+        const char *fclk_name, *fclk_real_name;
+        unsigned long fclk_rate;
 
-        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
-
-        dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
-        dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
+        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 
         seq_printf(s, "- DSS -\n");
 
-        seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
+        fclk_name = dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK);
+        fclk_real_name = dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK);
+        fclk_rate = dss_clk_get_rate(DSS_CLK_FCK);
 
-        if (cpu_is_omap3630())
-                seq_printf(s, "dss1_alwon_fclk = %lu / %lu  = %lu\n",
-                        dpll4_ck_rate,
-                        dpll4_ck_rate / dpll4_m4_ck_rate,
-                        dss_clk_get_rate(DSS_CLK_FCK1));
-        else
-                seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
-                        dpll4_ck_rate,
-                        dpll4_ck_rate / dpll4_m4_ck_rate,
-                        dss_clk_get_rate(DSS_CLK_FCK1));
+        if (dss.dpll4_m4_ck) {
+                dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
+                dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
+
+                seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
 
-        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+                if (cpu_is_omap3630() || cpu_is_omap44xx())
+                        seq_printf(s, "%s (%s) = %lu / %lu  = %lu\n",
+                                        fclk_name, fclk_real_name,
+                                        dpll4_ck_rate,
+                                        dpll4_ck_rate / dpll4_m4_ck_rate,
+                                        fclk_rate);
+                else
+                        seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
+                                        fclk_name, fclk_real_name,
+                                        dpll4_ck_rate,
+                                        dpll4_ck_rate / dpll4_m4_ck_rate,
+                                        fclk_rate);
+        } else {
+                seq_printf(s, "%s (%s) = %lu\n",
+                                fclk_name, fclk_real_name,
+                                fclk_rate);
+        }
+
+        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 }
 
 void dss_dump_regs(struct seq_file *s)
 {
 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 
-        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 
         DUMPREG(DSS_REVISION);
         DUMPREG(DSS_SYSCONFIG);
         DUMPREG(DSS_SYSSTATUS);
         DUMPREG(DSS_IRQSTATUS);
         DUMPREG(DSS_CONTROL);
-        DUMPREG(DSS_SDI_CONTROL);
-        DUMPREG(DSS_PLL_CONTROL);
-        DUMPREG(DSS_SDI_STATUS);
 
-        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
+                        OMAP_DISPLAY_TYPE_SDI) {
+                DUMPREG(DSS_SDI_CONTROL);
+                DUMPREG(DSS_PLL_CONTROL);
+                DUMPREG(DSS_SDI_STATUS);
+        }
+
+        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 #undef DUMPREG
 }
 
 void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
 {
         int b;
+        u8 start, end;
+
+        switch (clk_src) {
+        case DSS_CLK_SRC_FCK:
+                b = 0;
+                break;
+        case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
+                b = 1;
+                dsi_wait_pll_hsdiv_dispc_active();
+                break;
+        default:
+                BUG();
+        }
 
-        BUG_ON(clk_src != DSS_SRC_DSI1_PLL_FCLK &&
-                        clk_src != DSS_SRC_DSS1_ALWON_FCLK);
-
-        b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
-
-        if (clk_src == DSS_SRC_DSI1_PLL_FCLK)
-                dsi_wait_dsi1_pll_active();
+        dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
 
-        REG_FLD_MOD(DSS_CONTROL, b, 0, 0);      /* DISPC_CLK_SWITCH */
+        REG_FLD_MOD(DSS_CONTROL, b, start, end);        /* DISPC_CLK_SWITCH */
 
         dss.dispc_clk_source = clk_src;
 }
@@ -277,19 +328,51 @@ void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
 {
         int b;
 
-        BUG_ON(clk_src != DSS_SRC_DSI2_PLL_FCLK &&
-                        clk_src != DSS_SRC_DSS1_ALWON_FCLK);
-
-        b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
-
-        if (clk_src == DSS_SRC_DSI2_PLL_FCLK)
-                dsi_wait_dsi2_pll_active();
+        switch (clk_src) {
+        case DSS_CLK_SRC_FCK:
+                b = 0;
+                break;
+        case DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
+                b = 1;
+                dsi_wait_pll_hsdiv_dsi_active();
+                break;
+        default:
+                BUG();
+        }
 
         REG_FLD_MOD(DSS_CONTROL, b, 1, 1);      /* DSI_CLK_SWITCH */
 
         dss.dsi_clk_source = clk_src;
 }
 
+void dss_select_lcd_clk_source(enum omap_channel channel,
+                enum dss_clk_source clk_src)
+{
+        int b, ix, pos;
+
+        if (!dss_has_feature(FEAT_LCD_CLK_SRC))
+                return;
+
+        switch (clk_src) {
+        case DSS_CLK_SRC_FCK:
+                b = 0;
+                break;
+        case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
+                BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
+                b = 1;
+                dsi_wait_pll_hsdiv_dispc_active();
+                break;
+        default:
+                BUG();
+        }
+
+        pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12;
+        REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* LCDx_CLK_SWITCH */
+
+        ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
+        dss.lcd_clk_source[ix] = clk_src;
+}
+
 enum dss_clk_source dss_get_dispc_clk_source(void)
 {
         return dss.dispc_clk_source;
@@ -300,34 +383,52 @@ enum dss_clk_source dss_get_dsi_clk_source(void)
         return dss.dsi_clk_source;
 }
 
+enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
+{
+        int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
+        return dss.lcd_clk_source[ix];
+}
+
 /* calculate clock rates using dividers in cinfo */
 int dss_calc_clock_rates(struct dss_clock_info *cinfo)
 {
-        unsigned long prate;
+        if (dss.dpll4_m4_ck) {
+                unsigned long prate;
+                u16 fck_div_max = 16;
 
-        if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) ||
-                                                cinfo->fck_div == 0)
-                return -EINVAL;
+                if (cpu_is_omap3630() || cpu_is_omap44xx())
+                        fck_div_max = 32;
+
+                if (cinfo->fck_div > fck_div_max || cinfo->fck_div == 0)
+                        return -EINVAL;
 
-        prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
+                prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 
-        cinfo->fck = prate / cinfo->fck_div;
+                cinfo->fck = prate / cinfo->fck_div;
+        } else {
+                if (cinfo->fck_div != 0)
+                        return -EINVAL;
+                cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
+        }
 
         return 0;
 }
 
 int dss_set_clock_div(struct dss_clock_info *cinfo)
 {
-        unsigned long prate;
-        int r;
+        if (dss.dpll4_m4_ck) {
+                unsigned long prate;
+                int r;
 
-        if (cpu_is_omap34xx()) {
                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
                 DSSDBG("dpll4_m4 = %ld\n", prate);
 
                 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
                 if (r)
                         return r;
+        } else {
+                if (cinfo->fck_div != 0)
+                        return -EINVAL;
         }
 
         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
@@ -337,12 +438,14 @@ int dss_set_clock_div(struct dss_clock_info *cinfo)
 
 int dss_get_clock_div(struct dss_clock_info *cinfo)
 {
-        cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
+        cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
 
-        if (cpu_is_omap34xx()) {
+        if (dss.dpll4_m4_ck) {
                 unsigned long prate;
+
                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
-                if (cpu_is_omap3630())
+
+                if (cpu_is_omap3630() || cpu_is_omap44xx())
                         cinfo->fck_div = prate / (cinfo->fck);
                 else
                         cinfo->fck_div = prate / (cinfo->fck / 2);
@@ -355,7 +458,7 @@ int dss_get_clock_div(struct dss_clock_info *cinfo)
 
 unsigned long dss_get_dpll4_rate(void)
 {
-        if (cpu_is_omap34xx())
+        if (dss.dpll4_m4_ck)
                 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
         else
                 return 0;
@@ -369,16 +472,18 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
         struct dss_clock_info best_dss;
         struct dispc_clock_info best_dispc;
 
-        unsigned long fck;
+        unsigned long fck, max_dss_fck;
 
-        u16 fck_div;
+        u16 fck_div, fck_div_max = 16;
 
         int match = 0;
         int min_fck_per_pck;
 
         prate = dss_get_dpll4_rate();
 
-        fck = dss_clk_get_rate(DSS_CLK_FCK1);
+        max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
+
+        fck = dss_clk_get_rate(DSS_CLK_FCK);
         if (req_pck == dss.cache_req_pck &&
                         ((cpu_is_omap34xx() && prate == dss.cache_prate) ||
                          dss.cache_dss_cinfo.fck == fck)) {
@@ -391,7 +496,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
 
         if (min_fck_per_pck &&
-                req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
+                req_pck * min_fck_per_pck > max_dss_fck) {
                 DSSERR("Requested pixel clock not possible with the current "
                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
                                 "the constraint off.\n");
@@ -402,10 +507,10 @@ retry:
         memset(&best_dss, 0, sizeof(best_dss));
         memset(&best_dispc, 0, sizeof(best_dispc));
 
-        if (cpu_is_omap24xx()) {
+        if (dss.dpll4_m4_ck == NULL) {
                 struct dispc_clock_info cur_dispc;
                 /* XXX can we change the clock on omap2? */
-                fck = dss_clk_get_rate(DSS_CLK_FCK1);
+                fck = dss_clk_get_rate(DSS_CLK_FCK);
                 fck_div = 1;
 
                 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
@@ -417,17 +522,19 @@ retry:
                 best_dispc = cur_dispc;
 
                 goto found;
-        } else if (cpu_is_omap34xx()) {
-                for (fck_div = (cpu_is_omap3630() ? 32 : 16);
-                                        fck_div > 0; --fck_div) {
+        } else {
+                if (cpu_is_omap3630() || cpu_is_omap44xx())
+                        fck_div_max = 32;
+
+                for (fck_div = fck_div_max; fck_div > 0; --fck_div) {
                         struct dispc_clock_info cur_dispc;
 
-                        if (cpu_is_omap3630())
+                        if (fck_div_max == 32)
                                 fck = prate / fck_div;
                         else
                                 fck = prate / fck_div * 2;
 
-                        if (fck > DISPC_MAX_FCK)
+                        if (fck > max_dss_fck)
                                 continue;
 
                         if (min_fck_per_pck &&
@@ -450,8 +557,6 @@ retry:
                                         goto found;
                         }
                 }
-        } else {
-                BUG();
         }
 
 found:
@@ -482,31 +587,6 @@ found:
         return 0;
 }
 
-
-
-static irqreturn_t dss_irq_handler_omap2(int irq, void *arg)
-{
-        dispc_irq_handler();
-
-        return IRQ_HANDLED;
-}
-
-static irqreturn_t dss_irq_handler_omap3(int irq, void *arg)
-{
-        u32 irqstatus;
-
-        irqstatus = dss_read_reg(DSS_IRQSTATUS);
-
-        if (irqstatus & (1<<0)) /* DISPC_IRQ */
-                dispc_irq_handler();
-#ifdef CONFIG_OMAP2_DSS_DSI
-        if (irqstatus & (1<<1)) /* DSI_IRQ */
-                dsi_irq_handler();
-#endif
-
-        return IRQ_HANDLED;
-}
-
 static int _omap_dss_wait_reset(void)
 {
         int t = 0;
@@ -549,34 +629,45 @@ void dss_set_dac_pwrdn_bgz(bool enable)
         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 }
 
-int dss_init(bool skip_init)
+void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi)
+{
+        REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */
+}
+
+static int dss_init(void)
 {
         int r;
         u32 rev;
+        struct resource *dss_mem;
+        struct clk *dpll4_m4_ck;
 
-        dss.base = ioremap(DSS_BASE, DSS_SZ_REGS);
+        dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
+        if (!dss_mem) {
+                DSSERR("can't get IORESOURCE_MEM DSS\n");
+                r = -EINVAL;
+                goto fail0;
+        }
+        dss.base = ioremap(dss_mem->start, resource_size(dss_mem));
         if (!dss.base) {
                 DSSERR("can't ioremap DSS\n");
                 r = -ENOMEM;
                 goto fail0;
         }
 
-        if (!skip_init) {
-                /* disable LCD and DIGIT output. This seems to fix the synclost
-                 * problem that we get, if the bootloader starts the DSS and
-                 * the kernel resets it */
-                omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
+        /* disable LCD and DIGIT output. This seems to fix the synclost
+         * problem that we get, if the bootloader starts the DSS and
+         * the kernel resets it */
+        omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
 
-                /* We need to wait here a bit, otherwise we sometimes start to
-                 * get synclost errors, and after that only power cycle will
-                 * restore DSS functionality. I have no idea why this happens.
-                 * And we have to wait _before_ resetting the DSS, but after
-                 * enabling clocks.
-                 */
-                msleep(50);
+        /* We need to wait here a bit, otherwise we sometimes start to
+         * get synclost errors, and after that only power cycle will
+         * restore DSS functionality. I have no idea why this happens.
+         * And we have to wait _before_ resetting the DSS, but after
+         * enabling clocks.
+         */
+        msleep(50);
 
-                _omap_dss_reset();
-        }
+        _omap_dss_reset();
 
         /* autoidle */
         REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
@@ -589,29 +680,30 @@ int dss_init(bool skip_init)
         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
 #endif
-
-        r = request_irq(INT_24XX_DSS_IRQ,
-                        cpu_is_omap24xx()
-                        ? dss_irq_handler_omap2
-                        : dss_irq_handler_omap3,
-                        0, "OMAP DSS", NULL);
-
-        if (r < 0) {
-                DSSERR("omap2 dss: request_irq failed\n");
-                goto fail1;
-        }
-
         if (cpu_is_omap34xx()) {
-                dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
-                if (IS_ERR(dss.dpll4_m4_ck)) {
+                dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
+                if (IS_ERR(dpll4_m4_ck)) {
                         DSSERR("Failed to get dpll4_m4_ck\n");
-                        r = PTR_ERR(dss.dpll4_m4_ck);
-                        goto fail2;
+                        r = PTR_ERR(dpll4_m4_ck);
+                        goto fail1;
                 }
+        } else if (cpu_is_omap44xx()) {
+                dpll4_m4_ck = clk_get(NULL, "dpll_per_m5x2_ck");
+                if (IS_ERR(dpll4_m4_ck)) {
+                        DSSERR("Failed to get dpll4_m4_ck\n");
+                        r = PTR_ERR(dpll4_m4_ck);
+                        goto fail1;
+                }
+        } else { /* omap24xx */
+                dpll4_m4_ck = NULL;
         }
 
-        dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
-        dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
+        dss.dpll4_m4_ck = dpll4_m4_ck;
+
+        dss.dsi_clk_source = DSS_CLK_SRC_FCK;
+        dss.dispc_clk_source = DSS_CLK_SRC_FCK;
+        dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK;
+        dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK;
 
         dss_save_context();
 
@@ -621,21 +713,416 @@ int dss_init(bool skip_init)
 
         return 0;
 
-fail2:
-        free_irq(INT_24XX_DSS_IRQ, NULL);
 fail1:
         iounmap(dss.base);
 fail0:
         return r;
 }
 
-void dss_exit(void)
+static void dss_exit(void)
 {
-        if (cpu_is_omap34xx())
+        if (dss.dpll4_m4_ck)
                 clk_put(dss.dpll4_m4_ck);
 
-        free_irq(INT_24XX_DSS_IRQ, NULL);
-
         iounmap(dss.base);
 }
 
+/* CONTEXT */
+static int dss_get_ctx_id(void)
+{
+        struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
+        int r;
+
+        if (!pdata->board_data->get_last_off_on_transaction_id)
+                return 0;
+        r = pdata->board_data->get_last_off_on_transaction_id(&dss.pdev->dev);
+        if (r < 0) {
+                dev_err(&dss.pdev->dev, "getting transaction ID failed, "
+                                "will force context restore\n");
+                r = -1;
+        }
+        return r;
+}
+
+int dss_need_ctx_restore(void)
+{
+        int id = dss_get_ctx_id();
+
+        if (id < 0 || id != dss.ctx_id) {
+                DSSDBG("ctx id %d -> id %d\n",
+                                dss.ctx_id, id);
+                dss.ctx_id = id;
+                return 1;
+        } else {
+                return 0;
+        }
+}
+
+static void save_all_ctx(void)
+{
+        DSSDBG("save context\n");
+
+        dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
+
+        dss_save_context();
+        dispc_save_context();
+#ifdef CONFIG_OMAP2_DSS_DSI
+        dsi_save_context();
+#endif
+
+        dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
+}
+
+static void restore_all_ctx(void)
+{
+        DSSDBG("restore context\n");
+
+        dss_clk_enable_all_no_ctx();
+
+        dss_restore_context();
+        dispc_restore_context();
+#ifdef CONFIG_OMAP2_DSS_DSI
+        dsi_restore_context();
+#endif
+
+        dss_clk_disable_all_no_ctx();
+}
+
+static int dss_get_clock(struct clk **clock, const char *clk_name)
+{
+        struct clk *clk;
+
+        clk = clk_get(&dss.pdev->dev, clk_name);
+
+        if (IS_ERR(clk)) {
+                DSSERR("can't get clock %s", clk_name);
+                return PTR_ERR(clk);
+        }
+
+        *clock = clk;
+
+        DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
+
+        return 0;
+}
+
+static int dss_get_clocks(void)
+{
+        int r;
+        struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
+
+        dss.dss_ick = NULL;
+        dss.dss_fck = NULL;
+        dss.dss_sys_clk = NULL;
+        dss.dss_tv_fck = NULL;
+        dss.dss_video_fck = NULL;
+
+        r = dss_get_clock(&dss.dss_ick, "ick");
+        if (r)
+                goto err;
+
+        r = dss_get_clock(&dss.dss_fck, "fck");
+        if (r)
+                goto err;
+
+        if (!pdata->opt_clock_available) {
+                r = -ENODEV;
+                goto err;
+        }
+
+        if (pdata->opt_clock_available("sys_clk")) {
+                r = dss_get_clock(&dss.dss_sys_clk, "sys_clk");
+                if (r)
+                        goto err;
+        }
+
+        if (pdata->opt_clock_available("tv_clk")) {
+                r = dss_get_clock(&dss.dss_tv_fck, "tv_clk");
+                if (r)
+                        goto err;
+        }
+
+        if (pdata->opt_clock_available("video_clk")) {
+                r = dss_get_clock(&dss.dss_video_fck, "video_clk");
+                if (r)
+                        goto err;
+        }
+
+        return 0;
+
+err:
+        if (dss.dss_ick)
+                clk_put(dss.dss_ick);
+        if (dss.dss_fck)
+                clk_put(dss.dss_fck);
+        if (dss.dss_sys_clk)
+                clk_put(dss.dss_sys_clk);
+        if (dss.dss_tv_fck)
+                clk_put(dss.dss_tv_fck);
+        if (dss.dss_video_fck)
+                clk_put(dss.dss_video_fck);
+
+        return r;
+}
+
+static void dss_put_clocks(void)
+{
+        if (dss.dss_video_fck)
+                clk_put(dss.dss_video_fck);
+        if (dss.dss_tv_fck)
+                clk_put(dss.dss_tv_fck);
+        if (dss.dss_sys_clk)
+                clk_put(dss.dss_sys_clk);
+        clk_put(dss.dss_fck);
+        clk_put(dss.dss_ick);
+}
+
+unsigned long dss_clk_get_rate(enum dss_clock clk)
+{
+        switch (clk) {
+        case DSS_CLK_ICK:
+                return clk_get_rate(dss.dss_ick);
+        case DSS_CLK_FCK:
+                return clk_get_rate(dss.dss_fck);
+        case DSS_CLK_SYSCK:
+                return clk_get_rate(dss.dss_sys_clk);
+        case DSS_CLK_TVFCK:
+                return clk_get_rate(dss.dss_tv_fck);
+        case DSS_CLK_VIDFCK:
+                return clk_get_rate(dss.dss_video_fck);
+        }
+
+        BUG();
+        return 0;
+}
+
+static unsigned count_clk_bits(enum dss_clock clks)
+{
+        unsigned num_clks = 0;
+
+        if (clks & DSS_CLK_ICK)
+                ++num_clks;
+        if (clks & DSS_CLK_FCK)
+                ++num_clks;
+        if (clks & DSS_CLK_SYSCK)
+                ++num_clks;
+        if (clks & DSS_CLK_TVFCK)
+                ++num_clks;
+        if (clks & DSS_CLK_VIDFCK)
+                ++num_clks;
+
+        return num_clks;
+}
+
+static void dss_clk_enable_no_ctx(enum dss_clock clks)
+{
+        unsigned num_clks = count_clk_bits(clks);
+
+        if (clks & DSS_CLK_ICK)
+                clk_enable(dss.dss_ick);
+        if (clks & DSS_CLK_FCK)
+                clk_enable(dss.dss_fck);
+        if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk)
+                clk_enable(dss.dss_sys_clk);
+        if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck)
+                clk_enable(dss.dss_tv_fck);
+        if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck)
+                clk_enable(dss.dss_video_fck);
+
+        dss.num_clks_enabled += num_clks;
+}
+
+void dss_clk_enable(enum dss_clock clks)
+{
+        bool check_ctx = dss.num_clks_enabled == 0;
+
+        dss_clk_enable_no_ctx(clks);
+
+        /*
+         * HACK: On omap4 the registers may not be accessible right after
+         * enabling the clocks. At some point this will be handled by
+         * pm_runtime, but for the time begin this should make things work.
+         */
+        if (cpu_is_omap44xx() && check_ctx)
+                udelay(10);
+
+        if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore())
+                restore_all_ctx();
+}
+
+static void dss_clk_disable_no_ctx(enum dss_clock clks)
+{
+        unsigned num_clks = count_clk_bits(clks);
+
+        if (clks & DSS_CLK_ICK)
+                clk_disable(dss.dss_ick);
+        if (clks & DSS_CLK_FCK)
+                clk_disable(dss.dss_fck);
+        if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk)
+                clk_disable(dss.dss_sys_clk);
+        if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck)
+                clk_disable(dss.dss_tv_fck);
+        if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck)
+                clk_disable(dss.dss_video_fck);
+
+        dss.num_clks_enabled -= num_clks;
+}
+
+void dss_clk_disable(enum dss_clock clks)
+{
+        if (cpu_is_omap34xx()) {
+                unsigned num_clks = count_clk_bits(clks);
+
+                BUG_ON(dss.num_clks_enabled < num_clks);
+
+                if (dss.num_clks_enabled == num_clks)
+                        save_all_ctx();
+        }
+
+        dss_clk_disable_no_ctx(clks);
+}
+
+static void dss_clk_enable_all_no_ctx(void)
+{
+        enum dss_clock clks;
+
+        clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
+        if (cpu_is_omap34xx())
+                clks |= DSS_CLK_VIDFCK;
+        dss_clk_enable_no_ctx(clks);
+}
+
+static void dss_clk_disable_all_no_ctx(void)
+{
+        enum dss_clock clks;
+
+        clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
+        if (cpu_is_omap34xx())
+                clks |= DSS_CLK_VIDFCK;
+        dss_clk_disable_no_ctx(clks);
+}
+
+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
+/* CLOCKS */
+static void core_dump_clocks(struct seq_file *s)
+{
+        int i;
+        struct clk *clocks[5] = {
+                dss.dss_ick,
+                dss.dss_fck,
+                dss.dss_sys_clk,
+                dss.dss_tv_fck,
+                dss.dss_video_fck
+        };
+
+        seq_printf(s, "- CORE -\n");
+
+        seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled);
+
+        for (i = 0; i < 5; i++) {
+                if (!clocks[i])
+                        continue;
+                seq_printf(s, "%-15s\t%lu\t%d\n",
+                                clocks[i]->name,
+                                clk_get_rate(clocks[i]),
+                                clocks[i]->usecount);
+        }
+}
+#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
+
+/* DEBUGFS */
+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
+void dss_debug_dump_clocks(struct seq_file *s)
+{
+        core_dump_clocks(s);
+        dss_dump_clocks(s);
+        dispc_dump_clocks(s);
+#ifdef CONFIG_OMAP2_DSS_DSI
+        dsi_dump_clocks(s);
+#endif
+}
+#endif
+
+
+/* DSS HW IP initialisation */
+static int omap_dsshw_probe(struct platform_device *pdev)
+{
+        int r;
+
+        dss.pdev = pdev;
+
+        r = dss_get_clocks();
+        if (r)
+                goto err_clocks;
+
+        dss_clk_enable_all_no_ctx();
+
+        dss.ctx_id = dss_get_ctx_id();
+        DSSDBG("initial ctx id %u\n", dss.ctx_id);
+
+        r = dss_init();
+        if (r) {
+                DSSERR("Failed to initialize DSS\n");
+                goto err_dss;
+        }
+
+        r = dpi_init();
+        if (r) {
+                DSSERR("Failed to initialize DPI\n");
+                goto err_dpi;
+        }
+
+        r = sdi_init();
+        if (r) {
+                DSSERR("Failed to initialize SDI\n");
+                goto err_sdi;
+        }
+
+        dss_clk_disable_all_no_ctx();
+        return 0;
+err_sdi:
+        dpi_exit();
+err_dpi:
+        dss_exit();
+err_dss:
+        dss_clk_disable_all_no_ctx();
+        dss_put_clocks();
+err_clocks:
+        return r;
+}
+
+static int omap_dsshw_remove(struct platform_device *pdev)
+{
+
+        dss_exit();
+
+        /*
+         * As part of hwmod changes, DSS is not the only controller of dss
+         * clocks; hwmod framework itself will also enable clocks during hwmod
+         * init for dss, and autoidle is set in h/w for DSS. Hence, there's no
+         * need to disable clocks if their usecounts > 1.
+         */
+        WARN_ON(dss.num_clks_enabled > 0);
+
+        dss_put_clocks();
+        return 0;
+}
+
+static struct platform_driver omap_dsshw_driver = {
+        .probe          = omap_dsshw_probe,
+        .remove         = omap_dsshw_remove,
+        .driver         = {
+                .name   = "omapdss_dss",
+                .owner  = THIS_MODULE,
+        },
+};
+
+int dss_init_platform_driver(void)
+{
+        return platform_driver_register(&omap_dsshw_driver);
+}
+
+void dss_uninit_platform_driver(void)
+{
+        return platform_driver_unregister(&omap_dsshw_driver);
+}
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index b394951120ac..c2f582bb19c0 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -97,8 +97,6 @@ extern unsigned int dss_debug;
 #define FLD_MOD(orig, val, start, end) \
         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
 
-#define DISPC_MAX_FCK 173000000
-
 enum omap_burst_size {
         OMAP_DSS_BURST_4x32 = 0,
         OMAP_DSS_BURST_8x32 = 1,
@@ -112,17 +110,25 @@ enum omap_parallel_interface_mode {
 };
 
 enum dss_clock {
-        DSS_CLK_ICK     = 1 << 0,
-        DSS_CLK_FCK1    = 1 << 1,
-        DSS_CLK_FCK2    = 1 << 2,
-        DSS_CLK_54M     = 1 << 3,
-        DSS_CLK_96M     = 1 << 4,
+        DSS_CLK_ICK     = 1 << 0,       /* DSS_L3_ICLK and DSS_L4_ICLK */
+        DSS_CLK_FCK     = 1 << 1,       /* DSS1_ALWON_FCLK */
+        DSS_CLK_SYSCK   = 1 << 2,       /* DSS2_ALWON_FCLK */
+        DSS_CLK_TVFCK   = 1 << 3,       /* DSS_TV_FCLK */
+        DSS_CLK_VIDFCK  = 1 << 4,       /* DSS_96M_FCLK*/
 };
 
 enum dss_clk_source {
-        DSS_SRC_DSI1_PLL_FCLK,
-        DSS_SRC_DSI2_PLL_FCLK,
-        DSS_SRC_DSS1_ALWON_FCLK,
+        DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,        /* OMAP3: DSI1_PLL_FCLK
+                                                 * OMAP4: PLL1_CLK1 */
+        DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,          /* OMAP3: DSI2_PLL_FCLK
+                                                 * OMAP4: PLL1_CLK2 */
+        DSS_CLK_SRC_FCK,                        /* OMAP2/3: DSS1_ALWON_FCLK
+                                                 * OMAP4: DSS_FCLK */
+};
+
+enum dss_hdmi_venc_clk_source_select {
+        DSS_VENC_TV_CLK = 0,
+        DSS_HDMI_M_PCLK = 1,
 };
 
 struct dss_clock_info {
@@ -148,36 +154,42 @@ struct dsi_clock_info {
         unsigned long fint;
         unsigned long clkin4ddr;
         unsigned long clkin;
-        unsigned long dsi1_pll_fclk;
-        unsigned long dsi2_pll_fclk;
-
+        unsigned long dsi_pll_hsdiv_dispc_clk;  /* OMAP3: DSI1_PLL_CLK
+                                                 * OMAP4: PLLx_CLK1 */
+        unsigned long dsi_pll_hsdiv_dsi_clk;    /* OMAP3: DSI2_PLL_CLK
+                                                 * OMAP4: PLLx_CLK2 */
         unsigned long lp_clk;
 
         /* dividers */
         u16 regn;
         u16 regm;
-        u16 regm3;
-        u16 regm4;
-
+        u16 regm_dispc; /* OMAP3: REGM3
+                         * OMAP4: REGM4 */
+        u16 regm_dsi;   /* OMAP3: REGM4
+                         * OMAP4: REGM5 */
         u16 lp_clk_div;
 
         u8 highfreq;
-        bool use_dss2_fck;
+        bool use_sys_clk;
+};
+
+/* HDMI PLL structure */
+struct hdmi_pll_info {
+        u16 regn;
+        u16 regm;
+        u32 regmf;
+        u16 regm2;
+        u16 regsd;
+        u16 dcofreq;
 };
 
 struct seq_file;
 struct platform_device;
 
 /* core */
-void dss_clk_enable(enum dss_clock clks);
-void dss_clk_disable(enum dss_clock clks);
-unsigned long dss_clk_get_rate(enum dss_clock clk);
-int dss_need_ctx_restore(void);
-void dss_dump_clocks(struct seq_file *s);
 struct bus_type *dss_get_bus(void);
 struct regulator *dss_get_vdds_dsi(void);
 struct regulator *dss_get_vdds_sdi(void);
-struct regulator *dss_get_vdda_dac(void);
 
 /* display */
 int dss_suspend_all_devices(void);
@@ -214,13 +226,23 @@ void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr);
 void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
 
 /* DSS */
-int dss_init(bool skip_init);
-void dss_exit(void);
+int dss_init_platform_driver(void);
+void dss_uninit_platform_driver(void);
 
+void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
 void dss_save_context(void);
 void dss_restore_context(void);
+void dss_clk_enable(enum dss_clock clks);
+void dss_clk_disable(enum dss_clock clks);
+unsigned long dss_clk_get_rate(enum dss_clock clk);
+int dss_need_ctx_restore(void);
+const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src);
+void dss_dump_clocks(struct seq_file *s);
 
 void dss_dump_regs(struct seq_file *s);
+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
+void dss_debug_dump_clocks(struct seq_file *s);
+#endif
 
 void dss_sdi_init(u8 datapairs);
 int dss_sdi_enable(void);
@@ -228,8 +250,11 @@ void dss_sdi_disable(void);
 
 void dss_select_dispc_clk_source(enum dss_clk_source clk_src);
 void dss_select_dsi_clk_source(enum dss_clk_source clk_src);
+void dss_select_lcd_clk_source(enum omap_channel channel,
+                enum dss_clk_source clk_src);
 enum dss_clk_source dss_get_dispc_clk_source(void);
 enum dss_clk_source dss_get_dsi_clk_source(void);
+enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
 
 void dss_set_venc_output(enum omap_dss_venc_type type);
 void dss_set_dac_pwrdn_bgz(bool enable);
@@ -244,11 +269,11 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 
 /* SDI */
 #ifdef CONFIG_OMAP2_DSS_SDI
-int sdi_init(bool skip_init);
+int sdi_init(void);
 void sdi_exit(void);
 int sdi_init_display(struct omap_dss_device *display);
 #else
-static inline int sdi_init(bool skip_init)
+static inline int sdi_init(void)
 {
         return 0;
 }
@@ -259,8 +284,8 @@ static inline void sdi_exit(void)
 
 /* DSI */
 #ifdef CONFIG_OMAP2_DSS_DSI
-int dsi_init(struct platform_device *pdev);
-void dsi_exit(void);
+int dsi_init_platform_driver(void);
+void dsi_uninit_platform_driver(void);
 
 void dsi_dump_clocks(struct seq_file *s);
 void dsi_dump_irqs(struct seq_file *s);
@@ -271,7 +296,7 @@ void dsi_restore_context(void);
 
 int dsi_init_display(struct omap_dss_device *display);
 void dsi_irq_handler(void);
-unsigned long dsi_get_dsi1_pll_rate(void);
+unsigned long dsi_get_pll_hsdiv_dispc_rate(void);
 int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo);
 int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
                 struct dsi_clock_info *cinfo,
@@ -282,31 +307,36 @@ void dsi_pll_uninit(void);
 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
                 u32 fifo_size, enum omap_burst_size *burst_size,
                 u32 *fifo_low, u32 *fifo_high);
-void dsi_wait_dsi1_pll_active(void);
-void dsi_wait_dsi2_pll_active(void);
+void dsi_wait_pll_hsdiv_dispc_active(void);
+void dsi_wait_pll_hsdiv_dsi_active(void);
 #else
-static inline int dsi_init(struct platform_device *pdev)
+static inline int dsi_init_platform_driver(void)
 {
         return 0;
 }
-static inline void dsi_exit(void)
+static inline void dsi_uninit_platform_driver(void)
 {
 }
-static inline void dsi_wait_dsi1_pll_active(void)
+static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(void)
 {
+        WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
+        return 0;
 }
-static inline void dsi_wait_dsi2_pll_active(void)
+static inline void dsi_wait_pll_hsdiv_dispc_active(void)
+{
+}
+static inline void dsi_wait_pll_hsdiv_dsi_active(void)
 {
 }
 #endif
 
 /* DPI */
 #ifdef CONFIG_OMAP2_DSS_DPI
-int dpi_init(struct platform_device *pdev);
+int dpi_init(void);
 void dpi_exit(void);
 int dpi_init_display(struct omap_dss_device *dssdev);
 #else
-static inline int dpi_init(struct platform_device *pdev)
+static inline int dpi_init(void)
 {
         return 0;
 }
@@ -316,8 +346,8 @@ static inline void dpi_exit(void)
 #endif
 
 /* DISPC */
-int dispc_init(void);
-void dispc_exit(void);
+int dispc_init_platform_driver(void);
+void dispc_uninit_platform_driver(void);
 void dispc_dump_clocks(struct seq_file *s);
 void dispc_dump_irqs(struct seq_file *s);
 void dispc_dump_regs(struct seq_file *s);
@@ -350,6 +380,7 @@ void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height);
 void dispc_set_channel_out(enum omap_plane plane,
                 enum omap_channel channel_out);
 
+void dispc_enable_gamma_table(bool enable);
 int dispc_setup_plane(enum omap_plane plane,
                       u32 paddr, u16 screen_width,
                       u16 pos_x, u16 pos_y,
@@ -409,24 +440,50 @@ int dispc_get_clock_div(enum omap_channel channel,
 
 /* VENC */
 #ifdef CONFIG_OMAP2_DSS_VENC
-int venc_init(struct platform_device *pdev);
-void venc_exit(void);
+int venc_init_platform_driver(void);
+void venc_uninit_platform_driver(void);
 void venc_dump_regs(struct seq_file *s);
 int venc_init_display(struct omap_dss_device *display);
 #else
-static inline int venc_init(struct platform_device *pdev)
+static inline int venc_init_platform_driver(void)
+{
+        return 0;
+}
+static inline void venc_uninit_platform_driver(void)
+{
+}
+#endif
+
+/* HDMI */
+#ifdef CONFIG_OMAP4_DSS_HDMI
+int hdmi_init_platform_driver(void);
+void hdmi_uninit_platform_driver(void);
+int hdmi_init_display(struct omap_dss_device *dssdev);
+#else
+static inline int hdmi_init_display(struct omap_dss_device *dssdev)
+{
+        return 0;
+}
+static inline int hdmi_init_platform_driver(void)
 {
         return 0;
 }
-static inline void venc_exit(void)
+static inline void hdmi_uninit_platform_driver(void)
 {
 }
 #endif
+int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
+void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
+void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev);
+int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
+                                        struct omap_video_timings *timings);
+int hdmi_panel_init(void);
+void hdmi_panel_exit(void);
 
 /* RFBI */
 #ifdef CONFIG_OMAP2_DSS_RFBI
-int rfbi_init(void);
-void rfbi_exit(void);
+int rfbi_init_platform_driver(void);
+void rfbi_uninit_platform_driver(void);
 void rfbi_dump_regs(struct seq_file *s);
 
 int rfbi_configure(int rfbi_module, int bpp, int lines);
@@ -437,11 +494,11 @@ void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t);
 unsigned long rfbi_get_max_tx_rate(void);
 int rfbi_init_display(struct omap_dss_device *display);
 #else
-static inline int rfbi_init(void)
+static inline int rfbi_init_platform_driver(void)
 {
         return 0;
 }
-static inline void rfbi_exit(void)
+static inline void rfbi_uninit_platform_driver(void)
 {
 }
 #endif
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index cf3ef696e141..aa1622241d0d 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -25,14 +25,18 @@
 #include <plat/display.h>
 #include <plat/cpu.h>
 
+#include "dss.h"
 #include "dss_features.h"
 
 /* Defines a generic omap register field */
 struct dss_reg_field {
-        enum dss_feat_reg_field id;
         u8 start, end;
 };
 
+struct dss_param_range {
+        int min, max;
+};
+
 struct omap_dss_features {
         const struct dss_reg_field *reg_fields;
         const int num_reg_fields;
@@ -43,29 +47,68 @@ struct omap_dss_features {
         const int num_ovls;
         const enum omap_display_type *supported_displays;
         const enum omap_color_mode *supported_color_modes;
+        const char * const *clksrc_names;
+        const struct dss_param_range *dss_params;
 };
 
 /* This struct is assigned to one of the below during initialization */
 static struct omap_dss_features *omap_current_dss_features;
 
 static const struct dss_reg_field omap2_dss_reg_fields[] = {
-        { FEAT_REG_FIRHINC, 11, 0 },
-        { FEAT_REG_FIRVINC, 27, 16 },
-        { FEAT_REG_FIFOLOWTHRESHOLD, 8, 0 },
-        { FEAT_REG_FIFOHIGHTHRESHOLD, 24, 16 },
-        { FEAT_REG_FIFOSIZE, 8, 0 },
+        [FEAT_REG_FIRHINC]                      = { 11, 0 },
+        [FEAT_REG_FIRVINC]                      = { 27, 16 },
+        [FEAT_REG_FIFOLOWTHRESHOLD]             = { 8, 0 },
+        [FEAT_REG_FIFOHIGHTHRESHOLD]            = { 24, 16 },
+        [FEAT_REG_FIFOSIZE]                     = { 8, 0 },
+        [FEAT_REG_HORIZONTALACCU]               = { 9, 0 },
+        [FEAT_REG_VERTICALACCU]                 = { 25, 16 },
+        [FEAT_REG_DISPC_CLK_SWITCH]             = { 0, 0 },
+        [FEAT_REG_DSIPLL_REGN]                  = { 0, 0 },
+        [FEAT_REG_DSIPLL_REGM]                  = { 0, 0 },
+        [FEAT_REG_DSIPLL_REGM_DISPC]            = { 0, 0 },
+        [FEAT_REG_DSIPLL_REGM_DSI]              = { 0, 0 },
 };
 
 static const struct dss_reg_field omap3_dss_reg_fields[] = {
-        { FEAT_REG_FIRHINC, 12, 0 },
-        { FEAT_REG_FIRVINC, 28, 16 },
-        { FEAT_REG_FIFOLOWTHRESHOLD, 11, 0 },
-        { FEAT_REG_FIFOHIGHTHRESHOLD, 27, 16 },
-        { FEAT_REG_FIFOSIZE, 10, 0 },
+        [FEAT_REG_FIRHINC]                      = { 12, 0 },
+        [FEAT_REG_FIRVINC]                      = { 28, 16 },
+        [FEAT_REG_FIFOLOWTHRESHOLD]             = { 11, 0 },
+        [FEAT_REG_FIFOHIGHTHRESHOLD]            = { 27, 16 },
+        [FEAT_REG_FIFOSIZE]                     = { 10, 0 },
+        [FEAT_REG_HORIZONTALACCU]               = { 9, 0 },
+        [FEAT_REG_VERTICALACCU]                 = { 25, 16 },
+        [FEAT_REG_DISPC_CLK_SWITCH]             = { 0, 0 },
+        [FEAT_REG_DSIPLL_REGN]                  = { 7, 1 },
+        [FEAT_REG_DSIPLL_REGM]                  = { 18, 8 },
+        [FEAT_REG_DSIPLL_REGM_DISPC]            = { 22, 19 },
+        [FEAT_REG_DSIPLL_REGM_DSI]              = { 26, 23 },
+};
+
+static const struct dss_reg_field omap4_dss_reg_fields[] = {
+        [FEAT_REG_FIRHINC]                      = { 12, 0 },
+        [FEAT_REG_FIRVINC]                      = { 28, 16 },
+        [FEAT_REG_FIFOLOWTHRESHOLD]             = { 15, 0 },
+        [FEAT_REG_FIFOHIGHTHRESHOLD]            = { 31, 16 },
+        [FEAT_REG_FIFOSIZE]                     = { 15, 0 },
+        [FEAT_REG_HORIZONTALACCU]               = { 10, 0 },
+        [FEAT_REG_VERTICALACCU]                 = { 26, 16 },
+        [FEAT_REG_DISPC_CLK_SWITCH]             = { 9, 8 },
+        [FEAT_REG_DSIPLL_REGN]                  = { 8, 1 },
+        [FEAT_REG_DSIPLL_REGM]                  = { 20, 9 },
+        [FEAT_REG_DSIPLL_REGM_DISPC]            = { 25, 21 },
+        [FEAT_REG_DSIPLL_REGM_DSI]              = { 30, 26 },
 };
 
 static const enum omap_display_type omap2_dss_supported_displays[] = {
         /* OMAP_DSS_CHANNEL_LCD */
+        OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
+
+        /* OMAP_DSS_CHANNEL_DIGIT */
+        OMAP_DISPLAY_TYPE_VENC,
+};
+
+static const enum omap_display_type omap3430_dss_supported_displays[] = {
+        /* OMAP_DSS_CHANNEL_LCD */
         OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
         OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
 
@@ -73,10 +116,10 @@ static const enum omap_display_type omap2_dss_supported_displays[] = {
         OMAP_DISPLAY_TYPE_VENC,
 };
 
-static const enum omap_display_type omap3_dss_supported_displays[] = {
+static const enum omap_display_type omap3630_dss_supported_displays[] = {
         /* OMAP_DSS_CHANNEL_LCD */
         OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
-        OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
+        OMAP_DISPLAY_TYPE_DSI,
 
         /* OMAP_DSS_CHANNEL_DIGIT */
         OMAP_DISPLAY_TYPE_VENC,
@@ -87,7 +130,7 @@ static const enum omap_display_type omap4_dss_supported_displays[] = {
         OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
 
         /* OMAP_DSS_CHANNEL_DIGIT */
-        OMAP_DISPLAY_TYPE_VENC,
+        OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI,
 
         /* OMAP_DSS_CHANNEL_LCD2 */
         OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
@@ -134,6 +177,54 @@ static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
         OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
 };
 
+static const char * const omap2_dss_clk_source_names[] = {
+        [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]       = "N/A",
+        [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]         = "N/A",
+        [DSS_CLK_SRC_FCK]                       = "DSS_FCLK1",
+};
+
+static const char * const omap3_dss_clk_source_names[] = {
+        [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]       = "DSI1_PLL_FCLK",
+        [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]         = "DSI2_PLL_FCLK",
+        [DSS_CLK_SRC_FCK]                       = "DSS1_ALWON_FCLK",
+};
+
+static const char * const omap4_dss_clk_source_names[] = {
+        [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]       = "PLL1_CLK1",
+        [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]         = "PLL1_CLK2",
+        [DSS_CLK_SRC_FCK]                       = "DSS_FCLK",
+};
+
+static const struct dss_param_range omap2_dss_param_range[] = {
+        [FEAT_PARAM_DSS_FCK]                    = { 0, 173000000 },
+        [FEAT_PARAM_DSIPLL_REGN]                = { 0, 0 },
+        [FEAT_PARAM_DSIPLL_REGM]                = { 0, 0 },
+        [FEAT_PARAM_DSIPLL_REGM_DISPC]          = { 0, 0 },
+        [FEAT_PARAM_DSIPLL_REGM_DSI]            = { 0, 0 },
+        [FEAT_PARAM_DSIPLL_FINT]                = { 0, 0 },
+        [FEAT_PARAM_DSIPLL_LPDIV]               = { 0, 0 },
+};
+
+static const struct dss_param_range omap3_dss_param_range[] = {
+        [FEAT_PARAM_DSS_FCK]                    = { 0, 173000000 },
+        [FEAT_PARAM_DSIPLL_REGN]                = { 0, (1 << 7) - 1 },
+        [FEAT_PARAM_DSIPLL_REGM]                = { 0, (1 << 11) - 1 },
+        [FEAT_PARAM_DSIPLL_REGM_DISPC]          = { 0, (1 << 4) - 1 },
+        [FEAT_PARAM_DSIPLL_REGM_DSI]            = { 0, (1 << 4) - 1 },
+        [FEAT_PARAM_DSIPLL_FINT]                = { 750000, 2100000 },
+        [FEAT_PARAM_DSIPLL_LPDIV]               = { 1, (1 << 13) - 1},
+};
+
+static const struct dss_param_range omap4_dss_param_range[] = {
+        [FEAT_PARAM_DSS_FCK]                    = { 0, 186000000 },
+        [FEAT_PARAM_DSIPLL_REGN]                = { 0, (1 << 8) - 1 },
+        [FEAT_PARAM_DSIPLL_REGM]                = { 0, (1 << 12) - 1 },
+        [FEAT_PARAM_DSIPLL_REGM_DISPC]          = { 0, (1 << 5) - 1 },
+        [FEAT_PARAM_DSIPLL_REGM_DSI]            = { 0, (1 << 5) - 1 },
+        [FEAT_PARAM_DSIPLL_FINT]                = { 500000, 2500000 },
+        [FEAT_PARAM_DSIPLL_LPDIV]               = { 0, (1 << 13) - 1 },
+};
+
 /* OMAP2 DSS Features */
 static struct omap_dss_features omap2_dss_features = {
         .reg_fields = omap2_dss_reg_fields,
@@ -141,12 +232,15 @@ static struct omap_dss_features omap2_dss_features = {
 
         .has_feature    =
                 FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL |
-                FEAT_PCKFREEENABLE | FEAT_FUNCGATED,
+                FEAT_PCKFREEENABLE | FEAT_FUNCGATED |
+                FEAT_ROWREPEATENABLE | FEAT_RESIZECONF,
 
         .num_mgrs = 2,
         .num_ovls = 3,
         .supported_displays = omap2_dss_supported_displays,
         .supported_color_modes = omap2_dss_supported_color_modes,
+        .clksrc_names = omap2_dss_clk_source_names,
+        .dss_params = omap2_dss_param_range,
 };
 
 /* OMAP3 DSS Features */
@@ -157,12 +251,15 @@ static struct omap_dss_features omap3430_dss_features = {
         .has_feature    =
                 FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
                 FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
-                FEAT_FUNCGATED,
+                FEAT_FUNCGATED | FEAT_ROWREPEATENABLE |
+                FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF,
 
         .num_mgrs = 2,
         .num_ovls = 3,
-        .supported_displays = omap3_dss_supported_displays,
+        .supported_displays = omap3430_dss_supported_displays,
         .supported_color_modes = omap3_dss_supported_color_modes,
+        .clksrc_names = omap3_dss_clk_source_names,
+        .dss_params = omap3_dss_param_range,
 };
 
 static struct omap_dss_features omap3630_dss_features = {
@@ -172,27 +269,34 @@ static struct omap_dss_features omap3630_dss_features = {
         .has_feature    =
                 FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
                 FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
-                FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED,
+                FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED |
+                FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
+                FEAT_RESIZECONF,
 
         .num_mgrs = 2,
         .num_ovls = 3,
-        .supported_displays = omap3_dss_supported_displays,
+        .supported_displays = omap3630_dss_supported_displays,
         .supported_color_modes = omap3_dss_supported_color_modes,
+        .clksrc_names = omap3_dss_clk_source_names,
+        .dss_params = omap3_dss_param_range,
 };
 
 /* OMAP4 DSS Features */
 static struct omap_dss_features omap4_dss_features = {
-        .reg_fields = omap3_dss_reg_fields,
-        .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
+        .reg_fields = omap4_dss_reg_fields,
+        .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
 
         .has_feature    =
                 FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
-                FEAT_MGR_LCD2,
+                FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |
+                FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC,
 
         .num_mgrs = 3,
         .num_ovls = 3,
         .supported_displays = omap4_dss_supported_displays,
         .supported_color_modes = omap3_dss_supported_color_modes,
+        .clksrc_names = omap4_dss_clk_source_names,
+        .dss_params = omap4_dss_param_range,
 };
 
 /* Functions returning values related to a DSS feature */
@@ -206,6 +310,16 @@ int dss_feat_get_num_ovls(void)
         return omap_current_dss_features->num_ovls;
 }
 
+unsigned long dss_feat_get_param_min(enum dss_range_param param)
+{
+        return omap_current_dss_features->dss_params[param].min;
+}
+
+unsigned long dss_feat_get_param_max(enum dss_range_param param)
+{
+        return omap_current_dss_features->dss_params[param].max;
+}
+
 enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
 {
         return omap_current_dss_features->supported_displays[channel];
@@ -223,6 +337,11 @@ bool dss_feat_color_mode_supported(enum omap_plane plane,
                         color_mode;
 }
 
+const char *dss_feat_get_clk_source_name(enum dss_clk_source id)
+{
+        return omap_current_dss_features->clksrc_names[id];
+}
+
 /* DSS has_feature check */
 bool dss_has_feature(enum dss_feat_id id)
 {
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index b9c70be92588..12e9c4ef0dec 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -22,6 +22,7 @@
 
 #define MAX_DSS_MANAGERS        3
 #define MAX_DSS_OVERLAYS        3
+#define MAX_DSS_LCD_MANAGERS    2
 
 /* DSS has feature id */
 enum dss_feat_id {
@@ -33,6 +34,12 @@ enum dss_feat_id {
         FEAT_PCKFREEENABLE      = 1 << 5,
         FEAT_FUNCGATED          = 1 << 6,
         FEAT_MGR_LCD2           = 1 << 7,
+        FEAT_LINEBUFFERSPLIT    = 1 << 8,
+        FEAT_ROWREPEATENABLE    = 1 << 9,
+        FEAT_RESIZECONF         = 1 << 10,
+        /* Independent core clk divider */
+        FEAT_CORE_CLK_DIV       = 1 << 11,
+        FEAT_LCD_CLK_SRC        = 1 << 12,
 };
 
 /* DSS register field id */
@@ -42,15 +49,35 @@ enum dss_feat_reg_field {
         FEAT_REG_FIFOHIGHTHRESHOLD,
         FEAT_REG_FIFOLOWTHRESHOLD,
         FEAT_REG_FIFOSIZE,
+        FEAT_REG_HORIZONTALACCU,
+        FEAT_REG_VERTICALACCU,
+        FEAT_REG_DISPC_CLK_SWITCH,
+        FEAT_REG_DSIPLL_REGN,
+        FEAT_REG_DSIPLL_REGM,
+        FEAT_REG_DSIPLL_REGM_DISPC,
+        FEAT_REG_DSIPLL_REGM_DSI,
+};
+
+enum dss_range_param {
+        FEAT_PARAM_DSS_FCK,
+        FEAT_PARAM_DSIPLL_REGN,
+        FEAT_PARAM_DSIPLL_REGM,
+        FEAT_PARAM_DSIPLL_REGM_DISPC,
+        FEAT_PARAM_DSIPLL_REGM_DSI,
+        FEAT_PARAM_DSIPLL_FINT,
+        FEAT_PARAM_DSIPLL_LPDIV,
 };
 
 /* DSS Feature Functions */
 int dss_feat_get_num_mgrs(void);
 int dss_feat_get_num_ovls(void);
+unsigned long dss_feat_get_param_min(enum dss_range_param param);
+unsigned long dss_feat_get_param_max(enum dss_range_param param);
 enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
 bool dss_feat_color_mode_supported(enum omap_plane plane,
                 enum omap_color_mode color_mode);
+const char *dss_feat_get_clk_source_name(enum dss_clk_source id);
 
 bool dss_has_feature(enum dss_feat_id id);
 void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end);
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
new file mode 100644
index 000000000000..0d44f070ef36
--- /dev/null
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -0,0 +1,1332 @@
+/*
+ * hdmi.c
+ *
+ * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
+ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Authors: Yong Zhi
+ *      Mythri pk <mythripk@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define DSS_SUBSYS_NAME "HDMI"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <plat/display.h>
+
+#include "dss.h"
+#include "hdmi.h"
+
+static struct {
+        struct mutex lock;
+        struct omap_display_platform_data *pdata;
+        struct platform_device *pdev;
+        void __iomem *base_wp;  /* HDMI wrapper */
+        int code;
+        int mode;
+        u8 edid[HDMI_EDID_MAX_LENGTH];
+        u8 edid_set;
+        bool custom_set;
+        struct hdmi_config cfg;
+} hdmi;
+
+/*
+ * Logic for the below structure :
+ * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
+ * There is a correspondence between CEA/VESA timing and code, please
+ * refer to section 6.3 in HDMI 1.3 specification for timing code.
+ *
+ * In the below structure, cea_vesa_timings corresponds to all OMAP4
+ * supported CEA and VESA timing values.code_cea corresponds to the CEA
+ * code, It is used to get the timing from cea_vesa_timing array.Similarly
+ * with code_vesa. Code_index is used for back mapping, that is once EDID
+ * is read from the TV, EDID is parsed to find the timing values and then
+ * map it to corresponding CEA or VESA index.
+ */
+
+static const struct hdmi_timings cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = {
+        { {640, 480, 25200, 96, 16, 48, 2, 10, 33} , 0 , 0},
+        { {1280, 720, 74250, 40, 440, 220, 5, 5, 20}, 1, 1},
+        { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1},
+        { {720, 480, 27027, 62, 16, 60, 6, 9, 30}, 0, 0},
+        { {2880, 576, 108000, 256, 48, 272, 5, 5, 39}, 0, 0},
+        { {1440, 240, 27027, 124, 38, 114, 3, 4, 15}, 0, 0},
+        { {1440, 288, 27000, 126, 24, 138, 3, 2, 19}, 0, 0},
+        { {1920, 540, 74250, 44, 528, 148, 5, 2, 15}, 1, 1},
+        { {1920, 540, 74250, 44, 88, 148, 5, 2, 15}, 1, 1},
+        { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36}, 1, 1},
+        { {720, 576, 27000, 64, 12, 68, 5, 5, 39}, 0, 0},
+        { {1440, 576, 54000, 128, 24, 136, 5, 5, 39}, 0, 0},
+        { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36}, 1, 1},
+        { {2880, 480, 108108, 248, 64, 240, 6, 9, 30}, 0, 0},
+        { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36}, 1, 1},
+        /* VESA From Here */
+        { {640, 480, 25175, 96, 16, 48, 2 , 11, 31}, 0, 0},
+        { {800, 600, 40000, 128, 40, 88, 4 , 1, 23}, 1, 1},
+        { {848, 480, 33750, 112, 16, 112, 8 , 6, 23}, 1, 1},
+        { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20}, 1, 0},
+        { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, 1, 0},
+        { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18}, 1, 1},
+        { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36}, 1, 1},
+        { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38}, 1, 1},
+        { {1024, 768, 65000, 136, 24, 160, 6, 3, 29}, 0, 0},
+        { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32}, 1, 0},
+        { {1440, 900, 106500, 152, 80, 232, 6, 3, 25}, 1, 0},
+        { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30}, 1, 0},
+        { {1366, 768, 85500, 143, 70, 213, 3, 3, 24}, 1, 1},
+        { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36}, 1, 1},
+        { {1280, 768, 68250, 32, 48, 80, 7, 3, 12}, 0, 1},
+        { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23}, 0, 1},
+        { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21}, 0, 1},
+        { {1280, 800, 79500, 32, 48, 80, 6, 3, 14}, 0, 1},
+        { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1}
+};
+
+/*
+ * This is a static mapping array which maps the timing values
+ * with corresponding CEA / VESA code
+ */
+static const int code_index[OMAP_HDMI_TIMINGS_NB] = {
+        1, 19, 4, 2, 37, 6, 21, 20, 5, 16, 17, 29, 31, 35, 32,
+        /* <--15 CEA 17--> vesa*/
+        4, 9, 0xE, 0x17, 0x1C, 0x27, 0x20, 0x23, 0x10, 0x2A,
+        0X2F, 0x3A, 0X51, 0X52, 0x16, 0x29, 0x39, 0x1B
+};
+
+/*
+ * This is reverse static mapping which maps the CEA / VESA code
+ * to the corresponding timing values
+ */
+static const int code_cea[39] = {
+        -1,  0,  3,  3,  2,  8,  5,  5, -1, -1,
+        -1, -1, -1, -1, -1, -1,  9, 10, 10,  1,
+        7,   6,  6, -1, -1, -1, -1, -1, -1, 11,
+        11, 12, 14, -1, -1, 13, 13,  4,  4
+};
+
+static const int code_vesa[85] = {
+        -1, -1, -1, -1, 15, -1, -1, -1, -1, 16,
+        -1, -1, -1, -1, 17, -1, 23, -1, -1, -1,
+        -1, -1, 29, 18, -1, -1, -1, 32, 19, -1,
+        -1, -1, 21, -1, -1, 22, -1, -1, -1, 20,
+        -1, 30, 24, -1, -1, -1, -1, 25, -1, -1,
+        -1, -1, -1, -1, -1, -1, -1, 31, 26, -1,
+        -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+        -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+        -1, 27, 28, -1, 33};
+
+static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0};
+
+static inline void hdmi_write_reg(const struct hdmi_reg idx, u32 val)
+{
+        __raw_writel(val, hdmi.base_wp + idx.idx);
+}
+
+static inline u32 hdmi_read_reg(const struct hdmi_reg idx)
+{
+        return __raw_readl(hdmi.base_wp + idx.idx);
+}
+
+static inline int hdmi_wait_for_bit_change(const struct hdmi_reg idx,
+                                int b2, int b1, u32 val)
+{
+        u32 t = 0;
+        while (val != REG_GET(idx, b2, b1)) {
+                udelay(1);
+                if (t++ > 10000)
+                        return !val;
+        }
+        return val;
+}
+
+int hdmi_init_display(struct omap_dss_device *dssdev)
+{
+        DSSDBG("init_display\n");
+
+        return 0;
+}
+
+static int hdmi_pll_init(enum hdmi_clk_refsel refsel, int dcofreq,
+                struct hdmi_pll_info *fmt, u16 sd)
+{
+        u32 r;
+
+        /* PLL start always use manual mode */
+        REG_FLD_MOD(PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
+
+        r = hdmi_read_reg(PLLCTRL_CFG1);
+        r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
+        r = FLD_MOD(r, fmt->regn, 8, 1);  /* CFG1_PLL_REGN */
+
+        hdmi_write_reg(PLLCTRL_CFG1, r);
+
+        r = hdmi_read_reg(PLLCTRL_CFG2);
+
+        r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
+        r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
+        r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
+
+        if (dcofreq) {
+                /* divider programming for frequency beyond 1000Mhz */
+                REG_FLD_MOD(PLLCTRL_CFG3, sd, 17, 10);
+                r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
+        } else {
+                r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
+        }
+
+        hdmi_write_reg(PLLCTRL_CFG2, r);
+
+        r = hdmi_read_reg(PLLCTRL_CFG4);
+        r = FLD_MOD(r, fmt->regm2, 24, 18);
+        r = FLD_MOD(r, fmt->regmf, 17, 0);
+
+        hdmi_write_reg(PLLCTRL_CFG4, r);
+
+        /* go now */
+        REG_FLD_MOD(PLLCTRL_PLL_GO, 0x1, 0, 0);
+
+        /* wait for bit change */
+        if (hdmi_wait_for_bit_change(PLLCTRL_PLL_GO, 0, 0, 1) != 1) {
+                DSSERR("PLL GO bit not set\n");
+                return -ETIMEDOUT;
+        }
+
+        /* Wait till the lock bit is set in PLL status */
+        if (hdmi_wait_for_bit_change(PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
+                DSSWARN("cannot lock PLL\n");
+                DSSWARN("CFG1 0x%x\n",
+                        hdmi_read_reg(PLLCTRL_CFG1));
+                DSSWARN("CFG2 0x%x\n",
+                        hdmi_read_reg(PLLCTRL_CFG2));
+                DSSWARN("CFG4 0x%x\n",
+                        hdmi_read_reg(PLLCTRL_CFG4));
+                return -ETIMEDOUT;
+        }
+
+        DSSDBG("PLL locked!\n");
+
+        return 0;
+}
+
+/* PHY_PWR_CMD */
+static int hdmi_set_phy_pwr(enum hdmi_phy_pwr val)
+{
+        /* Command for power control of HDMI PHY */
+        REG_FLD_MOD(HDMI_WP_PWR_CTRL, val, 7, 6);
+
+        /* Status of the power control of HDMI PHY */
+        if (hdmi_wait_for_bit_change(HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
+                DSSERR("Failed to set PHY power mode to %d\n", val);
+                return -ETIMEDOUT;
+        }
+
+        return 0;
+}
+
+/* PLL_PWR_CMD */
+static int hdmi_set_pll_pwr(enum hdmi_pll_pwr val)
+{
+        /* Command for power control of HDMI PLL */
+        REG_FLD_MOD(HDMI_WP_PWR_CTRL, val, 3, 2);
+
+        /* wait till PHY_PWR_STATUS is set */
+        if (hdmi_wait_for_bit_change(HDMI_WP_PWR_CTRL, 1, 0, val) != val) {
+                DSSERR("Failed to set PHY_PWR_STATUS\n");
+                return -ETIMEDOUT;
+        }
+
+        return 0;
+}
+
+static int hdmi_pll_reset(void)
+{
+        /* SYSRESET  controlled by power FSM */
+        REG_FLD_MOD(PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
+
+        /* READ 0x0 reset is in progress */
+        if (hdmi_wait_for_bit_change(PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
+                DSSERR("Failed to sysreset PLL\n");
+                return -ETIMEDOUT;
+        }
+
+        return 0;
+}
+
+static int hdmi_phy_init(void)
+{
+        u16 r = 0;
+
+        r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_LDOON);
+        if (r)
+                return r;
+
+        r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_TXON);
+        if (r)
+                return r;
+
+        /*
+         * Read address 0 in order to get the SCP reset done completed
+         * Dummy access performed to make sure reset is done
+         */
+        hdmi_read_reg(HDMI_TXPHY_TX_CTRL);
+
+        /*
+         * Write to phy address 0 to configure the clock
+         * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
+         */
+        REG_FLD_MOD(HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
+
+        /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
+        hdmi_write_reg(HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
+
+        /* Setup max LDO voltage */
+        REG_FLD_MOD(HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
+
+        /* Write to phy address 3 to change the polarity control */
+        REG_FLD_MOD(HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
+
+        return 0;
+}
+
+static int hdmi_wait_softreset(void)
+{
+        /* reset W1 */
+        REG_FLD_MOD(HDMI_WP_SYSCONFIG, 0x1, 0, 0);
+
+        /* wait till SOFTRESET == 0 */
+        if (hdmi_wait_for_bit_change(HDMI_WP_SYSCONFIG, 0, 0, 0) != 0) {
+                DSSERR("sysconfig reset failed\n");
+                return -ETIMEDOUT;
+        }
+
+        return 0;
+}
+
+static int hdmi_pll_program(struct hdmi_pll_info *fmt)
+{
+        u16 r = 0;
+        enum hdmi_clk_refsel refsel;
+
+        /* wait for wrapper reset */
+        r = hdmi_wait_softreset();
+        if (r)
+                return r;
+
+        r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF);
+        if (r)
+                return r;
+
+        r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
+        if (r)
+                return r;
+
+        r = hdmi_pll_reset();
+        if (r)
+                return r;
+
+        refsel = HDMI_REFSEL_SYSCLK;
+
+        r = hdmi_pll_init(refsel, fmt->dcofreq, fmt, fmt->regsd);
+        if (r)
+                return r;
+
+        return 0;
+}
+
+static void hdmi_phy_off(void)
+{
+        hdmi_set_phy_pwr(HDMI_PHYPWRCMD_OFF);
+}
+
+static int hdmi_core_ddc_edid(u8 *pedid, int ext)
+{
+        u32 i, j;
+        char checksum = 0;
+        u32 offset = 0;
+
+        /* Turn on CLK for DDC */
+        REG_FLD_MOD(HDMI_CORE_AV_DPD, 0x7, 2, 0);
+
+        /*
+         * SW HACK : Without the Delay DDC(i2c bus) reads 0 values /
+         * right shifted values( The behavior is not consistent and seen only
+         * with some TV's)
+         */
+        usleep_range(800, 1000);
+
+        if (!ext) {
+                /* Clk SCL Devices */
+                REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0xA, 3, 0);
+
+                /* HDMI_CORE_DDC_STATUS_IN_PROG */
+                if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS,
+                                                4, 4, 0) != 0) {
+                        DSSERR("Failed to program DDC\n");
+                        return -ETIMEDOUT;
+                }
+
+                /* Clear FIFO */
+                REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x9, 3, 0);
+
+                /* HDMI_CORE_DDC_STATUS_IN_PROG */
+                if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS,
+                                                4, 4, 0) != 0) {
+                        DSSERR("Failed to program DDC\n");
+                        return -ETIMEDOUT;
+                }
+
+        } else {
+                if (ext % 2 != 0)
+                        offset = 0x80;
+        }
+
+        /* Load Segment Address Register */
+        REG_FLD_MOD(HDMI_CORE_DDC_SEGM, ext/2, 7, 0);
+
+        /* Load Slave Address Register */
+        REG_FLD_MOD(HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
+
+        /* Load Offset Address Register */
+        REG_FLD_MOD(HDMI_CORE_DDC_OFFSET, offset, 7, 0);
+
+        /* Load Byte Count */
+        REG_FLD_MOD(HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
+        REG_FLD_MOD(HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
+
+        /* Set DDC_CMD */
+        if (ext)
+                REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x4, 3, 0);
+        else
+                REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x2, 3, 0);
+
+        /* HDMI_CORE_DDC_STATUS_BUS_LOW */
+        if (REG_GET(HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
+                DSSWARN("I2C Bus Low?\n");
+                return -EIO;
+        }
+        /* HDMI_CORE_DDC_STATUS_NO_ACK */
+        if (REG_GET(HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
+                DSSWARN("I2C No Ack\n");
+                return -EIO;
+        }
+
+        i = ext * 128;
+        j = 0;
+        while (((REG_GET(HDMI_CORE_DDC_STATUS, 4, 4) == 1) ||
+                        (REG_GET(HDMI_CORE_DDC_STATUS, 2, 2) == 0)) &&
+                        j < 128) {
+
+                if (REG_GET(HDMI_CORE_DDC_STATUS, 2, 2) == 0) {
+                        /* FIFO not empty */
+                        pedid[i++] = REG_GET(HDMI_CORE_DDC_DATA, 7, 0);
+                        j++;
+                }
+        }
+
+        for (j = 0; j < 128; j++)
+                checksum += pedid[j];
+
+        if (checksum != 0) {
+                DSSERR("E-EDID checksum failed!!\n");
+                return -EIO;
+        }
+
+        return 0;
+}
+
+static int read_edid(u8 *pedid, u16 max_length)
+{
+        int r = 0, n = 0, i = 0;
+        int max_ext_blocks = (max_length / 128) - 1;
+
+        r = hdmi_core_ddc_edid(pedid, 0);
+        if (r) {
+                return r;
+        } else {
+                n = pedid[0x7e];
+
+                /*
+                 * README: need to comply with max_length set by the caller.
+                 * Better implementation should be to allocate necessary
+                 * memory to store EDID according to nb_block field found
+                 * in first block
+                 */
+                if (n > max_ext_blocks)
+                        n = max_ext_blocks;
+
+                for (i = 1; i <= n; i++) {
+                        r = hdmi_core_ddc_edid(pedid, i);
+                        if (r)
+                                return r;
+                }
+        }
+        return 0;
+}
+
+static int get_timings_index(void)
+{
+        int code;
+
+        if (hdmi.mode == 0)
+                code = code_vesa[hdmi.code];
+        else
+                code = code_cea[hdmi.code];
+
+        if (code == -1) {
+                /* HDMI code 4 corresponds to 640 * 480 VGA */
+                hdmi.code = 4;
+                /* DVI mode 1 corresponds to HDMI 0 to DVI */
+                hdmi.mode = HDMI_DVI;
+
+                code = code_vesa[hdmi.code];
+        }
+        return code;
+}
+
+static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
+{
+        int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0;
+        int timing_vsync = 0, timing_hsync = 0;
+        struct omap_video_timings temp;
+        struct hdmi_cm cm = {-1};
+        DSSDBG("hdmi_get_code\n");
+
+        for (i = 0; i < OMAP_HDMI_TIMINGS_NB; i++) {
+                temp = cea_vesa_timings[i].timings;
+                if ((temp.pixel_clock == timing->pixel_clock) &&
+                        (temp.x_res == timing->x_res) &&
+                        (temp.y_res == timing->y_res)) {
+
+                        temp_hsync = temp.hfp + temp.hsw + temp.hbp;
+                        timing_hsync = timing->hfp + timing->hsw + timing->hbp;
+                        temp_vsync = temp.vfp + temp.vsw + temp.vbp;
+                        timing_vsync = timing->vfp + timing->vsw + timing->vbp;
+
+                        DSSDBG("temp_hsync = %d , temp_vsync = %d"
+                                "timing_hsync = %d, timing_vsync = %d\n",
+                                temp_hsync, temp_hsync,
+                                timing_hsync, timing_vsync);
+
+                        if ((temp_hsync == timing_hsync) &&
+                                        (temp_vsync == timing_vsync)) {
+                                code = i;
+                                cm.code = code_index[i];
+                                if (code < 14)
+                                        cm.mode = HDMI_HDMI;
+                                else
+                                        cm.mode = HDMI_DVI;
+                                DSSDBG("Hdmi_code = %d mode = %d\n",
+                                         cm.code, cm.mode);
+                                break;
+                         }
+                }
+        }
+
+        return cm;
+}
+
+static void get_horz_vert_timing_info(int current_descriptor_addrs, u8 *edid ,
+                struct omap_video_timings *timings)
+{
+        /* X and Y resolution */
+        timings->x_res = (((edid[current_descriptor_addrs + 4] & 0xF0) << 4) |
+                         edid[current_descriptor_addrs + 2]);
+        timings->y_res = (((edid[current_descriptor_addrs + 7] & 0xF0) << 4) |
+                         edid[current_descriptor_addrs + 5]);
+
+        timings->pixel_clock = ((edid[current_descriptor_addrs + 1] << 8) |
+                                edid[current_descriptor_addrs]);
+
+        timings->pixel_clock = 10 * timings->pixel_clock;
+
+        /* HORIZONTAL FRONT PORCH */
+        timings->hfp = edid[current_descriptor_addrs + 8] |
+                        ((edid[current_descriptor_addrs + 11] & 0xc0) << 2);
+        /* HORIZONTAL SYNC WIDTH */
+        timings->hsw = edid[current_descriptor_addrs + 9] |
+                        ((edid[current_descriptor_addrs + 11] & 0x30) << 4);
+        /* HORIZONTAL BACK PORCH */
+        timings->hbp = (((edid[current_descriptor_addrs + 4] & 0x0F) << 8) |
+                        edid[current_descriptor_addrs + 3]) -
+                        (timings->hfp + timings->hsw);
+        /* VERTICAL FRONT PORCH */
+        timings->vfp = ((edid[current_descriptor_addrs + 10] & 0xF0) >> 4) |
+                        ((edid[current_descriptor_addrs + 11] & 0x0f) << 2);
+        /* VERTICAL SYNC WIDTH */
+        timings->vsw = (edid[current_descriptor_addrs + 10] & 0x0F) |
+                        ((edid[current_descriptor_addrs + 11] & 0x03) << 4);
+        /* VERTICAL BACK PORCH */
+        timings->vbp = (((edid[current_descriptor_addrs + 7] & 0x0F) << 8) |
+                        edid[current_descriptor_addrs + 6]) -
+                        (timings->vfp + timings->vsw);
+
+}
+
+/* Description : This function gets the resolution information from EDID */
+static void get_edid_timing_data(u8 *edid)
+{
+        u8 count;
+        u16 current_descriptor_addrs;
+        struct hdmi_cm cm;
+        struct omap_video_timings edid_timings;
+
+        /* seach block 0, there are 4 DTDs arranged in priority order */
+        for (count = 0; count < EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR; count++) {
+                current_descriptor_addrs =
+                        EDID_DESCRIPTOR_BLOCK0_ADDRESS +
+                        count * EDID_TIMING_DESCRIPTOR_SIZE;
+                get_horz_vert_timing_info(current_descriptor_addrs,
+                                edid, &edid_timings);
+                cm = hdmi_get_code(&edid_timings);
+                DSSDBG("Block0[%d] value matches code = %d , mode = %d\n",
+                        count, cm.code, cm.mode);
+                if (cm.code == -1) {
+                        continue;
+                } else {
+                        hdmi.code = cm.code;
+                        hdmi.mode = cm.mode;
+                        DSSDBG("code = %d , mode = %d\n",
+                                hdmi.code, hdmi.mode);
+                        return;
+                }
+        }
+        if (edid[0x7e] != 0x00) {
+                for (count = 0; count < EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR;
+                        count++) {
+                        current_descriptor_addrs =
+                        EDID_DESCRIPTOR_BLOCK1_ADDRESS +
+                        count * EDID_TIMING_DESCRIPTOR_SIZE;
+                        get_horz_vert_timing_info(current_descriptor_addrs,
+                                                edid, &edid_timings);
+                        cm = hdmi_get_code(&edid_timings);
+                        DSSDBG("Block1[%d] value matches code = %d, mode = %d",
+                                count, cm.code, cm.mode);
+                        if (cm.code == -1) {
+                                continue;
+                        } else {
+                                hdmi.code = cm.code;
+                                hdmi.mode = cm.mode;
+                                DSSDBG("code = %d , mode = %d\n",
+                                        hdmi.code, hdmi.mode);
+                                return;
+                        }
+                }
+        }
+
+        DSSINFO("no valid timing found , falling back to VGA\n");
+        hdmi.code = 4; /* setting default value of 640 480 VGA */
+        hdmi.mode = HDMI_DVI;
+}
+
+static void hdmi_read_edid(struct omap_video_timings *dp)
+{
+        int ret = 0, code;
+
+        memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH);
+
+        if (!hdmi.edid_set)
+                ret = read_edid(hdmi.edid, HDMI_EDID_MAX_LENGTH);
+
+        if (!ret) {
+                if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) {
+                        /* search for timings of default resolution */
+                        get_edid_timing_data(hdmi.edid);
+                        hdmi.edid_set = true;
+                }
+        } else {
+                DSSWARN("failed to read E-EDID\n");
+        }
+
+        if (!hdmi.edid_set) {
+                DSSINFO("fallback to VGA\n");
+                hdmi.code = 4; /* setting default value of 640 480 VGA */
+                hdmi.mode = HDMI_DVI;
+        }
+
+        code = get_timings_index();
+
+        *dp = cea_vesa_timings[code].timings;
+}
+
+static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
+                        struct hdmi_core_infoframe_avi *avi_cfg,
+                        struct hdmi_core_packet_enable_repeat *repeat_cfg)
+{
+        DSSDBG("Enter hdmi_core_init\n");
+
+        /* video core */
+        video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
+        video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
+        video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
+        video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
+        video_cfg->hdmi_dvi = HDMI_DVI;
+        video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
+
+        /* info frame */
+        avi_cfg->db1_format = 0;
+        avi_cfg->db1_active_info = 0;
+        avi_cfg->db1_bar_info_dv = 0;
+        avi_cfg->db1_scan_info = 0;
+        avi_cfg->db2_colorimetry = 0;
+        avi_cfg->db2_aspect_ratio = 0;
+        avi_cfg->db2_active_fmt_ar = 0;
+        avi_cfg->db3_itc = 0;
+        avi_cfg->db3_ec = 0;
+        avi_cfg->db3_q_range = 0;
+        avi_cfg->db3_nup_scaling = 0;
+        avi_cfg->db4_videocode = 0;
+        avi_cfg->db5_pixel_repeat = 0;
+        avi_cfg->db6_7_line_eoftop = 0 ;
+        avi_cfg->db8_9_line_sofbottom = 0;
+        avi_cfg->db10_11_pixel_eofleft = 0;
+        avi_cfg->db12_13_pixel_sofright = 0;
+
+        /* packet enable and repeat */
+        repeat_cfg->audio_pkt = 0;
+        repeat_cfg->audio_pkt_repeat = 0;
+        repeat_cfg->avi_infoframe = 0;
+        repeat_cfg->avi_infoframe_repeat = 0;
+        repeat_cfg->gen_cntrl_pkt = 0;
+        repeat_cfg->gen_cntrl_pkt_repeat = 0;
+        repeat_cfg->generic_pkt = 0;
+        repeat_cfg->generic_pkt_repeat = 0;
+}
+
+static void hdmi_core_powerdown_disable(void)
+{
+        DSSDBG("Enter hdmi_core_powerdown_disable\n");
+        REG_FLD_MOD(HDMI_CORE_CTRL1, 0x0, 0, 0);
+}
+
+static void hdmi_core_swreset_release(void)
+{
+        DSSDBG("Enter hdmi_core_swreset_release\n");
+        REG_FLD_MOD(HDMI_CORE_SYS_SRST, 0x0, 0, 0);
+}
+
+static void hdmi_core_swreset_assert(void)
+{
+        DSSDBG("Enter hdmi_core_swreset_assert\n");
+        REG_FLD_MOD(HDMI_CORE_SYS_SRST, 0x1, 0, 0);
+}
+
+/* DSS_HDMI_CORE_VIDEO_CONFIG */
+static void hdmi_core_video_config(struct hdmi_core_video_config *cfg)
+{
+        u32 r = 0;
+
+        /* sys_ctrl1 default configuration not tunable */
+        r = hdmi_read_reg(HDMI_CORE_CTRL1);
+        r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
+        r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
+        r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
+        r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
+        hdmi_write_reg(HDMI_CORE_CTRL1, r);
+
+        REG_FLD_MOD(HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
+
+        /* Vid_Mode */
+        r = hdmi_read_reg(HDMI_CORE_SYS_VID_MODE);
+
+        /* dither truncation configuration */
+        if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
+                r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
+                r = FLD_MOD(r, 1, 5, 5);
+        } else {
+                r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
+                r = FLD_MOD(r, 0, 5, 5);
+        }
+        hdmi_write_reg(HDMI_CORE_SYS_VID_MODE, r);
+
+        /* HDMI_Ctrl */
+        r = hdmi_read_reg(HDMI_CORE_AV_HDMI_CTRL);
+        r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
+        r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
+        r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
+        hdmi_write_reg(HDMI_CORE_AV_HDMI_CTRL, r);
+
+        /* TMDS_CTRL */
+        REG_FLD_MOD(HDMI_CORE_SYS_TMDS_CTRL,
+                cfg->tclk_sel_clkmult, 6, 5);
+}
+
+static void hdmi_core_aux_infoframe_avi_config(
+                struct hdmi_core_infoframe_avi info_avi)
+{
+        u32 val;
+        char sum = 0, checksum = 0;
+
+        sum += 0x82 + 0x002 + 0x00D;
+        hdmi_write_reg(HDMI_CORE_AV_AVI_TYPE, 0x082);
+        hdmi_write_reg(HDMI_CORE_AV_AVI_VERS, 0x002);
+        hdmi_write_reg(HDMI_CORE_AV_AVI_LEN, 0x00D);
+
+        val = (info_avi.db1_format << 5) |
+                (info_avi.db1_active_info << 4) |
+                (info_avi.db1_bar_info_dv << 2) |
+                (info_avi.db1_scan_info);
+        hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(0), val);
+        sum += val;
+
+        val = (info_avi.db2_colorimetry << 6) |
+                (info_avi.db2_aspect_ratio << 4) |
+                (info_avi.db2_active_fmt_ar);
+        hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(1), val);
+        sum += val;
+
+        val = (info_avi.db3_itc << 7) |
+                (info_avi.db3_ec << 4) |
+                (info_avi.db3_q_range << 2) |
+                (info_avi.db3_nup_scaling);
+        hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(2), val);
+        sum += val;
+
+        hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(3), info_avi.db4_videocode);
+        sum += info_avi.db4_videocode;
+
+        val = info_avi.db5_pixel_repeat;
+        hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(4), val);
+        sum += val;
+
+        val = info_avi.db6_7_line_eoftop & 0x00FF;
+        hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(5), val);
+        sum += val;
+
+        val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
+        hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(6), val);
+        sum += val;
+
+        val = info_avi.db8_9_line_sofbottom & 0x00FF;
+        hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(7), val);
+        sum += val;
+
+        val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
+        hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(8), val);
+        sum += val;
+
+        val = info_avi.db10_11_pixel_eofleft & 0x00FF;
+        hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(9), val);
+        sum += val;
+
+        val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
+        hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(10), val);
+        sum += val;
+
+        val = info_avi.db12_13_pixel_sofright & 0x00FF;
+        hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(11), val);
+        sum += val;
+
+        val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
+        hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(12), val);
+        sum += val;
+
+        checksum = 0x100 - sum;
+        hdmi_write_reg(HDMI_CORE_AV_AVI_CHSUM, checksum);
+}
+
+static void hdmi_core_av_packet_config(
+                struct hdmi_core_packet_enable_repeat repeat_cfg)
+{
+        /* enable/repeat the infoframe */
+        hdmi_write_reg(HDMI_CORE_AV_PB_CTRL1,
+                (repeat_cfg.audio_pkt << 5) |
+                (repeat_cfg.audio_pkt_repeat << 4) |
+                (repeat_cfg.avi_infoframe << 1) |
+                (repeat_cfg.avi_infoframe_repeat));
+
+        /* enable/repeat the packet */
+        hdmi_write_reg(HDMI_CORE_AV_PB_CTRL2,
+                (repeat_cfg.gen_cntrl_pkt << 3) |
+                (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
+                (repeat_cfg.generic_pkt << 1) |
+                (repeat_cfg.generic_pkt_repeat));
+}
+
+static void hdmi_wp_init(struct omap_video_timings *timings,
+                        struct hdmi_video_format *video_fmt,
+                        struct hdmi_video_interface *video_int)
+{
+        DSSDBG("Enter hdmi_wp_init\n");
+
+        timings->hbp = 0;
+        timings->hfp = 0;
+        timings->hsw = 0;
+        timings->vbp = 0;
+        timings->vfp = 0;
+        timings->vsw = 0;
+
+        video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
+        video_fmt->y_res = 0;
+        video_fmt->x_res = 0;
+
+        video_int->vsp = 0;
+        video_int->hsp = 0;
+
+        video_int->interlacing = 0;
+        video_int->tm = 0; /* HDMI_TIMING_SLAVE */
+
+}
+
+static void hdmi_wp_video_start(bool start)
+{
+        REG_FLD_MOD(HDMI_WP_VIDEO_CFG, start, 31, 31);
+}
+
+static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
+        struct omap_video_timings *timings, struct hdmi_config *param)
+{
+        DSSDBG("Enter hdmi_wp_video_init_format\n");
+
+        video_fmt->y_res = param->timings.timings.y_res;
+        video_fmt->x_res = param->timings.timings.x_res;
+
+        timings->hbp = param->timings.timings.hbp;
+        timings->hfp = param->timings.timings.hfp;
+        timings->hsw = param->timings.timings.hsw;
+        timings->vbp = param->timings.timings.vbp;
+        timings->vfp = param->timings.timings.vfp;
+        timings->vsw = param->timings.timings.vsw;
+}
+
+static void hdmi_wp_video_config_format(
+                struct hdmi_video_format *video_fmt)
+{
+        u32 l = 0;
+
+        REG_FLD_MOD(HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, 10, 8);
+
+        l |= FLD_VAL(video_fmt->y_res, 31, 16);
+        l |= FLD_VAL(video_fmt->x_res, 15, 0);
+        hdmi_write_reg(HDMI_WP_VIDEO_SIZE, l);
+}
+
+static void hdmi_wp_video_config_interface(
+                struct hdmi_video_interface *video_int)
+{
+        u32 r;
+        DSSDBG("Enter hdmi_wp_video_config_interface\n");
+
+        r = hdmi_read_reg(HDMI_WP_VIDEO_CFG);
+        r = FLD_MOD(r, video_int->vsp, 7, 7);
+        r = FLD_MOD(r, video_int->hsp, 6, 6);
+        r = FLD_MOD(r, video_int->interlacing, 3, 3);
+        r = FLD_MOD(r, video_int->tm, 1, 0);
+        hdmi_write_reg(HDMI_WP_VIDEO_CFG, r);
+}
+
+static void hdmi_wp_video_config_timing(
+                struct omap_video_timings *timings)
+{
+        u32 timing_h = 0;
+        u32 timing_v = 0;
+
+        DSSDBG("Enter hdmi_wp_video_config_timing\n");
+
+        timing_h |= FLD_VAL(timings->hbp, 31, 20);
+        timing_h |= FLD_VAL(timings->hfp, 19, 8);
+        timing_h |= FLD_VAL(timings->hsw, 7, 0);
+        hdmi_write_reg(HDMI_WP_VIDEO_TIMING_H, timing_h);
+
+        timing_v |= FLD_VAL(timings->vbp, 31, 20);
+        timing_v |= FLD_VAL(timings->vfp, 19, 8);
+        timing_v |= FLD_VAL(timings->vsw, 7, 0);
+        hdmi_write_reg(HDMI_WP_VIDEO_TIMING_V, timing_v);
+}
+
+static void hdmi_basic_configure(struct hdmi_config *cfg)
+{
+        /* HDMI */
+        struct omap_video_timings video_timing;
+        struct hdmi_video_format video_format;
+        struct hdmi_video_interface video_interface;
+        /* HDMI core */
+        struct hdmi_core_infoframe_avi avi_cfg;
+        struct hdmi_core_video_config v_core_cfg;
+        struct hdmi_core_packet_enable_repeat repeat_cfg;
+
+        hdmi_wp_init(&video_timing, &video_format,
+                &video_interface);
+
+        hdmi_core_init(&v_core_cfg,
+                &avi_cfg,
+                &repeat_cfg);
+
+        hdmi_wp_video_init_format(&video_format,
+                        &video_timing, cfg);
+
+        hdmi_wp_video_config_timing(&video_timing);
+
+        /* video config */
+        video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
+
+        hdmi_wp_video_config_format(&video_format);
+
+        video_interface.vsp = cfg->timings.vsync_pol;
+        video_interface.hsp = cfg->timings.hsync_pol;
+        video_interface.interlacing = cfg->interlace;
+        video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */
+
+        hdmi_wp_video_config_interface(&video_interface);
+
+        /*
+         * configure core video part
+         * set software reset in the core
+         */
+        hdmi_core_swreset_assert();
+
+        /* power down off */
+        hdmi_core_powerdown_disable();
+
+        v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
+        v_core_cfg.hdmi_dvi = cfg->cm.mode;
+
+        hdmi_core_video_config(&v_core_cfg);
+
+        /* release software reset in the core */
+        hdmi_core_swreset_release();
+
+        /*
+         * configure packet
+         * info frame video see doc CEA861-D page 65
+         */
+        avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
+        avi_cfg.db1_active_info =
+                HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
+        avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
+        avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
+        avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
+        avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
+        avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
+        avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
+        avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
+        avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
+        avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
+        avi_cfg.db4_videocode = cfg->cm.code;
+        avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
+        avi_cfg.db6_7_line_eoftop = 0;
+        avi_cfg.db8_9_line_sofbottom = 0;
+        avi_cfg.db10_11_pixel_eofleft = 0;
+        avi_cfg.db12_13_pixel_sofright = 0;
+
+        hdmi_core_aux_infoframe_avi_config(avi_cfg);
+
+        /* enable/repeat the infoframe */
+        repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
+        repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
+        /* wakeup */
+        repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
+        repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
+        hdmi_core_av_packet_config(repeat_cfg);
+}
+
+static void update_hdmi_timings(struct hdmi_config *cfg,
+                struct omap_video_timings *timings, int code)
+{
+        cfg->timings.timings.x_res = timings->x_res;
+        cfg->timings.timings.y_res = timings->y_res;
+        cfg->timings.timings.hbp = timings->hbp;
+        cfg->timings.timings.hfp = timings->hfp;
+        cfg->timings.timings.hsw = timings->hsw;
+        cfg->timings.timings.vbp = timings->vbp;
+        cfg->timings.timings.vfp = timings->vfp;
+        cfg->timings.timings.vsw = timings->vsw;
+        cfg->timings.timings.pixel_clock = timings->pixel_clock;
+        cfg->timings.vsync_pol = cea_vesa_timings[code].vsync_pol;
+        cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol;
+}
+
+static void hdmi_compute_pll(unsigned long clkin, int phy,
+        int n, struct hdmi_pll_info *pi)
+{
+        unsigned long refclk;
+        u32 mf;
+
+        /*
+         * Input clock is predivided by N + 1
+         * out put of which is reference clk
+         */
+        refclk = clkin / (n + 1);
+        pi->regn = n;
+
+        /*
+         * multiplier is pixel_clk/ref_clk
+         * Multiplying by 100 to avoid fractional part removal
+         */
+        pi->regm = (phy * 100/(refclk))/100;
+        pi->regm2 = 1;
+
+        /*
+         * fractional multiplier is remainder of the difference between
+         * multiplier and actual phy(required pixel clock thus should be
+         * multiplied by 2^18(262144) divided by the reference clock
+         */
+        mf = (phy - pi->regm * refclk) * 262144;
+        pi->regmf = mf/(refclk);
+
+        /*
+         * Dcofreq should be set to 1 if required pixel clock
+         * is greater than 1000MHz
+         */
+        pi->dcofreq = phy > 1000 * 100;
+        pi->regsd = ((pi->regm * clkin / 10) / ((n + 1) * 250) + 5) / 10;
+
+        DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
+        DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
+}
+
+static void hdmi_enable_clocks(int enable)
+{
+        if (enable)
+                dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK |
+                                DSS_CLK_SYSCK | DSS_CLK_VIDFCK);
+        else
+                dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK |
+                                DSS_CLK_SYSCK | DSS_CLK_VIDFCK);
+}
+
+static int hdmi_power_on(struct omap_dss_device *dssdev)
+{
+        int r, code = 0;
+        struct hdmi_pll_info pll_data;
+        struct omap_video_timings *p;
+        int clkin, n, phy;
+
+        hdmi_enable_clocks(1);
+
+        dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 0);
+
+        p = &dssdev->panel.timings;
+
+        DSSDBG("hdmi_power_on x_res= %d y_res = %d\n",
+                dssdev->panel.timings.x_res,
+                dssdev->panel.timings.y_res);
+
+        if (!hdmi.custom_set) {
+                DSSDBG("Read EDID as no EDID is not set on poweron\n");
+                hdmi_read_edid(p);
+        }
+        code = get_timings_index();
+        dssdev->panel.timings = cea_vesa_timings[code].timings;
+        update_hdmi_timings(&hdmi.cfg, p, code);
+
+        clkin = 3840; /* 38.4 MHz */
+        n = 15; /* this is a constant for our math */
+        phy = p->pixel_clock;
+
+        hdmi_compute_pll(clkin, phy, n, &pll_data);
+
+        hdmi_wp_video_start(0);
+
+        /* config the PLL and PHY first */
+        r = hdmi_pll_program(&pll_data);
+        if (r) {
+                DSSDBG("Failed to lock PLL\n");
+                goto err;
+        }
+
+        r = hdmi_phy_init();
+        if (r) {
+                DSSDBG("Failed to start PHY\n");
+                goto err;
+        }
+
+        hdmi.cfg.cm.mode = hdmi.mode;
+        hdmi.cfg.cm.code = hdmi.code;
+        hdmi_basic_configure(&hdmi.cfg);
+
+        /* Make selection of HDMI in DSS */
+        dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
+
+        /* Select the dispc clock source as PRCM clock, to ensure that it is not
+         * DSI PLL source as the clock selected by DSI PLL might not be
+         * sufficient for the resolution selected / that can be changed
+         * dynamically by user. This can be moved to single location , say
+         * Boardfile.
+         */
+        dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
+
+        /* bypass TV gamma table */
+        dispc_enable_gamma_table(0);
+
+        /* tv size */
+        dispc_set_digit_size(dssdev->panel.timings.x_res,
+                        dssdev->panel.timings.y_res);
+
+        dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 1);
+
+        hdmi_wp_video_start(1);
+
+        return 0;
+err:
+        hdmi_enable_clocks(0);
+        return -EIO;
+}
+
+static void hdmi_power_off(struct omap_dss_device *dssdev)
+{
+        dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 0);
+
+        hdmi_wp_video_start(0);
+        hdmi_phy_off();
+        hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF);
+        hdmi_enable_clocks(0);
+
+        hdmi.edid_set = 0;
+}
+
+int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
+                                        struct omap_video_timings *timings)
+{
+        struct hdmi_cm cm;
+
+        cm = hdmi_get_code(timings);
+        if (cm.code == -1) {
+                DSSERR("Invalid timing entered\n");
+                return -EINVAL;
+        }
+
+        return 0;
+
+}
+
+void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev)
+{
+        struct hdmi_cm cm;
+
+        hdmi.custom_set = 1;
+        cm = hdmi_get_code(&dssdev->panel.timings);
+        hdmi.code = cm.code;
+        hdmi.mode = cm.mode;
+        omapdss_hdmi_display_enable(dssdev);
+        hdmi.custom_set = 0;
+}
+
+int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
+{
+        int r = 0;
+
+        DSSDBG("ENTER hdmi_display_enable\n");
+
+        mutex_lock(&hdmi.lock);
+
+        r = omap_dss_start_device(dssdev);
+        if (r) {
+                DSSERR("failed to start device\n");
+                goto err0;
+        }
+
+        if (dssdev->platform_enable) {
+                r = dssdev->platform_enable(dssdev);
+                if (r) {
+                        DSSERR("failed to enable GPIO's\n");
+                        goto err1;
+                }
+        }
+
+        r = hdmi_power_on(dssdev);
+        if (r) {
+                DSSERR("failed to power on device\n");
+                goto err2;
+        }
+
+        mutex_unlock(&hdmi.lock);
+        return 0;
+
+err2:
+        if (dssdev->platform_disable)
+                dssdev->platform_disable(dssdev);
+err1:
+        omap_dss_stop_device(dssdev);
+err0:
+        mutex_unlock(&hdmi.lock);
+        return r;
+}
+
+void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
+{
+        DSSDBG("Enter hdmi_display_disable\n");
+
+        mutex_lock(&hdmi.lock);
+
+        hdmi_power_off(dssdev);
+
+        if (dssdev->platform_disable)
+                dssdev->platform_disable(dssdev);
+
+        omap_dss_stop_device(dssdev);
+
+        mutex_unlock(&hdmi.lock);
+}
+
+/* HDMI HW IP initialisation */
+static int omapdss_hdmihw_probe(struct platform_device *pdev)
+{
+        struct resource *hdmi_mem;
+
+        hdmi.pdata = pdev->dev.platform_data;
+        hdmi.pdev = pdev;
+
+        mutex_init(&hdmi.lock);
+
+        hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
+        if (!hdmi_mem) {
+                DSSERR("can't get IORESOURCE_MEM HDMI\n");
+                return -EINVAL;
+        }
+
+        /* Base address taken from platform */
+        hdmi.base_wp = ioremap(hdmi_mem->start, resource_size(hdmi_mem));
+        if (!hdmi.base_wp) {
+                DSSERR("can't ioremap WP\n");
+                return -ENOMEM;
+        }
+
+        hdmi_panel_init();
+
+        return 0;
+}
+
+static int omapdss_hdmihw_remove(struct platform_device *pdev)
+{
+        hdmi_panel_exit();
+
+        iounmap(hdmi.base_wp);
+
+        return 0;
+}
+
+static struct platform_driver omapdss_hdmihw_driver = {
+        .probe          = omapdss_hdmihw_probe,
+        .remove         = omapdss_hdmihw_remove,
+        .driver         = {
+                .name   = "omapdss_hdmi",
+                .owner  = THIS_MODULE,
+        },
+};
+
+int hdmi_init_platform_driver(void)
+{
+        return platform_driver_register(&omapdss_hdmihw_driver);
+}
+
+void hdmi_uninit_platform_driver(void)
+{
+        return platform_driver_unregister(&omapdss_hdmihw_driver);
+}
diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h
new file mode 100644
index 000000000000..9887ab96da3c
--- /dev/null
+++ b/drivers/video/omap2/dss/hdmi.h
@@ -0,0 +1,415 @@
+/*
+ * hdmi.h
+ *
+ * HDMI driver definition for TI OMAP4 processors.
+ *
+ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _OMAP4_DSS_HDMI_H_
+#define _OMAP4_DSS_HDMI_H_
+
+#include <linux/string.h>
+#include <plat/display.h>
+
+#define HDMI_WP         0x0
+#define HDMI_CORE_SYS           0x400
+#define HDMI_CORE_AV            0x900
+#define HDMI_PLLCTRL            0x200
+#define HDMI_PHY                0x300
+
+struct hdmi_reg { u16 idx; };
+
+#define HDMI_REG(idx)                   ((const struct hdmi_reg) { idx })
+
+/* HDMI Wrapper */
+#define HDMI_WP_REG(idx)                        HDMI_REG(HDMI_WP + idx)
+
+#define HDMI_WP_REVISION                        HDMI_WP_REG(0x0)
+#define HDMI_WP_SYSCONFIG                       HDMI_WP_REG(0x10)
+#define HDMI_WP_IRQSTATUS_RAW                   HDMI_WP_REG(0x24)
+#define HDMI_WP_IRQSTATUS                       HDMI_WP_REG(0x28)
+#define HDMI_WP_PWR_CTRL                        HDMI_WP_REG(0x40)
+#define HDMI_WP_IRQENABLE_SET                   HDMI_WP_REG(0x2C)
+#define HDMI_WP_VIDEO_CFG                       HDMI_WP_REG(0x50)
+#define HDMI_WP_VIDEO_SIZE                      HDMI_WP_REG(0x60)
+#define HDMI_WP_VIDEO_TIMING_H                  HDMI_WP_REG(0x68)
+#define HDMI_WP_VIDEO_TIMING_V                  HDMI_WP_REG(0x6C)
+#define HDMI_WP_WP_CLK                          HDMI_WP_REG(0x70)
+
+/* HDMI IP Core System */
+#define HDMI_CORE_SYS_REG(idx)                  HDMI_REG(HDMI_CORE_SYS + idx)
+
+#define HDMI_CORE_SYS_VND_IDL                   HDMI_CORE_SYS_REG(0x0)
+#define HDMI_CORE_SYS_DEV_IDL                   HDMI_CORE_SYS_REG(0x8)
+#define HDMI_CORE_SYS_DEV_IDH                   HDMI_CORE_SYS_REG(0xC)
+#define HDMI_CORE_SYS_DEV_REV                   HDMI_CORE_SYS_REG(0x10)
+#define HDMI_CORE_SYS_SRST                      HDMI_CORE_SYS_REG(0x14)
+#define HDMI_CORE_CTRL1                 HDMI_CORE_SYS_REG(0x20)
+#define HDMI_CORE_SYS_SYS_STAT                  HDMI_CORE_SYS_REG(0x24)
+#define HDMI_CORE_SYS_VID_ACEN                  HDMI_CORE_SYS_REG(0x124)
+#define HDMI_CORE_SYS_VID_MODE                  HDMI_CORE_SYS_REG(0x128)
+#define HDMI_CORE_SYS_INTR_STATE                HDMI_CORE_SYS_REG(0x1C0)
+#define HDMI_CORE_SYS_INTR1                     HDMI_CORE_SYS_REG(0x1C4)
+#define HDMI_CORE_SYS_INTR2                     HDMI_CORE_SYS_REG(0x1C8)
+#define HDMI_CORE_SYS_INTR3                     HDMI_CORE_SYS_REG(0x1CC)
+#define HDMI_CORE_SYS_INTR4                     HDMI_CORE_SYS_REG(0x1D0)
+#define HDMI_CORE_SYS_UMASK1                    HDMI_CORE_SYS_REG(0x1D4)
+#define HDMI_CORE_SYS_TMDS_CTRL         HDMI_CORE_SYS_REG(0x208)
+#define HDMI_CORE_SYS_DE_DLY                    HDMI_CORE_SYS_REG(0xC8)
+#define HDMI_CORE_SYS_DE_CTRL                   HDMI_CORE_SYS_REG(0xCC)
+#define HDMI_CORE_SYS_DE_TOP                    HDMI_CORE_SYS_REG(0xD0)
+#define HDMI_CORE_SYS_DE_CNTL                   HDMI_CORE_SYS_REG(0xD8)
+#define HDMI_CORE_SYS_DE_CNTH                   HDMI_CORE_SYS_REG(0xDC)
+#define HDMI_CORE_SYS_DE_LINL                   HDMI_CORE_SYS_REG(0xE0)
+#define HDMI_CORE_SYS_DE_LINH_1         HDMI_CORE_SYS_REG(0xE4)
+#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
+#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
+#define HDMI_CORE_CTRL1_BSEL_24BITBUS           0x1
+#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
+
+/* HDMI DDC E-DID */
+#define HDMI_CORE_DDC_CMD                       HDMI_CORE_SYS_REG(0x3CC)
+#define HDMI_CORE_DDC_STATUS                    HDMI_CORE_SYS_REG(0x3C8)
+#define HDMI_CORE_DDC_ADDR                      HDMI_CORE_SYS_REG(0x3B4)
+#define HDMI_CORE_DDC_OFFSET                    HDMI_CORE_SYS_REG(0x3BC)
+#define HDMI_CORE_DDC_COUNT1                    HDMI_CORE_SYS_REG(0x3C0)
+#define HDMI_CORE_DDC_COUNT2                    HDMI_CORE_SYS_REG(0x3C4)
+#define HDMI_CORE_DDC_DATA                      HDMI_CORE_SYS_REG(0x3D0)
+#define HDMI_CORE_DDC_SEGM                      HDMI_CORE_SYS_REG(0x3B8)
+
+/* HDMI IP Core Audio Video */
+#define HDMI_CORE_AV_REG(idx)                   HDMI_REG(HDMI_CORE_AV + idx)
+
+#define HDMI_CORE_AV_HDMI_CTRL                  HDMI_CORE_AV_REG(0xBC)
+#define HDMI_CORE_AV_DPD                        HDMI_CORE_AV_REG(0xF4)
+#define HDMI_CORE_AV_PB_CTRL1                   HDMI_CORE_AV_REG(0xF8)
+#define HDMI_CORE_AV_PB_CTRL2                   HDMI_CORE_AV_REG(0xFC)
+#define HDMI_CORE_AV_AVI_TYPE                   HDMI_CORE_AV_REG(0x100)
+#define HDMI_CORE_AV_AVI_VERS                   HDMI_CORE_AV_REG(0x104)
+#define HDMI_CORE_AV_AVI_LEN                    HDMI_CORE_AV_REG(0x108)
+#define HDMI_CORE_AV_AVI_CHSUM                  HDMI_CORE_AV_REG(0x10C)
+#define HDMI_CORE_AV_AVI_DBYTE(n)               HDMI_CORE_AV_REG(n * 4 + 0x110)
+#define HDMI_CORE_AV_AVI_DBYTE_NELEMS           HDMI_CORE_AV_REG(15)
+#define HDMI_CORE_AV_SPD_DBYTE                  HDMI_CORE_AV_REG(0x190)
+#define HDMI_CORE_AV_SPD_DBYTE_NELEMS           HDMI_CORE_AV_REG(27)
+#define HDMI_CORE_AV_MPEG_DBYTE         HDMI_CORE_AV_REG(0x290)
+#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS          HDMI_CORE_AV_REG(27)
+#define HDMI_CORE_AV_GEN_DBYTE                  HDMI_CORE_AV_REG(0x300)
+#define HDMI_CORE_AV_GEN_DBYTE_NELEMS           HDMI_CORE_AV_REG(31)
+#define HDMI_CORE_AV_GEN2_DBYTE         HDMI_CORE_AV_REG(0x380)
+#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS          HDMI_CORE_AV_REG(31)
+#define HDMI_CORE_AV_ACR_CTRL                   HDMI_CORE_AV_REG(0x4)
+#define HDMI_CORE_AV_FREQ_SVAL                  HDMI_CORE_AV_REG(0x8)
+#define HDMI_CORE_AV_N_SVAL1                    HDMI_CORE_AV_REG(0xC)
+#define HDMI_CORE_AV_N_SVAL2                    HDMI_CORE_AV_REG(0x10)
+#define HDMI_CORE_AV_N_SVAL3                    HDMI_CORE_AV_REG(0x14)
+#define HDMI_CORE_AV_CTS_SVAL1                  HDMI_CORE_AV_REG(0x18)
+#define HDMI_CORE_AV_CTS_SVAL2                  HDMI_CORE_AV_REG(0x1C)
+#define HDMI_CORE_AV_CTS_SVAL3                  HDMI_CORE_AV_REG(0x20)
+#define HDMI_CORE_AV_CTS_HVAL1                  HDMI_CORE_AV_REG(0x24)
+#define HDMI_CORE_AV_CTS_HVAL2                  HDMI_CORE_AV_REG(0x28)
+#define HDMI_CORE_AV_CTS_HVAL3                  HDMI_CORE_AV_REG(0x2C)
+#define HDMI_CORE_AV_AUD_MODE                   HDMI_CORE_AV_REG(0x50)
+#define HDMI_CORE_AV_SPDIF_CTRL         HDMI_CORE_AV_REG(0x54)
+#define HDMI_CORE_AV_HW_SPDIF_FS                HDMI_CORE_AV_REG(0x60)
+#define HDMI_CORE_AV_SWAP_I2S                   HDMI_CORE_AV_REG(0x64)
+#define HDMI_CORE_AV_SPDIF_ERTH         HDMI_CORE_AV_REG(0x6C)
+#define HDMI_CORE_AV_I2S_IN_MAP         HDMI_CORE_AV_REG(0x70)
+#define HDMI_CORE_AV_I2S_IN_CTRL                HDMI_CORE_AV_REG(0x74)
+#define HDMI_CORE_AV_I2S_CHST0                  HDMI_CORE_AV_REG(0x78)
+#define HDMI_CORE_AV_I2S_CHST1                  HDMI_CORE_AV_REG(0x7C)
+#define HDMI_CORE_AV_I2S_CHST2                  HDMI_CORE_AV_REG(0x80)
+#define HDMI_CORE_AV_I2S_CHST4                  HDMI_CORE_AV_REG(0x84)
+#define HDMI_CORE_AV_I2S_CHST5                  HDMI_CORE_AV_REG(0x88)
+#define HDMI_CORE_AV_ASRC                       HDMI_CORE_AV_REG(0x8C)
+#define HDMI_CORE_AV_I2S_IN_LEN         HDMI_CORE_AV_REG(0x90)
+#define HDMI_CORE_AV_HDMI_CTRL                  HDMI_CORE_AV_REG(0xBC)
+#define HDMI_CORE_AV_AUDO_TXSTAT                HDMI_CORE_AV_REG(0xC0)
+#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1           HDMI_CORE_AV_REG(0xCC)
+#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2           HDMI_CORE_AV_REG(0xD0)
+#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3           HDMI_CORE_AV_REG(0xD4)
+#define HDMI_CORE_AV_TEST_TXCTRL                HDMI_CORE_AV_REG(0xF0)
+#define HDMI_CORE_AV_DPD                        HDMI_CORE_AV_REG(0xF4)
+#define HDMI_CORE_AV_PB_CTRL1                   HDMI_CORE_AV_REG(0xF8)
+#define HDMI_CORE_AV_PB_CTRL2                   HDMI_CORE_AV_REG(0xFC)
+#define HDMI_CORE_AV_AVI_TYPE                   HDMI_CORE_AV_REG(0x100)
+#define HDMI_CORE_AV_AVI_VERS                   HDMI_CORE_AV_REG(0x104)
+#define HDMI_CORE_AV_AVI_LEN                    HDMI_CORE_AV_REG(0x108)
+#define HDMI_CORE_AV_AVI_CHSUM                  HDMI_CORE_AV_REG(0x10C)
+#define HDMI_CORE_AV_SPD_TYPE                   HDMI_CORE_AV_REG(0x180)
+#define HDMI_CORE_AV_SPD_VERS                   HDMI_CORE_AV_REG(0x184)
+#define HDMI_CORE_AV_SPD_LEN                    HDMI_CORE_AV_REG(0x188)
+#define HDMI_CORE_AV_SPD_CHSUM                  HDMI_CORE_AV_REG(0x18C)
+#define HDMI_CORE_AV_MPEG_TYPE                  HDMI_CORE_AV_REG(0x280)
+#define HDMI_CORE_AV_MPEG_VERS                  HDMI_CORE_AV_REG(0x284)
+#define HDMI_CORE_AV_MPEG_LEN                   HDMI_CORE_AV_REG(0x288)
+#define HDMI_CORE_AV_MPEG_CHSUM         HDMI_CORE_AV_REG(0x28C)
+#define HDMI_CORE_AV_CP_BYTE1                   HDMI_CORE_AV_REG(0x37C)
+#define HDMI_CORE_AV_CEC_ADDR_ID                HDMI_CORE_AV_REG(0x3FC)
+#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE           0x4
+#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE          0x4
+#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE          0x4
+#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE           0x4
+
+/* PLL */
+#define HDMI_PLL_REG(idx)                       HDMI_REG(HDMI_PLLCTRL + idx)
+
+#define PLLCTRL_PLL_CONTROL                     HDMI_PLL_REG(0x0)
+#define PLLCTRL_PLL_STATUS                      HDMI_PLL_REG(0x4)
+#define PLLCTRL_PLL_GO                          HDMI_PLL_REG(0x8)
+#define PLLCTRL_CFG1                            HDMI_PLL_REG(0xC)
+#define PLLCTRL_CFG2                            HDMI_PLL_REG(0x10)
+#define PLLCTRL_CFG3                            HDMI_PLL_REG(0x14)
+#define PLLCTRL_CFG4                            HDMI_PLL_REG(0x20)
+
+/* HDMI PHY */
+#define HDMI_PHY_REG(idx)                       HDMI_REG(HDMI_PHY + idx)
+
+#define HDMI_TXPHY_TX_CTRL                      HDMI_PHY_REG(0x0)
+#define HDMI_TXPHY_DIGITAL_CTRL         HDMI_PHY_REG(0x4)
+#define HDMI_TXPHY_POWER_CTRL                   HDMI_PHY_REG(0x8)
+#define HDMI_TXPHY_PAD_CFG_CTRL         HDMI_PHY_REG(0xC)
+
+/* HDMI EDID Length  */
+#define HDMI_EDID_MAX_LENGTH                    256
+#define EDID_TIMING_DESCRIPTOR_SIZE             0x12
+#define EDID_DESCRIPTOR_BLOCK0_ADDRESS          0x36
+#define EDID_DESCRIPTOR_BLOCK1_ADDRESS          0x80
+#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR      4
+#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR      4
+
+#define OMAP_HDMI_TIMINGS_NB                    34
+
+#define REG_FLD_MOD(idx, val, start, end) \
+        hdmi_write_reg(idx, FLD_MOD(hdmi_read_reg(idx), val, start, end))
+#define REG_GET(idx, start, end) \
+        FLD_GET(hdmi_read_reg(idx), start, end)
+
+/* HDMI timing structure */
+struct hdmi_timings {
+        struct omap_video_timings timings;
+        int vsync_pol;
+        int hsync_pol;
+};
+
+enum hdmi_phy_pwr {
+        HDMI_PHYPWRCMD_OFF = 0,
+        HDMI_PHYPWRCMD_LDOON = 1,
+        HDMI_PHYPWRCMD_TXON = 2
+};
+
+enum hdmi_pll_pwr {
+        HDMI_PLLPWRCMD_ALLOFF = 0,
+        HDMI_PLLPWRCMD_PLLONLY = 1,
+        HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
+        HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
+};
+
+enum hdmi_clk_refsel {
+        HDMI_REFSEL_PCLK = 0,
+        HDMI_REFSEL_REF1 = 1,
+        HDMI_REFSEL_REF2 = 2,
+        HDMI_REFSEL_SYSCLK = 3
+};
+
+enum hdmi_core_inputbus_width {
+        HDMI_INPUT_8BIT = 0,
+        HDMI_INPUT_10BIT = 1,
+        HDMI_INPUT_12BIT = 2
+};
+
+enum hdmi_core_dither_trunc {
+        HDMI_OUTPUTTRUNCATION_8BIT = 0,
+        HDMI_OUTPUTTRUNCATION_10BIT = 1,
+        HDMI_OUTPUTTRUNCATION_12BIT = 2,
+        HDMI_OUTPUTDITHER_8BIT = 3,
+        HDMI_OUTPUTDITHER_10BIT = 4,
+        HDMI_OUTPUTDITHER_12BIT = 5
+};
+
+enum hdmi_core_deepcolor_ed {
+        HDMI_DEEPCOLORPACKECTDISABLE = 0,
+        HDMI_DEEPCOLORPACKECTENABLE = 1
+};
+
+enum hdmi_core_packet_mode {
+        HDMI_PACKETMODERESERVEDVALUE = 0,
+        HDMI_PACKETMODE24BITPERPIXEL = 4,
+        HDMI_PACKETMODE30BITPERPIXEL = 5,
+        HDMI_PACKETMODE36BITPERPIXEL = 6,
+        HDMI_PACKETMODE48BITPERPIXEL = 7
+};
+
+enum hdmi_core_hdmi_dvi {
+        HDMI_DVI = 0,
+        HDMI_HDMI = 1
+};
+
+enum hdmi_core_tclkselclkmult {
+        HDMI_FPLL05IDCK = 0,
+        HDMI_FPLL10IDCK = 1,
+        HDMI_FPLL20IDCK = 2,
+        HDMI_FPLL40IDCK = 3
+};
+
+enum hdmi_core_packet_ctrl {
+        HDMI_PACKETENABLE = 1,
+        HDMI_PACKETDISABLE = 0,
+        HDMI_PACKETREPEATON = 1,
+        HDMI_PACKETREPEATOFF = 0
+};
+
+/* INFOFRAME_AVI_ definitions */
+enum hdmi_core_infoframe {
+        HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
+        HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
+        HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
+        HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
+        HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON =  1,
+        HDMI_INFOFRAME_AVI_DB1B_NO = 0,
+        HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
+        HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
+        HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
+        HDMI_INFOFRAME_AVI_DB1S_0 = 0,
+        HDMI_INFOFRAME_AVI_DB1S_1 = 1,
+        HDMI_INFOFRAME_AVI_DB1S_2 = 2,
+        HDMI_INFOFRAME_AVI_DB2C_NO = 0,
+        HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
+        HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
+        HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
+        HDMI_INFOFRAME_AVI_DB2M_NO = 0,
+        HDMI_INFOFRAME_AVI_DB2M_43 = 1,
+        HDMI_INFOFRAME_AVI_DB2M_169 = 2,
+        HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
+        HDMI_INFOFRAME_AVI_DB2R_43 = 9,
+        HDMI_INFOFRAME_AVI_DB2R_169 = 10,
+        HDMI_INFOFRAME_AVI_DB2R_149 = 11,
+        HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
+        HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
+        HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
+        HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
+        HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
+        HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
+        HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
+        HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
+        HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
+        HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
+        HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
+        HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
+        HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
+        HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
+        HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
+        HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
+        HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
+        HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
+        HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
+        HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
+        HDMI_INFOFRAME_AVI_DB5PR_10 = 9
+};
+
+enum hdmi_packing_mode {
+        HDMI_PACK_10b_RGB_YUV444 = 0,
+        HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
+        HDMI_PACK_20b_YUV422 = 2,
+        HDMI_PACK_ALREADYPACKED = 7
+};
+
+struct hdmi_core_video_config {
+        enum hdmi_core_inputbus_width   ip_bus_width;
+        enum hdmi_core_dither_trunc     op_dither_truc;
+        enum hdmi_core_deepcolor_ed     deep_color_pkt;
+        enum hdmi_core_packet_mode      pkt_mode;
+        enum hdmi_core_hdmi_dvi         hdmi_dvi;
+        enum hdmi_core_tclkselclkmult   tclk_sel_clkmult;
+};
+
+/*
+ * Refer to section 8.2 in HDMI 1.3 specification for
+ * details about infoframe databytes
+ */
+struct hdmi_core_infoframe_avi {
+        u8      db1_format;
+                /* Y0, Y1 rgb,yCbCr */
+        u8      db1_active_info;
+                /* A0  Active information Present */
+        u8      db1_bar_info_dv;
+                /* B0, B1 Bar info data valid */
+        u8      db1_scan_info;
+                /* S0, S1 scan information */
+        u8      db2_colorimetry;
+                /* C0, C1 colorimetry */
+        u8      db2_aspect_ratio;
+                /* M0, M1 Aspect ratio (4:3, 16:9) */
+        u8      db2_active_fmt_ar;
+                /* R0...R3 Active format aspect ratio */
+        u8      db3_itc;
+                /* ITC IT content. */
+        u8      db3_ec;
+                /* EC0, EC1, EC2 Extended colorimetry */
+        u8      db3_q_range;
+                /* Q1, Q0 Quantization range */
+        u8      db3_nup_scaling;
+                /* SC1, SC0 Non-uniform picture scaling */
+        u8      db4_videocode;
+                /* VIC0..6 Video format identification */
+        u8      db5_pixel_repeat;
+                /* PR0..PR3 Pixel repetition factor */
+        u16     db6_7_line_eoftop;
+                /* Line number end of top bar */
+        u16     db8_9_line_sofbottom;
+                /* Line number start of bottom bar */
+        u16     db10_11_pixel_eofleft;
+                /* Pixel number end of left bar */
+        u16     db12_13_pixel_sofright;
+                /* Pixel number start of right bar */
+};
+
+struct hdmi_core_packet_enable_repeat {
+        u32     audio_pkt;
+        u32     audio_pkt_repeat;
+        u32     avi_infoframe;
+        u32     avi_infoframe_repeat;
+        u32     gen_cntrl_pkt;
+        u32     gen_cntrl_pkt_repeat;
+        u32     generic_pkt;
+        u32     generic_pkt_repeat;
+};
+
+struct hdmi_video_format {
+        enum hdmi_packing_mode  packing_mode;
+        u32                     y_res;  /* Line per panel */
+        u32                     x_res;  /* pixel per line */
+};
+
+struct hdmi_video_interface {
+        int     vsp;    /* Vsync polarity */
+        int     hsp;    /* Hsync polarity */
+        int     interlacing;
+        int     tm;     /* Timing mode */
+};
+
+struct hdmi_cm {
+        int     code;
+        int     mode;
+};
+
+struct hdmi_config {
+        struct hdmi_timings timings;
+        u16     interlace;
+        struct hdmi_cm cm;
+};
+
+#endif
diff --git a/drivers/video/omap2/dss/hdmi_omap4_panel.c b/drivers/video/omap2/dss/hdmi_omap4_panel.c
new file mode 100644
index 000000000000..ffb5de94131f
--- /dev/null
+++ b/drivers/video/omap2/dss/hdmi_omap4_panel.c
@@ -0,0 +1,222 @@
+/*
+ * hdmi_omap4_panel.c
+ *
+ * HDMI library support functions for TI OMAP4 processors.
+ *
+ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Authors:     Mythri P k <mythripk@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/mutex.h>
+#include <linux/module.h>
+#include <plat/display.h>
+
+#include "dss.h"
+
+static struct {
+        struct mutex hdmi_lock;
+} hdmi;
+
+
+static int hdmi_panel_probe(struct omap_dss_device *dssdev)
+{
+        DSSDBG("ENTER hdmi_panel_probe\n");
+
+        dssdev->panel.config = OMAP_DSS_LCD_TFT |
+                        OMAP_DSS_LCD_IVS | OMAP_DSS_LCD_IHS;
+
+        /*
+         * Initialize the timings to 640 * 480
+         * This is only for framebuffer update not for TV timing setting
+         * Setting TV timing will be done only on enable
+         */
+        dssdev->panel.timings.x_res = 640;
+        dssdev->panel.timings.y_res = 480;
+
+        DSSDBG("hdmi_panel_probe x_res= %d y_res = %d\n",
+                dssdev->panel.timings.x_res,
+                dssdev->panel.timings.y_res);
+        return 0;
+}
+
+static void hdmi_panel_remove(struct omap_dss_device *dssdev)
+{
+
+}
+
+static int hdmi_panel_enable(struct omap_dss_device *dssdev)
+{
+        int r = 0;
+        DSSDBG("ENTER hdmi_panel_enable\n");
+
+        mutex_lock(&hdmi.hdmi_lock);
+
+        if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
+                r = -EINVAL;
+                goto err;
+        }
+
+        r = omapdss_hdmi_display_enable(dssdev);
+        if (r) {
+                DSSERR("failed to power on\n");
+                goto err;
+        }
+
+        dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+
+err:
+        mutex_unlock(&hdmi.hdmi_lock);
+
+        return r;
+}
+
+static void hdmi_panel_disable(struct omap_dss_device *dssdev)
+{
+        mutex_lock(&hdmi.hdmi_lock);
+
+        if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
+                omapdss_hdmi_display_disable(dssdev);
+
+        dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
+
+        mutex_unlock(&hdmi.hdmi_lock);
+}
+
+static int hdmi_panel_suspend(struct omap_dss_device *dssdev)
+{
+        int r = 0;
+
+        mutex_lock(&hdmi.hdmi_lock);
+
+        if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) {
+                r = -EINVAL;
+                goto err;
+        }
+
+        dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
+
+        omapdss_hdmi_display_disable(dssdev);
+
+err:
+        mutex_unlock(&hdmi.hdmi_lock);
+
+        return r;
+}
+
+static int hdmi_panel_resume(struct omap_dss_device *dssdev)
+{
+        int r = 0;
+
+        mutex_lock(&hdmi.hdmi_lock);
+
+        if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) {
+                r = -EINVAL;
+                goto err;
+        }
+
+        r = omapdss_hdmi_display_enable(dssdev);
+        if (r) {
+                DSSERR("failed to power on\n");
+                goto err;
+        }
+
+        dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+
+err:
+        mutex_unlock(&hdmi.hdmi_lock);
+
+        return r;
+}
+
+static void hdmi_get_timings(struct omap_dss_device *dssdev,
+                        struct omap_video_timings *timings)
+{
+        mutex_lock(&hdmi.hdmi_lock);
+
+        *timings = dssdev->panel.timings;
+
+        mutex_unlock(&hdmi.hdmi_lock);
+}
+
+static void hdmi_set_timings(struct omap_dss_device *dssdev,
+                        struct omap_video_timings *timings)
+{
+        DSSDBG("hdmi_set_timings\n");
+
+        mutex_lock(&hdmi.hdmi_lock);
+
+        dssdev->panel.timings = *timings;
+
+        if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
+                /* turn the hdmi off and on to get new timings to use */
+                omapdss_hdmi_display_disable(dssdev);
+                omapdss_hdmi_display_set_timing(dssdev);
+        }
+
+        mutex_unlock(&hdmi.hdmi_lock);
+}
+
+static int hdmi_check_timings(struct omap_dss_device *dssdev,
+                        struct omap_video_timings *timings)
+{
+        int r = 0;
+
+        DSSDBG("hdmi_check_timings\n");
+
+        mutex_lock(&hdmi.hdmi_lock);
+
+        r = omapdss_hdmi_display_check_timing(dssdev, timings);
+        if (r) {
+                DSSERR("Timing cannot be applied\n");
+                goto err;
+        }
+err:
+        mutex_unlock(&hdmi.hdmi_lock);
+        return r;
+}
+
+static struct omap_dss_driver hdmi_driver = {
+        .probe          = hdmi_panel_probe,
+        .remove         = hdmi_panel_remove,
+        .enable         = hdmi_panel_enable,
+        .disable        = hdmi_panel_disable,
+        .suspend        = hdmi_panel_suspend,
+        .resume         = hdmi_panel_resume,
+        .get_timings    = hdmi_get_timings,
+        .set_timings    = hdmi_set_timings,
+        .check_timings  = hdmi_check_timings,
+        .driver                 = {
+                .name   = "hdmi_panel",
+                .owner  = THIS_MODULE,
+        },
+};
+
+int hdmi_panel_init(void)
+{
+        mutex_init(&hdmi.hdmi_lock);
+
+        omap_dss_register_driver(&hdmi_driver);
+
+        return 0;
+}
+
+void hdmi_panel_exit(void)
+{
+        omap_dss_unregister_driver(&hdmi_driver);
+
+}
diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
index 172d4e697309..bcd37ec86952 100644
--- a/drivers/video/omap2/dss/manager.c
+++ b/drivers/video/omap2/dss/manager.c
@@ -515,6 +515,8 @@ static int dss_mgr_wait_for_vsync(struct omap_overlay_manager *mgr)
 
         if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC) {
                 irq = DISPC_IRQ_EVSYNC_ODD;
+        } else if (mgr->device->type == OMAP_DISPLAY_TYPE_HDMI) {
+                irq = DISPC_IRQ_EVSYNC_EVEN;
         } else {
                 if (mgr->id == OMAP_DSS_CHANNEL_LCD)
                         irq = DISPC_IRQ_VSYNC;
@@ -536,7 +538,8 @@ static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
         if (!dssdev || dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
                 return 0;
 
-        if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) {
+        if (dssdev->type == OMAP_DISPLAY_TYPE_VENC
+                        || dssdev->type == OMAP_DISPLAY_TYPE_HDMI) {
                 irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
         } else {
                 if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
@@ -613,7 +616,8 @@ int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
         if (!dssdev || dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
                 return 0;
 
-        if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) {
+        if (dssdev->type == OMAP_DISPLAY_TYPE_VENC
+                        || dssdev->type == OMAP_DISPLAY_TYPE_HDMI) {
                 irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
         } else {
                 if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
@@ -1377,6 +1381,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
                 case OMAP_DISPLAY_TYPE_DBI:
                 case OMAP_DISPLAY_TYPE_SDI:
                 case OMAP_DISPLAY_TYPE_VENC:
+                case OMAP_DISPLAY_TYPE_HDMI:
                         default_get_overlay_fifo_thresholds(ovl->id, size,
                                         &oc->burst_size, &oc->fifo_low,
                                         &oc->fifo_high);
@@ -1394,7 +1399,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
         }
 
         r = 0;
-        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
         if (!dss_cache.irq_enabled) {
                 u32 mask;
 
@@ -1407,7 +1412,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
                 dss_cache.irq_enabled = true;
         }
         configure_dispc();
-        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 
         spin_unlock_irqrestore(&dss_cache.lock, flags);
 
diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
index 456efef03c20..f1aca6d04011 100644
--- a/drivers/video/omap2/dss/overlay.c
+++ b/drivers/video/omap2/dss/overlay.c
@@ -490,7 +490,7 @@ static int omap_dss_set_manager(struct omap_overlay *ovl,
 
         ovl->manager = mgr;
 
-        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
         /* XXX: on manual update display, in auto update mode, a bug happens
          * here. When an overlay is first enabled on LCD, then it's disabled,
          * and the manager is changed to TV, we sometimes get SYNC_LOST_DIGIT
@@ -499,7 +499,7 @@ static int omap_dss_set_manager(struct omap_overlay *ovl,
          * but I don't understand how or why. */
         msleep(40);
         dispc_set_channel_out(ovl->id, mgr->id);
-        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 
         return 0;
 }
@@ -679,7 +679,8 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force)
                         lcd2_mgr->set_device(lcd2_mgr, dssdev);
                         mgr = lcd2_mgr;
                 }
-        } else if (dssdev->type != OMAP_DISPLAY_TYPE_VENC) {
+        } else if (dssdev->type != OMAP_DISPLAY_TYPE_VENC
+                        && dssdev->type != OMAP_DISPLAY_TYPE_HDMI) {
                 if (!lcd_mgr->device || force) {
                         if (lcd_mgr->device)
                                 lcd_mgr->unset_device(lcd_mgr);
@@ -688,7 +689,8 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force)
                 }
         }
 
-        if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) {
+        if (dssdev->type == OMAP_DISPLAY_TYPE_VENC
+                        || dssdev->type == OMAP_DISPLAY_TYPE_HDMI) {
                 if (!tv_mgr->device || force) {
                         if (tv_mgr->device)
                                 tv_mgr->unset_device(tv_mgr);
diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c
index 10a2ffe02882..5ea17f49c611 100644
--- a/drivers/video/omap2/dss/rfbi.c
+++ b/drivers/video/omap2/dss/rfbi.c
@@ -36,8 +36,6 @@
 #include <plat/display.h>
 #include "dss.h"
 
-#define RFBI_BASE               0x48050800
-
 struct rfbi_reg { u16 idx; };
 
 #define RFBI_REG(idx)           ((const struct rfbi_reg) { idx })
@@ -100,6 +98,7 @@ static int rfbi_convert_timings(struct rfbi_timings *t);
 static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div);
 
 static struct {
+        struct platform_device *pdev;
         void __iomem    *base;
 
         unsigned long   l4_khz;
@@ -142,9 +141,9 @@ static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
 static void rfbi_enable_clocks(bool enable)
 {
         if (enable)
-                dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+                dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
         else
-                dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+                dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 }
 
 void omap_rfbi_write_command(const void *buf, u32 len)
@@ -497,7 +496,7 @@ unsigned long rfbi_get_max_tx_rate(void)
         };
 
         l4_rate = rfbi.l4_khz / 1000;
-        dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000;
+        dss1_rate = dss_clk_get_rate(DSS_CLK_FCK) / 1000000;
 
         for (i = 0; i < ARRAY_SIZE(ftab); i++) {
                 /* Use a window instead of an exact match, to account
@@ -922,7 +921,7 @@ void rfbi_dump_regs(struct seq_file *s)
 {
 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r))
 
-        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 
         DUMPREG(RFBI_REVISION);
         DUMPREG(RFBI_SYSCONFIG);
@@ -953,54 +952,10 @@ void rfbi_dump_regs(struct seq_file *s)
         DUMPREG(RFBI_VSYNC_WIDTH);
         DUMPREG(RFBI_HSYNC_WIDTH);
 
-        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 #undef DUMPREG
 }
 
-int rfbi_init(void)
-{
-        u32 rev;
-        u32 l;
-
-        spin_lock_init(&rfbi.cmd_lock);
-
-        init_completion(&rfbi.cmd_done);
-        atomic_set(&rfbi.cmd_fifo_full, 0);
-        atomic_set(&rfbi.cmd_pending, 0);
-
-        rfbi.base = ioremap(RFBI_BASE, SZ_256);
-        if (!rfbi.base) {
-                DSSERR("can't ioremap RFBI\n");
-                return -ENOMEM;
-        }
-
-        rfbi_enable_clocks(1);
-
-        msleep(10);
-
-        rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000;
-
-        /* Enable autoidle and smart-idle */
-        l = rfbi_read_reg(RFBI_SYSCONFIG);
-        l |= (1 << 0) | (2 << 3);
-        rfbi_write_reg(RFBI_SYSCONFIG, l);
-
-        rev = rfbi_read_reg(RFBI_REVISION);
-        printk(KERN_INFO "OMAP RFBI rev %d.%d\n",
-               FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
-
-        rfbi_enable_clocks(0);
-
-        return 0;
-}
-
-void rfbi_exit(void)
-{
-        DSSDBG("rfbi_exit\n");
-
-        iounmap(rfbi.base);
-}
-
 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev)
 {
         int r;
@@ -1056,3 +1011,74 @@ int rfbi_init_display(struct omap_dss_device *dssdev)
         dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
         return 0;
 }
+
+/* RFBI HW IP initialisation */
+static int omap_rfbihw_probe(struct platform_device *pdev)
+{
+        u32 rev;
+        u32 l;
+        struct resource *rfbi_mem;
+
+        rfbi.pdev = pdev;
+
+        spin_lock_init(&rfbi.cmd_lock);
+
+        init_completion(&rfbi.cmd_done);
+        atomic_set(&rfbi.cmd_fifo_full, 0);
+        atomic_set(&rfbi.cmd_pending, 0);
+
+        rfbi_mem = platform_get_resource(rfbi.pdev, IORESOURCE_MEM, 0);
+        if (!rfbi_mem) {
+                DSSERR("can't get IORESOURCE_MEM RFBI\n");
+                return -EINVAL;
+        }
+        rfbi.base = ioremap(rfbi_mem->start, resource_size(rfbi_mem));
+        if (!rfbi.base) {
+                DSSERR("can't ioremap RFBI\n");
+                return -ENOMEM;
+        }
+
+        rfbi_enable_clocks(1);
+
+        msleep(10);
+
+        rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000;
+
+        /* Enable autoidle and smart-idle */
+        l = rfbi_read_reg(RFBI_SYSCONFIG);
+        l |= (1 << 0) | (2 << 3);
+        rfbi_write_reg(RFBI_SYSCONFIG, l);
+
+        rev = rfbi_read_reg(RFBI_REVISION);
+        dev_dbg(&pdev->dev, "OMAP RFBI rev %d.%d\n",
+               FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
+
+        rfbi_enable_clocks(0);
+
+        return 0;
+}
+
+static int omap_rfbihw_remove(struct platform_device *pdev)
+{
+        iounmap(rfbi.base);
+        return 0;
+}
+
+static struct platform_driver omap_rfbihw_driver = {
+        .probe          = omap_rfbihw_probe,
+        .remove         = omap_rfbihw_remove,
+        .driver         = {
+                .name   = "omapdss_rfbi",
+                .owner  = THIS_MODULE,
+        },
+};
+
+int rfbi_init_platform_driver(void)
+{
+        return platform_driver_register(&omap_rfbihw_driver);
+}
+
+void rfbi_uninit_platform_driver(void)
+{
+        return platform_driver_unregister(&omap_rfbihw_driver);
+}
diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
index b64adf7dfc88..54a53e648180 100644
--- a/drivers/video/omap2/dss/sdi.c
+++ b/drivers/video/omap2/dss/sdi.c
@@ -30,7 +30,6 @@
 #include "dss.h"
 
 static struct {
-        bool skip_init;
         bool update_enabled;
         struct regulator *vdds_sdi_reg;
 } sdi;
@@ -68,9 +67,7 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
         if (r)
                 goto err1;
 
-        /* In case of skip_init sdi_init has already enabled the clocks */
-        if (!sdi.skip_init)
-                dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 
         sdi_basic_init(dssdev);
 
@@ -80,14 +77,8 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
         dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
                         dssdev->panel.acbi, dssdev->panel.acb);
 
-        if (!sdi.skip_init) {
-                r = dss_calc_clock_div(1, t->pixel_clock * 1000,
-                                &dss_cinfo, &dispc_cinfo);
-        } else {
-                r = dss_get_clock_div(&dss_cinfo);
-                r = dispc_get_clock_div(dssdev->manager->id, &dispc_cinfo);
-        }
-
+        r = dss_calc_clock_div(1, t->pixel_clock * 1000,
+                        &dss_cinfo, &dispc_cinfo);
         if (r)
                 goto err2;
 
@@ -116,21 +107,17 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
         if (r)
                 goto err2;
 
-        if (!sdi.skip_init) {
-                dss_sdi_init(dssdev->phy.sdi.datapairs);
-                r = dss_sdi_enable();
-                if (r)
-                        goto err1;
-                mdelay(2);
-        }
+        dss_sdi_init(dssdev->phy.sdi.datapairs);
+        r = dss_sdi_enable();
+        if (r)
+                goto err1;
+        mdelay(2);
 
         dssdev->manager->enable(dssdev->manager);
 
-        sdi.skip_init = 0;
-
         return 0;
 err2:
-        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
         regulator_disable(sdi.vdds_sdi_reg);
 err1:
         omap_dss_stop_device(dssdev);
@@ -145,7 +132,7 @@ void omapdss_sdi_display_disable(struct omap_dss_device *dssdev)
 
         dss_sdi_disable();
 
-        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+        dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 
         regulator_disable(sdi.vdds_sdi_reg);
 
@@ -157,25 +144,24 @@ int sdi_init_display(struct omap_dss_device *dssdev)
 {
         DSSDBG("SDI init\n");
 
+        if (sdi.vdds_sdi_reg == NULL) {
+                struct regulator *vdds_sdi;
+
+                vdds_sdi = dss_get_vdds_sdi();
+
+                if (IS_ERR(vdds_sdi)) {
+                        DSSERR("can't get VDDS_SDI regulator\n");
+                        return PTR_ERR(vdds_sdi);
+                }
+
+                sdi.vdds_sdi_reg = vdds_sdi;
+        }
+
         return 0;
 }
 
-int sdi_init(bool skip_init)
+int sdi_init(void)
 {
-        /* we store this for first display enable, then clear it */
-        sdi.skip_init = skip_init;
-
-        sdi.vdds_sdi_reg = dss_get_vdds_sdi();
-        if (IS_ERR(sdi.vdds_sdi_reg)) {
-                DSSERR("can't get VDDS_SDI regulator\n");
-                return PTR_ERR(sdi.vdds_sdi_reg);
-        }
-        /*
-         * Enable clocks already here, otherwise there would be a toggle
-         * of them until sdi_display_enable is called.
-         */
-        if (skip_init)
-                dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
         return 0;
 }
 
diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
index eff35050e28a..8e35a5bae429 100644
--- a/drivers/video/omap2/dss/venc.c
+++ b/drivers/video/omap2/dss/venc.c
@@ -39,8 +39,6 @@
 
 #include "dss.h"
 
-#define VENC_BASE       0x48050C00
-
 /* Venc registers */
 #define VENC_REV_ID                             0x00
 #define VENC_STATUS                             0x04
@@ -289,6 +287,7 @@ const struct omap_video_timings omap_dss_ntsc_timings = {
 EXPORT_SYMBOL(omap_dss_ntsc_timings);
 
 static struct {
+        struct platform_device *pdev;
         void __iomem *base;
         struct mutex venc_lock;
         u32 wss_data;
@@ -381,11 +380,11 @@ static void venc_reset(void)
 static void venc_enable_clocks(int enable)
 {
         if (enable)
-                dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
-                                DSS_CLK_96M);
+                dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK |
+                                DSS_CLK_VIDFCK);
         else
-                dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
-                                DSS_CLK_96M);
+                dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK |
+                                DSS_CLK_VIDFCK);
 }
 
 static const struct venc_config *venc_timings_to_config(
@@ -641,50 +640,23 @@ static struct omap_dss_driver venc_driver = {
 };
 /* driver end */
 
-
-
-int venc_init(struct platform_device *pdev)
+int venc_init_display(struct omap_dss_device *dssdev)
 {
-        u8 rev_id;
+        DSSDBG("init_display\n");
 
-        mutex_init(&venc.venc_lock);
+        if (venc.vdda_dac_reg == NULL) {
+                struct regulator *vdda_dac;
 
-        venc.wss_data = 0;
+                vdda_dac = regulator_get(&venc.pdev->dev, "vdda_dac");
 
-        venc.base = ioremap(VENC_BASE, SZ_1K);
-        if (!venc.base) {
-                DSSERR("can't ioremap VENC\n");
-                return -ENOMEM;
-        }
+                if (IS_ERR(vdda_dac)) {
+                        DSSERR("can't get VDDA_DAC regulator\n");
+                        return PTR_ERR(vdda_dac);
+                }
 
-        venc.vdda_dac_reg = dss_get_vdda_dac();
-        if (IS_ERR(venc.vdda_dac_reg)) {
-                iounmap(venc.base);
-                DSSERR("can't get VDDA_DAC regulator\n");
-                return PTR_ERR(venc.vdda_dac_reg);
+                venc.vdda_dac_reg = vdda_dac;
         }
 
-        venc_enable_clocks(1);
-
-        rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
-        printk(KERN_INFO "OMAP VENC rev %d\n", rev_id);
-
-        venc_enable_clocks(0);
-
-        return omap_dss_register_driver(&venc_driver);
-}
-
-void venc_exit(void)
-{
-        omap_dss_unregister_driver(&venc_driver);
-
-        iounmap(venc.base);
-}
-
-int venc_init_display(struct omap_dss_device *dssdev)
-{
-        DSSDBG("init_display\n");
-
         return 0;
 }
 
@@ -740,3 +712,73 @@ void venc_dump_regs(struct seq_file *s)
 
 #undef DUMPREG
 }
+
+/* VENC HW IP initialisation */
+static int omap_venchw_probe(struct platform_device *pdev)
+{
+        u8 rev_id;
+        struct resource *venc_mem;
+
+        venc.pdev = pdev;
+
+        mutex_init(&venc.venc_lock);
+
+        venc.wss_data = 0;
+
+        venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
+        if (!venc_mem) {
+                DSSERR("can't get IORESOURCE_MEM VENC\n");
+                return -EINVAL;
+        }
+        venc.base = ioremap(venc_mem->start, resource_size(venc_mem));
+        if (!venc.base) {
+                DSSERR("can't ioremap VENC\n");
+                return -ENOMEM;
+        }
+
+        venc_enable_clocks(1);
+
+        rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
+        dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
+
+        venc_enable_clocks(0);
+
+        return omap_dss_register_driver(&venc_driver);
+}
+
+static int omap_venchw_remove(struct platform_device *pdev)
+{
+        if (venc.vdda_dac_reg != NULL) {
+                regulator_put(venc.vdda_dac_reg);
+                venc.vdda_dac_reg = NULL;
+        }
+        omap_dss_unregister_driver(&venc_driver);
+
+        iounmap(venc.base);
+        return 0;
+}
+
+static struct platform_driver omap_venchw_driver = {
+        .probe          = omap_venchw_probe,
+        .remove         = omap_venchw_remove,
+        .driver         = {
+                .name   = "omapdss_venc",
+                .owner  = THIS_MODULE,
+        },
+};
+
+int venc_init_platform_driver(void)
+{
+        if (cpu_is_omap44xx())
+                return 0;
+
+        return platform_driver_register(&omap_venchw_driver);
+}
+
+void venc_uninit_platform_driver(void)
+{
+        if (cpu_is_omap44xx())
+                return;
+
+        return platform_driver_unregister(&omap_venchw_driver);
+}
diff --git a/drivers/video/omap2/omapfb/Kconfig b/drivers/video/omap2/omapfb/Kconfig
index 65149b22cf37..aa33386c81ff 100644
--- a/drivers/video/omap2/omapfb/Kconfig
+++ b/drivers/video/omap2/omapfb/Kconfig
@@ -1,5 +1,5 @@
 menuconfig FB_OMAP2
-        tristate "OMAP2/3 frame buffer support (EXPERIMENTAL)"
+        tristate "OMAP2+ frame buffer support (EXPERIMENTAL)"
         depends on FB && OMAP2_DSS
 
         select OMAP2_VRAM
@@ -8,10 +8,10 @@ menuconfig FB_OMAP2
         select FB_CFB_COPYAREA
         select FB_CFB_IMAGEBLIT
         help
-          Frame buffer driver for OMAP2/3 based boards.
+          Frame buffer driver for OMAP2+ based boards.
 
 config FB_OMAP2_DEBUG_SUPPORT
-        bool "Debug support for OMAP2/3 FB"
+        bool "Debug support for OMAP2+ FB"
         default y
         depends on FB_OMAP2
         help
diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
index 4fdab8e9c496..505ec6672049 100644
--- a/drivers/video/omap2/omapfb/omapfb-main.c
+++ b/drivers/video/omap2/omapfb/omapfb-main.c
@@ -2090,7 +2090,7 @@ static int omapfb_set_def_mode(struct omapfb2_device *fbdev,
 {
         int r;
         u8 bpp;
-        struct omap_video_timings timings;
+        struct omap_video_timings timings, temp_timings;
 
         r = omapfb_mode_to_timings(mode_str, &timings, &bpp);
         if (r)
@@ -2100,14 +2100,23 @@ static int omapfb_set_def_mode(struct omapfb2_device *fbdev,
         fbdev->bpp_overrides[fbdev->num_bpp_overrides].bpp = bpp;
         ++fbdev->num_bpp_overrides;
 
-        if (!display->driver->check_timings || !display->driver->set_timings)
-                return -EINVAL;
+        if (display->driver->check_timings) {
+                r = display->driver->check_timings(display, &timings);
+                if (r)
+                        return r;
+        } else {
+                /* If check_timings is not present compare xres and yres */
+                if (display->driver->get_timings) {
+                        display->driver->get_timings(display, &temp_timings);
 
-        r = display->driver->check_timings(display, &timings);
-        if (r)
-                return r;
+                        if (temp_timings.x_res != timings.x_res ||
+                                temp_timings.y_res != timings.y_res)
+                                return -EINVAL;
+                }
+        }
 
-        display->driver->set_timings(display, &timings);
+        if (display->driver->set_timings)
+                        display->driver->set_timings(display, &timings);
 
         return 0;
 }
diff --git a/drivers/video/p9100.c b/drivers/video/p9100.c
index b6c3fc2db632..d57cc58c5168 100644
--- a/drivers/video/p9100.c
+++ b/drivers/video/p9100.c
@@ -249,7 +249,7 @@ static void p9100_init_fix(struct fb_info *info, int linebytes, struct device_no
         info->fix.accel = FB_ACCEL_SUN_CGTHREE;
 }
 
-static int __devinit p9100_probe(struct platform_device *op, const struct of_device_id *match)
+static int __devinit p9100_probe(struct platform_device *op)
 {
         struct device_node *dp = op->dev.of_node;
         struct fb_info *info;
@@ -352,7 +352,7 @@ static const struct of_device_id p9100_match[] = {
 };
 MODULE_DEVICE_TABLE(of, p9100_match);
 
-static struct of_platform_driver p9100_driver = {
+static struct platform_driver p9100_driver = {
         .driver = {
                 .name = "p9100",
                 .owner = THIS_MODULE,
@@ -367,12 +367,12 @@ static int __init p9100_init(void)
         if (fb_get_options("p9100fb", NULL))
                 return -ENODEV;
 
-        return of_register_platform_driver(&p9100_driver);
+        return platform_driver_register(&p9100_driver);
 }
 
 static void __exit p9100_exit(void)
 {
-        of_unregister_platform_driver(&p9100_driver);
+        platform_driver_unregister(&p9100_driver);
 }
 
 module_init(p9100_init);
diff --git a/drivers/video/platinumfb.c b/drivers/video/platinumfb.c
index a50e1977b316..ef532d9d3c99 100644
--- a/drivers/video/platinumfb.c
+++ b/drivers/video/platinumfb.c
@@ -533,8 +533,7 @@ static int __init platinumfb_setup(char *options)
 #define invalidate_cache(addr)
 #endif
 
-static int __devinit platinumfb_probe(struct platform_device* odev,
-                                      const struct of_device_id *match)
+static int __devinit platinumfb_probe(struct platform_device* odev)
 {
         struct device_node      *dp = odev->dev.of_node;
         struct fb_info          *info;
@@ -677,7 +676,7 @@ static struct of_device_id platinumfb_match[] =
         {},
 };
 
-static struct of_platform_driver platinum_driver = 
+static struct platform_driver platinum_driver = 
 {
         .driver = {
                 .name = "platinumfb",
@@ -697,14 +696,14 @@ static int __init platinumfb_init(void)
                 return -ENODEV;
         platinumfb_setup(option);
 #endif
-        of_register_platform_driver(&platinum_driver);
+        platform_driver_register(&platinum_driver);
 
         return 0;
 }
 
 static void __exit platinumfb_exit(void)
 {
-        of_unregister_platform_driver(&platinum_driver);
+        platform_driver_unregister(&platinum_driver);
 }
 
 MODULE_LICENSE("GPL");
diff --git a/drivers/video/riva/fbdev.c b/drivers/video/riva/fbdev.c
index da388186d617..d8ab7be4fd6b 100644
--- a/drivers/video/riva/fbdev.c
+++ b/drivers/video/riva/fbdev.c
@@ -355,6 +355,7 @@ static void riva_bl_init(struct riva_par *par)
         snprintf(name, sizeof(name), "rivabl%d", info->node);
 
         memset(&props, 0, sizeof(struct backlight_properties));
+        props.type = BACKLIGHT_RAW;
         props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
         bd = backlight_device_register(name, info->dev, par, &riva_bl_ops,
                                        &props);
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 83ce9a04d872..6817d187d46e 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -1340,6 +1340,7 @@ static int __devinit s3c_fb_probe(struct platform_device *pdev)
         sfb->bus_clk = clk_get(dev, "lcd");
         if (IS_ERR(sfb->bus_clk)) {
                 dev_err(dev, "failed to get bus clock\n");
+                ret = PTR_ERR(sfb->bus_clk);
                 goto err_sfb;
         }
 
diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c
index 75738a928610..ddedad9cd069 100644
--- a/drivers/video/s3fb.c
+++ b/drivers/video/s3fb.c
@@ -64,6 +64,8 @@ static const struct svga_fb_format s3fb_formats[] = {
 
 static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
         35000, 240000, 14318};
+static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4,
+        230000, 460000, 14318};
 
 static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
 
@@ -72,7 +74,8 @@ static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64",
                         "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge",
                         "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
                         "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P",
-                        "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X"};
+                        "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X",
+                        "S3 Trio3D"};
 
 #define CHIP_UNKNOWN            0x00
 #define CHIP_732_TRIO32         0x01
@@ -93,6 +96,7 @@ static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64",
 #define CHIP_360_TRIO3D_1X      0x10
 #define CHIP_362_TRIO3D_2X      0x11
 #define CHIP_368_TRIO3D_2X      0x12
+#define CHIP_365_TRIO3D         0x13
 
 #define CHIP_XXX_TRIO           0x80
 #define CHIP_XXX_TRIO64V2_DXGX  0x81
@@ -119,9 +123,11 @@ static const struct vga_regset s3_v_sync_start_regs[]   = {{0x10, 0, 7}, {0x07,
 static const struct vga_regset s3_v_sync_end_regs[]     = {{0x11, 0, 3}, VGA_REGSET_END};
 
 static const struct vga_regset s3_line_compare_regs[]   = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
-static const struct vga_regset s3_start_address_regs[]  = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END};
+static const struct vga_regset s3_start_address_regs[]  = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x69, 0, 4}, VGA_REGSET_END};
 static const struct vga_regset s3_offset_regs[]         = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
 
+static const struct vga_regset s3_dtpc_regs[]           = {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END};
+
 static const struct svga_timing_regs s3_timing_regs     = {
         s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
         s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
@@ -188,12 +194,19 @@ static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
         }
 }
 
+static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
+{
+        struct s3fb_info *par = info->par;
+
+        svga_tilecursor(par->state.vgabase, info, cursor);
+}
+
 static struct fb_tile_ops s3fb_tile_ops = {
         .fb_settile     = svga_settile,
         .fb_tilecopy    = svga_tilecopy,
         .fb_tilefill    = svga_tilefill,
         .fb_tileblit    = svga_tileblit,
-        .fb_tilecursor  = svga_tilecursor,
+        .fb_tilecursor  = s3fb_tilecursor,
         .fb_get_tilemax = svga_get_tilemax,
 };
 
@@ -202,7 +215,7 @@ static struct fb_tile_ops s3fb_fast_tile_ops = {
         .fb_tilecopy    = svga_tilecopy,
         .fb_tilefill    = svga_tilefill,
         .fb_tileblit    = svga_tileblit,
-        .fb_tilecursor  = svga_tilecursor,
+        .fb_tilecursor  = s3fb_tilecursor,
         .fb_get_tilemax = svga_get_tilemax,
 };
 
@@ -334,33 +347,34 @@ static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
         u8 regval;
         int rv;
 
-        rv = svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node);
+        rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll,
+                              1000000000 / pixclock, &m, &n, &r, info->node);
         if (rv < 0) {
                 printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node);
                 return;
         }
 
         /* Set VGA misc register  */
-        regval = vga_r(NULL, VGA_MIS_R);
-        vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
+        regval = vga_r(par->state.vgabase, VGA_MIS_R);
+        vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
 
         /* Set S3 clock registers */
         if (par->chip == CHIP_360_TRIO3D_1X ||
             par->chip == CHIP_362_TRIO3D_2X ||
             par->chip == CHIP_368_TRIO3D_2X) {
-                vga_wseq(NULL, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */
-                vga_wseq(NULL, 0x29, r >> 2); /* remaining highest bit of r */
+                vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6));   /* n and two bits of r */
+                vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */
         } else
-                vga_wseq(NULL, 0x12, (n - 2) | (r << 5));
-        vga_wseq(NULL, 0x13, m - 2);
+                vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5));
+        vga_wseq(par->state.vgabase, 0x13, m - 2);
 
         udelay(1000);
 
         /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
-        regval = vga_rseq (NULL, 0x15); /* | 0x80; */
-        vga_wseq(NULL, 0x15, regval & ~(1<<5));
-        vga_wseq(NULL, 0x15, regval |  (1<<5));
-        vga_wseq(NULL, 0x15, regval & ~(1<<5));
+        regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */
+        vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
+        vga_wseq(par->state.vgabase, 0x15, regval |  (1<<5));
+        vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
 }
 
 
@@ -372,7 +386,10 @@ static int s3fb_open(struct fb_info *info, int user)
 
         mutex_lock(&(par->open_lock));
         if (par->ref_count == 0) {
+                void __iomem *vgabase = par->state.vgabase;
+
                 memset(&(par->state), 0, sizeof(struct vgastate));
+                par->state.vgabase = vgabase;
                 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
                 par->state.num_crtc = 0x70;
                 par->state.num_seq = 0x20;
@@ -470,6 +487,7 @@ static int s3fb_set_par(struct fb_info *info)
         struct s3fb_info *par = info->par;
         u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes;
         u32 bpp = info->var.bits_per_pixel;
+        u32 htotal, hsstart;
 
         if (bpp != 0) {
                 info->fix.ypanstep = 1;
@@ -504,99 +522,112 @@ static int s3fb_set_par(struct fb_info *info)
         info->var.activate = FB_ACTIVATE_NOW;
 
         /* Unlock registers */
-        vga_wcrt(NULL, 0x38, 0x48);
-        vga_wcrt(NULL, 0x39, 0xA5);
-        vga_wseq(NULL, 0x08, 0x06);
-        svga_wcrt_mask(0x11, 0x00, 0x80);
+        vga_wcrt(par->state.vgabase, 0x38, 0x48);
+        vga_wcrt(par->state.vgabase, 0x39, 0xA5);
+        vga_wseq(par->state.vgabase, 0x08, 0x06);
+        svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
 
         /* Blank screen and turn off sync */
-        svga_wseq_mask(0x01, 0x20, 0x20);
-        svga_wcrt_mask(0x17, 0x00, 0x80);
+        svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
+        svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
 
         /* Set default values */
-        svga_set_default_gfx_regs();
-        svga_set_default_atc_regs();
-        svga_set_default_seq_regs();
-        svga_set_default_crt_regs();
-        svga_wcrt_multi(s3_line_compare_regs, 0xFFFFFFFF);
-        svga_wcrt_multi(s3_start_address_regs, 0);
+        svga_set_default_gfx_regs(par->state.vgabase);
+        svga_set_default_atc_regs(par->state.vgabase);
+        svga_set_default_seq_regs(par->state.vgabase);
+        svga_set_default_crt_regs(par->state.vgabase);
+        svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF);
+        svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0);
 
         /* S3 specific initialization */
-        svga_wcrt_mask(0x58, 0x10, 0x10); /* enable linear framebuffer */
-        svga_wcrt_mask(0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
+        svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */
+        svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
 
-/*      svga_wcrt_mask(0x33, 0x08, 0x08); */ /* DDR ?   */
-/*      svga_wcrt_mask(0x43, 0x01, 0x01); */ /* DDR ?   */
-        svga_wcrt_mask(0x33, 0x00, 0x08); /* no DDR ?   */
-        svga_wcrt_mask(0x43, 0x00, 0x01); /* no DDR ?   */
+/*      svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ?       */
+/*      svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ?       */
+        svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ?       */
+        svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ?       */
 
-        svga_wcrt_mask(0x5D, 0x00, 0x28); /* Clear strange HSlen bits */
+        svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */
 
-/*      svga_wcrt_mask(0x58, 0x03, 0x03); */
+/*      svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */
 
-/*      svga_wcrt_mask(0x53, 0x12, 0x13); */ /* enable MMIO */
-/*      svga_wcrt_mask(0x40, 0x08, 0x08); */ /* enable write buffer */
+/*      svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */
+/*      svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */
 
 
         /* Set the offset register */
         pr_debug("fb%d: offset register       : %d\n", info->node, offset_value);
-        svga_wcrt_multi(s3_offset_regs, offset_value);
+        svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);
 
         if (par->chip != CHIP_360_TRIO3D_1X &&
             par->chip != CHIP_362_TRIO3D_2X &&
             par->chip != CHIP_368_TRIO3D_2X) {
-                vga_wcrt(NULL, 0x54, 0x18); /* M parameter */
-                vga_wcrt(NULL, 0x60, 0xff); /* N parameter */
-                vga_wcrt(NULL, 0x61, 0xff); /* L parameter */
-                vga_wcrt(NULL, 0x62, 0xff); /* L parameter */
+                vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */
+                vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */
+                vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */
+                vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */
         }
 
-        vga_wcrt(NULL, 0x3A, 0x35);
-        svga_wattr(0x33, 0x00);
+        vga_wcrt(par->state.vgabase, 0x3A, 0x35);
+        svga_wattr(par->state.vgabase, 0x33, 0x00);
 
         if (info->var.vmode & FB_VMODE_DOUBLE)
-                svga_wcrt_mask(0x09, 0x80, 0x80);
+                svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
         else
-                svga_wcrt_mask(0x09, 0x00, 0x80);
+                svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
 
         if (info->var.vmode & FB_VMODE_INTERLACED)
-                svga_wcrt_mask(0x42, 0x20, 0x20);
+                svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20);
         else
-                svga_wcrt_mask(0x42, 0x00, 0x20);
+                svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20);
 
         /* Disable hardware graphics cursor */
-        svga_wcrt_mask(0x45, 0x00, 0x01);
+        svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01);
         /* Disable Streams engine */
-        svga_wcrt_mask(0x67, 0x00, 0x0C);
+        svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C);
 
         mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
 
         /* S3 virge DX hack */
         if (par->chip == CHIP_375_VIRGE_DX) {
-                vga_wcrt(NULL, 0x86, 0x80);
-                vga_wcrt(NULL, 0x90, 0x00);
+                vga_wcrt(par->state.vgabase, 0x86, 0x80);
+                vga_wcrt(par->state.vgabase, 0x90, 0x00);
         }
 
         /* S3 virge VX hack */
         if (par->chip == CHIP_988_VIRGE_VX) {
-                vga_wcrt(NULL, 0x50, 0x00);
-                vga_wcrt(NULL, 0x67, 0x50);
+                vga_wcrt(par->state.vgabase, 0x50, 0x00);
+                vga_wcrt(par->state.vgabase, 0x67, 0x50);
 
-                vga_wcrt(NULL, 0x63, (mode <= 2) ? 0x90 : 0x09);
-                vga_wcrt(NULL, 0x66, 0x90);
+                vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09);
+                vga_wcrt(par->state.vgabase, 0x66, 0x90);
         }
 
         if (par->chip == CHIP_360_TRIO3D_1X ||
             par->chip == CHIP_362_TRIO3D_2X ||
-            par->chip == CHIP_368_TRIO3D_2X) {
+            par->chip == CHIP_368_TRIO3D_2X ||
+            par->chip == CHIP_365_TRIO3D    ||
+            par->chip == CHIP_375_VIRGE_DX  ||
+            par->chip == CHIP_385_VIRGE_GX) {
                 dbytes = info->var.xres * ((bpp+7)/8);
-                vga_wcrt(NULL, 0x91, (dbytes + 7) / 8);
-                vga_wcrt(NULL, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);
+                vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8);
+                vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);
 
-                vga_wcrt(NULL, 0x66, 0x81);
+                vga_wcrt(par->state.vgabase, 0x66, 0x81);
         }
 
-        svga_wcrt_mask(0x31, 0x00, 0x40);
+        if (par->chip == CHIP_356_VIRGE_GX2  ||
+            par->chip == CHIP_357_VIRGE_GX2P ||
+            par->chip == CHIP_359_VIRGE_GX2P ||
+            par->chip == CHIP_360_TRIO3D_1X ||
+            par->chip == CHIP_362_TRIO3D_2X ||
+            par->chip == CHIP_368_TRIO3D_2X)
+                vga_wcrt(par->state.vgabase, 0x34, 0x00);
+        else    /* enable Data Transfer Position Control (DTPC) */
+                vga_wcrt(par->state.vgabase, 0x34, 0x10);
+
+        svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40);
         multiplex = 0;
         hmul = 1;
 
@@ -604,51 +635,51 @@ static int s3fb_set_par(struct fb_info *info)
         switch (mode) {
         case 0:
                 pr_debug("fb%d: text mode\n", info->node);
-                svga_set_textmode_vga_regs();
+                svga_set_textmode_vga_regs(par->state.vgabase);
 
                 /* Set additional registers like in 8-bit mode */
-                svga_wcrt_mask(0x50, 0x00, 0x30);
-                svga_wcrt_mask(0x67, 0x00, 0xF0);
+                svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
+                svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
 
                 /* Disable enhanced mode */
-                svga_wcrt_mask(0x3A, 0x00, 0x30);
+                svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
 
                 if (fasttext) {
                         pr_debug("fb%d: high speed text mode set\n", info->node);
-                        svga_wcrt_mask(0x31, 0x40, 0x40);
+                        svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40);
                 }
                 break;
         case 1:
                 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
-                vga_wgfx(NULL, VGA_GFX_MODE, 0x40);
+                vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
 
                 /* Set additional registers like in 8-bit mode */
-                svga_wcrt_mask(0x50, 0x00, 0x30);
-                svga_wcrt_mask(0x67, 0x00, 0xF0);
+                svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
+                svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
 
                 /* disable enhanced mode */
-                svga_wcrt_mask(0x3A, 0x00, 0x30);
+                svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
                 break;
         case 2:
                 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
 
                 /* Set additional registers like in 8-bit mode */
-                svga_wcrt_mask(0x50, 0x00, 0x30);
-                svga_wcrt_mask(0x67, 0x00, 0xF0);
+                svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
+                svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
 
                 /* disable enhanced mode */
-                svga_wcrt_mask(0x3A, 0x00, 0x30);
+                svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
                 break;
         case 3:
                 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
-                svga_wcrt_mask(0x50, 0x00, 0x30);
+                svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
                 if (info->var.pixclock > 20000 ||
                     par->chip == CHIP_360_TRIO3D_1X ||
                     par->chip == CHIP_362_TRIO3D_2X ||
                     par->chip == CHIP_368_TRIO3D_2X)
-                        svga_wcrt_mask(0x67, 0x00, 0xF0);
+                        svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
                 else {
-                        svga_wcrt_mask(0x67, 0x10, 0xF0);
+                        svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0);
                         multiplex = 1;
                 }
                 break;
@@ -656,12 +687,21 @@ static int s3fb_set_par(struct fb_info *info)
                 pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
                 if (par->chip == CHIP_988_VIRGE_VX) {
                         if (info->var.pixclock > 20000)
-                                svga_wcrt_mask(0x67, 0x20, 0xF0);
+                                svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
                         else
-                                svga_wcrt_mask(0x67, 0x30, 0xF0);
+                                svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
+                } else if (par->chip == CHIP_365_TRIO3D) {
+                        svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
+                        if (info->var.pixclock > 8695) {
+                                svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
+                                hmul = 2;
+                        } else {
+                                svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
+                                multiplex = 1;
+                        }
                 } else {
-                        svga_wcrt_mask(0x50, 0x10, 0x30);
-                        svga_wcrt_mask(0x67, 0x30, 0xF0);
+                        svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
+                        svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
                         if (par->chip != CHIP_360_TRIO3D_1X &&
                             par->chip != CHIP_362_TRIO3D_2X &&
                             par->chip != CHIP_368_TRIO3D_2X)
@@ -672,12 +712,21 @@ static int s3fb_set_par(struct fb_info *info)
                 pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
                 if (par->chip == CHIP_988_VIRGE_VX) {
                         if (info->var.pixclock > 20000)
-                                svga_wcrt_mask(0x67, 0x40, 0xF0);
+                                svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
                         else
-                                svga_wcrt_mask(0x67, 0x50, 0xF0);
+                                svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
+                } else if (par->chip == CHIP_365_TRIO3D) {
+                        svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
+                        if (info->var.pixclock > 8695) {
+                                svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
+                                hmul = 2;
+                        } else {
+                                svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
+                                multiplex = 1;
+                        }
                 } else {
-                        svga_wcrt_mask(0x50, 0x10, 0x30);
-                        svga_wcrt_mask(0x67, 0x50, 0xF0);
+                        svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
+                        svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
                         if (par->chip != CHIP_360_TRIO3D_1X &&
                             par->chip != CHIP_362_TRIO3D_2X &&
                             par->chip != CHIP_368_TRIO3D_2X)
@@ -687,12 +736,12 @@ static int s3fb_set_par(struct fb_info *info)
         case 6:
                 /* VIRGE VX case */
                 pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
-                svga_wcrt_mask(0x67, 0xD0, 0xF0);
+                svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
                 break;
         case 7:
                 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
-                svga_wcrt_mask(0x50, 0x30, 0x30);
-                svga_wcrt_mask(0x67, 0xD0, 0xF0);
+                svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30);
+                svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
                 break;
         default:
                 printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node);
@@ -700,25 +749,30 @@ static int s3fb_set_par(struct fb_info *info)
         }
 
         if (par->chip != CHIP_988_VIRGE_VX) {
-                svga_wseq_mask(0x15, multiplex ? 0x10 : 0x00, 0x10);
-                svga_wseq_mask(0x18, multiplex ? 0x80 : 0x00, 0x80);
+                svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);
+                svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);
         }
 
         s3_set_pixclock(info, info->var.pixclock);
-        svga_set_timings(&s3_timing_regs, &(info->var), hmul, 1,
+        svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1,
                          (info->var.vmode & FB_VMODE_DOUBLE)     ? 2 : 1,
                          (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
                          hmul, info->node);
 
         /* Set interlaced mode start/end register */
-        value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
-        value = ((value * hmul) / 8) - 5;
-        vga_wcrt(NULL, 0x3C, (value + 1) / 2);
+        htotal = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
+        htotal = ((htotal * hmul) / 8) - 5;
+        vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2);
+
+        /* Set Data Transfer Position */
+        hsstart = ((info->var.xres + info->var.right_margin) * hmul) / 8;
+        value = clamp((htotal + hsstart + 1) / 2, hsstart + 4, htotal + 1);
+        svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value);
 
         memset_io(info->screen_base, 0x00, screen_size);
         /* Device and screen back on */
-        svga_wcrt_mask(0x17, 0x80, 0x80);
-        svga_wseq_mask(0x01, 0x00, 0x20);
+        svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
+        svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
 
         return 0;
 }
@@ -788,31 +842,33 @@ static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 
 static int s3fb_blank(int blank_mode, struct fb_info *info)
 {
+        struct s3fb_info *par = info->par;
+
         switch (blank_mode) {
         case FB_BLANK_UNBLANK:
                 pr_debug("fb%d: unblank\n", info->node);
-                svga_wcrt_mask(0x56, 0x00, 0x06);
-                svga_wseq_mask(0x01, 0x00, 0x20);
+                svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
+                svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
                 break;
         case FB_BLANK_NORMAL:
                 pr_debug("fb%d: blank\n", info->node);
-                svga_wcrt_mask(0x56, 0x00, 0x06);
-                svga_wseq_mask(0x01, 0x20, 0x20);
+                svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
+                svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
                 break;
         case FB_BLANK_HSYNC_SUSPEND:
                 pr_debug("fb%d: hsync\n", info->node);
-                svga_wcrt_mask(0x56, 0x02, 0x06);
-                svga_wseq_mask(0x01, 0x20, 0x20);
+                svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06);
+                svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
                 break;
         case FB_BLANK_VSYNC_SUSPEND:
                 pr_debug("fb%d: vsync\n", info->node);
-                svga_wcrt_mask(0x56, 0x04, 0x06);
-                svga_wseq_mask(0x01, 0x20, 0x20);
+                svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06);
+                svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
                 break;
         case FB_BLANK_POWERDOWN:
                 pr_debug("fb%d: sync down\n", info->node);
-                svga_wcrt_mask(0x56, 0x06, 0x06);
-                svga_wseq_mask(0x01, 0x20, 0x20);
+                svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06);
+                svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
                 break;
         }
 
@@ -822,8 +878,9 @@ static int s3fb_blank(int blank_mode, struct fb_info *info)
 
 /* Pan the display */
 
-static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) {
-
+static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+        struct s3fb_info *par = info->par;
         unsigned int offset;
 
         /* Calculate the offset */
@@ -837,7 +894,7 @@ static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
         }
 
         /* Set the offset */
-        svga_wcrt_multi(s3_start_address_regs, offset);
+        svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset);
 
         return 0;
 }
@@ -863,12 +920,14 @@ static struct fb_ops s3fb_ops = {
 
 /* ------------------------------------------------------------------------- */
 
-static int __devinit s3_identification(int chip)
+static int __devinit s3_identification(struct s3fb_info *par)
 {
+        int chip = par->chip;
+
         if (chip == CHIP_XXX_TRIO) {
-                u8 cr30 = vga_rcrt(NULL, 0x30);
-                u8 cr2e = vga_rcrt(NULL, 0x2e);
-                u8 cr2f = vga_rcrt(NULL, 0x2f);
+                u8 cr30 = vga_rcrt(par->state.vgabase, 0x30);
+                u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e);
+                u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f);
 
                 if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
                         if (cr2e == 0x10)
@@ -883,7 +942,7 @@ static int __devinit s3_identification(int chip)
         }
 
         if (chip == CHIP_XXX_TRIO64V2_DXGX) {
-                u8 cr6f = vga_rcrt(NULL, 0x6f);
+                u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
 
                 if (! (cr6f & 0x01))
                         return CHIP_775_TRIO64V2_DX;
@@ -892,7 +951,7 @@ static int __devinit s3_identification(int chip)
         }
 
         if (chip == CHIP_XXX_VIRGE_DXGX) {
-                u8 cr6f = vga_rcrt(NULL, 0x6f);
+                u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
 
                 if (! (cr6f & 0x01))
                         return CHIP_375_VIRGE_DX;
@@ -901,7 +960,7 @@ static int __devinit s3_identification(int chip)
         }
 
         if (chip == CHIP_36X_TRIO3D_1X_2X) {
-                switch (vga_rcrt(NULL, 0x2f)) {
+                switch (vga_rcrt(par->state.vgabase, 0x2f)) {
                 case 0x00:
                         return CHIP_360_TRIO3D_1X;
                 case 0x01:
@@ -919,6 +978,8 @@ static int __devinit s3_identification(int chip)
 
 static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 {
+        struct pci_bus_region bus_reg;
+        struct resource vga_res;
         struct fb_info *info;
         struct s3fb_info *par;
         int rc;
@@ -968,31 +1029,42 @@ static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_i
                 goto err_iomap;
         }
 
+        bus_reg.start = 0;
+        bus_reg.end = 64 * 1024;
+
+        vga_res.flags = IORESOURCE_IO;
+
+        pcibios_bus_to_resource(dev, &vga_res, &bus_reg);
+
+        par->state.vgabase = (void __iomem *) vga_res.start;
+
         /* Unlock regs */
-        cr38 = vga_rcrt(NULL, 0x38);
-        cr39 = vga_rcrt(NULL, 0x39);
-        vga_wseq(NULL, 0x08, 0x06);
-        vga_wcrt(NULL, 0x38, 0x48);
-        vga_wcrt(NULL, 0x39, 0xA5);
+        cr38 = vga_rcrt(par->state.vgabase, 0x38);
+        cr39 = vga_rcrt(par->state.vgabase, 0x39);
+        vga_wseq(par->state.vgabase, 0x08, 0x06);
+        vga_wcrt(par->state.vgabase, 0x38, 0x48);
+        vga_wcrt(par->state.vgabase, 0x39, 0xA5);
 
         /* Identify chip type */
         par->chip = id->driver_data & CHIP_MASK;
-        par->rev = vga_rcrt(NULL, 0x2f);
+        par->rev = vga_rcrt(par->state.vgabase, 0x2f);
         if (par->chip & CHIP_UNDECIDED_FLAG)
-                par->chip = s3_identification(par->chip);
+                par->chip = s3_identification(par);
 
         /* Find how many physical memory there is on card */
         /* 0x36 register is accessible even if other registers are locked */
-        regval = vga_rcrt(NULL, 0x36);
+        regval = vga_rcrt(par->state.vgabase, 0x36);
         if (par->chip == CHIP_360_TRIO3D_1X ||
             par->chip == CHIP_362_TRIO3D_2X ||
-            par->chip == CHIP_368_TRIO3D_2X) {
+            par->chip == CHIP_368_TRIO3D_2X ||
+            par->chip == CHIP_365_TRIO3D) {
                 switch ((regval & 0xE0) >> 5) {
                 case 0: /* 8MB -- only 4MB usable for display */
                 case 1: /* 4MB with 32-bit bus */
                 case 2: /* 4MB */
                         info->screen_size = 4 << 20;
                         break;
+                case 4: /* 2MB on 365 Trio3D */
                 case 6: /* 2MB */
                         info->screen_size = 2 << 20;
                         break;
@@ -1002,13 +1074,13 @@ static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_i
         info->fix.smem_len = info->screen_size;
 
         /* Find MCLK frequency */
-        regval = vga_rseq(NULL, 0x10);
-        par->mclk_freq = ((vga_rseq(NULL, 0x11) + 2) * 14318) / ((regval & 0x1F)  + 2);
+        regval = vga_rseq(par->state.vgabase, 0x10);
+        par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F)  + 2);
         par->mclk_freq = par->mclk_freq >> (regval >> 5);
 
         /* Restore locks */
-        vga_wcrt(NULL, 0x38, cr38);
-        vga_wcrt(NULL, 0x39, cr39);
+        vga_wcrt(par->state.vgabase, 0x38, cr38);
+        vga_wcrt(par->state.vgabase, 0x39, cr39);
 
         strcpy(info->fix.id, s3_names [par->chip]);
         info->fix.mmio_start = 0;
@@ -1027,6 +1099,14 @@ static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_i
                 goto err_find_mode;
         }
 
+        /* maximize virtual vertical size for fast scrolling */
+        info->var.yres_virtual = info->fix.smem_len * 8 /
+                        (info->var.bits_per_pixel * info->var.xres_virtual);
+        if (info->var.yres_virtual < info->var.yres) {
+                dev_err(info->device, "virtual vertical size smaller than real\n");
+                goto err_find_mode;
+        }
+
         rc = fb_alloc_cmap(&info->cmap, 256, 0);
         if (rc < 0) {
                 dev_err(info->device, "cannot allocate colormap\n");
@@ -1044,8 +1124,8 @@ static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_i
 
         if (par->chip == CHIP_UNKNOWN)
                 printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
-                        info->node, vga_rcrt(NULL, 0x2d), vga_rcrt(NULL, 0x2e),
-                        vga_rcrt(NULL, 0x2f), vga_rcrt(NULL, 0x30));
+                        info->node, vga_rcrt(par->state.vgabase, 0x2d), vga_rcrt(par->state.vgabase, 0x2e),
+                        vga_rcrt(par->state.vgabase, 0x2f), vga_rcrt(par->state.vgabase, 0x30));
 
         /* Record a reference to the driver data */
         pci_set_drvdata(dev, info);
@@ -1192,6 +1272,7 @@ static struct pci_device_id s3_devices[] __devinitdata = {
         {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P},
         {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
         {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X},
+        {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D},
 
         {0, 0, 0, 0, 0, 0, 0}
 };
diff --git a/drivers/video/sh7760fb.c b/drivers/video/sh7760fb.c
index bea38fce2470..8fe19582c460 100644
--- a/drivers/video/sh7760fb.c
+++ b/drivers/video/sh7760fb.c
@@ -459,14 +459,14 @@ static int __devinit sh7760fb_probe(struct platform_device *pdev)
         }
 
         par->ioarea = request_mem_region(res->start,
-                                         (res->end - res->start), pdev->name);
+                                         resource_size(res), pdev->name);
         if (!par->ioarea) {
                 dev_err(&pdev->dev, "mmio area busy\n");
                 ret = -EBUSY;
                 goto out_fb;
         }
 
-        par->base = ioremap_nocache(res->start, res->end - res->start + 1);
+        par->base = ioremap_nocache(res->start, resource_size(res));
         if (!par->base) {
                 dev_err(&pdev->dev, "cannot remap\n");
                 ret = -ENODEV;
diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c
index bf12e53aed5c..757665bc500f 100644
--- a/drivers/video/sh_mobile_lcdcfb.c
+++ b/drivers/video/sh_mobile_lcdcfb.c
@@ -21,6 +21,8 @@
 #include <linux/ioctl.h>
 #include <linux/slab.h>
 #include <linux/console.h>
+#include <linux/backlight.h>
+#include <linux/gpio.h>
 #include <video/sh_mobile_lcdc.h>
 #include <asm/atomic.h>
 
@@ -67,6 +69,7 @@ static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
         [LDSM1R] = 0x428,
         [LDSM2R] = 0x42c,
         [LDSA1R] = 0x430,
+        [LDSA2R] = 0x434,
         [LDMLSR] = 0x438,
         [LDHCNR] = 0x448,
         [LDHSYNR] = 0x44c,
@@ -151,6 +154,7 @@ static bool banked(int reg_nr)
         case LDDFR:
         case LDSM1R:
         case LDSA1R:
+        case LDSA2R:
         case LDMLSR:
         case LDHCNR:
         case LDHSYNR:
@@ -463,6 +467,7 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
         struct sh_mobile_lcdc_board_cfg *board_cfg;
         unsigned long tmp;
         int bpp = 0;
+        unsigned long ldddsr;
         int k, m;
         int ret = 0;
 
@@ -541,16 +546,21 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
         }
 
         /* word and long word swap */
-        switch (bpp) {
-        case 16:
-                lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
-                break;
-        case 24:
-                lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 7);
-                break;
-        case 32:
-                lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 4);
-                break;
+        ldddsr = lcdc_read(priv, _LDDDSR);
+        if  (priv->ch[0].info->var.nonstd)
+                lcdc_write(priv, _LDDDSR, ldddsr | 7);
+        else {
+                switch (bpp) {
+                case 16:
+                        lcdc_write(priv, _LDDDSR, ldddsr | 6);
+                        break;
+                case 24:
+                        lcdc_write(priv, _LDDDSR, ldddsr | 7);
+                        break;
+                case 32:
+                        lcdc_write(priv, _LDDDSR, ldddsr | 4);
+                        break;
+                }
         }
 
         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
@@ -561,21 +571,40 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
 
                 /* set bpp format in PKF[4:0] */
                 tmp = lcdc_read_chan(ch, LDDFR);
-                tmp &= ~0x0001001f;
-                switch (ch->info->var.bits_per_pixel) {
-                case 16:
-                        tmp |= 0x03;
-                        break;
-                case 24:
-                        tmp |= 0x0b;
-                        break;
-                case 32:
-                        break;
+                tmp &= ~0x0003031f;
+                if (ch->info->var.nonstd) {
+                        tmp |= (ch->info->var.nonstd << 16);
+                        switch (ch->info->var.bits_per_pixel) {
+                        case 12:
+                                break;
+                        case 16:
+                                tmp |= (0x1 << 8);
+                                break;
+                        case 24:
+                                tmp |= (0x2 << 8);
+                                break;
+                        }
+                } else {
+                        switch (ch->info->var.bits_per_pixel) {
+                        case 16:
+                                tmp |= 0x03;
+                                break;
+                        case 24:
+                                tmp |= 0x0b;
+                                break;
+                        case 32:
+                                break;
+                        }
                 }
                 lcdc_write_chan(ch, LDDFR, tmp);
 
                 /* point out our frame buffer */
                 lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start);
+                if (ch->info->var.nonstd)
+                        lcdc_write_chan(ch, LDSA2R,
+                                ch->info->fix.smem_start +
+                                ch->info->var.xres *
+                                ch->info->var.yres_virtual);
 
                 /* set line size */
                 lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length);
@@ -618,6 +647,11 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
                         board_cfg->display_on(board_cfg->board_data, ch->info);
                         module_put(board_cfg->owner);
                 }
+
+                if (ch->bl) {
+                        ch->bl->props.power = FB_BLANK_UNBLANK;
+                        backlight_update_status(ch->bl);
+                }
         }
 
         return 0;
@@ -648,6 +682,11 @@ static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
                         sh_mobile_lcdc_clk_on(priv);
                 }
 
+                if (ch->bl) {
+                        ch->bl->props.power = FB_BLANK_POWERDOWN;
+                        backlight_update_status(ch->bl);
+                }
+
                 board_cfg = &ch->cfg.board_cfg;
                 if (try_module_get(board_cfg->owner) && board_cfg->display_off) {
                         board_cfg->display_off(board_cfg->board_data);
@@ -804,9 +843,15 @@ static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
         struct sh_mobile_lcdc_priv *priv = ch->lcdc;
         unsigned long ldrcntr;
         unsigned long new_pan_offset;
+        unsigned long base_addr_y, base_addr_c;
+        unsigned long c_offset;
 
-        new_pan_offset = (var->yoffset * info->fix.line_length) +
-                (var->xoffset * (info->var.bits_per_pixel / 8));
+        if (!var->nonstd)
+                new_pan_offset = (var->yoffset * info->fix.line_length) +
+                        (var->xoffset * (info->var.bits_per_pixel / 8));
+        else
+                new_pan_offset = (var->yoffset * info->fix.line_length) +
+                        (var->xoffset);
 
         if (new_pan_offset == ch->pan_offset)
                 return 0;       /* No change, do nothing */
@@ -814,7 +859,26 @@ static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
         ldrcntr = lcdc_read(priv, _LDRCNTR);
 
         /* Set the source address for the next refresh */
-        lcdc_write_chan_mirror(ch, LDSA1R, ch->dma_handle + new_pan_offset);
+        base_addr_y = ch->dma_handle + new_pan_offset;
+        if (var->nonstd) {
+                /* Set y offset */
+                c_offset = (var->yoffset *
+                        info->fix.line_length *
+                        (info->var.bits_per_pixel - 8)) / 8;
+                base_addr_c = ch->dma_handle + var->xres * var->yres_virtual +
+                        c_offset;
+                /* Set x offset */
+                if (info->var.bits_per_pixel == 24)
+                        base_addr_c += 2 * var->xoffset;
+                else
+                        base_addr_c += var->xoffset;
+        } else
+                base_addr_c = 0;
+
+        lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y);
+        if (base_addr_c)
+                lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c);
+
         if (lcdc_chan_is_sublcd(ch))
                 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
         else
@@ -885,7 +949,10 @@ static void sh_mobile_fb_reconfig(struct fb_info *info)
                 /* Couldn't reconfigure, hopefully, can continue as before */
                 return;
 
-        info->fix.line_length = mode1.xres * (ch->cfg.bpp / 8);
+        if (info->var.nonstd)
+                info->fix.line_length = mode1.xres;
+        else
+                info->fix.line_length = mode1.xres * (ch->cfg.bpp / 8);
 
         /*
          * fb_set_var() calls the notifier change internally, only if
@@ -980,8 +1047,81 @@ static struct fb_ops sh_mobile_lcdc_ops = {
         .fb_check_var   = sh_mobile_check_var,
 };
 
-static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
+static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev)
+{
+        struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
+        struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
+        int brightness = bdev->props.brightness;
+
+        if (bdev->props.power != FB_BLANK_UNBLANK ||
+            bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
+                brightness = 0;
+
+        return cfg->set_brightness(cfg->board_data, brightness);
+}
+
+static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev)
 {
+        struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
+        struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
+
+        return cfg->get_brightness(cfg->board_data);
+}
+
+static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev,
+                                   struct fb_info *info)
+{
+        return (info->bl_dev == bdev);
+}
+
+static struct backlight_ops sh_mobile_lcdc_bl_ops = {
+        .options        = BL_CORE_SUSPENDRESUME,
+        .update_status  = sh_mobile_lcdc_update_bl,
+        .get_brightness = sh_mobile_lcdc_get_brightness,
+        .check_fb       = sh_mobile_lcdc_check_fb,
+};
+
+static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent,
+                                               struct sh_mobile_lcdc_chan *ch)
+{
+        struct backlight_device *bl;
+
+        bl = backlight_device_register(ch->cfg.bl_info.name, parent, ch,
+                                       &sh_mobile_lcdc_bl_ops, NULL);
+        if (IS_ERR(bl)) {
+                dev_err(parent, "unable to register backlight device: %ld\n",
+                        PTR_ERR(bl));
+                return NULL;
+        }
+
+        bl->props.max_brightness = ch->cfg.bl_info.max_brightness;
+        bl->props.brightness = bl->props.max_brightness;
+        backlight_update_status(bl);
+
+        return bl;
+}
+
+static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev)
+{
+        backlight_device_unregister(bdev);
+}
+
+static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp,
+                                   int nonstd)
+{
+        if (nonstd) {
+                switch (bpp) {
+                case 12:
+                case 16:
+                case 24:
+                        var->bits_per_pixel = bpp;
+                        var->nonstd = nonstd;
+                        return 0;
+                default:
+                        return -EINVAL;
+                }
+        }
+
         switch (bpp) {
         case 16: /* PKF[4:0] = 00011 - RGB 565 */
                 var->red.offset = 11;
@@ -1198,6 +1338,10 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
                 init_completion(&ch->vsync_completion);
                 ch->pan_offset = 0;
 
+                /* probe the backlight is there is one defined */
+                if (ch->cfg.bl_info.max_brightness)
+                        ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch);
+
                 switch (pdata->ch[i].chan) {
                 case LCDC_CHAN_MAINLCD:
                         ch->enabled = 1 << 1;
@@ -1260,6 +1404,14 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
                      k < cfg->num_cfg && lcd_cfg;
                      k++, lcd_cfg++) {
                         unsigned long size = lcd_cfg->yres * lcd_cfg->xres;
+                        /* NV12 buffers must have even number of lines */
+                        if ((cfg->nonstd) && cfg->bpp == 12 &&
+                                        (lcd_cfg->yres & 0x1)) {
+                                dev_err(&pdev->dev, "yres must be multiple of 2"
+                                                " for YCbCr420 mode.\n");
+                                error = -EINVAL;
+                                goto err1;
+                        }
 
                         if (size > max_size) {
                                 max_cfg = lcd_cfg;
@@ -1274,7 +1426,11 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
                                 max_cfg->xres, max_cfg->yres);
 
                 info->fix = sh_mobile_lcdc_fix;
-                info->fix.smem_len = max_size * (cfg->bpp / 8) * 2;
+                info->fix.smem_len = max_size * 2 * cfg->bpp / 8;
+
+                 /* Only pan in 2 line steps for NV12 */
+                if (cfg->nonstd && cfg->bpp == 12)
+                        info->fix.ypanstep = 2;
 
                 if (!mode) {
                         mode = &default_720p;
@@ -1292,7 +1448,7 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
                 var->yres_virtual = var->yres * 2;
                 var->activate = FB_ACTIVATE_NOW;
 
-                error = sh_mobile_lcdc_set_bpp(var, cfg->bpp);
+                error = sh_mobile_lcdc_set_bpp(var, cfg->bpp, cfg->nonstd);
                 if (error)
                         break;
 
@@ -1316,7 +1472,11 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
                 }
 
                 info->fix.smem_start = ch->dma_handle;
-                info->fix.line_length = var->xres * (cfg->bpp / 8);
+                if (var->nonstd)
+                        info->fix.line_length = var->xres;
+                else
+                        info->fix.line_length = var->xres * (cfg->bpp / 8);
+
                 info->screen_base = buf;
                 info->device = &pdev->dev;
                 ch->display_var = *var;
@@ -1345,6 +1505,8 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
                         }
                 }
 
+                info->bl_dev = ch->bl;
+
                 error = register_framebuffer(info);
                 if (error < 0)
                         goto err1;
@@ -1404,6 +1566,11 @@ static int sh_mobile_lcdc_remove(struct platform_device *pdev)
                 framebuffer_release(info);
         }
 
+        for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
+                if (priv->ch[i].bl)
+                        sh_mobile_lcdc_bl_remove(priv->ch[i].bl);
+        }
+
         if (priv->dot_clk)
                 clk_put(priv->dot_clk);
 
diff --git a/drivers/video/sh_mobile_lcdcfb.h b/drivers/video/sh_mobile_lcdcfb.h
index 9ecee2fba1d7..4635eed63eee 100644
--- a/drivers/video/sh_mobile_lcdcfb.h
+++ b/drivers/video/sh_mobile_lcdcfb.h
@@ -8,7 +8,7 @@
 
 /* per-channel registers */
 enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
-       LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR,
+       LDSM2R, LDSA1R, LDSA2R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR,
        LDHAJR,
        NR_CH_REGS };
 
@@ -16,6 +16,7 @@ enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
 
 struct sh_mobile_lcdc_priv;
 struct fb_info;
+struct backlight_device;
 
 struct sh_mobile_lcdc_chan {
         struct sh_mobile_lcdc_priv *lcdc;
@@ -26,6 +27,7 @@ struct sh_mobile_lcdc_chan {
         u32 pseudo_palette[PALETTE_NR];
         unsigned long saved_ch_regs[NR_CH_REGS];
         struct fb_info *info;
+        struct backlight_device *bl;
         dma_addr_t dma_handle;
         struct fb_deferred_io defio;
         struct scatterlist *sglist;
diff --git a/drivers/video/sis/sis.h b/drivers/video/sis/sis.h
index eac7a01925f3..1987f1b7212f 100644
--- a/drivers/video/sis/sis.h
+++ b/drivers/video/sis/sis.h
@@ -495,6 +495,7 @@ struct sis_video_info {
         unsigned int    refresh_rate;
 
         unsigned int    chip;
+        unsigned int    chip_real_id;
         u8              revision_id;
         int             sisvga_enabled;         /* PCI device was enabled */
 
diff --git a/drivers/video/sis/sis_main.c b/drivers/video/sis/sis_main.c
index 2fb8c5a660fb..75259845933d 100644
--- a/drivers/video/sis/sis_main.c
+++ b/drivers/video/sis/sis_main.c
@@ -4563,6 +4563,11 @@ sisfb_post_sis315330(struct pci_dev *pdev)
 }
 #endif
 
+static inline int sisfb_xgi_is21(struct sis_video_info *ivideo)
+{
+        return ivideo->chip_real_id == XGI_21;
+}
+
 static void __devinit
 sisfb_post_xgi_delay(struct sis_video_info *ivideo, int delay)
 {
@@ -4627,11 +4632,11 @@ sisfb_post_xgi_rwtest(struct sis_video_info *ivideo, int starta,
         return 1;
 }
 
-static void __devinit
+static int __devinit
 sisfb_post_xgi_ramsize(struct sis_video_info *ivideo)
 {
         unsigned int buswidth, ranksize, channelab, mapsize;
-        int i, j, k, l;
+        int i, j, k, l, status;
         u8 reg, sr14;
         static const u8 dramsr13[12 * 5] = {
                 0x02, 0x0e, 0x0b, 0x80, 0x5d,
@@ -4673,7 +4678,7 @@ sisfb_post_xgi_ramsize(struct sis_video_info *ivideo)
                 SiS_SetReg(SISSR, 0x13, 0x35);
                 SiS_SetReg(SISSR, 0x14, 0x41);
                 /* TODO */
-                return;
+                return -ENOMEM;
         }
 
         /* Non-interleaving */
@@ -4835,6 +4840,7 @@ bail_out:
 
         j = (ivideo->chip == XGI_20) ? 5 : 9;
         k = (ivideo->chip == XGI_20) ? 12 : 4;
+        status = -EIO;
 
         for(i = 0; i < k; i++) {
 
@@ -4868,11 +4874,15 @@ bail_out:
                 SiS_SetRegANDOR(SISSR, 0x14, 0x0f, (reg & 0xf0));
                 sisfb_post_xgi_delay(ivideo, 1);
 
-                if(sisfb_post_xgi_rwtest(ivideo, j, ((reg >> 4) + channelab - 2 + 20), mapsize))
+                if (sisfb_post_xgi_rwtest(ivideo, j, ((reg >> 4) + channelab - 2 + 20), mapsize)) {
+                        status = 0;
                         break;
+                }
         }
 
         iounmap(ivideo->video_vbase);
+
+        return status;
 }
 
 static void __devinit
@@ -4931,6 +4941,175 @@ sisfb_post_xgi_setclocks(struct sis_video_info *ivideo, u8 regb)
         sisfb_post_xgi_delay(ivideo, 0x43);
 }
 
+static void __devinit
+sisfb_post_xgi_ddr2_mrs_default(struct sis_video_info *ivideo, u8 regb)
+{
+        unsigned char *bios = ivideo->bios_abase;
+        u8 v1;
+
+        SiS_SetReg(SISSR, 0x28, 0x64);
+        SiS_SetReg(SISSR, 0x29, 0x63);
+        sisfb_post_xgi_delay(ivideo, 15);
+        SiS_SetReg(SISSR, 0x18, 0x00);
+        SiS_SetReg(SISSR, 0x19, 0x20);
+        SiS_SetReg(SISSR, 0x16, 0x00);
+        SiS_SetReg(SISSR, 0x16, 0x80);
+        SiS_SetReg(SISSR, 0x18, 0xc5);
+        SiS_SetReg(SISSR, 0x19, 0x23);
+        SiS_SetReg(SISSR, 0x16, 0x00);
+        SiS_SetReg(SISSR, 0x16, 0x80);
+        sisfb_post_xgi_delay(ivideo, 1);
+        SiS_SetReg(SISCR, 0x97, 0x11);
+        sisfb_post_xgi_setclocks(ivideo, regb);
+        sisfb_post_xgi_delay(ivideo, 0x46);
+        SiS_SetReg(SISSR, 0x18, 0xc5);
+        SiS_SetReg(SISSR, 0x19, 0x23);
+        SiS_SetReg(SISSR, 0x16, 0x00);
+        SiS_SetReg(SISSR, 0x16, 0x80);
+        sisfb_post_xgi_delay(ivideo, 1);
+        SiS_SetReg(SISSR, 0x1b, 0x04);
+        sisfb_post_xgi_delay(ivideo, 1);
+        SiS_SetReg(SISSR, 0x1b, 0x00);
+        sisfb_post_xgi_delay(ivideo, 1);
+        v1 = 0x31;
+        if (ivideo->haveXGIROM) {
+                v1 = bios[0xf0];
+        }
+        SiS_SetReg(SISSR, 0x18, v1);
+        SiS_SetReg(SISSR, 0x19, 0x06);
+        SiS_SetReg(SISSR, 0x16, 0x04);
+        SiS_SetReg(SISSR, 0x16, 0x84);
+        sisfb_post_xgi_delay(ivideo, 1);
+}
+
+static void __devinit
+sisfb_post_xgi_ddr2_mrs_xg21(struct sis_video_info *ivideo)
+{
+        sisfb_post_xgi_setclocks(ivideo, 1);
+
+        SiS_SetReg(SISCR, 0x97, 0x11);
+        sisfb_post_xgi_delay(ivideo, 0x46);
+
+        SiS_SetReg(SISSR, 0x18, 0x00);  /* EMRS2 */
+        SiS_SetReg(SISSR, 0x19, 0x80);
+        SiS_SetReg(SISSR, 0x16, 0x05);
+        SiS_SetReg(SISSR, 0x16, 0x85);
+
+        SiS_SetReg(SISSR, 0x18, 0x00);  /* EMRS3 */
+        SiS_SetReg(SISSR, 0x19, 0xc0);
+        SiS_SetReg(SISSR, 0x16, 0x05);
+        SiS_SetReg(SISSR, 0x16, 0x85);
+
+        SiS_SetReg(SISSR, 0x18, 0x00);  /* EMRS1 */
+        SiS_SetReg(SISSR, 0x19, 0x40);
+        SiS_SetReg(SISSR, 0x16, 0x05);
+        SiS_SetReg(SISSR, 0x16, 0x85);
+
+        SiS_SetReg(SISSR, 0x18, 0x42);  /* MRS1 */
+        SiS_SetReg(SISSR, 0x19, 0x02);
+        SiS_SetReg(SISSR, 0x16, 0x05);
+        SiS_SetReg(SISSR, 0x16, 0x85);
+        sisfb_post_xgi_delay(ivideo, 1);
+
+        SiS_SetReg(SISSR, 0x1b, 0x04);
+        sisfb_post_xgi_delay(ivideo, 1);
+
+        SiS_SetReg(SISSR, 0x1b, 0x00);
+        sisfb_post_xgi_delay(ivideo, 1);
+
+        SiS_SetReg(SISSR, 0x18, 0x42);  /* MRS1 */
+        SiS_SetReg(SISSR, 0x19, 0x00);
+        SiS_SetReg(SISSR, 0x16, 0x05);
+        SiS_SetReg(SISSR, 0x16, 0x85);
+        sisfb_post_xgi_delay(ivideo, 1);
+}
+
+static void __devinit
+sisfb_post_xgi_ddr2(struct sis_video_info *ivideo, u8 regb)
+{
+        unsigned char *bios = ivideo->bios_abase;
+        static const u8 cs158[8] = {
+                0x88, 0xaa, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00
+        };
+        static const u8 cs160[8] = {
+                0x44, 0x77, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00
+        };
+        static const u8 cs168[8] = {
+                0x48, 0x78, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00
+        };
+        u8 reg;
+        u8 v1;
+        u8 v2;
+        u8 v3;
+
+        SiS_SetReg(SISCR, 0xb0, 0x80); /* DDR2 dual frequency mode */
+        SiS_SetReg(SISCR, 0x82, 0x77);
+        SiS_SetReg(SISCR, 0x86, 0x00);
+        reg = SiS_GetReg(SISCR, 0x86);
+        SiS_SetReg(SISCR, 0x86, 0x88);
+        reg = SiS_GetReg(SISCR, 0x86);
+        v1 = cs168[regb]; v2 = cs160[regb]; v3 = cs158[regb];
+        if (ivideo->haveXGIROM) {
+                v1 = bios[regb + 0x168];
+                v2 = bios[regb + 0x160];
+                v3 = bios[regb + 0x158];
+        }
+        SiS_SetReg(SISCR, 0x86, v1);
+        SiS_SetReg(SISCR, 0x82, 0x77);
+        SiS_SetReg(SISCR, 0x85, 0x00);
+        reg = SiS_GetReg(SISCR, 0x85);
+        SiS_SetReg(SISCR, 0x85, 0x88);
+        reg = SiS_GetReg(SISCR, 0x85);
+        SiS_SetReg(SISCR, 0x85, v2);
+        SiS_SetReg(SISCR, 0x82, v3);
+        SiS_SetReg(SISCR, 0x98, 0x01);
+        SiS_SetReg(SISCR, 0x9a, 0x02);
+        if (sisfb_xgi_is21(ivideo))
+                sisfb_post_xgi_ddr2_mrs_xg21(ivideo);
+        else
+                sisfb_post_xgi_ddr2_mrs_default(ivideo, regb);
+}
+
+static u8 __devinit
+sisfb_post_xgi_ramtype(struct sis_video_info *ivideo)
+{
+        unsigned char *bios = ivideo->bios_abase;
+        u8 ramtype;
+        u8 reg;
+        u8 v1;
+
+        ramtype = 0x00; v1 = 0x10;
+        if (ivideo->haveXGIROM) {
+                ramtype = bios[0x62];
+                v1 = bios[0x1d2];
+        }
+        if (!(ramtype & 0x80)) {
+                if (sisfb_xgi_is21(ivideo)) {
+                        SiS_SetRegAND(SISCR, 0xb4, 0xfd); /* GPIO control */
+                        SiS_SetRegOR(SISCR, 0x4a, 0x80);  /* GPIOH EN */
+                        reg = SiS_GetReg(SISCR, 0x48);
+                        SiS_SetRegOR(SISCR, 0xb4, 0x02);
+                        ramtype = reg & 0x01;             /* GPIOH */
+                } else if (ivideo->chip == XGI_20) {
+                        SiS_SetReg(SISCR, 0x97, v1);
+                        reg = SiS_GetReg(SISCR, 0x97);
+                        if (reg & 0x10) {
+                                ramtype = (reg & 0x01) << 1;
+                        }
+                } else {
+                        reg = SiS_GetReg(SISSR, 0x39);
+                        ramtype = reg & 0x02;
+                        if (!(ramtype)) {
+                                reg = SiS_GetReg(SISSR, 0x3a);
+                                ramtype = (reg >> 1) & 0x01;
+                        }
+                }
+        }
+        ramtype &= 0x07;
+
+        return ramtype;
+}
+
 static int __devinit
 sisfb_post_xgi(struct pci_dev *pdev)
 {
@@ -5213,9 +5392,23 @@ sisfb_post_xgi(struct pci_dev *pdev)
                 SiS_SetReg(SISCR, 0x77, v1);
         }
 
-        /* RAM type */
-
-        regb = 0;       /* ! */
+        /* RAM type:
+         *
+         * 0 == DDR1, 1 == DDR2, 2..7 == reserved?
+         *
+         * The code seems to written so that regb should equal ramtype,
+         * however, so far it has been hardcoded to 0. Enable other values only
+         * on XGI Z9, as it passes the POST, and add a warning for others.
+         */
+        ramtype = sisfb_post_xgi_ramtype(ivideo);
+        if (!sisfb_xgi_is21(ivideo) && ramtype) {
+                dev_warn(&pdev->dev,
+                         "RAM type something else than expected: %d\n",
+                         ramtype);
+                regb = 0;
+        } else {
+                regb = ramtype;
+        }
 
         v1 = 0xff;
         if(ivideo->haveXGIROM) {
@@ -5367,7 +5560,10 @@ sisfb_post_xgi(struct pci_dev *pdev)
                 }
         }
 
-        SiS_SetReg(SISSR, 0x17, 0x00);
+        if (regb == 1)
+                SiS_SetReg(SISSR, 0x17, 0x80);          /* DDR2 */
+        else
+                SiS_SetReg(SISSR, 0x17, 0x00);          /* DDR1 */
         SiS_SetReg(SISSR, 0x1a, 0x87);
 
         if(ivideo->chip == XGI_20) {
@@ -5375,31 +5571,6 @@ sisfb_post_xgi(struct pci_dev *pdev)
                 SiS_SetReg(SISSR, 0x1c, 0x00);
         }
 
-        ramtype = 0x00; v1 = 0x10;
-        if(ivideo->haveXGIROM) {
-                ramtype = bios[0x62];
-                v1 = bios[0x1d2];
-        }
-        if(!(ramtype & 0x80)) {
-                if(ivideo->chip == XGI_20) {
-                        SiS_SetReg(SISCR, 0x97, v1);
-                        reg = SiS_GetReg(SISCR, 0x97);
-                        if(reg & 0x10) {
-                                ramtype = (reg & 0x01) << 1;
-                        }
-                } else {
-                        reg = SiS_GetReg(SISSR, 0x39);
-                        ramtype = reg & 0x02;
-                        if(!(ramtype)) {
-                                reg = SiS_GetReg(SISSR, 0x3a);
-                                ramtype = (reg >> 1) & 0x01;
-                        }
-                }
-        }
-        ramtype &= 0x07;
-
-        regb = 0;       /* ! */
-
         switch(ramtype) {
         case 0:
                 sisfb_post_xgi_setclocks(ivideo, regb);
@@ -5485,61 +5656,7 @@ sisfb_post_xgi(struct pci_dev *pdev)
                 SiS_SetReg(SISSR, 0x1b, 0x00);
                 break;
         case 1:
-                SiS_SetReg(SISCR, 0x82, 0x77);
-                SiS_SetReg(SISCR, 0x86, 0x00);
-                reg = SiS_GetReg(SISCR, 0x86);
-                SiS_SetReg(SISCR, 0x86, 0x88);
-                reg = SiS_GetReg(SISCR, 0x86);
-                v1 = cs168[regb]; v2 = cs160[regb]; v3 = cs158[regb];
-                if(ivideo->haveXGIROM) {
-                        v1 = bios[regb + 0x168];
-                        v2 = bios[regb + 0x160];
-                        v3 = bios[regb + 0x158];
-                }
-                SiS_SetReg(SISCR, 0x86, v1);
-                SiS_SetReg(SISCR, 0x82, 0x77);
-                SiS_SetReg(SISCR, 0x85, 0x00);
-                reg = SiS_GetReg(SISCR, 0x85);
-                SiS_SetReg(SISCR, 0x85, 0x88);
-                reg = SiS_GetReg(SISCR, 0x85);
-                SiS_SetReg(SISCR, 0x85, v2);
-                SiS_SetReg(SISCR, 0x82, v3);
-                SiS_SetReg(SISCR, 0x98, 0x01);
-                SiS_SetReg(SISCR, 0x9a, 0x02);
-
-                SiS_SetReg(SISSR, 0x28, 0x64);
-                SiS_SetReg(SISSR, 0x29, 0x63);
-                sisfb_post_xgi_delay(ivideo, 15);
-                SiS_SetReg(SISSR, 0x18, 0x00);
-                SiS_SetReg(SISSR, 0x19, 0x20);
-                SiS_SetReg(SISSR, 0x16, 0x00);
-                SiS_SetReg(SISSR, 0x16, 0x80);
-                SiS_SetReg(SISSR, 0x18, 0xc5);
-                SiS_SetReg(SISSR, 0x19, 0x23);
-                SiS_SetReg(SISSR, 0x16, 0x00);
-                SiS_SetReg(SISSR, 0x16, 0x80);
-                sisfb_post_xgi_delay(ivideo, 1);
-                SiS_SetReg(SISCR, 0x97, 0x11);
-                sisfb_post_xgi_setclocks(ivideo, regb);
-                sisfb_post_xgi_delay(ivideo, 0x46);
-                SiS_SetReg(SISSR, 0x18, 0xc5);
-                SiS_SetReg(SISSR, 0x19, 0x23);
-                SiS_SetReg(SISSR, 0x16, 0x00);
-                SiS_SetReg(SISSR, 0x16, 0x80);
-                sisfb_post_xgi_delay(ivideo, 1);
-                SiS_SetReg(SISSR, 0x1b, 0x04);
-                sisfb_post_xgi_delay(ivideo, 1);
-                SiS_SetReg(SISSR, 0x1b, 0x00);
-                sisfb_post_xgi_delay(ivideo, 1);
-                v1 = 0x31;
-                if(ivideo->haveXGIROM) {
-                        v1 = bios[0xf0];
-                }
-                SiS_SetReg(SISSR, 0x18, v1);
-                SiS_SetReg(SISSR, 0x19, 0x06);
-                SiS_SetReg(SISSR, 0x16, 0x04);
-                SiS_SetReg(SISSR, 0x16, 0x84);
-                sisfb_post_xgi_delay(ivideo, 1);
+                sisfb_post_xgi_ddr2(ivideo, regb);
                 break;
         default:
                 sisfb_post_xgi_setclocks(ivideo, regb);
@@ -5648,6 +5765,7 @@ sisfb_post_xgi(struct pci_dev *pdev)
                 SiS_SetReg(SISSR, 0x14, bios[regb + 0xe0 + 8]);
 
         } else {
+                int err;
 
                 /* Set default mode, don't clear screen */
                 ivideo->SiS_Pr.SiS_UseOEM = false;
@@ -5661,10 +5779,16 @@ sisfb_post_xgi(struct pci_dev *pdev)
 
                 /* Disable read-cache */
                 SiS_SetRegAND(SISSR, 0x21, 0xdf);
-                sisfb_post_xgi_ramsize(ivideo);
+                err = sisfb_post_xgi_ramsize(ivideo);
                 /* Enable read-cache */
                 SiS_SetRegOR(SISSR, 0x21, 0x20);
 
+                if (err) {
+                        dev_err(&pdev->dev,
+                                "%s: RAM size detection failed: %d\n",
+                                __func__, err);
+                        return 0;
+                }
         }
 
 #if 0
@@ -5777,6 +5901,7 @@ sisfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 #endif
 
         ivideo->chip = chipinfo->chip;
+        ivideo->chip_real_id = chipinfo->chip;
         ivideo->sisvga_engine = chipinfo->vgaengine;
         ivideo->hwcursor_size = chipinfo->hwcursor_size;
         ivideo->CRT2_write_enable = chipinfo->CRT2_write_enable;
@@ -6010,6 +6135,18 @@ sisfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                 sisfb_detect_custom_timing(ivideo);
         }
 
+#ifdef CONFIG_FB_SIS_315
+        if (ivideo->chip == XGI_20) {
+                /* Check if our Z7 chip is actually Z9 */
+                SiS_SetRegOR(SISCR, 0x4a, 0x40);        /* GPIOG EN */
+                reg = SiS_GetReg(SISCR, 0x48);
+                if (reg & 0x02) {                       /* GPIOG */
+                        ivideo->chip_real_id = XGI_21;
+                        dev_info(&pdev->dev, "Z9 detected\n");
+                }
+        }
+#endif
+
         /* POST card in case this has not been done by the BIOS */
         if( (!ivideo->sisvga_enabled)
 #if !defined(__i386__) && !defined(__x86_64__)
diff --git a/drivers/video/sis/vgatypes.h b/drivers/video/sis/vgatypes.h
index 12c0dfaf2518..e3f9976cfef0 100644
--- a/drivers/video/sis/vgatypes.h
+++ b/drivers/video/sis/vgatypes.h
@@ -87,6 +87,7 @@ typedef enum _SIS_CHIP_TYPE {
     SIS_341,
     SIS_342,
     XGI_20  = 75,
+    XGI_21,
     XGI_40,
     MAX_SIS_CHIP
 } SIS_CHIP_TYPE;
diff --git a/drivers/video/sm501fb.c b/drivers/video/sm501fb.c
index bcb44a594ebc..46d1a64fe80d 100644
--- a/drivers/video/sm501fb.c
+++ b/drivers/video/sm501fb.c
@@ -41,6 +41,26 @@
 #include <linux/sm501.h>
 #include <linux/sm501-regs.h>
 
+#include "edid.h"
+
+static char *fb_mode = "640x480-16@60";
+static unsigned long default_bpp = 16;
+
+static struct fb_videomode __devinitdata sm501_default_mode = {
+        .refresh        = 60,
+        .xres           = 640,
+        .yres           = 480,
+        .pixclock       = 20833,
+        .left_margin    = 142,
+        .right_margin   = 13,
+        .upper_margin   = 21,
+        .lower_margin   = 1,
+        .hsync_len      = 69,
+        .vsync_len      = 3,
+        .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+        .vmode          = FB_VMODE_NONINTERLACED
+};
+
 #define NR_PALETTE      256
 
 enum sm501_controller {
@@ -77,6 +97,7 @@ struct sm501fb_info {
         void __iomem            *regs2d;        /* 2d remapped registers */
         void __iomem            *fbmem;         /* remapped framebuffer */
         size_t                   fbmem_len;     /* length of remapped region */
+        u8 *edid_data;
 };
 
 /* per-framebuffer private data */
@@ -117,7 +138,7 @@ static inline int v_total(struct fb_var_screeninfo *var)
 
 static inline void sm501fb_sync_regs(struct sm501fb_info *info)
 {
-        readl(info->regs);
+        smc501_readl(info->regs);
 }
 
 /* sm501_alloc_mem
@@ -262,7 +283,7 @@ static void sm501fb_setup_gamma(struct sm501fb_info *fbi,
 
         /* set gamma values */
         for (offset = 0; offset < 256 * 4; offset += 4) {
-                writel(value, fbi->regs + palette + offset);
+                smc501_writel(value, fbi->regs + palette + offset);
                 value += 0x010101;      /* Advance RGB by 1,1,1.*/
         }
 }
@@ -476,7 +497,8 @@ static int sm501fb_set_par_common(struct fb_info *info,
 
         /* set start of framebuffer to the screen */
 
-        writel(par->screen.sm_addr | SM501_ADDR_FLIP, fbi->regs + head_addr);
+        smc501_writel(par->screen.sm_addr | SM501_ADDR_FLIP,
+                        fbi->regs + head_addr);
 
         /* program CRT clock  */
 
@@ -519,7 +541,7 @@ static void sm501fb_set_par_geometry(struct fb_info *info,
         reg = info->fix.line_length;
         reg |= ((var->xres * var->bits_per_pixel)/8) << 16;
 
-        writel(reg, fbi->regs + (par->head == HEAD_CRT ?
+        smc501_writel(reg, fbi->regs + (par->head == HEAD_CRT ?
                     SM501_DC_CRT_FB_OFFSET :  SM501_DC_PANEL_FB_OFFSET));
 
         /* program horizontal total */
@@ -527,27 +549,27 @@ static void sm501fb_set_par_geometry(struct fb_info *info,
         reg  = (h_total(var) - 1) << 16;
         reg |= (var->xres - 1);
 
-        writel(reg, base + SM501_OFF_DC_H_TOT);
+        smc501_writel(reg, base + SM501_OFF_DC_H_TOT);
 
         /* program horizontal sync */
 
         reg  = var->hsync_len << 16;
         reg |= var->xres + var->right_margin - 1;
 
-        writel(reg, base + SM501_OFF_DC_H_SYNC);
+        smc501_writel(reg, base + SM501_OFF_DC_H_SYNC);
 
         /* program vertical total */
 
         reg  = (v_total(var) - 1) << 16;
         reg |= (var->yres - 1);
 
-        writel(reg, base + SM501_OFF_DC_V_TOT);
+        smc501_writel(reg, base + SM501_OFF_DC_V_TOT);
 
         /* program vertical sync */
         reg  = var->vsync_len << 16;
         reg |= var->yres + var->lower_margin - 1;
 
-        writel(reg, base + SM501_OFF_DC_V_SYNC);
+        smc501_writel(reg, base + SM501_OFF_DC_V_SYNC);
 }
 
 /* sm501fb_pan_crt
@@ -566,15 +588,15 @@ static int sm501fb_pan_crt(struct fb_var_screeninfo *var,
 
         xoffs = var->xoffset * bytes_pixel;
 
-        reg = readl(fbi->regs + SM501_DC_CRT_CONTROL);
+        reg = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL);
 
         reg &= ~SM501_DC_CRT_CONTROL_PIXEL_MASK;
         reg |= ((xoffs & 15) / bytes_pixel) << 4;
-        writel(reg, fbi->regs + SM501_DC_CRT_CONTROL);
+        smc501_writel(reg, fbi->regs + SM501_DC_CRT_CONTROL);
 
         reg = (par->screen.sm_addr + xoffs +
                var->yoffset * info->fix.line_length);
-        writel(reg | SM501_ADDR_FLIP, fbi->regs + SM501_DC_CRT_FB_ADDR);
+        smc501_writel(reg | SM501_ADDR_FLIP, fbi->regs + SM501_DC_CRT_FB_ADDR);
 
         sm501fb_sync_regs(fbi);
         return 0;
@@ -593,10 +615,10 @@ static int sm501fb_pan_pnl(struct fb_var_screeninfo *var,
         unsigned long reg;
 
         reg = var->xoffset | (var->xres_virtual << 16);
-        writel(reg, fbi->regs + SM501_DC_PANEL_FB_WIDTH);
+        smc501_writel(reg, fbi->regs + SM501_DC_PANEL_FB_WIDTH);
 
         reg = var->yoffset | (var->yres_virtual << 16);
-        writel(reg, fbi->regs + SM501_DC_PANEL_FB_HEIGHT);
+        smc501_writel(reg, fbi->regs + SM501_DC_PANEL_FB_HEIGHT);
 
         sm501fb_sync_regs(fbi);
         return 0;
@@ -622,7 +644,7 @@ static int sm501fb_set_par_crt(struct fb_info *info)
         /* enable CRT DAC - note 0 is on!*/
         sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER);
 
-        control = readl(fbi->regs + SM501_DC_CRT_CONTROL);
+        control = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL);
 
         control &= (SM501_DC_CRT_CONTROL_PIXEL_MASK |
                     SM501_DC_CRT_CONTROL_GAMMA |
@@ -684,7 +706,7 @@ static int sm501fb_set_par_crt(struct fb_info *info)
  out_update:
         dev_dbg(fbi->dev, "new control is %08lx\n", control);
 
-        writel(control, fbi->regs + SM501_DC_CRT_CONTROL);
+        smc501_writel(control, fbi->regs + SM501_DC_CRT_CONTROL);
         sm501fb_sync_regs(fbi);
 
         return 0;
@@ -696,18 +718,18 @@ static void sm501fb_panel_power(struct sm501fb_info *fbi, int to)
         void __iomem *ctrl_reg = fbi->regs + SM501_DC_PANEL_CONTROL;
         struct sm501_platdata_fbsub *pd = fbi->pdata->fb_pnl;
 
-        control = readl(ctrl_reg);
+        control = smc501_readl(ctrl_reg);
 
         if (to && (control & SM501_DC_PANEL_CONTROL_VDD) == 0) {
                 /* enable panel power */
 
                 control |= SM501_DC_PANEL_CONTROL_VDD;  /* FPVDDEN */
-                writel(control, ctrl_reg);
+                smc501_writel(control, ctrl_reg);
                 sm501fb_sync_regs(fbi);
                 mdelay(10);
 
                 control |= SM501_DC_PANEL_CONTROL_DATA; /* DATA */
-                writel(control, ctrl_reg);
+                smc501_writel(control, ctrl_reg);
                 sm501fb_sync_regs(fbi);
                 mdelay(10);
 
@@ -719,7 +741,7 @@ static void sm501fb_panel_power(struct sm501fb_info *fbi, int to)
                         else
                                 control |= SM501_DC_PANEL_CONTROL_BIAS;
 
-                        writel(control, ctrl_reg);
+                        smc501_writel(control, ctrl_reg);
                         sm501fb_sync_regs(fbi);
                         mdelay(10);
                 }
@@ -730,7 +752,7 @@ static void sm501fb_panel_power(struct sm501fb_info *fbi, int to)
                         else
                                 control |= SM501_DC_PANEL_CONTROL_FPEN;
 
-                        writel(control, ctrl_reg);
+                        smc501_writel(control, ctrl_reg);
                         sm501fb_sync_regs(fbi);
                         mdelay(10);
                 }
@@ -742,7 +764,7 @@ static void sm501fb_panel_power(struct sm501fb_info *fbi, int to)
                         else
                                 control &= ~SM501_DC_PANEL_CONTROL_FPEN;
 
-                        writel(control, ctrl_reg);
+                        smc501_writel(control, ctrl_reg);
                         sm501fb_sync_regs(fbi);
                         mdelay(10);
                 }
@@ -753,18 +775,18 @@ static void sm501fb_panel_power(struct sm501fb_info *fbi, int to)
                         else
                                 control &= ~SM501_DC_PANEL_CONTROL_BIAS;
 
-                        writel(control, ctrl_reg);
+                        smc501_writel(control, ctrl_reg);
                         sm501fb_sync_regs(fbi);
                         mdelay(10);
                 }
 
                 control &= ~SM501_DC_PANEL_CONTROL_DATA;
-                writel(control, ctrl_reg);
+                smc501_writel(control, ctrl_reg);
                 sm501fb_sync_regs(fbi);
                 mdelay(10);
 
                 control &= ~SM501_DC_PANEL_CONTROL_VDD;
-                writel(control, ctrl_reg);
+                smc501_writel(control, ctrl_reg);
                 sm501fb_sync_regs(fbi);
                 mdelay(10);
         }
@@ -799,7 +821,7 @@ static int sm501fb_set_par_pnl(struct fb_info *info)
 
         /* update control register */
 
-        control = readl(fbi->regs + SM501_DC_PANEL_CONTROL);
+        control = smc501_readl(fbi->regs + SM501_DC_PANEL_CONTROL);
         control &= (SM501_DC_PANEL_CONTROL_GAMMA |
                     SM501_DC_PANEL_CONTROL_VDD  |
                     SM501_DC_PANEL_CONTROL_DATA |
@@ -833,16 +855,16 @@ static int sm501fb_set_par_pnl(struct fb_info *info)
                 BUG();
         }
 
-        writel(0x0, fbi->regs + SM501_DC_PANEL_PANNING_CONTROL);
+        smc501_writel(0x0, fbi->regs + SM501_DC_PANEL_PANNING_CONTROL);
 
         /* panel plane top left and bottom right location */
 
-        writel(0x00, fbi->regs + SM501_DC_PANEL_TL_LOC);
+        smc501_writel(0x00, fbi->regs + SM501_DC_PANEL_TL_LOC);
 
         reg  = var->xres - 1;
         reg |= (var->yres - 1) << 16;
 
-        writel(reg, fbi->regs + SM501_DC_PANEL_BR_LOC);
+        smc501_writel(reg, fbi->regs + SM501_DC_PANEL_BR_LOC);
 
         /* program panel control register */
 
@@ -855,7 +877,7 @@ static int sm501fb_set_par_pnl(struct fb_info *info)
         if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
                 control |= SM501_DC_PANEL_CONTROL_VSP;
 
-        writel(control, fbi->regs + SM501_DC_PANEL_CONTROL);
+        smc501_writel(control, fbi->regs + SM501_DC_PANEL_CONTROL);
         sm501fb_sync_regs(fbi);
 
         /* ensure the panel interface is not tristated at this point */
@@ -924,7 +946,7 @@ static int sm501fb_setcolreg(unsigned regno,
                         val |= (green >> 8) << 8;
                         val |= blue >> 8;
 
-                        writel(val, base + (regno * 4));
+                        smc501_writel(val, base + (regno * 4));
                 }
 
                 break;
@@ -980,7 +1002,7 @@ static int sm501fb_blank_crt(int blank_mode, struct fb_info *info)
 
         dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info);
 
-        ctrl = readl(fbi->regs + SM501_DC_CRT_CONTROL);
+        ctrl = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL);
 
         switch (blank_mode) {
         case FB_BLANK_POWERDOWN:
@@ -1004,7 +1026,7 @@ static int sm501fb_blank_crt(int blank_mode, struct fb_info *info)
 
         }
 
-        writel(ctrl, fbi->regs + SM501_DC_CRT_CONTROL);
+        smc501_writel(ctrl, fbi->regs + SM501_DC_CRT_CONTROL);
         sm501fb_sync_regs(fbi);
 
         return 0;
@@ -1041,12 +1063,14 @@ static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
         if (cursor->image.depth > 1)
                 return -EINVAL;
 
-        hwc_addr = readl(base + SM501_OFF_HWC_ADDR);
+        hwc_addr = smc501_readl(base + SM501_OFF_HWC_ADDR);
 
         if (cursor->enable)
-                writel(hwc_addr | SM501_HWC_EN, base + SM501_OFF_HWC_ADDR);
+                smc501_writel(hwc_addr | SM501_HWC_EN,
+                                base + SM501_OFF_HWC_ADDR);
         else
-                writel(hwc_addr & ~SM501_HWC_EN, base + SM501_OFF_HWC_ADDR);
+                smc501_writel(hwc_addr & ~SM501_HWC_EN,
+                                base + SM501_OFF_HWC_ADDR);
 
         /* set data */
         if (cursor->set & FB_CUR_SETPOS) {
@@ -1060,7 +1084,7 @@ static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
 
                 //y += cursor->image.height;
 
-                writel(x | (y << 16), base + SM501_OFF_HWC_LOC);
+                smc501_writel(x | (y << 16), base + SM501_OFF_HWC_LOC);
         }
 
         if (cursor->set & FB_CUR_SETCMAP) {
@@ -1080,8 +1104,8 @@ static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
 
                 dev_dbg(fbi->dev, "fgcol %08lx, bgcol %08lx\n", fg, bg);
 
-                writel(bg, base + SM501_OFF_HWC_COLOR_1_2);
-                writel(fg, base + SM501_OFF_HWC_COLOR_3);
+                smc501_writel(bg, base + SM501_OFF_HWC_COLOR_1_2);
+                smc501_writel(fg, base + SM501_OFF_HWC_COLOR_3);
         }
 
         if (cursor->set & FB_CUR_SETSIZE ||
@@ -1102,7 +1126,7 @@ static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
                         __func__, cursor->image.width, cursor->image.height);
 
                 for (op = 0; op < (64*64*2)/8; op+=4)
-                        writel(0x0, dst + op);
+                        smc501_writel(0x0, dst + op);
 
                 for (y = 0; y < cursor->image.height; y++) {
                         for (x = 0; x < cursor->image.width; x++) {
@@ -1141,7 +1165,7 @@ static ssize_t sm501fb_crtsrc_show(struct device *dev,
         struct sm501fb_info *info = dev_get_drvdata(dev);
         unsigned long ctrl;
 
-        ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
+        ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
         ctrl &= SM501_DC_CRT_CONTROL_SEL;
 
         return snprintf(buf, PAGE_SIZE, "%s\n", ctrl ? "crt" : "panel");
@@ -1172,7 +1196,7 @@ static ssize_t sm501fb_crtsrc_store(struct device *dev,
 
         dev_info(dev, "setting crt source to head %d\n", head);
 
-        ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
+        ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
 
         if (head == HEAD_CRT) {
                 ctrl |= SM501_DC_CRT_CONTROL_SEL;
@@ -1184,7 +1208,7 @@ static ssize_t sm501fb_crtsrc_store(struct device *dev,
                 ctrl &= ~SM501_DC_CRT_CONTROL_TE;
         }
 
-        writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
+        smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
         sm501fb_sync_regs(info);
 
         return len;
@@ -1205,7 +1229,8 @@ static int sm501fb_show_regs(struct sm501fb_info *info, char *ptr,
         unsigned int reg;
 
         for (reg = start; reg < (len + start); reg += 4)
-                ptr += sprintf(ptr, "%08x = %08x\n", reg, readl(mem + reg));
+                ptr += sprintf(ptr, "%08x = %08x\n", reg,
+                                smc501_readl(mem + reg));
 
         return ptr - buf;
 }
@@ -1257,7 +1282,7 @@ static int sm501fb_sync(struct fb_info *info)
 
         /* wait for the 2d engine to be ready */
         while ((count > 0) &&
-               (readl(fbi->regs + SM501_SYSTEM_CONTROL) &
+               (smc501_readl(fbi->regs + SM501_SYSTEM_CONTROL) &
                 SM501_SYSCTRL_2D_ENGINE_STATUS) != 0)
                 count--;
 
@@ -1312,45 +1337,46 @@ static void sm501fb_copyarea(struct fb_info *info, const struct fb_copyarea *are
                 return;
 
         /* set the base addresses */
-        writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE);
-        writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_DESTINATION_BASE);
+        smc501_writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE);
+        smc501_writel(par->screen.sm_addr,
+                        fbi->regs2d + SM501_2D_DESTINATION_BASE);
 
         /* set the window width */
-        writel((info->var.xres << 16) | info->var.xres,
+        smc501_writel((info->var.xres << 16) | info->var.xres,
                fbi->regs2d + SM501_2D_WINDOW_WIDTH);
 
         /* set window stride */
-        writel((info->var.xres_virtual << 16) | info->var.xres_virtual,
+        smc501_writel((info->var.xres_virtual << 16) | info->var.xres_virtual,
                fbi->regs2d + SM501_2D_PITCH);
 
         /* set data format */
         switch (info->var.bits_per_pixel) {
         case 8:
-                writel(0, fbi->regs2d + SM501_2D_STRETCH);
+                smc501_writel(0, fbi->regs2d + SM501_2D_STRETCH);
                 break;
         case 16:
-                writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH);
+                smc501_writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH);
                 break;
         case 32:
-                writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH);
+                smc501_writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH);
                 break;
         }
 
         /* 2d compare mask */
-        writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK);
+        smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK);
 
         /* 2d mask */
-        writel(0xffffffff, fbi->regs2d + SM501_2D_MASK);
+        smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_MASK);
 
         /* source and destination x y */
-        writel((sx << 16) | sy, fbi->regs2d + SM501_2D_SOURCE);
-        writel((dx << 16) | dy, fbi->regs2d + SM501_2D_DESTINATION);
+        smc501_writel((sx << 16) | sy, fbi->regs2d + SM501_2D_SOURCE);
+        smc501_writel((dx << 16) | dy, fbi->regs2d + SM501_2D_DESTINATION);
 
         /* w/h */
-        writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION);
+        smc501_writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION);
 
         /* do area move */
-        writel(0x800000cc | rtl, fbi->regs2d + SM501_2D_CONTROL);
+        smc501_writel(0x800000cc | rtl, fbi->regs2d + SM501_2D_CONTROL);
 }
 
 static void sm501fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
@@ -1372,47 +1398,49 @@ static void sm501fb_fillrect(struct fb_info *info, const struct fb_fillrect *rec
                 return;
 
         /* set the base addresses */
-        writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE);
-        writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_DESTINATION_BASE);
+        smc501_writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE);
+        smc501_writel(par->screen.sm_addr,
+                        fbi->regs2d + SM501_2D_DESTINATION_BASE);
 
         /* set the window width */
-        writel((info->var.xres << 16) | info->var.xres,
+        smc501_writel((info->var.xres << 16) | info->var.xres,
                fbi->regs2d + SM501_2D_WINDOW_WIDTH);
 
         /* set window stride */
-        writel((info->var.xres_virtual << 16) | info->var.xres_virtual,
+        smc501_writel((info->var.xres_virtual << 16) | info->var.xres_virtual,
                fbi->regs2d + SM501_2D_PITCH);
 
         /* set data format */
         switch (info->var.bits_per_pixel) {
         case 8:
-                writel(0, fbi->regs2d + SM501_2D_STRETCH);
+                smc501_writel(0, fbi->regs2d + SM501_2D_STRETCH);
                 break;
         case 16:
-                writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH);
+                smc501_writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH);
                 break;
         case 32:
-                writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH);
+                smc501_writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH);
                 break;
         }
 
         /* 2d compare mask */
-        writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK);
+        smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK);
 
         /* 2d mask */
-        writel(0xffffffff, fbi->regs2d + SM501_2D_MASK);
+        smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_MASK);
 
         /* colour */
-        writel(rect->color, fbi->regs2d + SM501_2D_FOREGROUND);
+        smc501_writel(rect->color, fbi->regs2d + SM501_2D_FOREGROUND);
 
         /* x y */
-        writel((rect->dx << 16) | rect->dy, fbi->regs2d + SM501_2D_DESTINATION);
+        smc501_writel((rect->dx << 16) | rect->dy,
+                        fbi->regs2d + SM501_2D_DESTINATION);
 
         /* w/h */
-        writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION);
+        smc501_writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION);
 
         /* do rectangle fill */
-        writel(0x800100cc, fbi->regs2d + SM501_2D_CONTROL);
+        smc501_writel(0x800100cc, fbi->regs2d + SM501_2D_CONTROL);
 }
 
 
@@ -1470,11 +1498,12 @@ static int sm501_init_cursor(struct fb_info *fbi, unsigned int reg_base)
 
         /* initialise the colour registers */
 
-        writel(par->cursor.sm_addr, par->cursor_regs + SM501_OFF_HWC_ADDR);
+        smc501_writel(par->cursor.sm_addr,
+                        par->cursor_regs + SM501_OFF_HWC_ADDR);
 
-        writel(0x00, par->cursor_regs + SM501_OFF_HWC_LOC);
-        writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_1_2);
-        writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_3);
+        smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_LOC);
+        smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_1_2);
+        smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_3);
         sm501fb_sync_regs(info);
 
         return 0;
@@ -1581,7 +1610,7 @@ static int sm501fb_start(struct sm501fb_info *info,
 
         /* clear palette ram - undefined at power on */
         for (k = 0; k < (256 * 3); k++)
-                writel(0, info->regs + SM501_DC_PANEL_PALETTE + (k * 4));
+                smc501_writel(0, info->regs + SM501_DC_PANEL_PALETTE + (k * 4));
 
         /* enable display controller */
         sm501_unit_power(dev->parent, SM501_GATE_DISPLAY, 1);
@@ -1649,20 +1678,20 @@ static int sm501fb_init_fb(struct fb_info *fb,
         switch (head) {
         case HEAD_CRT:
                 pd = info->pdata->fb_crt;
-                ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
+                ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
                 enable = (ctrl & SM501_DC_CRT_CONTROL_ENABLE) ? 1 : 0;
 
                 /* ensure we set the correct source register */
                 if (info->pdata->fb_route != SM501_FB_CRT_PANEL) {
                         ctrl |= SM501_DC_CRT_CONTROL_SEL;
-                        writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
+                        smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
                 }
 
                 break;
 
         case HEAD_PANEL:
                 pd = info->pdata->fb_pnl;
-                ctrl = readl(info->regs + SM501_DC_PANEL_CONTROL);
+                ctrl = smc501_readl(info->regs + SM501_DC_PANEL_CONTROL);
                 enable = (ctrl & SM501_DC_PANEL_CONTROL_EN) ? 1 : 0;
                 break;
 
@@ -1680,7 +1709,7 @@ static int sm501fb_init_fb(struct fb_info *fb,
 
         if (head == HEAD_CRT && info->pdata->fb_route == SM501_FB_CRT_PANEL) {
                 ctrl &= ~SM501_DC_CRT_CONTROL_SEL;
-                writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
+                smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
                 enable = 0;
         }
 
@@ -1700,6 +1729,15 @@ static int sm501fb_init_fb(struct fb_info *fb,
                 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT |
                 FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN;
 
+#if defined(CONFIG_OF)
+#ifdef __BIG_ENDIAN
+        if (of_get_property(info->dev->parent->of_node, "little-endian", NULL))
+                fb->flags |= FBINFO_FOREIGN_ENDIAN;
+#else
+        if (of_get_property(info->dev->parent->of_node, "big-endian", NULL))
+                fb->flags |= FBINFO_FOREIGN_ENDIAN;
+#endif
+#endif
         /* fixed data */
 
         fb->fix.type            = FB_TYPE_PACKED_PIXELS;
@@ -1717,9 +1755,16 @@ static int sm501fb_init_fb(struct fb_info *fb,
         fb->var.vmode           = FB_VMODE_NONINTERLACED;
         fb->var.bits_per_pixel  = 16;
 
+        if (info->edid_data) {
+                        /* Now build modedb from EDID */
+                        fb_edid_to_monspecs(info->edid_data, &fb->monspecs);
+                        fb_videomode_to_modelist(fb->monspecs.modedb,
+                                                 fb->monspecs.modedb_len,
+                                                 &fb->modelist);
+        }
+
         if (enable && (pd->flags & SM501FB_FLAG_USE_INIT_MODE) && 0) {
                 /* TODO read the mode from the current display */
-
         } else {
                 if (pd->def_mode) {
                         dev_info(info->dev, "using supplied mode\n");
@@ -1729,12 +1774,37 @@ static int sm501fb_init_fb(struct fb_info *fb,
                         fb->var.xres_virtual = fb->var.xres;
                         fb->var.yres_virtual = fb->var.yres;
                 } else {
-                        ret = fb_find_mode(&fb->var, fb,
+                        if (info->edid_data) {
+                                ret = fb_find_mode(&fb->var, fb, fb_mode,
+                                        fb->monspecs.modedb,
+                                        fb->monspecs.modedb_len,
+                                        &sm501_default_mode, default_bpp);
+                                /* edid_data is no longer needed, free it */
+                                kfree(info->edid_data);
+                        } else {
+                                ret = fb_find_mode(&fb->var, fb,
                                            NULL, NULL, 0, NULL, 8);
+                        }
 
-                        if (ret == 0 || ret == 4) {
-                                dev_err(info->dev,
-                                        "failed to get initial mode\n");
+                        switch (ret) {
+                        case 1:
+                                dev_info(info->dev, "using mode specified in "
+                                                "@mode\n");
+                                break;
+                        case 2:
+                                dev_info(info->dev, "using mode specified in "
+                                        "@mode with ignored refresh rate\n");
+                                break;
+                        case 3:
+                                dev_info(info->dev, "using mode default "
+                                        "mode\n");
+                                break;
+                        case 4:
+                                dev_info(info->dev, "using mode from list\n");
+                                break;
+                        default:
+                                dev_info(info->dev, "ret = %d\n", ret);
+                                dev_info(info->dev, "failed to find mode\n");
                                 return -EINVAL;
                         }
                 }
@@ -1875,8 +1945,32 @@ static int __devinit sm501fb_probe(struct platform_device *pdev)
         }
 
         if (info->pdata == NULL) {
-                dev_info(dev, "using default configuration data\n");
+                int found = 0;
+#if defined(CONFIG_OF)
+                struct device_node *np = pdev->dev.parent->of_node;
+                const u8 *prop;
+                const char *cp;
+                int len;
+
                 info->pdata = &sm501fb_def_pdata;
+                if (np) {
+                        /* Get EDID */
+                        cp = of_get_property(np, "mode", &len);
+                        if (cp)
+                                strcpy(fb_mode, cp);
+                        prop = of_get_property(np, "edid", &len);
+                        if (prop && len == EDID_LENGTH) {
+                                info->edid_data = kmemdup(prop, EDID_LENGTH,
+                                                          GFP_KERNEL);
+                                if (info->edid_data)
+                                        found = 1;
+                        }
+                }
+#endif
+                if (!found) {
+                        dev_info(dev, "using default configuration data\n");
+                        info->pdata = &sm501fb_def_pdata;
+                }
         }
 
         /* probe for the presence of each panel */
@@ -2085,7 +2179,7 @@ static int sm501fb_suspend(struct platform_device *pdev, pm_message_t state)
         struct sm501fb_info *info = platform_get_drvdata(pdev);
 
         /* store crt control to resume with */
-        info->pm_crt_ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
+        info->pm_crt_ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
 
         sm501fb_suspend_fb(info, HEAD_CRT);
         sm501fb_suspend_fb(info, HEAD_PANEL);
@@ -2109,10 +2203,10 @@ static int sm501fb_resume(struct platform_device *pdev)
 
         /* restore the items we want to be saved for crt control */
 
-        crt_ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
+        crt_ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
         crt_ctrl &= ~SM501_CRT_CTRL_SAVE;
         crt_ctrl |= info->pm_crt_ctrl & SM501_CRT_CTRL_SAVE;
-        writel(crt_ctrl, info->regs + SM501_DC_CRT_CONTROL);
+        smc501_writel(crt_ctrl, info->regs + SM501_DC_CRT_CONTROL);
 
         sm501fb_resume_fb(info, HEAD_CRT);
         sm501fb_resume_fb(info, HEAD_PANEL);
@@ -2149,6 +2243,11 @@ static void __exit sm501fb_cleanup(void)
 module_init(sm501fb_init);
 module_exit(sm501fb_cleanup);
 
+module_param_named(mode, fb_mode, charp, 0);
+MODULE_PARM_DESC(mode,
+        "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
+module_param_named(bpp, default_bpp, ulong, 0);
+MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified mode");
 MODULE_AUTHOR("Ben Dooks, Vincent Sanders");
 MODULE_DESCRIPTION("SM501 Framebuffer driver");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/video/sunxvr1000.c b/drivers/video/sunxvr1000.c
index 5dbe06af2226..b7f27acaf817 100644
--- a/drivers/video/sunxvr1000.c
+++ b/drivers/video/sunxvr1000.c
@@ -111,8 +111,7 @@ static int __devinit gfb_set_fbinfo(struct gfb_info *gp)
         return 0;
 }
 
-static int __devinit gfb_probe(struct platform_device *op,
-                               const struct of_device_id *match)
+static int __devinit gfb_probe(struct platform_device *op)
 {
         struct device_node *dp = op->dev.of_node;
         struct fb_info *info;
@@ -198,7 +197,7 @@ static const struct of_device_id gfb_match[] = {
 };
 MODULE_DEVICE_TABLE(of, ffb_match);
 
-static struct of_platform_driver gfb_driver = {
+static struct platform_driver gfb_driver = {
         .probe          = gfb_probe,
         .remove         = __devexit_p(gfb_remove),
         .driver = {
@@ -213,12 +212,12 @@ static int __init gfb_init(void)
         if (fb_get_options("gfb", NULL))
                 return -ENODEV;
 
-        return of_register_platform_driver(&gfb_driver);
+        return platform_driver_register(&gfb_driver);
 }
 
 static void __exit gfb_exit(void)
 {
-        of_unregister_platform_driver(&gfb_driver);
+        platform_driver_unregister(&gfb_driver);
 }
 
 module_init(gfb_init);
diff --git a/drivers/video/svgalib.c b/drivers/video/svgalib.c
index fdb45674e2f6..33df9ec91795 100644
--- a/drivers/video/svgalib.c
+++ b/drivers/video/svgalib.c
@@ -20,12 +20,12 @@
 
 
 /* Write a CRT register value spread across multiple registers */
-void svga_wcrt_multi(const struct vga_regset *regset, u32 value) {
-
+void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value)
+{
         u8 regval, bitval, bitnum;
 
         while (regset->regnum != VGA_REGSET_END_VAL) {
-                regval = vga_rcrt(NULL, regset->regnum);
+                regval = vga_rcrt(regbase, regset->regnum);
                 bitnum = regset->lowbit;
                 while (bitnum <= regset->highbit) {
                         bitval = 1 << bitnum;
@@ -34,18 +34,18 @@ void svga_wcrt_multi(const struct vga_regset *regset, u32 value) {
                         bitnum ++;
                         value = value >> 1;
                 }
-                vga_wcrt(NULL, regset->regnum, regval);
+                vga_wcrt(regbase, regset->regnum, regval);
                 regset ++;
         }
 }
 
 /* Write a sequencer register value spread across multiple registers */
-void svga_wseq_multi(const struct vga_regset *regset, u32 value) {
-
+void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value)
+{
         u8 regval, bitval, bitnum;
 
         while (regset->regnum != VGA_REGSET_END_VAL) {
-                regval = vga_rseq(NULL, regset->regnum);
+                regval = vga_rseq(regbase, regset->regnum);
                 bitnum = regset->lowbit;
                 while (bitnum <= regset->highbit) {
                         bitval = 1 << bitnum;
@@ -54,7 +54,7 @@ void svga_wseq_multi(const struct vga_regset *regset, u32 value) {
                         bitnum ++;
                         value = value >> 1;
                 }
-                vga_wseq(NULL, regset->regnum, regval);
+                vga_wseq(regbase, regset->regnum, regval);
                 regset ++;
         }
 }
@@ -75,95 +75,95 @@ static unsigned int svga_regset_size(const struct vga_regset *regset)
 
 
 /* Set graphics controller registers to sane values */
-void svga_set_default_gfx_regs(void)
+void svga_set_default_gfx_regs(void __iomem *regbase)
 {
         /* All standard GFX registers (GR00 - GR08) */
-        vga_wgfx(NULL, VGA_GFX_SR_VALUE, 0x00);
-        vga_wgfx(NULL, VGA_GFX_SR_ENABLE, 0x00);
-        vga_wgfx(NULL, VGA_GFX_COMPARE_VALUE, 0x00);
-        vga_wgfx(NULL, VGA_GFX_DATA_ROTATE, 0x00);
-        vga_wgfx(NULL, VGA_GFX_PLANE_READ, 0x00);
-        vga_wgfx(NULL, VGA_GFX_MODE, 0x00);
-/*      vga_wgfx(NULL, VGA_GFX_MODE, 0x20); */
-/*      vga_wgfx(NULL, VGA_GFX_MODE, 0x40); */
-        vga_wgfx(NULL, VGA_GFX_MISC, 0x05);
-/*      vga_wgfx(NULL, VGA_GFX_MISC, 0x01); */
-        vga_wgfx(NULL, VGA_GFX_COMPARE_MASK, 0x0F);
-        vga_wgfx(NULL, VGA_GFX_BIT_MASK, 0xFF);
+        vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0x00);
+        vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0x00);
+        vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0x00);
+        vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0x00);
+        vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0x00);
+        vga_wgfx(regbase, VGA_GFX_MODE, 0x00);
+/*      vga_wgfx(regbase, VGA_GFX_MODE, 0x20); */
+/*      vga_wgfx(regbase, VGA_GFX_MODE, 0x40); */
+        vga_wgfx(regbase, VGA_GFX_MISC, 0x05);
+/*      vga_wgfx(regbase, VGA_GFX_MISC, 0x01); */
+        vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 0x0F);
+        vga_wgfx(regbase, VGA_GFX_BIT_MASK, 0xFF);
 }
 
 /* Set attribute controller registers to sane values */
-void svga_set_default_atc_regs(void)
+void svga_set_default_atc_regs(void __iomem *regbase)
 {
         u8 count;
 
-        vga_r(NULL, 0x3DA);
-        vga_w(NULL, VGA_ATT_W, 0x00);
+        vga_r(regbase, 0x3DA);
+        vga_w(regbase, VGA_ATT_W, 0x00);
 
         /* All standard ATC registers (AR00 - AR14) */
         for (count = 0; count <= 0xF; count ++)
-                svga_wattr(count, count);
+                svga_wattr(regbase, count, count);
 
-        svga_wattr(VGA_ATC_MODE, 0x01);
-/*      svga_wattr(VGA_ATC_MODE, 0x41); */
-        svga_wattr(VGA_ATC_OVERSCAN, 0x00);
-        svga_wattr(VGA_ATC_PLANE_ENABLE, 0x0F);
-        svga_wattr(VGA_ATC_PEL, 0x00);
-        svga_wattr(VGA_ATC_COLOR_PAGE, 0x00);
+        svga_wattr(regbase, VGA_ATC_MODE, 0x01);
+/*      svga_wattr(regbase, VGA_ATC_MODE, 0x41); */
+        svga_wattr(regbase, VGA_ATC_OVERSCAN, 0x00);
+        svga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 0x0F);
+        svga_wattr(regbase, VGA_ATC_PEL, 0x00);
+        svga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0x00);
 
-        vga_r(NULL, 0x3DA);
-        vga_w(NULL, VGA_ATT_W, 0x20);
+        vga_r(regbase, 0x3DA);
+        vga_w(regbase, VGA_ATT_W, 0x20);
 }
 
 /* Set sequencer registers to sane values */
-void svga_set_default_seq_regs(void)
+void svga_set_default_seq_regs(void __iomem *regbase)
 {
         /* Standard sequencer registers (SR01 - SR04), SR00 is not set */
-        vga_wseq(NULL, VGA_SEQ_CLOCK_MODE, VGA_SR01_CHAR_CLK_8DOTS);
-        vga_wseq(NULL, VGA_SEQ_PLANE_WRITE, VGA_SR02_ALL_PLANES);
-        vga_wseq(NULL, VGA_SEQ_CHARACTER_MAP, 0x00);
-/*      vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE | VGA_SR04_CHN_4M); */
-        vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE);
+        vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, VGA_SR01_CHAR_CLK_8DOTS);
+        vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, VGA_SR02_ALL_PLANES);
+        vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
+/*      vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE | VGA_SR04_CHN_4M); */
+        vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE);
 }
 
 /* Set CRTC registers to sane values */
-void svga_set_default_crt_regs(void)
+void svga_set_default_crt_regs(void __iomem *regbase)
 {
         /* Standard CRT registers CR03 CR08 CR09 CR14 CR17 */
-        svga_wcrt_mask(0x03, 0x80, 0x80);       /* Enable vertical retrace EVRA */
-        vga_wcrt(NULL, VGA_CRTC_PRESET_ROW, 0);
-        svga_wcrt_mask(VGA_CRTC_MAX_SCAN, 0, 0x1F);
-        vga_wcrt(NULL, VGA_CRTC_UNDERLINE, 0);
-        vga_wcrt(NULL, VGA_CRTC_MODE, 0xE3);
+        svga_wcrt_mask(regbase, 0x03, 0x80, 0x80);      /* Enable vertical retrace EVRA */
+        vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0);
+        svga_wcrt_mask(regbase, VGA_CRTC_MAX_SCAN, 0, 0x1F);
+        vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0);
+        vga_wcrt(regbase, VGA_CRTC_MODE, 0xE3);
 }
 
-void svga_set_textmode_vga_regs(void)
+void svga_set_textmode_vga_regs(void __iomem *regbase)
 {
-        /* svga_wseq_mask(0x1, 0x00, 0x01); */   /* Switch 8/9 pixel per char */
-        vga_wseq(NULL, VGA_SEQ_MEMORY_MODE,     VGA_SR04_EXT_MEM);
-        vga_wseq(NULL, VGA_SEQ_PLANE_WRITE,     0x03);
+        /* svga_wseq_mask(regbase, 0x1, 0x00, 0x01); */   /* Switch 8/9 pixel per char */
+        vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM);
+        vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x03);
 
-        vga_wcrt(NULL, VGA_CRTC_MAX_SCAN,       0x0f); /* 0x4f */
-        vga_wcrt(NULL, VGA_CRTC_UNDERLINE,      0x1f);
-        svga_wcrt_mask(VGA_CRTC_MODE,           0x23, 0x7f);
+        vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, 0x0f); /* 0x4f */
+        vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0x1f);
+        svga_wcrt_mask(regbase, VGA_CRTC_MODE, 0x23, 0x7f);
 
-        vga_wcrt(NULL, VGA_CRTC_CURSOR_START,   0x0d);
-        vga_wcrt(NULL, VGA_CRTC_CURSOR_END,     0x0e);
-        vga_wcrt(NULL, VGA_CRTC_CURSOR_HI,      0x00);
-        vga_wcrt(NULL, VGA_CRTC_CURSOR_LO,      0x00);
+        vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0x0d);
+        vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 0x0e);
+        vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0x00);
+        vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0x00);
 
-        vga_wgfx(NULL, VGA_GFX_MODE,            0x10); /* Odd/even memory mode */
-        vga_wgfx(NULL, VGA_GFX_MISC,            0x0E); /* Misc graphics register - text mode enable */
-        vga_wgfx(NULL, VGA_GFX_COMPARE_MASK,    0x00);
+        vga_wgfx(regbase, VGA_GFX_MODE, 0x10); /* Odd/even memory mode */
+        vga_wgfx(regbase, VGA_GFX_MISC, 0x0E); /* Misc graphics register - text mode enable */
+        vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 0x00);
 
-        vga_r(NULL, 0x3DA);
-        vga_w(NULL, VGA_ATT_W, 0x00);
+        vga_r(regbase, 0x3DA);
+        vga_w(regbase, VGA_ATT_W, 0x00);
 
-        svga_wattr(0x10, 0x0C);                 /* Attribute Mode Control Register - text mode, blinking and line graphics */
-        svga_wattr(0x13, 0x08);                 /* Horizontal Pixel Panning Register  */
+        svga_wattr(regbase, 0x10, 0x0C);                        /* Attribute Mode Control Register - text mode, blinking and line graphics */
+        svga_wattr(regbase, 0x13, 0x08);                        /* Horizontal Pixel Panning Register  */
 
-        vga_r(NULL, 0x3DA);
-        vga_w(NULL, VGA_ATT_W, 0x20);
+        vga_r(regbase, 0x3DA);
+        vga_w(regbase, VGA_ATT_W, 0x20);
 }
 
 #if 0
@@ -299,7 +299,7 @@ void svga_tileblit(struct fb_info *info, struct fb_tileblit *blit)
 }
 
 /* Set cursor in text (tileblit) mode */
-void svga_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
+void svga_tilecursor(void __iomem *regbase, struct fb_info *info, struct fb_tilecursor *cursor)
 {
         u8 cs = 0x0d;
         u8 ce = 0x0e;
@@ -310,7 +310,7 @@ void svga_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
         if (! cursor -> mode)
                 return;
 
-        svga_wcrt_mask(0x0A, 0x20, 0x20); /* disable cursor */
+        svga_wcrt_mask(regbase, 0x0A, 0x20, 0x20); /* disable cursor */
 
         if (cursor -> shape == FB_TILE_CURSOR_NONE)
                 return;
@@ -334,11 +334,11 @@ void svga_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
         }
 
         /* set cursor position */
-        vga_wcrt(NULL, 0x0E, pos >> 8);
-        vga_wcrt(NULL, 0x0F, pos & 0xFF);
+        vga_wcrt(regbase, 0x0E, pos >> 8);
+        vga_wcrt(regbase, 0x0F, pos & 0xFF);
 
-        vga_wcrt(NULL, 0x0B, ce); /* set cursor end */
-        vga_wcrt(NULL, 0x0A, cs); /* set cursor start and enable it */
+        vga_wcrt(regbase, 0x0B, ce); /* set cursor end */
+        vga_wcrt(regbase, 0x0A, cs); /* set cursor start and enable it */
 }
 
 int svga_get_tilemax(struct fb_info *info)
@@ -507,8 +507,9 @@ int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screenin
 }
 
 /* Set CRT timing registers */
-void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var,
-                        u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node)
+void svga_set_timings(void __iomem *regbase, const struct svga_timing_regs *tm,
+                      struct fb_var_screeninfo *var,
+                      u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node)
 {
         u8 regval;
         u32 value;
@@ -516,66 +517,66 @@ void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninf
         value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
         value = (value * hmul) / hdiv;
         pr_debug("fb%d: horizontal total      : %d\n", node, value);
-        svga_wcrt_multi(tm->h_total_regs, (value / 8) - 5);
+        svga_wcrt_multi(regbase, tm->h_total_regs, (value / 8) - 5);
 
         value = var->xres;
         value = (value * hmul) / hdiv;
         pr_debug("fb%d: horizontal display    : %d\n", node, value);
-        svga_wcrt_multi(tm->h_display_regs, (value / 8) - 1);
+        svga_wcrt_multi(regbase, tm->h_display_regs, (value / 8) - 1);
 
         value = var->xres;
         value = (value * hmul) / hdiv;
         pr_debug("fb%d: horizontal blank start: %d\n", node, value);
-        svga_wcrt_multi(tm->h_blank_start_regs, (value / 8) - 1 + hborder);
+        svga_wcrt_multi(regbase, tm->h_blank_start_regs, (value / 8) - 1 + hborder);
 
         value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
         value = (value * hmul) / hdiv;
         pr_debug("fb%d: horizontal blank end  : %d\n", node, value);
-        svga_wcrt_multi(tm->h_blank_end_regs, (value / 8) - 1 - hborder);
+        svga_wcrt_multi(regbase, tm->h_blank_end_regs, (value / 8) - 1 - hborder);
 
         value = var->xres + var->right_margin;
         value = (value * hmul) / hdiv;
         pr_debug("fb%d: horizontal sync start : %d\n", node, value);
-        svga_wcrt_multi(tm->h_sync_start_regs, (value / 8));
+        svga_wcrt_multi(regbase, tm->h_sync_start_regs, (value / 8));
 
         value = var->xres + var->right_margin + var->hsync_len;
         value = (value * hmul) / hdiv;
         pr_debug("fb%d: horizontal sync end   : %d\n", node, value);
-        svga_wcrt_multi(tm->h_sync_end_regs, (value / 8));
+        svga_wcrt_multi(regbase, tm->h_sync_end_regs, (value / 8));
 
         value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
         value = (value * vmul) / vdiv;
         pr_debug("fb%d: vertical total        : %d\n", node, value);
-        svga_wcrt_multi(tm->v_total_regs, value - 2);
+        svga_wcrt_multi(regbase, tm->v_total_regs, value - 2);
 
         value = var->yres;
         value = (value * vmul) / vdiv;
         pr_debug("fb%d: vertical display      : %d\n", node, value);
-        svga_wcrt_multi(tm->v_display_regs, value - 1);
+        svga_wcrt_multi(regbase, tm->v_display_regs, value - 1);
 
         value = var->yres;
         value = (value * vmul) / vdiv;
         pr_debug("fb%d: vertical blank start  : %d\n", node, value);
-        svga_wcrt_multi(tm->v_blank_start_regs, value);
+        svga_wcrt_multi(regbase, tm->v_blank_start_regs, value);
 
         value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
         value = (value * vmul) / vdiv;
         pr_debug("fb%d: vertical blank end    : %d\n", node, value);
-        svga_wcrt_multi(tm->v_blank_end_regs, value - 2);
+        svga_wcrt_multi(regbase, tm->v_blank_end_regs, value - 2);
 
         value = var->yres + var->lower_margin;
         value = (value * vmul) / vdiv;
         pr_debug("fb%d: vertical sync start   : %d\n", node, value);
-        svga_wcrt_multi(tm->v_sync_start_regs, value);
+        svga_wcrt_multi(regbase, tm->v_sync_start_regs, value);
 
         value = var->yres + var->lower_margin + var->vsync_len;
         value = (value * vmul) / vdiv;
         pr_debug("fb%d: vertical sync end     : %d\n", node, value);
-        svga_wcrt_multi(tm->v_sync_end_regs, value);
+        svga_wcrt_multi(regbase, tm->v_sync_end_regs, value);
 
         /* Set horizontal and vertical sync pulse polarity in misc register */
 
-        regval = vga_r(NULL, VGA_MIS_R);
+        regval = vga_r(regbase, VGA_MIS_R);
         if (var->sync & FB_SYNC_HOR_HIGH_ACT) {
                 pr_debug("fb%d: positive horizontal sync\n", node);
                 regval = regval & ~0x80;
@@ -590,7 +591,7 @@ void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninf
                 pr_debug("fb%d: negative vertical sync\n\n", node);
                 regval = regval | 0x40;
         }
-        vga_w(NULL, VGA_MIS_W, regval);
+        vga_w(regbase, VGA_MIS_W, regval);
 }
 
 
diff --git a/drivers/video/tcx.c b/drivers/video/tcx.c
index 77ad27955cf0..07c66e946634 100644
--- a/drivers/video/tcx.c
+++ b/drivers/video/tcx.c
@@ -362,8 +362,7 @@ static void tcx_unmap_regs(struct platform_device *op, struct fb_info *info,
                            info->screen_base, info->fix.smem_len);
 }
 
-static int __devinit tcx_probe(struct platform_device *op,
-                               const struct of_device_id *match)
+static int __devinit tcx_probe(struct platform_device *op)
 {
         struct device_node *dp = op->dev.of_node;
         struct fb_info *info;
@@ -481,6 +480,7 @@ out_dealloc_cmap:
 
 out_unmap_regs:
         tcx_unmap_regs(op, info, par);
+        framebuffer_release(info);
 
 out_err:
         return err;
@@ -511,7 +511,7 @@ static const struct of_device_id tcx_match[] = {
 };
 MODULE_DEVICE_TABLE(of, tcx_match);
 
-static struct of_platform_driver tcx_driver = {
+static struct platform_driver tcx_driver = {
         .driver = {
                 .name = "tcx",
                 .owner = THIS_MODULE,
@@ -526,12 +526,12 @@ static int __init tcx_init(void)
         if (fb_get_options("tcxfb", NULL))
                 return -ENODEV;
 
-        return of_register_platform_driver(&tcx_driver);
+        return platform_driver_register(&tcx_driver);
 }
 
 static void __exit tcx_exit(void)
 {
-        of_unregister_platform_driver(&tcx_driver);
+        platform_driver_unregister(&tcx_driver);
 }
 
 module_init(tcx_init);
diff --git a/drivers/video/tmiofb.c b/drivers/video/tmiofb.c
index dfef88c803d4..9710bf8caeae 100644
--- a/drivers/video/tmiofb.c
+++ b/drivers/video/tmiofb.c
@@ -250,8 +250,7 @@ static irqreturn_t tmiofb_irq(int irq, void *__info)
  */
 static int tmiofb_hw_stop(struct platform_device *dev)
 {
-        struct mfd_cell *cell = dev->dev.platform_data;
-        struct tmio_fb_data *data = cell->driver_data;
+        struct tmio_fb_data *data = mfd_get_data(dev);
         struct fb_info *info = platform_get_drvdata(dev);
         struct tmiofb_par *par = info->par;
 
@@ -268,7 +267,7 @@ static int tmiofb_hw_stop(struct platform_device *dev)
  */
 static int tmiofb_hw_init(struct platform_device *dev)
 {
-        struct mfd_cell *cell = dev->dev.platform_data;
+        const struct mfd_cell *cell = mfd_get_cell(dev);
         struct fb_info *info = platform_get_drvdata(dev);
         struct tmiofb_par *par = info->par;
         const struct resource *nlcr = &cell->resources[0];
@@ -312,8 +311,7 @@ static int tmiofb_hw_init(struct platform_device *dev)
  */
 static void tmiofb_hw_mode(struct platform_device *dev)
 {
-        struct mfd_cell *cell = dev->dev.platform_data;
-        struct tmio_fb_data *data = cell->driver_data;
+        struct tmio_fb_data *data = mfd_get_data(dev);
         struct fb_info *info = platform_get_drvdata(dev);
         struct fb_videomode *mode = info->mode;
         struct tmiofb_par *par = info->par;
@@ -559,9 +557,8 @@ static int tmiofb_ioctl(struct fb_info *fbi,
 static struct fb_videomode *
 tmiofb_find_mode(struct fb_info *info, struct fb_var_screeninfo *var)
 {
-        struct mfd_cell *cell =
-                info->device->platform_data;
-        struct tmio_fb_data *data = cell->driver_data;
+        struct tmio_fb_data *data =
+                        mfd_get_data(to_platform_device(info->device));
         struct fb_videomode *best = NULL;
         int i;
 
@@ -581,9 +578,8 @@ static int tmiofb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 {
 
         struct fb_videomode *mode;
-        struct mfd_cell *cell =
-                info->device->platform_data;
-        struct tmio_fb_data *data = cell->driver_data;
+        struct tmio_fb_data *data =
+                        mfd_get_data(to_platform_device(info->device));
 
         mode = tmiofb_find_mode(info, var);
         if (!mode || var->bits_per_pixel > 16)
@@ -683,8 +679,8 @@ static struct fb_ops tmiofb_ops = {
 
 static int __devinit tmiofb_probe(struct platform_device *dev)
 {
-        struct mfd_cell *cell = dev->dev.platform_data;
-        struct tmio_fb_data *data = cell->driver_data;
+        const struct mfd_cell *cell = mfd_get_cell(dev);
+        struct tmio_fb_data *data = mfd_get_data(dev);
         struct resource *ccr = platform_get_resource(dev, IORESOURCE_MEM, 1);
         struct resource *lcr = platform_get_resource(dev, IORESOURCE_MEM, 0);
         struct resource *vram = platform_get_resource(dev, IORESOURCE_MEM, 2);
@@ -811,7 +807,7 @@ err_ioremap_ccr:
 
 static int __devexit tmiofb_remove(struct platform_device *dev)
 {
-        struct mfd_cell *cell = dev->dev.platform_data;
+        const struct mfd_cell *cell = mfd_get_cell(dev);
         struct fb_info *info = platform_get_drvdata(dev);
         int irq = platform_get_irq(dev, 0);
         struct tmiofb_par *par;
@@ -941,7 +937,7 @@ static int tmiofb_suspend(struct platform_device *dev, pm_message_t state)
 #ifdef CONFIG_FB_TMIO_ACCELL
         struct tmiofb_par *par = info->par;
 #endif
-        struct mfd_cell *cell = dev->dev.platform_data;
+        const struct mfd_cell *cell = mfd_get_cell(dev);
         int retval = 0;
 
         console_lock();
@@ -973,7 +969,7 @@ static int tmiofb_suspend(struct platform_device *dev, pm_message_t state)
 static int tmiofb_resume(struct platform_device *dev)
 {
         struct fb_info *info = platform_get_drvdata(dev);
-        struct mfd_cell *cell = dev->dev.platform_data;
+        const struct mfd_cell *cell = mfd_get_cell(dev);
         int retval = 0;
 
         console_lock();
diff --git a/drivers/video/uvesafb.c b/drivers/video/uvesafb.c
index 52ec0959d462..7f8472cc993b 100644
--- a/drivers/video/uvesafb.c
+++ b/drivers/video/uvesafb.c
@@ -73,7 +73,7 @@ static void uvesafb_cn_callback(struct cn_msg *msg, struct netlink_skb_parms *ns
         struct uvesafb_task *utask;
         struct uvesafb_ktask *task;
 
-        if (!cap_raised(nsp->eff_cap, CAP_SYS_ADMIN))
+        if (!cap_raised(current_cap(), CAP_SYS_ADMIN))
                 return;
 
         if (msg->seq >= UVESAFB_TASKS_MAX)
@@ -1552,8 +1552,7 @@ static void __devinit uvesafb_init_mtrr(struct fb_info *info)
                         int rc;
 
                         /* Find the largest power-of-two */
-                        while (temp_size & (temp_size - 1))
-                                temp_size &= (temp_size - 1);
+                        temp_size = roundup_pow_of_two(temp_size);
 
                         /* Try and find a power of two to add */
                         do {
@@ -1566,6 +1565,28 @@ static void __devinit uvesafb_init_mtrr(struct fb_info *info)
 #endif /* CONFIG_MTRR */
 }
 
+static void __devinit uvesafb_ioremap(struct fb_info *info)
+{
+#ifdef CONFIG_X86
+        switch (mtrr) {
+        case 1: /* uncachable */
+                info->screen_base = ioremap_nocache(info->fix.smem_start, info->fix.smem_len);
+                break;
+        case 2: /* write-back */
+                info->screen_base = ioremap_cache(info->fix.smem_start, info->fix.smem_len);
+                break;
+        case 3: /* write-combining */
+                info->screen_base = ioremap_wc(info->fix.smem_start, info->fix.smem_len);
+                break;
+        case 4: /* write-through */
+        default:
+                info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
+                break;
+        }
+#else
+        info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
+#endif /* CONFIG_X86 */
+}
 
 static ssize_t uvesafb_show_vbe_ver(struct device *dev,
                 struct device_attribute *attr, char *buf)
@@ -1736,15 +1757,22 @@ static int __devinit uvesafb_probe(struct platform_device *dev)
 
         uvesafb_init_info(info, mode);
 
+        if (!request_region(0x3c0, 32, "uvesafb")) {
+                printk(KERN_ERR "uvesafb: request region 0x3c0-0x3e0 failed\n");
+                err = -EIO;
+                goto out_mode;
+        }
+
         if (!request_mem_region(info->fix.smem_start, info->fix.smem_len,
                                 "uvesafb")) {
                 printk(KERN_ERR "uvesafb: cannot reserve video memory at "
                                 "0x%lx\n", info->fix.smem_start);
                 err = -EIO;
-                goto out_mode;
+                goto out_reg;
         }
 
-        info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
+        uvesafb_init_mtrr(info);
+        uvesafb_ioremap(info);
 
         if (!info->screen_base) {
                 printk(KERN_ERR
@@ -1755,20 +1783,13 @@ static int __devinit uvesafb_probe(struct platform_device *dev)
                 goto out_mem;
         }
 
-        if (!request_region(0x3c0, 32, "uvesafb")) {
-                printk(KERN_ERR "uvesafb: request region 0x3c0-0x3e0 failed\n");
-                err = -EIO;
-                goto out_unmap;
-        }
-
-        uvesafb_init_mtrr(info);
         platform_set_drvdata(dev, info);
 
         if (register_framebuffer(info) < 0) {
                 printk(KERN_ERR
                         "uvesafb: failed to register framebuffer device\n");
                 err = -EINVAL;
-                goto out_reg;
+                goto out_unmap;
         }
 
         printk(KERN_INFO "uvesafb: framebuffer at 0x%lx, mapped to 0x%p, "
@@ -1785,12 +1806,12 @@ static int __devinit uvesafb_probe(struct platform_device *dev)
 
         return 0;
 
-out_reg:
-        release_region(0x3c0, 32);
 out_unmap:
         iounmap(info->screen_base);
 out_mem:
         release_mem_region(info->fix.smem_start, info->fix.smem_len);
+out_reg:
+        release_region(0x3c0, 32);
 out_mode:
         if (!list_empty(&info->modelist))
                 fb_destroy_modelist(&info->modelist);
diff --git a/drivers/video/vermilion/vermilion.c b/drivers/video/vermilion/vermilion.c
index 931a567f9aff..970e43d13f52 100644
--- a/drivers/video/vermilion/vermilion.c
+++ b/drivers/video/vermilion/vermilion.c
@@ -891,8 +891,7 @@ static int vmlfb_set_par(struct fb_info *info)
         int ret;
 
         mutex_lock(&vml_mutex);
-        list_del(&vinfo->head);
-        list_add(&vinfo->head, (subsys) ? &global_has_mode : &global_no_mode);
+        list_move(&vinfo->head, (subsys) ? &global_has_mode : &global_no_mode);
         ret = vmlfb_set_par_locked(vinfo);
 
         mutex_unlock(&vml_mutex);
diff --git a/drivers/video/vesafb.c b/drivers/video/vesafb.c
index 6a069d047914..a99bbe86db13 100644
--- a/drivers/video/vesafb.c
+++ b/drivers/video/vesafb.c
@@ -303,19 +303,6 @@ static int __init vesafb_probe(struct platform_device *dev)
         info->apertures->ranges[0].base = screen_info.lfb_base;
         info->apertures->ranges[0].size = size_total;
 
-        info->screen_base = ioremap(vesafb_fix.smem_start, vesafb_fix.smem_len);
-        if (!info->screen_base) {
-                printk(KERN_ERR
-                       "vesafb: abort, cannot ioremap video memory 0x%x @ 0x%lx\n",
-                        vesafb_fix.smem_len, vesafb_fix.smem_start);
-                err = -EIO;
-                goto err;
-        }
-
-        printk(KERN_INFO "vesafb: framebuffer at 0x%lx, mapped to 0x%p, "
-               "using %dk, total %dk\n",
-               vesafb_fix.smem_start, info->screen_base,
-               size_remap/1024, size_total/1024);
         printk(KERN_INFO "vesafb: mode is %dx%dx%d, linelength=%d, pages=%d\n",
                vesafb_defined.xres, vesafb_defined.yres, vesafb_defined.bits_per_pixel, vesafb_fix.line_length, screen_info.pages);
 
@@ -438,8 +425,7 @@ static int __init vesafb_probe(struct platform_device *dev)
                         int rc;
 
                         /* Find the largest power-of-two */
-                        while (temp_size & (temp_size - 1))
-                                temp_size &= (temp_size - 1);
+                        temp_size = roundup_pow_of_two(temp_size);
 
                         /* Try and find a power of two to add */
                         do {
@@ -451,6 +437,34 @@ static int __init vesafb_probe(struct platform_device *dev)
         }
 #endif
         
+        switch (mtrr) {
+        case 1: /* uncachable */
+                info->screen_base = ioremap_nocache(vesafb_fix.smem_start, vesafb_fix.smem_len);
+                break;
+        case 2: /* write-back */
+                info->screen_base = ioremap_cache(vesafb_fix.smem_start, vesafb_fix.smem_len);
+                break;
+        case 3: /* write-combining */
+                info->screen_base = ioremap_wc(vesafb_fix.smem_start, vesafb_fix.smem_len);
+                break;
+        case 4: /* write-through */
+        default:
+                info->screen_base = ioremap(vesafb_fix.smem_start, vesafb_fix.smem_len);
+                break;
+        }
+        if (!info->screen_base) {
+                printk(KERN_ERR
+                       "vesafb: abort, cannot ioremap video memory 0x%x @ 0x%lx\n",
+                        vesafb_fix.smem_len, vesafb_fix.smem_start);
+                err = -EIO;
+                goto err;
+        }
+
+        printk(KERN_INFO "vesafb: framebuffer at 0x%lx, mapped to 0x%p, "
+               "using %dk, total %dk\n",
+               vesafb_fix.smem_start, info->screen_base,
+               size_remap/1024, size_total/1024);
+
         info->fbops = &vesafb_ops;
         info->var = vesafb_defined;
         info->fix = vesafb_fix;
diff --git a/drivers/video/via/chip.h b/drivers/video/via/chip.h
index 48f1342897bd..781f3aa66b42 100644
--- a/drivers/video/via/chip.h
+++ b/drivers/video/via/chip.h
@@ -110,16 +110,13 @@
 struct tmds_chip_information {
         int tmds_chip_name;
         int tmds_chip_slave_addr;
-        int data_mode;
         int output_interface;
         int i2c_port;
-        int device_type;
 };
 
 struct lvds_chip_information {
         int lvds_chip_name;
         int lvds_chip_slave_addr;
-        int data_mode;
         int output_interface;
         int i2c_port;
 };
@@ -142,9 +139,6 @@ struct chip_information {
 
 struct crt_setting_information {
         int iga_path;
-        int h_active;
-        int v_active;
-        int bpp;
         int refresh_rate;
 };
 
@@ -162,8 +156,6 @@ struct lvds_setting_information {
         int h_active;
         int v_active;
         int bpp;
-        int refresh_rate;
-        int lcd_panel_id;
         int lcd_panel_hres;
         int lcd_panel_vres;
         int display_method;
@@ -188,7 +180,6 @@ struct GFX_DPA_SETTING {
 };
 
 struct VT1636_DPA_SETTING {
-        int PanelSizeID;
         u8 CLK_SEL_ST1;
         u8 CLK_SEL_ST2;
 };
diff --git a/drivers/video/via/dvi.c b/drivers/video/via/dvi.c
index 84e21b39dd0b..41ca198b5098 100644
--- a/drivers/video/via/dvi.c
+++ b/drivers/video/via/dvi.c
@@ -195,7 +195,9 @@ void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp,
         struct crt_mode_table *pDviTiming;
         unsigned long desirePixelClock, maxPixelClock;
         pDviTiming = mode->crtc;
-        desirePixelClock = pDviTiming->clk / 1000000;
+        desirePixelClock = pDviTiming->refresh_rate
+                * pDviTiming->crtc.hor_total * pDviTiming->crtc.ver_total
+                / 1000000;
         maxPixelClock = (unsigned long)viaparinfo->
                 tmds_setting_info->max_pixel_clock;
 
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 36d73f940d8b..5728fd76bc11 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -22,342 +22,290 @@
 #include <linux/via-core.h>
 #include "global.h"
 
-static struct pll_map pll_value[] = {
-        {25175000,
-                {99, 7, 3},
-                {85, 3, 4},     /* ignoring bit difference: 0x00008000 */
-                {141, 5, 4},
-                {141, 5, 4} },
-        {29581000,
-                {33, 4, 2},
-                {66, 2, 4},     /* ignoring bit difference: 0x00808000 */
-                {166, 5, 4},    /* ignoring bit difference: 0x00008000 */
-                {165, 5, 4} },
-        {26880000,
-                {15, 4, 1},
-                {30, 2, 3},     /* ignoring bit difference: 0x00808000 */
-                {150, 5, 4},
-                {150, 5, 4} },
-        {31500000,
-                {53, 3, 3},     /* ignoring bit difference: 0x00008000 */
-                {141, 4, 4},    /* ignoring bit difference: 0x00008000 */
-                {176, 5, 4},
-                {176, 5, 4} },
-        {31728000,
-                {31, 7, 1},
-                {177, 5, 4},    /* ignoring bit difference: 0x00008000 */
-                {177, 5, 4},
-                {142, 4, 4} },
-        {32688000,
-                {73, 4, 3},
-                {146, 4, 4},    /* ignoring bit difference: 0x00008000 */
-                {183, 5, 4},
-                {146, 4, 4} },
-        {36000000,
-                {101, 5, 3},    /* ignoring bit difference: 0x00008000 */
-                {161, 4, 4},    /* ignoring bit difference: 0x00008000 */
-                {202, 5, 4},
-                {161, 4, 4} },
-        {40000000,
-                {89, 4, 3},
-                {89, 4, 3},     /* ignoring bit difference: 0x00008000 */
-                {112, 5, 3},
-                {112, 5, 3} },
-        {41291000,
-                {23, 4, 1},
-                {69, 3, 3},     /* ignoring bit difference: 0x00008000 */
-                {115, 5, 3},
-                {115, 5, 3} },
-        {43163000,
-                {121, 5, 3},
-                {121, 5, 3},    /* ignoring bit difference: 0x00008000 */
-                {121, 5, 3},
-                {121, 5, 3} },
-        {45250000,
-                {127, 5, 3},
-                {127, 5, 3},    /* ignoring bit difference: 0x00808000 */
-                {127, 5, 3},
-                {127, 5, 3} },
-        {46000000,
-                {90, 7, 2},
-                {103, 4, 3},    /* ignoring bit difference: 0x00008000 */
-                {129, 5, 3},
-                {103, 4, 3} },
-        {46996000,
-                {105, 4, 3},    /* ignoring bit difference: 0x00008000 */
-                {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
-                {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
-                {105, 4, 3} },
-        {48000000,
-                {67, 20, 0},
-                {134, 5, 3},    /* ignoring bit difference: 0x00808000 */
-                {134, 5, 3},
-                {134, 5, 3} },
-        {48875000,
-                {99, 29, 0},
-                {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
-                {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
-                {137, 5, 3} },
-        {49500000,
-                {83, 6, 2},
-                {83, 3, 3},     /* ignoring bit difference: 0x00008000 */
-                {138, 5, 3},
-                {83, 3, 3} },
-        {52406000,
-                {117, 4, 3},
-                {117, 4, 3},    /* ignoring bit difference: 0x00008000 */
-                {117, 4, 3},
-                {88, 3, 3} },
-        {52977000,
-                {37, 5, 1},
-                {148, 5, 3},    /* ignoring bit difference: 0x00808000 */
-                {148, 5, 3},
-                {148, 5, 3} },
-        {56250000,
-                {55, 7, 1},     /* ignoring bit difference: 0x00008000 */
-                {126, 4, 3},    /* ignoring bit difference: 0x00008000 */
-                {157, 5, 3},
-                {157, 5, 3} },
-        {57275000,
-                {0, 0, 0},
-                {2, 2, 0},
-                {2, 2, 0},
-                {157, 5, 3} },  /* ignoring bit difference: 0x00808000 */
-        {60466000,
-                {76, 9, 1},
-                {169, 5, 3},    /* ignoring bit difference: 0x00808000 */
-                {169, 5, 3},    /* FIXED: old = {72, 2, 3} */
-                {169, 5, 3} },
-        {61500000,
-                {86, 20, 0},
-                {172, 5, 3},    /* ignoring bit difference: 0x00808000 */
-                {172, 5, 3},
-                {172, 5, 3} },
-        {65000000,
-                {109, 6, 2},    /* ignoring bit difference: 0x00008000 */
-                {109, 3, 3},    /* ignoring bit difference: 0x00008000 */
-                {109, 3, 3},
-                {109, 3, 3} },
-        {65178000,
-                {91, 5, 2},
-                {182, 5, 3},    /* ignoring bit difference: 0x00808000 */
-                {109, 3, 3},
-                {182, 5, 3} },
-        {66750000,
-                {75, 4, 2},
-                {150, 4, 3},    /* ignoring bit difference: 0x00808000 */
-                {150, 4, 3},
-                {112, 3, 3} },
-        {68179000,
-                {19, 4, 0},
-                {114, 3, 3},    /* ignoring bit difference: 0x00008000 */
-                {190, 5, 3},
-                {191, 5, 3} },
-        {69924000,
-                {83, 17, 0},
-                {195, 5, 3},    /* ignoring bit difference: 0x00808000 */
-                {195, 5, 3},
-                {195, 5, 3} },
-        {70159000,
-                {98, 20, 0},
-                {196, 5, 3},    /* ignoring bit difference: 0x00808000 */
-                {196, 5, 3},
-                {195, 5, 3} },
-        {72000000,
-                {121, 24, 0},
-                {161, 4, 3},    /* ignoring bit difference: 0x00808000 */
-                {161, 4, 3},
-                {161, 4, 3} },
-        {78750000,
-                {33, 3, 1},
-                {66, 3, 2},     /* ignoring bit difference: 0x00008000 */
-                {110, 5, 2},
-                {110, 5, 2} },
-        {80136000,
-                {28, 5, 0},
-                {68, 3, 2},     /* ignoring bit difference: 0x00008000 */
-                {112, 5, 2},
-                {112, 5, 2} },
-        {83375000,
-                {93, 2, 3},
-                {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
-                {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
-                {117, 5, 2} },
-        {83950000,
-                {41, 7, 0},
-                {117, 5, 2},    /* ignoring bit difference: 0x00008000 */
-                {117, 5, 2},
-                {117, 5, 2} },
-        {84750000,
-                {118, 5, 2},
-                {118, 5, 2},    /* ignoring bit difference: 0x00808000 */
-                {118, 5, 2},
-                {118, 5, 2} },
-        {85860000,
-                {84, 7, 1},
-                {120, 5, 2},    /* ignoring bit difference: 0x00808000 */
-                {120, 5, 2},
-                {118, 5, 2} },
-        {88750000,
-                {31, 5, 0},
-                {124, 5, 2},    /* ignoring bit difference: 0x00808000 */
-                {174, 7, 2},    /* ignoring bit difference: 0x00808000 */
-                {124, 5, 2} },
-        {94500000,
-                {33, 5, 0},
-                {132, 5, 2},    /* ignoring bit difference: 0x00008000 */
-                {132, 5, 2},
-                {132, 5, 2} },
-        {97750000,
-                {82, 6, 1},
-                {137, 5, 2},    /* ignoring bit difference: 0x00808000 */
-                {137, 5, 2},
-                {137, 5, 2} },
-        {101000000,
-                {127, 9, 1},
-                {141, 5, 2},    /* ignoring bit difference: 0x00808000 */
-                {141, 5, 2},
-                {141, 5, 2} },
-        {106500000,
-                {119, 4, 2},
-                {119, 4, 2},    /* ignoring bit difference: 0x00808000 */
-                {119, 4, 2},
-                {149, 5, 2} },
-        {108000000,
-                {121, 4, 2},
-                {121, 4, 2},    /* ignoring bit difference: 0x00808000 */
-                {151, 5, 2},
-                {151, 5, 2} },
-        {113309000,
-                {95, 12, 0},
-                {95, 3, 2},     /* ignoring bit difference: 0x00808000 */
-                {95, 3, 2},
-                {159, 5, 2} },
-        {118840000,
-                {83, 5, 1},
-                {166, 5, 2},    /* ignoring bit difference: 0x00808000 */
-                {166, 5, 2},
-                {166, 5, 2} },
-        {119000000,
-                {108, 13, 0},
-                {133, 4, 2},    /* ignoring bit difference: 0x00808000 */
-                {133, 4, 2},
-                {167, 5, 2} },
-        {121750000,
-                {85, 5, 1},
-                {170, 5, 2},    /* ignoring bit difference: 0x00808000 */
-                {68, 2, 2},
-                {0, 0, 0} },
-        {125104000,
-                {53, 6, 0},     /* ignoring bit difference: 0x00008000 */
-                {106, 3, 2},    /* ignoring bit difference: 0x00008000 */
-                {175, 5, 2},
-                {0, 0, 0} },
-        {135000000,
-                {94, 5, 1},
-                {28, 3, 0},     /* ignoring bit difference: 0x00804000 */
-                {151, 4, 2},
-                {189, 5, 2} },
-        {136700000,
-                {115, 12, 0},
-                {191, 5, 2},    /* ignoring bit difference: 0x00808000 */
-                {191, 5, 2},
-                {191, 5, 2} },
-        {138400000,
-                {87, 9, 0},
-                {116, 3, 2},    /* ignoring bit difference: 0x00808000 */
-                {116, 3, 2},
-                {194, 5, 2} },
-        {146760000,
-                {103, 5, 1},
-                {206, 5, 2},    /* ignoring bit difference: 0x00808000 */
-                {206, 5, 2},
-                {206, 5, 2} },
-        {153920000,
-                {86, 8, 0},
-                {86, 4, 1},     /* ignoring bit difference: 0x00808000 */
-                {86, 4, 1},
-                {86, 4, 1} },   /* FIXED: old = {84, 2, 1} */
-        {156000000,
-                {109, 5, 1},
-                {109, 5, 1},    /* ignoring bit difference: 0x00808000 */
-                {109, 5, 1},
-                {108, 5, 1} },
-        {157500000,
-                {55, 5, 0},     /* ignoring bit difference: 0x00008000 */
-                {22, 2, 0},     /* ignoring bit difference: 0x00802000 */
-                {110, 5, 1},
-                {110, 5, 1} },
-        {162000000,
-                {113, 5, 1},
-                {113, 5, 1},    /* ignoring bit difference: 0x00808000 */
-                {113, 5, 1},
-                {113, 5, 1} },
-        {187000000,
-                {118, 9, 0},
-                {131, 5, 1},    /* ignoring bit difference: 0x00808000 */
-                {131, 5, 1},
-                {131, 5, 1} },
-        {193295000,
-                {108, 8, 0},
-                {81, 3, 1},     /* ignoring bit difference: 0x00808000 */
-                {135, 5, 1},
-                {135, 5, 1} },
-        {202500000,
-                {99, 7, 0},
-                {85, 3, 1},     /* ignoring bit difference: 0x00808000 */
-                {142, 5, 1},
-                {142, 5, 1} },
-        {204000000,
-                {100, 7, 0},
-                {143, 5, 1},    /* ignoring bit difference: 0x00808000 */
-                {143, 5, 1},
-                {143, 5, 1} },
-        {218500000,
-                {92, 6, 0},
-                {153, 5, 1},    /* ignoring bit difference: 0x00808000 */
-                {153, 5, 1},
-                {153, 5, 1} },
-        {234000000,
-                {98, 6, 0},
-                {98, 3, 1},     /* ignoring bit difference: 0x00008000 */
-                {98, 3, 1},
-                {164, 5, 1} },
-        {267250000,
-                {112, 6, 0},
-                {112, 3, 1},    /* ignoring bit difference: 0x00808000 */
-                {187, 5, 1},
-                {187, 5, 1} },
-        {297500000,
-                {102, 5, 0},    /* ignoring bit difference: 0x00008000 */
-                {166, 4, 1},    /* ignoring bit difference: 0x00008000 */
-                {208, 5, 1},
-                {208, 5, 1} },
-        {74481000,
-                {26, 5, 0},
-                {125, 3, 3},    /* ignoring bit difference: 0x00808000 */
-                {208, 5, 3},
-                {209, 5, 3} },
-        {172798000,
-                {121, 5, 1},
-                {121, 5, 1},    /* ignoring bit difference: 0x00808000 */
-                {121, 5, 1},
-                {121, 5, 1} },
-        {122614000,
-                {60, 7, 0},
-                {137, 4, 2},    /* ignoring bit difference: 0x00808000 */
-                {137, 4, 2},
-                {172, 5, 2} },
-        {74270000,
-                {83, 8, 1},
-                {208, 5, 3},
-                {208, 5, 3},
-                {0, 0, 0} },
-        {148500000,
-                {83, 8, 0},
-                {208, 5, 2},
-                {166, 4, 2},
-                {208, 5, 2} }
+static struct pll_config cle266_pll_config[] = {
+        {19, 4, 0},
+        {26, 5, 0},
+        {28, 5, 0},
+        {31, 5, 0},
+        {33, 5, 0},
+        {55, 5, 0},
+        {102, 5, 0},
+        {53, 6, 0},
+        {92, 6, 0},
+        {98, 6, 0},
+        {112, 6, 0},
+        {41, 7, 0},
+        {60, 7, 0},
+        {99, 7, 0},
+        {100, 7, 0},
+        {83, 8, 0},
+        {86, 8, 0},
+        {108, 8, 0},
+        {87, 9, 0},
+        {118, 9, 0},
+        {95, 12, 0},
+        {115, 12, 0},
+        {108, 13, 0},
+        {83, 17, 0},
+        {67, 20, 0},
+        {86, 20, 0},
+        {98, 20, 0},
+        {121, 24, 0},
+        {99, 29, 0},
+        {33, 3, 1},
+        {15, 4, 1},
+        {23, 4, 1},
+        {37, 5, 1},
+        {83, 5, 1},
+        {85, 5, 1},
+        {94, 5, 1},
+        {103, 5, 1},
+        {109, 5, 1},
+        {113, 5, 1},
+        {121, 5, 1},
+        {82, 6, 1},
+        {31, 7, 1},
+        {55, 7, 1},
+        {84, 7, 1},
+        {83, 8, 1},
+        {76, 9, 1},
+        {127, 9, 1},
+        {33, 4, 2},
+        {75, 4, 2},
+        {119, 4, 2},
+        {121, 4, 2},
+        {91, 5, 2},
+        {118, 5, 2},
+        {83, 6, 2},
+        {109, 6, 2},
+        {90, 7, 2},
+        {93, 2, 3},
+        {53, 3, 3},
+        {73, 4, 3},
+        {89, 4, 3},
+        {105, 4, 3},
+        {117, 4, 3},
+        {101, 5, 3},
+        {121, 5, 3},
+        {127, 5, 3},
+        {99, 7, 3}
+};
+
+static struct pll_config k800_pll_config[] = {
+        {22, 2, 0},
+        {28, 3, 0},
+        {81, 3, 1},
+        {85, 3, 1},
+        {98, 3, 1},
+        {112, 3, 1},
+        {86, 4, 1},
+        {166, 4, 1},
+        {109, 5, 1},
+        {113, 5, 1},
+        {121, 5, 1},
+        {131, 5, 1},
+        {143, 5, 1},
+        {153, 5, 1},
+        {66, 3, 2},
+        {68, 3, 2},
+        {95, 3, 2},
+        {106, 3, 2},
+        {116, 3, 2},
+        {93, 4, 2},
+        {119, 4, 2},
+        {121, 4, 2},
+        {133, 4, 2},
+        {137, 4, 2},
+        {117, 5, 2},
+        {118, 5, 2},
+        {120, 5, 2},
+        {124, 5, 2},
+        {132, 5, 2},
+        {137, 5, 2},
+        {141, 5, 2},
+        {166, 5, 2},
+        {170, 5, 2},
+        {191, 5, 2},
+        {206, 5, 2},
+        {208, 5, 2},
+        {30, 2, 3},
+        {69, 3, 3},
+        {82, 3, 3},
+        {83, 3, 3},
+        {109, 3, 3},
+        {114, 3, 3},
+        {125, 3, 3},
+        {89, 4, 3},
+        {103, 4, 3},
+        {117, 4, 3},
+        {126, 4, 3},
+        {150, 4, 3},
+        {161, 4, 3},
+        {121, 5, 3},
+        {127, 5, 3},
+        {131, 5, 3},
+        {134, 5, 3},
+        {148, 5, 3},
+        {169, 5, 3},
+        {172, 5, 3},
+        {182, 5, 3},
+        {195, 5, 3},
+        {196, 5, 3},
+        {208, 5, 3},
+        {66, 2, 4},
+        {85, 3, 4},
+        {141, 4, 4},
+        {146, 4, 4},
+        {161, 4, 4},
+        {177, 5, 4}
+};
+
+static struct pll_config cx700_pll_config[] = {
+        {98, 3, 1},
+        {86, 4, 1},
+        {109, 5, 1},
+        {110, 5, 1},
+        {113, 5, 1},
+        {121, 5, 1},
+        {131, 5, 1},
+        {135, 5, 1},
+        {142, 5, 1},
+        {143, 5, 1},
+        {153, 5, 1},
+        {187, 5, 1},
+        {208, 5, 1},
+        {68, 2, 2},
+        {95, 3, 2},
+        {116, 3, 2},
+        {93, 4, 2},
+        {119, 4, 2},
+        {133, 4, 2},
+        {137, 4, 2},
+        {151, 4, 2},
+        {166, 4, 2},
+        {110, 5, 2},
+        {112, 5, 2},
+        {117, 5, 2},
+        {118, 5, 2},
+        {120, 5, 2},
+        {132, 5, 2},
+        {137, 5, 2},
+        {141, 5, 2},
+        {151, 5, 2},
+        {166, 5, 2},
+        {175, 5, 2},
+        {191, 5, 2},
+        {206, 5, 2},
+        {174, 7, 2},
+        {82, 3, 3},
+        {109, 3, 3},
+        {117, 4, 3},
+        {150, 4, 3},
+        {161, 4, 3},
+        {112, 5, 3},
+        {115, 5, 3},
+        {121, 5, 3},
+        {127, 5, 3},
+        {129, 5, 3},
+        {131, 5, 3},
+        {134, 5, 3},
+        {138, 5, 3},
+        {148, 5, 3},
+        {157, 5, 3},
+        {169, 5, 3},
+        {172, 5, 3},
+        {190, 5, 3},
+        {195, 5, 3},
+        {196, 5, 3},
+        {208, 5, 3},
+        {141, 5, 4},
+        {150, 5, 4},
+        {166, 5, 4},
+        {176, 5, 4},
+        {177, 5, 4},
+        {183, 5, 4},
+        {202, 5, 4}
+};
+
+static struct pll_config vx855_pll_config[] = {
+        {86, 4, 1},
+        {108, 5, 1},
+        {110, 5, 1},
+        {113, 5, 1},
+        {121, 5, 1},
+        {131, 5, 1},
+        {135, 5, 1},
+        {142, 5, 1},
+        {143, 5, 1},
+        {153, 5, 1},
+        {164, 5, 1},
+        {187, 5, 1},
+        {208, 5, 1},
+        {110, 5, 2},
+        {112, 5, 2},
+        {117, 5, 2},
+        {118, 5, 2},
+        {124, 5, 2},
+        {132, 5, 2},
+        {137, 5, 2},
+        {141, 5, 2},
+        {149, 5, 2},
+        {151, 5, 2},
+        {159, 5, 2},
+        {166, 5, 2},
+        {167, 5, 2},
+        {172, 5, 2},
+        {189, 5, 2},
+        {191, 5, 2},
+        {194, 5, 2},
+        {206, 5, 2},
+        {208, 5, 2},
+        {83, 3, 3},
+        {88, 3, 3},
+        {109, 3, 3},
+        {112, 3, 3},
+        {103, 4, 3},
+        {105, 4, 3},
+        {161, 4, 3},
+        {112, 5, 3},
+        {115, 5, 3},
+        {121, 5, 3},
+        {127, 5, 3},
+        {134, 5, 3},
+        {137, 5, 3},
+        {148, 5, 3},
+        {157, 5, 3},
+        {169, 5, 3},
+        {172, 5, 3},
+        {182, 5, 3},
+        {191, 5, 3},
+        {195, 5, 3},
+        {209, 5, 3},
+        {142, 4, 4},
+        {146, 4, 4},
+        {161, 4, 4},
+        {141, 5, 4},
+        {150, 5, 4},
+        {165, 5, 4},
+        {176, 5, 4}
+};
+
+/* according to VIA Technologies these values are based on experiment */
+static struct io_reg scaling_parameters[] = {
+        {VIACR, CR7A, 0xFF, 0x01},      /* LCD Scaling Parameter 1 */
+        {VIACR, CR7B, 0xFF, 0x02},      /* LCD Scaling Parameter 2 */
+        {VIACR, CR7C, 0xFF, 0x03},      /* LCD Scaling Parameter 3 */
+        {VIACR, CR7D, 0xFF, 0x04},      /* LCD Scaling Parameter 4 */
+        {VIACR, CR7E, 0xFF, 0x07},      /* LCD Scaling Parameter 5 */
+        {VIACR, CR7F, 0xFF, 0x0A},      /* LCD Scaling Parameter 6 */
+        {VIACR, CR80, 0xFF, 0x0D},      /* LCD Scaling Parameter 7 */
+        {VIACR, CR81, 0xFF, 0x13},      /* LCD Scaling Parameter 8 */
+        {VIACR, CR82, 0xFF, 0x16},      /* LCD Scaling Parameter 9 */
+        {VIACR, CR83, 0xFF, 0x19},      /* LCD Scaling Parameter 10 */
+        {VIACR, CR84, 0xFF, 0x1C},      /* LCD Scaling Parameter 11 */
+        {VIACR, CR85, 0xFF, 0x1D},      /* LCD Scaling Parameter 12 */
+        {VIACR, CR86, 0xFF, 0x1E},      /* LCD Scaling Parameter 13 */
+        {VIACR, CR87, 0xFF, 0x1F},      /* LCD Scaling Parameter 14 */
 };
 
 static struct fifo_depth_select display_fifo_depth_reg = {
@@ -751,7 +699,7 @@ void viafb_unlock_crt(void)
         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
 }
 
-void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
+static void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
 {
         outb(index, LUT_INDEX_WRITE);
         outb(r, LUT_DATA);
@@ -1674,43 +1622,63 @@ static u32 vx855_encode_pll(struct pll_config pll)
                 | pll.multiplier;
 }
 
-u32 viafb_get_clk_value(int clk)
+static inline u32 get_pll_internal_frequency(u32 ref_freq,
+        struct pll_config pll)
 {
-        u32 value = 0;
-        int i = 0;
+        return ref_freq / pll.divisor * pll.multiplier;
+}
 
-        while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk)
-                i++;
+static inline u32 get_pll_output_frequency(u32 ref_freq, struct pll_config pll)
+{
+        return get_pll_internal_frequency(ref_freq, pll)>>pll.rshift;
+}
 
-        if (i == NUM_TOTAL_PLL_TABLE) {
-                printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!");
-        } else {
-                switch (viaparinfo->chip_info->gfx_chip_name) {
-                case UNICHROME_CLE266:
-                case UNICHROME_K400:
-                        value = cle266_encode_pll(pll_value[i].cle266_pll);
-                        break;
+static struct pll_config get_pll_config(struct pll_config *config, int size,
+        int clk)
+{
+        struct pll_config best = config[0];
+        const u32 f0 = 14318180; /* X1 frequency */
+        int i;
 
-                case UNICHROME_K800:
-                case UNICHROME_PM800:
-                case UNICHROME_CN700:
-                        value = k800_encode_pll(pll_value[i].k800_pll);
-                        break;
+        for (i = 1; i < size; i++) {
+                if (abs(get_pll_output_frequency(f0, config[i]) - clk)
+                        < abs(get_pll_output_frequency(f0, best) - clk))
+                        best = config[i];
+        }
 
-                case UNICHROME_CX700:
-                case UNICHROME_CN750:
-                case UNICHROME_K8M890:
-                case UNICHROME_P4M890:
-                case UNICHROME_P4M900:
-                case UNICHROME_VX800:
-                        value = k800_encode_pll(pll_value[i].cx700_pll);
-                        break;
+        return best;
+}
 
-                case UNICHROME_VX855:
-                case UNICHROME_VX900:
-                        value = vx855_encode_pll(pll_value[i].vx855_pll);
-                        break;
-                }
+u32 viafb_get_clk_value(int clk)
+{
+        u32 value = 0;
+
+        switch (viaparinfo->chip_info->gfx_chip_name) {
+        case UNICHROME_CLE266:
+        case UNICHROME_K400:
+                value = cle266_encode_pll(get_pll_config(cle266_pll_config,
+                        ARRAY_SIZE(cle266_pll_config), clk));
+                break;
+        case UNICHROME_K800:
+        case UNICHROME_PM800:
+        case UNICHROME_CN700:
+                value = k800_encode_pll(get_pll_config(k800_pll_config,
+                        ARRAY_SIZE(k800_pll_config), clk));
+                break;
+        case UNICHROME_CX700:
+        case UNICHROME_CN750:
+        case UNICHROME_K8M890:
+        case UNICHROME_P4M890:
+        case UNICHROME_P4M900:
+        case UNICHROME_VX800:
+                value = k800_encode_pll(get_pll_config(cx700_pll_config,
+                        ARRAY_SIZE(cx700_pll_config), clk));
+                break;
+        case UNICHROME_VX855:
+        case UNICHROME_VX900:
+                value = vx855_encode_pll(get_pll_config(vx855_pll_config,
+                        ARRAY_SIZE(vx855_pll_config), clk));
+                break;
         }
 
         return value;
@@ -2034,7 +2002,7 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
         int i;
         int index = 0;
         int h_addr, v_addr;
-        u32 pll_D_N;
+        u32 pll_D_N, clock;
 
         for (i = 0; i < video_mode->mode_array; i++) {
                 index = i;
@@ -2087,7 +2055,9 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
 
-        pll_D_N = viafb_get_clk_value(crt_table[index].clk);
+        clock = crt_reg.hor_total * crt_reg.ver_total
+                * crt_table[index].refresh_rate;
+        pll_D_N = viafb_get_clk_value(clock);
         DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
         viafb_set_vclock(pll_D_N, set_iga);
 
@@ -2117,9 +2087,6 @@ void viafb_update_device_setting(int hres, int vres,
         int bpp, int vmode_refresh, int flag)
 {
         if (flag == 0) {
-                viaparinfo->crt_setting_info->h_active = hres;
-                viaparinfo->crt_setting_info->v_active = vres;
-                viaparinfo->crt_setting_info->bpp = bpp;
                 viaparinfo->crt_setting_info->refresh_rate =
                         vmode_refresh;
 
@@ -2129,13 +2096,9 @@ void viafb_update_device_setting(int hres, int vres,
                 viaparinfo->lvds_setting_info->h_active = hres;
                 viaparinfo->lvds_setting_info->v_active = vres;
                 viaparinfo->lvds_setting_info->bpp = bpp;
-                viaparinfo->lvds_setting_info->refresh_rate =
-                        vmode_refresh;
                 viaparinfo->lvds_setting_info2->h_active = hres;
                 viaparinfo->lvds_setting_info2->v_active = vres;
                 viaparinfo->lvds_setting_info2->bpp = bpp;
-                viaparinfo->lvds_setting_info2->refresh_rate =
-                        vmode_refresh;
         } else {
 
                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
@@ -2147,15 +2110,11 @@ void viafb_update_device_setting(int hres, int vres,
                         viaparinfo->lvds_setting_info->h_active = hres;
                         viaparinfo->lvds_setting_info->v_active = vres;
                         viaparinfo->lvds_setting_info->bpp = bpp;
-                        viaparinfo->lvds_setting_info->refresh_rate =
-                                vmode_refresh;
                 }
                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
                         viaparinfo->lvds_setting_info2->h_active = hres;
                         viaparinfo->lvds_setting_info2->v_active = vres;
                         viaparinfo->lvds_setting_info2->bpp = bpp;
-                        viaparinfo->lvds_setting_info2->refresh_rate =
-                                vmode_refresh;
                 }
         }
 }
@@ -2430,6 +2389,7 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
                 break;
         }
 
+        viafb_write_regx(scaling_parameters, ARRAY_SIZE(scaling_parameters));
         device_off();
         via_set_state(devices, VIA_STATE_OFF);
 
@@ -2608,35 +2568,43 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
 {
         int i;
+        struct crt_mode_table *best;
+        struct VideoModeTable *vmode = viafb_get_mode(hres, vres);
+
+        if (!vmode)
+                return RES_640X480_60HZ_PIXCLOCK;
 
-        for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
-                if ((hres == res_map_refresh_tbl[i].hres)
-                    && (vres == res_map_refresh_tbl[i].vres)
-                    && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
-                        return res_map_refresh_tbl[i].pixclock;
+        best = &vmode->crtc[0];
+        for (i = 1; i < vmode->mode_array; i++) {
+                if (abs(vmode->crtc[i].refresh_rate - vmode_refresh)
+                        < abs(best->refresh_rate - vmode_refresh))
+                        best = &vmode->crtc[i];
         }
-        return RES_640X480_60HZ_PIXCLOCK;
 
+        return 1000000000 / (best->crtc.hor_total * best->crtc.ver_total)
+                * 1000 / best->refresh_rate;
 }
 
 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
 {
-#define REFRESH_TOLERANCE 3
-        int i, nearest = -1, diff = REFRESH_TOLERANCE;
-        for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
-                if ((hres == res_map_refresh_tbl[i].hres)
-                    && (vres == res_map_refresh_tbl[i].vres)
-                    && (diff > (abs(long_refresh -
-                    res_map_refresh_tbl[i].vmode_refresh)))) {
-                        diff = abs(long_refresh - res_map_refresh_tbl[i].
-                                vmode_refresh);
-                        nearest = i;
-                }
+        int i;
+        struct crt_mode_table *best;
+        struct VideoModeTable *vmode = viafb_get_mode(hres, vres);
+
+        if (!vmode)
+                return 60;
+
+        best = &vmode->crtc[0];
+        for (i = 1; i < vmode->mode_array; i++) {
+                if (abs(vmode->crtc[i].refresh_rate - long_refresh)
+                        < abs(best->refresh_rate - long_refresh))
+                        best = &vmode->crtc[i];
         }
-#undef REFRESH_TOLERANCE
-        if (nearest > 0)
-                return res_map_refresh_tbl[nearest].vmode_refresh;
-        return 60;
+
+        if (abs(best->refresh_rate - long_refresh) > 3)
+                return 60;
+
+        return best->refresh_rate;
 }
 
 static void device_off(void)
diff --git a/drivers/video/via/hw.h b/drivers/video/via/hw.h
index 668d534542ef..7295263299f7 100644
--- a/drivers/video/via/hw.h
+++ b/drivers/video/via/hw.h
@@ -893,8 +893,6 @@ struct iga2_crtc_timing {
 /* VT3410 chipset*/
 #define VX900_FUNCTION3     0x3410
 
-#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
-
 struct IODATA {
         u8 Index;
         u8 Mask;
diff --git a/drivers/video/via/lcd.c b/drivers/video/via/lcd.c
index 3425c3969806..64bc7e763103 100644
--- a/drivers/video/via/lcd.c
+++ b/drivers/video/via/lcd.c
@@ -26,10 +26,12 @@
 
 /* CLE266 Software Power Sequence */
 /* {Mask}, {Data}, {Delay} */
-int PowerSequenceOn[3][3] = { {0x10, 0x08, 0x06}, {0x10, 0x08, 0x06},
-        {0x19, 0x1FE, 0x01} };
-int PowerSequenceOff[3][3] = { {0x06, 0x08, 0x10}, {0x00, 0x00, 0x00},
-        {0xD2, 0x19, 0x01} };
+static const int PowerSequenceOn[3][3] = {
+        {0x10, 0x08, 0x06}, {0x10, 0x08, 0x06}, {0x19, 0x1FE, 0x01}
+};
+static const int PowerSequenceOff[3][3] = {
+        {0x06, 0x08, 0x10}, {0x00, 0x00, 0x00}, {0xD2, 0x19, 0x01}
+};
 
 static struct _lcd_scaling_factor lcd_scaling_factor = {
         /* LCD Horizontal Scaling Factor Register */
@@ -95,8 +97,6 @@ void __devinit viafb_init_lcd_size(void)
         DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
 
         fp_id_to_vindex(viafb_lcd_panel_id);
-        viaparinfo->lvds_setting_info2->lcd_panel_id =
-                viaparinfo->lvds_setting_info->lcd_panel_id;
         viaparinfo->lvds_setting_info2->lcd_panel_hres =
                 viaparinfo->lvds_setting_info->lcd_panel_hres;
         viaparinfo->lvds_setting_info2->lcd_panel_vres =
@@ -203,176 +203,132 @@ static void __devinit fp_id_to_vindex(int panel_id)
         case 0x0:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 640;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID0_640X480;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
                 viaparinfo->lvds_setting_info->LCDDithering = 1;
                 break;
         case 0x1:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID1_800X600;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
                 viaparinfo->lvds_setting_info->LCDDithering = 1;
                 break;
         case 0x2:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID2_1024X768;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
                 viaparinfo->lvds_setting_info->LCDDithering = 1;
                 break;
         case 0x3:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID3_1280X768;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
                 viaparinfo->lvds_setting_info->LCDDithering = 1;
                 break;
         case 0x4:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID4_1280X1024;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
                 viaparinfo->lvds_setting_info->LCDDithering = 1;
                 break;
         case 0x5:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID5_1400X1050;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
                 viaparinfo->lvds_setting_info->LCDDithering = 1;
                 break;
         case 0x6:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID6_1600X1200;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
                 viaparinfo->lvds_setting_info->LCDDithering = 1;
                 break;
         case 0x8:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_IDA_800X480;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
                 viaparinfo->lvds_setting_info->LCDDithering = 1;
                 break;
         case 0x9:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID2_1024X768;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
                 viaparinfo->lvds_setting_info->LCDDithering = 1;
                 break;
         case 0xA:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID2_1024X768;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
                 viaparinfo->lvds_setting_info->LCDDithering = 0;
                 break;
         case 0xB:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID2_1024X768;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
                 viaparinfo->lvds_setting_info->LCDDithering = 0;
                 break;
         case 0xC:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID3_1280X768;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
                 viaparinfo->lvds_setting_info->LCDDithering = 0;
                 break;
         case 0xD:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID4_1280X1024;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
                 viaparinfo->lvds_setting_info->LCDDithering = 0;
                 break;
         case 0xE:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID5_1400X1050;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
                 viaparinfo->lvds_setting_info->LCDDithering = 0;
                 break;
         case 0xF:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID6_1600X1200;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
                 viaparinfo->lvds_setting_info->LCDDithering = 0;
                 break;
         case 0x10:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID7_1366X768;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
                 viaparinfo->lvds_setting_info->LCDDithering = 0;
                 break;
         case 0x11:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID8_1024X600;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
                 viaparinfo->lvds_setting_info->LCDDithering = 1;
                 break;
         case 0x12:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID3_1280X768;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
                 viaparinfo->lvds_setting_info->LCDDithering = 1;
                 break;
         case 0x13:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 800;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID9_1280X800;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
                 viaparinfo->lvds_setting_info->LCDDithering = 1;
                 break;
         case 0x14:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_IDB_1360X768;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
                 viaparinfo->lvds_setting_info->LCDDithering = 0;
                 break;
         case 0x15:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID3_1280X768;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
                 viaparinfo->lvds_setting_info->LCDDithering = 0;
                 break;
         case 0x16:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 640;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_IDC_480X640;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
                 viaparinfo->lvds_setting_info->LCDDithering = 1;
                 break;
@@ -380,16 +336,12 @@ static void __devinit fp_id_to_vindex(int panel_id)
                 /* OLPC XO-1.5 panel */
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1200;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 900;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_IDD_1200X900;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
                 viaparinfo->lvds_setting_info->LCDDithering = 0;
                 break;
         default:
                 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
                 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
-                viaparinfo->lvds_setting_info->lcd_panel_id =
-                        LCD_PANEL_ID1_800X600;
                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
                 viaparinfo->lvds_setting_info->LCDDithering = 1;
         }
@@ -610,7 +562,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
         int set_vres = plvds_setting_info->v_active;
         int panel_hres = plvds_setting_info->lcd_panel_hres;
         int panel_vres = plvds_setting_info->lcd_panel_vres;
-        u32 pll_D_N;
+        u32 pll_D_N, clock;
         struct display_timing mode_crt_reg, panel_crt_reg;
         struct crt_mode_table *panel_crt_table = NULL;
         struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
@@ -625,7 +577,9 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
         DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
         if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
                 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
-        plvds_setting_info->vclk = panel_crt_table->clk;
+        clock = panel_crt_reg.hor_total * panel_crt_reg.ver_total
+                * panel_crt_table->refresh_rate;
+        plvds_setting_info->vclk = clock;
         if (set_iga == IGA1) {
                 /* IGA1 doesn't have LCD scaling, so set it as centering. */
                 viafb_load_crtc_timing(lcd_centering_timging
@@ -660,7 +614,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
 
         fill_lcd_format();
 
-        pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);
+        pll_D_N = viafb_get_clk_value(clock);
         DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
         viafb_set_vclock(pll_D_N, set_iga);
         lcd_patch_skew(plvds_setting_info, plvds_chip_info);
@@ -1064,34 +1018,33 @@ static struct display_timing lcd_centering_timging(struct display_timing
 
 bool viafb_lcd_get_mobile_state(bool *mobile)
 {
-        unsigned char *romptr, *tableptr;
+        unsigned char __iomem *romptr, *tableptr, *biosptr;
         u8 core_base;
-        unsigned char *biosptr;
         /* Rom address */
-        u32 romaddr = 0x000C0000;
-        u16 start_pattern = 0;
+        const u32 romaddr = 0x000C0000;
+        u16 start_pattern;
 
         biosptr = ioremap(romaddr, 0x10000);
+        start_pattern = readw(biosptr);
 
-        memcpy(&start_pattern, biosptr, 2);
         /* Compare pattern */
         if (start_pattern == 0xAA55) {
                 /* Get the start of Table */
                 /* 0x1B means BIOS offset position */
                 romptr = biosptr + 0x1B;
-                tableptr = biosptr + *((u16 *) romptr);
+                tableptr = biosptr + readw(romptr);
 
                 /* Get the start of biosver structure */
                 /* 18 means BIOS version position. */
                 romptr = tableptr + 18;
-                romptr = biosptr + *((u16 *) romptr);
+                romptr = biosptr + readw(romptr);
 
                 /* The offset should be 44, but the
                    actual image is less three char. */
                 /* pRom += 44; */
                 romptr += 41;
 
-                core_base = *romptr++;
+                core_base = readb(romptr);
 
                 if (core_base & 0x8)
                         *mobile = false;
diff --git a/drivers/video/via/share.h b/drivers/video/via/share.h
index 2cbe1031b421..4b7831f0d012 100644
--- a/drivers/video/via/share.h
+++ b/drivers/video/via/share.h
@@ -627,77 +627,6 @@
 #define M2048x1536_R60_HSP      NEGATIVE
 #define M2048x1536_R60_VSP      POSITIVE
 
-/* define PLL index: */
-#define CLK_25_175M     25175000
-#define CLK_26_880M     26880000
-#define CLK_29_581M     29581000
-#define CLK_31_500M     31500000
-#define CLK_31_728M     31728000
-#define CLK_32_668M     32688000
-#define CLK_36_000M     36000000
-#define CLK_40_000M     40000000
-#define CLK_41_291M     41291000
-#define CLK_43_163M     43163000
-#define CLK_45_250M     45250000        /* 45.46MHz */
-#define CLK_46_000M     46000000
-#define CLK_46_996M     46996000
-#define CLK_48_000M     48000000
-#define CLK_48_875M     48875000
-#define CLK_49_500M     49500000
-#define CLK_52_406M     52406000
-#define CLK_52_977M     52977000
-#define CLK_56_250M     56250000
-#define CLK_57_275M     57275000
-#define CLK_60_466M     60466000
-#define CLK_61_500M     61500000
-#define CLK_65_000M     65000000
-#define CLK_65_178M     65178000
-#define CLK_66_750M     66750000        /* 67.116MHz */
-#define CLK_68_179M     68179000
-#define CLK_69_924M     69924000
-#define CLK_70_159M     70159000
-#define CLK_72_000M     72000000
-#define CLK_74_270M     74270000
-#define CLK_78_750M     78750000
-#define CLK_80_136M     80136000
-#define CLK_83_375M     83375000
-#define CLK_83_950M     83950000
-#define CLK_84_750M     84750000        /* 84.537Mhz */
-#define CLK_85_860M     85860000
-#define CLK_88_750M     88750000
-#define CLK_94_500M     94500000
-#define CLK_97_750M     97750000
-#define CLK_101_000M    101000000
-#define CLK_106_500M    106500000
-#define CLK_108_000M    108000000
-#define CLK_113_309M    113309000
-#define CLK_118_840M    118840000
-#define CLK_119_000M    119000000
-#define CLK_121_750M    121750000       /* 121.704MHz */
-#define CLK_125_104M    125104000
-#define CLK_135_000M    135000000
-#define CLK_136_700M    136700000
-#define CLK_138_400M    138400000
-#define CLK_146_760M    146760000
-#define CLK_148_500M    148500000
-
-#define CLK_153_920M    153920000
-#define CLK_156_000M    156000000
-#define CLK_157_500M    157500000
-#define CLK_162_000M    162000000
-#define CLK_187_000M    187000000
-#define CLK_193_295M    193295000
-#define CLK_202_500M    202500000
-#define CLK_204_000M    204000000
-#define CLK_218_500M    218500000
-#define CLK_234_000M    234000000
-#define CLK_267_250M    267250000
-#define CLK_297_500M    297500000
-#define CLK_74_481M     74481000
-#define CLK_172_798M    172798000
-#define CLK_122_614M    122614000
-
-
 /* Definition CRTC Timing Index */
 #define H_TOTAL_INDEX               0
 #define H_ADDR_INDEX                1
@@ -722,76 +651,7 @@
 
 /* Definition Video Mode Pixel Clock (picoseconds)
 */
-#define RES_480X640_60HZ_PIXCLOCK    39722
 #define RES_640X480_60HZ_PIXCLOCK    39722
-#define RES_640X480_75HZ_PIXCLOCK    31747
-#define RES_640X480_85HZ_PIXCLOCK    27777
-#define RES_640X480_100HZ_PIXCLOCK   23168
-#define RES_640X480_120HZ_PIXCLOCK   19081
-#define RES_720X480_60HZ_PIXCLOCK    37020
-#define RES_720X576_60HZ_PIXCLOCK    30611
-#define RES_800X600_60HZ_PIXCLOCK    25000
-#define RES_800X600_75HZ_PIXCLOCK    20203
-#define RES_800X600_85HZ_PIXCLOCK    17777
-#define RES_800X600_100HZ_PIXCLOCK   14667
-#define RES_800X600_120HZ_PIXCLOCK   11912
-#define RES_800X480_60HZ_PIXCLOCK    33805
-#define RES_848X480_60HZ_PIXCLOCK    31756
-#define RES_856X480_60HZ_PIXCLOCK    31518
-#define RES_1024X512_60HZ_PIXCLOCK   24218
-#define RES_1024X600_60HZ_PIXCLOCK   20460
-#define RES_1024X768_60HZ_PIXCLOCK   15385
-#define RES_1024X768_75HZ_PIXCLOCK   12699
-#define RES_1024X768_85HZ_PIXCLOCK   10582
-#define RES_1024X768_100HZ_PIXCLOCK  8825
-#define RES_1152X864_75HZ_PIXCLOCK   9259
-#define RES_1280X768_60HZ_PIXCLOCK   12480
-#define RES_1280X800_60HZ_PIXCLOCK   11994
-#define RES_1280X960_60HZ_PIXCLOCK   9259
-#define RES_1280X1024_60HZ_PIXCLOCK  9260
-#define RES_1280X1024_75HZ_PIXCLOCK  7408
-#define RES_1280X768_85HZ_PIXCLOCK   6349
-#define RES_1440X1050_60HZ_PIXCLOCK  7993
-#define RES_1600X1200_60HZ_PIXCLOCK  6172
-#define RES_1600X1200_75HZ_PIXCLOCK  4938
-#define RES_1280X720_60HZ_PIXCLOCK   13426
-#define RES_1200X900_60HZ_PIXCLOCK   17459
-#define RES_1920X1080_60HZ_PIXCLOCK  5787
-#define RES_1400X1050_60HZ_PIXCLOCK  8214
-#define RES_1400X1050_75HZ_PIXCLOCK  6410
-#define RES_1368X768_60HZ_PIXCLOCK   11647
-#define RES_960X600_60HZ_PIXCLOCK      22099
-#define RES_1000X600_60HZ_PIXCLOCK    20834
-#define RES_1024X576_60HZ_PIXCLOCK    21278
-#define RES_1088X612_60HZ_PIXCLOCK    18877
-#define RES_1152X720_60HZ_PIXCLOCK    14981
-#define RES_1200X720_60HZ_PIXCLOCK    14253
-#define RES_1280X600_60HZ_PIXCLOCK    16260
-#define RES_1280X720_50HZ_PIXCLOCK    16538
-#define RES_1280X768_50HZ_PIXCLOCK    15342
-#define RES_1366X768_50HZ_PIXCLOCK    14301
-#define RES_1366X768_60HZ_PIXCLOCK    11646
-#define RES_1360X768_60HZ_PIXCLOCK    11799
-#define RES_1440X900_60HZ_PIXCLOCK    9390
-#define RES_1440X900_75HZ_PIXCLOCK    7315
-#define RES_1600X900_60HZ_PIXCLOCK    8415
-#define RES_1600X1024_60HZ_PIXCLOCK   7315
-#define RES_1680X1050_60HZ_PIXCLOCK   6814
-#define RES_1680X1050_75HZ_PIXCLOCK   5348
-#define RES_1792X1344_60HZ_PIXCLOCK   4902
-#define RES_1856X1392_60HZ_PIXCLOCK   4577
-#define RES_1920X1200_60HZ_PIXCLOCK   5173
-#define RES_1920X1440_60HZ_PIXCLOCK   4274
-#define RES_1920X1440_75HZ_PIXCLOCK   3367
-#define RES_2048X1536_60HZ_PIXCLOCK   3742
-
-#define RES_1360X768_RB_60HZ_PIXCLOCK 13889
-#define RES_1400X1050_RB_60HZ_PIXCLOCK 9901
-#define RES_1440X900_RB_60HZ_PIXCLOCK   11268
-#define RES_1600X900_RB_60HZ_PIXCLOCK   10230
-#define RES_1680X1050_RB_60HZ_PIXCLOCK 8403
-#define RES_1920X1080_RB_60HZ_PIXCLOCK 7225
-#define RES_1920X1200_RB_60HZ_PIXCLOCK 6497
 
 /* LCD display method
 */
@@ -822,7 +682,6 @@ struct display_timing {
 
 struct crt_mode_table {
         int refresh_rate;
-        unsigned long clk;
         int h_sync_polarity;
         int v_sync_polarity;
         struct display_timing crtc;
diff --git a/drivers/video/via/tblDPASetting.c b/drivers/video/via/tblDPASetting.c
index 0c4c8cc712f4..73bb554e7c1e 100644
--- a/drivers/video/via/tblDPASetting.c
+++ b/drivers/video/via/tblDPASetting.c
@@ -20,17 +20,6 @@
  */
 
 #include "global.h"
-/* For VT3324: */
-struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3324[] = {
-        /* Panel ID,       CLK_SEL_ST1[09],    CLK_SEL_ST2[08] */
-        {LCD_PANEL_ID0_640X480, 0x00, 0x00},    /* For 640x480   */
-        {LCD_PANEL_ID1_800X600, 0x00, 0x00},    /* For 800x600   */
-        {LCD_PANEL_ID2_1024X768, 0x00, 0x00},   /* For 1024x768  */
-        {LCD_PANEL_ID3_1280X768, 0x00, 0x00},   /* For 1280x768  */
-        {LCD_PANEL_ID4_1280X1024, 0x00, 0x00},  /* For 1280x1024 */
-        {LCD_PANEL_ID5_1400X1050, 0x00, 0x00},  /* For 1400x1050 */
-        {LCD_PANEL_ID6_1600X1200, 0x0B, 0x03}   /* For 1600x1200 */
-};
 
 struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[] = {
 /*  ClkRange, DVP0, DVP0DataDriving,  DVP0ClockDriving, DVP1,
@@ -57,18 +46,6 @@ struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[] = {
          0x00},
 };
 
-/* For VT3327: */
-struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3327[] = {
-        /* Panel ID,       CLK_SEL_ST1[09],    CLK_SEL_ST2[08] */
-        {LCD_PANEL_ID0_640X480, 0x00, 0x00},    /* For 640x480   */
-        {LCD_PANEL_ID1_800X600, 0x00, 0x00},    /* For 800x600   */
-        {LCD_PANEL_ID2_1024X768, 0x00, 0x00},   /* For 1024x768  */
-        {LCD_PANEL_ID3_1280X768, 0x00, 0x00},   /* For 1280x768  */
-        {LCD_PANEL_ID4_1280X1024, 0x00, 0x00},  /* For 1280x1024 */
-        {LCD_PANEL_ID5_1400X1050, 0x00, 0x00},  /* For 1400x1050 */
-        {LCD_PANEL_ID6_1600X1200, 0x00, 0x00}   /* For 1600x1200 */
-};
-
 struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[] = {
 /*  ClkRange,DVP0, DVP0DataDriving,  DVP0ClockDriving, DVP1,
                                         DVP1Driving, DFPHigh,   DFPLow */
diff --git a/drivers/video/via/tblDPASetting.h b/drivers/video/via/tblDPASetting.h
index b065a83481d3..6db61519cb5d 100644
--- a/drivers/video/via/tblDPASetting.h
+++ b/drivers/video/via/tblDPASetting.h
@@ -38,9 +38,7 @@ enum DPA_RANGE {
         DPA_CLK_RANGE_150M
 };
 
-extern struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3324[7];
 extern struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[6];
-extern struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3327[7];
 extern struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[];
 extern struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3364[6];
 
diff --git a/drivers/video/via/via_i2c.c b/drivers/video/via/via_i2c.c
index 3844b558b7bd..78f1405dbab7 100644
--- a/drivers/video/via/via_i2c.c
+++ b/drivers/video/via/via_i2c.c
@@ -32,7 +32,7 @@
  */
 #define VIAFB_NUM_I2C           5
 static struct via_i2c_stuff via_i2c_par[VIAFB_NUM_I2C];
-struct viafb_dev *i2c_vdev;  /* Passed in from core */
+static struct viafb_dev *i2c_vdev;  /* Passed in from core */
 
 static void via_i2c_setscl(void *data, int state)
 {
@@ -209,7 +209,6 @@ static int create_i2c_bus(struct i2c_adapter *adapter,
         sprintf(adapter->name, "viafb i2c io_port idx 0x%02x",
                 adap_cfg->ioport_index);
         adapter->owner = THIS_MODULE;
-        adapter->id = 0x01FFFF;
         adapter->class = I2C_CLASS_DDC;
         adapter->algo_data = algo;
         if (pdev)
diff --git a/drivers/video/via/viafbdev.c b/drivers/video/via/viafbdev.c
index 4e66349e4366..f555b891cc72 100644
--- a/drivers/video/via/viafbdev.c
+++ b/drivers/video/via/viafbdev.c
@@ -43,11 +43,11 @@ static int viafb_second_size;
 static int viafb_accel = 1;
 
 /* Added for specifying active devices.*/
-char *viafb_active_dev;
+static char *viafb_active_dev;
 
 /*Added for specify lcd output port*/
-char *viafb_lcd_port = "";
-char *viafb_dvi_port = "";
+static char *viafb_lcd_port = "";
+static char *viafb_dvi_port = "";
 
 static void retrieve_device_setting(struct viafb_ioctl_setting
         *setting_info);
diff --git a/drivers/video/via/viafbdev.h b/drivers/video/via/viafbdev.h
index d66f963e930e..137996dc547e 100644
--- a/drivers/video/via/viafbdev.h
+++ b/drivers/video/via/viafbdev.h
@@ -94,9 +94,6 @@ extern int viafb_LCD_ON;
 extern int viafb_DVI_ON;
 extern int viafb_hotplug;
 
-extern int strict_strtoul(const char *cp, unsigned int base,
-        unsigned long *res);
-
 u8 viafb_gpio_i2c_read_lvds(struct lvds_setting_information
         *plvds_setting_info, struct lvds_chip_information
         *plvds_chip_info, u8 index);
diff --git a/drivers/video/via/viamode.c b/drivers/video/via/viamode.c
index 2dbad3c0f679..8c5bc41ff6a4 100644
--- a/drivers/video/via/viamode.c
+++ b/drivers/video/via/viamode.c
@@ -21,72 +21,6 @@
 
 #include <linux/via-core.h>
 #include "global.h"
-struct res_map_refresh res_map_refresh_tbl[] = {
-/*hres, vres, vclock, vmode_refresh*/
-        {480, 640, RES_480X640_60HZ_PIXCLOCK, 60},
-        {640, 480, RES_640X480_60HZ_PIXCLOCK, 60},
-        {640, 480, RES_640X480_75HZ_PIXCLOCK, 75},
-        {640, 480, RES_640X480_85HZ_PIXCLOCK, 85},
-        {640, 480, RES_640X480_100HZ_PIXCLOCK, 100},
-        {640, 480, RES_640X480_120HZ_PIXCLOCK, 120},
-        {720, 480, RES_720X480_60HZ_PIXCLOCK, 60},
-        {720, 576, RES_720X576_60HZ_PIXCLOCK, 60},
-        {800, 480, RES_800X480_60HZ_PIXCLOCK, 60},
-        {800, 600, RES_800X600_60HZ_PIXCLOCK, 60},
-        {800, 600, RES_800X600_75HZ_PIXCLOCK, 75},
-        {800, 600, RES_800X600_85HZ_PIXCLOCK, 85},
-        {800, 600, RES_800X600_100HZ_PIXCLOCK, 100},
-        {800, 600, RES_800X600_120HZ_PIXCLOCK, 120},
-        {848, 480, RES_848X480_60HZ_PIXCLOCK, 60},
-        {856, 480, RES_856X480_60HZ_PIXCLOCK, 60},
-        {1024, 512, RES_1024X512_60HZ_PIXCLOCK, 60},
-        {1024, 600, RES_1024X600_60HZ_PIXCLOCK, 60},
-        {1024, 768, RES_1024X768_60HZ_PIXCLOCK, 60},
-        {1024, 768, RES_1024X768_75HZ_PIXCLOCK, 75},
-        {1024, 768, RES_1024X768_85HZ_PIXCLOCK, 85},
-        {1024, 768, RES_1024X768_100HZ_PIXCLOCK, 100},
-/*  {1152,864, RES_1152X864_70HZ_PIXCLOCK,  70},*/
-        {1152, 864, RES_1152X864_75HZ_PIXCLOCK, 75},
-        {1280, 768, RES_1280X768_60HZ_PIXCLOCK, 60},
-        {1280, 800, RES_1280X800_60HZ_PIXCLOCK, 60},
-        {1280, 960, RES_1280X960_60HZ_PIXCLOCK, 60},
-        {1280, 1024, RES_1280X1024_60HZ_PIXCLOCK, 60},
-        {1280, 1024, RES_1280X1024_75HZ_PIXCLOCK, 75},
-        {1280, 1024, RES_1280X768_85HZ_PIXCLOCK, 85},
-        {1440, 1050, RES_1440X1050_60HZ_PIXCLOCK, 60},
-        {1600, 1200, RES_1600X1200_60HZ_PIXCLOCK, 60},
-        {1600, 1200, RES_1600X1200_75HZ_PIXCLOCK, 75},
-        {1280, 720, RES_1280X720_60HZ_PIXCLOCK, 60},
-        {1920, 1080, RES_1920X1080_60HZ_PIXCLOCK, 60},
-        {1400, 1050, RES_1400X1050_60HZ_PIXCLOCK, 60},
-        {1400, 1050, RES_1400X1050_75HZ_PIXCLOCK, 75},
-        {1368, 768, RES_1368X768_60HZ_PIXCLOCK, 60},
-        {960, 600, RES_960X600_60HZ_PIXCLOCK, 60},
-        {1000, 600, RES_1000X600_60HZ_PIXCLOCK, 60},
-        {1024, 576, RES_1024X576_60HZ_PIXCLOCK, 60},
-        {1088, 612, RES_1088X612_60HZ_PIXCLOCK, 60},
-        {1152, 720, RES_1152X720_60HZ_PIXCLOCK, 60},
-        {1200, 720, RES_1200X720_60HZ_PIXCLOCK, 60},
-        {1200, 900, RES_1200X900_60HZ_PIXCLOCK, 60},
-        {1280, 600, RES_1280X600_60HZ_PIXCLOCK, 60},
-        {1280, 720, RES_1280X720_50HZ_PIXCLOCK, 50},
-        {1280, 768, RES_1280X768_50HZ_PIXCLOCK, 50},
-        {1360, 768, RES_1360X768_60HZ_PIXCLOCK, 60},
-        {1366, 768, RES_1366X768_50HZ_PIXCLOCK, 50},
-        {1366, 768, RES_1366X768_60HZ_PIXCLOCK, 60},
-        {1440, 900, RES_1440X900_60HZ_PIXCLOCK, 60},
-        {1440, 900, RES_1440X900_75HZ_PIXCLOCK, 75},
-        {1600, 900, RES_1600X900_60HZ_PIXCLOCK, 60},
-        {1600, 1024, RES_1600X1024_60HZ_PIXCLOCK, 60},
-        {1680, 1050, RES_1680X1050_60HZ_PIXCLOCK, 60},
-        {1680, 1050, RES_1680X1050_75HZ_PIXCLOCK, 75},
-        {1792, 1344, RES_1792X1344_60HZ_PIXCLOCK, 60},
-        {1856, 1392, RES_1856X1392_60HZ_PIXCLOCK, 60},
-        {1920, 1200, RES_1920X1200_60HZ_PIXCLOCK, 60},
-        {1920, 1440, RES_1920X1440_60HZ_PIXCLOCK, 60},
-        {1920, 1440, RES_1920X1440_75HZ_PIXCLOCK, 75},
-        {2048, 1536, RES_2048X1536_60HZ_PIXCLOCK, 60}
-};
 
 struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
 {VIASR, SR15, 0x02, 0x02},
@@ -108,20 +42,6 @@ struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
 {VIACR, CR6A, 0xFF, 0x40},
 {VIACR, CR6B, 0xFF, 0x00},
 {VIACR, CR6C, 0xFF, 0x00},
-{VIACR, CR7A, 0xFF, 0x01},      /* LCD Scaling Parameter 1             */
-{VIACR, CR7B, 0xFF, 0x02},      /* LCD Scaling Parameter 2             */
-{VIACR, CR7C, 0xFF, 0x03},      /* LCD Scaling Parameter 3             */
-{VIACR, CR7D, 0xFF, 0x04},      /* LCD Scaling Parameter 4             */
-{VIACR, CR7E, 0xFF, 0x07},      /* LCD Scaling Parameter 5             */
-{VIACR, CR7F, 0xFF, 0x0A},      /* LCD Scaling Parameter 6             */
-{VIACR, CR80, 0xFF, 0x0D},      /* LCD Scaling Parameter 7             */
-{VIACR, CR81, 0xFF, 0x13},      /* LCD Scaling Parameter 8             */
-{VIACR, CR82, 0xFF, 0x16},      /* LCD Scaling Parameter 9             */
-{VIACR, CR83, 0xFF, 0x19},      /* LCD Scaling Parameter 10            */
-{VIACR, CR84, 0xFF, 0x1C},      /* LCD Scaling Parameter 11            */
-{VIACR, CR85, 0xFF, 0x1D},      /* LCD Scaling Parameter 12            */
-{VIACR, CR86, 0xFF, 0x1E},      /* LCD Scaling Parameter 13            */
-{VIACR, CR87, 0xFF, 0x1F},      /* LCD Scaling Parameter 14            */
 {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type                      */
 {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0                */
 {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1                */
@@ -172,20 +92,6 @@ struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
 {VIACR, CR78, 0xFF, 0x00},      /* LCD scaling Factor */
 {VIACR, CR79, 0xFF, 0x00},      /* LCD scaling Factor */
 {VIACR, CR9F, 0x03, 0x00},      /* LCD scaling Factor */
-{VIACR, CR7A, 0xFF, 0x01},      /* LCD Scaling Parameter 1 */
-{VIACR, CR7B, 0xFF, 0x02},      /* LCD Scaling Parameter 2 */
-{VIACR, CR7C, 0xFF, 0x03},      /* LCD Scaling Parameter 3 */
-{VIACR, CR7D, 0xFF, 0x04},      /* LCD Scaling Parameter 4 */
-{VIACR, CR7E, 0xFF, 0x07},      /* LCD Scaling Parameter 5 */
-{VIACR, CR7F, 0xFF, 0x0A},      /* LCD Scaling Parameter 6 */
-{VIACR, CR80, 0xFF, 0x0D},      /* LCD Scaling Parameter 7 */
-{VIACR, CR81, 0xFF, 0x13},      /* LCD Scaling Parameter 8 */
-{VIACR, CR82, 0xFF, 0x16},      /* LCD Scaling Parameter 9 */
-{VIACR, CR83, 0xFF, 0x19},      /* LCD Scaling Parameter 10 */
-{VIACR, CR84, 0xFF, 0x1C},      /* LCD Scaling Parameter 11 */
-{VIACR, CR85, 0xFF, 0x1D},      /* LCD Scaling Parameter 12 */
-{VIACR, CR86, 0xFF, 0x1E},      /* LCD Scaling Parameter 13 */
-{VIACR, CR87, 0xFF, 0x1F},      /* LCD Scaling Parameter 14 */
 {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type */
 {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0 */
 {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1 */
@@ -229,20 +135,6 @@ struct io_reg KM400_ModeXregs[] = {
         {VIACR, CR36, 0xFF, 0x01},      /* Power Mangement 3                  */
         {VIACR, CR68, 0xFF, 0x67},      /* Default FIFO For IGA2              */
         {VIACR, CR6A, 0x20, 0x20},      /* Extended FIFO On                   */
-        {VIACR, CR7A, 0xFF, 0x01},      /* LCD Scaling Parameter 1            */
-        {VIACR, CR7B, 0xFF, 0x02},      /* LCD Scaling Parameter 2            */
-        {VIACR, CR7C, 0xFF, 0x03},      /* LCD Scaling Parameter 3            */
-        {VIACR, CR7D, 0xFF, 0x04},      /* LCD Scaling Parameter 4            */
-        {VIACR, CR7E, 0xFF, 0x07},      /* LCD Scaling Parameter 5            */
-        {VIACR, CR7F, 0xFF, 0x0A},      /* LCD Scaling Parameter 6            */
-        {VIACR, CR80, 0xFF, 0x0D},      /* LCD Scaling Parameter 7            */
-        {VIACR, CR81, 0xFF, 0x13},      /* LCD Scaling Parameter 8            */
-        {VIACR, CR82, 0xFF, 0x16},      /* LCD Scaling Parameter 9            */
-        {VIACR, CR83, 0xFF, 0x19},      /* LCD Scaling Parameter 10           */
-        {VIACR, CR84, 0xFF, 0x1C},      /* LCD Scaling Parameter 11           */
-        {VIACR, CR85, 0xFF, 0x1D},      /* LCD Scaling Parameter 12           */
-        {VIACR, CR86, 0xFF, 0x1E},      /* LCD Scaling Parameter 13           */
-        {VIACR, CR87, 0xFF, 0x1F},      /* LCD Scaling Parameter 14           */
         {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type                     */
         {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0               */
         {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1               */
@@ -283,20 +175,6 @@ struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
 {VIACR, CR6A, 0xFF, 0x40},
 {VIACR, CR6B, 0xFF, 0x00},
 {VIACR, CR6C, 0xFF, 0x00},
-{VIACR, CR7A, 0xFF, 0x01},      /* LCD Scaling Parameter 1             */
-{VIACR, CR7B, 0xFF, 0x02},      /* LCD Scaling Parameter 2             */
-{VIACR, CR7C, 0xFF, 0x03},      /* LCD Scaling Parameter 3             */
-{VIACR, CR7D, 0xFF, 0x04},      /* LCD Scaling Parameter 4             */
-{VIACR, CR7E, 0xFF, 0x07},      /* LCD Scaling Parameter 5             */
-{VIACR, CR7F, 0xFF, 0x0A},      /* LCD Scaling Parameter 6             */
-{VIACR, CR80, 0xFF, 0x0D},      /* LCD Scaling Parameter 7             */
-{VIACR, CR81, 0xFF, 0x13},      /* LCD Scaling Parameter 8             */
-{VIACR, CR82, 0xFF, 0x16},      /* LCD Scaling Parameter 9             */
-{VIACR, CR83, 0xFF, 0x19},      /* LCD Scaling Parameter 10            */
-{VIACR, CR84, 0xFF, 0x1C},      /* LCD Scaling Parameter 11            */
-{VIACR, CR85, 0xFF, 0x1D},      /* LCD Scaling Parameter 12            */
-{VIACR, CR86, 0xFF, 0x1E},      /* LCD Scaling Parameter 13            */
-{VIACR, CR87, 0xFF, 0x1F},      /* LCD Scaling Parameter 14            */
 {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type                      */
 {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0                */
 {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1                */
@@ -342,20 +220,6 @@ struct io_reg VX855_ModeXregs[] = {
 {VIACR, CR6A, 0xFD, 0x60},
 {VIACR, CR6B, 0xFF, 0x00},
 {VIACR, CR6C, 0xFF, 0x00},
-{VIACR, CR7A, 0xFF, 0x01},          /* LCD Scaling Parameter 1             */
-{VIACR, CR7B, 0xFF, 0x02},          /* LCD Scaling Parameter 2             */
-{VIACR, CR7C, 0xFF, 0x03},          /* LCD Scaling Parameter 3             */
-{VIACR, CR7D, 0xFF, 0x04},          /* LCD Scaling Parameter 4             */
-{VIACR, CR7E, 0xFF, 0x07},          /* LCD Scaling Parameter 5             */
-{VIACR, CR7F, 0xFF, 0x0A},          /* LCD Scaling Parameter 6             */
-{VIACR, CR80, 0xFF, 0x0D},          /* LCD Scaling Parameter 7             */
-{VIACR, CR81, 0xFF, 0x13},          /* LCD Scaling Parameter 8             */
-{VIACR, CR82, 0xFF, 0x16},          /* LCD Scaling Parameter 9             */
-{VIACR, CR83, 0xFF, 0x19},          /* LCD Scaling Parameter 10            */
-{VIACR, CR84, 0xFF, 0x1C},          /* LCD Scaling Parameter 11            */
-{VIACR, CR85, 0xFF, 0x1D},          /* LCD Scaling Parameter 12            */
-{VIACR, CR86, 0xFF, 0x1E},          /* LCD Scaling Parameter 13            */
-{VIACR, CR87, 0xFF, 0x1F},          /* LCD Scaling Parameter 14            */
 {VIACR, CR88, 0xFF, 0x40},          /* LCD Panel Type                      */
 {VIACR, CR89, 0xFF, 0x00},          /* LCD Timing Control 0                */
 {VIACR, CR8A, 0xFF, 0x88},          /* LCD Timing Control 1                */
@@ -390,21 +254,6 @@ struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
 {VIAGR, GR20, 0xFF, 0x00},
 {VIAGR, GR21, 0xFF, 0x00},
 {VIAGR, GR22, 0xFF, 0x00},
-        /* LCD Parameters */
-{VIACR, CR7A, 0xFF, 0x01},      /* LCD Parameter 1 */
-{VIACR, CR7B, 0xFF, 0x02},      /* LCD Parameter 2 */
-{VIACR, CR7C, 0xFF, 0x03},      /* LCD Parameter 3 */
-{VIACR, CR7D, 0xFF, 0x04},      /* LCD Parameter 4 */
-{VIACR, CR7E, 0xFF, 0x07},      /* LCD Parameter 5 */
-{VIACR, CR7F, 0xFF, 0x0A},      /* LCD Parameter 6 */
-{VIACR, CR80, 0xFF, 0x0D},      /* LCD Parameter 7 */
-{VIACR, CR81, 0xFF, 0x13},      /* LCD Parameter 8 */
-{VIACR, CR82, 0xFF, 0x16},      /* LCD Parameter 9 */
-{VIACR, CR83, 0xFF, 0x19},      /* LCD Parameter 10 */
-{VIACR, CR84, 0xFF, 0x1C},      /* LCD Parameter 11 */
-{VIACR, CR85, 0xFF, 0x1D},      /* LCD Parameter 12 */
-{VIACR, CR86, 0xFF, 0x1E},      /* LCD Parameter 13 */
-{VIACR, CR87, 0xFF, 0x1F},      /* LCD Parameter 14 */
 
 };
 
@@ -443,328 +292,321 @@ struct VPITTable VPIT = {
 /********************/
 
 /* 480x640 */
-struct crt_mode_table CRTM480x640[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM480x640[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_25_175M, M480X640_R60_HSP, M480X640_R60_VSP,
+        {REFRESH_60, M480X640_R60_HSP, M480X640_R60_VSP,
          {624, 480, 480, 144, 504, 48, 663, 640, 640, 23, 641, 3} }     /* GTF*/
 };
 
 /* 640x480*/
-struct crt_mode_table CRTM640x480[] = {
-        /*r_rate,vclk,hsp,vsp */
+static struct crt_mode_table CRTM640x480[] = {
+        /*r_rate,hsp,vsp */
         /*HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_25_175M, M640X480_R60_HSP, M640X480_R60_VSP,
+        {REFRESH_60, M640X480_R60_HSP, M640X480_R60_VSP,
          {800, 640, 648, 144, 656, 96, 525, 480, 480, 45, 490, 2} },
-        {REFRESH_75, CLK_31_500M, M640X480_R75_HSP, M640X480_R75_VSP,
+        {REFRESH_75, M640X480_R75_HSP, M640X480_R75_VSP,
          {840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3} },
-        {REFRESH_85, CLK_36_000M, M640X480_R85_HSP, M640X480_R85_VSP,
+        {REFRESH_85, M640X480_R85_HSP, M640X480_R85_VSP,
          {832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3} },
-        {REFRESH_100, CLK_43_163M, M640X480_R100_HSP, M640X480_R100_VSP,
+        {REFRESH_100, M640X480_R100_HSP, M640X480_R100_VSP,
          {848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3} }, /*GTF*/
-            {REFRESH_120, CLK_52_406M, M640X480_R120_HSP,
-             M640X480_R120_VSP,
-             {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481,
-              3} } /*GTF*/
+        {REFRESH_120, M640X480_R120_HSP, M640X480_R120_VSP,
+         {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481, 3} } /*GTF*/
 };
 
 /*720x480 (GTF)*/
-struct crt_mode_table CRTM720x480[] = {
-        /*r_rate,vclk,hsp,vsp      */
+static struct crt_mode_table CRTM720x480[] = {
+        /*r_rate,hsp,vsp      */
         /*HT, HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_26_880M, M720X480_R60_HSP, M720X480_R60_VSP,
+        {REFRESH_60, M720X480_R60_HSP, M720X480_R60_VSP,
          {896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3} }
 
 };
 
 /*720x576 (GTF)*/
-struct crt_mode_table CRTM720x576[] = {
-        /*r_rate,vclk,hsp,vsp */
+static struct crt_mode_table CRTM720x576[] = {
+        /*r_rate,hsp,vsp */
         /*HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_32_668M, M720X576_R60_HSP, M720X576_R60_VSP,
+        {REFRESH_60, M720X576_R60_HSP, M720X576_R60_VSP,
          {912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3} }
 };
 
 /* 800x480 (CVT) */
-struct crt_mode_table CRTM800x480[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM800x480[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_29_581M, M800X480_R60_HSP, M800X480_R60_VSP,
+        {REFRESH_60, M800X480_R60_HSP, M800X480_R60_VSP,
          {992, 800, 800, 192, 824, 72, 500, 480, 480, 20, 483, 7} }
 };
 
 /* 800x600*/
-struct crt_mode_table CRTM800x600[] = {
-        /*r_rate,vclk,hsp,vsp     */
+static struct crt_mode_table CRTM800x600[] = {
+        /*r_rate,hsp,vsp     */
         /*HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_40_000M, M800X600_R60_HSP, M800X600_R60_VSP,
+        {REFRESH_60, M800X600_R60_HSP, M800X600_R60_VSP,
          {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4} },
-        {REFRESH_75, CLK_49_500M, M800X600_R75_HSP, M800X600_R75_VSP,
+        {REFRESH_75, M800X600_R75_HSP, M800X600_R75_VSP,
          {1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3} },
-        {REFRESH_85, CLK_56_250M, M800X600_R85_HSP, M800X600_R85_VSP,
+        {REFRESH_85, M800X600_R85_HSP, M800X600_R85_VSP,
          {1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3} },
-        {REFRESH_100, CLK_68_179M, M800X600_R100_HSP, M800X600_R100_VSP,
+        {REFRESH_100, M800X600_R100_HSP, M800X600_R100_VSP,
          {1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3} },
-        {REFRESH_120, CLK_83_950M, M800X600_R120_HSP,
-                  M800X600_R120_VSP,
-                  {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601,
-                   3} }
+        {REFRESH_120, M800X600_R120_HSP, M800X600_R120_VSP,
+         {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601, 3} }
 };
 
 /* 848x480 (CVT) */
-struct crt_mode_table CRTM848x480[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM848x480[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_31_500M, M848X480_R60_HSP, M848X480_R60_VSP,
+        {REFRESH_60, M848X480_R60_HSP, M848X480_R60_VSP,
          {1056, 848, 848, 208, 872, 80, 500, 480, 480, 20, 483, 5} }
 };
 
 /*856x480 (GTF) convert to 852x480*/
-struct crt_mode_table CRTM852x480[] = {
-        /*r_rate,vclk,hsp,vsp     */
+static struct crt_mode_table CRTM852x480[] = {
+        /*r_rate,hsp,vsp     */
         /*HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_31_728M, M852X480_R60_HSP, M852X480_R60_VSP,
+        {REFRESH_60, M852X480_R60_HSP, M852X480_R60_VSP,
         {1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3} }
 };
 
 /*1024x512 (GTF)*/
-struct crt_mode_table CRTM1024x512[] = {
-        /*r_rate,vclk,hsp,vsp     */
+static struct crt_mode_table CRTM1024x512[] = {
+        /*r_rate,hsp,vsp     */
         /*HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_41_291M, M1024X512_R60_HSP, M1024X512_R60_VSP,
+        {REFRESH_60, M1024X512_R60_HSP, M1024X512_R60_VSP,
          {1296, 1024, 1024, 272, 1056, 104, 531, 512, 512, 19, 513, 3} }
 
 };
 
 /* 1024x600*/
-struct crt_mode_table CRTM1024x600[] = {
-        /*r_rate,vclk,hsp,vsp */
+static struct crt_mode_table CRTM1024x600[] = {
+        /*r_rate,hsp,vsp */
         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_48_875M, M1024X600_R60_HSP, M1024X600_R60_VSP,
+        {REFRESH_60, M1024X600_R60_HSP, M1024X600_R60_VSP,
          {1312, 1024, 1024, 288, 1064, 104, 622, 600, 600, 22, 601, 3} },
 };
 
 /* 1024x768*/
-struct crt_mode_table CRTM1024x768[] = {
-        /*r_rate,vclk,hsp,vsp */
+static struct crt_mode_table CRTM1024x768[] = {
+        /*r_rate,hsp,vsp */
         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_65_000M, M1024X768_R60_HSP, M1024X768_R60_VSP,
+        {REFRESH_60, M1024X768_R60_HSP, M1024X768_R60_VSP,
         {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6} },
-        {REFRESH_75, CLK_78_750M, M1024X768_R75_HSP, M1024X768_R75_VSP,
+        {REFRESH_75, M1024X768_R75_HSP, M1024X768_R75_VSP,
         {1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3} },
-        {REFRESH_85, CLK_94_500M, M1024X768_R85_HSP, M1024X768_R85_VSP,
+        {REFRESH_85, M1024X768_R85_HSP, M1024X768_R85_VSP,
         {1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3} },
-        {REFRESH_100, CLK_113_309M, M1024X768_R100_HSP, M1024X768_R100_VSP,
+        {REFRESH_100, M1024X768_R100_HSP, M1024X768_R100_VSP,
         {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3} }
 };
 
 /* 1152x864*/
-struct crt_mode_table CRTM1152x864[] = {
-        /*r_rate,vclk,hsp,vsp      */
+static struct crt_mode_table CRTM1152x864[] = {
+        /*r_rate,hsp,vsp      */
         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_75, CLK_108_000M, M1152X864_R75_HSP, M1152X864_R75_VSP,
+        {REFRESH_75, M1152X864_R75_HSP, M1152X864_R75_VSP,
          {1600, 1152, 1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3} }
 
 };
 
 /* 1280x720 (HDMI 720P)*/
-struct crt_mode_table CRTM1280x720[] = {
-        /*r_rate,vclk,hsp,vsp */
+static struct crt_mode_table CRTM1280x720[] = {
+        /*r_rate,hsp,vsp */
         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE      */
-        {REFRESH_60, CLK_74_481M, M1280X720_R60_HSP, M1280X720_R60_VSP,
+        {REFRESH_60, M1280X720_R60_HSP, M1280X720_R60_VSP,
          {1648, 1280, 1280, 368, 1392, 40, 750, 720, 720, 30, 725, 5} },
-        {REFRESH_50, CLK_60_466M, M1280X720_R50_HSP, M1280X720_R50_VSP,
+        {REFRESH_50, M1280X720_R50_HSP, M1280X720_R50_VSP,
          {1632, 1280, 1280, 352, 1328, 128, 741, 720, 720, 21, 721, 3} }
 };
 
 /*1280x768 (GTF)*/
-struct crt_mode_table CRTM1280x768[] = {
-        /*r_rate,vclk,hsp,vsp     */
+static struct crt_mode_table CRTM1280x768[] = {
+        /*r_rate,hsp,vsp     */
         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_80_136M, M1280X768_R60_HSP, M1280X768_R60_VSP,
+        {REFRESH_60, M1280X768_R60_HSP, M1280X768_R60_VSP,
          {1680, 1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3} },
-        {REFRESH_50, CLK_65_178M, M1280X768_R50_HSP, M1280X768_R50_VSP,
+        {REFRESH_50, M1280X768_R50_HSP, M1280X768_R50_VSP,
          {1648, 1280, 1280, 368, 1336, 128, 791, 768, 768, 23, 769, 3} }
 };
 
 /* 1280x800 (CVT) */
-struct crt_mode_table CRTM1280x800[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1280x800[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_83_375M, M1280X800_R60_HSP, M1280X800_R60_VSP,
+        {REFRESH_60, M1280X800_R60_HSP, M1280X800_R60_VSP,
          {1680, 1280, 1280, 400, 1352, 128, 831, 800, 800, 31, 803, 6} }
 };
 
 /*1280x960*/
-struct crt_mode_table CRTM1280x960[] = {
-        /*r_rate,vclk,hsp,vsp */
+static struct crt_mode_table CRTM1280x960[] = {
+        /*r_rate,hsp,vsp */
         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_108_000M, M1280X960_R60_HSP, M1280X960_R60_VSP,
+        {REFRESH_60, M1280X960_R60_HSP, M1280X960_R60_VSP,
          {1800, 1280, 1280, 520, 1376, 112, 1000, 960, 960, 40, 961, 3} }
 };
 
 /* 1280x1024*/
-struct crt_mode_table CRTM1280x1024[] = {
-        /*r_rate,vclk,,hsp,vsp */
+static struct crt_mode_table CRTM1280x1024[] = {
+        /*r_rate,hsp,vsp */
         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_108_000M, M1280X1024_R60_HSP, M1280X1024_R60_VSP,
+        {REFRESH_60, M1280X1024_R60_HSP, M1280X1024_R60_VSP,
          {1688, 1280, 1280, 408, 1328, 112, 1066, 1024, 1024, 42, 1025,
           3} },
-        {REFRESH_75, CLK_135_000M, M1280X1024_R75_HSP, M1280X1024_R75_VSP,
+        {REFRESH_75, M1280X1024_R75_HSP, M1280X1024_R75_VSP,
          {1688, 1280, 1280, 408, 1296, 144, 1066, 1024, 1024, 42, 1025,
           3} },
-        {REFRESH_85, CLK_157_500M, M1280X1024_R85_HSP, M1280X1024_R85_VSP,
+        {REFRESH_85, M1280X1024_R85_HSP, M1280X1024_R85_VSP,
          {1728, 1280, 1280, 448, 1344, 160, 1072, 1024, 1024, 48, 1025, 3} }
 };
 
 /* 1368x768 (GTF) */
-struct crt_mode_table CRTM1368x768[] = {
-        /* r_rate,  vclk, hsp, vsp */
+static struct crt_mode_table CRTM1368x768[] = {
+        /* r_rate,  hsp, vsp */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP,
+        {REFRESH_60, M1368X768_R60_HSP, M1368X768_R60_VSP,
          {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} }
 };
 
 /*1440x1050 (GTF)*/
-struct crt_mode_table CRTM1440x1050[] = {
-        /*r_rate,vclk,hsp,vsp      */
+static struct crt_mode_table CRTM1440x1050[] = {
+        /*r_rate,hsp,vsp      */
         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_125_104M, M1440X1050_R60_HSP, M1440X1050_R60_VSP,
+        {REFRESH_60, M1440X1050_R60_HSP, M1440X1050_R60_VSP,
          {1936, 1440, 1440, 496, 1536, 152, 1077, 1040, 1040, 37, 1041, 3} }
 };
 
 /* 1600x1200*/
-struct crt_mode_table CRTM1600x1200[] = {
-        /*r_rate,vclk,hsp,vsp */
+static struct crt_mode_table CRTM1600x1200[] = {
+        /*r_rate,hsp,vsp */
         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_162_000M, M1600X1200_R60_HSP, M1600X1200_R60_VSP,
+        {REFRESH_60, M1600X1200_R60_HSP, M1600X1200_R60_VSP,
          {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201,
           3} },
-        {REFRESH_75, CLK_202_500M, M1600X1200_R75_HSP, M1600X1200_R75_VSP,
+        {REFRESH_75, M1600X1200_R75_HSP, M1600X1200_R75_VSP,
          {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 3} }
 
 };
 
 /* 1680x1050 (CVT) */
-struct crt_mode_table CRTM1680x1050[] = {
-        /* r_rate,          vclk,              hsp,             vsp  */
+static struct crt_mode_table CRTM1680x1050[] = {
+        /* r_rate,              hsp,             vsp  */
         /* HT,  HA,  HBS, HBE, HSS, HSE,    VT,  VA,  VBS, VBE,  VSS, VSE */
-        {REFRESH_60, CLK_146_760M, M1680x1050_R60_HSP, M1680x1050_R60_VSP,
+        {REFRESH_60, M1680x1050_R60_HSP, M1680x1050_R60_VSP,
          {2240, 1680, 1680, 560, 1784, 176, 1089, 1050, 1050, 39, 1053,
           6} },
-        {REFRESH_75, CLK_187_000M, M1680x1050_R75_HSP, M1680x1050_R75_VSP,
+        {REFRESH_75, M1680x1050_R75_HSP, M1680x1050_R75_VSP,
          {2272, 1680, 1680, 592, 1800, 176, 1099, 1050, 1050, 49, 1053, 6} }
 };
 
 /* 1680x1050 (CVT Reduce Blanking) */
-struct crt_mode_table CRTM1680x1050_RB[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1680x1050_RB[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE,    VT,  VA,  VBS, VBE,  VSS, VSE */
-        {REFRESH_60, CLK_119_000M, M1680x1050_RB_R60_HSP,
-         M1680x1050_RB_R60_VSP,
+        {REFRESH_60, M1680x1050_RB_R60_HSP, M1680x1050_RB_R60_VSP,
          {1840, 1680, 1680, 160, 1728, 32, 1080, 1050, 1050, 30, 1053, 6} }
 };
 
 /* 1920x1080 (CVT)*/
-struct crt_mode_table CRTM1920x1080[] = {
-        /*r_rate,vclk,hsp,vsp */
+static struct crt_mode_table CRTM1920x1080[] = {
+        /*r_rate,hsp,vsp */
         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_172_798M, M1920X1080_R60_HSP, M1920X1080_R60_VSP,
+        {REFRESH_60, M1920X1080_R60_HSP, M1920X1080_R60_VSP,
          {2576, 1920, 1920, 656, 2048, 200, 1120, 1080, 1080, 40, 1083, 5} }
 };
 
 /* 1920x1080 (CVT with Reduce Blanking) */
-struct crt_mode_table CRTM1920x1080_RB[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1920x1080_RB[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_138_400M, M1920X1080_RB_R60_HSP,
-         M1920X1080_RB_R60_VSP,
+        {REFRESH_60, M1920X1080_RB_R60_HSP, M1920X1080_RB_R60_VSP,
          {2080, 1920, 1920, 160, 1968, 32, 1111, 1080, 1080, 31, 1083, 5} }
 };
 
 /* 1920x1440*/
-struct crt_mode_table CRTM1920x1440[] = {
-        /*r_rate,vclk,hsp,vsp */
+static struct crt_mode_table CRTM1920x1440[] = {
+        /*r_rate,hsp,vsp */
         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_234_000M, M1920X1440_R60_HSP, M1920X1440_R60_VSP,
+        {REFRESH_60, M1920X1440_R60_HSP, M1920X1440_R60_VSP,
          {2600, 1920, 1920, 680, 2048, 208, 1500, 1440, 1440, 60, 1441,
           3} },
-        {REFRESH_75, CLK_297_500M, M1920X1440_R75_HSP, M1920X1440_R75_VSP,
+        {REFRESH_75, M1920X1440_R75_HSP, M1920X1440_R75_VSP,
          {2640, 1920, 1920, 720, 2064, 224, 1500, 1440, 1440, 60, 1441, 3} }
 };
 
 /* 1400x1050 (CVT) */
-struct crt_mode_table CRTM1400x1050[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1400x1050[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
-        {REFRESH_60, CLK_121_750M, M1400X1050_R60_HSP, M1400X1050_R60_VSP,
+        {REFRESH_60, M1400X1050_R60_HSP, M1400X1050_R60_VSP,
          {1864, 1400, 1400, 464, 1488, 144, 1089, 1050, 1050, 39, 1053,
           4} },
-        {REFRESH_75, CLK_156_000M, M1400X1050_R75_HSP, M1400X1050_R75_VSP,
+        {REFRESH_75, M1400X1050_R75_HSP, M1400X1050_R75_VSP,
          {1896, 1400, 1400, 496, 1504, 144, 1099, 1050, 1050, 49, 1053, 4} }
 };
 
 /* 1400x1050 (CVT Reduce Blanking) */
-struct crt_mode_table CRTM1400x1050_RB[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1400x1050_RB[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
-        {REFRESH_60, CLK_101_000M, M1400X1050_RB_R60_HSP,
-         M1400X1050_RB_R60_VSP,
+        {REFRESH_60, M1400X1050_RB_R60_HSP, M1400X1050_RB_R60_VSP,
          {1560, 1400, 1400, 160, 1448, 32, 1080, 1050, 1050, 30, 1053, 4} }
 };
 
 /* 960x600 (CVT) */
-struct crt_mode_table CRTM960x600[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM960x600[] = {
+        /* r_rate,          hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_45_250M, M960X600_R60_HSP, M960X600_R60_VSP,
+        {REFRESH_60, M960X600_R60_HSP, M960X600_R60_VSP,
          {1216, 960, 960, 256, 992, 96, 624, 600, 600, 24, 603, 6} }
 };
 
 /* 1000x600 (GTF) */
-struct crt_mode_table CRTM1000x600[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1000x600[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_48_000M, M1000X600_R60_HSP, M1000X600_R60_VSP,
+        {REFRESH_60, M1000X600_R60_HSP, M1000X600_R60_VSP,
          {1288, 1000, 1000, 288, 1040, 104, 622, 600, 600, 22, 601, 3} }
 };
 
 /* 1024x576 (GTF) */
-struct crt_mode_table CRTM1024x576[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1024x576[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_46_996M, M1024X576_R60_HSP, M1024X576_R60_VSP,
+        {REFRESH_60, M1024X576_R60_HSP, M1024X576_R60_VSP,
          {1312, 1024, 1024, 288, 1064, 104, 597, 576, 576, 21, 577, 3} }
 };
 
 /* 1088x612 (CVT) */
-struct crt_mode_table CRTM1088x612[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1088x612[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_52_977M, M1088X612_R60_HSP, M1088X612_R60_VSP,
+        {REFRESH_60, M1088X612_R60_HSP, M1088X612_R60_VSP,
          {1392, 1088, 1088, 304, 1136, 104, 636, 612, 612, 24, 615, 5} }
 };
 
 /* 1152x720 (CVT) */
-struct crt_mode_table CRTM1152x720[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1152x720[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_66_750M, M1152X720_R60_HSP, M1152X720_R60_VSP,
+        {REFRESH_60, M1152X720_R60_HSP, M1152X720_R60_VSP,
          {1488, 1152, 1152, 336, 1208, 112, 748, 720, 720, 28, 723, 6} }
 };
 
 /* 1200x720 (GTF) */
-struct crt_mode_table CRTM1200x720[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1200x720[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_70_159M, M1200X720_R60_HSP, M1200X720_R60_VSP,
+        {REFRESH_60, M1200X720_R60_HSP, M1200X720_R60_VSP,
          {1568, 1200, 1200, 368, 1256, 128, 746, 720, 720, 26, 721, 3} }
 };
 
 /* 1200x900 (DCON) */
-struct crt_mode_table DCON1200x900[] = {
-        /* r_rate,          vclk,               hsp,               vsp   */
-        {REFRESH_60, CLK_57_275M, M1200X900_R60_HSP, M1200X900_R60_VSP,
+static struct crt_mode_table DCON1200x900[] = {
+        /* r_rate,               hsp,               vsp   */
+        {REFRESH_60, M1200X900_R60_HSP, M1200X900_R60_VSP,
         /* The correct htotal is 1240, but this doesn't raster on VX855. */
         /* Via suggested changing to a multiple of 16, hence 1264.       */
         /*  HT,   HA,  HBS, HBE,  HSS, HSE,  VT,  VA, VBS, VBE, VSS, VSE */
@@ -772,126 +614,122 @@ struct crt_mode_table DCON1200x900[] = {
 };
 
 /* 1280x600 (GTF) */
-struct crt_mode_table CRTM1280x600[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1280x600[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE,  HSS, HSE, VT,  VA,  VBS, VBE,  VSS, VSE */
-        {REFRESH_60, CLK_61_500M, M1280x600_R60_HSP, M1280x600_R60_VSP,
+        {REFRESH_60, M1280x600_R60_HSP, M1280x600_R60_VSP,
          {1648, 1280, 1280, 368, 1336, 128, 622, 600, 600, 22, 601, 3} }
 };
 
 /* 1360x768 (CVT) */
-struct crt_mode_table CRTM1360x768[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1360x768[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_84_750M, M1360X768_R60_HSP, M1360X768_R60_VSP,
+        {REFRESH_60, M1360X768_R60_HSP, M1360X768_R60_VSP,
          {1776, 1360, 1360, 416, 1432, 136, 798, 768, 768, 30, 771, 5} }
 };
 
 /* 1360x768 (CVT Reduce Blanking) */
-struct crt_mode_table CRTM1360x768_RB[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1360x768_RB[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_72_000M, M1360X768_RB_R60_HSP,
-         M1360X768_RB_R60_VSP,
+        {REFRESH_60, M1360X768_RB_R60_HSP, M1360X768_RB_R60_VSP,
          {1520, 1360, 1360, 160, 1408, 32, 790, 768, 768, 22, 771, 5} }
 };
 
 /* 1366x768 (GTF) */
-struct crt_mode_table CRTM1366x768[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1366x768[] = {
+        /* r_rate,          hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP,
+        {REFRESH_60, M1368X768_R60_HSP, M1368X768_R60_VSP,
          {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} },
-        {REFRESH_50, CLK_69_924M, M1368X768_R50_HSP, M1368X768_R50_VSP,
+        {REFRESH_50, M1368X768_R50_HSP, M1368X768_R50_VSP,
          {1768, 1368, 1368, 400, 1424, 144, 791, 768, 768, 23, 769, 3} }
 };
 
 /* 1440x900 (CVT) */
-struct crt_mode_table CRTM1440x900[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1440x900[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_106_500M, M1440X900_R60_HSP, M1440X900_R60_VSP,
+        {REFRESH_60, M1440X900_R60_HSP, M1440X900_R60_VSP,
          {1904, 1440, 1440, 464, 1520, 152, 934, 900, 900, 34, 903, 6} },
-        {REFRESH_75, CLK_136_700M, M1440X900_R75_HSP, M1440X900_R75_VSP,
+        {REFRESH_75, M1440X900_R75_HSP, M1440X900_R75_VSP,
          {1936, 1440, 1440, 496, 1536, 152, 942, 900, 900, 42, 903, 6} }
 };
 
 /* 1440x900 (CVT Reduce Blanking) */
-struct crt_mode_table CRTM1440x900_RB[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1440x900_RB[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_88_750M, M1440X900_RB_R60_HSP,
-         M1440X900_RB_R60_VSP,
+        {REFRESH_60, M1440X900_RB_R60_HSP, M1440X900_RB_R60_VSP,
          {1600, 1440, 1440, 160, 1488, 32, 926, 900, 900, 26, 903, 6} }
 };
 
 /* 1600x900 (CVT) */
-struct crt_mode_table CRTM1600x900[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1600x900[] = {
+        /* r_rate,          hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_118_840M, M1600X900_R60_HSP, M1600X900_R60_VSP,
+        {REFRESH_60, M1600X900_R60_HSP, M1600X900_R60_VSP,
          {2112, 1600, 1600, 512, 1688, 168, 934, 900, 900, 34, 903, 5} }
 };
 
 /* 1600x900 (CVT Reduce Blanking) */
-struct crt_mode_table CRTM1600x900_RB[] = {
-        /* r_rate,        vclk,           hsp,        vsp   */
+static struct crt_mode_table CRTM1600x900_RB[] = {
+        /* r_rate,           hsp,        vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_97_750M, M1600X900_RB_R60_HSP,
-         M1600X900_RB_R60_VSP,
+        {REFRESH_60, M1600X900_RB_R60_HSP, M1600X900_RB_R60_VSP,
          {1760, 1600, 1600, 160, 1648, 32, 926, 900, 900, 26, 903, 5} }
 };
 
 /* 1600x1024 (GTF) */
-struct crt_mode_table CRTM1600x1024[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1600x1024[] = {
+        /* r_rate,          hsp,             vsp   */
         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
-        {REFRESH_60, CLK_136_700M, M1600X1024_R60_HSP, M1600X1024_R60_VSP,
+        {REFRESH_60, M1600X1024_R60_HSP, M1600X1024_R60_VSP,
          {2144, 1600, 1600, 544, 1704, 168, 1060, 1024, 1024, 36, 1025, 3} }
 };
 
 /* 1792x1344 (DMT) */
-struct crt_mode_table CRTM1792x1344[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1792x1344[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
-        {REFRESH_60, CLK_204_000M, M1792x1344_R60_HSP, M1792x1344_R60_VSP,
+        {REFRESH_60, M1792x1344_R60_HSP, M1792x1344_R60_VSP,
          {2448, 1792, 1792, 656, 1920, 200, 1394, 1344, 1344, 50, 1345, 3} }
 };
 
 /* 1856x1392 (DMT) */
-struct crt_mode_table CRTM1856x1392[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1856x1392[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
-        {REFRESH_60, CLK_218_500M, M1856x1392_R60_HSP, M1856x1392_R60_VSP,
+        {REFRESH_60, M1856x1392_R60_HSP, M1856x1392_R60_VSP,
          {2528, 1856, 1856, 672, 1952, 224, 1439, 1392, 1392, 47, 1393, 3} }
 };
 
 /* 1920x1200 (CVT) */
-struct crt_mode_table CRTM1920x1200[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1920x1200[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_193_295M, M1920X1200_R60_HSP, M1920X1200_R60_VSP,
+        {REFRESH_60, M1920X1200_R60_HSP, M1920X1200_R60_VSP,
          {2592, 1920, 1920, 672, 2056, 200, 1245, 1200, 1200, 45, 1203, 6} }
 };
 
 /* 1920x1200 (CVT with Reduce Blanking) */
-struct crt_mode_table CRTM1920x1200_RB[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM1920x1200_RB[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
-        {REFRESH_60, CLK_153_920M, M1920X1200_RB_R60_HSP,
-         M1920X1200_RB_R60_VSP,
+        {REFRESH_60, M1920X1200_RB_R60_HSP, M1920X1200_RB_R60_VSP,
          {2080, 1920, 1920, 160, 1968, 32, 1235, 1200, 1200, 35, 1203, 6} }
 };
 
 /* 2048x1536 (CVT) */
-struct crt_mode_table CRTM2048x1536[] = {
-        /* r_rate,          vclk,              hsp,             vsp   */
+static struct crt_mode_table CRTM2048x1536[] = {
+        /* r_rate,              hsp,             vsp   */
         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
-        {REFRESH_60, CLK_267_250M, M2048x1536_R60_HSP, M2048x1536_R60_VSP,
+        {REFRESH_60, M2048x1536_R60_HSP, M2048x1536_R60_VSP,
          {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} }
 };
 
-struct VideoModeTable viafb_modes[] = {
+static struct VideoModeTable viafb_modes[] = {
         /* Display : 480x640 (GTF) */
         {CRTM480x640, ARRAY_SIZE(CRTM480x640)},
 
@@ -1016,7 +854,7 @@ struct VideoModeTable viafb_modes[] = {
         {CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)}
 };
 
-struct VideoModeTable viafb_rb_modes[] = {
+static struct VideoModeTable viafb_rb_modes[] = {
         /* Display : 1360x768 (CVT Reduce Blanking) */
         {CRTM1360x768_RB, ARRAY_SIZE(CRTM1360x768_RB)},
 
@@ -1040,14 +878,12 @@ struct VideoModeTable viafb_rb_modes[] = {
 };
 
 struct crt_mode_table CEAM1280x720[] = {
-        {REFRESH_60, CLK_74_270M, M1280X720_CEA_R60_HSP,
-         M1280X720_CEA_R60_VSP,
+        {REFRESH_60, M1280X720_CEA_R60_HSP, M1280X720_CEA_R60_VSP,
          /* HT,    HA,   HBS,  HBE,  HSS, HSE,  VT,   VA,  VBS, VBE, VSS, VSE */
          {1650, 1280, 1280, 370, 1390, 40, 750, 720, 720, 30, 725, 5} }
 };
 struct crt_mode_table CEAM1920x1080[] = {
-        {REFRESH_60, CLK_148_500M, M1920X1080_CEA_R60_HSP,
-         M1920X1080_CEA_R60_VSP,
+        {REFRESH_60, M1920X1080_CEA_R60_HSP, M1920X1080_CEA_R60_VSP,
          /* HT,    HA,   HBS,  HBE,  HSS, HSE,  VT,  VA, VBS, VBE,  VSS, VSE */
          {2200, 1920, 1920, 300, 2008, 44, 1125, 1080, 1080, 45, 1084, 5} }
 };
@@ -1057,7 +893,6 @@ struct VideoModeTable CEA_HDMI_Modes[] = {
         {CEAM1920x1080, ARRAY_SIZE(CEAM1920x1080)}
 };
 
-int NUM_TOTAL_RES_MAP_REFRESH = ARRAY_SIZE(res_map_refresh_tbl);
 int NUM_TOTAL_CEA_MODES = ARRAY_SIZE(CEA_HDMI_Modes);
 int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs);
 int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs);
diff --git a/drivers/video/via/viamode.h b/drivers/video/via/viamode.h
index 5b1ced86514b..8a67ea1b5ef0 100644
--- a/drivers/video/via/viamode.h
+++ b/drivers/video/via/viamode.h
@@ -41,14 +41,6 @@ struct patch_table {
         struct io_reg *io_reg_table;
 };
 
-struct res_map_refresh {
-        int hres;
-        int vres;
-        int pixclock;
-        int vmode_refresh;
-};
-
-extern int NUM_TOTAL_RES_MAP_REFRESH;
 extern int NUM_TOTAL_CEA_MODES;
 extern int NUM_TOTAL_CN400_ModeXregs;
 extern int NUM_TOTAL_CN700_ModeXregs;
@@ -66,7 +58,6 @@ extern struct crt_mode_table CEAM1280x720[];
 extern struct crt_mode_table CEAM1920x1080[];
 extern struct VideoModeTable CEA_HDMI_Modes[];
 
-extern struct res_map_refresh res_map_refresh_tbl[];
 extern struct io_reg CN400_ModeXregs[];
 extern struct io_reg CN700_ModeXregs[];
 extern struct io_reg KM400_ModeXregs[];
diff --git a/drivers/video/via/vt1636.c b/drivers/video/via/vt1636.c
index 60e4192c2b34..ee2903b472cf 100644
--- a/drivers/video/via/vt1636.c
+++ b/drivers/video/via/vt1636.c
@@ -167,22 +167,6 @@ static int get_clk_range_index(u32 Clk)
                 return DPA_CLK_RANGE_150M;
 }
 
-static int get_lvds_dpa_setting_index(int panel_size_id,
-                             struct VT1636_DPA_SETTING *p_vt1636_dpasetting_tbl,
-                               int tbl_size)
-{
-        int i;
-
-        for (i = 0; i < tbl_size; i++) {
-                if (panel_size_id == p_vt1636_dpasetting_tbl->PanelSizeID)
-                        return i;
-
-                p_vt1636_dpasetting_tbl++;
-        }
-
-        return 0;
-}
-
 static void set_dpa_vt1636(struct lvds_setting_information
         *plvds_setting_info, struct lvds_chip_information *plvds_chip_info,
                     struct VT1636_DPA_SETTING *p_vt1636_dpa_setting)
@@ -206,7 +190,9 @@ void viafb_vt1636_patch_skew_on_vt3324(
         struct lvds_setting_information *plvds_setting_info,
         struct lvds_chip_information *plvds_chip_info)
 {
-        int index, size;
+        struct VT1636_DPA_SETTING dpa = {0x00, 0x00}, dpa_16x12 = {0x0B, 0x03},
+                *pdpa;
+        int index;
 
         DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3324.\n");
 
@@ -216,19 +202,21 @@ void viafb_vt1636_patch_skew_on_vt3324(
                     &GFX_DPA_SETTING_TBL_VT3324[index]);
 
         /* LVDS Transmitter DPA settings: */
-        size = ARRAY_SIZE(VT1636_DPA_SETTING_TBL_VT3324);
-        index =
-            get_lvds_dpa_setting_index(plvds_setting_info->lcd_panel_id,
-                                       VT1636_DPA_SETTING_TBL_VT3324, size);
-        set_dpa_vt1636(plvds_setting_info, plvds_chip_info,
-                       &VT1636_DPA_SETTING_TBL_VT3324[index]);
+        if (plvds_setting_info->lcd_panel_hres == 1600 &&
+                plvds_setting_info->lcd_panel_vres == 1200)
+                pdpa = &dpa_16x12;
+        else
+                pdpa = &dpa;
+
+        set_dpa_vt1636(plvds_setting_info, plvds_chip_info, pdpa);
 }
 
 void viafb_vt1636_patch_skew_on_vt3327(
         struct lvds_setting_information *plvds_setting_info,
         struct lvds_chip_information *plvds_chip_info)
 {
-        int index, size;
+        struct VT1636_DPA_SETTING dpa = {0x00, 0x00};
+        int index;
 
         DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3327.\n");
 
@@ -238,12 +226,7 @@ void viafb_vt1636_patch_skew_on_vt3327(
                     &GFX_DPA_SETTING_TBL_VT3327[index]);
 
         /* LVDS Transmitter DPA settings: */
-        size = ARRAY_SIZE(VT1636_DPA_SETTING_TBL_VT3327);
-        index =
-            get_lvds_dpa_setting_index(plvds_setting_info->lcd_panel_id,
-                                       VT1636_DPA_SETTING_TBL_VT3327, size);
-        set_dpa_vt1636(plvds_setting_info, plvds_chip_info,
-                       &VT1636_DPA_SETTING_TBL_VT3327[index]);
+        set_dpa_vt1636(plvds_setting_info, plvds_chip_info, &dpa);
 }
 
 void viafb_vt1636_patch_skew_on_vt3364(
diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c
index a2965ab92cfb..f9b3e3dc2421 100644
--- a/drivers/video/vt8623fb.c
+++ b/drivers/video/vt8623fb.c
@@ -121,13 +121,19 @@ MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, d
 
 /* ------------------------------------------------------------------------- */
 
+static void vt8623fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
+{
+        struct vt8623fb_info *par = info->par;
+
+        svga_tilecursor(par->state.vgabase, info, cursor);
+}
 
 static struct fb_tile_ops vt8623fb_tile_ops = {
         .fb_settile     = svga_settile,
         .fb_tilecopy    = svga_tilecopy,
         .fb_tilefill    = svga_tilefill,
         .fb_tileblit    = svga_tileblit,
-        .fb_tilecursor  = svga_tilecursor,
+        .fb_tilecursor  = vt8623fb_tilecursor,
         .fb_get_tilemax = svga_get_tilemax,
 };
 
@@ -253,6 +259,7 @@ static void vt8623fb_fillrect(struct fb_info *info, const struct fb_fillrect *re
 
 static void vt8623_set_pixclock(struct fb_info *info, u32 pixclock)
 {
+        struct vt8623fb_info *par = info->par;
         u16 m, n, r;
         u8 regval;
         int rv;
@@ -264,18 +271,18 @@ static void vt8623_set_pixclock(struct fb_info *info, u32 pixclock)
         }
 
         /* Set VGA misc register  */
-        regval = vga_r(NULL, VGA_MIS_R);
-        vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
+        regval = vga_r(par->state.vgabase, VGA_MIS_R);
+        vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
 
         /* Set clock registers */
-        vga_wseq(NULL, 0x46, (n  | (r << 6)));
-        vga_wseq(NULL, 0x47, m);
+        vga_wseq(par->state.vgabase, 0x46, (n  | (r << 6)));
+        vga_wseq(par->state.vgabase, 0x47, m);
 
         udelay(1000);
 
         /* PLL reset */
-        svga_wseq_mask(0x40, 0x02, 0x02);
-        svga_wseq_mask(0x40, 0x00, 0x02);
+        svga_wseq_mask(par->state.vgabase, 0x40, 0x02, 0x02);
+        svga_wseq_mask(par->state.vgabase, 0x40, 0x00, 0x02);
 }
 
 
@@ -285,7 +292,10 @@ static int vt8623fb_open(struct fb_info *info, int user)
 
         mutex_lock(&(par->open_lock));
         if (par->ref_count == 0) {
+                void __iomem *vgabase = par->state.vgabase;
+
                 memset(&(par->state), 0, sizeof(struct vgastate));
+                par->state.vgabase = vgabase;
                 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
                 par->state.num_crtc = 0xA2;
                 par->state.num_seq = 0x50;
@@ -373,6 +383,7 @@ static int vt8623fb_check_var(struct fb_var_screeninfo *var, struct fb_info *inf
 static int vt8623fb_set_par(struct fb_info *info)
 {
         u32 mode, offset_value, fetch_value, screen_size;
+        struct vt8623fb_info *par = info->par;
         u32 bpp = info->var.bits_per_pixel;
 
         if (bpp != 0) {
@@ -414,82 +425,82 @@ static int vt8623fb_set_par(struct fb_info *info)
         info->var.activate = FB_ACTIVATE_NOW;
 
         /* Unlock registers */
-        svga_wseq_mask(0x10, 0x01, 0x01);
-        svga_wcrt_mask(0x11, 0x00, 0x80);
-        svga_wcrt_mask(0x47, 0x00, 0x01);
+        svga_wseq_mask(par->state.vgabase, 0x10, 0x01, 0x01);
+        svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
+        svga_wcrt_mask(par->state.vgabase, 0x47, 0x00, 0x01);
 
         /* Device, screen and sync off */
-        svga_wseq_mask(0x01, 0x20, 0x20);
-        svga_wcrt_mask(0x36, 0x30, 0x30);
-        svga_wcrt_mask(0x17, 0x00, 0x80);
+        svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
+        svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30);
+        svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
 
         /* Set default values */
-        svga_set_default_gfx_regs();
-        svga_set_default_atc_regs();
-        svga_set_default_seq_regs();
-        svga_set_default_crt_regs();
-        svga_wcrt_multi(vt8623_line_compare_regs, 0xFFFFFFFF);
-        svga_wcrt_multi(vt8623_start_address_regs, 0);
+        svga_set_default_gfx_regs(par->state.vgabase);
+        svga_set_default_atc_regs(par->state.vgabase);
+        svga_set_default_seq_regs(par->state.vgabase);
+        svga_set_default_crt_regs(par->state.vgabase);
+        svga_wcrt_multi(par->state.vgabase, vt8623_line_compare_regs, 0xFFFFFFFF);
+        svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, 0);
 
-        svga_wcrt_multi(vt8623_offset_regs, offset_value);
-        svga_wseq_multi(vt8623_fetch_count_regs, fetch_value);
+        svga_wcrt_multi(par->state.vgabase, vt8623_offset_regs, offset_value);
+        svga_wseq_multi(par->state.vgabase, vt8623_fetch_count_regs, fetch_value);
 
         /* Clear H/V Skew */
-        svga_wcrt_mask(0x03, 0x00, 0x60);
-        svga_wcrt_mask(0x05, 0x00, 0x60);
+        svga_wcrt_mask(par->state.vgabase, 0x03, 0x00, 0x60);
+        svga_wcrt_mask(par->state.vgabase, 0x05, 0x00, 0x60);
 
         if (info->var.vmode & FB_VMODE_DOUBLE)
-                svga_wcrt_mask(0x09, 0x80, 0x80);
+                svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
         else
-                svga_wcrt_mask(0x09, 0x00, 0x80);
+                svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
 
-        svga_wseq_mask(0x1E, 0xF0, 0xF0); // DI/DVP bus
-        svga_wseq_mask(0x2A, 0x0F, 0x0F); // DI/DVP bus
-        svga_wseq_mask(0x16, 0x08, 0xBF); // FIFO read threshold
-        vga_wseq(NULL, 0x17, 0x1F);       // FIFO depth
-        vga_wseq(NULL, 0x18, 0x4E);
-        svga_wseq_mask(0x1A, 0x08, 0x08); // enable MMIO ?
+        svga_wseq_mask(par->state.vgabase, 0x1E, 0xF0, 0xF0); // DI/DVP bus
+        svga_wseq_mask(par->state.vgabase, 0x2A, 0x0F, 0x0F); // DI/DVP bus
+        svga_wseq_mask(par->state.vgabase, 0x16, 0x08, 0xBF); // FIFO read threshold
+        vga_wseq(par->state.vgabase, 0x17, 0x1F);       // FIFO depth
+        vga_wseq(par->state.vgabase, 0x18, 0x4E);
+        svga_wseq_mask(par->state.vgabase, 0x1A, 0x08, 0x08); // enable MMIO ?
 
-        vga_wcrt(NULL, 0x32, 0x00);
-        vga_wcrt(NULL, 0x34, 0x00);
-        vga_wcrt(NULL, 0x6A, 0x80);
-        vga_wcrt(NULL, 0x6A, 0xC0);
+        vga_wcrt(par->state.vgabase, 0x32, 0x00);
+        vga_wcrt(par->state.vgabase, 0x34, 0x00);
+        vga_wcrt(par->state.vgabase, 0x6A, 0x80);
+        vga_wcrt(par->state.vgabase, 0x6A, 0xC0);
 
-        vga_wgfx(NULL, 0x20, 0x00);
-        vga_wgfx(NULL, 0x21, 0x00);
-        vga_wgfx(NULL, 0x22, 0x00);
+        vga_wgfx(par->state.vgabase, 0x20, 0x00);
+        vga_wgfx(par->state.vgabase, 0x21, 0x00);
+        vga_wgfx(par->state.vgabase, 0x22, 0x00);
 
         /* Set SR15 according to number of bits per pixel */
         mode = svga_match_format(vt8623fb_formats, &(info->var), &(info->fix));
         switch (mode) {
         case 0:
                 pr_debug("fb%d: text mode\n", info->node);
-                svga_set_textmode_vga_regs();
-                svga_wseq_mask(0x15, 0x00, 0xFE);
-                svga_wcrt_mask(0x11, 0x60, 0x70);
+                svga_set_textmode_vga_regs(par->state.vgabase);
+                svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
+                svga_wcrt_mask(par->state.vgabase, 0x11, 0x60, 0x70);
                 break;
         case 1:
                 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
-                vga_wgfx(NULL, VGA_GFX_MODE, 0x40);
-                svga_wseq_mask(0x15, 0x20, 0xFE);
-                svga_wcrt_mask(0x11, 0x00, 0x70);
+                vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
+                svga_wseq_mask(par->state.vgabase, 0x15, 0x20, 0xFE);
+                svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70);
                 break;
         case 2:
                 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
-                svga_wseq_mask(0x15, 0x00, 0xFE);
-                svga_wcrt_mask(0x11, 0x00, 0x70);
+                svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
+                svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70);
                 break;
         case 3:
                 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
-                svga_wseq_mask(0x15, 0x22, 0xFE);
+                svga_wseq_mask(par->state.vgabase, 0x15, 0x22, 0xFE);
                 break;
         case 4:
                 pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
-                svga_wseq_mask(0x15, 0xB6, 0xFE);
+                svga_wseq_mask(par->state.vgabase, 0x15, 0xB6, 0xFE);
                 break;
         case 5:
                 pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
-                svga_wseq_mask(0x15, 0xAE, 0xFE);
+                svga_wseq_mask(par->state.vgabase, 0x15, 0xAE, 0xFE);
                 break;
         default:
                 printk(KERN_ERR "vt8623fb: unsupported mode - bug\n");
@@ -497,16 +508,16 @@ static int vt8623fb_set_par(struct fb_info *info)
         }
 
         vt8623_set_pixclock(info, info->var.pixclock);
-        svga_set_timings(&vt8623_timing_regs, &(info->var), 1, 1,
+        svga_set_timings(par->state.vgabase, &vt8623_timing_regs, &(info->var), 1, 1,
                          (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, 1,
                          1, info->node);
 
         memset_io(info->screen_base, 0x00, screen_size);
 
         /* Device and screen back on */
-        svga_wcrt_mask(0x17, 0x80, 0x80);
-        svga_wcrt_mask(0x36, 0x00, 0x30);
-        svga_wseq_mask(0x01, 0x00, 0x20);
+        svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
+        svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
+        svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
 
         return 0;
 }
@@ -569,31 +580,33 @@ static int vt8623fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 
 static int vt8623fb_blank(int blank_mode, struct fb_info *info)
 {
+        struct vt8623fb_info *par = info->par;
+
         switch (blank_mode) {
         case FB_BLANK_UNBLANK:
                 pr_debug("fb%d: unblank\n", info->node);
-                svga_wcrt_mask(0x36, 0x00, 0x30);
-                svga_wseq_mask(0x01, 0x00, 0x20);
+                svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
+                svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
                 break;
         case FB_BLANK_NORMAL:
                 pr_debug("fb%d: blank\n", info->node);
-                svga_wcrt_mask(0x36, 0x00, 0x30);
-                svga_wseq_mask(0x01, 0x20, 0x20);
+                svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
+                svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
                 break;
         case FB_BLANK_HSYNC_SUSPEND:
                 pr_debug("fb%d: DPMS standby (hsync off)\n", info->node);
-                svga_wcrt_mask(0x36, 0x10, 0x30);
-                svga_wseq_mask(0x01, 0x20, 0x20);
+                svga_wcrt_mask(par->state.vgabase, 0x36, 0x10, 0x30);
+                svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
                 break;
         case FB_BLANK_VSYNC_SUSPEND:
                 pr_debug("fb%d: DPMS suspend (vsync off)\n", info->node);
-                svga_wcrt_mask(0x36, 0x20, 0x30);
-                svga_wseq_mask(0x01, 0x20, 0x20);
+                svga_wcrt_mask(par->state.vgabase, 0x36, 0x20, 0x30);
+                svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
                 break;
         case FB_BLANK_POWERDOWN:
                 pr_debug("fb%d: DPMS off (no sync)\n", info->node);
-                svga_wcrt_mask(0x36, 0x30, 0x30);
-                svga_wseq_mask(0x01, 0x20, 0x20);
+                svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30);
+                svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
                 break;
         }
 
@@ -603,6 +616,7 @@ static int vt8623fb_blank(int blank_mode, struct fb_info *info)
 
 static int vt8623fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 {
+        struct vt8623fb_info *par = info->par;
         unsigned int offset;
 
         /* Calculate the offset */
@@ -616,7 +630,7 @@ static int vt8623fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *i
         }
 
         /* Set the offset */
-        svga_wcrt_multi(vt8623_start_address_regs, offset);
+        svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, offset);
 
         return 0;
 }
@@ -647,6 +661,8 @@ static struct fb_ops vt8623fb_ops = {
 
 static int __devinit vt8623_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 {
+        struct pci_bus_region bus_reg;
+        struct resource vga_res;
         struct fb_info *info;
         struct vt8623fb_info *par;
         unsigned int memsize1, memsize2;
@@ -705,9 +721,18 @@ static int __devinit vt8623_pci_probe(struct pci_dev *dev, const struct pci_devi
                 goto err_iomap_2;
         }
 
+        bus_reg.start = 0;
+        bus_reg.end = 64 * 1024;
+
+        vga_res.flags = IORESOURCE_IO;
+
+        pcibios_bus_to_resource(dev, &vga_res, &bus_reg);
+
+        par->state.vgabase = (void __iomem *) vga_res.start;
+
         /* Find how many physical memory there is on card */
-        memsize1 = (vga_rseq(NULL, 0x34) + 1) >> 1;
-        memsize2 = vga_rseq(NULL, 0x39) << 2;
+        memsize1 = (vga_rseq(par->state.vgabase, 0x34) + 1) >> 1;
+        memsize2 = vga_rseq(par->state.vgabase, 0x39) << 2;
 
         if ((16 <= memsize1) && (memsize1 <= 64) && (memsize1 == memsize2))
                 info->screen_size = memsize1 << 20;
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index 68bd23476c64..77dea015ff69 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -404,8 +404,7 @@ static int xilinxfb_release(struct device *dev)
  * OF bus binding
  */
 
-static int __devinit
-xilinxfb_of_probe(struct platform_device *op, const struct of_device_id *match)
+static int __devinit xilinxfb_of_probe(struct platform_device *op)
 {
         const u32 *prop;
         u32 *p;
@@ -418,8 +417,6 @@ xilinxfb_of_probe(struct platform_device *op, const struct of_device_id *match)
         /* Copy with the default pdata (not a ptr reference!) */
         pdata = xilinx_fb_default_pdata;
 
-        dev_dbg(&op->dev, "xilinxfb_of_probe(%p, %p)\n", op, match);
-
         /* Allocate the driver data region */
         drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
         if (!drvdata) {
@@ -505,7 +502,7 @@ static struct of_device_id xilinxfb_of_match[] __devinitdata = {
 };
 MODULE_DEVICE_TABLE(of, xilinxfb_of_match);
 
-static struct of_platform_driver xilinxfb_of_driver = {
+static struct platform_driver xilinxfb_of_driver = {
         .probe = xilinxfb_of_probe,
         .remove = __devexit_p(xilinxfb_of_remove),
         .driver = {
@@ -523,13 +520,13 @@ static struct of_platform_driver xilinxfb_of_driver = {
 static int __init
 xilinxfb_init(void)
 {
-        return of_register_platform_driver(&xilinxfb_of_driver);
+        return platform_driver_register(&xilinxfb_of_driver);
 }
 
 static void __exit
 xilinxfb_cleanup(void)
 {
-        of_unregister_platform_driver(&xilinxfb_of_driver);
+        platform_driver_unregister(&xilinxfb_of_driver);
 }
 
 module_init(xilinxfb_init);