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-rw-r--r--drivers/video/savage/savagefb.h206
-rw-r--r--drivers/video/savage/savagefb_driver.c818
2 files changed, 537 insertions, 487 deletions
diff --git a/drivers/video/savage/savagefb.h b/drivers/video/savage/savagefb.h
index ea17f7e0482c..58cfdfb41833 100644
--- a/drivers/video/savage/savagefb.h
+++ b/drivers/video/savage/savagefb.h
@@ -169,6 +169,7 @@ struct savagefb_par {
169 struct savagefb_i2c_chan chan; 169 struct savagefb_i2c_chan chan;
170 unsigned char *edid; 170 unsigned char *edid;
171 u32 pseudo_palette[16]; 171 u32 pseudo_palette[16];
172 int paletteEnabled;
172 int pm_state; 173 int pm_state;
173 int display_type; 174 int display_type;
174 int dvi; 175 int dvi;
@@ -244,105 +245,150 @@ struct savagefb_par {
244 245
245 246
246/* IO functions */ 247/* IO functions */
248static inline u8 savage_in8(u32 addr, struct savagefb_par *par)
249{
250 return readb(par->mmio.vbase + addr);
251}
252
253static inline u16 savage_in16(u32 addr, struct savagefb_par *par)
254{
255 return readw(par->mmio.vbase + addr);
256}
257
258static inline u32 savage_in32(u32 addr, struct savagefb_par *par)
259{
260 return readl(par->mmio.vbase + addr);
261}
262
263static inline void savage_out8(u32 addr, u8 val, struct savagefb_par *par)
264{
265 writeb(val, par->mmio.vbase + addr);
266}
267
268static inline void savage_out16(u32 addr, u16 val, struct savagefb_par *par)
269{
270 writew(val, par->mmio.vbase + addr);
271}
272
273static inline void savage_out32(u32 addr, u32 val, struct savagefb_par *par)
274{
275 writel(val, par->mmio.vbase + addr);
276}
277
278static inline u8 vga_in8(int addr, struct savagefb_par *par)
279{
280 return savage_in8(0x8000 + addr, par);
281}
282
283static inline u16 vga_in16(int addr, struct savagefb_par *par)
284{
285 return savage_in16(0x8000 + addr, par);
286}
287
288static inline u8 vga_in32(int addr, struct savagefb_par *par)
289{
290 return savage_in32(0x8000 + addr, par);
291}
292
293static inline void vga_out8(int addr, u8 val, struct savagefb_par *par)
294{
295 savage_out8(0x8000 + addr, val, par);
296}
297
298static inline void vga_out16(int addr, u16 val, struct savagefb_par *par)
299{
300 savage_out16(0x8000 + addr, val, par);
301}
302
303static inline void vga_out32(int addr, u32 val, struct savagefb_par *par)
304{
305 savage_out32(0x8000 + addr, val, par);
306}
247 307
248#define vga_in8(addr) (inb (addr)) 308static inline u8 VGArCR (u8 index, struct savagefb_par *par)
249#define vga_in16(addr) (inw (addr)) 309{
250#define vga_in32(addr) (inl (addr)) 310 vga_out8(0x3d4, index, par);
311 return vga_in8(0x3d5, par);
312}
313
314static inline u8 VGArGR (u8 index, struct savagefb_par *par)
315{
316 vga_out8(0x3ce, index, par);
317 return vga_in8(0x3cf, par);
318}
319
320static inline u8 VGArSEQ (u8 index, struct savagefb_par *par)
321{
322 vga_out8(0x3c4, index, par);
323 return vga_in8(0x3c5, par);
324}
251 325
252#define vga_out8(addr,val) (outb ((val), (addr))) 326static inline void VGAwCR(u8 index, u8 val, struct savagefb_par *par)
253#define vga_out16(addr,val) (outw ((val), (addr))) 327{
254#define vga_out32(addr,val) (outl ((val), (addr))) 328 vga_out8(0x3d4, index, par);
329 vga_out8(0x3d5, val, par);
330}
255 331
256#define savage_in16(addr) readw(par->mmio.vbase + (addr)) 332static inline void VGAwGR(u8 index, u8 val, struct savagefb_par *par)
257#define savage_in32(addr) readl(par->mmio.vbase + (addr)) 333{
334 vga_out8(0x3ce, index, par);
335 vga_out8(0x3cf, val, par);
336}
258 337
259#define savage_out16(addr,val) writew((val), par->mmio.vbase + (addr)) 338static inline void VGAwSEQ(u8 index, u8 val, struct savagefb_par *par)
260#define savage_out32(addr,val) writel((val), par->mmio.vbase + (addr)) 339{
340 vga_out8(0x3c4, index, par);
341 vga_out8 (0x3c5, val, par);
342}
261 343
262static inline u8 VGArCR (u8 index) 344static inline void VGAenablePalette(struct savagefb_par *par)
263{ 345{
264 outb (index, 0x3d4); 346 u8 tmp;
265 return inb (0x3d5); 347
348 tmp = vga_in8(0x3da, par);
349 vga_out8(0x3c0, 0x00, par);
350 par->paletteEnabled = 1;
266} 351}
267 352
268static inline u8 VGArGR (u8 index) 353static inline void VGAdisablePalette(struct savagefb_par *par)
269{ 354{
270 outb (index, 0x3ce); 355 u8 tmp;
271 return inb (0x3cf); 356
357 tmp = vga_in8(0x3da, par);
358 vga_out8(0x3c0, 0x20, par);
359 par->paletteEnabled = 0;
272} 360}
273 361
274static inline u8 VGArSEQ (u8 index) 362static inline void VGAwATTR(u8 index, u8 value, struct savagefb_par *par)
275{ 363{
276 outb (index, 0x3c4); 364 u8 tmp;
277 return inb (0x3c5); 365
366 if (par->paletteEnabled)
367 index &= ~0x20;
368 else
369 index |= 0x20;
370
371 tmp = vga_in8(0x3da, par);
372 vga_out8(0x3c0, index, par);
373 vga_out8 (0x3c0, value, par);
278} 374}
279 375
280#define VGAwCR(index, val) \ 376static inline void VGAwMISC(u8 value, struct savagefb_par *par)
281do { \ 377{
282 vga_out8 (0x3d4, index); \ 378 vga_out8(0x3c2, value, par);
283 vga_out8 (0x3d5, val); \ 379}
284} while (0)
285
286#define VGAwGR(index, val) \
287do { \
288 vga_out8 (0x3ce, index); \
289 vga_out8 (0x3cf, val); \
290} while (0)
291
292#define VGAwSEQ(index, val) \
293do { \
294 vga_out8 (0x3c4, index); \
295 vga_out8 (0x3c5, val); \
296} while (0)
297
298#define VGAenablePalette() \
299do { \
300 u8 tmp; \
301 \
302 tmp = vga_in8 (0x3da); \
303 vga_out8 (0x3c0, 0x00); \
304 paletteEnabled = 1; \
305} while (0)
306
307#define VGAdisablePalette() \
308do { \
309 u8 tmp; \
310 \
311 tmp = vga_in8 (0x3da); \
312 vga_out8 (0x3c0, 0x20); \
313 paletteEnabled = 0; \
314} while (0)
315
316#define VGAwATTR(index, value) \
317do { \
318 u8 tmp; \
319 \
320 if (paletteEnabled) \
321 index &= ~0x20; \
322 else \
323 index |= 0x20; \
324 \
325 tmp = vga_in8 (0x3da); \
326 vga_out8 (0x3c0, index); \
327 vga_out8 (0x3c0, value); \
328} while (0)
329
330#define VGAwMISC(value) \
331do { \
332 vga_out8 (0x3c2, value); \
333} while (0)
334 380
335#ifndef CONFIG_FB_SAVAGE_ACCEL 381#ifndef CONFIG_FB_SAVAGE_ACCEL
336#define savagefb_set_clip(x) 382#define savagefb_set_clip(x)
337#endif 383#endif
338 384
339#define VerticalRetraceWait() \ 385static inline void VerticalRetraceWait(struct savagefb_par *par)
340{ \ 386{
341 vga_out8 (0x3d4, 0x17); \ 387 vga_out8(0x3d4, 0x17, par);
342 if (vga_in8 (0x3d5) & 0x80) { \ 388 if (vga_in8(0x3d5, par) & 0x80) {
343 while ((vga_in8(0x3da) & 0x08) == 0x08) ; \ 389 while ((vga_in8(0x3da, par) & 0x08) == 0x08);
344 while ((vga_in8(0x3da) & 0x08) == 0x00) ; \ 390 while ((vga_in8(0x3da, par) & 0x08) == 0x00);
345 } \ 391 }
346} 392}
347 393
348extern int savagefb_probe_i2c_connector(struct fb_info *info, 394extern int savagefb_probe_i2c_connector(struct fb_info *info,
diff --git a/drivers/video/savage/savagefb_driver.c b/drivers/video/savage/savagefb_driver.c
index 378ea1e34de7..06e989ba3d13 100644
--- a/drivers/video/savage/savagefb_driver.c
+++ b/drivers/video/savage/savagefb_driver.c
@@ -74,7 +74,6 @@
74 74
75 75
76static char *mode_option __initdata = NULL; 76static char *mode_option __initdata = NULL;
77static int paletteEnabled = 0;
78 77
79#ifdef MODULE 78#ifdef MODULE
80 79
@@ -90,9 +89,9 @@ MODULE_DESCRIPTION("FBDev driver for S3 Savage PCI/AGP Chips");
90static void vgaHWSeqReset (struct savagefb_par *par, int start) 89static void vgaHWSeqReset (struct savagefb_par *par, int start)
91{ 90{
92 if (start) 91 if (start)
93 VGAwSEQ (0x00, 0x01); /* Synchronous Reset */ 92 VGAwSEQ (0x00, 0x01, par); /* Synchronous Reset */
94 else 93 else
95 VGAwSEQ (0x00, 0x03); /* End Reset */ 94 VGAwSEQ (0x00, 0x03, par); /* End Reset */
96} 95}
97 96
98static void vgaHWProtect (struct savagefb_par *par, int on) 97static void vgaHWProtect (struct savagefb_par *par, int on)
@@ -103,23 +102,23 @@ static void vgaHWProtect (struct savagefb_par *par, int on)
103 /* 102 /*
104 * Turn off screen and disable sequencer. 103 * Turn off screen and disable sequencer.
105 */ 104 */
106 tmp = VGArSEQ (0x01); 105 tmp = VGArSEQ (0x01, par);
107 106
108 vgaHWSeqReset (par, 1); /* start synchronous reset */ 107 vgaHWSeqReset (par, 1); /* start synchronous reset */
109 VGAwSEQ (0x01, tmp | 0x20); /* disable the display */ 108 VGAwSEQ (0x01, tmp | 0x20, par);/* disable the display */
110 109
111 VGAenablePalette(); 110 VGAenablePalette(par);
112 } else { 111 } else {
113 /* 112 /*
114 * Reenable sequencer, then turn on screen. 113 * Reenable sequencer, then turn on screen.
115 */ 114 */
116 115
117 tmp = VGArSEQ (0x01); 116 tmp = VGArSEQ (0x01, par);
118 117
119 VGAwSEQ (0x01, tmp & ~0x20); /* reenable display */ 118 VGAwSEQ (0x01, tmp & ~0x20, par);/* reenable display */
120 vgaHWSeqReset (par, 0); /* clear synchronous reset */ 119 vgaHWSeqReset (par, 0); /* clear synchronous reset */
121 120
122 VGAdisablePalette(); 121 VGAdisablePalette(par);
123 } 122 }
124} 123}
125 124
@@ -127,27 +126,27 @@ static void vgaHWRestore (struct savagefb_par *par)
127{ 126{
128 int i; 127 int i;
129 128
130 VGAwMISC (par->MiscOutReg); 129 VGAwMISC (par->MiscOutReg, par);
131 130
132 for (i = 1; i < 5; i++) 131 for (i = 1; i < 5; i++)
133 VGAwSEQ (i, par->Sequencer[i]); 132 VGAwSEQ (i, par->Sequencer[i], par);
134 133
135 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or 134 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or
136 CRTC[17] */ 135 CRTC[17] */
137 VGAwCR (17, par->CRTC[17] & ~0x80); 136 VGAwCR (17, par->CRTC[17] & ~0x80, par);
138 137
139 for (i = 0; i < 25; i++) 138 for (i = 0; i < 25; i++)
140 VGAwCR (i, par->CRTC[i]); 139 VGAwCR (i, par->CRTC[i], par);
141 140
142 for (i = 0; i < 9; i++) 141 for (i = 0; i < 9; i++)
143 VGAwGR (i, par->Graphics[i]); 142 VGAwGR (i, par->Graphics[i], par);
144 143
145 VGAenablePalette(); 144 VGAenablePalette(par);
146 145
147 for (i = 0; i < 21; i++) 146 for (i = 0; i < 21; i++)
148 VGAwATTR (i, par->Attribute[i]); 147 VGAwATTR (i, par->Attribute[i], par);
149 148
150 VGAdisablePalette(); 149 VGAdisablePalette(par);
151} 150}
152 151
153static void vgaHWInit (struct fb_var_screeninfo *var, 152static void vgaHWInit (struct fb_var_screeninfo *var,
@@ -267,7 +266,7 @@ savage3D_waitfifo(struct savagefb_par *par, int space)
267{ 266{
268 int slots = MAXFIFO - space; 267 int slots = MAXFIFO - space;
269 268
270 while ((savage_in32(0x48C00) & 0x0000ffff) > slots); 269 while ((savage_in32(0x48C00, par) & 0x0000ffff) > slots);
271} 270}
272 271
273static void 272static void
@@ -275,7 +274,7 @@ savage4_waitfifo(struct savagefb_par *par, int space)
275{ 274{
276 int slots = MAXFIFO - space; 275 int slots = MAXFIFO - space;
277 276
278 while ((savage_in32(0x48C60) & 0x001fffff) > slots); 277 while ((savage_in32(0x48C60, par) & 0x001fffff) > slots);
279} 278}
280 279
281static void 280static void
@@ -283,26 +282,26 @@ savage2000_waitfifo(struct savagefb_par *par, int space)
283{ 282{
284 int slots = MAXFIFO - space; 283 int slots = MAXFIFO - space;
285 284
286 while ((savage_in32(0x48C60) & 0x0000ffff) > slots); 285 while ((savage_in32(0x48C60, par) & 0x0000ffff) > slots);
287} 286}
288 287
289/* Wait for idle accelerator */ 288/* Wait for idle accelerator */
290static void 289static void
291savage3D_waitidle(struct savagefb_par *par) 290savage3D_waitidle(struct savagefb_par *par)
292{ 291{
293 while ((savage_in32(0x48C00) & 0x0008ffff) != 0x80000); 292 while ((savage_in32(0x48C00, par) & 0x0008ffff) != 0x80000);
294} 293}
295 294
296static void 295static void
297savage4_waitidle(struct savagefb_par *par) 296savage4_waitidle(struct savagefb_par *par)
298{ 297{
299 while ((savage_in32(0x48C60) & 0x00a00000) != 0x00a00000); 298 while ((savage_in32(0x48C60, par) & 0x00a00000) != 0x00a00000);
300} 299}
301 300
302static void 301static void
303savage2000_waitidle(struct savagefb_par *par) 302savage2000_waitidle(struct savagefb_par *par)
304{ 303{
305 while ((savage_in32(0x48C60) & 0x009fffff)); 304 while ((savage_in32(0x48C60, par) & 0x009fffff));
306} 305}
307 306
308 307
@@ -319,59 +318,64 @@ SavageSetup2DEngine (struct savagefb_par *par)
319 case S3_SAVAGE3D: 318 case S3_SAVAGE3D:
320 case S3_SAVAGE_MX: 319 case S3_SAVAGE_MX:
321 /* Disable BCI */ 320 /* Disable BCI */
322 savage_out32(0x48C18, savage_in32(0x48C18) & 0x3FF0); 321 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
323 /* Setup BCI command overflow buffer */ 322 /* Setup BCI command overflow buffer */
324 savage_out32(0x48C14, (par->cob_offset >> 11) | (par->cob_index << 29)); 323 savage_out32(0x48C14,
324 (par->cob_offset >> 11) | (par->cob_index << 29),
325 par);
325 /* Program shadow status update. */ 326 /* Program shadow status update. */
326 savage_out32(0x48C10, 0x78207220); 327 savage_out32(0x48C10, 0x78207220, par);
327 savage_out32(0x48C0C, 0); 328 savage_out32(0x48C0C, 0, par);
328 /* Enable BCI and command overflow buffer */ 329 /* Enable BCI and command overflow buffer */
329 savage_out32(0x48C18, savage_in32(0x48C18) | 0x0C); 330 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par);
330 break; 331 break;
331 case S3_SAVAGE4: 332 case S3_SAVAGE4:
332 case S3_PROSAVAGE: 333 case S3_PROSAVAGE:
333 case S3_SUPERSAVAGE: 334 case S3_SUPERSAVAGE:
334 /* Disable BCI */ 335 /* Disable BCI */
335 savage_out32(0x48C18, savage_in32(0x48C18) & 0x3FF0); 336 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
336 /* Program shadow status update */ 337 /* Program shadow status update */
337 savage_out32(0x48C10, 0x00700040); 338 savage_out32(0x48C10, 0x00700040, par);
338 savage_out32(0x48C0C, 0); 339 savage_out32(0x48C0C, 0, par);
339 /* Enable BCI without the COB */ 340 /* Enable BCI without the COB */
340 savage_out32(0x48C18, savage_in32(0x48C18) | 0x08); 341 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x08, par);
341 break; 342 break;
342 case S3_SAVAGE2000: 343 case S3_SAVAGE2000:
343 /* Disable BCI */ 344 /* Disable BCI */
344 savage_out32(0x48C18, 0); 345 savage_out32(0x48C18, 0, par);
345 /* Setup BCI command overflow buffer */ 346 /* Setup BCI command overflow buffer */
346 savage_out32(0x48C18, (par->cob_offset >> 7) | (par->cob_index)); 347 savage_out32(0x48C18,
348 (par->cob_offset >> 7) | (par->cob_index),
349 par);
347 /* Disable shadow status update */ 350 /* Disable shadow status update */
348 savage_out32(0x48A30, 0); 351 savage_out32(0x48A30, 0, par);
349 /* Enable BCI and command overflow buffer */ 352 /* Enable BCI and command overflow buffer */
350 savage_out32(0x48C18, savage_in32(0x48C18) | 0x00280000 ); 353 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x00280000,
354 par);
351 break; 355 break;
352 default: 356 default:
353 break; 357 break;
354 } 358 }
355 /* Turn on 16-bit register access. */ 359 /* Turn on 16-bit register access. */
356 vga_out8(0x3d4, 0x31); 360 vga_out8(0x3d4, 0x31, par);
357 vga_out8(0x3d5, 0x0c); 361 vga_out8(0x3d5, 0x0c, par);
358 362
359 /* Set stride to use GBD. */ 363 /* Set stride to use GBD. */
360 vga_out8 (0x3d4, 0x50); 364 vga_out8 (0x3d4, 0x50, par);
361 vga_out8 (0x3d5, vga_in8 (0x3d5 ) | 0xC1); 365 vga_out8 (0x3d5, vga_in8(0x3d5, par) | 0xC1, par);
362 366
363 /* Enable 2D engine. */ 367 /* Enable 2D engine. */
364 vga_out8 (0x3d4, 0x40 ); 368 vga_out8 (0x3d4, 0x40, par);
365 vga_out8 (0x3d5, 0x01 ); 369 vga_out8 (0x3d5, 0x01, par);
366 370
367 savage_out32 (MONO_PAT_0, ~0); 371 savage_out32 (MONO_PAT_0, ~0, par);
368 savage_out32 (MONO_PAT_1, ~0); 372 savage_out32 (MONO_PAT_1, ~0, par);
369 373
370 /* Setup plane masks */ 374 /* Setup plane masks */
371 savage_out32 (0x8128, ~0 ); /* enable all write planes */ 375 savage_out32 (0x8128, ~0, par); /* enable all write planes */
372 savage_out32 (0x812C, ~0 ); /* enable all read planes */ 376 savage_out32 (0x812C, ~0, par); /* enable all read planes */
373 savage_out16 (0x8134, 0x27 ); 377 savage_out16 (0x8134, 0x27, par);
374 savage_out16 (0x8136, 0x07 ); 378 savage_out16 (0x8136, 0x07, par);
375 379
376 /* Now set the GBD */ 380 /* Now set the GBD */
377 par->bci_ptr = 0; 381 par->bci_ptr = 0;
@@ -489,8 +493,8 @@ static void SavagePrintRegs(void)
489 for( i = 0; i < 0x70; i++ ) { 493 for( i = 0; i < 0x70; i++ ) {
490 if( !(i % 16) ) 494 if( !(i % 16) )
491 printk(KERN_DEBUG "\nSR%xx ", i >> 4 ); 495 printk(KERN_DEBUG "\nSR%xx ", i >> 4 );
492 vga_out8( 0x3c4, i ); 496 vga_out8( 0x3c4, i, par);
493 printk(KERN_DEBUG " %02x", vga_in8(0x3c5) ); 497 printk(KERN_DEBUG " %02x", vga_in8(0x3c5, par) );
494 } 498 }
495 499
496 printk(KERN_DEBUG "\n\nCR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC " 500 printk(KERN_DEBUG "\n\nCR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC "
@@ -499,8 +503,8 @@ static void SavagePrintRegs(void)
499 for( i = 0; i < 0xB7; i++ ) { 503 for( i = 0; i < 0xB7; i++ ) {
500 if( !(i % 16) ) 504 if( !(i % 16) )
501 printk(KERN_DEBUG "\nCR%xx ", i >> 4 ); 505 printk(KERN_DEBUG "\nCR%xx ", i >> 4 );
502 vga_out8( vgaCRIndex, i ); 506 vga_out8( vgaCRIndex, i, par);
503 printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg) ); 507 printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg, par) );
504 } 508 }
505 509
506 printk(KERN_DEBUG "\n\n"); 510 printk(KERN_DEBUG "\n\n");
@@ -513,152 +517,152 @@ static void savage_get_default_par(struct savagefb_par *par)
513{ 517{
514 unsigned char cr3a, cr53, cr66; 518 unsigned char cr3a, cr53, cr66;
515 519
516 vga_out16 (0x3d4, 0x4838); 520 vga_out16 (0x3d4, 0x4838, par);
517 vga_out16 (0x3d4, 0xa039); 521 vga_out16 (0x3d4, 0xa039, par);
518 vga_out16 (0x3c4, 0x0608); 522 vga_out16 (0x3c4, 0x0608, par);
519 523
520 vga_out8 (0x3d4, 0x66); 524 vga_out8 (0x3d4, 0x66, par);
521 cr66 = vga_in8 (0x3d5); 525 cr66 = vga_in8 (0x3d5, par);
522 vga_out8 (0x3d5, cr66 | 0x80); 526 vga_out8 (0x3d5, cr66 | 0x80, par);
523 vga_out8 (0x3d4, 0x3a); 527 vga_out8 (0x3d4, 0x3a, par);
524 cr3a = vga_in8 (0x3d5); 528 cr3a = vga_in8 (0x3d5, par);
525 vga_out8 (0x3d5, cr3a | 0x80); 529 vga_out8 (0x3d5, cr3a | 0x80, par);
526 vga_out8 (0x3d4, 0x53); 530 vga_out8 (0x3d4, 0x53, par);
527 cr53 = vga_in8 (0x3d5); 531 cr53 = vga_in8 (0x3d5, par);
528 vga_out8 (0x3d5, cr53 & 0x7f); 532 vga_out8 (0x3d5, cr53 & 0x7f, par);
529 533
530 vga_out8 (0x3d4, 0x66); 534 vga_out8 (0x3d4, 0x66, par);
531 vga_out8 (0x3d5, cr66); 535 vga_out8 (0x3d5, cr66, par);
532 vga_out8 (0x3d4, 0x3a); 536 vga_out8 (0x3d4, 0x3a, par);
533 vga_out8 (0x3d5, cr3a); 537 vga_out8 (0x3d5, cr3a, par);
534 538
535 vga_out8 (0x3d4, 0x66); 539 vga_out8 (0x3d4, 0x66, par);
536 vga_out8 (0x3d5, cr66); 540 vga_out8 (0x3d5, cr66, par);
537 vga_out8 (0x3d4, 0x3a); 541 vga_out8 (0x3d4, 0x3a, par);
538 vga_out8 (0x3d5, cr3a); 542 vga_out8 (0x3d5, cr3a, par);
539 543
540 /* unlock extended seq regs */ 544 /* unlock extended seq regs */
541 vga_out8 (0x3c4, 0x08); 545 vga_out8 (0x3c4, 0x08, par);
542 par->SR08 = vga_in8 (0x3c5); 546 par->SR08 = vga_in8 (0x3c5, par);
543 vga_out8 (0x3c5, 0x06); 547 vga_out8 (0x3c5, 0x06, par);
544 548
545 /* now save all the extended regs we need */ 549 /* now save all the extended regs we need */
546 vga_out8 (0x3d4, 0x31); 550 vga_out8 (0x3d4, 0x31, par);
547 par->CR31 = vga_in8 (0x3d5); 551 par->CR31 = vga_in8 (0x3d5, par);
548 vga_out8 (0x3d4, 0x32); 552 vga_out8 (0x3d4, 0x32, par);
549 par->CR32 = vga_in8 (0x3d5); 553 par->CR32 = vga_in8 (0x3d5, par);
550 vga_out8 (0x3d4, 0x34); 554 vga_out8 (0x3d4, 0x34, par);
551 par->CR34 = vga_in8 (0x3d5); 555 par->CR34 = vga_in8 (0x3d5, par);
552 vga_out8 (0x3d4, 0x36); 556 vga_out8 (0x3d4, 0x36, par);
553 par->CR36 = vga_in8 (0x3d5); 557 par->CR36 = vga_in8 (0x3d5, par);
554 vga_out8 (0x3d4, 0x3a); 558 vga_out8 (0x3d4, 0x3a, par);
555 par->CR3A = vga_in8 (0x3d5); 559 par->CR3A = vga_in8 (0x3d5, par);
556 vga_out8 (0x3d4, 0x40); 560 vga_out8 (0x3d4, 0x40, par);
557 par->CR40 = vga_in8 (0x3d5); 561 par->CR40 = vga_in8 (0x3d5, par);
558 vga_out8 (0x3d4, 0x42); 562 vga_out8 (0x3d4, 0x42, par);
559 par->CR42 = vga_in8 (0x3d5); 563 par->CR42 = vga_in8 (0x3d5, par);
560 vga_out8 (0x3d4, 0x45); 564 vga_out8 (0x3d4, 0x45, par);
561 par->CR45 = vga_in8 (0x3d5); 565 par->CR45 = vga_in8 (0x3d5, par);
562 vga_out8 (0x3d4, 0x50); 566 vga_out8 (0x3d4, 0x50, par);
563 par->CR50 = vga_in8 (0x3d5); 567 par->CR50 = vga_in8 (0x3d5, par);
564 vga_out8 (0x3d4, 0x51); 568 vga_out8 (0x3d4, 0x51, par);
565 par->CR51 = vga_in8 (0x3d5); 569 par->CR51 = vga_in8 (0x3d5, par);
566 vga_out8 (0x3d4, 0x53); 570 vga_out8 (0x3d4, 0x53, par);
567 par->CR53 = vga_in8 (0x3d5); 571 par->CR53 = vga_in8 (0x3d5, par);
568 vga_out8 (0x3d4, 0x58); 572 vga_out8 (0x3d4, 0x58, par);
569 par->CR58 = vga_in8 (0x3d5); 573 par->CR58 = vga_in8 (0x3d5, par);
570 vga_out8 (0x3d4, 0x60); 574 vga_out8 (0x3d4, 0x60, par);
571 par->CR60 = vga_in8 (0x3d5); 575 par->CR60 = vga_in8 (0x3d5, par);
572 vga_out8 (0x3d4, 0x66); 576 vga_out8 (0x3d4, 0x66, par);
573 par->CR66 = vga_in8 (0x3d5); 577 par->CR66 = vga_in8 (0x3d5, par);
574 vga_out8 (0x3d4, 0x67); 578 vga_out8 (0x3d4, 0x67, par);
575 par->CR67 = vga_in8 (0x3d5); 579 par->CR67 = vga_in8 (0x3d5, par);
576 vga_out8 (0x3d4, 0x68); 580 vga_out8 (0x3d4, 0x68, par);
577 par->CR68 = vga_in8 (0x3d5); 581 par->CR68 = vga_in8 (0x3d5, par);
578 vga_out8 (0x3d4, 0x69); 582 vga_out8 (0x3d4, 0x69, par);
579 par->CR69 = vga_in8 (0x3d5); 583 par->CR69 = vga_in8 (0x3d5, par);
580 vga_out8 (0x3d4, 0x6f); 584 vga_out8 (0x3d4, 0x6f, par);
581 par->CR6F = vga_in8 (0x3d5); 585 par->CR6F = vga_in8 (0x3d5, par);
582 586
583 vga_out8 (0x3d4, 0x33); 587 vga_out8 (0x3d4, 0x33, par);
584 par->CR33 = vga_in8 (0x3d5); 588 par->CR33 = vga_in8 (0x3d5, par);
585 vga_out8 (0x3d4, 0x86); 589 vga_out8 (0x3d4, 0x86, par);
586 par->CR86 = vga_in8 (0x3d5); 590 par->CR86 = vga_in8 (0x3d5, par);
587 vga_out8 (0x3d4, 0x88); 591 vga_out8 (0x3d4, 0x88, par);
588 par->CR88 = vga_in8 (0x3d5); 592 par->CR88 = vga_in8 (0x3d5, par);
589 vga_out8 (0x3d4, 0x90); 593 vga_out8 (0x3d4, 0x90, par);
590 par->CR90 = vga_in8 (0x3d5); 594 par->CR90 = vga_in8 (0x3d5, par);
591 vga_out8 (0x3d4, 0x91); 595 vga_out8 (0x3d4, 0x91, par);
592 par->CR91 = vga_in8 (0x3d5); 596 par->CR91 = vga_in8 (0x3d5, par);
593 vga_out8 (0x3d4, 0xb0); 597 vga_out8 (0x3d4, 0xb0, par);
594 par->CRB0 = vga_in8 (0x3d5) | 0x80; 598 par->CRB0 = vga_in8 (0x3d5, par) | 0x80;
595 599
596 /* extended mode timing regs */ 600 /* extended mode timing regs */
597 vga_out8 (0x3d4, 0x3b); 601 vga_out8 (0x3d4, 0x3b, par);
598 par->CR3B = vga_in8 (0x3d5); 602 par->CR3B = vga_in8 (0x3d5, par);
599 vga_out8 (0x3d4, 0x3c); 603 vga_out8 (0x3d4, 0x3c, par);
600 par->CR3C = vga_in8 (0x3d5); 604 par->CR3C = vga_in8 (0x3d5, par);
601 vga_out8 (0x3d4, 0x43); 605 vga_out8 (0x3d4, 0x43, par);
602 par->CR43 = vga_in8 (0x3d5); 606 par->CR43 = vga_in8 (0x3d5, par);
603 vga_out8 (0x3d4, 0x5d); 607 vga_out8 (0x3d4, 0x5d, par);
604 par->CR5D = vga_in8 (0x3d5); 608 par->CR5D = vga_in8 (0x3d5, par);
605 vga_out8 (0x3d4, 0x5e); 609 vga_out8 (0x3d4, 0x5e, par);
606 par->CR5E = vga_in8 (0x3d5); 610 par->CR5E = vga_in8 (0x3d5, par);
607 vga_out8 (0x3d4, 0x65); 611 vga_out8 (0x3d4, 0x65, par);
608 par->CR65 = vga_in8 (0x3d5); 612 par->CR65 = vga_in8 (0x3d5, par);
609 613
610 /* save seq extended regs for DCLK PLL programming */ 614 /* save seq extended regs for DCLK PLL programming */
611 vga_out8 (0x3c4, 0x0e); 615 vga_out8 (0x3c4, 0x0e, par);
612 par->SR0E = vga_in8 (0x3c5); 616 par->SR0E = vga_in8 (0x3c5, par);
613 vga_out8 (0x3c4, 0x0f); 617 vga_out8 (0x3c4, 0x0f, par);
614 par->SR0F = vga_in8 (0x3c5); 618 par->SR0F = vga_in8 (0x3c5, par);
615 vga_out8 (0x3c4, 0x10); 619 vga_out8 (0x3c4, 0x10, par);
616 par->SR10 = vga_in8 (0x3c5); 620 par->SR10 = vga_in8 (0x3c5, par);
617 vga_out8 (0x3c4, 0x11); 621 vga_out8 (0x3c4, 0x11, par);
618 par->SR11 = vga_in8 (0x3c5); 622 par->SR11 = vga_in8 (0x3c5, par);
619 vga_out8 (0x3c4, 0x12); 623 vga_out8 (0x3c4, 0x12, par);
620 par->SR12 = vga_in8 (0x3c5); 624 par->SR12 = vga_in8 (0x3c5, par);
621 vga_out8 (0x3c4, 0x13); 625 vga_out8 (0x3c4, 0x13, par);
622 par->SR13 = vga_in8 (0x3c5); 626 par->SR13 = vga_in8 (0x3c5, par);
623 vga_out8 (0x3c4, 0x29); 627 vga_out8 (0x3c4, 0x29, par);
624 par->SR29 = vga_in8 (0x3c5); 628 par->SR29 = vga_in8 (0x3c5, par);
625 629
626 vga_out8 (0x3c4, 0x15); 630 vga_out8 (0x3c4, 0x15, par);
627 par->SR15 = vga_in8 (0x3c5); 631 par->SR15 = vga_in8 (0x3c5, par);
628 vga_out8 (0x3c4, 0x30); 632 vga_out8 (0x3c4, 0x30, par);
629 par->SR30 = vga_in8 (0x3c5); 633 par->SR30 = vga_in8 (0x3c5, par);
630 vga_out8 (0x3c4, 0x18); 634 vga_out8 (0x3c4, 0x18, par);
631 par->SR18 = vga_in8 (0x3c5); 635 par->SR18 = vga_in8 (0x3c5, par);
632 636
633 /* Save flat panel expansion regsters. */ 637 /* Save flat panel expansion regsters. */
634 if (par->chip == S3_SAVAGE_MX) { 638 if (par->chip == S3_SAVAGE_MX) {
635 int i; 639 int i;
636 640
637 for (i = 0; i < 8; i++) { 641 for (i = 0; i < 8; i++) {
638 vga_out8 (0x3c4, 0x54+i); 642 vga_out8 (0x3c4, 0x54+i, par);
639 par->SR54[i] = vga_in8 (0x3c5); 643 par->SR54[i] = vga_in8 (0x3c5, par);
640 } 644 }
641 } 645 }
642 646
643 vga_out8 (0x3d4, 0x66); 647 vga_out8 (0x3d4, 0x66, par);
644 cr66 = vga_in8 (0x3d5); 648 cr66 = vga_in8 (0x3d5, par);
645 vga_out8 (0x3d5, cr66 | 0x80); 649 vga_out8 (0x3d5, cr66 | 0x80, par);
646 vga_out8 (0x3d4, 0x3a); 650 vga_out8 (0x3d4, 0x3a, par);
647 cr3a = vga_in8 (0x3d5); 651 cr3a = vga_in8 (0x3d5, par);
648 vga_out8 (0x3d5, cr3a | 0x80); 652 vga_out8 (0x3d5, cr3a | 0x80, par);
649 653
650 /* now save MIU regs */ 654 /* now save MIU regs */
651 if (par->chip != S3_SAVAGE_MX) { 655 if (par->chip != S3_SAVAGE_MX) {
652 par->MMPR0 = savage_in32(FIFO_CONTROL_REG); 656 par->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
653 par->MMPR1 = savage_in32(MIU_CONTROL_REG); 657 par->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
654 par->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG); 658 par->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
655 par->MMPR3 = savage_in32(MISC_TIMEOUT_REG); 659 par->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
656 } 660 }
657 661
658 vga_out8 (0x3d4, 0x3a); 662 vga_out8 (0x3d4, 0x3a, par);
659 vga_out8 (0x3d5, cr3a); 663 vga_out8 (0x3d5, cr3a, par);
660 vga_out8 (0x3d4, 0x66); 664 vga_out8 (0x3d4, 0x66, par);
661 vga_out8 (0x3d5, cr66); 665 vga_out8 (0x3d5, cr66, par);
662} 666}
663 667
664static void savage_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb) 668static void savage_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
@@ -868,8 +872,8 @@ static int savagefb_decode_var (struct fb_var_screeninfo *var,
868 * match. Fall back to traditional register-crunching. 872 * match. Fall back to traditional register-crunching.
869 */ 873 */
870 874
871 vga_out8 (0x3d4, 0x3a); 875 vga_out8 (0x3d4, 0x3a, par);
872 tmp = vga_in8 (0x3d5); 876 tmp = vga_in8 (0x3d5, par);
873 if (1 /*FIXME:psav->pci_burst*/) 877 if (1 /*FIXME:psav->pci_burst*/)
874 par->CR3A = (tmp & 0x7f) | 0x15; 878 par->CR3A = (tmp & 0x7f) | 0x15;
875 else 879 else
@@ -879,16 +883,16 @@ static int savagefb_decode_var (struct fb_var_screeninfo *var,
879 par->CR31 = 0x8c; 883 par->CR31 = 0x8c;
880 par->CR66 = 0x89; 884 par->CR66 = 0x89;
881 885
882 vga_out8 (0x3d4, 0x58); 886 vga_out8 (0x3d4, 0x58, par);
883 par->CR58 = vga_in8 (0x3d5) & 0x80; 887 par->CR58 = vga_in8 (0x3d5, par) & 0x80;
884 par->CR58 |= 0x13; 888 par->CR58 |= 0x13;
885 889
886 par->SR15 = 0x03 | 0x80; 890 par->SR15 = 0x03 | 0x80;
887 par->SR18 = 0x00; 891 par->SR18 = 0x00;
888 par->CR43 = par->CR45 = par->CR65 = 0x00; 892 par->CR43 = par->CR45 = par->CR65 = 0x00;
889 893
890 vga_out8 (0x3d4, 0x40); 894 vga_out8 (0x3d4, 0x40, par);
891 par->CR40 = vga_in8 (0x3d5) & ~0x01; 895 par->CR40 = vga_in8 (0x3d5, par) & ~0x01;
892 896
893 par->MMPR0 = 0x010400; 897 par->MMPR0 = 0x010400;
894 par->MMPR1 = 0x00; 898 par->MMPR1 = 0x00;
@@ -992,19 +996,19 @@ static int savagefb_decode_var (struct fb_var_screeninfo *var,
992 996
993 par->CR67 |= 1; 997 par->CR67 |= 1;
994 998
995 vga_out8(0x3d4, 0x36); 999 vga_out8(0x3d4, 0x36, par);
996 par->CR36 = vga_in8 (0x3d5); 1000 par->CR36 = vga_in8 (0x3d5, par);
997 vga_out8 (0x3d4, 0x68); 1001 vga_out8 (0x3d4, 0x68, par);
998 par->CR68 = vga_in8 (0x3d5); 1002 par->CR68 = vga_in8 (0x3d5, par);
999 par->CR69 = 0; 1003 par->CR69 = 0;
1000 vga_out8 (0x3d4, 0x6f); 1004 vga_out8 (0x3d4, 0x6f, par);
1001 par->CR6F = vga_in8 (0x3d5); 1005 par->CR6F = vga_in8 (0x3d5, par);
1002 vga_out8 (0x3d4, 0x86); 1006 vga_out8 (0x3d4, 0x86, par);
1003 par->CR86 = vga_in8 (0x3d5); 1007 par->CR86 = vga_in8 (0x3d5, par);
1004 vga_out8 (0x3d4, 0x88); 1008 vga_out8 (0x3d4, 0x88, par);
1005 par->CR88 = vga_in8 (0x3d5) | 0x08; 1009 par->CR88 = vga_in8 (0x3d5, par) | 0x08;
1006 vga_out8 (0x3d4, 0xb0); 1010 vga_out8 (0x3d4, 0xb0, par);
1007 par->CRB0 = vga_in8 (0x3d5) | 0x80; 1011 par->CRB0 = vga_in8 (0x3d5, par) | 0x80;
1008 1012
1009 return 0; 1013 return 0;
1010} 1014}
@@ -1033,11 +1037,11 @@ static int savagefb_setcolreg(unsigned regno,
1033 1037
1034 switch (info->var.bits_per_pixel) { 1038 switch (info->var.bits_per_pixel) {
1035 case 8: 1039 case 8:
1036 vga_out8 (0x3c8, regno); 1040 vga_out8 (0x3c8, regno, par);
1037 1041
1038 vga_out8 (0x3c9, red >> 10); 1042 vga_out8 (0x3c9, red >> 10, par);
1039 vga_out8 (0x3c9, green >> 10); 1043 vga_out8 (0x3c9, green >> 10, par);
1040 vga_out8 (0x3c9, blue >> 10); 1044 vga_out8 (0x3c9, blue >> 10, par);
1041 break; 1045 break;
1042 1046
1043 case 16: 1047 case 16:
@@ -1079,11 +1083,11 @@ static void savagefb_set_par_int (struct savagefb_par *par)
1079 1083
1080 par->SavageWaitIdle (par); 1084 par->SavageWaitIdle (par);
1081 1085
1082 vga_out8 (0x3c2, 0x23); 1086 vga_out8 (0x3c2, 0x23, par);
1083 1087
1084 vga_out16 (0x3d4, 0x4838); 1088 vga_out16 (0x3d4, 0x4838, par);
1085 vga_out16 (0x3d4, 0xa539); 1089 vga_out16 (0x3d4, 0xa539, par);
1086 vga_out16 (0x3c4, 0x0608); 1090 vga_out16 (0x3c4, 0x0608, par);
1087 1091
1088 vgaHWProtect (par, 1); 1092 vgaHWProtect (par, 1);
1089 1093
@@ -1094,197 +1098,197 @@ static void savagefb_set_par_int (struct savagefb_par *par)
1094 * switch to mode 3 here seems to eliminate the issue. 1098 * switch to mode 3 here seems to eliminate the issue.
1095 */ 1099 */
1096 1100
1097 VerticalRetraceWait(); 1101 VerticalRetraceWait(par);
1098 vga_out8 (0x3d4, 0x67); 1102 vga_out8 (0x3d4, 0x67, par);
1099 cr67 = vga_in8 (0x3d5); 1103 cr67 = vga_in8 (0x3d5, par);
1100 vga_out8 (0x3d5, cr67/*par->CR67*/ & ~0x0c); /* no STREAMS yet */ 1104 vga_out8 (0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */
1101 1105
1102 vga_out8 (0x3d4, 0x23); 1106 vga_out8 (0x3d4, 0x23, par);
1103 vga_out8 (0x3d5, 0x00); 1107 vga_out8 (0x3d5, 0x00, par);
1104 vga_out8 (0x3d4, 0x26); 1108 vga_out8 (0x3d4, 0x26, par);
1105 vga_out8 (0x3d5, 0x00); 1109 vga_out8 (0x3d5, 0x00, par);
1106 1110
1107 /* restore extended regs */ 1111 /* restore extended regs */
1108 vga_out8 (0x3d4, 0x66); 1112 vga_out8 (0x3d4, 0x66, par);
1109 vga_out8 (0x3d5, par->CR66); 1113 vga_out8 (0x3d5, par->CR66, par);
1110 vga_out8 (0x3d4, 0x3a); 1114 vga_out8 (0x3d4, 0x3a, par);
1111 vga_out8 (0x3d5, par->CR3A); 1115 vga_out8 (0x3d5, par->CR3A, par);
1112 vga_out8 (0x3d4, 0x31); 1116 vga_out8 (0x3d4, 0x31, par);
1113 vga_out8 (0x3d5, par->CR31); 1117 vga_out8 (0x3d5, par->CR31, par);
1114 vga_out8 (0x3d4, 0x32); 1118 vga_out8 (0x3d4, 0x32, par);
1115 vga_out8 (0x3d5, par->CR32); 1119 vga_out8 (0x3d5, par->CR32, par);
1116 vga_out8 (0x3d4, 0x58); 1120 vga_out8 (0x3d4, 0x58, par);
1117 vga_out8 (0x3d5, par->CR58); 1121 vga_out8 (0x3d5, par->CR58, par);
1118 vga_out8 (0x3d4, 0x53); 1122 vga_out8 (0x3d4, 0x53, par);
1119 vga_out8 (0x3d5, par->CR53 & 0x7f); 1123 vga_out8 (0x3d5, par->CR53 & 0x7f, par);
1120 1124
1121 vga_out16 (0x3c4, 0x0608); 1125 vga_out16 (0x3c4, 0x0608, par);
1122 1126
1123 /* Restore DCLK registers. */ 1127 /* Restore DCLK registers. */
1124 1128
1125 vga_out8 (0x3c4, 0x0e); 1129 vga_out8 (0x3c4, 0x0e, par);
1126 vga_out8 (0x3c5, par->SR0E); 1130 vga_out8 (0x3c5, par->SR0E, par);
1127 vga_out8 (0x3c4, 0x0f); 1131 vga_out8 (0x3c4, 0x0f, par);
1128 vga_out8 (0x3c5, par->SR0F); 1132 vga_out8 (0x3c5, par->SR0F, par);
1129 vga_out8 (0x3c4, 0x29); 1133 vga_out8 (0x3c4, 0x29, par);
1130 vga_out8 (0x3c5, par->SR29); 1134 vga_out8 (0x3c5, par->SR29, par);
1131 vga_out8 (0x3c4, 0x15); 1135 vga_out8 (0x3c4, 0x15, par);
1132 vga_out8 (0x3c5, par->SR15); 1136 vga_out8 (0x3c5, par->SR15, par);
1133 1137
1134 /* Restore flat panel expansion regsters. */ 1138 /* Restore flat panel expansion regsters. */
1135 if( par->chip == S3_SAVAGE_MX ) { 1139 if( par->chip == S3_SAVAGE_MX ) {
1136 int i; 1140 int i;
1137 1141
1138 for( i = 0; i < 8; i++ ) { 1142 for( i = 0; i < 8; i++ ) {
1139 vga_out8 (0x3c4, 0x54+i); 1143 vga_out8 (0x3c4, 0x54+i, par);
1140 vga_out8 (0x3c5, par->SR54[i]); 1144 vga_out8 (0x3c5, par->SR54[i], par);
1141 } 1145 }
1142 } 1146 }
1143 1147
1144 vgaHWRestore (par); 1148 vgaHWRestore (par);
1145 1149
1146 /* extended mode timing registers */ 1150 /* extended mode timing registers */
1147 vga_out8 (0x3d4, 0x53); 1151 vga_out8 (0x3d4, 0x53, par);
1148 vga_out8 (0x3d5, par->CR53); 1152 vga_out8 (0x3d5, par->CR53, par);
1149 vga_out8 (0x3d4, 0x5d); 1153 vga_out8 (0x3d4, 0x5d, par);
1150 vga_out8 (0x3d5, par->CR5D); 1154 vga_out8 (0x3d5, par->CR5D, par);
1151 vga_out8 (0x3d4, 0x5e); 1155 vga_out8 (0x3d4, 0x5e, par);
1152 vga_out8 (0x3d5, par->CR5E); 1156 vga_out8 (0x3d5, par->CR5E, par);
1153 vga_out8 (0x3d4, 0x3b); 1157 vga_out8 (0x3d4, 0x3b, par);
1154 vga_out8 (0x3d5, par->CR3B); 1158 vga_out8 (0x3d5, par->CR3B, par);
1155 vga_out8 (0x3d4, 0x3c); 1159 vga_out8 (0x3d4, 0x3c, par);
1156 vga_out8 (0x3d5, par->CR3C); 1160 vga_out8 (0x3d5, par->CR3C, par);
1157 vga_out8 (0x3d4, 0x43); 1161 vga_out8 (0x3d4, 0x43, par);
1158 vga_out8 (0x3d5, par->CR43); 1162 vga_out8 (0x3d5, par->CR43, par);
1159 vga_out8 (0x3d4, 0x65); 1163 vga_out8 (0x3d4, 0x65, par);
1160 vga_out8 (0x3d5, par->CR65); 1164 vga_out8 (0x3d5, par->CR65, par);
1161 1165
1162 /* restore the desired video mode with cr67 */ 1166 /* restore the desired video mode with cr67 */
1163 vga_out8 (0x3d4, 0x67); 1167 vga_out8 (0x3d4, 0x67, par);
1164 /* following part not present in X11 driver */ 1168 /* following part not present in X11 driver */
1165 cr67 = vga_in8 (0x3d5) & 0xf; 1169 cr67 = vga_in8 (0x3d5, par) & 0xf;
1166 vga_out8 (0x3d5, 0x50 | cr67); 1170 vga_out8 (0x3d5, 0x50 | cr67, par);
1167 udelay (10000); 1171 udelay (10000);
1168 vga_out8 (0x3d4, 0x67); 1172 vga_out8 (0x3d4, 0x67, par);
1169 /* end of part */ 1173 /* end of part */
1170 vga_out8 (0x3d5, par->CR67 & ~0x0c); 1174 vga_out8 (0x3d5, par->CR67 & ~0x0c, par);
1171 1175
1172 /* other mode timing and extended regs */ 1176 /* other mode timing and extended regs */
1173 vga_out8 (0x3d4, 0x34); 1177 vga_out8 (0x3d4, 0x34, par);
1174 vga_out8 (0x3d5, par->CR34); 1178 vga_out8 (0x3d5, par->CR34, par);
1175 vga_out8 (0x3d4, 0x40); 1179 vga_out8 (0x3d4, 0x40, par);
1176 vga_out8 (0x3d5, par->CR40); 1180 vga_out8 (0x3d5, par->CR40, par);
1177 vga_out8 (0x3d4, 0x42); 1181 vga_out8 (0x3d4, 0x42, par);
1178 vga_out8 (0x3d5, par->CR42); 1182 vga_out8 (0x3d5, par->CR42, par);
1179 vga_out8 (0x3d4, 0x45); 1183 vga_out8 (0x3d4, 0x45, par);
1180 vga_out8 (0x3d5, par->CR45); 1184 vga_out8 (0x3d5, par->CR45, par);
1181 vga_out8 (0x3d4, 0x50); 1185 vga_out8 (0x3d4, 0x50, par);
1182 vga_out8 (0x3d5, par->CR50); 1186 vga_out8 (0x3d5, par->CR50, par);
1183 vga_out8 (0x3d4, 0x51); 1187 vga_out8 (0x3d4, 0x51, par);
1184 vga_out8 (0x3d5, par->CR51); 1188 vga_out8 (0x3d5, par->CR51, par);
1185 1189
1186 /* memory timings */ 1190 /* memory timings */
1187 vga_out8 (0x3d4, 0x36); 1191 vga_out8 (0x3d4, 0x36, par);
1188 vga_out8 (0x3d5, par->CR36); 1192 vga_out8 (0x3d5, par->CR36, par);
1189 vga_out8 (0x3d4, 0x60); 1193 vga_out8 (0x3d4, 0x60, par);
1190 vga_out8 (0x3d5, par->CR60); 1194 vga_out8 (0x3d5, par->CR60, par);
1191 vga_out8 (0x3d4, 0x68); 1195 vga_out8 (0x3d4, 0x68, par);
1192 vga_out8 (0x3d5, par->CR68); 1196 vga_out8 (0x3d5, par->CR68, par);
1193 vga_out8 (0x3d4, 0x69); 1197 vga_out8 (0x3d4, 0x69, par);
1194 vga_out8 (0x3d5, par->CR69); 1198 vga_out8 (0x3d5, par->CR69, par);
1195 vga_out8 (0x3d4, 0x6f); 1199 vga_out8 (0x3d4, 0x6f, par);
1196 vga_out8 (0x3d5, par->CR6F); 1200 vga_out8 (0x3d5, par->CR6F, par);
1197 1201
1198 vga_out8 (0x3d4, 0x33); 1202 vga_out8 (0x3d4, 0x33, par);
1199 vga_out8 (0x3d5, par->CR33); 1203 vga_out8 (0x3d5, par->CR33, par);
1200 vga_out8 (0x3d4, 0x86); 1204 vga_out8 (0x3d4, 0x86, par);
1201 vga_out8 (0x3d5, par->CR86); 1205 vga_out8 (0x3d5, par->CR86, par);
1202 vga_out8 (0x3d4, 0x88); 1206 vga_out8 (0x3d4, 0x88, par);
1203 vga_out8 (0x3d5, par->CR88); 1207 vga_out8 (0x3d5, par->CR88, par);
1204 vga_out8 (0x3d4, 0x90); 1208 vga_out8 (0x3d4, 0x90, par);
1205 vga_out8 (0x3d5, par->CR90); 1209 vga_out8 (0x3d5, par->CR90, par);
1206 vga_out8 (0x3d4, 0x91); 1210 vga_out8 (0x3d4, 0x91, par);
1207 vga_out8 (0x3d5, par->CR91); 1211 vga_out8 (0x3d5, par->CR91, par);
1208 1212
1209 if (par->chip == S3_SAVAGE4) { 1213 if (par->chip == S3_SAVAGE4) {
1210 vga_out8 (0x3d4, 0xb0); 1214 vga_out8 (0x3d4, 0xb0, par);
1211 vga_out8 (0x3d5, par->CRB0); 1215 vga_out8 (0x3d5, par->CRB0, par);
1212 } 1216 }
1213 1217
1214 vga_out8 (0x3d4, 0x32); 1218 vga_out8 (0x3d4, 0x32, par);
1215 vga_out8 (0x3d5, par->CR32); 1219 vga_out8 (0x3d5, par->CR32, par);
1216 1220
1217 /* unlock extended seq regs */ 1221 /* unlock extended seq regs */
1218 vga_out8 (0x3c4, 0x08); 1222 vga_out8 (0x3c4, 0x08, par);
1219 vga_out8 (0x3c5, 0x06); 1223 vga_out8 (0x3c5, 0x06, par);
1220 1224
1221 /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates 1225 /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates
1222 * that we should leave the default SR10 and SR11 values there. 1226 * that we should leave the default SR10 and SR11 values there.
1223 */ 1227 */
1224 if (par->SR10 != 255) { 1228 if (par->SR10 != 255) {
1225 vga_out8 (0x3c4, 0x10); 1229 vga_out8 (0x3c4, 0x10, par);
1226 vga_out8 (0x3c5, par->SR10); 1230 vga_out8 (0x3c5, par->SR10, par);
1227 vga_out8 (0x3c4, 0x11); 1231 vga_out8 (0x3c4, 0x11, par);
1228 vga_out8 (0x3c5, par->SR11); 1232 vga_out8 (0x3c5, par->SR11, par);
1229 } 1233 }
1230 1234
1231 /* restore extended seq regs for dclk */ 1235 /* restore extended seq regs for dclk */
1232 vga_out8 (0x3c4, 0x0e); 1236 vga_out8 (0x3c4, 0x0e, par);
1233 vga_out8 (0x3c5, par->SR0E); 1237 vga_out8 (0x3c5, par->SR0E, par);
1234 vga_out8 (0x3c4, 0x0f); 1238 vga_out8 (0x3c4, 0x0f, par);
1235 vga_out8 (0x3c5, par->SR0F); 1239 vga_out8 (0x3c5, par->SR0F, par);
1236 vga_out8 (0x3c4, 0x12); 1240 vga_out8 (0x3c4, 0x12, par);
1237 vga_out8 (0x3c5, par->SR12); 1241 vga_out8 (0x3c5, par->SR12, par);
1238 vga_out8 (0x3c4, 0x13); 1242 vga_out8 (0x3c4, 0x13, par);
1239 vga_out8 (0x3c5, par->SR13); 1243 vga_out8 (0x3c5, par->SR13, par);
1240 vga_out8 (0x3c4, 0x29); 1244 vga_out8 (0x3c4, 0x29, par);
1241 vga_out8 (0x3c5, par->SR29); 1245 vga_out8 (0x3c5, par->SR29, par);
1242 1246
1243 vga_out8 (0x3c4, 0x18); 1247 vga_out8 (0x3c4, 0x18, par);
1244 vga_out8 (0x3c5, par->SR18); 1248 vga_out8 (0x3c5, par->SR18, par);
1245 1249
1246 /* load new m, n pll values for dclk & mclk */ 1250 /* load new m, n pll values for dclk & mclk */
1247 vga_out8 (0x3c4, 0x15); 1251 vga_out8 (0x3c4, 0x15, par);
1248 tmp = vga_in8 (0x3c5) & ~0x21; 1252 tmp = vga_in8 (0x3c5, par) & ~0x21;
1249 1253
1250 vga_out8 (0x3c5, tmp | 0x03); 1254 vga_out8 (0x3c5, tmp | 0x03, par);
1251 vga_out8 (0x3c5, tmp | 0x23); 1255 vga_out8 (0x3c5, tmp | 0x23, par);
1252 vga_out8 (0x3c5, tmp | 0x03); 1256 vga_out8 (0x3c5, tmp | 0x03, par);
1253 vga_out8 (0x3c5, par->SR15); 1257 vga_out8 (0x3c5, par->SR15, par);
1254 udelay (100); 1258 udelay (100);
1255 1259
1256 vga_out8 (0x3c4, 0x30); 1260 vga_out8 (0x3c4, 0x30, par);
1257 vga_out8 (0x3c5, par->SR30); 1261 vga_out8 (0x3c5, par->SR30, par);
1258 vga_out8 (0x3c4, 0x08); 1262 vga_out8 (0x3c4, 0x08, par);
1259 vga_out8 (0x3c5, par->SR08); 1263 vga_out8 (0x3c5, par->SR08, par);
1260 1264
1261 /* now write out cr67 in full, possibly starting STREAMS */ 1265 /* now write out cr67 in full, possibly starting STREAMS */
1262 VerticalRetraceWait(); 1266 VerticalRetraceWait(par);
1263 vga_out8 (0x3d4, 0x67); 1267 vga_out8 (0x3d4, 0x67, par);
1264 vga_out8 (0x3d5, par->CR67); 1268 vga_out8 (0x3d5, par->CR67, par);
1265 1269
1266 vga_out8 (0x3d4, 0x66); 1270 vga_out8 (0x3d4, 0x66, par);
1267 cr66 = vga_in8 (0x3d5); 1271 cr66 = vga_in8 (0x3d5, par);
1268 vga_out8 (0x3d5, cr66 | 0x80); 1272 vga_out8 (0x3d5, cr66 | 0x80, par);
1269 vga_out8 (0x3d4, 0x3a); 1273 vga_out8 (0x3d4, 0x3a, par);
1270 cr3a = vga_in8 (0x3d5); 1274 cr3a = vga_in8 (0x3d5, par);
1271 vga_out8 (0x3d5, cr3a | 0x80); 1275 vga_out8 (0x3d5, cr3a | 0x80, par);
1272 1276
1273 if (par->chip != S3_SAVAGE_MX) { 1277 if (par->chip != S3_SAVAGE_MX) {
1274 VerticalRetraceWait(); 1278 VerticalRetraceWait(par);
1275 savage_out32 (FIFO_CONTROL_REG, par->MMPR0); 1279 savage_out32 (FIFO_CONTROL_REG, par->MMPR0, par);
1276 par->SavageWaitIdle (par); 1280 par->SavageWaitIdle (par);
1277 savage_out32 (MIU_CONTROL_REG, par->MMPR1); 1281 savage_out32 (MIU_CONTROL_REG, par->MMPR1, par);
1278 par->SavageWaitIdle (par); 1282 par->SavageWaitIdle (par);
1279 savage_out32 (STREAMS_TIMEOUT_REG, par->MMPR2); 1283 savage_out32 (STREAMS_TIMEOUT_REG, par->MMPR2, par);
1280 par->SavageWaitIdle (par); 1284 par->SavageWaitIdle (par);
1281 savage_out32 (MISC_TIMEOUT_REG, par->MMPR3); 1285 savage_out32 (MISC_TIMEOUT_REG, par->MMPR3, par);
1282 } 1286 }
1283 1287
1284 vga_out8 (0x3d4, 0x66); 1288 vga_out8 (0x3d4, 0x66, par);
1285 vga_out8 (0x3d5, cr66); 1289 vga_out8 (0x3d5, cr66, par);
1286 vga_out8 (0x3d4, 0x3a); 1290 vga_out8 (0x3d4, 0x3a, par);
1287 vga_out8 (0x3d5, cr3a); 1291 vga_out8 (0x3d5, cr3a, par);
1288 1292
1289 SavageSetup2DEngine (par); 1293 SavageSetup2DEngine (par);
1290 vgaHWProtect (par, 0); 1294 vgaHWProtect (par, 0);
@@ -1299,10 +1303,10 @@ static void savagefb_update_start (struct savagefb_par *par,
1299 * ((var->bits_per_pixel+7) / 8)) >> 2; 1303 * ((var->bits_per_pixel+7) / 8)) >> 2;
1300 1304
1301 /* now program the start address registers */ 1305 /* now program the start address registers */
1302 vga_out16(0x3d4, (base & 0x00ff00) | 0x0c); 1306 vga_out16(0x3d4, (base & 0x00ff00) | 0x0c, par);
1303 vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d); 1307 vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d, par);
1304 vga_out8 (0x3d4, 0x69); 1308 vga_out8 (0x3d4, 0x69, par);
1305 vga_out8 (0x3d5, (base & 0x7f0000) >> 16); 1309 vga_out8 (0x3d5, (base & 0x7f0000) >> 16, par);
1306} 1310}
1307 1311
1308 1312
@@ -1406,12 +1410,12 @@ static int savagefb_blank(int blank, struct fb_info *info)
1406 u8 sr8 = 0, srd = 0; 1410 u8 sr8 = 0, srd = 0;
1407 1411
1408 if (par->display_type == DISP_CRT) { 1412 if (par->display_type == DISP_CRT) {
1409 vga_out8(0x3c4, 0x08); 1413 vga_out8(0x3c4, 0x08, par);
1410 sr8 = vga_in8(0x3c5); 1414 sr8 = vga_in8(0x3c5, par);
1411 sr8 |= 0x06; 1415 sr8 |= 0x06;
1412 vga_out8(0x3c5, sr8); 1416 vga_out8(0x3c5, sr8, par);
1413 vga_out8(0x3c4, 0x0d); 1417 vga_out8(0x3c4, 0x0d, par);
1414 srd = vga_in8(0x3c5); 1418 srd = vga_in8(0x3c5, par);
1415 srd &= 0x03; 1419 srd &= 0x03;
1416 1420
1417 switch (blank) { 1421 switch (blank) {
@@ -1429,8 +1433,8 @@ static int savagefb_blank(int blank, struct fb_info *info)
1429 break; 1433 break;
1430 } 1434 }
1431 1435
1432 vga_out8(0x3c4, 0x0d); 1436 vga_out8(0x3c4, 0x0d, par);
1433 vga_out8(0x3c5, srd); 1437 vga_out8(0x3c5, srd, par);
1434 } 1438 }
1435 1439
1436 if (par->display_type == DISP_LCD || 1440 if (par->display_type == DISP_LCD ||
@@ -1438,14 +1442,14 @@ static int savagefb_blank(int blank, struct fb_info *info)
1438 switch(blank) { 1442 switch(blank) {
1439 case FB_BLANK_UNBLANK: 1443 case FB_BLANK_UNBLANK:
1440 case FB_BLANK_NORMAL: 1444 case FB_BLANK_NORMAL:
1441 vga_out8(0x3c4, 0x31); /* SR31 bit 4 - FP enable */ 1445 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1442 vga_out8(0x3c5, vga_in8(0x3c5) | 0x10); 1446 vga_out8(0x3c5, vga_in8(0x3c5, par) | 0x10, par);
1443 break; 1447 break;
1444 case FB_BLANK_VSYNC_SUSPEND: 1448 case FB_BLANK_VSYNC_SUSPEND:
1445 case FB_BLANK_HSYNC_SUSPEND: 1449 case FB_BLANK_HSYNC_SUSPEND:
1446 case FB_BLANK_POWERDOWN: 1450 case FB_BLANK_POWERDOWN:
1447 vga_out8(0x3c4, 0x31); /* SR31 bit 4 - FP enable */ 1451 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1448 vga_out8(0x3c5, vga_in8(0x3c5) & ~0x10); 1452 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x10, par);
1449 break; 1453 break;
1450 } 1454 }
1451 } 1455 }
@@ -1498,15 +1502,15 @@ static void savage_enable_mmio (struct savagefb_par *par)
1498 1502
1499 DBG ("savage_enable_mmio\n"); 1503 DBG ("savage_enable_mmio\n");
1500 1504
1501 val = vga_in8 (0x3c3); 1505 val = vga_in8 (0x3c3, par);
1502 vga_out8 (0x3c3, val | 0x01); 1506 vga_out8 (0x3c3, val | 0x01, par);
1503 val = vga_in8 (0x3cc); 1507 val = vga_in8 (0x3cc, par);
1504 vga_out8 (0x3c2, val | 0x01); 1508 vga_out8 (0x3c2, val | 0x01, par);
1505 1509
1506 if (par->chip >= S3_SAVAGE4) { 1510 if (par->chip >= S3_SAVAGE4) {
1507 vga_out8 (0x3d4, 0x40); 1511 vga_out8 (0x3d4, 0x40, par);
1508 val = vga_in8 (0x3d5); 1512 val = vga_in8 (0x3d5, par);
1509 vga_out8 (0x3d5, val | 1); 1513 vga_out8 (0x3d5, val | 1, par);
1510 } 1514 }
1511} 1515}
1512 1516
@@ -1518,9 +1522,9 @@ static void savage_disable_mmio (struct savagefb_par *par)
1518 DBG ("savage_disable_mmio\n"); 1522 DBG ("savage_disable_mmio\n");
1519 1523
1520 if(par->chip >= S3_SAVAGE4 ) { 1524 if(par->chip >= S3_SAVAGE4 ) {
1521 vga_out8 (0x3d4, 0x40); 1525 vga_out8 (0x3d4, 0x40, par);
1522 val = vga_in8 (0x3d5); 1526 val = vga_in8 (0x3d5, par);
1523 vga_out8 (0x3d5, val | 1); 1527 vga_out8 (0x3d5, val | 1, par);
1524 } 1528 }
1525} 1529}
1526 1530
@@ -1640,30 +1644,30 @@ static int __devinit savage_init_hw (struct savagefb_par *par)
1640 DBG("savage_init_hw"); 1644 DBG("savage_init_hw");
1641 1645
1642 /* unprotect CRTC[0-7] */ 1646 /* unprotect CRTC[0-7] */
1643 vga_out8(0x3d4, 0x11); 1647 vga_out8(0x3d4, 0x11, par);
1644 tmp = vga_in8(0x3d5); 1648 tmp = vga_in8(0x3d5, par);
1645 vga_out8(0x3d5, tmp & 0x7f); 1649 vga_out8(0x3d5, tmp & 0x7f, par);
1646 1650
1647 /* unlock extended regs */ 1651 /* unlock extended regs */
1648 vga_out16(0x3d4, 0x4838); 1652 vga_out16(0x3d4, 0x4838, par);
1649 vga_out16(0x3d4, 0xa039); 1653 vga_out16(0x3d4, 0xa039, par);
1650 vga_out16(0x3c4, 0x0608); 1654 vga_out16(0x3c4, 0x0608, par);
1651 1655
1652 vga_out8(0x3d4, 0x40); 1656 vga_out8(0x3d4, 0x40, par);
1653 tmp = vga_in8(0x3d5); 1657 tmp = vga_in8(0x3d5, par);
1654 vga_out8(0x3d5, tmp & ~0x01); 1658 vga_out8(0x3d5, tmp & ~0x01, par);
1655 1659
1656 /* unlock sys regs */ 1660 /* unlock sys regs */
1657 vga_out8(0x3d4, 0x38); 1661 vga_out8(0x3d4, 0x38, par);
1658 vga_out8(0x3d5, 0x48); 1662 vga_out8(0x3d5, 0x48, par);
1659 1663
1660 /* Unlock system registers. */ 1664 /* Unlock system registers. */
1661 vga_out16(0x3d4, 0x4838); 1665 vga_out16(0x3d4, 0x4838, par);
1662 1666
1663 /* Next go on to detect amount of installed ram */ 1667 /* Next go on to detect amount of installed ram */
1664 1668
1665 vga_out8(0x3d4, 0x36); /* for register CR36 (CONFG_REG1), */ 1669 vga_out8(0x3d4, 0x36, par); /* for register CR36 (CONFG_REG1), */
1666 config1 = vga_in8(0x3d5); /* get amount of vram installed */ 1670 config1 = vga_in8(0x3d5, par); /* get amount of vram installed */
1667 1671
1668 /* Compute the amount of video memory and offscreen memory. */ 1672 /* Compute the amount of video memory and offscreen memory. */
1669 1673
@@ -1679,8 +1683,8 @@ static int __devinit savage_init_hw (struct savagefb_par *par)
1679 * when it really means 8MB. Why do it the same when you 1683 * when it really means 8MB. Why do it the same when you
1680 * can do it different... 1684 * can do it different...
1681 */ 1685 */
1682 vga_out8(0x3d4, 0x68); /* memory control 1 */ 1686 vga_out8(0x3d4, 0x68, par); /* memory control 1 */
1683 if( (vga_in8(0x3d5) & 0xC0) == (0x01 << 6) ) 1687 if( (vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6) )
1684 RamSavage4[1] = 8; 1688 RamSavage4[1] = 8;
1685 1689
1686 /*FALLTHROUGH*/ 1690 /*FALLTHROUGH*/
@@ -1709,13 +1713,13 @@ static int __devinit savage_init_hw (struct savagefb_par *par)
1709 printk (KERN_INFO "savagefb: probed videoram: %dk\n", videoRam); 1713 printk (KERN_INFO "savagefb: probed videoram: %dk\n", videoRam);
1710 1714
1711 /* reset graphics engine to avoid memory corruption */ 1715 /* reset graphics engine to avoid memory corruption */
1712 vga_out8 (0x3d4, 0x66); 1716 vga_out8 (0x3d4, 0x66, par);
1713 cr66 = vga_in8 (0x3d5); 1717 cr66 = vga_in8 (0x3d5, par);
1714 vga_out8 (0x3d5, cr66 | 0x02); 1718 vga_out8 (0x3d5, cr66 | 0x02, par);
1715 udelay (10000); 1719 udelay (10000);
1716 1720
1717 vga_out8 (0x3d4, 0x66); 1721 vga_out8 (0x3d4, 0x66, par);
1718 vga_out8 (0x3d5, cr66 & ~0x02); /* clear reset flag */ 1722 vga_out8 (0x3d5, cr66 & ~0x02, par); /* clear reset flag */
1719 udelay (10000); 1723 udelay (10000);
1720 1724
1721 1725
@@ -1723,13 +1727,13 @@ static int __devinit savage_init_hw (struct savagefb_par *par)
1723 * reset memory interface, 3D engine, AGP master, PCI master, 1727 * reset memory interface, 3D engine, AGP master, PCI master,
1724 * master engine unit, motion compensation/LPB 1728 * master engine unit, motion compensation/LPB
1725 */ 1729 */
1726 vga_out8 (0x3d4, 0x3f); 1730 vga_out8 (0x3d4, 0x3f, par);
1727 cr3f = vga_in8 (0x3d5); 1731 cr3f = vga_in8 (0x3d5, par);
1728 vga_out8 (0x3d5, cr3f | 0x08); 1732 vga_out8 (0x3d5, cr3f | 0x08, par);
1729 udelay (10000); 1733 udelay (10000);
1730 1734
1731 vga_out8 (0x3d4, 0x3f); 1735 vga_out8 (0x3d4, 0x3f, par);
1732 vga_out8 (0x3d5, cr3f & ~0x08); /* clear reset flags */ 1736 vga_out8 (0x3d5, cr3f & ~0x08, par); /* clear reset flags */
1733 udelay (10000); 1737 udelay (10000);
1734 1738
1735 /* Savage ramdac speeds */ 1739 /* Savage ramdac speeds */
@@ -1740,15 +1744,15 @@ static int __devinit savage_init_hw (struct savagefb_par *par)
1740 par->clock[3] = 220000; 1744 par->clock[3] = 220000;
1741 1745
1742 /* detect current mclk */ 1746 /* detect current mclk */
1743 vga_out8(0x3c4, 0x08); 1747 vga_out8(0x3c4, 0x08, par);
1744 sr8 = vga_in8(0x3c5); 1748 sr8 = vga_in8(0x3c5, par);
1745 vga_out8(0x3c5, 0x06); 1749 vga_out8(0x3c5, 0x06, par);
1746 vga_out8(0x3c4, 0x10); 1750 vga_out8(0x3c4, 0x10, par);
1747 n = vga_in8(0x3c5); 1751 n = vga_in8(0x3c5, par);
1748 vga_out8(0x3c4, 0x11); 1752 vga_out8(0x3c4, 0x11, par);
1749 m = vga_in8(0x3c5); 1753 m = vga_in8(0x3c5, par);
1750 vga_out8(0x3c4, 0x08); 1754 vga_out8(0x3c4, 0x08, par);
1751 vga_out8(0x3c5, sr8); 1755 vga_out8(0x3c5, sr8, par);
1752 m &= 0x7f; 1756 m &= 0x7f;
1753 n1 = n & 0x1f; 1757 n1 = n & 0x1f;
1754 n2 = (n >> 5) & 0x03; 1758 n2 = (n >> 5) & 0x03;
@@ -1762,10 +1766,10 @@ static int __devinit savage_init_hw (struct savagefb_par *par)
1762 if (par->chip == S3_SAVAGE4) { 1766 if (par->chip == S3_SAVAGE4) {
1763 unsigned char sr30 = 0x00; 1767 unsigned char sr30 = 0x00;
1764 1768
1765 vga_out8(0x3c4, 0x30); 1769 vga_out8(0x3c4, 0x30, par);
1766 /* clear bit 1 */ 1770 /* clear bit 1 */
1767 vga_out8(0x3c5, vga_in8(0x3c5) & ~0x02); 1771 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x02, par);
1768 sr30 = vga_in8(0x3c5); 1772 sr30 = vga_in8(0x3c5, par);
1769 if (sr30 & 0x02 /*0x04 */) { 1773 if (sr30 & 0x02 /*0x04 */) {
1770 dvi = 1; 1774 dvi = 1;
1771 printk("savagefb: Digital Flat Panel Detected\n"); 1775 printk("savagefb: Digital Flat Panel Detected\n");
@@ -1782,12 +1786,12 @@ static int __devinit savage_init_hw (struct savagefb_par *par)
1782 /* Check LCD panel parrmation */ 1786 /* Check LCD panel parrmation */
1783 1787
1784 if (par->display_type == DISP_LCD) { 1788 if (par->display_type == DISP_LCD) {
1785 unsigned char cr6b = VGArCR( 0x6b ); 1789 unsigned char cr6b = VGArCR( 0x6b, par);
1786 1790
1787 int panelX = (VGArSEQ (0x61) + 1791 int panelX = (VGArSEQ (0x61, par) +
1788 ((VGArSEQ (0x66) & 0x02) << 7) + 1) * 8; 1792 ((VGArSEQ (0x66, par) & 0x02) << 7) + 1) * 8;
1789 int panelY = (VGArSEQ (0x69) + 1793 int panelY = (VGArSEQ (0x69, par) +
1790 ((VGArSEQ (0x6e) & 0x70) << 4) + 1); 1794 ((VGArSEQ (0x6e, par) & 0x70) << 4) + 1);
1791 1795
1792 char * sTechnology = "Unknown"; 1796 char * sTechnology = "Unknown";
1793 1797
@@ -1809,9 +1813,9 @@ static int __devinit savage_init_hw (struct savagefb_par *par)
1809 ActiveDUO = 0x80 1813 ActiveDUO = 0x80
1810 }; 1814 };
1811 1815
1812 if ((VGArSEQ (0x39) & 0x03) == 0) { 1816 if ((VGArSEQ (0x39, par) & 0x03) == 0) {
1813 sTechnology = "TFT"; 1817 sTechnology = "TFT";
1814 } else if ((VGArSEQ (0x30) & 0x01) == 0) { 1818 } else if ((VGArSEQ (0x30, par) & 0x01) == 0) {
1815 sTechnology = "DSTN"; 1819 sTechnology = "DSTN";
1816 } else { 1820 } else {
1817 sTechnology = "STN"; 1821 sTechnology = "STN";
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 00:49:50 -0500