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-rw-r--r--drivers/video/geode/Kconfig17
-rw-r--r--drivers/video/geode/Makefile4
-rw-r--r--drivers/video/geode/display_gx.c156
-rw-r--r--drivers/video/geode/display_gx.h96
-rw-r--r--drivers/video/geode/gxfb_core.c423
-rw-r--r--drivers/video/geode/video_gx.c262
-rw-r--r--drivers/video/geode/video_gx.h47
7 files changed, 1003 insertions, 2 deletions
diff --git a/drivers/video/geode/Kconfig b/drivers/video/geode/Kconfig
index 42fb9a89a792..4e173ef20a7d 100644
--- a/drivers/video/geode/Kconfig
+++ b/drivers/video/geode/Kconfig
@@ -8,9 +8,24 @@ config FB_GEODE
8 Say 'Y' here to allow you to select framebuffer drivers for 8 Say 'Y' here to allow you to select framebuffer drivers for
9 the AMD Geode family of processors. 9 the AMD Geode family of processors.
10 10
11config FB_GEODE_GX
12 tristate "AMD Geode GX framebuffer support (EXPERIMENTAL)"
13 depends on FB && FB_GEODE && EXPERIMENTAL
14 select FB_CFB_FILLRECT
15 select FB_CFB_COPYAREA
16 select FB_CFB_IMAGEBLIT
17 ---help---
18 Framebuffer driver for the display controller integrated into the
19 AMD Geode GX processors.
20
21 To compile this driver as a module, choose M here: the module will be
22 called gxfb.
23
24 If unsure, say N.
25
11config FB_GEODE_GX1 26config FB_GEODE_GX1
12 tristate "AMD Geode GX1 framebuffer support (EXPERIMENTAL)" 27 tristate "AMD Geode GX1 framebuffer support (EXPERIMENTAL)"
13 depends on FB_GEODE && EXPERIMENTAL 28 depends on FB && FB_GEODE && EXPERIMENTAL
14 select FB_CFB_FILLRECT 29 select FB_CFB_FILLRECT
15 select FB_CFB_COPYAREA 30 select FB_CFB_COPYAREA
16 select FB_CFB_IMAGEBLIT 31 select FB_CFB_IMAGEBLIT
diff --git a/drivers/video/geode/Makefile b/drivers/video/geode/Makefile
index 13ad501ea990..f896565bc312 100644
--- a/drivers/video/geode/Makefile
+++ b/drivers/video/geode/Makefile
@@ -1,5 +1,7 @@
1# Makefile for the Geode family framebuffer drivers 1# Makefile for the Geode family framebuffer drivers
2 2
3obj-$(CONFIG_FB_GEODE_GX1) += gx1fb.o 3obj-$(CONFIG_FB_GEODE_GX1) += gx1fb.o
4obj-$(CONFIG_FB_GEODE_GX) += gxfb.o
4 5
5gx1fb-objs := gx1fb_core.o display_gx1.o video_cs5530.o 6gx1fb-objs := gx1fb_core.o display_gx1.o video_cs5530.o
7gxfb-objs := gxfb_core.o display_gx.o video_gx.o
diff --git a/drivers/video/geode/display_gx.c b/drivers/video/geode/display_gx.c
new file mode 100644
index 000000000000..825c3405f5c2
--- /dev/null
+++ b/drivers/video/geode/display_gx.c
@@ -0,0 +1,156 @@
1/*
2 * Geode GX display controller.
3 *
4 * Copyright (C) 2005 Arcom Control Systems Ltd.
5 *
6 * Portions from AMD's original 2.4 driver:
7 * Copyright (C) 2004 Advanced Micro Devices, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by * the
11 * Free Software Foundation; either version 2 of the License, or * (at your
12 * option) any later version.
13 */
14#include <linux/spinlock.h>
15#include <linux/fb.h>
16#include <linux/delay.h>
17#include <asm/io.h>
18#include <asm/div64.h>
19#include <asm/delay.h>
20
21#include "geodefb.h"
22#include "display_gx.h"
23
24int gx_frame_buffer_size(void)
25{
26 /* Assuming 16 MiB. */
27 return 16*1024*1024;
28}
29
30int gx_line_delta(int xres, int bpp)
31{
32 /* Must be a multiple of 8 bytes. */
33 return (xres * (bpp >> 3) + 7) & ~0x7;
34}
35
36static void gx_set_mode(struct fb_info *info)
37{
38 struct geodefb_par *par = info->par;
39 u32 gcfg, dcfg;
40 int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
41 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
42
43 /* Unlock the display controller registers. */
44 readl(par->dc_regs + DC_UNLOCK);
45 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
46
47 gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
48 dcfg = readl(par->dc_regs + DC_DISPLAY_CFG);
49
50 /* Disable the timing generator. */
51 dcfg &= ~(DC_DCFG_TGEN);
52 writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
53
54 /* Wait for pending memory requests before disabling the FIFO load. */
55 udelay(100);
56
57 /* Disable FIFO load and compression. */
58 gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
59 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
60
61 /* Setup DCLK and its divisor. */
62 par->vid_ops->set_dclk(info);
63
64 /*
65 * Setup new mode.
66 */
67
68 /* Clear all unused feature bits. */
69 gcfg &= DC_GCFG_YUVM | DC_GCFG_VDSE;
70 dcfg = 0;
71
72 /* Set FIFO priority (default 6/5) and enable. */
73 /* FIXME: increase fifo priority for 1280x1024 and higher modes? */
74 gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
75
76 /* Framebuffer start offset. */
77 writel(0, par->dc_regs + DC_FB_ST_OFFSET);
78
79 /* Line delta and line buffer length. */
80 writel(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH);
81 writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
82 par->dc_regs + DC_LINE_SIZE);
83
84 /* Enable graphics and video data and unmask address lines. */
85 dcfg |= DC_DCFG_GDEN | DC_DCFG_VDEN | DC_DCFG_A20M | DC_DCFG_A18M;
86
87 /* Set pixel format. */
88 switch (info->var.bits_per_pixel) {
89 case 8:
90 dcfg |= DC_DCFG_DISP_MODE_8BPP;
91 break;
92 case 16:
93 dcfg |= DC_DCFG_DISP_MODE_16BPP;
94 dcfg |= DC_DCFG_16BPP_MODE_565;
95 break;
96 case 32:
97 dcfg |= DC_DCFG_DISP_MODE_24BPP;
98 dcfg |= DC_DCFG_PALB;
99 break;
100 }
101
102 /* Enable timing generator. */
103 dcfg |= DC_DCFG_TGEN;
104
105 /* Horizontal and vertical timings. */
106 hactive = info->var.xres;
107 hblankstart = hactive;
108 hsyncstart = hblankstart + info->var.right_margin;
109 hsyncend = hsyncstart + info->var.hsync_len;
110 hblankend = hsyncend + info->var.left_margin;
111 htotal = hblankend;
112
113 vactive = info->var.yres;
114 vblankstart = vactive;
115 vsyncstart = vblankstart + info->var.lower_margin;
116 vsyncend = vsyncstart + info->var.vsync_len;
117 vblankend = vsyncend + info->var.upper_margin;
118 vtotal = vblankend;
119
120 writel((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING);
121 writel((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING);
122 writel((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING);
123
124 writel((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING);
125 writel((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING);
126 writel((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING);
127
128 /* Write final register values. */
129 writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
130 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
131
132 par->vid_ops->configure_display(info);
133
134 /* Relock display controller registers */
135 writel(0, par->dc_regs + DC_UNLOCK);
136}
137
138static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
139 unsigned red, unsigned green, unsigned blue)
140{
141 struct geodefb_par *par = info->par;
142 int val;
143
144 /* Hardware palette is in RGB 8-8-8 format. */
145 val = (red << 8) & 0xff0000;
146 val |= (green) & 0x00ff00;
147 val |= (blue >> 8) & 0x0000ff;
148
149 writel(regno, par->dc_regs + DC_PAL_ADDRESS);
150 writel(val, par->dc_regs + DC_PAL_DATA);
151}
152
153struct geode_dc_ops gx_dc_ops = {
154 .set_mode = gx_set_mode,
155 .set_palette_reg = gx_set_hw_palette_reg,
156};
diff --git a/drivers/video/geode/display_gx.h b/drivers/video/geode/display_gx.h
new file mode 100644
index 000000000000..86c623361305
--- /dev/null
+++ b/drivers/video/geode/display_gx.h
@@ -0,0 +1,96 @@
1/*
2 * Geode GX display controller
3 *
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#ifndef __DISPLAY_GX_H__
12#define __DISPLAY_GX_H__
13
14int gx_frame_buffer_size(void);
15int gx_line_delta(int xres, int bpp);
16
17extern struct geode_dc_ops gx_dc_ops;
18
19/* Display controller registers */
20
21#define DC_UNLOCK 0x00
22# define DC_UNLOCK_CODE 0x00004758
23
24#define DC_GENERAL_CFG 0x04
25# define DC_GCFG_DFLE 0x00000001
26# define DC_GCFG_CURE 0x00000002
27# define DC_GCFG_ICNE 0x00000004
28# define DC_GCFG_VIDE 0x00000008
29# define DC_GCFG_CMPE 0x00000020
30# define DC_GCFG_DECE 0x00000040
31# define DC_GCFG_VGAE 0x00000080
32# define DC_GCFG_DFHPSL_MASK 0x00000F00
33# define DC_GCFG_DFHPSL_POS 8
34# define DC_GCFG_DFHPEL_MASK 0x0000F000
35# define DC_GCFG_DFHPEL_POS 12
36# define DC_GCFG_STFM 0x00010000
37# define DC_GCFG_FDTY 0x00020000
38# define DC_GCFG_VGAFT 0x00040000
39# define DC_GCFG_VDSE 0x00080000
40# define DC_GCFG_YUVM 0x00100000
41# define DC_GCFG_VFSL 0x00800000
42# define DC_GCFG_SIGE 0x01000000
43# define DC_GCFG_SGRE 0x02000000
44# define DC_GCFG_SGFR 0x04000000
45# define DC_GCFG_CRC_MODE 0x08000000
46# define DC_GCFG_DIAG 0x10000000
47# define DC_GCFG_CFRW 0x20000000
48
49#define DC_DISPLAY_CFG 0x08
50# define DC_DCFG_TGEN 0x00000001
51# define DC_DCFG_GDEN 0x00000008
52# define DC_DCFG_VDEN 0x00000010
53# define DC_DCFG_TRUP 0x00000040
54# define DC_DCFG_DISP_MODE_MASK 0x00000300
55# define DC_DCFG_DISP_MODE_8BPP 0x00000000
56# define DC_DCFG_DISP_MODE_16BPP 0x00000100
57# define DC_DCFG_DISP_MODE_24BPP 0x00000200
58# define DC_DCFG_16BPP_MODE_MASK 0x00000c00
59# define DC_DCFG_16BPP_MODE_565 0x00000000
60# define DC_DCFG_16BPP_MODE_555 0x00000100
61# define DC_DCFG_16BPP_MODE_444 0x00000200
62# define DC_DCFG_DCEN 0x00080000
63# define DC_DCFG_PALB 0x02000000
64# define DC_DCFG_FRLK 0x04000000
65# define DC_DCFG_VISL 0x08000000
66# define DC_DCFG_FRSL 0x20000000
67# define DC_DCFG_A18M 0x40000000
68# define DC_DCFG_A20M 0x80000000
69
70#define DC_FB_ST_OFFSET 0x10
71
72#define DC_LINE_SIZE 0x30
73# define DC_LINE_SIZE_FB_LINE_SIZE_MASK 0x000007ff
74# define DC_LINE_SIZE_FB_LINE_SIZE_POS 0
75# define DC_LINE_SIZE_CB_LINE_SIZE_MASK 0x007f0000
76# define DC_LINE_SIZE_CB_LINE_SIZE_POS 16
77# define DC_LINE_SIZE_VID_LINE_SIZE_MASK 0xff000000
78# define DC_LINE_SIZE_VID_LINE_SIZE_POS 24
79
80#define DC_GFX_PITCH 0x34
81# define DC_GFX_PITCH_FB_PITCH_MASK 0x0000ffff
82# define DC_GFX_PITCH_FB_PITCH_POS 0
83# define DC_GFX_PITCH_CB_PITCH_MASK 0xffff0000
84# define DC_GFX_PITCH_CB_PITCH_POS 16
85
86#define DC_H_ACTIVE_TIMING 0x40
87#define DC_H_BLANK_TIMING 0x44
88#define DC_H_SYNC_TIMING 0x48
89#define DC_V_ACTIVE_TIMING 0x50
90#define DC_V_BLANK_TIMING 0x54
91#define DC_V_SYNC_TIMING 0x58
92
93#define DC_PAL_ADDRESS 0x70
94#define DC_PAL_DATA 0x74
95
96#endif /* !__DISPLAY_GX1_H__ */
diff --git a/drivers/video/geode/gxfb_core.c b/drivers/video/geode/gxfb_core.c
new file mode 100644
index 000000000000..89c34b15f5d4
--- /dev/null
+++ b/drivers/video/geode/gxfb_core.c
@@ -0,0 +1,423 @@
1/*
2 * Geode GX framebuffer driver.
3 *
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 *
12 * This driver assumes that the BIOS has created a virtual PCI device header
13 * for the video device. The PCI header is assumed to contain the following
14 * BARs:
15 *
16 * BAR0 - framebuffer memory
17 * BAR1 - graphics processor registers
18 * BAR2 - display controller registers
19 * BAR3 - video processor and flat panel control registers.
20 *
21 * 16 MiB of framebuffer memory is assumed to be available.
22 */
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/errno.h>
26#include <linux/string.h>
27#include <linux/mm.h>
28#include <linux/tty.h>
29#include <linux/slab.h>
30#include <linux/delay.h>
31#include <linux/fb.h>
32#include <linux/init.h>
33#include <linux/pci.h>
34
35#include "geodefb.h"
36#include "display_gx.h"
37#include "video_gx.h"
38
39static char mode_option[32] = "640x480-16@60";
40
41/* Modes relevant to the GX (taken from modedb.c) */
42static const struct fb_videomode __initdata gx_modedb[] = {
43 /* 640x480-60 VESA */
44 { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
45 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
46 /* 640x480-75 VESA */
47 { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
48 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
49 /* 640x480-85 VESA */
50 { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
51 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
52 /* 800x600-60 VESA */
53 { NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
54 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
55 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
56 /* 800x600-75 VESA */
57 { NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
58 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
59 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
60 /* 800x600-85 VESA */
61 { NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
62 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
63 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
64 /* 1024x768-60 VESA */
65 { NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
66 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
67 /* 1024x768-75 VESA */
68 { NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
69 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
70 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
71 /* 1024x768-85 VESA */
72 { NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
73 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
74 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
75 /* 1280x960-60 VESA */
76 { NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
77 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
78 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
79 /* 1280x960-85 VESA */
80 { NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
81 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
82 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
83 /* 1280x1024-60 VESA */
84 { NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
85 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
86 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
87 /* 1280x1024-75 VESA */
88 { NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
89 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
90 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
91 /* 1280x1024-85 VESA */
92 { NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
93 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
94 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
95 /* 1600x1200-60 VESA */
96 { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
97 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
98 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
99 /* 1600x1200-75 VESA */
100 { NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
101 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
102 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
103 /* 1600x1200-85 VESA */
104 { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
105 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
106 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
107};
108
109static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
110{
111 if (var->xres > 1600 || var->yres > 1200)
112 return -EINVAL;
113 if ((var->xres > 1280 || var->yres > 1024) && var->bits_per_pixel > 16)
114 return -EINVAL;
115
116 if (var->bits_per_pixel == 32) {
117 var->red.offset = 16; var->red.length = 8;
118 var->green.offset = 8; var->green.length = 8;
119 var->blue.offset = 0; var->blue.length = 8;
120 } else if (var->bits_per_pixel == 16) {
121 var->red.offset = 11; var->red.length = 5;
122 var->green.offset = 5; var->green.length = 6;
123 var->blue.offset = 0; var->blue.length = 5;
124 } else if (var->bits_per_pixel == 8) {
125 var->red.offset = 0; var->red.length = 8;
126 var->green.offset = 0; var->green.length = 8;
127 var->blue.offset = 0; var->blue.length = 8;
128 } else
129 return -EINVAL;
130 var->transp.offset = 0; var->transp.length = 0;
131
132 /* Enough video memory? */
133 if (gx_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len)
134 return -EINVAL;
135
136 /* FIXME: Check timing parameters here? */
137
138 return 0;
139}
140
141static int gxfb_set_par(struct fb_info *info)
142{
143 struct geodefb_par *par = info->par;
144
145 if (info->var.bits_per_pixel > 8) {
146 info->fix.visual = FB_VISUAL_TRUECOLOR;
147 fb_dealloc_cmap(&info->cmap);
148 } else {
149 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
150 fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0);
151 }
152
153 info->fix.line_length = gx_line_delta(info->var.xres, info->var.bits_per_pixel);
154
155 par->dc_ops->set_mode(info);
156
157 return 0;
158}
159
160static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
161{
162 chan &= 0xffff;
163 chan >>= 16 - bf->length;
164 return chan << bf->offset;
165}
166
167static int gxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
168 unsigned blue, unsigned transp,
169 struct fb_info *info)
170{
171 struct geodefb_par *par = info->par;
172
173 if (info->var.grayscale) {
174 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
175 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
176 }
177
178 /* Truecolor has hardware independent palette */
179 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
180 u32 *pal = info->pseudo_palette;
181 u32 v;
182
183 if (regno >= 16)
184 return -EINVAL;
185
186 v = chan_to_field(red, &info->var.red);
187 v |= chan_to_field(green, &info->var.green);
188 v |= chan_to_field(blue, &info->var.blue);
189
190 pal[regno] = v;
191 } else {
192 if (regno >= 256)
193 return -EINVAL;
194
195 par->dc_ops->set_palette_reg(info, regno, red, green, blue);
196 }
197
198 return 0;
199}
200
201static int gxfb_blank(int blank_mode, struct fb_info *info)
202{
203 struct geodefb_par *par = info->par;
204
205 return par->vid_ops->blank_display(info, blank_mode);
206}
207
208static int __init gxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
209{
210 struct geodefb_par *par = info->par;
211 int fb_len;
212 int ret;
213
214 ret = pci_enable_device(dev);
215 if (ret < 0)
216 return ret;
217
218 ret = pci_request_region(dev, 3, "gxfb (video processor)");
219 if (ret < 0)
220 return ret;
221 par->vid_regs = ioremap(pci_resource_start(dev, 3),
222 pci_resource_len(dev, 3));
223 if (!par->vid_regs)
224 return -ENOMEM;
225
226 ret = pci_request_region(dev, 2, "gxfb (display controller)");
227 if (ret < 0)
228 return ret;
229 par->dc_regs = ioremap(pci_resource_start(dev, 2), pci_resource_len(dev, 2));
230 if (!par->dc_regs)
231 return -ENOMEM;
232
233 ret = pci_request_region(dev, 0, "gxfb (framebuffer)");
234 if (ret < 0)
235 return ret;
236 if ((fb_len = gx_frame_buffer_size()) < 0)
237 return -ENOMEM;
238 info->fix.smem_start = pci_resource_start(dev, 0);
239 info->fix.smem_len = fb_len;
240 info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
241 if (!info->screen_base)
242 return -ENOMEM;
243
244 dev_info(&dev->dev, "%d Kibyte of video memory at 0x%lx\n",
245 info->fix.smem_len / 1024, info->fix.smem_start);
246
247 return 0;
248}
249
250static struct fb_ops gxfb_ops = {
251 .owner = THIS_MODULE,
252 .fb_check_var = gxfb_check_var,
253 .fb_set_par = gxfb_set_par,
254 .fb_setcolreg = gxfb_setcolreg,
255 .fb_blank = gxfb_blank,
256 /* No HW acceleration for now. */
257 .fb_fillrect = cfb_fillrect,
258 .fb_copyarea = cfb_copyarea,
259 .fb_imageblit = cfb_imageblit,
260};
261
262static struct fb_info * __init gxfb_init_fbinfo(struct device *dev)
263{
264 struct geodefb_par *par;
265 struct fb_info *info;
266
267 /* Alloc enough space for the pseudo palette. */
268 info = framebuffer_alloc(sizeof(struct geodefb_par) + sizeof(u32) * 16, dev);
269 if (!info)
270 return NULL;
271
272 par = info->par;
273
274 strcpy(info->fix.id, "Geode GX");
275
276 info->fix.type = FB_TYPE_PACKED_PIXELS;
277 info->fix.type_aux = 0;
278 info->fix.xpanstep = 0;
279 info->fix.ypanstep = 0;
280 info->fix.ywrapstep = 0;
281 info->fix.accel = FB_ACCEL_NONE;
282
283 info->var.nonstd = 0;
284 info->var.activate = FB_ACTIVATE_NOW;
285 info->var.height = -1;
286 info->var.width = -1;
287 info->var.accel_flags = 0;
288 info->var.vmode = FB_VMODE_NONINTERLACED;
289
290 info->fbops = &gxfb_ops;
291 info->flags = FBINFO_DEFAULT;
292 info->node = -1;
293
294 info->pseudo_palette = (void *)par + sizeof(struct geodefb_par);
295
296 info->var.grayscale = 0;
297
298 return info;
299}
300
301static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
302{
303 struct geodefb_par *par;
304 struct fb_info *info;
305 int ret;
306
307 info = gxfb_init_fbinfo(&pdev->dev);
308 if (!info)
309 return -ENOMEM;
310 par = info->par;
311
312 /* GX display controller and GX video device. */
313 par->dc_ops = &gx_dc_ops;
314 par->vid_ops = &gx_vid_ops;
315
316 if ((ret = gxfb_map_video_memory(info, pdev)) < 0) {
317 dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
318 goto err;
319 }
320
321 ret = fb_find_mode(&info->var, info, mode_option,
322 gx_modedb, ARRAY_SIZE(gx_modedb), NULL, 16);
323 if (ret == 0 || ret == 4) {
324 dev_err(&pdev->dev, "could not find valid video mode\n");
325 ret = -EINVAL;
326 goto err;
327 }
328
329 /* Clear the frame buffer of garbage. */
330 memset_io(info->screen_base, 0, info->fix.smem_len);
331
332 gxfb_check_var(&info->var, info);
333 gxfb_set_par(info);
334
335 if (register_framebuffer(info) < 0) {
336 ret = -EINVAL;
337 goto err;
338 }
339 pci_set_drvdata(pdev, info);
340 printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id);
341 return 0;
342
343 err:
344 if (info->screen_base) {
345 iounmap(info->screen_base);
346 pci_release_region(pdev, 0);
347 }
348 if (par->vid_regs) {
349 iounmap(par->vid_regs);
350 pci_release_region(pdev, 3);
351 }
352 if (par->dc_regs) {
353 iounmap(par->dc_regs);
354 pci_release_region(pdev, 2);
355 }
356
357 pci_disable_device(pdev);
358
359 if (info)
360 framebuffer_release(info);
361 return ret;
362}
363
364static void gxfb_remove(struct pci_dev *pdev)
365{
366 struct fb_info *info = pci_get_drvdata(pdev);
367 struct geodefb_par *par = info->par;
368
369 unregister_framebuffer(info);
370
371 iounmap((void __iomem *)info->screen_base);
372 pci_release_region(pdev, 0);
373
374 iounmap(par->vid_regs);
375 pci_release_region(pdev, 3);
376
377 iounmap(par->dc_regs);
378 pci_release_region(pdev, 2);
379
380 pci_disable_device(pdev);
381 pci_set_drvdata(pdev, NULL);
382
383 framebuffer_release(info);
384}
385
386static struct pci_device_id gxfb_id_table[] = {
387 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_VIDEO,
388 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
389 0xff0000, 0 },
390 { 0, }
391};
392
393MODULE_DEVICE_TABLE(pci, gxfb_id_table);
394
395static struct pci_driver gxfb_driver = {
396 .name = "gxfb",
397 .id_table = gxfb_id_table,
398 .probe = gxfb_probe,
399 .remove = gxfb_remove,
400};
401
402static int __init gxfb_init(void)
403{
404#ifndef MODULE
405 if (fb_get_options("gxfb", NULL))
406 return -ENODEV;
407#endif
408 return pci_register_driver(&gxfb_driver);
409}
410
411static void __exit gxfb_cleanup(void)
412{
413 pci_unregister_driver(&gxfb_driver);
414}
415
416module_init(gxfb_init);
417module_exit(gxfb_cleanup);
418
419module_param_string(mode, mode_option, sizeof(mode_option), 0444);
420MODULE_PARM_DESC(mode, "video mode (<x>x<y>[-<bpp>][@<refr>])");
421
422MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX");
423MODULE_LICENSE("GPL");
diff --git a/drivers/video/geode/video_gx.c b/drivers/video/geode/video_gx.c
new file mode 100644
index 000000000000..2b2a7880ea75
--- /dev/null
+++ b/drivers/video/geode/video_gx.c
@@ -0,0 +1,262 @@
1/*
2 * Geode GX video processor device.
3 *
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
5 *
6 * Portions from AMD's original 2.4 driver:
7 * Copyright (C) 2004 Advanced Micro Devices, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/fb.h>
15#include <linux/delay.h>
16#include <asm/io.h>
17#include <asm/delay.h>
18#include <asm/msr.h>
19
20#include "geodefb.h"
21#include "video_gx.h"
22
23
24/*
25 * Tables of register settings for various DOTCLKs.
26 */
27struct gx_pll_entry {
28 long pixclock; /* ps */
29 u32 sys_rstpll_bits;
30 u32 dotpll_value;
31};
32
33#define POSTDIV3 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
34#define PREMULT2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPREMULT2)
35#define PREDIV2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
36
37static const struct gx_pll_entry gx_pll_table_48MHz[] = {
38 { 40123, POSTDIV3, 0x00000BF2 }, /* 24.9230 */
39 { 39721, 0, 0x00000037 }, /* 25.1750 */
40 { 35308, POSTDIV3|PREMULT2, 0x00000B1A }, /* 28.3220 */
41 { 31746, POSTDIV3, 0x000002D2 }, /* 31.5000 */
42 { 27777, POSTDIV3|PREMULT2, 0x00000FE2 }, /* 36.0000 */
43 { 26666, POSTDIV3, 0x0000057A }, /* 37.5000 */
44 { 25000, POSTDIV3, 0x0000030A }, /* 40.0000 */
45 { 22271, 0, 0x00000063 }, /* 44.9000 */
46 { 20202, 0, 0x0000054B }, /* 49.5000 */
47 { 20000, 0, 0x0000026E }, /* 50.0000 */
48 { 19860, PREMULT2, 0x00000037 }, /* 50.3500 */
49 { 18518, POSTDIV3|PREMULT2, 0x00000B0D }, /* 54.0000 */
50 { 17777, 0, 0x00000577 }, /* 56.2500 */
51 { 17733, 0, 0x000007F7 }, /* 56.3916 */
52 { 17653, 0, 0x0000057B }, /* 56.6444 */
53 { 16949, PREMULT2, 0x00000707 }, /* 59.0000 */
54 { 15873, POSTDIV3|PREMULT2, 0x00000B39 }, /* 63.0000 */
55 { 15384, POSTDIV3|PREMULT2, 0x00000B45 }, /* 65.0000 */
56 { 14814, POSTDIV3|PREMULT2, 0x00000FC1 }, /* 67.5000 */
57 { 14124, POSTDIV3, 0x00000561 }, /* 70.8000 */
58 { 13888, POSTDIV3, 0x000007E1 }, /* 72.0000 */
59 { 13426, PREMULT2, 0x00000F4A }, /* 74.4810 */
60 { 13333, 0, 0x00000052 }, /* 75.0000 */
61 { 12698, 0, 0x00000056 }, /* 78.7500 */
62 { 12500, POSTDIV3|PREMULT2, 0x00000709 }, /* 80.0000 */
63 { 11135, PREMULT2, 0x00000262 }, /* 89.8000 */
64 { 10582, 0, 0x000002D2 }, /* 94.5000 */
65 { 10101, PREMULT2, 0x00000B4A }, /* 99.0000 */
66 { 10000, PREMULT2, 0x00000036 }, /* 100.0000 */
67 { 9259, 0, 0x000007E2 }, /* 108.0000 */
68 { 8888, 0, 0x000007F6 }, /* 112.5000 */
69 { 7692, POSTDIV3|PREMULT2, 0x00000FB0 }, /* 130.0000 */
70 { 7407, POSTDIV3|PREMULT2, 0x00000B50 }, /* 135.0000 */
71 { 6349, 0, 0x00000055 }, /* 157.5000 */
72 { 6172, 0, 0x000009C1 }, /* 162.0000 */
73 { 5787, PREMULT2, 0x0000002D }, /* 172.798 */
74 { 5698, 0, 0x000002C1 }, /* 175.5000 */
75 { 5291, 0, 0x000002D1 }, /* 189.0000 */
76 { 4938, 0, 0x00000551 }, /* 202.5000 */
77 { 4357, 0, 0x0000057D }, /* 229.5000 */
78};
79
80static const struct gx_pll_entry gx_pll_table_14MHz[] = {
81 { 39721, 0, 0x00000037 }, /* 25.1750 */
82 { 35308, 0, 0x00000B7B }, /* 28.3220 */
83 { 31746, 0, 0x000004D3 }, /* 31.5000 */
84 { 27777, 0, 0x00000BE3 }, /* 36.0000 */
85 { 26666, 0, 0x0000074F }, /* 37.5000 */
86 { 25000, 0, 0x0000050B }, /* 40.0000 */
87 { 22271, 0, 0x00000063 }, /* 44.9000 */
88 { 20202, 0, 0x0000054B }, /* 49.5000 */
89 { 20000, 0, 0x0000026E }, /* 50.0000 */
90 { 19860, 0, 0x000007C3 }, /* 50.3500 */
91 { 18518, 0, 0x000007E3 }, /* 54.0000 */
92 { 17777, 0, 0x00000577 }, /* 56.2500 */
93 { 17733, 0, 0x000002FB }, /* 56.3916 */
94 { 17653, 0, 0x0000057B }, /* 56.6444 */
95 { 16949, 0, 0x0000058B }, /* 59.0000 */
96 { 15873, 0, 0x0000095E }, /* 63.0000 */
97 { 15384, 0, 0x0000096A }, /* 65.0000 */
98 { 14814, 0, 0x00000BC2 }, /* 67.5000 */
99 { 14124, 0, 0x0000098A }, /* 70.8000 */
100 { 13888, 0, 0x00000BE2 }, /* 72.0000 */
101 { 13333, 0, 0x00000052 }, /* 75.0000 */
102 { 12698, 0, 0x00000056 }, /* 78.7500 */
103 { 12500, 0, 0x0000050A }, /* 80.0000 */
104 { 11135, 0, 0x0000078E }, /* 89.8000 */
105 { 10582, 0, 0x000002D2 }, /* 94.5000 */
106 { 10101, 0, 0x000011F6 }, /* 99.0000 */
107 { 10000, 0, 0x0000054E }, /* 100.0000 */
108 { 9259, 0, 0x000007E2 }, /* 108.0000 */
109 { 8888, 0, 0x000002FA }, /* 112.5000 */
110 { 7692, 0, 0x00000BB1 }, /* 130.0000 */
111 { 7407, 0, 0x00000975 }, /* 135.0000 */
112 { 6349, 0, 0x00000055 }, /* 157.5000 */
113 { 6172, 0, 0x000009C1 }, /* 162.0000 */
114 { 5698, 0, 0x000002C1 }, /* 175.5000 */
115 { 5291, 0, 0x00000539 }, /* 189.0000 */
116 { 4938, 0, 0x00000551 }, /* 202.5000 */
117 { 4357, 0, 0x0000057D }, /* 229.5000 */
118};
119
120static void gx_set_dclk_frequency(struct fb_info *info)
121{
122 const struct gx_pll_entry *pll_table;
123 int pll_table_len;
124 int i, best_i;
125 long min, diff;
126 u64 dotpll, sys_rstpll;
127 int timeout = 1000;
128
129 /* Rev. 1 Geode GXs use a 14 MHz reference clock instead of 48 MHz. */
130 if (cpu_data->x86_mask == 1) {
131 pll_table = gx_pll_table_14MHz;
132 pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
133 } else {
134 pll_table = gx_pll_table_48MHz;
135 pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz);
136 }
137
138 /* Search the table for the closest pixclock. */
139 best_i = 0;
140 min = abs(pll_table[0].pixclock - info->var.pixclock);
141 for (i = 1; i < pll_table_len; i++) {
142 diff = abs(pll_table[i].pixclock - info->var.pixclock);
143 if (diff < min) {
144 min = diff;
145 best_i = i;
146 }
147 }
148
149 rdmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
150 rdmsrl(MSR_GLCP_DOTPLL, dotpll);
151
152 /* Program new M, N and P. */
153 dotpll &= 0x00000000ffffffffull;
154 dotpll |= (u64)pll_table[best_i].dotpll_value << 32;
155 dotpll |= MSR_GLCP_DOTPLL_DOTRESET;
156 dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;
157
158 wrmsrl(MSR_GLCP_DOTPLL, dotpll);
159
160 /* Program dividers. */
161 sys_rstpll &= ~( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2
162 | MSR_GLCP_SYS_RSTPLL_DOTPREMULT2
163 | MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 );
164 sys_rstpll |= pll_table[best_i].sys_rstpll_bits;
165
166 wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
167
168 /* Clear reset bit to start PLL. */
169 dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);
170 wrmsrl(MSR_GLCP_DOTPLL, dotpll);
171
172 /* Wait for LOCK bit. */
173 do {
174 rdmsrl(MSR_GLCP_DOTPLL, dotpll);
175 } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
176}
177
178static void gx_configure_display(struct fb_info *info)
179{
180 struct geodefb_par *par = info->par;
181 u32 dcfg, fp_pm;
182
183 dcfg = readl(par->vid_regs + GX_DCFG);
184
185 /* Clear bits from existing mode. */
186 dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK
187 | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL
188 | GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN);
189
190 /* Set default sync skew. */
191 dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT;
192
193 /* Enable hsync and vsync. */
194 dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN;
195
196 /* Sync polarities. */
197 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
198 dcfg |= GX_DCFG_CRT_HSYNC_POL;
199 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
200 dcfg |= GX_DCFG_CRT_VSYNC_POL;
201
202 writel(dcfg, par->vid_regs + GX_DCFG);
203
204 /* Power on flat panel. */
205 fp_pm = readl(par->vid_regs + GX_FP_PM);
206 fp_pm |= GX_FP_PM_P;
207 writel(fp_pm, par->vid_regs + GX_FP_PM);
208}
209
210static int gx_blank_display(struct fb_info *info, int blank_mode)
211{
212 struct geodefb_par *par = info->par;
213 u32 dcfg, fp_pm;
214 int blank, hsync, vsync;
215
216 /* CRT power saving modes. */
217 switch (blank_mode) {
218 case FB_BLANK_UNBLANK:
219 blank = 0; hsync = 1; vsync = 1;
220 break;
221 case FB_BLANK_NORMAL:
222 blank = 1; hsync = 1; vsync = 1;
223 break;
224 case FB_BLANK_VSYNC_SUSPEND:
225 blank = 1; hsync = 1; vsync = 0;
226 break;
227 case FB_BLANK_HSYNC_SUSPEND:
228 blank = 1; hsync = 0; vsync = 1;
229 break;
230 case FB_BLANK_POWERDOWN:
231 blank = 1; hsync = 0; vsync = 0;
232 break;
233 default:
234 return -EINVAL;
235 }
236 dcfg = readl(par->vid_regs + GX_DCFG);
237 dcfg &= ~(GX_DCFG_DAC_BL_EN
238 | GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN);
239 if (!blank)
240 dcfg |= GX_DCFG_DAC_BL_EN;
241 if (hsync)
242 dcfg |= GX_DCFG_HSYNC_EN;
243 if (vsync)
244 dcfg |= GX_DCFG_VSYNC_EN;
245 writel(dcfg, par->vid_regs + GX_DCFG);
246
247 /* Power on/off flat panel. */
248 fp_pm = readl(par->vid_regs + GX_FP_PM);
249 if (blank_mode == FB_BLANK_POWERDOWN)
250 fp_pm &= ~GX_FP_PM_P;
251 else
252 fp_pm |= GX_FP_PM_P;
253 writel(fp_pm, par->vid_regs + GX_FP_PM);
254
255 return 0;
256}
257
258struct geode_vid_ops gx_vid_ops = {
259 .set_dclk = gx_set_dclk_frequency,
260 .configure_display = gx_configure_display,
261 .blank_display = gx_blank_display,
262};
diff --git a/drivers/video/geode/video_gx.h b/drivers/video/geode/video_gx.h
new file mode 100644
index 000000000000..2d9211f3ed84
--- /dev/null
+++ b/drivers/video/geode/video_gx.h
@@ -0,0 +1,47 @@
1/*
2 * Geode GX video device
3 *
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#ifndef __VIDEO_GX_H__
12#define __VIDEO_GX_H__
13
14extern struct geode_vid_ops gx_vid_ops;
15
16/* Geode GX video processor registers */
17
18#define GX_DCFG 0x0008
19# define GX_DCFG_CRT_EN 0x00000001
20# define GX_DCFG_HSYNC_EN 0x00000002
21# define GX_DCFG_VSYNC_EN 0x00000004
22# define GX_DCFG_DAC_BL_EN 0x00000008
23# define GX_DCFG_CRT_HSYNC_POL 0x00000100
24# define GX_DCFG_CRT_VSYNC_POL 0x00000200
25# define GX_DCFG_CRT_SYNC_SKW_MASK 0x0001C000
26# define GX_DCFG_CRT_SYNC_SKW_DFLT 0x00010000
27# define GX_DCFG_VG_CK 0x00100000
28# define GX_DCFG_GV_GAM 0x00200000
29# define GX_DCFG_DAC_VREF 0x04000000
30
31/* Geode GX flat panel display control registers */
32#define GX_FP_PM 0x410
33# define GX_FP_PM_P 0x01000000
34
35/* Geode GX clock control MSRs */
36
37#define MSR_GLCP_SYS_RSTPLL 0x4c000014
38# define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (0x0000000000000002ull)
39# define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 (0x0000000000000004ull)
40# define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 (0x0000000000000008ull)
41
42#define MSR_GLCP_DOTPLL 0x4c000015
43# define MSR_GLCP_DOTPLL_DOTRESET (0x0000000000000001ull)
44# define MSR_GLCP_DOTPLL_BYPASS (0x0000000000008000ull)
45# define MSR_GLCP_DOTPLL_LOCK (0x0000000002000000ull)
46
47#endif /* !__VIDEO_GX_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 22:07:08 -0500