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-rw-r--r--drivers/video/Kconfig32
-rw-r--r--drivers/video/Makefile1
-rw-r--r--drivers/video/atmel_lcdfb.c2
-rw-r--r--drivers/video/aty/radeon_accel.c291
-rw-r--r--drivers/video/aty/radeon_backlight.c2
-rw-r--r--drivers/video/aty/radeon_base.c22
-rw-r--r--drivers/video/aty/radeon_pm.c6
-rw-r--r--drivers/video/aty/radeonfb.h38
-rw-r--r--drivers/video/backlight/corgi_lcd.c4
-rw-r--r--drivers/video/backlight/da903x.c2
-rw-r--r--drivers/video/backlight/lcd.c11
-rw-r--r--drivers/video/cirrusfb.c5
-rw-r--r--drivers/video/console/fbcon.c17
-rw-r--r--drivers/video/fbmem.c63
-rw-r--r--drivers/video/macfb.c74
-rw-r--r--drivers/video/mb862xx/Makefile5
-rw-r--r--drivers/video/mb862xx/mb862xx_reg.h138
-rw-r--r--drivers/video/mb862xx/mb862xxfb.c1061
-rw-r--r--drivers/video/mb862xx/mb862xxfb.h83
-rw-r--r--drivers/video/omap/Makefile1
-rw-r--r--drivers/video/omap/lcd_sx1.c327
-rw-r--r--drivers/video/omap/omapfb_main.c2
-rw-r--r--drivers/video/pxafb.c5
-rw-r--r--drivers/video/tmiofb.c10
-rw-r--r--drivers/video/via/global.h3
-rw-r--r--drivers/video/via/viafbdev.c17
-rw-r--r--drivers/video/xen-fbfront.c6
-rw-r--r--drivers/video/xilinxfb.c5
28 files changed, 1567 insertions, 666 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 0f13448c6f79..3f3ce13fef43 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -2083,6 +2083,38 @@ config FB_METRONOME
2083 controller. The pre-release name for this device was 8track 2083 controller. The pre-release name for this device was 8track
2084 and could also have been called by some vendors as PVI-nnnn. 2084 and could also have been called by some vendors as PVI-nnnn.
2085 2085
2086config FB_MB862XX
2087 tristate "Fujitsu MB862xx GDC support"
2088 depends on FB
2089 select FB_CFB_FILLRECT
2090 select FB_CFB_COPYAREA
2091 select FB_CFB_IMAGEBLIT
2092 ---help---
2093 Frame buffer driver for Fujitsu Carmine/Coral-P(A)/Lime controllers.
2094
2095config FB_MB862XX_PCI_GDC
2096 bool "Carmine/Coral-P(A) GDC"
2097 depends on PCI && FB_MB862XX
2098 ---help---
2099 This enables framebuffer support for Fujitsu Carmine/Coral-P(A)
2100 PCI graphics controller devices.
2101
2102config FB_MB862XX_LIME
2103 bool "Lime GDC"
2104 depends on FB_MB862XX
2105 depends on OF && !FB_MB862XX_PCI_GDC
2106 select FB_FOREIGN_ENDIAN
2107 select FB_LITTLE_ENDIAN
2108 ---help---
2109 Framebuffer support for Fujitsu Lime GDC on host CPU bus.
2110
2111config FB_PRE_INIT_FB
2112 bool "Don't reinitialize, use bootloader's GDC/Display configuration"
2113 depends on FB_MB862XX_LIME
2114 ---help---
2115 Select this option if display contents should be inherited as set by
2116 the bootloader.
2117
2086source "drivers/video/omap/Kconfig" 2118source "drivers/video/omap/Kconfig"
2087 2119
2088source "drivers/video/backlight/Kconfig" 2120source "drivers/video/backlight/Kconfig"
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 248bddc8d0b0..e39e33e797da 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -122,6 +122,7 @@ obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o
122obj-$(CONFIG_FB_OMAP) += omap/ 122obj-$(CONFIG_FB_OMAP) += omap/
123obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o 123obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o
124obj-$(CONFIG_FB_CARMINE) += carminefb.o 124obj-$(CONFIG_FB_CARMINE) += carminefb.o
125obj-$(CONFIG_FB_MB862XX) += mb862xx/
125 126
126# Platform or fallback drivers go here 127# Platform or fallback drivers go here
127obj-$(CONFIG_FB_UVESA) += uvesafb.o 128obj-$(CONFIG_FB_UVESA) += uvesafb.o
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index f8d0a57a07cb..9a577a800db5 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -132,7 +132,7 @@ static void init_backlight(struct atmel_lcdfb_info *sinfo)
132 132
133 bl = backlight_device_register("backlight", &sinfo->pdev->dev, 133 bl = backlight_device_register("backlight", &sinfo->pdev->dev,
134 sinfo, &atmel_lcdc_bl_ops); 134 sinfo, &atmel_lcdc_bl_ops);
135 if (IS_ERR(sinfo->backlight)) { 135 if (IS_ERR(bl)) {
136 dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n", 136 dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n",
137 PTR_ERR(bl)); 137 PTR_ERR(bl));
138 return; 138 return;
diff --git a/drivers/video/aty/radeon_accel.c b/drivers/video/aty/radeon_accel.c
index 8718f7349d6b..a469a3d6edcb 100644
--- a/drivers/video/aty/radeon_accel.c
+++ b/drivers/video/aty/radeon_accel.c
@@ -5,61 +5,61 @@
5 * --dte 5 * --dte
6 */ 6 */
7 7
8#define FLUSH_CACHE_WORKAROUND 1 8static void radeon_fixup_offset(struct radeonfb_info *rinfo)
9
10void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries)
11{ 9{
12 int i; 10 u32 local_base;
11
12 /* *** Ugly workaround *** */
13 /*
14 * On some platforms, the video memory is mapped at 0 in radeon chip space
15 * (like PPCs) by the firmware. X will always move it up so that it's seen
16 * by the chip to be at the same address as the PCI BAR.
17 * That means that when switching back from X, there is a mismatch between
18 * the offsets programmed into the engine. This means that potentially,
19 * accel operations done before radeonfb has a chance to re-init the engine
20 * will have incorrect offsets, and potentially trash system memory !
21 *
22 * The correct fix is for fbcon to never call any accel op before the engine
23 * has properly been re-initialized (by a call to set_var), but this is a
24 * complex fix. This workaround in the meantime, called before every accel
25 * operation, makes sure the offsets are in sync.
26 */
13 27
14 for (i=0; i<2000000; i++) { 28 radeon_fifo_wait (1);
15 rinfo->fifo_free = INREG(RBBM_STATUS) & 0x7f; 29 local_base = INREG(MC_FB_LOCATION) << 16;
16 if (rinfo->fifo_free >= entries) 30 if (local_base == rinfo->fb_local_base)
17 return; 31 return;
18 udelay(10);
19 }
20 printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
21 /* XXX Todo: attempt to reset the engine */
22}
23 32
24static inline void radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) 33 rinfo->fb_local_base = local_base;
25{
26 if (entries <= rinfo->fifo_free)
27 rinfo->fifo_free -= entries;
28 else
29 radeon_fifo_update_and_wait(rinfo, entries);
30}
31 34
32static inline void radeonfb_set_creg(struct radeonfb_info *rinfo, u32 reg, 35 radeon_fifo_wait (3);
33 u32 *cache, u32 new_val) 36 OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
34{ 37 (rinfo->fb_local_base >> 10));
35 if (new_val == *cache) 38 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
36 return; 39 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
37 *cache = new_val;
38 radeon_fifo_wait(rinfo, 1);
39 OUTREG(reg, new_val);
40} 40}
41 41
42static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo, 42static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo,
43 const struct fb_fillrect *region) 43 const struct fb_fillrect *region)
44{ 44{
45 radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache, 45 radeon_fifo_wait(4);
46 rinfo->dp_gui_mc_base | GMC_BRUSH_SOLID_COLOR | ROP3_P); 46
47 radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache, 47 OUTREG(DP_GUI_MASTER_CNTL,
48 DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 48 rinfo->dp_gui_master_cntl /* contains, like GMC_DST_32BPP */
49 radeonfb_set_creg(rinfo, DP_BRUSH_FRGD_CLR, &rinfo->dp_brush_fg_cache, 49 | GMC_BRUSH_SOLID_COLOR
50 region->color); 50 | ROP3_P);
51 51 if (radeon_get_dstbpp(rinfo->depth) != DST_8BPP)
52 /* Ensure the dst cache is flushed and the engine idle before 52 OUTREG(DP_BRUSH_FRGD_CLR, rinfo->pseudo_palette[region->color]);
53 * issuing the operation. 53 else
54 * 54 OUTREG(DP_BRUSH_FRGD_CLR, region->color);
55 * This works around engine lockups on some cards 55 OUTREG(DP_WRITE_MSK, 0xffffffff);
56 */ 56 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
57#if FLUSH_CACHE_WORKAROUND 57
58 radeon_fifo_wait(rinfo, 2); 58 radeon_fifo_wait(2);
59 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); 59 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
60 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); 60 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
61#endif 61
62 radeon_fifo_wait(rinfo, 2); 62 radeon_fifo_wait(2);
63 OUTREG(DST_Y_X, (region->dy << 16) | region->dx); 63 OUTREG(DST_Y_X, (region->dy << 16) | region->dx);
64 OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height); 64 OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height);
65} 65}
@@ -70,14 +70,15 @@ void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
70 struct fb_fillrect modded; 70 struct fb_fillrect modded;
71 int vxres, vyres; 71 int vxres, vyres;
72 72
73 WARN_ON(rinfo->gfx_mode); 73 if (info->state != FBINFO_STATE_RUNNING)
74 if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
75 return; 74 return;
76 if (info->flags & FBINFO_HWACCEL_DISABLED) { 75 if (info->flags & FBINFO_HWACCEL_DISABLED) {
77 cfb_fillrect(info, region); 76 cfb_fillrect(info, region);
78 return; 77 return;
79 } 78 }
80 79
80 radeon_fixup_offset(rinfo);
81
81 vxres = info->var.xres_virtual; 82 vxres = info->var.xres_virtual;
82 vyres = info->var.yres_virtual; 83 vyres = info->var.yres_virtual;
83 84
@@ -90,10 +91,6 @@ void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
90 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx; 91 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
91 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy; 92 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
92 93
93 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
94 info->fix.visual == FB_VISUAL_DIRECTCOLOR )
95 modded.color = ((u32 *) (info->pseudo_palette))[region->color];
96
97 radeonfb_prim_fillrect(rinfo, &modded); 94 radeonfb_prim_fillrect(rinfo, &modded);
98} 95}
99 96
@@ -112,22 +109,22 @@ static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo,
112 if ( xdir < 0 ) { sx += w-1; dx += w-1; } 109 if ( xdir < 0 ) { sx += w-1; dx += w-1; }
113 if ( ydir < 0 ) { sy += h-1; dy += h-1; } 110 if ( ydir < 0 ) { sy += h-1; dy += h-1; }
114 111
115 radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache, 112 radeon_fifo_wait(3);
116 rinfo->dp_gui_mc_base | 113 OUTREG(DP_GUI_MASTER_CNTL,
117 GMC_BRUSH_NONE | 114 rinfo->dp_gui_master_cntl /* i.e. GMC_DST_32BPP */
118 GMC_SRC_DATATYPE_COLOR | 115 | GMC_BRUSH_NONE
119 ROP3_S | 116 | GMC_SRC_DSTCOLOR
120 DP_SRC_SOURCE_MEMORY); 117 | ROP3_S
121 radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache, 118 | DP_SRC_SOURCE_MEMORY );
122 (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0) | 119 OUTREG(DP_WRITE_MSK, 0xffffffff);
123 (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0)); 120 OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0)
124 121 | (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0));
125#if FLUSH_CACHE_WORKAROUND 122
126 radeon_fifo_wait(rinfo, 2); 123 radeon_fifo_wait(2);
127 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); 124 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
128 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); 125 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
129#endif 126
130 radeon_fifo_wait(rinfo, 3); 127 radeon_fifo_wait(3);
131 OUTREG(SRC_Y_X, (sy << 16) | sx); 128 OUTREG(SRC_Y_X, (sy << 16) | sx);
132 OUTREG(DST_Y_X, (dy << 16) | dx); 129 OUTREG(DST_Y_X, (dy << 16) | dx);
133 OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w); 130 OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w);
@@ -146,14 +143,15 @@ void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
146 modded.width = area->width; 143 modded.width = area->width;
147 modded.height = area->height; 144 modded.height = area->height;
148 145
149 WARN_ON(rinfo->gfx_mode); 146 if (info->state != FBINFO_STATE_RUNNING)
150 if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
151 return; 147 return;
152 if (info->flags & FBINFO_HWACCEL_DISABLED) { 148 if (info->flags & FBINFO_HWACCEL_DISABLED) {
153 cfb_copyarea(info, area); 149 cfb_copyarea(info, area);
154 return; 150 return;
155 } 151 }
156 152
153 radeon_fixup_offset(rinfo);
154
157 vxres = info->var.xres_virtual; 155 vxres = info->var.xres_virtual;
158 vyres = info->var.yres_virtual; 156 vyres = info->var.yres_virtual;
159 157
@@ -170,112 +168,13 @@ void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
170 radeonfb_prim_copyarea(rinfo, &modded); 168 radeonfb_prim_copyarea(rinfo, &modded);
171} 169}
172 170
173static void radeonfb_prim_imageblit(struct radeonfb_info *rinfo,
174 const struct fb_image *image,
175 u32 fg, u32 bg)
176{
177 unsigned int src_bytes, dwords;
178 u32 *bits;
179
180 radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache,
181 rinfo->dp_gui_mc_base |
182 GMC_BRUSH_NONE |
183 GMC_SRC_DATATYPE_MONO_FG_BG |
184 ROP3_S |
185 GMC_BYTE_ORDER_MSB_TO_LSB |
186 DP_SRC_SOURCE_HOST_DATA);
187 radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache,
188 DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
189 radeonfb_set_creg(rinfo, DP_SRC_FRGD_CLR, &rinfo->dp_src_fg_cache, fg);
190 radeonfb_set_creg(rinfo, DP_SRC_BKGD_CLR, &rinfo->dp_src_bg_cache, bg);
191
192 radeon_fifo_wait(rinfo, 1);
193 OUTREG(DST_Y_X, (image->dy << 16) | image->dx);
194
195 /* Ensure the dst cache is flushed and the engine idle before
196 * issuing the operation.
197 *
198 * This works around engine lockups on some cards
199 */
200#if FLUSH_CACHE_WORKAROUND
201 radeon_fifo_wait(rinfo, 2);
202 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
203 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
204#endif
205
206 /* X here pads width to a multiple of 32 and uses the clipper to
207 * adjust the result. Is that really necessary ? Things seem to
208 * work ok for me without that and the doco doesn't seem to imply
209 * there is such a restriction.
210 */
211 OUTREG(DST_WIDTH_HEIGHT, (image->width << 16) | image->height);
212
213 src_bytes = (((image->width * image->depth) + 7) / 8) * image->height;
214 dwords = (src_bytes + 3) / 4;
215 bits = (u32*)(image->data);
216
217 while(dwords >= 8) {
218 radeon_fifo_wait(rinfo, 8);
219#if BITS_PER_LONG == 64
220 __raw_writeq(*((u64 *)(bits)), rinfo->mmio_base + HOST_DATA0);
221 __raw_writeq(*((u64 *)(bits+2)), rinfo->mmio_base + HOST_DATA2);
222 __raw_writeq(*((u64 *)(bits+4)), rinfo->mmio_base + HOST_DATA4);
223 __raw_writeq(*((u64 *)(bits+6)), rinfo->mmio_base + HOST_DATA6);
224 bits += 8;
225#else
226 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA0);
227 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA1);
228 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA2);
229 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA3);
230 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA4);
231 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA5);
232 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA6);
233 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA7);
234#endif
235 dwords -= 8;
236 }
237 while(dwords--) {
238 radeon_fifo_wait(rinfo, 1);
239 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA0);
240 }
241}
242
243void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image) 171void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image)
244{ 172{
245 struct radeonfb_info *rinfo = info->par; 173 struct radeonfb_info *rinfo = info->par;
246 u32 fg, bg;
247
248 WARN_ON(rinfo->gfx_mode);
249 if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
250 return;
251 174
252 if (!image->width || !image->height) 175 if (info->state != FBINFO_STATE_RUNNING)
253 return; 176 return;
254 177 radeon_engine_idle();
255 /* We only do 1 bpp color expansion for now */
256 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1)
257 goto fallback;
258
259 /* Fallback if running out of the screen. We may do clipping
260 * in the future */
261 if ((image->dx + image->width) > info->var.xres_virtual ||
262 (image->dy + image->height) > info->var.yres_virtual)
263 goto fallback;
264
265 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
266 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
267 fg = ((u32*)(info->pseudo_palette))[image->fg_color];
268 bg = ((u32*)(info->pseudo_palette))[image->bg_color];
269 } else {
270 fg = image->fg_color;
271 bg = image->bg_color;
272 }
273
274 radeonfb_prim_imageblit(rinfo, image, fg, bg);
275 return;
276
277 fallback:
278 radeon_engine_idle(rinfo);
279 178
280 cfb_imageblit(info, image); 179 cfb_imageblit(info, image);
281} 180}
@@ -286,8 +185,7 @@ int radeonfb_sync(struct fb_info *info)
286 185
287 if (info->state != FBINFO_STATE_RUNNING) 186 if (info->state != FBINFO_STATE_RUNNING)
288 return 0; 187 return 0;
289 188 radeon_engine_idle();
290 radeon_engine_idle(rinfo);
291 189
292 return 0; 190 return 0;
293} 191}
@@ -363,10 +261,9 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
363 /* disable 3D engine */ 261 /* disable 3D engine */
364 OUTREG(RB3D_CNTL, 0); 262 OUTREG(RB3D_CNTL, 0);
365 263
366 rinfo->fifo_free = 0;
367 radeonfb_engine_reset(rinfo); 264 radeonfb_engine_reset(rinfo);
368 265
369 radeon_fifo_wait(rinfo, 1); 266 radeon_fifo_wait (1);
370 if (IS_R300_VARIANT(rinfo)) { 267 if (IS_R300_VARIANT(rinfo)) {
371 OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) | 268 OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) |
372 RB2D_DC_AUTOFLUSH_ENABLE | 269 RB2D_DC_AUTOFLUSH_ENABLE |
@@ -380,7 +277,7 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
380 OUTREG(RB2D_DSTCACHE_MODE, 0); 277 OUTREG(RB2D_DSTCACHE_MODE, 0);
381 } 278 }
382 279
383 radeon_fifo_wait(rinfo, 3); 280 radeon_fifo_wait (3);
384 /* We re-read MC_FB_LOCATION from card as it can have been 281 /* We re-read MC_FB_LOCATION from card as it can have been
385 * modified by XFree drivers (ouch !) 282 * modified by XFree drivers (ouch !)
386 */ 283 */
@@ -391,57 +288,41 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
391 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); 288 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
392 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); 289 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
393 290
394 radeon_fifo_wait(rinfo, 1); 291 radeon_fifo_wait (1);
395#ifdef __BIG_ENDIAN 292#if defined(__BIG_ENDIAN)
396 OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); 293 OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
397#else 294#else
398 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); 295 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
399#endif 296#endif
400 radeon_fifo_wait(rinfo, 2); 297 radeon_fifo_wait (2);
401 OUTREG(DEFAULT_SC_TOP_LEFT, 0); 298 OUTREG(DEFAULT_SC_TOP_LEFT, 0);
402 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | 299 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
403 DEFAULT_SC_BOTTOM_MAX)); 300 DEFAULT_SC_BOTTOM_MAX));
404 301
405 /* set default DP_GUI_MASTER_CNTL */
406 temp = radeon_get_dstbpp(rinfo->depth); 302 temp = radeon_get_dstbpp(rinfo->depth);
407 rinfo->dp_gui_mc_base = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS); 303 rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
408 304
409 rinfo->dp_gui_mc_cache = rinfo->dp_gui_mc_base | 305 radeon_fifo_wait (1);
410 GMC_BRUSH_SOLID_COLOR | 306 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
411 GMC_SRC_DATATYPE_COLOR; 307 GMC_BRUSH_SOLID_COLOR |
412 radeon_fifo_wait(rinfo, 1); 308 GMC_SRC_DATATYPE_COLOR));
413 OUTREG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_mc_cache);
414 309
310 radeon_fifo_wait (7);
415 311
416 /* clear line drawing regs */ 312 /* clear line drawing regs */
417 radeon_fifo_wait(rinfo, 2);
418 OUTREG(DST_LINE_START, 0); 313 OUTREG(DST_LINE_START, 0);
419 OUTREG(DST_LINE_END, 0); 314 OUTREG(DST_LINE_END, 0);
420 315
421 /* set brush and source color regs */ 316 /* set brush color regs */
422 rinfo->dp_brush_fg_cache = 0xffffffff; 317 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
423 rinfo->dp_brush_bg_cache = 0x00000000; 318 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
424 rinfo->dp_src_fg_cache = 0xffffffff; 319
425 rinfo->dp_src_bg_cache = 0x00000000; 320 /* set source color regs */
426 radeon_fifo_wait(rinfo, 4); 321 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
427 OUTREG(DP_BRUSH_FRGD_CLR, rinfo->dp_brush_fg_cache); 322 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
428 OUTREG(DP_BRUSH_BKGD_CLR, rinfo->dp_brush_bg_cache);
429 OUTREG(DP_SRC_FRGD_CLR, rinfo->dp_src_fg_cache);
430 OUTREG(DP_SRC_BKGD_CLR, rinfo->dp_src_bg_cache);
431
432 /* Default direction */
433 rinfo->dp_cntl_cache = DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM;
434 radeon_fifo_wait(rinfo, 1);
435 OUTREG(DP_CNTL, rinfo->dp_cntl_cache);
436 323
437 /* default write mask */ 324 /* default write mask */
438 radeon_fifo_wait(rinfo, 1);
439 OUTREG(DP_WRITE_MSK, 0xffffffff); 325 OUTREG(DP_WRITE_MSK, 0xffffffff);
440 326
441 /* Default to no swapping of host data */ 327 radeon_engine_idle ();
442 radeon_fifo_wait(rinfo, 1);
443 OUTREG(RBBM_GUICNTL, RBBM_GUICNTL_HOST_DATA_SWAP_NONE);
444
445 /* Make sure it's settled */
446 radeon_engine_idle(rinfo);
447} 328}
diff --git a/drivers/video/aty/radeon_backlight.c b/drivers/video/aty/radeon_backlight.c
index f343ba83f0ae..1a056adb61c8 100644
--- a/drivers/video/aty/radeon_backlight.c
+++ b/drivers/video/aty/radeon_backlight.c
@@ -66,7 +66,7 @@ static int radeon_bl_update_status(struct backlight_device *bd)
66 level = bd->props.brightness; 66 level = bd->props.brightness;
67 67
68 del_timer_sync(&rinfo->lvds_timer); 68 del_timer_sync(&rinfo->lvds_timer);
69 radeon_engine_idle(rinfo); 69 radeon_engine_idle();
70 70
71 lvds_gen_cntl = INREG(LVDS_GEN_CNTL); 71 lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
72 if (level > 0) { 72 if (level > 0) {
diff --git a/drivers/video/aty/radeon_base.c b/drivers/video/aty/radeon_base.c
index 9a5821c65ebf..d0f1a7fc2c9d 100644
--- a/drivers/video/aty/radeon_base.c
+++ b/drivers/video/aty/radeon_base.c
@@ -852,6 +852,7 @@ static int radeonfb_pan_display (struct fb_var_screeninfo *var,
852 if (rinfo->asleep) 852 if (rinfo->asleep)
853 return 0; 853 return 0;
854 854
855 radeon_fifo_wait(2);
855 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset) 856 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
856 * var->bits_per_pixel / 8) & ~7); 857 * var->bits_per_pixel / 8) & ~7);
857 return 0; 858 return 0;
@@ -881,6 +882,7 @@ static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
881 if (rc) 882 if (rc)
882 return rc; 883 return rc;
883 884
885 radeon_fifo_wait(2);
884 if (value & 0x01) { 886 if (value & 0x01) {
885 tmp = INREG(LVDS_GEN_CNTL); 887 tmp = INREG(LVDS_GEN_CNTL);
886 888
@@ -938,7 +940,7 @@ int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
938 if (rinfo->lock_blank) 940 if (rinfo->lock_blank)
939 return 0; 941 return 0;
940 942
941 radeon_engine_idle(rinfo); 943 radeon_engine_idle();
942 944
943 val = INREG(CRTC_EXT_CNTL); 945 val = INREG(CRTC_EXT_CNTL);
944 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | 946 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
@@ -1046,7 +1048,7 @@ static int radeonfb_blank (int blank, struct fb_info *info)
1046 1048
1047 if (rinfo->asleep) 1049 if (rinfo->asleep)
1048 return 0; 1050 return 0;
1049 1051
1050 return radeon_screen_blank(rinfo, blank, 0); 1052 return radeon_screen_blank(rinfo, blank, 0);
1051} 1053}
1052 1054
@@ -1072,6 +1074,8 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1072 pindex = regno; 1074 pindex = regno;
1073 1075
1074 if (!rinfo->asleep) { 1076 if (!rinfo->asleep) {
1077 radeon_fifo_wait(9);
1078
1075 if (rinfo->bpp == 16) { 1079 if (rinfo->bpp == 16) {
1076 pindex = regno * 8; 1080 pindex = regno * 8;
1077 1081
@@ -1240,6 +1244,8 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg
1240{ 1244{
1241 int i; 1245 int i;
1242 1246
1247 radeon_fifo_wait(20);
1248
1243 /* Workaround from XFree */ 1249 /* Workaround from XFree */
1244 if (rinfo->is_mobility) { 1250 if (rinfo->is_mobility) {
1245 /* A temporal workaround for the occational blanking on certain laptop 1251 /* A temporal workaround for the occational blanking on certain laptop
@@ -1335,7 +1341,7 @@ static void radeon_lvds_timer_func(unsigned long data)
1335{ 1341{
1336 struct radeonfb_info *rinfo = (struct radeonfb_info *)data; 1342 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1337 1343
1338 radeon_engine_idle(rinfo); 1344 radeon_engine_idle();
1339 1345
1340 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); 1346 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1341} 1347}
@@ -1353,11 +1359,10 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1353 if (nomodeset) 1359 if (nomodeset)
1354 return; 1360 return;
1355 1361
1356 radeon_engine_idle(rinfo);
1357
1358 if (!regs_only) 1362 if (!regs_only)
1359 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0); 1363 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1360 1364
1365 radeon_fifo_wait(31);
1361 for (i=0; i<10; i++) 1366 for (i=0; i<10; i++)
1362 OUTREG(common_regs[i].reg, common_regs[i].val); 1367 OUTREG(common_regs[i].reg, common_regs[i].val);
1363 1368
@@ -1385,6 +1390,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1385 radeon_write_pll_regs(rinfo, mode); 1390 radeon_write_pll_regs(rinfo, mode);
1386 1391
1387 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { 1392 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1393 radeon_fifo_wait(10);
1388 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); 1394 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1389 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); 1395 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1390 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); 1396 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
@@ -1399,6 +1405,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1399 if (!regs_only) 1405 if (!regs_only)
1400 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0); 1406 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1401 1407
1408 radeon_fifo_wait(2);
1402 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); 1409 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1403 1410
1404 return; 1411 return;
@@ -1549,7 +1556,7 @@ static int radeonfb_set_par(struct fb_info *info)
1549 /* We always want engine to be idle on a mode switch, even 1556 /* We always want engine to be idle on a mode switch, even
1550 * if we won't actually change the mode 1557 * if we won't actually change the mode
1551 */ 1558 */
1552 radeon_engine_idle(rinfo); 1559 radeon_engine_idle();
1553 1560
1554 hSyncStart = mode->xres + mode->right_margin; 1561 hSyncStart = mode->xres + mode->right_margin;
1555 hSyncEnd = hSyncStart + mode->hsync_len; 1562 hSyncEnd = hSyncStart + mode->hsync_len;
@@ -1844,6 +1851,7 @@ static int radeonfb_set_par(struct fb_info *info)
1844 return 0; 1851 return 0;
1845} 1852}
1846 1853
1854
1847static struct fb_ops radeonfb_ops = { 1855static struct fb_ops radeonfb_ops = {
1848 .owner = THIS_MODULE, 1856 .owner = THIS_MODULE,
1849 .fb_check_var = radeonfb_check_var, 1857 .fb_check_var = radeonfb_check_var,
@@ -1867,7 +1875,6 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1867 info->par = rinfo; 1875 info->par = rinfo;
1868 info->pseudo_palette = rinfo->pseudo_palette; 1876 info->pseudo_palette = rinfo->pseudo_palette;
1869 info->flags = FBINFO_DEFAULT 1877 info->flags = FBINFO_DEFAULT
1870 | FBINFO_HWACCEL_IMAGEBLIT
1871 | FBINFO_HWACCEL_COPYAREA 1878 | FBINFO_HWACCEL_COPYAREA
1872 | FBINFO_HWACCEL_FILLRECT 1879 | FBINFO_HWACCEL_FILLRECT
1873 | FBINFO_HWACCEL_XPAN 1880 | FBINFO_HWACCEL_XPAN
@@ -1999,6 +2006,7 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo)
1999 u32 tom = INREG(NB_TOM); 2006 u32 tom = INREG(NB_TOM);
2000 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); 2007 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2001 2008
2009 radeon_fifo_wait(6);
2002 OUTREG(MC_FB_LOCATION, tom); 2010 OUTREG(MC_FB_LOCATION, tom);
2003 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 2011 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2004 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 2012 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
diff --git a/drivers/video/aty/radeon_pm.c b/drivers/video/aty/radeon_pm.c
index 3df5015f1d13..675abdafc2d8 100644
--- a/drivers/video/aty/radeon_pm.c
+++ b/drivers/video/aty/radeon_pm.c
@@ -2653,9 +2653,9 @@ int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
2653 2653
2654 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { 2654 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
2655 /* Make sure engine is reset */ 2655 /* Make sure engine is reset */
2656 radeon_engine_idle(rinfo); 2656 radeon_engine_idle();
2657 radeonfb_engine_reset(rinfo); 2657 radeonfb_engine_reset(rinfo);
2658 radeon_engine_idle(rinfo); 2658 radeon_engine_idle();
2659 } 2659 }
2660 2660
2661 /* Blank display and LCD */ 2661 /* Blank display and LCD */
@@ -2767,7 +2767,7 @@ int radeonfb_pci_resume(struct pci_dev *pdev)
2767 2767
2768 rinfo->asleep = 0; 2768 rinfo->asleep = 0;
2769 } else 2769 } else
2770 radeon_engine_idle(rinfo); 2770 radeon_engine_idle();
2771 2771
2772 /* Restore display & engine */ 2772 /* Restore display & engine */
2773 radeon_write_mode (rinfo, &rinfo->state, 1); 2773 radeon_write_mode (rinfo, &rinfo->state, 1);
diff --git a/drivers/video/aty/radeonfb.h b/drivers/video/aty/radeonfb.h
index ea0b5b47acaf..3ea1b00fdd22 100644
--- a/drivers/video/aty/radeonfb.h
+++ b/drivers/video/aty/radeonfb.h
@@ -336,15 +336,7 @@ struct radeonfb_info {
336 int mon2_type; 336 int mon2_type;
337 u8 *mon2_EDID; 337 u8 *mon2_EDID;
338 338
339 /* accel bits */ 339 u32 dp_gui_master_cntl;
340 u32 dp_gui_mc_base;
341 u32 dp_gui_mc_cache;
342 u32 dp_cntl_cache;
343 u32 dp_brush_fg_cache;
344 u32 dp_brush_bg_cache;
345 u32 dp_src_fg_cache;
346 u32 dp_src_bg_cache;
347 u32 fifo_free;
348 340
349 struct pll_info pll; 341 struct pll_info pll;
350 342
@@ -356,7 +348,6 @@ struct radeonfb_info {
356 int lock_blank; 348 int lock_blank;
357 int dynclk; 349 int dynclk;
358 int no_schedule; 350 int no_schedule;
359 int gfx_mode;
360 enum radeon_pm_mode pm_mode; 351 enum radeon_pm_mode pm_mode;
361 reinit_function_ptr reinit_func; 352 reinit_function_ptr reinit_func;
362 353
@@ -401,14 +392,8 @@ static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
401#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) 392#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
402#define INREG16(addr) readw((rinfo->mmio_base)+addr) 393#define INREG16(addr) readw((rinfo->mmio_base)+addr)
403#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) 394#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
404
405#ifdef CONFIG_PPC
406#define INREG(addr) ({ eieio(); ld_le32(rinfo->mmio_base+(addr)); })
407#define OUTREG(addr,val) do { eieio(); st_le32(rinfo->mmio_base+(addr),(val)); } while(0)
408#else
409#define INREG(addr) readl((rinfo->mmio_base)+addr) 395#define INREG(addr) readl((rinfo->mmio_base)+addr)
410#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) 396#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
411#endif
412 397
413static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, 398static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
414 u32 val, u32 mask) 399 u32 val, u32 mask)
@@ -550,7 +535,17 @@ static inline u32 radeon_get_dstbpp(u16 depth)
550 * 2D Engine helper routines 535 * 2D Engine helper routines
551 */ 536 */
552 537
553extern void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries); 538static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
539{
540 int i;
541
542 for (i=0; i<2000000; i++) {
543 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
544 return;
545 udelay(1);
546 }
547 printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
548}
554 549
555static inline void radeon_engine_flush (struct radeonfb_info *rinfo) 550static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
556{ 551{
@@ -563,7 +558,7 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
563 /* Ensure FIFO is empty, ie, make sure the flush commands 558 /* Ensure FIFO is empty, ie, make sure the flush commands
564 * has reached the cache 559 * has reached the cache
565 */ 560 */
566 radeon_fifo_update_and_wait(rinfo, 64); 561 _radeon_fifo_wait (rinfo, 64);
567 562
568 /* Wait for the flush to complete */ 563 /* Wait for the flush to complete */
569 for (i=0; i < 2000000; i++) { 564 for (i=0; i < 2000000; i++) {
@@ -575,12 +570,12 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
575} 570}
576 571
577 572
578static inline void radeon_engine_idle(struct radeonfb_info *rinfo) 573static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
579{ 574{
580 int i; 575 int i;
581 576
582 /* ensure FIFO is empty before waiting for idle */ 577 /* ensure FIFO is empty before waiting for idle */
583 radeon_fifo_update_and_wait (rinfo, 64); 578 _radeon_fifo_wait (rinfo, 64);
584 579
585 for (i=0; i<2000000; i++) { 580 for (i=0; i<2000000; i++) {
586 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { 581 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
@@ -593,6 +588,8 @@ static inline void radeon_engine_idle(struct radeonfb_info *rinfo)
593} 588}
594 589
595 590
591#define radeon_engine_idle() _radeon_engine_idle(rinfo)
592#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
596#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) 593#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
597 594
598 595
@@ -622,7 +619,6 @@ extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
622extern int radeonfb_sync(struct fb_info *info); 619extern int radeonfb_sync(struct fb_info *info);
623extern void radeonfb_engine_init (struct radeonfb_info *rinfo); 620extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
624extern void radeonfb_engine_reset(struct radeonfb_info *rinfo); 621extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
625extern void radeon_fixup_mem_offset(struct radeonfb_info *rinfo);
626 622
627/* Other functions */ 623/* Other functions */
628extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch); 624extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
diff --git a/drivers/video/backlight/corgi_lcd.c b/drivers/video/backlight/corgi_lcd.c
index 2afd47eefe74..f8a4bb20f41a 100644
--- a/drivers/video/backlight/corgi_lcd.c
+++ b/drivers/video/backlight/corgi_lcd.c
@@ -439,7 +439,7 @@ static int corgi_bl_update_status(struct backlight_device *bd)
439 return corgi_bl_set_intensity(lcd, intensity); 439 return corgi_bl_set_intensity(lcd, intensity);
440} 440}
441 441
442void corgibl_limit_intensity(int limit) 442void corgi_lcd_limit_intensity(int limit)
443{ 443{
444 if (limit) 444 if (limit)
445 corgibl_flags |= CORGIBL_BATTLOW; 445 corgibl_flags |= CORGIBL_BATTLOW;
@@ -448,7 +448,7 @@ void corgibl_limit_intensity(int limit)
448 448
449 backlight_update_status(the_corgi_lcd->bl_dev); 449 backlight_update_status(the_corgi_lcd->bl_dev);
450} 450}
451EXPORT_SYMBOL(corgibl_limit_intensity); 451EXPORT_SYMBOL(corgi_lcd_limit_intensity);
452 452
453static struct backlight_ops corgi_bl_ops = { 453static struct backlight_ops corgi_bl_ops = {
454 .get_brightness = corgi_bl_get_intensity, 454 .get_brightness = corgi_bl_get_intensity,
diff --git a/drivers/video/backlight/da903x.c b/drivers/video/backlight/da903x.c
index 242c38250166..93bb4340cc64 100644
--- a/drivers/video/backlight/da903x.c
+++ b/drivers/video/backlight/da903x.c
@@ -119,6 +119,7 @@ static int da903x_backlight_probe(struct platform_device *pdev)
119 default: 119 default:
120 dev_err(&pdev->dev, "invalid backlight device ID(%d)\n", 120 dev_err(&pdev->dev, "invalid backlight device ID(%d)\n",
121 pdev->id); 121 pdev->id);
122 kfree(data);
122 return -EINVAL; 123 return -EINVAL;
123 } 124 }
124 125
@@ -130,6 +131,7 @@ static int da903x_backlight_probe(struct platform_device *pdev)
130 data, &da903x_backlight_ops); 131 data, &da903x_backlight_ops);
131 if (IS_ERR(bl)) { 132 if (IS_ERR(bl)) {
132 dev_err(&pdev->dev, "failed to register backlight\n"); 133 dev_err(&pdev->dev, "failed to register backlight\n");
134 kfree(data);
133 return PTR_ERR(bl); 135 return PTR_ERR(bl);
134 } 136 }
135 137
diff --git a/drivers/video/backlight/lcd.c b/drivers/video/backlight/lcd.c
index 8e1731d3b228..680e57b616cd 100644
--- a/drivers/video/backlight/lcd.c
+++ b/drivers/video/backlight/lcd.c
@@ -42,10 +42,13 @@ static int fb_notifier_callback(struct notifier_block *self,
42 42
43 mutex_lock(&ld->ops_lock); 43 mutex_lock(&ld->ops_lock);
44 if (!ld->ops->check_fb || ld->ops->check_fb(ld, evdata->info)) { 44 if (!ld->ops->check_fb || ld->ops->check_fb(ld, evdata->info)) {
45 if (event == FB_EVENT_BLANK) 45 if (event == FB_EVENT_BLANK) {
46 ld->ops->set_power(ld, *(int *)evdata->data); 46 if (ld->ops->set_power)
47 else 47 ld->ops->set_power(ld, *(int *)evdata->data);
48 ld->ops->set_mode(ld, evdata->data); 48 } else {
49 if (ld->ops->set_mode)
50 ld->ops->set_mode(ld, evdata->data);
51 }
49 } 52 }
50 mutex_unlock(&ld->ops_lock); 53 mutex_unlock(&ld->ops_lock);
51 return 0; 54 return 0;
diff --git a/drivers/video/cirrusfb.c b/drivers/video/cirrusfb.c
index 048b139f0e50..a2aa6ddffbe2 100644
--- a/drivers/video/cirrusfb.c
+++ b/drivers/video/cirrusfb.c
@@ -2049,7 +2049,7 @@ static void cirrusfb_pci_unmap(struct fb_info *info)
2049#endif /* CONFIG_PCI */ 2049#endif /* CONFIG_PCI */
2050 2050
2051#ifdef CONFIG_ZORRO 2051#ifdef CONFIG_ZORRO
2052static void __devexit cirrusfb_zorro_unmap(struct fb_info *info) 2052static void cirrusfb_zorro_unmap(struct fb_info *info)
2053{ 2053{
2054 struct cirrusfb_info *cinfo = info->par; 2054 struct cirrusfb_info *cinfo = info->par;
2055 struct zorro_dev *zdev = to_zorro_dev(info->device); 2055 struct zorro_dev *zdev = to_zorro_dev(info->device);
@@ -2462,8 +2462,7 @@ static int __init cirrusfb_init(void)
2462 2462
2463#ifndef MODULE 2463#ifndef MODULE
2464static int __init cirrusfb_setup(char *options) { 2464static int __init cirrusfb_setup(char *options) {
2465 char *this_opt, s[32]; 2465 char *this_opt;
2466 int i;
2467 2466
2468 DPRINTK("ENTER\n"); 2467 DPRINTK("ENTER\n");
2469 2468
diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c
index 64b3d30027b8..0b2adefe9e3d 100644
--- a/drivers/video/console/fbcon.c
+++ b/drivers/video/console/fbcon.c
@@ -2118,7 +2118,7 @@ static void fbcon_bmove_rec(struct vc_data *vc, struct display *p, int sy, int s
2118 height, width); 2118 height, width);
2119} 2119}
2120 2120
2121static __inline__ void updatescrollmode(struct display *p, 2121static void updatescrollmode(struct display *p,
2122 struct fb_info *info, 2122 struct fb_info *info,
2123 struct vc_data *vc) 2123 struct vc_data *vc)
2124{ 2124{
@@ -2389,16 +2389,13 @@ static int fbcon_blank(struct vc_data *vc, int blank, int mode_switch)
2389 2389
2390 if (!fbcon_is_inactive(vc, info)) { 2390 if (!fbcon_is_inactive(vc, info)) {
2391 if (ops->blank_state != blank) { 2391 if (ops->blank_state != blank) {
2392 int ret = 1;
2393
2394 ops->blank_state = blank; 2392 ops->blank_state = blank;
2395 fbcon_cursor(vc, blank ? CM_ERASE : CM_DRAW); 2393 fbcon_cursor(vc, blank ? CM_ERASE : CM_DRAW);
2396 ops->cursor_flash = (!blank); 2394 ops->cursor_flash = (!blank);
2397 2395
2398 if (info->fbops->fb_blank) 2396 if (!(info->flags & FBINFO_MISC_USEREVENT))
2399 ret = info->fbops->fb_blank(blank, info); 2397 if (fb_blank(info, blank))
2400 if (ret) 2398 fbcon_generic_blank(vc, info, blank);
2401 fbcon_generic_blank(vc, info, blank);
2402 } 2399 }
2403 2400
2404 if (!blank) 2401 if (!blank)
@@ -3534,12 +3531,18 @@ static void fbcon_exit(void)
3534 softback_buf = 0UL; 3531 softback_buf = 0UL;
3535 3532
3536 for (i = 0; i < FB_MAX; i++) { 3533 for (i = 0; i < FB_MAX; i++) {
3534 int pending;
3535
3537 mapped = 0; 3536 mapped = 0;
3538 info = registered_fb[i]; 3537 info = registered_fb[i];
3539 3538
3540 if (info == NULL) 3539 if (info == NULL)
3541 continue; 3540 continue;
3542 3541
3542 pending = cancel_work_sync(&info->queue);
3543 DPRINTK("fbcon: %s pending work\n", (pending ? "canceled" :
3544 "no"));
3545
3543 for (j = first_fb_vc; j <= last_fb_vc; j++) { 3546 for (j = first_fb_vc; j <= last_fb_vc; j++) {
3544 if (con2fb_map[j] == i) 3547 if (con2fb_map[j] == i)
3545 mapped = 1; 3548 mapped = 1;
diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c
index cd5f20da738a..3c65b0d67617 100644
--- a/drivers/video/fbmem.c
+++ b/drivers/video/fbmem.c
@@ -230,7 +230,7 @@ static void fb_set_logo_directpalette(struct fb_info *info,
230 greenshift = info->var.green.offset; 230 greenshift = info->var.green.offset;
231 blueshift = info->var.blue.offset; 231 blueshift = info->var.blue.offset;
232 232
233 for (i = 32; i < logo->clutsize; i++) 233 for (i = 32; i < 32 + logo->clutsize; i++)
234 palette[i] = i << redshift | i << greenshift | i << blueshift; 234 palette[i] = i << redshift | i << greenshift | i << blueshift;
235} 235}
236 236
@@ -1002,13 +1002,9 @@ fb_blank(struct fb_info *info, int blank)
1002 return ret; 1002 return ret;
1003} 1003}
1004 1004
1005static long 1005static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
1006fb_ioctl(struct file *file, unsigned int cmd, 1006 unsigned long arg)
1007 unsigned long arg)
1008{ 1007{
1009 struct inode *inode = file->f_path.dentry->d_inode;
1010 int fbidx = iminor(inode);
1011 struct fb_info *info;
1012 struct fb_ops *fb; 1008 struct fb_ops *fb;
1013 struct fb_var_screeninfo var; 1009 struct fb_var_screeninfo var;
1014 struct fb_fix_screeninfo fix; 1010 struct fb_fix_screeninfo fix;
@@ -1018,14 +1014,10 @@ fb_ioctl(struct file *file, unsigned int cmd,
1018 void __user *argp = (void __user *)arg; 1014 void __user *argp = (void __user *)arg;
1019 long ret = 0; 1015 long ret = 0;
1020 1016
1021 info = registered_fb[fbidx];
1022 mutex_lock(&info->lock);
1023 fb = info->fbops; 1017 fb = info->fbops;
1024 1018 if (!fb)
1025 if (!fb) {
1026 mutex_unlock(&info->lock);
1027 return -ENODEV; 1019 return -ENODEV;
1028 } 1020
1029 switch (cmd) { 1021 switch (cmd) {
1030 case FBIOGET_VSCREENINFO: 1022 case FBIOGET_VSCREENINFO:
1031 ret = copy_to_user(argp, &info->var, 1023 ret = copy_to_user(argp, &info->var,
@@ -1126,6 +1118,21 @@ fb_ioctl(struct file *file, unsigned int cmd,
1126 else 1118 else
1127 ret = fb->fb_ioctl(info, cmd, arg); 1119 ret = fb->fb_ioctl(info, cmd, arg);
1128 } 1120 }
1121 return ret;
1122}
1123
1124static long fb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1125__acquires(&info->lock)
1126__releases(&info->lock)
1127{
1128 struct inode *inode = file->f_path.dentry->d_inode;
1129 int fbidx = iminor(inode);
1130 struct fb_info *info;
1131 long ret;
1132
1133 info = registered_fb[fbidx];
1134 mutex_lock(&info->lock);
1135 ret = do_fb_ioctl(info, cmd, arg);
1129 mutex_unlock(&info->lock); 1136 mutex_unlock(&info->lock);
1130 return ret; 1137 return ret;
1131} 1138}
@@ -1157,8 +1164,8 @@ struct fb_cmap32 {
1157 compat_caddr_t transp; 1164 compat_caddr_t transp;
1158}; 1165};
1159 1166
1160static int fb_getput_cmap(struct inode *inode, struct file *file, 1167static int fb_getput_cmap(struct fb_info *info, unsigned int cmd,
1161 unsigned int cmd, unsigned long arg) 1168 unsigned long arg)
1162{ 1169{
1163 struct fb_cmap_user __user *cmap; 1170 struct fb_cmap_user __user *cmap;
1164 struct fb_cmap32 __user *cmap32; 1171 struct fb_cmap32 __user *cmap32;
@@ -1181,7 +1188,7 @@ static int fb_getput_cmap(struct inode *inode, struct file *file,
1181 put_user(compat_ptr(data), &cmap->transp)) 1188 put_user(compat_ptr(data), &cmap->transp))
1182 return -EFAULT; 1189 return -EFAULT;
1183 1190
1184 err = fb_ioctl(file, cmd, (unsigned long) cmap); 1191 err = do_fb_ioctl(info, cmd, (unsigned long) cmap);
1185 1192
1186 if (!err) { 1193 if (!err) {
1187 if (copy_in_user(&cmap32->start, 1194 if (copy_in_user(&cmap32->start,
@@ -1223,8 +1230,8 @@ static int do_fscreeninfo_to_user(struct fb_fix_screeninfo *fix,
1223 return err; 1230 return err;
1224} 1231}
1225 1232
1226static int fb_get_fscreeninfo(struct inode *inode, struct file *file, 1233static int fb_get_fscreeninfo(struct fb_info *info, unsigned int cmd,
1227 unsigned int cmd, unsigned long arg) 1234 unsigned long arg)
1228{ 1235{
1229 mm_segment_t old_fs; 1236 mm_segment_t old_fs;
1230 struct fb_fix_screeninfo fix; 1237 struct fb_fix_screeninfo fix;
@@ -1235,7 +1242,7 @@ static int fb_get_fscreeninfo(struct inode *inode, struct file *file,
1235 1242
1236 old_fs = get_fs(); 1243 old_fs = get_fs();
1237 set_fs(KERNEL_DS); 1244 set_fs(KERNEL_DS);
1238 err = fb_ioctl(file, cmd, (unsigned long) &fix); 1245 err = do_fb_ioctl(info, cmd, (unsigned long) &fix);
1239 set_fs(old_fs); 1246 set_fs(old_fs);
1240 1247
1241 if (!err) 1248 if (!err)
@@ -1244,8 +1251,10 @@ static int fb_get_fscreeninfo(struct inode *inode, struct file *file,
1244 return err; 1251 return err;
1245} 1252}
1246 1253
1247static long 1254static long fb_compat_ioctl(struct file *file, unsigned int cmd,
1248fb_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 1255 unsigned long arg)
1256__acquires(&info->lock)
1257__releases(&info->lock)
1249{ 1258{
1250 struct inode *inode = file->f_path.dentry->d_inode; 1259 struct inode *inode = file->f_path.dentry->d_inode;
1251 int fbidx = iminor(inode); 1260 int fbidx = iminor(inode);
@@ -1262,16 +1271,16 @@ fb_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1262 case FBIOPUT_CON2FBMAP: 1271 case FBIOPUT_CON2FBMAP:
1263 arg = (unsigned long) compat_ptr(arg); 1272 arg = (unsigned long) compat_ptr(arg);
1264 case FBIOBLANK: 1273 case FBIOBLANK:
1265 ret = fb_ioctl(file, cmd, arg); 1274 ret = do_fb_ioctl(info, cmd, arg);
1266 break; 1275 break;
1267 1276
1268 case FBIOGET_FSCREENINFO: 1277 case FBIOGET_FSCREENINFO:
1269 ret = fb_get_fscreeninfo(inode, file, cmd, arg); 1278 ret = fb_get_fscreeninfo(info, cmd, arg);
1270 break; 1279 break;
1271 1280
1272 case FBIOGETCMAP: 1281 case FBIOGETCMAP:
1273 case FBIOPUTCMAP: 1282 case FBIOPUTCMAP:
1274 ret = fb_getput_cmap(inode, file, cmd, arg); 1283 ret = fb_getput_cmap(info, cmd, arg);
1275 break; 1284 break;
1276 1285
1277 default: 1286 default:
@@ -1286,6 +1295,8 @@ fb_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1286 1295
1287static int 1296static int
1288fb_mmap(struct file *file, struct vm_area_struct * vma) 1297fb_mmap(struct file *file, struct vm_area_struct * vma)
1298__acquires(&info->lock)
1299__releases(&info->lock)
1289{ 1300{
1290 int fbidx = iminor(file->f_path.dentry->d_inode); 1301 int fbidx = iminor(file->f_path.dentry->d_inode);
1291 struct fb_info *info = registered_fb[fbidx]; 1302 struct fb_info *info = registered_fb[fbidx];
@@ -1339,6 +1350,8 @@ fb_mmap(struct file *file, struct vm_area_struct * vma)
1339 1350
1340static int 1351static int
1341fb_open(struct inode *inode, struct file *file) 1352fb_open(struct inode *inode, struct file *file)
1353__acquires(&info->lock)
1354__releases(&info->lock)
1342{ 1355{
1343 int fbidx = iminor(inode); 1356 int fbidx = iminor(inode);
1344 struct fb_info *info; 1357 struct fb_info *info;
@@ -1374,6 +1387,8 @@ out:
1374 1387
1375static int 1388static int
1376fb_release(struct inode *inode, struct file *file) 1389fb_release(struct inode *inode, struct file *file)
1390__acquires(&info->lock)
1391__releases(&info->lock)
1377{ 1392{
1378 struct fb_info * const info = file->private_data; 1393 struct fb_info * const info = file->private_data;
1379 1394
diff --git a/drivers/video/macfb.c b/drivers/video/macfb.c
index b790ddff76f9..ee380d5f3410 100644
--- a/drivers/video/macfb.c
+++ b/drivers/video/macfb.c
@@ -164,7 +164,6 @@ static struct fb_var_screeninfo macfb_defined = {
164}; 164};
165 165
166static struct fb_fix_screeninfo macfb_fix = { 166static struct fb_fix_screeninfo macfb_fix = {
167 .id = "Macintosh ",
168 .type = FB_TYPE_PACKED_PIXELS, 167 .type = FB_TYPE_PACKED_PIXELS,
169 .accel = FB_ACCEL_NONE, 168 .accel = FB_ACCEL_NONE,
170}; 169};
@@ -760,22 +759,22 @@ static int __init macfb_init(void)
760 759
761 switch(ndev->dr_hw) { 760 switch(ndev->dr_hw) {
762 case NUBUS_DRHW_APPLE_MDC: 761 case NUBUS_DRHW_APPLE_MDC:
763 strcat( macfb_fix.id, "Display Card" ); 762 strcpy(macfb_fix.id, "Mac Disp. Card");
764 macfb_setpalette = mdc_setpalette; 763 macfb_setpalette = mdc_setpalette;
765 macfb_defined.activate = FB_ACTIVATE_NOW; 764 macfb_defined.activate = FB_ACTIVATE_NOW;
766 break; 765 break;
767 case NUBUS_DRHW_APPLE_TFB: 766 case NUBUS_DRHW_APPLE_TFB:
768 strcat( macfb_fix.id, "Toby" ); 767 strcpy(macfb_fix.id, "Toby");
769 macfb_setpalette = toby_setpalette; 768 macfb_setpalette = toby_setpalette;
770 macfb_defined.activate = FB_ACTIVATE_NOW; 769 macfb_defined.activate = FB_ACTIVATE_NOW;
771 break; 770 break;
772 case NUBUS_DRHW_APPLE_JET: 771 case NUBUS_DRHW_APPLE_JET:
773 strcat( macfb_fix.id, "Jet"); 772 strcpy(macfb_fix.id, "Jet");
774 macfb_setpalette = jet_setpalette; 773 macfb_setpalette = jet_setpalette;
775 macfb_defined.activate = FB_ACTIVATE_NOW; 774 macfb_defined.activate = FB_ACTIVATE_NOW;
776 break; 775 break;
777 default: 776 default:
778 strcat( macfb_fix.id, "Generic NuBus" ); 777 strcpy(macfb_fix.id, "Generic NuBus");
779 break; 778 break;
780 } 779 }
781 } 780 }
@@ -786,21 +785,11 @@ static int __init macfb_init(void)
786 if (!video_is_nubus) 785 if (!video_is_nubus)
787 switch( mac_bi_data.id ) 786 switch( mac_bi_data.id )
788 { 787 {
789 /* These don't have onboard video. Eventually, we may
790 be able to write separate framebuffer drivers for
791 them (tobyfb.c, hiresfb.c, etc, etc) */
792 case MAC_MODEL_II:
793 case MAC_MODEL_IIX:
794 case MAC_MODEL_IICX:
795 case MAC_MODEL_IIFX:
796 strcat( macfb_fix.id, "Generic NuBus" );
797 break;
798
799 /* Valkyrie Quadras */ 788 /* Valkyrie Quadras */
800 case MAC_MODEL_Q630: 789 case MAC_MODEL_Q630:
801 /* I'm not sure about this one */ 790 /* I'm not sure about this one */
802 case MAC_MODEL_P588: 791 case MAC_MODEL_P588:
803 strcat( macfb_fix.id, "Valkyrie built-in" ); 792 strcpy(macfb_fix.id, "Valkyrie");
804 macfb_setpalette = valkyrie_setpalette; 793 macfb_setpalette = valkyrie_setpalette;
805 macfb_defined.activate = FB_ACTIVATE_NOW; 794 macfb_defined.activate = FB_ACTIVATE_NOW;
806 valkyrie_cmap_regs = ioremap(DAC_BASE, 0x1000); 795 valkyrie_cmap_regs = ioremap(DAC_BASE, 0x1000);
@@ -823,7 +812,7 @@ static int __init macfb_init(void)
823 case MAC_MODEL_Q700: 812 case MAC_MODEL_Q700:
824 case MAC_MODEL_Q900: 813 case MAC_MODEL_Q900:
825 case MAC_MODEL_Q950: 814 case MAC_MODEL_Q950:
826 strcat( macfb_fix.id, "DAFB built-in" ); 815 strcpy(macfb_fix.id, "DAFB");
827 macfb_setpalette = dafb_setpalette; 816 macfb_setpalette = dafb_setpalette;
828 macfb_defined.activate = FB_ACTIVATE_NOW; 817 macfb_defined.activate = FB_ACTIVATE_NOW;
829 dafb_cmap_regs = ioremap(DAFB_BASE, 0x1000); 818 dafb_cmap_regs = ioremap(DAFB_BASE, 0x1000);
@@ -831,7 +820,7 @@ static int __init macfb_init(void)
831 820
832 /* LC II uses the V8 framebuffer */ 821 /* LC II uses the V8 framebuffer */
833 case MAC_MODEL_LCII: 822 case MAC_MODEL_LCII:
834 strcat( macfb_fix.id, "V8 built-in" ); 823 strcpy(macfb_fix.id, "V8");
835 macfb_setpalette = v8_brazil_setpalette; 824 macfb_setpalette = v8_brazil_setpalette;
836 macfb_defined.activate = FB_ACTIVATE_NOW; 825 macfb_defined.activate = FB_ACTIVATE_NOW;
837 v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000); 826 v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000);
@@ -843,7 +832,7 @@ static int __init macfb_init(void)
843 case MAC_MODEL_IIVI: 832 case MAC_MODEL_IIVI:
844 case MAC_MODEL_IIVX: 833 case MAC_MODEL_IIVX:
845 case MAC_MODEL_P600: 834 case MAC_MODEL_P600:
846 strcat( macfb_fix.id, "Brazil built-in" ); 835 strcpy(macfb_fix.id, "Brazil");
847 macfb_setpalette = v8_brazil_setpalette; 836 macfb_setpalette = v8_brazil_setpalette;
848 macfb_defined.activate = FB_ACTIVATE_NOW; 837 macfb_defined.activate = FB_ACTIVATE_NOW;
849 v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000); 838 v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000);
@@ -860,7 +849,7 @@ static int __init macfb_init(void)
860 case MAC_MODEL_P460: 849 case MAC_MODEL_P460:
861 macfb_setpalette = v8_brazil_setpalette; 850 macfb_setpalette = v8_brazil_setpalette;
862 macfb_defined.activate = FB_ACTIVATE_NOW; 851 macfb_defined.activate = FB_ACTIVATE_NOW;
863 strcat( macfb_fix.id, "Sonora built-in" ); 852 strcpy(macfb_fix.id, "Sonora");
864 v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000); 853 v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000);
865 break; 854 break;
866 855
@@ -871,7 +860,7 @@ static int __init macfb_init(void)
871 case MAC_MODEL_IISI: 860 case MAC_MODEL_IISI:
872 macfb_setpalette = rbv_setpalette; 861 macfb_setpalette = rbv_setpalette;
873 macfb_defined.activate = FB_ACTIVATE_NOW; 862 macfb_defined.activate = FB_ACTIVATE_NOW;
874 strcat( macfb_fix.id, "RBV built-in" ); 863 strcpy(macfb_fix.id, "RBV");
875 rbv_cmap_regs = ioremap(DAC_BASE, 0x1000); 864 rbv_cmap_regs = ioremap(DAC_BASE, 0x1000);
876 break; 865 break;
877 866
@@ -880,7 +869,7 @@ static int __init macfb_init(void)
880 case MAC_MODEL_C660: 869 case MAC_MODEL_C660:
881 macfb_setpalette = civic_setpalette; 870 macfb_setpalette = civic_setpalette;
882 macfb_defined.activate = FB_ACTIVATE_NOW; 871 macfb_defined.activate = FB_ACTIVATE_NOW;
883 strcat( macfb_fix.id, "Civic built-in" ); 872 strcpy(macfb_fix.id, "Civic");
884 civic_cmap_regs = ioremap(CIVIC_BASE, 0x1000); 873 civic_cmap_regs = ioremap(CIVIC_BASE, 0x1000);
885 break; 874 break;
886 875
@@ -901,7 +890,7 @@ static int __init macfb_init(void)
901 v8_brazil_cmap_regs = 890 v8_brazil_cmap_regs =
902 ioremap(DAC_BASE, 0x1000); 891 ioremap(DAC_BASE, 0x1000);
903 } 892 }
904 strcat( macfb_fix.id, "LC built-in" ); 893 strcpy(macfb_fix.id, "LC");
905 break; 894 break;
906 /* We think this may be like the LC II */ 895 /* We think this may be like the LC II */
907 case MAC_MODEL_CCL: 896 case MAC_MODEL_CCL:
@@ -911,18 +900,18 @@ static int __init macfb_init(void)
911 v8_brazil_cmap_regs = 900 v8_brazil_cmap_regs =
912 ioremap(DAC_BASE, 0x1000); 901 ioremap(DAC_BASE, 0x1000);
913 } 902 }
914 strcat( macfb_fix.id, "Color Classic built-in" ); 903 strcpy(macfb_fix.id, "Color Classic");
915 break; 904 break;
916 905
917 /* And we *do* mean "weirdos" */ 906 /* And we *do* mean "weirdos" */
918 case MAC_MODEL_TV: 907 case MAC_MODEL_TV:
919 strcat( macfb_fix.id, "Mac TV built-in" ); 908 strcpy(macfb_fix.id, "Mac TV");
920 break; 909 break;
921 910
922 /* These don't have colour, so no need to worry */ 911 /* These don't have colour, so no need to worry */
923 case MAC_MODEL_SE30: 912 case MAC_MODEL_SE30:
924 case MAC_MODEL_CLII: 913 case MAC_MODEL_CLII:
925 strcat( macfb_fix.id, "Monochrome built-in" ); 914 strcpy(macfb_fix.id, "Monochrome");
926 break; 915 break;
927 916
928 /* Powerbooks are particularly difficult. Many of 917 /* Powerbooks are particularly difficult. Many of
@@ -935,7 +924,7 @@ static int __init macfb_init(void)
935 case MAC_MODEL_PB140: 924 case MAC_MODEL_PB140:
936 case MAC_MODEL_PB145: 925 case MAC_MODEL_PB145:
937 case MAC_MODEL_PB170: 926 case MAC_MODEL_PB170:
938 strcat( macfb_fix.id, "DDC built-in" ); 927 strcpy(macfb_fix.id, "DDC");
939 break; 928 break;
940 929
941 /* Internal is GSC, External (if present) is ViSC */ 930 /* Internal is GSC, External (if present) is ViSC */
@@ -945,13 +934,13 @@ static int __init macfb_init(void)
945 case MAC_MODEL_PB180: 934 case MAC_MODEL_PB180:
946 case MAC_MODEL_PB210: 935 case MAC_MODEL_PB210:
947 case MAC_MODEL_PB230: 936 case MAC_MODEL_PB230:
948 strcat( macfb_fix.id, "GSC built-in" ); 937 strcpy(macfb_fix.id, "GSC");
949 break; 938 break;
950 939
951 /* Internal is TIM, External is ViSC */ 940 /* Internal is TIM, External is ViSC */
952 case MAC_MODEL_PB165C: 941 case MAC_MODEL_PB165C:
953 case MAC_MODEL_PB180C: 942 case MAC_MODEL_PB180C:
954 strcat( macfb_fix.id, "TIM built-in" ); 943 strcpy(macfb_fix.id, "TIM");
955 break; 944 break;
956 945
957 /* Internal is CSC, External is Keystone+Ariel. */ 946 /* Internal is CSC, External is Keystone+Ariel. */
@@ -963,12 +952,12 @@ static int __init macfb_init(void)
963 case MAC_MODEL_PB280C: 952 case MAC_MODEL_PB280C:
964 macfb_setpalette = csc_setpalette; 953 macfb_setpalette = csc_setpalette;
965 macfb_defined.activate = FB_ACTIVATE_NOW; 954 macfb_defined.activate = FB_ACTIVATE_NOW;
966 strcat( macfb_fix.id, "CSC built-in" ); 955 strcpy(macfb_fix.id, "CSC");
967 csc_cmap_regs = ioremap(CSC_BASE, 0x1000); 956 csc_cmap_regs = ioremap(CSC_BASE, 0x1000);
968 break; 957 break;
969 958
970 default: 959 default:
971 strcat( macfb_fix.id, "Unknown/Unsupported built-in" ); 960 strcpy(macfb_fix.id, "Unknown");
972 break; 961 break;
973 } 962 }
974 963
@@ -978,16 +967,23 @@ static int __init macfb_init(void)
978 fb_info.pseudo_palette = pseudo_palette; 967 fb_info.pseudo_palette = pseudo_palette;
979 fb_info.flags = FBINFO_DEFAULT; 968 fb_info.flags = FBINFO_DEFAULT;
980 969
981 fb_alloc_cmap(&fb_info.cmap, video_cmap_len, 0); 970 err = fb_alloc_cmap(&fb_info.cmap, video_cmap_len, 0);
971 if (err)
972 goto fail_unmap;
982 973
983 err = register_framebuffer(&fb_info); 974 err = register_framebuffer(&fb_info);
984 if (!err) 975 if (err)
985 printk("fb%d: %s frame buffer device\n", 976 goto fail_dealloc;
986 fb_info.node, fb_info.fix.id); 977
987 else { 978 printk("fb%d: %s frame buffer device\n",
988 iounmap(fb_info.screen_base); 979 fb_info.node, fb_info.fix.id);
989 iounmap_macfb(); 980 return 0;
990 } 981
982fail_dealloc:
983 fb_dealloc_cmap(&fb_info.cmap);
984fail_unmap:
985 iounmap(fb_info.screen_base);
986 iounmap_macfb();
991 return err; 987 return err;
992} 988}
993 989
diff --git a/drivers/video/mb862xx/Makefile b/drivers/video/mb862xx/Makefile
new file mode 100644
index 000000000000..07664814bb1d
--- /dev/null
+++ b/drivers/video/mb862xx/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the MB862xx framebuffer driver
3#
4
5obj-$(CONFIG_FB_MB862XX) := mb862xxfb.o
diff --git a/drivers/video/mb862xx/mb862xx_reg.h b/drivers/video/mb862xx/mb862xx_reg.h
new file mode 100644
index 000000000000..2ba65e118500
--- /dev/null
+++ b/drivers/video/mb862xx/mb862xx_reg.h
@@ -0,0 +1,138 @@
1/*
2 * Fujitsu MB862xx Graphics Controller Registers/Bits
3 */
4
5#ifndef _MB862XX_REG_H
6#define _MB862XX_REG_H
7
8#ifdef MB862XX_MMIO_BOTTOM
9#define MB862XX_MMIO_BASE 0x03fc0000
10#else
11#define MB862XX_MMIO_BASE 0x01fc0000
12#endif
13#define MB862XX_I2C_BASE 0x0000c000
14#define MB862XX_DISP_BASE 0x00010000
15#define MB862XX_CAP_BASE 0x00018000
16#define MB862XX_DRAW_BASE 0x00030000
17#define MB862XX_GEO_BASE 0x00038000
18#define MB862XX_PIO_BASE 0x00038000
19#define MB862XX_MMIO_SIZE 0x40000
20
21/* Host interface/pio registers */
22#define GC_IST 0x00000020
23#define GC_IMASK 0x00000024
24#define GC_SRST 0x0000002c
25#define GC_CCF 0x00000038
26#define GC_CID 0x000000f0
27#define GC_REVISION 0x00000084
28
29#define GC_CCF_CGE_100 0x00000000
30#define GC_CCF_CGE_133 0x00040000
31#define GC_CCF_CGE_166 0x00080000
32#define GC_CCF_COT_100 0x00000000
33#define GC_CCF_COT_133 0x00010000
34#define GC_CID_CNAME_MSK 0x0000ff00
35#define GC_CID_VERSION_MSK 0x000000ff
36
37/* define enabled interrupts hereby */
38#define GC_INT_EN 0x00000000
39
40/* Memory interface mode register */
41#define GC_MMR 0x0000fffc
42
43/* Display Controller registers */
44#define GC_DCM0 0x00000000
45#define GC_HTP 0x00000004
46#define GC_HDB_HDP 0x00000008
47#define GC_VSW_HSW_HSP 0x0000000c
48#define GC_VTR 0x00000010
49#define GC_VDP_VSP 0x00000014
50#define GC_WY_WX 0x00000018
51#define GC_WH_WW 0x0000001c
52#define GC_L0M 0x00000020
53#define GC_L0OA0 0x00000024
54#define GC_L0DA0 0x00000028
55#define GC_L0DY_L0DX 0x0000002c
56#define GC_DCM1 0x00000100
57#define GC_L0EM 0x00000110
58#define GC_L0WY_L0WX 0x00000114
59#define GC_L0WH_L0WW 0x00000118
60#define GC_DCM2 0x00000104
61#define GC_DCM3 0x00000108
62#define GC_CPM_CUTC 0x000000a0
63#define GC_CUOA0 0x000000a4
64#define GC_CUY0_CUX0 0x000000a8
65#define GC_CUOA1 0x000000ac
66#define GC_CUY1_CUX1 0x000000b0
67#define GC_L0PAL0 0x00000400
68
69#define GC_CPM_CEN0 0x00100000
70#define GC_CPM_CEN1 0x00200000
71
72#define GC_DCM01_ESY 0x00000004
73#define GC_DCM01_SC 0x00003f00
74#define GC_DCM01_RESV 0x00004000
75#define GC_DCM01_CKS 0x00008000
76#define GC_DCM01_L0E 0x00010000
77#define GC_DCM01_DEN 0x80000000
78#define GC_L0M_L0C_8 0x00000000
79#define GC_L0M_L0C_16 0x80000000
80#define GC_L0EM_L0EC_24 0x40000000
81#define GC_L0M_L0W_UNIT 64
82
83#define GC_DISP_REFCLK_400 400
84
85/* Carmine specific */
86#define MB86297_DRAW_BASE 0x00020000
87#define MB86297_DISP0_BASE 0x00100000
88#define MB86297_DISP1_BASE 0x00140000
89#define MB86297_WRBACK_BASE 0x00180000
90#define MB86297_CAP0_BASE 0x00200000
91#define MB86297_CAP1_BASE 0x00280000
92#define MB86297_DRAMCTRL_BASE 0x00300000
93#define MB86297_CTRL_BASE 0x00400000
94#define MB86297_I2C_BASE 0x00500000
95
96#define GC_CTRL_STATUS 0x00000000
97#define GC_CTRL_INT_MASK 0x00000004
98#define GC_CTRL_CLK_ENABLE 0x0000000c
99#define GC_CTRL_SOFT_RST 0x00000010
100
101#define GC_CTRL_CLK_EN_DRAM 0x00000001
102#define GC_CTRL_CLK_EN_2D3D 0x00000002
103#define GC_CTRL_CLK_EN_DISP0 0x00000020
104#define GC_CTRL_CLK_EN_DISP1 0x00000040
105
106#define GC_2D3D_REV 0x000004b4
107#define GC_RE_REVISION 0x24240200
108
109/* define enabled interrupts hereby */
110#define GC_CARMINE_INT_EN 0x00000004
111
112/* DRAM controller */
113#define GC_DCTL_MODE_ADD 0x00000000
114#define GC_DCTL_SETTIME1_EMODE 0x00000004
115#define GC_DCTL_REFRESH_SETTIME2 0x00000008
116#define GC_DCTL_RSV0_STATES 0x0000000C
117#define GC_DCTL_RSV2_RSV1 0x00000010
118#define GC_DCTL_DDRIF2_DDRIF1 0x00000014
119#define GC_DCTL_IOCONT1_IOCONT0 0x00000024
120
121#define GC_DCTL_STATES_MSK 0x0000000f
122#define GC_DCTL_INIT_WAIT_CNT 3000
123#define GC_DCTL_INIT_WAIT_INTERVAL 1
124
125/* DRAM ctrl values for Carmine PCI Eval. board */
126#define GC_EVB_DCTL_MODE_ADD 0x012105c3
127#define GC_EVB_DCTL_MODE_ADD_AFT_RST 0x002105c3
128#define GC_EVB_DCTL_SETTIME1_EMODE 0x47498000
129#define GC_EVB_DCTL_REFRESH_SETTIME2 0x00422a22
130#define GC_EVB_DCTL_RSV0_STATES 0x00200003
131#define GC_EVB_DCTL_RSV0_STATES_AFT_RST 0x00200002
132#define GC_EVB_DCTL_RSV2_RSV1 0x0000000f
133#define GC_EVB_DCTL_DDRIF2_DDRIF1 0x00556646
134#define GC_EVB_DCTL_IOCONT1_IOCONT0 0x05550555
135
136#define GC_DISP_REFCLK_533 533
137
138#endif
diff --git a/drivers/video/mb862xx/mb862xxfb.c b/drivers/video/mb862xx/mb862xxfb.c
new file mode 100644
index 000000000000..fb64234a3825
--- /dev/null
+++ b/drivers/video/mb862xx/mb862xxfb.c
@@ -0,0 +1,1061 @@
1/*
2 * drivers/mb862xx/mb862xxfb.c
3 *
4 * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver
5 *
6 * (C) 2008 Anatolij Gustschin <agust@denx.de>
7 * DENX Software Engineering
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#undef DEBUG
16
17#include <linux/fb.h>
18#include <linux/delay.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/pci.h>
22#if defined(CONFIG_PPC_OF)
23#include <linux/of_platform.h>
24#endif
25#include "mb862xxfb.h"
26#include "mb862xx_reg.h"
27
28#define NR_PALETTE 256
29#define MB862XX_MEM_SIZE 0x1000000
30#define CORALP_MEM_SIZE 0x4000000
31#define CARMINE_MEM_SIZE 0x8000000
32#define DRV_NAME "mb862xxfb"
33
34#if defined(CONFIG_LWMON5)
35static struct mb862xx_gc_mode lwmon5_gc_mode = {
36 /* Mode for Sharp LQ104V1DG61 TFT LCD Panel */
37 { "640x480", 60, 640, 480, 40000, 48, 16, 32, 11, 96, 2, 0, 0, 0 },
38 /* 16 bits/pixel, 32MB, 100MHz, SDRAM memory mode value */
39 16, 0x2000000, GC_CCF_COT_100, 0x414fb7f2
40};
41#endif
42
43#if defined(CONFIG_SOCRATES)
44static struct mb862xx_gc_mode socrates_gc_mode = {
45 /* Mode for Prime View PM070WL4 TFT LCD Panel */
46 { "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 },
47 /* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */
48 16, 0x1000000, GC_CCF_COT_133, 0x4157ba63
49};
50#endif
51
52/* Helpers */
53static inline int h_total(struct fb_var_screeninfo *var)
54{
55 return var->xres + var->left_margin +
56 var->right_margin + var->hsync_len;
57}
58
59static inline int v_total(struct fb_var_screeninfo *var)
60{
61 return var->yres + var->upper_margin +
62 var->lower_margin + var->vsync_len;
63}
64
65static inline int hsp(struct fb_var_screeninfo *var)
66{
67 return var->xres + var->right_margin - 1;
68}
69
70static inline int vsp(struct fb_var_screeninfo *var)
71{
72 return var->yres + var->lower_margin - 1;
73}
74
75static inline int d_pitch(struct fb_var_screeninfo *var)
76{
77 return var->xres * var->bits_per_pixel / 8;
78}
79
80static inline unsigned int chan_to_field(unsigned int chan,
81 struct fb_bitfield *bf)
82{
83 chan &= 0xffff;
84 chan >>= 16 - bf->length;
85 return chan << bf->offset;
86}
87
88static int mb862xxfb_setcolreg(unsigned regno,
89 unsigned red, unsigned green, unsigned blue,
90 unsigned transp, struct fb_info *info)
91{
92 struct mb862xxfb_par *par = info->par;
93 unsigned int val;
94
95 switch (info->fix.visual) {
96 case FB_VISUAL_TRUECOLOR:
97 if (regno < 16) {
98 val = chan_to_field(red, &info->var.red);
99 val |= chan_to_field(green, &info->var.green);
100 val |= chan_to_field(blue, &info->var.blue);
101 par->pseudo_palette[regno] = val;
102 }
103 break;
104 case FB_VISUAL_PSEUDOCOLOR:
105 if (regno < 256) {
106 val = (red >> 8) << 16;
107 val |= (green >> 8) << 8;
108 val |= blue >> 8;
109 outreg(disp, GC_L0PAL0 + (regno * 4), val);
110 }
111 break;
112 default:
113 return 1; /* unsupported type */
114 }
115 return 0;
116}
117
118static int mb862xxfb_check_var(struct fb_var_screeninfo *var,
119 struct fb_info *fbi)
120{
121 unsigned long tmp;
122
123 if (fbi->dev)
124 dev_dbg(fbi->dev, "%s\n", __func__);
125
126 /* check if these values fit into the registers */
127 if (var->hsync_len > 255 || var->vsync_len > 255)
128 return -EINVAL;
129
130 if ((var->xres + var->right_margin) >= 4096)
131 return -EINVAL;
132
133 if ((var->yres + var->lower_margin) > 4096)
134 return -EINVAL;
135
136 if (h_total(var) > 4096 || v_total(var) > 4096)
137 return -EINVAL;
138
139 if (var->xres_virtual > 4096 || var->yres_virtual > 4096)
140 return -EINVAL;
141
142 if (var->bits_per_pixel <= 8)
143 var->bits_per_pixel = 8;
144 else if (var->bits_per_pixel <= 16)
145 var->bits_per_pixel = 16;
146 else if (var->bits_per_pixel <= 32)
147 var->bits_per_pixel = 32;
148
149 /*
150 * can cope with 8,16 or 24/32bpp if resulting
151 * pitch is divisible by 64 without remainder
152 */
153 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) {
154 int r;
155
156 var->bits_per_pixel = 0;
157 do {
158 var->bits_per_pixel += 8;
159 r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT;
160 } while (r && var->bits_per_pixel <= 32);
161
162 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT)
163 return -EINVAL;
164 }
165
166 /* line length is going to be 128 bit aligned */
167 tmp = (var->xres * var->bits_per_pixel) / 8;
168 if ((tmp & 15) != 0)
169 return -EINVAL;
170
171 /* set r/g/b positions and validate bpp */
172 switch (var->bits_per_pixel) {
173 case 8:
174 var->red.length = var->bits_per_pixel;
175 var->green.length = var->bits_per_pixel;
176 var->blue.length = var->bits_per_pixel;
177 var->red.offset = 0;
178 var->green.offset = 0;
179 var->blue.offset = 0;
180 var->transp.length = 0;
181 break;
182 case 16:
183 var->red.length = 5;
184 var->green.length = 5;
185 var->blue.length = 5;
186 var->red.offset = 10;
187 var->green.offset = 5;
188 var->blue.offset = 0;
189 var->transp.length = 0;
190 break;
191 case 24:
192 case 32:
193 var->transp.length = 8;
194 var->red.length = 8;
195 var->green.length = 8;
196 var->blue.length = 8;
197 var->transp.offset = 24;
198 var->red.offset = 16;
199 var->green.offset = 8;
200 var->blue.offset = 0;
201 break;
202 default:
203 return -EINVAL;
204 }
205 return 0;
206}
207
208/*
209 * set display parameters
210 */
211static int mb862xxfb_set_par(struct fb_info *fbi)
212{
213 struct mb862xxfb_par *par = fbi->par;
214 unsigned long reg, sc;
215
216 dev_dbg(par->dev, "%s\n", __func__);
217
218 if (par->pre_init)
219 return 0;
220
221 /* disp off */
222 reg = inreg(disp, GC_DCM1);
223 reg &= ~GC_DCM01_DEN;
224 outreg(disp, GC_DCM1, reg);
225
226 /* set display reference clock div. */
227 sc = par->refclk / (1000000 / fbi->var.pixclock) - 1;
228 reg = inreg(disp, GC_DCM1);
229 reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC);
230 reg |= sc << 8;
231 outreg(disp, GC_DCM1, reg);
232 dev_dbg(par->dev, "SC 0x%lx\n", sc);
233
234 /* disp dimension, format */
235 reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT,
236 (fbi->var.yres - 1));
237 if (fbi->var.bits_per_pixel == 16)
238 reg |= GC_L0M_L0C_16;
239 outreg(disp, GC_L0M, reg);
240
241 if (fbi->var.bits_per_pixel == 32) {
242 reg = inreg(disp, GC_L0EM);
243 outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24);
244 }
245 outreg(disp, GC_WY_WX, 0);
246 reg = pack(fbi->var.yres - 1, fbi->var.xres);
247 outreg(disp, GC_WH_WW, reg);
248 outreg(disp, GC_L0OA0, 0);
249 outreg(disp, GC_L0DA0, 0);
250 outreg(disp, GC_L0DY_L0DX, 0);
251 outreg(disp, GC_L0WY_L0WX, 0);
252 outreg(disp, GC_L0WH_L0WW, reg);
253
254 /* both HW-cursors off */
255 reg = inreg(disp, GC_CPM_CUTC);
256 reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1);
257 outreg(disp, GC_CPM_CUTC, reg);
258
259 /* timings */
260 reg = pack(fbi->var.xres - 1, fbi->var.xres - 1);
261 outreg(disp, GC_HDB_HDP, reg);
262 reg = pack((fbi->var.yres - 1), vsp(&fbi->var));
263 outreg(disp, GC_VDP_VSP, reg);
264 reg = ((fbi->var.vsync_len - 1) << 24) |
265 pack((fbi->var.hsync_len - 1), hsp(&fbi->var));
266 outreg(disp, GC_VSW_HSW_HSP, reg);
267 outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0));
268 outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0));
269
270 /* display on */
271 reg = inreg(disp, GC_DCM1);
272 reg |= GC_DCM01_DEN | GC_DCM01_L0E;
273 reg &= ~GC_DCM01_ESY;
274 outreg(disp, GC_DCM1, reg);
275 return 0;
276}
277
278static int mb862xxfb_pan(struct fb_var_screeninfo *var,
279 struct fb_info *info)
280{
281 struct mb862xxfb_par *par = info->par;
282 unsigned long reg;
283
284 reg = pack(var->yoffset, var->xoffset);
285 outreg(disp, GC_L0WY_L0WX, reg);
286
287 reg = pack(var->yres_virtual, var->xres_virtual);
288 outreg(disp, GC_L0WH_L0WW, reg);
289 return 0;
290}
291
292static int mb862xxfb_blank(int mode, struct fb_info *fbi)
293{
294 struct mb862xxfb_par *par = fbi->par;
295 unsigned long reg;
296
297 dev_dbg(fbi->dev, "blank mode=%d\n", mode);
298
299 switch (mode) {
300 case FB_BLANK_POWERDOWN:
301 reg = inreg(disp, GC_DCM1);
302 reg &= ~GC_DCM01_DEN;
303 outreg(disp, GC_DCM1, reg);
304 break;
305 case FB_BLANK_UNBLANK:
306 reg = inreg(disp, GC_DCM1);
307 reg |= GC_DCM01_DEN;
308 outreg(disp, GC_DCM1, reg);
309 break;
310 case FB_BLANK_NORMAL:
311 case FB_BLANK_VSYNC_SUSPEND:
312 case FB_BLANK_HSYNC_SUSPEND:
313 default:
314 return 1;
315 }
316 return 0;
317}
318
319/* framebuffer ops */
320static struct fb_ops mb862xxfb_ops = {
321 .owner = THIS_MODULE,
322 .fb_check_var = mb862xxfb_check_var,
323 .fb_set_par = mb862xxfb_set_par,
324 .fb_setcolreg = mb862xxfb_setcolreg,
325 .fb_blank = mb862xxfb_blank,
326 .fb_pan_display = mb862xxfb_pan,
327 .fb_fillrect = cfb_fillrect,
328 .fb_copyarea = cfb_copyarea,
329 .fb_imageblit = cfb_imageblit,
330};
331
332/* initialize fb_info data */
333static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
334{
335 struct mb862xxfb_par *par = fbi->par;
336 struct mb862xx_gc_mode *mode = par->gc_mode;
337 unsigned long reg;
338
339 fbi->fbops = &mb862xxfb_ops;
340 fbi->pseudo_palette = par->pseudo_palette;
341 fbi->screen_base = par->fb_base;
342 fbi->screen_size = par->mapped_vram;
343
344 strcpy(fbi->fix.id, DRV_NAME);
345 fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
346 fbi->fix.smem_len = par->mapped_vram;
347 fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
348 fbi->fix.mmio_len = par->mmio_len;
349 fbi->fix.accel = FB_ACCEL_NONE;
350 fbi->fix.type = FB_TYPE_PACKED_PIXELS;
351 fbi->fix.type_aux = 0;
352 fbi->fix.xpanstep = 1;
353 fbi->fix.ypanstep = 1;
354 fbi->fix.ywrapstep = 0;
355
356 reg = inreg(disp, GC_DCM1);
357 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) {
358 /* get the disp mode from active display cfg */
359 unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1;
360 unsigned long hsp, vsp, ht, vt;
361
362 dev_dbg(par->dev, "using bootloader's disp. mode\n");
363 fbi->var.pixclock = (sc * 1000000) / par->refclk;
364 fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1;
365 reg = inreg(disp, GC_VDP_VSP);
366 fbi->var.yres = ((reg >> 16) & 0x0fff) + 1;
367 vsp = (reg & 0x0fff) + 1;
368 fbi->var.xres_virtual = fbi->var.xres;
369 fbi->var.yres_virtual = fbi->var.yres;
370 reg = inreg(disp, GC_L0EM);
371 if (reg & GC_L0EM_L0EC_24) {
372 fbi->var.bits_per_pixel = 32;
373 } else {
374 reg = inreg(disp, GC_L0M);
375 if (reg & GC_L0M_L0C_16)
376 fbi->var.bits_per_pixel = 16;
377 else
378 fbi->var.bits_per_pixel = 8;
379 }
380 reg = inreg(disp, GC_VSW_HSW_HSP);
381 fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1;
382 fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1;
383 hsp = (reg & 0xffff) + 1;
384 ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1;
385 fbi->var.right_margin = hsp - fbi->var.xres;
386 fbi->var.left_margin = ht - hsp - fbi->var.hsync_len;
387 vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1;
388 fbi->var.lower_margin = vsp - fbi->var.yres;
389 fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len;
390 } else if (mode) {
391 dev_dbg(par->dev, "using supplied mode\n");
392 fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode);
393 fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8;
394 } else {
395 int ret;
396
397 ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60",
398 NULL, 0, NULL, 16);
399 if (ret == 0 || ret == 4) {
400 dev_err(par->dev,
401 "failed to get initial mode\n");
402 return -EINVAL;
403 }
404 }
405
406 fbi->var.xoffset = 0;
407 fbi->var.yoffset = 0;
408 fbi->var.grayscale = 0;
409 fbi->var.nonstd = 0;
410 fbi->var.height = -1;
411 fbi->var.width = -1;
412 fbi->var.accel_flags = 0;
413 fbi->var.vmode = FB_VMODE_NONINTERLACED;
414 fbi->var.activate = FB_ACTIVATE_NOW;
415 fbi->flags = FBINFO_DEFAULT |
416#ifdef __BIG_ENDIAN
417 FBINFO_FOREIGN_ENDIAN |
418#endif
419 FBINFO_HWACCEL_XPAN |
420 FBINFO_HWACCEL_YPAN;
421
422 /* check and possibly fix bpp */
423 if ((fbi->fbops->fb_check_var)(&fbi->var, fbi))
424 dev_err(par->dev, "check_var() failed on initial setup?\n");
425
426 fbi->fix.visual = fbi->var.bits_per_pixel == 8 ?
427 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
428 fbi->fix.line_length = (fbi->var.xres_virtual *
429 fbi->var.bits_per_pixel) / 8;
430 return 0;
431}
432
433/*
434 * show some display controller and cursor registers
435 */
436static ssize_t mb862xxfb_show_dispregs(struct device *dev,
437 struct device_attribute *attr, char *buf)
438{
439 struct fb_info *fbi = dev_get_drvdata(dev);
440 struct mb862xxfb_par *par = fbi->par;
441 char *ptr = buf;
442 unsigned int reg;
443
444 for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4)
445 ptr += sprintf(ptr, "%08x = %08x\n",
446 reg, inreg(disp, reg));
447
448 for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4)
449 ptr += sprintf(ptr, "%08x = %08x\n",
450 reg, inreg(disp, reg));
451
452 for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4)
453 ptr += sprintf(ptr, "%08x = %08x\n",
454 reg, inreg(disp, reg));
455
456 return ptr - buf;
457}
458
459static DEVICE_ATTR(dispregs, 0444, mb862xxfb_show_dispregs, NULL);
460
461irqreturn_t mb862xx_intr(int irq, void *dev_id)
462{
463 struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id;
464 unsigned long reg_ist, mask;
465
466 if (!par)
467 return IRQ_NONE;
468
469 if (par->type == BT_CARMINE) {
470 /* Get Interrupt Status */
471 reg_ist = inreg(ctrl, GC_CTRL_STATUS);
472 mask = inreg(ctrl, GC_CTRL_INT_MASK);
473 if (reg_ist == 0)
474 return IRQ_HANDLED;
475
476 reg_ist &= mask;
477 if (reg_ist == 0)
478 return IRQ_HANDLED;
479
480 /* Clear interrupt status */
481 outreg(ctrl, 0x0, reg_ist);
482 } else {
483 /* Get status */
484 reg_ist = inreg(host, GC_IST);
485 mask = inreg(host, GC_IMASK);
486
487 reg_ist &= mask;
488 if (reg_ist == 0)
489 return IRQ_HANDLED;
490
491 /* Clear status */
492 outreg(host, GC_IST, ~reg_ist);
493 }
494 return IRQ_HANDLED;
495}
496
497#if defined(CONFIG_FB_MB862XX_LIME)
498/*
499 * GDC (Lime, Coral(B/Q), Mint, ...) on host bus
500 */
501static int mb862xx_gdc_init(struct mb862xxfb_par *par)
502{
503 unsigned long ccf, mmr;
504 unsigned long ver, rev;
505
506 if (!par)
507 return -ENODEV;
508
509#if defined(CONFIG_FB_PRE_INIT_FB)
510 par->pre_init = 1;
511#endif
512 par->host = par->mmio_base;
513 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
514 par->disp = par->mmio_base + MB862XX_DISP_BASE;
515 par->cap = par->mmio_base + MB862XX_CAP_BASE;
516 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
517 par->geo = par->mmio_base + MB862XX_GEO_BASE;
518 par->pio = par->mmio_base + MB862XX_PIO_BASE;
519
520 par->refclk = GC_DISP_REFCLK_400;
521
522 ver = inreg(host, GC_CID);
523 rev = inreg(pio, GC_REVISION);
524 if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) {
525 dev_info(par->dev, "Fujitsu Lime v1.%d found\n",
526 (int)rev & 0xff);
527 par->type = BT_LIME;
528 ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100;
529 mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2;
530 } else {
531 dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev);
532 return -ENODEV;
533 }
534
535 if (!par->pre_init) {
536 outreg(host, GC_CCF, ccf);
537 udelay(200);
538 outreg(host, GC_MMR, mmr);
539 udelay(10);
540 }
541
542 /* interrupt status */
543 outreg(host, GC_IST, 0);
544 outreg(host, GC_IMASK, GC_INT_EN);
545 return 0;
546}
547
548static int __devinit of_platform_mb862xx_probe(struct of_device *ofdev,
549 const struct of_device_id *id)
550{
551 struct device_node *np = ofdev->node;
552 struct device *dev = &ofdev->dev;
553 struct mb862xxfb_par *par;
554 struct fb_info *info;
555 struct resource res;
556 resource_size_t res_size;
557 unsigned long ret = -ENODEV;
558
559 if (of_address_to_resource(np, 0, &res)) {
560 dev_err(dev, "Invalid address\n");
561 return -ENXIO;
562 }
563
564 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
565 if (info == NULL) {
566 dev_err(dev, "cannot allocate framebuffer\n");
567 return -ENOMEM;
568 }
569
570 par = info->par;
571 par->info = info;
572 par->dev = dev;
573
574 par->irq = irq_of_parse_and_map(np, 0);
575 if (par->irq == NO_IRQ) {
576 dev_err(dev, "failed to map irq\n");
577 ret = -ENODEV;
578 goto fbrel;
579 }
580
581 res_size = 1 + res.end - res.start;
582 par->res = request_mem_region(res.start, res_size, DRV_NAME);
583 if (par->res == NULL) {
584 dev_err(dev, "Cannot claim framebuffer/mmio\n");
585 ret = -ENXIO;
586 goto irqdisp;
587 }
588
589#if defined(CONFIG_LWMON5)
590 par->gc_mode = &lwmon5_gc_mode;
591#endif
592
593#if defined(CONFIG_SOCRATES)
594 par->gc_mode = &socrates_gc_mode;
595#endif
596
597 par->fb_base_phys = res.start;
598 par->mmio_base_phys = res.start + MB862XX_MMIO_BASE;
599 par->mmio_len = MB862XX_MMIO_SIZE;
600 if (par->gc_mode)
601 par->mapped_vram = par->gc_mode->max_vram;
602 else
603 par->mapped_vram = MB862XX_MEM_SIZE;
604
605 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
606 if (par->fb_base == NULL) {
607 dev_err(dev, "Cannot map framebuffer\n");
608 goto rel_reg;
609 }
610
611 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
612 if (par->mmio_base == NULL) {
613 dev_err(dev, "Cannot map registers\n");
614 goto fb_unmap;
615 }
616
617 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
618 (u64)par->fb_base_phys, (ulong)par->mapped_vram);
619 dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n",
620 (u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq);
621
622 if (mb862xx_gdc_init(par))
623 goto io_unmap;
624
625 if (request_irq(par->irq, mb862xx_intr, IRQF_DISABLED,
626 DRV_NAME, (void *)par)) {
627 dev_err(dev, "Cannot request irq\n");
628 goto io_unmap;
629 }
630
631 mb862xxfb_init_fbinfo(info);
632
633 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
634 dev_err(dev, "Could not allocate cmap for fb_info.\n");
635 goto free_irq;
636 }
637
638 if ((info->fbops->fb_set_par)(info))
639 dev_err(dev, "set_var() failed on initial setup?\n");
640
641 if (register_framebuffer(info)) {
642 dev_err(dev, "failed to register framebuffer\n");
643 goto rel_cmap;
644 }
645
646 dev_set_drvdata(dev, info);
647
648 if (device_create_file(dev, &dev_attr_dispregs))
649 dev_err(dev, "Can't create sysfs regdump file\n");
650 return 0;
651
652rel_cmap:
653 fb_dealloc_cmap(&info->cmap);
654free_irq:
655 outreg(host, GC_IMASK, 0);
656 free_irq(par->irq, (void *)par);
657io_unmap:
658 iounmap(par->mmio_base);
659fb_unmap:
660 iounmap(par->fb_base);
661rel_reg:
662 release_mem_region(res.start, res_size);
663irqdisp:
664 irq_dispose_mapping(par->irq);
665fbrel:
666 dev_set_drvdata(dev, NULL);
667 framebuffer_release(info);
668 return ret;
669}
670
671static int __devexit of_platform_mb862xx_remove(struct of_device *ofdev)
672{
673 struct fb_info *fbi = dev_get_drvdata(&ofdev->dev);
674 struct mb862xxfb_par *par = fbi->par;
675 resource_size_t res_size = 1 + par->res->end - par->res->start;
676 unsigned long reg;
677
678 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
679
680 /* display off */
681 reg = inreg(disp, GC_DCM1);
682 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
683 outreg(disp, GC_DCM1, reg);
684
685 /* disable interrupts */
686 outreg(host, GC_IMASK, 0);
687
688 free_irq(par->irq, (void *)par);
689 irq_dispose_mapping(par->irq);
690
691 device_remove_file(&ofdev->dev, &dev_attr_dispregs);
692
693 unregister_framebuffer(fbi);
694 fb_dealloc_cmap(&fbi->cmap);
695
696 iounmap(par->mmio_base);
697 iounmap(par->fb_base);
698
699 dev_set_drvdata(&ofdev->dev, NULL);
700 release_mem_region(par->res->start, res_size);
701 framebuffer_release(fbi);
702 return 0;
703}
704
705/*
706 * common types
707 */
708static struct of_device_id __devinitdata of_platform_mb862xx_tbl[] = {
709 { .compatible = "fujitsu,MB86276", },
710 { .compatible = "fujitsu,lime", },
711 { .compatible = "fujitsu,MB86277", },
712 { .compatible = "fujitsu,mint", },
713 { .compatible = "fujitsu,MB86293", },
714 { .compatible = "fujitsu,MB86294", },
715 { .compatible = "fujitsu,coral", },
716 { /* end */ }
717};
718
719static struct of_platform_driver of_platform_mb862xxfb_driver = {
720 .owner = THIS_MODULE,
721 .name = DRV_NAME,
722 .match_table = of_platform_mb862xx_tbl,
723 .probe = of_platform_mb862xx_probe,
724 .remove = __devexit_p(of_platform_mb862xx_remove),
725};
726#endif
727
728#if defined(CONFIG_FB_MB862XX_PCI_GDC)
729static int coralp_init(struct mb862xxfb_par *par)
730{
731 int cn, ver;
732
733 par->host = par->mmio_base;
734 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
735 par->disp = par->mmio_base + MB862XX_DISP_BASE;
736 par->cap = par->mmio_base + MB862XX_CAP_BASE;
737 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
738 par->geo = par->mmio_base + MB862XX_GEO_BASE;
739 par->pio = par->mmio_base + MB862XX_PIO_BASE;
740
741 par->refclk = GC_DISP_REFCLK_400;
742
743 ver = inreg(host, GC_CID);
744 cn = (ver & GC_CID_CNAME_MSK) >> 8;
745 ver = ver & GC_CID_VERSION_MSK;
746 if (cn == 3) {
747 dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
748 (ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
749 par->pdev->revision);
750 outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
751 udelay(200);
752 outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
753 udelay(10);
754 /* Clear interrupt status */
755 outreg(host, GC_IST, 0);
756 } else {
757 return -ENODEV;
758 }
759 return 0;
760}
761
762static int init_dram_ctrl(struct mb862xxfb_par *par)
763{
764 unsigned long i = 0;
765
766 /*
767 * Set io mode first! Spec. says IC may be destroyed
768 * if not set to SSTL2/LVCMOS before init.
769 */
770 outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0);
771
772 /* DRAM init */
773 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD);
774 outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE);
775 outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2,
776 GC_EVB_DCTL_REFRESH_SETTIME2);
777 outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1);
778 outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1);
779 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES);
780
781 /* DLL reset done? */
782 while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) {
783 udelay(GC_DCTL_INIT_WAIT_INTERVAL);
784 if (i++ > GC_DCTL_INIT_WAIT_CNT) {
785 dev_err(par->dev, "VRAM init failed.\n");
786 return -EINVAL;
787 }
788 }
789 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST);
790 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST);
791 return 0;
792}
793
794static int carmine_init(struct mb862xxfb_par *par)
795{
796 unsigned long reg;
797
798 par->ctrl = par->mmio_base + MB86297_CTRL_BASE;
799 par->i2c = par->mmio_base + MB86297_I2C_BASE;
800 par->disp = par->mmio_base + MB86297_DISP0_BASE;
801 par->disp1 = par->mmio_base + MB86297_DISP1_BASE;
802 par->cap = par->mmio_base + MB86297_CAP0_BASE;
803 par->cap1 = par->mmio_base + MB86297_CAP1_BASE;
804 par->draw = par->mmio_base + MB86297_DRAW_BASE;
805 par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;
806 par->wrback = par->mmio_base + MB86297_WRBACK_BASE;
807
808 par->refclk = GC_DISP_REFCLK_533;
809
810 /* warm up */
811 reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0;
812 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
813
814 /* check for engine module revision */
815 if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION)
816 dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n",
817 par->pdev->revision);
818 else
819 goto err_init;
820
821 reg &= ~GC_CTRL_CLK_EN_2D3D;
822 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
823
824 /* set up vram */
825 if (init_dram_ctrl(par) < 0)
826 goto err_init;
827
828 outreg(ctrl, GC_CTRL_INT_MASK, 0);
829 return 0;
830
831err_init:
832 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
833 return -EINVAL;
834}
835
836static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par)
837{
838 switch (par->type) {
839 case BT_CORALP:
840 return coralp_init(par);
841 case BT_CARMINE:
842 return carmine_init(par);
843 default:
844 return -ENODEV;
845 }
846}
847
848#define CHIP_ID(id) \
849 { PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) }
850
851static struct pci_device_id mb862xx_pci_tbl[] __devinitdata = {
852 /* MB86295/MB86296 */
853 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP),
854 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA),
855 /* MB86297 */
856 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE),
857 { 0, }
858};
859
860MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl);
861
862static int __devinit mb862xx_pci_probe(struct pci_dev *pdev,
863 const struct pci_device_id *ent)
864{
865 struct mb862xxfb_par *par;
866 struct fb_info *info;
867 struct device *dev = &pdev->dev;
868 int ret;
869
870 ret = pci_enable_device(pdev);
871 if (ret < 0) {
872 dev_err(dev, "Cannot enable PCI device\n");
873 goto out;
874 }
875
876 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
877 if (!info) {
878 dev_err(dev, "framebuffer alloc failed\n");
879 ret = -ENOMEM;
880 goto dis_dev;
881 }
882
883 par = info->par;
884 par->info = info;
885 par->dev = dev;
886 par->pdev = pdev;
887 par->irq = pdev->irq;
888
889 ret = pci_request_regions(pdev, DRV_NAME);
890 if (ret < 0) {
891 dev_err(dev, "Cannot reserve region(s) for PCI device\n");
892 goto rel_fb;
893 }
894
895 switch (pdev->device) {
896 case PCI_DEVICE_ID_FUJITSU_CORALP:
897 case PCI_DEVICE_ID_FUJITSU_CORALPA:
898 par->fb_base_phys = pci_resource_start(par->pdev, 0);
899 par->mapped_vram = CORALP_MEM_SIZE;
900 par->mmio_base_phys = par->fb_base_phys + MB862XX_MMIO_BASE;
901 par->mmio_len = MB862XX_MMIO_SIZE;
902 par->type = BT_CORALP;
903 break;
904 case PCI_DEVICE_ID_FUJITSU_CARMINE:
905 par->fb_base_phys = pci_resource_start(par->pdev, 2);
906 par->mmio_base_phys = pci_resource_start(par->pdev, 3);
907 par->mmio_len = pci_resource_len(par->pdev, 3);
908 par->mapped_vram = CARMINE_MEM_SIZE;
909 par->type = BT_CARMINE;
910 break;
911 default:
912 /* should never occur */
913 goto rel_reg;
914 }
915
916 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
917 if (par->fb_base == NULL) {
918 dev_err(dev, "Cannot map framebuffer\n");
919 goto rel_reg;
920 }
921
922 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
923 if (par->mmio_base == NULL) {
924 dev_err(dev, "Cannot map registers\n");
925 ret = -EIO;
926 goto fb_unmap;
927 }
928
929 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
930 (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
931 dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
932 (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
933
934 if (mb862xx_pci_gdc_init(par))
935 goto io_unmap;
936
937 if (request_irq(par->irq, mb862xx_intr, IRQF_DISABLED | IRQF_SHARED,
938 DRV_NAME, (void *)par)) {
939 dev_err(dev, "Cannot request irq\n");
940 goto io_unmap;
941 }
942
943 mb862xxfb_init_fbinfo(info);
944
945 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
946 dev_err(dev, "Could not allocate cmap for fb_info.\n");
947 ret = -ENOMEM;
948 goto free_irq;
949 }
950
951 if ((info->fbops->fb_set_par)(info))
952 dev_err(dev, "set_var() failed on initial setup?\n");
953
954 ret = register_framebuffer(info);
955 if (ret < 0) {
956 dev_err(dev, "failed to register framebuffer\n");
957 goto rel_cmap;
958 }
959
960 pci_set_drvdata(pdev, info);
961
962 if (device_create_file(dev, &dev_attr_dispregs))
963 dev_err(dev, "Can't create sysfs regdump file\n");
964
965 if (par->type == BT_CARMINE)
966 outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN);
967 else
968 outreg(host, GC_IMASK, GC_INT_EN);
969
970 return 0;
971
972rel_cmap:
973 fb_dealloc_cmap(&info->cmap);
974free_irq:
975 free_irq(par->irq, (void *)par);
976io_unmap:
977 iounmap(par->mmio_base);
978fb_unmap:
979 iounmap(par->fb_base);
980rel_reg:
981 pci_release_regions(pdev);
982rel_fb:
983 framebuffer_release(info);
984dis_dev:
985 pci_disable_device(pdev);
986out:
987 return ret;
988}
989
990static void __devexit mb862xx_pci_remove(struct pci_dev *pdev)
991{
992 struct fb_info *fbi = pci_get_drvdata(pdev);
993 struct mb862xxfb_par *par = fbi->par;
994 unsigned long reg;
995
996 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
997
998 /* display off */
999 reg = inreg(disp, GC_DCM1);
1000 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
1001 outreg(disp, GC_DCM1, reg);
1002
1003 if (par->type == BT_CARMINE) {
1004 outreg(ctrl, GC_CTRL_INT_MASK, 0);
1005 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
1006 } else {
1007 outreg(host, GC_IMASK, 0);
1008 }
1009
1010 device_remove_file(&pdev->dev, &dev_attr_dispregs);
1011
1012 pci_set_drvdata(pdev, NULL);
1013 unregister_framebuffer(fbi);
1014 fb_dealloc_cmap(&fbi->cmap);
1015
1016 free_irq(par->irq, (void *)par);
1017 iounmap(par->mmio_base);
1018 iounmap(par->fb_base);
1019
1020 pci_release_regions(pdev);
1021 framebuffer_release(fbi);
1022 pci_disable_device(pdev);
1023}
1024
1025static struct pci_driver mb862xxfb_pci_driver = {
1026 .name = DRV_NAME,
1027 .id_table = mb862xx_pci_tbl,
1028 .probe = mb862xx_pci_probe,
1029 .remove = __devexit_p(mb862xx_pci_remove),
1030};
1031#endif
1032
1033static int __devinit mb862xxfb_init(void)
1034{
1035 int ret = -ENODEV;
1036
1037#if defined(CONFIG_FB_MB862XX_LIME)
1038 ret = of_register_platform_driver(&of_platform_mb862xxfb_driver);
1039#endif
1040#if defined(CONFIG_FB_MB862XX_PCI_GDC)
1041 ret = pci_register_driver(&mb862xxfb_pci_driver);
1042#endif
1043 return ret;
1044}
1045
1046static void __exit mb862xxfb_exit(void)
1047{
1048#if defined(CONFIG_FB_MB862XX_LIME)
1049 of_unregister_platform_driver(&of_platform_mb862xxfb_driver);
1050#endif
1051#if defined(CONFIG_FB_MB862XX_PCI_GDC)
1052 pci_unregister_driver(&mb862xxfb_pci_driver);
1053#endif
1054}
1055
1056module_init(mb862xxfb_init);
1057module_exit(mb862xxfb_exit);
1058
1059MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver");
1060MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
1061MODULE_LICENSE("GPL v2");
diff --git a/drivers/video/mb862xx/mb862xxfb.h b/drivers/video/mb862xx/mb862xxfb.h
new file mode 100644
index 000000000000..c4c8f4dd2217
--- /dev/null
+++ b/drivers/video/mb862xx/mb862xxfb.h
@@ -0,0 +1,83 @@
1#ifndef __MB862XX_H__
2#define __MB862XX_H__
3
4#define PCI_VENDOR_ID_FUJITSU_LIMITED 0x10cf
5#define PCI_DEVICE_ID_FUJITSU_CORALP 0x2019
6#define PCI_DEVICE_ID_FUJITSU_CORALPA 0x201e
7#define PCI_DEVICE_ID_FUJITSU_CARMINE 0x202b
8
9#define GC_MMR_CORALP_EVB_VAL 0x11d7fa13
10
11enum gdctype {
12 BT_NONE,
13 BT_LIME,
14 BT_MINT,
15 BT_CORAL,
16 BT_CORALP,
17 BT_CARMINE,
18};
19
20struct mb862xx_gc_mode {
21 struct fb_videomode def_mode; /* mode of connected display */
22 unsigned int def_bpp; /* default depth */
23 unsigned long max_vram; /* connected SDRAM size */
24 unsigned long ccf; /* gdc clk */
25 unsigned long mmr; /* memory mode for SDRAM */
26};
27
28/* private data */
29struct mb862xxfb_par {
30 struct fb_info *info; /* fb info head */
31 struct device *dev;
32 struct pci_dev *pdev;
33 struct resource *res; /* framebuffer/mmio resource */
34
35 resource_size_t fb_base_phys; /* fb base, 36-bit PPC440EPx */
36 resource_size_t mmio_base_phys; /* io base addr */
37 void __iomem *fb_base; /* remapped framebuffer */
38 void __iomem *mmio_base; /* remapped registers */
39 size_t mapped_vram; /* length of remapped vram */
40 size_t mmio_len; /* length of register region */
41
42 void __iomem *host; /* relocatable reg. bases */
43 void __iomem *i2c;
44 void __iomem *disp;
45 void __iomem *disp1;
46 void __iomem *cap;
47 void __iomem *cap1;
48 void __iomem *draw;
49 void __iomem *geo;
50 void __iomem *pio;
51 void __iomem *ctrl;
52 void __iomem *dram_ctrl;
53 void __iomem *wrback;
54
55 unsigned int irq;
56 unsigned int type; /* GDC type */
57 unsigned int refclk; /* disp. reference clock */
58 struct mb862xx_gc_mode *gc_mode; /* GDC mode init data */
59 int pre_init; /* don't init display if 1 */
60
61 u32 pseudo_palette[16];
62};
63
64#if defined(CONFIG_FB_MB862XX_LIME) && defined(CONFIG_FB_MB862XX_PCI_GDC)
65#error "Select Lime GDC or CoralP/Carmine support, but not both together"
66#endif
67#if defined(CONFIG_FB_MB862XX_LIME)
68#define gdc_read __raw_readl
69#define gdc_write __raw_writel
70#else
71#define gdc_read readl
72#define gdc_write writel
73#endif
74
75#define inreg(type, off) \
76 gdc_read((par->type + (off)))
77
78#define outreg(type, off, val) \
79 gdc_write((val), (par->type + (off)))
80
81#define pack(a, b) (((a) << 16) | (b))
82
83#endif
diff --git a/drivers/video/omap/Makefile b/drivers/video/omap/Makefile
index 99da8b6d2c36..ed13889c1162 100644
--- a/drivers/video/omap/Makefile
+++ b/drivers/video/omap/Makefile
@@ -23,7 +23,6 @@ objs-y$(CONFIG_MACH_OMAP_PALMZ71) += lcd_palmz71.o
23objs-$(CONFIG_ARCH_OMAP16XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1610.o 23objs-$(CONFIG_ARCH_OMAP16XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1610.o
24objs-$(CONFIG_ARCH_OMAP15XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1510.o 24objs-$(CONFIG_ARCH_OMAP15XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1510.o
25objs-y$(CONFIG_MACH_OMAP_OSK) += lcd_osk.o 25objs-y$(CONFIG_MACH_OMAP_OSK) += lcd_osk.o
26objs-y$(CONFIG_MACH_SX1) += lcd_sx1.o
27 26
28omapfb-objs := $(objs-yy) 27omapfb-objs := $(objs-yy)
29 28
diff --git a/drivers/video/omap/lcd_sx1.c b/drivers/video/omap/lcd_sx1.c
deleted file mode 100644
index e55de201b8ff..000000000000
--- a/drivers/video/omap/lcd_sx1.c
+++ /dev/null
@@ -1,327 +0,0 @@
1/*
2 * LCD panel support for the Siemens SX1 mobile phone
3 *
4 * Current version : Vovan888@gmail.com, great help from FCA00000
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25
26#include <mach/gpio.h>
27#include <mach/omapfb.h>
28#include <mach/mcbsp.h>
29#include <mach/mux.h>
30
31/*
32 * OMAP310 GPIO registers
33 */
34#define GPIO_DATA_INPUT 0xfffce000
35#define GPIO_DATA_OUTPUT 0xfffce004
36#define GPIO_DIR_CONTROL 0xfffce008
37#define GPIO_INT_CONTROL 0xfffce00c
38#define GPIO_INT_MASK 0xfffce010
39#define GPIO_INT_STATUS 0xfffce014
40#define GPIO_PIN_CONTROL 0xfffce018
41
42
43#define A_LCD_SSC_RD 3
44#define A_LCD_SSC_SD 7
45#define _A_LCD_RESET 9
46#define _A_LCD_SSC_CS 12
47#define _A_LCD_SSC_A0 13
48
49#define DSP_REG 0xE1017024
50
51const unsigned char INIT_1[12] = {
52 0x1C, 0x02, 0x88, 0x00, 0x1E, 0xE0, 0x00, 0xDC, 0x00, 0x02, 0x00
53};
54
55const unsigned char INIT_2[127] = {
56 0x15, 0x00, 0x29, 0x00, 0x3E, 0x00, 0x51, 0x00,
57 0x65, 0x00, 0x7A, 0x00, 0x8D, 0x00, 0xA1, 0x00,
58 0xB6, 0x00, 0xC7, 0x00, 0xD8, 0x00, 0xEB, 0x00,
59 0xFB, 0x00, 0x0B, 0x01, 0x1B, 0x01, 0x27, 0x01,
60 0x34, 0x01, 0x41, 0x01, 0x4C, 0x01, 0x55, 0x01,
61 0x5F, 0x01, 0x68, 0x01, 0x70, 0x01, 0x78, 0x01,
62 0x7E, 0x01, 0x86, 0x01, 0x8C, 0x01, 0x94, 0x01,
63 0x9B, 0x01, 0xA1, 0x01, 0xA4, 0x01, 0xA9, 0x01,
64 0xAD, 0x01, 0xB2, 0x01, 0xB7, 0x01, 0xBC, 0x01,
65 0xC0, 0x01, 0xC4, 0x01, 0xC8, 0x01, 0xCB, 0x01,
66 0xCF, 0x01, 0xD2, 0x01, 0xD5, 0x01, 0xD8, 0x01,
67 0xDB, 0x01, 0xE0, 0x01, 0xE3, 0x01, 0xE6, 0x01,
68 0xE8, 0x01, 0xEB, 0x01, 0xEE, 0x01, 0xF1, 0x01,
69 0xF3, 0x01, 0xF8, 0x01, 0xF9, 0x01, 0xFC, 0x01,
70 0x00, 0x02, 0x03, 0x02, 0x07, 0x02, 0x09, 0x02,
71 0x0E, 0x02, 0x13, 0x02, 0x1C, 0x02, 0x00
72};
73
74const unsigned char INIT_3[15] = {
75 0x14, 0x26, 0x33, 0x3D, 0x45, 0x4D, 0x53, 0x59,
76 0x5E, 0x63, 0x67, 0x6D, 0x71, 0x78, 0xFF
77};
78
79static void epson_sendbyte(int flag, unsigned char byte)
80{
81 int i, shifter = 0x80;
82
83 if (!flag)
84 gpio_set_value(_A_LCD_SSC_A0, 0);
85 mdelay(2);
86 gpio_set_value(A_LCD_SSC_RD, 1);
87
88 gpio_set_value(A_LCD_SSC_SD, flag);
89
90 OMAP_MCBSP_WRITE(OMAP1510_MCBSP3_BASE, PCR0, 0x2200);
91 OMAP_MCBSP_WRITE(OMAP1510_MCBSP3_BASE, PCR0, 0x2202);
92 for (i = 0; i < 8; i++) {
93 OMAP_MCBSP_WRITE(OMAP1510_MCBSP3_BASE, PCR0, 0x2200);
94 gpio_set_value(A_LCD_SSC_SD, shifter & byte);
95 OMAP_MCBSP_WRITE(OMAP1510_MCBSP3_BASE, PCR0, 0x2202);
96 shifter >>= 1;
97 }
98 gpio_set_value(_A_LCD_SSC_A0, 1);
99}
100
101static void init_system(void)
102{
103 omap_mcbsp_request(OMAP_MCBSP3);
104 omap_mcbsp_stop(OMAP_MCBSP3);
105}
106
107static void setup_GPIO(void)
108{
109 /* new wave */
110 gpio_request(A_LCD_SSC_RD, "lcd_ssc_rd");
111 gpio_request(A_LCD_SSC_SD, "lcd_ssc_sd");
112 gpio_request(_A_LCD_RESET, "lcd_reset");
113 gpio_request(_A_LCD_SSC_CS, "lcd_ssc_cs");
114 gpio_request(_A_LCD_SSC_A0, "lcd_ssc_a0");
115
116 /* set GPIOs to output, with initial data */
117 gpio_direction_output(A_LCD_SSC_RD, 1);
118 gpio_direction_output(A_LCD_SSC_SD, 0);
119 gpio_direction_output(_A_LCD_RESET, 0);
120 gpio_direction_output(_A_LCD_SSC_CS, 1);
121 gpio_direction_output(_A_LCD_SSC_A0, 1);
122}
123
124static void display_init(void)
125{
126 int i;
127
128 omap_cfg_reg(MCBSP3_CLKX);
129
130 mdelay(2);
131 setup_GPIO();
132 mdelay(2);
133
134 /* reset LCD */
135 gpio_set_value(A_LCD_SSC_SD, 1);
136 epson_sendbyte(0, 0x25);
137
138 gpio_set_value(_A_LCD_RESET, 0);
139 mdelay(10);
140 gpio_set_value(_A_LCD_RESET, 1);
141
142 gpio_set_value(_A_LCD_SSC_CS, 1);
143 mdelay(2);
144 gpio_set_value(_A_LCD_SSC_CS, 0);
145
146 /* init LCD, phase 1 */
147 epson_sendbyte(0, 0xCA);
148 for (i = 0; i < 10; i++)
149 epson_sendbyte(1, INIT_1[i]);
150 gpio_set_value(_A_LCD_SSC_CS, 1);
151 gpio_set_value(_A_LCD_SSC_CS, 0);
152
153 /* init LCD phase 2 */
154 epson_sendbyte(0, 0xCB);
155 for (i = 0; i < 125; i++)
156 epson_sendbyte(1, INIT_2[i]);
157 gpio_set_value(_A_LCD_SSC_CS, 1);
158 gpio_set_value(_A_LCD_SSC_CS, 0);
159
160 /* init LCD phase 2a */
161 epson_sendbyte(0, 0xCC);
162 for (i = 0; i < 14; i++)
163 epson_sendbyte(1, INIT_3[i]);
164 gpio_set_value(_A_LCD_SSC_CS, 1);
165 gpio_set_value(_A_LCD_SSC_CS, 0);
166
167 /* init LCD phase 3 */
168 epson_sendbyte(0, 0xBC);
169 epson_sendbyte(1, 0x08);
170 gpio_set_value(_A_LCD_SSC_CS, 1);
171 gpio_set_value(_A_LCD_SSC_CS, 0);
172
173 /* init LCD phase 4 */
174 epson_sendbyte(0, 0x07);
175 epson_sendbyte(1, 0x05);
176 gpio_set_value(_A_LCD_SSC_CS, 1);
177 gpio_set_value(_A_LCD_SSC_CS, 0);
178
179 /* init LCD phase 5 */
180 epson_sendbyte(0, 0x94);
181 gpio_set_value(_A_LCD_SSC_CS, 1);
182 gpio_set_value(_A_LCD_SSC_CS, 0);
183
184 /* init LCD phase 6 */
185 epson_sendbyte(0, 0xC6);
186 epson_sendbyte(1, 0x80);
187 gpio_set_value(_A_LCD_SSC_CS, 1);
188 mdelay(100); /* used to be 1000 */
189 gpio_set_value(_A_LCD_SSC_CS, 0);
190
191 /* init LCD phase 7 */
192 epson_sendbyte(0, 0x16);
193 epson_sendbyte(1, 0x02);
194 epson_sendbyte(1, 0x00);
195 epson_sendbyte(1, 0xB1);
196 epson_sendbyte(1, 0x00);
197 gpio_set_value(_A_LCD_SSC_CS, 1);
198 gpio_set_value(_A_LCD_SSC_CS, 0);
199
200 /* init LCD phase 8 */
201 epson_sendbyte(0, 0x76);
202 epson_sendbyte(1, 0x00);
203 epson_sendbyte(1, 0x00);
204 epson_sendbyte(1, 0xDB);
205 epson_sendbyte(1, 0x00);
206 gpio_set_value(_A_LCD_SSC_CS, 1);
207 gpio_set_value(_A_LCD_SSC_CS, 0);
208
209 /* init LCD phase 9 */
210 epson_sendbyte(0, 0xAF);
211 gpio_set_value(_A_LCD_SSC_CS, 1);
212}
213
214static int sx1_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
215{
216 return 0;
217}
218
219static void sx1_panel_cleanup(struct lcd_panel *panel)
220{
221}
222
223static void sx1_panel_disable(struct lcd_panel *panel)
224{
225 printk(KERN_INFO "SX1: LCD panel disable\n");
226 sx1_setmmipower(0);
227 gpio_set_value(_A_LCD_SSC_CS, 1);
228
229 epson_sendbyte(0, 0x25);
230 gpio_set_value(_A_LCD_SSC_CS, 0);
231
232 epson_sendbyte(0, 0xAE);
233 gpio_set_value(_A_LCD_SSC_CS, 1);
234 mdelay(100);
235 gpio_set_value(_A_LCD_SSC_CS, 0);
236
237 epson_sendbyte(0, 0x95);
238 gpio_set_value(_A_LCD_SSC_CS, 1);
239}
240
241static int sx1_panel_enable(struct lcd_panel *panel)
242{
243 printk(KERN_INFO "lcd_sx1: LCD panel enable\n");
244 init_system();
245 display_init();
246
247 sx1_setmmipower(1);
248 sx1_setbacklight(0x18);
249 sx1_setkeylight (0x06);
250 return 0;
251}
252
253
254static unsigned long sx1_panel_get_caps(struct lcd_panel *panel)
255{
256 return 0;
257}
258
259struct lcd_panel sx1_panel = {
260 .name = "sx1",
261 .config = OMAP_LCDC_PANEL_TFT | OMAP_LCDC_INV_VSYNC |
262 OMAP_LCDC_INV_HSYNC | OMAP_LCDC_INV_PIX_CLOCK |
263 OMAP_LCDC_INV_OUTPUT_EN,
264
265 .x_res = 176,
266 .y_res = 220,
267 .data_lines = 16,
268 .bpp = 16,
269 .hsw = 5,
270 .hfp = 5,
271 .hbp = 5,
272 .vsw = 2,
273 .vfp = 1,
274 .vbp = 1,
275 .pixel_clock = 1500,
276
277 .init = sx1_panel_init,
278 .cleanup = sx1_panel_cleanup,
279 .enable = sx1_panel_enable,
280 .disable = sx1_panel_disable,
281 .get_caps = sx1_panel_get_caps,
282};
283
284static int sx1_panel_probe(struct platform_device *pdev)
285{
286 omapfb_register_panel(&sx1_panel);
287 return 0;
288}
289
290static int sx1_panel_remove(struct platform_device *pdev)
291{
292 return 0;
293}
294
295static int sx1_panel_suspend(struct platform_device *pdev, pm_message_t mesg)
296{
297 return 0;
298}
299
300static int sx1_panel_resume(struct platform_device *pdev)
301{
302 return 0;
303}
304
305struct platform_driver sx1_panel_driver = {
306 .probe = sx1_panel_probe,
307 .remove = sx1_panel_remove,
308 .suspend = sx1_panel_suspend,
309 .resume = sx1_panel_resume,
310 .driver = {
311 .name = "lcd_sx1",
312 .owner = THIS_MODULE,
313 },
314};
315
316static int sx1_panel_drv_init(void)
317{
318 return platform_driver_register(&sx1_panel_driver);
319}
320
321static void sx1_panel_drv_cleanup(void)
322{
323 platform_driver_unregister(&sx1_panel_driver);
324}
325
326module_init(sx1_panel_drv_init);
327module_exit(sx1_panel_drv_cleanup);
diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
index 5a5e407dc45f..1a49519dafa4 100644
--- a/drivers/video/omap/omapfb_main.c
+++ b/drivers/video/omap/omapfb_main.c
@@ -392,7 +392,7 @@ static void set_fb_fix(struct fb_info *fbi)
392 int bpp; 392 int bpp;
393 393
394 rg = &plane->fbdev->mem_desc.region[plane->idx]; 394 rg = &plane->fbdev->mem_desc.region[plane->idx];
395 fbi->screen_base = (char __iomem *)rg->vaddr; 395 fbi->screen_base = rg->vaddr;
396 fix->smem_start = rg->paddr; 396 fix->smem_start = rg->paddr;
397 fix->smem_len = rg->size; 397 fix->smem_len = rg->size;
398 398
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index 97204497d9f7..cc59c52e1103 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -804,6 +804,9 @@ static int pxafb_smart_thread(void *arg)
804 804
805static int pxafb_smart_init(struct pxafb_info *fbi) 805static int pxafb_smart_init(struct pxafb_info *fbi)
806{ 806{
807 if (!(fbi->lccr0 | LCCR0_LCDT))
808 return 0;
809
807 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi, 810 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
808 "lcd_refresh"); 811 "lcd_refresh");
809 if (IS_ERR(fbi->smart_thread)) { 812 if (IS_ERR(fbi->smart_thread)) {
@@ -1372,7 +1375,7 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1372 fbi->cmap_inverse = inf->cmap_inverse; 1375 fbi->cmap_inverse = inf->cmap_inverse;
1373 fbi->cmap_static = inf->cmap_static; 1376 fbi->cmap_static = inf->cmap_static;
1374 1377
1375 switch (lcd_conn & 0xf) { 1378 switch (lcd_conn & LCD_TYPE_MASK) {
1376 case LCD_TYPE_MONO_STN: 1379 case LCD_TYPE_MONO_STN:
1377 fbi->lccr0 = LCCR0_CMS; 1380 fbi->lccr0 = LCCR0_CMS;
1378 break; 1381 break;
diff --git a/drivers/video/tmiofb.c b/drivers/video/tmiofb.c
index 2a380011e9ba..7baf2dd12d50 100644
--- a/drivers/video/tmiofb.c
+++ b/drivers/video/tmiofb.c
@@ -222,6 +222,9 @@ static irqreturn_t tmiofb_irq(int irq, void *__info)
222 unsigned int bbisc = tmio_ioread16(par->lcr + LCR_BBISC); 222 unsigned int bbisc = tmio_ioread16(par->lcr + LCR_BBISC);
223 223
224 224
225 tmio_iowrite16(bbisc, par->lcr + LCR_BBISC);
226
227#ifdef CONFIG_FB_TMIO_ACCELL
225 /* 228 /*
226 * We were in polling mode and now we got correct irq. 229 * We were in polling mode and now we got correct irq.
227 * Switch back to IRQ-based sync of command FIFO 230 * Switch back to IRQ-based sync of command FIFO
@@ -231,9 +234,6 @@ static irqreturn_t tmiofb_irq(int irq, void *__info)
231 par->use_polling = false; 234 par->use_polling = false;
232 } 235 }
233 236
234 tmio_iowrite16(bbisc, par->lcr + LCR_BBISC);
235
236#ifdef CONFIG_FB_TMIO_ACCELL
237 if (bbisc & 1) 237 if (bbisc & 1)
238 wake_up(&par->wait_acc); 238 wake_up(&par->wait_acc);
239#endif 239#endif
@@ -938,7 +938,9 @@ static void tmiofb_dump_regs(struct platform_device *dev)
938static int tmiofb_suspend(struct platform_device *dev, pm_message_t state) 938static int tmiofb_suspend(struct platform_device *dev, pm_message_t state)
939{ 939{
940 struct fb_info *info = platform_get_drvdata(dev); 940 struct fb_info *info = platform_get_drvdata(dev);
941#ifdef CONFIG_FB_TMIO_ACCELL
941 struct tmiofb_par *par = info->par; 942 struct tmiofb_par *par = info->par;
943#endif
942 struct mfd_cell *cell = dev->dev.platform_data; 944 struct mfd_cell *cell = dev->dev.platform_data;
943 int retval = 0; 945 int retval = 0;
944 946
@@ -950,12 +952,14 @@ static int tmiofb_suspend(struct platform_device *dev, pm_message_t state)
950 info->fbops->fb_sync(info); 952 info->fbops->fb_sync(info);
951 953
952 954
955#ifdef CONFIG_FB_TMIO_ACCELL
953 /* 956 /*
954 * The fb should be usable even if interrupts are disabled (and they are 957 * The fb should be usable even if interrupts are disabled (and they are
955 * during suspend/resume). Switch temporary to forced polling. 958 * during suspend/resume). Switch temporary to forced polling.
956 */ 959 */
957 printk(KERN_INFO "tmiofb: switching to polling\n"); 960 printk(KERN_INFO "tmiofb: switching to polling\n");
958 par->use_polling = true; 961 par->use_polling = true;
962#endif
959 tmiofb_hw_stop(dev); 963 tmiofb_hw_stop(dev);
960 964
961 if (cell->suspend) 965 if (cell->suspend)
diff --git a/drivers/video/via/global.h b/drivers/video/via/global.h
index 8e5263c5b812..7543d5f7e309 100644
--- a/drivers/video/via/global.h
+++ b/drivers/video/via/global.h
@@ -38,7 +38,6 @@
38#include "iface.h" 38#include "iface.h"
39#include "viafbdev.h" 39#include "viafbdev.h"
40#include "chip.h" 40#include "chip.h"
41#include "debug.h"
42#include "accel.h" 41#include "accel.h"
43#include "share.h" 42#include "share.h"
44#include "dvi.h" 43#include "dvi.h"
@@ -48,12 +47,10 @@
48 47
49#include "lcd.h" 48#include "lcd.h"
50#include "ioctl.h" 49#include "ioctl.h"
51#include "viamode.h"
52#include "via_utility.h" 50#include "via_utility.h"
53#include "vt1636.h" 51#include "vt1636.h"
54#include "tblDPASetting.h" 52#include "tblDPASetting.h"
55#include "tbl1636.h" 53#include "tbl1636.h"
56#include "viafbdev.h"
57 54
58/* External struct*/ 55/* External struct*/
59 56
diff --git a/drivers/video/via/viafbdev.c b/drivers/video/via/viafbdev.c
index 0132eae06f55..73ac754ad801 100644
--- a/drivers/video/via/viafbdev.c
+++ b/drivers/video/via/viafbdev.c
@@ -2036,30 +2036,30 @@ static int viafb_vt1636_proc_write(struct file *file,
2036 return count; 2036 return count;
2037} 2037}
2038 2038
2039static void viafb_init_proc(struct proc_dir_entry *viafb_entry) 2039static void viafb_init_proc(struct proc_dir_entry **viafb_entry)
2040{ 2040{
2041 struct proc_dir_entry *entry; 2041 struct proc_dir_entry *entry;
2042 viafb_entry = proc_mkdir("viafb", NULL); 2042 *viafb_entry = proc_mkdir("viafb", NULL);
2043 if (viafb_entry) { 2043 if (viafb_entry) {
2044 entry = create_proc_entry("dvp0", 0, viafb_entry); 2044 entry = create_proc_entry("dvp0", 0, *viafb_entry);
2045 if (entry) { 2045 if (entry) {
2046 entry->owner = THIS_MODULE; 2046 entry->owner = THIS_MODULE;
2047 entry->read_proc = viafb_dvp0_proc_read; 2047 entry->read_proc = viafb_dvp0_proc_read;
2048 entry->write_proc = viafb_dvp0_proc_write; 2048 entry->write_proc = viafb_dvp0_proc_write;
2049 } 2049 }
2050 entry = create_proc_entry("dvp1", 0, viafb_entry); 2050 entry = create_proc_entry("dvp1", 0, *viafb_entry);
2051 if (entry) { 2051 if (entry) {
2052 entry->owner = THIS_MODULE; 2052 entry->owner = THIS_MODULE;
2053 entry->read_proc = viafb_dvp1_proc_read; 2053 entry->read_proc = viafb_dvp1_proc_read;
2054 entry->write_proc = viafb_dvp1_proc_write; 2054 entry->write_proc = viafb_dvp1_proc_write;
2055 } 2055 }
2056 entry = create_proc_entry("dfph", 0, viafb_entry); 2056 entry = create_proc_entry("dfph", 0, *viafb_entry);
2057 if (entry) { 2057 if (entry) {
2058 entry->owner = THIS_MODULE; 2058 entry->owner = THIS_MODULE;
2059 entry->read_proc = viafb_dfph_proc_read; 2059 entry->read_proc = viafb_dfph_proc_read;
2060 entry->write_proc = viafb_dfph_proc_write; 2060 entry->write_proc = viafb_dfph_proc_write;
2061 } 2061 }
2062 entry = create_proc_entry("dfpl", 0, viafb_entry); 2062 entry = create_proc_entry("dfpl", 0, *viafb_entry);
2063 if (entry) { 2063 if (entry) {
2064 entry->owner = THIS_MODULE; 2064 entry->owner = THIS_MODULE;
2065 entry->read_proc = viafb_dfpl_proc_read; 2065 entry->read_proc = viafb_dfpl_proc_read;
@@ -2068,7 +2068,7 @@ static void viafb_init_proc(struct proc_dir_entry *viafb_entry)
2068 if (VT1636_LVDS == viaparinfo->chip_info->lvds_chip_info. 2068 if (VT1636_LVDS == viaparinfo->chip_info->lvds_chip_info.
2069 lvds_chip_name || VT1636_LVDS == 2069 lvds_chip_name || VT1636_LVDS ==
2070 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) { 2070 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2071 entry = create_proc_entry("vt1636", 0, viafb_entry); 2071 entry = create_proc_entry("vt1636", 0, *viafb_entry);
2072 if (entry) { 2072 if (entry) {
2073 entry->owner = THIS_MODULE; 2073 entry->owner = THIS_MODULE;
2074 entry->read_proc = viafb_vt1636_proc_read; 2074 entry->read_proc = viafb_vt1636_proc_read;
@@ -2087,6 +2087,7 @@ static void viafb_remove_proc(struct proc_dir_entry *viafb_entry)
2087 remove_proc_entry("dfpl", viafb_entry); 2087 remove_proc_entry("dfpl", viafb_entry);
2088 remove_proc_entry("vt1636", viafb_entry); 2088 remove_proc_entry("vt1636", viafb_entry);
2089 remove_proc_entry("vt1625", viafb_entry); 2089 remove_proc_entry("vt1625", viafb_entry);
2090 remove_proc_entry("viafb", NULL);
2090} 2091}
2091 2092
2092static int __devinit via_pci_probe(void) 2093static int __devinit via_pci_probe(void)
@@ -2348,7 +2349,7 @@ static int __devinit via_pci_probe(void)
2348 viafbinfo->node, viafbinfo->fix.id, default_var.xres, 2349 viafbinfo->node, viafbinfo->fix.id, default_var.xres,
2349 default_var.yres, default_var.bits_per_pixel); 2350 default_var.yres, default_var.bits_per_pixel);
2350 2351
2351 viafb_init_proc(viaparinfo->proc_entry); 2352 viafb_init_proc(&viaparinfo->proc_entry);
2352 viafb_init_dac(IGA2); 2353 viafb_init_dac(IGA2);
2353 return 0; 2354 return 0;
2354} 2355}
diff --git a/drivers/video/xen-fbfront.c b/drivers/video/xen-fbfront.c
index a463b3dd837b..2493f05e9f61 100644
--- a/drivers/video/xen-fbfront.c
+++ b/drivers/video/xen-fbfront.c
@@ -668,7 +668,7 @@ static struct xenbus_device_id xenfb_ids[] = {
668 { "" } 668 { "" }
669}; 669};
670 670
671static struct xenbus_driver xenfb = { 671static struct xenbus_driver xenfb_driver = {
672 .name = "vfb", 672 .name = "vfb",
673 .owner = THIS_MODULE, 673 .owner = THIS_MODULE,
674 .ids = xenfb_ids, 674 .ids = xenfb_ids,
@@ -687,12 +687,12 @@ static int __init xenfb_init(void)
687 if (xen_initial_domain()) 687 if (xen_initial_domain())
688 return -ENODEV; 688 return -ENODEV;
689 689
690 return xenbus_register_frontend(&xenfb); 690 return xenbus_register_frontend(&xenfb_driver);
691} 691}
692 692
693static void __exit xenfb_cleanup(void) 693static void __exit xenfb_cleanup(void)
694{ 694{
695 xenbus_unregister_driver(&xenfb); 695 xenbus_unregister_driver(&xenfb_driver);
696} 696}
697 697
698module_init(xenfb_init); 698module_init(xenfb_init);
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index 5da3d2423cc0..40a3a2afbfe7 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -298,8 +298,9 @@ static int xilinxfb_assign(struct device *dev, unsigned long physaddr,
298 298
299 /* Put a banner in the log (for DEBUG) */ 299 /* Put a banner in the log (for DEBUG) */
300 dev_dbg(dev, "regs: phys=%lx, virt=%p\n", physaddr, drvdata->regs); 300 dev_dbg(dev, "regs: phys=%lx, virt=%p\n", physaddr, drvdata->regs);
301 dev_dbg(dev, "fb: phys=%p, virt=%p, size=%x\n", 301 dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n",
302 (void*)drvdata->fb_phys, drvdata->fb_virt, fbsize); 302 (unsigned long long) drvdata->fb_phys, drvdata->fb_virt,
303 fbsize);
303 304
304 return 0; /* success */ 305 return 0; /* success */
305 306
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 14:49:00 -0500