diff options
Diffstat (limited to 'drivers/video')
-rw-r--r-- | drivers/video/intelfb/intelfb.h | 3 | ||||
-rw-r--r-- | drivers/video/intelfb/intelfbdrv.c | 3 | ||||
-rw-r--r-- | drivers/video/intelfb/intelfbhw.c | 149 | ||||
-rw-r--r-- | drivers/video/intelfb/intelfbhw.h | 9 |
4 files changed, 98 insertions, 66 deletions
diff --git a/drivers/video/intelfb/intelfb.h b/drivers/video/intelfb/intelfb.h index da29d007f215..d0da38434817 100644 --- a/drivers/video/intelfb/intelfb.h +++ b/drivers/video/intelfb/intelfb.h | |||
@@ -277,6 +277,9 @@ struct intelfb_info { | |||
277 | 277 | ||
278 | /* driver registered */ | 278 | /* driver registered */ |
279 | int registered; | 279 | int registered; |
280 | |||
281 | /* index into plls */ | ||
282 | int pll_index; | ||
280 | }; | 283 | }; |
281 | 284 | ||
282 | /*** function prototypes ***/ | 285 | /*** function prototypes ***/ |
diff --git a/drivers/video/intelfb/intelfbdrv.c b/drivers/video/intelfb/intelfbdrv.c index 995b47c165a7..7fb9f96bab3f 100644 --- a/drivers/video/intelfb/intelfbdrv.c +++ b/drivers/video/intelfb/intelfbdrv.c | |||
@@ -584,8 +584,7 @@ intelfb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
584 | /* Get the chipset info. */ | 584 | /* Get the chipset info. */ |
585 | dinfo->pci_chipset = pdev->device; | 585 | dinfo->pci_chipset = pdev->device; |
586 | 586 | ||
587 | if (intelfbhw_get_chipset(pdev, &dinfo->name, &dinfo->chipset, | 587 | if (intelfbhw_get_chipset(pdev, dinfo)) { |
588 | &dinfo->mobile)) { | ||
589 | cleanup(dinfo); | 588 | cleanup(dinfo); |
590 | return -ENODEV; | 589 | return -ENODEV; |
591 | } | 590 | } |
diff --git a/drivers/video/intelfb/intelfbhw.c b/drivers/video/intelfb/intelfbhw.c index a3a94642b79b..bf742aad08e9 100644 --- a/drivers/video/intelfb/intelfbhw.c +++ b/drivers/video/intelfb/intelfbhw.c | |||
@@ -61,67 +61,71 @@ struct pll_min_max plls[PLLS_MAX] = { | |||
61 | }; | 61 | }; |
62 | 62 | ||
63 | int | 63 | int |
64 | intelfbhw_get_chipset(struct pci_dev *pdev, const char **name, int *chipset, | 64 | intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo) |
65 | int *mobile) | ||
66 | { | 65 | { |
67 | u32 tmp; | 66 | u32 tmp; |
68 | 67 | if (!pdev || !dinfo) | |
69 | if (!pdev || !name || !chipset || !mobile) | ||
70 | return 1; | 68 | return 1; |
71 | 69 | ||
72 | switch (pdev->device) { | 70 | switch (pdev->device) { |
73 | case PCI_DEVICE_ID_INTEL_830M: | 71 | case PCI_DEVICE_ID_INTEL_830M: |
74 | *name = "Intel(R) 830M"; | 72 | dinfo->name = "Intel(R) 830M"; |
75 | *chipset = INTEL_830M; | 73 | dinfo->chipset = INTEL_830M; |
76 | *mobile = 1; | 74 | dinfo->mobile = 1; |
75 | dinfo->pll_index = PLLS_I8xx; | ||
77 | return 0; | 76 | return 0; |
78 | case PCI_DEVICE_ID_INTEL_845G: | 77 | case PCI_DEVICE_ID_INTEL_845G: |
79 | *name = "Intel(R) 845G"; | 78 | dinfo->name = "Intel(R) 845G"; |
80 | *chipset = INTEL_845G; | 79 | dinfo->chipset = INTEL_845G; |
81 | *mobile = 0; | 80 | dinfo->mobile = 0; |
81 | dinfo->pll_index = PLLS_I8xx; | ||
82 | return 0; | 82 | return 0; |
83 | case PCI_DEVICE_ID_INTEL_85XGM: | 83 | case PCI_DEVICE_ID_INTEL_85XGM: |
84 | tmp = 0; | 84 | tmp = 0; |
85 | *mobile = 1; | 85 | dinfo->mobile = 1; |
86 | dinfo->pll_index = PLLS_I8xx; | ||
86 | pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp); | 87 | pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp); |
87 | switch ((tmp >> INTEL_85X_VARIANT_SHIFT) & | 88 | switch ((tmp >> INTEL_85X_VARIANT_SHIFT) & |
88 | INTEL_85X_VARIANT_MASK) { | 89 | INTEL_85X_VARIANT_MASK) { |
89 | case INTEL_VAR_855GME: | 90 | case INTEL_VAR_855GME: |
90 | *name = "Intel(R) 855GME"; | 91 | dinfo->name = "Intel(R) 855GME"; |
91 | *chipset = INTEL_855GME; | 92 | dinfo->chipset = INTEL_855GME; |
92 | return 0; | 93 | return 0; |
93 | case INTEL_VAR_855GM: | 94 | case INTEL_VAR_855GM: |
94 | *name = "Intel(R) 855GM"; | 95 | dinfo->name = "Intel(R) 855GM"; |
95 | *chipset = INTEL_855GM; | 96 | dinfo->chipset = INTEL_855GM; |
96 | return 0; | 97 | return 0; |
97 | case INTEL_VAR_852GME: | 98 | case INTEL_VAR_852GME: |
98 | *name = "Intel(R) 852GME"; | 99 | dinfo->name = "Intel(R) 852GME"; |
99 | *chipset = INTEL_852GME; | 100 | dinfo->chipset = INTEL_852GME; |
100 | return 0; | 101 | return 0; |
101 | case INTEL_VAR_852GM: | 102 | case INTEL_VAR_852GM: |
102 | *name = "Intel(R) 852GM"; | 103 | dinfo->name = "Intel(R) 852GM"; |
103 | *chipset = INTEL_852GM; | 104 | dinfo->chipset = INTEL_852GM; |
104 | return 0; | 105 | return 0; |
105 | default: | 106 | default: |
106 | *name = "Intel(R) 852GM/855GM"; | 107 | dinfo->name = "Intel(R) 852GM/855GM"; |
107 | *chipset = INTEL_85XGM; | 108 | dinfo->chipset = INTEL_85XGM; |
108 | return 0; | 109 | return 0; |
109 | } | 110 | } |
110 | break; | 111 | break; |
111 | case PCI_DEVICE_ID_INTEL_865G: | 112 | case PCI_DEVICE_ID_INTEL_865G: |
112 | *name = "Intel(R) 865G"; | 113 | dinfo->name = "Intel(R) 865G"; |
113 | *chipset = INTEL_865G; | 114 | dinfo->chipset = INTEL_865G; |
114 | *mobile = 0; | 115 | dinfo->mobile = 0; |
116 | dinfo->pll_index = PLLS_I8xx; | ||
115 | return 0; | 117 | return 0; |
116 | case PCI_DEVICE_ID_INTEL_915G: | 118 | case PCI_DEVICE_ID_INTEL_915G: |
117 | *name = "Intel(R) 915G"; | 119 | dinfo->name = "Intel(R) 915G"; |
118 | *chipset = INTEL_915G; | 120 | dinfo->chipset = INTEL_915G; |
119 | *mobile = 0; | 121 | dinfo->mobile = 0; |
122 | dinfo->pll_index = PLLS_I9xx; | ||
120 | return 0; | 123 | return 0; |
121 | case PCI_DEVICE_ID_INTEL_915GM: | 124 | case PCI_DEVICE_ID_INTEL_915GM: |
122 | *name = "Intel(R) 915GM"; | 125 | dinfo->name = "Intel(R) 915GM"; |
123 | *chipset = INTEL_915GM; | 126 | dinfo->chipset = INTEL_915GM; |
124 | *mobile = 1; | 127 | dinfo->mobile = 1; |
128 | dinfo->pll_index = PLLS_I9xx; | ||
125 | return 0; | 129 | return 0; |
126 | default: | 130 | default: |
127 | return 1; | 131 | return 1; |
@@ -549,14 +553,33 @@ intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw, | |||
549 | } | 553 | } |
550 | 554 | ||
551 | 555 | ||
556 | static int calc_vclock3(int index, int m, int n, int p) | ||
557 | { | ||
558 | return PLL_REFCLK * m / n / p; | ||
559 | } | ||
560 | |||
561 | static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2) | ||
562 | { | ||
563 | switch(index) | ||
564 | { | ||
565 | case PLLS_I9xx: | ||
566 | return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / | ||
567 | ((p1)) * (p2 ? 10 : 5))); | ||
568 | case PLLS_I8xx: | ||
569 | default: | ||
570 | return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / | ||
571 | ((p1+2) * (1 << (p2 + 1))))); | ||
572 | } | ||
573 | } | ||
574 | |||
552 | void | 575 | void |
553 | intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw) | 576 | intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw) |
554 | { | 577 | { |
555 | #if REGDUMP | 578 | #if REGDUMP |
556 | int i, m1, m2, n, p1, p2; | 579 | int i, m1, m2, n, p1, p2; |
557 | 580 | int index = dinfo->pll_index; | |
558 | DBG_MSG("intelfbhw_print_hw_state\n"); | 581 | DBG_MSG("intelfbhw_print_hw_state\n"); |
559 | 582 | ||
560 | if (!hw || !dinfo) | 583 | if (!hw || !dinfo) |
561 | return; | 584 | return; |
562 | /* Read in as much of the HW state as possible. */ | 585 | /* Read in as much of the HW state as possible. */ |
@@ -573,9 +596,10 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw) | |||
573 | p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK; | 596 | p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK; |
574 | p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK; | 597 | p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK; |
575 | printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", | 598 | printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", |
576 | m1, m2, n, p1, p2); | 599 | m1, m2, n, p1, p2); |
577 | printk(" VGA0: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2)); | 600 | printk(" VGA0: clock is %d\n", |
578 | 601 | calc_vclock(index, m1, m2, n, p1, p2)); | |
602 | |||
579 | n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; | 603 | n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
580 | m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; | 604 | m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
581 | m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; | 605 | m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
@@ -585,16 +609,16 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw) | |||
585 | p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK; | 609 | p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK; |
586 | p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK; | 610 | p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK; |
587 | printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", | 611 | printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", |
588 | m1, m2, n, p1, p2); | 612 | m1, m2, n, p1, p2); |
589 | printk(" VGA1: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2)); | 613 | printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2)); |
590 | 614 | ||
591 | printk(" DPLL_A: 0x%08x\n", hw->dpll_a); | 615 | printk(" DPLL_A: 0x%08x\n", hw->dpll_a); |
592 | printk(" DPLL_B: 0x%08x\n", hw->dpll_b); | 616 | printk(" DPLL_B: 0x%08x\n", hw->dpll_b); |
593 | printk(" FPA0: 0x%08x\n", hw->fpa0); | 617 | printk(" FPA0: 0x%08x\n", hw->fpa0); |
594 | printk(" FPA1: 0x%08x\n", hw->fpa1); | 618 | printk(" FPA1: 0x%08x\n", hw->fpa1); |
595 | printk(" FPB0: 0x%08x\n", hw->fpb0); | 619 | printk(" FPB0: 0x%08x\n", hw->fpb0); |
596 | printk(" FPB1: 0x%08x\n", hw->fpb1); | 620 | printk(" FPB1: 0x%08x\n", hw->fpb1); |
597 | 621 | ||
598 | n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; | 622 | n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
599 | m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; | 623 | m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
600 | m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; | 624 | m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
@@ -604,9 +628,9 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw) | |||
604 | p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK; | 628 | p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK; |
605 | p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK; | 629 | p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK; |
606 | printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", | 630 | printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", |
607 | m1, m2, n, p1, p2); | 631 | m1, m2, n, p1, p2); |
608 | printk(" PLLA0: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2)); | 632 | printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2)); |
609 | 633 | ||
610 | n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; | 634 | n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
611 | m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; | 635 | m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
612 | m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; | 636 | m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
@@ -616,16 +640,16 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw) | |||
616 | p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK; | 640 | p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK; |
617 | p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK; | 641 | p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK; |
618 | printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", | 642 | printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", |
619 | m1, m2, n, p1, p2); | 643 | m1, m2, n, p1, p2); |
620 | printk(" PLLA1: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2)); | 644 | printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2)); |
621 | 645 | ||
622 | #if 0 | 646 | #if 0 |
623 | printk(" PALETTE_A:\n"); | 647 | printk(" PALETTE_A:\n"); |
624 | for (i = 0; i < PALETTE_8_ENTRIES) | 648 | for (i = 0; i < PALETTE_8_ENTRIES) |
625 | printk(" %3d: 0x%08x\n", i, hw->palette_a[i]; | 649 | printk(" %3d: 0x%08x\n", i, hw->palette_a[i]); |
626 | printk(" PALETTE_B:\n"); | 650 | printk(" PALETTE_B:\n"); |
627 | for (i = 0; i < PALETTE_8_ENTRIES) | 651 | for (i = 0; i < PALETTE_8_ENTRIES) |
628 | printk(" %3d: 0x%08x\n", i, hw->palette_b[i]; | 652 | printk(" %3d: 0x%08x\n", i, hw->palette_b[i]); |
629 | #endif | 653 | #endif |
630 | 654 | ||
631 | printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a); | 655 | printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a); |
@@ -700,12 +724,12 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw) | |||
700 | } | 724 | } |
701 | for (i = 0; i < 3; i++) { | 725 | for (i = 0; i < 3; i++) { |
702 | printk(" SWF3%d 0x%08x\n", i, | 726 | printk(" SWF3%d 0x%08x\n", i, |
703 | hw->swf3x[i]); | 727 | hw->swf3x[i]); |
704 | } | 728 | } |
705 | for (i = 0; i < 8; i++) | 729 | for (i = 0; i < 8; i++) |
706 | printk(" FENCE%d 0x%08x\n", i, | 730 | printk(" FENCE%d 0x%08x\n", i, |
707 | hw->fence[i]); | 731 | hw->fence[i]); |
708 | 732 | ||
709 | printk(" INSTPM 0x%08x\n", hw->instpm); | 733 | printk(" INSTPM 0x%08x\n", hw->instpm); |
710 | printk(" MEM_MODE 0x%08x\n", hw->mem_mode); | 734 | printk(" MEM_MODE 0x%08x\n", hw->mem_mode); |
711 | printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0); | 735 | printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0); |
@@ -715,6 +739,8 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw) | |||
715 | #endif | 739 | #endif |
716 | } | 740 | } |
717 | 741 | ||
742 | |||
743 | |||
718 | /* Split the M parameter into M1 and M2. */ | 744 | /* Split the M parameter into M1 and M2. */ |
719 | static int | 745 | static int |
720 | splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2) | 746 | splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2) |
@@ -742,7 +768,17 @@ splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2) | |||
742 | { | 768 | { |
743 | int p1, p2; | 769 | int p1, p2; |
744 | 770 | ||
745 | if (index==PLLS_I8xx) | 771 | if (index == PLLS_I9xx) |
772 | { | ||
773 | p1 = (p / 10) + 1; | ||
774 | p2 = 0; | ||
775 | |||
776 | *retp1 = (unsigned int)p1; | ||
777 | *retp2 = (unsigned int)p2; | ||
778 | return 0; | ||
779 | } | ||
780 | |||
781 | if (index == PLLS_I8xx) | ||
746 | { | 782 | { |
747 | if (p % 4 == 0) | 783 | if (p % 4 == 0) |
748 | p2 = 1; | 784 | p2 = 1; |
@@ -812,7 +848,7 @@ calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *re | |||
812 | m = plls[index].min_m; | 848 | m = plls[index].min_m; |
813 | if (m > plls[index].max_m) | 849 | if (m > plls[index].max_m) |
814 | m = plls[index].max_m; | 850 | m = plls[index].max_m; |
815 | f_out = CALC_VCLOCK3(m, n, p); | 851 | f_out = calc_vclock3(index, m, n, p); |
816 | if (splitm(index, m, &m1, &m2)) { | 852 | if (splitm(index, m, &m1, &m2)) { |
817 | WRN_MSG("cannot split m = %d\n", m); | 853 | WRN_MSG("cannot split m = %d\n", m); |
818 | n++; | 854 | n++; |
@@ -849,14 +885,15 @@ calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *re | |||
849 | DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), " | 885 | DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), " |
850 | "f: %d (%d), VCO: %d\n", | 886 | "f: %d (%d), VCO: %d\n", |
851 | m, m1, m2, n, n1, p, p1, p2, | 887 | m, m1, m2, n, n1, p, p1, p2, |
852 | CALC_VCLOCK3(m, n, p), CALC_VCLOCK(m1, m2, n1, p1, p2), | 888 | calc_vclock3(index, m, n, p), |
853 | CALC_VCLOCK3(m, n, p) * p); | 889 | calc_vclock(index, m1, m2, n1, p1, p2), |
890 | calc_vclock3(index, m, n, p) * p); | ||
854 | *retm1 = m1; | 891 | *retm1 = m1; |
855 | *retm2 = m2; | 892 | *retm2 = m2; |
856 | *retn = n1; | 893 | *retn = n1; |
857 | *retp1 = p1; | 894 | *retp1 = p1; |
858 | *retp2 = p2; | 895 | *retp2 = p2; |
859 | *retclock = CALC_VCLOCK(m1, m2, n1, p1, p2); | 896 | *retclock = calc_vclock(index, m1, m2, n1, p1, p2); |
860 | 897 | ||
861 | return 0; | 898 | return 0; |
862 | } | 899 | } |
@@ -953,7 +990,7 @@ intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw, | |||
953 | /* Desired clock in kHz */ | 990 | /* Desired clock in kHz */ |
954 | clock_target = 1000000000 / var->pixclock; | 991 | clock_target = 1000000000 / var->pixclock; |
955 | 992 | ||
956 | if (calc_pll_params(PLLS_I8xx, clock_target, &m1, &m2, &n, &p1, &p2, &clock)) { | 993 | if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2, &n, &p1, &p2, &clock)) { |
957 | WRN_MSG("calc_pll_params failed\n"); | 994 | WRN_MSG("calc_pll_params failed\n"); |
958 | return 1; | 995 | return 1; |
959 | } | 996 | } |
diff --git a/drivers/video/intelfb/intelfbhw.h b/drivers/video/intelfb/intelfbhw.h index e3c305c66d5c..a3ec8f92eb64 100644 --- a/drivers/video/intelfb/intelfbhw.h +++ b/drivers/video/intelfb/intelfbhw.h | |||
@@ -158,12 +158,6 @@ | |||
158 | #define MIN_CLOCK 25000 | 158 | #define MIN_CLOCK 25000 |
159 | #define MAX_CLOCK 350000 | 159 | #define MAX_CLOCK 350000 |
160 | 160 | ||
161 | #define CALC_VCLOCK(m1, m2, n, p1, p2) \ | ||
162 | ((PLL_REFCLK * (5 * ((m1) + 2) + ((m2) + 2)) / ((n) + 2)) / \ | ||
163 | (((p1) + 2) * (1 << (p2 + 1)))) | ||
164 | |||
165 | #define CALC_VCLOCK3(m, n, p) ((PLL_REFCLK * (m) / (n)) / (p)) | ||
166 | |||
167 | /* Two pipes */ | 161 | /* Two pipes */ |
168 | #define PIPE_A 0 | 162 | #define PIPE_A 0 |
169 | #define PIPE_B 1 | 163 | #define PIPE_B 1 |
@@ -507,8 +501,7 @@ | |||
507 | 501 | ||
508 | 502 | ||
509 | /* function protoypes */ | 503 | /* function protoypes */ |
510 | extern int intelfbhw_get_chipset(struct pci_dev *pdev, const char **name, | 504 | extern int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo); |
511 | int *chipset, int *mobile); | ||
512 | extern int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size, | 505 | extern int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size, |
513 | int *stolen_size); | 506 | int *stolen_size); |
514 | extern int intelfbhw_check_non_crt(struct intelfb_info *dinfo); | 507 | extern int intelfbhw_check_non_crt(struct intelfb_info *dinfo); |