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-rw-r--r--drivers/video/fbsysfs.c8
-rw-r--r--drivers/video/modedb.c5
-rw-r--r--drivers/video/nvidia/nvidia.c7
-rw-r--r--drivers/video/pxafb.c8
-rw-r--r--drivers/video/sa1100fb.c2
-rw-r--r--drivers/video/tridentfb.c28
6 files changed, 44 insertions, 14 deletions
diff --git a/drivers/video/fbsysfs.c b/drivers/video/fbsysfs.c
index ed1d4d1ac4f7..1147b899f007 100644
--- a/drivers/video/fbsysfs.c
+++ b/drivers/video/fbsysfs.c
@@ -414,6 +414,13 @@ static ssize_t show_pan(struct class_device *class_device, char *buf)
414 fb_info->var.xoffset); 414 fb_info->var.xoffset);
415} 415}
416 416
417static ssize_t show_name(struct class_device *class_device, char *buf)
418{
419 struct fb_info *fb_info = (struct fb_info *)class_get_devdata(class_device);
420
421 return snprintf(buf, PAGE_SIZE, "%s\n", fb_info->fix.id);
422}
423
417static struct class_device_attribute class_device_attrs[] = { 424static struct class_device_attribute class_device_attrs[] = {
418 __ATTR(bits_per_pixel, S_IRUGO|S_IWUSR, show_bpp, store_bpp), 425 __ATTR(bits_per_pixel, S_IRUGO|S_IWUSR, show_bpp, store_bpp),
419 __ATTR(blank, S_IRUGO|S_IWUSR, show_blank, store_blank), 426 __ATTR(blank, S_IRUGO|S_IWUSR, show_blank, store_blank),
@@ -424,6 +431,7 @@ static struct class_device_attribute class_device_attrs[] = {
424 __ATTR(modes, S_IRUGO|S_IWUSR, show_modes, store_modes), 431 __ATTR(modes, S_IRUGO|S_IWUSR, show_modes, store_modes),
425 __ATTR(pan, S_IRUGO|S_IWUSR, show_pan, store_pan), 432 __ATTR(pan, S_IRUGO|S_IWUSR, show_pan, store_pan),
426 __ATTR(virtual_size, S_IRUGO|S_IWUSR, show_virtual, store_virtual), 433 __ATTR(virtual_size, S_IRUGO|S_IWUSR, show_virtual, store_virtual),
434 __ATTR(name, S_IRUGO, show_name, NULL),
427}; 435};
428 436
429int fb_init_class_device(struct fb_info *fb_info) 437int fb_init_class_device(struct fb_info *fb_info)
diff --git a/drivers/video/modedb.c b/drivers/video/modedb.c
index fbf659b6dab0..3edc9f49344b 100644
--- a/drivers/video/modedb.c
+++ b/drivers/video/modedb.c
@@ -246,6 +246,11 @@ static const struct fb_videomode modedb[] = {
246 /* 480x300 @ 72 Hz, 48.0 kHz hsync */ 246 /* 480x300 @ 72 Hz, 48.0 kHz hsync */
247 NULL, 72, 480, 300, 33386, 40, 24, 11, 19, 80, 3, 247 NULL, 72, 480, 300, 33386, 40, 24, 11, 19, 80, 3,
248 0, FB_VMODE_DOUBLE 248 0, FB_VMODE_DOUBLE
249 }, {
250 /* 1920x1200 @ 60 Hz, 74.5 Khz hsync */
251 NULL, 60, 1920, 1200, 5177, 128, 336, 1, 38, 208, 3,
252 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
253 FB_VMODE_NONINTERLACED
249 }, 254 },
250}; 255};
251 256
diff --git a/drivers/video/nvidia/nvidia.c b/drivers/video/nvidia/nvidia.c
index b2e6b2407869..52b16850a54e 100644
--- a/drivers/video/nvidia/nvidia.c
+++ b/drivers/video/nvidia/nvidia.c
@@ -1324,6 +1324,13 @@ static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1324 1324
1325 fb_videomode_to_var(&nvidiafb_default_var, &modedb); 1325 fb_videomode_to_var(&nvidiafb_default_var, &modedb);
1326 nvidiafb_default_var.bits_per_pixel = 8; 1326 nvidiafb_default_var.bits_per_pixel = 8;
1327 } else if (par->fpWidth && par->fpHeight) {
1328 char buf[16];
1329
1330 memset(buf, 0, 16);
1331 snprintf(buf, 15, "%dx%d", par->fpWidth, par->fpHeight);
1332 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1333 specs->modedb_len, &modedb, 8);
1327 } 1334 }
1328 1335
1329 if (mode_option) 1336 if (mode_option)
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index 16e37a535d85..30112816420c 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -717,6 +717,9 @@ static void pxafb_enable_controller(struct pxafb_info *fbi)
717 DPRINTK("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2); 717 DPRINTK("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
718 DPRINTK("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3); 718 DPRINTK("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
719 719
720 /* enable LCD controller clock */
721 pxa_set_cken(CKEN16_LCD, 1);
722
720 /* Sequence from 11.7.10 */ 723 /* Sequence from 11.7.10 */
721 LCCR3 = fbi->reg_lccr3; 724 LCCR3 = fbi->reg_lccr3;
722 LCCR2 = fbi->reg_lccr2; 725 LCCR2 = fbi->reg_lccr2;
@@ -750,6 +753,9 @@ static void pxafb_disable_controller(struct pxafb_info *fbi)
750 753
751 schedule_timeout(20 * HZ / 1000); 754 schedule_timeout(20 * HZ / 1000);
752 remove_wait_queue(&fbi->ctrlr_wait, &wait); 755 remove_wait_queue(&fbi->ctrlr_wait, &wait);
756
757 /* disable LCD controller clock */
758 pxa_set_cken(CKEN16_LCD, 0);
753} 759}
754 760
755/* 761/*
@@ -1299,8 +1305,6 @@ int __init pxafb_probe(struct device *dev)
1299 ret = -ENOMEM; 1305 ret = -ENOMEM;
1300 goto failed; 1306 goto failed;
1301 } 1307 }
1302 /* enable LCD controller clock */
1303 pxa_set_cken(CKEN16_LCD, 1);
1304 1308
1305 ret = request_irq(IRQ_LCD, pxafb_handle_irq, SA_INTERRUPT, "LCD", fbi); 1309 ret = request_irq(IRQ_LCD, pxafb_handle_irq, SA_INTERRUPT, "LCD", fbi);
1306 if (ret) { 1310 if (ret) {
diff --git a/drivers/video/sa1100fb.c b/drivers/video/sa1100fb.c
index 2d29db7ef800..beeec7b51425 100644
--- a/drivers/video/sa1100fb.c
+++ b/drivers/video/sa1100fb.c
@@ -598,7 +598,7 @@ sa1100fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
598 * requests for the LCD controller. If we hit this, it means we're 598 * requests for the LCD controller. If we hit this, it means we're
599 * doing nothing but LCD DMA. 599 * doing nothing but LCD DMA.
600 */ 600 */
601static unsigned int sa1100fb_display_dma_period(struct fb_var_screeninfo *var) 601static inline unsigned int sa1100fb_display_dma_period(struct fb_var_screeninfo *var)
602{ 602{
603 /* 603 /*
604 * Period = pixclock * bits_per_byte * bytes_per_transfer 604 * Period = pixclock * bits_per_byte * bytes_per_transfer
diff --git a/drivers/video/tridentfb.c b/drivers/video/tridentfb.c
index da8004e5d03d..698ca9232e73 100644
--- a/drivers/video/tridentfb.c
+++ b/drivers/video/tridentfb.c
@@ -454,13 +454,16 @@ static struct accel_switch accel_image = {
454static void tridentfb_fillrect(struct fb_info * info, const struct fb_fillrect *fr) 454static void tridentfb_fillrect(struct fb_info * info, const struct fb_fillrect *fr)
455{ 455{
456 int bpp = info->var.bits_per_pixel; 456 int bpp = info->var.bits_per_pixel;
457 int col; 457 int col = 0;
458 458
459 switch (bpp) { 459 switch (bpp) {
460 default: 460 default:
461 case 8: col = fr->color; 461 case 8: col |= fr->color;
462 col |= col << 8;
463 col |= col << 16;
462 break; 464 break;
463 case 16: col = ((u32 *)(info->pseudo_palette))[fr->color]; 465 case 16: col = ((u32 *)(info->pseudo_palette))[fr->color];
466
464 break; 467 break;
465 case 32: col = ((u32 *)(info->pseudo_palette))[fr->color]; 468 case 32: col = ((u32 *)(info->pseudo_palette))[fr->color];
466 break; 469 break;
@@ -882,8 +885,9 @@ static int tridentfb_set_par(struct fb_info *info)
882 885
883 write3X4(GraphEngReg, 0x80); //enable GE for text acceleration 886 write3X4(GraphEngReg, 0x80); //enable GE for text acceleration
884 887
885// if (info->var.accel_flags & FB_ACCELF_TEXT) 888#ifdef CONFIG_FB_TRIDENT_ACCEL
886//FIXME acc->init_accel(info->var.xres,bpp); 889 acc->init_accel(info->var.xres,bpp);
890#endif
887 891
888 switch (bpp) { 892 switch (bpp) {
889 case 8: tmp = 0x00; break; 893 case 8: tmp = 0x00; break;
@@ -900,7 +904,7 @@ static int tridentfb_set_par(struct fb_info *info)
900 write3X4(DRAMControl, tmp); //both IO,linear enable 904 write3X4(DRAMControl, tmp); //both IO,linear enable
901 905
902 write3X4(InterfaceSel, read3X4(InterfaceSel) | 0x40); 906 write3X4(InterfaceSel, read3X4(InterfaceSel) | 0x40);
903 write3X4(Performance,0x20); 907 write3X4(Performance,0x92);
904 write3X4(PCIReg,0x07); //MMIO & PCI read and write burst enable 908 write3X4(PCIReg,0x07); //MMIO & PCI read and write burst enable
905 909
906 /* convert from picoseconds to MHz */ 910 /* convert from picoseconds to MHz */
@@ -981,12 +985,14 @@ static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
981 t_outb(green>>10,0x3C9); 985 t_outb(green>>10,0x3C9);
982 t_outb(blue>>10,0x3C9); 986 t_outb(blue>>10,0x3C9);
983 987
984 } else 988 } else if (bpp == 16) { /* RGB 565 */
985 if (bpp == 16) /* RGB 565 */ 989 u32 col;
986 ((u32*)info->pseudo_palette)[regno] = (red & 0xF800) | 990
987 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11); 991 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
988 else 992 ((blue & 0xF800) >> 11);
989 if (bpp == 32) /* ARGB 8888 */ 993 col |= col << 16;
994 ((u32 *)(info->pseudo_palette))[regno] = col;
995 } else if (bpp == 32) /* ARGB 8888 */
990 ((u32*)info->pseudo_palette)[regno] = 996 ((u32*)info->pseudo_palette)[regno] =
991 ((transp & 0xFF00) <<16) | 997 ((transp & 0xFF00) <<16) |
992 ((red & 0xFF00) << 8) | 998 ((red & 0xFF00) << 8) |