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-rw-r--r--drivers/video/omap2/dss/apply.c18
-rw-r--r--drivers/video/omap2/dss/dispc.c29
-rw-r--r--drivers/video/omap2/dss/dss.h8
3 files changed, 27 insertions, 28 deletions
diff --git a/drivers/video/omap2/dss/apply.c b/drivers/video/omap2/dss/apply.c
index e85ec05238ab..7cdc09641b1f 100644
--- a/drivers/video/omap2/dss/apply.c
+++ b/drivers/video/omap2/dss/apply.c
@@ -666,22 +666,8 @@ static void dss_mgr_write_regs_extra(struct omap_overlay_manager *mgr)
666 dispc_mgr_set_timings(mgr->id, &mp->timings); 666 dispc_mgr_set_timings(mgr->id, &mp->timings);
667 667
668 /* lcd_config parameters */ 668 /* lcd_config parameters */
669 if (dss_mgr_is_lcd(mgr->id)) { 669 if (dss_mgr_is_lcd(mgr->id))
670 dispc_mgr_set_io_pad_mode(mp->lcd_config.io_pad_mode); 670 dispc_mgr_set_lcd_config(mgr->id, &mp->lcd_config);
671
672 dispc_mgr_enable_stallmode(mgr->id, mp->lcd_config.stallmode);
673 dispc_mgr_enable_fifohandcheck(mgr->id,
674 mp->lcd_config.fifohandcheck);
675
676 dispc_mgr_set_clock_div(mgr->id, &mp->lcd_config.clock_info);
677
678 dispc_mgr_set_tft_data_lines(mgr->id,
679 mp->lcd_config.video_port_width);
680
681 dispc_lcd_enable_signal_polarity(mp->lcd_config.lcden_sig_polarity);
682
683 dispc_mgr_set_lcd_type_tft(mgr->id);
684 }
685 671
686 mp->extra_info_dirty = false; 672 mp->extra_info_dirty = false;
687 if (mp->updating) 673 if (mp->updating)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 31880618f0e6..b65591ebaf27 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -2768,7 +2768,7 @@ bool dispc_wb_is_enabled(void)
2768 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0); 2768 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2769} 2769}
2770 2770
2771void dispc_lcd_enable_signal_polarity(bool act_high) 2771static void dispc_lcd_enable_signal_polarity(bool act_high)
2772{ 2772{
2773 if (!dss_has_feature(FEAT_LCDENABLEPOL)) 2773 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2774 return; 2774 return;
@@ -2792,13 +2792,13 @@ void dispc_pck_free_enable(bool enable)
2792 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); 2792 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2793} 2793}
2794 2794
2795void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) 2795static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2796{ 2796{
2797 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); 2797 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2798} 2798}
2799 2799
2800 2800
2801void dispc_mgr_set_lcd_type_tft(enum omap_channel channel) 2801static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2802{ 2802{
2803 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1); 2803 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2804} 2804}
@@ -2854,7 +2854,7 @@ void dispc_mgr_setup(enum omap_channel channel,
2854 } 2854 }
2855} 2855}
2856 2856
2857void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines) 2857static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2858{ 2858{
2859 int code; 2859 int code;
2860 2860
@@ -2879,7 +2879,7 @@ void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2879 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code); 2879 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2880} 2880}
2881 2881
2882void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode) 2882static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2883{ 2883{
2884 u32 l; 2884 u32 l;
2885 int gpout0, gpout1; 2885 int gpout0, gpout1;
@@ -2908,11 +2908,28 @@ void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2908 dispc_write_reg(DISPC_CONTROL, l); 2908 dispc_write_reg(DISPC_CONTROL, l);
2909} 2909}
2910 2910
2911void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable) 2911static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2912{ 2912{
2913 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable); 2913 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2914} 2914}
2915 2915
2916void dispc_mgr_set_lcd_config(enum omap_channel channel,
2917 const struct dss_lcd_mgr_config *config)
2918{
2919 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2920
2921 dispc_mgr_enable_stallmode(channel, config->stallmode);
2922 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2923
2924 dispc_mgr_set_clock_div(channel, &config->clock_info);
2925
2926 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2927
2928 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2929
2930 dispc_mgr_set_lcd_type_tft(channel);
2931}
2932
2916static bool _dispc_mgr_size_ok(u16 width, u16 height) 2933static bool _dispc_mgr_size_ok(u16 width, u16 height)
2917{ 2934{
2918 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) && 2935 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index d1e7bea077a6..959718a7de30 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -409,7 +409,6 @@ void dispc_runtime_put(void);
409void dispc_enable_sidle(void); 409void dispc_enable_sidle(void);
410void dispc_disable_sidle(void); 410void dispc_disable_sidle(void);
411 411
412void dispc_lcd_enable_signal_polarity(bool act_high);
413void dispc_lcd_enable_signal(bool enable); 412void dispc_lcd_enable_signal(bool enable);
414void dispc_pck_free_enable(bool enable); 413void dispc_pck_free_enable(bool enable);
415void dispc_enable_fifomerge(bool enable); 414void dispc_enable_fifomerge(bool enable);
@@ -436,7 +435,6 @@ int dispc_ovl_enable(enum omap_plane plane, bool enable);
436void dispc_ovl_set_channel_out(enum omap_plane plane, 435void dispc_ovl_set_channel_out(enum omap_plane plane,
437 enum omap_channel channel); 436 enum omap_channel channel);
438 437
439void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable);
440u32 dispc_mgr_get_vsync_irq(enum omap_channel channel); 438u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
441u32 dispc_mgr_get_framedone_irq(enum omap_channel channel); 439u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
442bool dispc_mgr_go_busy(enum omap_channel channel); 440bool dispc_mgr_go_busy(enum omap_channel channel);
@@ -444,10 +442,8 @@ void dispc_mgr_go(enum omap_channel channel);
444bool dispc_mgr_is_enabled(enum omap_channel channel); 442bool dispc_mgr_is_enabled(enum omap_channel channel);
445void dispc_mgr_enable(enum omap_channel channel, bool enable); 443void dispc_mgr_enable(enum omap_channel channel, bool enable);
446bool dispc_mgr_is_channel_enabled(enum omap_channel channel); 444bool dispc_mgr_is_channel_enabled(enum omap_channel channel);
447void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode); 445void dispc_mgr_set_lcd_config(enum omap_channel channel,
448void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable); 446 const struct dss_lcd_mgr_config *config);
449void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
450void dispc_mgr_set_lcd_type_tft(enum omap_channel channel);
451void dispc_mgr_set_timings(enum omap_channel channel, 447void dispc_mgr_set_timings(enum omap_channel channel,
452 const struct omap_video_timings *timings); 448 const struct omap_video_timings *timings);
453unsigned long dispc_mgr_lclk_rate(enum omap_channel channel); 449unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);