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path: root/drivers/video/vt8623fb.c
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Diffstat (limited to 'drivers/video/vt8623fb.c')
-rw-r--r--drivers/video/vt8623fb.c43
1 files changed, 23 insertions, 20 deletions
diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c
index 9de76811200e..edcfee8bc90b 100644
--- a/drivers/video/vt8623fb.c
+++ b/drivers/video/vt8623fb.c
@@ -253,6 +253,7 @@ static void vt8623fb_fillrect(struct fb_info *info, const struct fb_fillrect *re
253 253
254static void vt8623_set_pixclock(struct fb_info *info, u32 pixclock) 254static void vt8623_set_pixclock(struct fb_info *info, u32 pixclock)
255{ 255{
256 struct vt8623fb_info *par = info->par;
256 u16 m, n, r; 257 u16 m, n, r;
257 u8 regval; 258 u8 regval;
258 int rv; 259 int rv;
@@ -274,8 +275,8 @@ static void vt8623_set_pixclock(struct fb_info *info, u32 pixclock)
274 udelay(1000); 275 udelay(1000);
275 276
276 /* PLL reset */ 277 /* PLL reset */
277 svga_wseq_mask(0x40, 0x02, 0x02); 278 svga_wseq_mask(par->state.vgabase, 0x40, 0x02, 0x02);
278 svga_wseq_mask(0x40, 0x00, 0x02); 279 svga_wseq_mask(par->state.vgabase, 0x40, 0x00, 0x02);
279} 280}
280 281
281 282
@@ -415,12 +416,12 @@ static int vt8623fb_set_par(struct fb_info *info)
415 info->var.activate = FB_ACTIVATE_NOW; 416 info->var.activate = FB_ACTIVATE_NOW;
416 417
417 /* Unlock registers */ 418 /* Unlock registers */
418 svga_wseq_mask(0x10, 0x01, 0x01); 419 svga_wseq_mask(par->state.vgabase, 0x10, 0x01, 0x01);
419 svga_wcrt_mask(0x11, 0x00, 0x80); 420 svga_wcrt_mask(0x11, 0x00, 0x80);
420 svga_wcrt_mask(0x47, 0x00, 0x01); 421 svga_wcrt_mask(0x47, 0x00, 0x01);
421 422
422 /* Device, screen and sync off */ 423 /* Device, screen and sync off */
423 svga_wseq_mask(0x01, 0x20, 0x20); 424 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
424 svga_wcrt_mask(0x36, 0x30, 0x30); 425 svga_wcrt_mask(0x36, 0x30, 0x30);
425 svga_wcrt_mask(0x17, 0x00, 0x80); 426 svga_wcrt_mask(0x17, 0x00, 0x80);
426 427
@@ -444,12 +445,12 @@ static int vt8623fb_set_par(struct fb_info *info)
444 else 445 else
445 svga_wcrt_mask(0x09, 0x00, 0x80); 446 svga_wcrt_mask(0x09, 0x00, 0x80);
446 447
447 svga_wseq_mask(0x1E, 0xF0, 0xF0); // DI/DVP bus 448 svga_wseq_mask(par->state.vgabase, 0x1E, 0xF0, 0xF0); // DI/DVP bus
448 svga_wseq_mask(0x2A, 0x0F, 0x0F); // DI/DVP bus 449 svga_wseq_mask(par->state.vgabase, 0x2A, 0x0F, 0x0F); // DI/DVP bus
449 svga_wseq_mask(0x16, 0x08, 0xBF); // FIFO read threshold 450 svga_wseq_mask(par->state.vgabase, 0x16, 0x08, 0xBF); // FIFO read threshold
450 vga_wseq(NULL, 0x17, 0x1F); // FIFO depth 451 vga_wseq(NULL, 0x17, 0x1F); // FIFO depth
451 vga_wseq(NULL, 0x18, 0x4E); 452 vga_wseq(NULL, 0x18, 0x4E);
452 svga_wseq_mask(0x1A, 0x08, 0x08); // enable MMIO ? 453 svga_wseq_mask(par->state.vgabase, 0x1A, 0x08, 0x08); // enable MMIO ?
453 454
454 vga_wcrt(NULL, 0x32, 0x00); 455 vga_wcrt(NULL, 0x32, 0x00);
455 vga_wcrt(NULL, 0x34, 0x00); 456 vga_wcrt(NULL, 0x34, 0x00);
@@ -466,31 +467,31 @@ static int vt8623fb_set_par(struct fb_info *info)
466 case 0: 467 case 0:
467 pr_debug("fb%d: text mode\n", info->node); 468 pr_debug("fb%d: text mode\n", info->node);
468 svga_set_textmode_vga_regs(); 469 svga_set_textmode_vga_regs();
469 svga_wseq_mask(0x15, 0x00, 0xFE); 470 svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
470 svga_wcrt_mask(0x11, 0x60, 0x70); 471 svga_wcrt_mask(0x11, 0x60, 0x70);
471 break; 472 break;
472 case 1: 473 case 1:
473 pr_debug("fb%d: 4 bit pseudocolor\n", info->node); 474 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
474 vga_wgfx(NULL, VGA_GFX_MODE, 0x40); 475 vga_wgfx(NULL, VGA_GFX_MODE, 0x40);
475 svga_wseq_mask(0x15, 0x20, 0xFE); 476 svga_wseq_mask(par->state.vgabase, 0x15, 0x20, 0xFE);
476 svga_wcrt_mask(0x11, 0x00, 0x70); 477 svga_wcrt_mask(0x11, 0x00, 0x70);
477 break; 478 break;
478 case 2: 479 case 2:
479 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); 480 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
480 svga_wseq_mask(0x15, 0x00, 0xFE); 481 svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
481 svga_wcrt_mask(0x11, 0x00, 0x70); 482 svga_wcrt_mask(0x11, 0x00, 0x70);
482 break; 483 break;
483 case 3: 484 case 3:
484 pr_debug("fb%d: 8 bit pseudocolor\n", info->node); 485 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
485 svga_wseq_mask(0x15, 0x22, 0xFE); 486 svga_wseq_mask(par->state.vgabase, 0x15, 0x22, 0xFE);
486 break; 487 break;
487 case 4: 488 case 4:
488 pr_debug("fb%d: 5/6/5 truecolor\n", info->node); 489 pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
489 svga_wseq_mask(0x15, 0xB6, 0xFE); 490 svga_wseq_mask(par->state.vgabase, 0x15, 0xB6, 0xFE);
490 break; 491 break;
491 case 5: 492 case 5:
492 pr_debug("fb%d: 8/8/8 truecolor\n", info->node); 493 pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
493 svga_wseq_mask(0x15, 0xAE, 0xFE); 494 svga_wseq_mask(par->state.vgabase, 0x15, 0xAE, 0xFE);
494 break; 495 break;
495 default: 496 default:
496 printk(KERN_ERR "vt8623fb: unsupported mode - bug\n"); 497 printk(KERN_ERR "vt8623fb: unsupported mode - bug\n");
@@ -507,7 +508,7 @@ static int vt8623fb_set_par(struct fb_info *info)
507 /* Device and screen back on */ 508 /* Device and screen back on */
508 svga_wcrt_mask(0x17, 0x80, 0x80); 509 svga_wcrt_mask(0x17, 0x80, 0x80);
509 svga_wcrt_mask(0x36, 0x00, 0x30); 510 svga_wcrt_mask(0x36, 0x00, 0x30);
510 svga_wseq_mask(0x01, 0x00, 0x20); 511 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
511 512
512 return 0; 513 return 0;
513} 514}
@@ -570,31 +571,33 @@ static int vt8623fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
570 571
571static int vt8623fb_blank(int blank_mode, struct fb_info *info) 572static int vt8623fb_blank(int blank_mode, struct fb_info *info)
572{ 573{
574 struct vt8623fb_info *par = info->par;
575
573 switch (blank_mode) { 576 switch (blank_mode) {
574 case FB_BLANK_UNBLANK: 577 case FB_BLANK_UNBLANK:
575 pr_debug("fb%d: unblank\n", info->node); 578 pr_debug("fb%d: unblank\n", info->node);
576 svga_wcrt_mask(0x36, 0x00, 0x30); 579 svga_wcrt_mask(0x36, 0x00, 0x30);
577 svga_wseq_mask(0x01, 0x00, 0x20); 580 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
578 break; 581 break;
579 case FB_BLANK_NORMAL: 582 case FB_BLANK_NORMAL:
580 pr_debug("fb%d: blank\n", info->node); 583 pr_debug("fb%d: blank\n", info->node);
581 svga_wcrt_mask(0x36, 0x00, 0x30); 584 svga_wcrt_mask(0x36, 0x00, 0x30);
582 svga_wseq_mask(0x01, 0x20, 0x20); 585 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
583 break; 586 break;
584 case FB_BLANK_HSYNC_SUSPEND: 587 case FB_BLANK_HSYNC_SUSPEND:
585 pr_debug("fb%d: DPMS standby (hsync off)\n", info->node); 588 pr_debug("fb%d: DPMS standby (hsync off)\n", info->node);
586 svga_wcrt_mask(0x36, 0x10, 0x30); 589 svga_wcrt_mask(0x36, 0x10, 0x30);
587 svga_wseq_mask(0x01, 0x20, 0x20); 590 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
588 break; 591 break;
589 case FB_BLANK_VSYNC_SUSPEND: 592 case FB_BLANK_VSYNC_SUSPEND:
590 pr_debug("fb%d: DPMS suspend (vsync off)\n", info->node); 593 pr_debug("fb%d: DPMS suspend (vsync off)\n", info->node);
591 svga_wcrt_mask(0x36, 0x20, 0x30); 594 svga_wcrt_mask(0x36, 0x20, 0x30);
592 svga_wseq_mask(0x01, 0x20, 0x20); 595 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
593 break; 596 break;
594 case FB_BLANK_POWERDOWN: 597 case FB_BLANK_POWERDOWN:
595 pr_debug("fb%d: DPMS off (no sync)\n", info->node); 598 pr_debug("fb%d: DPMS off (no sync)\n", info->node);
596 svga_wcrt_mask(0x36, 0x30, 0x30); 599 svga_wcrt_mask(0x36, 0x30, 0x30);
597 svga_wseq_mask(0x01, 0x20, 0x20); 600 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
598 break; 601 break;
599 } 602 }
600 603